1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
62 static const struct objfile_data
*mips_pdr_data
;
64 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
66 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
67 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
68 #define ST0_FR (1 << 26)
70 /* The sizes of floating point registers. */
74 MIPS_FPU_SINGLE_REGSIZE
= 4,
75 MIPS_FPU_DOUBLE_REGSIZE
= 8
84 static const char *mips_abi_string
;
86 static const char *mips_abi_strings
[] = {
97 /* The standard register names, and all the valid aliases for them. */
104 /* Aliases for o32 and most other ABIs. */
105 const struct register_alias mips_o32_aliases
[] = {
112 /* Aliases for n32 and n64. */
113 const struct register_alias mips_n32_n64_aliases
[] = {
120 /* Aliases for ABI-independent registers. */
121 const struct register_alias mips_register_aliases
[] = {
122 /* The architecture manuals specify these ABI-independent names for
124 #define R(n) { "r" #n, n }
125 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
126 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
127 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
128 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
131 /* k0 and k1 are sometimes called these instead (for "kernel
136 /* This is the traditional GDB name for the CP0 status register. */
137 { "sr", MIPS_PS_REGNUM
},
139 /* This is the traditional GDB name for the CP0 BadVAddr register. */
140 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
142 /* This is the traditional GDB name for the FCSR. */
143 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
146 const struct register_alias mips_numeric_register_aliases
[] = {
147 #define R(n) { #n, n }
148 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
149 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
150 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
151 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto
= 1;
159 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
161 static int mips_debug
= 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc
*mips_tdesc_gp32
;
169 struct target_desc
*mips_tdesc_gp64
;
171 const struct mips_regnum
*
172 mips_regnum (struct gdbarch
*gdbarch
)
174 return gdbarch_tdep (gdbarch
)->regnum
;
178 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
180 return mips_regnum (gdbarch
)->fp0
+ 12;
183 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
185 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
187 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
189 #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
191 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
193 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
194 functions to test, set, or clear bit 0 of addresses. */
197 is_mips16_addr (CORE_ADDR addr
)
203 unmake_mips16_addr (CORE_ADDR addr
)
205 return ((addr
) & ~(CORE_ADDR
) 1);
208 /* Return the MIPS ABI associated with GDBARCH. */
210 mips_abi (struct gdbarch
*gdbarch
)
212 return gdbarch_tdep (gdbarch
)->mips_abi
;
216 mips_isa_regsize (struct gdbarch
*gdbarch
)
218 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
220 /* If we know how big the registers are, use that size. */
221 if (tdep
->register_size_valid_p
)
222 return tdep
->register_size
;
224 /* Fall back to the previous behavior. */
225 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
226 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
229 /* Return the currently configured (or set) saved register size. */
232 mips_abi_regsize (struct gdbarch
*gdbarch
)
234 switch (mips_abi (gdbarch
))
236 case MIPS_ABI_EABI32
:
242 case MIPS_ABI_EABI64
:
244 case MIPS_ABI_UNKNOWN
:
247 internal_error (__FILE__
, __LINE__
, _("bad switch"));
251 /* Functions for setting and testing a bit in a minimal symbol that
252 marks it as 16-bit function. The MSB of the minimal symbol's
253 "info" field is used for this purpose.
255 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
256 i.e. refers to a 16-bit function, and sets a "special" bit in a
257 minimal symbol to mark it as a 16-bit function
259 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
262 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
264 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
266 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
267 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
272 msymbol_is_special (struct minimal_symbol
*msym
)
274 return MSYMBOL_TARGET_FLAG_1 (msym
);
277 /* XFER a value from the big/little/left end of the register.
278 Depending on the size of the value it might occupy the entire
279 register or just part of it. Make an allowance for this, aligning
280 things accordingly. */
283 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
284 int reg_num
, int length
,
285 enum bfd_endian endian
, gdb_byte
*in
,
286 const gdb_byte
*out
, int buf_offset
)
290 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
291 /* Need to transfer the left or right part of the register, based on
292 the targets byte order. */
296 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
298 case BFD_ENDIAN_LITTLE
:
301 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
305 internal_error (__FILE__
, __LINE__
, _("bad switch"));
308 fprintf_unfiltered (gdb_stderr
,
309 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
310 reg_num
, reg_offset
, buf_offset
, length
);
311 if (mips_debug
&& out
!= NULL
)
314 fprintf_unfiltered (gdb_stdlog
, "out ");
315 for (i
= 0; i
< length
; i
++)
316 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
319 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
322 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
324 if (mips_debug
&& in
!= NULL
)
327 fprintf_unfiltered (gdb_stdlog
, "in ");
328 for (i
= 0; i
< length
; i
++)
329 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
332 fprintf_unfiltered (gdb_stdlog
, "\n");
335 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
336 compatiblity mode. A return value of 1 means that we have
337 physical 64-bit registers, but should treat them as 32-bit registers. */
340 mips2_fp_compat (struct frame_info
*frame
)
342 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
343 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
345 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
349 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
350 in all the places we deal with FP registers. PR gdb/413. */
351 /* Otherwise check the FR bit in the status register - it controls
352 the FP compatiblity mode. If it is clear we are in compatibility
354 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
361 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
363 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
365 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
367 /* The list of available "set mips " and "show mips " commands */
369 static struct cmd_list_element
*setmipscmdlist
= NULL
;
370 static struct cmd_list_element
*showmipscmdlist
= NULL
;
372 /* Integer registers 0 thru 31 are handled explicitly by
373 mips_register_name(). Processor specific registers 32 and above
374 are listed in the following tables. */
377 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
381 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
382 "sr", "lo", "hi", "bad", "cause", "pc",
383 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
384 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
385 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
386 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
387 "fsr", "fir", "" /*"fp" */ , "",
388 "", "", "", "", "", "", "", "",
389 "", "", "", "", "", "", "", "",
392 /* Names of IDT R3041 registers. */
394 static const char *mips_r3041_reg_names
[] = {
395 "sr", "lo", "hi", "bad", "cause", "pc",
396 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
397 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
398 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
399 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
400 "fsr", "fir", "", /*"fp" */ "",
401 "", "", "bus", "ccfg", "", "", "", "",
402 "", "", "port", "cmp", "", "", "epc", "prid",
405 /* Names of tx39 registers. */
407 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
408 "sr", "lo", "hi", "bad", "cause", "pc",
409 "", "", "", "", "", "", "", "",
410 "", "", "", "", "", "", "", "",
411 "", "", "", "", "", "", "", "",
412 "", "", "", "", "", "", "", "",
414 "", "", "", "", "", "", "", "",
415 "", "", "config", "cache", "debug", "depc", "epc", ""
418 /* Names of IRIX registers. */
419 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
420 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
421 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
422 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
423 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
424 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
428 /* Return the name of the register corresponding to REGNO. */
430 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
432 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
433 /* GPR names for all ABIs other than n32/n64. */
434 static char *mips_gpr_names
[] = {
435 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
436 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
437 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
438 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
441 /* GPR names for n32 and n64 ABIs. */
442 static char *mips_n32_n64_gpr_names
[] = {
443 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
444 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
445 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
446 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
449 enum mips_abi abi
= mips_abi (gdbarch
);
451 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
452 but then don't make the raw register names visible. */
453 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
454 if (regno
< gdbarch_num_regs (gdbarch
))
457 /* The MIPS integer registers are always mapped from 0 to 31. The
458 names of the registers (which reflects the conventions regarding
459 register use) vary depending on the ABI. */
460 if (0 <= rawnum
&& rawnum
< 32)
462 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
463 return mips_n32_n64_gpr_names
[rawnum
];
465 return mips_gpr_names
[rawnum
];
467 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
468 return tdesc_register_name (gdbarch
, rawnum
);
469 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
471 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
472 return tdep
->mips_processor_reg_names
[rawnum
- 32];
475 internal_error (__FILE__
, __LINE__
,
476 _("mips_register_name: bad register number %d"), rawnum
);
479 /* Return the groups that a MIPS register can be categorised into. */
482 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
483 struct reggroup
*reggroup
)
488 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
489 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
490 if (reggroup
== all_reggroup
)
492 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
493 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
494 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
495 (gdbarch), as not all architectures are multi-arch. */
496 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
497 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
498 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
500 if (reggroup
== float_reggroup
)
501 return float_p
&& pseudo
;
502 if (reggroup
== vector_reggroup
)
503 return vector_p
&& pseudo
;
504 if (reggroup
== general_reggroup
)
505 return (!vector_p
&& !float_p
) && pseudo
;
506 /* Save the pseudo registers. Need to make certain that any code
507 extracting register values from a saved register cache also uses
509 if (reggroup
== save_reggroup
)
510 return raw_p
&& pseudo
;
511 /* Restore the same pseudo register. */
512 if (reggroup
== restore_reggroup
)
513 return raw_p
&& pseudo
;
517 /* Return the groups that a MIPS register can be categorised into.
518 This version is only used if we have a target description which
519 describes real registers (and their groups). */
522 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
523 struct reggroup
*reggroup
)
525 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
526 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
529 /* Only save, restore, and display the pseudo registers. Need to
530 make certain that any code extracting register values from a
531 saved register cache also uses pseudo registers.
533 Note: saving and restoring the pseudo registers is slightly
534 strange; if we have 64 bits, we should save and restore all
535 64 bits. But this is hard and has little benefit. */
539 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
543 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
546 /* Map the symbol table registers which live in the range [1 *
547 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
548 registers. Take care of alignment and size problems. */
551 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
552 int cookednum
, gdb_byte
*buf
)
554 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
555 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
556 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
557 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
558 regcache_raw_read (regcache
, rawnum
, buf
);
559 else if (register_size (gdbarch
, rawnum
) >
560 register_size (gdbarch
, cookednum
))
562 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
563 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
566 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
568 regcache_raw_read_signed (regcache
, rawnum
, ®val
);
569 store_signed_integer (buf
, 4, byte_order
, regval
);
573 internal_error (__FILE__
, __LINE__
, _("bad register size"));
577 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
578 struct regcache
*regcache
, int cookednum
,
581 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
582 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
583 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
584 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
585 regcache_raw_write (regcache
, rawnum
, buf
);
586 else if (register_size (gdbarch
, rawnum
) >
587 register_size (gdbarch
, cookednum
))
589 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
590 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
593 /* Sign extend the shortened version of the register prior
594 to placing it in the raw register. This is required for
595 some mips64 parts in order to avoid unpredictable behavior. */
596 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
597 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
598 regcache_raw_write_signed (regcache
, rawnum
, regval
);
602 internal_error (__FILE__
, __LINE__
, _("bad register size"));
605 /* Table to translate MIPS16 register field to actual register number. */
606 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
608 /* Heuristic_proc_start may hunt through the text section for a long
609 time across a 2400 baud serial line. Allows the user to limit this
612 static unsigned int heuristic_fence_post
= 0;
614 /* Number of bytes of storage in the actual machine representation for
615 register N. NOTE: This defines the pseudo register type so need to
616 rebuild the architecture vector. */
618 static int mips64_transfers_32bit_regs_p
= 0;
621 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
622 struct cmd_list_element
*c
)
624 struct gdbarch_info info
;
625 gdbarch_info_init (&info
);
626 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
627 instead of relying on globals. Doing that would let generic code
628 handle the search for this specific architecture. */
629 if (!gdbarch_update_p (info
))
631 mips64_transfers_32bit_regs_p
= 0;
632 error (_("32-bit compatibility mode not supported"));
636 /* Convert to/from a register and the corresponding memory value. */
639 mips_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
641 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
642 && register_size (gdbarch
, regnum
) == 4
643 && (regnum
% gdbarch_num_regs (gdbarch
))
644 >= mips_regnum (gdbarch
)->fp0
645 && (regnum
% gdbarch_num_regs (gdbarch
))
646 < mips_regnum (gdbarch
)->fp0
+ 32
647 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
651 mips_register_to_value (struct frame_info
*frame
, int regnum
,
652 struct type
*type
, gdb_byte
*to
)
654 get_frame_register (frame
, regnum
+ 0, to
+ 4);
655 get_frame_register (frame
, regnum
+ 1, to
+ 0);
659 mips_value_to_register (struct frame_info
*frame
, int regnum
,
660 struct type
*type
, const gdb_byte
*from
)
662 put_frame_register (frame
, regnum
+ 0, from
+ 4);
663 put_frame_register (frame
, regnum
+ 1, from
+ 0);
666 /* Return the GDB type object for the "standard" data type of data in
670 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
672 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
673 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
674 && (regnum
% gdbarch_num_regs (gdbarch
))
675 < mips_regnum (gdbarch
)->fp0
+ 32)
677 /* The floating-point registers raw, or cooked, always match
678 mips_isa_regsize(), and also map 1:1, byte for byte. */
679 if (mips_isa_regsize (gdbarch
) == 4)
680 return builtin_type (gdbarch
)->builtin_float
;
682 return builtin_type (gdbarch
)->builtin_double
;
684 else if (regnum
< gdbarch_num_regs (gdbarch
))
686 /* The raw or ISA registers. These are all sized according to
688 if (mips_isa_regsize (gdbarch
) == 4)
689 return builtin_type (gdbarch
)->builtin_int32
;
691 return builtin_type (gdbarch
)->builtin_int64
;
695 /* The cooked or ABI registers. These are sized according to
696 the ABI (with a few complications). */
697 if (regnum
>= (gdbarch_num_regs (gdbarch
)
698 + mips_regnum (gdbarch
)->fp_control_status
)
699 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
700 /* The pseudo/cooked view of the embedded registers is always
701 32-bit. The raw view is handled below. */
702 return builtin_type (gdbarch
)->builtin_int32
;
703 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
704 /* The target, while possibly using a 64-bit register buffer,
705 is only transfering 32-bits of each integer register.
706 Reflect this in the cooked/pseudo (ABI) register value. */
707 return builtin_type (gdbarch
)->builtin_int32
;
708 else if (mips_abi_regsize (gdbarch
) == 4)
709 /* The ABI is restricted to 32-bit registers (the ISA could be
711 return builtin_type (gdbarch
)->builtin_int32
;
714 return builtin_type (gdbarch
)->builtin_int64
;
718 /* Return the GDB type for the pseudo register REGNUM, which is the
719 ABI-level view. This function is only called if there is a target
720 description which includes registers, so we know precisely the
721 types of hardware registers. */
724 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
726 const int num_regs
= gdbarch_num_regs (gdbarch
);
727 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
728 int rawnum
= regnum
% num_regs
;
729 struct type
*rawtype
;
731 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
733 /* Absent registers are still absent. */
734 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
735 if (TYPE_LENGTH (rawtype
) == 0)
738 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
739 /* Present the floating point registers however the hardware did;
740 do not try to convert between FPU layouts. */
743 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
745 /* The pseudo/cooked view of embedded registers is always
746 32-bit, even if the target transfers 64-bit values for them.
747 New targets relying on XML descriptions should only transfer
748 the necessary 32 bits, but older versions of GDB expected 64,
749 so allow the target to provide 64 bits without interfering
750 with the displayed type. */
751 return builtin_type (gdbarch
)->builtin_int32
;
754 /* Use pointer types for registers if we can. For n32 we can not,
755 since we do not have a 64-bit pointer type. */
756 if (mips_abi_regsize (gdbarch
)
757 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
759 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
760 return builtin_type (gdbarch
)->builtin_data_ptr
;
761 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
762 return builtin_type (gdbarch
)->builtin_func_ptr
;
765 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
766 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
767 return builtin_type (gdbarch
)->builtin_int32
;
769 /* For all other registers, pass through the hardware type. */
773 /* Should the upper word of 64-bit addresses be zeroed? */
774 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
777 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
779 switch (mask_address_var
)
781 case AUTO_BOOLEAN_TRUE
:
783 case AUTO_BOOLEAN_FALSE
:
786 case AUTO_BOOLEAN_AUTO
:
787 return tdep
->default_mask_address_p
;
789 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
795 show_mask_address (struct ui_file
*file
, int from_tty
,
796 struct cmd_list_element
*c
, const char *value
)
798 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
800 deprecated_show_value_hack (file
, from_tty
, c
, value
);
801 switch (mask_address_var
)
803 case AUTO_BOOLEAN_TRUE
:
804 printf_filtered ("The 32 bit mips address mask is enabled\n");
806 case AUTO_BOOLEAN_FALSE
:
807 printf_filtered ("The 32 bit mips address mask is disabled\n");
809 case AUTO_BOOLEAN_AUTO
:
811 ("The 32 bit address mask is set automatically. Currently %s\n",
812 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
815 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
820 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
823 mips_pc_is_mips16 (CORE_ADDR memaddr
)
825 struct minimal_symbol
*sym
;
827 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
828 if (is_mips16_addr (memaddr
))
831 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
832 the high bit of the info field. Use this to decide if the function is
833 MIPS16 or normal MIPS. */
834 sym
= lookup_minimal_symbol_by_pc (memaddr
);
836 return msymbol_is_special (sym
);
841 /* MIPS believes that the PC has a sign extended value. Perhaps the
842 all registers should be sign extended for simplicity? */
845 mips_read_pc (struct regcache
*regcache
)
848 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
849 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
854 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
856 return frame_unwind_register_signed
857 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
861 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
863 return frame_unwind_register_signed
864 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
867 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
868 dummy frame. The frame ID's base needs to match the TOS value
869 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
872 static struct frame_id
873 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
875 return frame_id_build
876 (get_frame_register_signed (this_frame
,
877 gdbarch_num_regs (gdbarch
)
879 get_frame_pc (this_frame
));
883 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
885 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
886 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
889 /* Fetch and return instruction from the specified location. If the PC
890 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
893 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
895 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
896 gdb_byte buf
[MIPS_INSN32_SIZE
];
900 if (mips_pc_is_mips16 (addr
))
902 instlen
= MIPS_INSN16_SIZE
;
903 addr
= unmake_mips16_addr (addr
);
906 instlen
= MIPS_INSN32_SIZE
;
907 status
= target_read_memory (addr
, buf
, instlen
);
909 memory_error (status
, addr
);
910 return extract_unsigned_integer (buf
, instlen
, byte_order
);
913 /* These the fields of 32 bit mips instructions */
914 #define mips32_op(x) (x >> 26)
915 #define itype_op(x) (x >> 26)
916 #define itype_rs(x) ((x >> 21) & 0x1f)
917 #define itype_rt(x) ((x >> 16) & 0x1f)
918 #define itype_immediate(x) (x & 0xffff)
920 #define jtype_op(x) (x >> 26)
921 #define jtype_target(x) (x & 0x03ffffff)
923 #define rtype_op(x) (x >> 26)
924 #define rtype_rs(x) ((x >> 21) & 0x1f)
925 #define rtype_rt(x) ((x >> 16) & 0x1f)
926 #define rtype_rd(x) ((x >> 11) & 0x1f)
927 #define rtype_shamt(x) ((x >> 6) & 0x1f)
928 #define rtype_funct(x) (x & 0x3f)
931 mips32_relative_offset (ULONGEST inst
)
933 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
936 /* Determine where to set a single step breakpoint while considering
937 branch prediction. */
939 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
941 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
944 inst
= mips_fetch_instruction (gdbarch
, pc
);
945 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
947 if (itype_op (inst
) >> 2 == 5)
948 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
950 op
= (itype_op (inst
) & 0x03);
965 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
966 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
968 int tf
= itype_rt (inst
) & 0x01;
969 int cnum
= itype_rt (inst
) >> 2;
971 get_frame_register_signed (frame
,
972 mips_regnum (get_frame_arch (frame
))->
974 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
976 if (((cond
>> cnum
) & 0x01) == tf
)
977 pc
+= mips32_relative_offset (inst
) + 4;
982 pc
+= 4; /* Not a branch, next instruction is easy */
985 { /* This gets way messy */
987 /* Further subdivide into SPECIAL, REGIMM and other */
988 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
990 case 0: /* SPECIAL */
991 op
= rtype_funct (inst
);
996 /* Set PC to that address */
997 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
999 case 12: /* SYSCALL */
1001 struct gdbarch_tdep
*tdep
;
1003 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1004 if (tdep
->syscall_next_pc
!= NULL
)
1005 pc
= tdep
->syscall_next_pc (frame
);
1014 break; /* end SPECIAL */
1015 case 1: /* REGIMM */
1017 op
= itype_rt (inst
); /* branch condition */
1022 case 16: /* BLTZAL */
1023 case 18: /* BLTZALL */
1025 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1026 pc
+= mips32_relative_offset (inst
) + 4;
1028 pc
+= 8; /* after the delay slot */
1032 case 17: /* BGEZAL */
1033 case 19: /* BGEZALL */
1034 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1035 pc
+= mips32_relative_offset (inst
) + 4;
1037 pc
+= 8; /* after the delay slot */
1039 /* All of the other instructions in the REGIMM category */
1044 break; /* end REGIMM */
1049 reg
= jtype_target (inst
) << 2;
1050 /* Upper four bits get never changed... */
1051 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1054 /* FIXME case JALX : */
1057 reg
= jtype_target (inst
) << 2;
1058 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1059 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1061 break; /* The new PC will be alternate mode */
1062 case 4: /* BEQ, BEQL */
1064 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1065 get_frame_register_signed (frame
, itype_rt (inst
)))
1066 pc
+= mips32_relative_offset (inst
) + 4;
1070 case 5: /* BNE, BNEL */
1072 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1073 get_frame_register_signed (frame
, itype_rt (inst
)))
1074 pc
+= mips32_relative_offset (inst
) + 4;
1078 case 6: /* BLEZ, BLEZL */
1079 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1080 pc
+= mips32_relative_offset (inst
) + 4;
1086 greater_branch
: /* BGTZ, BGTZL */
1087 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1088 pc
+= mips32_relative_offset (inst
) + 4;
1095 } /* mips32_next_pc */
1097 /* Decoding the next place to set a breakpoint is irregular for the
1098 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1099 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1100 We dont want to set a single step instruction on the extend instruction
1104 /* Lots of mips16 instruction formats */
1105 /* Predicting jumps requires itype,ritype,i8type
1106 and their extensions extItype,extritype,extI8type
1108 enum mips16_inst_fmts
1110 itype
, /* 0 immediate 5,10 */
1111 ritype
, /* 1 5,3,8 */
1112 rrtype
, /* 2 5,3,3,5 */
1113 rritype
, /* 3 5,3,3,5 */
1114 rrrtype
, /* 4 5,3,3,3,2 */
1115 rriatype
, /* 5 5,3,3,1,4 */
1116 shifttype
, /* 6 5,3,3,3,2 */
1117 i8type
, /* 7 5,3,8 */
1118 i8movtype
, /* 8 5,3,3,5 */
1119 i8mov32rtype
, /* 9 5,3,5,3 */
1120 i64type
, /* 10 5,3,8 */
1121 ri64type
, /* 11 5,3,3,5 */
1122 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1123 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1124 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1125 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1126 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1127 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1128 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1129 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1130 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1131 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1133 /* I am heaping all the fields of the formats into one structure and
1134 then, only the fields which are involved in instruction extension */
1138 unsigned int regx
; /* Function in i8 type */
1143 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1144 for the bits which make up the immediate extension. */
1147 extended_offset (unsigned int extension
)
1150 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1152 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1154 value
|= extension
& 0x01f; /* extract 4:0 */
1158 /* Only call this function if you know that this is an extendable
1159 instruction. It won't malfunction, but why make excess remote memory
1160 references? If the immediate operands get sign extended or something,
1161 do it after the extension is performed. */
1162 /* FIXME: Every one of these cases needs to worry about sign extension
1163 when the offset is to be used in relative addressing. */
1166 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1168 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1170 pc
&= 0xfffffffe; /* clear the low order bit */
1171 target_read_memory (pc
, buf
, 2);
1172 return extract_unsigned_integer (buf
, 2, byte_order
);
1176 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1177 unsigned int extension
,
1179 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1184 switch (insn_format
)
1191 value
= extended_offset (extension
);
1192 value
= value
<< 11; /* rom for the original value */
1193 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1197 value
= inst
& 0x7ff;
1198 /* FIXME : Consider sign extension */
1207 { /* A register identifier and an offset */
1208 /* Most of the fields are the same as I type but the
1209 immediate value is of a different length */
1213 value
= extended_offset (extension
);
1214 value
= value
<< 8; /* from the original instruction */
1215 value
|= inst
& 0xff; /* eleven bits from instruction */
1216 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1217 if (value
& 0x4000) /* test the sign bit , bit 26 */
1219 value
&= ~0x3fff; /* remove the sign bit */
1225 value
= inst
& 0xff; /* 8 bits */
1226 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1227 /* FIXME: Do sign extension , this format needs it */
1228 if (value
& 0x80) /* THIS CONFUSES ME */
1230 value
&= 0xef; /* remove the sign bit */
1240 unsigned long value
;
1241 unsigned int nexthalf
;
1242 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1243 value
= value
<< 16;
1244 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit still set */
1252 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1254 upk
->offset
= offset
;
1261 add_offset_16 (CORE_ADDR pc
, int offset
)
1263 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1267 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1268 unsigned int extension
, unsigned int insn
)
1270 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1271 int op
= (insn
>> 11);
1274 case 2: /* Branch */
1277 struct upk_mips16 upk
;
1278 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1279 offset
= upk
.offset
;
1285 pc
+= (offset
<< 1) + 2;
1288 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1290 struct upk_mips16 upk
;
1291 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1292 pc
= add_offset_16 (pc
, upk
.offset
);
1293 if ((insn
>> 10) & 0x01) /* Exchange mode */
1294 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1301 struct upk_mips16 upk
;
1303 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1304 reg
= get_frame_register_signed (frame
, upk
.regx
);
1306 pc
+= (upk
.offset
<< 1) + 2;
1313 struct upk_mips16 upk
;
1315 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1316 reg
= get_frame_register_signed (frame
, upk
.regx
);
1318 pc
+= (upk
.offset
<< 1) + 2;
1323 case 12: /* I8 Formats btez btnez */
1325 struct upk_mips16 upk
;
1327 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1328 /* upk.regx contains the opcode */
1329 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1330 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1331 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1332 /* pc = add_offset_16(pc,upk.offset) ; */
1333 pc
+= (upk
.offset
<< 1) + 2;
1338 case 29: /* RR Formats JR, JALR, JALR-RA */
1340 struct upk_mips16 upk
;
1341 /* upk.fmt = rrtype; */
1346 upk
.regx
= (insn
>> 8) & 0x07;
1347 upk
.regy
= (insn
>> 5) & 0x07;
1355 break; /* Function return instruction */
1361 break; /* BOGUS Guess */
1363 pc
= get_frame_register_signed (frame
, reg
);
1370 /* This is an instruction extension. Fetch the real instruction
1371 (which follows the extension) and decode things based on
1375 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1376 fetch_mips_16 (gdbarch
, pc
));
1389 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1391 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1392 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1393 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1396 /* The mips_next_pc function supports single_step when the remote
1397 target monitor or stub is not developed enough to do a single_step.
1398 It works by decoding the current instruction and predicting where a
1399 branch will go. This isnt hard because all the data is available.
1400 The MIPS32 and MIPS16 variants are quite different. */
1402 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1404 if (is_mips16_addr (pc
))
1405 return mips16_next_pc (frame
, pc
);
1407 return mips32_next_pc (frame
, pc
);
1410 struct mips_frame_cache
1413 struct trad_frame_saved_reg
*saved_regs
;
1416 /* Set a register's saved stack address in temp_saved_regs. If an
1417 address has already been set for this register, do nothing; this
1418 way we will only recognize the first save of a given register in a
1421 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1422 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1423 Strictly speaking, only the second range is used as it is only second
1424 range (the ABI instead of ISA registers) that comes into play when finding
1425 saved registers in a frame. */
1428 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1429 int regnum
, CORE_ADDR offset
)
1431 if (this_cache
!= NULL
1432 && this_cache
->saved_regs
[regnum
].addr
== -1)
1434 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1436 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1442 /* Fetch the immediate value from a MIPS16 instruction.
1443 If the previous instruction was an EXTEND, use it to extend
1444 the upper bits of the immediate value. This is a helper function
1445 for mips16_scan_prologue. */
1448 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1449 unsigned short inst
, /* current instruction */
1450 int nbits
, /* number of bits in imm field */
1451 int scale
, /* scale factor to be applied to imm */
1452 int is_signed
) /* is the imm field signed? */
1456 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1458 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1459 if (offset
& 0x8000) /* check for negative extend */
1460 offset
= 0 - (0x10000 - (offset
& 0xffff));
1461 return offset
| (inst
& 0x1f);
1465 int max_imm
= 1 << nbits
;
1466 int mask
= max_imm
- 1;
1467 int sign_bit
= max_imm
>> 1;
1469 offset
= inst
& mask
;
1470 if (is_signed
&& (offset
& sign_bit
))
1471 offset
= 0 - (max_imm
- offset
);
1472 return offset
* scale
;
1477 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1478 the associated FRAME_CACHE if not null.
1479 Return the address of the first instruction past the prologue. */
1482 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1483 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1484 struct frame_info
*this_frame
,
1485 struct mips_frame_cache
*this_cache
)
1488 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1490 long frame_offset
= 0; /* Size of stack frame. */
1491 long frame_adjust
= 0; /* Offset of FP from SP. */
1492 int frame_reg
= MIPS_SP_REGNUM
;
1493 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1494 unsigned inst
= 0; /* current instruction */
1495 unsigned entry_inst
= 0; /* the entry instruction */
1496 unsigned save_inst
= 0; /* the save instruction */
1499 int extend_bytes
= 0;
1500 int prev_extend_bytes
;
1501 CORE_ADDR end_prologue_addr
= 0;
1503 /* Can be called when there's no process, and hence when there's no
1505 if (this_frame
!= NULL
)
1506 sp
= get_frame_register_signed (this_frame
,
1507 gdbarch_num_regs (gdbarch
)
1512 if (limit_pc
> start_pc
+ 200)
1513 limit_pc
= start_pc
+ 200;
1515 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1517 /* Save the previous instruction. If it's an EXTEND, we'll extract
1518 the immediate offset extension from it in mips16_get_imm. */
1521 /* Fetch and decode the instruction. */
1522 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1524 /* Normally we ignore extend instructions. However, if it is
1525 not followed by a valid prologue instruction, then this
1526 instruction is not part of the prologue either. We must
1527 remember in this case to adjust the end_prologue_addr back
1529 if ((inst
& 0xf800) == 0xf000) /* extend */
1531 extend_bytes
= MIPS_INSN16_SIZE
;
1535 prev_extend_bytes
= extend_bytes
;
1538 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1539 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1541 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1542 if (offset
< 0) /* negative stack adjustment? */
1543 frame_offset
-= offset
;
1545 /* Exit loop if a positive stack adjustment is found, which
1546 usually means that the stack cleanup code in the function
1547 epilogue is reached. */
1550 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1552 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1553 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1554 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1556 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1558 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1559 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1560 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1562 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1564 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1565 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1567 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1569 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1570 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1572 else if (inst
== 0x673d) /* move $s1, $sp */
1577 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1579 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1580 frame_addr
= sp
+ offset
;
1582 frame_adjust
= offset
;
1584 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1586 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1587 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1588 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1590 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1592 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1593 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1594 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1596 else if ((inst
& 0xf81f) == 0xe809
1597 && (inst
& 0x700) != 0x700) /* entry */
1598 entry_inst
= inst
; /* save for later processing */
1599 else if ((inst
& 0xff80) == 0x6480) /* save */
1601 save_inst
= inst
; /* save for later processing */
1602 if (prev_extend_bytes
) /* extend */
1603 save_inst
|= prev_inst
<< 16;
1605 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1606 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1607 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1609 /* This instruction is part of the prologue, but we don't
1610 need to do anything special to handle it. */
1614 /* This instruction is not an instruction typically found
1615 in a prologue, so we must have reached the end of the
1617 if (end_prologue_addr
== 0)
1618 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1622 /* The entry instruction is typically the first instruction in a function,
1623 and it stores registers at offsets relative to the value of the old SP
1624 (before the prologue). But the value of the sp parameter to this
1625 function is the new SP (after the prologue has been executed). So we
1626 can't calculate those offsets until we've seen the entire prologue,
1627 and can calculate what the old SP must have been. */
1628 if (entry_inst
!= 0)
1630 int areg_count
= (entry_inst
>> 8) & 7;
1631 int sreg_count
= (entry_inst
>> 6) & 3;
1633 /* The entry instruction always subtracts 32 from the SP. */
1636 /* Now we can calculate what the SP must have been at the
1637 start of the function prologue. */
1640 /* Check if a0-a3 were saved in the caller's argument save area. */
1641 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1643 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1644 offset
+= mips_abi_regsize (gdbarch
);
1647 /* Check if the ra register was pushed on the stack. */
1649 if (entry_inst
& 0x20)
1651 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1652 offset
-= mips_abi_regsize (gdbarch
);
1655 /* Check if the s0 and s1 registers were pushed on the stack. */
1656 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1658 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1659 offset
-= mips_abi_regsize (gdbarch
);
1663 /* The SAVE instruction is similar to ENTRY, except that defined by the
1664 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1665 size of the frame is specified as an immediate field of instruction
1666 and an extended variation exists which lets additional registers and
1667 frame space to be specified. The instruction always treats registers
1668 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1669 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1671 static int args_table
[16] = {
1672 0, 0, 0, 0, 1, 1, 1, 1,
1673 2, 2, 2, 0, 3, 3, 4, -1,
1675 static int astatic_table
[16] = {
1676 0, 1, 2, 3, 0, 1, 2, 3,
1677 0, 1, 2, 4, 0, 1, 0, -1,
1679 int aregs
= (save_inst
>> 16) & 0xf;
1680 int xsregs
= (save_inst
>> 24) & 0x7;
1681 int args
= args_table
[aregs
];
1682 int astatic
= astatic_table
[aregs
];
1687 warning (_("Invalid number of argument registers encoded in SAVE."));
1692 warning (_("Invalid number of static registers encoded in SAVE."));
1696 /* For standard SAVE the frame size of 0 means 128. */
1697 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1698 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1701 frame_offset
+= frame_size
;
1703 /* Now we can calculate what the SP must have been at the
1704 start of the function prologue. */
1707 /* Check if A0-A3 were saved in the caller's argument save area. */
1708 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1710 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1711 offset
+= mips_abi_regsize (gdbarch
);
1716 /* Check if the RA register was pushed on the stack. */
1717 if (save_inst
& 0x40)
1719 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1720 offset
-= mips_abi_regsize (gdbarch
);
1723 /* Check if the S8 register was pushed on the stack. */
1726 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1727 offset
-= mips_abi_regsize (gdbarch
);
1730 /* Check if S2-S7 were pushed on the stack. */
1731 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1733 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1734 offset
-= mips_abi_regsize (gdbarch
);
1737 /* Check if the S1 register was pushed on the stack. */
1738 if (save_inst
& 0x10)
1740 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1741 offset
-= mips_abi_regsize (gdbarch
);
1743 /* Check if the S0 register was pushed on the stack. */
1744 if (save_inst
& 0x20)
1746 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1747 offset
-= mips_abi_regsize (gdbarch
);
1750 /* Check if A0-A3 were pushed on the stack. */
1751 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1753 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1754 offset
-= mips_abi_regsize (gdbarch
);
1758 if (this_cache
!= NULL
)
1761 (get_frame_register_signed (this_frame
,
1762 gdbarch_num_regs (gdbarch
) + frame_reg
)
1763 + frame_offset
- frame_adjust
);
1764 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1765 be able to get rid of the assignment below, evetually. But it's
1766 still needed for now. */
1767 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1768 + mips_regnum (gdbarch
)->pc
]
1769 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1772 /* If we didn't reach the end of the prologue when scanning the function
1773 instructions, then set end_prologue_addr to the address of the
1774 instruction immediately after the last one we scanned. */
1775 if (end_prologue_addr
== 0)
1776 end_prologue_addr
= cur_pc
;
1778 return end_prologue_addr
;
1781 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1782 Procedures that use the 32-bit instruction set are handled by the
1783 mips_insn32 unwinder. */
1785 static struct mips_frame_cache
*
1786 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1788 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1789 struct mips_frame_cache
*cache
;
1791 if ((*this_cache
) != NULL
)
1792 return (*this_cache
);
1793 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1794 (*this_cache
) = cache
;
1795 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1797 /* Analyze the function prologue. */
1799 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1800 CORE_ADDR start_addr
;
1802 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1803 if (start_addr
== 0)
1804 start_addr
= heuristic_proc_start (gdbarch
, pc
);
1805 /* We can't analyze the prologue if we couldn't find the begining
1807 if (start_addr
== 0)
1810 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
1813 /* gdbarch_sp_regnum contains the value and not the address. */
1814 trad_frame_set_value (cache
->saved_regs
,
1815 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
1818 return (*this_cache
);
1822 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1823 struct frame_id
*this_id
)
1825 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1827 /* This marks the outermost frame. */
1828 if (info
->base
== 0)
1830 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
1833 static struct value
*
1834 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
1835 void **this_cache
, int regnum
)
1837 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1839 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1843 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
1844 struct frame_info
*this_frame
, void **this_cache
)
1846 CORE_ADDR pc
= get_frame_pc (this_frame
);
1847 if (mips_pc_is_mips16 (pc
))
1852 static const struct frame_unwind mips_insn16_frame_unwind
=
1855 mips_insn16_frame_this_id
,
1856 mips_insn16_frame_prev_register
,
1858 mips_insn16_frame_sniffer
1862 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
1865 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1870 static const struct frame_base mips_insn16_frame_base
=
1872 &mips_insn16_frame_unwind
,
1873 mips_insn16_frame_base_address
,
1874 mips_insn16_frame_base_address
,
1875 mips_insn16_frame_base_address
1878 static const struct frame_base
*
1879 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
1881 CORE_ADDR pc
= get_frame_pc (this_frame
);
1882 if (mips_pc_is_mips16 (pc
))
1883 return &mips_insn16_frame_base
;
1888 /* Mark all the registers as unset in the saved_regs array
1889 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1892 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
1894 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1898 const int num_regs
= gdbarch_num_regs (gdbarch
);
1901 for (i
= 0; i
< num_regs
; i
++)
1903 this_cache
->saved_regs
[i
].addr
= -1;
1908 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1909 the associated FRAME_CACHE if not null.
1910 Return the address of the first instruction past the prologue. */
1913 mips32_scan_prologue (struct gdbarch
*gdbarch
,
1914 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1915 struct frame_info
*this_frame
,
1916 struct mips_frame_cache
*this_cache
)
1919 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1922 int frame_reg
= MIPS_SP_REGNUM
;
1924 CORE_ADDR end_prologue_addr
= 0;
1925 int seen_sp_adjust
= 0;
1926 int load_immediate_bytes
= 0;
1927 int in_delay_slot
= 0;
1928 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
1930 /* Can be called when there's no process, and hence when there's no
1932 if (this_frame
!= NULL
)
1933 sp
= get_frame_register_signed (this_frame
,
1934 gdbarch_num_regs (gdbarch
)
1939 if (limit_pc
> start_pc
+ 200)
1940 limit_pc
= start_pc
+ 200;
1945 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1947 unsigned long inst
, high_word
, low_word
;
1950 /* Fetch the instruction. */
1951 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
1953 /* Save some code by pre-extracting some useful fields. */
1954 high_word
= (inst
>> 16) & 0xffff;
1955 low_word
= inst
& 0xffff;
1956 reg
= high_word
& 0x1f;
1958 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1959 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1960 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1962 if (low_word
& 0x8000) /* negative stack adjustment? */
1963 frame_offset
+= 0x10000 - low_word
;
1965 /* Exit loop if a positive stack adjustment is found, which
1966 usually means that the stack cleanup code in the function
1967 epilogue is reached. */
1971 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1972 && !regsize_is_64_bits
)
1974 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
1976 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1977 && regsize_is_64_bits
)
1979 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1980 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
1982 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1984 /* Old gcc frame, r30 is virtual frame pointer. */
1985 if ((long) low_word
!= frame_offset
)
1986 frame_addr
= sp
+ low_word
;
1987 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1989 unsigned alloca_adjust
;
1992 frame_addr
= get_frame_register_signed
1993 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
1995 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1996 if (alloca_adjust
> 0)
1998 /* FP > SP + frame_size. This may be because of
1999 an alloca or somethings similar. Fix sp to
2000 "pre-alloca" value, and try again. */
2001 sp
+= alloca_adjust
;
2002 /* Need to reset the status of all registers. Otherwise,
2003 we will hit a guard that prevents the new address
2004 for each register to be recomputed during the second
2006 reset_saved_regs (gdbarch
, this_cache
);
2011 /* move $30,$sp. With different versions of gas this will be either
2012 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2013 Accept any one of these. */
2014 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2016 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2017 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2019 unsigned alloca_adjust
;
2022 frame_addr
= get_frame_register_signed
2023 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2025 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2026 if (alloca_adjust
> 0)
2028 /* FP > SP + frame_size. This may be because of
2029 an alloca or somethings similar. Fix sp to
2030 "pre-alloca" value, and try again. */
2032 /* Need to reset the status of all registers. Otherwise,
2033 we will hit a guard that prevents the new address
2034 for each register to be recomputed during the second
2036 reset_saved_regs (gdbarch
, this_cache
);
2041 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2042 && !regsize_is_64_bits
)
2044 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2046 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2047 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2048 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2049 || high_word
== 0x3c1c /* lui $gp,n */
2050 || high_word
== 0x279c /* addiu $gp,$gp,n */
2051 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2052 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2055 /* These instructions are part of the prologue, but we don't
2056 need to do anything special to handle them. */
2058 /* The instructions below load $at or $t0 with an immediate
2059 value in preparation for a stack adjustment via
2060 subu $sp,$sp,[$at,$t0]. These instructions could also
2061 initialize a local variable, so we accept them only before
2062 a stack adjustment instruction was seen. */
2063 else if (!seen_sp_adjust
2064 && (high_word
== 0x3c01 /* lui $at,n */
2065 || high_word
== 0x3c08 /* lui $t0,n */
2066 || high_word
== 0x3421 /* ori $at,$at,n */
2067 || high_word
== 0x3508 /* ori $t0,$t0,n */
2068 || high_word
== 0x3401 /* ori $at,$zero,n */
2069 || high_word
== 0x3408 /* ori $t0,$zero,n */
2072 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2076 /* This instruction is not an instruction typically found
2077 in a prologue, so we must have reached the end of the
2079 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2080 loop now? Why would we need to continue scanning the function
2082 if (end_prologue_addr
== 0)
2083 end_prologue_addr
= cur_pc
;
2085 /* Check for branches and jumps. For now, only jump to
2086 register are caught (i.e. returns). */
2087 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2091 /* If the previous instruction was a jump, we must have reached
2092 the end of the prologue by now. Stop scanning so that we do
2093 not go past the function return. */
2098 if (this_cache
!= NULL
)
2101 (get_frame_register_signed (this_frame
,
2102 gdbarch_num_regs (gdbarch
) + frame_reg
)
2104 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2105 this assignment below, eventually. But it's still needed
2107 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2108 + mips_regnum (gdbarch
)->pc
]
2109 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2113 /* If we didn't reach the end of the prologue when scanning the function
2114 instructions, then set end_prologue_addr to the address of the
2115 instruction immediately after the last one we scanned. */
2116 /* brobecker/2004-10-10: I don't think this would ever happen, but
2117 we may as well be careful and do our best if we have a null
2118 end_prologue_addr. */
2119 if (end_prologue_addr
== 0)
2120 end_prologue_addr
= cur_pc
;
2122 /* In a frameless function, we might have incorrectly
2123 skipped some load immediate instructions. Undo the skipping
2124 if the load immediate was not followed by a stack adjustment. */
2125 if (load_immediate_bytes
&& !seen_sp_adjust
)
2126 end_prologue_addr
-= load_immediate_bytes
;
2128 return end_prologue_addr
;
2131 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2132 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2133 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2136 static struct mips_frame_cache
*
2137 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2139 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2140 struct mips_frame_cache
*cache
;
2142 if ((*this_cache
) != NULL
)
2143 return (*this_cache
);
2145 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2146 (*this_cache
) = cache
;
2147 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2149 /* Analyze the function prologue. */
2151 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2152 CORE_ADDR start_addr
;
2154 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2155 if (start_addr
== 0)
2156 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2157 /* We can't analyze the prologue if we couldn't find the begining
2159 if (start_addr
== 0)
2162 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2165 /* gdbarch_sp_regnum contains the value and not the address. */
2166 trad_frame_set_value (cache
->saved_regs
,
2167 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2170 return (*this_cache
);
2174 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2175 struct frame_id
*this_id
)
2177 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2179 /* This marks the outermost frame. */
2180 if (info
->base
== 0)
2182 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2185 static struct value
*
2186 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2187 void **this_cache
, int regnum
)
2189 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2191 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2195 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2196 struct frame_info
*this_frame
, void **this_cache
)
2198 CORE_ADDR pc
= get_frame_pc (this_frame
);
2199 if (! mips_pc_is_mips16 (pc
))
2204 static const struct frame_unwind mips_insn32_frame_unwind
=
2207 mips_insn32_frame_this_id
,
2208 mips_insn32_frame_prev_register
,
2210 mips_insn32_frame_sniffer
2214 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2217 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2222 static const struct frame_base mips_insn32_frame_base
=
2224 &mips_insn32_frame_unwind
,
2225 mips_insn32_frame_base_address
,
2226 mips_insn32_frame_base_address
,
2227 mips_insn32_frame_base_address
2230 static const struct frame_base
*
2231 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2233 CORE_ADDR pc
= get_frame_pc (this_frame
);
2234 if (! mips_pc_is_mips16 (pc
))
2235 return &mips_insn32_frame_base
;
2240 static struct trad_frame_cache
*
2241 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2244 CORE_ADDR start_addr
;
2245 CORE_ADDR stack_addr
;
2246 struct trad_frame_cache
*this_trad_cache
;
2247 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2248 int num_regs
= gdbarch_num_regs (gdbarch
);
2250 if ((*this_cache
) != NULL
)
2251 return (*this_cache
);
2252 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2253 (*this_cache
) = this_trad_cache
;
2255 /* The return address is in the link register. */
2256 trad_frame_set_reg_realreg (this_trad_cache
,
2257 gdbarch_pc_regnum (gdbarch
),
2258 num_regs
+ MIPS_RA_REGNUM
);
2260 /* Frame ID, since it's a frameless / stackless function, no stack
2261 space is allocated and SP on entry is the current SP. */
2262 pc
= get_frame_pc (this_frame
);
2263 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2264 stack_addr
= get_frame_register_signed (this_frame
,
2265 num_regs
+ MIPS_SP_REGNUM
);
2266 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2268 /* Assume that the frame's base is the same as the
2270 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2272 return this_trad_cache
;
2276 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2277 struct frame_id
*this_id
)
2279 struct trad_frame_cache
*this_trad_cache
2280 = mips_stub_frame_cache (this_frame
, this_cache
);
2281 trad_frame_get_id (this_trad_cache
, this_id
);
2284 static struct value
*
2285 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2286 void **this_cache
, int regnum
)
2288 struct trad_frame_cache
*this_trad_cache
2289 = mips_stub_frame_cache (this_frame
, this_cache
);
2290 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2294 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2295 struct frame_info
*this_frame
, void **this_cache
)
2298 struct obj_section
*s
;
2299 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2300 struct minimal_symbol
*msym
;
2302 /* Use the stub unwinder for unreadable code. */
2303 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2306 if (in_plt_section (pc
, NULL
))
2309 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2310 s
= find_pc_section (pc
);
2313 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2314 ".MIPS.stubs") == 0)
2317 /* Calling a PIC function from a non-PIC function passes through a
2318 stub. The stub for foo is named ".pic.foo". */
2319 msym
= lookup_minimal_symbol_by_pc (pc
);
2321 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2322 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2328 static const struct frame_unwind mips_stub_frame_unwind
=
2331 mips_stub_frame_this_id
,
2332 mips_stub_frame_prev_register
,
2334 mips_stub_frame_sniffer
2338 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2341 struct trad_frame_cache
*this_trad_cache
2342 = mips_stub_frame_cache (this_frame
, this_cache
);
2343 return trad_frame_get_this_base (this_trad_cache
);
2346 static const struct frame_base mips_stub_frame_base
=
2348 &mips_stub_frame_unwind
,
2349 mips_stub_frame_base_address
,
2350 mips_stub_frame_base_address
,
2351 mips_stub_frame_base_address
2354 static const struct frame_base
*
2355 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2357 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2358 return &mips_stub_frame_base
;
2363 /* mips_addr_bits_remove - remove useless address bits */
2366 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2368 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2369 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2370 /* This hack is a work-around for existing boards using PMON, the
2371 simulator, and any other 64-bit targets that doesn't have true
2372 64-bit addressing. On these targets, the upper 32 bits of
2373 addresses are ignored by the hardware. Thus, the PC or SP are
2374 likely to have been sign extended to all 1s by instruction
2375 sequences that load 32-bit addresses. For example, a typical
2376 piece of code that loads an address is this:
2378 lui $r2, <upper 16 bits>
2379 ori $r2, <lower 16 bits>
2381 But the lui sign-extends the value such that the upper 32 bits
2382 may be all 1s. The workaround is simply to mask off these
2383 bits. In the future, gcc may be changed to support true 64-bit
2384 addressing, and this masking will have to be disabled. */
2385 return addr
&= 0xffffffffUL
;
2390 /* Instructions used during single-stepping of atomic sequences. */
2391 #define LL_OPCODE 0x30
2392 #define LLD_OPCODE 0x34
2393 #define SC_OPCODE 0x38
2394 #define SCD_OPCODE 0x3c
2396 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2397 instruction and ending with a SC/SCD instruction. If such a sequence
2398 is found, attempt to step through it. A breakpoint is placed at the end of
2402 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2403 struct address_space
*aspace
, CORE_ADDR pc
)
2405 CORE_ADDR breaks
[2] = {-1, -1};
2407 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2411 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2412 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2417 insn
= mips_fetch_instruction (gdbarch
, loc
);
2418 /* Assume all atomic sequences start with a ll/lld instruction. */
2419 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2422 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2424 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2427 loc
+= MIPS_INSN32_SIZE
;
2428 insn
= mips_fetch_instruction (gdbarch
, loc
);
2430 /* Assume that there is at most one branch in the atomic
2431 sequence. If a branch is found, put a breakpoint in its
2432 destination address. */
2433 switch (itype_op (insn
))
2435 case 0: /* SPECIAL */
2436 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2437 return 0; /* fallback to the standard single-step code. */
2439 case 1: /* REGIMM */
2440 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2444 return 0; /* fallback to the standard single-step code. */
2451 case 22: /* BLEZL */
2452 case 23: /* BGTTL */
2458 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2463 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2464 if (last_breakpoint
>= 1)
2465 return 0; /* More than one branch found, fallback to the
2466 standard single-step code. */
2467 breaks
[1] = branch_bp
;
2471 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2475 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2476 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2479 loc
+= MIPS_INSN32_SIZE
;
2481 /* Insert a breakpoint right after the end of the atomic sequence. */
2484 /* Check for duplicated breakpoints. Check also for a breakpoint
2485 placed (branch instruction's destination) in the atomic sequence */
2486 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2487 last_breakpoint
= 0;
2489 /* Effectively inserts the breakpoints. */
2490 for (index
= 0; index
<= last_breakpoint
; index
++)
2491 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2496 /* mips_software_single_step() is called just before we want to resume
2497 the inferior, if we want to single-step it but there is no hardware
2498 or kernel single-step support (MIPS on GNU/Linux for example). We find
2499 the target of the coming instruction and breakpoint it. */
2502 mips_software_single_step (struct frame_info
*frame
)
2504 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2505 struct address_space
*aspace
= get_frame_address_space (frame
);
2506 CORE_ADDR pc
, next_pc
;
2508 pc
= get_frame_pc (frame
);
2509 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2512 next_pc
= mips_next_pc (frame
, pc
);
2514 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2518 /* Test whether the PC points to the return instruction at the
2519 end of a function. */
2522 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2524 if (mips_pc_is_mips16 (pc
))
2525 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2526 generates a "jr $ra"; other times it generates code to load
2527 the return address from the stack to an accessible register (such
2528 as $a3), then a "jr" using that register. This second case
2529 is almost impossible to distinguish from an indirect jump
2530 used for switch statements, so we don't even try. */
2531 return mips_fetch_instruction (gdbarch
, pc
) == 0xe820; /* jr $ra */
2533 return mips_fetch_instruction (gdbarch
, pc
) == 0x3e00008; /* jr $ra */
2537 /* This fencepost looks highly suspicious to me. Removing it also
2538 seems suspicious as it could affect remote debugging across serial
2542 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2548 struct inferior
*inf
;
2550 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2552 fence
= start_pc
- heuristic_fence_post
;
2556 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2557 fence
= VM_MIN_ADDRESS
;
2559 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2561 inf
= current_inferior ();
2563 /* search back for previous return */
2564 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2565 if (start_pc
< fence
)
2567 /* It's not clear to me why we reach this point when
2568 stop_soon, but with this test, at least we
2569 don't print out warnings for every child forked (eg, on
2570 decstation). 22apr93 rich@cygnus.com. */
2571 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2573 static int blurb_printed
= 0;
2575 warning (_("GDB can't find the start of the function at %s."),
2576 paddress (gdbarch
, pc
));
2580 /* This actually happens frequently in embedded
2581 development, when you first connect to a board
2582 and your stack pointer and pc are nowhere in
2583 particular. This message needs to give people
2584 in that situation enough information to
2585 determine that it's no big deal. */
2586 printf_filtered ("\n\
2587 GDB is unable to find the start of the function at %s\n\
2588 and thus can't determine the size of that function's stack frame.\n\
2589 This means that GDB may be unable to access that stack frame, or\n\
2590 the frames below it.\n\
2591 This problem is most likely caused by an invalid program counter or\n\
2593 However, if you think GDB should simply search farther back\n\
2594 from %s for code which looks like the beginning of a\n\
2595 function, you can increase the range of the search using the `set\n\
2596 heuristic-fence-post' command.\n",
2597 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2604 else if (mips_pc_is_mips16 (start_pc
))
2606 unsigned short inst
;
2608 /* On MIPS16, any one of the following is likely to be the
2609 start of a function:
2615 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2616 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2617 if ((inst
& 0xff80) == 0x6480) /* save */
2619 if (start_pc
- instlen
>= fence
)
2621 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2622 if ((inst
& 0xf800) == 0xf000) /* extend */
2623 start_pc
-= instlen
;
2627 else if (((inst
& 0xf81f) == 0xe809
2628 && (inst
& 0x700) != 0x700) /* entry */
2629 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2630 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2631 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2633 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2634 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2639 else if (mips_about_to_return (gdbarch
, start_pc
))
2641 /* Skip return and its delay slot. */
2642 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2649 struct mips_objfile_private
2655 /* According to the current ABI, should the type be passed in a
2656 floating-point register (assuming that there is space)? When there
2657 is no FPU, FP are not even considered as possible candidates for
2658 FP registers and, consequently this returns false - forces FP
2659 arguments into integer registers. */
2662 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2663 struct type
*arg_type
)
2665 return ((typecode
== TYPE_CODE_FLT
2666 || (MIPS_EABI (gdbarch
)
2667 && (typecode
== TYPE_CODE_STRUCT
2668 || typecode
== TYPE_CODE_UNION
)
2669 && TYPE_NFIELDS (arg_type
) == 1
2670 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2672 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2675 /* On o32, argument passing in GPRs depends on the alignment of the type being
2676 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2679 mips_type_needs_double_align (struct type
*type
)
2681 enum type_code typecode
= TYPE_CODE (type
);
2683 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2685 else if (typecode
== TYPE_CODE_STRUCT
)
2687 if (TYPE_NFIELDS (type
) < 1)
2689 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2691 else if (typecode
== TYPE_CODE_UNION
)
2695 n
= TYPE_NFIELDS (type
);
2696 for (i
= 0; i
< n
; i
++)
2697 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2704 /* Adjust the address downward (direction of stack growth) so that it
2705 is correctly aligned for a new stack frame. */
2707 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2709 return align_down (addr
, 16);
2713 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2714 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2715 int nargs
, struct value
**args
, CORE_ADDR sp
,
2716 int struct_return
, CORE_ADDR struct_addr
)
2722 int stack_offset
= 0;
2723 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2724 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2725 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2726 int regsize
= mips_abi_regsize (gdbarch
);
2728 /* For shared libraries, "t9" needs to point at the function
2730 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2732 /* Set the return address register to point to the entry point of
2733 the program, where a breakpoint lies in wait. */
2734 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2736 /* First ensure that the stack and structure return address (if any)
2737 are properly aligned. The stack has to be at least 64-bit
2738 aligned even on 32-bit machines, because doubles must be 64-bit
2739 aligned. For n32 and n64, stack frames need to be 128-bit
2740 aligned, so we round to this widest known alignment. */
2742 sp
= align_down (sp
, 16);
2743 struct_addr
= align_down (struct_addr
, 16);
2745 /* Now make space on the stack for the args. We allocate more
2746 than necessary for EABI, because the first few arguments are
2747 passed in registers, but that's OK. */
2748 for (argnum
= 0; argnum
< nargs
; argnum
++)
2749 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2750 sp
-= align_up (len
, 16);
2753 fprintf_unfiltered (gdb_stdlog
,
2754 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2755 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2757 /* Initialize the integer and float register pointers. */
2758 argreg
= MIPS_A0_REGNUM
;
2759 float_argreg
= mips_fpa0_regnum (gdbarch
);
2761 /* The struct_return pointer occupies the first parameter-passing reg. */
2765 fprintf_unfiltered (gdb_stdlog
,
2766 "mips_eabi_push_dummy_call: struct_return reg=%d %s\n",
2767 argreg
, paddress (gdbarch
, struct_addr
));
2768 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2771 /* Now load as many as possible of the first arguments into
2772 registers, and push the rest onto the stack. Loop thru args
2773 from first to last. */
2774 for (argnum
= 0; argnum
< nargs
; argnum
++)
2776 const gdb_byte
*val
;
2777 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2778 struct value
*arg
= args
[argnum
];
2779 struct type
*arg_type
= check_typedef (value_type (arg
));
2780 int len
= TYPE_LENGTH (arg_type
);
2781 enum type_code typecode
= TYPE_CODE (arg_type
);
2784 fprintf_unfiltered (gdb_stdlog
,
2785 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2786 argnum
+ 1, len
, (int) typecode
);
2788 /* The EABI passes structures that do not fit in a register by
2791 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2793 store_unsigned_integer (valbuf
, regsize
, byte_order
,
2794 value_address (arg
));
2795 typecode
= TYPE_CODE_PTR
;
2799 fprintf_unfiltered (gdb_stdlog
, " push");
2802 val
= value_contents (arg
);
2804 /* 32-bit ABIs always start floating point arguments in an
2805 even-numbered floating point register. Round the FP register
2806 up before the check to see if there are any FP registers
2807 left. Non MIPS_EABI targets also pass the FP in the integer
2808 registers so also round up normal registers. */
2809 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2811 if ((float_argreg
& 1))
2815 /* Floating point arguments passed in registers have to be
2816 treated specially. On 32-bit architectures, doubles
2817 are passed in register pairs; the even register gets
2818 the low word, and the odd register gets the high word.
2819 On non-EABI processors, the first two floating point arguments are
2820 also copied to general registers, because MIPS16 functions
2821 don't use float registers for arguments. This duplication of
2822 arguments in general registers can't hurt non-MIPS16 functions
2823 because those registers are normally skipped. */
2824 /* MIPS_EABI squeezes a struct that contains a single floating
2825 point value into an FP register instead of pushing it onto the
2827 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
2828 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
2830 /* EABI32 will pass doubles in consecutive registers, even on
2831 64-bit cores. At one time, we used to check the size of
2832 `float_argreg' to determine whether or not to pass doubles
2833 in consecutive registers, but this is not sufficient for
2834 making the ABI determination. */
2835 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2837 int low_offset
= gdbarch_byte_order (gdbarch
)
2838 == BFD_ENDIAN_BIG
? 4 : 0;
2841 /* Write the low word of the double to the even register(s). */
2842 regval
= extract_signed_integer (val
+ low_offset
,
2845 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2846 float_argreg
, phex (regval
, 4));
2847 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
2849 /* Write the high word of the double to the odd register(s). */
2850 regval
= extract_signed_integer (val
+ 4 - low_offset
,
2853 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2854 float_argreg
, phex (regval
, 4));
2855 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
2859 /* This is a floating point value that fits entirely
2860 in a single register. */
2861 /* On 32 bit ABI's the float_argreg is further adjusted
2862 above to ensure that it is even register aligned. */
2863 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
2865 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2866 float_argreg
, phex (regval
, len
));
2867 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
2872 /* Copy the argument to general registers or the stack in
2873 register-sized pieces. Large arguments are split between
2874 registers and stack. */
2875 /* Note: structs whose size is not a multiple of regsize
2876 are treated specially: Irix cc passes
2877 them in registers where gcc sometimes puts them on the
2878 stack. For maximum compatibility, we will put them in
2880 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2882 /* Note: Floating-point values that didn't fit into an FP
2883 register are only written to memory. */
2886 /* Remember if the argument was written to the stack. */
2887 int stack_used_p
= 0;
2888 int partial_len
= (len
< regsize
? len
: regsize
);
2891 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2894 /* Write this portion of the argument to the stack. */
2895 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
2897 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2899 /* Should shorter than int integer values be
2900 promoted to int before being stored? */
2901 int longword_offset
= 0;
2904 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2907 && (typecode
== TYPE_CODE_INT
2908 || typecode
== TYPE_CODE_PTR
2909 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2910 longword_offset
= regsize
- len
;
2911 else if ((typecode
== TYPE_CODE_STRUCT
2912 || typecode
== TYPE_CODE_UNION
)
2913 && TYPE_LENGTH (arg_type
) < regsize
)
2914 longword_offset
= regsize
- len
;
2919 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
2920 paddress (gdbarch
, stack_offset
));
2921 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
2922 paddress (gdbarch
, longword_offset
));
2925 addr
= sp
+ stack_offset
+ longword_offset
;
2930 fprintf_unfiltered (gdb_stdlog
, " @%s ",
2931 paddress (gdbarch
, addr
));
2932 for (i
= 0; i
< partial_len
; i
++)
2934 fprintf_unfiltered (gdb_stdlog
, "%02x",
2938 write_memory (addr
, val
, partial_len
);
2941 /* Note!!! This is NOT an else clause. Odd sized
2942 structs may go thru BOTH paths. Floating point
2943 arguments will not. */
2944 /* Write this portion of the argument to a general
2945 purpose register. */
2946 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
2947 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2950 extract_signed_integer (val
, partial_len
, byte_order
);
2953 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2955 phex (regval
, regsize
));
2956 regcache_cooked_write_signed (regcache
, argreg
, regval
);
2963 /* Compute the the offset into the stack at which we
2964 will copy the next parameter.
2966 In the new EABI (and the NABI32), the stack_offset
2967 only needs to be adjusted when it has been used. */
2970 stack_offset
+= align_up (partial_len
, regsize
);
2974 fprintf_unfiltered (gdb_stdlog
, "\n");
2977 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2979 /* Return adjusted stack pointer. */
2983 /* Determine the return value convention being used. */
2985 static enum return_value_convention
2986 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2987 struct type
*type
, struct regcache
*regcache
,
2988 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2990 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2991 int fp_return_type
= 0;
2992 int offset
, regnum
, xfer
;
2994 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2995 return RETURN_VALUE_STRUCT_CONVENTION
;
2997 /* Floating point type? */
2998 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3000 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3002 /* Structs with a single field of float type
3003 are returned in a floating point register. */
3004 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3005 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3006 && TYPE_NFIELDS (type
) == 1)
3008 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3010 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3017 /* A floating-point value belongs in the least significant part
3020 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3021 regnum
= mips_regnum (gdbarch
)->fp0
;
3025 /* An integer value goes in V0/V1. */
3027 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3028 regnum
= MIPS_V0_REGNUM
;
3031 offset
< TYPE_LENGTH (type
);
3032 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3034 xfer
= mips_abi_regsize (gdbarch
);
3035 if (offset
+ xfer
> TYPE_LENGTH (type
))
3036 xfer
= TYPE_LENGTH (type
) - offset
;
3037 mips_xfer_register (gdbarch
, regcache
,
3038 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3039 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3043 return RETURN_VALUE_REGISTER_CONVENTION
;
3047 /* N32/N64 ABI stuff. */
3049 /* Search for a naturally aligned double at OFFSET inside a struct
3050 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3054 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3059 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3062 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3065 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3068 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3071 struct type
*field_type
;
3073 /* We're only looking at normal fields. */
3074 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3075 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3078 /* If we have gone past the offset, there is no double to pass. */
3079 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3083 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3085 /* If this field is entirely before the requested offset, go
3086 on to the next one. */
3087 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3090 /* If this is our special aligned double, we can stop. */
3091 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3092 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3095 /* This field starts at or before the requested offset, and
3096 overlaps it. If it is a structure, recurse inwards. */
3097 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3104 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3105 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3106 int nargs
, struct value
**args
, CORE_ADDR sp
,
3107 int struct_return
, CORE_ADDR struct_addr
)
3113 int stack_offset
= 0;
3114 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3115 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3116 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3118 /* For shared libraries, "t9" needs to point at the function
3120 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3122 /* Set the return address register to point to the entry point of
3123 the program, where a breakpoint lies in wait. */
3124 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3126 /* First ensure that the stack and structure return address (if any)
3127 are properly aligned. The stack has to be at least 64-bit
3128 aligned even on 32-bit machines, because doubles must be 64-bit
3129 aligned. For n32 and n64, stack frames need to be 128-bit
3130 aligned, so we round to this widest known alignment. */
3132 sp
= align_down (sp
, 16);
3133 struct_addr
= align_down (struct_addr
, 16);
3135 /* Now make space on the stack for the args. */
3136 for (argnum
= 0; argnum
< nargs
; argnum
++)
3137 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3138 sp
-= align_up (len
, 16);
3141 fprintf_unfiltered (gdb_stdlog
,
3142 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3143 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3145 /* Initialize the integer and float register pointers. */
3146 argreg
= MIPS_A0_REGNUM
;
3147 float_argreg
= mips_fpa0_regnum (gdbarch
);
3149 /* The struct_return pointer occupies the first parameter-passing reg. */
3153 fprintf_unfiltered (gdb_stdlog
,
3154 "mips_n32n64_push_dummy_call: struct_return reg=%d %s\n",
3155 argreg
, paddress (gdbarch
, struct_addr
));
3156 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3159 /* Now load as many as possible of the first arguments into
3160 registers, and push the rest onto the stack. Loop thru args
3161 from first to last. */
3162 for (argnum
= 0; argnum
< nargs
; argnum
++)
3164 const gdb_byte
*val
;
3165 struct value
*arg
= args
[argnum
];
3166 struct type
*arg_type
= check_typedef (value_type (arg
));
3167 int len
= TYPE_LENGTH (arg_type
);
3168 enum type_code typecode
= TYPE_CODE (arg_type
);
3171 fprintf_unfiltered (gdb_stdlog
,
3172 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3173 argnum
+ 1, len
, (int) typecode
);
3175 val
= value_contents (arg
);
3177 /* A 128-bit long double value requires an even-odd pair of
3178 floating-point registers. */
3180 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3181 && (float_argreg
& 1))
3187 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3188 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3190 /* This is a floating point value that fits entirely
3191 in a single register or a pair of registers. */
3192 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3193 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3195 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3196 float_argreg
, phex (regval
, reglen
));
3197 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3200 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3201 argreg
, phex (regval
, reglen
));
3202 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3207 regval
= extract_unsigned_integer (val
+ reglen
,
3208 reglen
, byte_order
);
3210 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3211 float_argreg
, phex (regval
, reglen
));
3212 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3215 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3216 argreg
, phex (regval
, reglen
));
3217 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3224 /* Copy the argument to general registers or the stack in
3225 register-sized pieces. Large arguments are split between
3226 registers and stack. */
3227 /* For N32/N64, structs, unions, or other composite types are
3228 treated as a sequence of doublewords, and are passed in integer
3229 or floating point registers as though they were simple scalar
3230 parameters to the extent that they fit, with any excess on the
3231 stack packed according to the normal memory layout of the
3233 The caller does not reserve space for the register arguments;
3234 the callee is responsible for reserving it if required. */
3235 /* Note: Floating-point values that didn't fit into an FP
3236 register are only written to memory. */
3239 /* Remember if the argument was written to the stack. */
3240 int stack_used_p
= 0;
3241 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3244 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3247 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3248 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3250 /* Write this portion of the argument to the stack. */
3251 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3253 /* Should shorter than int integer values be
3254 promoted to int before being stored? */
3255 int longword_offset
= 0;
3258 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3260 if ((typecode
== TYPE_CODE_INT
3261 || typecode
== TYPE_CODE_PTR
)
3263 longword_offset
= MIPS64_REGSIZE
- len
;
3268 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3269 paddress (gdbarch
, stack_offset
));
3270 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3271 paddress (gdbarch
, longword_offset
));
3274 addr
= sp
+ stack_offset
+ longword_offset
;
3279 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3280 paddress (gdbarch
, addr
));
3281 for (i
= 0; i
< partial_len
; i
++)
3283 fprintf_unfiltered (gdb_stdlog
, "%02x",
3287 write_memory (addr
, val
, partial_len
);
3290 /* Note!!! This is NOT an else clause. Odd sized
3291 structs may go thru BOTH paths. */
3292 /* Write this portion of the argument to a general
3293 purpose register. */
3294 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3298 /* Sign extend pointers, 32-bit integers and signed
3299 16-bit and 8-bit integers; everything else is taken
3302 if ((partial_len
== 4
3303 && (typecode
== TYPE_CODE_PTR
3304 || typecode
== TYPE_CODE_INT
))
3306 && typecode
== TYPE_CODE_INT
3307 && !TYPE_UNSIGNED (arg_type
)))
3308 regval
= extract_signed_integer (val
, partial_len
,
3311 regval
= extract_unsigned_integer (val
, partial_len
,
3314 /* A non-floating-point argument being passed in a
3315 general register. If a struct or union, and if
3316 the remaining length is smaller than the register
3317 size, we have to adjust the register value on
3320 It does not seem to be necessary to do the
3321 same for integral types. */
3323 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3324 && partial_len
< MIPS64_REGSIZE
3325 && (typecode
== TYPE_CODE_STRUCT
3326 || typecode
== TYPE_CODE_UNION
))
3327 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3331 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3333 phex (regval
, MIPS64_REGSIZE
));
3334 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3336 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3337 TYPE_LENGTH (arg_type
) - len
))
3340 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3342 phex (regval
, MIPS64_REGSIZE
));
3343 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3354 /* Compute the the offset into the stack at which we
3355 will copy the next parameter.
3357 In N32 (N64?), the stack_offset only needs to be
3358 adjusted when it has been used. */
3361 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3365 fprintf_unfiltered (gdb_stdlog
, "\n");
3368 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3370 /* Return adjusted stack pointer. */
3374 static enum return_value_convention
3375 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3376 struct type
*type
, struct regcache
*regcache
,
3377 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3379 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3381 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3383 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3384 if needed), as appropriate for the type. Composite results (struct,
3385 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3388 * A struct with only one or two floating point fields is returned in $f0
3389 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3392 * Any other composite results of at most 128 bits are returned in
3393 $2 (first 64 bits) and $3 (remainder, if necessary).
3395 * Larger composite results are handled by converting the function to a
3396 procedure with an implicit first parameter, which is a pointer to an area
3397 reserved by the caller to receive the result. [The o32-bit ABI requires
3398 that all composite results be handled by conversion to implicit first
3399 parameters. The MIPS/SGI Fortran implementation has always made a
3400 specific exception to return COMPLEX results in the floating point
3403 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3404 return RETURN_VALUE_STRUCT_CONVENTION
;
3405 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3406 && TYPE_LENGTH (type
) == 16
3407 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3409 /* A 128-bit floating-point value fills both $f0 and $f2. The
3410 two registers are used in the same as memory order, so the
3411 eight bytes with the lower memory address are in $f0. */
3413 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3414 mips_xfer_register (gdbarch
, regcache
,
3415 gdbarch_num_regs (gdbarch
)
3416 + mips_regnum (gdbarch
)->fp0
,
3417 8, gdbarch_byte_order (gdbarch
),
3418 readbuf
, writebuf
, 0);
3419 mips_xfer_register (gdbarch
, regcache
,
3420 gdbarch_num_regs (gdbarch
)
3421 + mips_regnum (gdbarch
)->fp0
+ 2,
3422 8, gdbarch_byte_order (gdbarch
),
3423 readbuf
? readbuf
+ 8 : readbuf
,
3424 writebuf
? writebuf
+ 8 : writebuf
, 0);
3425 return RETURN_VALUE_REGISTER_CONVENTION
;
3427 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3428 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3430 /* A single or double floating-point value that fits in FP0. */
3432 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3433 mips_xfer_register (gdbarch
, regcache
,
3434 gdbarch_num_regs (gdbarch
)
3435 + mips_regnum (gdbarch
)->fp0
,
3437 gdbarch_byte_order (gdbarch
),
3438 readbuf
, writebuf
, 0);
3439 return RETURN_VALUE_REGISTER_CONVENTION
;
3441 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3442 && TYPE_NFIELDS (type
) <= 2
3443 && TYPE_NFIELDS (type
) >= 1
3444 && ((TYPE_NFIELDS (type
) == 1
3445 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3447 || (TYPE_NFIELDS (type
) == 2
3448 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3450 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3451 == TYPE_CODE_FLT
))))
3453 /* A struct that contains one or two floats. Each value is part
3454 in the least significant part of their floating point
3455 register (or GPR, for soft float). */
3458 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3459 ? mips_regnum (gdbarch
)->fp0
3461 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3463 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3466 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3468 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3470 /* A 16-byte long double field goes in two consecutive
3472 mips_xfer_register (gdbarch
, regcache
,
3473 gdbarch_num_regs (gdbarch
) + regnum
,
3475 gdbarch_byte_order (gdbarch
),
3476 readbuf
, writebuf
, offset
);
3477 mips_xfer_register (gdbarch
, regcache
,
3478 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3480 gdbarch_byte_order (gdbarch
),
3481 readbuf
, writebuf
, offset
+ 8);
3484 mips_xfer_register (gdbarch
, regcache
,
3485 gdbarch_num_regs (gdbarch
) + regnum
,
3486 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3487 gdbarch_byte_order (gdbarch
),
3488 readbuf
, writebuf
, offset
);
3490 return RETURN_VALUE_REGISTER_CONVENTION
;
3492 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3493 || TYPE_CODE (type
) == TYPE_CODE_UNION
3494 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3496 /* A composite type. Extract the left justified value,
3497 regardless of the byte order. I.e. DO NOT USE
3501 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3502 offset
< TYPE_LENGTH (type
);
3503 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3505 int xfer
= register_size (gdbarch
, regnum
);
3506 if (offset
+ xfer
> TYPE_LENGTH (type
))
3507 xfer
= TYPE_LENGTH (type
) - offset
;
3509 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3510 offset
, xfer
, regnum
);
3511 mips_xfer_register (gdbarch
, regcache
,
3512 gdbarch_num_regs (gdbarch
) + regnum
,
3513 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3516 return RETURN_VALUE_REGISTER_CONVENTION
;
3520 /* A scalar extract each part but least-significant-byte
3524 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3525 offset
< TYPE_LENGTH (type
);
3526 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3528 int xfer
= register_size (gdbarch
, regnum
);
3529 if (offset
+ xfer
> TYPE_LENGTH (type
))
3530 xfer
= TYPE_LENGTH (type
) - offset
;
3532 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3533 offset
, xfer
, regnum
);
3534 mips_xfer_register (gdbarch
, regcache
,
3535 gdbarch_num_regs (gdbarch
) + regnum
,
3536 xfer
, gdbarch_byte_order (gdbarch
),
3537 readbuf
, writebuf
, offset
);
3539 return RETURN_VALUE_REGISTER_CONVENTION
;
3543 /* O32 ABI stuff. */
3546 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3547 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3548 int nargs
, struct value
**args
, CORE_ADDR sp
,
3549 int struct_return
, CORE_ADDR struct_addr
)
3555 int stack_offset
= 0;
3556 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3557 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3558 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3560 /* For shared libraries, "t9" needs to point at the function
3562 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3564 /* Set the return address register to point to the entry point of
3565 the program, where a breakpoint lies in wait. */
3566 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3568 /* First ensure that the stack and structure return address (if any)
3569 are properly aligned. The stack has to be at least 64-bit
3570 aligned even on 32-bit machines, because doubles must be 64-bit
3571 aligned. For n32 and n64, stack frames need to be 128-bit
3572 aligned, so we round to this widest known alignment. */
3574 sp
= align_down (sp
, 16);
3575 struct_addr
= align_down (struct_addr
, 16);
3577 /* Now make space on the stack for the args. */
3578 for (argnum
= 0; argnum
< nargs
; argnum
++)
3580 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3581 int arglen
= TYPE_LENGTH (arg_type
);
3583 /* Align to double-word if necessary. */
3584 if (mips_type_needs_double_align (arg_type
))
3585 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3586 /* Allocate space on the stack. */
3587 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3589 sp
-= align_up (len
, 16);
3592 fprintf_unfiltered (gdb_stdlog
,
3593 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3594 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3596 /* Initialize the integer and float register pointers. */
3597 argreg
= MIPS_A0_REGNUM
;
3598 float_argreg
= mips_fpa0_regnum (gdbarch
);
3600 /* The struct_return pointer occupies the first parameter-passing reg. */
3604 fprintf_unfiltered (gdb_stdlog
,
3605 "mips_o32_push_dummy_call: struct_return reg=%d %s\n",
3606 argreg
, paddress (gdbarch
, struct_addr
));
3607 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3608 stack_offset
+= MIPS32_REGSIZE
;
3611 /* Now load as many as possible of the first arguments into
3612 registers, and push the rest onto the stack. Loop thru args
3613 from first to last. */
3614 for (argnum
= 0; argnum
< nargs
; argnum
++)
3616 const gdb_byte
*val
;
3617 struct value
*arg
= args
[argnum
];
3618 struct type
*arg_type
= check_typedef (value_type (arg
));
3619 int len
= TYPE_LENGTH (arg_type
);
3620 enum type_code typecode
= TYPE_CODE (arg_type
);
3623 fprintf_unfiltered (gdb_stdlog
,
3624 "mips_o32_push_dummy_call: %d len=%d type=%d",
3625 argnum
+ 1, len
, (int) typecode
);
3627 val
= value_contents (arg
);
3629 /* 32-bit ABIs always start floating point arguments in an
3630 even-numbered floating point register. Round the FP register
3631 up before the check to see if there are any FP registers
3632 left. O32/O64 targets also pass the FP in the integer
3633 registers so also round up normal registers. */
3634 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3636 if ((float_argreg
& 1))
3640 /* Floating point arguments passed in registers have to be
3641 treated specially. On 32-bit architectures, doubles
3642 are passed in register pairs; the even register gets
3643 the low word, and the odd register gets the high word.
3644 On O32/O64, the first two floating point arguments are
3645 also copied to general registers, because MIPS16 functions
3646 don't use float registers for arguments. This duplication of
3647 arguments in general registers can't hurt non-MIPS16 functions
3648 because those registers are normally skipped. */
3650 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3651 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3653 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3655 int low_offset
= gdbarch_byte_order (gdbarch
)
3656 == BFD_ENDIAN_BIG
? 4 : 0;
3657 unsigned long regval
;
3659 /* Write the low word of the double to the even register(s). */
3660 regval
= extract_unsigned_integer (val
+ low_offset
,
3663 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3664 float_argreg
, phex (regval
, 4));
3665 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3667 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3668 argreg
, phex (regval
, 4));
3669 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3671 /* Write the high word of the double to the odd register(s). */
3672 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3675 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3676 float_argreg
, phex (regval
, 4));
3677 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3680 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3681 argreg
, phex (regval
, 4));
3682 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3686 /* This is a floating point value that fits entirely
3687 in a single register. */
3688 /* On 32 bit ABI's the float_argreg is further adjusted
3689 above to ensure that it is even register aligned. */
3690 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
3692 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3693 float_argreg
, phex (regval
, len
));
3694 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3695 /* Although two FP registers are reserved for each
3696 argument, only one corresponding integer register is
3699 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3700 argreg
, phex (regval
, len
));
3701 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3703 /* Reserve space for the FP register. */
3704 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3708 /* Copy the argument to general registers or the stack in
3709 register-sized pieces. Large arguments are split between
3710 registers and stack. */
3711 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3712 are treated specially: Irix cc passes
3713 them in registers where gcc sometimes puts them on the
3714 stack. For maximum compatibility, we will put them in
3716 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3717 && len
% MIPS32_REGSIZE
!= 0);
3718 /* Structures should be aligned to eight bytes (even arg registers)
3719 on MIPS_ABI_O32, if their first member has double precision. */
3720 if (mips_type_needs_double_align (arg_type
))
3725 stack_offset
+= MIPS32_REGSIZE
;
3730 /* Remember if the argument was written to the stack. */
3731 int stack_used_p
= 0;
3732 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3735 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3738 /* Write this portion of the argument to the stack. */
3739 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3740 || odd_sized_struct
)
3742 /* Should shorter than int integer values be
3743 promoted to int before being stored? */
3744 int longword_offset
= 0;
3750 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3751 paddress (gdbarch
, stack_offset
));
3752 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3753 paddress (gdbarch
, longword_offset
));
3756 addr
= sp
+ stack_offset
+ longword_offset
;
3761 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3762 paddress (gdbarch
, addr
));
3763 for (i
= 0; i
< partial_len
; i
++)
3765 fprintf_unfiltered (gdb_stdlog
, "%02x",
3769 write_memory (addr
, val
, partial_len
);
3772 /* Note!!! This is NOT an else clause. Odd sized
3773 structs may go thru BOTH paths. */
3774 /* Write this portion of the argument to a general
3775 purpose register. */
3776 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3778 LONGEST regval
= extract_signed_integer (val
, partial_len
,
3780 /* Value may need to be sign extended, because
3781 mips_isa_regsize() != mips_abi_regsize(). */
3783 /* A non-floating-point argument being passed in a
3784 general register. If a struct or union, and if
3785 the remaining length is smaller than the register
3786 size, we have to adjust the register value on
3789 It does not seem to be necessary to do the
3790 same for integral types.
3792 Also don't do this adjustment on O64 binaries.
3794 cagney/2001-07-23: gdb/179: Also, GCC, when
3795 outputting LE O32 with sizeof (struct) <
3796 mips_abi_regsize(), generates a left shift
3797 as part of storing the argument in a register
3798 (the left shift isn't generated when
3799 sizeof (struct) >= mips_abi_regsize()). Since
3800 it is quite possible that this is GCC
3801 contradicting the LE/O32 ABI, GDB has not been
3802 adjusted to accommodate this. Either someone
3803 needs to demonstrate that the LE/O32 ABI
3804 specifies such a left shift OR this new ABI gets
3805 identified as such and GDB gets tweaked
3808 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3809 && partial_len
< MIPS32_REGSIZE
3810 && (typecode
== TYPE_CODE_STRUCT
3811 || typecode
== TYPE_CODE_UNION
))
3812 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3816 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3818 phex (regval
, MIPS32_REGSIZE
));
3819 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3822 /* Prevent subsequent floating point arguments from
3823 being passed in floating point registers. */
3824 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
3830 /* Compute the the offset into the stack at which we
3831 will copy the next parameter.
3833 In older ABIs, the caller reserved space for
3834 registers that contained arguments. This was loosely
3835 refered to as their "home". Consequently, space is
3836 always allocated. */
3838 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3842 fprintf_unfiltered (gdb_stdlog
, "\n");
3845 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3847 /* Return adjusted stack pointer. */
3851 static enum return_value_convention
3852 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3853 struct type
*type
, struct regcache
*regcache
,
3854 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3856 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3858 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3859 || TYPE_CODE (type
) == TYPE_CODE_UNION
3860 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3861 return RETURN_VALUE_STRUCT_CONVENTION
;
3862 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3863 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3865 /* A single-precision floating-point value. It fits in the
3866 least significant part of FP0. */
3868 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3869 mips_xfer_register (gdbarch
, regcache
,
3870 gdbarch_num_regs (gdbarch
)
3871 + mips_regnum (gdbarch
)->fp0
,
3873 gdbarch_byte_order (gdbarch
),
3874 readbuf
, writebuf
, 0);
3875 return RETURN_VALUE_REGISTER_CONVENTION
;
3877 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3878 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3880 /* A double-precision floating-point value. The most
3881 significant part goes in FP1, and the least significant in
3884 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3885 switch (gdbarch_byte_order (gdbarch
))
3887 case BFD_ENDIAN_LITTLE
:
3888 mips_xfer_register (gdbarch
, regcache
,
3889 gdbarch_num_regs (gdbarch
)
3890 + mips_regnum (gdbarch
)->fp0
+
3891 0, 4, gdbarch_byte_order (gdbarch
),
3892 readbuf
, writebuf
, 0);
3893 mips_xfer_register (gdbarch
, regcache
,
3894 gdbarch_num_regs (gdbarch
)
3895 + mips_regnum (gdbarch
)->fp0
+ 1,
3896 4, gdbarch_byte_order (gdbarch
),
3897 readbuf
, writebuf
, 4);
3899 case BFD_ENDIAN_BIG
:
3900 mips_xfer_register (gdbarch
, regcache
,
3901 gdbarch_num_regs (gdbarch
)
3902 + mips_regnum (gdbarch
)->fp0
+ 1,
3903 4, gdbarch_byte_order (gdbarch
),
3904 readbuf
, writebuf
, 0);
3905 mips_xfer_register (gdbarch
, regcache
,
3906 gdbarch_num_regs (gdbarch
)
3907 + mips_regnum (gdbarch
)->fp0
+ 0,
3908 4, gdbarch_byte_order (gdbarch
),
3909 readbuf
, writebuf
, 4);
3912 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3914 return RETURN_VALUE_REGISTER_CONVENTION
;
3917 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3918 && TYPE_NFIELDS (type
) <= 2
3919 && TYPE_NFIELDS (type
) >= 1
3920 && ((TYPE_NFIELDS (type
) == 1
3921 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3923 || (TYPE_NFIELDS (type
) == 2
3924 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3926 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3928 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3930 /* A struct that contains one or two floats. Each value is part
3931 in the least significant part of their floating point
3933 gdb_byte reg
[MAX_REGISTER_SIZE
];
3936 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3937 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3939 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3942 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3944 mips_xfer_register (gdbarch
, regcache
,
3945 gdbarch_num_regs (gdbarch
) + regnum
,
3946 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3947 gdbarch_byte_order (gdbarch
),
3948 readbuf
, writebuf
, offset
);
3950 return RETURN_VALUE_REGISTER_CONVENTION
;
3954 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3955 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3957 /* A structure or union. Extract the left justified value,
3958 regardless of the byte order. I.e. DO NOT USE
3962 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3963 offset
< TYPE_LENGTH (type
);
3964 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3966 int xfer
= register_size (gdbarch
, regnum
);
3967 if (offset
+ xfer
> TYPE_LENGTH (type
))
3968 xfer
= TYPE_LENGTH (type
) - offset
;
3970 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3971 offset
, xfer
, regnum
);
3972 mips_xfer_register (gdbarch
, regcache
,
3973 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3974 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3976 return RETURN_VALUE_REGISTER_CONVENTION
;
3981 /* A scalar extract each part but least-significant-byte
3982 justified. o32 thinks registers are 4 byte, regardless of
3986 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3987 offset
< TYPE_LENGTH (type
);
3988 offset
+= MIPS32_REGSIZE
, regnum
++)
3990 int xfer
= MIPS32_REGSIZE
;
3991 if (offset
+ xfer
> TYPE_LENGTH (type
))
3992 xfer
= TYPE_LENGTH (type
) - offset
;
3994 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3995 offset
, xfer
, regnum
);
3996 mips_xfer_register (gdbarch
, regcache
,
3997 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3998 gdbarch_byte_order (gdbarch
),
3999 readbuf
, writebuf
, offset
);
4001 return RETURN_VALUE_REGISTER_CONVENTION
;
4005 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4009 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4010 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4012 struct value
**args
, CORE_ADDR sp
,
4013 int struct_return
, CORE_ADDR struct_addr
)
4019 int stack_offset
= 0;
4020 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4021 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4022 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4024 /* For shared libraries, "t9" needs to point at the function
4026 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4028 /* Set the return address register to point to the entry point of
4029 the program, where a breakpoint lies in wait. */
4030 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4032 /* First ensure that the stack and structure return address (if any)
4033 are properly aligned. The stack has to be at least 64-bit
4034 aligned even on 32-bit machines, because doubles must be 64-bit
4035 aligned. For n32 and n64, stack frames need to be 128-bit
4036 aligned, so we round to this widest known alignment. */
4038 sp
= align_down (sp
, 16);
4039 struct_addr
= align_down (struct_addr
, 16);
4041 /* Now make space on the stack for the args. */
4042 for (argnum
= 0; argnum
< nargs
; argnum
++)
4044 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4045 int arglen
= TYPE_LENGTH (arg_type
);
4047 /* Allocate space on the stack. */
4048 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4050 sp
-= align_up (len
, 16);
4053 fprintf_unfiltered (gdb_stdlog
,
4054 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4055 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4057 /* Initialize the integer and float register pointers. */
4058 argreg
= MIPS_A0_REGNUM
;
4059 float_argreg
= mips_fpa0_regnum (gdbarch
);
4061 /* The struct_return pointer occupies the first parameter-passing reg. */
4065 fprintf_unfiltered (gdb_stdlog
,
4066 "mips_o64_push_dummy_call: struct_return reg=%d %s\n",
4067 argreg
, paddress (gdbarch
, struct_addr
));
4068 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4069 stack_offset
+= MIPS64_REGSIZE
;
4072 /* Now load as many as possible of the first arguments into
4073 registers, and push the rest onto the stack. Loop thru args
4074 from first to last. */
4075 for (argnum
= 0; argnum
< nargs
; argnum
++)
4077 const gdb_byte
*val
;
4078 struct value
*arg
= args
[argnum
];
4079 struct type
*arg_type
= check_typedef (value_type (arg
));
4080 int len
= TYPE_LENGTH (arg_type
);
4081 enum type_code typecode
= TYPE_CODE (arg_type
);
4084 fprintf_unfiltered (gdb_stdlog
,
4085 "mips_o64_push_dummy_call: %d len=%d type=%d",
4086 argnum
+ 1, len
, (int) typecode
);
4088 val
= value_contents (arg
);
4090 /* Floating point arguments passed in registers have to be
4091 treated specially. On 32-bit architectures, doubles
4092 are passed in register pairs; the even register gets
4093 the low word, and the odd register gets the high word.
4094 On O32/O64, the first two floating point arguments are
4095 also copied to general registers, because MIPS16 functions
4096 don't use float registers for arguments. This duplication of
4097 arguments in general registers can't hurt non-MIPS16 functions
4098 because those registers are normally skipped. */
4100 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4101 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4103 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4105 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4106 float_argreg
, phex (regval
, len
));
4107 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4109 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4110 argreg
, phex (regval
, len
));
4111 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4113 /* Reserve space for the FP register. */
4114 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4118 /* Copy the argument to general registers or the stack in
4119 register-sized pieces. Large arguments are split between
4120 registers and stack. */
4121 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4122 are treated specially: Irix cc passes them in registers
4123 where gcc sometimes puts them on the stack. For maximum
4124 compatibility, we will put them in both places. */
4125 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4126 && len
% MIPS64_REGSIZE
!= 0);
4129 /* Remember if the argument was written to the stack. */
4130 int stack_used_p
= 0;
4131 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4134 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4137 /* Write this portion of the argument to the stack. */
4138 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4139 || odd_sized_struct
)
4141 /* Should shorter than int integer values be
4142 promoted to int before being stored? */
4143 int longword_offset
= 0;
4146 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4148 if ((typecode
== TYPE_CODE_INT
4149 || typecode
== TYPE_CODE_PTR
4150 || typecode
== TYPE_CODE_FLT
)
4152 longword_offset
= MIPS64_REGSIZE
- len
;
4157 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4158 paddress (gdbarch
, stack_offset
));
4159 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4160 paddress (gdbarch
, longword_offset
));
4163 addr
= sp
+ stack_offset
+ longword_offset
;
4168 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4169 paddress (gdbarch
, addr
));
4170 for (i
= 0; i
< partial_len
; i
++)
4172 fprintf_unfiltered (gdb_stdlog
, "%02x",
4176 write_memory (addr
, val
, partial_len
);
4179 /* Note!!! This is NOT an else clause. Odd sized
4180 structs may go thru BOTH paths. */
4181 /* Write this portion of the argument to a general
4182 purpose register. */
4183 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4185 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4187 /* Value may need to be sign extended, because
4188 mips_isa_regsize() != mips_abi_regsize(). */
4190 /* A non-floating-point argument being passed in a
4191 general register. If a struct or union, and if
4192 the remaining length is smaller than the register
4193 size, we have to adjust the register value on
4196 It does not seem to be necessary to do the
4197 same for integral types. */
4199 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4200 && partial_len
< MIPS64_REGSIZE
4201 && (typecode
== TYPE_CODE_STRUCT
4202 || typecode
== TYPE_CODE_UNION
))
4203 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4207 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4209 phex (regval
, MIPS64_REGSIZE
));
4210 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4213 /* Prevent subsequent floating point arguments from
4214 being passed in floating point registers. */
4215 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4221 /* Compute the the offset into the stack at which we
4222 will copy the next parameter.
4224 In older ABIs, the caller reserved space for
4225 registers that contained arguments. This was loosely
4226 refered to as their "home". Consequently, space is
4227 always allocated. */
4229 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4233 fprintf_unfiltered (gdb_stdlog
, "\n");
4236 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4238 /* Return adjusted stack pointer. */
4242 static enum return_value_convention
4243 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4244 struct type
*type
, struct regcache
*regcache
,
4245 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4247 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4249 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4250 || TYPE_CODE (type
) == TYPE_CODE_UNION
4251 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4252 return RETURN_VALUE_STRUCT_CONVENTION
;
4253 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4255 /* A floating-point value. It fits in the least significant
4258 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4259 mips_xfer_register (gdbarch
, regcache
,
4260 gdbarch_num_regs (gdbarch
)
4261 + mips_regnum (gdbarch
)->fp0
,
4263 gdbarch_byte_order (gdbarch
),
4264 readbuf
, writebuf
, 0);
4265 return RETURN_VALUE_REGISTER_CONVENTION
;
4269 /* A scalar extract each part but least-significant-byte
4273 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4274 offset
< TYPE_LENGTH (type
);
4275 offset
+= MIPS64_REGSIZE
, regnum
++)
4277 int xfer
= MIPS64_REGSIZE
;
4278 if (offset
+ xfer
> TYPE_LENGTH (type
))
4279 xfer
= TYPE_LENGTH (type
) - offset
;
4281 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4282 offset
, xfer
, regnum
);
4283 mips_xfer_register (gdbarch
, regcache
,
4284 gdbarch_num_regs (gdbarch
) + regnum
,
4285 xfer
, gdbarch_byte_order (gdbarch
),
4286 readbuf
, writebuf
, offset
);
4288 return RETURN_VALUE_REGISTER_CONVENTION
;
4292 /* Floating point register management.
4294 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4295 64bit operations, these early MIPS cpus treat fp register pairs
4296 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4297 registers and offer a compatibility mode that emulates the MIPS2 fp
4298 model. When operating in MIPS2 fp compat mode, later cpu's split
4299 double precision floats into two 32-bit chunks and store them in
4300 consecutive fp regs. To display 64-bit floats stored in this
4301 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4302 Throw in user-configurable endianness and you have a real mess.
4304 The way this works is:
4305 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4306 double-precision value will be split across two logical registers.
4307 The lower-numbered logical register will hold the low-order bits,
4308 regardless of the processor's endianness.
4309 - If we are on a 64-bit processor, and we are looking for a
4310 single-precision value, it will be in the low ordered bits
4311 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4312 save slot in memory.
4313 - If we are in 64-bit mode, everything is straightforward.
4315 Note that this code only deals with "live" registers at the top of the
4316 stack. We will attempt to deal with saved registers later, when
4317 the raw/cooked register interface is in place. (We need a general
4318 interface that can deal with dynamic saved register sizes -- fp
4319 regs could be 32 bits wide in one frame and 64 on the frame above
4322 /* Copy a 32-bit single-precision value from the current frame
4323 into rare_buffer. */
4326 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4327 gdb_byte
*rare_buffer
)
4329 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4330 int raw_size
= register_size (gdbarch
, regno
);
4331 gdb_byte
*raw_buffer
= alloca (raw_size
);
4333 if (!frame_register_read (frame
, regno
, raw_buffer
))
4334 error (_("can't read register %d (%s)"),
4335 regno
, gdbarch_register_name (gdbarch
, regno
));
4338 /* We have a 64-bit value for this register. Find the low-order
4342 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4347 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4351 memcpy (rare_buffer
, raw_buffer
, 4);
4355 /* Copy a 64-bit double-precision value from the current frame into
4356 rare_buffer. This may include getting half of it from the next
4360 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4361 gdb_byte
*rare_buffer
)
4363 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4364 int raw_size
= register_size (gdbarch
, regno
);
4366 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4368 /* We have a 64-bit value for this register, and we should use
4370 if (!frame_register_read (frame
, regno
, rare_buffer
))
4371 error (_("can't read register %d (%s)"),
4372 regno
, gdbarch_register_name (gdbarch
, regno
));
4376 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4378 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4379 internal_error (__FILE__
, __LINE__
,
4380 _("mips_read_fp_register_double: bad access to "
4381 "odd-numbered FP register"));
4383 /* mips_read_fp_register_single will find the correct 32 bits from
4385 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4387 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4388 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4392 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4393 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4399 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4401 { /* do values for FP (float) regs */
4402 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4403 gdb_byte
*raw_buffer
;
4404 double doub
, flt1
; /* doubles extracted from raw hex data */
4407 raw_buffer
= alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
));
4409 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4410 fprintf_filtered (file
, "%*s",
4411 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4414 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4416 struct value_print_options opts
;
4418 /* 4-byte registers: Print hex and floating. Also print even
4419 numbered registers as doubles. */
4420 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4421 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
, raw_buffer
, &inv1
);
4423 get_formatted_print_options (&opts
, 'x');
4424 print_scalar_formatted (raw_buffer
,
4425 builtin_type (gdbarch
)->builtin_uint32
,
4428 fprintf_filtered (file
, " flt: ");
4430 fprintf_filtered (file
, " <invalid float> ");
4432 fprintf_filtered (file
, "%-17.9g", flt1
);
4434 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4436 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4437 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4440 fprintf_filtered (file
, " dbl: ");
4442 fprintf_filtered (file
, "<invalid double>");
4444 fprintf_filtered (file
, "%-24.17g", doub
);
4449 struct value_print_options opts
;
4451 /* Eight byte registers: print each one as hex, float and double. */
4452 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4453 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4456 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4457 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4460 get_formatted_print_options (&opts
, 'x');
4461 print_scalar_formatted (raw_buffer
,
4462 builtin_type (gdbarch
)->builtin_uint64
,
4465 fprintf_filtered (file
, " flt: ");
4467 fprintf_filtered (file
, "<invalid float>");
4469 fprintf_filtered (file
, "%-17.9g", flt1
);
4471 fprintf_filtered (file
, " dbl: ");
4473 fprintf_filtered (file
, "<invalid double>");
4475 fprintf_filtered (file
, "%-24.17g", doub
);
4480 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4483 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4484 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4486 struct value_print_options opts
;
4488 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4490 mips_print_fp_register (file
, frame
, regnum
);
4494 /* Get the data in raw format. */
4495 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4497 fprintf_filtered (file
, "%s: [Invalid]",
4498 gdbarch_register_name (gdbarch
, regnum
));
4502 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4504 /* The problem with printing numeric register names (r26, etc.) is that
4505 the user can't use them on input. Probably the best solution is to
4506 fix it so that either the numeric or the funky (a2, etc.) names
4507 are accepted on input. */
4508 if (regnum
< MIPS_NUMREGS
)
4509 fprintf_filtered (file
, "(r%d): ", regnum
);
4511 fprintf_filtered (file
, ": ");
4513 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4515 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4519 get_formatted_print_options (&opts
, 'x');
4520 print_scalar_formatted (raw_buffer
+ offset
,
4521 register_type (gdbarch
, regnum
), &opts
, 0,
4525 /* Replacement for generic do_registers_info.
4526 Print regs in pretty columns. */
4529 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4532 fprintf_filtered (file
, " ");
4533 mips_print_fp_register (file
, frame
, regnum
);
4534 fprintf_filtered (file
, "\n");
4539 /* Print a row's worth of GP (int) registers, with name labels above */
4542 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4545 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4546 /* do values for GP (int) regs */
4547 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4548 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4552 /* For GP registers, we print a separate row of names above the vals */
4553 for (col
= 0, regnum
= start_regnum
;
4554 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4555 + gdbarch_num_pseudo_regs (gdbarch
);
4558 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4559 continue; /* unused register */
4560 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4562 break; /* end the row: reached FP register */
4563 /* Large registers are handled separately. */
4564 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4567 break; /* End the row before this register. */
4569 /* Print this register on a row by itself. */
4570 mips_print_register (file
, frame
, regnum
);
4571 fprintf_filtered (file
, "\n");
4575 fprintf_filtered (file
, " ");
4576 fprintf_filtered (file
,
4577 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4578 gdbarch_register_name (gdbarch
, regnum
));
4585 /* print the R0 to R31 names */
4586 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4587 fprintf_filtered (file
, "\n R%-4d",
4588 start_regnum
% gdbarch_num_regs (gdbarch
));
4590 fprintf_filtered (file
, "\n ");
4592 /* now print the values in hex, 4 or 8 to the row */
4593 for (col
= 0, regnum
= start_regnum
;
4594 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4595 + gdbarch_num_pseudo_regs (gdbarch
);
4598 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4599 continue; /* unused register */
4600 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4602 break; /* end row: reached FP register */
4603 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4604 break; /* End row: large register. */
4606 /* OK: get the data in raw format. */
4607 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4608 error (_("can't read register %d (%s)"),
4609 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4610 /* pad small registers */
4612 byte
< (mips_abi_regsize (gdbarch
)
4613 - register_size (gdbarch
, regnum
)); byte
++)
4614 printf_filtered (" ");
4615 /* Now print the register value in hex, endian order. */
4616 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4618 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4619 byte
< register_size (gdbarch
, regnum
); byte
++)
4620 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4622 for (byte
= register_size (gdbarch
, regnum
) - 1;
4624 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4625 fprintf_filtered (file
, " ");
4628 if (col
> 0) /* ie. if we actually printed anything... */
4629 fprintf_filtered (file
, "\n");
4634 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4637 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4638 struct frame_info
*frame
, int regnum
, int all
)
4640 if (regnum
!= -1) /* do one specified register */
4642 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4643 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4644 error (_("Not a valid register for the current processor type"));
4646 mips_print_register (file
, frame
, regnum
);
4647 fprintf_filtered (file
, "\n");
4650 /* do all (or most) registers */
4652 regnum
= gdbarch_num_regs (gdbarch
);
4653 while (regnum
< gdbarch_num_regs (gdbarch
)
4654 + gdbarch_num_pseudo_regs (gdbarch
))
4656 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4659 if (all
) /* true for "INFO ALL-REGISTERS" command */
4660 regnum
= print_fp_register_row (file
, frame
, regnum
);
4662 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4665 regnum
= print_gp_register_row (file
, frame
, regnum
);
4670 /* Is this a branch with a delay slot? */
4673 is_delayed (unsigned long insn
)
4676 for (i
= 0; i
< NUMOPCODES
; ++i
)
4677 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4678 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4680 return (i
< NUMOPCODES
4681 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4682 | INSN_COND_BRANCH_DELAY
4683 | INSN_COND_BRANCH_LIKELY
)));
4687 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4688 struct frame_info
*frame
)
4690 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4691 CORE_ADDR pc
= get_frame_pc (frame
);
4692 gdb_byte buf
[MIPS_INSN32_SIZE
];
4694 /* There is no branch delay slot on MIPS16. */
4695 if (mips_pc_is_mips16 (pc
))
4698 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
4701 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4702 /* If error reading memory, guess that it is not a delayed
4705 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
4708 /* To skip prologues, I use this predicate. Returns either PC itself
4709 if the code at PC does not look like a function prologue; otherwise
4710 returns an address that (if we're lucky) follows the prologue. If
4711 LENIENT, then we must skip everything which is involved in setting
4712 up the frame (it's OK to skip more, just so long as we don't skip
4713 anything which might clobber the registers which are being saved.
4714 We must skip more in the case where part of the prologue is in the
4715 delay slot of a non-prologue instruction). */
4718 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4721 CORE_ADDR func_addr
;
4723 /* See if we can determine the end of the prologue via the symbol table.
4724 If so, then return either PC, or the PC after the prologue, whichever
4726 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4728 CORE_ADDR post_prologue_pc
4729 = skip_prologue_using_sal (gdbarch
, func_addr
);
4730 if (post_prologue_pc
!= 0)
4731 return max (pc
, post_prologue_pc
);
4734 /* Can't determine prologue from the symbol table, need to examine
4737 /* Find an upper limit on the function prologue using the debug
4738 information. If the debug information could not be used to provide
4739 that bound, then use an arbitrary large number as the upper bound. */
4740 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
4742 limit_pc
= pc
+ 100; /* Magic. */
4744 if (mips_pc_is_mips16 (pc
))
4745 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4747 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4750 /* Check whether the PC is in a function epilogue (32-bit version).
4751 This is a helper function for mips_in_function_epilogue_p. */
4753 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4755 CORE_ADDR func_addr
= 0, func_end
= 0;
4757 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4759 /* The MIPS epilogue is max. 12 bytes long. */
4760 CORE_ADDR addr
= func_end
- 12;
4762 if (addr
< func_addr
+ 4)
4763 addr
= func_addr
+ 4;
4767 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4769 unsigned long high_word
;
4772 inst
= mips_fetch_instruction (gdbarch
, pc
);
4773 high_word
= (inst
>> 16) & 0xffff;
4775 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4776 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4777 && inst
!= 0x03e00008 /* jr $ra */
4778 && inst
!= 0x00000000) /* nop */
4788 /* Check whether the PC is in a function epilogue (16-bit version).
4789 This is a helper function for mips_in_function_epilogue_p. */
4791 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4793 CORE_ADDR func_addr
= 0, func_end
= 0;
4795 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4797 /* The MIPS epilogue is max. 12 bytes long. */
4798 CORE_ADDR addr
= func_end
- 12;
4800 if (addr
< func_addr
+ 4)
4801 addr
= func_addr
+ 4;
4805 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4807 unsigned short inst
;
4809 inst
= mips_fetch_instruction (gdbarch
, pc
);
4811 if ((inst
& 0xf800) == 0xf000) /* extend */
4814 if (inst
!= 0x6300 /* addiu $sp,offset */
4815 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
4816 && inst
!= 0xe820 /* jr $ra */
4817 && inst
!= 0xe8a0 /* jrc $ra */
4818 && inst
!= 0x6500) /* nop */
4828 /* The epilogue is defined here as the area at the end of a function,
4829 after an instruction which destroys the function's stack frame. */
4831 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4833 if (mips_pc_is_mips16 (pc
))
4834 return mips16_in_function_epilogue_p (gdbarch
, pc
);
4836 return mips32_in_function_epilogue_p (gdbarch
, pc
);
4839 /* Root of all "set mips "/"show mips " commands. This will eventually be
4840 used for all MIPS-specific commands. */
4843 show_mips_command (char *args
, int from_tty
)
4845 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4849 set_mips_command (char *args
, int from_tty
)
4852 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4853 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4856 /* Commands to show/set the MIPS FPU type. */
4859 show_mipsfpu_command (char *args
, int from_tty
)
4863 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
4866 ("The MIPS floating-point coprocessor is unknown "
4867 "because the current architecture is not MIPS.\n");
4871 switch (MIPS_FPU_TYPE (target_gdbarch
))
4873 case MIPS_FPU_SINGLE
:
4874 fpu
= "single-precision";
4876 case MIPS_FPU_DOUBLE
:
4877 fpu
= "double-precision";
4880 fpu
= "absent (none)";
4883 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4885 if (mips_fpu_type_auto
)
4887 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4891 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4896 set_mipsfpu_command (char *args
, int from_tty
)
4899 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4900 show_mipsfpu_command (args
, from_tty
);
4904 set_mipsfpu_single_command (char *args
, int from_tty
)
4906 struct gdbarch_info info
;
4907 gdbarch_info_init (&info
);
4908 mips_fpu_type
= MIPS_FPU_SINGLE
;
4909 mips_fpu_type_auto
= 0;
4910 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4911 instead of relying on globals. Doing that would let generic code
4912 handle the search for this specific architecture. */
4913 if (!gdbarch_update_p (info
))
4914 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4918 set_mipsfpu_double_command (char *args
, int from_tty
)
4920 struct gdbarch_info info
;
4921 gdbarch_info_init (&info
);
4922 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4923 mips_fpu_type_auto
= 0;
4924 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4925 instead of relying on globals. Doing that would let generic code
4926 handle the search for this specific architecture. */
4927 if (!gdbarch_update_p (info
))
4928 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4932 set_mipsfpu_none_command (char *args
, int from_tty
)
4934 struct gdbarch_info info
;
4935 gdbarch_info_init (&info
);
4936 mips_fpu_type
= MIPS_FPU_NONE
;
4937 mips_fpu_type_auto
= 0;
4938 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4939 instead of relying on globals. Doing that would let generic code
4940 handle the search for this specific architecture. */
4941 if (!gdbarch_update_p (info
))
4942 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4946 set_mipsfpu_auto_command (char *args
, int from_tty
)
4948 mips_fpu_type_auto
= 1;
4951 /* Attempt to identify the particular processor model by reading the
4952 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4953 the relevant processor still exists (it dates back to '94) and
4954 secondly this is not the way to do this. The processor type should
4955 be set by forcing an architecture change. */
4958 deprecated_mips_set_processor_regs_hack (void)
4960 struct regcache
*regcache
= get_current_regcache ();
4961 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
4962 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4965 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
4966 if ((prid
& ~0xf) == 0x700)
4967 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4970 /* Just like reinit_frame_cache, but with the right arguments to be
4971 callable as an sfunc. */
4974 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4975 struct cmd_list_element
*c
)
4977 reinit_frame_cache ();
4981 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4983 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4984 disassembler needs to be able to locally determine the ISA, and
4985 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4987 if (mips_pc_is_mips16 (memaddr
))
4988 info
->mach
= bfd_mach_mips16
;
4990 /* Round down the instruction address to the appropriate boundary. */
4991 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4993 /* Set the disassembler options. */
4994 if (!info
->disassembler_options
)
4995 /* This string is not recognized explicitly by the disassembler,
4996 but it tells the disassembler to not try to guess the ABI from
4997 the bfd elf headers, such that, if the user overrides the ABI
4998 of a program linked as NewABI, the disassembly will follow the
4999 register naming conventions specified by the user. */
5000 info
->disassembler_options
= "gpr-names=32";
5002 /* Call the appropriate disassembler based on the target endian-ness. */
5003 if (info
->endian
== BFD_ENDIAN_BIG
)
5004 return print_insn_big_mips (memaddr
, info
);
5006 return print_insn_little_mips (memaddr
, info
);
5010 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5012 /* Set up the disassembler info, so that we get the right
5013 register names from libopcodes. */
5014 info
->disassembler_options
= "gpr-names=n32";
5015 info
->flavour
= bfd_target_elf_flavour
;
5017 return gdb_print_insn_mips (memaddr
, info
);
5021 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5023 /* Set up the disassembler info, so that we get the right
5024 register names from libopcodes. */
5025 info
->disassembler_options
= "gpr-names=64";
5026 info
->flavour
= bfd_target_elf_flavour
;
5028 return gdb_print_insn_mips (memaddr
, info
);
5031 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
5032 counter value to determine whether a 16- or 32-bit breakpoint should be used.
5033 It returns a pointer to a string of bytes that encode a breakpoint
5034 instruction, stores the length of the string to *lenptr, and adjusts pc (if
5035 necessary) to point to the actual memory location where the breakpoint
5036 should be inserted. */
5038 static const gdb_byte
*
5039 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
5041 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5043 if (mips_pc_is_mips16 (*pcptr
))
5045 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5046 *pcptr
= unmake_mips16_addr (*pcptr
);
5047 *lenptr
= sizeof (mips16_big_breakpoint
);
5048 return mips16_big_breakpoint
;
5052 /* The IDT board uses an unusual breakpoint value, and
5053 sometimes gets confused when it sees the usual MIPS
5054 breakpoint instruction. */
5055 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5056 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5057 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5058 /* Likewise, IRIX appears to expect a different breakpoint,
5059 although this is not apparent until you try to use pthreads. */
5060 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5062 *lenptr
= sizeof (big_breakpoint
);
5064 if (strcmp (target_shortname
, "mips") == 0)
5065 return idt_big_breakpoint
;
5066 else if (strcmp (target_shortname
, "ddb") == 0
5067 || strcmp (target_shortname
, "pmon") == 0
5068 || strcmp (target_shortname
, "lsi") == 0)
5069 return pmon_big_breakpoint
;
5070 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5071 return irix_big_breakpoint
;
5073 return big_breakpoint
;
5078 if (mips_pc_is_mips16 (*pcptr
))
5080 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5081 *pcptr
= unmake_mips16_addr (*pcptr
);
5082 *lenptr
= sizeof (mips16_little_breakpoint
);
5083 return mips16_little_breakpoint
;
5087 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5088 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5089 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5091 *lenptr
= sizeof (little_breakpoint
);
5093 if (strcmp (target_shortname
, "mips") == 0)
5094 return idt_little_breakpoint
;
5095 else if (strcmp (target_shortname
, "ddb") == 0
5096 || strcmp (target_shortname
, "pmon") == 0
5097 || strcmp (target_shortname
, "lsi") == 0)
5098 return pmon_little_breakpoint
;
5100 return little_breakpoint
;
5105 /* If PC is in a mips16 call or return stub, return the address of the target
5106 PC, which is either the callee or the caller. There are several
5107 cases which must be handled:
5109 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5110 target PC is in $31 ($ra).
5111 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5112 and the target PC is in $2.
5113 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5114 before the jal instruction, this is effectively a call stub
5115 and the the target PC is in $2. Otherwise this is effectively
5116 a return stub and the target PC is in $18.
5118 See the source code for the stubs in gcc/config/mips/mips16.S for
5122 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5124 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5126 CORE_ADDR start_addr
;
5128 /* Find the starting address and name of the function containing the PC. */
5129 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5132 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5133 target PC is in $31 ($ra). */
5134 if (strcmp (name
, "__mips16_ret_sf") == 0
5135 || strcmp (name
, "__mips16_ret_df") == 0)
5136 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5138 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5140 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5141 and the target PC is in $2. */
5142 if (name
[19] >= '0' && name
[19] <= '9')
5143 return get_frame_register_signed (frame
, 2);
5145 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5146 before the jal instruction, this is effectively a call stub
5147 and the the target PC is in $2. Otherwise this is effectively
5148 a return stub and the target PC is in $18. */
5149 else if (name
[19] == 's' || name
[19] == 'd')
5151 if (pc
== start_addr
)
5153 /* Check if the target of the stub is a compiler-generated
5154 stub. Such a stub for a function bar might have a name
5155 like __fn_stub_bar, and might look like this:
5160 la $1,bar (becomes a lui/addiu pair)
5162 So scan down to the lui/addi and extract the target
5163 address from those two instructions. */
5165 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5169 /* See if the name of the target function is __fn_stub_*. */
5170 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5173 if (strncmp (name
, "__fn_stub_", 10) != 0
5174 && strcmp (name
, "etext") != 0
5175 && strcmp (name
, "_etext") != 0)
5178 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5179 The limit on the search is arbitrarily set to 20
5180 instructions. FIXME. */
5181 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5183 inst
= mips_fetch_instruction (gdbarch
, target_pc
);
5184 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5185 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5186 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5187 return pc
| (inst
& 0xffff); /* low word */
5190 /* Couldn't find the lui/addui pair, so return stub address. */
5194 /* This is the 'return' part of a call stub. The return
5195 address is in $r18. */
5196 return get_frame_register_signed (frame
, 18);
5199 return 0; /* not a stub */
5202 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5203 PC of the stub target. The stub just loads $t9 and jumps to it,
5204 so that $t9 has the correct value at function entry. */
5207 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5209 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5210 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5211 struct minimal_symbol
*msym
;
5213 gdb_byte stub_code
[16];
5214 int32_t stub_words
[4];
5216 /* The stub for foo is named ".pic.foo", and is either two
5217 instructions inserted before foo or a three instruction sequence
5218 which jumps to foo. */
5219 msym
= lookup_minimal_symbol_by_pc (pc
);
5221 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5222 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5223 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5226 /* A two-instruction header. */
5227 if (MSYMBOL_SIZE (msym
) == 8)
5230 /* A three-instruction (plus delay slot) trampoline. */
5231 if (MSYMBOL_SIZE (msym
) == 16)
5233 if (target_read_memory (pc
, stub_code
, 16) != 0)
5235 for (i
= 0; i
< 4; i
++)
5236 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
5239 /* A stub contains these instructions:
5242 addiu t9, t9, %lo(target)
5245 This works even for N64, since stubs are only generated with
5247 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5248 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5249 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5250 && stub_words
[3] == 0x00000000)
5251 return (((stub_words
[0] & 0x0000ffff) << 16)
5252 + (stub_words
[2] & 0x0000ffff));
5255 /* Not a recognized stub. */
5260 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5262 CORE_ADDR target_pc
;
5264 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5268 target_pc
= find_solib_trampoline_target (frame
, pc
);
5272 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5279 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5280 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5283 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5286 if (num
>= 0 && num
< 32)
5288 else if (num
>= 38 && num
< 70)
5289 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5291 regnum
= mips_regnum (gdbarch
)->hi
;
5293 regnum
= mips_regnum (gdbarch
)->lo
;
5295 /* This will hopefully (eventually) provoke a warning. Should
5296 we be calling complaint() here? */
5297 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5298 return gdbarch_num_regs (gdbarch
) + regnum
;
5302 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5303 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5306 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5309 if (num
>= 0 && num
< 32)
5311 else if (num
>= 32 && num
< 64)
5312 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5314 regnum
= mips_regnum (gdbarch
)->hi
;
5316 regnum
= mips_regnum (gdbarch
)->lo
;
5318 /* This will hopefully (eventually) provoke a warning. Should we
5319 be calling complaint() here? */
5320 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5321 return gdbarch_num_regs (gdbarch
) + regnum
;
5325 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5327 /* Only makes sense to supply raw registers. */
5328 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5329 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5330 decide if it is valid. Should instead define a standard sim/gdb
5331 register numbering scheme. */
5332 if (gdbarch_register_name (gdbarch
,
5333 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5334 && gdbarch_register_name (gdbarch
,
5335 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
5338 return LEGACY_SIM_REGNO_IGNORE
;
5342 /* Convert an integer into an address. Extracting the value signed
5343 guarantees a correctly sign extended address. */
5346 mips_integer_to_address (struct gdbarch
*gdbarch
,
5347 struct type
*type
, const gdb_byte
*buf
)
5349 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5350 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
5353 /* Dummy virtual frame pointer method. This is no more or less accurate
5354 than most other architectures; we just need to be explicit about it,
5355 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5356 an assertion failure. */
5359 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5360 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5362 *reg
= MIPS_SP_REGNUM
;
5367 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5369 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5370 const char *name
= bfd_get_section_name (abfd
, sect
);
5372 if (*abip
!= MIPS_ABI_UNKNOWN
)
5375 if (strncmp (name
, ".mdebug.", 8) != 0)
5378 if (strcmp (name
, ".mdebug.abi32") == 0)
5379 *abip
= MIPS_ABI_O32
;
5380 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5381 *abip
= MIPS_ABI_N32
;
5382 else if (strcmp (name
, ".mdebug.abi64") == 0)
5383 *abip
= MIPS_ABI_N64
;
5384 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5385 *abip
= MIPS_ABI_O64
;
5386 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5387 *abip
= MIPS_ABI_EABI32
;
5388 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5389 *abip
= MIPS_ABI_EABI64
;
5391 warning (_("unsupported ABI %s."), name
+ 8);
5395 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5397 int *lbp
= (int *) obj
;
5398 const char *name
= bfd_get_section_name (abfd
, sect
);
5400 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5402 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5404 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5405 warning (_("unrecognized .gcc_compiled_longXX"));
5408 static enum mips_abi
5409 global_mips_abi (void)
5413 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5414 if (mips_abi_strings
[i
] == mips_abi_string
)
5415 return (enum mips_abi
) i
;
5417 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5421 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5423 /* If the size matches the set of 32-bit or 64-bit integer registers,
5424 assume that's what we've got. */
5425 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5426 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5428 /* If the size matches the full set of registers GDB traditionally
5429 knows about, including floating point, for either 32-bit or
5430 64-bit, assume that's what we've got. */
5431 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5432 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5434 /* Otherwise we don't have a useful guess. */
5437 static struct value
*
5438 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5440 const int *reg_p
= baton
;
5441 return value_of_register (*reg_p
, frame
);
5444 static struct gdbarch
*
5445 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5447 struct gdbarch
*gdbarch
;
5448 struct gdbarch_tdep
*tdep
;
5450 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5452 enum mips_fpu_type fpu_type
;
5453 struct tdesc_arch_data
*tdesc_data
= NULL
;
5454 int elf_fpu_type
= 0;
5456 /* Check any target description for validity. */
5457 if (tdesc_has_registers (info
.target_desc
))
5459 static const char *const mips_gprs
[] = {
5460 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5461 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5462 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5463 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5465 static const char *const mips_fprs
[] = {
5466 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5467 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5468 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5469 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5472 const struct tdesc_feature
*feature
;
5475 feature
= tdesc_find_feature (info
.target_desc
,
5476 "org.gnu.gdb.mips.cpu");
5477 if (feature
== NULL
)
5480 tdesc_data
= tdesc_data_alloc ();
5483 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5484 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5488 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5489 MIPS_EMBED_LO_REGNUM
, "lo");
5490 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5491 MIPS_EMBED_HI_REGNUM
, "hi");
5492 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5493 MIPS_EMBED_PC_REGNUM
, "pc");
5497 tdesc_data_cleanup (tdesc_data
);
5501 feature
= tdesc_find_feature (info
.target_desc
,
5502 "org.gnu.gdb.mips.cp0");
5503 if (feature
== NULL
)
5505 tdesc_data_cleanup (tdesc_data
);
5510 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5511 MIPS_EMBED_BADVADDR_REGNUM
,
5513 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5514 MIPS_PS_REGNUM
, "status");
5515 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5516 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5520 tdesc_data_cleanup (tdesc_data
);
5524 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5525 backend is not prepared for that, though. */
5526 feature
= tdesc_find_feature (info
.target_desc
,
5527 "org.gnu.gdb.mips.fpu");
5528 if (feature
== NULL
)
5530 tdesc_data_cleanup (tdesc_data
);
5535 for (i
= 0; i
< 32; i
++)
5536 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5537 i
+ MIPS_EMBED_FP0_REGNUM
,
5540 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5541 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5542 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5543 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5547 tdesc_data_cleanup (tdesc_data
);
5551 /* It would be nice to detect an attempt to use a 64-bit ABI
5552 when only 32-bit registers are provided. */
5555 /* First of all, extract the elf_flags, if available. */
5556 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5557 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5558 else if (arches
!= NULL
)
5559 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5563 fprintf_unfiltered (gdb_stdlog
,
5564 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5566 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5567 switch ((elf_flags
& EF_MIPS_ABI
))
5569 case E_MIPS_ABI_O32
:
5570 found_abi
= MIPS_ABI_O32
;
5572 case E_MIPS_ABI_O64
:
5573 found_abi
= MIPS_ABI_O64
;
5575 case E_MIPS_ABI_EABI32
:
5576 found_abi
= MIPS_ABI_EABI32
;
5578 case E_MIPS_ABI_EABI64
:
5579 found_abi
= MIPS_ABI_EABI64
;
5582 if ((elf_flags
& EF_MIPS_ABI2
))
5583 found_abi
= MIPS_ABI_N32
;
5585 found_abi
= MIPS_ABI_UNKNOWN
;
5589 /* GCC creates a pseudo-section whose name describes the ABI. */
5590 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5591 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5593 /* If we have no useful BFD information, use the ABI from the last
5594 MIPS architecture (if there is one). */
5595 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5596 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5598 /* Try the architecture for any hint of the correct ABI. */
5599 if (found_abi
== MIPS_ABI_UNKNOWN
5600 && info
.bfd_arch_info
!= NULL
5601 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5603 switch (info
.bfd_arch_info
->mach
)
5605 case bfd_mach_mips3900
:
5606 found_abi
= MIPS_ABI_EABI32
;
5608 case bfd_mach_mips4100
:
5609 case bfd_mach_mips5000
:
5610 found_abi
= MIPS_ABI_EABI64
;
5612 case bfd_mach_mips8000
:
5613 case bfd_mach_mips10000
:
5614 /* On Irix, ELF64 executables use the N64 ABI. The
5615 pseudo-sections which describe the ABI aren't present
5616 on IRIX. (Even for executables created by gcc.) */
5617 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5618 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5619 found_abi
= MIPS_ABI_N64
;
5621 found_abi
= MIPS_ABI_N32
;
5626 /* Default 64-bit objects to N64 instead of O32. */
5627 if (found_abi
== MIPS_ABI_UNKNOWN
5628 && info
.abfd
!= NULL
5629 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5630 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5631 found_abi
= MIPS_ABI_N64
;
5634 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5637 /* What has the user specified from the command line? */
5638 wanted_abi
= global_mips_abi ();
5640 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5643 /* Now that we have found what the ABI for this binary would be,
5644 check whether the user is overriding it. */
5645 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5646 mips_abi
= wanted_abi
;
5647 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5648 mips_abi
= found_abi
;
5650 mips_abi
= MIPS_ABI_O32
;
5652 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5655 /* Also used when doing an architecture lookup. */
5657 fprintf_unfiltered (gdb_stdlog
,
5658 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5659 mips64_transfers_32bit_regs_p
);
5661 /* Determine the MIPS FPU type. */
5664 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5665 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5666 Tag_GNU_MIPS_ABI_FP
);
5667 #endif /* HAVE_ELF */
5669 if (!mips_fpu_type_auto
)
5670 fpu_type
= mips_fpu_type
;
5671 else if (elf_fpu_type
!= 0)
5673 switch (elf_fpu_type
)
5676 fpu_type
= MIPS_FPU_DOUBLE
;
5679 fpu_type
= MIPS_FPU_SINGLE
;
5683 /* Soft float or unknown. */
5684 fpu_type
= MIPS_FPU_NONE
;
5688 else if (info
.bfd_arch_info
!= NULL
5689 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5690 switch (info
.bfd_arch_info
->mach
)
5692 case bfd_mach_mips3900
:
5693 case bfd_mach_mips4100
:
5694 case bfd_mach_mips4111
:
5695 case bfd_mach_mips4120
:
5696 fpu_type
= MIPS_FPU_NONE
;
5698 case bfd_mach_mips4650
:
5699 fpu_type
= MIPS_FPU_SINGLE
;
5702 fpu_type
= MIPS_FPU_DOUBLE
;
5705 else if (arches
!= NULL
)
5706 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5708 fpu_type
= MIPS_FPU_DOUBLE
;
5710 fprintf_unfiltered (gdb_stdlog
,
5711 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5713 /* Check for blatant incompatibilities. */
5715 /* If we have only 32-bit registers, then we can't debug a 64-bit
5717 if (info
.target_desc
5718 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5719 && mips_abi
!= MIPS_ABI_EABI32
5720 && mips_abi
!= MIPS_ABI_O32
)
5722 if (tdesc_data
!= NULL
)
5723 tdesc_data_cleanup (tdesc_data
);
5727 /* try to find a pre-existing architecture */
5728 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5730 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5732 /* MIPS needs to be pedantic about which ABI the object is
5734 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5736 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5738 /* Need to be pedantic about which register virtual size is
5740 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5741 != mips64_transfers_32bit_regs_p
)
5743 /* Be pedantic about which FPU is selected. */
5744 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5747 if (tdesc_data
!= NULL
)
5748 tdesc_data_cleanup (tdesc_data
);
5749 return arches
->gdbarch
;
5752 /* Need a new architecture. Fill in a target specific vector. */
5753 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5754 gdbarch
= gdbarch_alloc (&info
, tdep
);
5755 tdep
->elf_flags
= elf_flags
;
5756 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5757 tdep
->found_abi
= found_abi
;
5758 tdep
->mips_abi
= mips_abi
;
5759 tdep
->mips_fpu_type
= fpu_type
;
5760 tdep
->register_size_valid_p
= 0;
5761 tdep
->register_size
= 0;
5762 tdep
->gregset
= NULL
;
5763 tdep
->gregset64
= NULL
;
5764 tdep
->fpregset
= NULL
;
5765 tdep
->fpregset64
= NULL
;
5767 if (info
.target_desc
)
5769 /* Some useful properties can be inferred from the target. */
5770 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5772 tdep
->register_size_valid_p
= 1;
5773 tdep
->register_size
= 4;
5775 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5777 tdep
->register_size_valid_p
= 1;
5778 tdep
->register_size
= 8;
5782 /* Initially set everything according to the default ABI/ISA. */
5783 set_gdbarch_short_bit (gdbarch
, 16);
5784 set_gdbarch_int_bit (gdbarch
, 32);
5785 set_gdbarch_float_bit (gdbarch
, 32);
5786 set_gdbarch_double_bit (gdbarch
, 64);
5787 set_gdbarch_long_double_bit (gdbarch
, 64);
5788 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5789 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5790 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5792 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5793 mips_elf_make_msymbol_special
);
5795 /* Fill in the OS dependant register numbers and names. */
5797 const char **reg_names
;
5798 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5799 struct mips_regnum
);
5800 if (tdesc_has_registers (info
.target_desc
))
5802 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5803 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5804 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5805 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5806 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5807 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5808 regnum
->fp_control_status
= 70;
5809 regnum
->fp_implementation_revision
= 71;
5810 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5813 else if (info
.osabi
== GDB_OSABI_IRIX
)
5818 regnum
->badvaddr
= 66;
5821 regnum
->fp_control_status
= 69;
5822 regnum
->fp_implementation_revision
= 70;
5824 reg_names
= mips_irix_reg_names
;
5828 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5829 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5830 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5831 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5832 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5833 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5834 regnum
->fp_control_status
= 70;
5835 regnum
->fp_implementation_revision
= 71;
5837 if (info
.bfd_arch_info
!= NULL
5838 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5839 reg_names
= mips_tx39_reg_names
;
5841 reg_names
= mips_generic_reg_names
;
5843 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5844 replaced by gdbarch_read_pc? */
5845 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5846 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5847 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5848 set_gdbarch_num_regs (gdbarch
, num_regs
);
5849 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5850 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5851 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
5852 tdep
->mips_processor_reg_names
= reg_names
;
5853 tdep
->regnum
= regnum
;
5859 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5860 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5861 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5862 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5863 tdep
->default_mask_address_p
= 0;
5864 set_gdbarch_long_bit (gdbarch
, 32);
5865 set_gdbarch_ptr_bit (gdbarch
, 32);
5866 set_gdbarch_long_long_bit (gdbarch
, 64);
5869 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5870 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5871 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5872 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5873 tdep
->default_mask_address_p
= 0;
5874 set_gdbarch_long_bit (gdbarch
, 32);
5875 set_gdbarch_ptr_bit (gdbarch
, 32);
5876 set_gdbarch_long_long_bit (gdbarch
, 64);
5878 case MIPS_ABI_EABI32
:
5879 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5880 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5881 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5882 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5883 tdep
->default_mask_address_p
= 0;
5884 set_gdbarch_long_bit (gdbarch
, 32);
5885 set_gdbarch_ptr_bit (gdbarch
, 32);
5886 set_gdbarch_long_long_bit (gdbarch
, 64);
5888 case MIPS_ABI_EABI64
:
5889 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5890 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5891 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5892 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5893 tdep
->default_mask_address_p
= 0;
5894 set_gdbarch_long_bit (gdbarch
, 64);
5895 set_gdbarch_ptr_bit (gdbarch
, 64);
5896 set_gdbarch_long_long_bit (gdbarch
, 64);
5899 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5900 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5901 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5902 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5903 tdep
->default_mask_address_p
= 0;
5904 set_gdbarch_long_bit (gdbarch
, 32);
5905 set_gdbarch_ptr_bit (gdbarch
, 32);
5906 set_gdbarch_long_long_bit (gdbarch
, 64);
5907 set_gdbarch_long_double_bit (gdbarch
, 128);
5908 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5911 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5912 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5913 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5914 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5915 tdep
->default_mask_address_p
= 0;
5916 set_gdbarch_long_bit (gdbarch
, 64);
5917 set_gdbarch_ptr_bit (gdbarch
, 64);
5918 set_gdbarch_long_long_bit (gdbarch
, 64);
5919 set_gdbarch_long_double_bit (gdbarch
, 128);
5920 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5923 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5926 /* GCC creates a pseudo-section whose name specifies the size of
5927 longs, since -mlong32 or -mlong64 may be used independent of
5928 other options. How those options affect pointer sizes is ABI and
5929 architecture dependent, so use them to override the default sizes
5930 set by the ABI. This table shows the relationship between ABI,
5931 -mlongXX, and size of pointers:
5933 ABI -mlongXX ptr bits
5934 --- -------- --------
5948 Note that for o32 and eabi32, pointers are always 32 bits
5949 regardless of any -mlongXX option. For all others, pointers and
5950 longs are the same, as set by -mlongXX or set by defaults.
5953 if (info
.abfd
!= NULL
)
5957 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5960 set_gdbarch_long_bit (gdbarch
, long_bit
);
5964 case MIPS_ABI_EABI32
:
5969 case MIPS_ABI_EABI64
:
5970 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5973 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5978 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5979 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5982 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5983 flag in object files because to do so would make it impossible to
5984 link with libraries compiled without "-gp32". This is
5985 unnecessarily restrictive.
5987 We could solve this problem by adding "-gp32" multilibs to gcc,
5988 but to set this flag before gcc is built with such multilibs will
5989 break too many systems.''
5991 But even more unhelpfully, the default linker output target for
5992 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5993 for 64-bit programs - you need to change the ABI to change this,
5994 and not all gcc targets support that currently. Therefore using
5995 this flag to detect 32-bit mode would do the wrong thing given
5996 the current gcc - it would make GDB treat these 64-bit programs
5997 as 32-bit programs by default. */
5999 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6000 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6002 /* Add/remove bits from an address. The MIPS needs be careful to
6003 ensure that all 32 bit addresses are sign extended to 64 bits. */
6004 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6006 /* Unwind the frame. */
6007 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6008 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
6009 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
6011 /* Map debug register numbers onto internal register numbers. */
6012 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6013 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6014 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6015 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6016 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6017 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6019 /* MIPS version of CALL_DUMMY */
6021 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6022 replaced by a command, and all targets will default to on stack
6023 (regardless of the stack's execute status). */
6024 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6025 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6027 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6028 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6029 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6031 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6032 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6034 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6036 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6038 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6039 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6040 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6042 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6044 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6046 if (mips_abi
== MIPS_ABI_N32
)
6047 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6048 else if (mips_abi
== MIPS_ABI_N64
)
6049 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6051 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6053 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6054 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6055 need to all be folded into the target vector. Since they are
6056 being used as guards for target_stopped_by_watchpoint, why not have
6057 target_stopped_by_watchpoint return the type of watchpoint that the code
6059 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6061 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6063 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
6065 /* Virtual tables. */
6066 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6068 mips_register_g_packet_guesses (gdbarch
);
6070 /* Hook in OS ABI-specific overrides, if they have been registered. */
6071 info
.tdep_info
= (void *) tdesc_data
;
6072 gdbarch_init_osabi (info
, gdbarch
);
6074 /* Unwind the frame. */
6075 dwarf2_append_unwinders (gdbarch
);
6076 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6077 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6078 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6079 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6080 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6081 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6082 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6086 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6087 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6089 /* Override the normal target description methods to handle our
6090 dual real and pseudo registers. */
6091 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6092 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
6094 num_regs
= gdbarch_num_regs (gdbarch
);
6095 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6096 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6097 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6100 /* Add ABI-specific aliases for the registers. */
6101 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6102 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6103 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6104 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6106 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6107 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6108 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6110 /* Add some other standard aliases. */
6111 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6112 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6113 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6115 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6116 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6117 value_of_mips_user_reg
,
6118 &mips_numeric_register_aliases
[i
].regnum
);
6124 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6126 struct gdbarch_info info
;
6128 /* Force the architecture to update, and (if it's a MIPS architecture)
6129 mips_gdbarch_init will take care of the rest. */
6130 gdbarch_info_init (&info
);
6131 gdbarch_update_p (info
);
6134 /* Print out which MIPS ABI is in use. */
6137 show_mips_abi (struct ui_file
*file
,
6139 struct cmd_list_element
*ignored_cmd
,
6140 const char *ignored_value
)
6142 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6145 "The MIPS ABI is unknown because the current architecture "
6149 enum mips_abi global_abi
= global_mips_abi ();
6150 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6151 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6153 if (global_abi
== MIPS_ABI_UNKNOWN
)
6156 "The MIPS ABI is set automatically (currently \"%s\").\n",
6158 else if (global_abi
== actual_abi
)
6161 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6165 /* Probably shouldn't happen... */
6168 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6169 actual_abi_str
, mips_abi_strings
[global_abi
]);
6175 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6177 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6181 int ef_mips_32bitmode
;
6182 /* Determine the ISA. */
6183 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6201 /* Determine the size of a pointer. */
6202 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6203 fprintf_unfiltered (file
,
6204 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6206 fprintf_unfiltered (file
,
6207 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6209 fprintf_unfiltered (file
,
6210 "mips_dump_tdep: ef_mips_arch = %d\n",
6212 fprintf_unfiltered (file
,
6213 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6214 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6215 fprintf_unfiltered (file
,
6216 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6217 mips_mask_address_p (tdep
),
6218 tdep
->default_mask_address_p
);
6220 fprintf_unfiltered (file
,
6221 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6222 MIPS_DEFAULT_FPU_TYPE
,
6223 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6224 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6225 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6227 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6228 MIPS_EABI (gdbarch
));
6229 fprintf_unfiltered (file
,
6230 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6231 MIPS_FPU_TYPE (gdbarch
),
6232 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6233 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6234 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6238 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6241 _initialize_mips_tdep (void)
6243 static struct cmd_list_element
*mipsfpulist
= NULL
;
6244 struct cmd_list_element
*c
;
6246 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6247 if (MIPS_ABI_LAST
+ 1
6248 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6249 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6251 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6253 mips_pdr_data
= register_objfile_data ();
6255 /* Create feature sets with the appropriate properties. The values
6256 are not important. */
6257 mips_tdesc_gp32
= allocate_target_description ();
6258 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6260 mips_tdesc_gp64
= allocate_target_description ();
6261 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6263 /* Add root prefix command for all "set mips"/"show mips" commands */
6264 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6265 _("Various MIPS specific commands."),
6266 &setmipscmdlist
, "set mips ", 0, &setlist
);
6268 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6269 _("Various MIPS specific commands."),
6270 &showmipscmdlist
, "show mips ", 0, &showlist
);
6272 /* Allow the user to override the ABI. */
6273 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6274 &mips_abi_string
, _("\
6275 Set the MIPS ABI used by this program."), _("\
6276 Show the MIPS ABI used by this program."), _("\
6277 This option can be set to one of:\n\
6278 auto - the default ABI associated with the current binary\n\
6287 &setmipscmdlist
, &showmipscmdlist
);
6289 /* Let the user turn off floating point and set the fence post for
6290 heuristic_proc_start. */
6292 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6293 _("Set use of MIPS floating-point coprocessor."),
6294 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6295 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6296 _("Select single-precision MIPS floating-point coprocessor."),
6298 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6299 _("Select double-precision MIPS floating-point coprocessor."),
6301 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6302 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6303 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6304 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6305 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6306 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6307 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6308 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6309 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6310 _("Select MIPS floating-point coprocessor automatically."),
6312 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6313 _("Show current use of MIPS floating-point coprocessor target."),
6316 /* We really would like to have both "0" and "unlimited" work, but
6317 command.c doesn't deal with that. So make it a var_zinteger
6318 because the user can always use "999999" or some such for unlimited. */
6319 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6320 &heuristic_fence_post
, _("\
6321 Set the distance searched for the start of a function."), _("\
6322 Show the distance searched for the start of a function."), _("\
6323 If you are debugging a stripped executable, GDB needs to search through the\n\
6324 program for the start of a function. This command sets the distance of the\n\
6325 search. The only need to set it is when debugging a stripped executable."),
6326 reinit_frame_cache_sfunc
,
6327 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
6328 &setlist
, &showlist
);
6330 /* Allow the user to control whether the upper bits of 64-bit
6331 addresses should be zeroed. */
6332 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6333 &mask_address_var
, _("\
6334 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6335 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6336 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
6337 allow GDB to determine the correct value."),
6338 NULL
, show_mask_address
,
6339 &setmipscmdlist
, &showmipscmdlist
);
6341 /* Allow the user to control the size of 32 bit registers within the
6342 raw remote packet. */
6343 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6344 &mips64_transfers_32bit_regs_p
, _("\
6345 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6347 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6349 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6350 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6351 64 bits for others. Use \"off\" to disable compatibility mode"),
6352 set_mips64_transfers_32bit_regs
,
6353 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6354 &setlist
, &showlist
);
6356 /* Debug this files internals. */
6357 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6359 Set mips debugging."), _("\
6360 Show mips debugging."), _("\
6361 When non-zero, mips specific debugging is enabled."),
6363 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
6364 &setdebuglist
, &showdebuglist
);