1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 /* Some MIPS boards don't support floating point while others only
146 support single-precision floating-point operations. */
150 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
151 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
152 MIPS_FPU_NONE
/* No floating point. */
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto
= 1;
159 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
161 static int mips_debug
= 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc
*mips_tdesc_gp32
;
169 struct target_desc
*mips_tdesc_gp64
;
171 /* MIPS specific per-architecture information */
174 /* from the elf header */
178 enum mips_abi mips_abi
;
179 enum mips_abi found_abi
;
180 enum mips_fpu_type mips_fpu_type
;
181 int mips_last_arg_regnum
;
182 int mips_last_fp_arg_regnum
;
183 int default_mask_address_p
;
184 /* Is the target using 64-bit raw integer registers but only
185 storing a left-aligned 32-bit value in each? */
186 int mips64_transfers_32bit_regs_p
;
187 /* Indexes for various registers. IRIX and embedded have
188 different values. This contains the "public" fields. Don't
189 add any that do not need to be public. */
190 const struct mips_regnum
*regnum
;
191 /* Register names table for the current register set. */
192 const char **mips_processor_reg_names
;
194 /* The size of register data available from the target, if known.
195 This doesn't quite obsolete the manual
196 mips64_transfers_32bit_regs_p, since that is documented to force
197 left alignment even for big endian (very strange). */
198 int register_size_valid_p
;
202 const struct mips_regnum
*
203 mips_regnum (struct gdbarch
*gdbarch
)
205 return gdbarch_tdep (gdbarch
)->regnum
;
209 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
211 return mips_regnum (gdbarch
)->fp0
+ 12;
214 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
215 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
217 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
219 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
221 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
223 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
224 functions to test, set, or clear bit 0 of addresses. */
227 is_mips16_addr (CORE_ADDR addr
)
233 unmake_mips16_addr (CORE_ADDR addr
)
235 return ((addr
) & ~(CORE_ADDR
) 1);
238 /* Return the MIPS ABI associated with GDBARCH. */
240 mips_abi (struct gdbarch
*gdbarch
)
242 return gdbarch_tdep (gdbarch
)->mips_abi
;
246 mips_isa_regsize (struct gdbarch
*gdbarch
)
248 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
250 /* If we know how big the registers are, use that size. */
251 if (tdep
->register_size_valid_p
)
252 return tdep
->register_size
;
254 /* Fall back to the previous behavior. */
255 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
256 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
259 /* Return the currently configured (or set) saved register size. */
262 mips_abi_regsize (struct gdbarch
*gdbarch
)
264 switch (mips_abi (gdbarch
))
266 case MIPS_ABI_EABI32
:
272 case MIPS_ABI_EABI64
:
274 case MIPS_ABI_UNKNOWN
:
277 internal_error (__FILE__
, __LINE__
, _("bad switch"));
281 /* Functions for setting and testing a bit in a minimal symbol that
282 marks it as 16-bit function. The MSB of the minimal symbol's
283 "info" field is used for this purpose.
285 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
286 i.e. refers to a 16-bit function, and sets a "special" bit in a
287 minimal symbol to mark it as a 16-bit function
289 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
292 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
294 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
296 MSYMBOL_INFO (msym
) = (char *)
297 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
298 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
303 msymbol_is_special (struct minimal_symbol
*msym
)
305 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
308 /* XFER a value from the big/little/left end of the register.
309 Depending on the size of the value it might occupy the entire
310 register or just part of it. Make an allowance for this, aligning
311 things accordingly. */
314 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
315 int reg_num
, int length
,
316 enum bfd_endian endian
, gdb_byte
*in
,
317 const gdb_byte
*out
, int buf_offset
)
321 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
322 /* Need to transfer the left or right part of the register, based on
323 the targets byte order. */
327 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
329 case BFD_ENDIAN_LITTLE
:
332 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
336 internal_error (__FILE__
, __LINE__
, _("bad switch"));
339 fprintf_unfiltered (gdb_stderr
,
340 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
341 reg_num
, reg_offset
, buf_offset
, length
);
342 if (mips_debug
&& out
!= NULL
)
345 fprintf_unfiltered (gdb_stdlog
, "out ");
346 for (i
= 0; i
< length
; i
++)
347 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
350 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
353 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
355 if (mips_debug
&& in
!= NULL
)
358 fprintf_unfiltered (gdb_stdlog
, "in ");
359 for (i
= 0; i
< length
; i
++)
360 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
363 fprintf_unfiltered (gdb_stdlog
, "\n");
366 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
367 compatiblity mode. A return value of 1 means that we have
368 physical 64-bit registers, but should treat them as 32-bit registers. */
371 mips2_fp_compat (struct frame_info
*frame
)
373 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
374 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
376 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
380 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
381 in all the places we deal with FP registers. PR gdb/413. */
382 /* Otherwise check the FR bit in the status register - it controls
383 the FP compatiblity mode. If it is clear we are in compatibility
385 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
392 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
394 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
396 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
398 static struct type
*mips_float_register_type (void);
399 static struct type
*mips_double_register_type (void);
401 /* The list of available "set mips " and "show mips " commands */
403 static struct cmd_list_element
*setmipscmdlist
= NULL
;
404 static struct cmd_list_element
*showmipscmdlist
= NULL
;
406 /* Integer registers 0 thru 31 are handled explicitly by
407 mips_register_name(). Processor specific registers 32 and above
408 are listed in the following tables. */
411 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
415 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
416 "sr", "lo", "hi", "bad", "cause", "pc",
417 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
418 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
419 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
420 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
421 "fsr", "fir", "" /*"fp" */ , "",
422 "", "", "", "", "", "", "", "",
423 "", "", "", "", "", "", "", "",
426 /* Names of IDT R3041 registers. */
428 static const char *mips_r3041_reg_names
[] = {
429 "sr", "lo", "hi", "bad", "cause", "pc",
430 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
431 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
432 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
433 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
434 "fsr", "fir", "", /*"fp" */ "",
435 "", "", "bus", "ccfg", "", "", "", "",
436 "", "", "port", "cmp", "", "", "epc", "prid",
439 /* Names of tx39 registers. */
441 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
442 "sr", "lo", "hi", "bad", "cause", "pc",
443 "", "", "", "", "", "", "", "",
444 "", "", "", "", "", "", "", "",
445 "", "", "", "", "", "", "", "",
446 "", "", "", "", "", "", "", "",
448 "", "", "", "", "", "", "", "",
449 "", "", "config", "cache", "debug", "depc", "epc", ""
452 /* Names of IRIX registers. */
453 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
454 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
455 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
456 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
457 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
458 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
462 /* Return the name of the register corresponding to REGNO. */
464 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
466 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
467 /* GPR names for all ABIs other than n32/n64. */
468 static char *mips_gpr_names
[] = {
469 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
470 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
471 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
472 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
475 /* GPR names for n32 and n64 ABIs. */
476 static char *mips_n32_n64_gpr_names
[] = {
477 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
478 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
479 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
480 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
483 enum mips_abi abi
= mips_abi (gdbarch
);
485 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
486 but then don't make the raw register names visible. */
487 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
488 if (regno
< gdbarch_num_regs (gdbarch
))
491 /* The MIPS integer registers are always mapped from 0 to 31. The
492 names of the registers (which reflects the conventions regarding
493 register use) vary depending on the ABI. */
494 if (0 <= rawnum
&& rawnum
< 32)
496 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
497 return mips_n32_n64_gpr_names
[rawnum
];
499 return mips_gpr_names
[rawnum
];
501 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
502 return tdesc_register_name (gdbarch
, rawnum
);
503 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
505 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
506 return tdep
->mips_processor_reg_names
[rawnum
- 32];
509 internal_error (__FILE__
, __LINE__
,
510 _("mips_register_name: bad register number %d"), rawnum
);
513 /* Return the groups that a MIPS register can be categorised into. */
516 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
517 struct reggroup
*reggroup
)
522 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
523 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
524 if (reggroup
== all_reggroup
)
526 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
527 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
528 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
529 (gdbarch), as not all architectures are multi-arch. */
530 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
531 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
532 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
534 if (reggroup
== float_reggroup
)
535 return float_p
&& pseudo
;
536 if (reggroup
== vector_reggroup
)
537 return vector_p
&& pseudo
;
538 if (reggroup
== general_reggroup
)
539 return (!vector_p
&& !float_p
) && pseudo
;
540 /* Save the pseudo registers. Need to make certain that any code
541 extracting register values from a saved register cache also uses
543 if (reggroup
== save_reggroup
)
544 return raw_p
&& pseudo
;
545 /* Restore the same pseudo register. */
546 if (reggroup
== restore_reggroup
)
547 return raw_p
&& pseudo
;
551 /* Return the groups that a MIPS register can be categorised into.
552 This version is only used if we have a target description which
553 describes real registers (and their groups). */
556 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
557 struct reggroup
*reggroup
)
559 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
560 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
563 /* Only save, restore, and display the pseudo registers. Need to
564 make certain that any code extracting register values from a
565 saved register cache also uses pseudo registers.
567 Note: saving and restoring the pseudo registers is slightly
568 strange; if we have 64 bits, we should save and restore all
569 64 bits. But this is hard and has little benefit. */
573 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
577 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
580 /* Map the symbol table registers which live in the range [1 *
581 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
582 registers. Take care of alignment and size problems. */
585 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
586 int cookednum
, gdb_byte
*buf
)
588 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
589 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
590 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
591 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
592 regcache_raw_read (regcache
, rawnum
, buf
);
593 else if (register_size (gdbarch
, rawnum
) >
594 register_size (gdbarch
, cookednum
))
596 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
597 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
598 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
600 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
603 internal_error (__FILE__
, __LINE__
, _("bad register size"));
607 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
608 struct regcache
*regcache
, int cookednum
,
611 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
612 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
613 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
614 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
615 regcache_raw_write (regcache
, rawnum
, buf
);
616 else if (register_size (gdbarch
, rawnum
) >
617 register_size (gdbarch
, cookednum
))
619 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
620 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
621 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
623 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
626 internal_error (__FILE__
, __LINE__
, _("bad register size"));
629 /* Table to translate MIPS16 register field to actual register number. */
630 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
632 /* Heuristic_proc_start may hunt through the text section for a long
633 time across a 2400 baud serial line. Allows the user to limit this
636 static unsigned int heuristic_fence_post
= 0;
638 /* Number of bytes of storage in the actual machine representation for
639 register N. NOTE: This defines the pseudo register type so need to
640 rebuild the architecture vector. */
642 static int mips64_transfers_32bit_regs_p
= 0;
645 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
646 struct cmd_list_element
*c
)
648 struct gdbarch_info info
;
649 gdbarch_info_init (&info
);
650 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
651 instead of relying on globals. Doing that would let generic code
652 handle the search for this specific architecture. */
653 if (!gdbarch_update_p (info
))
655 mips64_transfers_32bit_regs_p
= 0;
656 error (_("32-bit compatibility mode not supported"));
660 /* Convert to/from a register and the corresponding memory value. */
663 mips_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
665 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
666 && register_size (gdbarch
, regnum
) == 4
667 && (regnum
% gdbarch_num_regs (gdbarch
))
668 >= mips_regnum (gdbarch
)->fp0
669 && (regnum
% gdbarch_num_regs (gdbarch
))
670 < mips_regnum (gdbarch
)->fp0
+ 32
671 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
675 mips_register_to_value (struct frame_info
*frame
, int regnum
,
676 struct type
*type
, gdb_byte
*to
)
678 get_frame_register (frame
, regnum
+ 0, to
+ 4);
679 get_frame_register (frame
, regnum
+ 1, to
+ 0);
683 mips_value_to_register (struct frame_info
*frame
, int regnum
,
684 struct type
*type
, const gdb_byte
*from
)
686 put_frame_register (frame
, regnum
+ 0, from
+ 4);
687 put_frame_register (frame
, regnum
+ 1, from
+ 0);
690 /* Return the GDB type object for the "standard" data type of data in
694 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
696 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
697 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
698 && (regnum
% gdbarch_num_regs (gdbarch
))
699 < mips_regnum (gdbarch
)->fp0
+ 32)
701 /* The floating-point registers raw, or cooked, always match
702 mips_isa_regsize(), and also map 1:1, byte for byte. */
703 if (mips_isa_regsize (gdbarch
) == 4)
704 return builtin_type_ieee_single
;
706 return builtin_type_ieee_double
;
708 else if (regnum
< gdbarch_num_regs (gdbarch
))
710 /* The raw or ISA registers. These are all sized according to
712 if (mips_isa_regsize (gdbarch
) == 4)
713 return builtin_type_int32
;
715 return builtin_type_int64
;
719 /* The cooked or ABI registers. These are sized according to
720 the ABI (with a few complications). */
721 if (regnum
>= (gdbarch_num_regs (gdbarch
)
722 + mips_regnum (gdbarch
)->fp_control_status
)
723 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
724 /* The pseudo/cooked view of the embedded registers is always
725 32-bit. The raw view is handled below. */
726 return builtin_type_int32
;
727 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
728 /* The target, while possibly using a 64-bit register buffer,
729 is only transfering 32-bits of each integer register.
730 Reflect this in the cooked/pseudo (ABI) register value. */
731 return builtin_type_int32
;
732 else if (mips_abi_regsize (gdbarch
) == 4)
733 /* The ABI is restricted to 32-bit registers (the ISA could be
735 return builtin_type_int32
;
738 return builtin_type_int64
;
742 /* Return the GDB type for the pseudo register REGNUM, which is the
743 ABI-level view. This function is only called if there is a target
744 description which includes registers, so we know precisely the
745 types of hardware registers. */
748 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
750 const int num_regs
= gdbarch_num_regs (gdbarch
);
751 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
752 int rawnum
= regnum
% num_regs
;
753 struct type
*rawtype
;
755 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
757 /* Absent registers are still absent. */
758 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
759 if (TYPE_LENGTH (rawtype
) == 0)
762 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
763 /* Present the floating point registers however the hardware did;
764 do not try to convert between FPU layouts. */
767 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
769 /* The pseudo/cooked view of embedded registers is always
770 32-bit, even if the target transfers 64-bit values for them.
771 New targets relying on XML descriptions should only transfer
772 the necessary 32 bits, but older versions of GDB expected 64,
773 so allow the target to provide 64 bits without interfering
774 with the displayed type. */
775 return builtin_type_int32
;
778 /* Use pointer types for registers if we can. For n32 we can not,
779 since we do not have a 64-bit pointer type. */
780 if (mips_abi_regsize (gdbarch
) == TYPE_LENGTH (builtin_type_void_data_ptr
))
782 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
783 return builtin_type_void_data_ptr
;
784 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
785 return builtin_type_void_func_ptr
;
788 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
789 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
790 return builtin_type_int32
;
792 /* For all other registers, pass through the hardware type. */
796 /* Should the upper word of 64-bit addresses be zeroed? */
797 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
800 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
802 switch (mask_address_var
)
804 case AUTO_BOOLEAN_TRUE
:
806 case AUTO_BOOLEAN_FALSE
:
809 case AUTO_BOOLEAN_AUTO
:
810 return tdep
->default_mask_address_p
;
812 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
818 show_mask_address (struct ui_file
*file
, int from_tty
,
819 struct cmd_list_element
*c
, const char *value
)
821 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
823 deprecated_show_value_hack (file
, from_tty
, c
, value
);
824 switch (mask_address_var
)
826 case AUTO_BOOLEAN_TRUE
:
827 printf_filtered ("The 32 bit mips address mask is enabled\n");
829 case AUTO_BOOLEAN_FALSE
:
830 printf_filtered ("The 32 bit mips address mask is disabled\n");
832 case AUTO_BOOLEAN_AUTO
:
834 ("The 32 bit address mask is set automatically. Currently %s\n",
835 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
838 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
843 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
846 mips_pc_is_mips16 (CORE_ADDR memaddr
)
848 struct minimal_symbol
*sym
;
850 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
851 if (is_mips16_addr (memaddr
))
854 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
855 the high bit of the info field. Use this to decide if the function is
856 MIPS16 or normal MIPS. */
857 sym
= lookup_minimal_symbol_by_pc (memaddr
);
859 return msymbol_is_special (sym
);
864 /* MIPS believes that the PC has a sign extended value. Perhaps the
865 all registers should be sign extended for simplicity? */
868 mips_read_pc (struct regcache
*regcache
)
871 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
872 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
877 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
879 return frame_unwind_register_signed
880 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
884 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
886 return frame_unwind_register_signed
887 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
890 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
891 dummy frame. The frame ID's base needs to match the TOS value
892 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
895 static struct frame_id
896 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
898 return frame_id_build
899 (frame_unwind_register_signed (next_frame
,
900 gdbarch_num_regs (gdbarch
)
902 frame_pc_unwind (next_frame
));
906 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
908 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
909 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
912 /* Fetch and return instruction from the specified location. If the PC
913 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
916 mips_fetch_instruction (CORE_ADDR addr
)
918 gdb_byte buf
[MIPS_INSN32_SIZE
];
922 if (mips_pc_is_mips16 (addr
))
924 instlen
= MIPS_INSN16_SIZE
;
925 addr
= unmake_mips16_addr (addr
);
928 instlen
= MIPS_INSN32_SIZE
;
929 status
= target_read_memory (addr
, buf
, instlen
);
931 memory_error (status
, addr
);
932 return extract_unsigned_integer (buf
, instlen
);
935 /* These the fields of 32 bit mips instructions */
936 #define mips32_op(x) (x >> 26)
937 #define itype_op(x) (x >> 26)
938 #define itype_rs(x) ((x >> 21) & 0x1f)
939 #define itype_rt(x) ((x >> 16) & 0x1f)
940 #define itype_immediate(x) (x & 0xffff)
942 #define jtype_op(x) (x >> 26)
943 #define jtype_target(x) (x & 0x03ffffff)
945 #define rtype_op(x) (x >> 26)
946 #define rtype_rs(x) ((x >> 21) & 0x1f)
947 #define rtype_rt(x) ((x >> 16) & 0x1f)
948 #define rtype_rd(x) ((x >> 11) & 0x1f)
949 #define rtype_shamt(x) ((x >> 6) & 0x1f)
950 #define rtype_funct(x) (x & 0x3f)
953 mips32_relative_offset (ULONGEST inst
)
955 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
958 /* Determine where to set a single step breakpoint while considering
959 branch prediction. */
961 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
965 inst
= mips_fetch_instruction (pc
);
966 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
968 if (itype_op (inst
) >> 2 == 5)
969 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
971 op
= (itype_op (inst
) & 0x03);
986 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
987 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
989 int tf
= itype_rt (inst
) & 0x01;
990 int cnum
= itype_rt (inst
) >> 2;
992 get_frame_register_signed (frame
,
993 mips_regnum (get_frame_arch (frame
))->
995 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
997 if (((cond
>> cnum
) & 0x01) == tf
)
998 pc
+= mips32_relative_offset (inst
) + 4;
1003 pc
+= 4; /* Not a branch, next instruction is easy */
1006 { /* This gets way messy */
1008 /* Further subdivide into SPECIAL, REGIMM and other */
1009 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1011 case 0: /* SPECIAL */
1012 op
= rtype_funct (inst
);
1017 /* Set PC to that address */
1018 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1024 break; /* end SPECIAL */
1025 case 1: /* REGIMM */
1027 op
= itype_rt (inst
); /* branch condition */
1032 case 16: /* BLTZAL */
1033 case 18: /* BLTZALL */
1035 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1036 pc
+= mips32_relative_offset (inst
) + 4;
1038 pc
+= 8; /* after the delay slot */
1042 case 17: /* BGEZAL */
1043 case 19: /* BGEZALL */
1044 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1045 pc
+= mips32_relative_offset (inst
) + 4;
1047 pc
+= 8; /* after the delay slot */
1049 /* All of the other instructions in the REGIMM category */
1054 break; /* end REGIMM */
1059 reg
= jtype_target (inst
) << 2;
1060 /* Upper four bits get never changed... */
1061 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1064 /* FIXME case JALX : */
1067 reg
= jtype_target (inst
) << 2;
1068 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1069 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1071 break; /* The new PC will be alternate mode */
1072 case 4: /* BEQ, BEQL */
1074 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1075 get_frame_register_signed (frame
, itype_rt (inst
)))
1076 pc
+= mips32_relative_offset (inst
) + 4;
1080 case 5: /* BNE, BNEL */
1082 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1083 get_frame_register_signed (frame
, itype_rt (inst
)))
1084 pc
+= mips32_relative_offset (inst
) + 4;
1088 case 6: /* BLEZ, BLEZL */
1089 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1090 pc
+= mips32_relative_offset (inst
) + 4;
1096 greater_branch
: /* BGTZ, BGTZL */
1097 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1098 pc
+= mips32_relative_offset (inst
) + 4;
1105 } /* mips32_next_pc */
1107 /* Decoding the next place to set a breakpoint is irregular for the
1108 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1109 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1110 We dont want to set a single step instruction on the extend instruction
1114 /* Lots of mips16 instruction formats */
1115 /* Predicting jumps requires itype,ritype,i8type
1116 and their extensions extItype,extritype,extI8type
1118 enum mips16_inst_fmts
1120 itype
, /* 0 immediate 5,10 */
1121 ritype
, /* 1 5,3,8 */
1122 rrtype
, /* 2 5,3,3,5 */
1123 rritype
, /* 3 5,3,3,5 */
1124 rrrtype
, /* 4 5,3,3,3,2 */
1125 rriatype
, /* 5 5,3,3,1,4 */
1126 shifttype
, /* 6 5,3,3,3,2 */
1127 i8type
, /* 7 5,3,8 */
1128 i8movtype
, /* 8 5,3,3,5 */
1129 i8mov32rtype
, /* 9 5,3,5,3 */
1130 i64type
, /* 10 5,3,8 */
1131 ri64type
, /* 11 5,3,3,5 */
1132 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1133 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1134 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1135 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1136 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1137 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1138 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1139 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1140 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1141 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1143 /* I am heaping all the fields of the formats into one structure and
1144 then, only the fields which are involved in instruction extension */
1148 unsigned int regx
; /* Function in i8 type */
1153 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1154 for the bits which make up the immediate extension. */
1157 extended_offset (unsigned int extension
)
1160 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1162 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1164 value
|= extension
& 0x01f; /* extract 4:0 */
1168 /* Only call this function if you know that this is an extendable
1169 instruction. It won't malfunction, but why make excess remote memory
1170 references? If the immediate operands get sign extended or something,
1171 do it after the extension is performed. */
1172 /* FIXME: Every one of these cases needs to worry about sign extension
1173 when the offset is to be used in relative addressing. */
1176 fetch_mips_16 (CORE_ADDR pc
)
1179 pc
&= 0xfffffffe; /* clear the low order bit */
1180 target_read_memory (pc
, buf
, 2);
1181 return extract_unsigned_integer (buf
, 2);
1185 unpack_mips16 (CORE_ADDR pc
,
1186 unsigned int extension
,
1188 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1193 switch (insn_format
)
1200 value
= extended_offset (extension
);
1201 value
= value
<< 11; /* rom for the original value */
1202 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1206 value
= inst
& 0x7ff;
1207 /* FIXME : Consider sign extension */
1216 { /* A register identifier and an offset */
1217 /* Most of the fields are the same as I type but the
1218 immediate value is of a different length */
1222 value
= extended_offset (extension
);
1223 value
= value
<< 8; /* from the original instruction */
1224 value
|= inst
& 0xff; /* eleven bits from instruction */
1225 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1226 if (value
& 0x4000) /* test the sign bit , bit 26 */
1228 value
&= ~0x3fff; /* remove the sign bit */
1234 value
= inst
& 0xff; /* 8 bits */
1235 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1236 /* FIXME: Do sign extension , this format needs it */
1237 if (value
& 0x80) /* THIS CONFUSES ME */
1239 value
&= 0xef; /* remove the sign bit */
1249 unsigned long value
;
1250 unsigned int nexthalf
;
1251 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1252 value
= value
<< 16;
1253 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1261 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1263 upk
->offset
= offset
;
1270 add_offset_16 (CORE_ADDR pc
, int offset
)
1272 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1276 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1277 unsigned int extension
, unsigned int insn
)
1279 int op
= (insn
>> 11);
1282 case 2: /* Branch */
1285 struct upk_mips16 upk
;
1286 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1287 offset
= upk
.offset
;
1293 pc
+= (offset
<< 1) + 2;
1296 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1298 struct upk_mips16 upk
;
1299 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1300 pc
= add_offset_16 (pc
, upk
.offset
);
1301 if ((insn
>> 10) & 0x01) /* Exchange mode */
1302 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1309 struct upk_mips16 upk
;
1311 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1312 reg
= get_frame_register_signed (frame
, upk
.regx
);
1314 pc
+= (upk
.offset
<< 1) + 2;
1321 struct upk_mips16 upk
;
1323 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1324 reg
= get_frame_register_signed (frame
, upk
.regx
);
1326 pc
+= (upk
.offset
<< 1) + 2;
1331 case 12: /* I8 Formats btez btnez */
1333 struct upk_mips16 upk
;
1335 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1336 /* upk.regx contains the opcode */
1337 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1338 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1339 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1340 /* pc = add_offset_16(pc,upk.offset) ; */
1341 pc
+= (upk
.offset
<< 1) + 2;
1346 case 29: /* RR Formats JR, JALR, JALR-RA */
1348 struct upk_mips16 upk
;
1349 /* upk.fmt = rrtype; */
1354 upk
.regx
= (insn
>> 8) & 0x07;
1355 upk
.regy
= (insn
>> 5) & 0x07;
1363 break; /* Function return instruction */
1369 break; /* BOGUS Guess */
1371 pc
= get_frame_register_signed (frame
, reg
);
1378 /* This is an instruction extension. Fetch the real instruction
1379 (which follows the extension) and decode things based on
1383 pc
= extended_mips16_next_pc (frame
, pc
, insn
, fetch_mips_16 (pc
));
1396 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1398 unsigned int insn
= fetch_mips_16 (pc
);
1399 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1402 /* The mips_next_pc function supports single_step when the remote
1403 target monitor or stub is not developed enough to do a single_step.
1404 It works by decoding the current instruction and predicting where a
1405 branch will go. This isnt hard because all the data is available.
1406 The MIPS32 and MIPS16 variants are quite different. */
1408 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1410 if (is_mips16_addr (pc
))
1411 return mips16_next_pc (frame
, pc
);
1413 return mips32_next_pc (frame
, pc
);
1416 struct mips_frame_cache
1419 struct trad_frame_saved_reg
*saved_regs
;
1422 /* Set a register's saved stack address in temp_saved_regs. If an
1423 address has already been set for this register, do nothing; this
1424 way we will only recognize the first save of a given register in a
1427 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1428 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1429 Strictly speaking, only the second range is used as it is only second
1430 range (the ABI instead of ISA registers) that comes into play when finding
1431 saved registers in a frame. */
1434 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1437 if (this_cache
!= NULL
1438 && this_cache
->saved_regs
[regnum
].addr
== -1)
1440 this_cache
->saved_regs
[regnum
1441 + 0 * gdbarch_num_regs (current_gdbarch
)].addr
1443 this_cache
->saved_regs
[regnum
1444 + 1 * gdbarch_num_regs (current_gdbarch
)].addr
1450 /* Fetch the immediate value from a MIPS16 instruction.
1451 If the previous instruction was an EXTEND, use it to extend
1452 the upper bits of the immediate value. This is a helper function
1453 for mips16_scan_prologue. */
1456 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1457 unsigned short inst
, /* current instruction */
1458 int nbits
, /* number of bits in imm field */
1459 int scale
, /* scale factor to be applied to imm */
1460 int is_signed
) /* is the imm field signed? */
1464 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1466 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1467 if (offset
& 0x8000) /* check for negative extend */
1468 offset
= 0 - (0x10000 - (offset
& 0xffff));
1469 return offset
| (inst
& 0x1f);
1473 int max_imm
= 1 << nbits
;
1474 int mask
= max_imm
- 1;
1475 int sign_bit
= max_imm
>> 1;
1477 offset
= inst
& mask
;
1478 if (is_signed
&& (offset
& sign_bit
))
1479 offset
= 0 - (max_imm
- offset
);
1480 return offset
* scale
;
1485 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1486 the associated FRAME_CACHE if not null.
1487 Return the address of the first instruction past the prologue. */
1490 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1491 struct frame_info
*next_frame
,
1492 struct mips_frame_cache
*this_cache
)
1495 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1497 long frame_offset
= 0; /* Size of stack frame. */
1498 long frame_adjust
= 0; /* Offset of FP from SP. */
1499 int frame_reg
= MIPS_SP_REGNUM
;
1500 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1501 unsigned inst
= 0; /* current instruction */
1502 unsigned entry_inst
= 0; /* the entry instruction */
1503 unsigned save_inst
= 0; /* the save instruction */
1506 int extend_bytes
= 0;
1507 int prev_extend_bytes
;
1508 CORE_ADDR end_prologue_addr
= 0;
1509 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1511 /* Can be called when there's no process, and hence when there's no
1513 if (next_frame
!= NULL
)
1514 sp
= frame_unwind_register_signed (next_frame
,
1515 gdbarch_num_regs (gdbarch
)
1520 if (limit_pc
> start_pc
+ 200)
1521 limit_pc
= start_pc
+ 200;
1523 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1525 /* Save the previous instruction. If it's an EXTEND, we'll extract
1526 the immediate offset extension from it in mips16_get_imm. */
1529 /* Fetch and decode the instruction. */
1530 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1532 /* Normally we ignore extend instructions. However, if it is
1533 not followed by a valid prologue instruction, then this
1534 instruction is not part of the prologue either. We must
1535 remember in this case to adjust the end_prologue_addr back
1537 if ((inst
& 0xf800) == 0xf000) /* extend */
1539 extend_bytes
= MIPS_INSN16_SIZE
;
1543 prev_extend_bytes
= extend_bytes
;
1546 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1547 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1549 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1550 if (offset
< 0) /* negative stack adjustment? */
1551 frame_offset
-= offset
;
1553 /* Exit loop if a positive stack adjustment is found, which
1554 usually means that the stack cleanup code in the function
1555 epilogue is reached. */
1558 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1560 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1561 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1562 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1564 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1566 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1567 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1568 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1570 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1572 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1573 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1575 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1577 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1578 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1580 else if (inst
== 0x673d) /* move $s1, $sp */
1585 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1587 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1588 frame_addr
= sp
+ offset
;
1590 frame_adjust
= offset
;
1592 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1594 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1595 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1596 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1598 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1600 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1601 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1602 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1604 else if ((inst
& 0xf81f) == 0xe809
1605 && (inst
& 0x700) != 0x700) /* entry */
1606 entry_inst
= inst
; /* save for later processing */
1607 else if ((inst
& 0xff80) == 0x6480) /* save */
1609 save_inst
= inst
; /* save for later processing */
1610 if (prev_extend_bytes
) /* extend */
1611 save_inst
|= prev_inst
<< 16;
1613 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1614 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1615 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1617 /* This instruction is part of the prologue, but we don't
1618 need to do anything special to handle it. */
1622 /* This instruction is not an instruction typically found
1623 in a prologue, so we must have reached the end of the
1625 if (end_prologue_addr
== 0)
1626 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1630 /* The entry instruction is typically the first instruction in a function,
1631 and it stores registers at offsets relative to the value of the old SP
1632 (before the prologue). But the value of the sp parameter to this
1633 function is the new SP (after the prologue has been executed). So we
1634 can't calculate those offsets until we've seen the entire prologue,
1635 and can calculate what the old SP must have been. */
1636 if (entry_inst
!= 0)
1638 int areg_count
= (entry_inst
>> 8) & 7;
1639 int sreg_count
= (entry_inst
>> 6) & 3;
1641 /* The entry instruction always subtracts 32 from the SP. */
1644 /* Now we can calculate what the SP must have been at the
1645 start of the function prologue. */
1648 /* Check if a0-a3 were saved in the caller's argument save area. */
1649 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1651 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1652 offset
+= mips_abi_regsize (gdbarch
);
1655 /* Check if the ra register was pushed on the stack. */
1657 if (entry_inst
& 0x20)
1659 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1660 offset
-= mips_abi_regsize (gdbarch
);
1663 /* Check if the s0 and s1 registers were pushed on the stack. */
1664 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1666 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1667 offset
-= mips_abi_regsize (gdbarch
);
1671 /* The SAVE instruction is similar to ENTRY, except that defined by the
1672 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1673 size of the frame is specified as an immediate field of instruction
1674 and an extended variation exists which lets additional registers and
1675 frame space to be specified. The instruction always treats registers
1676 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1677 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1679 static int args_table
[16] = {
1680 0, 0, 0, 0, 1, 1, 1, 1,
1681 2, 2, 2, 0, 3, 3, 4, -1,
1683 static int astatic_table
[16] = {
1684 0, 1, 2, 3, 0, 1, 2, 3,
1685 0, 1, 2, 4, 0, 1, 0, -1,
1687 int aregs
= (save_inst
>> 16) & 0xf;
1688 int xsregs
= (save_inst
>> 24) & 0x7;
1689 int args
= args_table
[aregs
];
1690 int astatic
= astatic_table
[aregs
];
1695 warning (_("Invalid number of argument registers encoded in SAVE."));
1700 warning (_("Invalid number of static registers encoded in SAVE."));
1704 /* For standard SAVE the frame size of 0 means 128. */
1705 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1706 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1709 frame_offset
+= frame_size
;
1711 /* Now we can calculate what the SP must have been at the
1712 start of the function prologue. */
1715 /* Check if A0-A3 were saved in the caller's argument save area. */
1716 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1718 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1719 offset
+= mips_abi_regsize (gdbarch
);
1724 /* Check if the RA register was pushed on the stack. */
1725 if (save_inst
& 0x40)
1727 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1728 offset
-= mips_abi_regsize (gdbarch
);
1731 /* Check if the S8 register was pushed on the stack. */
1734 set_reg_offset (this_cache
, 30, sp
+ offset
);
1735 offset
-= mips_abi_regsize (gdbarch
);
1738 /* Check if S2-S7 were pushed on the stack. */
1739 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1741 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1742 offset
-= mips_abi_regsize (gdbarch
);
1745 /* Check if the S1 register was pushed on the stack. */
1746 if (save_inst
& 0x10)
1748 set_reg_offset (this_cache
, 17, sp
+ offset
);
1749 offset
-= mips_abi_regsize (gdbarch
);
1751 /* Check if the S0 register was pushed on the stack. */
1752 if (save_inst
& 0x20)
1754 set_reg_offset (this_cache
, 16, sp
+ offset
);
1755 offset
-= mips_abi_regsize (gdbarch
);
1758 /* Check if A0-A3 were pushed on the stack. */
1759 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1761 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1762 offset
-= mips_abi_regsize (gdbarch
);
1766 if (this_cache
!= NULL
)
1769 (frame_unwind_register_signed (next_frame
,
1770 gdbarch_num_regs (gdbarch
) + frame_reg
)
1771 + frame_offset
- frame_adjust
);
1772 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1773 be able to get rid of the assignment below, evetually. But it's
1774 still needed for now. */
1775 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1776 + mips_regnum (gdbarch
)->pc
]
1777 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1780 /* If we didn't reach the end of the prologue when scanning the function
1781 instructions, then set end_prologue_addr to the address of the
1782 instruction immediately after the last one we scanned. */
1783 if (end_prologue_addr
== 0)
1784 end_prologue_addr
= cur_pc
;
1786 return end_prologue_addr
;
1789 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1790 Procedures that use the 32-bit instruction set are handled by the
1791 mips_insn32 unwinder. */
1793 static struct mips_frame_cache
*
1794 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1796 struct mips_frame_cache
*cache
;
1798 if ((*this_cache
) != NULL
)
1799 return (*this_cache
);
1800 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1801 (*this_cache
) = cache
;
1802 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1804 /* Analyze the function prologue. */
1806 const CORE_ADDR pc
=
1807 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1808 CORE_ADDR start_addr
;
1810 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1811 if (start_addr
== 0)
1812 start_addr
= heuristic_proc_start (pc
);
1813 /* We can't analyze the prologue if we couldn't find the begining
1815 if (start_addr
== 0)
1818 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1821 /* gdbarch_sp_regnum contains the value and not the address. */
1822 trad_frame_set_value (cache
->saved_regs
,
1823 gdbarch_num_regs (get_frame_arch (next_frame
))
1827 return (*this_cache
);
1831 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1832 struct frame_id
*this_id
)
1834 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1836 (*this_id
) = frame_id_build (info
->base
,
1837 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1841 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1843 int regnum
, int *optimizedp
,
1844 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1845 int *realnump
, gdb_byte
*valuep
)
1847 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1849 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1850 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1853 static const struct frame_unwind mips_insn16_frame_unwind
=
1856 mips_insn16_frame_this_id
,
1857 mips_insn16_frame_prev_register
1860 static const struct frame_unwind
*
1861 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1863 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1864 if (mips_pc_is_mips16 (pc
))
1865 return &mips_insn16_frame_unwind
;
1870 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1873 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1878 static const struct frame_base mips_insn16_frame_base
=
1880 &mips_insn16_frame_unwind
,
1881 mips_insn16_frame_base_address
,
1882 mips_insn16_frame_base_address
,
1883 mips_insn16_frame_base_address
1886 static const struct frame_base
*
1887 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1889 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1890 return &mips_insn16_frame_base
;
1895 /* Mark all the registers as unset in the saved_regs array
1896 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1899 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1901 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1905 const int num_regs
= gdbarch_num_regs (current_gdbarch
);
1908 for (i
= 0; i
< num_regs
; i
++)
1910 this_cache
->saved_regs
[i
].addr
= -1;
1915 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1916 the associated FRAME_CACHE if not null.
1917 Return the address of the first instruction past the prologue. */
1920 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1921 struct frame_info
*next_frame
,
1922 struct mips_frame_cache
*this_cache
)
1925 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1928 int frame_reg
= MIPS_SP_REGNUM
;
1930 CORE_ADDR end_prologue_addr
= 0;
1931 int seen_sp_adjust
= 0;
1932 int load_immediate_bytes
= 0;
1933 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1934 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
1936 /* Can be called when there's no process, and hence when there's no
1938 if (next_frame
!= NULL
)
1939 sp
= frame_unwind_register_signed (next_frame
,
1940 gdbarch_num_regs (gdbarch
)
1945 if (limit_pc
> start_pc
+ 200)
1946 limit_pc
= start_pc
+ 200;
1951 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1953 unsigned long inst
, high_word
, low_word
;
1956 /* Fetch the instruction. */
1957 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1959 /* Save some code by pre-extracting some useful fields. */
1960 high_word
= (inst
>> 16) & 0xffff;
1961 low_word
= inst
& 0xffff;
1962 reg
= high_word
& 0x1f;
1964 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1965 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1966 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1968 if (low_word
& 0x8000) /* negative stack adjustment? */
1969 frame_offset
+= 0x10000 - low_word
;
1971 /* Exit loop if a positive stack adjustment is found, which
1972 usually means that the stack cleanup code in the function
1973 epilogue is reached. */
1977 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1978 && !regsize_is_64_bits
)
1980 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1982 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1983 && regsize_is_64_bits
)
1985 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1986 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1988 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1990 /* Old gcc frame, r30 is virtual frame pointer. */
1991 if ((long) low_word
!= frame_offset
)
1992 frame_addr
= sp
+ low_word
;
1993 else if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1995 unsigned alloca_adjust
;
1998 frame_addr
= frame_unwind_register_signed
1999 (next_frame
, gdbarch_num_regs (gdbarch
) + 30);
2001 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2002 if (alloca_adjust
> 0)
2004 /* FP > SP + frame_size. This may be because of
2005 an alloca or somethings similar. Fix sp to
2006 "pre-alloca" value, and try again. */
2007 sp
+= alloca_adjust
;
2008 /* Need to reset the status of all registers. Otherwise,
2009 we will hit a guard that prevents the new address
2010 for each register to be recomputed during the second
2012 reset_saved_regs (this_cache
);
2017 /* move $30,$sp. With different versions of gas this will be either
2018 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2019 Accept any one of these. */
2020 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2022 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2023 if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2025 unsigned alloca_adjust
;
2028 frame_addr
= frame_unwind_register_signed
2029 (next_frame
, gdbarch_num_regs (gdbarch
) + 30);
2031 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2032 if (alloca_adjust
> 0)
2034 /* FP > SP + frame_size. This may be because of
2035 an alloca or somethings similar. Fix sp to
2036 "pre-alloca" value, and try again. */
2038 /* Need to reset the status of all registers. Otherwise,
2039 we will hit a guard that prevents the new address
2040 for each register to be recomputed during the second
2042 reset_saved_regs (this_cache
);
2047 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2048 && !regsize_is_64_bits
)
2050 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
2052 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2053 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2054 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2055 || high_word
== 0x3c1c /* lui $gp,n */
2056 || high_word
== 0x279c /* addiu $gp,$gp,n */
2057 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2058 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2061 /* These instructions are part of the prologue, but we don't
2062 need to do anything special to handle them. */
2064 /* The instructions below load $at or $t0 with an immediate
2065 value in preparation for a stack adjustment via
2066 subu $sp,$sp,[$at,$t0]. These instructions could also
2067 initialize a local variable, so we accept them only before
2068 a stack adjustment instruction was seen. */
2069 else if (!seen_sp_adjust
2070 && (high_word
== 0x3c01 /* lui $at,n */
2071 || high_word
== 0x3c08 /* lui $t0,n */
2072 || high_word
== 0x3421 /* ori $at,$at,n */
2073 || high_word
== 0x3508 /* ori $t0,$t0,n */
2074 || high_word
== 0x3401 /* ori $at,$zero,n */
2075 || high_word
== 0x3408 /* ori $t0,$zero,n */
2078 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2082 /* This instruction is not an instruction typically found
2083 in a prologue, so we must have reached the end of the
2085 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2086 loop now? Why would we need to continue scanning the function
2088 if (end_prologue_addr
== 0)
2089 end_prologue_addr
= cur_pc
;
2093 if (this_cache
!= NULL
)
2096 (frame_unwind_register_signed (next_frame
,
2097 gdbarch_num_regs (gdbarch
) + frame_reg
)
2099 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2100 this assignment below, eventually. But it's still needed
2102 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2103 + mips_regnum (gdbarch
)->pc
]
2104 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2108 /* If we didn't reach the end of the prologue when scanning the function
2109 instructions, then set end_prologue_addr to the address of the
2110 instruction immediately after the last one we scanned. */
2111 /* brobecker/2004-10-10: I don't think this would ever happen, but
2112 we may as well be careful and do our best if we have a null
2113 end_prologue_addr. */
2114 if (end_prologue_addr
== 0)
2115 end_prologue_addr
= cur_pc
;
2117 /* In a frameless function, we might have incorrectly
2118 skipped some load immediate instructions. Undo the skipping
2119 if the load immediate was not followed by a stack adjustment. */
2120 if (load_immediate_bytes
&& !seen_sp_adjust
)
2121 end_prologue_addr
-= load_immediate_bytes
;
2123 return end_prologue_addr
;
2126 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2127 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2128 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2131 static struct mips_frame_cache
*
2132 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2134 struct mips_frame_cache
*cache
;
2136 if ((*this_cache
) != NULL
)
2137 return (*this_cache
);
2139 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2140 (*this_cache
) = cache
;
2141 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2143 /* Analyze the function prologue. */
2145 const CORE_ADDR pc
=
2146 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2147 CORE_ADDR start_addr
;
2149 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2150 if (start_addr
== 0)
2151 start_addr
= heuristic_proc_start (pc
);
2152 /* We can't analyze the prologue if we couldn't find the begining
2154 if (start_addr
== 0)
2157 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
2160 /* gdbarch_sp_regnum contains the value and not the address. */
2161 trad_frame_set_value (cache
->saved_regs
,
2162 gdbarch_num_regs (get_frame_arch (next_frame
))
2166 return (*this_cache
);
2170 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2171 struct frame_id
*this_id
)
2173 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2175 (*this_id
) = frame_id_build (info
->base
,
2176 frame_func_unwind (next_frame
, NORMAL_FRAME
));
2180 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2182 int regnum
, int *optimizedp
,
2183 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2184 int *realnump
, gdb_byte
*valuep
)
2186 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2188 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2189 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2192 static const struct frame_unwind mips_insn32_frame_unwind
=
2195 mips_insn32_frame_this_id
,
2196 mips_insn32_frame_prev_register
2199 static const struct frame_unwind
*
2200 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2202 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2203 if (! mips_pc_is_mips16 (pc
))
2204 return &mips_insn32_frame_unwind
;
2209 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2212 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2217 static const struct frame_base mips_insn32_frame_base
=
2219 &mips_insn32_frame_unwind
,
2220 mips_insn32_frame_base_address
,
2221 mips_insn32_frame_base_address
,
2222 mips_insn32_frame_base_address
2225 static const struct frame_base
*
2226 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2228 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2229 return &mips_insn32_frame_base
;
2234 static struct trad_frame_cache
*
2235 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2238 CORE_ADDR start_addr
;
2239 CORE_ADDR stack_addr
;
2240 struct trad_frame_cache
*this_trad_cache
;
2241 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2243 if ((*this_cache
) != NULL
)
2244 return (*this_cache
);
2245 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2246 (*this_cache
) = this_trad_cache
;
2248 /* The return address is in the link register. */
2249 trad_frame_set_reg_realreg (this_trad_cache
,
2250 gdbarch_pc_regnum (gdbarch
),
2251 (gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
));
2253 /* Frame ID, since it's a frameless / stackless function, no stack
2254 space is allocated and SP on entry is the current SP. */
2255 pc
= frame_pc_unwind (next_frame
);
2256 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2257 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2258 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2260 /* Assume that the frame's base is the same as the
2262 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2264 return this_trad_cache
;
2268 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2269 struct frame_id
*this_id
)
2271 struct trad_frame_cache
*this_trad_cache
2272 = mips_stub_frame_cache (next_frame
, this_cache
);
2273 trad_frame_get_id (this_trad_cache
, this_id
);
2277 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2279 int regnum
, int *optimizedp
,
2280 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2281 int *realnump
, gdb_byte
*valuep
)
2283 struct trad_frame_cache
*this_trad_cache
2284 = mips_stub_frame_cache (next_frame
, this_cache
);
2285 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2286 lvalp
, addrp
, realnump
, valuep
);
2289 static const struct frame_unwind mips_stub_frame_unwind
=
2292 mips_stub_frame_this_id
,
2293 mips_stub_frame_prev_register
2296 static const struct frame_unwind
*
2297 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2300 struct obj_section
*s
;
2301 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2303 /* Use the stub unwinder for unreadable code. */
2304 if (target_read_memory (frame_pc_unwind (next_frame
), dummy
, 4) != 0)
2305 return &mips_stub_frame_unwind
;
2307 if (in_plt_section (pc
, NULL
))
2308 return &mips_stub_frame_unwind
;
2310 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2311 s
= find_pc_section (pc
);
2314 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2315 ".MIPS.stubs") == 0)
2316 return &mips_stub_frame_unwind
;
2322 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2325 struct trad_frame_cache
*this_trad_cache
2326 = mips_stub_frame_cache (next_frame
, this_cache
);
2327 return trad_frame_get_this_base (this_trad_cache
);
2330 static const struct frame_base mips_stub_frame_base
=
2332 &mips_stub_frame_unwind
,
2333 mips_stub_frame_base_address
,
2334 mips_stub_frame_base_address
,
2335 mips_stub_frame_base_address
2338 static const struct frame_base
*
2339 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2341 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2342 return &mips_stub_frame_base
;
2347 /* mips_addr_bits_remove - remove useless address bits */
2350 mips_addr_bits_remove (CORE_ADDR addr
)
2352 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2353 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2354 /* This hack is a work-around for existing boards using PMON, the
2355 simulator, and any other 64-bit targets that doesn't have true
2356 64-bit addressing. On these targets, the upper 32 bits of
2357 addresses are ignored by the hardware. Thus, the PC or SP are
2358 likely to have been sign extended to all 1s by instruction
2359 sequences that load 32-bit addresses. For example, a typical
2360 piece of code that loads an address is this:
2362 lui $r2, <upper 16 bits>
2363 ori $r2, <lower 16 bits>
2365 But the lui sign-extends the value such that the upper 32 bits
2366 may be all 1s. The workaround is simply to mask off these
2367 bits. In the future, gcc may be changed to support true 64-bit
2368 addressing, and this masking will have to be disabled. */
2369 return addr
&= 0xffffffffUL
;
2374 /* Instructions used during single-stepping of atomic sequences. */
2375 #define LL_OPCODE 0x30
2376 #define LLD_OPCODE 0x34
2377 #define SC_OPCODE 0x38
2378 #define SCD_OPCODE 0x3c
2380 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2381 instruction and ending with a SC/SCD instruction. If such a sequence
2382 is found, attempt to step through it. A breakpoint is placed at the end of
2386 deal_with_atomic_sequence (CORE_ADDR pc
)
2388 CORE_ADDR breaks
[2] = {-1, -1};
2390 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2394 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2395 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2400 insn
= mips_fetch_instruction (loc
);
2401 /* Assume all atomic sequences start with a ll/lld instruction. */
2402 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2405 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2407 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2410 loc
+= MIPS_INSN32_SIZE
;
2411 insn
= mips_fetch_instruction (loc
);
2413 /* Assume that there is at most one branch in the atomic
2414 sequence. If a branch is found, put a breakpoint in its
2415 destination address. */
2416 switch (itype_op (insn
))
2418 case 0: /* SPECIAL */
2419 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2420 return 0; /* fallback to the standard single-step code. */
2422 case 1: /* REGIMM */
2423 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2427 return 0; /* fallback to the standard single-step code. */
2434 case 22: /* BLEZL */
2435 case 23: /* BGTTL */
2441 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2446 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2447 if (last_breakpoint
>= 1)
2448 return 0; /* More than one branch found, fallback to the
2449 standard single-step code. */
2450 breaks
[1] = branch_bp
;
2454 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2458 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2459 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2462 loc
+= MIPS_INSN32_SIZE
;
2464 /* Insert a breakpoint right after the end of the atomic sequence. */
2467 /* Check for duplicated breakpoints. Check also for a breakpoint
2468 placed (branch instruction's destination) in the atomic sequence */
2469 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2470 last_breakpoint
= 0;
2472 /* Effectively inserts the breakpoints. */
2473 for (index
= 0; index
<= last_breakpoint
; index
++)
2474 insert_single_step_breakpoint (breaks
[index
]);
2479 /* mips_software_single_step() is called just before we want to resume
2480 the inferior, if we want to single-step it but there is no hardware
2481 or kernel single-step support (MIPS on GNU/Linux for example). We find
2482 the target of the coming instruction and breakpoint it. */
2485 mips_software_single_step (struct frame_info
*frame
)
2487 CORE_ADDR pc
, next_pc
;
2489 pc
= get_frame_pc (frame
);
2490 if (deal_with_atomic_sequence (pc
))
2493 next_pc
= mips_next_pc (frame
, pc
);
2495 insert_single_step_breakpoint (next_pc
);
2499 /* Test whether the PC points to the return instruction at the
2500 end of a function. */
2503 mips_about_to_return (CORE_ADDR pc
)
2505 if (mips_pc_is_mips16 (pc
))
2506 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2507 generates a "jr $ra"; other times it generates code to load
2508 the return address from the stack to an accessible register (such
2509 as $a3), then a "jr" using that register. This second case
2510 is almost impossible to distinguish from an indirect jump
2511 used for switch statements, so we don't even try. */
2512 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2514 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2518 /* This fencepost looks highly suspicious to me. Removing it also
2519 seems suspicious as it could affect remote debugging across serial
2523 heuristic_proc_start (CORE_ADDR pc
)
2530 pc
= gdbarch_addr_bits_remove (current_gdbarch
, pc
);
2532 fence
= start_pc
- heuristic_fence_post
;
2536 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2537 fence
= VM_MIN_ADDRESS
;
2539 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2541 /* search back for previous return */
2542 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2543 if (start_pc
< fence
)
2545 /* It's not clear to me why we reach this point when
2546 stop_soon, but with this test, at least we
2547 don't print out warnings for every child forked (eg, on
2548 decstation). 22apr93 rich@cygnus.com. */
2549 if (stop_soon
== NO_STOP_QUIETLY
)
2551 static int blurb_printed
= 0;
2553 warning (_("GDB can't find the start of the function at 0x%s."),
2558 /* This actually happens frequently in embedded
2559 development, when you first connect to a board
2560 and your stack pointer and pc are nowhere in
2561 particular. This message needs to give people
2562 in that situation enough information to
2563 determine that it's no big deal. */
2564 printf_filtered ("\n\
2565 GDB is unable to find the start of the function at 0x%s\n\
2566 and thus can't determine the size of that function's stack frame.\n\
2567 This means that GDB may be unable to access that stack frame, or\n\
2568 the frames below it.\n\
2569 This problem is most likely caused by an invalid program counter or\n\
2571 However, if you think GDB should simply search farther back\n\
2572 from 0x%s for code which looks like the beginning of a\n\
2573 function, you can increase the range of the search using the `set\n\
2574 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2581 else if (mips_pc_is_mips16 (start_pc
))
2583 unsigned short inst
;
2585 /* On MIPS16, any one of the following is likely to be the
2586 start of a function:
2592 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2593 inst
= mips_fetch_instruction (start_pc
);
2594 if ((inst
& 0xff80) == 0x6480) /* save */
2596 if (start_pc
- instlen
>= fence
)
2598 inst
= mips_fetch_instruction (start_pc
- instlen
);
2599 if ((inst
& 0xf800) == 0xf000) /* extend */
2600 start_pc
-= instlen
;
2604 else if (((inst
& 0xf81f) == 0xe809
2605 && (inst
& 0x700) != 0x700) /* entry */
2606 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2607 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2608 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2610 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2611 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2616 else if (mips_about_to_return (start_pc
))
2618 /* Skip return and its delay slot. */
2619 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2626 struct mips_objfile_private
2632 /* According to the current ABI, should the type be passed in a
2633 floating-point register (assuming that there is space)? When there
2634 is no FPU, FP are not even considered as possible candidates for
2635 FP registers and, consequently this returns false - forces FP
2636 arguments into integer registers. */
2639 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2641 return ((typecode
== TYPE_CODE_FLT
2643 && (typecode
== TYPE_CODE_STRUCT
2644 || typecode
== TYPE_CODE_UNION
)
2645 && TYPE_NFIELDS (arg_type
) == 1
2646 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2648 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2651 /* On o32, argument passing in GPRs depends on the alignment of the type being
2652 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2655 mips_type_needs_double_align (struct type
*type
)
2657 enum type_code typecode
= TYPE_CODE (type
);
2659 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2661 else if (typecode
== TYPE_CODE_STRUCT
)
2663 if (TYPE_NFIELDS (type
) < 1)
2665 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2667 else if (typecode
== TYPE_CODE_UNION
)
2671 n
= TYPE_NFIELDS (type
);
2672 for (i
= 0; i
< n
; i
++)
2673 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2680 /* Adjust the address downward (direction of stack growth) so that it
2681 is correctly aligned for a new stack frame. */
2683 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2685 return align_down (addr
, 16);
2689 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2690 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2691 int nargs
, struct value
**args
, CORE_ADDR sp
,
2692 int struct_return
, CORE_ADDR struct_addr
)
2698 int stack_offset
= 0;
2699 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2700 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2701 int regsize
= mips_abi_regsize (gdbarch
);
2703 /* For shared libraries, "t9" needs to point at the function
2705 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2707 /* Set the return address register to point to the entry point of
2708 the program, where a breakpoint lies in wait. */
2709 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2711 /* First ensure that the stack and structure return address (if any)
2712 are properly aligned. The stack has to be at least 64-bit
2713 aligned even on 32-bit machines, because doubles must be 64-bit
2714 aligned. For n32 and n64, stack frames need to be 128-bit
2715 aligned, so we round to this widest known alignment. */
2717 sp
= align_down (sp
, 16);
2718 struct_addr
= align_down (struct_addr
, 16);
2720 /* Now make space on the stack for the args. We allocate more
2721 than necessary for EABI, because the first few arguments are
2722 passed in registers, but that's OK. */
2723 for (argnum
= 0; argnum
< nargs
; argnum
++)
2724 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2725 sp
-= align_up (len
, 16);
2728 fprintf_unfiltered (gdb_stdlog
,
2729 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2730 paddr_nz (sp
), (long) align_up (len
, 16));
2732 /* Initialize the integer and float register pointers. */
2733 argreg
= MIPS_A0_REGNUM
;
2734 float_argreg
= mips_fpa0_regnum (gdbarch
);
2736 /* The struct_return pointer occupies the first parameter-passing reg. */
2740 fprintf_unfiltered (gdb_stdlog
,
2741 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2742 argreg
, paddr_nz (struct_addr
));
2743 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2746 /* Now load as many as possible of the first arguments into
2747 registers, and push the rest onto the stack. Loop thru args
2748 from first to last. */
2749 for (argnum
= 0; argnum
< nargs
; argnum
++)
2751 const gdb_byte
*val
;
2752 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2753 struct value
*arg
= args
[argnum
];
2754 struct type
*arg_type
= check_typedef (value_type (arg
));
2755 int len
= TYPE_LENGTH (arg_type
);
2756 enum type_code typecode
= TYPE_CODE (arg_type
);
2759 fprintf_unfiltered (gdb_stdlog
,
2760 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2761 argnum
+ 1, len
, (int) typecode
);
2763 /* The EABI passes structures that do not fit in a register by
2766 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2768 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2769 typecode
= TYPE_CODE_PTR
;
2773 fprintf_unfiltered (gdb_stdlog
, " push");
2776 val
= value_contents (arg
);
2778 /* 32-bit ABIs always start floating point arguments in an
2779 even-numbered floating point register. Round the FP register
2780 up before the check to see if there are any FP registers
2781 left. Non MIPS_EABI targets also pass the FP in the integer
2782 registers so also round up normal registers. */
2783 if (regsize
< 8 && fp_register_arg_p (typecode
, arg_type
))
2785 if ((float_argreg
& 1))
2789 /* Floating point arguments passed in registers have to be
2790 treated specially. On 32-bit architectures, doubles
2791 are passed in register pairs; the even register gets
2792 the low word, and the odd register gets the high word.
2793 On non-EABI processors, the first two floating point arguments are
2794 also copied to general registers, because MIPS16 functions
2795 don't use float registers for arguments. This duplication of
2796 arguments in general registers can't hurt non-MIPS16 functions
2797 because those registers are normally skipped. */
2798 /* MIPS_EABI squeezes a struct that contains a single floating
2799 point value into an FP register instead of pushing it onto the
2801 if (fp_register_arg_p (typecode
, arg_type
)
2802 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2804 /* EABI32 will pass doubles in consecutive registers, even on
2805 64-bit cores. At one time, we used to check the size of
2806 `float_argreg' to determine whether or not to pass doubles
2807 in consecutive registers, but this is not sufficient for
2808 making the ABI determination. */
2809 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2811 int low_offset
= gdbarch_byte_order (gdbarch
)
2812 == BFD_ENDIAN_BIG
? 4 : 0;
2813 unsigned long regval
;
2815 /* Write the low word of the double to the even register(s). */
2816 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2818 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2819 float_argreg
, phex (regval
, 4));
2820 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2822 /* Write the high word of the double to the odd register(s). */
2823 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2825 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2826 float_argreg
, phex (regval
, 4));
2827 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2831 /* This is a floating point value that fits entirely
2832 in a single register. */
2833 /* On 32 bit ABI's the float_argreg is further adjusted
2834 above to ensure that it is even register aligned. */
2835 LONGEST regval
= extract_unsigned_integer (val
, len
);
2837 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2838 float_argreg
, phex (regval
, len
));
2839 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2844 /* Copy the argument to general registers or the stack in
2845 register-sized pieces. Large arguments are split between
2846 registers and stack. */
2847 /* Note: structs whose size is not a multiple of regsize
2848 are treated specially: Irix cc passes
2849 them in registers where gcc sometimes puts them on the
2850 stack. For maximum compatibility, we will put them in
2852 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2854 /* Note: Floating-point values that didn't fit into an FP
2855 register are only written to memory. */
2858 /* Remember if the argument was written to the stack. */
2859 int stack_used_p
= 0;
2860 int partial_len
= (len
< regsize
? len
: regsize
);
2863 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2866 /* Write this portion of the argument to the stack. */
2867 if (argreg
> MIPS_LAST_ARG_REGNUM
2869 || fp_register_arg_p (typecode
, arg_type
))
2871 /* Should shorter than int integer values be
2872 promoted to int before being stored? */
2873 int longword_offset
= 0;
2876 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2879 && (typecode
== TYPE_CODE_INT
2880 || typecode
== TYPE_CODE_PTR
2881 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2882 longword_offset
= regsize
- len
;
2883 else if ((typecode
== TYPE_CODE_STRUCT
2884 || typecode
== TYPE_CODE_UNION
)
2885 && TYPE_LENGTH (arg_type
) < regsize
)
2886 longword_offset
= regsize
- len
;
2891 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2892 paddr_nz (stack_offset
));
2893 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2894 paddr_nz (longword_offset
));
2897 addr
= sp
+ stack_offset
+ longword_offset
;
2902 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2904 for (i
= 0; i
< partial_len
; i
++)
2906 fprintf_unfiltered (gdb_stdlog
, "%02x",
2910 write_memory (addr
, val
, partial_len
);
2913 /* Note!!! This is NOT an else clause. Odd sized
2914 structs may go thru BOTH paths. Floating point
2915 arguments will not. */
2916 /* Write this portion of the argument to a general
2917 purpose register. */
2918 if (argreg
<= MIPS_LAST_ARG_REGNUM
2919 && !fp_register_arg_p (typecode
, arg_type
))
2922 extract_unsigned_integer (val
, partial_len
);
2925 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2927 phex (regval
, regsize
));
2928 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2935 /* Compute the the offset into the stack at which we
2936 will copy the next parameter.
2938 In the new EABI (and the NABI32), the stack_offset
2939 only needs to be adjusted when it has been used. */
2942 stack_offset
+= align_up (partial_len
, regsize
);
2946 fprintf_unfiltered (gdb_stdlog
, "\n");
2949 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2951 /* Return adjusted stack pointer. */
2955 /* Determine the return value convention being used. */
2957 static enum return_value_convention
2958 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2959 struct type
*type
, struct regcache
*regcache
,
2960 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2962 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2963 return RETURN_VALUE_STRUCT_CONVENTION
;
2965 memset (readbuf
, 0, TYPE_LENGTH (type
));
2966 return RETURN_VALUE_REGISTER_CONVENTION
;
2970 /* N32/N64 ABI stuff. */
2972 /* Search for a naturally aligned double at OFFSET inside a struct
2973 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
2977 mips_n32n64_fp_arg_chunk_p (struct type
*arg_type
, int offset
)
2981 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
2984 if (MIPS_FPU_TYPE
!= MIPS_FPU_DOUBLE
)
2987 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
2990 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
2993 struct type
*field_type
;
2995 /* We're only looking at normal fields. */
2996 if (TYPE_FIELD_STATIC (arg_type
, i
)
2997 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3000 /* If we have gone past the offset, there is no double to pass. */
3001 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3005 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3007 /* If this field is entirely before the requested offset, go
3008 on to the next one. */
3009 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3012 /* If this is our special aligned double, we can stop. */
3013 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3014 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3017 /* This field starts at or before the requested offset, and
3018 overlaps it. If it is a structure, recurse inwards. */
3019 return mips_n32n64_fp_arg_chunk_p (field_type
, offset
- pos
);
3026 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3027 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3028 int nargs
, struct value
**args
, CORE_ADDR sp
,
3029 int struct_return
, CORE_ADDR struct_addr
)
3035 int stack_offset
= 0;
3036 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3037 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3039 /* For shared libraries, "t9" needs to point at the function
3041 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3043 /* Set the return address register to point to the entry point of
3044 the program, where a breakpoint lies in wait. */
3045 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3047 /* First ensure that the stack and structure return address (if any)
3048 are properly aligned. The stack has to be at least 64-bit
3049 aligned even on 32-bit machines, because doubles must be 64-bit
3050 aligned. For n32 and n64, stack frames need to be 128-bit
3051 aligned, so we round to this widest known alignment. */
3053 sp
= align_down (sp
, 16);
3054 struct_addr
= align_down (struct_addr
, 16);
3056 /* Now make space on the stack for the args. */
3057 for (argnum
= 0; argnum
< nargs
; argnum
++)
3058 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3059 sp
-= align_up (len
, 16);
3062 fprintf_unfiltered (gdb_stdlog
,
3063 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3064 paddr_nz (sp
), (long) align_up (len
, 16));
3066 /* Initialize the integer and float register pointers. */
3067 argreg
= MIPS_A0_REGNUM
;
3068 float_argreg
= mips_fpa0_regnum (gdbarch
);
3070 /* The struct_return pointer occupies the first parameter-passing reg. */
3074 fprintf_unfiltered (gdb_stdlog
,
3075 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3076 argreg
, paddr_nz (struct_addr
));
3077 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3080 /* Now load as many as possible of the first arguments into
3081 registers, and push the rest onto the stack. Loop thru args
3082 from first to last. */
3083 for (argnum
= 0; argnum
< nargs
; argnum
++)
3085 const gdb_byte
*val
;
3086 struct value
*arg
= args
[argnum
];
3087 struct type
*arg_type
= check_typedef (value_type (arg
));
3088 int len
= TYPE_LENGTH (arg_type
);
3089 enum type_code typecode
= TYPE_CODE (arg_type
);
3092 fprintf_unfiltered (gdb_stdlog
,
3093 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3094 argnum
+ 1, len
, (int) typecode
);
3096 val
= value_contents (arg
);
3098 if (fp_register_arg_p (typecode
, arg_type
)
3099 && argreg
<= MIPS_LAST_ARG_REGNUM
)
3101 /* This is a floating point value that fits entirely
3102 in a single register. */
3103 LONGEST regval
= extract_unsigned_integer (val
, len
);
3105 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3106 float_argreg
, phex (regval
, len
));
3107 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3110 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3111 argreg
, phex (regval
, len
));
3112 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3118 /* Copy the argument to general registers or the stack in
3119 register-sized pieces. Large arguments are split between
3120 registers and stack. */
3121 /* For N32/N64, structs, unions, or other composite types are
3122 treated as a sequence of doublewords, and are passed in integer
3123 or floating point registers as though they were simple scalar
3124 parameters to the extent that they fit, with any excess on the
3125 stack packed according to the normal memory layout of the
3127 The caller does not reserve space for the register arguments;
3128 the callee is responsible for reserving it if required. */
3129 /* Note: Floating-point values that didn't fit into an FP
3130 register are only written to memory. */
3133 /* Remember if the argument was written to the stack. */
3134 int stack_used_p
= 0;
3135 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3138 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3141 if (fp_register_arg_p (typecode
, arg_type
))
3142 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM
);
3144 /* Write this portion of the argument to the stack. */
3145 if (argreg
> MIPS_LAST_ARG_REGNUM
)
3147 /* Should shorter than int integer values be
3148 promoted to int before being stored? */
3149 int longword_offset
= 0;
3152 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3154 if ((typecode
== TYPE_CODE_INT
3155 || typecode
== TYPE_CODE_PTR
3156 || typecode
== TYPE_CODE_FLT
)
3158 longword_offset
= MIPS64_REGSIZE
- len
;
3163 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3164 paddr_nz (stack_offset
));
3165 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3166 paddr_nz (longword_offset
));
3169 addr
= sp
+ stack_offset
+ longword_offset
;
3174 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3176 for (i
= 0; i
< partial_len
; i
++)
3178 fprintf_unfiltered (gdb_stdlog
, "%02x",
3182 write_memory (addr
, val
, partial_len
);
3185 /* Note!!! This is NOT an else clause. Odd sized
3186 structs may go thru BOTH paths. */
3187 /* Write this portion of the argument to a general
3188 purpose register. */
3189 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3193 /* Sign extend pointers, 32-bit integers and signed
3194 16-bit and 8-bit integers; everything else is taken
3197 if ((partial_len
== 4
3198 && (typecode
== TYPE_CODE_PTR
3199 || typecode
== TYPE_CODE_INT
))
3201 && typecode
== TYPE_CODE_INT
3202 && !TYPE_UNSIGNED (arg_type
)))
3203 regval
= extract_signed_integer (val
, partial_len
);
3205 regval
= extract_unsigned_integer (val
, partial_len
);
3207 /* A non-floating-point argument being passed in a
3208 general register. If a struct or union, and if
3209 the remaining length is smaller than the register
3210 size, we have to adjust the register value on
3213 It does not seem to be necessary to do the
3214 same for integral types. */
3216 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3217 && partial_len
< MIPS64_REGSIZE
3218 && (typecode
== TYPE_CODE_STRUCT
3219 || typecode
== TYPE_CODE_UNION
))
3220 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3224 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3226 phex (regval
, MIPS64_REGSIZE
));
3227 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3229 if (mips_n32n64_fp_arg_chunk_p (arg_type
,
3230 TYPE_LENGTH (arg_type
) - len
))
3233 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3235 phex (regval
, MIPS64_REGSIZE
));
3236 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3247 /* Compute the the offset into the stack at which we
3248 will copy the next parameter.
3250 In N32 (N64?), the stack_offset only needs to be
3251 adjusted when it has been used. */
3254 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3258 fprintf_unfiltered (gdb_stdlog
, "\n");
3261 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3263 /* Return adjusted stack pointer. */
3267 static enum return_value_convention
3268 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3269 struct type
*type
, struct regcache
*regcache
,
3270 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3272 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3274 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3276 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3277 if needed), as appropriate for the type. Composite results (struct,
3278 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3281 * A struct with only one or two floating point fields is returned in $f0
3282 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3285 * Any other struct or union results of at most 128 bits are returned in
3286 $2 (first 64 bits) and $3 (remainder, if necessary).
3288 * Larger composite results are handled by converting the function to a
3289 procedure with an implicit first parameter, which is a pointer to an area
3290 reserved by the caller to receive the result. [The o32-bit ABI requires
3291 that all composite results be handled by conversion to implicit first
3292 parameters. The MIPS/SGI Fortran implementation has always made a
3293 specific exception to return COMPLEX results in the floating point
3296 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
3297 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3298 return RETURN_VALUE_STRUCT_CONVENTION
;
3299 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3300 && TYPE_LENGTH (type
) == 16
3301 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3303 /* A 128-bit floating-point value fills both $f0 and $f2. The
3304 two registers are used in the same as memory order, so the
3305 eight bytes with the lower memory address are in $f0. */
3307 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3308 mips_xfer_register (gdbarch
, regcache
,
3309 gdbarch_num_regs (gdbarch
)
3310 + mips_regnum (gdbarch
)->fp0
,
3311 8, gdbarch_byte_order (gdbarch
),
3312 readbuf
, writebuf
, 0);
3313 mips_xfer_register (gdbarch
, regcache
,
3314 gdbarch_num_regs (gdbarch
)
3315 + mips_regnum (gdbarch
)->fp0
+ 2,
3316 8, gdbarch_byte_order (gdbarch
),
3317 readbuf
? readbuf
+ 8 : readbuf
,
3318 writebuf
? writebuf
+ 8 : writebuf
, 0);
3319 return RETURN_VALUE_REGISTER_CONVENTION
;
3321 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3322 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3324 /* A single or double floating-point value that fits in FP0. */
3326 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3327 mips_xfer_register (gdbarch
, regcache
,
3328 gdbarch_num_regs (gdbarch
)
3329 + mips_regnum (gdbarch
)->fp0
,
3331 gdbarch_byte_order (gdbarch
),
3332 readbuf
, writebuf
, 0);
3333 return RETURN_VALUE_REGISTER_CONVENTION
;
3335 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3336 && TYPE_NFIELDS (type
) <= 2
3337 && TYPE_NFIELDS (type
) >= 1
3338 && ((TYPE_NFIELDS (type
) == 1
3339 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3341 || (TYPE_NFIELDS (type
) == 2
3342 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3344 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3346 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3348 /* A struct that contains one or two floats. Each value is part
3349 in the least significant part of their floating point
3353 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3354 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3356 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3359 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3361 mips_xfer_register (gdbarch
, regcache
,
3362 gdbarch_num_regs (gdbarch
) + regnum
,
3363 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3364 gdbarch_byte_order (gdbarch
),
3365 readbuf
, writebuf
, offset
);
3367 return RETURN_VALUE_REGISTER_CONVENTION
;
3369 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3370 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3372 /* A structure or union. Extract the left justified value,
3373 regardless of the byte order. I.e. DO NOT USE
3377 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3378 offset
< TYPE_LENGTH (type
);
3379 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3381 int xfer
= register_size (gdbarch
, regnum
);
3382 if (offset
+ xfer
> TYPE_LENGTH (type
))
3383 xfer
= TYPE_LENGTH (type
) - offset
;
3385 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3386 offset
, xfer
, regnum
);
3387 mips_xfer_register (gdbarch
, regcache
,
3388 gdbarch_num_regs (gdbarch
) + regnum
,
3389 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3392 return RETURN_VALUE_REGISTER_CONVENTION
;
3396 /* A scalar extract each part but least-significant-byte
3400 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3401 offset
< TYPE_LENGTH (type
);
3402 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3404 int xfer
= register_size (gdbarch
, regnum
);
3405 if (offset
+ xfer
> TYPE_LENGTH (type
))
3406 xfer
= TYPE_LENGTH (type
) - offset
;
3408 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3409 offset
, xfer
, regnum
);
3410 mips_xfer_register (gdbarch
, regcache
,
3411 gdbarch_num_regs (gdbarch
) + regnum
,
3412 xfer
, gdbarch_byte_order (gdbarch
),
3413 readbuf
, writebuf
, offset
);
3415 return RETURN_VALUE_REGISTER_CONVENTION
;
3419 /* O32 ABI stuff. */
3422 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3423 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3424 int nargs
, struct value
**args
, CORE_ADDR sp
,
3425 int struct_return
, CORE_ADDR struct_addr
)
3431 int stack_offset
= 0;
3432 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3433 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3435 /* For shared libraries, "t9" needs to point at the function
3437 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3439 /* Set the return address register to point to the entry point of
3440 the program, where a breakpoint lies in wait. */
3441 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3443 /* First ensure that the stack and structure return address (if any)
3444 are properly aligned. The stack has to be at least 64-bit
3445 aligned even on 32-bit machines, because doubles must be 64-bit
3446 aligned. For n32 and n64, stack frames need to be 128-bit
3447 aligned, so we round to this widest known alignment. */
3449 sp
= align_down (sp
, 16);
3450 struct_addr
= align_down (struct_addr
, 16);
3452 /* Now make space on the stack for the args. */
3453 for (argnum
= 0; argnum
< nargs
; argnum
++)
3455 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3456 int arglen
= TYPE_LENGTH (arg_type
);
3458 /* Align to double-word if necessary. */
3459 if (mips_type_needs_double_align (arg_type
))
3460 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3461 /* Allocate space on the stack. */
3462 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3464 sp
-= align_up (len
, 16);
3467 fprintf_unfiltered (gdb_stdlog
,
3468 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3469 paddr_nz (sp
), (long) align_up (len
, 16));
3471 /* Initialize the integer and float register pointers. */
3472 argreg
= MIPS_A0_REGNUM
;
3473 float_argreg
= mips_fpa0_regnum (gdbarch
);
3475 /* The struct_return pointer occupies the first parameter-passing reg. */
3479 fprintf_unfiltered (gdb_stdlog
,
3480 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3481 argreg
, paddr_nz (struct_addr
));
3482 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3483 stack_offset
+= MIPS32_REGSIZE
;
3486 /* Now load as many as possible of the first arguments into
3487 registers, and push the rest onto the stack. Loop thru args
3488 from first to last. */
3489 for (argnum
= 0; argnum
< nargs
; argnum
++)
3491 const gdb_byte
*val
;
3492 struct value
*arg
= args
[argnum
];
3493 struct type
*arg_type
= check_typedef (value_type (arg
));
3494 int len
= TYPE_LENGTH (arg_type
);
3495 enum type_code typecode
= TYPE_CODE (arg_type
);
3498 fprintf_unfiltered (gdb_stdlog
,
3499 "mips_o32_push_dummy_call: %d len=%d type=%d",
3500 argnum
+ 1, len
, (int) typecode
);
3502 val
= value_contents (arg
);
3504 /* 32-bit ABIs always start floating point arguments in an
3505 even-numbered floating point register. Round the FP register
3506 up before the check to see if there are any FP registers
3507 left. O32/O64 targets also pass the FP in the integer
3508 registers so also round up normal registers. */
3509 if (fp_register_arg_p (typecode
, arg_type
))
3511 if ((float_argreg
& 1))
3515 /* Floating point arguments passed in registers have to be
3516 treated specially. On 32-bit architectures, doubles
3517 are passed in register pairs; the even register gets
3518 the low word, and the odd register gets the high word.
3519 On O32/O64, the first two floating point arguments are
3520 also copied to general registers, because MIPS16 functions
3521 don't use float registers for arguments. This duplication of
3522 arguments in general registers can't hurt non-MIPS16 functions
3523 because those registers are normally skipped. */
3525 if (fp_register_arg_p (typecode
, arg_type
)
3526 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3528 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3530 int low_offset
= gdbarch_byte_order (gdbarch
)
3531 == BFD_ENDIAN_BIG
? 4 : 0;
3532 unsigned long regval
;
3534 /* Write the low word of the double to the even register(s). */
3535 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3537 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3538 float_argreg
, phex (regval
, 4));
3539 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3541 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3542 argreg
, phex (regval
, 4));
3543 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3545 /* Write the high word of the double to the odd register(s). */
3546 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3548 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3549 float_argreg
, phex (regval
, 4));
3550 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3553 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3554 argreg
, phex (regval
, 4));
3555 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3559 /* This is a floating point value that fits entirely
3560 in a single register. */
3561 /* On 32 bit ABI's the float_argreg is further adjusted
3562 above to ensure that it is even register aligned. */
3563 LONGEST regval
= extract_unsigned_integer (val
, len
);
3565 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3566 float_argreg
, phex (regval
, len
));
3567 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3568 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3569 registers for each argument. The below is (my
3570 guess) to ensure that the corresponding integer
3571 register has reserved the same space. */
3573 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3574 argreg
, phex (regval
, len
));
3575 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3578 /* Reserve space for the FP register. */
3579 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3583 /* Copy the argument to general registers or the stack in
3584 register-sized pieces. Large arguments are split between
3585 registers and stack. */
3586 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3587 are treated specially: Irix cc passes
3588 them in registers where gcc sometimes puts them on the
3589 stack. For maximum compatibility, we will put them in
3591 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3592 && len
% MIPS32_REGSIZE
!= 0);
3593 /* Structures should be aligned to eight bytes (even arg registers)
3594 on MIPS_ABI_O32, if their first member has double precision. */
3595 if (mips_type_needs_double_align (arg_type
))
3600 stack_offset
+= MIPS32_REGSIZE
;
3605 /* Remember if the argument was written to the stack. */
3606 int stack_used_p
= 0;
3607 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3610 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3613 /* Write this portion of the argument to the stack. */
3614 if (argreg
> MIPS_LAST_ARG_REGNUM
3615 || odd_sized_struct
)
3617 /* Should shorter than int integer values be
3618 promoted to int before being stored? */
3619 int longword_offset
= 0;
3625 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3626 paddr_nz (stack_offset
));
3627 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3628 paddr_nz (longword_offset
));
3631 addr
= sp
+ stack_offset
+ longword_offset
;
3636 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3638 for (i
= 0; i
< partial_len
; i
++)
3640 fprintf_unfiltered (gdb_stdlog
, "%02x",
3644 write_memory (addr
, val
, partial_len
);
3647 /* Note!!! This is NOT an else clause. Odd sized
3648 structs may go thru BOTH paths. */
3649 /* Write this portion of the argument to a general
3650 purpose register. */
3651 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3653 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3654 /* Value may need to be sign extended, because
3655 mips_isa_regsize() != mips_abi_regsize(). */
3657 /* A non-floating-point argument being passed in a
3658 general register. If a struct or union, and if
3659 the remaining length is smaller than the register
3660 size, we have to adjust the register value on
3663 It does not seem to be necessary to do the
3664 same for integral types.
3666 Also don't do this adjustment on O64 binaries.
3668 cagney/2001-07-23: gdb/179: Also, GCC, when
3669 outputting LE O32 with sizeof (struct) <
3670 mips_abi_regsize(), generates a left shift
3671 as part of storing the argument in a register
3672 (the left shift isn't generated when
3673 sizeof (struct) >= mips_abi_regsize()). Since
3674 it is quite possible that this is GCC
3675 contradicting the LE/O32 ABI, GDB has not been
3676 adjusted to accommodate this. Either someone
3677 needs to demonstrate that the LE/O32 ABI
3678 specifies such a left shift OR this new ABI gets
3679 identified as such and GDB gets tweaked
3682 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3683 && partial_len
< MIPS32_REGSIZE
3684 && (typecode
== TYPE_CODE_STRUCT
3685 || typecode
== TYPE_CODE_UNION
))
3686 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3690 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3692 phex (regval
, MIPS32_REGSIZE
));
3693 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3696 /* Prevent subsequent floating point arguments from
3697 being passed in floating point registers. */
3698 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3704 /* Compute the the offset into the stack at which we
3705 will copy the next parameter.
3707 In older ABIs, the caller reserved space for
3708 registers that contained arguments. This was loosely
3709 refered to as their "home". Consequently, space is
3710 always allocated. */
3712 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3716 fprintf_unfiltered (gdb_stdlog
, "\n");
3719 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3721 /* Return adjusted stack pointer. */
3725 static enum return_value_convention
3726 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3727 struct regcache
*regcache
,
3728 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3730 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3732 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3733 || TYPE_CODE (type
) == TYPE_CODE_UNION
3734 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3735 return RETURN_VALUE_STRUCT_CONVENTION
;
3736 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3737 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3739 /* A single-precision floating-point value. It fits in the
3740 least significant part of FP0. */
3742 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3743 mips_xfer_register (gdbarch
, regcache
,
3744 gdbarch_num_regs (gdbarch
)
3745 + mips_regnum (gdbarch
)->fp0
,
3747 gdbarch_byte_order (gdbarch
),
3748 readbuf
, writebuf
, 0);
3749 return RETURN_VALUE_REGISTER_CONVENTION
;
3751 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3752 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3754 /* A double-precision floating-point value. The most
3755 significant part goes in FP1, and the least significant in
3758 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3759 switch (gdbarch_byte_order (gdbarch
))
3761 case BFD_ENDIAN_LITTLE
:
3762 mips_xfer_register (gdbarch
, regcache
,
3763 gdbarch_num_regs (gdbarch
)
3764 + mips_regnum (gdbarch
)->fp0
+
3765 0, 4, gdbarch_byte_order (gdbarch
),
3766 readbuf
, writebuf
, 0);
3767 mips_xfer_register (gdbarch
, regcache
,
3768 gdbarch_num_regs (gdbarch
)
3769 + mips_regnum (gdbarch
)->fp0
+ 1,
3770 4, gdbarch_byte_order (gdbarch
),
3771 readbuf
, writebuf
, 4);
3773 case BFD_ENDIAN_BIG
:
3774 mips_xfer_register (gdbarch
, regcache
,
3775 gdbarch_num_regs (gdbarch
)
3776 + mips_regnum (gdbarch
)->fp0
+ 1,
3777 4, gdbarch_byte_order (gdbarch
),
3778 readbuf
, writebuf
, 0);
3779 mips_xfer_register (gdbarch
, regcache
,
3780 gdbarch_num_regs (gdbarch
)
3781 + mips_regnum (gdbarch
)->fp0
+ 0,
3782 4, gdbarch_byte_order (gdbarch
),
3783 readbuf
, writebuf
, 4);
3786 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3788 return RETURN_VALUE_REGISTER_CONVENTION
;
3791 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3792 && TYPE_NFIELDS (type
) <= 2
3793 && TYPE_NFIELDS (type
) >= 1
3794 && ((TYPE_NFIELDS (type
) == 1
3795 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3797 || (TYPE_NFIELDS (type
) == 2
3798 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3800 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3802 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3804 /* A struct that contains one or two floats. Each value is part
3805 in the least significant part of their floating point
3807 gdb_byte reg
[MAX_REGISTER_SIZE
];
3810 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3811 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3813 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3816 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3818 mips_xfer_register (gdbarch
, regcache
,
3819 gdbarch_num_regs (gdbarch
) + regnum
,
3820 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3821 gdbarch_byte_order (gdbarch
),
3822 readbuf
, writebuf
, offset
);
3824 return RETURN_VALUE_REGISTER_CONVENTION
;
3828 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3829 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3831 /* A structure or union. Extract the left justified value,
3832 regardless of the byte order. I.e. DO NOT USE
3836 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3837 offset
< TYPE_LENGTH (type
);
3838 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3840 int xfer
= register_size (gdbarch
, regnum
);
3841 if (offset
+ xfer
> TYPE_LENGTH (type
))
3842 xfer
= TYPE_LENGTH (type
) - offset
;
3844 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3845 offset
, xfer
, regnum
);
3846 mips_xfer_register (gdbarch
, regcache
,
3847 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3848 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3850 return RETURN_VALUE_REGISTER_CONVENTION
;
3855 /* A scalar extract each part but least-significant-byte
3856 justified. o32 thinks registers are 4 byte, regardless of
3860 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3861 offset
< TYPE_LENGTH (type
);
3862 offset
+= MIPS32_REGSIZE
, regnum
++)
3864 int xfer
= MIPS32_REGSIZE
;
3865 if (offset
+ xfer
> TYPE_LENGTH (type
))
3866 xfer
= TYPE_LENGTH (type
) - offset
;
3868 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3869 offset
, xfer
, regnum
);
3870 mips_xfer_register (gdbarch
, regcache
,
3871 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3872 gdbarch_byte_order (gdbarch
),
3873 readbuf
, writebuf
, offset
);
3875 return RETURN_VALUE_REGISTER_CONVENTION
;
3879 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3883 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3884 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3886 struct value
**args
, CORE_ADDR sp
,
3887 int struct_return
, CORE_ADDR struct_addr
)
3893 int stack_offset
= 0;
3894 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3895 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3897 /* For shared libraries, "t9" needs to point at the function
3899 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3901 /* Set the return address register to point to the entry point of
3902 the program, where a breakpoint lies in wait. */
3903 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3905 /* First ensure that the stack and structure return address (if any)
3906 are properly aligned. The stack has to be at least 64-bit
3907 aligned even on 32-bit machines, because doubles must be 64-bit
3908 aligned. For n32 and n64, stack frames need to be 128-bit
3909 aligned, so we round to this widest known alignment. */
3911 sp
= align_down (sp
, 16);
3912 struct_addr
= align_down (struct_addr
, 16);
3914 /* Now make space on the stack for the args. */
3915 for (argnum
= 0; argnum
< nargs
; argnum
++)
3917 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3918 int arglen
= TYPE_LENGTH (arg_type
);
3920 /* Allocate space on the stack. */
3921 len
+= align_up (arglen
, MIPS64_REGSIZE
);
3923 sp
-= align_up (len
, 16);
3926 fprintf_unfiltered (gdb_stdlog
,
3927 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3928 paddr_nz (sp
), (long) align_up (len
, 16));
3930 /* Initialize the integer and float register pointers. */
3931 argreg
= MIPS_A0_REGNUM
;
3932 float_argreg
= mips_fpa0_regnum (gdbarch
);
3934 /* The struct_return pointer occupies the first parameter-passing reg. */
3938 fprintf_unfiltered (gdb_stdlog
,
3939 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3940 argreg
, paddr_nz (struct_addr
));
3941 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3942 stack_offset
+= MIPS64_REGSIZE
;
3945 /* Now load as many as possible of the first arguments into
3946 registers, and push the rest onto the stack. Loop thru args
3947 from first to last. */
3948 for (argnum
= 0; argnum
< nargs
; argnum
++)
3950 const gdb_byte
*val
;
3951 struct value
*arg
= args
[argnum
];
3952 struct type
*arg_type
= check_typedef (value_type (arg
));
3953 int len
= TYPE_LENGTH (arg_type
);
3954 enum type_code typecode
= TYPE_CODE (arg_type
);
3957 fprintf_unfiltered (gdb_stdlog
,
3958 "mips_o64_push_dummy_call: %d len=%d type=%d",
3959 argnum
+ 1, len
, (int) typecode
);
3961 val
= value_contents (arg
);
3963 /* Floating point arguments passed in registers have to be
3964 treated specially. On 32-bit architectures, doubles
3965 are passed in register pairs; the even register gets
3966 the low word, and the odd register gets the high word.
3967 On O32/O64, the first two floating point arguments are
3968 also copied to general registers, because MIPS16 functions
3969 don't use float registers for arguments. This duplication of
3970 arguments in general registers can't hurt non-MIPS16 functions
3971 because those registers are normally skipped. */
3973 if (fp_register_arg_p (typecode
, arg_type
)
3974 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3976 LONGEST regval
= extract_unsigned_integer (val
, len
);
3978 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3979 float_argreg
, phex (regval
, len
));
3980 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3982 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3983 argreg
, phex (regval
, len
));
3984 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3986 /* Reserve space for the FP register. */
3987 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
3991 /* Copy the argument to general registers or the stack in
3992 register-sized pieces. Large arguments are split between
3993 registers and stack. */
3994 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
3995 are treated specially: Irix cc passes them in registers
3996 where gcc sometimes puts them on the stack. For maximum
3997 compatibility, we will put them in both places. */
3998 int odd_sized_struct
= (len
> MIPS64_REGSIZE
3999 && len
% MIPS64_REGSIZE
!= 0);
4002 /* Remember if the argument was written to the stack. */
4003 int stack_used_p
= 0;
4004 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4007 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4010 /* Write this portion of the argument to the stack. */
4011 if (argreg
> MIPS_LAST_ARG_REGNUM
4012 || odd_sized_struct
)
4014 /* Should shorter than int integer values be
4015 promoted to int before being stored? */
4016 int longword_offset
= 0;
4019 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4021 if ((typecode
== TYPE_CODE_INT
4022 || typecode
== TYPE_CODE_PTR
4023 || typecode
== TYPE_CODE_FLT
)
4025 longword_offset
= MIPS64_REGSIZE
- len
;
4030 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4031 paddr_nz (stack_offset
));
4032 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4033 paddr_nz (longword_offset
));
4036 addr
= sp
+ stack_offset
+ longword_offset
;
4041 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4043 for (i
= 0; i
< partial_len
; i
++)
4045 fprintf_unfiltered (gdb_stdlog
, "%02x",
4049 write_memory (addr
, val
, partial_len
);
4052 /* Note!!! This is NOT an else clause. Odd sized
4053 structs may go thru BOTH paths. */
4054 /* Write this portion of the argument to a general
4055 purpose register. */
4056 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
4058 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4059 /* Value may need to be sign extended, because
4060 mips_isa_regsize() != mips_abi_regsize(). */
4062 /* A non-floating-point argument being passed in a
4063 general register. If a struct or union, and if
4064 the remaining length is smaller than the register
4065 size, we have to adjust the register value on
4068 It does not seem to be necessary to do the
4069 same for integral types. */
4071 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4072 && partial_len
< MIPS64_REGSIZE
4073 && (typecode
== TYPE_CODE_STRUCT
4074 || typecode
== TYPE_CODE_UNION
))
4075 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4079 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4081 phex (regval
, MIPS64_REGSIZE
));
4082 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4085 /* Prevent subsequent floating point arguments from
4086 being passed in floating point registers. */
4087 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4093 /* Compute the the offset into the stack at which we
4094 will copy the next parameter.
4096 In older ABIs, the caller reserved space for
4097 registers that contained arguments. This was loosely
4098 refered to as their "home". Consequently, space is
4099 always allocated. */
4101 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4105 fprintf_unfiltered (gdb_stdlog
, "\n");
4108 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4110 /* Return adjusted stack pointer. */
4114 static enum return_value_convention
4115 mips_o64_return_value (struct gdbarch
*gdbarch
,
4116 struct type
*type
, struct regcache
*regcache
,
4117 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4119 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4121 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4122 || TYPE_CODE (type
) == TYPE_CODE_UNION
4123 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4124 return RETURN_VALUE_STRUCT_CONVENTION
;
4125 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
4127 /* A floating-point value. It fits in the least significant
4130 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4131 mips_xfer_register (gdbarch
, regcache
,
4132 gdbarch_num_regs (gdbarch
)
4133 + mips_regnum (gdbarch
)->fp0
,
4135 gdbarch_byte_order (gdbarch
),
4136 readbuf
, writebuf
, 0);
4137 return RETURN_VALUE_REGISTER_CONVENTION
;
4141 /* A scalar extract each part but least-significant-byte
4145 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4146 offset
< TYPE_LENGTH (type
);
4147 offset
+= MIPS64_REGSIZE
, regnum
++)
4149 int xfer
= MIPS64_REGSIZE
;
4150 if (offset
+ xfer
> TYPE_LENGTH (type
))
4151 xfer
= TYPE_LENGTH (type
) - offset
;
4153 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4154 offset
, xfer
, regnum
);
4155 mips_xfer_register (gdbarch
, regcache
,
4156 gdbarch_num_regs (gdbarch
) + regnum
,
4157 xfer
, gdbarch_byte_order (gdbarch
),
4158 readbuf
, writebuf
, offset
);
4160 return RETURN_VALUE_REGISTER_CONVENTION
;
4164 /* Floating point register management.
4166 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4167 64bit operations, these early MIPS cpus treat fp register pairs
4168 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4169 registers and offer a compatibility mode that emulates the MIPS2 fp
4170 model. When operating in MIPS2 fp compat mode, later cpu's split
4171 double precision floats into two 32-bit chunks and store them in
4172 consecutive fp regs. To display 64-bit floats stored in this
4173 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4174 Throw in user-configurable endianness and you have a real mess.
4176 The way this works is:
4177 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4178 double-precision value will be split across two logical registers.
4179 The lower-numbered logical register will hold the low-order bits,
4180 regardless of the processor's endianness.
4181 - If we are on a 64-bit processor, and we are looking for a
4182 single-precision value, it will be in the low ordered bits
4183 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4184 save slot in memory.
4185 - If we are in 64-bit mode, everything is straightforward.
4187 Note that this code only deals with "live" registers at the top of the
4188 stack. We will attempt to deal with saved registers later, when
4189 the raw/cooked register interface is in place. (We need a general
4190 interface that can deal with dynamic saved register sizes -- fp
4191 regs could be 32 bits wide in one frame and 64 on the frame above
4194 static struct type
*
4195 mips_float_register_type (void)
4197 return builtin_type_ieee_single
;
4200 static struct type
*
4201 mips_double_register_type (void)
4203 return builtin_type_ieee_double
;
4206 /* Copy a 32-bit single-precision value from the current frame
4207 into rare_buffer. */
4210 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4211 gdb_byte
*rare_buffer
)
4213 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4214 int raw_size
= register_size (gdbarch
, regno
);
4215 gdb_byte
*raw_buffer
= alloca (raw_size
);
4217 if (!frame_register_read (frame
, regno
, raw_buffer
))
4218 error (_("can't read register %d (%s)"),
4219 regno
, gdbarch_register_name (gdbarch
, regno
));
4222 /* We have a 64-bit value for this register. Find the low-order
4226 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4231 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4235 memcpy (rare_buffer
, raw_buffer
, 4);
4239 /* Copy a 64-bit double-precision value from the current frame into
4240 rare_buffer. This may include getting half of it from the next
4244 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4245 gdb_byte
*rare_buffer
)
4247 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4248 int raw_size
= register_size (gdbarch
, regno
);
4250 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4252 /* We have a 64-bit value for this register, and we should use
4254 if (!frame_register_read (frame
, regno
, rare_buffer
))
4255 error (_("can't read register %d (%s)"),
4256 regno
, gdbarch_register_name (gdbarch
, regno
));
4260 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4262 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4263 internal_error (__FILE__
, __LINE__
,
4264 _("mips_read_fp_register_double: bad access to "
4265 "odd-numbered FP register"));
4267 /* mips_read_fp_register_single will find the correct 32 bits from
4269 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4271 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4272 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4276 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4277 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4283 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4285 { /* do values for FP (float) regs */
4286 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4287 gdb_byte
*raw_buffer
;
4288 double doub
, flt1
; /* doubles extracted from raw hex data */
4291 raw_buffer
= alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
));
4293 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4294 fprintf_filtered (file
, "%*s",
4295 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4298 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4300 /* 4-byte registers: Print hex and floating. Also print even
4301 numbered registers as doubles. */
4302 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4303 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4305 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4308 fprintf_filtered (file
, " flt: ");
4310 fprintf_filtered (file
, " <invalid float> ");
4312 fprintf_filtered (file
, "%-17.9g", flt1
);
4314 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4316 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4317 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4320 fprintf_filtered (file
, " dbl: ");
4322 fprintf_filtered (file
, "<invalid double>");
4324 fprintf_filtered (file
, "%-24.17g", doub
);
4329 /* Eight byte registers: print each one as hex, float and double. */
4330 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4331 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4333 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4334 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4337 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4340 fprintf_filtered (file
, " flt: ");
4342 fprintf_filtered (file
, "<invalid float>");
4344 fprintf_filtered (file
, "%-17.9g", flt1
);
4346 fprintf_filtered (file
, " dbl: ");
4348 fprintf_filtered (file
, "<invalid double>");
4350 fprintf_filtered (file
, "%-24.17g", doub
);
4355 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4358 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4359 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4362 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4364 mips_print_fp_register (file
, frame
, regnum
);
4368 /* Get the data in raw format. */
4369 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4371 fprintf_filtered (file
, "%s: [Invalid]",
4372 gdbarch_register_name (gdbarch
, regnum
));
4376 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4378 /* The problem with printing numeric register names (r26, etc.) is that
4379 the user can't use them on input. Probably the best solution is to
4380 fix it so that either the numeric or the funky (a2, etc.) names
4381 are accepted on input. */
4382 if (regnum
< MIPS_NUMREGS
)
4383 fprintf_filtered (file
, "(r%d): ", regnum
);
4385 fprintf_filtered (file
, ": ");
4387 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4389 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4393 print_scalar_formatted (raw_buffer
+ offset
,
4394 register_type (gdbarch
, regnum
), 'x', 0,
4398 /* Replacement for generic do_registers_info.
4399 Print regs in pretty columns. */
4402 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4405 fprintf_filtered (file
, " ");
4406 mips_print_fp_register (file
, frame
, regnum
);
4407 fprintf_filtered (file
, "\n");
4412 /* Print a row's worth of GP (int) registers, with name labels above */
4415 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4418 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4419 /* do values for GP (int) regs */
4420 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4421 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4425 /* For GP registers, we print a separate row of names above the vals */
4426 for (col
= 0, regnum
= start_regnum
;
4427 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4428 + gdbarch_num_pseudo_regs (gdbarch
);
4431 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4432 continue; /* unused register */
4433 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4435 break; /* end the row: reached FP register */
4436 /* Large registers are handled separately. */
4437 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4440 break; /* End the row before this register. */
4442 /* Print this register on a row by itself. */
4443 mips_print_register (file
, frame
, regnum
);
4444 fprintf_filtered (file
, "\n");
4448 fprintf_filtered (file
, " ");
4449 fprintf_filtered (file
,
4450 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4451 gdbarch_register_name (gdbarch
, regnum
));
4458 /* print the R0 to R31 names */
4459 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4460 fprintf_filtered (file
, "\n R%-4d",
4461 start_regnum
% gdbarch_num_regs (gdbarch
));
4463 fprintf_filtered (file
, "\n ");
4465 /* now print the values in hex, 4 or 8 to the row */
4466 for (col
= 0, regnum
= start_regnum
;
4467 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4468 + gdbarch_num_pseudo_regs (gdbarch
);
4471 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4472 continue; /* unused register */
4473 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4475 break; /* end row: reached FP register */
4476 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4477 break; /* End row: large register. */
4479 /* OK: get the data in raw format. */
4480 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4481 error (_("can't read register %d (%s)"),
4482 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4483 /* pad small registers */
4485 byte
< (mips_abi_regsize (gdbarch
)
4486 - register_size (gdbarch
, regnum
)); byte
++)
4487 printf_filtered (" ");
4488 /* Now print the register value in hex, endian order. */
4489 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4491 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4492 byte
< register_size (gdbarch
, regnum
); byte
++)
4493 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4495 for (byte
= register_size (gdbarch
, regnum
) - 1;
4497 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4498 fprintf_filtered (file
, " ");
4501 if (col
> 0) /* ie. if we actually printed anything... */
4502 fprintf_filtered (file
, "\n");
4507 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4510 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4511 struct frame_info
*frame
, int regnum
, int all
)
4513 if (regnum
!= -1) /* do one specified register */
4515 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4516 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4517 error (_("Not a valid register for the current processor type"));
4519 mips_print_register (file
, frame
, regnum
);
4520 fprintf_filtered (file
, "\n");
4523 /* do all (or most) registers */
4525 regnum
= gdbarch_num_regs (gdbarch
);
4526 while (regnum
< gdbarch_num_regs (gdbarch
)
4527 + gdbarch_num_pseudo_regs (gdbarch
))
4529 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4532 if (all
) /* true for "INFO ALL-REGISTERS" command */
4533 regnum
= print_fp_register_row (file
, frame
, regnum
);
4535 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4538 regnum
= print_gp_register_row (file
, frame
, regnum
);
4543 /* Is this a branch with a delay slot? */
4546 is_delayed (unsigned long insn
)
4549 for (i
= 0; i
< NUMOPCODES
; ++i
)
4550 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4551 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4553 return (i
< NUMOPCODES
4554 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4555 | INSN_COND_BRANCH_DELAY
4556 | INSN_COND_BRANCH_LIKELY
)));
4560 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4561 struct frame_info
*frame
)
4563 CORE_ADDR pc
= get_frame_pc (frame
);
4564 gdb_byte buf
[MIPS_INSN32_SIZE
];
4566 /* There is no branch delay slot on MIPS16. */
4567 if (mips_pc_is_mips16 (pc
))
4570 if (!breakpoint_here_p (pc
+ 4))
4573 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4574 /* If error reading memory, guess that it is not a delayed
4577 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4580 /* To skip prologues, I use this predicate. Returns either PC itself
4581 if the code at PC does not look like a function prologue; otherwise
4582 returns an address that (if we're lucky) follows the prologue. If
4583 LENIENT, then we must skip everything which is involved in setting
4584 up the frame (it's OK to skip more, just so long as we don't skip
4585 anything which might clobber the registers which are being saved.
4586 We must skip more in the case where part of the prologue is in the
4587 delay slot of a non-prologue instruction). */
4590 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4593 CORE_ADDR func_addr
;
4595 /* See if we can determine the end of the prologue via the symbol table.
4596 If so, then return either PC, or the PC after the prologue, whichever
4598 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4600 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4601 if (post_prologue_pc
!= 0)
4602 return max (pc
, post_prologue_pc
);
4605 /* Can't determine prologue from the symbol table, need to examine
4608 /* Find an upper limit on the function prologue using the debug
4609 information. If the debug information could not be used to provide
4610 that bound, then use an arbitrary large number as the upper bound. */
4611 limit_pc
= skip_prologue_using_sal (pc
);
4613 limit_pc
= pc
+ 100; /* Magic. */
4615 if (mips_pc_is_mips16 (pc
))
4616 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4618 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4621 /* Check whether the PC is in a function epilogue (32-bit version).
4622 This is a helper function for mips_in_function_epilogue_p. */
4624 mips32_in_function_epilogue_p (CORE_ADDR pc
)
4626 CORE_ADDR func_addr
= 0, func_end
= 0;
4628 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4630 /* The MIPS epilogue is max. 12 bytes long. */
4631 CORE_ADDR addr
= func_end
- 12;
4633 if (addr
< func_addr
+ 4)
4634 addr
= func_addr
+ 4;
4638 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4640 unsigned long high_word
;
4643 inst
= mips_fetch_instruction (pc
);
4644 high_word
= (inst
>> 16) & 0xffff;
4646 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4647 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4648 && inst
!= 0x03e00008 /* jr $ra */
4649 && inst
!= 0x00000000) /* nop */
4659 /* Check whether the PC is in a function epilogue (16-bit version).
4660 This is a helper function for mips_in_function_epilogue_p. */
4662 mips16_in_function_epilogue_p (CORE_ADDR pc
)
4664 CORE_ADDR func_addr
= 0, func_end
= 0;
4666 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4668 /* The MIPS epilogue is max. 12 bytes long. */
4669 CORE_ADDR addr
= func_end
- 12;
4671 if (addr
< func_addr
+ 4)
4672 addr
= func_addr
+ 4;
4676 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4678 unsigned short inst
;
4680 inst
= mips_fetch_instruction (pc
);
4682 if ((inst
& 0xf800) == 0xf000) /* extend */
4685 if (inst
!= 0x6300 /* addiu $sp,offset */
4686 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
4687 && inst
!= 0xe820 /* jr $ra */
4688 && inst
!= 0xe8a0 /* jrc $ra */
4689 && inst
!= 0x6500) /* nop */
4699 /* The epilogue is defined here as the area at the end of a function,
4700 after an instruction which destroys the function's stack frame. */
4702 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4704 if (mips_pc_is_mips16 (pc
))
4705 return mips16_in_function_epilogue_p (pc
);
4707 return mips32_in_function_epilogue_p (pc
);
4710 /* Root of all "set mips "/"show mips " commands. This will eventually be
4711 used for all MIPS-specific commands. */
4714 show_mips_command (char *args
, int from_tty
)
4716 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4720 set_mips_command (char *args
, int from_tty
)
4723 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4724 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4727 /* Commands to show/set the MIPS FPU type. */
4730 show_mipsfpu_command (char *args
, int from_tty
)
4734 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
4737 ("The MIPS floating-point coprocessor is unknown "
4738 "because the current architecture is not MIPS.\n");
4742 switch (MIPS_FPU_TYPE
)
4744 case MIPS_FPU_SINGLE
:
4745 fpu
= "single-precision";
4747 case MIPS_FPU_DOUBLE
:
4748 fpu
= "double-precision";
4751 fpu
= "absent (none)";
4754 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4756 if (mips_fpu_type_auto
)
4758 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4762 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4767 set_mipsfpu_command (char *args
, int from_tty
)
4770 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4771 show_mipsfpu_command (args
, from_tty
);
4775 set_mipsfpu_single_command (char *args
, int from_tty
)
4777 struct gdbarch_info info
;
4778 gdbarch_info_init (&info
);
4779 mips_fpu_type
= MIPS_FPU_SINGLE
;
4780 mips_fpu_type_auto
= 0;
4781 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4782 instead of relying on globals. Doing that would let generic code
4783 handle the search for this specific architecture. */
4784 if (!gdbarch_update_p (info
))
4785 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4789 set_mipsfpu_double_command (char *args
, int from_tty
)
4791 struct gdbarch_info info
;
4792 gdbarch_info_init (&info
);
4793 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4794 mips_fpu_type_auto
= 0;
4795 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4796 instead of relying on globals. Doing that would let generic code
4797 handle the search for this specific architecture. */
4798 if (!gdbarch_update_p (info
))
4799 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4803 set_mipsfpu_none_command (char *args
, int from_tty
)
4805 struct gdbarch_info info
;
4806 gdbarch_info_init (&info
);
4807 mips_fpu_type
= MIPS_FPU_NONE
;
4808 mips_fpu_type_auto
= 0;
4809 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4810 instead of relying on globals. Doing that would let generic code
4811 handle the search for this specific architecture. */
4812 if (!gdbarch_update_p (info
))
4813 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4817 set_mipsfpu_auto_command (char *args
, int from_tty
)
4819 mips_fpu_type_auto
= 1;
4822 /* Attempt to identify the particular processor model by reading the
4823 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4824 the relevant processor still exists (it dates back to '94) and
4825 secondly this is not the way to do this. The processor type should
4826 be set by forcing an architecture change. */
4829 deprecated_mips_set_processor_regs_hack (void)
4831 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4834 regcache_cooked_read_unsigned (get_current_regcache (),
4835 MIPS_PRID_REGNUM
, &prid
);
4836 if ((prid
& ~0xf) == 0x700)
4837 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4840 /* Just like reinit_frame_cache, but with the right arguments to be
4841 callable as an sfunc. */
4844 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4845 struct cmd_list_element
*c
)
4847 reinit_frame_cache ();
4851 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4853 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4855 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4856 disassembler needs to be able to locally determine the ISA, and
4857 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4859 if (mips_pc_is_mips16 (memaddr
))
4860 info
->mach
= bfd_mach_mips16
;
4862 /* Round down the instruction address to the appropriate boundary. */
4863 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4865 /* Set the disassembler options. */
4866 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4868 /* Set up the disassembler info, so that we get the right
4869 register names from libopcodes. */
4870 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4871 info
->disassembler_options
= "gpr-names=n32";
4873 info
->disassembler_options
= "gpr-names=64";
4874 info
->flavour
= bfd_target_elf_flavour
;
4877 /* This string is not recognized explicitly by the disassembler,
4878 but it tells the disassembler to not try to guess the ABI from
4879 the bfd elf headers, such that, if the user overrides the ABI
4880 of a program linked as NewABI, the disassembly will follow the
4881 register naming conventions specified by the user. */
4882 info
->disassembler_options
= "gpr-names=32";
4884 /* Call the appropriate disassembler based on the target endian-ness. */
4885 if (info
->endian
== BFD_ENDIAN_BIG
)
4886 return print_insn_big_mips (memaddr
, info
);
4888 return print_insn_little_mips (memaddr
, info
);
4891 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4892 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4893 It returns a pointer to a string of bytes that encode a breakpoint
4894 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4895 necessary) to point to the actual memory location where the breakpoint
4896 should be inserted. */
4898 static const gdb_byte
*
4899 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
4901 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4903 if (mips_pc_is_mips16 (*pcptr
))
4905 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4906 *pcptr
= unmake_mips16_addr (*pcptr
);
4907 *lenptr
= sizeof (mips16_big_breakpoint
);
4908 return mips16_big_breakpoint
;
4912 /* The IDT board uses an unusual breakpoint value, and
4913 sometimes gets confused when it sees the usual MIPS
4914 breakpoint instruction. */
4915 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4916 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4917 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4919 *lenptr
= sizeof (big_breakpoint
);
4921 if (strcmp (target_shortname
, "mips") == 0)
4922 return idt_big_breakpoint
;
4923 else if (strcmp (target_shortname
, "ddb") == 0
4924 || strcmp (target_shortname
, "pmon") == 0
4925 || strcmp (target_shortname
, "lsi") == 0)
4926 return pmon_big_breakpoint
;
4928 return big_breakpoint
;
4933 if (mips_pc_is_mips16 (*pcptr
))
4935 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4936 *pcptr
= unmake_mips16_addr (*pcptr
);
4937 *lenptr
= sizeof (mips16_little_breakpoint
);
4938 return mips16_little_breakpoint
;
4942 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4943 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4944 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4946 *lenptr
= sizeof (little_breakpoint
);
4948 if (strcmp (target_shortname
, "mips") == 0)
4949 return idt_little_breakpoint
;
4950 else if (strcmp (target_shortname
, "ddb") == 0
4951 || strcmp (target_shortname
, "pmon") == 0
4952 || strcmp (target_shortname
, "lsi") == 0)
4953 return pmon_little_breakpoint
;
4955 return little_breakpoint
;
4960 /* If PC is in a mips16 call or return stub, return the address of the target
4961 PC, which is either the callee or the caller. There are several
4962 cases which must be handled:
4964 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4965 target PC is in $31 ($ra).
4966 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4967 and the target PC is in $2.
4968 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4969 before the jal instruction, this is effectively a call stub
4970 and the the target PC is in $2. Otherwise this is effectively
4971 a return stub and the target PC is in $18.
4973 See the source code for the stubs in gcc/config/mips/mips16.S for
4977 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
4980 CORE_ADDR start_addr
;
4982 /* Find the starting address and name of the function containing the PC. */
4983 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4986 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4987 target PC is in $31 ($ra). */
4988 if (strcmp (name
, "__mips16_ret_sf") == 0
4989 || strcmp (name
, "__mips16_ret_df") == 0)
4990 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
4992 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4994 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4995 and the target PC is in $2. */
4996 if (name
[19] >= '0' && name
[19] <= '9')
4997 return get_frame_register_signed (frame
, 2);
4999 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5000 before the jal instruction, this is effectively a call stub
5001 and the the target PC is in $2. Otherwise this is effectively
5002 a return stub and the target PC is in $18. */
5003 else if (name
[19] == 's' || name
[19] == 'd')
5005 if (pc
== start_addr
)
5007 /* Check if the target of the stub is a compiler-generated
5008 stub. Such a stub for a function bar might have a name
5009 like __fn_stub_bar, and might look like this:
5014 la $1,bar (becomes a lui/addiu pair)
5016 So scan down to the lui/addi and extract the target
5017 address from those two instructions. */
5019 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5023 /* See if the name of the target function is __fn_stub_*. */
5024 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5027 if (strncmp (name
, "__fn_stub_", 10) != 0
5028 && strcmp (name
, "etext") != 0
5029 && strcmp (name
, "_etext") != 0)
5032 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5033 The limit on the search is arbitrarily set to 20
5034 instructions. FIXME. */
5035 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5037 inst
= mips_fetch_instruction (target_pc
);
5038 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5039 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5040 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5041 return pc
| (inst
& 0xffff); /* low word */
5044 /* Couldn't find the lui/addui pair, so return stub address. */
5048 /* This is the 'return' part of a call stub. The return
5049 address is in $r18. */
5050 return get_frame_register_signed (frame
, 18);
5053 return 0; /* not a stub */
5056 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5057 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5060 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5063 if (num
>= 0 && num
< 32)
5065 else if (num
>= 38 && num
< 70)
5066 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5068 regnum
= mips_regnum (gdbarch
)->hi
;
5070 regnum
= mips_regnum (gdbarch
)->lo
;
5072 /* This will hopefully (eventually) provoke a warning. Should
5073 we be calling complaint() here? */
5074 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5075 return gdbarch_num_regs (gdbarch
) + regnum
;
5079 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5080 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5083 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5086 if (num
>= 0 && num
< 32)
5088 else if (num
>= 32 && num
< 64)
5089 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5091 regnum
= mips_regnum (gdbarch
)->hi
;
5093 regnum
= mips_regnum (gdbarch
)->lo
;
5095 /* This will hopefully (eventually) provoke a warning. Should we
5096 be calling complaint() here? */
5097 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5098 return gdbarch_num_regs (gdbarch
) + regnum
;
5102 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5104 /* Only makes sense to supply raw registers. */
5105 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5106 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5107 decide if it is valid. Should instead define a standard sim/gdb
5108 register numbering scheme. */
5109 if (gdbarch_register_name (gdbarch
,
5110 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5111 && gdbarch_register_name (gdbarch
,
5112 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
5115 return LEGACY_SIM_REGNO_IGNORE
;
5119 /* Convert an integer into an address. Extracting the value signed
5120 guarantees a correctly sign extended address. */
5123 mips_integer_to_address (struct gdbarch
*gdbarch
,
5124 struct type
*type
, const gdb_byte
*buf
)
5126 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
5129 /* Dummy virtual frame pointer method. This is no more or less accurate
5130 than most other architectures; we just need to be explicit about it,
5131 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5132 an assertion failure. */
5135 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5136 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5138 *reg
= MIPS_SP_REGNUM
;
5143 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5145 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5146 const char *name
= bfd_get_section_name (abfd
, sect
);
5148 if (*abip
!= MIPS_ABI_UNKNOWN
)
5151 if (strncmp (name
, ".mdebug.", 8) != 0)
5154 if (strcmp (name
, ".mdebug.abi32") == 0)
5155 *abip
= MIPS_ABI_O32
;
5156 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5157 *abip
= MIPS_ABI_N32
;
5158 else if (strcmp (name
, ".mdebug.abi64") == 0)
5159 *abip
= MIPS_ABI_N64
;
5160 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5161 *abip
= MIPS_ABI_O64
;
5162 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5163 *abip
= MIPS_ABI_EABI32
;
5164 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5165 *abip
= MIPS_ABI_EABI64
;
5167 warning (_("unsupported ABI %s."), name
+ 8);
5171 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5173 int *lbp
= (int *) obj
;
5174 const char *name
= bfd_get_section_name (abfd
, sect
);
5176 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5178 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5180 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5181 warning (_("unrecognized .gcc_compiled_longXX"));
5184 static enum mips_abi
5185 global_mips_abi (void)
5189 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5190 if (mips_abi_strings
[i
] == mips_abi_string
)
5191 return (enum mips_abi
) i
;
5193 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5197 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5199 /* If the size matches the set of 32-bit or 64-bit integer registers,
5200 assume that's what we've got. */
5201 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5202 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5204 /* If the size matches the full set of registers GDB traditionally
5205 knows about, including floating point, for either 32-bit or
5206 64-bit, assume that's what we've got. */
5207 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5208 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5210 /* Otherwise we don't have a useful guess. */
5213 static struct value
*
5214 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5216 const int *reg_p
= baton
;
5217 return value_of_register (*reg_p
, frame
);
5220 static struct gdbarch
*
5221 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5223 struct gdbarch
*gdbarch
;
5224 struct gdbarch_tdep
*tdep
;
5226 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5228 enum mips_fpu_type fpu_type
;
5229 struct tdesc_arch_data
*tdesc_data
= NULL
;
5230 int elf_fpu_type
= 0;
5232 /* Check any target description for validity. */
5233 if (tdesc_has_registers (info
.target_desc
))
5235 static const char *const mips_gprs
[] = {
5236 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5237 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5238 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5239 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5241 static const char *const mips_fprs
[] = {
5242 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5243 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5244 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5245 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5248 const struct tdesc_feature
*feature
;
5251 feature
= tdesc_find_feature (info
.target_desc
,
5252 "org.gnu.gdb.mips.cpu");
5253 if (feature
== NULL
)
5256 tdesc_data
= tdesc_data_alloc ();
5259 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5260 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5264 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5265 MIPS_EMBED_LO_REGNUM
, "lo");
5266 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5267 MIPS_EMBED_HI_REGNUM
, "hi");
5268 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5269 MIPS_EMBED_PC_REGNUM
, "pc");
5273 tdesc_data_cleanup (tdesc_data
);
5277 feature
= tdesc_find_feature (info
.target_desc
,
5278 "org.gnu.gdb.mips.cp0");
5279 if (feature
== NULL
)
5281 tdesc_data_cleanup (tdesc_data
);
5286 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5287 MIPS_EMBED_BADVADDR_REGNUM
,
5289 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5290 MIPS_PS_REGNUM
, "status");
5291 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5292 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5296 tdesc_data_cleanup (tdesc_data
);
5300 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5301 backend is not prepared for that, though. */
5302 feature
= tdesc_find_feature (info
.target_desc
,
5303 "org.gnu.gdb.mips.fpu");
5304 if (feature
== NULL
)
5306 tdesc_data_cleanup (tdesc_data
);
5311 for (i
= 0; i
< 32; i
++)
5312 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5313 i
+ MIPS_EMBED_FP0_REGNUM
,
5316 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5317 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5318 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5319 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5323 tdesc_data_cleanup (tdesc_data
);
5327 /* It would be nice to detect an attempt to use a 64-bit ABI
5328 when only 32-bit registers are provided. */
5331 /* First of all, extract the elf_flags, if available. */
5332 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5333 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5334 else if (arches
!= NULL
)
5335 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5339 fprintf_unfiltered (gdb_stdlog
,
5340 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5342 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5343 switch ((elf_flags
& EF_MIPS_ABI
))
5345 case E_MIPS_ABI_O32
:
5346 found_abi
= MIPS_ABI_O32
;
5348 case E_MIPS_ABI_O64
:
5349 found_abi
= MIPS_ABI_O64
;
5351 case E_MIPS_ABI_EABI32
:
5352 found_abi
= MIPS_ABI_EABI32
;
5354 case E_MIPS_ABI_EABI64
:
5355 found_abi
= MIPS_ABI_EABI64
;
5358 if ((elf_flags
& EF_MIPS_ABI2
))
5359 found_abi
= MIPS_ABI_N32
;
5361 found_abi
= MIPS_ABI_UNKNOWN
;
5365 /* GCC creates a pseudo-section whose name describes the ABI. */
5366 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5367 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5369 /* If we have no useful BFD information, use the ABI from the last
5370 MIPS architecture (if there is one). */
5371 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5372 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5374 /* Try the architecture for any hint of the correct ABI. */
5375 if (found_abi
== MIPS_ABI_UNKNOWN
5376 && info
.bfd_arch_info
!= NULL
5377 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5379 switch (info
.bfd_arch_info
->mach
)
5381 case bfd_mach_mips3900
:
5382 found_abi
= MIPS_ABI_EABI32
;
5384 case bfd_mach_mips4100
:
5385 case bfd_mach_mips5000
:
5386 found_abi
= MIPS_ABI_EABI64
;
5388 case bfd_mach_mips8000
:
5389 case bfd_mach_mips10000
:
5390 /* On Irix, ELF64 executables use the N64 ABI. The
5391 pseudo-sections which describe the ABI aren't present
5392 on IRIX. (Even for executables created by gcc.) */
5393 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5394 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5395 found_abi
= MIPS_ABI_N64
;
5397 found_abi
= MIPS_ABI_N32
;
5402 /* Default 64-bit objects to N64 instead of O32. */
5403 if (found_abi
== MIPS_ABI_UNKNOWN
5404 && info
.abfd
!= NULL
5405 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5406 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5407 found_abi
= MIPS_ABI_N64
;
5410 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5413 /* What has the user specified from the command line? */
5414 wanted_abi
= global_mips_abi ();
5416 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5419 /* Now that we have found what the ABI for this binary would be,
5420 check whether the user is overriding it. */
5421 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5422 mips_abi
= wanted_abi
;
5423 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5424 mips_abi
= found_abi
;
5426 mips_abi
= MIPS_ABI_O32
;
5428 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5431 /* Also used when doing an architecture lookup. */
5433 fprintf_unfiltered (gdb_stdlog
,
5434 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5435 mips64_transfers_32bit_regs_p
);
5437 /* Determine the MIPS FPU type. */
5440 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5441 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5442 Tag_GNU_MIPS_ABI_FP
);
5443 #endif /* HAVE_ELF */
5445 if (!mips_fpu_type_auto
)
5446 fpu_type
= mips_fpu_type
;
5447 else if (elf_fpu_type
!= 0)
5449 switch (elf_fpu_type
)
5452 fpu_type
= MIPS_FPU_DOUBLE
;
5455 fpu_type
= MIPS_FPU_SINGLE
;
5459 /* Soft float or unknown. */
5460 fpu_type
= MIPS_FPU_NONE
;
5464 else if (info
.bfd_arch_info
!= NULL
5465 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5466 switch (info
.bfd_arch_info
->mach
)
5468 case bfd_mach_mips3900
:
5469 case bfd_mach_mips4100
:
5470 case bfd_mach_mips4111
:
5471 case bfd_mach_mips4120
:
5472 fpu_type
= MIPS_FPU_NONE
;
5474 case bfd_mach_mips4650
:
5475 fpu_type
= MIPS_FPU_SINGLE
;
5478 fpu_type
= MIPS_FPU_DOUBLE
;
5481 else if (arches
!= NULL
)
5482 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5484 fpu_type
= MIPS_FPU_DOUBLE
;
5486 fprintf_unfiltered (gdb_stdlog
,
5487 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5489 /* Check for blatant incompatibilities. */
5491 /* If we have only 32-bit registers, then we can't debug a 64-bit
5493 if (info
.target_desc
5494 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5495 && mips_abi
!= MIPS_ABI_EABI32
5496 && mips_abi
!= MIPS_ABI_O32
)
5498 if (tdesc_data
!= NULL
)
5499 tdesc_data_cleanup (tdesc_data
);
5503 /* try to find a pre-existing architecture */
5504 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5506 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5508 /* MIPS needs to be pedantic about which ABI the object is
5510 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5512 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5514 /* Need to be pedantic about which register virtual size is
5516 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5517 != mips64_transfers_32bit_regs_p
)
5519 /* Be pedantic about which FPU is selected. */
5520 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5523 if (tdesc_data
!= NULL
)
5524 tdesc_data_cleanup (tdesc_data
);
5525 return arches
->gdbarch
;
5528 /* Need a new architecture. Fill in a target specific vector. */
5529 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5530 gdbarch
= gdbarch_alloc (&info
, tdep
);
5531 tdep
->elf_flags
= elf_flags
;
5532 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5533 tdep
->found_abi
= found_abi
;
5534 tdep
->mips_abi
= mips_abi
;
5535 tdep
->mips_fpu_type
= fpu_type
;
5536 tdep
->register_size_valid_p
= 0;
5537 tdep
->register_size
= 0;
5539 if (info
.target_desc
)
5541 /* Some useful properties can be inferred from the target. */
5542 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5544 tdep
->register_size_valid_p
= 1;
5545 tdep
->register_size
= 4;
5547 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5549 tdep
->register_size_valid_p
= 1;
5550 tdep
->register_size
= 8;
5554 /* Initially set everything according to the default ABI/ISA. */
5555 set_gdbarch_short_bit (gdbarch
, 16);
5556 set_gdbarch_int_bit (gdbarch
, 32);
5557 set_gdbarch_float_bit (gdbarch
, 32);
5558 set_gdbarch_double_bit (gdbarch
, 64);
5559 set_gdbarch_long_double_bit (gdbarch
, 64);
5560 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5561 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5562 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5564 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5565 mips_elf_make_msymbol_special
);
5567 /* Fill in the OS dependant register numbers and names. */
5569 const char **reg_names
;
5570 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5571 struct mips_regnum
);
5572 if (tdesc_has_registers (info
.target_desc
))
5574 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5575 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5576 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5577 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5578 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5579 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5580 regnum
->fp_control_status
= 70;
5581 regnum
->fp_implementation_revision
= 71;
5582 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5585 else if (info
.osabi
== GDB_OSABI_IRIX
)
5590 regnum
->badvaddr
= 66;
5593 regnum
->fp_control_status
= 69;
5594 regnum
->fp_implementation_revision
= 70;
5596 reg_names
= mips_irix_reg_names
;
5600 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5601 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5602 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5603 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5604 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5605 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5606 regnum
->fp_control_status
= 70;
5607 regnum
->fp_implementation_revision
= 71;
5609 if (info
.bfd_arch_info
!= NULL
5610 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5611 reg_names
= mips_tx39_reg_names
;
5613 reg_names
= mips_generic_reg_names
;
5615 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5616 replaced by read_pc? */
5617 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5618 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5619 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5620 set_gdbarch_num_regs (gdbarch
, num_regs
);
5621 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5622 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5623 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
5624 tdep
->mips_processor_reg_names
= reg_names
;
5625 tdep
->regnum
= regnum
;
5631 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5632 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5633 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5634 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5635 tdep
->default_mask_address_p
= 0;
5636 set_gdbarch_long_bit (gdbarch
, 32);
5637 set_gdbarch_ptr_bit (gdbarch
, 32);
5638 set_gdbarch_long_long_bit (gdbarch
, 64);
5641 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5642 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5643 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5644 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5645 tdep
->default_mask_address_p
= 0;
5646 set_gdbarch_long_bit (gdbarch
, 32);
5647 set_gdbarch_ptr_bit (gdbarch
, 32);
5648 set_gdbarch_long_long_bit (gdbarch
, 64);
5650 case MIPS_ABI_EABI32
:
5651 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5652 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5653 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5654 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5655 tdep
->default_mask_address_p
= 0;
5656 set_gdbarch_long_bit (gdbarch
, 32);
5657 set_gdbarch_ptr_bit (gdbarch
, 32);
5658 set_gdbarch_long_long_bit (gdbarch
, 64);
5660 case MIPS_ABI_EABI64
:
5661 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5662 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5663 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5664 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5665 tdep
->default_mask_address_p
= 0;
5666 set_gdbarch_long_bit (gdbarch
, 64);
5667 set_gdbarch_ptr_bit (gdbarch
, 64);
5668 set_gdbarch_long_long_bit (gdbarch
, 64);
5671 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5672 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5673 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5674 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5675 tdep
->default_mask_address_p
= 0;
5676 set_gdbarch_long_bit (gdbarch
, 32);
5677 set_gdbarch_ptr_bit (gdbarch
, 32);
5678 set_gdbarch_long_long_bit (gdbarch
, 64);
5679 set_gdbarch_long_double_bit (gdbarch
, 128);
5680 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5683 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5684 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5685 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5686 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5687 tdep
->default_mask_address_p
= 0;
5688 set_gdbarch_long_bit (gdbarch
, 64);
5689 set_gdbarch_ptr_bit (gdbarch
, 64);
5690 set_gdbarch_long_long_bit (gdbarch
, 64);
5691 set_gdbarch_long_double_bit (gdbarch
, 128);
5692 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5695 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5698 /* GCC creates a pseudo-section whose name specifies the size of
5699 longs, since -mlong32 or -mlong64 may be used independent of
5700 other options. How those options affect pointer sizes is ABI and
5701 architecture dependent, so use them to override the default sizes
5702 set by the ABI. This table shows the relationship between ABI,
5703 -mlongXX, and size of pointers:
5705 ABI -mlongXX ptr bits
5706 --- -------- --------
5720 Note that for o32 and eabi32, pointers are always 32 bits
5721 regardless of any -mlongXX option. For all others, pointers and
5722 longs are the same, as set by -mlongXX or set by defaults.
5725 if (info
.abfd
!= NULL
)
5729 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5732 set_gdbarch_long_bit (gdbarch
, long_bit
);
5736 case MIPS_ABI_EABI32
:
5741 case MIPS_ABI_EABI64
:
5742 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5745 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5750 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5751 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5754 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5755 flag in object files because to do so would make it impossible to
5756 link with libraries compiled without "-gp32". This is
5757 unnecessarily restrictive.
5759 We could solve this problem by adding "-gp32" multilibs to gcc,
5760 but to set this flag before gcc is built with such multilibs will
5761 break too many systems.''
5763 But even more unhelpfully, the default linker output target for
5764 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5765 for 64-bit programs - you need to change the ABI to change this,
5766 and not all gcc targets support that currently. Therefore using
5767 this flag to detect 32-bit mode would do the wrong thing given
5768 the current gcc - it would make GDB treat these 64-bit programs
5769 as 32-bit programs by default. */
5771 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5772 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5774 /* Add/remove bits from an address. The MIPS needs be careful to
5775 ensure that all 32 bit addresses are sign extended to 64 bits. */
5776 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5778 /* Unwind the frame. */
5779 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5780 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5781 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5783 /* Map debug register numbers onto internal register numbers. */
5784 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5785 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5786 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5787 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5788 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5789 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5790 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5791 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5793 /* MIPS version of CALL_DUMMY */
5795 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5796 replaced by a command, and all targets will default to on stack
5797 (regardless of the stack's execute status). */
5798 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5799 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5801 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5802 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5803 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5805 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5806 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5808 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5810 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
5812 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5813 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5814 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5816 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5818 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5820 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5822 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5823 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5824 need to all be folded into the target vector. Since they are
5825 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5826 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5828 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5830 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5832 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5834 /* Virtual tables. */
5835 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5837 mips_register_g_packet_guesses (gdbarch
);
5839 /* Hook in OS ABI-specific overrides, if they have been registered. */
5840 info
.tdep_info
= (void *) tdesc_data
;
5841 gdbarch_init_osabi (info
, gdbarch
);
5843 /* Unwind the frame. */
5844 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
5845 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5846 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5847 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5848 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
5849 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5850 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5851 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5855 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
5856 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
5858 /* Override the normal target description methods to handle our
5859 dual real and pseudo registers. */
5860 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5861 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
5863 num_regs
= gdbarch_num_regs (gdbarch
);
5864 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5865 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
5866 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5869 /* Add ABI-specific aliases for the registers. */
5870 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
5871 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
5872 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
5873 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
5875 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
5876 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
5877 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
5879 /* Add some other standard aliases. */
5880 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
5881 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
5882 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
5888 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5890 struct gdbarch_info info
;
5892 /* Force the architecture to update, and (if it's a MIPS architecture)
5893 mips_gdbarch_init will take care of the rest. */
5894 gdbarch_info_init (&info
);
5895 gdbarch_update_p (info
);
5898 /* Print out which MIPS ABI is in use. */
5901 show_mips_abi (struct ui_file
*file
,
5903 struct cmd_list_element
*ignored_cmd
,
5904 const char *ignored_value
)
5906 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5909 "The MIPS ABI is unknown because the current architecture "
5913 enum mips_abi global_abi
= global_mips_abi ();
5914 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5915 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5917 if (global_abi
== MIPS_ABI_UNKNOWN
)
5920 "The MIPS ABI is set automatically (currently \"%s\").\n",
5922 else if (global_abi
== actual_abi
)
5925 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5929 /* Probably shouldn't happen... */
5932 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5933 actual_abi_str
, mips_abi_strings
[global_abi
]);
5939 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
5941 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5945 int ef_mips_32bitmode
;
5946 /* Determine the ISA. */
5947 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5965 /* Determine the size of a pointer. */
5966 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5967 fprintf_unfiltered (file
,
5968 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5970 fprintf_unfiltered (file
,
5971 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5973 fprintf_unfiltered (file
,
5974 "mips_dump_tdep: ef_mips_arch = %d\n",
5976 fprintf_unfiltered (file
,
5977 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5978 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5979 fprintf_unfiltered (file
,
5980 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5981 mips_mask_address_p (tdep
),
5982 tdep
->default_mask_address_p
);
5984 fprintf_unfiltered (file
,
5985 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5986 MIPS_DEFAULT_FPU_TYPE
,
5987 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5988 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5989 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5991 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5992 fprintf_unfiltered (file
,
5993 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5995 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5996 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5997 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6001 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6004 _initialize_mips_tdep (void)
6006 static struct cmd_list_element
*mipsfpulist
= NULL
;
6007 struct cmd_list_element
*c
;
6009 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6010 if (MIPS_ABI_LAST
+ 1
6011 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6012 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6014 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6016 mips_pdr_data
= register_objfile_data ();
6018 /* Create feature sets with the appropriate properties. The values
6019 are not important. */
6020 mips_tdesc_gp32
= allocate_target_description ();
6021 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6023 mips_tdesc_gp64
= allocate_target_description ();
6024 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6026 /* Add root prefix command for all "set mips"/"show mips" commands */
6027 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6028 _("Various MIPS specific commands."),
6029 &setmipscmdlist
, "set mips ", 0, &setlist
);
6031 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6032 _("Various MIPS specific commands."),
6033 &showmipscmdlist
, "show mips ", 0, &showlist
);
6035 /* Allow the user to override the ABI. */
6036 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6037 &mips_abi_string
, _("\
6038 Set the MIPS ABI used by this program."), _("\
6039 Show the MIPS ABI used by this program."), _("\
6040 This option can be set to one of:\n\
6041 auto - the default ABI associated with the current binary\n\
6050 &setmipscmdlist
, &showmipscmdlist
);
6052 /* Let the user turn off floating point and set the fence post for
6053 heuristic_proc_start. */
6055 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6056 _("Set use of MIPS floating-point coprocessor."),
6057 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6058 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6059 _("Select single-precision MIPS floating-point coprocessor."),
6061 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6062 _("Select double-precision MIPS floating-point coprocessor."),
6064 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6065 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6066 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6067 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6068 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6069 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6070 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6071 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6072 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6073 _("Select MIPS floating-point coprocessor automatically."),
6075 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6076 _("Show current use of MIPS floating-point coprocessor target."),
6079 /* We really would like to have both "0" and "unlimited" work, but
6080 command.c doesn't deal with that. So make it a var_zinteger
6081 because the user can always use "999999" or some such for unlimited. */
6082 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6083 &heuristic_fence_post
, _("\
6084 Set the distance searched for the start of a function."), _("\
6085 Show the distance searched for the start of a function."), _("\
6086 If you are debugging a stripped executable, GDB needs to search through the\n\
6087 program for the start of a function. This command sets the distance of the\n\
6088 search. The only need to set it is when debugging a stripped executable."),
6089 reinit_frame_cache_sfunc
,
6090 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
6091 &setlist
, &showlist
);
6093 /* Allow the user to control whether the upper bits of 64-bit
6094 addresses should be zeroed. */
6095 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6096 &mask_address_var
, _("\
6097 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6098 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6099 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6100 allow GDB to determine the correct value."),
6101 NULL
, show_mask_address
,
6102 &setmipscmdlist
, &showmipscmdlist
);
6104 /* Allow the user to control the size of 32 bit registers within the
6105 raw remote packet. */
6106 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6107 &mips64_transfers_32bit_regs_p
, _("\
6108 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6110 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6112 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6113 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6114 64 bits for others. Use \"off\" to disable compatibility mode"),
6115 set_mips64_transfers_32bit_regs
,
6116 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6117 &setlist
, &showlist
);
6119 /* Debug this files internals. */
6120 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6122 Set mips debugging."), _("\
6123 Show mips debugging."), _("\
6124 When non-zero, mips specific debugging is enabled."),
6126 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
6127 &setdebuglist
, &showdebuglist
);