1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
54 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
55 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
57 /* A useful bit in the CP0 status register (PS_REGNUM). */
58 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
59 #define ST0_FR (1 << 26)
61 /* The sizes of floating point registers. */
65 MIPS_FPU_SINGLE_REGSIZE
= 4,
66 MIPS_FPU_DOUBLE_REGSIZE
= 8
70 static const char *mips_abi_string
;
72 static const char *mips_abi_strings
[] = {
83 struct frame_extra_info
85 mips_extra_func_info_t proc_desc
;
89 /* Various MIPS ISA options (related to stack analysis) can be
90 overridden dynamically. Establish an enum/array for managing
93 static const char size_auto
[] = "auto";
94 static const char size_32
[] = "32";
95 static const char size_64
[] = "64";
97 static const char *size_enums
[] = {
104 /* Some MIPS boards don't support floating point while others only
105 support single-precision floating-point operations. See also
106 FP_REGISTER_DOUBLE. */
110 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
111 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
112 MIPS_FPU_NONE
/* No floating point. */
115 #ifndef MIPS_DEFAULT_FPU_TYPE
116 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
118 static int mips_fpu_type_auto
= 1;
119 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
121 static int mips_debug
= 0;
123 /* MIPS specific per-architecture information */
126 /* from the elf header */
130 enum mips_abi mips_abi
;
131 enum mips_abi found_abi
;
132 enum mips_fpu_type mips_fpu_type
;
133 int mips_last_arg_regnum
;
134 int mips_last_fp_arg_regnum
;
135 int mips_default_saved_regsize
;
136 int mips_fp_register_double
;
137 int mips_default_stack_argsize
;
138 int default_mask_address_p
;
139 /* Is the target using 64-bit raw integer registers but only
140 storing a left-aligned 32-bit value in each? */
141 int mips64_transfers_32bit_regs_p
;
142 /* Indexes for various registers. IRIX and embedded have
143 different values. This contains the "public" fields. Don't
144 add any that do not need to be public. */
145 const struct mips_regnum
*regnum
;
146 /* Register names table for the current register set. */
147 const char **mips_processor_reg_names
;
150 const struct mips_regnum
*
151 mips_regnum (struct gdbarch
*gdbarch
)
153 return gdbarch_tdep (gdbarch
)->regnum
;
157 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
159 return mips_regnum (gdbarch
)->fp0
+ 12;
162 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
163 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
165 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
167 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
169 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
171 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
172 functions to test, set, or clear bit 0 of addresses. */
175 is_mips16_addr (CORE_ADDR addr
)
181 make_mips16_addr (CORE_ADDR addr
)
187 unmake_mips16_addr (CORE_ADDR addr
)
189 return ((addr
) & ~1);
192 /* Return the contents of register REGNUM as a signed integer. */
195 read_signed_register (int regnum
)
197 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
198 deprecated_read_register_gen (regnum
, buf
);
199 return (extract_signed_integer
200 (buf
, register_size (current_gdbarch
, regnum
)));
204 read_signed_register_pid (int regnum
, ptid_t ptid
)
209 if (ptid_equal (ptid
, inferior_ptid
))
210 return read_signed_register (regnum
);
212 save_ptid
= inferior_ptid
;
214 inferior_ptid
= ptid
;
216 retval
= read_signed_register (regnum
);
218 inferior_ptid
= save_ptid
;
223 /* Return the MIPS ABI associated with GDBARCH. */
225 mips_abi (struct gdbarch
*gdbarch
)
227 return gdbarch_tdep (gdbarch
)->mips_abi
;
231 mips_regsize (struct gdbarch
*gdbarch
)
233 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
234 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
237 /* Return the currently configured (or set) saved register size. */
239 static const char *mips_saved_regsize_string
= size_auto
;
242 mips_saved_regsize (struct gdbarch_tdep
*tdep
)
244 if (mips_saved_regsize_string
== size_auto
)
245 return tdep
->mips_default_saved_regsize
;
246 else if (mips_saved_regsize_string
== size_64
)
248 else /* if (mips_saved_regsize_string == size_32) */
252 /* Functions for setting and testing a bit in a minimal symbol that
253 marks it as 16-bit function. The MSB of the minimal symbol's
254 "info" field is used for this purpose.
256 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
257 i.e. refers to a 16-bit function, and sets a "special" bit in a
258 minimal symbol to mark it as a 16-bit function
260 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
263 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
265 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
267 MSYMBOL_INFO (msym
) = (char *)
268 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
269 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
274 msymbol_is_special (struct minimal_symbol
*msym
)
276 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
279 /* XFER a value from the big/little/left end of the register.
280 Depending on the size of the value it might occupy the entire
281 register or just part of it. Make an allowance for this, aligning
282 things accordingly. */
285 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
286 enum bfd_endian endian
, bfd_byte
* in
,
287 const bfd_byte
* out
, int buf_offset
)
289 bfd_byte reg
[MAX_REGISTER_SIZE
];
291 gdb_assert (reg_num
>= NUM_REGS
);
292 /* Need to transfer the left or right part of the register, based on
293 the targets byte order. */
297 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
299 case BFD_ENDIAN_LITTLE
:
302 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
306 internal_error (__FILE__
, __LINE__
, "bad switch");
309 fprintf_unfiltered (gdb_stderr
,
310 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
311 reg_num
, reg_offset
, buf_offset
, length
);
312 if (mips_debug
&& out
!= NULL
)
315 fprintf_unfiltered (gdb_stdlog
, "out ");
316 for (i
= 0; i
< length
; i
++)
317 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
320 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
323 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
325 if (mips_debug
&& in
!= NULL
)
328 fprintf_unfiltered (gdb_stdlog
, "in ");
329 for (i
= 0; i
< length
; i
++)
330 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
333 fprintf_unfiltered (gdb_stdlog
, "\n");
336 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
337 compatiblity mode. A return value of 1 means that we have
338 physical 64-bit registers, but should treat them as 32-bit registers. */
341 mips2_fp_compat (void)
343 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
345 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
350 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
351 in all the places we deal with FP registers. PR gdb/413. */
352 /* Otherwise check the FR bit in the status register - it controls
353 the FP compatiblity mode. If it is clear we are in compatibility
355 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
362 /* Indicate that the ABI makes use of double-precision registers
363 provided by the FPU (rather than combining pairs of registers to
364 form double-precision values). See also MIPS_FPU_TYPE. */
365 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
367 /* The amount of space reserved on the stack for registers. This is
368 different to MIPS_SAVED_REGSIZE as it determines the alignment of
369 data allocated after the registers have run out. */
371 static const char *mips_stack_argsize_string
= size_auto
;
374 mips_stack_argsize (struct gdbarch_tdep
*tdep
)
376 if (mips_stack_argsize_string
== size_auto
)
377 return tdep
->mips_default_stack_argsize
;
378 else if (mips_stack_argsize_string
== size_64
)
380 else /* if (mips_stack_argsize_string == size_32) */
384 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
386 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
387 struct frame_info
*, int);
389 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
391 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
393 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
395 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
396 struct frame_info
*next_frame
,
399 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
400 mips_extra_func_info_t proc_desc
);
402 static struct type
*mips_float_register_type (void);
403 static struct type
*mips_double_register_type (void);
405 /* The list of available "set mips " and "show mips " commands */
407 static struct cmd_list_element
*setmipscmdlist
= NULL
;
408 static struct cmd_list_element
*showmipscmdlist
= NULL
;
410 /* Integer registers 0 thru 31 are handled explicitly by
411 mips_register_name(). Processor specific registers 32 and above
412 are listed in the followign tables. */
415 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
419 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
420 "sr", "lo", "hi", "bad", "cause", "pc",
421 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
422 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
423 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
424 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
425 "fsr", "fir", "" /*"fp" */ , "",
426 "", "", "", "", "", "", "", "",
427 "", "", "", "", "", "", "", "",
430 /* Names of IDT R3041 registers. */
432 static const char *mips_r3041_reg_names
[] = {
433 "sr", "lo", "hi", "bad", "cause", "pc",
434 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
435 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
436 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
437 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
438 "fsr", "fir", "", /*"fp" */ "",
439 "", "", "bus", "ccfg", "", "", "", "",
440 "", "", "port", "cmp", "", "", "epc", "prid",
443 /* Names of tx39 registers. */
445 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
446 "sr", "lo", "hi", "bad", "cause", "pc",
447 "", "", "", "", "", "", "", "",
448 "", "", "", "", "", "", "", "",
449 "", "", "", "", "", "", "", "",
450 "", "", "", "", "", "", "", "",
452 "", "", "", "", "", "", "", "",
453 "", "", "config", "cache", "debug", "depc", "epc", ""
456 /* Names of IRIX registers. */
457 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
458 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
459 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
460 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
461 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
462 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
466 /* Return the name of the register corresponding to REGNO. */
468 mips_register_name (int regno
)
470 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
471 /* GPR names for all ABIs other than n32/n64. */
472 static char *mips_gpr_names
[] = {
473 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
474 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
475 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
476 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
479 /* GPR names for n32 and n64 ABIs. */
480 static char *mips_n32_n64_gpr_names
[] = {
481 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
482 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
483 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
484 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
487 enum mips_abi abi
= mips_abi (current_gdbarch
);
489 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
490 don't make the raw register names visible. */
491 int rawnum
= regno
% NUM_REGS
;
492 if (regno
< NUM_REGS
)
495 /* The MIPS integer registers are always mapped from 0 to 31. The
496 names of the registers (which reflects the conventions regarding
497 register use) vary depending on the ABI. */
498 if (0 <= rawnum
&& rawnum
< 32)
500 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
501 return mips_n32_n64_gpr_names
[rawnum
];
503 return mips_gpr_names
[rawnum
];
505 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
507 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
508 return tdep
->mips_processor_reg_names
[rawnum
- 32];
511 internal_error (__FILE__
, __LINE__
,
512 "mips_register_name: bad register number %d", rawnum
);
515 /* Return the groups that a MIPS register can be categorised into. */
518 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
519 struct reggroup
*reggroup
)
524 int rawnum
= regnum
% NUM_REGS
;
525 int pseudo
= regnum
/ NUM_REGS
;
526 if (reggroup
== all_reggroup
)
528 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
529 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
530 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
531 (gdbarch), as not all architectures are multi-arch. */
532 raw_p
= rawnum
< NUM_REGS
;
533 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
535 if (reggroup
== float_reggroup
)
536 return float_p
&& pseudo
;
537 if (reggroup
== vector_reggroup
)
538 return vector_p
&& pseudo
;
539 if (reggroup
== general_reggroup
)
540 return (!vector_p
&& !float_p
) && pseudo
;
541 /* Save the pseudo registers. Need to make certain that any code
542 extracting register values from a saved register cache also uses
544 if (reggroup
== save_reggroup
)
545 return raw_p
&& pseudo
;
546 /* Restore the same pseudo register. */
547 if (reggroup
== restore_reggroup
)
548 return raw_p
&& pseudo
;
552 /* Map the symbol table registers which live in the range [1 *
553 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
554 registers. Take care of alignment and size problems. */
557 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
558 int cookednum
, void *buf
)
560 int rawnum
= cookednum
% NUM_REGS
;
561 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
562 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
563 regcache_raw_read (regcache
, rawnum
, buf
);
564 else if (register_size (gdbarch
, rawnum
) >
565 register_size (gdbarch
, cookednum
))
567 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
568 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
569 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
571 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
574 internal_error (__FILE__
, __LINE__
, "bad register size");
578 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
579 struct regcache
*regcache
, int cookednum
,
582 int rawnum
= cookednum
% NUM_REGS
;
583 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
584 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
585 regcache_raw_write (regcache
, rawnum
, buf
);
586 else if (register_size (gdbarch
, rawnum
) >
587 register_size (gdbarch
, cookednum
))
589 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
590 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
591 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
593 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
596 internal_error (__FILE__
, __LINE__
, "bad register size");
599 /* Table to translate MIPS16 register field to actual register number. */
600 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
602 /* Heuristic_proc_start may hunt through the text section for a long
603 time across a 2400 baud serial line. Allows the user to limit this
606 static unsigned int heuristic_fence_post
= 0;
608 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
609 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
610 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
611 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
612 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
613 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
614 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
615 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
616 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
617 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
618 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
619 this will corrupt pdr.iline. Fortunately we don't use it. */
620 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
621 #define _PROC_MAGIC_ 0x0F0F0F0F
622 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
623 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
625 struct linked_proc_info
627 struct mips_extra_func_info info
;
628 struct linked_proc_info
*next
;
630 *linked_proc_desc_table
= NULL
;
632 /* Number of bytes of storage in the actual machine representation for
633 register N. NOTE: This defines the pseudo register type so need to
634 rebuild the architecture vector. */
636 static int mips64_transfers_32bit_regs_p
= 0;
639 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
640 struct cmd_list_element
*c
)
642 struct gdbarch_info info
;
643 gdbarch_info_init (&info
);
644 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
645 instead of relying on globals. Doing that would let generic code
646 handle the search for this specific architecture. */
647 if (!gdbarch_update_p (info
))
649 mips64_transfers_32bit_regs_p
= 0;
650 error ("32-bit compatibility mode not supported");
654 /* Convert to/from a register and the corresponding memory value. */
657 mips_convert_register_p (int regnum
, struct type
*type
)
659 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
660 && register_size (current_gdbarch
, regnum
) == 4
661 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
662 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
663 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
667 mips_register_to_value (struct frame_info
*frame
, int regnum
,
668 struct type
*type
, void *to
)
670 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
671 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
675 mips_value_to_register (struct frame_info
*frame
, int regnum
,
676 struct type
*type
, const void *from
)
678 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
679 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
682 /* Return the GDB type object for the "standard" data type of data in
686 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
688 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
689 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
690 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
692 /* The floating-point registers raw, or cooked, always match
693 mips_regsize(), and also map 1:1, byte for byte. */
694 switch (gdbarch_byte_order (gdbarch
))
697 if (mips_regsize (gdbarch
) == 4)
698 return builtin_type_ieee_single_big
;
700 return builtin_type_ieee_double_big
;
701 case BFD_ENDIAN_LITTLE
:
702 if (mips_regsize (gdbarch
) == 4)
703 return builtin_type_ieee_single_little
;
705 return builtin_type_ieee_double_little
;
706 case BFD_ENDIAN_UNKNOWN
:
708 internal_error (__FILE__
, __LINE__
, "bad switch");
712 (NUM_REGS
+ mips_regnum (current_gdbarch
)->fp_control_status
)
713 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
714 /* The pseudo/cooked view of the embedded registers is always
715 32-bit. The raw view is handled below. */
716 return builtin_type_int32
;
717 else if (regnum
>= NUM_REGS
&& mips_regsize (gdbarch
)
718 && gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
719 /* The target, while using a 64-bit register buffer, is only
720 transfering 32-bits of each integer register. Reflect this in
721 the cooked/pseudo register value. */
722 return builtin_type_int32
;
723 else if (mips_regsize (gdbarch
) == 8)
725 return builtin_type_int64
;
728 return builtin_type_int32
;
731 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
736 return read_signed_register (SP_REGNUM
);
739 /* Should the upper word of 64-bit addresses be zeroed? */
740 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
743 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
745 switch (mask_address_var
)
747 case AUTO_BOOLEAN_TRUE
:
749 case AUTO_BOOLEAN_FALSE
:
752 case AUTO_BOOLEAN_AUTO
:
753 return tdep
->default_mask_address_p
;
755 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
761 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
763 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
764 switch (mask_address_var
)
766 case AUTO_BOOLEAN_TRUE
:
767 printf_filtered ("The 32 bit mips address mask is enabled\n");
769 case AUTO_BOOLEAN_FALSE
:
770 printf_filtered ("The 32 bit mips address mask is disabled\n");
772 case AUTO_BOOLEAN_AUTO
:
774 ("The 32 bit address mask is set automatically. Currently %s\n",
775 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
778 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
783 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
786 pc_is_mips16 (bfd_vma memaddr
)
788 struct minimal_symbol
*sym
;
790 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
791 if (is_mips16_addr (memaddr
))
794 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
795 the high bit of the info field. Use this to decide if the function is
796 MIPS16 or normal MIPS. */
797 sym
= lookup_minimal_symbol_by_pc (memaddr
);
799 return msymbol_is_special (sym
);
804 /* MIPS believes that the PC has a sign extended value. Perhaphs the
805 all registers should be sign extended for simplicity? */
808 mips_read_pc (ptid_t ptid
)
810 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
814 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
816 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
819 /* This returns the PC of the first inst after the prologue. If we can't
820 find the prologue, then return 0. */
823 after_prologue (CORE_ADDR pc
, mips_extra_func_info_t proc_desc
)
825 struct symtab_and_line sal
;
826 CORE_ADDR func_addr
, func_end
;
828 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
829 to read the stack pointer from the current machine state, because
830 the current machine state has nothing to do with the information
831 we need from the proc_desc; and the process may or may not exist
834 proc_desc
= find_proc_desc (pc
, NULL
, 0);
838 /* If function is frameless, then we need to do it the hard way. I
839 strongly suspect that frameless always means prologueless... */
840 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
841 && PROC_FRAME_OFFSET (proc_desc
) == 0)
845 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
846 return 0; /* Unknown */
848 sal
= find_pc_line (func_addr
, 0);
850 if (sal
.end
< func_end
)
853 /* The line after the prologue is after the end of the function. In this
854 case, tell the caller to find the prologue the hard way. */
859 /* Decode a MIPS32 instruction that saves a register in the stack, and
860 set the appropriate bit in the general register mask or float register mask
861 to indicate which register is saved. This is a helper function
862 for mips_find_saved_regs. */
865 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
866 unsigned long *float_mask
)
870 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
871 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
872 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
874 /* It might be possible to use the instruction to
875 find the offset, rather than the code below which
876 is based on things being in a certain order in the
877 frame, but figuring out what the instruction's offset
878 is relative to might be a little tricky. */
879 reg
= (inst
& 0x001f0000) >> 16;
880 *gen_mask
|= (1 << reg
);
882 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
883 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
884 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
887 reg
= ((inst
& 0x001f0000) >> 16);
888 *float_mask
|= (1 << reg
);
892 /* Decode a MIPS16 instruction that saves a register in the stack, and
893 set the appropriate bit in the general register or float register mask
894 to indicate which register is saved. This is a helper function
895 for mips_find_saved_regs. */
898 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
900 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
902 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
903 *gen_mask
|= (1 << reg
);
905 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
907 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
908 *gen_mask
|= (1 << reg
);
910 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
911 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
912 *gen_mask
|= (1 << RA_REGNUM
);
916 /* Fetch and return instruction from the specified location. If the PC
917 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
920 mips_fetch_instruction (CORE_ADDR addr
)
922 char buf
[MIPS_INSTLEN
];
926 if (pc_is_mips16 (addr
))
928 instlen
= MIPS16_INSTLEN
;
929 addr
= unmake_mips16_addr (addr
);
932 instlen
= MIPS_INSTLEN
;
933 status
= read_memory_nobpt (addr
, buf
, instlen
);
935 memory_error (status
, addr
);
936 return extract_unsigned_integer (buf
, instlen
);
940 /* These the fields of 32 bit mips instructions */
941 #define mips32_op(x) (x >> 26)
942 #define itype_op(x) (x >> 26)
943 #define itype_rs(x) ((x >> 21) & 0x1f)
944 #define itype_rt(x) ((x >> 16) & 0x1f)
945 #define itype_immediate(x) (x & 0xffff)
947 #define jtype_op(x) (x >> 26)
948 #define jtype_target(x) (x & 0x03ffffff)
950 #define rtype_op(x) (x >> 26)
951 #define rtype_rs(x) ((x >> 21) & 0x1f)
952 #define rtype_rt(x) ((x >> 16) & 0x1f)
953 #define rtype_rd(x) ((x >> 11) & 0x1f)
954 #define rtype_shamt(x) ((x >> 6) & 0x1f)
955 #define rtype_funct(x) (x & 0x3f)
958 mips32_relative_offset (unsigned long inst
)
961 x
= itype_immediate (inst
);
962 if (x
& 0x8000) /* sign bit set */
964 x
|= 0xffff0000; /* sign extension */
970 /* Determine whate to set a single step breakpoint while considering
973 mips32_next_pc (CORE_ADDR pc
)
977 inst
= mips_fetch_instruction (pc
);
978 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
980 if (itype_op (inst
) >> 2 == 5)
981 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
983 op
= (itype_op (inst
) & 0x03);
998 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
999 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1001 int tf
= itype_rt (inst
) & 0x01;
1002 int cnum
= itype_rt (inst
) >> 2;
1004 read_signed_register (mips_regnum (current_gdbarch
)->
1006 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1008 if (((cond
>> cnum
) & 0x01) == tf
)
1009 pc
+= mips32_relative_offset (inst
) + 4;
1014 pc
+= 4; /* Not a branch, next instruction is easy */
1017 { /* This gets way messy */
1019 /* Further subdivide into SPECIAL, REGIMM and other */
1020 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1022 case 0: /* SPECIAL */
1023 op
= rtype_funct (inst
);
1028 /* Set PC to that address */
1029 pc
= read_signed_register (rtype_rs (inst
));
1035 break; /* end SPECIAL */
1036 case 1: /* REGIMM */
1038 op
= itype_rt (inst
); /* branch condition */
1043 case 16: /* BLTZAL */
1044 case 18: /* BLTZALL */
1046 if (read_signed_register (itype_rs (inst
)) < 0)
1047 pc
+= mips32_relative_offset (inst
) + 4;
1049 pc
+= 8; /* after the delay slot */
1053 case 17: /* BGEZAL */
1054 case 19: /* BGEZALL */
1055 if (read_signed_register (itype_rs (inst
)) >= 0)
1056 pc
+= mips32_relative_offset (inst
) + 4;
1058 pc
+= 8; /* after the delay slot */
1060 /* All of the other instructions in the REGIMM category */
1065 break; /* end REGIMM */
1070 reg
= jtype_target (inst
) << 2;
1071 /* Upper four bits get never changed... */
1072 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1075 /* FIXME case JALX : */
1078 reg
= jtype_target (inst
) << 2;
1079 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1080 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1082 break; /* The new PC will be alternate mode */
1083 case 4: /* BEQ, BEQL */
1085 if (read_signed_register (itype_rs (inst
)) ==
1086 read_signed_register (itype_rt (inst
)))
1087 pc
+= mips32_relative_offset (inst
) + 4;
1091 case 5: /* BNE, BNEL */
1093 if (read_signed_register (itype_rs (inst
)) !=
1094 read_signed_register (itype_rt (inst
)))
1095 pc
+= mips32_relative_offset (inst
) + 4;
1099 case 6: /* BLEZ, BLEZL */
1100 if (read_signed_register (itype_rs (inst
) <= 0))
1101 pc
+= mips32_relative_offset (inst
) + 4;
1107 greater_branch
: /* BGTZ, BGTZL */
1108 if (read_signed_register (itype_rs (inst
) > 0))
1109 pc
+= mips32_relative_offset (inst
) + 4;
1116 } /* mips32_next_pc */
1118 /* Decoding the next place to set a breakpoint is irregular for the
1119 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1120 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1121 We dont want to set a single step instruction on the extend instruction
1125 /* Lots of mips16 instruction formats */
1126 /* Predicting jumps requires itype,ritype,i8type
1127 and their extensions extItype,extritype,extI8type
1129 enum mips16_inst_fmts
1131 itype
, /* 0 immediate 5,10 */
1132 ritype
, /* 1 5,3,8 */
1133 rrtype
, /* 2 5,3,3,5 */
1134 rritype
, /* 3 5,3,3,5 */
1135 rrrtype
, /* 4 5,3,3,3,2 */
1136 rriatype
, /* 5 5,3,3,1,4 */
1137 shifttype
, /* 6 5,3,3,3,2 */
1138 i8type
, /* 7 5,3,8 */
1139 i8movtype
, /* 8 5,3,3,5 */
1140 i8mov32rtype
, /* 9 5,3,5,3 */
1141 i64type
, /* 10 5,3,8 */
1142 ri64type
, /* 11 5,3,3,5 */
1143 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1144 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1145 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1146 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1147 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1148 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1149 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1150 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1151 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1152 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1154 /* I am heaping all the fields of the formats into one structure and
1155 then, only the fields which are involved in instruction extension */
1159 unsigned int regx
; /* Function in i8 type */
1164 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1165 for the bits which make up the immediatate extension. */
1168 extended_offset (unsigned int extension
)
1171 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1173 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1175 value
|= extension
& 0x01f; /* extract 4:0 */
1179 /* Only call this function if you know that this is an extendable
1180 instruction, It wont malfunction, but why make excess remote memory references?
1181 If the immediate operands get sign extended or somthing, do it after
1182 the extension is performed.
1184 /* FIXME: Every one of these cases needs to worry about sign extension
1185 when the offset is to be used in relative addressing */
1189 fetch_mips_16 (CORE_ADDR pc
)
1192 pc
&= 0xfffffffe; /* clear the low order bit */
1193 target_read_memory (pc
, buf
, 2);
1194 return extract_unsigned_integer (buf
, 2);
1198 unpack_mips16 (CORE_ADDR pc
,
1199 unsigned int extension
,
1201 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1206 switch (insn_format
)
1213 value
= extended_offset (extension
);
1214 value
= value
<< 11; /* rom for the original value */
1215 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1219 value
= inst
& 0x7ff;
1220 /* FIXME : Consider sign extension */
1229 { /* A register identifier and an offset */
1230 /* Most of the fields are the same as I type but the
1231 immediate value is of a different length */
1235 value
= extended_offset (extension
);
1236 value
= value
<< 8; /* from the original instruction */
1237 value
|= inst
& 0xff; /* eleven bits from instruction */
1238 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1239 if (value
& 0x4000) /* test the sign bit , bit 26 */
1241 value
&= ~0x3fff; /* remove the sign bit */
1247 value
= inst
& 0xff; /* 8 bits */
1248 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1249 /* FIXME: Do sign extension , this format needs it */
1250 if (value
& 0x80) /* THIS CONFUSES ME */
1252 value
&= 0xef; /* remove the sign bit */
1262 unsigned long value
;
1263 unsigned int nexthalf
;
1264 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1265 value
= value
<< 16;
1266 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1274 internal_error (__FILE__
, __LINE__
, "bad switch");
1276 upk
->offset
= offset
;
1283 add_offset_16 (CORE_ADDR pc
, int offset
)
1285 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1289 extended_mips16_next_pc (CORE_ADDR pc
,
1290 unsigned int extension
, unsigned int insn
)
1292 int op
= (insn
>> 11);
1295 case 2: /* Branch */
1298 struct upk_mips16 upk
;
1299 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1300 offset
= upk
.offset
;
1306 pc
+= (offset
<< 1) + 2;
1309 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1311 struct upk_mips16 upk
;
1312 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1313 pc
= add_offset_16 (pc
, upk
.offset
);
1314 if ((insn
>> 10) & 0x01) /* Exchange mode */
1315 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1322 struct upk_mips16 upk
;
1324 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1325 reg
= read_signed_register (upk
.regx
);
1327 pc
+= (upk
.offset
<< 1) + 2;
1334 struct upk_mips16 upk
;
1336 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1337 reg
= read_signed_register (upk
.regx
);
1339 pc
+= (upk
.offset
<< 1) + 2;
1344 case 12: /* I8 Formats btez btnez */
1346 struct upk_mips16 upk
;
1348 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1349 /* upk.regx contains the opcode */
1350 reg
= read_signed_register (24); /* Test register is 24 */
1351 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1352 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1353 /* pc = add_offset_16(pc,upk.offset) ; */
1354 pc
+= (upk
.offset
<< 1) + 2;
1359 case 29: /* RR Formats JR, JALR, JALR-RA */
1361 struct upk_mips16 upk
;
1362 /* upk.fmt = rrtype; */
1367 upk
.regx
= (insn
>> 8) & 0x07;
1368 upk
.regy
= (insn
>> 5) & 0x07;
1376 break; /* Function return instruction */
1382 break; /* BOGUS Guess */
1384 pc
= read_signed_register (reg
);
1391 /* This is an instruction extension. Fetch the real instruction
1392 (which follows the extension) and decode things based on
1396 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1409 mips16_next_pc (CORE_ADDR pc
)
1411 unsigned int insn
= fetch_mips_16 (pc
);
1412 return extended_mips16_next_pc (pc
, 0, insn
);
1415 /* The mips_next_pc function supports single_step when the remote
1416 target monitor or stub is not developed enough to do a single_step.
1417 It works by decoding the current instruction and predicting where a
1418 branch will go. This isnt hard because all the data is available.
1419 The MIPS32 and MIPS16 variants are quite different */
1421 mips_next_pc (CORE_ADDR pc
)
1424 return mips16_next_pc (pc
);
1426 return mips32_next_pc (pc
);
1429 /* Set up the 'saved_regs' array. This is a data structure containing
1430 the addresses on the stack where each register has been saved, for
1431 each stack frame. Registers that have not been saved will have
1432 zero here. The stack pointer register is special: rather than the
1433 address where the stack register has been saved,
1434 saved_regs[SP_REGNUM] will have the actual value of the previous
1435 frame's stack register. */
1438 mips_find_saved_regs (struct frame_info
*fci
)
1441 /* r0 bit means kernel trap */
1443 /* What registers have been saved? Bitmasks. */
1444 unsigned long gen_mask
, float_mask
;
1445 mips_extra_func_info_t proc_desc
;
1447 CORE_ADDR
*saved_regs
;
1448 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1450 if (deprecated_get_frame_saved_regs (fci
) != NULL
)
1452 saved_regs
= frame_saved_regs_zalloc (fci
);
1454 /* If it is the frame for sigtramp, the saved registers are located
1455 in a sigcontext structure somewhere on the stack. If the stack
1456 layout for sigtramp changes we might have to change these
1457 constants and the companion fixup_sigtramp in mdebugread.c */
1458 #ifndef SIGFRAME_BASE
1459 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1460 above the sigtramp frame. */
1461 #define SIGFRAME_BASE mips_regsize (current_gdbarch)
1462 /* FIXME! Are these correct?? */
1463 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch))
1464 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch))
1465 #define SIGFRAME_FPREGSAVE_OFF \
1466 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch))
1468 if ((get_frame_type (fci
) == SIGTRAMP_FRAME
))
1470 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1472 CORE_ADDR reg_position
=
1473 (get_frame_base (fci
) + SIGFRAME_REGSAVE_OFF
+
1474 ireg
* mips_regsize (current_gdbarch
));
1475 set_reg_offset (saved_regs
, ireg
, reg_position
);
1477 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1479 CORE_ADDR reg_position
= (get_frame_base (fci
)
1480 + SIGFRAME_FPREGSAVE_OFF
1481 + ireg
* mips_regsize (current_gdbarch
));
1482 set_reg_offset (saved_regs
,
1483 mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1487 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->pc
,
1488 get_frame_base (fci
) + SIGFRAME_PC_OFF
);
1489 /* SP_REGNUM, contains the value and not the address. */
1490 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1494 proc_desc
= get_frame_extra_info (fci
)->proc_desc
;
1495 if (proc_desc
== NULL
)
1496 /* I'm not sure how/whether this can happen. Normally when we
1497 can't find a proc_desc, we "synthesize" one using
1498 heuristic_proc_desc and set the saved_regs right away. */
1501 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1502 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1503 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1505 if ( /* In any frame other than the innermost or a frame interrupted
1506 by a signal, we assume that all registers have been saved.
1507 This assumes that all register saves in a function happen
1508 before the first function call. */
1509 (get_next_frame (fci
) == NULL
1510 || (get_frame_type (get_next_frame (fci
)) == SIGTRAMP_FRAME
))
1511 /* In a dummy frame we know exactly where things are saved. */
1512 && !PROC_DESC_IS_DUMMY (proc_desc
)
1513 /* Don't bother unless we are inside a function prologue.
1514 Outside the prologue, we know where everything is. */
1515 && in_prologue (get_frame_pc (fci
), PROC_LOW_ADDR (proc_desc
))
1516 /* Not sure exactly what kernel_trap means, but if it means the
1517 kernel saves the registers without a prologue doing it, we
1518 better not examine the prologue to see whether registers
1519 have been saved yet. */
1522 /* We need to figure out whether the registers that the
1523 proc_desc claims are saved have been saved yet. */
1527 /* Bitmasks; set if we have found a save for the register. */
1528 unsigned long gen_save_found
= 0;
1529 unsigned long float_save_found
= 0;
1532 /* If the address is odd, assume this is MIPS16 code. */
1533 addr
= PROC_LOW_ADDR (proc_desc
);
1534 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1536 /* Scan through this function's instructions preceding the
1537 current PC, and look for those that save registers. */
1538 while (addr
< get_frame_pc (fci
))
1540 inst
= mips_fetch_instruction (addr
);
1541 if (pc_is_mips16 (addr
))
1542 mips16_decode_reg_save (inst
, &gen_save_found
);
1544 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1547 gen_mask
= gen_save_found
;
1548 float_mask
= float_save_found
;
1551 /* Fill in the offsets for the registers which gen_mask says were
1554 CORE_ADDR reg_position
= (get_frame_base (fci
)
1555 + PROC_REG_OFFSET (proc_desc
));
1556 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1557 if (gen_mask
& 0x80000000)
1559 set_reg_offset (saved_regs
, ireg
, reg_position
);
1560 reg_position
-= mips_saved_regsize (tdep
);
1564 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1565 order of that normally used by gcc. Therefore, we have to fetch
1566 the first instruction of the function, and if it's an entry
1567 instruction that saves $s0 or $s1, correct their saved addresses. */
1568 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1570 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1571 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1575 int sreg_count
= (inst
>> 6) & 3;
1577 /* Check if the ra register was pushed on the stack. */
1578 CORE_ADDR reg_position
= (get_frame_base (fci
)
1579 + PROC_REG_OFFSET (proc_desc
));
1581 reg_position
-= mips_saved_regsize (tdep
);
1583 /* Check if the s0 and s1 registers were pushed on the
1585 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1587 set_reg_offset (saved_regs
, reg
, reg_position
);
1588 reg_position
-= mips_saved_regsize (tdep
);
1593 /* Fill in the offsets for the registers which float_mask says were
1596 CORE_ADDR reg_position
= (get_frame_base (fci
)
1597 + PROC_FREG_OFFSET (proc_desc
));
1599 /* Fill in the offsets for the float registers which float_mask
1601 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1602 if (float_mask
& 0x80000000)
1604 if (mips_saved_regsize (tdep
) == 4
1605 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1607 /* On a big endian 32 bit ABI, floating point registers
1608 are paired to form doubles such that the most
1609 significant part is in $f[N+1] and the least
1610 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1611 registers are also spilled as a pair and stored as a
1614 When little-endian the least significant part is
1615 stored first leading to the memory order $f[N] and
1618 Unfortunately, when big-endian the most significant
1619 part of the double is stored first, and the least
1620 significant is stored second. This leads to the
1621 registers being ordered in memory as firt $f[N+1] and
1624 For the big-endian case make certain that the
1625 addresses point at the correct (swapped) locations
1626 $f[N] and $f[N+1] pair (keep in mind that
1627 reg_position is decremented each time through the
1630 set_reg_offset (saved_regs
,
1631 mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1632 reg_position
- mips_saved_regsize (tdep
));
1634 set_reg_offset (saved_regs
,
1635 mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1636 reg_position
+ mips_saved_regsize (tdep
));
1639 set_reg_offset (saved_regs
,
1640 mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1642 reg_position
-= mips_saved_regsize (tdep
);
1645 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->pc
,
1646 saved_regs
[RA_REGNUM
]);
1649 /* SP_REGNUM, contains the value and not the address. */
1650 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1654 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1656 /* Always a pseudo. */
1657 gdb_assert (regno
>= NUM_REGS
);
1661 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1664 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1665 /* The SP_REGNUM is special, its value is stored in saved_regs.
1666 In fact, it is so special that it can even only be fetched
1667 using a raw register number! Once this code as been converted
1668 to frame-unwind the problem goes away. */
1669 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1671 return frame_unwind_register_signed (fi
, regno
);
1675 /* mips_addr_bits_remove - remove useless address bits */
1678 mips_addr_bits_remove (CORE_ADDR addr
)
1680 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1681 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
1682 /* This hack is a work-around for existing boards using PMON, the
1683 simulator, and any other 64-bit targets that doesn't have true
1684 64-bit addressing. On these targets, the upper 32 bits of
1685 addresses are ignored by the hardware. Thus, the PC or SP are
1686 likely to have been sign extended to all 1s by instruction
1687 sequences that load 32-bit addresses. For example, a typical
1688 piece of code that loads an address is this:
1690 lui $r2, <upper 16 bits>
1691 ori $r2, <lower 16 bits>
1693 But the lui sign-extends the value such that the upper 32 bits
1694 may be all 1s. The workaround is simply to mask off these
1695 bits. In the future, gcc may be changed to support true 64-bit
1696 addressing, and this masking will have to be disabled. */
1697 return addr
&= 0xffffffffUL
;
1702 /* mips_software_single_step() is called just before we want to resume
1703 the inferior, if we want to single-step it but there is no hardware
1704 or kernel single-step support (MIPS on GNU/Linux for example). We find
1705 the target of the coming instruction and breakpoint it.
1707 single_step is also called just after the inferior stops. If we had
1708 set up a simulated single-step, we undo our damage. */
1711 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1713 static CORE_ADDR next_pc
;
1714 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1715 static binsn_quantum break_mem
;
1718 if (insert_breakpoints_p
)
1720 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
1721 next_pc
= mips_next_pc (pc
);
1723 target_insert_breakpoint (next_pc
, break_mem
);
1726 target_remove_breakpoint (next_pc
, break_mem
);
1730 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1735 ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev
))
1736 : get_next_frame (prev
)
1737 ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev
)) : read_pc ());
1738 tmp
= SKIP_TRAMPOLINE_CODE (pc
);
1739 return tmp
? tmp
: pc
;
1744 mips_frame_saved_pc (struct frame_info
*frame
)
1747 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1749 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
1751 /* Always unwind the cooked PC register value. */
1752 saved_pc
= frame_unwind_register_signed (frame
, NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
);
1756 mips_extra_func_info_t proc_desc
1757 = get_frame_extra_info (frame
)->proc_desc
;
1758 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1759 saved_pc
= read_memory_integer ((get_frame_base (frame
)
1760 - mips_saved_regsize (tdep
)),
1761 mips_saved_regsize (tdep
));
1764 /* We have to get the saved pc from the sigcontext if it is
1765 a signal handler frame. */
1766 int pcreg
= (get_frame_type (frame
) == SIGTRAMP_FRAME
1767 ? mips_regnum (current_gdbarch
)->pc
1768 : proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1769 saved_pc
= read_next_frame_reg (frame
, NUM_REGS
+ pcreg
);
1772 return ADDR_BITS_REMOVE (saved_pc
);
1775 static struct mips_extra_func_info temp_proc_desc
;
1777 /* This hack will go away once the get_prev_frame() code has been
1778 modified to set the frame's type first. That is BEFORE init extra
1779 frame info et.al. is called. This is because it will become
1780 possible to skip the init extra info call for sigtramp and dummy
1782 static CORE_ADDR
*temp_saved_regs
;
1784 /* Set a register's saved stack address in temp_saved_regs. If an
1785 address has already been set for this register, do nothing; this
1786 way we will only recognize the first save of a given register in a
1789 For simplicity, save the address in both [0 .. NUM_REGS) and
1790 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1791 is used as it is only second range (the ABI instead of ISA
1792 registers) that comes into play when finding saved registers in a
1796 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
1798 if (saved_regs
[regno
] == 0)
1800 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
1801 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
1806 /* Test whether the PC points to the return instruction at the
1807 end of a function. */
1810 mips_about_to_return (CORE_ADDR pc
)
1812 if (pc_is_mips16 (pc
))
1813 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1814 generates a "jr $ra"; other times it generates code to load
1815 the return address from the stack to an accessible register (such
1816 as $a3), then a "jr" using that register. This second case
1817 is almost impossible to distinguish from an indirect jump
1818 used for switch statements, so we don't even try. */
1819 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1821 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1825 /* This fencepost looks highly suspicious to me. Removing it also
1826 seems suspicious as it could affect remote debugging across serial
1830 heuristic_proc_start (CORE_ADDR pc
)
1837 pc
= ADDR_BITS_REMOVE (pc
);
1839 fence
= start_pc
- heuristic_fence_post
;
1843 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
1844 fence
= VM_MIN_ADDRESS
;
1846 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1848 /* search back for previous return */
1849 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1850 if (start_pc
< fence
)
1852 /* It's not clear to me why we reach this point when
1853 stop_soon, but with this test, at least we
1854 don't print out warnings for every child forked (eg, on
1855 decstation). 22apr93 rich@cygnus.com. */
1856 if (stop_soon
== NO_STOP_QUIETLY
)
1858 static int blurb_printed
= 0;
1861 ("Warning: GDB can't find the start of the function at 0x%s.",
1866 /* This actually happens frequently in embedded
1867 development, when you first connect to a board
1868 and your stack pointer and pc are nowhere in
1869 particular. This message needs to give people
1870 in that situation enough information to
1871 determine that it's no big deal. */
1872 printf_filtered ("\n\
1873 GDB is unable to find the start of the function at 0x%s\n\
1874 and thus can't determine the size of that function's stack frame.\n\
1875 This means that GDB may be unable to access that stack frame, or\n\
1876 the frames below it.\n\
1877 This problem is most likely caused by an invalid program counter or\n\
1879 However, if you think GDB should simply search farther back\n\
1880 from 0x%s for code which looks like the beginning of a\n\
1881 function, you can increase the range of the search using the `set\n\
1882 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
1889 else if (pc_is_mips16 (start_pc
))
1891 unsigned short inst
;
1893 /* On MIPS16, any one of the following is likely to be the
1894 start of a function:
1898 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1899 inst
= mips_fetch_instruction (start_pc
);
1900 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1901 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1902 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1903 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1905 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1906 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1911 else if (mips_about_to_return (start_pc
))
1913 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1920 /* Fetch the immediate value from a MIPS16 instruction.
1921 If the previous instruction was an EXTEND, use it to extend
1922 the upper bits of the immediate value. This is a helper function
1923 for mips16_heuristic_proc_desc. */
1926 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1927 unsigned short inst
, /* current instruction */
1928 int nbits
, /* number of bits in imm field */
1929 int scale
, /* scale factor to be applied to imm */
1930 int is_signed
) /* is the imm field signed? */
1934 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1936 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1937 if (offset
& 0x8000) /* check for negative extend */
1938 offset
= 0 - (0x10000 - (offset
& 0xffff));
1939 return offset
| (inst
& 0x1f);
1943 int max_imm
= 1 << nbits
;
1944 int mask
= max_imm
- 1;
1945 int sign_bit
= max_imm
>> 1;
1947 offset
= inst
& mask
;
1948 if (is_signed
&& (offset
& sign_bit
))
1949 offset
= 0 - (max_imm
- offset
);
1950 return offset
* scale
;
1955 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1956 stream from start_pc to limit_pc. */
1959 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1960 struct frame_info
*next_frame
, CORE_ADDR sp
)
1963 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1964 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1965 unsigned inst
= 0; /* current instruction */
1966 unsigned entry_inst
= 0; /* the entry instruction */
1968 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1970 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1971 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1973 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1975 /* Save the previous instruction. If it's an EXTEND, we'll extract
1976 the immediate offset extension from it in mips16_get_imm. */
1979 /* Fetch and decode the instruction. */
1980 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1981 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1982 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1984 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1985 if (offset
< 0) /* negative stack adjustment? */
1986 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1988 /* Exit loop if a positive stack adjustment is found, which
1989 usually means that the stack cleanup code in the function
1990 epilogue is reached. */
1993 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1995 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1996 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1997 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1998 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2000 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2002 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2003 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2004 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2005 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2007 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2009 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2010 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2011 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2013 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2015 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2016 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2017 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2019 else if (inst
== 0x673d) /* move $s1, $sp */
2022 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2024 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2026 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2027 frame_addr
= sp
+ offset
;
2028 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2029 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2031 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2033 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2034 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2035 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2036 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2038 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2040 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2041 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2042 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2043 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2045 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2046 entry_inst
= inst
; /* save for later processing */
2047 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2048 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2051 /* The entry instruction is typically the first instruction in a function,
2052 and it stores registers at offsets relative to the value of the old SP
2053 (before the prologue). But the value of the sp parameter to this
2054 function is the new SP (after the prologue has been executed). So we
2055 can't calculate those offsets until we've seen the entire prologue,
2056 and can calculate what the old SP must have been. */
2057 if (entry_inst
!= 0)
2059 int areg_count
= (entry_inst
>> 8) & 7;
2060 int sreg_count
= (entry_inst
>> 6) & 3;
2062 /* The entry instruction always subtracts 32 from the SP. */
2063 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2065 /* Now we can calculate what the SP must have been at the
2066 start of the function prologue. */
2067 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2069 /* Check if a0-a3 were saved in the caller's argument save area. */
2070 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2072 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2073 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2074 offset
+= mips_saved_regsize (tdep
);
2077 /* Check if the ra register was pushed on the stack. */
2079 if (entry_inst
& 0x20)
2081 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2082 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2083 offset
-= mips_saved_regsize (tdep
);
2086 /* Check if the s0 and s1 registers were pushed on the stack. */
2087 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2089 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2090 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2091 offset
-= mips_saved_regsize (tdep
);
2097 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2098 struct frame_info
*next_frame
, CORE_ADDR sp
)
2101 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2103 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2104 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2105 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2106 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2107 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2109 unsigned long inst
, high_word
, low_word
;
2112 /* Fetch the instruction. */
2113 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2115 /* Save some code by pre-extracting some useful fields. */
2116 high_word
= (inst
>> 16) & 0xffff;
2117 low_word
= inst
& 0xffff;
2118 reg
= high_word
& 0x1f;
2120 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2121 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2122 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2124 if (low_word
& 0x8000) /* negative stack adjustment? */
2125 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2127 /* Exit loop if a positive stack adjustment is found, which
2128 usually means that the stack cleanup code in the function
2129 epilogue is reached. */
2132 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2134 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2135 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2137 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2139 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2140 but the register size used is only 32 bits. Make the address
2141 for the saved register point to the lower 32 bits. */
2142 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2143 set_reg_offset (temp_saved_regs
, reg
,
2144 sp
+ low_word
+ 8 - mips_regsize (current_gdbarch
));
2146 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2148 /* Old gcc frame, r30 is virtual frame pointer. */
2149 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2150 frame_addr
= sp
+ low_word
;
2151 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2153 unsigned alloca_adjust
;
2154 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2155 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2156 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2157 if (alloca_adjust
> 0)
2159 /* FP > SP + frame_size. This may be because
2160 * of an alloca or somethings similar.
2161 * Fix sp to "pre-alloca" value, and try again.
2163 sp
+= alloca_adjust
;
2168 /* move $30,$sp. With different versions of gas this will be either
2169 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2170 Accept any one of these. */
2171 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2173 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2174 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2176 unsigned alloca_adjust
;
2177 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2178 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2179 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2180 if (alloca_adjust
> 0)
2182 /* FP > SP + frame_size. This may be because
2183 * of an alloca or somethings similar.
2184 * Fix sp to "pre-alloca" value, and try again.
2186 sp
+= alloca_adjust
;
2191 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2193 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2194 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2199 static mips_extra_func_info_t
2200 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2201 struct frame_info
*next_frame
, int cur_frame
)
2206 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2212 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2213 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2214 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2215 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2216 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2217 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2219 if (start_pc
+ 200 < limit_pc
)
2220 limit_pc
= start_pc
+ 200;
2221 if (pc_is_mips16 (start_pc
))
2222 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2224 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2225 return &temp_proc_desc
;
2228 struct mips_objfile_private
2234 /* Global used to communicate between non_heuristic_proc_desc and
2235 compare_pdr_entries within qsort (). */
2236 static bfd
*the_bfd
;
2239 compare_pdr_entries (const void *a
, const void *b
)
2241 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2242 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2246 else if (lhs
== rhs
)
2252 static mips_extra_func_info_t
2253 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2255 CORE_ADDR startaddr
;
2256 mips_extra_func_info_t proc_desc
;
2257 struct block
*b
= block_for_pc (pc
);
2259 struct obj_section
*sec
;
2260 struct mips_objfile_private
*priv
;
2262 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2265 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2267 *addrptr
= startaddr
;
2271 sec
= find_pc_section (pc
);
2274 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2276 /* Search the ".pdr" section generated by GAS. This includes most of
2277 the information normally found in ECOFF PDRs. */
2279 the_bfd
= sec
->objfile
->obfd
;
2281 && (the_bfd
->format
== bfd_object
2282 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2283 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2285 /* Right now GAS only outputs the address as a four-byte sequence.
2286 This means that we should not bother with this method on 64-bit
2287 targets (until that is fixed). */
2289 priv
= obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2290 sizeof (struct mips_objfile_private
));
2292 sec
->objfile
->obj_private
= priv
;
2294 else if (priv
== NULL
)
2298 priv
= obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2299 sizeof (struct mips_objfile_private
));
2301 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2304 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2305 priv
->contents
= obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2307 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2308 priv
->contents
, 0, priv
->size
);
2310 /* In general, the .pdr section is sorted. However, in the
2311 presence of multiple code sections (and other corner cases)
2312 it can become unsorted. Sort it so that we can use a faster
2314 qsort (priv
->contents
, priv
->size
/ 32, 32,
2315 compare_pdr_entries
);
2320 sec
->objfile
->obj_private
= priv
;
2324 if (priv
->size
!= 0)
2330 high
= priv
->size
/ 32;
2336 mid
= (low
+ high
) / 2;
2338 ptr
= priv
->contents
+ mid
* 32;
2339 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2340 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2341 SECT_OFF_TEXT (sec
->objfile
));
2342 if (pdr_pc
== startaddr
)
2344 if (pdr_pc
> startaddr
)
2349 while (low
!= high
);
2353 struct symbol
*sym
= find_pc_function (pc
);
2355 /* Fill in what we need of the proc_desc. */
2356 proc_desc
= (mips_extra_func_info_t
)
2357 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2358 sizeof (struct mips_extra_func_info
));
2359 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2361 /* Only used for dummy frames. */
2362 PROC_HIGH_ADDR (proc_desc
) = 0;
2364 PROC_FRAME_OFFSET (proc_desc
)
2365 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2366 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2368 PROC_FRAME_ADJUST (proc_desc
) = 0;
2369 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2371 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2373 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2375 PROC_FREG_OFFSET (proc_desc
)
2376 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2377 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2379 proc_desc
->pdr
.isym
= (long) sym
;
2389 if (startaddr
> BLOCK_START (b
))
2391 /* This is the "pathological" case referred to in a comment in
2392 print_frame_info. It might be better to move this check into
2397 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2399 /* If we never found a PDR for this function in symbol reading, then
2400 examine prologues to find the information. */
2403 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2404 if (PROC_FRAME_REG (proc_desc
) == -1)
2414 static mips_extra_func_info_t
2415 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2417 mips_extra_func_info_t proc_desc
;
2418 CORE_ADDR startaddr
= 0;
2420 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2424 /* IF this is the topmost frame AND
2425 * (this proc does not have debugging information OR
2426 * the PC is in the procedure prologue)
2427 * THEN create a "heuristic" proc_desc (by analyzing
2428 * the actual code) to replace the "official" proc_desc.
2430 if (next_frame
== NULL
)
2432 struct symtab_and_line val
;
2433 struct symbol
*proc_symbol
=
2434 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2438 val
= find_pc_line (BLOCK_START
2439 (SYMBOL_BLOCK_VALUE (proc_symbol
)), 0);
2440 val
.pc
= val
.end
? val
.end
: pc
;
2442 if (!proc_symbol
|| pc
< val
.pc
)
2444 mips_extra_func_info_t found_heuristic
=
2445 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2446 pc
, next_frame
, cur_frame
);
2447 if (found_heuristic
)
2448 proc_desc
= found_heuristic
;
2454 /* Is linked_proc_desc_table really necessary? It only seems to be used
2455 by procedure call dummys. However, the procedures being called ought
2456 to have their own proc_descs, and even if they don't,
2457 heuristic_proc_desc knows how to create them! */
2459 struct linked_proc_info
*link
;
2461 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2462 if (PROC_LOW_ADDR (&link
->info
) <= pc
2463 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2467 startaddr
= heuristic_proc_start (pc
);
2469 proc_desc
= heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2475 get_frame_pointer (struct frame_info
*frame
, mips_extra_func_info_t proc_desc
)
2477 return (read_next_frame_reg (frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2478 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2481 static mips_extra_func_info_t cached_proc_desc
;
2484 mips_frame_chain (struct frame_info
*frame
)
2486 mips_extra_func_info_t proc_desc
;
2488 CORE_ADDR saved_pc
= DEPRECATED_FRAME_SAVED_PC (frame
);
2490 /* Check if the PC is inside a call stub. If it is, fetch the
2491 PC of the caller of that stub. */
2492 if ((tmp
= SKIP_TRAMPOLINE_CODE (saved_pc
)) != 0)
2495 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc
, 0, 0))
2497 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2498 is well, frame->frame the bottom of the current frame will
2499 contain that value. */
2500 return get_frame_base (frame
);
2503 /* Look up the procedure descriptor for this PC. */
2504 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2508 cached_proc_desc
= proc_desc
;
2510 /* If no frame pointer and frame size is zero, we must be at end
2511 of stack (or otherwise hosed). If we don't check frame size,
2512 we loop forever if we see a zero size frame. */
2513 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2514 && PROC_FRAME_OFFSET (proc_desc
) == 0
2515 /* The previous frame from a sigtramp frame might be frameless
2516 and have frame size zero. */
2517 && !(get_frame_type (frame
) == SIGTRAMP_FRAME
)
2518 /* For a generic dummy frame, let get_frame_pointer() unwind a
2519 register value saved as part of the dummy frame call. */
2520 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0)))
2523 return get_frame_pointer (frame
, proc_desc
);
2527 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2530 mips_extra_func_info_t proc_desc
;
2532 if (get_frame_type (fci
) == DUMMY_FRAME
)
2535 /* Use proc_desc calculated in frame_chain. When there is no
2536 next frame, i.e, get_next_frame (fci) == NULL, we call
2537 find_proc_desc () to calculate it, passing an explicit
2538 NULL as the frame parameter. */
2540 get_next_frame (fci
)
2542 : find_proc_desc (get_frame_pc (fci
),
2543 NULL
/* i.e, get_next_frame (fci) */ ,
2546 frame_extra_info_zalloc (fci
, sizeof (struct frame_extra_info
));
2548 get_frame_extra_info (fci
)->proc_desc
=
2549 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2552 /* Fixup frame-pointer - only needed for top frame */
2553 /* This may not be quite right, if proc has a real frame register.
2554 Get the value of the frame relative sp, procedure might have been
2555 interrupted by a signal at it's very start. */
2556 if (get_frame_pc (fci
) == PROC_LOW_ADDR (proc_desc
)
2557 && !PROC_DESC_IS_DUMMY (proc_desc
))
2558 deprecated_update_frame_base_hack (fci
,
2559 read_next_frame_reg (get_next_frame
2563 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci
), 0, 0))
2564 /* Do not ``fix'' fci->frame. It will have the value of the
2565 generic dummy frame's top-of-stack (since the draft
2566 fci->frame is obtained by returning the unwound stack
2567 pointer) and that is what we want. That way the fci->frame
2568 value will match the top-of-stack value that was saved as
2569 part of the dummy frames data. */
2572 deprecated_update_frame_base_hack (fci
,
2573 get_frame_pointer (get_next_frame
2577 if (proc_desc
== &temp_proc_desc
)
2581 /* Do not set the saved registers for a sigtramp frame,
2582 mips_find_saved_registers will do that for us. We can't
2583 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2585 /* FIXME: cagney/2002-11-18: This problem will go away once
2586 frame.c:get_prev_frame() is modified to set the frame's
2587 type before calling functions like this. */
2588 find_pc_partial_function (get_frame_pc (fci
), &name
,
2589 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2590 if (!PC_IN_SIGTRAMP (get_frame_pc (fci
), name
))
2592 frame_saved_regs_zalloc (fci
);
2593 /* Set value of previous frame's stack pointer.
2594 Remember that saved_regs[SP_REGNUM] is special in
2595 that it contains the value of the stack pointer
2596 register. The other saved_regs values are addresses
2597 (in the inferior) at which a given register's value
2599 set_reg_offset (temp_saved_regs
, SP_REGNUM
,
2600 get_frame_base (fci
));
2601 set_reg_offset (temp_saved_regs
, mips_regnum (current_gdbarch
)->pc
,
2602 temp_saved_regs
[RA_REGNUM
]);
2603 memcpy (deprecated_get_frame_saved_regs (fci
), temp_saved_regs
,
2604 SIZEOF_FRAME_SAVED_REGS
);
2608 /* hack: if argument regs are saved, guess these contain args */
2609 /* assume we can't tell how many args for now */
2610 get_frame_extra_info (fci
)->num_args
= -1;
2611 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2613 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2615 get_frame_extra_info (fci
)->num_args
= regnum
- A0_REGNUM
+ 1;
2622 /* MIPS stack frames are almost impenetrable. When execution stops,
2623 we basically have to look at symbol information for the function
2624 that we stopped in, which tells us *which* register (if any) is
2625 the base of the frame pointer, and what offset from that register
2626 the frame itself is at.
2628 This presents a problem when trying to examine a stack in memory
2629 (that isn't executing at the moment), using the "frame" command. We
2630 don't have a PC, nor do we have any registers except SP.
2632 This routine takes two arguments, SP and PC, and tries to make the
2633 cached frames look as if these two arguments defined a frame on the
2634 cache. This allows the rest of info frame to extract the important
2635 arguments without difficulty. */
2638 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2641 error ("MIPS frame specifications require two arguments: sp and pc");
2643 return create_new_frame (argv
[0], argv
[1]);
2646 /* According to the current ABI, should the type be passed in a
2647 floating-point register (assuming that there is space)? When there
2648 is no FPU, FP are not even considered as possibile candidates for
2649 FP registers and, consequently this returns false - forces FP
2650 arguments into integer registers. */
2653 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2655 return ((typecode
== TYPE_CODE_FLT
2657 && (typecode
== TYPE_CODE_STRUCT
2658 || typecode
== TYPE_CODE_UNION
)
2659 && TYPE_NFIELDS (arg_type
) == 1
2660 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2661 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2664 /* On o32, argument passing in GPRs depends on the alignment of the type being
2665 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2668 mips_type_needs_double_align (struct type
*type
)
2670 enum type_code typecode
= TYPE_CODE (type
);
2672 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2674 else if (typecode
== TYPE_CODE_STRUCT
)
2676 if (TYPE_NFIELDS (type
) < 1)
2678 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2680 else if (typecode
== TYPE_CODE_UNION
)
2684 n
= TYPE_NFIELDS (type
);
2685 for (i
= 0; i
< n
; i
++)
2686 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2693 /* Adjust the address downward (direction of stack growth) so that it
2694 is correctly aligned for a new stack frame. */
2696 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2698 return align_down (addr
, 16);
2701 /* Determine how a return value is stored within the MIPS register
2702 file, given the return type `valtype'. */
2704 struct return_value_word
2713 return_value_location (struct type
*valtype
,
2714 struct return_value_word
*hi
,
2715 struct return_value_word
*lo
)
2717 int len
= TYPE_LENGTH (valtype
);
2718 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2720 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2721 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2722 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2724 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2726 /* We need to break a 64bit float in two 32 bit halves and
2727 spread them across a floating-point register pair. */
2728 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2729 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
2730 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2731 && register_size (current_gdbarch
,
2732 mips_regnum (current_gdbarch
)->
2733 fp0
) == 8) ? 4 : 0);
2734 hi
->reg_offset
= lo
->reg_offset
;
2735 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
2736 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
2742 /* The floating point value fits in a single floating-point
2744 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2745 && register_size (current_gdbarch
,
2746 mips_regnum (current_gdbarch
)->
2748 && len
== 4) ? 4 : 0);
2749 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
2760 /* Locate a result possibly spread across two registers. */
2762 lo
->reg
= regnum
+ 0;
2763 hi
->reg
= regnum
+ 1;
2764 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2765 && len
< mips_saved_regsize (tdep
))
2767 /* "un-left-justify" the value in the low register */
2768 lo
->reg_offset
= mips_saved_regsize (tdep
) - len
;
2773 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_saved_regsize (tdep
) /* odd-size structs */
2774 && len
< mips_saved_regsize (tdep
) * 2
2775 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2776 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2778 /* "un-left-justify" the value spread across two registers. */
2779 lo
->reg_offset
= 2 * mips_saved_regsize (tdep
) - len
;
2780 lo
->len
= mips_saved_regsize (tdep
) - lo
->reg_offset
;
2782 hi
->len
= len
- lo
->len
;
2786 /* Only perform a partial copy of the second register. */
2789 if (len
> mips_saved_regsize (tdep
))
2791 lo
->len
= mips_saved_regsize (tdep
);
2792 hi
->len
= len
- mips_saved_regsize (tdep
);
2800 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2801 && register_size (current_gdbarch
, regnum
) == 8
2802 && mips_saved_regsize (tdep
) == 4)
2804 /* Account for the fact that only the least-signficant part
2805 of the register is being used */
2806 lo
->reg_offset
+= 4;
2807 hi
->reg_offset
+= 4;
2810 hi
->buf_offset
= lo
->len
;
2814 /* Should call_function allocate stack space for a struct return? */
2817 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
2819 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2820 return (TYPE_LENGTH (type
) > 2 * mips_saved_regsize (tdep
));
2823 /* Should call_function pass struct by reference?
2824 For each architecture, structs are passed either by
2825 value or by reference, depending on their size. */
2828 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
2830 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
2831 int len
= TYPE_LENGTH (check_typedef (type
));
2832 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2834 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2835 return (len
> mips_saved_regsize (tdep
));
2841 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2842 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2843 int nargs
, struct value
**args
, CORE_ADDR sp
,
2844 int struct_return
, CORE_ADDR struct_addr
)
2850 int stack_offset
= 0;
2851 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2853 /* For shared libraries, "t9" needs to point at the function
2855 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2857 /* Set the return address register to point to the entry point of
2858 the program, where a breakpoint lies in wait. */
2859 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2861 /* First ensure that the stack and structure return address (if any)
2862 are properly aligned. The stack has to be at least 64-bit
2863 aligned even on 32-bit machines, because doubles must be 64-bit
2864 aligned. For n32 and n64, stack frames need to be 128-bit
2865 aligned, so we round to this widest known alignment. */
2867 sp
= align_down (sp
, 16);
2868 struct_addr
= align_down (struct_addr
, 16);
2870 /* Now make space on the stack for the args. We allocate more
2871 than necessary for EABI, because the first few arguments are
2872 passed in registers, but that's OK. */
2873 for (argnum
= 0; argnum
< nargs
; argnum
++)
2874 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2875 mips_stack_argsize (tdep
));
2876 sp
-= align_up (len
, 16);
2879 fprintf_unfiltered (gdb_stdlog
,
2880 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2881 paddr_nz (sp
), (long) align_up (len
, 16));
2883 /* Initialize the integer and float register pointers. */
2885 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2887 /* The struct_return pointer occupies the first parameter-passing reg. */
2891 fprintf_unfiltered (gdb_stdlog
,
2892 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2893 argreg
, paddr_nz (struct_addr
));
2894 write_register (argreg
++, struct_addr
);
2897 /* Now load as many as possible of the first arguments into
2898 registers, and push the rest onto the stack. Loop thru args
2899 from first to last. */
2900 for (argnum
= 0; argnum
< nargs
; argnum
++)
2903 char valbuf
[MAX_REGISTER_SIZE
];
2904 struct value
*arg
= args
[argnum
];
2905 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2906 int len
= TYPE_LENGTH (arg_type
);
2907 enum type_code typecode
= TYPE_CODE (arg_type
);
2910 fprintf_unfiltered (gdb_stdlog
,
2911 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2912 argnum
+ 1, len
, (int) typecode
);
2914 /* The EABI passes structures that do not fit in a register by
2916 if (len
> mips_saved_regsize (tdep
)
2917 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2919 store_unsigned_integer (valbuf
, mips_saved_regsize (tdep
),
2920 VALUE_ADDRESS (arg
));
2921 typecode
= TYPE_CODE_PTR
;
2922 len
= mips_saved_regsize (tdep
);
2925 fprintf_unfiltered (gdb_stdlog
, " push");
2928 val
= (char *) VALUE_CONTENTS (arg
);
2930 /* 32-bit ABIs always start floating point arguments in an
2931 even-numbered floating point register. Round the FP register
2932 up before the check to see if there are any FP registers
2933 left. Non MIPS_EABI targets also pass the FP in the integer
2934 registers so also round up normal registers. */
2935 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
2937 if ((float_argreg
& 1))
2941 /* Floating point arguments passed in registers have to be
2942 treated specially. On 32-bit architectures, doubles
2943 are passed in register pairs; the even register gets
2944 the low word, and the odd register gets the high word.
2945 On non-EABI processors, the first two floating point arguments are
2946 also copied to general registers, because MIPS16 functions
2947 don't use float registers for arguments. This duplication of
2948 arguments in general registers can't hurt non-MIPS16 functions
2949 because those registers are normally skipped. */
2950 /* MIPS_EABI squeezes a struct that contains a single floating
2951 point value into an FP register instead of pushing it onto the
2953 if (fp_register_arg_p (typecode
, arg_type
)
2954 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2956 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2958 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2959 unsigned long regval
;
2961 /* Write the low word of the double to the even register(s). */
2962 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2964 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2965 float_argreg
, phex (regval
, 4));
2966 write_register (float_argreg
++, regval
);
2968 /* Write the high word of the double to the odd register(s). */
2969 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2971 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2972 float_argreg
, phex (regval
, 4));
2973 write_register (float_argreg
++, regval
);
2977 /* This is a floating point value that fits entirely
2978 in a single register. */
2979 /* On 32 bit ABI's the float_argreg is further adjusted
2980 above to ensure that it is even register aligned. */
2981 LONGEST regval
= extract_unsigned_integer (val
, len
);
2983 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2984 float_argreg
, phex (regval
, len
));
2985 write_register (float_argreg
++, regval
);
2990 /* Copy the argument to general registers or the stack in
2991 register-sized pieces. Large arguments are split between
2992 registers and stack. */
2993 /* Note: structs whose size is not a multiple of
2994 mips_regsize() are treated specially: Irix cc passes them
2995 in registers where gcc sometimes puts them on the stack.
2996 For maximum compatibility, we will put them in both
2998 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
2999 && (len
% mips_saved_regsize (tdep
) != 0));
3001 /* Note: Floating-point values that didn't fit into an FP
3002 register are only written to memory. */
3005 /* Remember if the argument was written to the stack. */
3006 int stack_used_p
= 0;
3007 int partial_len
= (len
< mips_saved_regsize (tdep
)
3008 ? len
: mips_saved_regsize (tdep
));
3011 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3014 /* Write this portion of the argument to the stack. */
3015 if (argreg
> MIPS_LAST_ARG_REGNUM
3017 || fp_register_arg_p (typecode
, arg_type
))
3019 /* Should shorter than int integer values be
3020 promoted to int before being stored? */
3021 int longword_offset
= 0;
3024 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3026 if (mips_stack_argsize (tdep
) == 8
3027 && (typecode
== TYPE_CODE_INT
3028 || typecode
== TYPE_CODE_PTR
3029 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3030 longword_offset
= mips_stack_argsize (tdep
) - len
;
3031 else if ((typecode
== TYPE_CODE_STRUCT
3032 || typecode
== TYPE_CODE_UNION
)
3033 && (TYPE_LENGTH (arg_type
)
3034 < mips_stack_argsize (tdep
)))
3035 longword_offset
= mips_stack_argsize (tdep
) - len
;
3040 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3041 paddr_nz (stack_offset
));
3042 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3043 paddr_nz (longword_offset
));
3046 addr
= sp
+ stack_offset
+ longword_offset
;
3051 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3053 for (i
= 0; i
< partial_len
; i
++)
3055 fprintf_unfiltered (gdb_stdlog
, "%02x",
3059 write_memory (addr
, val
, partial_len
);
3062 /* Note!!! This is NOT an else clause. Odd sized
3063 structs may go thru BOTH paths. Floating point
3064 arguments will not. */
3065 /* Write this portion of the argument to a general
3066 purpose register. */
3067 if (argreg
<= MIPS_LAST_ARG_REGNUM
3068 && !fp_register_arg_p (typecode
, arg_type
))
3071 extract_unsigned_integer (val
, partial_len
);
3074 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3077 mips_saved_regsize (tdep
)));
3078 write_register (argreg
, regval
);
3085 /* Compute the the offset into the stack at which we
3086 will copy the next parameter.
3088 In the new EABI (and the NABI32), the stack_offset
3089 only needs to be adjusted when it has been used. */
3092 stack_offset
+= align_up (partial_len
,
3093 mips_stack_argsize (tdep
));
3097 fprintf_unfiltered (gdb_stdlog
, "\n");
3100 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3102 /* Return adjusted stack pointer. */
3106 /* Given a return value in `regbuf' with a type `valtype', extract and
3107 copy its value into `valbuf'. */
3110 mips_eabi_extract_return_value (struct type
*valtype
,
3111 char regbuf
[], char *valbuf
)
3113 struct return_value_word lo
;
3114 struct return_value_word hi
;
3115 return_value_location (valtype
, &hi
, &lo
);
3117 memcpy (valbuf
+ lo
.buf_offset
,
3118 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3119 lo
.reg_offset
, lo
.len
);
3122 memcpy (valbuf
+ hi
.buf_offset
,
3123 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3124 hi
.reg_offset
, hi
.len
);
3127 /* Given a return value in `valbuf' with a type `valtype', write it's
3128 value into the appropriate register. */
3131 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3133 char raw_buffer
[MAX_REGISTER_SIZE
];
3134 struct return_value_word lo
;
3135 struct return_value_word hi
;
3136 return_value_location (valtype
, &hi
, &lo
);
3138 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3139 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3140 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3141 raw_buffer
, register_size (current_gdbarch
,
3146 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3147 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3148 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3150 register_size (current_gdbarch
,
3155 /* N32/N64 ABI stuff. */
3158 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3159 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3160 int nargs
, struct value
**args
, CORE_ADDR sp
,
3161 int struct_return
, CORE_ADDR struct_addr
)
3167 int stack_offset
= 0;
3168 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3170 /* For shared libraries, "t9" needs to point at the function
3172 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3174 /* Set the return address register to point to the entry point of
3175 the program, where a breakpoint lies in wait. */
3176 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3178 /* First ensure that the stack and structure return address (if any)
3179 are properly aligned. The stack has to be at least 64-bit
3180 aligned even on 32-bit machines, because doubles must be 64-bit
3181 aligned. For n32 and n64, stack frames need to be 128-bit
3182 aligned, so we round to this widest known alignment. */
3184 sp
= align_down (sp
, 16);
3185 struct_addr
= align_down (struct_addr
, 16);
3187 /* Now make space on the stack for the args. */
3188 for (argnum
= 0; argnum
< nargs
; argnum
++)
3189 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3190 mips_stack_argsize (tdep
));
3191 sp
-= align_up (len
, 16);
3194 fprintf_unfiltered (gdb_stdlog
,
3195 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3196 paddr_nz (sp
), (long) align_up (len
, 16));
3198 /* Initialize the integer and float register pointers. */
3200 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3202 /* The struct_return pointer occupies the first parameter-passing reg. */
3206 fprintf_unfiltered (gdb_stdlog
,
3207 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3208 argreg
, paddr_nz (struct_addr
));
3209 write_register (argreg
++, struct_addr
);
3212 /* Now load as many as possible of the first arguments into
3213 registers, and push the rest onto the stack. Loop thru args
3214 from first to last. */
3215 for (argnum
= 0; argnum
< nargs
; argnum
++)
3218 char valbuf
[MAX_REGISTER_SIZE
];
3219 struct value
*arg
= args
[argnum
];
3220 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3221 int len
= TYPE_LENGTH (arg_type
);
3222 enum type_code typecode
= TYPE_CODE (arg_type
);
3225 fprintf_unfiltered (gdb_stdlog
,
3226 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3227 argnum
+ 1, len
, (int) typecode
);
3229 val
= (char *) VALUE_CONTENTS (arg
);
3231 if (fp_register_arg_p (typecode
, arg_type
)
3232 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3234 /* This is a floating point value that fits entirely
3235 in a single register. */
3236 /* On 32 bit ABI's the float_argreg is further adjusted
3237 above to ensure that it is even register aligned. */
3238 LONGEST regval
= extract_unsigned_integer (val
, len
);
3240 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3241 float_argreg
, phex (regval
, len
));
3242 write_register (float_argreg
++, regval
);
3245 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3246 argreg
, phex (regval
, len
));
3247 write_register (argreg
, regval
);
3252 /* Copy the argument to general registers or the stack in
3253 register-sized pieces. Large arguments are split between
3254 registers and stack. */
3255 /* Note: structs whose size is not a multiple of
3256 mips_regsize() are treated specially: Irix cc passes them
3257 in registers where gcc sometimes puts them on the stack.
3258 For maximum compatibility, we will put them in both
3260 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3261 && (len
% mips_saved_regsize (tdep
) != 0));
3262 /* Note: Floating-point values that didn't fit into an FP
3263 register are only written to memory. */
3266 /* Rememer if the argument was written to the stack. */
3267 int stack_used_p
= 0;
3268 int partial_len
= (len
< mips_saved_regsize (tdep
)
3269 ? len
: mips_saved_regsize (tdep
));
3272 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3275 /* Write this portion of the argument to the stack. */
3276 if (argreg
> MIPS_LAST_ARG_REGNUM
3278 || fp_register_arg_p (typecode
, arg_type
))
3280 /* Should shorter than int integer values be
3281 promoted to int before being stored? */
3282 int longword_offset
= 0;
3285 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3287 if (mips_stack_argsize (tdep
) == 8
3288 && (typecode
== TYPE_CODE_INT
3289 || typecode
== TYPE_CODE_PTR
3290 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3291 longword_offset
= mips_stack_argsize (tdep
) - len
;
3296 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3297 paddr_nz (stack_offset
));
3298 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3299 paddr_nz (longword_offset
));
3302 addr
= sp
+ stack_offset
+ longword_offset
;
3307 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3309 for (i
= 0; i
< partial_len
; i
++)
3311 fprintf_unfiltered (gdb_stdlog
, "%02x",
3315 write_memory (addr
, val
, partial_len
);
3318 /* Note!!! This is NOT an else clause. Odd sized
3319 structs may go thru BOTH paths. Floating point
3320 arguments will not. */
3321 /* Write this portion of the argument to a general
3322 purpose register. */
3323 if (argreg
<= MIPS_LAST_ARG_REGNUM
3324 && !fp_register_arg_p (typecode
, arg_type
))
3327 extract_unsigned_integer (val
, partial_len
);
3329 /* A non-floating-point argument being passed in a
3330 general register. If a struct or union, and if
3331 the remaining length is smaller than the register
3332 size, we have to adjust the register value on
3335 It does not seem to be necessary to do the
3336 same for integral types.
3338 cagney/2001-07-23: gdb/179: Also, GCC, when
3339 outputting LE O32 with sizeof (struct) <
3340 mips_saved_regsize(), generates a left shift as
3341 part of storing the argument in a register a
3342 register (the left shift isn't generated when
3343 sizeof (struct) >= mips_saved_regsize()). Since
3344 it is quite possible that this is GCC
3345 contradicting the LE/O32 ABI, GDB has not been
3346 adjusted to accommodate this. Either someone
3347 needs to demonstrate that the LE/O32 ABI
3348 specifies such a left shift OR this new ABI gets
3349 identified as such and GDB gets tweaked
3352 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3353 && partial_len
< mips_saved_regsize (tdep
)
3354 && (typecode
== TYPE_CODE_STRUCT
||
3355 typecode
== TYPE_CODE_UNION
))
3356 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3360 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3363 mips_saved_regsize (tdep
)));
3364 write_register (argreg
, regval
);
3371 /* Compute the the offset into the stack at which we
3372 will copy the next parameter.
3374 In N32 (N64?), the stack_offset only needs to be
3375 adjusted when it has been used. */
3378 stack_offset
+= align_up (partial_len
,
3379 mips_stack_argsize (tdep
));
3383 fprintf_unfiltered (gdb_stdlog
, "\n");
3386 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3388 /* Return adjusted stack pointer. */
3392 static enum return_value_convention
3393 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3394 struct type
*type
, struct regcache
*regcache
,
3395 void *readbuf
, const void *writebuf
)
3397 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3398 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3399 || TYPE_CODE (type
) == TYPE_CODE_UNION
3400 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3401 || TYPE_LENGTH (type
) > 2 * mips_saved_regsize (tdep
))
3402 return RETURN_VALUE_STRUCT_CONVENTION
;
3403 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3404 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3406 /* A floating-point value belongs in the least significant part
3409 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3410 mips_xfer_register (regcache
,
3411 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3413 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3414 return RETURN_VALUE_REGISTER_CONVENTION
;
3416 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3417 && TYPE_NFIELDS (type
) <= 2
3418 && TYPE_NFIELDS (type
) >= 1
3419 && ((TYPE_NFIELDS (type
) == 1
3420 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3422 || (TYPE_NFIELDS (type
) == 2
3423 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3425 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3427 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3429 /* A struct that contains one or two floats. Each value is part
3430 in the least significant part of their floating point
3432 bfd_byte reg
[MAX_REGISTER_SIZE
];
3435 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3436 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3438 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3441 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3443 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3444 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3445 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3447 return RETURN_VALUE_REGISTER_CONVENTION
;
3449 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3450 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3452 /* A structure or union. Extract the left justified value,
3453 regardless of the byte order. I.e. DO NOT USE
3457 for (offset
= 0, regnum
= V0_REGNUM
;
3458 offset
< TYPE_LENGTH (type
);
3459 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3461 int xfer
= register_size (current_gdbarch
, regnum
);
3462 if (offset
+ xfer
> TYPE_LENGTH (type
))
3463 xfer
= TYPE_LENGTH (type
) - offset
;
3465 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3466 offset
, xfer
, regnum
);
3467 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3468 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3470 return RETURN_VALUE_REGISTER_CONVENTION
;
3474 /* A scalar extract each part but least-significant-byte
3478 for (offset
= 0, regnum
= V0_REGNUM
;
3479 offset
< TYPE_LENGTH (type
);
3480 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3482 int xfer
= register_size (current_gdbarch
, regnum
);
3484 if (offset
+ xfer
> TYPE_LENGTH (type
))
3485 xfer
= TYPE_LENGTH (type
) - offset
;
3487 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3488 offset
, xfer
, regnum
);
3489 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3490 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3492 return RETURN_VALUE_REGISTER_CONVENTION
;
3496 /* O32 ABI stuff. */
3499 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3500 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3501 int nargs
, struct value
**args
, CORE_ADDR sp
,
3502 int struct_return
, CORE_ADDR struct_addr
)
3508 int stack_offset
= 0;
3509 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3511 /* For shared libraries, "t9" needs to point at the function
3513 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3515 /* Set the return address register to point to the entry point of
3516 the program, where a breakpoint lies in wait. */
3517 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3519 /* First ensure that the stack and structure return address (if any)
3520 are properly aligned. The stack has to be at least 64-bit
3521 aligned even on 32-bit machines, because doubles must be 64-bit
3522 aligned. For n32 and n64, stack frames need to be 128-bit
3523 aligned, so we round to this widest known alignment. */
3525 sp
= align_down (sp
, 16);
3526 struct_addr
= align_down (struct_addr
, 16);
3528 /* Now make space on the stack for the args. */
3529 for (argnum
= 0; argnum
< nargs
; argnum
++)
3530 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3531 mips_stack_argsize (tdep
));
3532 sp
-= align_up (len
, 16);
3535 fprintf_unfiltered (gdb_stdlog
,
3536 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3537 paddr_nz (sp
), (long) align_up (len
, 16));
3539 /* Initialize the integer and float register pointers. */
3541 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3543 /* The struct_return pointer occupies the first parameter-passing reg. */
3547 fprintf_unfiltered (gdb_stdlog
,
3548 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3549 argreg
, paddr_nz (struct_addr
));
3550 write_register (argreg
++, struct_addr
);
3551 stack_offset
+= mips_stack_argsize (tdep
);
3554 /* Now load as many as possible of the first arguments into
3555 registers, and push the rest onto the stack. Loop thru args
3556 from first to last. */
3557 for (argnum
= 0; argnum
< nargs
; argnum
++)
3560 char valbuf
[MAX_REGISTER_SIZE
];
3561 struct value
*arg
= args
[argnum
];
3562 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3563 int len
= TYPE_LENGTH (arg_type
);
3564 enum type_code typecode
= TYPE_CODE (arg_type
);
3567 fprintf_unfiltered (gdb_stdlog
,
3568 "mips_o32_push_dummy_call: %d len=%d type=%d",
3569 argnum
+ 1, len
, (int) typecode
);
3571 val
= (char *) VALUE_CONTENTS (arg
);
3573 /* 32-bit ABIs always start floating point arguments in an
3574 even-numbered floating point register. Round the FP register
3575 up before the check to see if there are any FP registers
3576 left. O32/O64 targets also pass the FP in the integer
3577 registers so also round up normal registers. */
3578 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
3580 if ((float_argreg
& 1))
3584 /* Floating point arguments passed in registers have to be
3585 treated specially. On 32-bit architectures, doubles
3586 are passed in register pairs; the even register gets
3587 the low word, and the odd register gets the high word.
3588 On O32/O64, the first two floating point arguments are
3589 also copied to general registers, because MIPS16 functions
3590 don't use float registers for arguments. This duplication of
3591 arguments in general registers can't hurt non-MIPS16 functions
3592 because those registers are normally skipped. */
3594 if (fp_register_arg_p (typecode
, arg_type
)
3595 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3597 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3599 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3600 unsigned long regval
;
3602 /* Write the low word of the double to the even register(s). */
3603 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3605 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3606 float_argreg
, phex (regval
, 4));
3607 write_register (float_argreg
++, regval
);
3609 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3610 argreg
, phex (regval
, 4));
3611 write_register (argreg
++, regval
);
3613 /* Write the high word of the double to the odd register(s). */
3614 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3616 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3617 float_argreg
, phex (regval
, 4));
3618 write_register (float_argreg
++, regval
);
3621 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3622 argreg
, phex (regval
, 4));
3623 write_register (argreg
++, regval
);
3627 /* This is a floating point value that fits entirely
3628 in a single register. */
3629 /* On 32 bit ABI's the float_argreg is further adjusted
3630 above to ensure that it is even register aligned. */
3631 LONGEST regval
= extract_unsigned_integer (val
, len
);
3633 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3634 float_argreg
, phex (regval
, len
));
3635 write_register (float_argreg
++, regval
);
3636 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3637 registers for each argument. The below is (my
3638 guess) to ensure that the corresponding integer
3639 register has reserved the same space. */
3641 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3642 argreg
, phex (regval
, len
));
3643 write_register (argreg
, regval
);
3644 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3646 /* Reserve space for the FP register. */
3647 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
3651 /* Copy the argument to general registers or the stack in
3652 register-sized pieces. Large arguments are split between
3653 registers and stack. */
3654 /* Note: structs whose size is not a multiple of
3655 mips_regsize() are treated specially: Irix cc passes them
3656 in registers where gcc sometimes puts them on the stack.
3657 For maximum compatibility, we will put them in both
3659 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3660 && (len
% mips_saved_regsize (tdep
) != 0));
3661 /* Structures should be aligned to eight bytes (even arg registers)
3662 on MIPS_ABI_O32, if their first member has double precision. */
3663 if (mips_saved_regsize (tdep
) < 8
3664 && mips_type_needs_double_align (arg_type
))
3669 /* Note: Floating-point values that didn't fit into an FP
3670 register are only written to memory. */
3673 /* Remember if the argument was written to the stack. */
3674 int stack_used_p
= 0;
3675 int partial_len
= (len
< mips_saved_regsize (tdep
)
3676 ? len
: mips_saved_regsize (tdep
));
3679 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3682 /* Write this portion of the argument to the stack. */
3683 if (argreg
> MIPS_LAST_ARG_REGNUM
3685 || fp_register_arg_p (typecode
, arg_type
))
3687 /* Should shorter than int integer values be
3688 promoted to int before being stored? */
3689 int longword_offset
= 0;
3692 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3694 if (mips_stack_argsize (tdep
) == 8
3695 && (typecode
== TYPE_CODE_INT
3696 || typecode
== TYPE_CODE_PTR
3697 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3698 longword_offset
= mips_stack_argsize (tdep
) - len
;
3703 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3704 paddr_nz (stack_offset
));
3705 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3706 paddr_nz (longword_offset
));
3709 addr
= sp
+ stack_offset
+ longword_offset
;
3714 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3716 for (i
= 0; i
< partial_len
; i
++)
3718 fprintf_unfiltered (gdb_stdlog
, "%02x",
3722 write_memory (addr
, val
, partial_len
);
3725 /* Note!!! This is NOT an else clause. Odd sized
3726 structs may go thru BOTH paths. Floating point
3727 arguments will not. */
3728 /* Write this portion of the argument to a general
3729 purpose register. */
3730 if (argreg
<= MIPS_LAST_ARG_REGNUM
3731 && !fp_register_arg_p (typecode
, arg_type
))
3733 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3734 /* Value may need to be sign extended, because
3735 mips_regsize() != mips_saved_regsize(). */
3737 /* A non-floating-point argument being passed in a
3738 general register. If a struct or union, and if
3739 the remaining length is smaller than the register
3740 size, we have to adjust the register value on
3743 It does not seem to be necessary to do the
3744 same for integral types.
3746 Also don't do this adjustment on O64 binaries.
3748 cagney/2001-07-23: gdb/179: Also, GCC, when
3749 outputting LE O32 with sizeof (struct) <
3750 mips_saved_regsize(), generates a left shift as
3751 part of storing the argument in a register a
3752 register (the left shift isn't generated when
3753 sizeof (struct) >= mips_saved_regsize()). Since
3754 it is quite possible that this is GCC
3755 contradicting the LE/O32 ABI, GDB has not been
3756 adjusted to accommodate this. Either someone
3757 needs to demonstrate that the LE/O32 ABI
3758 specifies such a left shift OR this new ABI gets
3759 identified as such and GDB gets tweaked
3762 if (mips_saved_regsize (tdep
) < 8
3763 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3764 && partial_len
< mips_saved_regsize (tdep
)
3765 && (typecode
== TYPE_CODE_STRUCT
||
3766 typecode
== TYPE_CODE_UNION
))
3767 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3771 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3774 mips_saved_regsize (tdep
)));
3775 write_register (argreg
, regval
);
3778 /* Prevent subsequent floating point arguments from
3779 being passed in floating point registers. */
3780 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3786 /* Compute the the offset into the stack at which we
3787 will copy the next parameter.
3789 In older ABIs, the caller reserved space for
3790 registers that contained arguments. This was loosely
3791 refered to as their "home". Consequently, space is
3792 always allocated. */
3794 stack_offset
+= align_up (partial_len
,
3795 mips_stack_argsize (tdep
));
3799 fprintf_unfiltered (gdb_stdlog
, "\n");
3802 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3804 /* Return adjusted stack pointer. */
3808 static enum return_value_convention
3809 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3810 struct regcache
*regcache
,
3811 void *readbuf
, const void *writebuf
)
3813 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3815 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3816 || TYPE_CODE (type
) == TYPE_CODE_UNION
3817 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3818 return RETURN_VALUE_STRUCT_CONVENTION
;
3819 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3820 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3822 /* A single-precision floating-point value. It fits in the
3823 least significant part of FP0. */
3825 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3826 mips_xfer_register (regcache
,
3827 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3829 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3830 return RETURN_VALUE_REGISTER_CONVENTION
;
3832 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3833 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3835 /* A double-precision floating-point value. The most
3836 significant part goes in FP1, and the least significant in
3839 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3840 switch (TARGET_BYTE_ORDER
)
3842 case BFD_ENDIAN_LITTLE
:
3843 mips_xfer_register (regcache
,
3844 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3845 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3846 mips_xfer_register (regcache
,
3847 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3848 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3850 case BFD_ENDIAN_BIG
:
3851 mips_xfer_register (regcache
,
3852 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3853 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3854 mips_xfer_register (regcache
,
3855 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3856 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3859 internal_error (__FILE__
, __LINE__
, "bad switch");
3861 return RETURN_VALUE_REGISTER_CONVENTION
;
3864 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3865 && TYPE_NFIELDS (type
) <= 2
3866 && TYPE_NFIELDS (type
) >= 1
3867 && ((TYPE_NFIELDS (type
) == 1
3868 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3870 || (TYPE_NFIELDS (type
) == 2
3871 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3873 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3875 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3877 /* A struct that contains one or two floats. Each value is part
3878 in the least significant part of their floating point
3880 bfd_byte reg
[MAX_REGISTER_SIZE
];
3883 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3884 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3886 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3889 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3891 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3892 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3893 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3895 return RETURN_VALUE_REGISTER_CONVENTION
;
3899 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3900 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3902 /* A structure or union. Extract the left justified value,
3903 regardless of the byte order. I.e. DO NOT USE
3907 for (offset
= 0, regnum
= V0_REGNUM
;
3908 offset
< TYPE_LENGTH (type
);
3909 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3911 int xfer
= register_size (current_gdbarch
, regnum
);
3912 if (offset
+ xfer
> TYPE_LENGTH (type
))
3913 xfer
= TYPE_LENGTH (type
) - offset
;
3915 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3916 offset
, xfer
, regnum
);
3917 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3918 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3920 return RETURN_VALUE_REGISTER_CONVENTION
;
3925 /* A scalar extract each part but least-significant-byte
3926 justified. o32 thinks registers are 4 byte, regardless of
3927 the ISA. mips_stack_argsize controls this. */
3930 for (offset
= 0, regnum
= V0_REGNUM
;
3931 offset
< TYPE_LENGTH (type
);
3932 offset
+= mips_stack_argsize (tdep
), regnum
++)
3934 int xfer
= mips_stack_argsize (tdep
);
3936 if (offset
+ xfer
> TYPE_LENGTH (type
))
3937 xfer
= TYPE_LENGTH (type
) - offset
;
3939 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3940 offset
, xfer
, regnum
);
3941 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3942 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3944 return RETURN_VALUE_REGISTER_CONVENTION
;
3948 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3952 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3953 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3955 struct value
**args
, CORE_ADDR sp
,
3956 int struct_return
, CORE_ADDR struct_addr
)
3962 int stack_offset
= 0;
3963 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3965 /* For shared libraries, "t9" needs to point at the function
3967 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3969 /* Set the return address register to point to the entry point of
3970 the program, where a breakpoint lies in wait. */
3971 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3973 /* First ensure that the stack and structure return address (if any)
3974 are properly aligned. The stack has to be at least 64-bit
3975 aligned even on 32-bit machines, because doubles must be 64-bit
3976 aligned. For n32 and n64, stack frames need to be 128-bit
3977 aligned, so we round to this widest known alignment. */
3979 sp
= align_down (sp
, 16);
3980 struct_addr
= align_down (struct_addr
, 16);
3982 /* Now make space on the stack for the args. */
3983 for (argnum
= 0; argnum
< nargs
; argnum
++)
3984 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3985 mips_stack_argsize (tdep
));
3986 sp
-= align_up (len
, 16);
3989 fprintf_unfiltered (gdb_stdlog
,
3990 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3991 paddr_nz (sp
), (long) align_up (len
, 16));
3993 /* Initialize the integer and float register pointers. */
3995 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3997 /* The struct_return pointer occupies the first parameter-passing reg. */
4001 fprintf_unfiltered (gdb_stdlog
,
4002 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4003 argreg
, paddr_nz (struct_addr
));
4004 write_register (argreg
++, struct_addr
);
4005 stack_offset
+= mips_stack_argsize (tdep
);
4008 /* Now load as many as possible of the first arguments into
4009 registers, and push the rest onto the stack. Loop thru args
4010 from first to last. */
4011 for (argnum
= 0; argnum
< nargs
; argnum
++)
4014 char valbuf
[MAX_REGISTER_SIZE
];
4015 struct value
*arg
= args
[argnum
];
4016 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4017 int len
= TYPE_LENGTH (arg_type
);
4018 enum type_code typecode
= TYPE_CODE (arg_type
);
4021 fprintf_unfiltered (gdb_stdlog
,
4022 "mips_o64_push_dummy_call: %d len=%d type=%d",
4023 argnum
+ 1, len
, (int) typecode
);
4025 val
= (char *) VALUE_CONTENTS (arg
);
4027 /* 32-bit ABIs always start floating point arguments in an
4028 even-numbered floating point register. Round the FP register
4029 up before the check to see if there are any FP registers
4030 left. O32/O64 targets also pass the FP in the integer
4031 registers so also round up normal registers. */
4032 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
4034 if ((float_argreg
& 1))
4038 /* Floating point arguments passed in registers have to be
4039 treated specially. On 32-bit architectures, doubles
4040 are passed in register pairs; the even register gets
4041 the low word, and the odd register gets the high word.
4042 On O32/O64, the first two floating point arguments are
4043 also copied to general registers, because MIPS16 functions
4044 don't use float registers for arguments. This duplication of
4045 arguments in general registers can't hurt non-MIPS16 functions
4046 because those registers are normally skipped. */
4048 if (fp_register_arg_p (typecode
, arg_type
)
4049 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4051 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4053 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4054 unsigned long regval
;
4056 /* Write the low word of the double to the even register(s). */
4057 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4059 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4060 float_argreg
, phex (regval
, 4));
4061 write_register (float_argreg
++, regval
);
4063 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4064 argreg
, phex (regval
, 4));
4065 write_register (argreg
++, regval
);
4067 /* Write the high word of the double to the odd register(s). */
4068 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4070 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4071 float_argreg
, phex (regval
, 4));
4072 write_register (float_argreg
++, regval
);
4075 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4076 argreg
, phex (regval
, 4));
4077 write_register (argreg
++, regval
);
4081 /* This is a floating point value that fits entirely
4082 in a single register. */
4083 /* On 32 bit ABI's the float_argreg is further adjusted
4084 above to ensure that it is even register aligned. */
4085 LONGEST regval
= extract_unsigned_integer (val
, len
);
4087 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4088 float_argreg
, phex (regval
, len
));
4089 write_register (float_argreg
++, regval
);
4090 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4091 registers for each argument. The below is (my
4092 guess) to ensure that the corresponding integer
4093 register has reserved the same space. */
4095 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4096 argreg
, phex (regval
, len
));
4097 write_register (argreg
, regval
);
4098 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
4100 /* Reserve space for the FP register. */
4101 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
4105 /* Copy the argument to general registers or the stack in
4106 register-sized pieces. Large arguments are split between
4107 registers and stack. */
4108 /* Note: structs whose size is not a multiple of
4109 mips_regsize() are treated specially: Irix cc passes them
4110 in registers where gcc sometimes puts them on the stack.
4111 For maximum compatibility, we will put them in both
4113 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
4114 && (len
% mips_saved_regsize (tdep
) != 0));
4115 /* Structures should be aligned to eight bytes (even arg registers)
4116 on MIPS_ABI_O32, if their first member has double precision. */
4117 if (mips_saved_regsize (tdep
) < 8
4118 && mips_type_needs_double_align (arg_type
))
4123 /* Note: Floating-point values that didn't fit into an FP
4124 register are only written to memory. */
4127 /* Remember if the argument was written to the stack. */
4128 int stack_used_p
= 0;
4129 int partial_len
= (len
< mips_saved_regsize (tdep
)
4130 ? len
: mips_saved_regsize (tdep
));
4133 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4136 /* Write this portion of the argument to the stack. */
4137 if (argreg
> MIPS_LAST_ARG_REGNUM
4139 || fp_register_arg_p (typecode
, arg_type
))
4141 /* Should shorter than int integer values be
4142 promoted to int before being stored? */
4143 int longword_offset
= 0;
4146 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4148 if (mips_stack_argsize (tdep
) == 8
4149 && (typecode
== TYPE_CODE_INT
4150 || typecode
== TYPE_CODE_PTR
4151 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4152 longword_offset
= mips_stack_argsize (tdep
) - len
;
4157 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4158 paddr_nz (stack_offset
));
4159 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4160 paddr_nz (longword_offset
));
4163 addr
= sp
+ stack_offset
+ longword_offset
;
4168 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4170 for (i
= 0; i
< partial_len
; i
++)
4172 fprintf_unfiltered (gdb_stdlog
, "%02x",
4176 write_memory (addr
, val
, partial_len
);
4179 /* Note!!! This is NOT an else clause. Odd sized
4180 structs may go thru BOTH paths. Floating point
4181 arguments will not. */
4182 /* Write this portion of the argument to a general
4183 purpose register. */
4184 if (argreg
<= MIPS_LAST_ARG_REGNUM
4185 && !fp_register_arg_p (typecode
, arg_type
))
4187 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4188 /* Value may need to be sign extended, because
4189 mips_regsize() != mips_saved_regsize(). */
4191 /* A non-floating-point argument being passed in a
4192 general register. If a struct or union, and if
4193 the remaining length is smaller than the register
4194 size, we have to adjust the register value on
4197 It does not seem to be necessary to do the
4198 same for integral types.
4200 Also don't do this adjustment on O64 binaries.
4202 cagney/2001-07-23: gdb/179: Also, GCC, when
4203 outputting LE O32 with sizeof (struct) <
4204 mips_saved_regsize(), generates a left shift as
4205 part of storing the argument in a register a
4206 register (the left shift isn't generated when
4207 sizeof (struct) >= mips_saved_regsize()). Since
4208 it is quite possible that this is GCC
4209 contradicting the LE/O32 ABI, GDB has not been
4210 adjusted to accommodate this. Either someone
4211 needs to demonstrate that the LE/O32 ABI
4212 specifies such a left shift OR this new ABI gets
4213 identified as such and GDB gets tweaked
4216 if (mips_saved_regsize (tdep
) < 8
4217 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4218 && partial_len
< mips_saved_regsize (tdep
)
4219 && (typecode
== TYPE_CODE_STRUCT
||
4220 typecode
== TYPE_CODE_UNION
))
4221 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
4225 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4228 mips_saved_regsize (tdep
)));
4229 write_register (argreg
, regval
);
4232 /* Prevent subsequent floating point arguments from
4233 being passed in floating point registers. */
4234 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4240 /* Compute the the offset into the stack at which we
4241 will copy the next parameter.
4243 In older ABIs, the caller reserved space for
4244 registers that contained arguments. This was loosely
4245 refered to as their "home". Consequently, space is
4246 always allocated. */
4248 stack_offset
+= align_up (partial_len
,
4249 mips_stack_argsize (tdep
));
4253 fprintf_unfiltered (gdb_stdlog
, "\n");
4256 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
4258 /* Return adjusted stack pointer. */
4263 mips_o64_extract_return_value (struct type
*valtype
,
4264 char regbuf
[], char *valbuf
)
4266 struct return_value_word lo
;
4267 struct return_value_word hi
;
4268 return_value_location (valtype
, &hi
, &lo
);
4270 memcpy (valbuf
+ lo
.buf_offset
,
4271 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4272 lo
.reg_offset
, lo
.len
);
4275 memcpy (valbuf
+ hi
.buf_offset
,
4276 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4277 hi
.reg_offset
, hi
.len
);
4281 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4283 char raw_buffer
[MAX_REGISTER_SIZE
];
4284 struct return_value_word lo
;
4285 struct return_value_word hi
;
4286 return_value_location (valtype
, &hi
, &lo
);
4288 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4289 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4290 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4291 raw_buffer
, register_size (current_gdbarch
,
4296 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4297 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4298 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4300 register_size (current_gdbarch
,
4306 mips_pop_frame (void)
4309 struct frame_info
*frame
= get_current_frame ();
4310 CORE_ADDR new_sp
= get_frame_base (frame
);
4311 mips_extra_func_info_t proc_desc
;
4312 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4314 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
4316 generic_pop_dummy_frame ();
4317 flush_cached_frames ();
4321 proc_desc
= get_frame_extra_info (frame
)->proc_desc
;
4322 write_register (mips_regnum (current_gdbarch
)->pc
,
4323 DEPRECATED_FRAME_SAVED_PC (frame
));
4324 mips_find_saved_regs (frame
);
4325 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
4326 if (regnum
!= SP_REGNUM
&& regnum
!= mips_regnum (current_gdbarch
)->pc
4327 && deprecated_get_frame_saved_regs (frame
)[regnum
])
4329 /* Floating point registers must not be sign extended, in case
4330 mips_saved_regsize() = 4 but sizeof (FP0_REGNUM) == 8. */
4332 if (mips_regnum (current_gdbarch
)->fp0
<= regnum
4333 && regnum
< mips_regnum (current_gdbarch
)->fp0
+ 32)
4334 write_register (regnum
,
4335 read_memory_unsigned_integer
4336 (deprecated_get_frame_saved_regs (frame
)[regnum
],
4337 mips_saved_regsize (tdep
)));
4339 write_register (regnum
,
4340 read_memory_integer (deprecated_get_frame_saved_regs
4342 mips_saved_regsize (tdep
)));
4345 write_register (SP_REGNUM
, new_sp
);
4346 flush_cached_frames ();
4348 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
4350 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
4352 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
4353 pi_ptr
!= NULL
; prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
4355 if (&pi_ptr
->info
== proc_desc
)
4360 error ("Can't locate dummy extra frame info\n");
4362 if (prev_ptr
!= NULL
)
4363 prev_ptr
->next
= pi_ptr
->next
;
4365 linked_proc_desc_table
= pi_ptr
->next
;
4369 write_register (mips_regnum (current_gdbarch
)->hi
,
4370 read_memory_integer ((new_sp
4371 - 2 * mips_saved_regsize (tdep
)),
4372 mips_saved_regsize (tdep
)));
4373 write_register (mips_regnum (current_gdbarch
)->lo
,
4374 read_memory_integer ((new_sp
4375 - 3 * mips_saved_regsize (tdep
)),
4376 mips_saved_regsize (tdep
)));
4377 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
4378 write_register (mips_regnum (current_gdbarch
)->fp_control_status
,
4379 read_memory_integer ((new_sp
4381 4 * mips_saved_regsize (tdep
)),
4382 mips_saved_regsize (tdep
)));
4386 /* Floating point register management.
4388 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4389 64bit operations, these early MIPS cpus treat fp register pairs
4390 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4391 registers and offer a compatibility mode that emulates the MIPS2 fp
4392 model. When operating in MIPS2 fp compat mode, later cpu's split
4393 double precision floats into two 32-bit chunks and store them in
4394 consecutive fp regs. To display 64-bit floats stored in this
4395 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4396 Throw in user-configurable endianness and you have a real mess.
4398 The way this works is:
4399 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4400 double-precision value will be split across two logical registers.
4401 The lower-numbered logical register will hold the low-order bits,
4402 regardless of the processor's endianness.
4403 - If we are on a 64-bit processor, and we are looking for a
4404 single-precision value, it will be in the low ordered bits
4405 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4406 save slot in memory.
4407 - If we are in 64-bit mode, everything is straightforward.
4409 Note that this code only deals with "live" registers at the top of the
4410 stack. We will attempt to deal with saved registers later, when
4411 the raw/cooked register interface is in place. (We need a general
4412 interface that can deal with dynamic saved register sizes -- fp
4413 regs could be 32 bits wide in one frame and 64 on the frame above
4416 static struct type
*
4417 mips_float_register_type (void)
4419 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4420 return builtin_type_ieee_single_big
;
4422 return builtin_type_ieee_single_little
;
4425 static struct type
*
4426 mips_double_register_type (void)
4428 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4429 return builtin_type_ieee_double_big
;
4431 return builtin_type_ieee_double_little
;
4434 /* Copy a 32-bit single-precision value from the current frame
4435 into rare_buffer. */
4438 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4441 int raw_size
= register_size (current_gdbarch
, regno
);
4442 char *raw_buffer
= alloca (raw_size
);
4444 if (!frame_register_read (frame
, regno
, raw_buffer
))
4445 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4448 /* We have a 64-bit value for this register. Find the low-order
4452 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4457 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4461 memcpy (rare_buffer
, raw_buffer
, 4);
4465 /* Copy a 64-bit double-precision value from the current frame into
4466 rare_buffer. This may include getting half of it from the next
4470 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4473 int raw_size
= register_size (current_gdbarch
, regno
);
4475 if (raw_size
== 8 && !mips2_fp_compat ())
4477 /* We have a 64-bit value for this register, and we should use
4479 if (!frame_register_read (frame
, regno
, rare_buffer
))
4480 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4484 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4485 internal_error (__FILE__
, __LINE__
,
4486 "mips_read_fp_register_double: bad access to "
4487 "odd-numbered FP register");
4489 /* mips_read_fp_register_single will find the correct 32 bits from
4491 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4493 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4494 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4498 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4499 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4505 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4507 { /* do values for FP (float) regs */
4509 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
4510 int inv1
, inv2
, namelen
;
4513 (char *) alloca (2 *
4514 register_size (current_gdbarch
,
4515 mips_regnum (current_gdbarch
)->fp0
));
4517 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4518 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4521 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4523 /* 4-byte registers: Print hex and floating. Also print even
4524 numbered registers as doubles. */
4525 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4526 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4528 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4531 fprintf_filtered (file
, " flt: ");
4533 fprintf_filtered (file
, " <invalid float> ");
4535 fprintf_filtered (file
, "%-17.9g", flt1
);
4537 if (regnum
% 2 == 0)
4539 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4540 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4543 fprintf_filtered (file
, " dbl: ");
4545 fprintf_filtered (file
, "<invalid double>");
4547 fprintf_filtered (file
, "%-24.17g", doub
);
4552 /* Eight byte registers: print each one as hex, float and double. */
4553 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4554 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4556 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4557 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4560 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4563 fprintf_filtered (file
, " flt: ");
4565 fprintf_filtered (file
, "<invalid float>");
4567 fprintf_filtered (file
, "%-17.9g", flt1
);
4569 fprintf_filtered (file
, " dbl: ");
4571 fprintf_filtered (file
, "<invalid double>");
4573 fprintf_filtered (file
, "%-24.17g", doub
);
4578 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4579 int regnum
, int all
)
4581 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4582 char raw_buffer
[MAX_REGISTER_SIZE
];
4585 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4587 mips_print_fp_register (file
, frame
, regnum
);
4591 /* Get the data in raw format. */
4592 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4594 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4598 fputs_filtered (REGISTER_NAME (regnum
), file
);
4600 /* The problem with printing numeric register names (r26, etc.) is that
4601 the user can't use them on input. Probably the best solution is to
4602 fix it so that either the numeric or the funky (a2, etc.) names
4603 are accepted on input. */
4604 if (regnum
< MIPS_NUMREGS
)
4605 fprintf_filtered (file
, "(r%d): ", regnum
);
4607 fprintf_filtered (file
, ": ");
4609 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4611 register_size (current_gdbarch
,
4612 regnum
) - register_size (current_gdbarch
, regnum
);
4616 print_scalar_formatted (raw_buffer
+ offset
,
4617 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4621 /* Replacement for generic do_registers_info.
4622 Print regs in pretty columns. */
4625 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4628 fprintf_filtered (file
, " ");
4629 mips_print_fp_register (file
, frame
, regnum
);
4630 fprintf_filtered (file
, "\n");
4635 /* Print a row's worth of GP (int) registers, with name labels above */
4638 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4641 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4642 /* do values for GP (int) regs */
4643 char raw_buffer
[MAX_REGISTER_SIZE
];
4644 int ncols
= (mips_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4648 /* For GP registers, we print a separate row of names above the vals */
4649 fprintf_filtered (file
, " ");
4650 for (col
= 0, regnum
= start_regnum
;
4651 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4653 if (*REGISTER_NAME (regnum
) == '\0')
4654 continue; /* unused register */
4655 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4657 break; /* end the row: reached FP register */
4658 fprintf_filtered (file
,
4659 mips_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4660 REGISTER_NAME (regnum
));
4663 /* print the R0 to R31 names */
4664 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4665 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4667 fprintf_filtered (file
, "\n ");
4669 /* now print the values in hex, 4 or 8 to the row */
4670 for (col
= 0, regnum
= start_regnum
;
4671 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4673 if (*REGISTER_NAME (regnum
) == '\0')
4674 continue; /* unused register */
4675 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4677 break; /* end row: reached FP register */
4678 /* OK: get the data in raw format. */
4679 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4680 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4681 /* pad small registers */
4683 byte
< (mips_regsize (current_gdbarch
)
4684 - register_size (current_gdbarch
, regnum
)); byte
++)
4685 printf_filtered (" ");
4686 /* Now print the register value in hex, endian order. */
4687 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4689 register_size (current_gdbarch
,
4690 regnum
) - register_size (current_gdbarch
, regnum
);
4691 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4692 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4694 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4696 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4697 fprintf_filtered (file
, " ");
4700 if (col
> 0) /* ie. if we actually printed anything... */
4701 fprintf_filtered (file
, "\n");
4706 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4709 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4710 struct frame_info
*frame
, int regnum
, int all
)
4712 if (regnum
!= -1) /* do one specified register */
4714 gdb_assert (regnum
>= NUM_REGS
);
4715 if (*(REGISTER_NAME (regnum
)) == '\0')
4716 error ("Not a valid register for the current processor type");
4718 mips_print_register (file
, frame
, regnum
, 0);
4719 fprintf_filtered (file
, "\n");
4722 /* do all (or most) registers */
4725 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4727 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4730 if (all
) /* true for "INFO ALL-REGISTERS" command */
4731 regnum
= print_fp_register_row (file
, frame
, regnum
);
4733 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4736 regnum
= print_gp_register_row (file
, frame
, regnum
);
4741 /* Is this a branch with a delay slot? */
4743 static int is_delayed (unsigned long);
4746 is_delayed (unsigned long insn
)
4749 for (i
= 0; i
< NUMOPCODES
; ++i
)
4750 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4751 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4753 return (i
< NUMOPCODES
4754 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4755 | INSN_COND_BRANCH_DELAY
4756 | INSN_COND_BRANCH_LIKELY
)));
4760 mips_step_skips_delay (CORE_ADDR pc
)
4762 char buf
[MIPS_INSTLEN
];
4764 /* There is no branch delay slot on MIPS16. */
4765 if (pc_is_mips16 (pc
))
4768 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4769 /* If error reading memory, guess that it is not a delayed branch. */
4771 return is_delayed ((unsigned long)
4772 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4776 /* Given PC at the function's start address, attempt to find the
4777 prologue end using SAL information. Return zero if the skip fails.
4779 A non-optimized prologue traditionally has one SAL for the function
4780 and a second for the function body. A single line function has
4781 them both pointing at the same line.
4783 An optimized prologue is similar but the prologue may contain
4784 instructions (SALs) from the instruction body. Need to skip those
4785 while not getting into the function body.
4787 The functions end point and an increasing SAL line are used as
4788 indicators of the prologue's endpoint.
4790 This code is based on the function refine_prologue_limit (versions
4791 found in both ia64 and ppc). */
4794 skip_prologue_using_sal (CORE_ADDR func_addr
)
4796 struct symtab_and_line prologue_sal
;
4800 /* Get an initial range for the function. */
4801 find_pc_partial_function (func_addr
, NULL
, &start_pc
, &end_pc
);
4802 start_pc
+= FUNCTION_START_OFFSET
;
4804 prologue_sal
= find_pc_line (start_pc
, 0);
4805 if (prologue_sal
.line
!= 0)
4807 while (prologue_sal
.end
< end_pc
)
4809 struct symtab_and_line sal
;
4811 sal
= find_pc_line (prologue_sal
.end
, 0);
4814 /* Assume that a consecutive SAL for the same (or larger)
4815 line mark the prologue -> body transition. */
4816 if (sal
.line
>= prologue_sal
.line
)
4818 /* The case in which compiler's optimizer/scheduler has
4819 moved instructions into the prologue. We look ahead in
4820 the function looking for address ranges whose
4821 corresponding line number is less the first one that we
4822 found for the function. This is more conservative then
4823 refine_prologue_limit which scans a large number of SALs
4824 looking for any in the prologue */
4828 return prologue_sal
.end
;
4831 /* Skip the PC past function prologue instructions (32-bit version).
4832 This is a helper function for mips_skip_prologue. */
4835 mips32_skip_prologue (CORE_ADDR pc
)
4839 int seen_sp_adjust
= 0;
4840 int load_immediate_bytes
= 0;
4842 /* Find an upper bound on the prologue. */
4843 end_pc
= skip_prologue_using_sal (pc
);
4845 end_pc
= pc
+ 100; /* Magic. */
4847 /* Skip the typical prologue instructions. These are the stack adjustment
4848 instruction and the instructions that save registers on the stack
4849 or in the gcc frame. */
4850 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4852 unsigned long high_word
;
4854 inst
= mips_fetch_instruction (pc
);
4855 high_word
= (inst
>> 16) & 0xffff;
4857 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4858 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4860 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4861 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4863 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4864 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4865 && (inst
& 0x001F0000)) /* reg != $zero */
4868 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4870 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4872 continue; /* reg != $zero */
4874 /* move $s8,$sp. With different versions of gas this will be either
4875 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4876 Accept any one of these. */
4877 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4880 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4882 else if (high_word
== 0x3c1c) /* lui $gp,n */
4884 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4886 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4887 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4889 /* The following instructions load $at or $t0 with an immediate
4890 value in preparation for a stack adjustment via
4891 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4892 a local variable, so we accept them only before a stack adjustment
4893 instruction was seen. */
4894 else if (!seen_sp_adjust
)
4896 if (high_word
== 0x3c01 || /* lui $at,n */
4897 high_word
== 0x3c08) /* lui $t0,n */
4899 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4902 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4903 high_word
== 0x3508 || /* ori $t0,$t0,n */
4904 high_word
== 0x3401 || /* ori $at,$zero,n */
4905 high_word
== 0x3408) /* ori $t0,$zero,n */
4907 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4917 /* In a frameless function, we might have incorrectly
4918 skipped some load immediate instructions. Undo the skipping
4919 if the load immediate was not followed by a stack adjustment. */
4920 if (load_immediate_bytes
&& !seen_sp_adjust
)
4921 pc
-= load_immediate_bytes
;
4925 /* Skip the PC past function prologue instructions (16-bit version).
4926 This is a helper function for mips_skip_prologue. */
4929 mips16_skip_prologue (CORE_ADDR pc
)
4932 int extend_bytes
= 0;
4933 int prev_extend_bytes
;
4935 /* Table of instructions likely to be found in a function prologue. */
4938 unsigned short inst
;
4939 unsigned short mask
;
4945 , /* addiu $sp,offset */
4948 , /* daddiu $sp,offset */
4951 , /* sw reg,n($sp) */
4954 , /* sd reg,n($sp) */
4957 , /* sw $ra,n($sp) */
4960 , /* sd $ra,n($sp) */
4966 , /* sw $a0-$a3,n($s1) */
4969 , /* move reg,$a0-$a3 */
4972 , /* entry pseudo-op */
4975 , /* addiu $s1,$sp,n */
4977 0, 0} /* end of table marker */
4980 /* Find an upper bound on the prologue. */
4981 end_pc
= skip_prologue_using_sal (pc
);
4983 end_pc
= pc
+ 100; /* Magic. */
4985 /* Skip the typical prologue instructions. These are the stack adjustment
4986 instruction and the instructions that save registers on the stack
4987 or in the gcc frame. */
4988 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4990 unsigned short inst
;
4993 inst
= mips_fetch_instruction (pc
);
4995 /* Normally we ignore an extend instruction. However, if it is
4996 not followed by a valid prologue instruction, we must adjust
4997 the pc back over the extend so that it won't be considered
4998 part of the prologue. */
4999 if ((inst
& 0xf800) == 0xf000) /* extend */
5001 extend_bytes
= MIPS16_INSTLEN
;
5004 prev_extend_bytes
= extend_bytes
;
5007 /* Check for other valid prologue instructions besides extend. */
5008 for (i
= 0; table
[i
].mask
!= 0; i
++)
5009 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
5011 if (table
[i
].mask
!= 0) /* it was in table? */
5012 continue; /* ignore it */
5016 /* Return the current pc, adjusted backwards by 2 if
5017 the previous instruction was an extend. */
5018 return pc
- prev_extend_bytes
;
5024 /* To skip prologues, I use this predicate. Returns either PC itself
5025 if the code at PC does not look like a function prologue; otherwise
5026 returns an address that (if we're lucky) follows the prologue. If
5027 LENIENT, then we must skip everything which is involved in setting
5028 up the frame (it's OK to skip more, just so long as we don't skip
5029 anything which might clobber the registers which are being saved.
5030 We must skip more in the case where part of the prologue is in the
5031 delay slot of a non-prologue instruction). */
5034 mips_skip_prologue (CORE_ADDR pc
)
5036 /* See if we can determine the end of the prologue via the symbol table.
5037 If so, then return either PC, or the PC after the prologue, whichever
5040 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
5042 if (post_prologue_pc
!= 0)
5043 return max (pc
, post_prologue_pc
);
5045 /* Can't determine prologue from the symbol table, need to examine
5048 if (pc_is_mips16 (pc
))
5049 return mips16_skip_prologue (pc
);
5051 return mips32_skip_prologue (pc
);
5054 /* Exported procedure: Is PC in the signal trampoline code */
5057 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
5059 if (sigtramp_address
== 0)
5061 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
5064 /* Root of all "set mips "/"show mips " commands. This will eventually be
5065 used for all MIPS-specific commands. */
5068 show_mips_command (char *args
, int from_tty
)
5070 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5074 set_mips_command (char *args
, int from_tty
)
5077 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5078 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5081 /* Commands to show/set the MIPS FPU type. */
5084 show_mipsfpu_command (char *args
, int from_tty
)
5087 switch (MIPS_FPU_TYPE
)
5089 case MIPS_FPU_SINGLE
:
5090 fpu
= "single-precision";
5092 case MIPS_FPU_DOUBLE
:
5093 fpu
= "double-precision";
5096 fpu
= "absent (none)";
5099 internal_error (__FILE__
, __LINE__
, "bad switch");
5101 if (mips_fpu_type_auto
)
5103 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5107 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5112 set_mipsfpu_command (char *args
, int from_tty
)
5115 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5116 show_mipsfpu_command (args
, from_tty
);
5120 set_mipsfpu_single_command (char *args
, int from_tty
)
5122 struct gdbarch_info info
;
5123 gdbarch_info_init (&info
);
5124 mips_fpu_type
= MIPS_FPU_SINGLE
;
5125 mips_fpu_type_auto
= 0;
5126 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5127 instead of relying on globals. Doing that would let generic code
5128 handle the search for this specific architecture. */
5129 if (!gdbarch_update_p (info
))
5130 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5134 set_mipsfpu_double_command (char *args
, int from_tty
)
5136 struct gdbarch_info info
;
5137 gdbarch_info_init (&info
);
5138 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5139 mips_fpu_type_auto
= 0;
5140 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5141 instead of relying on globals. Doing that would let generic code
5142 handle the search for this specific architecture. */
5143 if (!gdbarch_update_p (info
))
5144 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5148 set_mipsfpu_none_command (char *args
, int from_tty
)
5150 struct gdbarch_info info
;
5151 gdbarch_info_init (&info
);
5152 mips_fpu_type
= MIPS_FPU_NONE
;
5153 mips_fpu_type_auto
= 0;
5154 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5155 instead of relying on globals. Doing that would let generic code
5156 handle the search for this specific architecture. */
5157 if (!gdbarch_update_p (info
))
5158 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5162 set_mipsfpu_auto_command (char *args
, int from_tty
)
5164 mips_fpu_type_auto
= 1;
5167 /* Attempt to identify the particular processor model by reading the
5168 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5169 the relevant processor still exists (it dates back to '94) and
5170 secondly this is not the way to do this. The processor type should
5171 be set by forcing an architecture change. */
5174 deprecated_mips_set_processor_regs_hack (void)
5176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5179 prid
= read_register (PRID_REGNUM
);
5181 if ((prid
& ~0xf) == 0x700)
5182 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5185 /* Just like reinit_frame_cache, but with the right arguments to be
5186 callable as an sfunc. */
5189 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5190 struct cmd_list_element
*c
)
5192 reinit_frame_cache ();
5196 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5198 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5199 mips_extra_func_info_t proc_desc
;
5201 /* Search for the function containing this address. Set the low bit
5202 of the address when searching, in case we were given an even address
5203 that is the start of a 16-bit function. If we didn't do this,
5204 the search would fail because the symbol table says the function
5205 starts at an odd address, i.e. 1 byte past the given address. */
5206 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5207 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5209 /* Make an attempt to determine if this is a 16-bit function. If
5210 the procedure descriptor exists and the address therein is odd,
5211 it's definitely a 16-bit function. Otherwise, we have to just
5212 guess that if the address passed in is odd, it's 16-bits. */
5213 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5214 disassembler needs to be able to locally determine the ISA, and
5215 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5219 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5220 info
->mach
= bfd_mach_mips16
;
5224 if (pc_is_mips16 (memaddr
))
5225 info
->mach
= bfd_mach_mips16
;
5228 /* Round down the instruction address to the appropriate boundary. */
5229 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5231 /* Set the disassembler options. */
5232 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5234 /* Set up the disassembler info, so that we get the right
5235 register names from libopcodes. */
5236 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5237 info
->disassembler_options
= "gpr-names=n32";
5239 info
->disassembler_options
= "gpr-names=64";
5240 info
->flavour
= bfd_target_elf_flavour
;
5243 /* This string is not recognized explicitly by the disassembler,
5244 but it tells the disassembler to not try to guess the ABI from
5245 the bfd elf headers, such that, if the user overrides the ABI
5246 of a program linked as NewABI, the disassembly will follow the
5247 register naming conventions specified by the user. */
5248 info
->disassembler_options
= "gpr-names=32";
5250 /* Call the appropriate disassembler based on the target endian-ness. */
5251 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5252 return print_insn_big_mips (memaddr
, info
);
5254 return print_insn_little_mips (memaddr
, info
);
5257 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5258 counter value to determine whether a 16- or 32-bit breakpoint should be
5259 used. It returns a pointer to a string of bytes that encode a breakpoint
5260 instruction, stores the length of the string to *lenptr, and adjusts pc
5261 (if necessary) to point to the actual memory location where the
5262 breakpoint should be inserted. */
5264 static const unsigned char *
5265 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5267 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5269 if (pc_is_mips16 (*pcptr
))
5271 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5272 *pcptr
= unmake_mips16_addr (*pcptr
);
5273 *lenptr
= sizeof (mips16_big_breakpoint
);
5274 return mips16_big_breakpoint
;
5278 /* The IDT board uses an unusual breakpoint value, and
5279 sometimes gets confused when it sees the usual MIPS
5280 breakpoint instruction. */
5281 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5282 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5283 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5285 *lenptr
= sizeof (big_breakpoint
);
5287 if (strcmp (target_shortname
, "mips") == 0)
5288 return idt_big_breakpoint
;
5289 else if (strcmp (target_shortname
, "ddb") == 0
5290 || strcmp (target_shortname
, "pmon") == 0
5291 || strcmp (target_shortname
, "lsi") == 0)
5292 return pmon_big_breakpoint
;
5294 return big_breakpoint
;
5299 if (pc_is_mips16 (*pcptr
))
5301 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5302 *pcptr
= unmake_mips16_addr (*pcptr
);
5303 *lenptr
= sizeof (mips16_little_breakpoint
);
5304 return mips16_little_breakpoint
;
5308 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5309 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5310 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5312 *lenptr
= sizeof (little_breakpoint
);
5314 if (strcmp (target_shortname
, "mips") == 0)
5315 return idt_little_breakpoint
;
5316 else if (strcmp (target_shortname
, "ddb") == 0
5317 || strcmp (target_shortname
, "pmon") == 0
5318 || strcmp (target_shortname
, "lsi") == 0)
5319 return pmon_little_breakpoint
;
5321 return little_breakpoint
;
5326 /* If PC is in a mips16 call or return stub, return the address of the target
5327 PC, which is either the callee or the caller. There are several
5328 cases which must be handled:
5330 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5331 target PC is in $31 ($ra).
5332 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5333 and the target PC is in $2.
5334 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5335 before the jal instruction, this is effectively a call stub
5336 and the the target PC is in $2. Otherwise this is effectively
5337 a return stub and the target PC is in $18.
5339 See the source code for the stubs in gcc/config/mips/mips16.S for
5342 This function implements the SKIP_TRAMPOLINE_CODE macro.
5346 mips_skip_stub (CORE_ADDR pc
)
5349 CORE_ADDR start_addr
;
5351 /* Find the starting address and name of the function containing the PC. */
5352 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5355 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5356 target PC is in $31 ($ra). */
5357 if (strcmp (name
, "__mips16_ret_sf") == 0
5358 || strcmp (name
, "__mips16_ret_df") == 0)
5359 return read_signed_register (RA_REGNUM
);
5361 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5363 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5364 and the target PC is in $2. */
5365 if (name
[19] >= '0' && name
[19] <= '9')
5366 return read_signed_register (2);
5368 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5369 before the jal instruction, this is effectively a call stub
5370 and the the target PC is in $2. Otherwise this is effectively
5371 a return stub and the target PC is in $18. */
5372 else if (name
[19] == 's' || name
[19] == 'd')
5374 if (pc
== start_addr
)
5376 /* Check if the target of the stub is a compiler-generated
5377 stub. Such a stub for a function bar might have a name
5378 like __fn_stub_bar, and might look like this:
5383 la $1,bar (becomes a lui/addiu pair)
5385 So scan down to the lui/addi and extract the target
5386 address from those two instructions. */
5388 CORE_ADDR target_pc
= read_signed_register (2);
5392 /* See if the name of the target function is __fn_stub_*. */
5393 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5396 if (strncmp (name
, "__fn_stub_", 10) != 0
5397 && strcmp (name
, "etext") != 0
5398 && strcmp (name
, "_etext") != 0)
5401 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5402 The limit on the search is arbitrarily set to 20
5403 instructions. FIXME. */
5404 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5406 inst
= mips_fetch_instruction (target_pc
);
5407 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5408 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5409 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5410 return pc
| (inst
& 0xffff); /* low word */
5413 /* Couldn't find the lui/addui pair, so return stub address. */
5417 /* This is the 'return' part of a call stub. The return
5418 address is in $r18. */
5419 return read_signed_register (18);
5422 return 0; /* not a stub */
5426 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5427 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5430 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5432 CORE_ADDR start_addr
;
5434 /* Find the starting address of the function containing the PC. If the
5435 caller didn't give us a name, look it up at the same time. */
5436 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5440 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5442 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5443 if (name
[19] >= '0' && name
[19] <= '9')
5445 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5446 before the jal instruction, this is effectively a call stub. */
5447 else if (name
[19] == 's' || name
[19] == 'd')
5448 return pc
== start_addr
;
5451 return 0; /* not a stub */
5455 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5456 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5459 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5461 CORE_ADDR start_addr
;
5463 /* Find the starting address of the function containing the PC. */
5464 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5467 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5468 if (strcmp (name
, "__mips16_ret_sf") == 0
5469 || strcmp (name
, "__mips16_ret_df") == 0)
5472 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5473 i.e. after the jal instruction, this is effectively a return stub. */
5474 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5475 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5478 return 0; /* not a stub */
5482 /* Return non-zero if the PC is in a library helper function that should
5483 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5486 mips_ignore_helper (CORE_ADDR pc
)
5490 /* Find the starting address and name of the function containing the PC. */
5491 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5494 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5495 that we want to ignore. */
5496 return (strcmp (name
, "__mips16_ret_sf") == 0
5497 || strcmp (name
, "__mips16_ret_df") == 0);
5501 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5502 the register stored on the stack (32) is different to its real raw
5503 size (64). The below ensures that registers are fetched from the
5504 stack using their ABI size and then stored into the RAW_BUFFER
5505 using their raw size.
5507 The alternative to adding this function would be to add an ABI
5508 macro - REGISTER_STACK_SIZE(). */
5511 mips_get_saved_register (char *raw_buffer
,
5514 struct frame_info
*frame
,
5515 int regnum
, enum lval_type
*lvalp
)
5518 enum lval_type lvalx
;
5522 /* Always a pseudo. */
5523 gdb_assert (regnum
>= NUM_REGS
);
5525 /* Make certain that all needed parameters are present. */
5530 if (optimizedp
== NULL
)
5531 optimizedp
= &optimizedx
;
5533 if ((regnum
% NUM_REGS
) == SP_REGNUM
)
5534 /* The SP_REGNUM is special, its value is stored in saved_regs.
5535 In fact, it is so special that it can even only be fetched
5536 using a raw register number! Once this code as been converted
5537 to frame-unwind the problem goes away. */
5538 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5539 regnum
% NUM_REGS
, optimizedp
, lvalp
, addrp
,
5540 &realnumx
, raw_buffer
);
5542 /* Get it from the next frame. */
5543 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5544 regnum
, optimizedp
, lvalp
, addrp
,
5545 &realnumx
, raw_buffer
);
5548 /* Immediately after a function call, return the saved pc.
5549 Can't always go through the frames for this because on some machines
5550 the new frame is not set up until the new function executes
5551 some instructions. */
5554 mips_saved_pc_after_call (struct frame_info
*frame
)
5556 return read_signed_register (RA_REGNUM
);
5560 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5561 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5564 mips_stab_reg_to_regnum (int num
)
5567 if (num
>= 0 && num
< 32)
5569 else if (num
>= 38 && num
< 70)
5570 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5572 regnum
= mips_regnum (current_gdbarch
)->hi
;
5574 regnum
= mips_regnum (current_gdbarch
)->lo
;
5576 /* This will hopefully (eventually) provoke a warning. Should
5577 we be calling complaint() here? */
5578 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5579 return NUM_REGS
+ regnum
;
5583 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5584 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5587 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5590 if (num
>= 0 && num
< 32)
5592 else if (num
>= 32 && num
< 64)
5593 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5595 regnum
= mips_regnum (current_gdbarch
)->hi
;
5597 regnum
= mips_regnum (current_gdbarch
)->lo
;
5599 /* This will hopefully (eventually) provoke a warning. Should we
5600 be calling complaint() here? */
5601 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5602 return NUM_REGS
+ regnum
;
5606 mips_register_sim_regno (int regnum
)
5608 /* Only makes sense to supply raw registers. */
5609 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5610 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5611 decide if it is valid. Should instead define a standard sim/gdb
5612 register numbering scheme. */
5613 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5614 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5617 return LEGACY_SIM_REGNO_IGNORE
;
5621 /* Convert an integer into an address. By first converting the value
5622 into a pointer and then extracting it signed, the address is
5623 guarenteed to be correctly sign extended. */
5626 mips_integer_to_address (struct type
*type
, void *buf
)
5628 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5629 LONGEST val
= unpack_long (type
, buf
);
5630 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5631 return extract_signed_integer (tmp
,
5632 TYPE_LENGTH (builtin_type_void_data_ptr
));
5636 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5638 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5639 const char *name
= bfd_get_section_name (abfd
, sect
);
5641 if (*abip
!= MIPS_ABI_UNKNOWN
)
5644 if (strncmp (name
, ".mdebug.", 8) != 0)
5647 if (strcmp (name
, ".mdebug.abi32") == 0)
5648 *abip
= MIPS_ABI_O32
;
5649 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5650 *abip
= MIPS_ABI_N32
;
5651 else if (strcmp (name
, ".mdebug.abi64") == 0)
5652 *abip
= MIPS_ABI_N64
;
5653 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5654 *abip
= MIPS_ABI_O64
;
5655 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5656 *abip
= MIPS_ABI_EABI32
;
5657 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5658 *abip
= MIPS_ABI_EABI64
;
5660 warning ("unsupported ABI %s.", name
+ 8);
5663 static enum mips_abi
5664 global_mips_abi (void)
5668 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5669 if (mips_abi_strings
[i
] == mips_abi_string
)
5670 return (enum mips_abi
) i
;
5672 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5675 static struct gdbarch
*
5676 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5678 struct gdbarch
*gdbarch
;
5679 struct gdbarch_tdep
*tdep
;
5681 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5683 enum mips_fpu_type fpu_type
;
5685 /* First of all, extract the elf_flags, if available. */
5686 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5687 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5688 else if (arches
!= NULL
)
5689 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5693 fprintf_unfiltered (gdb_stdlog
,
5694 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5696 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5697 switch ((elf_flags
& EF_MIPS_ABI
))
5699 case E_MIPS_ABI_O32
:
5700 found_abi
= MIPS_ABI_O32
;
5702 case E_MIPS_ABI_O64
:
5703 found_abi
= MIPS_ABI_O64
;
5705 case E_MIPS_ABI_EABI32
:
5706 found_abi
= MIPS_ABI_EABI32
;
5708 case E_MIPS_ABI_EABI64
:
5709 found_abi
= MIPS_ABI_EABI64
;
5712 if ((elf_flags
& EF_MIPS_ABI2
))
5713 found_abi
= MIPS_ABI_N32
;
5715 found_abi
= MIPS_ABI_UNKNOWN
;
5719 /* GCC creates a pseudo-section whose name describes the ABI. */
5720 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5721 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5723 /* If we have no usefu BFD information, use the ABI from the last
5724 MIPS architecture (if there is one). */
5725 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5726 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5728 /* Try the architecture for any hint of the correct ABI. */
5729 if (found_abi
== MIPS_ABI_UNKNOWN
5730 && info
.bfd_arch_info
!= NULL
5731 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5733 switch (info
.bfd_arch_info
->mach
)
5735 case bfd_mach_mips3900
:
5736 found_abi
= MIPS_ABI_EABI32
;
5738 case bfd_mach_mips4100
:
5739 case bfd_mach_mips5000
:
5740 found_abi
= MIPS_ABI_EABI64
;
5742 case bfd_mach_mips8000
:
5743 case bfd_mach_mips10000
:
5744 /* On Irix, ELF64 executables use the N64 ABI. The
5745 pseudo-sections which describe the ABI aren't present
5746 on IRIX. (Even for executables created by gcc.) */
5747 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5748 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5749 found_abi
= MIPS_ABI_N64
;
5751 found_abi
= MIPS_ABI_N32
;
5757 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5760 /* What has the user specified from the command line? */
5761 wanted_abi
= global_mips_abi ();
5763 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5766 /* Now that we have found what the ABI for this binary would be,
5767 check whether the user is overriding it. */
5768 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5769 mips_abi
= wanted_abi
;
5770 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5771 mips_abi
= found_abi
;
5773 mips_abi
= MIPS_ABI_O32
;
5775 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5778 /* Also used when doing an architecture lookup. */
5780 fprintf_unfiltered (gdb_stdlog
,
5781 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5782 mips64_transfers_32bit_regs_p
);
5784 /* Determine the MIPS FPU type. */
5785 if (!mips_fpu_type_auto
)
5786 fpu_type
= mips_fpu_type
;
5787 else if (info
.bfd_arch_info
!= NULL
5788 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5789 switch (info
.bfd_arch_info
->mach
)
5791 case bfd_mach_mips3900
:
5792 case bfd_mach_mips4100
:
5793 case bfd_mach_mips4111
:
5794 fpu_type
= MIPS_FPU_NONE
;
5796 case bfd_mach_mips4650
:
5797 fpu_type
= MIPS_FPU_SINGLE
;
5800 fpu_type
= MIPS_FPU_DOUBLE
;
5803 else if (arches
!= NULL
)
5804 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5806 fpu_type
= MIPS_FPU_DOUBLE
;
5808 fprintf_unfiltered (gdb_stdlog
,
5809 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5811 /* try to find a pre-existing architecture */
5812 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5814 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5816 /* MIPS needs to be pedantic about which ABI the object is
5818 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5820 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5822 /* Need to be pedantic about which register virtual size is
5824 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5825 != mips64_transfers_32bit_regs_p
)
5827 /* Be pedantic about which FPU is selected. */
5828 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5830 return arches
->gdbarch
;
5833 /* Need a new architecture. Fill in a target specific vector. */
5834 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5835 gdbarch
= gdbarch_alloc (&info
, tdep
);
5836 tdep
->elf_flags
= elf_flags
;
5837 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5838 tdep
->found_abi
= found_abi
;
5839 tdep
->mips_abi
= mips_abi
;
5840 tdep
->mips_fpu_type
= fpu_type
;
5842 /* Initially set everything according to the default ABI/ISA. */
5843 set_gdbarch_short_bit (gdbarch
, 16);
5844 set_gdbarch_int_bit (gdbarch
, 32);
5845 set_gdbarch_float_bit (gdbarch
, 32);
5846 set_gdbarch_double_bit (gdbarch
, 64);
5847 set_gdbarch_long_double_bit (gdbarch
, 64);
5848 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5849 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5850 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5852 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5853 mips_elf_make_msymbol_special
);
5855 /* Fill in the OS dependant register numbers and names. */
5857 const char **reg_names
;
5858 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5859 struct mips_regnum
);
5860 if (info
.osabi
== GDB_OSABI_IRIX
)
5865 regnum
->badvaddr
= 66;
5868 regnum
->fp_control_status
= 69;
5869 regnum
->fp_implementation_revision
= 70;
5871 reg_names
= mips_irix_reg_names
;
5875 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5876 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5877 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5878 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5879 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5880 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5881 regnum
->fp_control_status
= 70;
5882 regnum
->fp_implementation_revision
= 71;
5884 if (info
.bfd_arch_info
!= NULL
5885 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5886 reg_names
= mips_tx39_reg_names
;
5888 reg_names
= mips_generic_reg_names
;
5890 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5891 replaced by read_pc? */
5892 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
);
5893 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5894 set_gdbarch_num_regs (gdbarch
, num_regs
);
5895 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5896 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5897 tdep
->mips_processor_reg_names
= reg_names
;
5898 tdep
->regnum
= regnum
;
5904 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5905 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5906 tdep
->mips_default_saved_regsize
= 4;
5907 tdep
->mips_default_stack_argsize
= 4;
5908 tdep
->mips_fp_register_double
= 0;
5909 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5910 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5911 tdep
->default_mask_address_p
= 0;
5912 set_gdbarch_long_bit (gdbarch
, 32);
5913 set_gdbarch_ptr_bit (gdbarch
, 32);
5914 set_gdbarch_long_long_bit (gdbarch
, 64);
5917 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5918 set_gdbarch_deprecated_store_return_value (gdbarch
,
5919 mips_o64_store_return_value
);
5920 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5921 mips_o64_extract_return_value
);
5922 tdep
->mips_default_saved_regsize
= 8;
5923 tdep
->mips_default_stack_argsize
= 8;
5924 tdep
->mips_fp_register_double
= 1;
5925 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5926 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5927 tdep
->default_mask_address_p
= 0;
5928 set_gdbarch_long_bit (gdbarch
, 32);
5929 set_gdbarch_ptr_bit (gdbarch
, 32);
5930 set_gdbarch_long_long_bit (gdbarch
, 64);
5931 set_gdbarch_use_struct_convention (gdbarch
,
5932 always_use_struct_convention
);
5934 case MIPS_ABI_EABI32
:
5935 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5936 set_gdbarch_deprecated_store_return_value (gdbarch
,
5937 mips_eabi_store_return_value
);
5938 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5939 mips_eabi_extract_return_value
);
5940 tdep
->mips_default_saved_regsize
= 4;
5941 tdep
->mips_default_stack_argsize
= 4;
5942 tdep
->mips_fp_register_double
= 0;
5943 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5944 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5945 tdep
->default_mask_address_p
= 0;
5946 set_gdbarch_long_bit (gdbarch
, 32);
5947 set_gdbarch_ptr_bit (gdbarch
, 32);
5948 set_gdbarch_long_long_bit (gdbarch
, 64);
5949 set_gdbarch_deprecated_reg_struct_has_addr
5950 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5951 set_gdbarch_use_struct_convention (gdbarch
,
5952 mips_eabi_use_struct_convention
);
5954 case MIPS_ABI_EABI64
:
5955 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5956 set_gdbarch_deprecated_store_return_value (gdbarch
,
5957 mips_eabi_store_return_value
);
5958 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5959 mips_eabi_extract_return_value
);
5960 tdep
->mips_default_saved_regsize
= 8;
5961 tdep
->mips_default_stack_argsize
= 8;
5962 tdep
->mips_fp_register_double
= 1;
5963 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5964 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5965 tdep
->default_mask_address_p
= 0;
5966 set_gdbarch_long_bit (gdbarch
, 64);
5967 set_gdbarch_ptr_bit (gdbarch
, 64);
5968 set_gdbarch_long_long_bit (gdbarch
, 64);
5969 set_gdbarch_deprecated_reg_struct_has_addr
5970 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5971 set_gdbarch_use_struct_convention (gdbarch
,
5972 mips_eabi_use_struct_convention
);
5975 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5976 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5977 tdep
->mips_default_saved_regsize
= 8;
5978 tdep
->mips_default_stack_argsize
= 8;
5979 tdep
->mips_fp_register_double
= 1;
5980 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5981 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5982 tdep
->default_mask_address_p
= 0;
5983 set_gdbarch_long_bit (gdbarch
, 32);
5984 set_gdbarch_ptr_bit (gdbarch
, 32);
5985 set_gdbarch_long_long_bit (gdbarch
, 64);
5988 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5989 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5990 tdep
->mips_default_saved_regsize
= 8;
5991 tdep
->mips_default_stack_argsize
= 8;
5992 tdep
->mips_fp_register_double
= 1;
5993 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5994 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5995 tdep
->default_mask_address_p
= 0;
5996 set_gdbarch_long_bit (gdbarch
, 64);
5997 set_gdbarch_ptr_bit (gdbarch
, 64);
5998 set_gdbarch_long_long_bit (gdbarch
, 64);
6001 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
6004 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6005 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6008 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6009 flag in object files because to do so would make it impossible to
6010 link with libraries compiled without "-gp32". This is
6011 unnecessarily restrictive.
6013 We could solve this problem by adding "-gp32" multilibs to gcc,
6014 but to set this flag before gcc is built with such multilibs will
6015 break too many systems.''
6017 But even more unhelpfully, the default linker output target for
6018 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6019 for 64-bit programs - you need to change the ABI to change this,
6020 and not all gcc targets support that currently. Therefore using
6021 this flag to detect 32-bit mode would do the wrong thing given
6022 the current gcc - it would make GDB treat these 64-bit programs
6023 as 32-bit programs by default. */
6025 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6026 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6027 set_gdbarch_deprecated_target_read_fp (gdbarch
, mips_read_sp
); /* Draft FRAME base. */
6028 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6030 /* Add/remove bits from an address. The MIPS needs be careful to
6031 ensure that all 32 bit addresses are sign extended to 64 bits. */
6032 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6034 /* There's a mess in stack frame creation. See comments in
6035 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
6036 set_gdbarch_deprecated_init_frame_pc_first (gdbarch
,
6037 mips_init_frame_pc_first
);
6039 /* Map debug register numbers onto internal register numbers. */
6040 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6041 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6042 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6043 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
6044 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6045 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6046 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6047 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6049 /* Initialize a frame */
6050 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch
,
6051 mips_find_saved_regs
);
6052 set_gdbarch_deprecated_init_extra_frame_info (gdbarch
,
6053 mips_init_extra_frame_info
);
6055 /* MIPS version of CALL_DUMMY */
6057 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6058 replaced by a command, and all targets will default to on stack
6059 (regardless of the stack's execute status). */
6060 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6061 set_gdbarch_deprecated_pop_frame (gdbarch
, mips_pop_frame
);
6062 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6063 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch
,
6064 generic_save_dummy_frame_tos
);
6066 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6067 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6068 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6070 set_gdbarch_deprecated_frame_chain (gdbarch
, mips_frame_chain
);
6071 set_gdbarch_frameless_function_invocation (gdbarch
,
6072 generic_frameless_function_invocation_not
);
6073 set_gdbarch_deprecated_frame_saved_pc (gdbarch
, mips_frame_saved_pc
);
6074 set_gdbarch_frame_args_skip (gdbarch
, 0);
6076 set_gdbarch_deprecated_get_saved_register (gdbarch
,
6077 mips_get_saved_register
);
6079 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6080 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6082 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6083 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
,
6084 mips_saved_pc_after_call
);
6086 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6087 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6088 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6090 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6092 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6093 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
6095 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6097 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6098 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6099 need to all be folded into the target vector. Since they are
6100 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6101 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6103 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6105 /* Hook in OS ABI-specific overrides, if they have been registered. */
6106 gdbarch_init_osabi (info
, gdbarch
);
6108 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6110 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6111 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6117 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6119 struct gdbarch_info info
;
6121 /* Force the architecture to update, and (if it's a MIPS architecture)
6122 mips_gdbarch_init will take care of the rest. */
6123 gdbarch_info_init (&info
);
6124 gdbarch_update_p (info
);
6127 /* Print out which MIPS ABI is in use. */
6130 show_mips_abi (char *ignore_args
, int from_tty
)
6132 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6134 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6137 enum mips_abi global_abi
= global_mips_abi ();
6138 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6139 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6141 if (global_abi
== MIPS_ABI_UNKNOWN
)
6143 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6145 else if (global_abi
== actual_abi
)
6147 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6151 /* Probably shouldn't happen... */
6153 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6154 actual_abi_str
, mips_abi_strings
[global_abi
]);
6160 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6162 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6166 int ef_mips_32bitmode
;
6167 /* determine the ISA */
6168 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6186 /* determine the size of a pointer */
6187 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6188 fprintf_unfiltered (file
,
6189 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6191 fprintf_unfiltered (file
,
6192 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6194 fprintf_unfiltered (file
,
6195 "mips_dump_tdep: ef_mips_arch = %d\n",
6197 fprintf_unfiltered (file
,
6198 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6199 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6200 fprintf_unfiltered (file
,
6201 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6202 mips_mask_address_p (tdep
),
6203 tdep
->default_mask_address_p
);
6205 fprintf_unfiltered (file
,
6206 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6207 FP_REGISTER_DOUBLE
);
6208 fprintf_unfiltered (file
,
6209 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6210 MIPS_DEFAULT_FPU_TYPE
,
6211 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6212 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6213 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6215 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6216 fprintf_unfiltered (file
,
6217 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6219 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6220 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6221 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6223 fprintf_unfiltered (file
,
6224 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6225 FP_REGISTER_DOUBLE
);
6226 fprintf_unfiltered (file
,
6227 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6228 mips_stack_argsize (tdep
));
6229 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6230 fprintf_unfiltered (file
,
6231 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6232 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6233 fprintf_unfiltered (file
,
6234 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6235 XSTRING (ATTACH_DETACH
));
6236 fprintf_unfiltered (file
,
6237 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6238 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6239 fprintf_unfiltered (file
,
6240 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6241 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6242 fprintf_unfiltered (file
,
6243 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6244 FIRST_EMBED_REGNUM
);
6245 fprintf_unfiltered (file
,
6246 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6247 XSTRING (IGNORE_HELPER_CALL (PC
)));
6248 fprintf_unfiltered (file
,
6249 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6250 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6251 fprintf_unfiltered (file
,
6252 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6253 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6254 fprintf_unfiltered (file
,
6255 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6257 #ifdef MACHINE_CPROC_FP_OFFSET
6258 fprintf_unfiltered (file
,
6259 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6260 MACHINE_CPROC_FP_OFFSET
);
6262 #ifdef MACHINE_CPROC_PC_OFFSET
6263 fprintf_unfiltered (file
,
6264 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6265 MACHINE_CPROC_PC_OFFSET
);
6267 #ifdef MACHINE_CPROC_SP_OFFSET
6268 fprintf_unfiltered (file
,
6269 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6270 MACHINE_CPROC_SP_OFFSET
);
6272 fprintf_unfiltered (file
,
6273 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6275 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6276 fprintf_unfiltered (file
,
6277 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6278 fprintf_unfiltered (file
,
6279 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6280 fprintf_unfiltered (file
,
6281 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6282 MIPS_LAST_ARG_REGNUM
,
6283 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6284 fprintf_unfiltered (file
,
6285 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6286 fprintf_unfiltered (file
,
6287 "mips_dump_tdep: mips_saved_regsize() = %d\n",
6288 mips_saved_regsize (tdep
));
6289 fprintf_unfiltered (file
,
6290 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6291 fprintf_unfiltered (file
,
6292 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6293 fprintf_unfiltered (file
,
6294 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6295 fprintf_unfiltered (file
,
6296 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6297 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6298 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6299 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6300 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6301 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6302 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6303 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6304 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6305 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6306 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6307 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6309 fprintf_unfiltered (file
,
6310 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6313 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6316 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6318 fprintf_unfiltered (file
,
6319 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6320 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6321 fprintf_unfiltered (file
,
6322 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6323 fprintf_unfiltered (file
,
6324 "mips_dump_tdep: SIGFRAME_BASE = %d\n", SIGFRAME_BASE
);
6325 fprintf_unfiltered (file
,
6326 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6327 SIGFRAME_FPREGSAVE_OFF
);
6328 fprintf_unfiltered (file
,
6329 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6331 fprintf_unfiltered (file
,
6332 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6333 SIGFRAME_REGSAVE_OFF
);
6334 fprintf_unfiltered (file
,
6335 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6336 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6337 fprintf_unfiltered (file
,
6338 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6339 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6340 fprintf_unfiltered (file
,
6341 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6342 SOFTWARE_SINGLE_STEP_P ());
6343 fprintf_unfiltered (file
,
6344 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6345 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6346 #ifdef STACK_END_ADDR
6347 fprintf_unfiltered (file
,
6348 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6351 fprintf_unfiltered (file
,
6352 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6353 XSTRING (STEP_SKIPS_DELAY (PC
)));
6354 fprintf_unfiltered (file
,
6355 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6356 STEP_SKIPS_DELAY_P
);
6357 fprintf_unfiltered (file
,
6358 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6359 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6360 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6361 fprintf_unfiltered (file
,
6362 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6363 fprintf_unfiltered (file
,
6364 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6365 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6366 (TYPE
, CNT
, OTHERTYPE
)));
6367 fprintf_unfiltered (file
,
6368 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6369 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6371 fprintf_unfiltered (file
,
6372 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6373 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6376 fprintf_unfiltered (file
,
6377 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6379 #ifdef TRACE_FLAVOR_SIZE
6380 fprintf_unfiltered (file
,
6381 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6385 fprintf_unfiltered (file
,
6386 "mips_dump_tdep: TRACE_SET # %s\n",
6387 XSTRING (TRACE_SET (X
, STATE
)));
6389 #ifdef UNUSED_REGNUM
6390 fprintf_unfiltered (file
,
6391 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6393 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6394 fprintf_unfiltered (file
,
6395 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6396 (long) VM_MIN_ADDRESS
);
6397 fprintf_unfiltered (file
,
6398 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6399 fprintf_unfiltered (file
,
6400 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_
);
6403 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6406 _initialize_mips_tdep (void)
6408 static struct cmd_list_element
*mipsfpulist
= NULL
;
6409 struct cmd_list_element
*c
;
6411 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6412 if (MIPS_ABI_LAST
+ 1
6413 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6414 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6416 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6418 /* Add root prefix command for all "set mips"/"show mips" commands */
6419 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6420 "Various MIPS specific commands.",
6421 &setmipscmdlist
, "set mips ", 0, &setlist
);
6423 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6424 "Various MIPS specific commands.",
6425 &showmipscmdlist
, "show mips ", 0, &showlist
);
6427 /* Allow the user to override the saved register size. */
6428 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6431 &mips_saved_regsize_string
, "\
6432 Set size of general purpose registers saved on the stack.\n\
6433 This option can be set to one of:\n\
6434 32 - Force GDB to treat saved GP registers as 32-bit\n\
6435 64 - Force GDB to treat saved GP registers as 64-bit\n\
6436 auto - Allow GDB to use the target's default setting or autodetect the\n\
6437 saved GP register size from information contained in the executable.\n\
6438 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6440 /* Allow the user to override the argument stack size. */
6441 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6444 &mips_stack_argsize_string
, "\
6445 Set the amount of stack space reserved for each argument.\n\
6446 This option can be set to one of:\n\
6447 32 - Force GDB to allocate 32-bit chunks per argument\n\
6448 64 - Force GDB to allocate 64-bit chunks per argument\n\
6449 auto - Allow GDB to determine the correct setting from the current\n\
6450 target and executable (default)", &setmipscmdlist
), &showmipscmdlist
);
6452 /* Allow the user to override the ABI. */
6453 c
= add_set_enum_cmd
6454 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6455 "Set the ABI used by this program.\n"
6456 "This option can be set to one of:\n"
6457 " auto - the default ABI associated with the current binary\n"
6459 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6460 set_cmd_sfunc (c
, mips_abi_update
);
6461 add_cmd ("abi", class_obscure
, show_mips_abi
,
6462 "Show ABI in use by MIPS target", &showmipscmdlist
);
6464 /* Let the user turn off floating point and set the fence post for
6465 heuristic_proc_start. */
6467 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6468 "Set use of MIPS floating-point coprocessor.",
6469 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6470 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6471 "Select single-precision MIPS floating-point coprocessor.",
6473 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6474 "Select double-precision MIPS floating-point coprocessor.",
6476 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6477 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6478 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6479 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6480 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6481 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6482 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6483 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6484 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6485 "Select MIPS floating-point coprocessor automatically.",
6487 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6488 "Show current use of MIPS floating-point coprocessor target.",
6491 /* We really would like to have both "0" and "unlimited" work, but
6492 command.c doesn't deal with that. So make it a var_zinteger
6493 because the user can always use "999999" or some such for unlimited. */
6494 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6495 (char *) &heuristic_fence_post
, "\
6496 Set the distance searched for the start of a function.\n\
6497 If you are debugging a stripped executable, GDB needs to search through the\n\
6498 program for the start of a function. This command sets the distance of the\n\
6499 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6500 /* We need to throw away the frame cache when we set this, since it
6501 might change our ability to get backtraces. */
6502 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6503 add_show_from_set (c
, &showlist
);
6505 /* Allow the user to control whether the upper bits of 64-bit
6506 addresses should be zeroed. */
6507 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6508 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6509 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6510 allow GDB to determine the correct value.\n", "\
6511 Show zeroing of upper 32 bits of 64-bit addresses.",
6512 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6514 /* Allow the user to control the size of 32 bit registers within the
6515 raw remote packet. */
6516 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6517 var_boolean
, &mips64_transfers_32bit_regs_p
, "\
6518 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6519 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6520 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6521 64 bits for others. Use \"off\" to disable compatibility mode", "\
6522 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6523 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6524 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6525 64 bits for others. Use \"off\" to disable compatibility mode", set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6527 /* Debug this files internals. */
6528 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6529 &mips_debug
, "Set mips debugging.\n\
6530 When non-zero, mips specific debugging is enabled.", &setdebuglist
), &showdebuglist
);