1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
41 /* FIXME: Put this declaration in frame.h. */
42 extern struct obstack frame_cache_obstack
;
45 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
48 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
50 static void mips_print_register
PARAMS ((int, int));
52 static mips_extra_func_info_t
53 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
55 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
57 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
59 static void mips_set_fpu_command
PARAMS ((char *, int,
60 struct cmd_list_element
*));
62 static void mips_show_fpu_command
PARAMS ((char *, int,
63 struct cmd_list_element
*));
65 void mips_set_processor_type_command
PARAMS ((char *, int));
67 int mips_set_processor_type
PARAMS ((char *));
69 static void mips_show_processor_type_command
PARAMS ((char *, int));
71 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
72 struct cmd_list_element
*));
74 static mips_extra_func_info_t
75 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
*next_frame
));
77 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
78 mips_extra_func_info_t proc_desc
));
80 /* This value is the model of MIPS in use. It is derived from the value
81 of the PrID register. */
83 char *mips_processor_type
;
85 char *tmp_mips_processor_type
;
87 /* Some MIPS boards don't support floating point, so we permit the
88 user to turn it off. */
90 enum mips_fpu_type mips_fpu
;
92 static char *mips_fpu_string
;
94 /* A set of original names, to be used when restoring back to generic
95 registers from a specific set. */
97 char *mips_generic_reg_names
[] = REGISTER_NAMES
;
99 /* Names of IDT R3041 registers. */
101 char *mips_r3041_reg_names
[] = {
102 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
103 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
104 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
105 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
106 "sr", "lo", "hi", "bad", "cause","pc",
107 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
108 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
109 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
110 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
111 "fsr", "fir", "fp", "",
112 "", "", "bus", "ccfg", "", "", "", "",
113 "", "", "port", "cmp", "", "", "epc", "prid",
116 /* Names of IDT R3051 registers. */
118 char *mips_r3051_reg_names
[] = {
119 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
120 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
121 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
122 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
123 "sr", "lo", "hi", "bad", "cause","pc",
124 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
125 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
126 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
127 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
128 "fsr", "fir", "fp", "",
129 "inx", "rand", "elo", "", "ctxt", "", "", "",
130 "", "", "ehi", "", "", "", "epc", "prid",
133 /* Names of IDT R3081 registers. */
135 char *mips_r3081_reg_names
[] = {
136 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
137 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
138 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
139 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
140 "sr", "lo", "hi", "bad", "cause","pc",
141 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
142 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
143 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
144 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
145 "fsr", "fir", "fp", "",
146 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
147 "", "", "ehi", "", "", "", "epc", "prid",
150 /* Names of LSI 33k registers. */
152 char *mips_lsi33k_reg_names
[] = {
153 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
154 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
155 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
156 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
157 "epc", "hi", "lo", "sr", "cause","badvaddr",
158 "dcic", "bpc", "bda", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "",
163 "", "", "", "", "", "", "", "",
164 "", "", "", "", "", "", "", "",
170 } mips_processor_type_table
[] = {
171 { "generic", mips_generic_reg_names
},
172 { "r3041", mips_r3041_reg_names
},
173 { "r3051", mips_r3051_reg_names
},
174 { "r3071", mips_r3081_reg_names
},
175 { "r3081", mips_r3081_reg_names
},
176 { "lsi33k", mips_lsi33k_reg_names
},
180 /* Table to translate MIPS16 register field to actual register number. */
181 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
183 /* Heuristic_proc_start may hunt through the text section for a long
184 time across a 2400 baud serial line. Allows the user to limit this
187 static unsigned int heuristic_fence_post
= 0;
189 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
190 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
191 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
192 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
193 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
194 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
195 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
196 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
197 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
198 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
199 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
200 #define _PROC_MAGIC_ 0x0F0F0F0F
201 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
202 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
204 struct linked_proc_info
206 struct mips_extra_func_info info
;
207 struct linked_proc_info
*next
;
208 } *linked_proc_desc_table
= NULL
;
211 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
214 pc_is_mips16 (bfd_vma memaddr
)
216 struct minimal_symbol
*sym
;
218 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
219 if (IS_MIPS16_ADDR (memaddr
))
222 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
223 the high bit of the info field. Use this to decide if the function is
224 MIPS16 or normal MIPS. */
225 sym
= lookup_minimal_symbol_by_pc (memaddr
);
227 return MSYMBOL_IS_SPECIAL (sym
);
233 /* This returns the PC of the first inst after the prologue. If we can't
234 find the prologue, then return 0. */
237 after_prologue (pc
, proc_desc
)
239 mips_extra_func_info_t proc_desc
;
241 struct symtab_and_line sal
;
242 CORE_ADDR func_addr
, func_end
;
245 proc_desc
= find_proc_desc (pc
, NULL
);
249 /* If function is frameless, then we need to do it the hard way. I
250 strongly suspect that frameless always means prologueless... */
251 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
252 && PROC_FRAME_OFFSET (proc_desc
) == 0)
256 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
257 return 0; /* Unknown */
259 sal
= find_pc_line (func_addr
, 0);
261 if (sal
.end
< func_end
)
264 /* The line after the prologue is after the end of the function. In this
265 case, tell the caller to find the prologue the hard way. */
270 /* Decode a MIPS32 instruction that saves a register in the stack, and
271 set the appropriate bit in the general register mask or float register mask
272 to indicate which register is saved. This is a helper function
273 for mips_find_saved_regs. */
276 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
278 unsigned long *gen_mask
;
279 unsigned long *float_mask
;
283 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
284 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
285 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
287 /* It might be possible to use the instruction to
288 find the offset, rather than the code below which
289 is based on things being in a certain order in the
290 frame, but figuring out what the instruction's offset
291 is relative to might be a little tricky. */
292 reg
= (inst
& 0x001f0000) >> 16;
293 *gen_mask
|= (1 << reg
);
295 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
296 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
297 || (inst
& 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */
300 reg
= ((inst
& 0x001f0000) >> 16);
301 *float_mask
|= (1 << reg
);
305 /* Decode a MIPS16 instruction that saves a register in the stack, and
306 set the appropriate bit in the general register or float register mask
307 to indicate which register is saved. This is a helper function
308 for mips_find_saved_regs. */
311 mips16_decode_reg_save (inst
, gen_mask
)
313 unsigned long *gen_mask
;
315 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
317 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
318 *gen_mask
|= (1 << reg
);
320 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
322 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
323 *gen_mask
|= (1 << reg
);
325 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
326 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
327 *gen_mask
|= (1 << RA_REGNUM
);
331 /* Fetch and return instruction from the specified location. If the PC
332 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
335 mips_fetch_instruction (addr
)
338 char buf
[MIPS_INSTLEN
];
342 if (pc_is_mips16 (addr
))
344 instlen
= MIPS16_INSTLEN
;
345 addr
= UNMAKE_MIPS16_ADDR (addr
);
348 instlen
= MIPS_INSTLEN
;
349 status
= read_memory_nobpt (addr
, buf
, instlen
);
351 memory_error (status
, addr
);
352 return extract_unsigned_integer (buf
, instlen
);
356 /* These the fields of 32 bit mips instructions */
357 #define mips32_op(x) (x >> 25)
358 #define itype_op(x) (x >> 25)
359 #define itype_rs(x) ((x >> 21)& 0x1f)
360 #define itype_rt(x) ((x >> 16) & 0x1f)
361 #define itype_immediate(x) ( x & 0xffff)
363 #define jtype_op(x) (x >> 25)
364 #define jtype_target(x) ( x & 0x03fffff)
366 #define rtype_op(x) (x >>25)
367 #define rtype_rs(x) ((x>>21) & 0x1f)
368 #define rtype_rt(x) ((x>>16) & 0x1f)
369 #define rtype_rd(x) ((x>>11) & 0x1f)
370 #define rtype_shamt(x) ((x>>6) & 0x1f)
371 #define rtype_funct(x) (x & 0x3f )
374 mips32_relative_offset(unsigned long inst
)
376 x
= itype_immediate(inst
) ;
377 if (x
& 0x8000) /* sign bit set */
379 x
|= 0xffff0000 ; /* sign extension */
385 /* Determine whate to set a single step breakpoint while considering
388 mips32_next_pc(CORE_ADDR pc
)
392 inst
= mips_fetch_instruction(pc
) ;
393 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
394 { if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
395 { op
= ((inst
>> 25) & 0x03) ;
398 case 0 : goto equal_branch
; /* BEQL */
399 case 1 : goto neq_branch
; /* BNEZ */
400 case 2 : goto less_branch
; /* BLEZ */
401 case 3 : goto greater_branch
; /* BGTZ */
405 else pc
+= 4 ; /* Not a branch, next instruction is easy */
408 { /* This gets way messy */
410 /* Further subdivide into SPECIAL, REGIMM and other */
411 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
413 case 0 : /* SPECIAL */
414 op
= rtype_funct(inst
) ;
419 pc
= read_register(rtype_rs(inst
)) ; /* Set PC to that address */
424 break ; /* end special */
425 case 1 : /* REGIMM */
427 op
= jtype_op(inst
) ; /* branch condition */
428 switch (jtype_op(inst
))
432 case 16 : /* BLTZALL */
433 case 18 : /* BLTZALL */
435 if (read_register(itype_rs(inst
)) < 0)
436 pc
+= mips32_relative_offset(inst
) + 4 ;
437 else pc
+= 8 ; /* after the delay slot */
441 case 17 : /* BGEZAL */
442 case 19 : /* BGEZALL */
443 greater_equal_branch
:
444 if (read_register(itype_rs(inst
)) >= 0)
445 pc
+= mips32_relative_offset(inst
) + 4 ;
446 else pc
+= 8 ; /* after the delay slot */
448 /* All of the other intructions in the REGIMM catagory */
452 break ; /* end REGIMM */
455 { unsigned long reg
;
456 reg
= jtype_target(inst
) << 2 ;
457 pc
= reg
+ ((pc
+4) & 0xf0000000) ;
458 /* Whats this mysterious 0xf000000 adjustment ??? */
461 /* FIXME case JALX :*/
462 { unsigned long reg
;
463 reg
= jtype_target(inst
) << 2 ;
464 pc
= reg
+ ((pc
+4) & 0xf0000000) + 1 ; /* yes, +1 */
465 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
467 break ; /* The new PC will be alternate mode */
468 case 4 : /* BEQ , BEQL */
470 if (read_register(itype_rs(inst
)) ==
471 read_register(itype_rt(inst
)))
472 pc
+= mips32_relative_offset(inst
) + 4 ;
475 case 5 : /* BNE , BNEL */
477 if (read_register(itype_rs(inst
)) !=
478 read_register(itype_rs(inst
)))
479 pc
+= mips32_relative_offset(inst
) + 4 ;
482 case 6 : /* BLEZ , BLEZL */
484 if (read_register(itype_rs(inst
) <= 0))
485 pc
+= mips32_relative_offset(inst
) + 4 ;
489 greater_branch
: /* BGTZ BGTZL */
490 if (read_register(itype_rs(inst
) > 0))
491 pc
+= mips32_relative_offset(inst
) + 4 ;
498 } /* mips32_next_pc */
500 /* Decoding the next place to set a breakpoint is irregular for the
501 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
502 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
503 We dont want to set a single step instruction on the extend instruction
507 /* Lots of mips16 instruction formats */
508 /* Predicting jumps requires itype,ritype,i8type
509 and their extensions extItype,extritype,extI8type
511 enum mips16_inst_fmts
513 itype
, /* 0 immediate 5,10 */
514 ritype
, /* 1 5,3,8 */
515 rrtype
, /* 2 5,3,3,5 */
516 rritype
, /* 3 5,3,3,5 */
517 rrrtype
, /* 4 5,3,3,3,2 */
518 rriatype
, /* 5 5,3,3,1,4 */
519 shifttype
, /* 6 5,3,3,3,2 */
520 i8type
, /* 7 5,3,8 */
521 i8movtype
, /* 8 5,3,3,5 */
522 i8mov32rtype
, /* 9 5,3,5,3 */
523 i64type
, /* 10 5,3,8 */
524 ri64type
, /* 11 5,3,3,5 */
525 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
526 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
527 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
528 extRRItype
, /* 15 5,5,5,5,3,3,5 */
529 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
530 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
531 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
532 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
533 extRi64type
, /* 20 5,6,5,5,3,3,5 */
534 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
536 /* I am heaping all the fields of the formats into one structure and then,
537 only the fields which are involved in instruction extension */
540 unsigned short inst
;
541 enum mips16_inst_fmts fmt
;
542 unsigned long offset
;
543 unsigned int regx
; /* Function in i8 type */
549 static void print_unpack(char * comment
,
550 struct upk_mips16
* u
)
552 printf("%s %04x ,f(%d) off(%08x) (x(%x) y(%x)\n",
553 comment
,u
->inst
,u
->fmt
,u
->offset
,u
->regx
,u
->regy
) ;
556 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
557 format for the bits which make up the immediatate extension.
560 extended_offset(unsigned long extension
)
562 unsigned long value
;
563 value
= (extension
>> 21) & 0x3f ; /* * extract 15:11 */
565 value
|= (extension
>> 16) & 0x1f ; /* extrace 10:5 */
567 value
|= extension
& 0x01f ; /* extract 4:0 */
571 /* Only call this function if you know that this is an extendable
572 instruction, It wont malfunction, but why make excess remote memory references?
573 If the immediate operands get sign extended or somthing, do it after
574 the extension is performed.
576 /* FIXME: Every one of these cases needs to worry about sign extension
577 when the offset is to be used in relative addressing */
580 static unsigned short fetch_mips_16(CORE_ADDR pc
)
583 pc
&= 0xfffffffe ; /* clear the low order bit */
584 target_read_memory(pc
,buf
,2) ;
585 return extract_unsigned_integer(buf
,2) ;
589 unpack_mips16(CORE_ADDR pc
,
590 struct upk_mips16
* upk
)
593 unsigned long extension
;
595 extpc
= (pc
- 4) & ~0x01 ; /* Extensions are 32 bit instructions */
596 /* Decrement to previous address and loose the 16bit mode flag */
597 /* return if the instruction was extendable, but not actually extended */
598 extended
= ((mips32_op(extension
) == 30) ? 1 : 0) ;
599 if (extended
) { extension
= mips_fetch_instruction(extpc
) ;}
604 unsigned long value
;
606 { value
= extended_offset(extension
) ;
607 value
= value
<< 11 ; /* rom for the original value */
608 value
|= upk
->inst
& 0x7ff ; /* eleven bits from instruction */
611 { value
= upk
->inst
& 0x7ff ;
612 /* FIXME : Consider sign extension */
614 upk
->offset
= value
;
619 { /* A register identifier and an offset */
620 /* Most of the fields are the same as I type but the
621 immediate value is of a different length */
622 unsigned long value
;
625 value
= extended_offset(extension
) ;
626 value
= value
<< 8 ; /* from the original instruction */
627 value
|= upk
->inst
& 0xff ; /* eleven bits from instruction */
628 upk
->regx
= (extension
>> 8) & 0x07 ; /* or i8 funct */
629 if (value
& 0x4000) /* test the sign bit , bit 26 */
630 { value
&= ~ 0x3fff ; /* remove the sign bit */
635 value
= upk
->inst
& 0xff ; /* 8 bits */
636 upk
->regx
= (upk
->inst
>> 8) & 0x07 ; /* or i8 funct */
637 /* FIXME: Do sign extension , this format needs it */
638 if (value
& 0x80) /* THIS CONFUSES ME */
639 { value
&= 0xef ; /* remove the sign bit */
644 upk
->offset
= value
;
649 unsigned long value
;
650 unsigned short nexthalf
;
651 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f) ;
652 value
= value
<< 16 ;
653 nexthalf
= mips_fetch_instruction(pc
+2) ; /* low bit still set */
655 upk
->offset
= value
;
659 printf_filtered("Decoding unimplemented instruction format type\n") ;
662 /* print_unpack("UPK",upk) ; */
666 #define mips16_op(x) (x >> 11)
668 /* This is a map of the opcodes which ae known to perform branches */
669 static unsigned char map16
[32] =
676 static CORE_ADDR
add_offset_16(CORE_ADDR pc
, int offset
)
678 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000))) ;
684 static struct upk_mips16 upk
;
686 CORE_ADDR
mips16_next_pc(CORE_ADDR pc
)
690 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
691 inst
= fetch_mips_16(pc
) ;
693 op
= mips16_op(upk
.inst
) ;
699 case 2 : /* Branch */
701 unpack_mips16(pc
,&upk
) ;
703 offset
= upk
.offset
;
708 pc
+= (offset
<< 1) + 2 ;
711 case 3 : /* JAL , JALX - Watch out, these are 32 bit instruction*/
713 unpack_mips16(pc
,&upk
) ;
714 pc
= add_offset_16(pc
,upk
.offset
) ;
715 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
716 pc
= pc
& ~ 0x01 ; /* Clear low bit, indicate 32 bit mode */
721 unpack_mips16(pc
,&upk
) ;
722 reg
= read_register(upk
.regx
) ;
724 pc
+= (upk
.offset
<< 1) + 2 ;
729 unpack_mips16(pc
,&upk
) ;
730 reg
= read_register(upk
.regx
) ;
732 pc
+= (upk
.offset
<< 1) + 2 ;
735 case 12 : /* I8 Formats btez btnez */
737 unpack_mips16(pc
,&upk
) ;
738 /* upk.regx contains the opcode */
739 reg
= read_register(24) ; /* Test register is 24 */
740 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
741 || ((upk
.regx
== 1 ) && (reg
!= 0))) /* BTNEZ */
742 /* pc = add_offset_16(pc,upk.offset) ; */
743 pc
+= (upk
.offset
<< 1) + 2 ;
746 case 29 : /* RR Formats JR, JALR, JALR-RA */
748 op
= upk
.inst
& 0x1f ;
751 upk
.regx
= (upk
.inst
>> 8) & 0x07 ;
752 upk
.regy
= (upk
.inst
>> 5) & 0x07 ;
755 case 0 : reg
= upk
.regx
; break ;
756 case 1 : reg
= 31 ; break ; /* Function return instruction*/
757 case 2 : reg
= upk
.regx
; break ;
758 default: reg
= 31 ; break ; /* BOGUS Guess */
760 pc
= read_register(reg
) ;
764 case 30 : /* This is an extend instruction */
765 pc
+= 4 ; /* Dont be setting breakpints on the second half */
768 printf("Filtered - next PC probably incorrrect due to jump inst\n");
773 else pc
+= 2 ; /* just a good old instruction */
774 /* See if we CAN actually break on the next instruction */
775 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
777 } /* mips16_next_pc */
779 /* The mips_next_pc function supports single_tep when the remote target monitor or
780 stub is not developed enough to so a single_step.
781 It works by decoding the current instruction and predicting where a branch
782 will go. This isnt hard because all the data is available.
783 The MIPS32 and MIPS16 variants are quite different
785 CORE_ADDR
mips_next_pc(CORE_ADDR pc
)
788 /* inst = mips_fetch_instruction(pc) ; */
789 /* if (pc_is_mips16) <----- This is failing */
791 return mips16_next_pc(pc
) ;
792 else return mips32_next_pc(pc
) ;
795 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
799 mips_find_saved_regs (fci
)
800 struct frame_info
*fci
;
803 CORE_ADDR reg_position
;
804 /* r0 bit means kernel trap */
806 /* What registers have been saved? Bitmasks. */
807 unsigned long gen_mask
, float_mask
;
808 mips_extra_func_info_t proc_desc
;
811 fci
->saved_regs
= (struct frame_saved_regs
*)
812 obstack_alloc (&frame_cache_obstack
, sizeof(struct frame_saved_regs
));
813 memset (fci
->saved_regs
, 0, sizeof (struct frame_saved_regs
));
815 /* If it is the frame for sigtramp, the saved registers are located
816 in a sigcontext structure somewhere on the stack.
817 If the stack layout for sigtramp changes we might have to change these
818 constants and the companion fixup_sigtramp in mdebugread.c */
819 #ifndef SIGFRAME_BASE
820 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
821 above the sigtramp frame. */
822 #define SIGFRAME_BASE MIPS_REGSIZE
823 /* FIXME! Are these correct?? */
824 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
825 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
826 #define SIGFRAME_FPREGSAVE_OFF \
827 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
829 #ifndef SIGFRAME_REG_SIZE
830 /* FIXME! Is this correct?? */
831 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
833 if (fci
->signal_handler_caller
)
835 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
837 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
838 + ireg
* SIGFRAME_REG_SIZE
;
839 fci
->saved_regs
->regs
[ireg
] = reg_position
;
841 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
843 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
844 + ireg
* SIGFRAME_REG_SIZE
;
845 fci
->saved_regs
->regs
[FP0_REGNUM
+ ireg
] = reg_position
;
847 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
851 proc_desc
= fci
->proc_desc
;
852 if (proc_desc
== NULL
)
853 /* I'm not sure how/whether this can happen. Normally when we can't
854 find a proc_desc, we "synthesize" one using heuristic_proc_desc
855 and set the saved_regs right away. */
858 kernel_trap
= PROC_REG_MASK(proc_desc
) & 1;
859 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK(proc_desc
);
860 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc
);
862 if (/* In any frame other than the innermost or a frame interrupted by
863 a signal, we assume that all registers have been saved.
864 This assumes that all register saves in a function happen before
865 the first function call. */
866 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
868 /* In a dummy frame we know exactly where things are saved. */
869 && !PROC_DESC_IS_DUMMY (proc_desc
)
871 /* Don't bother unless we are inside a function prologue. Outside the
872 prologue, we know where everything is. */
874 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
876 /* Not sure exactly what kernel_trap means, but if it means
877 the kernel saves the registers without a prologue doing it,
878 we better not examine the prologue to see whether registers
879 have been saved yet. */
882 /* We need to figure out whether the registers that the proc_desc
883 claims are saved have been saved yet. */
887 /* Bitmasks; set if we have found a save for the register. */
888 unsigned long gen_save_found
= 0;
889 unsigned long float_save_found
= 0;
892 /* If the address is odd, assume this is MIPS16 code. */
893 addr
= PROC_LOW_ADDR (proc_desc
);
894 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
896 /* Scan through this function's instructions preceding the current
897 PC, and look for those that save registers. */
898 while (addr
< fci
->pc
)
900 inst
= mips_fetch_instruction (addr
);
901 if (pc_is_mips16 (addr
))
902 mips16_decode_reg_save (inst
, &gen_save_found
);
904 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
907 gen_mask
= gen_save_found
;
908 float_mask
= float_save_found
;
911 /* Fill in the offsets for the registers which gen_mask says
913 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
914 for (ireg
= MIPS_NUMREGS
-1; gen_mask
; --ireg
, gen_mask
<<= 1)
915 if (gen_mask
& 0x80000000)
917 fci
->saved_regs
->regs
[ireg
] = reg_position
;
918 reg_position
-= MIPS_REGSIZE
;
921 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
922 of that normally used by gcc. Therefore, we have to fetch the first
923 instruction of the function, and if it's an entry instruction that
924 saves $s0 or $s1, correct their saved addresses. */
925 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
927 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
928 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
931 int sreg_count
= (inst
>> 6) & 3;
933 /* Check if the ra register was pushed on the stack. */
934 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
936 reg_position
-= MIPS_REGSIZE
;
938 /* Check if the s0 and s1 registers were pushed on the stack. */
939 for (reg
= 16; reg
< sreg_count
+16; reg
++)
941 fci
->saved_regs
->regs
[reg
] = reg_position
;
942 reg_position
-= MIPS_REGSIZE
;
947 /* Fill in the offsets for the registers which float_mask says
949 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
951 /* The freg_offset points to where the first *double* register
952 is saved. So skip to the high-order word. */
953 if (! GDB_TARGET_IS_MIPS64
)
954 reg_position
+= MIPS_REGSIZE
;
956 /* Fill in the offsets for the float registers which float_mask says
958 for (ireg
= MIPS_NUMREGS
-1; float_mask
; --ireg
, float_mask
<<= 1)
959 if (float_mask
& 0x80000000)
961 fci
->saved_regs
->regs
[FP0_REGNUM
+ireg
] = reg_position
;
962 reg_position
-= MIPS_REGSIZE
;
965 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->saved_regs
->regs
[RA_REGNUM
];
969 read_next_frame_reg(fi
, regno
)
970 struct frame_info
*fi
;
973 for (; fi
; fi
= fi
->next
)
975 /* We have to get the saved sp from the sigcontext
976 if it is a signal handler frame. */
977 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
981 if (fi
->saved_regs
== NULL
)
982 mips_find_saved_regs (fi
);
983 if (fi
->saved_regs
->regs
[regno
])
984 return read_memory_integer(fi
->saved_regs
->regs
[regno
], MIPS_REGSIZE
);
987 return read_register (regno
);
990 /* mips_addr_bits_remove - remove useless address bits */
993 mips_addr_bits_remove (addr
)
996 #if GDB_TARGET_IS_MIPS64
997 if ((addr
>> 32 == (CORE_ADDR
)0xffffffff)
998 && (strcmp (target_shortname
,"pmon")==0
999 || strcmp (target_shortname
,"ddb")==0
1000 || strcmp (target_shortname
,"sim")==0))
1002 /* This hack is a work-around for existing boards using PMON,
1003 the simulator, and any other 64-bit targets that doesn't have
1004 true 64-bit addressing. On these targets, the upper 32 bits
1005 of addresses are ignored by the hardware. Thus, the PC or SP
1006 are likely to have been sign extended to all 1s by instruction
1007 sequences that load 32-bit addresses. For example, a typical
1008 piece of code that loads an address is this:
1009 lui $r2, <upper 16 bits>
1010 ori $r2, <lower 16 bits>
1011 But the lui sign-extends the value such that the upper 32 bits
1012 may be all 1s. The workaround is simply to mask off these bits.
1013 In the future, gcc may be changed to support true 64-bit
1014 addressing, and this masking will have to be disabled. */
1015 addr
&= (CORE_ADDR
)0xffffffff;
1018 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1019 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1020 So we still have to mask off useless bits from addresses. */
1021 addr
&= (CORE_ADDR
)0xffffffff;
1028 mips_init_frame_pc_first (fromleaf
, prev
)
1030 struct frame_info
*prev
;
1034 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1035 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1036 tmp
= mips_skip_stub (pc
);
1037 prev
->pc
= tmp
? tmp
: pc
;
1042 mips_frame_saved_pc(frame
)
1043 struct frame_info
*frame
;
1046 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
1047 /* We have to get the saved pc from the sigcontext
1048 if it is a signal handler frame. */
1049 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1050 : (proc_desc
? PROC_PC_REG(proc_desc
) : RA_REGNUM
);
1052 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
1053 saved_pc
= read_memory_integer(frame
->frame
- MIPS_REGSIZE
, MIPS_REGSIZE
);
1055 saved_pc
= read_next_frame_reg(frame
, pcreg
);
1057 return ADDR_BITS_REMOVE (saved_pc
);
1060 static struct mips_extra_func_info temp_proc_desc
;
1061 static struct frame_saved_regs temp_saved_regs
;
1063 /* Set a register's saved stack address in temp_saved_regs. If an address
1064 has already been set for this register, do nothing; this way we will
1065 only recognize the first save of a given register in a function prologue.
1066 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1069 set_reg_offset (regno
, offset
)
1073 if (temp_saved_regs
.regs
[regno
] == 0)
1074 temp_saved_regs
.regs
[regno
] = offset
;
1078 /* This fencepost looks highly suspicious to me. Removing it also
1079 seems suspicious as it could affect remote debugging across serial
1083 heuristic_proc_start(pc
)
1091 pc
= ADDR_BITS_REMOVE (pc
);
1093 fence
= start_pc
- heuristic_fence_post
;
1094 if (start_pc
== 0) return 0;
1096 if (heuristic_fence_post
== UINT_MAX
1097 || fence
< VM_MIN_ADDRESS
)
1098 fence
= VM_MIN_ADDRESS
;
1100 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1102 /* search back for previous return */
1103 for (start_pc
-= instlen
; ; start_pc
-= instlen
)
1104 if (start_pc
< fence
)
1106 /* It's not clear to me why we reach this point when
1107 stop_soon_quietly, but with this test, at least we
1108 don't print out warnings for every child forked (eg, on
1109 decstation). 22apr93 rich@cygnus.com. */
1110 if (!stop_soon_quietly
)
1112 static int blurb_printed
= 0;
1114 if (fence
== VM_MIN_ADDRESS
)
1115 warning("Hit beginning of text section without finding");
1117 warning("Hit heuristic-fence-post without finding");
1119 warning("enclosing function for address 0x%s", paddr_nz (pc
));
1123 This warning occurs if you are debugging a function without any symbols\n\
1124 (for example, in a stripped executable). In that case, you may wish to\n\
1125 increase the size of the search with the `set heuristic-fence-post' command.\n\
1127 Otherwise, you told GDB there was a function where there isn't one, or\n\
1128 (more likely) you have encountered a bug in GDB.\n");
1135 else if (pc_is_mips16 (start_pc
))
1137 unsigned short inst
;
1139 /* On MIPS16, any one of the following is likely to be the
1140 start of a function:
1144 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1145 inst
= mips_fetch_instruction (start_pc
);
1146 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1147 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1148 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1149 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1151 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1152 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1157 else if (ABOUT_TO_RETURN(start_pc
))
1159 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1164 /* skip nops (usually 1) 0 - is this */
1165 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1166 start_pc
+= MIPS_INSTLEN
;
1171 /* Fetch the immediate value from a MIPS16 instruction.
1172 If the previous instruction was an EXTEND, use it to extend
1173 the upper bits of the immediate value. This is a helper function
1174 for mips16_heuristic_proc_desc. */
1177 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1178 unsigned short prev_inst
; /* previous instruction */
1179 unsigned short inst
; /* current instruction */
1180 int nbits
; /* number of bits in imm field */
1181 int scale
; /* scale factor to be applied to imm */
1182 int is_signed
; /* is the imm field signed? */
1186 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1188 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1189 if (offset
& 0x8000) /* check for negative extend */
1190 offset
= 0 - (0x10000 - (offset
& 0xffff));
1191 return offset
| (inst
& 0x1f);
1195 int max_imm
= 1 << nbits
;
1196 int mask
= max_imm
- 1;
1197 int sign_bit
= max_imm
>> 1;
1199 offset
= inst
& mask
;
1200 if (is_signed
&& (offset
& sign_bit
))
1201 offset
= 0 - (max_imm
- offset
);
1202 return offset
* scale
;
1207 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1208 stream from start_pc to limit_pc. */
1211 mips16_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1212 CORE_ADDR start_pc
, limit_pc
;
1213 struct frame_info
*next_frame
;
1217 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1218 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1219 unsigned inst
= 0; /* current instruction */
1220 unsigned entry_inst
= 0; /* the entry instruction */
1223 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0; /* size of stack frame */
1224 PROC_FRAME_ADJUST(&temp_proc_desc
) = 0; /* offset of FP from SP */
1226 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1228 /* Save the previous instruction. If it's an EXTEND, we'll extract
1229 the immediate offset extension from it in mips16_get_imm. */
1232 /* Fetch and decode the instruction. */
1233 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1234 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1235 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1237 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1238 if (offset
< 0) /* negative stack adjustment? */
1239 PROC_FRAME_OFFSET(&temp_proc_desc
) -= offset
;
1241 /* Exit loop if a positive stack adjustment is found, which
1242 usually means that the stack cleanup code in the function
1243 epilogue is reached. */
1246 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1248 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1249 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1250 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1251 set_reg_offset (reg
, sp
+ offset
);
1253 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1255 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1256 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1257 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1258 set_reg_offset (reg
, sp
+ offset
);
1260 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1262 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1263 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1264 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1266 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1268 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1269 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1270 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1272 else if (inst
== 0x673d) /* move $s1, $sp */
1275 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1277 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1279 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1280 frame_addr
= sp
+ offset
;
1281 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1282 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1284 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1286 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1287 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1288 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1289 set_reg_offset (reg
, frame_addr
+ offset
);
1291 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1293 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1294 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1295 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1296 set_reg_offset (reg
, frame_addr
+ offset
);
1298 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1299 entry_inst
= inst
; /* save for later processing */
1300 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1301 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1304 /* The entry instruction is typically the first instruction in a function,
1305 and it stores registers at offsets relative to the value of the old SP
1306 (before the prologue). But the value of the sp parameter to this
1307 function is the new SP (after the prologue has been executed). So we
1308 can't calculate those offsets until we've seen the entire prologue,
1309 and can calculate what the old SP must have been. */
1310 if (entry_inst
!= 0)
1312 int areg_count
= (entry_inst
>> 8) & 7;
1313 int sreg_count
= (entry_inst
>> 6) & 3;
1315 /* The entry instruction always subtracts 32 from the SP. */
1316 PROC_FRAME_OFFSET(&temp_proc_desc
) += 32;
1318 /* Now we can calculate what the SP must have been at the
1319 start of the function prologue. */
1320 sp
+= PROC_FRAME_OFFSET(&temp_proc_desc
);
1322 /* Check if a0-a3 were saved in the caller's argument save area. */
1323 for (reg
= 4, offset
= 0; reg
< areg_count
+4; reg
++)
1325 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1326 set_reg_offset (reg
, sp
+ offset
);
1327 offset
+= MIPS_REGSIZE
;
1330 /* Check if the ra register was pushed on the stack. */
1332 if (entry_inst
& 0x20)
1334 PROC_REG_MASK(&temp_proc_desc
) |= 1 << RA_REGNUM
;
1335 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1336 offset
-= MIPS_REGSIZE
;
1339 /* Check if the s0 and s1 registers were pushed on the stack. */
1340 for (reg
= 16; reg
< sreg_count
+16; reg
++)
1342 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1343 set_reg_offset (reg
, sp
+ offset
);
1344 offset
-= MIPS_REGSIZE
;
1350 mips32_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1351 CORE_ADDR start_pc
, limit_pc
;
1352 struct frame_info
*next_frame
;
1356 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1358 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
1359 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1360 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1362 unsigned long inst
, high_word
, low_word
;
1365 /* Fetch the instruction. */
1366 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1368 /* Save some code by pre-extracting some useful fields. */
1369 high_word
= (inst
>> 16) & 0xffff;
1370 low_word
= inst
& 0xffff;
1371 reg
= high_word
& 0x1f;
1373 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1374 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1375 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1377 if (low_word
& 0x8000) /* negative stack adjustment? */
1378 PROC_FRAME_OFFSET(&temp_proc_desc
) += 0x10000 - low_word
;
1380 /* Exit loop if a positive stack adjustment is found, which
1381 usually means that the stack cleanup code in the function
1382 epilogue is reached. */
1385 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1387 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1388 set_reg_offset (reg
, sp
+ low_word
);
1390 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1392 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1393 but the register size used is only 32 bits. Make the address
1394 for the saved register point to the lower 32 bits. */
1395 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1396 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1398 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1400 /* Old gcc frame, r30 is virtual frame pointer. */
1401 if ((long)low_word
!= PROC_FRAME_OFFSET(&temp_proc_desc
))
1402 frame_addr
= sp
+ low_word
;
1403 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1405 unsigned alloca_adjust
;
1406 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1407 frame_addr
= read_next_frame_reg(next_frame
, 30);
1408 alloca_adjust
= (unsigned)(frame_addr
- (sp
+ low_word
));
1409 if (alloca_adjust
> 0)
1411 /* FP > SP + frame_size. This may be because
1412 * of an alloca or somethings similar.
1413 * Fix sp to "pre-alloca" value, and try again.
1415 sp
+= alloca_adjust
;
1420 /* move $30,$sp. With different versions of gas this will be either
1421 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1422 Accept any one of these. */
1423 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1425 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1426 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1428 unsigned alloca_adjust
;
1429 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1430 frame_addr
= read_next_frame_reg(next_frame
, 30);
1431 alloca_adjust
= (unsigned)(frame_addr
- sp
);
1432 if (alloca_adjust
> 0)
1434 /* FP > SP + frame_size. This may be because
1435 * of an alloca or somethings similar.
1436 * Fix sp to "pre-alloca" value, and try again.
1438 sp
+= alloca_adjust
;
1443 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1445 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1446 set_reg_offset (reg
, frame_addr
+ low_word
);
1451 static mips_extra_func_info_t
1452 heuristic_proc_desc(start_pc
, limit_pc
, next_frame
)
1453 CORE_ADDR start_pc
, limit_pc
;
1454 struct frame_info
*next_frame
;
1456 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1458 if (start_pc
== 0) return NULL
;
1459 memset (&temp_proc_desc
, '\0', sizeof(temp_proc_desc
));
1460 memset (&temp_saved_regs
, '\0', sizeof(struct frame_saved_regs
));
1461 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1462 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1463 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1465 if (start_pc
+ 200 < limit_pc
)
1466 limit_pc
= start_pc
+ 200;
1467 if (pc_is_mips16 (start_pc
))
1468 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1470 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1471 return &temp_proc_desc
;
1474 static mips_extra_func_info_t
1475 non_heuristic_proc_desc (pc
, addrptr
)
1479 CORE_ADDR startaddr
;
1480 mips_extra_func_info_t proc_desc
;
1481 struct block
*b
= block_for_pc(pc
);
1484 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1486 *addrptr
= startaddr
;
1487 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1491 if (startaddr
> BLOCK_START (b
))
1492 /* This is the "pathological" case referred to in a comment in
1493 print_frame_info. It might be better to move this check into
1497 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1500 /* If we never found a PDR for this function in symbol reading, then
1501 examine prologues to find the information. */
1504 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1505 if (PROC_FRAME_REG (proc_desc
) == -1)
1515 static mips_extra_func_info_t
1516 find_proc_desc (pc
, next_frame
)
1518 struct frame_info
*next_frame
;
1520 mips_extra_func_info_t proc_desc
;
1521 CORE_ADDR startaddr
;
1523 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1527 /* IF this is the topmost frame AND
1528 * (this proc does not have debugging information OR
1529 * the PC is in the procedure prologue)
1530 * THEN create a "heuristic" proc_desc (by analyzing
1531 * the actual code) to replace the "official" proc_desc.
1533 if (next_frame
== NULL
)
1535 struct symtab_and_line val
;
1536 struct symbol
*proc_symbol
=
1537 PROC_DESC_IS_DUMMY(proc_desc
) ? 0 : PROC_SYMBOL(proc_desc
);
1541 val
= find_pc_line (BLOCK_START
1542 (SYMBOL_BLOCK_VALUE(proc_symbol
)),
1544 val
.pc
= val
.end
? val
.end
: pc
;
1546 if (!proc_symbol
|| pc
< val
.pc
)
1548 mips_extra_func_info_t found_heuristic
=
1549 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1551 if (found_heuristic
)
1552 proc_desc
= found_heuristic
;
1558 /* Is linked_proc_desc_table really necessary? It only seems to be used
1559 by procedure call dummys. However, the procedures being called ought
1560 to have their own proc_descs, and even if they don't,
1561 heuristic_proc_desc knows how to create them! */
1563 register struct linked_proc_info
*link
;
1565 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1566 if (PROC_LOW_ADDR(&link
->info
) <= pc
1567 && PROC_HIGH_ADDR(&link
->info
) > pc
)
1571 startaddr
= heuristic_proc_start (pc
);
1574 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1580 get_frame_pointer(frame
, proc_desc
)
1581 struct frame_info
*frame
;
1582 mips_extra_func_info_t proc_desc
;
1584 return ADDR_BITS_REMOVE (
1585 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1586 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1589 mips_extra_func_info_t cached_proc_desc
;
1592 mips_frame_chain(frame
)
1593 struct frame_info
*frame
;
1595 mips_extra_func_info_t proc_desc
;
1597 CORE_ADDR saved_pc
= FRAME_SAVED_PC(frame
);
1599 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1602 /* Check if the PC is inside a call stub. If it is, fetch the
1603 PC of the caller of that stub. */
1604 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1607 /* Look up the procedure descriptor for this PC. */
1608 proc_desc
= find_proc_desc(saved_pc
, frame
);
1612 cached_proc_desc
= proc_desc
;
1614 /* If no frame pointer and frame size is zero, we must be at end
1615 of stack (or otherwise hosed). If we don't check frame size,
1616 we loop forever if we see a zero size frame. */
1617 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1618 && PROC_FRAME_OFFSET (proc_desc
) == 0
1619 /* The previous frame from a sigtramp frame might be frameless
1620 and have frame size zero. */
1621 && !frame
->signal_handler_caller
)
1624 return get_frame_pointer (frame
, proc_desc
);
1628 init_extra_frame_info(fci
)
1629 struct frame_info
*fci
;
1633 /* Use proc_desc calculated in frame_chain */
1634 mips_extra_func_info_t proc_desc
=
1635 fci
->next
? cached_proc_desc
: find_proc_desc(fci
->pc
, fci
->next
);
1637 fci
->saved_regs
= NULL
;
1639 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1642 /* Fixup frame-pointer - only needed for top frame */
1643 /* This may not be quite right, if proc has a real frame register.
1644 Get the value of the frame relative sp, procedure might have been
1645 interrupted by a signal at it's very start. */
1646 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1647 && !PROC_DESC_IS_DUMMY (proc_desc
))
1648 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1650 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1652 if (proc_desc
== &temp_proc_desc
)
1656 /* Do not set the saved registers for a sigtramp frame,
1657 mips_find_saved_registers will do that for us.
1658 We can't use fci->signal_handler_caller, it is not yet set. */
1659 find_pc_partial_function (fci
->pc
, &name
,
1660 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
1661 if (!IN_SIGTRAMP (fci
->pc
, name
))
1663 fci
->saved_regs
= (struct frame_saved_regs
*)
1664 obstack_alloc (&frame_cache_obstack
,
1665 sizeof (struct frame_saved_regs
));
1666 *fci
->saved_regs
= temp_saved_regs
;
1667 fci
->saved_regs
->regs
[PC_REGNUM
]
1668 = fci
->saved_regs
->regs
[RA_REGNUM
];
1672 /* hack: if argument regs are saved, guess these contain args */
1673 fci
->num_args
= -1; /* assume we can't tell how many args for now */
1674 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1676 if (PROC_REG_MASK(proc_desc
) & (1 << regnum
))
1678 fci
->num_args
= regnum
- A0_REGNUM
+ 1;
1685 /* MIPS stack frames are almost impenetrable. When execution stops,
1686 we basically have to look at symbol information for the function
1687 that we stopped in, which tells us *which* register (if any) is
1688 the base of the frame pointer, and what offset from that register
1689 the frame itself is at.
1691 This presents a problem when trying to examine a stack in memory
1692 (that isn't executing at the moment), using the "frame" command. We
1693 don't have a PC, nor do we have any registers except SP.
1695 This routine takes two arguments, SP and PC, and tries to make the
1696 cached frames look as if these two arguments defined a frame on the
1697 cache. This allows the rest of info frame to extract the important
1698 arguments without difficulty. */
1701 setup_arbitrary_frame (argc
, argv
)
1706 error ("MIPS frame specifications require two arguments: sp and pc");
1708 return create_new_frame (argv
[0], argv
[1]);
1712 mips_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
1717 CORE_ADDR struct_addr
;
1723 int stack_offset
= 0;
1725 /* Macros to round N up or down to the next A boundary; A must be
1727 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1728 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1730 /* First ensure that the stack and structure return address (if any)
1731 are properly aligned. The stack has to be 64-bit aligned even
1732 on 32-bit machines, because doubles must be 64-bit aligned. */
1733 sp
= ROUND_DOWN (sp
, 8);
1734 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_REGSIZE
);
1736 /* Now make space on the stack for the args. We allocate more
1737 than necessary for EABI, because the first few arguments are
1738 passed in registers, but that's OK. */
1739 for (argnum
= 0; argnum
< nargs
; argnum
++)
1740 len
+= ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args
[argnum
])), MIPS_REGSIZE
);
1741 sp
-= ROUND_UP (len
, 8);
1743 /* Initialize the integer and float register pointers. */
1745 float_argreg
= FPA0_REGNUM
;
1747 /* the struct_return pointer occupies the first parameter-passing reg */
1749 write_register (argreg
++, struct_addr
);
1751 /* Now load as many as possible of the first arguments into
1752 registers, and push the rest onto the stack. Loop thru args
1753 from first to last. */
1754 for (argnum
= 0; argnum
< nargs
; argnum
++)
1757 char valbuf
[MAX_REGISTER_RAW_SIZE
];
1758 value_ptr arg
= args
[argnum
];
1759 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1760 int len
= TYPE_LENGTH (arg_type
);
1761 enum type_code typecode
= TYPE_CODE (arg_type
);
1763 /* The EABI passes structures that do not fit in a register by
1764 reference. In all other cases, pass the structure by value. */
1765 if (MIPS_EABI
&& len
> MIPS_REGSIZE
&&
1766 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1768 store_address (valbuf
, MIPS_REGSIZE
, VALUE_ADDRESS (arg
));
1769 typecode
= TYPE_CODE_PTR
;
1774 val
= (char *)VALUE_CONTENTS (arg
);
1776 /* 32-bit ABIs always start floating point arguments in an
1777 even-numbered floating point register. */
1778 if (!GDB_TARGET_IS_MIPS64
&& typecode
== TYPE_CODE_FLT
1779 && (float_argreg
& 1))
1782 /* Floating point arguments passed in registers have to be
1783 treated specially. On 32-bit architectures, doubles
1784 are passed in register pairs; the even register gets
1785 the low word, and the odd register gets the high word.
1786 On non-EABI processors, the first two floating point arguments are
1787 also copied to general registers, because MIPS16 functions
1788 don't use float registers for arguments. This duplication of
1789 arguments in general registers can't hurt non-MIPS16 functions
1790 because those registers are normally skipped. */
1791 if (typecode
== TYPE_CODE_FLT
1792 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
1793 && mips_fpu
!= MIPS_FPU_NONE
)
1795 if (!GDB_TARGET_IS_MIPS64
&& len
== 8)
1797 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
1798 unsigned long regval
;
1800 /* Write the low word of the double to the even register(s). */
1801 regval
= extract_unsigned_integer (val
+low_offset
, 4);
1802 write_register (float_argreg
++, regval
);
1804 write_register (argreg
+1, regval
);
1806 /* Write the high word of the double to the odd register(s). */
1807 regval
= extract_unsigned_integer (val
+4-low_offset
, 4);
1808 write_register (float_argreg
++, regval
);
1811 write_register (argreg
, regval
);
1818 /* This is a floating point value that fits entirely
1819 in a single register. */
1820 CORE_ADDR regval
= extract_address (val
, len
);
1821 write_register (float_argreg
++, regval
);
1824 write_register (argreg
, regval
);
1825 argreg
+= GDB_TARGET_IS_MIPS64
? 1 : 2;
1831 /* Copy the argument to general registers or the stack in
1832 register-sized pieces. Large arguments are split between
1833 registers and stack. */
1834 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
1835 are treated specially: Irix cc passes them in registers
1836 where gcc sometimes puts them on the stack. For maximum
1837 compatibility, we will put them in both places. */
1839 int odd_sized_struct
= ((len
> MIPS_REGSIZE
) &&
1840 (len
% MIPS_REGSIZE
!= 0));
1843 int partial_len
= len
< MIPS_REGSIZE
? len
: MIPS_REGSIZE
;
1845 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
1847 /* Write this portion of the argument to the stack. */
1848 /* Should shorter than int integer values be
1849 promoted to int before being stored? */
1851 int longword_offset
= 0;
1852 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1853 if (MIPS_REGSIZE
== 8 &&
1854 (typecode
== TYPE_CODE_INT
||
1855 typecode
== TYPE_CODE_PTR
||
1856 typecode
== TYPE_CODE_FLT
) && len
<= 4)
1857 longword_offset
= MIPS_REGSIZE
- len
;
1858 else if ((typecode
== TYPE_CODE_STRUCT
||
1859 typecode
== TYPE_CODE_UNION
) &&
1860 TYPE_LENGTH (arg_type
) < MIPS_REGSIZE
)
1861 longword_offset
= MIPS_REGSIZE
- len
;
1863 write_memory (sp
+ stack_offset
+ longword_offset
,
1867 /* Note!!! This is NOT an else clause.
1868 Odd sized structs may go thru BOTH paths. */
1869 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
1871 CORE_ADDR regval
= extract_address (val
, partial_len
);
1873 /* A non-floating-point argument being passed in a
1874 general register. If a struct or union, and if
1875 the remaining length is smaller than the register
1876 size, we have to adjust the register value on
1879 It does not seem to be necessary to do the
1880 same for integral types.
1882 Also don't do this adjustment on EABI targets. */
1885 TARGET_BYTE_ORDER
== BIG_ENDIAN
&&
1886 partial_len
< MIPS_REGSIZE
&&
1887 (typecode
== TYPE_CODE_STRUCT
||
1888 typecode
== TYPE_CODE_UNION
))
1889 regval
<<= ((MIPS_REGSIZE
- partial_len
) *
1892 write_register (argreg
, regval
);
1895 /* If this is the old ABI, prevent subsequent floating
1896 point arguments from being passed in floating point
1899 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
1905 /* The offset onto the stack at which we will start
1906 copying parameters (after the registers are used up)
1907 begins at (4 * MIPS_REGSIZE) in the old ABI. This
1908 leaves room for the "home" area for register parameters.
1910 In the new EABI, the 8 register parameters do not
1911 have "home" stack space reserved for them, so the
1912 stack offset does not get incremented until after
1913 we have used up the 8 parameter registers. */
1914 if (!(MIPS_EABI
&& argnum
< 8))
1915 stack_offset
+= ROUND_UP (partial_len
, MIPS_REGSIZE
);
1920 /* Set the return address register to point to the entry
1921 point of the program, where a breakpoint lies in wait. */
1922 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS());
1924 /* Return adjusted stack pointer. */
1929 mips_push_register(CORE_ADDR
*sp
, int regno
)
1931 char buffer
[MAX_REGISTER_RAW_SIZE
];
1932 int regsize
= REGISTER_RAW_SIZE (regno
);
1935 read_register_gen (regno
, buffer
);
1936 write_memory (*sp
, buffer
, regsize
);
1939 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
1940 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
1943 mips_push_dummy_frame()
1946 struct linked_proc_info
*link
= (struct linked_proc_info
*)
1947 xmalloc(sizeof(struct linked_proc_info
));
1948 mips_extra_func_info_t proc_desc
= &link
->info
;
1949 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
1950 CORE_ADDR old_sp
= sp
;
1951 link
->next
= linked_proc_desc_table
;
1952 linked_proc_desc_table
= link
;
1954 /* FIXME! are these correct ? */
1955 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
1956 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
1957 #define FLOAT_REG_SAVE_MASK MASK(0,19)
1958 #define FLOAT_SINGLE_REG_SAVE_MASK \
1959 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
1961 * The registers we must save are all those not preserved across
1962 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
1963 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
1964 * and FP Control/Status registers.
1967 * Dummy frame layout:
1970 * Saved MMHI, MMLO, FPC_CSR
1975 * Saved D18 (i.e. F19, F18)
1977 * Saved D0 (i.e. F1, F0)
1978 * Argument build area and stack arguments written via mips_push_arguments
1982 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
1983 PROC_FRAME_REG(proc_desc
) = PUSH_FP_REGNUM
;
1984 PROC_FRAME_OFFSET(proc_desc
) = 0;
1985 PROC_FRAME_ADJUST(proc_desc
) = 0;
1986 mips_push_register (&sp
, PC_REGNUM
);
1987 mips_push_register (&sp
, HI_REGNUM
);
1988 mips_push_register (&sp
, LO_REGNUM
);
1989 mips_push_register (&sp
, mips_fpu
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
1991 /* Save general CPU registers */
1992 PROC_REG_MASK(proc_desc
) = GEN_REG_SAVE_MASK
;
1993 PROC_REG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved R31) from FP */
1994 for (ireg
= 32; --ireg
>= 0; )
1995 if (PROC_REG_MASK(proc_desc
) & (1 << ireg
))
1996 mips_push_register (&sp
, ireg
);
1998 /* Save floating point registers starting with high order word */
1999 PROC_FREG_MASK(proc_desc
) =
2000 mips_fpu
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2001 : mips_fpu
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2002 PROC_FREG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved D18) from FP */
2003 for (ireg
= 32; --ireg
>= 0; )
2004 if (PROC_FREG_MASK(proc_desc
) & (1 << ireg
))
2005 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2007 /* Update the frame pointer for the call dummy and the stack pointer.
2008 Set the procedure's starting and ending addresses to point to the
2009 call dummy address at the entry point. */
2010 write_register (PUSH_FP_REGNUM
, old_sp
);
2011 write_register (SP_REGNUM
, sp
);
2012 PROC_LOW_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS();
2013 PROC_HIGH_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS() + 4;
2014 SET_PROC_DESC_IS_DUMMY(proc_desc
);
2015 PROC_PC_REG(proc_desc
) = RA_REGNUM
;
2021 register int regnum
;
2022 struct frame_info
*frame
= get_current_frame ();
2023 CORE_ADDR new_sp
= FRAME_FP (frame
);
2025 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
2027 write_register (PC_REGNUM
, FRAME_SAVED_PC(frame
));
2028 if (frame
->saved_regs
== NULL
)
2029 mips_find_saved_regs (frame
);
2030 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2032 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2033 && frame
->saved_regs
->regs
[regnum
])
2034 write_register (regnum
,
2035 read_memory_integer (frame
->saved_regs
->regs
[regnum
],
2038 write_register (SP_REGNUM
, new_sp
);
2039 flush_cached_frames ();
2041 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
2043 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2045 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2047 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2049 if (&pi_ptr
->info
== proc_desc
)
2054 error ("Can't locate dummy extra frame info\n");
2056 if (prev_ptr
!= NULL
)
2057 prev_ptr
->next
= pi_ptr
->next
;
2059 linked_proc_desc_table
= pi_ptr
->next
;
2063 write_register (HI_REGNUM
,
2064 read_memory_integer (new_sp
- 2*MIPS_REGSIZE
, MIPS_REGSIZE
));
2065 write_register (LO_REGNUM
,
2066 read_memory_integer (new_sp
- 3*MIPS_REGSIZE
, MIPS_REGSIZE
));
2067 if (mips_fpu
!= MIPS_FPU_NONE
)
2068 write_register (FCRCS_REGNUM
,
2069 read_memory_integer (new_sp
- 4*MIPS_REGSIZE
, MIPS_REGSIZE
));
2074 mips_print_register (regnum
, all
)
2077 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2079 /* Get the data in raw format. */
2080 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2082 printf_filtered ("%s: [Invalid]", reg_names
[regnum
]);
2086 /* If an even floating point register, also print as double. */
2087 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2088 && !((regnum
-FP0_REGNUM
) & 1))
2089 if (REGISTER_RAW_SIZE(regnum
) == 4) /* this would be silly on MIPS64 */
2091 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2093 read_relative_register_raw_bytes (regnum
, dbuffer
);
2094 read_relative_register_raw_bytes (regnum
+1, dbuffer
+MIPS_REGSIZE
);
2095 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2097 printf_filtered ("(d%d: ", regnum
-FP0_REGNUM
);
2098 val_print (builtin_type_double
, dbuffer
, 0,
2099 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2100 printf_filtered ("); ");
2102 fputs_filtered (reg_names
[regnum
], gdb_stdout
);
2104 /* The problem with printing numeric register names (r26, etc.) is that
2105 the user can't use them on input. Probably the best solution is to
2106 fix it so that either the numeric or the funky (a2, etc.) names
2107 are accepted on input. */
2108 if (regnum
< MIPS_NUMREGS
)
2109 printf_filtered ("(r%d): ", regnum
);
2111 printf_filtered (": ");
2113 /* If virtual format is floating, print it that way. */
2114 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2115 if (REGISTER_RAW_SIZE(regnum
) == 8)
2116 { /* show 8-byte floats as float AND double: */
2117 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2119 printf_filtered (" (float) ");
2120 val_print (builtin_type_float
, raw_buffer
+ offset
, 0,
2121 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2122 printf_filtered (", (double) ");
2123 val_print (builtin_type_double
, raw_buffer
, 0,
2124 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2127 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0,
2128 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2129 /* Else print as integer in hex. */
2131 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
2132 'x', 0, gdb_stdout
);
2135 /* Replacement for generic do_registers_info.
2136 Print regs in pretty columns. */
2139 do_fp_register_row (regnum
)
2141 { /* do values for FP (float) regs */
2142 char *raw_buffer
[2];
2144 /* use HI and LO to control the order of combining two flt regs */
2145 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2146 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2147 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2148 int inv1
, inv2
, inv3
;
2150 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2151 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2152 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2154 /* Get the data in raw format. */
2155 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2156 error ("can't read register %d (%s)", regnum
, reg_names
[regnum
]);
2157 if (REGISTER_RAW_SIZE(regnum
) == 4)
2159 /* 4-byte registers: we can fit two registers per row. */
2160 /* Also print every pair of 4-byte regs as an 8-byte double. */
2161 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2162 error ("can't read register %d (%s)",
2163 regnum
+ 1, reg_names
[regnum
+ 1]);
2165 /* copy the two floats into one double, and unpack both */
2166 memcpy (dbl_buffer
, raw_buffer
, sizeof(dbl_buffer
));
2167 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2168 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2169 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2171 printf_filtered (inv1
? " %-5s: <invalid float>" :
2172 " %-5s%-17.9g", reg_names
[regnum
], flt1
);
2173 printf_filtered (inv2
? " %-5s: <invalid float>" :
2174 " %-5s%-17.9g", reg_names
[regnum
+ 1], flt2
);
2175 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2176 " dbl: %-24.17g\n", doub
);
2177 /* may want to do hex display here (future enhancement) */
2181 { /* eight byte registers: print each one as float AND as double. */
2182 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2184 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof(dbl_buffer
));
2185 flt1
= unpack_double (builtin_type_float
,
2186 &raw_buffer
[HI
][offset
], &inv1
);
2187 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2189 printf_filtered (inv1
? " %-5s: <invalid float>" :
2190 " %-5s flt: %-17.9g", reg_names
[regnum
], flt1
);
2191 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2192 " dbl: %-24.17g\n", doub
);
2193 /* may want to do hex display here (future enhancement) */
2199 /* Print a row's worth of GP (int) registers, with name labels above */
2202 do_gp_register_row (regnum
)
2205 /* do values for GP (int) regs */
2206 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2207 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2209 int start_regnum
= regnum
;
2210 int numregs
= NUM_REGS
;
2212 /* start-sanitize-sky */
2213 #ifdef NUM_R5900_REGS
2214 numregs
= NUM_R5900_REGS
;
2216 /* end-sanitize-sky */
2218 /* For GP registers, we print a separate row of names above the vals */
2219 printf_filtered (" ");
2220 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2222 if (*reg_names
[regnum
] == '\0')
2223 continue; /* unused register */
2224 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2225 break; /* end the row: reached FP register */
2226 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2230 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2231 start_regnum
); /* print the R0 to R31 names */
2233 regnum
= start_regnum
; /* go back to start of row */
2234 /* now print the values in hex, 4 or 8 to the row */
2235 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2237 if (*reg_names
[regnum
] == '\0')
2238 continue; /* unused register */
2239 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2240 break; /* end row: reached FP register */
2241 /* OK: get the data in raw format. */
2242 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2243 error ("can't read register %d (%s)", regnum
, reg_names
[regnum
]);
2244 /* pad small registers */
2245 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_RAW_SIZE (regnum
)); byte
++)
2246 printf_filtered (" ");
2247 /* Now print the register value in hex, endian order. */
2248 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2249 for (byte
= 0; byte
< REGISTER_RAW_SIZE (regnum
); byte
++)
2250 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2252 for (byte
= REGISTER_RAW_SIZE (regnum
) - 1; byte
>= 0; byte
--)
2253 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2254 printf_filtered (" ");
2257 if (col
> 0) /* ie. if we actually printed anything... */
2258 printf_filtered ("\n");
2263 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2266 mips_do_registers_info (regnum
, fpregs
)
2270 if (regnum
!= -1) /* do one specified register */
2272 if (*(reg_names
[regnum
]) == '\0')
2273 error ("Not a valid register for the current processor type");
2275 mips_print_register (regnum
, 0);
2276 printf_filtered ("\n");
2278 else /* do all (or most) registers */
2281 while (regnum
< NUM_REGS
)
2283 if (TYPE_CODE(REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2284 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2285 regnum
= do_fp_register_row (regnum
); /* FP regs */
2287 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2289 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2290 /* start-sanitize-sky */
2291 #ifdef NUM_R5900_REGS
2292 /* For the sky project, NUM_REGS includes the vector slaves,
2293 which are handled elsewhere */
2294 if (regnum
>= NUM_R5900_REGS
)
2297 /* end-sanitize-sky */
2302 /* Return number of args passed to a frame. described by FIP.
2303 Can return -1, meaning no way to tell. */
2306 mips_frame_num_args (frame
)
2307 struct frame_info
*frame
;
2309 #if 0 /* FIXME Use or lose this! */
2310 struct chain_info_t
*p
;
2312 p
= mips_find_cached_frame (FRAME_FP (frame
));
2314 return p
->the_info
.numargs
;
2319 /* Is this a branch with a delay slot? */
2321 static int is_delayed
PARAMS ((unsigned long));
2328 for (i
= 0; i
< NUMOPCODES
; ++i
)
2329 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2330 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2332 return (i
< NUMOPCODES
2333 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2334 | INSN_COND_BRANCH_DELAY
2335 | INSN_COND_BRANCH_LIKELY
)));
2339 mips_step_skips_delay (pc
)
2342 char buf
[MIPS_INSTLEN
];
2344 /* There is no branch delay slot on MIPS16. */
2345 if (pc_is_mips16 (pc
))
2348 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2349 /* If error reading memory, guess that it is not a delayed branch. */
2351 return is_delayed ((unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2355 /* Skip the PC past function prologue instructions (32-bit version).
2356 This is a helper function for mips_skip_prologue. */
2359 mips32_skip_prologue (pc
, lenient
)
2360 CORE_ADDR pc
; /* starting PC to search from */
2365 int seen_sp_adjust
= 0;
2366 int load_immediate_bytes
= 0;
2368 /* Skip the typical prologue instructions. These are the stack adjustment
2369 instruction and the instructions that save registers on the stack
2370 or in the gcc frame. */
2371 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2373 unsigned long high_word
;
2375 inst
= mips_fetch_instruction (pc
);
2376 high_word
= (inst
>> 16) & 0xffff;
2379 if (lenient
&& is_delayed (inst
))
2383 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2384 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2386 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2387 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2389 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2390 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2391 && (inst
& 0x001F0000)) /* reg != $zero */
2394 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2396 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2398 continue; /* reg != $zero */
2400 /* move $s8,$sp. With different versions of gas this will be either
2401 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2402 Accept any one of these. */
2403 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2406 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2408 else if (high_word
== 0x3c1c) /* lui $gp,n */
2410 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2412 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2413 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2415 /* The following instructions load $at or $t0 with an immediate
2416 value in preparation for a stack adjustment via
2417 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2418 a local variable, so we accept them only before a stack adjustment
2419 instruction was seen. */
2420 else if (!seen_sp_adjust
)
2422 if (high_word
== 0x3c01 || /* lui $at,n */
2423 high_word
== 0x3c08) /* lui $t0,n */
2425 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2428 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2429 high_word
== 0x3508 || /* ori $t0,$t0,n */
2430 high_word
== 0x3401 || /* ori $at,$zero,n */
2431 high_word
== 0x3408) /* ori $t0,$zero,n */
2433 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2443 /* In a frameless function, we might have incorrectly
2444 skipped some load immediate instructions. Undo the skipping
2445 if the load immediate was not followed by a stack adjustment. */
2446 if (load_immediate_bytes
&& !seen_sp_adjust
)
2447 pc
-= load_immediate_bytes
;
2451 /* Skip the PC past function prologue instructions (16-bit version).
2452 This is a helper function for mips_skip_prologue. */
2455 mips16_skip_prologue (pc
, lenient
)
2456 CORE_ADDR pc
; /* starting PC to search from */
2460 int extend_bytes
= 0;
2461 int prev_extend_bytes
;
2463 /* Table of instructions likely to be found in a function prologue. */
2466 unsigned short inst
;
2467 unsigned short mask
;
2470 { 0x6300, 0xff00 }, /* addiu $sp,offset */
2471 { 0xfb00, 0xff00 }, /* daddiu $sp,offset */
2472 { 0xd000, 0xf800 }, /* sw reg,n($sp) */
2473 { 0xf900, 0xff00 }, /* sd reg,n($sp) */
2474 { 0x6200, 0xff00 }, /* sw $ra,n($sp) */
2475 { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */
2476 { 0x673d, 0xffff }, /* move $s1,sp */
2477 { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */
2478 { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */
2479 { 0xe809, 0xf81f }, /* entry pseudo-op */
2480 { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */
2481 { 0, 0 } /* end of table marker */
2484 /* Skip the typical prologue instructions. These are the stack adjustment
2485 instruction and the instructions that save registers on the stack
2486 or in the gcc frame. */
2487 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2489 unsigned short inst
;
2492 inst
= mips_fetch_instruction (pc
);
2494 /* Normally we ignore an extend instruction. However, if it is
2495 not followed by a valid prologue instruction, we must adjust
2496 the pc back over the extend so that it won't be considered
2497 part of the prologue. */
2498 if ((inst
& 0xf800) == 0xf000) /* extend */
2500 extend_bytes
= MIPS16_INSTLEN
;
2503 prev_extend_bytes
= extend_bytes
;
2506 /* Check for other valid prologue instructions besides extend. */
2507 for (i
= 0; table
[i
].mask
!= 0; i
++)
2508 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2510 if (table
[i
].mask
!= 0) /* it was in table? */
2511 continue; /* ignore it */
2512 else /* non-prologue */
2514 /* Return the current pc, adjusted backwards by 2 if
2515 the previous instruction was an extend. */
2516 return pc
- prev_extend_bytes
;
2522 /* To skip prologues, I use this predicate. Returns either PC itself
2523 if the code at PC does not look like a function prologue; otherwise
2524 returns an address that (if we're lucky) follows the prologue. If
2525 LENIENT, then we must skip everything which is involved in setting
2526 up the frame (it's OK to skip more, just so long as we don't skip
2527 anything which might clobber the registers which are being saved.
2528 We must skip more in the case where part of the prologue is in the
2529 delay slot of a non-prologue instruction). */
2532 mips_skip_prologue (pc
, lenient
)
2536 /* See if we can determine the end of the prologue via the symbol table.
2537 If so, then return either PC, or the PC after the prologue, whichever
2540 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2542 if (post_prologue_pc
!= 0)
2543 return max (pc
, post_prologue_pc
);
2545 /* Can't determine prologue from the symbol table, need to examine
2548 if (pc_is_mips16 (pc
))
2549 return mips16_skip_prologue (pc
, lenient
);
2551 return mips32_skip_prologue (pc
, lenient
);
2555 /* The lenient prologue stuff should be superseded by the code in
2556 init_extra_frame_info which looks to see whether the stores mentioned
2557 in the proc_desc have actually taken place. */
2559 /* Is address PC in the prologue (loosely defined) for function at
2563 mips_in_lenient_prologue (startaddr
, pc
)
2564 CORE_ADDR startaddr
;
2567 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2568 return pc
>= startaddr
&& pc
< end_prologue
;
2572 /* Given a return value in `regbuf' with a type `valtype',
2573 extract and copy its value into `valbuf'. */
2575 mips_extract_return_value (valtype
, regbuf
, valbuf
)
2576 struct type
*valtype
;
2577 char regbuf
[REGISTER_BYTES
];
2582 int len
= TYPE_LENGTH (valtype
);
2585 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2586 && (mips_fpu
== MIPS_FPU_DOUBLE
2587 || (mips_fpu
== MIPS_FPU_SINGLE
&& len
<= MIPS_FPU_SINGLE_REGSIZE
)))
2588 regnum
= FP0_REGNUM
;
2590 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2591 { /* "un-left-justify" the value from the register */
2592 if (len
< REGISTER_RAW_SIZE (regnum
))
2593 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2594 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2595 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2596 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2597 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2598 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2600 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
2601 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
2604 /* Given a return value in `regbuf' with a type `valtype',
2605 write it's value into the appropriate register. */
2607 mips_store_return_value (valtype
, valbuf
)
2608 struct type
*valtype
;
2613 int len
= TYPE_LENGTH (valtype
);
2614 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2617 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2618 && (mips_fpu
== MIPS_FPU_DOUBLE
2619 || (mips_fpu
== MIPS_FPU_SINGLE
&& len
<= MIPS_REGSIZE
)))
2620 regnum
= FP0_REGNUM
;
2622 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2623 { /* "left-justify" the value in the register */
2624 if (len
< REGISTER_RAW_SIZE (regnum
))
2625 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2626 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2627 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2628 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2629 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2630 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2632 memcpy(raw_buffer
+ offset
, valbuf
, len
);
2633 REGISTER_CONVERT_FROM_TYPE(regnum
, valtype
, raw_buffer
);
2634 write_register_bytes(REGISTER_BYTE (regnum
), raw_buffer
,
2635 len
> REGISTER_RAW_SIZE (regnum
) ?
2636 len
: REGISTER_RAW_SIZE (regnum
));
2639 /* Exported procedure: Is PC in the signal trampoline code */
2642 in_sigtramp (pc
, ignore
)
2644 char *ignore
; /* function name */
2646 if (sigtramp_address
== 0)
2648 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
2651 /* Command to set FPU type. mips_fpu_string will have been set to the
2652 user's argument. Set mips_fpu based on mips_fpu_string, and then
2653 canonicalize mips_fpu_string. */
2657 mips_set_fpu_command (args
, from_tty
, c
)
2660 struct cmd_list_element
*c
;
2664 if (mips_fpu_string
== NULL
|| *mips_fpu_string
== '\0')
2665 mips_fpu
= MIPS_FPU_DOUBLE
;
2666 else if (strcasecmp (mips_fpu_string
, "double") == 0
2667 || strcasecmp (mips_fpu_string
, "on") == 0
2668 || strcasecmp (mips_fpu_string
, "1") == 0
2669 || strcasecmp (mips_fpu_string
, "yes") == 0)
2670 mips_fpu
= MIPS_FPU_DOUBLE
;
2671 else if (strcasecmp (mips_fpu_string
, "none") == 0
2672 || strcasecmp (mips_fpu_string
, "off") == 0
2673 || strcasecmp (mips_fpu_string
, "0") == 0
2674 || strcasecmp (mips_fpu_string
, "no") == 0)
2675 mips_fpu
= MIPS_FPU_NONE
;
2676 else if (strcasecmp (mips_fpu_string
, "single") == 0)
2677 mips_fpu
= MIPS_FPU_SINGLE
;
2679 err
= strsave (mips_fpu_string
);
2681 if (mips_fpu_string
!= NULL
)
2682 free (mips_fpu_string
);
2686 case MIPS_FPU_DOUBLE
:
2687 mips_fpu_string
= strsave ("double");
2689 case MIPS_FPU_SINGLE
:
2690 mips_fpu_string
= strsave ("single");
2693 mips_fpu_string
= strsave ("none");
2699 struct cleanup
*cleanups
= make_cleanup (free
, err
);
2700 error ("Unknown FPU type `%s'. Use `double', `none', or `single'.",
2702 do_cleanups (cleanups
);
2707 mips_show_fpu_command (args
, from_tty
, c
)
2710 struct cmd_list_element
*c
;
2714 /* Command to set the processor type. */
2717 mips_set_processor_type_command (args
, from_tty
)
2723 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
2725 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
2726 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2727 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
2729 /* Restore the value. */
2730 tmp_mips_processor_type
= strsave (mips_processor_type
);
2735 if (!mips_set_processor_type (tmp_mips_processor_type
))
2737 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
2738 /* Restore its value. */
2739 tmp_mips_processor_type
= strsave (mips_processor_type
);
2744 mips_show_processor_type_command (args
, from_tty
)
2750 /* Modify the actual processor type. */
2753 mips_set_processor_type (str
)
2761 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2763 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
2765 mips_processor_type
= str
;
2767 for (j
= 0; j
< NUM_REGS
; ++j
)
2768 reg_names
[j
] = mips_processor_type_table
[i
].regnames
[j
];
2772 /* FIXME tweak fpu flag too */
2779 /* Attempt to identify the particular processor model by reading the
2783 mips_read_processor_type ()
2787 prid
= read_register (PRID_REGNUM
);
2789 if ((prid
& ~0xf) == 0x700)
2790 return savestring ("r3041", strlen("r3041"));
2795 /* Just like reinit_frame_cache, but with the right arguments to be
2796 callable as an sfunc. */
2799 reinit_frame_cache_sfunc (args
, from_tty
, c
)
2802 struct cmd_list_element
*c
;
2804 reinit_frame_cache ();
2808 gdb_print_insn_mips (memaddr
, info
)
2810 disassemble_info
*info
;
2812 mips_extra_func_info_t proc_desc
;
2814 /* Search for the function containing this address. Set the low bit
2815 of the address when searching, in case we were given an even address
2816 that is the start of a 16-bit function. If we didn't do this,
2817 the search would fail because the symbol table says the function
2818 starts at an odd address, i.e. 1 byte past the given address. */
2819 memaddr
= ADDR_BITS_REMOVE (memaddr
);
2820 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
2822 /* Make an attempt to determine if this is a 16-bit function. If
2823 the procedure descriptor exists and the address therein is odd,
2824 it's definitely a 16-bit function. Otherwise, we have to just
2825 guess that if the address passed in is odd, it's 16-bits. */
2827 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
2829 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
2831 /* Round down the instruction address to the appropriate boundary. */
2832 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
2834 /* Call the appropriate disassembler based on the target endian-ness. */
2835 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2836 return print_insn_big_mips (memaddr
, info
);
2838 return print_insn_little_mips (memaddr
, info
);
2841 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
2842 counter value to determine whether a 16- or 32-bit breakpoint should be
2843 used. It returns a pointer to a string of bytes that encode a breakpoint
2844 instruction, stores the length of the string to *lenptr, and adjusts pc
2845 (if necessary) to point to the actual memory location where the
2846 breakpoint should be inserted. */
2848 unsigned char *mips_breakpoint_from_pc (pcptr
, lenptr
)
2852 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2854 if (pc_is_mips16 (*pcptr
))
2856 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
2857 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2858 *lenptr
= sizeof(mips16_big_breakpoint
);
2859 return mips16_big_breakpoint
;
2863 static char big_breakpoint
[] = BIG_BREAKPOINT
;
2864 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
2865 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
2867 *lenptr
= sizeof(big_breakpoint
);
2869 if (strcmp (target_shortname
, "mips") == 0)
2870 return idt_big_breakpoint
;
2871 else if (strcmp (target_shortname
, "ddb") == 0
2872 || strcmp (target_shortname
, "pmon") == 0
2873 || strcmp (target_shortname
, "lsi") == 0)
2874 return pmon_big_breakpoint
;
2876 return big_breakpoint
;
2881 if (pc_is_mips16 (*pcptr
))
2883 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
2884 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2885 *lenptr
= sizeof(mips16_little_breakpoint
);
2886 return mips16_little_breakpoint
;
2890 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
2891 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
2892 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
2894 *lenptr
= sizeof(little_breakpoint
);
2896 if (strcmp (target_shortname
, "mips") == 0)
2897 return idt_little_breakpoint
;
2898 else if (strcmp (target_shortname
, "ddb") == 0
2899 || strcmp (target_shortname
, "pmon") == 0
2900 || strcmp (target_shortname
, "lsi") == 0)
2901 return pmon_little_breakpoint
;
2903 return little_breakpoint
;
2908 /* Test whether the PC points to the return instruction at the
2909 end of a function. This implements the ABOUT_TO_RETURN macro. */
2912 mips_about_to_return (pc
)
2915 if (pc_is_mips16 (pc
))
2916 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2917 generates a "jr $ra"; other times it generates code to load
2918 the return address from the stack to an accessible register (such
2919 as $a3), then a "jr" using that register. This second case
2920 is almost impossible to distinguish from an indirect jump
2921 used for switch statements, so we don't even try. */
2922 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2924 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2928 /* If PC is in a mips16 call or return stub, return the address of the target
2929 PC, which is either the callee or the caller. There are several
2930 cases which must be handled:
2932 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
2933 target PC is in $31 ($ra).
2934 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
2935 and the target PC is in $2.
2936 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2937 before the jal instruction, this is effectively a call stub
2938 and the the target PC is in $2. Otherwise this is effectively
2939 a return stub and the target PC is in $18.
2941 See the source code for the stubs in gcc/config/mips/mips16.S for
2944 This function implements the SKIP_TRAMPOLINE_CODE macro.
2952 CORE_ADDR start_addr
;
2954 /* Find the starting address and name of the function containing the PC. */
2955 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2958 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
2959 target PC is in $31 ($ra). */
2960 if (strcmp (name
, "__mips16_ret_sf") == 0
2961 || strcmp (name
, "__mips16_ret_df") == 0)
2962 return read_register (RA_REGNUM
);
2964 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
2966 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
2967 and the target PC is in $2. */
2968 if (name
[19] >= '0' && name
[19] <= '9')
2969 return read_register (2);
2971 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2972 before the jal instruction, this is effectively a call stub
2973 and the the target PC is in $2. Otherwise this is effectively
2974 a return stub and the target PC is in $18. */
2975 else if (name
[19] == 's' || name
[19] == 'd')
2977 if (pc
== start_addr
)
2979 /* Check if the target of the stub is a compiler-generated
2980 stub. Such a stub for a function bar might have a name
2981 like __fn_stub_bar, and might look like this:
2986 la $1,bar (becomes a lui/addiu pair)
2988 So scan down to the lui/addi and extract the target
2989 address from those two instructions. */
2991 CORE_ADDR target_pc
= read_register (2);
2995 /* See if the name of the target function is __fn_stub_*. */
2996 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
2998 if (strncmp (name
, "__fn_stub_", 10) != 0
2999 && strcmp (name
, "etext") != 0
3000 && strcmp (name
, "_etext") != 0)
3003 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3004 The limit on the search is arbitrarily set to 20
3005 instructions. FIXME. */
3006 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3008 inst
= mips_fetch_instruction (target_pc
);
3009 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3010 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3011 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3012 return pc
| (inst
& 0xffff); /* low word */
3015 /* Couldn't find the lui/addui pair, so return stub address. */
3019 /* This is the 'return' part of a call stub. The return
3020 address is in $r18. */
3021 return read_register (18);
3024 return 0; /* not a stub */
3028 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3029 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3032 mips_in_call_stub (pc
, name
)
3036 CORE_ADDR start_addr
;
3038 /* Find the starting address of the function containing the PC. If the
3039 caller didn't give us a name, look it up at the same time. */
3040 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3043 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3045 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3046 if (name
[19] >= '0' && name
[19] <= '9')
3048 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3049 before the jal instruction, this is effectively a call stub. */
3050 else if (name
[19] == 's' || name
[19] == 'd')
3051 return pc
== start_addr
;
3054 return 0; /* not a stub */
3058 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3059 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3062 mips_in_return_stub (pc
, name
)
3066 CORE_ADDR start_addr
;
3068 /* Find the starting address of the function containing the PC. */
3069 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3072 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3073 if (strcmp (name
, "__mips16_ret_sf") == 0
3074 || strcmp (name
, "__mips16_ret_df") == 0)
3077 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3078 i.e. after the jal instruction, this is effectively a return stub. */
3079 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3080 && (name
[19] == 's' || name
[19] == 'd')
3081 && pc
!= start_addr
)
3084 return 0; /* not a stub */
3088 /* Return non-zero if the PC is in a library helper function that should
3089 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3092 mips_ignore_helper (pc
)
3097 /* Find the starting address and name of the function containing the PC. */
3098 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3101 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3102 that we want to ignore. */
3103 return (strcmp (name
, "__mips16_ret_sf") == 0
3104 || strcmp (name
, "__mips16_ret_df") == 0);
3109 _initialize_mips_tdep ()
3111 struct cmd_list_element
*c
;
3113 if (!tm_print_insn
) /* Someone may have already set it */
3114 tm_print_insn
= gdb_print_insn_mips
;
3116 /* Let the user turn off floating point and set the fence post for
3117 heuristic_proc_start. */
3119 c
= add_set_cmd ("mipsfpu", class_support
, var_string_noescape
,
3120 (char *) &mips_fpu_string
,
3121 "Set use of floating point coprocessor.\n\
3122 Set to `none' to avoid using floating point instructions when calling\n\
3123 functions or dealing with return values. Set to `single' to use only\n\
3124 single precision floating point as on the R4650. Set to `double' for\n\
3125 normal floating point support.",
3127 c
->function
.sfunc
= mips_set_fpu_command
;
3128 c
= add_show_from_set (c
, &showlist
);
3129 c
->function
.sfunc
= mips_show_fpu_command
;
3131 #ifndef MIPS_DEFAULT_FPU_TYPE
3132 mips_fpu
= MIPS_FPU_DOUBLE
;
3133 mips_fpu_string
= strsave ("double");
3135 mips_fpu
= MIPS_DEFAULT_FPU_TYPE
;
3138 case MIPS_FPU_DOUBLE
: mips_fpu_string
= strsave ("double"); break;
3139 case MIPS_FPU_SINGLE
: mips_fpu_string
= strsave ("single"); break;
3140 case MIPS_FPU_NONE
: mips_fpu_string
= strsave ("none"); break;
3144 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
3145 (char *) &tmp_mips_processor_type
,
3146 "Set the type of MIPS processor in use.\n\
3147 Set this to be able to access processor-type-specific registers.\n\
3150 c
->function
.cfunc
= mips_set_processor_type_command
;
3151 c
= add_show_from_set (c
, &showlist
);
3152 c
->function
.cfunc
= mips_show_processor_type_command
;
3154 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
3155 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
3157 /* We really would like to have both "0" and "unlimited" work, but
3158 command.c doesn't deal with that. So make it a var_zinteger
3159 because the user can always use "999999" or some such for unlimited. */
3160 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
3161 (char *) &heuristic_fence_post
,
3163 Set the distance searched for the start of a function.\n\
3164 If you are debugging a stripped executable, GDB needs to search through the\n\
3165 program for the start of a function. This command sets the distance of the\n\
3166 search. The only need to set it is when debugging a stripped executable.",
3168 /* We need to throw away the frame cache when we set this, since it
3169 might change our ability to get backtraces. */
3170 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
3171 add_show_from_set (c
, &showlist
);