1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 #include "target-descriptions.h"
60 #include "dwarf2-frame.h"
62 static const struct objfile_data
*mips_pdr_data
;
64 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
66 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
67 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
68 #define ST0_FR (1 << 26)
70 /* The sizes of floating point registers. */
74 MIPS_FPU_SINGLE_REGSIZE
= 4,
75 MIPS_FPU_DOUBLE_REGSIZE
= 8
84 static const char *mips_abi_string
;
86 static const char *mips_abi_strings
[] = {
97 /* Some MIPS boards don't support floating point while others only
98 support single-precision floating-point operations. */
102 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
103 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
104 MIPS_FPU_NONE
/* No floating point. */
107 #ifndef MIPS_DEFAULT_FPU_TYPE
108 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
110 static int mips_fpu_type_auto
= 1;
111 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
113 static int mips_debug
= 0;
115 /* Properties (for struct target_desc) describing the g/G packet
117 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
118 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
120 /* MIPS specific per-architecture information */
123 /* from the elf header */
127 enum mips_abi mips_abi
;
128 enum mips_abi found_abi
;
129 enum mips_fpu_type mips_fpu_type
;
130 int mips_last_arg_regnum
;
131 int mips_last_fp_arg_regnum
;
132 int default_mask_address_p
;
133 /* Is the target using 64-bit raw integer registers but only
134 storing a left-aligned 32-bit value in each? */
135 int mips64_transfers_32bit_regs_p
;
136 /* Indexes for various registers. IRIX and embedded have
137 different values. This contains the "public" fields. Don't
138 add any that do not need to be public. */
139 const struct mips_regnum
*regnum
;
140 /* Register names table for the current register set. */
141 const char **mips_processor_reg_names
;
143 /* The size of register data available from the target, if known.
144 This doesn't quite obsolete the manual
145 mips64_transfers_32bit_regs_p, since that is documented to force
146 left alignment even for big endian (very strange). */
147 int register_size_valid_p
;
152 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
158 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
159 They are implemented as a pair of 64bit doubles where the high
160 part holds the result of the operation rounded to double, and
161 the low double holds the difference between the exact result and
162 the rounded result. So "high" + "low" contains the result with
163 added precision. Unfortunately, the floatformat structure used
164 by GDB is not powerful enough to describe this format. As a temporary
165 measure, we define a 128bit floatformat that only uses the high part.
166 We lose a bit of precision but that's probably the best we can do
167 for now with the current infrastructure. */
169 static const struct floatformat floatformat_n32n64_long_double_big
=
171 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
172 floatformat_intbit_no
,
173 "floatformat_n32n64_long_double_big",
174 n32n64_floatformat_always_valid
177 static const struct floatformat
*floatformats_n32n64_long
[BFD_ENDIAN_UNKNOWN
] =
179 &floatformat_n32n64_long_double_big
,
180 &floatformat_n32n64_long_double_big
183 const struct mips_regnum
*
184 mips_regnum (struct gdbarch
*gdbarch
)
186 return gdbarch_tdep (gdbarch
)->regnum
;
190 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
192 return mips_regnum (gdbarch
)->fp0
+ 12;
195 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
196 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
198 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
200 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
202 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
204 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
205 functions to test, set, or clear bit 0 of addresses. */
208 is_mips16_addr (CORE_ADDR addr
)
214 unmake_mips16_addr (CORE_ADDR addr
)
216 return ((addr
) & ~(CORE_ADDR
) 1);
219 /* Return the contents of register REGNUM as a signed integer. */
222 read_signed_register (int regnum
)
225 regcache_cooked_read_signed (current_regcache
, regnum
, &val
);
230 read_signed_register_pid (int regnum
, ptid_t ptid
)
235 if (ptid_equal (ptid
, inferior_ptid
))
236 return read_signed_register (regnum
);
238 save_ptid
= inferior_ptid
;
240 inferior_ptid
= ptid
;
242 retval
= read_signed_register (regnum
);
244 inferior_ptid
= save_ptid
;
249 /* Return the MIPS ABI associated with GDBARCH. */
251 mips_abi (struct gdbarch
*gdbarch
)
253 return gdbarch_tdep (gdbarch
)->mips_abi
;
257 mips_isa_regsize (struct gdbarch
*gdbarch
)
259 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
261 /* If we know how big the registers are, use that size. */
262 if (tdep
->register_size_valid_p
)
263 return tdep
->register_size
;
265 /* Fall back to the previous behavior. */
266 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
267 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
270 /* Return the currently configured (or set) saved register size. */
273 mips_abi_regsize (struct gdbarch
*gdbarch
)
275 switch (mips_abi (gdbarch
))
277 case MIPS_ABI_EABI32
:
283 case MIPS_ABI_EABI64
:
285 case MIPS_ABI_UNKNOWN
:
288 internal_error (__FILE__
, __LINE__
, _("bad switch"));
292 /* Functions for setting and testing a bit in a minimal symbol that
293 marks it as 16-bit function. The MSB of the minimal symbol's
294 "info" field is used for this purpose.
296 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
297 i.e. refers to a 16-bit function, and sets a "special" bit in a
298 minimal symbol to mark it as a 16-bit function
300 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
303 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
305 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
307 MSYMBOL_INFO (msym
) = (char *)
308 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
309 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
314 msymbol_is_special (struct minimal_symbol
*msym
)
316 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
319 /* XFER a value from the big/little/left end of the register.
320 Depending on the size of the value it might occupy the entire
321 register or just part of it. Make an allowance for this, aligning
322 things accordingly. */
325 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
326 enum bfd_endian endian
, gdb_byte
*in
,
327 const gdb_byte
*out
, int buf_offset
)
330 gdb_assert (reg_num
>= gdbarch_num_regs (current_gdbarch
));
331 /* Need to transfer the left or right part of the register, based on
332 the targets byte order. */
336 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
338 case BFD_ENDIAN_LITTLE
:
341 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
345 internal_error (__FILE__
, __LINE__
, _("bad switch"));
348 fprintf_unfiltered (gdb_stderr
,
349 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
350 reg_num
, reg_offset
, buf_offset
, length
);
351 if (mips_debug
&& out
!= NULL
)
354 fprintf_unfiltered (gdb_stdlog
, "out ");
355 for (i
= 0; i
< length
; i
++)
356 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
359 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
362 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
364 if (mips_debug
&& in
!= NULL
)
367 fprintf_unfiltered (gdb_stdlog
, "in ");
368 for (i
= 0; i
< length
; i
++)
369 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
372 fprintf_unfiltered (gdb_stdlog
, "\n");
375 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
376 compatiblity mode. A return value of 1 means that we have
377 physical 64-bit registers, but should treat them as 32-bit registers. */
380 mips2_fp_compat (void)
382 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
384 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
389 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
390 in all the places we deal with FP registers. PR gdb/413. */
391 /* Otherwise check the FR bit in the status register - it controls
392 the FP compatiblity mode. If it is clear we are in compatibility
394 if ((read_register (MIPS_PS_REGNUM
) & ST0_FR
) == 0)
401 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
403 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
405 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
407 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
409 static struct type
*mips_float_register_type (void);
410 static struct type
*mips_double_register_type (void);
412 /* The list of available "set mips " and "show mips " commands */
414 static struct cmd_list_element
*setmipscmdlist
= NULL
;
415 static struct cmd_list_element
*showmipscmdlist
= NULL
;
417 /* Integer registers 0 thru 31 are handled explicitly by
418 mips_register_name(). Processor specific registers 32 and above
419 are listed in the following tables. */
422 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
426 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
427 "sr", "lo", "hi", "bad", "cause", "pc",
428 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
429 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
430 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
431 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
432 "fsr", "fir", "" /*"fp" */ , "",
433 "", "", "", "", "", "", "", "",
434 "", "", "", "", "", "", "", "",
437 /* Names of IDT R3041 registers. */
439 static const char *mips_r3041_reg_names
[] = {
440 "sr", "lo", "hi", "bad", "cause", "pc",
441 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
442 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
443 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
444 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
445 "fsr", "fir", "", /*"fp" */ "",
446 "", "", "bus", "ccfg", "", "", "", "",
447 "", "", "port", "cmp", "", "", "epc", "prid",
450 /* Names of tx39 registers. */
452 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
453 "sr", "lo", "hi", "bad", "cause", "pc",
454 "", "", "", "", "", "", "", "",
455 "", "", "", "", "", "", "", "",
456 "", "", "", "", "", "", "", "",
457 "", "", "", "", "", "", "", "",
459 "", "", "", "", "", "", "", "",
460 "", "", "config", "cache", "debug", "depc", "epc", ""
463 /* Names of IRIX registers. */
464 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
465 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
466 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
467 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
468 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
469 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
473 /* Return the name of the register corresponding to REGNO. */
475 mips_register_name (int regno
)
477 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
478 /* GPR names for all ABIs other than n32/n64. */
479 static char *mips_gpr_names
[] = {
480 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
481 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
482 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
483 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
486 /* GPR names for n32 and n64 ABIs. */
487 static char *mips_n32_n64_gpr_names
[] = {
488 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
489 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
490 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
491 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
494 enum mips_abi abi
= mips_abi (current_gdbarch
);
496 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
497 but then don't make the raw register names visible. */
498 int rawnum
= regno
% gdbarch_num_regs (current_gdbarch
);
499 if (regno
< gdbarch_num_regs (current_gdbarch
))
502 /* The MIPS integer registers are always mapped from 0 to 31. The
503 names of the registers (which reflects the conventions regarding
504 register use) vary depending on the ABI. */
505 if (0 <= rawnum
&& rawnum
< 32)
507 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
508 return mips_n32_n64_gpr_names
[rawnum
];
510 return mips_gpr_names
[rawnum
];
512 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (current_gdbarch
))
514 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
515 return tdep
->mips_processor_reg_names
[rawnum
- 32];
518 internal_error (__FILE__
, __LINE__
,
519 _("mips_register_name: bad register number %d"), rawnum
);
522 /* Return the groups that a MIPS register can be categorised into. */
525 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
526 struct reggroup
*reggroup
)
531 int rawnum
= regnum
% gdbarch_num_regs (current_gdbarch
);
532 int pseudo
= regnum
/ gdbarch_num_regs (current_gdbarch
);
533 if (reggroup
== all_reggroup
)
535 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
536 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
537 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
538 (gdbarch), as not all architectures are multi-arch. */
539 raw_p
= rawnum
< gdbarch_num_regs (current_gdbarch
);
540 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
542 if (reggroup
== float_reggroup
)
543 return float_p
&& pseudo
;
544 if (reggroup
== vector_reggroup
)
545 return vector_p
&& pseudo
;
546 if (reggroup
== general_reggroup
)
547 return (!vector_p
&& !float_p
) && pseudo
;
548 /* Save the pseudo registers. Need to make certain that any code
549 extracting register values from a saved register cache also uses
551 if (reggroup
== save_reggroup
)
552 return raw_p
&& pseudo
;
553 /* Restore the same pseudo register. */
554 if (reggroup
== restore_reggroup
)
555 return raw_p
&& pseudo
;
559 /* Map the symbol table registers which live in the range [1 *
560 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
561 registers. Take care of alignment and size problems. */
564 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
565 int cookednum
, gdb_byte
*buf
)
567 int rawnum
= cookednum
% gdbarch_num_regs (current_gdbarch
);
568 gdb_assert (cookednum
>= gdbarch_num_regs (current_gdbarch
)
569 && cookednum
< 2 * gdbarch_num_regs (current_gdbarch
));
570 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
571 regcache_raw_read (regcache
, rawnum
, buf
);
572 else if (register_size (gdbarch
, rawnum
) >
573 register_size (gdbarch
, cookednum
))
575 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
576 || gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
577 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
579 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
582 internal_error (__FILE__
, __LINE__
, _("bad register size"));
586 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
587 struct regcache
*regcache
, int cookednum
,
590 int rawnum
= cookednum
% gdbarch_num_regs (current_gdbarch
);
591 gdb_assert (cookednum
>= gdbarch_num_regs (current_gdbarch
)
592 && cookednum
< 2 * gdbarch_num_regs (current_gdbarch
));
593 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
594 regcache_raw_write (regcache
, rawnum
, buf
);
595 else if (register_size (gdbarch
, rawnum
) >
596 register_size (gdbarch
, cookednum
))
598 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
599 || gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
600 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
602 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
605 internal_error (__FILE__
, __LINE__
, _("bad register size"));
608 /* Table to translate MIPS16 register field to actual register number. */
609 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
611 /* Heuristic_proc_start may hunt through the text section for a long
612 time across a 2400 baud serial line. Allows the user to limit this
615 static unsigned int heuristic_fence_post
= 0;
617 /* Number of bytes of storage in the actual machine representation for
618 register N. NOTE: This defines the pseudo register type so need to
619 rebuild the architecture vector. */
621 static int mips64_transfers_32bit_regs_p
= 0;
624 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
625 struct cmd_list_element
*c
)
627 struct gdbarch_info info
;
628 gdbarch_info_init (&info
);
629 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
630 instead of relying on globals. Doing that would let generic code
631 handle the search for this specific architecture. */
632 if (!gdbarch_update_p (info
))
634 mips64_transfers_32bit_regs_p
= 0;
635 error (_("32-bit compatibility mode not supported"));
639 /* Convert to/from a register and the corresponding memory value. */
642 mips_convert_register_p (int regnum
, struct type
*type
)
644 return (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
645 && register_size (current_gdbarch
, regnum
) == 4
646 && (regnum
% gdbarch_num_regs (current_gdbarch
))
647 >= mips_regnum (current_gdbarch
)->fp0
648 && (regnum
% gdbarch_num_regs (current_gdbarch
))
649 < mips_regnum (current_gdbarch
)->fp0
+ 32
650 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
654 mips_register_to_value (struct frame_info
*frame
, int regnum
,
655 struct type
*type
, gdb_byte
*to
)
657 get_frame_register (frame
, regnum
+ 0, to
+ 4);
658 get_frame_register (frame
, regnum
+ 1, to
+ 0);
662 mips_value_to_register (struct frame_info
*frame
, int regnum
,
663 struct type
*type
, const gdb_byte
*from
)
665 put_frame_register (frame
, regnum
+ 0, from
+ 4);
666 put_frame_register (frame
, regnum
+ 1, from
+ 0);
669 /* Return the GDB type object for the "standard" data type of data in
673 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
675 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (current_gdbarch
));
676 if ((regnum
% gdbarch_num_regs (current_gdbarch
))
677 >= mips_regnum (current_gdbarch
)->fp0
678 && (regnum
% gdbarch_num_regs (current_gdbarch
))
679 < mips_regnum (current_gdbarch
)->fp0
+ 32)
681 /* The floating-point registers raw, or cooked, always match
682 mips_isa_regsize(), and also map 1:1, byte for byte. */
683 if (mips_isa_regsize (gdbarch
) == 4)
684 return builtin_type_ieee_single
;
686 return builtin_type_ieee_double
;
688 else if (regnum
< gdbarch_num_regs (current_gdbarch
))
690 /* The raw or ISA registers. These are all sized according to
692 if (mips_isa_regsize (gdbarch
) == 4)
693 return builtin_type_int32
;
695 return builtin_type_int64
;
699 /* The cooked or ABI registers. These are sized according to
700 the ABI (with a few complications). */
701 if (regnum
>= (gdbarch_num_regs (current_gdbarch
)
702 + mips_regnum (current_gdbarch
)->fp_control_status
)
703 && regnum
<= gdbarch_num_regs (current_gdbarch
)
704 + MIPS_LAST_EMBED_REGNUM
)
705 /* The pseudo/cooked view of the embedded registers is always
706 32-bit. The raw view is handled below. */
707 return builtin_type_int32
;
708 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
709 /* The target, while possibly using a 64-bit register buffer,
710 is only transfering 32-bits of each integer register.
711 Reflect this in the cooked/pseudo (ABI) register value. */
712 return builtin_type_int32
;
713 else if (mips_abi_regsize (gdbarch
) == 4)
714 /* The ABI is restricted to 32-bit registers (the ISA could be
716 return builtin_type_int32
;
719 return builtin_type_int64
;
724 /* Should the upper word of 64-bit addresses be zeroed? */
725 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
728 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
730 switch (mask_address_var
)
732 case AUTO_BOOLEAN_TRUE
:
734 case AUTO_BOOLEAN_FALSE
:
737 case AUTO_BOOLEAN_AUTO
:
738 return tdep
->default_mask_address_p
;
740 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
746 show_mask_address (struct ui_file
*file
, int from_tty
,
747 struct cmd_list_element
*c
, const char *value
)
749 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
751 deprecated_show_value_hack (file
, from_tty
, c
, value
);
752 switch (mask_address_var
)
754 case AUTO_BOOLEAN_TRUE
:
755 printf_filtered ("The 32 bit mips address mask is enabled\n");
757 case AUTO_BOOLEAN_FALSE
:
758 printf_filtered ("The 32 bit mips address mask is disabled\n");
760 case AUTO_BOOLEAN_AUTO
:
762 ("The 32 bit address mask is set automatically. Currently %s\n",
763 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
766 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
771 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
774 mips_pc_is_mips16 (CORE_ADDR memaddr
)
776 struct minimal_symbol
*sym
;
778 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
779 if (is_mips16_addr (memaddr
))
782 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
783 the high bit of the info field. Use this to decide if the function is
784 MIPS16 or normal MIPS. */
785 sym
= lookup_minimal_symbol_by_pc (memaddr
);
787 return msymbol_is_special (sym
);
792 /* MIPS believes that the PC has a sign extended value. Perhaps the
793 all registers should be sign extended for simplicity? */
796 mips_read_pc (ptid_t ptid
)
798 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
802 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
804 return frame_unwind_register_signed (next_frame
,
805 gdbarch_num_regs (current_gdbarch
)
806 + mips_regnum (gdbarch
)->pc
);
810 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
812 return frame_unwind_register_signed (next_frame
,
813 gdbarch_num_regs (current_gdbarch
)
817 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
818 dummy frame. The frame ID's base needs to match the TOS value
819 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
822 static struct frame_id
823 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
825 return frame_id_build
826 (frame_unwind_register_signed (next_frame
,
827 gdbarch_num_regs (current_gdbarch
)
829 frame_pc_unwind (next_frame
));
833 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
835 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
838 /* Fetch and return instruction from the specified location. If the PC
839 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
842 mips_fetch_instruction (CORE_ADDR addr
)
844 gdb_byte buf
[MIPS_INSN32_SIZE
];
848 if (mips_pc_is_mips16 (addr
))
850 instlen
= MIPS_INSN16_SIZE
;
851 addr
= unmake_mips16_addr (addr
);
854 instlen
= MIPS_INSN32_SIZE
;
855 status
= read_memory_nobpt (addr
, buf
, instlen
);
857 memory_error (status
, addr
);
858 return extract_unsigned_integer (buf
, instlen
);
861 /* These the fields of 32 bit mips instructions */
862 #define mips32_op(x) (x >> 26)
863 #define itype_op(x) (x >> 26)
864 #define itype_rs(x) ((x >> 21) & 0x1f)
865 #define itype_rt(x) ((x >> 16) & 0x1f)
866 #define itype_immediate(x) (x & 0xffff)
868 #define jtype_op(x) (x >> 26)
869 #define jtype_target(x) (x & 0x03ffffff)
871 #define rtype_op(x) (x >> 26)
872 #define rtype_rs(x) ((x >> 21) & 0x1f)
873 #define rtype_rt(x) ((x >> 16) & 0x1f)
874 #define rtype_rd(x) ((x >> 11) & 0x1f)
875 #define rtype_shamt(x) ((x >> 6) & 0x1f)
876 #define rtype_funct(x) (x & 0x3f)
879 mips32_relative_offset (ULONGEST inst
)
881 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
884 /* Determine where to set a single step breakpoint while considering
885 branch prediction. */
887 mips32_next_pc (CORE_ADDR pc
)
891 inst
= mips_fetch_instruction (pc
);
892 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
894 if (itype_op (inst
) >> 2 == 5)
895 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
897 op
= (itype_op (inst
) & 0x03);
912 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
913 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
915 int tf
= itype_rt (inst
) & 0x01;
916 int cnum
= itype_rt (inst
) >> 2;
918 read_signed_register (mips_regnum (current_gdbarch
)->
920 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
922 if (((cond
>> cnum
) & 0x01) == tf
)
923 pc
+= mips32_relative_offset (inst
) + 4;
928 pc
+= 4; /* Not a branch, next instruction is easy */
931 { /* This gets way messy */
933 /* Further subdivide into SPECIAL, REGIMM and other */
934 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
936 case 0: /* SPECIAL */
937 op
= rtype_funct (inst
);
942 /* Set PC to that address */
943 pc
= read_signed_register (rtype_rs (inst
));
949 break; /* end SPECIAL */
952 op
= itype_rt (inst
); /* branch condition */
957 case 16: /* BLTZAL */
958 case 18: /* BLTZALL */
960 if (read_signed_register (itype_rs (inst
)) < 0)
961 pc
+= mips32_relative_offset (inst
) + 4;
963 pc
+= 8; /* after the delay slot */
967 case 17: /* BGEZAL */
968 case 19: /* BGEZALL */
969 if (read_signed_register (itype_rs (inst
)) >= 0)
970 pc
+= mips32_relative_offset (inst
) + 4;
972 pc
+= 8; /* after the delay slot */
974 /* All of the other instructions in the REGIMM category */
979 break; /* end REGIMM */
984 reg
= jtype_target (inst
) << 2;
985 /* Upper four bits get never changed... */
986 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
989 /* FIXME case JALX : */
992 reg
= jtype_target (inst
) << 2;
993 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
994 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
996 break; /* The new PC will be alternate mode */
997 case 4: /* BEQ, BEQL */
999 if (read_signed_register (itype_rs (inst
)) ==
1000 read_signed_register (itype_rt (inst
)))
1001 pc
+= mips32_relative_offset (inst
) + 4;
1005 case 5: /* BNE, BNEL */
1007 if (read_signed_register (itype_rs (inst
)) !=
1008 read_signed_register (itype_rt (inst
)))
1009 pc
+= mips32_relative_offset (inst
) + 4;
1013 case 6: /* BLEZ, BLEZL */
1014 if (read_signed_register (itype_rs (inst
)) <= 0)
1015 pc
+= mips32_relative_offset (inst
) + 4;
1021 greater_branch
: /* BGTZ, BGTZL */
1022 if (read_signed_register (itype_rs (inst
)) > 0)
1023 pc
+= mips32_relative_offset (inst
) + 4;
1030 } /* mips32_next_pc */
1032 /* Decoding the next place to set a breakpoint is irregular for the
1033 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1034 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1035 We dont want to set a single step instruction on the extend instruction
1039 /* Lots of mips16 instruction formats */
1040 /* Predicting jumps requires itype,ritype,i8type
1041 and their extensions extItype,extritype,extI8type
1043 enum mips16_inst_fmts
1045 itype
, /* 0 immediate 5,10 */
1046 ritype
, /* 1 5,3,8 */
1047 rrtype
, /* 2 5,3,3,5 */
1048 rritype
, /* 3 5,3,3,5 */
1049 rrrtype
, /* 4 5,3,3,3,2 */
1050 rriatype
, /* 5 5,3,3,1,4 */
1051 shifttype
, /* 6 5,3,3,3,2 */
1052 i8type
, /* 7 5,3,8 */
1053 i8movtype
, /* 8 5,3,3,5 */
1054 i8mov32rtype
, /* 9 5,3,5,3 */
1055 i64type
, /* 10 5,3,8 */
1056 ri64type
, /* 11 5,3,3,5 */
1057 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1058 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1059 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1060 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1061 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1062 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1063 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1064 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1065 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1066 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1068 /* I am heaping all the fields of the formats into one structure and
1069 then, only the fields which are involved in instruction extension */
1073 unsigned int regx
; /* Function in i8 type */
1078 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1079 for the bits which make up the immediatate extension. */
1082 extended_offset (unsigned int extension
)
1085 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1087 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1089 value
|= extension
& 0x01f; /* extract 4:0 */
1093 /* Only call this function if you know that this is an extendable
1094 instruction, It wont malfunction, but why make excess remote memory references?
1095 If the immediate operands get sign extended or somthing, do it after
1096 the extension is performed.
1098 /* FIXME: Every one of these cases needs to worry about sign extension
1099 when the offset is to be used in relative addressing */
1103 fetch_mips_16 (CORE_ADDR pc
)
1106 pc
&= 0xfffffffe; /* clear the low order bit */
1107 target_read_memory (pc
, buf
, 2);
1108 return extract_unsigned_integer (buf
, 2);
1112 unpack_mips16 (CORE_ADDR pc
,
1113 unsigned int extension
,
1115 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1120 switch (insn_format
)
1127 value
= extended_offset (extension
);
1128 value
= value
<< 11; /* rom for the original value */
1129 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1133 value
= inst
& 0x7ff;
1134 /* FIXME : Consider sign extension */
1143 { /* A register identifier and an offset */
1144 /* Most of the fields are the same as I type but the
1145 immediate value is of a different length */
1149 value
= extended_offset (extension
);
1150 value
= value
<< 8; /* from the original instruction */
1151 value
|= inst
& 0xff; /* eleven bits from instruction */
1152 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1153 if (value
& 0x4000) /* test the sign bit , bit 26 */
1155 value
&= ~0x3fff; /* remove the sign bit */
1161 value
= inst
& 0xff; /* 8 bits */
1162 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1163 /* FIXME: Do sign extension , this format needs it */
1164 if (value
& 0x80) /* THIS CONFUSES ME */
1166 value
&= 0xef; /* remove the sign bit */
1176 unsigned long value
;
1177 unsigned int nexthalf
;
1178 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1179 value
= value
<< 16;
1180 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1188 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1190 upk
->offset
= offset
;
1197 add_offset_16 (CORE_ADDR pc
, int offset
)
1199 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1203 extended_mips16_next_pc (CORE_ADDR pc
,
1204 unsigned int extension
, unsigned int insn
)
1206 int op
= (insn
>> 11);
1209 case 2: /* Branch */
1212 struct upk_mips16 upk
;
1213 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1214 offset
= upk
.offset
;
1220 pc
+= (offset
<< 1) + 2;
1223 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1225 struct upk_mips16 upk
;
1226 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1227 pc
= add_offset_16 (pc
, upk
.offset
);
1228 if ((insn
>> 10) & 0x01) /* Exchange mode */
1229 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1236 struct upk_mips16 upk
;
1238 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1239 reg
= read_signed_register (upk
.regx
);
1241 pc
+= (upk
.offset
<< 1) + 2;
1248 struct upk_mips16 upk
;
1250 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1251 reg
= read_signed_register (upk
.regx
);
1253 pc
+= (upk
.offset
<< 1) + 2;
1258 case 12: /* I8 Formats btez btnez */
1260 struct upk_mips16 upk
;
1262 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1263 /* upk.regx contains the opcode */
1264 reg
= read_signed_register (24); /* Test register is 24 */
1265 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1266 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1267 /* pc = add_offset_16(pc,upk.offset) ; */
1268 pc
+= (upk
.offset
<< 1) + 2;
1273 case 29: /* RR Formats JR, JALR, JALR-RA */
1275 struct upk_mips16 upk
;
1276 /* upk.fmt = rrtype; */
1281 upk
.regx
= (insn
>> 8) & 0x07;
1282 upk
.regy
= (insn
>> 5) & 0x07;
1290 break; /* Function return instruction */
1296 break; /* BOGUS Guess */
1298 pc
= read_signed_register (reg
);
1305 /* This is an instruction extension. Fetch the real instruction
1306 (which follows the extension) and decode things based on
1310 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1323 mips16_next_pc (CORE_ADDR pc
)
1325 unsigned int insn
= fetch_mips_16 (pc
);
1326 return extended_mips16_next_pc (pc
, 0, insn
);
1329 /* The mips_next_pc function supports single_step when the remote
1330 target monitor or stub is not developed enough to do a single_step.
1331 It works by decoding the current instruction and predicting where a
1332 branch will go. This isnt hard because all the data is available.
1333 The MIPS32 and MIPS16 variants are quite different */
1335 mips_next_pc (CORE_ADDR pc
)
1338 return mips16_next_pc (pc
);
1340 return mips32_next_pc (pc
);
1343 struct mips_frame_cache
1346 struct trad_frame_saved_reg
*saved_regs
;
1349 /* Set a register's saved stack address in temp_saved_regs. If an
1350 address has already been set for this register, do nothing; this
1351 way we will only recognize the first save of a given register in a
1354 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1355 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1356 Strictly speaking, only the second range is used as it is only second
1357 range (the ABI instead of ISA registers) that comes into play when finding
1358 saved registers in a frame. */
1361 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1364 if (this_cache
!= NULL
1365 && this_cache
->saved_regs
[regnum
].addr
== -1)
1367 this_cache
->saved_regs
[regnum
1368 + 0 * gdbarch_num_regs (current_gdbarch
)].addr
1370 this_cache
->saved_regs
[regnum
1371 + 1 * gdbarch_num_regs (current_gdbarch
)].addr
1377 /* Fetch the immediate value from a MIPS16 instruction.
1378 If the previous instruction was an EXTEND, use it to extend
1379 the upper bits of the immediate value. This is a helper function
1380 for mips16_scan_prologue. */
1383 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1384 unsigned short inst
, /* current instruction */
1385 int nbits
, /* number of bits in imm field */
1386 int scale
, /* scale factor to be applied to imm */
1387 int is_signed
) /* is the imm field signed? */
1391 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1393 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1394 if (offset
& 0x8000) /* check for negative extend */
1395 offset
= 0 - (0x10000 - (offset
& 0xffff));
1396 return offset
| (inst
& 0x1f);
1400 int max_imm
= 1 << nbits
;
1401 int mask
= max_imm
- 1;
1402 int sign_bit
= max_imm
>> 1;
1404 offset
= inst
& mask
;
1405 if (is_signed
&& (offset
& sign_bit
))
1406 offset
= 0 - (max_imm
- offset
);
1407 return offset
* scale
;
1412 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1413 the associated FRAME_CACHE if not null.
1414 Return the address of the first instruction past the prologue. */
1417 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1418 struct frame_info
*next_frame
,
1419 struct mips_frame_cache
*this_cache
)
1422 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1424 long frame_offset
= 0; /* Size of stack frame. */
1425 long frame_adjust
= 0; /* Offset of FP from SP. */
1426 int frame_reg
= MIPS_SP_REGNUM
;
1427 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1428 unsigned inst
= 0; /* current instruction */
1429 unsigned entry_inst
= 0; /* the entry instruction */
1432 int extend_bytes
= 0;
1433 int prev_extend_bytes
;
1434 CORE_ADDR end_prologue_addr
= 0;
1436 /* Can be called when there's no process, and hence when there's no
1438 if (next_frame
!= NULL
)
1439 sp
= read_next_frame_reg (next_frame
, gdbarch_num_regs (current_gdbarch
)
1444 if (limit_pc
> start_pc
+ 200)
1445 limit_pc
= start_pc
+ 200;
1447 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1449 /* Save the previous instruction. If it's an EXTEND, we'll extract
1450 the immediate offset extension from it in mips16_get_imm. */
1453 /* Fetch and decode the instruction. */
1454 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1456 /* Normally we ignore extend instructions. However, if it is
1457 not followed by a valid prologue instruction, then this
1458 instruction is not part of the prologue either. We must
1459 remember in this case to adjust the end_prologue_addr back
1461 if ((inst
& 0xf800) == 0xf000) /* extend */
1463 extend_bytes
= MIPS_INSN16_SIZE
;
1467 prev_extend_bytes
= extend_bytes
;
1470 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1471 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1473 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1474 if (offset
< 0) /* negative stack adjustment? */
1475 frame_offset
-= offset
;
1477 /* Exit loop if a positive stack adjustment is found, which
1478 usually means that the stack cleanup code in the function
1479 epilogue is reached. */
1482 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1484 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1485 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1486 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1488 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1490 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1491 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1492 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1494 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1496 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1497 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1499 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1501 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1502 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1504 else if (inst
== 0x673d) /* move $s1, $sp */
1509 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1511 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1512 frame_addr
= sp
+ offset
;
1514 frame_adjust
= offset
;
1516 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1518 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1519 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1520 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1522 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1524 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1525 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1526 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1528 else if ((inst
& 0xf81f) == 0xe809
1529 && (inst
& 0x700) != 0x700) /* entry */
1530 entry_inst
= inst
; /* save for later processing */
1531 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1532 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1533 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1535 /* This instruction is part of the prologue, but we don't
1536 need to do anything special to handle it. */
1540 /* This instruction is not an instruction typically found
1541 in a prologue, so we must have reached the end of the
1543 if (end_prologue_addr
== 0)
1544 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1548 /* The entry instruction is typically the first instruction in a function,
1549 and it stores registers at offsets relative to the value of the old SP
1550 (before the prologue). But the value of the sp parameter to this
1551 function is the new SP (after the prologue has been executed). So we
1552 can't calculate those offsets until we've seen the entire prologue,
1553 and can calculate what the old SP must have been. */
1554 if (entry_inst
!= 0)
1556 int areg_count
= (entry_inst
>> 8) & 7;
1557 int sreg_count
= (entry_inst
>> 6) & 3;
1559 /* The entry instruction always subtracts 32 from the SP. */
1562 /* Now we can calculate what the SP must have been at the
1563 start of the function prologue. */
1566 /* Check if a0-a3 were saved in the caller's argument save area. */
1567 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1569 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1570 offset
+= mips_abi_regsize (current_gdbarch
);
1573 /* Check if the ra register was pushed on the stack. */
1575 if (entry_inst
& 0x20)
1577 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1578 offset
-= mips_abi_regsize (current_gdbarch
);
1581 /* Check if the s0 and s1 registers were pushed on the stack. */
1582 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1584 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1585 offset
-= mips_abi_regsize (current_gdbarch
);
1589 if (this_cache
!= NULL
)
1592 (frame_unwind_register_signed (next_frame
,
1593 gdbarch_num_regs (current_gdbarch
)
1595 + frame_offset
- frame_adjust
);
1596 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1597 be able to get rid of the assignment below, evetually. But it's
1598 still needed for now. */
1599 this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1600 + mips_regnum (current_gdbarch
)->pc
]
1601 = this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1605 /* If we didn't reach the end of the prologue when scanning the function
1606 instructions, then set end_prologue_addr to the address of the
1607 instruction immediately after the last one we scanned. */
1608 if (end_prologue_addr
== 0)
1609 end_prologue_addr
= cur_pc
;
1611 return end_prologue_addr
;
1614 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1615 Procedures that use the 32-bit instruction set are handled by the
1616 mips_insn32 unwinder. */
1618 static struct mips_frame_cache
*
1619 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1621 struct mips_frame_cache
*cache
;
1623 if ((*this_cache
) != NULL
)
1624 return (*this_cache
);
1625 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1626 (*this_cache
) = cache
;
1627 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1629 /* Analyze the function prologue. */
1631 const CORE_ADDR pc
=
1632 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1633 CORE_ADDR start_addr
;
1635 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1636 if (start_addr
== 0)
1637 start_addr
= heuristic_proc_start (pc
);
1638 /* We can't analyze the prologue if we couldn't find the begining
1640 if (start_addr
== 0)
1643 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1646 /* SP_REGNUM, contains the value and not the address. */
1647 trad_frame_set_value (cache
->saved_regs
, gdbarch_num_regs (current_gdbarch
)
1648 + MIPS_SP_REGNUM
, cache
->base
);
1650 return (*this_cache
);
1654 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1655 struct frame_id
*this_id
)
1657 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1659 (*this_id
) = frame_id_build (info
->base
,
1660 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1664 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1666 int regnum
, int *optimizedp
,
1667 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1668 int *realnump
, gdb_byte
*valuep
)
1670 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1672 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1673 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1676 static const struct frame_unwind mips_insn16_frame_unwind
=
1679 mips_insn16_frame_this_id
,
1680 mips_insn16_frame_prev_register
1683 static const struct frame_unwind
*
1684 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1686 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1687 if (mips_pc_is_mips16 (pc
))
1688 return &mips_insn16_frame_unwind
;
1693 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1696 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1701 static const struct frame_base mips_insn16_frame_base
=
1703 &mips_insn16_frame_unwind
,
1704 mips_insn16_frame_base_address
,
1705 mips_insn16_frame_base_address
,
1706 mips_insn16_frame_base_address
1709 static const struct frame_base
*
1710 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1712 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1713 return &mips_insn16_frame_base
;
1718 /* Mark all the registers as unset in the saved_regs array
1719 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1722 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1724 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1728 const int num_regs
= gdbarch_num_regs (current_gdbarch
);
1731 for (i
= 0; i
< num_regs
; i
++)
1733 this_cache
->saved_regs
[i
].addr
= -1;
1738 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1739 the associated FRAME_CACHE if not null.
1740 Return the address of the first instruction past the prologue. */
1743 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1744 struct frame_info
*next_frame
,
1745 struct mips_frame_cache
*this_cache
)
1748 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1751 int frame_reg
= MIPS_SP_REGNUM
;
1753 CORE_ADDR end_prologue_addr
= 0;
1754 int seen_sp_adjust
= 0;
1755 int load_immediate_bytes
= 0;
1757 /* Can be called when there's no process, and hence when there's no
1759 if (next_frame
!= NULL
)
1760 sp
= read_next_frame_reg (next_frame
, gdbarch_num_regs (current_gdbarch
)
1765 if (limit_pc
> start_pc
+ 200)
1766 limit_pc
= start_pc
+ 200;
1771 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1773 unsigned long inst
, high_word
, low_word
;
1776 /* Fetch the instruction. */
1777 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1779 /* Save some code by pre-extracting some useful fields. */
1780 high_word
= (inst
>> 16) & 0xffff;
1781 low_word
= inst
& 0xffff;
1782 reg
= high_word
& 0x1f;
1784 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1785 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1786 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1788 if (low_word
& 0x8000) /* negative stack adjustment? */
1789 frame_offset
+= 0x10000 - low_word
;
1791 /* Exit loop if a positive stack adjustment is found, which
1792 usually means that the stack cleanup code in the function
1793 epilogue is reached. */
1797 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1799 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1801 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1803 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1804 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1806 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1808 /* Old gcc frame, r30 is virtual frame pointer. */
1809 if ((long) low_word
!= frame_offset
)
1810 frame_addr
= sp
+ low_word
;
1811 else if (frame_reg
== MIPS_SP_REGNUM
)
1813 unsigned alloca_adjust
;
1816 frame_addr
= read_next_frame_reg (next_frame
,
1818 (current_gdbarch
) + 30);
1819 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1820 if (alloca_adjust
> 0)
1822 /* FP > SP + frame_size. This may be because of
1823 an alloca or somethings similar. Fix sp to
1824 "pre-alloca" value, and try again. */
1825 sp
+= alloca_adjust
;
1826 /* Need to reset the status of all registers. Otherwise,
1827 we will hit a guard that prevents the new address
1828 for each register to be recomputed during the second
1830 reset_saved_regs (this_cache
);
1835 /* move $30,$sp. With different versions of gas this will be either
1836 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1837 Accept any one of these. */
1838 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1840 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1841 if (frame_reg
== MIPS_SP_REGNUM
)
1843 unsigned alloca_adjust
;
1846 frame_addr
= read_next_frame_reg (next_frame
,
1848 (current_gdbarch
) + 30);
1849 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1850 if (alloca_adjust
> 0)
1852 /* FP > SP + frame_size. This may be because of
1853 an alloca or somethings similar. Fix sp to
1854 "pre-alloca" value, and try again. */
1856 /* Need to reset the status of all registers. Otherwise,
1857 we will hit a guard that prevents the new address
1858 for each register to be recomputed during the second
1860 reset_saved_regs (this_cache
);
1865 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1867 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
1869 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1870 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1871 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1872 || high_word
== 0x3c1c /* lui $gp,n */
1873 || high_word
== 0x279c /* addiu $gp,$gp,n */
1874 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1875 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
1878 /* These instructions are part of the prologue, but we don't
1879 need to do anything special to handle them. */
1881 /* The instructions below load $at or $t0 with an immediate
1882 value in preparation for a stack adjustment via
1883 subu $sp,$sp,[$at,$t0]. These instructions could also
1884 initialize a local variable, so we accept them only before
1885 a stack adjustment instruction was seen. */
1886 else if (!seen_sp_adjust
1887 && (high_word
== 0x3c01 /* lui $at,n */
1888 || high_word
== 0x3c08 /* lui $t0,n */
1889 || high_word
== 0x3421 /* ori $at,$at,n */
1890 || high_word
== 0x3508 /* ori $t0,$t0,n */
1891 || high_word
== 0x3401 /* ori $at,$zero,n */
1892 || high_word
== 0x3408 /* ori $t0,$zero,n */
1895 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
1899 /* This instruction is not an instruction typically found
1900 in a prologue, so we must have reached the end of the
1902 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
1903 loop now? Why would we need to continue scanning the function
1905 if (end_prologue_addr
== 0)
1906 end_prologue_addr
= cur_pc
;
1910 if (this_cache
!= NULL
)
1913 (frame_unwind_register_signed (next_frame
,
1914 gdbarch_num_regs (current_gdbarch
)
1917 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
1918 this assignment below, eventually. But it's still needed
1920 this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1921 + mips_regnum (current_gdbarch
)->pc
]
1922 = this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1926 /* If we didn't reach the end of the prologue when scanning the function
1927 instructions, then set end_prologue_addr to the address of the
1928 instruction immediately after the last one we scanned. */
1929 /* brobecker/2004-10-10: I don't think this would ever happen, but
1930 we may as well be careful and do our best if we have a null
1931 end_prologue_addr. */
1932 if (end_prologue_addr
== 0)
1933 end_prologue_addr
= cur_pc
;
1935 /* In a frameless function, we might have incorrectly
1936 skipped some load immediate instructions. Undo the skipping
1937 if the load immediate was not followed by a stack adjustment. */
1938 if (load_immediate_bytes
&& !seen_sp_adjust
)
1939 end_prologue_addr
-= load_immediate_bytes
;
1941 return end_prologue_addr
;
1944 /* Heuristic unwinder for procedures using 32-bit instructions (covers
1945 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
1946 instructions (a.k.a. MIPS16) are handled by the mips_insn16
1949 static struct mips_frame_cache
*
1950 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1952 struct mips_frame_cache
*cache
;
1954 if ((*this_cache
) != NULL
)
1955 return (*this_cache
);
1957 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1958 (*this_cache
) = cache
;
1959 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1961 /* Analyze the function prologue. */
1963 const CORE_ADDR pc
=
1964 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1965 CORE_ADDR start_addr
;
1967 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1968 if (start_addr
== 0)
1969 start_addr
= heuristic_proc_start (pc
);
1970 /* We can't analyze the prologue if we couldn't find the begining
1972 if (start_addr
== 0)
1975 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1978 /* SP_REGNUM, contains the value and not the address. */
1979 trad_frame_set_value (cache
->saved_regs
,
1980 gdbarch_num_regs (current_gdbarch
) + MIPS_SP_REGNUM
,
1983 return (*this_cache
);
1987 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1988 struct frame_id
*this_id
)
1990 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1992 (*this_id
) = frame_id_build (info
->base
,
1993 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1997 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
1999 int regnum
, int *optimizedp
,
2000 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2001 int *realnump
, gdb_byte
*valuep
)
2003 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2005 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2006 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2009 static const struct frame_unwind mips_insn32_frame_unwind
=
2012 mips_insn32_frame_this_id
,
2013 mips_insn32_frame_prev_register
2016 static const struct frame_unwind
*
2017 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2019 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2020 if (! mips_pc_is_mips16 (pc
))
2021 return &mips_insn32_frame_unwind
;
2026 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2029 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2034 static const struct frame_base mips_insn32_frame_base
=
2036 &mips_insn32_frame_unwind
,
2037 mips_insn32_frame_base_address
,
2038 mips_insn32_frame_base_address
,
2039 mips_insn32_frame_base_address
2042 static const struct frame_base
*
2043 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2045 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2046 return &mips_insn32_frame_base
;
2051 static struct trad_frame_cache
*
2052 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2055 CORE_ADDR start_addr
;
2056 CORE_ADDR stack_addr
;
2057 struct trad_frame_cache
*this_trad_cache
;
2059 if ((*this_cache
) != NULL
)
2060 return (*this_cache
);
2061 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2062 (*this_cache
) = this_trad_cache
;
2064 /* The return address is in the link register. */
2065 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, MIPS_RA_REGNUM
);
2067 /* Frame ID, since it's a frameless / stackless function, no stack
2068 space is allocated and SP on entry is the current SP. */
2069 pc
= frame_pc_unwind (next_frame
);
2070 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2071 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2072 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2074 /* Assume that the frame's base is the same as the
2076 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2078 return this_trad_cache
;
2082 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2083 struct frame_id
*this_id
)
2085 struct trad_frame_cache
*this_trad_cache
2086 = mips_stub_frame_cache (next_frame
, this_cache
);
2087 trad_frame_get_id (this_trad_cache
, this_id
);
2091 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2093 int regnum
, int *optimizedp
,
2094 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2095 int *realnump
, gdb_byte
*valuep
)
2097 struct trad_frame_cache
*this_trad_cache
2098 = mips_stub_frame_cache (next_frame
, this_cache
);
2099 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2100 lvalp
, addrp
, realnump
, valuep
);
2103 static const struct frame_unwind mips_stub_frame_unwind
=
2106 mips_stub_frame_this_id
,
2107 mips_stub_frame_prev_register
2110 static const struct frame_unwind
*
2111 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2113 struct obj_section
*s
;
2114 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2116 if (in_plt_section (pc
, NULL
))
2117 return &mips_stub_frame_unwind
;
2119 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2120 s
= find_pc_section (pc
);
2123 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2124 ".MIPS.stubs") == 0)
2125 return &mips_stub_frame_unwind
;
2131 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2134 struct trad_frame_cache
*this_trad_cache
2135 = mips_stub_frame_cache (next_frame
, this_cache
);
2136 return trad_frame_get_this_base (this_trad_cache
);
2139 static const struct frame_base mips_stub_frame_base
=
2141 &mips_stub_frame_unwind
,
2142 mips_stub_frame_base_address
,
2143 mips_stub_frame_base_address
,
2144 mips_stub_frame_base_address
2147 static const struct frame_base
*
2148 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2150 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2151 return &mips_stub_frame_base
;
2157 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2159 /* Always a pseudo. */
2160 gdb_assert (regno
>= gdbarch_num_regs (current_gdbarch
));
2164 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2168 return frame_unwind_register_signed (fi
, regno
);
2172 /* mips_addr_bits_remove - remove useless address bits */
2175 mips_addr_bits_remove (CORE_ADDR addr
)
2177 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2178 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2179 /* This hack is a work-around for existing boards using PMON, the
2180 simulator, and any other 64-bit targets that doesn't have true
2181 64-bit addressing. On these targets, the upper 32 bits of
2182 addresses are ignored by the hardware. Thus, the PC or SP are
2183 likely to have been sign extended to all 1s by instruction
2184 sequences that load 32-bit addresses. For example, a typical
2185 piece of code that loads an address is this:
2187 lui $r2, <upper 16 bits>
2188 ori $r2, <lower 16 bits>
2190 But the lui sign-extends the value such that the upper 32 bits
2191 may be all 1s. The workaround is simply to mask off these
2192 bits. In the future, gcc may be changed to support true 64-bit
2193 addressing, and this masking will have to be disabled. */
2194 return addr
&= 0xffffffffUL
;
2199 /* mips_software_single_step() is called just before we want to resume
2200 the inferior, if we want to single-step it but there is no hardware
2201 or kernel single-step support (MIPS on GNU/Linux for example). We find
2202 the target of the coming instruction and breakpoint it. */
2205 mips_software_single_step (struct regcache
*regcache
)
2207 CORE_ADDR pc
, next_pc
;
2209 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2210 next_pc
= mips_next_pc (pc
);
2212 insert_single_step_breakpoint (next_pc
);
2216 /* Test whether the PC points to the return instruction at the
2217 end of a function. */
2220 mips_about_to_return (CORE_ADDR pc
)
2222 if (mips_pc_is_mips16 (pc
))
2223 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2224 generates a "jr $ra"; other times it generates code to load
2225 the return address from the stack to an accessible register (such
2226 as $a3), then a "jr" using that register. This second case
2227 is almost impossible to distinguish from an indirect jump
2228 used for switch statements, so we don't even try. */
2229 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2231 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2235 /* This fencepost looks highly suspicious to me. Removing it also
2236 seems suspicious as it could affect remote debugging across serial
2240 heuristic_proc_start (CORE_ADDR pc
)
2247 pc
= ADDR_BITS_REMOVE (pc
);
2249 fence
= start_pc
- heuristic_fence_post
;
2253 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2254 fence
= VM_MIN_ADDRESS
;
2256 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2258 /* search back for previous return */
2259 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2260 if (start_pc
< fence
)
2262 /* It's not clear to me why we reach this point when
2263 stop_soon, but with this test, at least we
2264 don't print out warnings for every child forked (eg, on
2265 decstation). 22apr93 rich@cygnus.com. */
2266 if (stop_soon
== NO_STOP_QUIETLY
)
2268 static int blurb_printed
= 0;
2270 warning (_("GDB can't find the start of the function at 0x%s."),
2275 /* This actually happens frequently in embedded
2276 development, when you first connect to a board
2277 and your stack pointer and pc are nowhere in
2278 particular. This message needs to give people
2279 in that situation enough information to
2280 determine that it's no big deal. */
2281 printf_filtered ("\n\
2282 GDB is unable to find the start of the function at 0x%s\n\
2283 and thus can't determine the size of that function's stack frame.\n\
2284 This means that GDB may be unable to access that stack frame, or\n\
2285 the frames below it.\n\
2286 This problem is most likely caused by an invalid program counter or\n\
2288 However, if you think GDB should simply search farther back\n\
2289 from 0x%s for code which looks like the beginning of a\n\
2290 function, you can increase the range of the search using the `set\n\
2291 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2298 else if (mips_pc_is_mips16 (start_pc
))
2300 unsigned short inst
;
2302 /* On MIPS16, any one of the following is likely to be the
2303 start of a function:
2307 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2308 inst
= mips_fetch_instruction (start_pc
);
2309 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2310 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2311 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2312 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2314 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2315 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2320 else if (mips_about_to_return (start_pc
))
2322 /* Skip return and its delay slot. */
2323 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2330 struct mips_objfile_private
2336 /* According to the current ABI, should the type be passed in a
2337 floating-point register (assuming that there is space)? When there
2338 is no FPU, FP are not even considered as possible candidates for
2339 FP registers and, consequently this returns false - forces FP
2340 arguments into integer registers. */
2343 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2345 return ((typecode
== TYPE_CODE_FLT
2347 && (typecode
== TYPE_CODE_STRUCT
2348 || typecode
== TYPE_CODE_UNION
)
2349 && TYPE_NFIELDS (arg_type
) == 1
2350 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2352 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2355 /* On o32, argument passing in GPRs depends on the alignment of the type being
2356 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2359 mips_type_needs_double_align (struct type
*type
)
2361 enum type_code typecode
= TYPE_CODE (type
);
2363 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2365 else if (typecode
== TYPE_CODE_STRUCT
)
2367 if (TYPE_NFIELDS (type
) < 1)
2369 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2371 else if (typecode
== TYPE_CODE_UNION
)
2375 n
= TYPE_NFIELDS (type
);
2376 for (i
= 0; i
< n
; i
++)
2377 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2384 /* Adjust the address downward (direction of stack growth) so that it
2385 is correctly aligned for a new stack frame. */
2387 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2389 return align_down (addr
, 16);
2393 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2394 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2395 int nargs
, struct value
**args
, CORE_ADDR sp
,
2396 int struct_return
, CORE_ADDR struct_addr
)
2402 int stack_offset
= 0;
2403 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2404 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2405 int regsize
= mips_abi_regsize (gdbarch
);
2407 /* For shared libraries, "t9" needs to point at the function
2409 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2411 /* Set the return address register to point to the entry point of
2412 the program, where a breakpoint lies in wait. */
2413 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2415 /* First ensure that the stack and structure return address (if any)
2416 are properly aligned. The stack has to be at least 64-bit
2417 aligned even on 32-bit machines, because doubles must be 64-bit
2418 aligned. For n32 and n64, stack frames need to be 128-bit
2419 aligned, so we round to this widest known alignment. */
2421 sp
= align_down (sp
, 16);
2422 struct_addr
= align_down (struct_addr
, 16);
2424 /* Now make space on the stack for the args. We allocate more
2425 than necessary for EABI, because the first few arguments are
2426 passed in registers, but that's OK. */
2427 for (argnum
= 0; argnum
< nargs
; argnum
++)
2428 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2429 sp
-= align_up (len
, 16);
2432 fprintf_unfiltered (gdb_stdlog
,
2433 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2434 paddr_nz (sp
), (long) align_up (len
, 16));
2436 /* Initialize the integer and float register pointers. */
2437 argreg
= MIPS_A0_REGNUM
;
2438 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2440 /* The struct_return pointer occupies the first parameter-passing reg. */
2444 fprintf_unfiltered (gdb_stdlog
,
2445 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2446 argreg
, paddr_nz (struct_addr
));
2447 write_register (argreg
++, struct_addr
);
2450 /* Now load as many as possible of the first arguments into
2451 registers, and push the rest onto the stack. Loop thru args
2452 from first to last. */
2453 for (argnum
= 0; argnum
< nargs
; argnum
++)
2455 const gdb_byte
*val
;
2456 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2457 struct value
*arg
= args
[argnum
];
2458 struct type
*arg_type
= check_typedef (value_type (arg
));
2459 int len
= TYPE_LENGTH (arg_type
);
2460 enum type_code typecode
= TYPE_CODE (arg_type
);
2463 fprintf_unfiltered (gdb_stdlog
,
2464 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2465 argnum
+ 1, len
, (int) typecode
);
2467 /* The EABI passes structures that do not fit in a register by
2470 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2472 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2473 typecode
= TYPE_CODE_PTR
;
2477 fprintf_unfiltered (gdb_stdlog
, " push");
2480 val
= value_contents (arg
);
2482 /* 32-bit ABIs always start floating point arguments in an
2483 even-numbered floating point register. Round the FP register
2484 up before the check to see if there are any FP registers
2485 left. Non MIPS_EABI targets also pass the FP in the integer
2486 registers so also round up normal registers. */
2487 if (regsize
< 8 && fp_register_arg_p (typecode
, arg_type
))
2489 if ((float_argreg
& 1))
2493 /* Floating point arguments passed in registers have to be
2494 treated specially. On 32-bit architectures, doubles
2495 are passed in register pairs; the even register gets
2496 the low word, and the odd register gets the high word.
2497 On non-EABI processors, the first two floating point arguments are
2498 also copied to general registers, because MIPS16 functions
2499 don't use float registers for arguments. This duplication of
2500 arguments in general registers can't hurt non-MIPS16 functions
2501 because those registers are normally skipped. */
2502 /* MIPS_EABI squeezes a struct that contains a single floating
2503 point value into an FP register instead of pushing it onto the
2505 if (fp_register_arg_p (typecode
, arg_type
)
2506 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2508 /* EABI32 will pass doubles in consecutive registers, even on
2509 64-bit cores. At one time, we used to check the size of
2510 `float_argreg' to determine whether or not to pass doubles
2511 in consecutive registers, but this is not sufficient for
2512 making the ABI determination. */
2513 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2515 int low_offset
= gdbarch_byte_order (current_gdbarch
)
2516 == BFD_ENDIAN_BIG
? 4 : 0;
2517 unsigned long regval
;
2519 /* Write the low word of the double to the even register(s). */
2520 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2522 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2523 float_argreg
, phex (regval
, 4));
2524 write_register (float_argreg
++, regval
);
2526 /* Write the high word of the double to the odd register(s). */
2527 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2529 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2530 float_argreg
, phex (regval
, 4));
2531 write_register (float_argreg
++, regval
);
2535 /* This is a floating point value that fits entirely
2536 in a single register. */
2537 /* On 32 bit ABI's the float_argreg is further adjusted
2538 above to ensure that it is even register aligned. */
2539 LONGEST regval
= extract_unsigned_integer (val
, len
);
2541 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2542 float_argreg
, phex (regval
, len
));
2543 write_register (float_argreg
++, regval
);
2548 /* Copy the argument to general registers or the stack in
2549 register-sized pieces. Large arguments are split between
2550 registers and stack. */
2551 /* Note: structs whose size is not a multiple of regsize
2552 are treated specially: Irix cc passes
2553 them in registers where gcc sometimes puts them on the
2554 stack. For maximum compatibility, we will put them in
2556 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2558 /* Note: Floating-point values that didn't fit into an FP
2559 register are only written to memory. */
2562 /* Remember if the argument was written to the stack. */
2563 int stack_used_p
= 0;
2564 int partial_len
= (len
< regsize
? len
: regsize
);
2567 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2570 /* Write this portion of the argument to the stack. */
2571 if (argreg
> MIPS_LAST_ARG_REGNUM
2573 || fp_register_arg_p (typecode
, arg_type
))
2575 /* Should shorter than int integer values be
2576 promoted to int before being stored? */
2577 int longword_offset
= 0;
2580 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
2583 && (typecode
== TYPE_CODE_INT
2584 || typecode
== TYPE_CODE_PTR
2585 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2586 longword_offset
= regsize
- len
;
2587 else if ((typecode
== TYPE_CODE_STRUCT
2588 || typecode
== TYPE_CODE_UNION
)
2589 && TYPE_LENGTH (arg_type
) < regsize
)
2590 longword_offset
= regsize
- len
;
2595 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2596 paddr_nz (stack_offset
));
2597 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2598 paddr_nz (longword_offset
));
2601 addr
= sp
+ stack_offset
+ longword_offset
;
2606 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2608 for (i
= 0; i
< partial_len
; i
++)
2610 fprintf_unfiltered (gdb_stdlog
, "%02x",
2614 write_memory (addr
, val
, partial_len
);
2617 /* Note!!! This is NOT an else clause. Odd sized
2618 structs may go thru BOTH paths. Floating point
2619 arguments will not. */
2620 /* Write this portion of the argument to a general
2621 purpose register. */
2622 if (argreg
<= MIPS_LAST_ARG_REGNUM
2623 && !fp_register_arg_p (typecode
, arg_type
))
2626 extract_unsigned_integer (val
, partial_len
);
2629 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2631 phex (regval
, regsize
));
2632 write_register (argreg
, regval
);
2639 /* Compute the the offset into the stack at which we
2640 will copy the next parameter.
2642 In the new EABI (and the NABI32), the stack_offset
2643 only needs to be adjusted when it has been used. */
2646 stack_offset
+= align_up (partial_len
, regsize
);
2650 fprintf_unfiltered (gdb_stdlog
, "\n");
2653 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2655 /* Return adjusted stack pointer. */
2659 /* Determine the return value convention being used. */
2661 static enum return_value_convention
2662 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2663 struct type
*type
, struct regcache
*regcache
,
2664 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2666 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2667 return RETURN_VALUE_STRUCT_CONVENTION
;
2669 memset (readbuf
, 0, TYPE_LENGTH (type
));
2670 return RETURN_VALUE_REGISTER_CONVENTION
;
2674 /* N32/N64 ABI stuff. */
2677 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2678 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2679 int nargs
, struct value
**args
, CORE_ADDR sp
,
2680 int struct_return
, CORE_ADDR struct_addr
)
2686 int stack_offset
= 0;
2687 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2688 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2690 /* For shared libraries, "t9" needs to point at the function
2692 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2694 /* Set the return address register to point to the entry point of
2695 the program, where a breakpoint lies in wait. */
2696 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2698 /* First ensure that the stack and structure return address (if any)
2699 are properly aligned. The stack has to be at least 64-bit
2700 aligned even on 32-bit machines, because doubles must be 64-bit
2701 aligned. For n32 and n64, stack frames need to be 128-bit
2702 aligned, so we round to this widest known alignment. */
2704 sp
= align_down (sp
, 16);
2705 struct_addr
= align_down (struct_addr
, 16);
2707 /* Now make space on the stack for the args. */
2708 for (argnum
= 0; argnum
< nargs
; argnum
++)
2709 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
2710 sp
-= align_up (len
, 16);
2713 fprintf_unfiltered (gdb_stdlog
,
2714 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2715 paddr_nz (sp
), (long) align_up (len
, 16));
2717 /* Initialize the integer and float register pointers. */
2718 argreg
= MIPS_A0_REGNUM
;
2719 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2721 /* The struct_return pointer occupies the first parameter-passing reg. */
2725 fprintf_unfiltered (gdb_stdlog
,
2726 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2727 argreg
, paddr_nz (struct_addr
));
2728 write_register (argreg
++, struct_addr
);
2731 /* Now load as many as possible of the first arguments into
2732 registers, and push the rest onto the stack. Loop thru args
2733 from first to last. */
2734 for (argnum
= 0; argnum
< nargs
; argnum
++)
2736 const gdb_byte
*val
;
2737 struct value
*arg
= args
[argnum
];
2738 struct type
*arg_type
= check_typedef (value_type (arg
));
2739 int len
= TYPE_LENGTH (arg_type
);
2740 enum type_code typecode
= TYPE_CODE (arg_type
);
2743 fprintf_unfiltered (gdb_stdlog
,
2744 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2745 argnum
+ 1, len
, (int) typecode
);
2747 val
= value_contents (arg
);
2749 if (fp_register_arg_p (typecode
, arg_type
)
2750 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2752 /* This is a floating point value that fits entirely
2753 in a single register. */
2754 /* On 32 bit ABI's the float_argreg is further adjusted
2755 above to ensure that it is even register aligned. */
2756 LONGEST regval
= extract_unsigned_integer (val
, len
);
2758 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2759 float_argreg
, phex (regval
, len
));
2760 write_register (float_argreg
++, regval
);
2763 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2764 argreg
, phex (regval
, len
));
2765 write_register (argreg
, regval
);
2770 /* Copy the argument to general registers or the stack in
2771 register-sized pieces. Large arguments are split between
2772 registers and stack. */
2773 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
2774 are treated specially: Irix cc passes them in registers
2775 where gcc sometimes puts them on the stack. For maximum
2776 compatibility, we will put them in both places. */
2777 int odd_sized_struct
= (len
> MIPS64_REGSIZE
2778 && len
% MIPS64_REGSIZE
!= 0);
2779 /* Note: Floating-point values that didn't fit into an FP
2780 register are only written to memory. */
2783 /* Remember if the argument was written to the stack. */
2784 int stack_used_p
= 0;
2785 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
2788 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2791 /* Write this portion of the argument to the stack. */
2792 if (argreg
> MIPS_LAST_ARG_REGNUM
2794 || fp_register_arg_p (typecode
, arg_type
))
2796 /* Should shorter than int integer values be
2797 promoted to int before being stored? */
2798 int longword_offset
= 0;
2801 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
2803 if ((typecode
== TYPE_CODE_INT
2804 || typecode
== TYPE_CODE_PTR
2805 || typecode
== TYPE_CODE_FLT
)
2807 longword_offset
= MIPS64_REGSIZE
- len
;
2812 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2813 paddr_nz (stack_offset
));
2814 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2815 paddr_nz (longword_offset
));
2818 addr
= sp
+ stack_offset
+ longword_offset
;
2823 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2825 for (i
= 0; i
< partial_len
; i
++)
2827 fprintf_unfiltered (gdb_stdlog
, "%02x",
2831 write_memory (addr
, val
, partial_len
);
2834 /* Note!!! This is NOT an else clause. Odd sized
2835 structs may go thru BOTH paths. Floating point
2836 arguments will not. */
2837 /* Write this portion of the argument to a general
2838 purpose register. */
2839 if (argreg
<= MIPS_LAST_ARG_REGNUM
2840 && !fp_register_arg_p (typecode
, arg_type
))
2843 extract_unsigned_integer (val
, partial_len
);
2845 /* A non-floating-point argument being passed in a
2846 general register. If a struct or union, and if
2847 the remaining length is smaller than the register
2848 size, we have to adjust the register value on
2851 It does not seem to be necessary to do the
2852 same for integral types. */
2854 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
2855 && partial_len
< MIPS64_REGSIZE
2856 && (typecode
== TYPE_CODE_STRUCT
2857 || typecode
== TYPE_CODE_UNION
))
2858 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
2862 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2864 phex (regval
, MIPS64_REGSIZE
));
2865 write_register (argreg
, regval
);
2872 /* Compute the the offset into the stack at which we
2873 will copy the next parameter.
2875 In N32 (N64?), the stack_offset only needs to be
2876 adjusted when it has been used. */
2879 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
2883 fprintf_unfiltered (gdb_stdlog
, "\n");
2886 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2888 /* Return adjusted stack pointer. */
2892 static enum return_value_convention
2893 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
2894 struct type
*type
, struct regcache
*regcache
,
2895 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2897 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2898 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2899 || TYPE_CODE (type
) == TYPE_CODE_UNION
2900 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
2901 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
2902 return RETURN_VALUE_STRUCT_CONVENTION
;
2903 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2904 && TYPE_LENGTH (type
) == 16
2905 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2907 /* A 128-bit floating-point value fills both $f0 and $f2. The
2908 two registers are used in the same as memory order, so the
2909 eight bytes with the lower memory address are in $f0. */
2911 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
2912 mips_xfer_register (regcache
,
2913 gdbarch_num_regs (current_gdbarch
)
2914 + mips_regnum (current_gdbarch
)->fp0
,
2915 8, gdbarch_byte_order (current_gdbarch
),
2916 readbuf
, writebuf
, 0);
2917 mips_xfer_register (regcache
,
2918 gdbarch_num_regs (current_gdbarch
)
2919 + mips_regnum (current_gdbarch
)->fp0
+ 2,
2920 8, gdbarch_byte_order (current_gdbarch
),
2921 readbuf
? readbuf
+ 8 : readbuf
,
2922 writebuf
? writebuf
+ 8 : writebuf
, 0);
2923 return RETURN_VALUE_REGISTER_CONVENTION
;
2925 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2926 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2928 /* A floating-point value belongs in the least significant part
2931 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
2932 mips_xfer_register (regcache
,
2933 gdbarch_num_regs (current_gdbarch
)
2934 + mips_regnum (current_gdbarch
)->fp0
,
2936 gdbarch_byte_order (current_gdbarch
),
2937 readbuf
, writebuf
, 0);
2938 return RETURN_VALUE_REGISTER_CONVENTION
;
2940 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2941 && TYPE_NFIELDS (type
) <= 2
2942 && TYPE_NFIELDS (type
) >= 1
2943 && ((TYPE_NFIELDS (type
) == 1
2944 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2946 || (TYPE_NFIELDS (type
) == 2
2947 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2949 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
2951 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2953 /* A struct that contains one or two floats. Each value is part
2954 in the least significant part of their floating point
2958 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
2959 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
2961 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
2964 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
2966 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
2968 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
2969 gdbarch_byte_order (current_gdbarch
),
2970 readbuf
, writebuf
, offset
);
2972 return RETURN_VALUE_REGISTER_CONVENTION
;
2974 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2975 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2977 /* A structure or union. Extract the left justified value,
2978 regardless of the byte order. I.e. DO NOT USE
2982 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
2983 offset
< TYPE_LENGTH (type
);
2984 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
2986 int xfer
= register_size (current_gdbarch
, regnum
);
2987 if (offset
+ xfer
> TYPE_LENGTH (type
))
2988 xfer
= TYPE_LENGTH (type
) - offset
;
2990 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
2991 offset
, xfer
, regnum
);
2992 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
2994 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
2996 return RETURN_VALUE_REGISTER_CONVENTION
;
3000 /* A scalar extract each part but least-significant-byte
3004 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3005 offset
< TYPE_LENGTH (type
);
3006 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3008 int xfer
= register_size (current_gdbarch
, regnum
);
3009 if (offset
+ xfer
> TYPE_LENGTH (type
))
3010 xfer
= TYPE_LENGTH (type
) - offset
;
3012 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3013 offset
, xfer
, regnum
);
3014 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3016 gdbarch_byte_order (current_gdbarch
),
3017 readbuf
, writebuf
, offset
);
3019 return RETURN_VALUE_REGISTER_CONVENTION
;
3023 /* O32 ABI stuff. */
3026 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3027 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3028 int nargs
, struct value
**args
, CORE_ADDR sp
,
3029 int struct_return
, CORE_ADDR struct_addr
)
3035 int stack_offset
= 0;
3036 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3037 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3039 /* For shared libraries, "t9" needs to point at the function
3041 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3043 /* Set the return address register to point to the entry point of
3044 the program, where a breakpoint lies in wait. */
3045 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3047 /* First ensure that the stack and structure return address (if any)
3048 are properly aligned. The stack has to be at least 64-bit
3049 aligned even on 32-bit machines, because doubles must be 64-bit
3050 aligned. For n32 and n64, stack frames need to be 128-bit
3051 aligned, so we round to this widest known alignment. */
3053 sp
= align_down (sp
, 16);
3054 struct_addr
= align_down (struct_addr
, 16);
3056 /* Now make space on the stack for the args. */
3057 for (argnum
= 0; argnum
< nargs
; argnum
++)
3059 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3060 int arglen
= TYPE_LENGTH (arg_type
);
3062 /* Align to double-word if necessary. */
3063 if (mips_type_needs_double_align (arg_type
))
3064 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3065 /* Allocate space on the stack. */
3066 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3068 sp
-= align_up (len
, 16);
3071 fprintf_unfiltered (gdb_stdlog
,
3072 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3073 paddr_nz (sp
), (long) align_up (len
, 16));
3075 /* Initialize the integer and float register pointers. */
3076 argreg
= MIPS_A0_REGNUM
;
3077 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3079 /* The struct_return pointer occupies the first parameter-passing reg. */
3083 fprintf_unfiltered (gdb_stdlog
,
3084 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3085 argreg
, paddr_nz (struct_addr
));
3086 write_register (argreg
++, struct_addr
);
3087 stack_offset
+= MIPS32_REGSIZE
;
3090 /* Now load as many as possible of the first arguments into
3091 registers, and push the rest onto the stack. Loop thru args
3092 from first to last. */
3093 for (argnum
= 0; argnum
< nargs
; argnum
++)
3095 const gdb_byte
*val
;
3096 struct value
*arg
= args
[argnum
];
3097 struct type
*arg_type
= check_typedef (value_type (arg
));
3098 int len
= TYPE_LENGTH (arg_type
);
3099 enum type_code typecode
= TYPE_CODE (arg_type
);
3102 fprintf_unfiltered (gdb_stdlog
,
3103 "mips_o32_push_dummy_call: %d len=%d type=%d",
3104 argnum
+ 1, len
, (int) typecode
);
3106 val
= value_contents (arg
);
3108 /* 32-bit ABIs always start floating point arguments in an
3109 even-numbered floating point register. Round the FP register
3110 up before the check to see if there are any FP registers
3111 left. O32/O64 targets also pass the FP in the integer
3112 registers so also round up normal registers. */
3113 if (fp_register_arg_p (typecode
, arg_type
))
3115 if ((float_argreg
& 1))
3119 /* Floating point arguments passed in registers have to be
3120 treated specially. On 32-bit architectures, doubles
3121 are passed in register pairs; the even register gets
3122 the low word, and the odd register gets the high word.
3123 On O32/O64, the first two floating point arguments are
3124 also copied to general registers, because MIPS16 functions
3125 don't use float registers for arguments. This duplication of
3126 arguments in general registers can't hurt non-MIPS16 functions
3127 because those registers are normally skipped. */
3129 if (fp_register_arg_p (typecode
, arg_type
)
3130 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3132 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3134 int low_offset
= gdbarch_byte_order (current_gdbarch
)
3135 == BFD_ENDIAN_BIG
? 4 : 0;
3136 unsigned long regval
;
3138 /* Write the low word of the double to the even register(s). */
3139 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3141 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3142 float_argreg
, phex (regval
, 4));
3143 write_register (float_argreg
++, regval
);
3145 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3146 argreg
, phex (regval
, 4));
3147 write_register (argreg
++, regval
);
3149 /* Write the high word of the double to the odd register(s). */
3150 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3152 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3153 float_argreg
, phex (regval
, 4));
3154 write_register (float_argreg
++, regval
);
3157 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3158 argreg
, phex (regval
, 4));
3159 write_register (argreg
++, regval
);
3163 /* This is a floating point value that fits entirely
3164 in a single register. */
3165 /* On 32 bit ABI's the float_argreg is further adjusted
3166 above to ensure that it is even register aligned. */
3167 LONGEST regval
= extract_unsigned_integer (val
, len
);
3169 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3170 float_argreg
, phex (regval
, len
));
3171 write_register (float_argreg
++, regval
);
3172 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3173 registers for each argument. The below is (my
3174 guess) to ensure that the corresponding integer
3175 register has reserved the same space. */
3177 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3178 argreg
, phex (regval
, len
));
3179 write_register (argreg
, regval
);
3182 /* Reserve space for the FP register. */
3183 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3187 /* Copy the argument to general registers or the stack in
3188 register-sized pieces. Large arguments are split between
3189 registers and stack. */
3190 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3191 are treated specially: Irix cc passes
3192 them in registers where gcc sometimes puts them on the
3193 stack. For maximum compatibility, we will put them in
3195 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3196 && len
% MIPS32_REGSIZE
!= 0);
3197 /* Structures should be aligned to eight bytes (even arg registers)
3198 on MIPS_ABI_O32, if their first member has double precision. */
3199 if (mips_type_needs_double_align (arg_type
))
3204 stack_offset
+= MIPS32_REGSIZE
;
3209 /* Remember if the argument was written to the stack. */
3210 int stack_used_p
= 0;
3211 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3214 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3217 /* Write this portion of the argument to the stack. */
3218 if (argreg
> MIPS_LAST_ARG_REGNUM
3219 || odd_sized_struct
)
3221 /* Should shorter than int integer values be
3222 promoted to int before being stored? */
3223 int longword_offset
= 0;
3229 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3230 paddr_nz (stack_offset
));
3231 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3232 paddr_nz (longword_offset
));
3235 addr
= sp
+ stack_offset
+ longword_offset
;
3240 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3242 for (i
= 0; i
< partial_len
; i
++)
3244 fprintf_unfiltered (gdb_stdlog
, "%02x",
3248 write_memory (addr
, val
, partial_len
);
3251 /* Note!!! This is NOT an else clause. Odd sized
3252 structs may go thru BOTH paths. */
3253 /* Write this portion of the argument to a general
3254 purpose register. */
3255 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3257 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3258 /* Value may need to be sign extended, because
3259 mips_isa_regsize() != mips_abi_regsize(). */
3261 /* A non-floating-point argument being passed in a
3262 general register. If a struct or union, and if
3263 the remaining length is smaller than the register
3264 size, we have to adjust the register value on
3267 It does not seem to be necessary to do the
3268 same for integral types.
3270 Also don't do this adjustment on O64 binaries.
3272 cagney/2001-07-23: gdb/179: Also, GCC, when
3273 outputting LE O32 with sizeof (struct) <
3274 mips_abi_regsize(), generates a left shift
3275 as part of storing the argument in a register
3276 (the left shift isn't generated when
3277 sizeof (struct) >= mips_abi_regsize()). Since
3278 it is quite possible that this is GCC
3279 contradicting the LE/O32 ABI, GDB has not been
3280 adjusted to accommodate this. Either someone
3281 needs to demonstrate that the LE/O32 ABI
3282 specifies such a left shift OR this new ABI gets
3283 identified as such and GDB gets tweaked
3286 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
3287 && partial_len
< MIPS32_REGSIZE
3288 && (typecode
== TYPE_CODE_STRUCT
3289 || typecode
== TYPE_CODE_UNION
))
3290 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3294 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3296 phex (regval
, MIPS32_REGSIZE
));
3297 write_register (argreg
, regval
);
3300 /* Prevent subsequent floating point arguments from
3301 being passed in floating point registers. */
3302 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3308 /* Compute the the offset into the stack at which we
3309 will copy the next parameter.
3311 In older ABIs, the caller reserved space for
3312 registers that contained arguments. This was loosely
3313 refered to as their "home". Consequently, space is
3314 always allocated. */
3316 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3320 fprintf_unfiltered (gdb_stdlog
, "\n");
3323 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3325 /* Return adjusted stack pointer. */
3329 static enum return_value_convention
3330 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3331 struct regcache
*regcache
,
3332 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3334 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3336 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3337 || TYPE_CODE (type
) == TYPE_CODE_UNION
3338 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3339 return RETURN_VALUE_STRUCT_CONVENTION
;
3340 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3341 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3343 /* A single-precision floating-point value. It fits in the
3344 least significant part of FP0. */
3346 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3347 mips_xfer_register (regcache
,
3348 gdbarch_num_regs (current_gdbarch
)
3349 + mips_regnum (current_gdbarch
)->fp0
,
3351 gdbarch_byte_order (current_gdbarch
),
3352 readbuf
, writebuf
, 0);
3353 return RETURN_VALUE_REGISTER_CONVENTION
;
3355 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3356 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3358 /* A double-precision floating-point value. The most
3359 significant part goes in FP1, and the least significant in
3362 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3363 switch (gdbarch_byte_order (current_gdbarch
))
3365 case BFD_ENDIAN_LITTLE
:
3366 mips_xfer_register (regcache
,
3367 gdbarch_num_regs (current_gdbarch
)
3368 + mips_regnum (current_gdbarch
)->fp0
+
3369 0, 4, gdbarch_byte_order (current_gdbarch
),
3370 readbuf
, writebuf
, 0);
3371 mips_xfer_register (regcache
,
3372 gdbarch_num_regs (current_gdbarch
)
3373 + mips_regnum (current_gdbarch
)->fp0
+ 1,
3374 4, gdbarch_byte_order (current_gdbarch
),
3375 readbuf
, writebuf
, 4);
3377 case BFD_ENDIAN_BIG
:
3378 mips_xfer_register (regcache
,
3379 gdbarch_num_regs (current_gdbarch
)
3380 + mips_regnum (current_gdbarch
)->fp0
+ 1,
3381 4, gdbarch_byte_order (current_gdbarch
),
3382 readbuf
, writebuf
, 0);
3383 mips_xfer_register (regcache
,
3384 gdbarch_num_regs (current_gdbarch
)
3385 + mips_regnum (current_gdbarch
)->fp0
+ 0,
3386 4, gdbarch_byte_order (current_gdbarch
),
3387 readbuf
, writebuf
, 4);
3390 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3392 return RETURN_VALUE_REGISTER_CONVENTION
;
3395 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3396 && TYPE_NFIELDS (type
) <= 2
3397 && TYPE_NFIELDS (type
) >= 1
3398 && ((TYPE_NFIELDS (type
) == 1
3399 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3401 || (TYPE_NFIELDS (type
) == 2
3402 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3404 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3406 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3408 /* A struct that contains one or two floats. Each value is part
3409 in the least significant part of their floating point
3411 gdb_byte reg
[MAX_REGISTER_SIZE
];
3414 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3415 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3417 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3420 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3422 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3424 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3425 gdbarch_byte_order (current_gdbarch
),
3426 readbuf
, writebuf
, offset
);
3428 return RETURN_VALUE_REGISTER_CONVENTION
;
3432 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3433 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3435 /* A structure or union. Extract the left justified value,
3436 regardless of the byte order. I.e. DO NOT USE
3440 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3441 offset
< TYPE_LENGTH (type
);
3442 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3444 int xfer
= register_size (current_gdbarch
, regnum
);
3445 if (offset
+ xfer
> TYPE_LENGTH (type
))
3446 xfer
= TYPE_LENGTH (type
) - offset
;
3448 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3449 offset
, xfer
, regnum
);
3450 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3452 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3454 return RETURN_VALUE_REGISTER_CONVENTION
;
3459 /* A scalar extract each part but least-significant-byte
3460 justified. o32 thinks registers are 4 byte, regardless of
3464 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3465 offset
< TYPE_LENGTH (type
);
3466 offset
+= MIPS32_REGSIZE
, regnum
++)
3468 int xfer
= MIPS32_REGSIZE
;
3469 if (offset
+ xfer
> TYPE_LENGTH (type
))
3470 xfer
= TYPE_LENGTH (type
) - offset
;
3472 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3473 offset
, xfer
, regnum
);
3474 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3476 gdbarch_byte_order (current_gdbarch
),
3477 readbuf
, writebuf
, offset
);
3479 return RETURN_VALUE_REGISTER_CONVENTION
;
3483 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3487 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3488 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3490 struct value
**args
, CORE_ADDR sp
,
3491 int struct_return
, CORE_ADDR struct_addr
)
3497 int stack_offset
= 0;
3498 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3499 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3501 /* For shared libraries, "t9" needs to point at the function
3503 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3505 /* Set the return address register to point to the entry point of
3506 the program, where a breakpoint lies in wait. */
3507 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3509 /* First ensure that the stack and structure return address (if any)
3510 are properly aligned. The stack has to be at least 64-bit
3511 aligned even on 32-bit machines, because doubles must be 64-bit
3512 aligned. For n32 and n64, stack frames need to be 128-bit
3513 aligned, so we round to this widest known alignment. */
3515 sp
= align_down (sp
, 16);
3516 struct_addr
= align_down (struct_addr
, 16);
3518 /* Now make space on the stack for the args. */
3519 for (argnum
= 0; argnum
< nargs
; argnum
++)
3521 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3522 int arglen
= TYPE_LENGTH (arg_type
);
3524 /* Allocate space on the stack. */
3525 len
+= align_up (arglen
, MIPS64_REGSIZE
);
3527 sp
-= align_up (len
, 16);
3530 fprintf_unfiltered (gdb_stdlog
,
3531 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3532 paddr_nz (sp
), (long) align_up (len
, 16));
3534 /* Initialize the integer and float register pointers. */
3535 argreg
= MIPS_A0_REGNUM
;
3536 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3538 /* The struct_return pointer occupies the first parameter-passing reg. */
3542 fprintf_unfiltered (gdb_stdlog
,
3543 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3544 argreg
, paddr_nz (struct_addr
));
3545 write_register (argreg
++, struct_addr
);
3546 stack_offset
+= MIPS64_REGSIZE
;
3549 /* Now load as many as possible of the first arguments into
3550 registers, and push the rest onto the stack. Loop thru args
3551 from first to last. */
3552 for (argnum
= 0; argnum
< nargs
; argnum
++)
3554 const gdb_byte
*val
;
3555 struct value
*arg
= args
[argnum
];
3556 struct type
*arg_type
= check_typedef (value_type (arg
));
3557 int len
= TYPE_LENGTH (arg_type
);
3558 enum type_code typecode
= TYPE_CODE (arg_type
);
3561 fprintf_unfiltered (gdb_stdlog
,
3562 "mips_o64_push_dummy_call: %d len=%d type=%d",
3563 argnum
+ 1, len
, (int) typecode
);
3565 val
= value_contents (arg
);
3567 /* Floating point arguments passed in registers have to be
3568 treated specially. On 32-bit architectures, doubles
3569 are passed in register pairs; the even register gets
3570 the low word, and the odd register gets the high word.
3571 On O32/O64, the first two floating point arguments are
3572 also copied to general registers, because MIPS16 functions
3573 don't use float registers for arguments. This duplication of
3574 arguments in general registers can't hurt non-MIPS16 functions
3575 because those registers are normally skipped. */
3577 if (fp_register_arg_p (typecode
, arg_type
)
3578 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3580 LONGEST regval
= extract_unsigned_integer (val
, len
);
3582 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3583 float_argreg
, phex (regval
, len
));
3584 write_register (float_argreg
++, regval
);
3586 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3587 argreg
, phex (regval
, len
));
3588 write_register (argreg
, regval
);
3590 /* Reserve space for the FP register. */
3591 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
3595 /* Copy the argument to general registers or the stack in
3596 register-sized pieces. Large arguments are split between
3597 registers and stack. */
3598 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
3599 are treated specially: Irix cc passes them in registers
3600 where gcc sometimes puts them on the stack. For maximum
3601 compatibility, we will put them in both places. */
3602 int odd_sized_struct
= (len
> MIPS64_REGSIZE
3603 && len
% MIPS64_REGSIZE
!= 0);
3606 /* Remember if the argument was written to the stack. */
3607 int stack_used_p
= 0;
3608 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3611 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3614 /* Write this portion of the argument to the stack. */
3615 if (argreg
> MIPS_LAST_ARG_REGNUM
3616 || odd_sized_struct
)
3618 /* Should shorter than int integer values be
3619 promoted to int before being stored? */
3620 int longword_offset
= 0;
3623 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3625 if ((typecode
== TYPE_CODE_INT
3626 || typecode
== TYPE_CODE_PTR
3627 || typecode
== TYPE_CODE_FLT
)
3629 longword_offset
= MIPS64_REGSIZE
- len
;
3634 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3635 paddr_nz (stack_offset
));
3636 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3637 paddr_nz (longword_offset
));
3640 addr
= sp
+ stack_offset
+ longword_offset
;
3645 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3647 for (i
= 0; i
< partial_len
; i
++)
3649 fprintf_unfiltered (gdb_stdlog
, "%02x",
3653 write_memory (addr
, val
, partial_len
);
3656 /* Note!!! This is NOT an else clause. Odd sized
3657 structs may go thru BOTH paths. */
3658 /* Write this portion of the argument to a general
3659 purpose register. */
3660 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3662 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3663 /* Value may need to be sign extended, because
3664 mips_isa_regsize() != mips_abi_regsize(). */
3666 /* A non-floating-point argument being passed in a
3667 general register. If a struct or union, and if
3668 the remaining length is smaller than the register
3669 size, we have to adjust the register value on
3672 It does not seem to be necessary to do the
3673 same for integral types. */
3675 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
3676 && partial_len
< MIPS64_REGSIZE
3677 && (typecode
== TYPE_CODE_STRUCT
3678 || typecode
== TYPE_CODE_UNION
))
3679 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3683 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3685 phex (regval
, MIPS64_REGSIZE
));
3686 write_register (argreg
, regval
);
3689 /* Prevent subsequent floating point arguments from
3690 being passed in floating point registers. */
3691 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3697 /* Compute the the offset into the stack at which we
3698 will copy the next parameter.
3700 In older ABIs, the caller reserved space for
3701 registers that contained arguments. This was loosely
3702 refered to as their "home". Consequently, space is
3703 always allocated. */
3705 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3709 fprintf_unfiltered (gdb_stdlog
, "\n");
3712 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3714 /* Return adjusted stack pointer. */
3718 static enum return_value_convention
3719 mips_o64_return_value (struct gdbarch
*gdbarch
,
3720 struct type
*type
, struct regcache
*regcache
,
3721 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3723 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3725 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3726 || TYPE_CODE (type
) == TYPE_CODE_UNION
3727 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3728 return RETURN_VALUE_STRUCT_CONVENTION
;
3729 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
3731 /* A floating-point value. It fits in the least significant
3734 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3735 mips_xfer_register (regcache
,
3736 gdbarch_num_regs (current_gdbarch
)
3737 + mips_regnum (current_gdbarch
)->fp0
,
3739 gdbarch_byte_order (current_gdbarch
),
3740 readbuf
, writebuf
, 0);
3741 return RETURN_VALUE_REGISTER_CONVENTION
;
3745 /* A scalar extract each part but least-significant-byte
3749 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3750 offset
< TYPE_LENGTH (type
);
3751 offset
+= MIPS64_REGSIZE
, regnum
++)
3753 int xfer
= MIPS64_REGSIZE
;
3754 if (offset
+ xfer
> TYPE_LENGTH (type
))
3755 xfer
= TYPE_LENGTH (type
) - offset
;
3757 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3758 offset
, xfer
, regnum
);
3759 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3761 gdbarch_byte_order (current_gdbarch
),
3762 readbuf
, writebuf
, offset
);
3764 return RETURN_VALUE_REGISTER_CONVENTION
;
3768 /* Floating point register management.
3770 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3771 64bit operations, these early MIPS cpus treat fp register pairs
3772 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3773 registers and offer a compatibility mode that emulates the MIPS2 fp
3774 model. When operating in MIPS2 fp compat mode, later cpu's split
3775 double precision floats into two 32-bit chunks and store them in
3776 consecutive fp regs. To display 64-bit floats stored in this
3777 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3778 Throw in user-configurable endianness and you have a real mess.
3780 The way this works is:
3781 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3782 double-precision value will be split across two logical registers.
3783 The lower-numbered logical register will hold the low-order bits,
3784 regardless of the processor's endianness.
3785 - If we are on a 64-bit processor, and we are looking for a
3786 single-precision value, it will be in the low ordered bits
3787 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3788 save slot in memory.
3789 - If we are in 64-bit mode, everything is straightforward.
3791 Note that this code only deals with "live" registers at the top of the
3792 stack. We will attempt to deal with saved registers later, when
3793 the raw/cooked register interface is in place. (We need a general
3794 interface that can deal with dynamic saved register sizes -- fp
3795 regs could be 32 bits wide in one frame and 64 on the frame above
3798 static struct type
*
3799 mips_float_register_type (void)
3801 return builtin_type_ieee_single
;
3804 static struct type
*
3805 mips_double_register_type (void)
3807 return builtin_type_ieee_double
;
3810 /* Copy a 32-bit single-precision value from the current frame
3811 into rare_buffer. */
3814 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3815 gdb_byte
*rare_buffer
)
3817 int raw_size
= register_size (current_gdbarch
, regno
);
3818 gdb_byte
*raw_buffer
= alloca (raw_size
);
3820 if (!frame_register_read (frame
, regno
, raw_buffer
))
3821 error (_("can't read register %d (%s)"), regno
, REGISTER_NAME (regno
));
3824 /* We have a 64-bit value for this register. Find the low-order
3828 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3833 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3837 memcpy (rare_buffer
, raw_buffer
, 4);
3841 /* Copy a 64-bit double-precision value from the current frame into
3842 rare_buffer. This may include getting half of it from the next
3846 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
3847 gdb_byte
*rare_buffer
)
3849 int raw_size
= register_size (current_gdbarch
, regno
);
3851 if (raw_size
== 8 && !mips2_fp_compat ())
3853 /* We have a 64-bit value for this register, and we should use
3855 if (!frame_register_read (frame
, regno
, rare_buffer
))
3856 error (_("can't read register %d (%s)"), regno
, REGISTER_NAME (regno
));
3860 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
3861 internal_error (__FILE__
, __LINE__
,
3862 _("mips_read_fp_register_double: bad access to "
3863 "odd-numbered FP register"));
3865 /* mips_read_fp_register_single will find the correct 32 bits from
3867 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3869 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
3870 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
3874 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
3875 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
3881 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
3883 { /* do values for FP (float) regs */
3884 gdb_byte
*raw_buffer
;
3885 double doub
, flt1
; /* doubles extracted from raw hex data */
3888 raw_buffer
= alloca (2 * register_size (current_gdbarch
,
3889 mips_regnum (current_gdbarch
)->fp0
));
3891 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
3892 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
3895 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
3897 /* 4-byte registers: Print hex and floating. Also print even
3898 numbered registers as doubles. */
3899 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3900 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3902 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
3905 fprintf_filtered (file
, " flt: ");
3907 fprintf_filtered (file
, " <invalid float> ");
3909 fprintf_filtered (file
, "%-17.9g", flt1
);
3911 if (regnum
% 2 == 0)
3913 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3914 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
3917 fprintf_filtered (file
, " dbl: ");
3919 fprintf_filtered (file
, "<invalid double>");
3921 fprintf_filtered (file
, "%-24.17g", doub
);
3926 /* Eight byte registers: print each one as hex, float and double. */
3927 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3928 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3930 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3931 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
3934 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
3937 fprintf_filtered (file
, " flt: ");
3939 fprintf_filtered (file
, "<invalid float>");
3941 fprintf_filtered (file
, "%-17.9g", flt1
);
3943 fprintf_filtered (file
, " dbl: ");
3945 fprintf_filtered (file
, "<invalid double>");
3947 fprintf_filtered (file
, "%-24.17g", doub
);
3952 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
3953 int regnum
, int all
)
3955 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3956 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
3959 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
3961 mips_print_fp_register (file
, frame
, regnum
);
3965 /* Get the data in raw format. */
3966 if (!frame_register_read (frame
, regnum
, raw_buffer
))
3968 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
3972 fputs_filtered (REGISTER_NAME (regnum
), file
);
3974 /* The problem with printing numeric register names (r26, etc.) is that
3975 the user can't use them on input. Probably the best solution is to
3976 fix it so that either the numeric or the funky (a2, etc.) names
3977 are accepted on input. */
3978 if (regnum
< MIPS_NUMREGS
)
3979 fprintf_filtered (file
, "(r%d): ", regnum
);
3981 fprintf_filtered (file
, ": ");
3983 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3985 register_size (current_gdbarch
,
3986 regnum
) - register_size (current_gdbarch
, regnum
);
3990 print_scalar_formatted (raw_buffer
+ offset
,
3991 register_type (gdbarch
, regnum
), 'x', 0,
3995 /* Replacement for generic do_registers_info.
3996 Print regs in pretty columns. */
3999 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4002 fprintf_filtered (file
, " ");
4003 mips_print_fp_register (file
, frame
, regnum
);
4004 fprintf_filtered (file
, "\n");
4009 /* Print a row's worth of GP (int) registers, with name labels above */
4012 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4015 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4016 /* do values for GP (int) regs */
4017 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4018 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4022 /* For GP registers, we print a separate row of names above the vals */
4023 for (col
= 0, regnum
= start_regnum
;
4024 col
< ncols
&& regnum
< gdbarch_num_regs (current_gdbarch
)
4025 + gdbarch_num_pseudo_regs (current_gdbarch
);
4028 if (*REGISTER_NAME (regnum
) == '\0')
4029 continue; /* unused register */
4030 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4032 break; /* end the row: reached FP register */
4034 fprintf_filtered (file
, " ");
4035 fprintf_filtered (file
,
4036 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4037 REGISTER_NAME (regnum
));
4044 /* print the R0 to R31 names */
4045 if ((start_regnum
% gdbarch_num_regs (current_gdbarch
)) < MIPS_NUMREGS
)
4046 fprintf_filtered (file
, "\n R%-4d",
4047 start_regnum
% gdbarch_num_regs (current_gdbarch
));
4049 fprintf_filtered (file
, "\n ");
4051 /* now print the values in hex, 4 or 8 to the row */
4052 for (col
= 0, regnum
= start_regnum
;
4053 col
< ncols
&& regnum
< gdbarch_num_regs (current_gdbarch
)
4054 + gdbarch_num_pseudo_regs (current_gdbarch
);
4057 if (*REGISTER_NAME (regnum
) == '\0')
4058 continue; /* unused register */
4059 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4061 break; /* end row: reached FP register */
4062 /* OK: get the data in raw format. */
4063 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4064 error (_("can't read register %d (%s)"), regnum
, REGISTER_NAME (regnum
));
4065 /* pad small registers */
4067 byte
< (mips_abi_regsize (current_gdbarch
)
4068 - register_size (current_gdbarch
, regnum
)); byte
++)
4069 printf_filtered (" ");
4070 /* Now print the register value in hex, endian order. */
4071 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4073 register_size (current_gdbarch
,
4074 regnum
) - register_size (current_gdbarch
, regnum
);
4075 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4076 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4078 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4080 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4081 fprintf_filtered (file
, " ");
4084 if (col
> 0) /* ie. if we actually printed anything... */
4085 fprintf_filtered (file
, "\n");
4090 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4093 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4094 struct frame_info
*frame
, int regnum
, int all
)
4096 if (regnum
!= -1) /* do one specified register */
4098 gdb_assert (regnum
>= gdbarch_num_regs (current_gdbarch
));
4099 if (*(REGISTER_NAME (regnum
)) == '\0')
4100 error (_("Not a valid register for the current processor type"));
4102 mips_print_register (file
, frame
, regnum
, 0);
4103 fprintf_filtered (file
, "\n");
4106 /* do all (or most) registers */
4108 regnum
= gdbarch_num_regs (current_gdbarch
);
4109 while (regnum
< gdbarch_num_regs (current_gdbarch
)
4110 + gdbarch_num_pseudo_regs (current_gdbarch
))
4112 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4115 if (all
) /* true for "INFO ALL-REGISTERS" command */
4116 regnum
= print_fp_register_row (file
, frame
, regnum
);
4118 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4121 regnum
= print_gp_register_row (file
, frame
, regnum
);
4126 /* Is this a branch with a delay slot? */
4129 is_delayed (unsigned long insn
)
4132 for (i
= 0; i
< NUMOPCODES
; ++i
)
4133 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4134 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4136 return (i
< NUMOPCODES
4137 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4138 | INSN_COND_BRANCH_DELAY
4139 | INSN_COND_BRANCH_LIKELY
)));
4143 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4144 struct frame_info
*frame
)
4146 CORE_ADDR pc
= get_frame_pc (frame
);
4147 gdb_byte buf
[MIPS_INSN32_SIZE
];
4149 /* There is no branch delay slot on MIPS16. */
4150 if (mips_pc_is_mips16 (pc
))
4153 if (!breakpoint_here_p (pc
+ 4))
4156 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4157 /* If error reading memory, guess that it is not a delayed
4160 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4163 /* To skip prologues, I use this predicate. Returns either PC itself
4164 if the code at PC does not look like a function prologue; otherwise
4165 returns an address that (if we're lucky) follows the prologue. If
4166 LENIENT, then we must skip everything which is involved in setting
4167 up the frame (it's OK to skip more, just so long as we don't skip
4168 anything which might clobber the registers which are being saved.
4169 We must skip more in the case where part of the prologue is in the
4170 delay slot of a non-prologue instruction). */
4173 mips_skip_prologue (CORE_ADDR pc
)
4176 CORE_ADDR func_addr
;
4178 /* See if we can determine the end of the prologue via the symbol table.
4179 If so, then return either PC, or the PC after the prologue, whichever
4181 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4183 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4184 if (post_prologue_pc
!= 0)
4185 return max (pc
, post_prologue_pc
);
4188 /* Can't determine prologue from the symbol table, need to examine
4191 /* Find an upper limit on the function prologue using the debug
4192 information. If the debug information could not be used to provide
4193 that bound, then use an arbitrary large number as the upper bound. */
4194 limit_pc
= skip_prologue_using_sal (pc
);
4196 limit_pc
= pc
+ 100; /* Magic. */
4198 if (mips_pc_is_mips16 (pc
))
4199 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4201 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4204 /* Root of all "set mips "/"show mips " commands. This will eventually be
4205 used for all MIPS-specific commands. */
4208 show_mips_command (char *args
, int from_tty
)
4210 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4214 set_mips_command (char *args
, int from_tty
)
4217 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4218 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4221 /* Commands to show/set the MIPS FPU type. */
4224 show_mipsfpu_command (char *args
, int from_tty
)
4227 switch (MIPS_FPU_TYPE
)
4229 case MIPS_FPU_SINGLE
:
4230 fpu
= "single-precision";
4232 case MIPS_FPU_DOUBLE
:
4233 fpu
= "double-precision";
4236 fpu
= "absent (none)";
4239 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4241 if (mips_fpu_type_auto
)
4243 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4247 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4252 set_mipsfpu_command (char *args
, int from_tty
)
4255 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4256 show_mipsfpu_command (args
, from_tty
);
4260 set_mipsfpu_single_command (char *args
, int from_tty
)
4262 struct gdbarch_info info
;
4263 gdbarch_info_init (&info
);
4264 mips_fpu_type
= MIPS_FPU_SINGLE
;
4265 mips_fpu_type_auto
= 0;
4266 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4267 instead of relying on globals. Doing that would let generic code
4268 handle the search for this specific architecture. */
4269 if (!gdbarch_update_p (info
))
4270 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4274 set_mipsfpu_double_command (char *args
, int from_tty
)
4276 struct gdbarch_info info
;
4277 gdbarch_info_init (&info
);
4278 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4279 mips_fpu_type_auto
= 0;
4280 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4281 instead of relying on globals. Doing that would let generic code
4282 handle the search for this specific architecture. */
4283 if (!gdbarch_update_p (info
))
4284 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4288 set_mipsfpu_none_command (char *args
, int from_tty
)
4290 struct gdbarch_info info
;
4291 gdbarch_info_init (&info
);
4292 mips_fpu_type
= MIPS_FPU_NONE
;
4293 mips_fpu_type_auto
= 0;
4294 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4295 instead of relying on globals. Doing that would let generic code
4296 handle the search for this specific architecture. */
4297 if (!gdbarch_update_p (info
))
4298 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4302 set_mipsfpu_auto_command (char *args
, int from_tty
)
4304 mips_fpu_type_auto
= 1;
4307 /* Attempt to identify the particular processor model by reading the
4308 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4309 the relevant processor still exists (it dates back to '94) and
4310 secondly this is not the way to do this. The processor type should
4311 be set by forcing an architecture change. */
4314 deprecated_mips_set_processor_regs_hack (void)
4316 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4319 prid
= read_register (MIPS_PRID_REGNUM
);
4321 if ((prid
& ~0xf) == 0x700)
4322 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4325 /* Just like reinit_frame_cache, but with the right arguments to be
4326 callable as an sfunc. */
4329 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4330 struct cmd_list_element
*c
)
4332 reinit_frame_cache ();
4336 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4338 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4340 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4341 disassembler needs to be able to locally determine the ISA, and
4342 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4344 if (mips_pc_is_mips16 (memaddr
))
4345 info
->mach
= bfd_mach_mips16
;
4347 /* Round down the instruction address to the appropriate boundary. */
4348 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4350 /* Set the disassembler options. */
4351 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4353 /* Set up the disassembler info, so that we get the right
4354 register names from libopcodes. */
4355 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4356 info
->disassembler_options
= "gpr-names=n32";
4358 info
->disassembler_options
= "gpr-names=64";
4359 info
->flavour
= bfd_target_elf_flavour
;
4362 /* This string is not recognized explicitly by the disassembler,
4363 but it tells the disassembler to not try to guess the ABI from
4364 the bfd elf headers, such that, if the user overrides the ABI
4365 of a program linked as NewABI, the disassembly will follow the
4366 register naming conventions specified by the user. */
4367 info
->disassembler_options
= "gpr-names=32";
4369 /* Call the appropriate disassembler based on the target endian-ness. */
4370 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4371 return print_insn_big_mips (memaddr
, info
);
4373 return print_insn_little_mips (memaddr
, info
);
4376 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4377 counter value to determine whether a 16- or 32-bit breakpoint should be
4378 used. It returns a pointer to a string of bytes that encode a breakpoint
4379 instruction, stores the length of the string to *lenptr, and adjusts pc
4380 (if necessary) to point to the actual memory location where the
4381 breakpoint should be inserted. */
4383 static const gdb_byte
*
4384 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4386 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4388 if (mips_pc_is_mips16 (*pcptr
))
4390 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4391 *pcptr
= unmake_mips16_addr (*pcptr
);
4392 *lenptr
= sizeof (mips16_big_breakpoint
);
4393 return mips16_big_breakpoint
;
4397 /* The IDT board uses an unusual breakpoint value, and
4398 sometimes gets confused when it sees the usual MIPS
4399 breakpoint instruction. */
4400 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4401 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4402 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4404 *lenptr
= sizeof (big_breakpoint
);
4406 if (strcmp (target_shortname
, "mips") == 0)
4407 return idt_big_breakpoint
;
4408 else if (strcmp (target_shortname
, "ddb") == 0
4409 || strcmp (target_shortname
, "pmon") == 0
4410 || strcmp (target_shortname
, "lsi") == 0)
4411 return pmon_big_breakpoint
;
4413 return big_breakpoint
;
4418 if (mips_pc_is_mips16 (*pcptr
))
4420 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4421 *pcptr
= unmake_mips16_addr (*pcptr
);
4422 *lenptr
= sizeof (mips16_little_breakpoint
);
4423 return mips16_little_breakpoint
;
4427 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4428 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4429 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4431 *lenptr
= sizeof (little_breakpoint
);
4433 if (strcmp (target_shortname
, "mips") == 0)
4434 return idt_little_breakpoint
;
4435 else if (strcmp (target_shortname
, "ddb") == 0
4436 || strcmp (target_shortname
, "pmon") == 0
4437 || strcmp (target_shortname
, "lsi") == 0)
4438 return pmon_little_breakpoint
;
4440 return little_breakpoint
;
4445 /* If PC is in a mips16 call or return stub, return the address of the target
4446 PC, which is either the callee or the caller. There are several
4447 cases which must be handled:
4449 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4450 target PC is in $31 ($ra).
4451 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4452 and the target PC is in $2.
4453 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4454 before the jal instruction, this is effectively a call stub
4455 and the the target PC is in $2. Otherwise this is effectively
4456 a return stub and the target PC is in $18.
4458 See the source code for the stubs in gcc/config/mips/mips16.S for
4462 mips_skip_trampoline_code (CORE_ADDR pc
)
4465 CORE_ADDR start_addr
;
4467 /* Find the starting address and name of the function containing the PC. */
4468 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4471 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4472 target PC is in $31 ($ra). */
4473 if (strcmp (name
, "__mips16_ret_sf") == 0
4474 || strcmp (name
, "__mips16_ret_df") == 0)
4475 return read_signed_register (MIPS_RA_REGNUM
);
4477 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4479 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4480 and the target PC is in $2. */
4481 if (name
[19] >= '0' && name
[19] <= '9')
4482 return read_signed_register (2);
4484 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4485 before the jal instruction, this is effectively a call stub
4486 and the the target PC is in $2. Otherwise this is effectively
4487 a return stub and the target PC is in $18. */
4488 else if (name
[19] == 's' || name
[19] == 'd')
4490 if (pc
== start_addr
)
4492 /* Check if the target of the stub is a compiler-generated
4493 stub. Such a stub for a function bar might have a name
4494 like __fn_stub_bar, and might look like this:
4499 la $1,bar (becomes a lui/addiu pair)
4501 So scan down to the lui/addi and extract the target
4502 address from those two instructions. */
4504 CORE_ADDR target_pc
= read_signed_register (2);
4508 /* See if the name of the target function is __fn_stub_*. */
4509 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4512 if (strncmp (name
, "__fn_stub_", 10) != 0
4513 && strcmp (name
, "etext") != 0
4514 && strcmp (name
, "_etext") != 0)
4517 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4518 The limit on the search is arbitrarily set to 20
4519 instructions. FIXME. */
4520 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
4522 inst
= mips_fetch_instruction (target_pc
);
4523 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4524 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4525 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4526 return pc
| (inst
& 0xffff); /* low word */
4529 /* Couldn't find the lui/addui pair, so return stub address. */
4533 /* This is the 'return' part of a call stub. The return
4534 address is in $r18. */
4535 return read_signed_register (18);
4538 return 0; /* not a stub */
4541 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4542 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4545 mips_stab_reg_to_regnum (int num
)
4548 if (num
>= 0 && num
< 32)
4550 else if (num
>= 38 && num
< 70)
4551 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4553 regnum
= mips_regnum (current_gdbarch
)->hi
;
4555 regnum
= mips_regnum (current_gdbarch
)->lo
;
4557 /* This will hopefully (eventually) provoke a warning. Should
4558 we be calling complaint() here? */
4559 return gdbarch_num_regs (current_gdbarch
)
4560 + gdbarch_num_pseudo_regs (current_gdbarch
);
4561 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4565 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4566 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4569 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4572 if (num
>= 0 && num
< 32)
4574 else if (num
>= 32 && num
< 64)
4575 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4577 regnum
= mips_regnum (current_gdbarch
)->hi
;
4579 regnum
= mips_regnum (current_gdbarch
)->lo
;
4581 /* This will hopefully (eventually) provoke a warning. Should we
4582 be calling complaint() here? */
4583 return gdbarch_num_regs (current_gdbarch
)
4584 + gdbarch_num_pseudo_regs (current_gdbarch
);
4585 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4589 mips_register_sim_regno (int regnum
)
4591 /* Only makes sense to supply raw registers. */
4592 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
));
4593 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4594 decide if it is valid. Should instead define a standard sim/gdb
4595 register numbering scheme. */
4596 if (REGISTER_NAME (gdbarch_num_regs (current_gdbarch
) + regnum
) != NULL
4597 && REGISTER_NAME (gdbarch_num_regs (current_gdbarch
) + regnum
)[0] != '\0')
4600 return LEGACY_SIM_REGNO_IGNORE
;
4604 /* Convert an integer into an address. Extracting the value signed
4605 guarantees a correctly sign extended address. */
4608 mips_integer_to_address (struct gdbarch
*gdbarch
,
4609 struct type
*type
, const gdb_byte
*buf
)
4611 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
4615 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4617 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4618 const char *name
= bfd_get_section_name (abfd
, sect
);
4620 if (*abip
!= MIPS_ABI_UNKNOWN
)
4623 if (strncmp (name
, ".mdebug.", 8) != 0)
4626 if (strcmp (name
, ".mdebug.abi32") == 0)
4627 *abip
= MIPS_ABI_O32
;
4628 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4629 *abip
= MIPS_ABI_N32
;
4630 else if (strcmp (name
, ".mdebug.abi64") == 0)
4631 *abip
= MIPS_ABI_N64
;
4632 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4633 *abip
= MIPS_ABI_O64
;
4634 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4635 *abip
= MIPS_ABI_EABI32
;
4636 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4637 *abip
= MIPS_ABI_EABI64
;
4639 warning (_("unsupported ABI %s."), name
+ 8);
4643 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
4645 int *lbp
= (int *) obj
;
4646 const char *name
= bfd_get_section_name (abfd
, sect
);
4648 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
4650 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
4652 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
4653 warning (_("unrecognized .gcc_compiled_longXX"));
4656 static enum mips_abi
4657 global_mips_abi (void)
4661 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4662 if (mips_abi_strings
[i
] == mips_abi_string
)
4663 return (enum mips_abi
) i
;
4665 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
4669 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
4671 static struct target_desc
*tdesc_gp32
, *tdesc_gp64
;
4673 if (tdesc_gp32
== NULL
)
4675 /* Create feature sets with the appropriate properties. The values
4676 are not important. */
4678 tdesc_gp32
= allocate_target_description ();
4679 set_tdesc_property (tdesc_gp32
, PROPERTY_GP32
, "");
4681 tdesc_gp64
= allocate_target_description ();
4682 set_tdesc_property (tdesc_gp64
, PROPERTY_GP64
, "");
4685 /* If the size matches the set of 32-bit or 64-bit integer registers,
4686 assume that's what we've got. */
4687 register_remote_g_packet_guess (gdbarch
, 38 * 4, tdesc_gp32
);
4688 register_remote_g_packet_guess (gdbarch
, 38 * 8, tdesc_gp64
);
4690 /* If the size matches the full set of registers GDB traditionally
4691 knows about, including floating point, for either 32-bit or
4692 64-bit, assume that's what we've got. */
4693 register_remote_g_packet_guess (gdbarch
, 90 * 4, tdesc_gp32
);
4694 register_remote_g_packet_guess (gdbarch
, 90 * 8, tdesc_gp64
);
4696 /* Otherwise we don't have a useful guess. */
4699 static struct gdbarch
*
4700 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4702 struct gdbarch
*gdbarch
;
4703 struct gdbarch_tdep
*tdep
;
4705 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4707 enum mips_fpu_type fpu_type
;
4709 /* First of all, extract the elf_flags, if available. */
4710 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4711 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4712 else if (arches
!= NULL
)
4713 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
4717 fprintf_unfiltered (gdb_stdlog
,
4718 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
4720 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4721 switch ((elf_flags
& EF_MIPS_ABI
))
4723 case E_MIPS_ABI_O32
:
4724 found_abi
= MIPS_ABI_O32
;
4726 case E_MIPS_ABI_O64
:
4727 found_abi
= MIPS_ABI_O64
;
4729 case E_MIPS_ABI_EABI32
:
4730 found_abi
= MIPS_ABI_EABI32
;
4732 case E_MIPS_ABI_EABI64
:
4733 found_abi
= MIPS_ABI_EABI64
;
4736 if ((elf_flags
& EF_MIPS_ABI2
))
4737 found_abi
= MIPS_ABI_N32
;
4739 found_abi
= MIPS_ABI_UNKNOWN
;
4743 /* GCC creates a pseudo-section whose name describes the ABI. */
4744 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4745 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
4747 /* If we have no useful BFD information, use the ABI from the last
4748 MIPS architecture (if there is one). */
4749 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
4750 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
4752 /* Try the architecture for any hint of the correct ABI. */
4753 if (found_abi
== MIPS_ABI_UNKNOWN
4754 && info
.bfd_arch_info
!= NULL
4755 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4757 switch (info
.bfd_arch_info
->mach
)
4759 case bfd_mach_mips3900
:
4760 found_abi
= MIPS_ABI_EABI32
;
4762 case bfd_mach_mips4100
:
4763 case bfd_mach_mips5000
:
4764 found_abi
= MIPS_ABI_EABI64
;
4766 case bfd_mach_mips8000
:
4767 case bfd_mach_mips10000
:
4768 /* On Irix, ELF64 executables use the N64 ABI. The
4769 pseudo-sections which describe the ABI aren't present
4770 on IRIX. (Even for executables created by gcc.) */
4771 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4772 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4773 found_abi
= MIPS_ABI_N64
;
4775 found_abi
= MIPS_ABI_N32
;
4780 /* Default 64-bit objects to N64 instead of O32. */
4781 if (found_abi
== MIPS_ABI_UNKNOWN
4782 && info
.abfd
!= NULL
4783 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4784 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4785 found_abi
= MIPS_ABI_N64
;
4788 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
4791 /* What has the user specified from the command line? */
4792 wanted_abi
= global_mips_abi ();
4794 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
4797 /* Now that we have found what the ABI for this binary would be,
4798 check whether the user is overriding it. */
4799 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
4800 mips_abi
= wanted_abi
;
4801 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
4802 mips_abi
= found_abi
;
4804 mips_abi
= MIPS_ABI_O32
;
4806 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
4809 /* Also used when doing an architecture lookup. */
4811 fprintf_unfiltered (gdb_stdlog
,
4812 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
4813 mips64_transfers_32bit_regs_p
);
4815 /* Determine the MIPS FPU type. */
4816 if (!mips_fpu_type_auto
)
4817 fpu_type
= mips_fpu_type
;
4818 else if (info
.bfd_arch_info
!= NULL
4819 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4820 switch (info
.bfd_arch_info
->mach
)
4822 case bfd_mach_mips3900
:
4823 case bfd_mach_mips4100
:
4824 case bfd_mach_mips4111
:
4825 case bfd_mach_mips4120
:
4826 fpu_type
= MIPS_FPU_NONE
;
4828 case bfd_mach_mips4650
:
4829 fpu_type
= MIPS_FPU_SINGLE
;
4832 fpu_type
= MIPS_FPU_DOUBLE
;
4835 else if (arches
!= NULL
)
4836 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
4838 fpu_type
= MIPS_FPU_DOUBLE
;
4840 fprintf_unfiltered (gdb_stdlog
,
4841 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
4843 /* Check for blatant incompatibilities. */
4845 /* If we have only 32-bit registers, then we can't debug a 64-bit
4847 if (info
.target_desc
4848 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
4849 && mips_abi
!= MIPS_ABI_EABI32
4850 && mips_abi
!= MIPS_ABI_O32
)
4853 /* try to find a pre-existing architecture */
4854 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4856 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4858 /* MIPS needs to be pedantic about which ABI the object is
4860 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4862 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4864 /* Need to be pedantic about which register virtual size is
4866 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
4867 != mips64_transfers_32bit_regs_p
)
4869 /* Be pedantic about which FPU is selected. */
4870 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
4872 return arches
->gdbarch
;
4875 /* Need a new architecture. Fill in a target specific vector. */
4876 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4877 gdbarch
= gdbarch_alloc (&info
, tdep
);
4878 tdep
->elf_flags
= elf_flags
;
4879 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
4880 tdep
->found_abi
= found_abi
;
4881 tdep
->mips_abi
= mips_abi
;
4882 tdep
->mips_fpu_type
= fpu_type
;
4883 tdep
->register_size_valid_p
= 0;
4884 tdep
->register_size
= 0;
4886 if (info
.target_desc
)
4888 /* Some useful properties can be inferred from the target. */
4889 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
4891 tdep
->register_size_valid_p
= 1;
4892 tdep
->register_size
= 4;
4894 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
4896 tdep
->register_size_valid_p
= 1;
4897 tdep
->register_size
= 8;
4901 /* Initially set everything according to the default ABI/ISA. */
4902 set_gdbarch_short_bit (gdbarch
, 16);
4903 set_gdbarch_int_bit (gdbarch
, 32);
4904 set_gdbarch_float_bit (gdbarch
, 32);
4905 set_gdbarch_double_bit (gdbarch
, 64);
4906 set_gdbarch_long_double_bit (gdbarch
, 64);
4907 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
4908 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
4909 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
4911 set_gdbarch_elf_make_msymbol_special (gdbarch
,
4912 mips_elf_make_msymbol_special
);
4914 /* Fill in the OS dependant register numbers and names. */
4916 const char **reg_names
;
4917 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
4918 struct mips_regnum
);
4919 if (info
.osabi
== GDB_OSABI_IRIX
)
4924 regnum
->badvaddr
= 66;
4927 regnum
->fp_control_status
= 69;
4928 regnum
->fp_implementation_revision
= 70;
4930 reg_names
= mips_irix_reg_names
;
4934 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
4935 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
4936 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
4937 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
4938 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
4939 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
4940 regnum
->fp_control_status
= 70;
4941 regnum
->fp_implementation_revision
= 71;
4943 if (info
.bfd_arch_info
!= NULL
4944 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
4945 reg_names
= mips_tx39_reg_names
;
4947 reg_names
= mips_generic_reg_names
;
4949 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
4950 replaced by read_pc? */
4951 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
4952 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
4953 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
4954 set_gdbarch_num_regs (gdbarch
, num_regs
);
4955 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
4956 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4957 tdep
->mips_processor_reg_names
= reg_names
;
4958 tdep
->regnum
= regnum
;
4964 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
4965 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
4966 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
4967 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
4968 tdep
->default_mask_address_p
= 0;
4969 set_gdbarch_long_bit (gdbarch
, 32);
4970 set_gdbarch_ptr_bit (gdbarch
, 32);
4971 set_gdbarch_long_long_bit (gdbarch
, 64);
4974 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
4975 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
4976 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
4977 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
4978 tdep
->default_mask_address_p
= 0;
4979 set_gdbarch_long_bit (gdbarch
, 32);
4980 set_gdbarch_ptr_bit (gdbarch
, 32);
4981 set_gdbarch_long_long_bit (gdbarch
, 64);
4983 case MIPS_ABI_EABI32
:
4984 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
4985 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
4986 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
4987 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
4988 tdep
->default_mask_address_p
= 0;
4989 set_gdbarch_long_bit (gdbarch
, 32);
4990 set_gdbarch_ptr_bit (gdbarch
, 32);
4991 set_gdbarch_long_long_bit (gdbarch
, 64);
4993 case MIPS_ABI_EABI64
:
4994 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
4995 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
4996 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
4997 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
4998 tdep
->default_mask_address_p
= 0;
4999 set_gdbarch_long_bit (gdbarch
, 64);
5000 set_gdbarch_ptr_bit (gdbarch
, 64);
5001 set_gdbarch_long_long_bit (gdbarch
, 64);
5004 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5005 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5006 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5007 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5008 tdep
->default_mask_address_p
= 0;
5009 set_gdbarch_long_bit (gdbarch
, 32);
5010 set_gdbarch_ptr_bit (gdbarch
, 32);
5011 set_gdbarch_long_long_bit (gdbarch
, 64);
5012 set_gdbarch_long_double_bit (gdbarch
, 128);
5013 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5016 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5017 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5018 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5019 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5020 tdep
->default_mask_address_p
= 0;
5021 set_gdbarch_long_bit (gdbarch
, 64);
5022 set_gdbarch_ptr_bit (gdbarch
, 64);
5023 set_gdbarch_long_long_bit (gdbarch
, 64);
5024 set_gdbarch_long_double_bit (gdbarch
, 128);
5025 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5028 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5031 /* GCC creates a pseudo-section whose name specifies the size of
5032 longs, since -mlong32 or -mlong64 may be used independent of
5033 other options. How those options affect pointer sizes is ABI and
5034 architecture dependent, so use them to override the default sizes
5035 set by the ABI. This table shows the relationship between ABI,
5036 -mlongXX, and size of pointers:
5038 ABI -mlongXX ptr bits
5039 --- -------- --------
5053 Note that for o32 and eabi32, pointers are always 32 bits
5054 regardless of any -mlongXX option. For all others, pointers and
5055 longs are the same, as set by -mlongXX or set by defaults.
5058 if (info
.abfd
!= NULL
)
5062 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5065 set_gdbarch_long_bit (gdbarch
, long_bit
);
5069 case MIPS_ABI_EABI32
:
5074 case MIPS_ABI_EABI64
:
5075 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5078 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5083 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5084 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5087 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5088 flag in object files because to do so would make it impossible to
5089 link with libraries compiled without "-gp32". This is
5090 unnecessarily restrictive.
5092 We could solve this problem by adding "-gp32" multilibs to gcc,
5093 but to set this flag before gcc is built with such multilibs will
5094 break too many systems.''
5096 But even more unhelpfully, the default linker output target for
5097 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5098 for 64-bit programs - you need to change the ABI to change this,
5099 and not all gcc targets support that currently. Therefore using
5100 this flag to detect 32-bit mode would do the wrong thing given
5101 the current gcc - it would make GDB treat these 64-bit programs
5102 as 32-bit programs by default. */
5104 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5105 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5107 /* Add/remove bits from an address. The MIPS needs be careful to
5108 ensure that all 32 bit addresses are sign extended to 64 bits. */
5109 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5111 /* Unwind the frame. */
5112 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5113 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5114 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5116 /* Map debug register numbers onto internal register numbers. */
5117 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5118 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5119 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5120 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5121 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5122 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5123 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5124 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5126 /* MIPS version of CALL_DUMMY */
5128 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5129 replaced by a command, and all targets will default to on stack
5130 (regardless of the stack's execute status). */
5131 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5132 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5134 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5135 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5136 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5138 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5139 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5141 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5143 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5144 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5145 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5147 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5149 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5151 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5153 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5154 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5155 need to all be folded into the target vector. Since they are
5156 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5157 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5159 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5161 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5163 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5165 /* Virtual tables. */
5166 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5168 mips_register_g_packet_guesses (gdbarch
);
5170 /* Hook in OS ABI-specific overrides, if they have been registered. */
5171 gdbarch_init_osabi (info
, gdbarch
);
5173 /* Unwind the frame. */
5174 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
5175 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5176 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5177 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5178 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
5179 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5180 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5181 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5187 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5189 struct gdbarch_info info
;
5191 /* Force the architecture to update, and (if it's a MIPS architecture)
5192 mips_gdbarch_init will take care of the rest. */
5193 gdbarch_info_init (&info
);
5194 gdbarch_update_p (info
);
5197 /* Print out which MIPS ABI is in use. */
5200 show_mips_abi (struct ui_file
*file
,
5202 struct cmd_list_element
*ignored_cmd
,
5203 const char *ignored_value
)
5205 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5208 "The MIPS ABI is unknown because the current architecture "
5212 enum mips_abi global_abi
= global_mips_abi ();
5213 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5214 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5216 if (global_abi
== MIPS_ABI_UNKNOWN
)
5219 "The MIPS ABI is set automatically (currently \"%s\").\n",
5221 else if (global_abi
== actual_abi
)
5224 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5228 /* Probably shouldn't happen... */
5231 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5232 actual_abi_str
, mips_abi_strings
[global_abi
]);
5238 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5240 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5244 int ef_mips_32bitmode
;
5245 /* Determine the ISA. */
5246 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5264 /* Determine the size of a pointer. */
5265 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5266 fprintf_unfiltered (file
,
5267 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5269 fprintf_unfiltered (file
,
5270 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5272 fprintf_unfiltered (file
,
5273 "mips_dump_tdep: ef_mips_arch = %d\n",
5275 fprintf_unfiltered (file
,
5276 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5277 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5278 fprintf_unfiltered (file
,
5279 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5280 mips_mask_address_p (tdep
),
5281 tdep
->default_mask_address_p
);
5283 fprintf_unfiltered (file
,
5284 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5285 MIPS_DEFAULT_FPU_TYPE
,
5286 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5287 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5288 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5290 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5291 fprintf_unfiltered (file
,
5292 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5294 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5295 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5296 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5300 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5303 _initialize_mips_tdep (void)
5305 static struct cmd_list_element
*mipsfpulist
= NULL
;
5306 struct cmd_list_element
*c
;
5308 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5309 if (MIPS_ABI_LAST
+ 1
5310 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5311 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
5313 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5315 mips_pdr_data
= register_objfile_data ();
5317 /* Add root prefix command for all "set mips"/"show mips" commands */
5318 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5319 _("Various MIPS specific commands."),
5320 &setmipscmdlist
, "set mips ", 0, &setlist
);
5322 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5323 _("Various MIPS specific commands."),
5324 &showmipscmdlist
, "show mips ", 0, &showlist
);
5326 /* Allow the user to override the ABI. */
5327 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
5328 &mips_abi_string
, _("\
5329 Set the MIPS ABI used by this program."), _("\
5330 Show the MIPS ABI used by this program."), _("\
5331 This option can be set to one of:\n\
5332 auto - the default ABI associated with the current binary\n\
5341 &setmipscmdlist
, &showmipscmdlist
);
5343 /* Let the user turn off floating point and set the fence post for
5344 heuristic_proc_start. */
5346 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5347 _("Set use of MIPS floating-point coprocessor."),
5348 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5349 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5350 _("Select single-precision MIPS floating-point coprocessor."),
5352 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5353 _("Select double-precision MIPS floating-point coprocessor."),
5355 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5356 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5357 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5358 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5359 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
5360 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5361 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5362 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5363 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5364 _("Select MIPS floating-point coprocessor automatically."),
5366 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5367 _("Show current use of MIPS floating-point coprocessor target."),
5370 /* We really would like to have both "0" and "unlimited" work, but
5371 command.c doesn't deal with that. So make it a var_zinteger
5372 because the user can always use "999999" or some such for unlimited. */
5373 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5374 &heuristic_fence_post
, _("\
5375 Set the distance searched for the start of a function."), _("\
5376 Show the distance searched for the start of a function."), _("\
5377 If you are debugging a stripped executable, GDB needs to search through the\n\
5378 program for the start of a function. This command sets the distance of the\n\
5379 search. The only need to set it is when debugging a stripped executable."),
5380 reinit_frame_cache_sfunc
,
5381 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5382 &setlist
, &showlist
);
5384 /* Allow the user to control whether the upper bits of 64-bit
5385 addresses should be zeroed. */
5386 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
5387 &mask_address_var
, _("\
5388 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5389 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5390 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5391 allow GDB to determine the correct value."),
5392 NULL
, show_mask_address
,
5393 &setmipscmdlist
, &showmipscmdlist
);
5395 /* Allow the user to control the size of 32 bit registers within the
5396 raw remote packet. */
5397 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
5398 &mips64_transfers_32bit_regs_p
, _("\
5399 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5401 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5403 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5404 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5405 64 bits for others. Use \"off\" to disable compatibility mode"),
5406 set_mips64_transfers_32bit_regs
,
5407 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
5408 &setlist
, &showlist
);
5410 /* Debug this files internals. */
5411 add_setshow_zinteger_cmd ("mips", class_maintenance
,
5413 Set mips debugging."), _("\
5414 Show mips debugging."), _("\
5415 When non-zero, mips specific debugging is enabled."),
5417 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
5418 &setdebuglist
, &showdebuglist
);