1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
63 static const struct objfile_data
*mips_pdr_data
;
65 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
67 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
68 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
69 #define ST0_FR (1 << 26)
71 /* The sizes of floating point registers. */
75 MIPS_FPU_SINGLE_REGSIZE
= 4,
76 MIPS_FPU_DOUBLE_REGSIZE
= 8
85 static const char *mips_abi_string
;
87 static const char *mips_abi_strings
[] = {
98 /* The standard register names, and all the valid aliases for them. */
105 /* Aliases for o32 and most other ABIs. */
106 const struct register_alias mips_o32_aliases
[] = {
113 /* Aliases for n32 and n64. */
114 const struct register_alias mips_n32_n64_aliases
[] = {
121 /* Aliases for ABI-independent registers. */
122 const struct register_alias mips_register_aliases
[] = {
123 /* The architecture manuals specify these ABI-independent names for
125 #define R(n) { "r" #n, n }
126 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
127 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
128 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
129 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
132 /* k0 and k1 are sometimes called these instead (for "kernel
137 /* This is the traditional GDB name for the CP0 status register. */
138 { "sr", MIPS_PS_REGNUM
},
140 /* This is the traditional GDB name for the CP0 BadVAddr register. */
141 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
143 /* This is the traditional GDB name for the FCSR. */
144 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
147 const struct register_alias mips_numeric_register_aliases
[] = {
148 #define R(n) { #n, n }
149 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
150 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
151 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
152 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
156 #ifndef MIPS_DEFAULT_FPU_TYPE
157 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
159 static int mips_fpu_type_auto
= 1;
160 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
162 static int mips_debug
= 0;
164 /* Properties (for struct target_desc) describing the g/G packet
166 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
167 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
169 struct target_desc
*mips_tdesc_gp32
;
170 struct target_desc
*mips_tdesc_gp64
;
172 const struct mips_regnum
*
173 mips_regnum (struct gdbarch
*gdbarch
)
175 return gdbarch_tdep (gdbarch
)->regnum
;
179 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
181 return mips_regnum (gdbarch
)->fp0
+ 12;
184 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
186 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
188 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
189 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
191 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
192 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
194 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
196 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
197 functions to test, set, or clear bit 0 of addresses. */
200 is_mips16_addr (CORE_ADDR addr
)
206 unmake_mips16_addr (CORE_ADDR addr
)
208 return ((addr
) & ~(CORE_ADDR
) 1);
212 make_mips16_addr (CORE_ADDR addr
)
214 return ((addr
) | (CORE_ADDR
) 1);
217 /* Return the MIPS ABI associated with GDBARCH. */
219 mips_abi (struct gdbarch
*gdbarch
)
221 return gdbarch_tdep (gdbarch
)->mips_abi
;
225 mips_isa_regsize (struct gdbarch
*gdbarch
)
227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
229 /* If we know how big the registers are, use that size. */
230 if (tdep
->register_size_valid_p
)
231 return tdep
->register_size
;
233 /* Fall back to the previous behavior. */
234 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
235 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
238 /* Return the currently configured (or set) saved register size. */
241 mips_abi_regsize (struct gdbarch
*gdbarch
)
243 switch (mips_abi (gdbarch
))
245 case MIPS_ABI_EABI32
:
251 case MIPS_ABI_EABI64
:
253 case MIPS_ABI_UNKNOWN
:
256 internal_error (__FILE__
, __LINE__
, _("bad switch"));
260 /* Functions for setting and testing a bit in a minimal symbol that
261 marks it as 16-bit function. The MSB of the minimal symbol's
262 "info" field is used for this purpose.
264 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
265 i.e. refers to a 16-bit function, and sets a "special" bit in a
266 minimal symbol to mark it as a 16-bit function
268 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
271 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
273 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
275 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
280 msymbol_is_special (struct minimal_symbol
*msym
)
282 return MSYMBOL_TARGET_FLAG_1 (msym
);
285 /* XFER a value from the big/little/left end of the register.
286 Depending on the size of the value it might occupy the entire
287 register or just part of it. Make an allowance for this, aligning
288 things accordingly. */
291 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
292 int reg_num
, int length
,
293 enum bfd_endian endian
, gdb_byte
*in
,
294 const gdb_byte
*out
, int buf_offset
)
298 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
299 /* Need to transfer the left or right part of the register, based on
300 the targets byte order. */
304 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
306 case BFD_ENDIAN_LITTLE
:
309 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
313 internal_error (__FILE__
, __LINE__
, _("bad switch"));
316 fprintf_unfiltered (gdb_stderr
,
317 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
318 reg_num
, reg_offset
, buf_offset
, length
);
319 if (mips_debug
&& out
!= NULL
)
322 fprintf_unfiltered (gdb_stdlog
, "out ");
323 for (i
= 0; i
< length
; i
++)
324 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
327 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
330 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
332 if (mips_debug
&& in
!= NULL
)
335 fprintf_unfiltered (gdb_stdlog
, "in ");
336 for (i
= 0; i
< length
; i
++)
337 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
340 fprintf_unfiltered (gdb_stdlog
, "\n");
343 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
344 compatiblity mode. A return value of 1 means that we have
345 physical 64-bit registers, but should treat them as 32-bit registers. */
348 mips2_fp_compat (struct frame_info
*frame
)
350 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
351 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
353 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
357 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
358 in all the places we deal with FP registers. PR gdb/413. */
359 /* Otherwise check the FR bit in the status register - it controls
360 the FP compatiblity mode. If it is clear we are in compatibility
362 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
369 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
371 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
373 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
375 /* The list of available "set mips " and "show mips " commands. */
377 static struct cmd_list_element
*setmipscmdlist
= NULL
;
378 static struct cmd_list_element
*showmipscmdlist
= NULL
;
380 /* Integer registers 0 thru 31 are handled explicitly by
381 mips_register_name(). Processor specific registers 32 and above
382 are listed in the following tables. */
385 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
389 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
390 "sr", "lo", "hi", "bad", "cause", "pc",
391 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
392 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
393 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
394 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
395 "fsr", "fir", "" /*"fp" */ , "",
396 "", "", "", "", "", "", "", "",
397 "", "", "", "", "", "", "", "",
400 /* Names of IDT R3041 registers. */
402 static const char *mips_r3041_reg_names
[] = {
403 "sr", "lo", "hi", "bad", "cause", "pc",
404 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
405 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
406 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
407 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
408 "fsr", "fir", "", /*"fp" */ "",
409 "", "", "bus", "ccfg", "", "", "", "",
410 "", "", "port", "cmp", "", "", "epc", "prid",
413 /* Names of tx39 registers. */
415 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
416 "sr", "lo", "hi", "bad", "cause", "pc",
417 "", "", "", "", "", "", "", "",
418 "", "", "", "", "", "", "", "",
419 "", "", "", "", "", "", "", "",
420 "", "", "", "", "", "", "", "",
422 "", "", "", "", "", "", "", "",
423 "", "", "config", "cache", "debug", "depc", "epc", ""
426 /* Names of IRIX registers. */
427 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
428 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
429 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
430 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
431 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
432 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
436 /* Return the name of the register corresponding to REGNO. */
438 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
440 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
441 /* GPR names for all ABIs other than n32/n64. */
442 static char *mips_gpr_names
[] = {
443 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
444 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
445 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
446 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
449 /* GPR names for n32 and n64 ABIs. */
450 static char *mips_n32_n64_gpr_names
[] = {
451 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
452 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
453 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
454 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
457 enum mips_abi abi
= mips_abi (gdbarch
);
459 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
460 but then don't make the raw register names visible. This (upper)
461 range of user visible register numbers are the pseudo-registers.
463 This approach was adopted accommodate the following scenario:
464 It is possible to debug a 64-bit device using a 32-bit
465 programming model. In such instances, the raw registers are
466 configured to be 64-bits wide, while the pseudo registers are
467 configured to be 32-bits wide. The registers that the user
468 sees - the pseudo registers - match the users expectations
469 given the programming model being used. */
470 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
471 if (regno
< gdbarch_num_regs (gdbarch
))
474 /* The MIPS integer registers are always mapped from 0 to 31. The
475 names of the registers (which reflects the conventions regarding
476 register use) vary depending on the ABI. */
477 if (0 <= rawnum
&& rawnum
< 32)
479 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
480 return mips_n32_n64_gpr_names
[rawnum
];
482 return mips_gpr_names
[rawnum
];
484 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
485 return tdesc_register_name (gdbarch
, rawnum
);
486 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
488 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
489 return tdep
->mips_processor_reg_names
[rawnum
- 32];
492 internal_error (__FILE__
, __LINE__
,
493 _("mips_register_name: bad register number %d"), rawnum
);
496 /* Return the groups that a MIPS register can be categorised into. */
499 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
500 struct reggroup
*reggroup
)
505 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
506 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
507 if (reggroup
== all_reggroup
)
509 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
510 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
511 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
512 (gdbarch), as not all architectures are multi-arch. */
513 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
514 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
515 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
517 if (reggroup
== float_reggroup
)
518 return float_p
&& pseudo
;
519 if (reggroup
== vector_reggroup
)
520 return vector_p
&& pseudo
;
521 if (reggroup
== general_reggroup
)
522 return (!vector_p
&& !float_p
) && pseudo
;
523 /* Save the pseudo registers. Need to make certain that any code
524 extracting register values from a saved register cache also uses
526 if (reggroup
== save_reggroup
)
527 return raw_p
&& pseudo
;
528 /* Restore the same pseudo register. */
529 if (reggroup
== restore_reggroup
)
530 return raw_p
&& pseudo
;
534 /* Return the groups that a MIPS register can be categorised into.
535 This version is only used if we have a target description which
536 describes real registers (and their groups). */
539 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
540 struct reggroup
*reggroup
)
542 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
543 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
546 /* Only save, restore, and display the pseudo registers. Need to
547 make certain that any code extracting register values from a
548 saved register cache also uses pseudo registers.
550 Note: saving and restoring the pseudo registers is slightly
551 strange; if we have 64 bits, we should save and restore all
552 64 bits. But this is hard and has little benefit. */
556 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
560 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
563 /* Map the symbol table registers which live in the range [1 *
564 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
565 registers. Take care of alignment and size problems. */
567 static enum register_status
568 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
569 int cookednum
, gdb_byte
*buf
)
571 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
572 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
573 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
574 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
575 return regcache_raw_read (regcache
, rawnum
, buf
);
576 else if (register_size (gdbarch
, rawnum
) >
577 register_size (gdbarch
, cookednum
))
579 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
580 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
583 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
585 enum register_status status
;
587 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
588 if (status
== REG_VALID
)
589 store_signed_integer (buf
, 4, byte_order
, regval
);
594 internal_error (__FILE__
, __LINE__
, _("bad register size"));
598 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
599 struct regcache
*regcache
, int cookednum
,
602 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
603 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
604 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
605 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
606 regcache_raw_write (regcache
, rawnum
, buf
);
607 else if (register_size (gdbarch
, rawnum
) >
608 register_size (gdbarch
, cookednum
))
610 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
611 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
614 /* Sign extend the shortened version of the register prior
615 to placing it in the raw register. This is required for
616 some mips64 parts in order to avoid unpredictable behavior. */
617 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
618 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
619 regcache_raw_write_signed (regcache
, rawnum
, regval
);
623 internal_error (__FILE__
, __LINE__
, _("bad register size"));
627 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
628 struct agent_expr
*ax
, int reg
)
630 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
631 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
632 && reg
< 2 * gdbarch_num_regs (gdbarch
));
634 ax_reg_mask (ax
, rawnum
);
640 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
641 struct agent_expr
*ax
, int reg
)
643 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
644 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
645 && reg
< 2 * gdbarch_num_regs (gdbarch
));
646 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
650 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
652 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
653 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
656 ax_simple (ax
, aop_lsh
);
659 ax_simple (ax
, aop_rsh_signed
);
663 internal_error (__FILE__
, __LINE__
, _("bad register size"));
668 /* Table to translate MIPS16 register field to actual register number. */
669 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
671 /* Heuristic_proc_start may hunt through the text section for a long
672 time across a 2400 baud serial line. Allows the user to limit this
675 static unsigned int heuristic_fence_post
= 0;
677 /* Number of bytes of storage in the actual machine representation for
678 register N. NOTE: This defines the pseudo register type so need to
679 rebuild the architecture vector. */
681 static int mips64_transfers_32bit_regs_p
= 0;
684 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
685 struct cmd_list_element
*c
)
687 struct gdbarch_info info
;
688 gdbarch_info_init (&info
);
689 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
690 instead of relying on globals. Doing that would let generic code
691 handle the search for this specific architecture. */
692 if (!gdbarch_update_p (info
))
694 mips64_transfers_32bit_regs_p
= 0;
695 error (_("32-bit compatibility mode not supported"));
699 /* Convert to/from a register and the corresponding memory value. */
701 /* This predicate tests for the case of an 8 byte floating point
702 value that is being transferred to or from a pair of floating point
703 registers each of which are (or are considered to be) only 4 bytes
706 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
709 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
710 && register_size (gdbarch
, regnum
) == 4
711 && (regnum
% gdbarch_num_regs (gdbarch
))
712 >= mips_regnum (gdbarch
)->fp0
713 && (regnum
% gdbarch_num_regs (gdbarch
))
714 < mips_regnum (gdbarch
)->fp0
+ 32
715 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
718 /* This predicate tests for the case of a value of less than 8
719 bytes in width that is being transfered to or from an 8 byte
720 general purpose register. */
722 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
725 int num_regs
= gdbarch_num_regs (gdbarch
);
727 return (register_size (gdbarch
, regnum
) == 8
728 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
729 && TYPE_LENGTH (type
) < 8);
733 mips_convert_register_p (struct gdbarch
*gdbarch
,
734 int regnum
, struct type
*type
)
736 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
737 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
741 mips_register_to_value (struct frame_info
*frame
, int regnum
,
742 struct type
*type
, gdb_byte
*to
,
743 int *optimizedp
, int *unavailablep
)
745 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
747 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
749 get_frame_register (frame
, regnum
+ 0, to
+ 4);
750 get_frame_register (frame
, regnum
+ 1, to
+ 0);
752 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
753 optimizedp
, unavailablep
))
756 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
757 optimizedp
, unavailablep
))
759 *optimizedp
= *unavailablep
= 0;
762 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
764 int len
= TYPE_LENGTH (type
);
767 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
768 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
769 optimizedp
, unavailablep
))
772 *optimizedp
= *unavailablep
= 0;
777 internal_error (__FILE__
, __LINE__
,
778 _("mips_register_to_value: unrecognized case"));
783 mips_value_to_register (struct frame_info
*frame
, int regnum
,
784 struct type
*type
, const gdb_byte
*from
)
786 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
788 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
790 put_frame_register (frame
, regnum
+ 0, from
+ 4);
791 put_frame_register (frame
, regnum
+ 1, from
+ 0);
793 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
796 int len
= TYPE_LENGTH (type
);
798 /* Sign extend values, irrespective of type, that are stored to
799 a 64-bit general purpose register. (32-bit unsigned values
800 are stored as signed quantities within a 64-bit register.
801 When performing an operation, in compiled code, that combines
802 a 32-bit unsigned value with a signed 64-bit value, a type
803 conversion is first performed that zeroes out the high 32 bits.) */
804 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
807 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
809 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
810 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
811 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
815 if (from
[len
-1] & 0x80)
816 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
818 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
819 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
820 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
825 internal_error (__FILE__
, __LINE__
,
826 _("mips_value_to_register: unrecognized case"));
830 /* Return the GDB type object for the "standard" data type of data in
834 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
836 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
837 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
838 && (regnum
% gdbarch_num_regs (gdbarch
))
839 < mips_regnum (gdbarch
)->fp0
+ 32)
841 /* The floating-point registers raw, or cooked, always match
842 mips_isa_regsize(), and also map 1:1, byte for byte. */
843 if (mips_isa_regsize (gdbarch
) == 4)
844 return builtin_type (gdbarch
)->builtin_float
;
846 return builtin_type (gdbarch
)->builtin_double
;
848 else if (regnum
< gdbarch_num_regs (gdbarch
))
850 /* The raw or ISA registers. These are all sized according to
852 if (mips_isa_regsize (gdbarch
) == 4)
853 return builtin_type (gdbarch
)->builtin_int32
;
855 return builtin_type (gdbarch
)->builtin_int64
;
859 /* The cooked or ABI registers. These are sized according to
860 the ABI (with a few complications). */
861 if (regnum
>= (gdbarch_num_regs (gdbarch
)
862 + mips_regnum (gdbarch
)->fp_control_status
)
863 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
864 /* The pseudo/cooked view of the embedded registers is always
865 32-bit. The raw view is handled below. */
866 return builtin_type (gdbarch
)->builtin_int32
;
867 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
868 /* The target, while possibly using a 64-bit register buffer,
869 is only transfering 32-bits of each integer register.
870 Reflect this in the cooked/pseudo (ABI) register value. */
871 return builtin_type (gdbarch
)->builtin_int32
;
872 else if (mips_abi_regsize (gdbarch
) == 4)
873 /* The ABI is restricted to 32-bit registers (the ISA could be
875 return builtin_type (gdbarch
)->builtin_int32
;
878 return builtin_type (gdbarch
)->builtin_int64
;
882 /* Return the GDB type for the pseudo register REGNUM, which is the
883 ABI-level view. This function is only called if there is a target
884 description which includes registers, so we know precisely the
885 types of hardware registers. */
888 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
890 const int num_regs
= gdbarch_num_regs (gdbarch
);
891 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
892 int rawnum
= regnum
% num_regs
;
893 struct type
*rawtype
;
895 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
897 /* Absent registers are still absent. */
898 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
899 if (TYPE_LENGTH (rawtype
) == 0)
902 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
903 /* Present the floating point registers however the hardware did;
904 do not try to convert between FPU layouts. */
907 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
909 /* The pseudo/cooked view of embedded registers is always
910 32-bit, even if the target transfers 64-bit values for them.
911 New targets relying on XML descriptions should only transfer
912 the necessary 32 bits, but older versions of GDB expected 64,
913 so allow the target to provide 64 bits without interfering
914 with the displayed type. */
915 return builtin_type (gdbarch
)->builtin_int32
;
918 /* Use pointer types for registers if we can. For n32 we can not,
919 since we do not have a 64-bit pointer type. */
920 if (mips_abi_regsize (gdbarch
)
921 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
923 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
924 return builtin_type (gdbarch
)->builtin_data_ptr
;
925 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
926 return builtin_type (gdbarch
)->builtin_func_ptr
;
929 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
930 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
931 return builtin_type (gdbarch
)->builtin_int32
;
933 /* For all other registers, pass through the hardware type. */
937 /* Should the upper word of 64-bit addresses be zeroed? */
938 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
941 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
943 switch (mask_address_var
)
945 case AUTO_BOOLEAN_TRUE
:
947 case AUTO_BOOLEAN_FALSE
:
950 case AUTO_BOOLEAN_AUTO
:
951 return tdep
->default_mask_address_p
;
953 internal_error (__FILE__
, __LINE__
,
954 _("mips_mask_address_p: bad switch"));
960 show_mask_address (struct ui_file
*file
, int from_tty
,
961 struct cmd_list_element
*c
, const char *value
)
963 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
965 deprecated_show_value_hack (file
, from_tty
, c
, value
);
966 switch (mask_address_var
)
968 case AUTO_BOOLEAN_TRUE
:
969 printf_filtered ("The 32 bit mips address mask is enabled\n");
971 case AUTO_BOOLEAN_FALSE
:
972 printf_filtered ("The 32 bit mips address mask is disabled\n");
974 case AUTO_BOOLEAN_AUTO
:
976 ("The 32 bit address mask is set automatically. Currently %s\n",
977 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
980 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
985 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
988 mips_pc_is_mips16 (CORE_ADDR memaddr
)
990 struct minimal_symbol
*sym
;
992 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
993 if (is_mips16_addr (memaddr
))
996 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
997 the high bit of the info field. Use this to decide if the function is
998 MIPS16 or normal MIPS. */
999 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1001 return msymbol_is_special (sym
);
1006 /* MIPS believes that the PC has a sign extended value. Perhaps the
1007 all registers should be sign extended for simplicity? */
1010 mips_read_pc (struct regcache
*regcache
)
1013 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1014 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1015 if (is_mips16_addr (pc
))
1016 pc
= unmake_mips16_addr (pc
);
1021 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1025 pc
= frame_unwind_register_signed
1026 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
1027 if (is_mips16_addr (pc
))
1028 pc
= unmake_mips16_addr (pc
);
1033 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1035 return frame_unwind_register_signed
1036 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1039 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1040 dummy frame. The frame ID's base needs to match the TOS value
1041 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1044 static struct frame_id
1045 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1047 return frame_id_build
1048 (get_frame_register_signed (this_frame
,
1049 gdbarch_num_regs (gdbarch
)
1051 get_frame_pc (this_frame
));
1055 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1057 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1058 if (mips_pc_is_mips16 (pc
))
1059 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
1061 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1064 /* Fetch and return instruction from the specified location. If the PC
1065 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1068 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1070 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1071 gdb_byte buf
[MIPS_INSN32_SIZE
];
1075 if (mips_pc_is_mips16 (addr
))
1077 instlen
= MIPS_INSN16_SIZE
;
1078 addr
= unmake_mips16_addr (addr
);
1081 instlen
= MIPS_INSN32_SIZE
;
1082 status
= target_read_memory (addr
, buf
, instlen
);
1084 memory_error (status
, addr
);
1085 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1088 /* These are the fields of 32 bit mips instructions. */
1089 #define mips32_op(x) (x >> 26)
1090 #define itype_op(x) (x >> 26)
1091 #define itype_rs(x) ((x >> 21) & 0x1f)
1092 #define itype_rt(x) ((x >> 16) & 0x1f)
1093 #define itype_immediate(x) (x & 0xffff)
1095 #define jtype_op(x) (x >> 26)
1096 #define jtype_target(x) (x & 0x03ffffff)
1098 #define rtype_op(x) (x >> 26)
1099 #define rtype_rs(x) ((x >> 21) & 0x1f)
1100 #define rtype_rt(x) ((x >> 16) & 0x1f)
1101 #define rtype_rd(x) ((x >> 11) & 0x1f)
1102 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1103 #define rtype_funct(x) (x & 0x3f)
1106 mips32_relative_offset (ULONGEST inst
)
1108 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1111 /* Determine where to set a single step breakpoint while considering
1112 branch prediction. */
1114 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1116 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1119 inst
= mips_fetch_instruction (gdbarch
, pc
);
1120 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1123 if (itype_op (inst
) >> 2 == 5)
1124 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1126 op
= (itype_op (inst
) & 0x03);
1136 goto greater_branch
;
1141 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1142 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1144 int tf
= itype_rt (inst
) & 0x01;
1145 int cnum
= itype_rt (inst
) >> 2;
1147 get_frame_register_signed (frame
,
1148 mips_regnum (get_frame_arch (frame
))->
1150 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1152 if (((cond
>> cnum
) & 0x01) == tf
)
1153 pc
+= mips32_relative_offset (inst
) + 4;
1158 pc
+= 4; /* Not a branch, next instruction is easy. */
1161 { /* This gets way messy. */
1163 /* Further subdivide into SPECIAL, REGIMM and other. */
1164 switch (op
= itype_op (inst
) & 0x07) /* Extract bits 28,27,26. */
1166 case 0: /* SPECIAL */
1167 op
= rtype_funct (inst
);
1172 /* Set PC to that address. */
1173 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1175 case 12: /* SYSCALL */
1177 struct gdbarch_tdep
*tdep
;
1179 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1180 if (tdep
->syscall_next_pc
!= NULL
)
1181 pc
= tdep
->syscall_next_pc (frame
);
1190 break; /* end SPECIAL */
1191 case 1: /* REGIMM */
1193 op
= itype_rt (inst
); /* branch condition */
1198 case 16: /* BLTZAL */
1199 case 18: /* BLTZALL */
1201 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1202 pc
+= mips32_relative_offset (inst
) + 4;
1204 pc
+= 8; /* after the delay slot */
1208 case 17: /* BGEZAL */
1209 case 19: /* BGEZALL */
1210 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1211 pc
+= mips32_relative_offset (inst
) + 4;
1213 pc
+= 8; /* after the delay slot */
1215 /* All of the other instructions in the REGIMM category */
1220 break; /* end REGIMM */
1225 reg
= jtype_target (inst
) << 2;
1226 /* Upper four bits get never changed... */
1227 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1230 /* FIXME case JALX : */
1233 reg
= jtype_target (inst
) << 2;
1234 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1235 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1237 break; /* The new PC will be alternate mode */
1238 case 4: /* BEQ, BEQL */
1240 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1241 get_frame_register_signed (frame
, itype_rt (inst
)))
1242 pc
+= mips32_relative_offset (inst
) + 4;
1246 case 5: /* BNE, BNEL */
1248 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1249 get_frame_register_signed (frame
, itype_rt (inst
)))
1250 pc
+= mips32_relative_offset (inst
) + 4;
1254 case 6: /* BLEZ, BLEZL */
1255 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1256 pc
+= mips32_relative_offset (inst
) + 4;
1262 greater_branch
: /* BGTZ, BGTZL */
1263 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1264 pc
+= mips32_relative_offset (inst
) + 4;
1271 } /* mips32_next_pc */
1273 /* Decoding the next place to set a breakpoint is irregular for the
1274 mips 16 variant, but fortunately, there fewer instructions. We have
1275 to cope ith extensions for 16 bit instructions and a pair of actual
1276 32 bit instructions. We dont want to set a single step instruction
1277 on the extend instruction either. */
1279 /* Lots of mips16 instruction formats */
1280 /* Predicting jumps requires itype,ritype,i8type
1281 and their extensions extItype,extritype,extI8type. */
1282 enum mips16_inst_fmts
1284 itype
, /* 0 immediate 5,10 */
1285 ritype
, /* 1 5,3,8 */
1286 rrtype
, /* 2 5,3,3,5 */
1287 rritype
, /* 3 5,3,3,5 */
1288 rrrtype
, /* 4 5,3,3,3,2 */
1289 rriatype
, /* 5 5,3,3,1,4 */
1290 shifttype
, /* 6 5,3,3,3,2 */
1291 i8type
, /* 7 5,3,8 */
1292 i8movtype
, /* 8 5,3,3,5 */
1293 i8mov32rtype
, /* 9 5,3,5,3 */
1294 i64type
, /* 10 5,3,8 */
1295 ri64type
, /* 11 5,3,3,5 */
1296 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1297 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1298 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1299 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1300 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1301 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1302 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1303 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1304 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1305 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1307 /* I am heaping all the fields of the formats into one structure and
1308 then, only the fields which are involved in instruction extension. */
1312 unsigned int regx
; /* Function in i8 type. */
1317 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1318 for the bits which make up the immediate extension. */
1321 extended_offset (unsigned int extension
)
1324 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1326 value
|= (extension
>> 16) & 0x1f; /* extract 10:5 */
1328 value
|= extension
& 0x01f; /* extract 4:0 */
1332 /* Only call this function if you know that this is an extendable
1333 instruction. It won't malfunction, but why make excess remote memory
1334 references? If the immediate operands get sign extended or something,
1335 do it after the extension is performed. */
1336 /* FIXME: Every one of these cases needs to worry about sign extension
1337 when the offset is to be used in relative addressing. */
1340 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1342 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1344 pc
&= 0xfffffffe; /* Clear the low order bit. */
1345 target_read_memory (pc
, buf
, 2);
1346 return extract_unsigned_integer (buf
, 2, byte_order
);
1350 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1351 unsigned int extension
,
1353 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1358 switch (insn_format
)
1365 value
= extended_offset (extension
);
1366 value
= value
<< 11; /* rom for the original value */
1367 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1371 value
= inst
& 0x7ff;
1372 /* FIXME : Consider sign extension. */
1381 { /* A register identifier and an offset. */
1382 /* Most of the fields are the same as I type but the
1383 immediate value is of a different length. */
1387 value
= extended_offset (extension
);
1388 value
= value
<< 8; /* from the original instruction */
1389 value
|= inst
& 0xff; /* eleven bits from instruction */
1390 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1391 if (value
& 0x4000) /* Test the sign bit, bit 26. */
1393 value
&= ~0x3fff; /* Remove the sign bit. */
1399 value
= inst
& 0xff; /* 8 bits */
1400 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1401 /* FIXME: Do sign extension, this format needs it. */
1402 if (value
& 0x80) /* THIS CONFUSES ME. */
1404 value
&= 0xef; /* Remove the sign bit. */
1414 unsigned long value
;
1415 unsigned int nexthalf
;
1416 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1417 value
= value
<< 16;
1418 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit
1427 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1429 upk
->offset
= offset
;
1436 add_offset_16 (CORE_ADDR pc
, int offset
)
1438 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1442 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1443 unsigned int extension
, unsigned int insn
)
1445 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1446 int op
= (insn
>> 11);
1449 case 2: /* Branch */
1452 struct upk_mips16 upk
;
1453 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1454 offset
= upk
.offset
;
1460 pc
+= (offset
<< 1) + 2;
1463 case 3: /* JAL , JALX - Watch out, these are 32 bit
1466 struct upk_mips16 upk
;
1467 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1468 pc
= add_offset_16 (pc
, upk
.offset
);
1469 if ((insn
>> 10) & 0x01) /* Exchange mode */
1470 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
1477 struct upk_mips16 upk
;
1479 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1480 reg
= get_frame_register_signed (frame
, upk
.regx
);
1482 pc
+= (upk
.offset
<< 1) + 2;
1489 struct upk_mips16 upk
;
1491 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1492 reg
= get_frame_register_signed (frame
, upk
.regx
);
1494 pc
+= (upk
.offset
<< 1) + 2;
1499 case 12: /* I8 Formats btez btnez */
1501 struct upk_mips16 upk
;
1503 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1504 /* upk.regx contains the opcode */
1505 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1506 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1507 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1508 /* pc = add_offset_16(pc,upk.offset) ; */
1509 pc
+= (upk
.offset
<< 1) + 2;
1514 case 29: /* RR Formats JR, JALR, JALR-RA */
1516 struct upk_mips16 upk
;
1517 /* upk.fmt = rrtype; */
1522 upk
.regx
= (insn
>> 8) & 0x07;
1523 upk
.regy
= (insn
>> 5) & 0x07;
1531 break; /* Function return instruction. */
1537 break; /* BOGUS Guess */
1539 pc
= get_frame_register_signed (frame
, reg
);
1546 /* This is an instruction extension. Fetch the real instruction
1547 (which follows the extension) and decode things based on
1551 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1552 fetch_mips_16 (gdbarch
, pc
));
1565 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1567 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1568 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1569 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1572 /* The mips_next_pc function supports single_step when the remote
1573 target monitor or stub is not developed enough to do a single_step.
1574 It works by decoding the current instruction and predicting where a
1575 branch will go. This isnt hard because all the data is available.
1576 The MIPS32 and MIPS16 variants are quite different. */
1578 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1580 if (is_mips16_addr (pc
))
1581 return mips16_next_pc (frame
, pc
);
1583 return mips32_next_pc (frame
, pc
);
1586 struct mips_frame_cache
1589 struct trad_frame_saved_reg
*saved_regs
;
1592 /* Set a register's saved stack address in temp_saved_regs. If an
1593 address has already been set for this register, do nothing; this
1594 way we will only recognize the first save of a given register in a
1597 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1598 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1599 Strictly speaking, only the second range is used as it is only second
1600 range (the ABI instead of ISA registers) that comes into play when finding
1601 saved registers in a frame. */
1604 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1605 int regnum
, CORE_ADDR offset
)
1607 if (this_cache
!= NULL
1608 && this_cache
->saved_regs
[regnum
].addr
== -1)
1610 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1612 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1618 /* Fetch the immediate value from a MIPS16 instruction.
1619 If the previous instruction was an EXTEND, use it to extend
1620 the upper bits of the immediate value. This is a helper function
1621 for mips16_scan_prologue. */
1624 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1625 unsigned short inst
, /* current instruction */
1626 int nbits
, /* number of bits in imm field */
1627 int scale
, /* scale factor to be applied to imm */
1628 int is_signed
) /* is the imm field signed? */
1632 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1634 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1635 if (offset
& 0x8000) /* check for negative extend */
1636 offset
= 0 - (0x10000 - (offset
& 0xffff));
1637 return offset
| (inst
& 0x1f);
1641 int max_imm
= 1 << nbits
;
1642 int mask
= max_imm
- 1;
1643 int sign_bit
= max_imm
>> 1;
1645 offset
= inst
& mask
;
1646 if (is_signed
&& (offset
& sign_bit
))
1647 offset
= 0 - (max_imm
- offset
);
1648 return offset
* scale
;
1653 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1654 the associated FRAME_CACHE if not null.
1655 Return the address of the first instruction past the prologue. */
1658 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1659 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1660 struct frame_info
*this_frame
,
1661 struct mips_frame_cache
*this_cache
)
1664 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
1666 long frame_offset
= 0; /* Size of stack frame. */
1667 long frame_adjust
= 0; /* Offset of FP from SP. */
1668 int frame_reg
= MIPS_SP_REGNUM
;
1669 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
1670 unsigned inst
= 0; /* current instruction */
1671 unsigned entry_inst
= 0; /* the entry instruction */
1672 unsigned save_inst
= 0; /* the save instruction */
1675 int extend_bytes
= 0;
1676 int prev_extend_bytes
;
1677 CORE_ADDR end_prologue_addr
= 0;
1679 /* Can be called when there's no process, and hence when there's no
1681 if (this_frame
!= NULL
)
1682 sp
= get_frame_register_signed (this_frame
,
1683 gdbarch_num_regs (gdbarch
)
1688 if (limit_pc
> start_pc
+ 200)
1689 limit_pc
= start_pc
+ 200;
1691 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1693 /* Save the previous instruction. If it's an EXTEND, we'll extract
1694 the immediate offset extension from it in mips16_get_imm. */
1697 /* Fetch and decode the instruction. */
1698 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1700 /* Normally we ignore extend instructions. However, if it is
1701 not followed by a valid prologue instruction, then this
1702 instruction is not part of the prologue either. We must
1703 remember in this case to adjust the end_prologue_addr back
1705 if ((inst
& 0xf800) == 0xf000) /* extend */
1707 extend_bytes
= MIPS_INSN16_SIZE
;
1711 prev_extend_bytes
= extend_bytes
;
1714 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1715 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1717 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1718 if (offset
< 0) /* Negative stack adjustment? */
1719 frame_offset
-= offset
;
1721 /* Exit loop if a positive stack adjustment is found, which
1722 usually means that the stack cleanup code in the function
1723 epilogue is reached. */
1726 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1728 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1729 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1730 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1732 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1734 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1735 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1736 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1738 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1740 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1741 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1743 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1745 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1746 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1748 else if (inst
== 0x673d) /* move $s1, $sp */
1753 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1755 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1756 frame_addr
= sp
+ offset
;
1758 frame_adjust
= offset
;
1760 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1762 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1763 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1764 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1766 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1768 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1769 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1770 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1772 else if ((inst
& 0xf81f) == 0xe809
1773 && (inst
& 0x700) != 0x700) /* entry */
1774 entry_inst
= inst
; /* Save for later processing. */
1775 else if ((inst
& 0xff80) == 0x6480) /* save */
1777 save_inst
= inst
; /* Save for later processing. */
1778 if (prev_extend_bytes
) /* extend */
1779 save_inst
|= prev_inst
<< 16;
1781 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1782 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1783 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1785 /* This instruction is part of the prologue, but we don't
1786 need to do anything special to handle it. */
1790 /* This instruction is not an instruction typically found
1791 in a prologue, so we must have reached the end of the
1793 if (end_prologue_addr
== 0)
1794 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1798 /* The entry instruction is typically the first instruction in a function,
1799 and it stores registers at offsets relative to the value of the old SP
1800 (before the prologue). But the value of the sp parameter to this
1801 function is the new SP (after the prologue has been executed). So we
1802 can't calculate those offsets until we've seen the entire prologue,
1803 and can calculate what the old SP must have been. */
1804 if (entry_inst
!= 0)
1806 int areg_count
= (entry_inst
>> 8) & 7;
1807 int sreg_count
= (entry_inst
>> 6) & 3;
1809 /* The entry instruction always subtracts 32 from the SP. */
1812 /* Now we can calculate what the SP must have been at the
1813 start of the function prologue. */
1816 /* Check if a0-a3 were saved in the caller's argument save area. */
1817 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1819 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1820 offset
+= mips_abi_regsize (gdbarch
);
1823 /* Check if the ra register was pushed on the stack. */
1825 if (entry_inst
& 0x20)
1827 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1828 offset
-= mips_abi_regsize (gdbarch
);
1831 /* Check if the s0 and s1 registers were pushed on the stack. */
1832 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1834 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1835 offset
-= mips_abi_regsize (gdbarch
);
1839 /* The SAVE instruction is similar to ENTRY, except that defined by the
1840 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1841 size of the frame is specified as an immediate field of instruction
1842 and an extended variation exists which lets additional registers and
1843 frame space to be specified. The instruction always treats registers
1844 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1845 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1847 static int args_table
[16] = {
1848 0, 0, 0, 0, 1, 1, 1, 1,
1849 2, 2, 2, 0, 3, 3, 4, -1,
1851 static int astatic_table
[16] = {
1852 0, 1, 2, 3, 0, 1, 2, 3,
1853 0, 1, 2, 4, 0, 1, 0, -1,
1855 int aregs
= (save_inst
>> 16) & 0xf;
1856 int xsregs
= (save_inst
>> 24) & 0x7;
1857 int args
= args_table
[aregs
];
1858 int astatic
= astatic_table
[aregs
];
1863 warning (_("Invalid number of argument registers encoded in SAVE."));
1868 warning (_("Invalid number of static registers encoded in SAVE."));
1872 /* For standard SAVE the frame size of 0 means 128. */
1873 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1874 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1877 frame_offset
+= frame_size
;
1879 /* Now we can calculate what the SP must have been at the
1880 start of the function prologue. */
1883 /* Check if A0-A3 were saved in the caller's argument save area. */
1884 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1886 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1887 offset
+= mips_abi_regsize (gdbarch
);
1892 /* Check if the RA register was pushed on the stack. */
1893 if (save_inst
& 0x40)
1895 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1896 offset
-= mips_abi_regsize (gdbarch
);
1899 /* Check if the S8 register was pushed on the stack. */
1902 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1903 offset
-= mips_abi_regsize (gdbarch
);
1906 /* Check if S2-S7 were pushed on the stack. */
1907 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1909 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1910 offset
-= mips_abi_regsize (gdbarch
);
1913 /* Check if the S1 register was pushed on the stack. */
1914 if (save_inst
& 0x10)
1916 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1917 offset
-= mips_abi_regsize (gdbarch
);
1919 /* Check if the S0 register was pushed on the stack. */
1920 if (save_inst
& 0x20)
1922 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1923 offset
-= mips_abi_regsize (gdbarch
);
1926 /* Check if A0-A3 were pushed on the stack. */
1927 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1929 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1930 offset
-= mips_abi_regsize (gdbarch
);
1934 if (this_cache
!= NULL
)
1937 (get_frame_register_signed (this_frame
,
1938 gdbarch_num_regs (gdbarch
) + frame_reg
)
1939 + frame_offset
- frame_adjust
);
1940 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1941 be able to get rid of the assignment below, evetually. But it's
1942 still needed for now. */
1943 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1944 + mips_regnum (gdbarch
)->pc
]
1945 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1948 /* If we didn't reach the end of the prologue when scanning the function
1949 instructions, then set end_prologue_addr to the address of the
1950 instruction immediately after the last one we scanned. */
1951 if (end_prologue_addr
== 0)
1952 end_prologue_addr
= cur_pc
;
1954 return end_prologue_addr
;
1957 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1958 Procedures that use the 32-bit instruction set are handled by the
1959 mips_insn32 unwinder. */
1961 static struct mips_frame_cache
*
1962 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1964 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1965 struct mips_frame_cache
*cache
;
1967 if ((*this_cache
) != NULL
)
1968 return (*this_cache
);
1969 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1970 (*this_cache
) = cache
;
1971 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1973 /* Analyze the function prologue. */
1975 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1976 CORE_ADDR start_addr
;
1978 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1979 if (start_addr
== 0)
1980 start_addr
= heuristic_proc_start (gdbarch
, pc
);
1981 /* We can't analyze the prologue if we couldn't find the begining
1983 if (start_addr
== 0)
1986 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
1989 /* gdbarch_sp_regnum contains the value and not the address. */
1990 trad_frame_set_value (cache
->saved_regs
,
1991 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
1994 return (*this_cache
);
1998 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1999 struct frame_id
*this_id
)
2001 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2003 /* This marks the outermost frame. */
2004 if (info
->base
== 0)
2006 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2009 static struct value
*
2010 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2011 void **this_cache
, int regnum
)
2013 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2015 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2019 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2020 struct frame_info
*this_frame
, void **this_cache
)
2022 CORE_ADDR pc
= get_frame_pc (this_frame
);
2023 if (mips_pc_is_mips16 (pc
))
2028 static const struct frame_unwind mips_insn16_frame_unwind
=
2031 default_frame_unwind_stop_reason
,
2032 mips_insn16_frame_this_id
,
2033 mips_insn16_frame_prev_register
,
2035 mips_insn16_frame_sniffer
2039 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2042 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2047 static const struct frame_base mips_insn16_frame_base
=
2049 &mips_insn16_frame_unwind
,
2050 mips_insn16_frame_base_address
,
2051 mips_insn16_frame_base_address
,
2052 mips_insn16_frame_base_address
2055 static const struct frame_base
*
2056 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2058 CORE_ADDR pc
= get_frame_pc (this_frame
);
2059 if (mips_pc_is_mips16 (pc
))
2060 return &mips_insn16_frame_base
;
2065 /* Mark all the registers as unset in the saved_regs array
2066 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2069 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
2071 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2075 const int num_regs
= gdbarch_num_regs (gdbarch
);
2078 for (i
= 0; i
< num_regs
; i
++)
2080 this_cache
->saved_regs
[i
].addr
= -1;
2085 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2086 the associated FRAME_CACHE if not null.
2087 Return the address of the first instruction past the prologue. */
2090 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2091 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2092 struct frame_info
*this_frame
,
2093 struct mips_frame_cache
*this_cache
)
2096 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
2100 int frame_reg
= MIPS_SP_REGNUM
;
2102 CORE_ADDR end_prologue_addr
= 0;
2103 int seen_sp_adjust
= 0;
2104 int load_immediate_bytes
= 0;
2105 int in_delay_slot
= 0;
2106 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2108 /* Can be called when there's no process, and hence when there's no
2110 if (this_frame
!= NULL
)
2111 sp
= get_frame_register_signed (this_frame
,
2112 gdbarch_num_regs (gdbarch
)
2117 if (limit_pc
> start_pc
+ 200)
2118 limit_pc
= start_pc
+ 200;
2123 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2125 unsigned long inst
, high_word
, low_word
;
2128 /* Fetch the instruction. */
2129 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2131 /* Save some code by pre-extracting some useful fields. */
2132 high_word
= (inst
>> 16) & 0xffff;
2133 low_word
= inst
& 0xffff;
2134 reg
= high_word
& 0x1f;
2136 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2137 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2138 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2140 if (low_word
& 0x8000) /* Negative stack adjustment? */
2141 frame_offset
+= 0x10000 - low_word
;
2143 /* Exit loop if a positive stack adjustment is found, which
2144 usually means that the stack cleanup code in the function
2145 epilogue is reached. */
2149 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2150 && !regsize_is_64_bits
)
2152 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2154 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2155 && regsize_is_64_bits
)
2157 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2158 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2160 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2162 /* Old gcc frame, r30 is virtual frame pointer. */
2163 if ((long) low_word
!= frame_offset
)
2164 frame_addr
= sp
+ low_word
;
2165 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2167 unsigned alloca_adjust
;
2170 frame_addr
= get_frame_register_signed
2171 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2173 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2174 if (alloca_adjust
> 0)
2176 /* FP > SP + frame_size. This may be because of
2177 an alloca or somethings similar. Fix sp to
2178 "pre-alloca" value, and try again. */
2179 sp
+= alloca_adjust
;
2180 /* Need to reset the status of all registers. Otherwise,
2181 we will hit a guard that prevents the new address
2182 for each register to be recomputed during the second
2184 reset_saved_regs (gdbarch
, this_cache
);
2189 /* move $30,$sp. With different versions of gas this will be either
2190 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2191 Accept any one of these. */
2192 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2194 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2195 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2197 unsigned alloca_adjust
;
2200 frame_addr
= get_frame_register_signed
2201 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2203 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2204 if (alloca_adjust
> 0)
2206 /* FP > SP + frame_size. This may be because of
2207 an alloca or somethings similar. Fix sp to
2208 "pre-alloca" value, and try again. */
2210 /* Need to reset the status of all registers. Otherwise,
2211 we will hit a guard that prevents the new address
2212 for each register to be recomputed during the second
2214 reset_saved_regs (gdbarch
, this_cache
);
2219 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2220 && !regsize_is_64_bits
)
2222 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2224 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2225 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2226 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2227 || high_word
== 0x3c1c /* lui $gp,n */
2228 || high_word
== 0x279c /* addiu $gp,$gp,n */
2229 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2230 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2233 /* These instructions are part of the prologue, but we don't
2234 need to do anything special to handle them. */
2236 /* The instructions below load $at or $t0 with an immediate
2237 value in preparation for a stack adjustment via
2238 subu $sp,$sp,[$at,$t0]. These instructions could also
2239 initialize a local variable, so we accept them only before
2240 a stack adjustment instruction was seen. */
2241 else if (!seen_sp_adjust
2242 && (high_word
== 0x3c01 /* lui $at,n */
2243 || high_word
== 0x3c08 /* lui $t0,n */
2244 || high_word
== 0x3421 /* ori $at,$at,n */
2245 || high_word
== 0x3508 /* ori $t0,$t0,n */
2246 || high_word
== 0x3401 /* ori $at,$zero,n */
2247 || high_word
== 0x3408 /* ori $t0,$zero,n */
2250 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2254 /* This instruction is not an instruction typically found
2255 in a prologue, so we must have reached the end of the
2257 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2258 loop now? Why would we need to continue scanning the function
2260 if (end_prologue_addr
== 0)
2261 end_prologue_addr
= cur_pc
;
2263 /* Check for branches and jumps. For now, only jump to
2264 register are caught (i.e. returns). */
2265 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2269 /* If the previous instruction was a jump, we must have reached
2270 the end of the prologue by now. Stop scanning so that we do
2271 not go past the function return. */
2276 if (this_cache
!= NULL
)
2279 (get_frame_register_signed (this_frame
,
2280 gdbarch_num_regs (gdbarch
) + frame_reg
)
2282 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2283 this assignment below, eventually. But it's still needed
2285 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2286 + mips_regnum (gdbarch
)->pc
]
2287 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2291 /* If we didn't reach the end of the prologue when scanning the function
2292 instructions, then set end_prologue_addr to the address of the
2293 instruction immediately after the last one we scanned. */
2294 /* brobecker/2004-10-10: I don't think this would ever happen, but
2295 we may as well be careful and do our best if we have a null
2296 end_prologue_addr. */
2297 if (end_prologue_addr
== 0)
2298 end_prologue_addr
= cur_pc
;
2300 /* In a frameless function, we might have incorrectly
2301 skipped some load immediate instructions. Undo the skipping
2302 if the load immediate was not followed by a stack adjustment. */
2303 if (load_immediate_bytes
&& !seen_sp_adjust
)
2304 end_prologue_addr
-= load_immediate_bytes
;
2306 return end_prologue_addr
;
2309 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2310 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2311 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2314 static struct mips_frame_cache
*
2315 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2317 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2318 struct mips_frame_cache
*cache
;
2320 if ((*this_cache
) != NULL
)
2321 return (*this_cache
);
2323 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2324 (*this_cache
) = cache
;
2325 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2327 /* Analyze the function prologue. */
2329 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2330 CORE_ADDR start_addr
;
2332 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2333 if (start_addr
== 0)
2334 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2335 /* We can't analyze the prologue if we couldn't find the begining
2337 if (start_addr
== 0)
2340 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2343 /* gdbarch_sp_regnum contains the value and not the address. */
2344 trad_frame_set_value (cache
->saved_regs
,
2345 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2348 return (*this_cache
);
2352 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2353 struct frame_id
*this_id
)
2355 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2357 /* This marks the outermost frame. */
2358 if (info
->base
== 0)
2360 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2363 static struct value
*
2364 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2365 void **this_cache
, int regnum
)
2367 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2369 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2373 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2374 struct frame_info
*this_frame
, void **this_cache
)
2376 CORE_ADDR pc
= get_frame_pc (this_frame
);
2377 if (! mips_pc_is_mips16 (pc
))
2382 static const struct frame_unwind mips_insn32_frame_unwind
=
2385 default_frame_unwind_stop_reason
,
2386 mips_insn32_frame_this_id
,
2387 mips_insn32_frame_prev_register
,
2389 mips_insn32_frame_sniffer
2393 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2396 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2401 static const struct frame_base mips_insn32_frame_base
=
2403 &mips_insn32_frame_unwind
,
2404 mips_insn32_frame_base_address
,
2405 mips_insn32_frame_base_address
,
2406 mips_insn32_frame_base_address
2409 static const struct frame_base
*
2410 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2412 CORE_ADDR pc
= get_frame_pc (this_frame
);
2413 if (! mips_pc_is_mips16 (pc
))
2414 return &mips_insn32_frame_base
;
2419 static struct trad_frame_cache
*
2420 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2423 CORE_ADDR start_addr
;
2424 CORE_ADDR stack_addr
;
2425 struct trad_frame_cache
*this_trad_cache
;
2426 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2427 int num_regs
= gdbarch_num_regs (gdbarch
);
2429 if ((*this_cache
) != NULL
)
2430 return (*this_cache
);
2431 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2432 (*this_cache
) = this_trad_cache
;
2434 /* The return address is in the link register. */
2435 trad_frame_set_reg_realreg (this_trad_cache
,
2436 gdbarch_pc_regnum (gdbarch
),
2437 num_regs
+ MIPS_RA_REGNUM
);
2439 /* Frame ID, since it's a frameless / stackless function, no stack
2440 space is allocated and SP on entry is the current SP. */
2441 pc
= get_frame_pc (this_frame
);
2442 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2443 stack_addr
= get_frame_register_signed (this_frame
,
2444 num_regs
+ MIPS_SP_REGNUM
);
2445 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2447 /* Assume that the frame's base is the same as the
2449 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2451 return this_trad_cache
;
2455 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2456 struct frame_id
*this_id
)
2458 struct trad_frame_cache
*this_trad_cache
2459 = mips_stub_frame_cache (this_frame
, this_cache
);
2460 trad_frame_get_id (this_trad_cache
, this_id
);
2463 static struct value
*
2464 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2465 void **this_cache
, int regnum
)
2467 struct trad_frame_cache
*this_trad_cache
2468 = mips_stub_frame_cache (this_frame
, this_cache
);
2469 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2473 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2474 struct frame_info
*this_frame
, void **this_cache
)
2477 struct obj_section
*s
;
2478 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2479 struct minimal_symbol
*msym
;
2481 /* Use the stub unwinder for unreadable code. */
2482 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2485 if (in_plt_section (pc
, NULL
))
2488 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2489 s
= find_pc_section (pc
);
2492 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2493 ".MIPS.stubs") == 0)
2496 /* Calling a PIC function from a non-PIC function passes through a
2497 stub. The stub for foo is named ".pic.foo". */
2498 msym
= lookup_minimal_symbol_by_pc (pc
);
2500 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2501 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2507 static const struct frame_unwind mips_stub_frame_unwind
=
2510 default_frame_unwind_stop_reason
,
2511 mips_stub_frame_this_id
,
2512 mips_stub_frame_prev_register
,
2514 mips_stub_frame_sniffer
2518 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2521 struct trad_frame_cache
*this_trad_cache
2522 = mips_stub_frame_cache (this_frame
, this_cache
);
2523 return trad_frame_get_this_base (this_trad_cache
);
2526 static const struct frame_base mips_stub_frame_base
=
2528 &mips_stub_frame_unwind
,
2529 mips_stub_frame_base_address
,
2530 mips_stub_frame_base_address
,
2531 mips_stub_frame_base_address
2534 static const struct frame_base
*
2535 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2537 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2538 return &mips_stub_frame_base
;
2543 /* mips_addr_bits_remove - remove useless address bits */
2546 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2548 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2550 if (is_mips16_addr (addr
))
2551 addr
= unmake_mips16_addr (addr
);
2553 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2554 /* This hack is a work-around for existing boards using PMON, the
2555 simulator, and any other 64-bit targets that doesn't have true
2556 64-bit addressing. On these targets, the upper 32 bits of
2557 addresses are ignored by the hardware. Thus, the PC or SP are
2558 likely to have been sign extended to all 1s by instruction
2559 sequences that load 32-bit addresses. For example, a typical
2560 piece of code that loads an address is this:
2562 lui $r2, <upper 16 bits>
2563 ori $r2, <lower 16 bits>
2565 But the lui sign-extends the value such that the upper 32 bits
2566 may be all 1s. The workaround is simply to mask off these
2567 bits. In the future, gcc may be changed to support true 64-bit
2568 addressing, and this masking will have to be disabled. */
2569 return addr
&= 0xffffffffUL
;
2574 /* Instructions used during single-stepping of atomic sequences. */
2575 #define LL_OPCODE 0x30
2576 #define LLD_OPCODE 0x34
2577 #define SC_OPCODE 0x38
2578 #define SCD_OPCODE 0x3c
2580 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2581 instruction and ending with a SC/SCD instruction. If such a sequence
2582 is found, attempt to step through it. A breakpoint is placed at the end of
2586 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2587 struct address_space
*aspace
, CORE_ADDR pc
)
2589 CORE_ADDR breaks
[2] = {-1, -1};
2591 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2595 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2596 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2601 insn
= mips_fetch_instruction (gdbarch
, loc
);
2602 /* Assume all atomic sequences start with a ll/lld instruction. */
2603 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2606 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2608 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2611 loc
+= MIPS_INSN32_SIZE
;
2612 insn
= mips_fetch_instruction (gdbarch
, loc
);
2614 /* Assume that there is at most one branch in the atomic
2615 sequence. If a branch is found, put a breakpoint in its
2616 destination address. */
2617 switch (itype_op (insn
))
2619 case 0: /* SPECIAL */
2620 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2621 return 0; /* fallback to the standard single-step code. */
2623 case 1: /* REGIMM */
2624 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2628 return 0; /* fallback to the standard single-step code. */
2635 case 22: /* BLEZL */
2636 case 23: /* BGTTL */
2642 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2647 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2648 if (last_breakpoint
>= 1)
2649 return 0; /* More than one branch found, fallback to the
2650 standard single-step code. */
2651 breaks
[1] = branch_bp
;
2655 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2659 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2660 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2663 loc
+= MIPS_INSN32_SIZE
;
2665 /* Insert a breakpoint right after the end of the atomic sequence. */
2668 /* Check for duplicated breakpoints. Check also for a breakpoint
2669 placed (branch instruction's destination) in the atomic sequence. */
2670 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2671 last_breakpoint
= 0;
2673 /* Effectively inserts the breakpoints. */
2674 for (index
= 0; index
<= last_breakpoint
; index
++)
2675 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2680 /* mips_software_single_step() is called just before we want to resume
2681 the inferior, if we want to single-step it but there is no hardware
2682 or kernel single-step support (MIPS on GNU/Linux for example). We find
2683 the target of the coming instruction and breakpoint it. */
2686 mips_software_single_step (struct frame_info
*frame
)
2688 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2689 struct address_space
*aspace
= get_frame_address_space (frame
);
2690 CORE_ADDR pc
, next_pc
;
2692 pc
= get_frame_pc (frame
);
2693 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2696 next_pc
= mips_next_pc (frame
, pc
);
2698 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2702 /* Test whether the PC points to the return instruction at the
2703 end of a function. */
2706 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2708 if (mips_pc_is_mips16 (pc
))
2709 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2710 generates a "jr $ra"; other times it generates code to load
2711 the return address from the stack to an accessible register (such
2712 as $a3), then a "jr" using that register. This second case
2713 is almost impossible to distinguish from an indirect jump
2714 used for switch statements, so we don't even try. */
2715 return mips_fetch_instruction (gdbarch
, pc
) == 0xe820; /* jr $ra */
2717 return mips_fetch_instruction (gdbarch
, pc
) == 0x3e00008; /* jr $ra */
2721 /* This fencepost looks highly suspicious to me. Removing it also
2722 seems suspicious as it could affect remote debugging across serial
2726 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2732 struct inferior
*inf
;
2734 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2736 fence
= start_pc
- heuristic_fence_post
;
2740 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2741 fence
= VM_MIN_ADDRESS
;
2743 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2745 inf
= current_inferior ();
2747 /* Search back for previous return. */
2748 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2749 if (start_pc
< fence
)
2751 /* It's not clear to me why we reach this point when
2752 stop_soon, but with this test, at least we
2753 don't print out warnings for every child forked (eg, on
2754 decstation). 22apr93 rich@cygnus.com. */
2755 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2757 static int blurb_printed
= 0;
2759 warning (_("GDB can't find the start of the function at %s."),
2760 paddress (gdbarch
, pc
));
2764 /* This actually happens frequently in embedded
2765 development, when you first connect to a board
2766 and your stack pointer and pc are nowhere in
2767 particular. This message needs to give people
2768 in that situation enough information to
2769 determine that it's no big deal. */
2770 printf_filtered ("\n\
2771 GDB is unable to find the start of the function at %s\n\
2772 and thus can't determine the size of that function's stack frame.\n\
2773 This means that GDB may be unable to access that stack frame, or\n\
2774 the frames below it.\n\
2775 This problem is most likely caused by an invalid program counter or\n\
2777 However, if you think GDB should simply search farther back\n\
2778 from %s for code which looks like the beginning of a\n\
2779 function, you can increase the range of the search using the `set\n\
2780 heuristic-fence-post' command.\n",
2781 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2788 else if (mips_pc_is_mips16 (start_pc
))
2790 unsigned short inst
;
2792 /* On MIPS16, any one of the following is likely to be the
2793 start of a function:
2799 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
2800 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2801 if ((inst
& 0xff80) == 0x6480) /* save */
2803 if (start_pc
- instlen
>= fence
)
2805 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2806 if ((inst
& 0xf800) == 0xf000) /* extend */
2807 start_pc
-= instlen
;
2811 else if (((inst
& 0xf81f) == 0xe809
2812 && (inst
& 0x700) != 0x700) /* entry */
2813 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2814 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2815 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2817 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2818 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2823 else if (mips_about_to_return (gdbarch
, start_pc
))
2825 /* Skip return and its delay slot. */
2826 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2833 struct mips_objfile_private
2839 /* According to the current ABI, should the type be passed in a
2840 floating-point register (assuming that there is space)? When there
2841 is no FPU, FP are not even considered as possible candidates for
2842 FP registers and, consequently this returns false - forces FP
2843 arguments into integer registers. */
2846 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2847 struct type
*arg_type
)
2849 return ((typecode
== TYPE_CODE_FLT
2850 || (MIPS_EABI (gdbarch
)
2851 && (typecode
== TYPE_CODE_STRUCT
2852 || typecode
== TYPE_CODE_UNION
)
2853 && TYPE_NFIELDS (arg_type
) == 1
2854 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2856 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2859 /* On o32, argument passing in GPRs depends on the alignment of the type being
2860 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2863 mips_type_needs_double_align (struct type
*type
)
2865 enum type_code typecode
= TYPE_CODE (type
);
2867 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2869 else if (typecode
== TYPE_CODE_STRUCT
)
2871 if (TYPE_NFIELDS (type
) < 1)
2873 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2875 else if (typecode
== TYPE_CODE_UNION
)
2879 n
= TYPE_NFIELDS (type
);
2880 for (i
= 0; i
< n
; i
++)
2881 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2888 /* Adjust the address downward (direction of stack growth) so that it
2889 is correctly aligned for a new stack frame. */
2891 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2893 return align_down (addr
, 16);
2897 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2898 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2899 int nargs
, struct value
**args
, CORE_ADDR sp
,
2900 int struct_return
, CORE_ADDR struct_addr
)
2906 int stack_offset
= 0;
2907 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2908 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2909 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2910 int regsize
= mips_abi_regsize (gdbarch
);
2912 /* For shared libraries, "t9" needs to point at the function
2914 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2916 /* Set the return address register to point to the entry point of
2917 the program, where a breakpoint lies in wait. */
2918 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2920 /* First ensure that the stack and structure return address (if any)
2921 are properly aligned. The stack has to be at least 64-bit
2922 aligned even on 32-bit machines, because doubles must be 64-bit
2923 aligned. For n32 and n64, stack frames need to be 128-bit
2924 aligned, so we round to this widest known alignment. */
2926 sp
= align_down (sp
, 16);
2927 struct_addr
= align_down (struct_addr
, 16);
2929 /* Now make space on the stack for the args. We allocate more
2930 than necessary for EABI, because the first few arguments are
2931 passed in registers, but that's OK. */
2932 for (argnum
= 0; argnum
< nargs
; argnum
++)
2933 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2934 sp
-= align_up (len
, 16);
2937 fprintf_unfiltered (gdb_stdlog
,
2938 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2939 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2941 /* Initialize the integer and float register pointers. */
2942 argreg
= MIPS_A0_REGNUM
;
2943 float_argreg
= mips_fpa0_regnum (gdbarch
);
2945 /* The struct_return pointer occupies the first parameter-passing reg. */
2949 fprintf_unfiltered (gdb_stdlog
,
2950 "mips_eabi_push_dummy_call: "
2951 "struct_return reg=%d %s\n",
2952 argreg
, paddress (gdbarch
, struct_addr
));
2953 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2956 /* Now load as many as possible of the first arguments into
2957 registers, and push the rest onto the stack. Loop thru args
2958 from first to last. */
2959 for (argnum
= 0; argnum
< nargs
; argnum
++)
2961 const gdb_byte
*val
;
2962 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2963 struct value
*arg
= args
[argnum
];
2964 struct type
*arg_type
= check_typedef (value_type (arg
));
2965 int len
= TYPE_LENGTH (arg_type
);
2966 enum type_code typecode
= TYPE_CODE (arg_type
);
2969 fprintf_unfiltered (gdb_stdlog
,
2970 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2971 argnum
+ 1, len
, (int) typecode
);
2973 /* Function pointer arguments to mips16 code need to be made into
2975 if (typecode
== TYPE_CODE_PTR
2976 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
2978 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
2980 if (mips_pc_is_mips16 (addr
))
2982 store_signed_integer (valbuf
, len
, byte_order
,
2983 make_mips16_addr (addr
));
2987 val
= value_contents (arg
);
2989 /* The EABI passes structures that do not fit in a register by
2991 else if (len
> regsize
2992 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2994 store_unsigned_integer (valbuf
, regsize
, byte_order
,
2995 value_address (arg
));
2996 typecode
= TYPE_CODE_PTR
;
3000 fprintf_unfiltered (gdb_stdlog
, " push");
3003 val
= value_contents (arg
);
3005 /* 32-bit ABIs always start floating point arguments in an
3006 even-numbered floating point register. Round the FP register
3007 up before the check to see if there are any FP registers
3008 left. Non MIPS_EABI targets also pass the FP in the integer
3009 registers so also round up normal registers. */
3010 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3012 if ((float_argreg
& 1))
3016 /* Floating point arguments passed in registers have to be
3017 treated specially. On 32-bit architectures, doubles
3018 are passed in register pairs; the even register gets
3019 the low word, and the odd register gets the high word.
3020 On non-EABI processors, the first two floating point arguments are
3021 also copied to general registers, because MIPS16 functions
3022 don't use float registers for arguments. This duplication of
3023 arguments in general registers can't hurt non-MIPS16 functions
3024 because those registers are normally skipped. */
3025 /* MIPS_EABI squeezes a struct that contains a single floating
3026 point value into an FP register instead of pushing it onto the
3028 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3029 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3031 /* EABI32 will pass doubles in consecutive registers, even on
3032 64-bit cores. At one time, we used to check the size of
3033 `float_argreg' to determine whether or not to pass doubles
3034 in consecutive registers, but this is not sufficient for
3035 making the ABI determination. */
3036 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
3038 int low_offset
= gdbarch_byte_order (gdbarch
)
3039 == BFD_ENDIAN_BIG
? 4 : 0;
3042 /* Write the low word of the double to the even register(s). */
3043 regval
= extract_signed_integer (val
+ low_offset
,
3046 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3047 float_argreg
, phex (regval
, 4));
3048 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3050 /* Write the high word of the double to the odd register(s). */
3051 regval
= extract_signed_integer (val
+ 4 - low_offset
,
3054 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3055 float_argreg
, phex (regval
, 4));
3056 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3060 /* This is a floating point value that fits entirely
3061 in a single register. */
3062 /* On 32 bit ABI's the float_argreg is further adjusted
3063 above to ensure that it is even register aligned. */
3064 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
3066 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3067 float_argreg
, phex (regval
, len
));
3068 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3073 /* Copy the argument to general registers or the stack in
3074 register-sized pieces. Large arguments are split between
3075 registers and stack. */
3076 /* Note: structs whose size is not a multiple of regsize
3077 are treated specially: Irix cc passes
3078 them in registers where gcc sometimes puts them on the
3079 stack. For maximum compatibility, we will put them in
3081 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3083 /* Note: Floating-point values that didn't fit into an FP
3084 register are only written to memory. */
3087 /* Remember if the argument was written to the stack. */
3088 int stack_used_p
= 0;
3089 int partial_len
= (len
< regsize
? len
: regsize
);
3092 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3095 /* Write this portion of the argument to the stack. */
3096 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3098 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3100 /* Should shorter than int integer values be
3101 promoted to int before being stored? */
3102 int longword_offset
= 0;
3105 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3108 && (typecode
== TYPE_CODE_INT
3109 || typecode
== TYPE_CODE_PTR
3110 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3111 longword_offset
= regsize
- len
;
3112 else if ((typecode
== TYPE_CODE_STRUCT
3113 || typecode
== TYPE_CODE_UNION
)
3114 && TYPE_LENGTH (arg_type
) < regsize
)
3115 longword_offset
= regsize
- len
;
3120 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3121 paddress (gdbarch
, stack_offset
));
3122 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3123 paddress (gdbarch
, longword_offset
));
3126 addr
= sp
+ stack_offset
+ longword_offset
;
3131 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3132 paddress (gdbarch
, addr
));
3133 for (i
= 0; i
< partial_len
; i
++)
3135 fprintf_unfiltered (gdb_stdlog
, "%02x",
3139 write_memory (addr
, val
, partial_len
);
3142 /* Note!!! This is NOT an else clause. Odd sized
3143 structs may go thru BOTH paths. Floating point
3144 arguments will not. */
3145 /* Write this portion of the argument to a general
3146 purpose register. */
3147 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3148 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3151 extract_signed_integer (val
, partial_len
, byte_order
);
3154 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3156 phex (regval
, regsize
));
3157 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3164 /* Compute the offset into the stack at which we will
3165 copy the next parameter.
3167 In the new EABI (and the NABI32), the stack_offset
3168 only needs to be adjusted when it has been used. */
3171 stack_offset
+= align_up (partial_len
, regsize
);
3175 fprintf_unfiltered (gdb_stdlog
, "\n");
3178 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3180 /* Return adjusted stack pointer. */
3184 /* Determine the return value convention being used. */
3186 static enum return_value_convention
3187 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3188 struct type
*type
, struct regcache
*regcache
,
3189 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3191 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3192 int fp_return_type
= 0;
3193 int offset
, regnum
, xfer
;
3195 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3196 return RETURN_VALUE_STRUCT_CONVENTION
;
3198 /* Floating point type? */
3199 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3201 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3203 /* Structs with a single field of float type
3204 are returned in a floating point register. */
3205 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3206 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3207 && TYPE_NFIELDS (type
) == 1)
3209 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3211 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3218 /* A floating-point value belongs in the least significant part
3221 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3222 regnum
= mips_regnum (gdbarch
)->fp0
;
3226 /* An integer value goes in V0/V1. */
3228 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3229 regnum
= MIPS_V0_REGNUM
;
3232 offset
< TYPE_LENGTH (type
);
3233 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3235 xfer
= mips_abi_regsize (gdbarch
);
3236 if (offset
+ xfer
> TYPE_LENGTH (type
))
3237 xfer
= TYPE_LENGTH (type
) - offset
;
3238 mips_xfer_register (gdbarch
, regcache
,
3239 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3240 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3244 return RETURN_VALUE_REGISTER_CONVENTION
;
3248 /* N32/N64 ABI stuff. */
3250 /* Search for a naturally aligned double at OFFSET inside a struct
3251 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3255 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3260 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3263 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3266 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3269 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3272 struct type
*field_type
;
3274 /* We're only looking at normal fields. */
3275 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3276 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3279 /* If we have gone past the offset, there is no double to pass. */
3280 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3284 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3286 /* If this field is entirely before the requested offset, go
3287 on to the next one. */
3288 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3291 /* If this is our special aligned double, we can stop. */
3292 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3293 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3296 /* This field starts at or before the requested offset, and
3297 overlaps it. If it is a structure, recurse inwards. */
3298 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3305 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3306 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3307 int nargs
, struct value
**args
, CORE_ADDR sp
,
3308 int struct_return
, CORE_ADDR struct_addr
)
3314 int stack_offset
= 0;
3315 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3316 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3317 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3319 /* For shared libraries, "t9" needs to point at the function
3321 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3323 /* Set the return address register to point to the entry point of
3324 the program, where a breakpoint lies in wait. */
3325 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3327 /* First ensure that the stack and structure return address (if any)
3328 are properly aligned. The stack has to be at least 64-bit
3329 aligned even on 32-bit machines, because doubles must be 64-bit
3330 aligned. For n32 and n64, stack frames need to be 128-bit
3331 aligned, so we round to this widest known alignment. */
3333 sp
= align_down (sp
, 16);
3334 struct_addr
= align_down (struct_addr
, 16);
3336 /* Now make space on the stack for the args. */
3337 for (argnum
= 0; argnum
< nargs
; argnum
++)
3338 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3339 sp
-= align_up (len
, 16);
3342 fprintf_unfiltered (gdb_stdlog
,
3343 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3344 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3346 /* Initialize the integer and float register pointers. */
3347 argreg
= MIPS_A0_REGNUM
;
3348 float_argreg
= mips_fpa0_regnum (gdbarch
);
3350 /* The struct_return pointer occupies the first parameter-passing reg. */
3354 fprintf_unfiltered (gdb_stdlog
,
3355 "mips_n32n64_push_dummy_call: "
3356 "struct_return reg=%d %s\n",
3357 argreg
, paddress (gdbarch
, struct_addr
));
3358 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3361 /* Now load as many as possible of the first arguments into
3362 registers, and push the rest onto the stack. Loop thru args
3363 from first to last. */
3364 for (argnum
= 0; argnum
< nargs
; argnum
++)
3366 const gdb_byte
*val
;
3367 struct value
*arg
= args
[argnum
];
3368 struct type
*arg_type
= check_typedef (value_type (arg
));
3369 int len
= TYPE_LENGTH (arg_type
);
3370 enum type_code typecode
= TYPE_CODE (arg_type
);
3373 fprintf_unfiltered (gdb_stdlog
,
3374 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3375 argnum
+ 1, len
, (int) typecode
);
3377 val
= value_contents (arg
);
3379 /* A 128-bit long double value requires an even-odd pair of
3380 floating-point registers. */
3382 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3383 && (float_argreg
& 1))
3389 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3390 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3392 /* This is a floating point value that fits entirely
3393 in a single register or a pair of registers. */
3394 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3395 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3397 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3398 float_argreg
, phex (regval
, reglen
));
3399 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3402 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3403 argreg
, phex (regval
, reglen
));
3404 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3409 regval
= extract_unsigned_integer (val
+ reglen
,
3410 reglen
, byte_order
);
3412 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3413 float_argreg
, phex (regval
, reglen
));
3414 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3417 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3418 argreg
, phex (regval
, reglen
));
3419 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3426 /* Copy the argument to general registers or the stack in
3427 register-sized pieces. Large arguments are split between
3428 registers and stack. */
3429 /* For N32/N64, structs, unions, or other composite types are
3430 treated as a sequence of doublewords, and are passed in integer
3431 or floating point registers as though they were simple scalar
3432 parameters to the extent that they fit, with any excess on the
3433 stack packed according to the normal memory layout of the
3435 The caller does not reserve space for the register arguments;
3436 the callee is responsible for reserving it if required. */
3437 /* Note: Floating-point values that didn't fit into an FP
3438 register are only written to memory. */
3441 /* Remember if the argument was written to the stack. */
3442 int stack_used_p
= 0;
3443 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3446 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3449 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3450 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3452 /* Write this portion of the argument to the stack. */
3453 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3455 /* Should shorter than int integer values be
3456 promoted to int before being stored? */
3457 int longword_offset
= 0;
3460 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3462 if ((typecode
== TYPE_CODE_INT
3463 || typecode
== TYPE_CODE_PTR
)
3465 longword_offset
= MIPS64_REGSIZE
- len
;
3470 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3471 paddress (gdbarch
, stack_offset
));
3472 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3473 paddress (gdbarch
, longword_offset
));
3476 addr
= sp
+ stack_offset
+ longword_offset
;
3481 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3482 paddress (gdbarch
, addr
));
3483 for (i
= 0; i
< partial_len
; i
++)
3485 fprintf_unfiltered (gdb_stdlog
, "%02x",
3489 write_memory (addr
, val
, partial_len
);
3492 /* Note!!! This is NOT an else clause. Odd sized
3493 structs may go thru BOTH paths. */
3494 /* Write this portion of the argument to a general
3495 purpose register. */
3496 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3500 /* Sign extend pointers, 32-bit integers and signed
3501 16-bit and 8-bit integers; everything else is taken
3504 if ((partial_len
== 4
3505 && (typecode
== TYPE_CODE_PTR
3506 || typecode
== TYPE_CODE_INT
))
3508 && typecode
== TYPE_CODE_INT
3509 && !TYPE_UNSIGNED (arg_type
)))
3510 regval
= extract_signed_integer (val
, partial_len
,
3513 regval
= extract_unsigned_integer (val
, partial_len
,
3516 /* A non-floating-point argument being passed in a
3517 general register. If a struct or union, and if
3518 the remaining length is smaller than the register
3519 size, we have to adjust the register value on
3522 It does not seem to be necessary to do the
3523 same for integral types. */
3525 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3526 && partial_len
< MIPS64_REGSIZE
3527 && (typecode
== TYPE_CODE_STRUCT
3528 || typecode
== TYPE_CODE_UNION
))
3529 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3533 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3535 phex (regval
, MIPS64_REGSIZE
));
3536 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3538 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3539 TYPE_LENGTH (arg_type
) - len
))
3542 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3544 phex (regval
, MIPS64_REGSIZE
));
3545 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3556 /* Compute the offset into the stack at which we will
3557 copy the next parameter.
3559 In N32 (N64?), the stack_offset only needs to be
3560 adjusted when it has been used. */
3563 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3567 fprintf_unfiltered (gdb_stdlog
, "\n");
3570 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3572 /* Return adjusted stack pointer. */
3576 static enum return_value_convention
3577 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3578 struct type
*type
, struct regcache
*regcache
,
3579 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3581 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3583 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3585 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3586 if needed), as appropriate for the type. Composite results (struct,
3587 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3590 * A struct with only one or two floating point fields is returned in $f0
3591 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3594 * Any other composite results of at most 128 bits are returned in
3595 $2 (first 64 bits) and $3 (remainder, if necessary).
3597 * Larger composite results are handled by converting the function to a
3598 procedure with an implicit first parameter, which is a pointer to an area
3599 reserved by the caller to receive the result. [The o32-bit ABI requires
3600 that all composite results be handled by conversion to implicit first
3601 parameters. The MIPS/SGI Fortran implementation has always made a
3602 specific exception to return COMPLEX results in the floating point
3605 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3606 return RETURN_VALUE_STRUCT_CONVENTION
;
3607 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3608 && TYPE_LENGTH (type
) == 16
3609 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3611 /* A 128-bit floating-point value fills both $f0 and $f2. The
3612 two registers are used in the same as memory order, so the
3613 eight bytes with the lower memory address are in $f0. */
3615 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3616 mips_xfer_register (gdbarch
, regcache
,
3617 gdbarch_num_regs (gdbarch
)
3618 + mips_regnum (gdbarch
)->fp0
,
3619 8, gdbarch_byte_order (gdbarch
),
3620 readbuf
, writebuf
, 0);
3621 mips_xfer_register (gdbarch
, regcache
,
3622 gdbarch_num_regs (gdbarch
)
3623 + mips_regnum (gdbarch
)->fp0
+ 2,
3624 8, gdbarch_byte_order (gdbarch
),
3625 readbuf
? readbuf
+ 8 : readbuf
,
3626 writebuf
? writebuf
+ 8 : writebuf
, 0);
3627 return RETURN_VALUE_REGISTER_CONVENTION
;
3629 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3630 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3632 /* A single or double floating-point value that fits in FP0. */
3634 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3635 mips_xfer_register (gdbarch
, regcache
,
3636 gdbarch_num_regs (gdbarch
)
3637 + mips_regnum (gdbarch
)->fp0
,
3639 gdbarch_byte_order (gdbarch
),
3640 readbuf
, writebuf
, 0);
3641 return RETURN_VALUE_REGISTER_CONVENTION
;
3643 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3644 && TYPE_NFIELDS (type
) <= 2
3645 && TYPE_NFIELDS (type
) >= 1
3646 && ((TYPE_NFIELDS (type
) == 1
3647 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3649 || (TYPE_NFIELDS (type
) == 2
3650 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3652 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3653 == TYPE_CODE_FLT
))))
3655 /* A struct that contains one or two floats. Each value is part
3656 in the least significant part of their floating point
3657 register (or GPR, for soft float). */
3660 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3661 ? mips_regnum (gdbarch
)->fp0
3663 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3665 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3668 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3670 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3672 /* A 16-byte long double field goes in two consecutive
3674 mips_xfer_register (gdbarch
, regcache
,
3675 gdbarch_num_regs (gdbarch
) + regnum
,
3677 gdbarch_byte_order (gdbarch
),
3678 readbuf
, writebuf
, offset
);
3679 mips_xfer_register (gdbarch
, regcache
,
3680 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3682 gdbarch_byte_order (gdbarch
),
3683 readbuf
, writebuf
, offset
+ 8);
3686 mips_xfer_register (gdbarch
, regcache
,
3687 gdbarch_num_regs (gdbarch
) + regnum
,
3688 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3689 gdbarch_byte_order (gdbarch
),
3690 readbuf
, writebuf
, offset
);
3692 return RETURN_VALUE_REGISTER_CONVENTION
;
3694 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3695 || TYPE_CODE (type
) == TYPE_CODE_UNION
3696 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3698 /* A composite type. Extract the left justified value,
3699 regardless of the byte order. I.e. DO NOT USE
3703 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3704 offset
< TYPE_LENGTH (type
);
3705 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3707 int xfer
= register_size (gdbarch
, regnum
);
3708 if (offset
+ xfer
> TYPE_LENGTH (type
))
3709 xfer
= TYPE_LENGTH (type
) - offset
;
3711 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3712 offset
, xfer
, regnum
);
3713 mips_xfer_register (gdbarch
, regcache
,
3714 gdbarch_num_regs (gdbarch
) + regnum
,
3715 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3718 return RETURN_VALUE_REGISTER_CONVENTION
;
3722 /* A scalar extract each part but least-significant-byte
3726 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3727 offset
< TYPE_LENGTH (type
);
3728 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3730 int xfer
= register_size (gdbarch
, regnum
);
3731 if (offset
+ xfer
> TYPE_LENGTH (type
))
3732 xfer
= TYPE_LENGTH (type
) - offset
;
3734 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3735 offset
, xfer
, regnum
);
3736 mips_xfer_register (gdbarch
, regcache
,
3737 gdbarch_num_regs (gdbarch
) + regnum
,
3738 xfer
, gdbarch_byte_order (gdbarch
),
3739 readbuf
, writebuf
, offset
);
3741 return RETURN_VALUE_REGISTER_CONVENTION
;
3745 /* O32 ABI stuff. */
3748 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3749 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3750 int nargs
, struct value
**args
, CORE_ADDR sp
,
3751 int struct_return
, CORE_ADDR struct_addr
)
3757 int stack_offset
= 0;
3758 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3759 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3760 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3762 /* For shared libraries, "t9" needs to point at the function
3764 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3766 /* Set the return address register to point to the entry point of
3767 the program, where a breakpoint lies in wait. */
3768 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3770 /* First ensure that the stack and structure return address (if any)
3771 are properly aligned. The stack has to be at least 64-bit
3772 aligned even on 32-bit machines, because doubles must be 64-bit
3773 aligned. For n32 and n64, stack frames need to be 128-bit
3774 aligned, so we round to this widest known alignment. */
3776 sp
= align_down (sp
, 16);
3777 struct_addr
= align_down (struct_addr
, 16);
3779 /* Now make space on the stack for the args. */
3780 for (argnum
= 0; argnum
< nargs
; argnum
++)
3782 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3783 int arglen
= TYPE_LENGTH (arg_type
);
3785 /* Align to double-word if necessary. */
3786 if (mips_type_needs_double_align (arg_type
))
3787 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3788 /* Allocate space on the stack. */
3789 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3791 sp
-= align_up (len
, 16);
3794 fprintf_unfiltered (gdb_stdlog
,
3795 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3796 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3798 /* Initialize the integer and float register pointers. */
3799 argreg
= MIPS_A0_REGNUM
;
3800 float_argreg
= mips_fpa0_regnum (gdbarch
);
3802 /* The struct_return pointer occupies the first parameter-passing reg. */
3806 fprintf_unfiltered (gdb_stdlog
,
3807 "mips_o32_push_dummy_call: "
3808 "struct_return reg=%d %s\n",
3809 argreg
, paddress (gdbarch
, struct_addr
));
3810 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3811 stack_offset
+= MIPS32_REGSIZE
;
3814 /* Now load as many as possible of the first arguments into
3815 registers, and push the rest onto the stack. Loop thru args
3816 from first to last. */
3817 for (argnum
= 0; argnum
< nargs
; argnum
++)
3819 const gdb_byte
*val
;
3820 struct value
*arg
= args
[argnum
];
3821 struct type
*arg_type
= check_typedef (value_type (arg
));
3822 int len
= TYPE_LENGTH (arg_type
);
3823 enum type_code typecode
= TYPE_CODE (arg_type
);
3826 fprintf_unfiltered (gdb_stdlog
,
3827 "mips_o32_push_dummy_call: %d len=%d type=%d",
3828 argnum
+ 1, len
, (int) typecode
);
3830 val
= value_contents (arg
);
3832 /* 32-bit ABIs always start floating point arguments in an
3833 even-numbered floating point register. Round the FP register
3834 up before the check to see if there are any FP registers
3835 left. O32/O64 targets also pass the FP in the integer
3836 registers so also round up normal registers. */
3837 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3839 if ((float_argreg
& 1))
3843 /* Floating point arguments passed in registers have to be
3844 treated specially. On 32-bit architectures, doubles
3845 are passed in register pairs; the even register gets
3846 the low word, and the odd register gets the high word.
3847 On O32/O64, the first two floating point arguments are
3848 also copied to general registers, because MIPS16 functions
3849 don't use float registers for arguments. This duplication of
3850 arguments in general registers can't hurt non-MIPS16 functions
3851 because those registers are normally skipped. */
3853 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3854 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3856 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3858 int low_offset
= gdbarch_byte_order (gdbarch
)
3859 == BFD_ENDIAN_BIG
? 4 : 0;
3860 unsigned long regval
;
3862 /* Write the low word of the double to the even register(s). */
3863 regval
= extract_unsigned_integer (val
+ low_offset
,
3866 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3867 float_argreg
, phex (regval
, 4));
3868 regcache_cooked_write_unsigned (regcache
,
3869 float_argreg
++, regval
);
3871 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3872 argreg
, phex (regval
, 4));
3873 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3875 /* Write the high word of the double to the odd register(s). */
3876 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3879 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3880 float_argreg
, phex (regval
, 4));
3881 regcache_cooked_write_unsigned (regcache
,
3882 float_argreg
++, regval
);
3885 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3886 argreg
, phex (regval
, 4));
3887 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3891 /* This is a floating point value that fits entirely
3892 in a single register. */
3893 /* On 32 bit ABI's the float_argreg is further adjusted
3894 above to ensure that it is even register aligned. */
3895 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
3897 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3898 float_argreg
, phex (regval
, len
));
3899 regcache_cooked_write_unsigned (regcache
,
3900 float_argreg
++, regval
);
3901 /* Although two FP registers are reserved for each
3902 argument, only one corresponding integer register is
3905 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3906 argreg
, phex (regval
, len
));
3907 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3909 /* Reserve space for the FP register. */
3910 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3914 /* Copy the argument to general registers or the stack in
3915 register-sized pieces. Large arguments are split between
3916 registers and stack. */
3917 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3918 are treated specially: Irix cc passes
3919 them in registers where gcc sometimes puts them on the
3920 stack. For maximum compatibility, we will put them in
3922 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3923 && len
% MIPS32_REGSIZE
!= 0);
3924 /* Structures should be aligned to eight bytes (even arg registers)
3925 on MIPS_ABI_O32, if their first member has double precision. */
3926 if (mips_type_needs_double_align (arg_type
))
3931 stack_offset
+= MIPS32_REGSIZE
;
3936 /* Remember if the argument was written to the stack. */
3937 int stack_used_p
= 0;
3938 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3941 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3944 /* Write this portion of the argument to the stack. */
3945 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3946 || odd_sized_struct
)
3948 /* Should shorter than int integer values be
3949 promoted to int before being stored? */
3950 int longword_offset
= 0;
3956 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3957 paddress (gdbarch
, stack_offset
));
3958 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3959 paddress (gdbarch
, longword_offset
));
3962 addr
= sp
+ stack_offset
+ longword_offset
;
3967 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3968 paddress (gdbarch
, addr
));
3969 for (i
= 0; i
< partial_len
; i
++)
3971 fprintf_unfiltered (gdb_stdlog
, "%02x",
3975 write_memory (addr
, val
, partial_len
);
3978 /* Note!!! This is NOT an else clause. Odd sized
3979 structs may go thru BOTH paths. */
3980 /* Write this portion of the argument to a general
3981 purpose register. */
3982 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3984 LONGEST regval
= extract_signed_integer (val
, partial_len
,
3986 /* Value may need to be sign extended, because
3987 mips_isa_regsize() != mips_abi_regsize(). */
3989 /* A non-floating-point argument being passed in a
3990 general register. If a struct or union, and if
3991 the remaining length is smaller than the register
3992 size, we have to adjust the register value on
3995 It does not seem to be necessary to do the
3996 same for integral types.
3998 Also don't do this adjustment on O64 binaries.
4000 cagney/2001-07-23: gdb/179: Also, GCC, when
4001 outputting LE O32 with sizeof (struct) <
4002 mips_abi_regsize(), generates a left shift
4003 as part of storing the argument in a register
4004 (the left shift isn't generated when
4005 sizeof (struct) >= mips_abi_regsize()). Since
4006 it is quite possible that this is GCC
4007 contradicting the LE/O32 ABI, GDB has not been
4008 adjusted to accommodate this. Either someone
4009 needs to demonstrate that the LE/O32 ABI
4010 specifies such a left shift OR this new ABI gets
4011 identified as such and GDB gets tweaked
4014 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4015 && partial_len
< MIPS32_REGSIZE
4016 && (typecode
== TYPE_CODE_STRUCT
4017 || typecode
== TYPE_CODE_UNION
))
4018 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
4022 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4024 phex (regval
, MIPS32_REGSIZE
));
4025 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4028 /* Prevent subsequent floating point arguments from
4029 being passed in floating point registers. */
4030 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4036 /* Compute the offset into the stack at which we will
4037 copy the next parameter.
4039 In older ABIs, the caller reserved space for
4040 registers that contained arguments. This was loosely
4041 refered to as their "home". Consequently, space is
4042 always allocated. */
4044 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
4048 fprintf_unfiltered (gdb_stdlog
, "\n");
4051 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4053 /* Return adjusted stack pointer. */
4057 static enum return_value_convention
4058 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4059 struct type
*type
, struct regcache
*regcache
,
4060 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4062 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4064 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4065 || TYPE_CODE (type
) == TYPE_CODE_UNION
4066 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4067 return RETURN_VALUE_STRUCT_CONVENTION
;
4068 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4069 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4071 /* A single-precision floating-point value. It fits in the
4072 least significant part of FP0. */
4074 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4075 mips_xfer_register (gdbarch
, regcache
,
4076 gdbarch_num_regs (gdbarch
)
4077 + mips_regnum (gdbarch
)->fp0
,
4079 gdbarch_byte_order (gdbarch
),
4080 readbuf
, writebuf
, 0);
4081 return RETURN_VALUE_REGISTER_CONVENTION
;
4083 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4084 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4086 /* A double-precision floating-point value. The most
4087 significant part goes in FP1, and the least significant in
4090 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4091 switch (gdbarch_byte_order (gdbarch
))
4093 case BFD_ENDIAN_LITTLE
:
4094 mips_xfer_register (gdbarch
, regcache
,
4095 gdbarch_num_regs (gdbarch
)
4096 + mips_regnum (gdbarch
)->fp0
+
4097 0, 4, gdbarch_byte_order (gdbarch
),
4098 readbuf
, writebuf
, 0);
4099 mips_xfer_register (gdbarch
, regcache
,
4100 gdbarch_num_regs (gdbarch
)
4101 + mips_regnum (gdbarch
)->fp0
+ 1,
4102 4, gdbarch_byte_order (gdbarch
),
4103 readbuf
, writebuf
, 4);
4105 case BFD_ENDIAN_BIG
:
4106 mips_xfer_register (gdbarch
, regcache
,
4107 gdbarch_num_regs (gdbarch
)
4108 + mips_regnum (gdbarch
)->fp0
+ 1,
4109 4, gdbarch_byte_order (gdbarch
),
4110 readbuf
, writebuf
, 0);
4111 mips_xfer_register (gdbarch
, regcache
,
4112 gdbarch_num_regs (gdbarch
)
4113 + mips_regnum (gdbarch
)->fp0
+ 0,
4114 4, gdbarch_byte_order (gdbarch
),
4115 readbuf
, writebuf
, 4);
4118 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4120 return RETURN_VALUE_REGISTER_CONVENTION
;
4123 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4124 && TYPE_NFIELDS (type
) <= 2
4125 && TYPE_NFIELDS (type
) >= 1
4126 && ((TYPE_NFIELDS (type
) == 1
4127 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4129 || (TYPE_NFIELDS (type
) == 2
4130 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4132 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4134 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4136 /* A struct that contains one or two floats. Each value is part
4137 in the least significant part of their floating point
4139 gdb_byte reg
[MAX_REGISTER_SIZE
];
4142 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4143 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4145 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4148 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4150 mips_xfer_register (gdbarch
, regcache
,
4151 gdbarch_num_regs (gdbarch
) + regnum
,
4152 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4153 gdbarch_byte_order (gdbarch
),
4154 readbuf
, writebuf
, offset
);
4156 return RETURN_VALUE_REGISTER_CONVENTION
;
4160 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4161 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4163 /* A structure or union. Extract the left justified value,
4164 regardless of the byte order. I.e. DO NOT USE
4168 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4169 offset
< TYPE_LENGTH (type
);
4170 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4172 int xfer
= register_size (gdbarch
, regnum
);
4173 if (offset
+ xfer
> TYPE_LENGTH (type
))
4174 xfer
= TYPE_LENGTH (type
) - offset
;
4176 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4177 offset
, xfer
, regnum
);
4178 mips_xfer_register (gdbarch
, regcache
,
4179 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4180 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4182 return RETURN_VALUE_REGISTER_CONVENTION
;
4187 /* A scalar extract each part but least-significant-byte
4188 justified. o32 thinks registers are 4 byte, regardless of
4192 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4193 offset
< TYPE_LENGTH (type
);
4194 offset
+= MIPS32_REGSIZE
, regnum
++)
4196 int xfer
= MIPS32_REGSIZE
;
4197 if (offset
+ xfer
> TYPE_LENGTH (type
))
4198 xfer
= TYPE_LENGTH (type
) - offset
;
4200 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4201 offset
, xfer
, regnum
);
4202 mips_xfer_register (gdbarch
, regcache
,
4203 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4204 gdbarch_byte_order (gdbarch
),
4205 readbuf
, writebuf
, offset
);
4207 return RETURN_VALUE_REGISTER_CONVENTION
;
4211 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4215 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4216 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4218 struct value
**args
, CORE_ADDR sp
,
4219 int struct_return
, CORE_ADDR struct_addr
)
4225 int stack_offset
= 0;
4226 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4227 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4228 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4230 /* For shared libraries, "t9" needs to point at the function
4232 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4234 /* Set the return address register to point to the entry point of
4235 the program, where a breakpoint lies in wait. */
4236 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4238 /* First ensure that the stack and structure return address (if any)
4239 are properly aligned. The stack has to be at least 64-bit
4240 aligned even on 32-bit machines, because doubles must be 64-bit
4241 aligned. For n32 and n64, stack frames need to be 128-bit
4242 aligned, so we round to this widest known alignment. */
4244 sp
= align_down (sp
, 16);
4245 struct_addr
= align_down (struct_addr
, 16);
4247 /* Now make space on the stack for the args. */
4248 for (argnum
= 0; argnum
< nargs
; argnum
++)
4250 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4251 int arglen
= TYPE_LENGTH (arg_type
);
4253 /* Allocate space on the stack. */
4254 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4256 sp
-= align_up (len
, 16);
4259 fprintf_unfiltered (gdb_stdlog
,
4260 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4261 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4263 /* Initialize the integer and float register pointers. */
4264 argreg
= MIPS_A0_REGNUM
;
4265 float_argreg
= mips_fpa0_regnum (gdbarch
);
4267 /* The struct_return pointer occupies the first parameter-passing reg. */
4271 fprintf_unfiltered (gdb_stdlog
,
4272 "mips_o64_push_dummy_call: "
4273 "struct_return reg=%d %s\n",
4274 argreg
, paddress (gdbarch
, struct_addr
));
4275 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4276 stack_offset
+= MIPS64_REGSIZE
;
4279 /* Now load as many as possible of the first arguments into
4280 registers, and push the rest onto the stack. Loop thru args
4281 from first to last. */
4282 for (argnum
= 0; argnum
< nargs
; argnum
++)
4284 const gdb_byte
*val
;
4285 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4286 struct value
*arg
= args
[argnum
];
4287 struct type
*arg_type
= check_typedef (value_type (arg
));
4288 int len
= TYPE_LENGTH (arg_type
);
4289 enum type_code typecode
= TYPE_CODE (arg_type
);
4292 fprintf_unfiltered (gdb_stdlog
,
4293 "mips_o64_push_dummy_call: %d len=%d type=%d",
4294 argnum
+ 1, len
, (int) typecode
);
4296 val
= value_contents (arg
);
4298 /* Function pointer arguments to mips16 code need to be made into
4300 if (typecode
== TYPE_CODE_PTR
4301 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4303 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4305 if (mips_pc_is_mips16 (addr
))
4307 store_signed_integer (valbuf
, len
, byte_order
,
4308 make_mips16_addr (addr
));
4313 /* Floating point arguments passed in registers have to be
4314 treated specially. On 32-bit architectures, doubles
4315 are passed in register pairs; the even register gets
4316 the low word, and the odd register gets the high word.
4317 On O32/O64, the first two floating point arguments are
4318 also copied to general registers, because MIPS16 functions
4319 don't use float registers for arguments. This duplication of
4320 arguments in general registers can't hurt non-MIPS16 functions
4321 because those registers are normally skipped. */
4323 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4324 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4326 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4328 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4329 float_argreg
, phex (regval
, len
));
4330 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4332 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4333 argreg
, phex (regval
, len
));
4334 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4336 /* Reserve space for the FP register. */
4337 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4341 /* Copy the argument to general registers or the stack in
4342 register-sized pieces. Large arguments are split between
4343 registers and stack. */
4344 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4345 are treated specially: Irix cc passes them in registers
4346 where gcc sometimes puts them on the stack. For maximum
4347 compatibility, we will put them in both places. */
4348 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4349 && len
% MIPS64_REGSIZE
!= 0);
4352 /* Remember if the argument was written to the stack. */
4353 int stack_used_p
= 0;
4354 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4357 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4360 /* Write this portion of the argument to the stack. */
4361 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4362 || odd_sized_struct
)
4364 /* Should shorter than int integer values be
4365 promoted to int before being stored? */
4366 int longword_offset
= 0;
4369 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4371 if ((typecode
== TYPE_CODE_INT
4372 || typecode
== TYPE_CODE_PTR
4373 || typecode
== TYPE_CODE_FLT
)
4375 longword_offset
= MIPS64_REGSIZE
- len
;
4380 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4381 paddress (gdbarch
, stack_offset
));
4382 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4383 paddress (gdbarch
, longword_offset
));
4386 addr
= sp
+ stack_offset
+ longword_offset
;
4391 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4392 paddress (gdbarch
, addr
));
4393 for (i
= 0; i
< partial_len
; i
++)
4395 fprintf_unfiltered (gdb_stdlog
, "%02x",
4399 write_memory (addr
, val
, partial_len
);
4402 /* Note!!! This is NOT an else clause. Odd sized
4403 structs may go thru BOTH paths. */
4404 /* Write this portion of the argument to a general
4405 purpose register. */
4406 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4408 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4410 /* Value may need to be sign extended, because
4411 mips_isa_regsize() != mips_abi_regsize(). */
4413 /* A non-floating-point argument being passed in a
4414 general register. If a struct or union, and if
4415 the remaining length is smaller than the register
4416 size, we have to adjust the register value on
4419 It does not seem to be necessary to do the
4420 same for integral types. */
4422 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4423 && partial_len
< MIPS64_REGSIZE
4424 && (typecode
== TYPE_CODE_STRUCT
4425 || typecode
== TYPE_CODE_UNION
))
4426 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4430 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4432 phex (regval
, MIPS64_REGSIZE
));
4433 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4436 /* Prevent subsequent floating point arguments from
4437 being passed in floating point registers. */
4438 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4444 /* Compute the offset into the stack at which we will
4445 copy the next parameter.
4447 In older ABIs, the caller reserved space for
4448 registers that contained arguments. This was loosely
4449 refered to as their "home". Consequently, space is
4450 always allocated. */
4452 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4456 fprintf_unfiltered (gdb_stdlog
, "\n");
4459 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4461 /* Return adjusted stack pointer. */
4465 static enum return_value_convention
4466 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4467 struct type
*type
, struct regcache
*regcache
,
4468 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4470 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4472 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4473 || TYPE_CODE (type
) == TYPE_CODE_UNION
4474 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4475 return RETURN_VALUE_STRUCT_CONVENTION
;
4476 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4478 /* A floating-point value. It fits in the least significant
4481 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4482 mips_xfer_register (gdbarch
, regcache
,
4483 gdbarch_num_regs (gdbarch
)
4484 + mips_regnum (gdbarch
)->fp0
,
4486 gdbarch_byte_order (gdbarch
),
4487 readbuf
, writebuf
, 0);
4488 return RETURN_VALUE_REGISTER_CONVENTION
;
4492 /* A scalar extract each part but least-significant-byte
4496 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4497 offset
< TYPE_LENGTH (type
);
4498 offset
+= MIPS64_REGSIZE
, regnum
++)
4500 int xfer
= MIPS64_REGSIZE
;
4501 if (offset
+ xfer
> TYPE_LENGTH (type
))
4502 xfer
= TYPE_LENGTH (type
) - offset
;
4504 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4505 offset
, xfer
, regnum
);
4506 mips_xfer_register (gdbarch
, regcache
,
4507 gdbarch_num_regs (gdbarch
) + regnum
,
4508 xfer
, gdbarch_byte_order (gdbarch
),
4509 readbuf
, writebuf
, offset
);
4511 return RETURN_VALUE_REGISTER_CONVENTION
;
4515 /* Floating point register management.
4517 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4518 64bit operations, these early MIPS cpus treat fp register pairs
4519 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4520 registers and offer a compatibility mode that emulates the MIPS2 fp
4521 model. When operating in MIPS2 fp compat mode, later cpu's split
4522 double precision floats into two 32-bit chunks and store them in
4523 consecutive fp regs. To display 64-bit floats stored in this
4524 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4525 Throw in user-configurable endianness and you have a real mess.
4527 The way this works is:
4528 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4529 double-precision value will be split across two logical registers.
4530 The lower-numbered logical register will hold the low-order bits,
4531 regardless of the processor's endianness.
4532 - If we are on a 64-bit processor, and we are looking for a
4533 single-precision value, it will be in the low ordered bits
4534 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4535 save slot in memory.
4536 - If we are in 64-bit mode, everything is straightforward.
4538 Note that this code only deals with "live" registers at the top of the
4539 stack. We will attempt to deal with saved registers later, when
4540 the raw/cooked register interface is in place. (We need a general
4541 interface that can deal with dynamic saved register sizes -- fp
4542 regs could be 32 bits wide in one frame and 64 on the frame above
4545 /* Copy a 32-bit single-precision value from the current frame
4546 into rare_buffer. */
4549 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4550 gdb_byte
*rare_buffer
)
4552 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4553 int raw_size
= register_size (gdbarch
, regno
);
4554 gdb_byte
*raw_buffer
= alloca (raw_size
);
4556 if (!frame_register_read (frame
, regno
, raw_buffer
))
4557 error (_("can't read register %d (%s)"),
4558 regno
, gdbarch_register_name (gdbarch
, regno
));
4561 /* We have a 64-bit value for this register. Find the low-order
4565 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4570 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4574 memcpy (rare_buffer
, raw_buffer
, 4);
4578 /* Copy a 64-bit double-precision value from the current frame into
4579 rare_buffer. This may include getting half of it from the next
4583 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4584 gdb_byte
*rare_buffer
)
4586 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4587 int raw_size
= register_size (gdbarch
, regno
);
4589 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4591 /* We have a 64-bit value for this register, and we should use
4593 if (!frame_register_read (frame
, regno
, rare_buffer
))
4594 error (_("can't read register %d (%s)"),
4595 regno
, gdbarch_register_name (gdbarch
, regno
));
4599 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4601 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4602 internal_error (__FILE__
, __LINE__
,
4603 _("mips_read_fp_register_double: bad access to "
4604 "odd-numbered FP register"));
4606 /* mips_read_fp_register_single will find the correct 32 bits from
4608 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4610 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4611 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4615 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4616 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4622 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4624 { /* Do values for FP (float) regs. */
4625 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4626 gdb_byte
*raw_buffer
;
4627 double doub
, flt1
; /* Doubles extracted from raw hex data. */
4630 raw_buffer
= alloca (2 * register_size (gdbarch
,
4631 mips_regnum (gdbarch
)->fp0
));
4633 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4634 fprintf_filtered (file
, "%*s",
4635 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4638 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4640 struct value_print_options opts
;
4642 /* 4-byte registers: Print hex and floating. Also print even
4643 numbered registers as doubles. */
4644 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4645 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4648 get_formatted_print_options (&opts
, 'x');
4649 print_scalar_formatted (raw_buffer
,
4650 builtin_type (gdbarch
)->builtin_uint32
,
4653 fprintf_filtered (file
, " flt: ");
4655 fprintf_filtered (file
, " <invalid float> ");
4657 fprintf_filtered (file
, "%-17.9g", flt1
);
4659 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4661 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4662 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4665 fprintf_filtered (file
, " dbl: ");
4667 fprintf_filtered (file
, "<invalid double>");
4669 fprintf_filtered (file
, "%-24.17g", doub
);
4674 struct value_print_options opts
;
4676 /* Eight byte registers: print each one as hex, float and double. */
4677 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4678 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4681 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4682 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4685 get_formatted_print_options (&opts
, 'x');
4686 print_scalar_formatted (raw_buffer
,
4687 builtin_type (gdbarch
)->builtin_uint64
,
4690 fprintf_filtered (file
, " flt: ");
4692 fprintf_filtered (file
, "<invalid float>");
4694 fprintf_filtered (file
, "%-17.9g", flt1
);
4696 fprintf_filtered (file
, " dbl: ");
4698 fprintf_filtered (file
, "<invalid double>");
4700 fprintf_filtered (file
, "%-24.17g", doub
);
4705 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4708 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4710 struct value_print_options opts
;
4713 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4715 mips_print_fp_register (file
, frame
, regnum
);
4719 val
= get_frame_register_value (frame
, regnum
);
4720 if (value_optimized_out (val
))
4722 fprintf_filtered (file
, "%s: [Invalid]",
4723 gdbarch_register_name (gdbarch
, regnum
));
4727 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4729 /* The problem with printing numeric register names (r26, etc.) is that
4730 the user can't use them on input. Probably the best solution is to
4731 fix it so that either the numeric or the funky (a2, etc.) names
4732 are accepted on input. */
4733 if (regnum
< MIPS_NUMREGS
)
4734 fprintf_filtered (file
, "(r%d): ", regnum
);
4736 fprintf_filtered (file
, ": ");
4738 get_formatted_print_options (&opts
, 'x');
4739 val_print_scalar_formatted (value_type (val
),
4740 value_contents_for_printing (val
),
4741 value_embedded_offset (val
),
4746 /* Replacement for generic do_registers_info.
4747 Print regs in pretty columns. */
4750 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4753 fprintf_filtered (file
, " ");
4754 mips_print_fp_register (file
, frame
, regnum
);
4755 fprintf_filtered (file
, "\n");
4760 /* Print a row's worth of GP (int) registers, with name labels above. */
4763 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4766 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4767 /* Do values for GP (int) regs. */
4768 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4769 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
4774 /* For GP registers, we print a separate row of names above the vals. */
4775 for (col
= 0, regnum
= start_regnum
;
4776 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4777 + gdbarch_num_pseudo_regs (gdbarch
);
4780 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4781 continue; /* unused register */
4782 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4784 break; /* End the row: reached FP register. */
4785 /* Large registers are handled separately. */
4786 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4789 break; /* End the row before this register. */
4791 /* Print this register on a row by itself. */
4792 mips_print_register (file
, frame
, regnum
);
4793 fprintf_filtered (file
, "\n");
4797 fprintf_filtered (file
, " ");
4798 fprintf_filtered (file
,
4799 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4800 gdbarch_register_name (gdbarch
, regnum
));
4807 /* Print the R0 to R31 names. */
4808 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4809 fprintf_filtered (file
, "\n R%-4d",
4810 start_regnum
% gdbarch_num_regs (gdbarch
));
4812 fprintf_filtered (file
, "\n ");
4814 /* Now print the values in hex, 4 or 8 to the row. */
4815 for (col
= 0, regnum
= start_regnum
;
4816 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4817 + gdbarch_num_pseudo_regs (gdbarch
);
4820 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4821 continue; /* unused register */
4822 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4824 break; /* End row: reached FP register. */
4825 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4826 break; /* End row: large register. */
4828 /* OK: get the data in raw format. */
4829 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4830 error (_("can't read register %d (%s)"),
4831 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4832 /* pad small registers */
4834 byte
< (mips_abi_regsize (gdbarch
)
4835 - register_size (gdbarch
, regnum
)); byte
++)
4836 printf_filtered (" ");
4837 /* Now print the register value in hex, endian order. */
4838 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4840 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4841 byte
< register_size (gdbarch
, regnum
); byte
++)
4842 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4844 for (byte
= register_size (gdbarch
, regnum
) - 1;
4846 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4847 fprintf_filtered (file
, " ");
4850 if (col
> 0) /* ie. if we actually printed anything... */
4851 fprintf_filtered (file
, "\n");
4856 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
4859 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4860 struct frame_info
*frame
, int regnum
, int all
)
4862 if (regnum
!= -1) /* Do one specified register. */
4864 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4865 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4866 error (_("Not a valid register for the current processor type"));
4868 mips_print_register (file
, frame
, regnum
);
4869 fprintf_filtered (file
, "\n");
4872 /* Do all (or most) registers. */
4874 regnum
= gdbarch_num_regs (gdbarch
);
4875 while (regnum
< gdbarch_num_regs (gdbarch
)
4876 + gdbarch_num_pseudo_regs (gdbarch
))
4878 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4881 if (all
) /* True for "INFO ALL-REGISTERS" command. */
4882 regnum
= print_fp_register_row (file
, frame
, regnum
);
4884 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
4887 regnum
= print_gp_register_row (file
, frame
, regnum
);
4892 /* Is this a branch with a delay slot? */
4895 is_delayed (unsigned long insn
)
4898 for (i
= 0; i
< NUMOPCODES
; ++i
)
4899 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4900 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4902 return (i
< NUMOPCODES
4903 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4904 | INSN_COND_BRANCH_DELAY
4905 | INSN_COND_BRANCH_LIKELY
)));
4909 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4910 struct frame_info
*frame
)
4912 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4913 CORE_ADDR pc
= get_frame_pc (frame
);
4914 gdb_byte buf
[MIPS_INSN32_SIZE
];
4916 /* There is no branch delay slot on MIPS16. */
4917 if (mips_pc_is_mips16 (pc
))
4920 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
4923 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4924 /* If error reading memory, guess that it is not a delayed
4927 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
4930 /* To skip prologues, I use this predicate. Returns either PC itself
4931 if the code at PC does not look like a function prologue; otherwise
4932 returns an address that (if we're lucky) follows the prologue. If
4933 LENIENT, then we must skip everything which is involved in setting
4934 up the frame (it's OK to skip more, just so long as we don't skip
4935 anything which might clobber the registers which are being saved.
4936 We must skip more in the case where part of the prologue is in the
4937 delay slot of a non-prologue instruction). */
4940 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4943 CORE_ADDR func_addr
;
4945 /* See if we can determine the end of the prologue via the symbol table.
4946 If so, then return either PC, or the PC after the prologue, whichever
4948 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4950 CORE_ADDR post_prologue_pc
4951 = skip_prologue_using_sal (gdbarch
, func_addr
);
4952 if (post_prologue_pc
!= 0)
4953 return max (pc
, post_prologue_pc
);
4956 /* Can't determine prologue from the symbol table, need to examine
4959 /* Find an upper limit on the function prologue using the debug
4960 information. If the debug information could not be used to provide
4961 that bound, then use an arbitrary large number as the upper bound. */
4962 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
4964 limit_pc
= pc
+ 100; /* Magic. */
4966 if (mips_pc_is_mips16 (pc
))
4967 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4969 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4972 /* Check whether the PC is in a function epilogue (32-bit version).
4973 This is a helper function for mips_in_function_epilogue_p. */
4975 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4977 CORE_ADDR func_addr
= 0, func_end
= 0;
4979 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4981 /* The MIPS epilogue is max. 12 bytes long. */
4982 CORE_ADDR addr
= func_end
- 12;
4984 if (addr
< func_addr
+ 4)
4985 addr
= func_addr
+ 4;
4989 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4991 unsigned long high_word
;
4994 inst
= mips_fetch_instruction (gdbarch
, pc
);
4995 high_word
= (inst
>> 16) & 0xffff;
4997 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4998 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4999 && inst
!= 0x03e00008 /* jr $ra */
5000 && inst
!= 0x00000000) /* nop */
5010 /* Check whether the PC is in a function epilogue (16-bit version).
5011 This is a helper function for mips_in_function_epilogue_p. */
5013 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5015 CORE_ADDR func_addr
= 0, func_end
= 0;
5017 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5019 /* The MIPS epilogue is max. 12 bytes long. */
5020 CORE_ADDR addr
= func_end
- 12;
5022 if (addr
< func_addr
+ 4)
5023 addr
= func_addr
+ 4;
5027 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
5029 unsigned short inst
;
5031 inst
= mips_fetch_instruction (gdbarch
, pc
);
5033 if ((inst
& 0xf800) == 0xf000) /* extend */
5036 if (inst
!= 0x6300 /* addiu $sp,offset */
5037 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
5038 && inst
!= 0xe820 /* jr $ra */
5039 && inst
!= 0xe8a0 /* jrc $ra */
5040 && inst
!= 0x6500) /* nop */
5050 /* The epilogue is defined here as the area at the end of a function,
5051 after an instruction which destroys the function's stack frame. */
5053 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5055 if (mips_pc_is_mips16 (pc
))
5056 return mips16_in_function_epilogue_p (gdbarch
, pc
);
5058 return mips32_in_function_epilogue_p (gdbarch
, pc
);
5061 /* Root of all "set mips "/"show mips " commands. This will eventually be
5062 used for all MIPS-specific commands. */
5065 show_mips_command (char *args
, int from_tty
)
5067 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5071 set_mips_command (char *args
, int from_tty
)
5074 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5075 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5078 /* Commands to show/set the MIPS FPU type. */
5081 show_mipsfpu_command (char *args
, int from_tty
)
5085 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5088 ("The MIPS floating-point coprocessor is unknown "
5089 "because the current architecture is not MIPS.\n");
5093 switch (MIPS_FPU_TYPE (target_gdbarch
))
5095 case MIPS_FPU_SINGLE
:
5096 fpu
= "single-precision";
5098 case MIPS_FPU_DOUBLE
:
5099 fpu
= "double-precision";
5102 fpu
= "absent (none)";
5105 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5107 if (mips_fpu_type_auto
)
5108 printf_unfiltered ("The MIPS floating-point coprocessor "
5109 "is set automatically (currently %s)\n",
5113 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5118 set_mipsfpu_command (char *args
, int from_tty
)
5120 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
5121 "\"single\",\"none\" or \"auto\".\n");
5122 show_mipsfpu_command (args
, from_tty
);
5126 set_mipsfpu_single_command (char *args
, int from_tty
)
5128 struct gdbarch_info info
;
5129 gdbarch_info_init (&info
);
5130 mips_fpu_type
= MIPS_FPU_SINGLE
;
5131 mips_fpu_type_auto
= 0;
5132 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5133 instead of relying on globals. Doing that would let generic code
5134 handle the search for this specific architecture. */
5135 if (!gdbarch_update_p (info
))
5136 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5140 set_mipsfpu_double_command (char *args
, int from_tty
)
5142 struct gdbarch_info info
;
5143 gdbarch_info_init (&info
);
5144 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5145 mips_fpu_type_auto
= 0;
5146 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5147 instead of relying on globals. Doing that would let generic code
5148 handle the search for this specific architecture. */
5149 if (!gdbarch_update_p (info
))
5150 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5154 set_mipsfpu_none_command (char *args
, int from_tty
)
5156 struct gdbarch_info info
;
5157 gdbarch_info_init (&info
);
5158 mips_fpu_type
= MIPS_FPU_NONE
;
5159 mips_fpu_type_auto
= 0;
5160 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5161 instead of relying on globals. Doing that would let generic code
5162 handle the search for this specific architecture. */
5163 if (!gdbarch_update_p (info
))
5164 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5168 set_mipsfpu_auto_command (char *args
, int from_tty
)
5170 mips_fpu_type_auto
= 1;
5173 /* Attempt to identify the particular processor model by reading the
5174 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5175 the relevant processor still exists (it dates back to '94) and
5176 secondly this is not the way to do this. The processor type should
5177 be set by forcing an architecture change. */
5180 deprecated_mips_set_processor_regs_hack (void)
5182 struct regcache
*regcache
= get_current_regcache ();
5183 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5184 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5187 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5188 if ((prid
& ~0xf) == 0x700)
5189 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5192 /* Just like reinit_frame_cache, but with the right arguments to be
5193 callable as an sfunc. */
5196 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5197 struct cmd_list_element
*c
)
5199 reinit_frame_cache ();
5203 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5205 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5206 disassembler needs to be able to locally determine the ISA, and
5207 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5209 if (mips_pc_is_mips16 (memaddr
))
5210 info
->mach
= bfd_mach_mips16
;
5212 /* Round down the instruction address to the appropriate boundary. */
5213 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5215 /* Set the disassembler options. */
5216 if (!info
->disassembler_options
)
5217 /* This string is not recognized explicitly by the disassembler,
5218 but it tells the disassembler to not try to guess the ABI from
5219 the bfd elf headers, such that, if the user overrides the ABI
5220 of a program linked as NewABI, the disassembly will follow the
5221 register naming conventions specified by the user. */
5222 info
->disassembler_options
= "gpr-names=32";
5224 /* Call the appropriate disassembler based on the target endian-ness. */
5225 if (info
->endian
== BFD_ENDIAN_BIG
)
5226 return print_insn_big_mips (memaddr
, info
);
5228 return print_insn_little_mips (memaddr
, info
);
5232 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5234 /* Set up the disassembler info, so that we get the right
5235 register names from libopcodes. */
5236 info
->disassembler_options
= "gpr-names=n32";
5237 info
->flavour
= bfd_target_elf_flavour
;
5239 return gdb_print_insn_mips (memaddr
, info
);
5243 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5245 /* Set up the disassembler info, so that we get the right
5246 register names from libopcodes. */
5247 info
->disassembler_options
= "gpr-names=64";
5248 info
->flavour
= bfd_target_elf_flavour
;
5250 return gdb_print_insn_mips (memaddr
, info
);
5253 /* This function implements gdbarch_breakpoint_from_pc. It uses the
5254 program counter value to determine whether a 16- or 32-bit breakpoint
5255 should be used. It returns a pointer to a string of bytes that encode a
5256 breakpoint instruction, stores the length of the string to *lenptr, and
5257 adjusts pc (if necessary) to point to the actual memory location where
5258 the breakpoint should be inserted. */
5260 static const gdb_byte
*
5261 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
5262 CORE_ADDR
*pcptr
, int *lenptr
)
5264 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5266 if (mips_pc_is_mips16 (*pcptr
))
5268 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5269 *pcptr
= unmake_mips16_addr (*pcptr
);
5270 *lenptr
= sizeof (mips16_big_breakpoint
);
5271 return mips16_big_breakpoint
;
5275 /* The IDT board uses an unusual breakpoint value, and
5276 sometimes gets confused when it sees the usual MIPS
5277 breakpoint instruction. */
5278 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5279 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5280 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5281 /* Likewise, IRIX appears to expect a different breakpoint,
5282 although this is not apparent until you try to use pthreads. */
5283 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5285 *lenptr
= sizeof (big_breakpoint
);
5287 if (strcmp (target_shortname
, "mips") == 0)
5288 return idt_big_breakpoint
;
5289 else if (strcmp (target_shortname
, "ddb") == 0
5290 || strcmp (target_shortname
, "pmon") == 0
5291 || strcmp (target_shortname
, "lsi") == 0)
5292 return pmon_big_breakpoint
;
5293 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5294 return irix_big_breakpoint
;
5296 return big_breakpoint
;
5301 if (mips_pc_is_mips16 (*pcptr
))
5303 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5304 *pcptr
= unmake_mips16_addr (*pcptr
);
5305 *lenptr
= sizeof (mips16_little_breakpoint
);
5306 return mips16_little_breakpoint
;
5310 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5311 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5312 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5314 *lenptr
= sizeof (little_breakpoint
);
5316 if (strcmp (target_shortname
, "mips") == 0)
5317 return idt_little_breakpoint
;
5318 else if (strcmp (target_shortname
, "ddb") == 0
5319 || strcmp (target_shortname
, "pmon") == 0
5320 || strcmp (target_shortname
, "lsi") == 0)
5321 return pmon_little_breakpoint
;
5323 return little_breakpoint
;
5328 /* If PC is in a mips16 call or return stub, return the address of the target
5329 PC, which is either the callee or the caller. There are several
5330 cases which must be handled:
5332 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5333 target PC is in $31 ($ra).
5334 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5335 and the target PC is in $2.
5336 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5337 before the jal instruction, this is effectively a call stub
5338 and the target PC is in $2. Otherwise this is effectively
5339 a return stub and the target PC is in $18.
5341 See the source code for the stubs in gcc/config/mips/mips16.S for
5345 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5347 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5349 CORE_ADDR start_addr
;
5351 /* Find the starting address and name of the function containing the PC. */
5352 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5355 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5356 target PC is in $31 ($ra). */
5357 if (strcmp (name
, "__mips16_ret_sf") == 0
5358 || strcmp (name
, "__mips16_ret_df") == 0)
5359 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5361 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5363 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5364 and the target PC is in $2. */
5365 if (name
[19] >= '0' && name
[19] <= '9')
5366 return get_frame_register_signed (frame
, 2);
5368 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5369 before the jal instruction, this is effectively a call stub
5370 and the target PC is in $2. Otherwise this is effectively
5371 a return stub and the target PC is in $18. */
5372 else if (name
[19] == 's' || name
[19] == 'd')
5374 if (pc
== start_addr
)
5376 /* Check if the target of the stub is a compiler-generated
5377 stub. Such a stub for a function bar might have a name
5378 like __fn_stub_bar, and might look like this:
5383 la $1,bar (becomes a lui/addiu pair)
5385 So scan down to the lui/addi and extract the target
5386 address from those two instructions. */
5388 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5392 /* See if the name of the target function is __fn_stub_*. */
5393 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5396 if (strncmp (name
, "__fn_stub_", 10) != 0
5397 && strcmp (name
, "etext") != 0
5398 && strcmp (name
, "_etext") != 0)
5401 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5402 The limit on the search is arbitrarily set to 20
5403 instructions. FIXME. */
5404 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5406 inst
= mips_fetch_instruction (gdbarch
, target_pc
);
5407 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5408 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5409 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5410 return pc
| (inst
& 0xffff); /* low word */
5413 /* Couldn't find the lui/addui pair, so return stub address. */
5417 /* This is the 'return' part of a call stub. The return
5418 address is in $r18. */
5419 return get_frame_register_signed (frame
, 18);
5422 return 0; /* not a stub */
5425 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5426 PC of the stub target. The stub just loads $t9 and jumps to it,
5427 so that $t9 has the correct value at function entry. */
5430 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5432 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5433 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5434 struct minimal_symbol
*msym
;
5436 gdb_byte stub_code
[16];
5437 int32_t stub_words
[4];
5439 /* The stub for foo is named ".pic.foo", and is either two
5440 instructions inserted before foo or a three instruction sequence
5441 which jumps to foo. */
5442 msym
= lookup_minimal_symbol_by_pc (pc
);
5444 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5445 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5446 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5449 /* A two-instruction header. */
5450 if (MSYMBOL_SIZE (msym
) == 8)
5453 /* A three-instruction (plus delay slot) trampoline. */
5454 if (MSYMBOL_SIZE (msym
) == 16)
5456 if (target_read_memory (pc
, stub_code
, 16) != 0)
5458 for (i
= 0; i
< 4; i
++)
5459 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
5462 /* A stub contains these instructions:
5465 addiu t9, t9, %lo(target)
5468 This works even for N64, since stubs are only generated with
5470 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5471 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5472 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5473 && stub_words
[3] == 0x00000000)
5474 return (((stub_words
[0] & 0x0000ffff) << 16)
5475 + (stub_words
[2] & 0x0000ffff));
5478 /* Not a recognized stub. */
5483 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5485 CORE_ADDR target_pc
;
5487 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5491 target_pc
= find_solib_trampoline_target (frame
, pc
);
5495 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5502 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5503 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5506 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5509 if (num
>= 0 && num
< 32)
5511 else if (num
>= 38 && num
< 70)
5512 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5514 regnum
= mips_regnum (gdbarch
)->hi
;
5516 regnum
= mips_regnum (gdbarch
)->lo
;
5518 /* This will hopefully (eventually) provoke a warning. Should
5519 we be calling complaint() here? */
5520 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5521 return gdbarch_num_regs (gdbarch
) + regnum
;
5525 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5526 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5529 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5532 if (num
>= 0 && num
< 32)
5534 else if (num
>= 32 && num
< 64)
5535 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5537 regnum
= mips_regnum (gdbarch
)->hi
;
5539 regnum
= mips_regnum (gdbarch
)->lo
;
5541 /* This will hopefully (eventually) provoke a warning. Should we
5542 be calling complaint() here? */
5543 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5544 return gdbarch_num_regs (gdbarch
) + regnum
;
5548 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5550 /* Only makes sense to supply raw registers. */
5551 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5552 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5553 decide if it is valid. Should instead define a standard sim/gdb
5554 register numbering scheme. */
5555 if (gdbarch_register_name (gdbarch
,
5556 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5557 && gdbarch_register_name (gdbarch
,
5558 gdbarch_num_regs (gdbarch
)
5559 + regnum
)[0] != '\0')
5562 return LEGACY_SIM_REGNO_IGNORE
;
5566 /* Convert an integer into an address. Extracting the value signed
5567 guarantees a correctly sign extended address. */
5570 mips_integer_to_address (struct gdbarch
*gdbarch
,
5571 struct type
*type
, const gdb_byte
*buf
)
5573 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5574 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
5577 /* Dummy virtual frame pointer method. This is no more or less accurate
5578 than most other architectures; we just need to be explicit about it,
5579 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5580 an assertion failure. */
5583 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5584 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5586 *reg
= MIPS_SP_REGNUM
;
5591 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5593 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5594 const char *name
= bfd_get_section_name (abfd
, sect
);
5596 if (*abip
!= MIPS_ABI_UNKNOWN
)
5599 if (strncmp (name
, ".mdebug.", 8) != 0)
5602 if (strcmp (name
, ".mdebug.abi32") == 0)
5603 *abip
= MIPS_ABI_O32
;
5604 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5605 *abip
= MIPS_ABI_N32
;
5606 else if (strcmp (name
, ".mdebug.abi64") == 0)
5607 *abip
= MIPS_ABI_N64
;
5608 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5609 *abip
= MIPS_ABI_O64
;
5610 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5611 *abip
= MIPS_ABI_EABI32
;
5612 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5613 *abip
= MIPS_ABI_EABI64
;
5615 warning (_("unsupported ABI %s."), name
+ 8);
5619 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5621 int *lbp
= (int *) obj
;
5622 const char *name
= bfd_get_section_name (abfd
, sect
);
5624 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5626 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5628 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5629 warning (_("unrecognized .gcc_compiled_longXX"));
5632 static enum mips_abi
5633 global_mips_abi (void)
5637 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5638 if (mips_abi_strings
[i
] == mips_abi_string
)
5639 return (enum mips_abi
) i
;
5641 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5645 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5647 /* If the size matches the set of 32-bit or 64-bit integer registers,
5648 assume that's what we've got. */
5649 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5650 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5652 /* If the size matches the full set of registers GDB traditionally
5653 knows about, including floating point, for either 32-bit or
5654 64-bit, assume that's what we've got. */
5655 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5656 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5658 /* Otherwise we don't have a useful guess. */
5661 static struct value
*
5662 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5664 const int *reg_p
= baton
;
5665 return value_of_register (*reg_p
, frame
);
5668 static struct gdbarch
*
5669 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5671 struct gdbarch
*gdbarch
;
5672 struct gdbarch_tdep
*tdep
;
5674 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5676 enum mips_fpu_type fpu_type
;
5677 struct tdesc_arch_data
*tdesc_data
= NULL
;
5678 int elf_fpu_type
= 0;
5680 /* Check any target description for validity. */
5681 if (tdesc_has_registers (info
.target_desc
))
5683 static const char *const mips_gprs
[] = {
5684 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5685 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5686 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5687 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5689 static const char *const mips_fprs
[] = {
5690 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5691 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5692 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5693 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5696 const struct tdesc_feature
*feature
;
5699 feature
= tdesc_find_feature (info
.target_desc
,
5700 "org.gnu.gdb.mips.cpu");
5701 if (feature
== NULL
)
5704 tdesc_data
= tdesc_data_alloc ();
5707 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5708 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5712 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5713 MIPS_EMBED_LO_REGNUM
, "lo");
5714 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5715 MIPS_EMBED_HI_REGNUM
, "hi");
5716 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5717 MIPS_EMBED_PC_REGNUM
, "pc");
5721 tdesc_data_cleanup (tdesc_data
);
5725 feature
= tdesc_find_feature (info
.target_desc
,
5726 "org.gnu.gdb.mips.cp0");
5727 if (feature
== NULL
)
5729 tdesc_data_cleanup (tdesc_data
);
5734 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5735 MIPS_EMBED_BADVADDR_REGNUM
,
5737 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5738 MIPS_PS_REGNUM
, "status");
5739 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5740 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5744 tdesc_data_cleanup (tdesc_data
);
5748 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5749 backend is not prepared for that, though. */
5750 feature
= tdesc_find_feature (info
.target_desc
,
5751 "org.gnu.gdb.mips.fpu");
5752 if (feature
== NULL
)
5754 tdesc_data_cleanup (tdesc_data
);
5759 for (i
= 0; i
< 32; i
++)
5760 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5761 i
+ MIPS_EMBED_FP0_REGNUM
,
5764 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5765 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5766 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5767 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5771 tdesc_data_cleanup (tdesc_data
);
5775 /* It would be nice to detect an attempt to use a 64-bit ABI
5776 when only 32-bit registers are provided. */
5779 /* First of all, extract the elf_flags, if available. */
5780 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5781 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5782 else if (arches
!= NULL
)
5783 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5787 fprintf_unfiltered (gdb_stdlog
,
5788 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5790 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5791 switch ((elf_flags
& EF_MIPS_ABI
))
5793 case E_MIPS_ABI_O32
:
5794 found_abi
= MIPS_ABI_O32
;
5796 case E_MIPS_ABI_O64
:
5797 found_abi
= MIPS_ABI_O64
;
5799 case E_MIPS_ABI_EABI32
:
5800 found_abi
= MIPS_ABI_EABI32
;
5802 case E_MIPS_ABI_EABI64
:
5803 found_abi
= MIPS_ABI_EABI64
;
5806 if ((elf_flags
& EF_MIPS_ABI2
))
5807 found_abi
= MIPS_ABI_N32
;
5809 found_abi
= MIPS_ABI_UNKNOWN
;
5813 /* GCC creates a pseudo-section whose name describes the ABI. */
5814 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5815 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5817 /* If we have no useful BFD information, use the ABI from the last
5818 MIPS architecture (if there is one). */
5819 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5820 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5822 /* Try the architecture for any hint of the correct ABI. */
5823 if (found_abi
== MIPS_ABI_UNKNOWN
5824 && info
.bfd_arch_info
!= NULL
5825 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5827 switch (info
.bfd_arch_info
->mach
)
5829 case bfd_mach_mips3900
:
5830 found_abi
= MIPS_ABI_EABI32
;
5832 case bfd_mach_mips4100
:
5833 case bfd_mach_mips5000
:
5834 found_abi
= MIPS_ABI_EABI64
;
5836 case bfd_mach_mips8000
:
5837 case bfd_mach_mips10000
:
5838 /* On Irix, ELF64 executables use the N64 ABI. The
5839 pseudo-sections which describe the ABI aren't present
5840 on IRIX. (Even for executables created by gcc.) */
5841 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5842 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5843 found_abi
= MIPS_ABI_N64
;
5845 found_abi
= MIPS_ABI_N32
;
5850 /* Default 64-bit objects to N64 instead of O32. */
5851 if (found_abi
== MIPS_ABI_UNKNOWN
5852 && info
.abfd
!= NULL
5853 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5854 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5855 found_abi
= MIPS_ABI_N64
;
5858 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5861 /* What has the user specified from the command line? */
5862 wanted_abi
= global_mips_abi ();
5864 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5867 /* Now that we have found what the ABI for this binary would be,
5868 check whether the user is overriding it. */
5869 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5870 mips_abi
= wanted_abi
;
5871 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5872 mips_abi
= found_abi
;
5874 mips_abi
= MIPS_ABI_O32
;
5876 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5879 /* Also used when doing an architecture lookup. */
5881 fprintf_unfiltered (gdb_stdlog
,
5882 "mips_gdbarch_init: "
5883 "mips64_transfers_32bit_regs_p = %d\n",
5884 mips64_transfers_32bit_regs_p
);
5886 /* Determine the MIPS FPU type. */
5889 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5890 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5891 Tag_GNU_MIPS_ABI_FP
);
5892 #endif /* HAVE_ELF */
5894 if (!mips_fpu_type_auto
)
5895 fpu_type
= mips_fpu_type
;
5896 else if (elf_fpu_type
!= 0)
5898 switch (elf_fpu_type
)
5901 fpu_type
= MIPS_FPU_DOUBLE
;
5904 fpu_type
= MIPS_FPU_SINGLE
;
5908 /* Soft float or unknown. */
5909 fpu_type
= MIPS_FPU_NONE
;
5913 else if (info
.bfd_arch_info
!= NULL
5914 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5915 switch (info
.bfd_arch_info
->mach
)
5917 case bfd_mach_mips3900
:
5918 case bfd_mach_mips4100
:
5919 case bfd_mach_mips4111
:
5920 case bfd_mach_mips4120
:
5921 fpu_type
= MIPS_FPU_NONE
;
5923 case bfd_mach_mips4650
:
5924 fpu_type
= MIPS_FPU_SINGLE
;
5927 fpu_type
= MIPS_FPU_DOUBLE
;
5930 else if (arches
!= NULL
)
5931 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5933 fpu_type
= MIPS_FPU_DOUBLE
;
5935 fprintf_unfiltered (gdb_stdlog
,
5936 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5938 /* Check for blatant incompatibilities. */
5940 /* If we have only 32-bit registers, then we can't debug a 64-bit
5942 if (info
.target_desc
5943 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5944 && mips_abi
!= MIPS_ABI_EABI32
5945 && mips_abi
!= MIPS_ABI_O32
)
5947 if (tdesc_data
!= NULL
)
5948 tdesc_data_cleanup (tdesc_data
);
5952 /* Try to find a pre-existing architecture. */
5953 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5955 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5957 /* MIPS needs to be pedantic about which ABI the object is
5959 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5961 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5963 /* Need to be pedantic about which register virtual size is
5965 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5966 != mips64_transfers_32bit_regs_p
)
5968 /* Be pedantic about which FPU is selected. */
5969 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5972 if (tdesc_data
!= NULL
)
5973 tdesc_data_cleanup (tdesc_data
);
5974 return arches
->gdbarch
;
5977 /* Need a new architecture. Fill in a target specific vector. */
5978 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5979 gdbarch
= gdbarch_alloc (&info
, tdep
);
5980 tdep
->elf_flags
= elf_flags
;
5981 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5982 tdep
->found_abi
= found_abi
;
5983 tdep
->mips_abi
= mips_abi
;
5984 tdep
->mips_fpu_type
= fpu_type
;
5985 tdep
->register_size_valid_p
= 0;
5986 tdep
->register_size
= 0;
5987 tdep
->gregset
= NULL
;
5988 tdep
->gregset64
= NULL
;
5989 tdep
->fpregset
= NULL
;
5990 tdep
->fpregset64
= NULL
;
5992 if (info
.target_desc
)
5994 /* Some useful properties can be inferred from the target. */
5995 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5997 tdep
->register_size_valid_p
= 1;
5998 tdep
->register_size
= 4;
6000 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
6002 tdep
->register_size_valid_p
= 1;
6003 tdep
->register_size
= 8;
6007 /* Initially set everything according to the default ABI/ISA. */
6008 set_gdbarch_short_bit (gdbarch
, 16);
6009 set_gdbarch_int_bit (gdbarch
, 32);
6010 set_gdbarch_float_bit (gdbarch
, 32);
6011 set_gdbarch_double_bit (gdbarch
, 64);
6012 set_gdbarch_long_double_bit (gdbarch
, 64);
6013 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6014 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6015 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6017 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6018 mips_ax_pseudo_register_collect
);
6019 set_gdbarch_ax_pseudo_register_push_stack
6020 (gdbarch
, mips_ax_pseudo_register_push_stack
);
6022 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6023 mips_elf_make_msymbol_special
);
6025 /* Fill in the OS dependant register numbers and names. */
6027 const char **reg_names
;
6028 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
6029 struct mips_regnum
);
6030 if (tdesc_has_registers (info
.target_desc
))
6032 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6033 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6034 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6035 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6036 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6037 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6038 regnum
->fp_control_status
= 70;
6039 regnum
->fp_implementation_revision
= 71;
6040 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
6043 else if (info
.osabi
== GDB_OSABI_IRIX
)
6048 regnum
->badvaddr
= 66;
6051 regnum
->fp_control_status
= 69;
6052 regnum
->fp_implementation_revision
= 70;
6054 reg_names
= mips_irix_reg_names
;
6058 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6059 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6060 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6061 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6062 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6063 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6064 regnum
->fp_control_status
= 70;
6065 regnum
->fp_implementation_revision
= 71;
6067 if (info
.bfd_arch_info
!= NULL
6068 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6069 reg_names
= mips_tx39_reg_names
;
6071 reg_names
= mips_generic_reg_names
;
6073 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
6074 replaced by gdbarch_read_pc? */
6075 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6076 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6077 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6078 set_gdbarch_num_regs (gdbarch
, num_regs
);
6079 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6080 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6081 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
6082 tdep
->mips_processor_reg_names
= reg_names
;
6083 tdep
->regnum
= regnum
;
6089 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6090 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6091 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6092 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6093 tdep
->default_mask_address_p
= 0;
6094 set_gdbarch_long_bit (gdbarch
, 32);
6095 set_gdbarch_ptr_bit (gdbarch
, 32);
6096 set_gdbarch_long_long_bit (gdbarch
, 64);
6099 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6100 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6101 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6102 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6103 tdep
->default_mask_address_p
= 0;
6104 set_gdbarch_long_bit (gdbarch
, 32);
6105 set_gdbarch_ptr_bit (gdbarch
, 32);
6106 set_gdbarch_long_long_bit (gdbarch
, 64);
6108 case MIPS_ABI_EABI32
:
6109 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6110 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6111 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6112 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6113 tdep
->default_mask_address_p
= 0;
6114 set_gdbarch_long_bit (gdbarch
, 32);
6115 set_gdbarch_ptr_bit (gdbarch
, 32);
6116 set_gdbarch_long_long_bit (gdbarch
, 64);
6118 case MIPS_ABI_EABI64
:
6119 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6120 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6121 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6122 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6123 tdep
->default_mask_address_p
= 0;
6124 set_gdbarch_long_bit (gdbarch
, 64);
6125 set_gdbarch_ptr_bit (gdbarch
, 64);
6126 set_gdbarch_long_long_bit (gdbarch
, 64);
6129 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6130 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6131 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6132 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6133 tdep
->default_mask_address_p
= 0;
6134 set_gdbarch_long_bit (gdbarch
, 32);
6135 set_gdbarch_ptr_bit (gdbarch
, 32);
6136 set_gdbarch_long_long_bit (gdbarch
, 64);
6137 set_gdbarch_long_double_bit (gdbarch
, 128);
6138 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6141 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6142 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6143 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6144 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6145 tdep
->default_mask_address_p
= 0;
6146 set_gdbarch_long_bit (gdbarch
, 64);
6147 set_gdbarch_ptr_bit (gdbarch
, 64);
6148 set_gdbarch_long_long_bit (gdbarch
, 64);
6149 set_gdbarch_long_double_bit (gdbarch
, 128);
6150 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6153 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6156 /* GCC creates a pseudo-section whose name specifies the size of
6157 longs, since -mlong32 or -mlong64 may be used independent of
6158 other options. How those options affect pointer sizes is ABI and
6159 architecture dependent, so use them to override the default sizes
6160 set by the ABI. This table shows the relationship between ABI,
6161 -mlongXX, and size of pointers:
6163 ABI -mlongXX ptr bits
6164 --- -------- --------
6178 Note that for o32 and eabi32, pointers are always 32 bits
6179 regardless of any -mlongXX option. For all others, pointers and
6180 longs are the same, as set by -mlongXX or set by defaults. */
6182 if (info
.abfd
!= NULL
)
6186 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6189 set_gdbarch_long_bit (gdbarch
, long_bit
);
6193 case MIPS_ABI_EABI32
:
6198 case MIPS_ABI_EABI64
:
6199 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6202 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6207 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6208 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6211 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6212 flag in object files because to do so would make it impossible to
6213 link with libraries compiled without "-gp32". This is
6214 unnecessarily restrictive.
6216 We could solve this problem by adding "-gp32" multilibs to gcc,
6217 but to set this flag before gcc is built with such multilibs will
6218 break too many systems.''
6220 But even more unhelpfully, the default linker output target for
6221 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6222 for 64-bit programs - you need to change the ABI to change this,
6223 and not all gcc targets support that currently. Therefore using
6224 this flag to detect 32-bit mode would do the wrong thing given
6225 the current gcc - it would make GDB treat these 64-bit programs
6226 as 32-bit programs by default. */
6228 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6229 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6231 /* Add/remove bits from an address. The MIPS needs be careful to
6232 ensure that all 32 bit addresses are sign extended to 64 bits. */
6233 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6235 /* Unwind the frame. */
6236 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6237 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
6238 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
6240 /* Map debug register numbers onto internal register numbers. */
6241 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6242 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6243 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6244 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6245 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6246 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6248 /* MIPS version of CALL_DUMMY. */
6250 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6251 replaced by a command, and all targets will default to on stack
6252 (regardless of the stack's execute status). */
6253 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6254 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6256 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6257 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6258 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6260 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6261 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6263 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6265 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6267 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6268 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6269 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6271 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6273 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6275 if (mips_abi
== MIPS_ABI_N32
)
6276 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6277 else if (mips_abi
== MIPS_ABI_N64
)
6278 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6280 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6282 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6283 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6284 need to all be folded into the target vector. Since they are
6285 being used as guards for target_stopped_by_watchpoint, why not have
6286 target_stopped_by_watchpoint return the type of watchpoint that the code
6288 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6290 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6292 set_gdbarch_single_step_through_delay (gdbarch
,
6293 mips_single_step_through_delay
);
6295 /* Virtual tables. */
6296 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6298 mips_register_g_packet_guesses (gdbarch
);
6300 /* Hook in OS ABI-specific overrides, if they have been registered. */
6301 info
.tdep_info
= (void *) tdesc_data
;
6302 gdbarch_init_osabi (info
, gdbarch
);
6304 /* Unwind the frame. */
6305 dwarf2_append_unwinders (gdbarch
);
6306 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6307 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6308 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6309 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6310 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6311 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6312 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6316 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6317 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6319 /* Override the normal target description methods to handle our
6320 dual real and pseudo registers. */
6321 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6322 set_gdbarch_register_reggroup_p (gdbarch
,
6323 mips_tdesc_register_reggroup_p
);
6325 num_regs
= gdbarch_num_regs (gdbarch
);
6326 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6327 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6328 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6331 /* Add ABI-specific aliases for the registers. */
6332 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6333 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6334 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6335 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6337 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6338 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6339 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6341 /* Add some other standard aliases. */
6342 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6343 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6344 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6346 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6347 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6348 value_of_mips_user_reg
,
6349 &mips_numeric_register_aliases
[i
].regnum
);
6355 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6357 struct gdbarch_info info
;
6359 /* Force the architecture to update, and (if it's a MIPS architecture)
6360 mips_gdbarch_init will take care of the rest. */
6361 gdbarch_info_init (&info
);
6362 gdbarch_update_p (info
);
6365 /* Print out which MIPS ABI is in use. */
6368 show_mips_abi (struct ui_file
*file
,
6370 struct cmd_list_element
*ignored_cmd
,
6371 const char *ignored_value
)
6373 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6376 "The MIPS ABI is unknown because the current architecture "
6380 enum mips_abi global_abi
= global_mips_abi ();
6381 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6382 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6384 if (global_abi
== MIPS_ABI_UNKNOWN
)
6387 "The MIPS ABI is set automatically (currently \"%s\").\n",
6389 else if (global_abi
== actual_abi
)
6392 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6396 /* Probably shouldn't happen... */
6397 fprintf_filtered (file
,
6398 "The (auto detected) MIPS ABI \"%s\" is in use "
6399 "even though the user setting was \"%s\".\n",
6400 actual_abi_str
, mips_abi_strings
[global_abi
]);
6406 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6408 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6412 int ef_mips_32bitmode
;
6413 /* Determine the ISA. */
6414 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6432 /* Determine the size of a pointer. */
6433 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6434 fprintf_unfiltered (file
,
6435 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6437 fprintf_unfiltered (file
,
6438 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6440 fprintf_unfiltered (file
,
6441 "mips_dump_tdep: ef_mips_arch = %d\n",
6443 fprintf_unfiltered (file
,
6444 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6445 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6446 fprintf_unfiltered (file
,
6448 "mips_mask_address_p() %d (default %d)\n",
6449 mips_mask_address_p (tdep
),
6450 tdep
->default_mask_address_p
);
6452 fprintf_unfiltered (file
,
6453 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6454 MIPS_DEFAULT_FPU_TYPE
,
6455 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6456 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6457 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6459 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6460 MIPS_EABI (gdbarch
));
6461 fprintf_unfiltered (file
,
6462 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6463 MIPS_FPU_TYPE (gdbarch
),
6464 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6465 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6466 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6470 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6473 _initialize_mips_tdep (void)
6475 static struct cmd_list_element
*mipsfpulist
= NULL
;
6476 struct cmd_list_element
*c
;
6478 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6479 if (MIPS_ABI_LAST
+ 1
6480 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6481 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6483 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6485 mips_pdr_data
= register_objfile_data ();
6487 /* Create feature sets with the appropriate properties. The values
6488 are not important. */
6489 mips_tdesc_gp32
= allocate_target_description ();
6490 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6492 mips_tdesc_gp64
= allocate_target_description ();
6493 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6495 /* Add root prefix command for all "set mips"/"show mips" commands. */
6496 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6497 _("Various MIPS specific commands."),
6498 &setmipscmdlist
, "set mips ", 0, &setlist
);
6500 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6501 _("Various MIPS specific commands."),
6502 &showmipscmdlist
, "show mips ", 0, &showlist
);
6504 /* Allow the user to override the ABI. */
6505 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6506 &mips_abi_string
, _("\
6507 Set the MIPS ABI used by this program."), _("\
6508 Show the MIPS ABI used by this program."), _("\
6509 This option can be set to one of:\n\
6510 auto - the default ABI associated with the current binary\n\
6519 &setmipscmdlist
, &showmipscmdlist
);
6521 /* Let the user turn off floating point and set the fence post for
6522 heuristic_proc_start. */
6524 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6525 _("Set use of MIPS floating-point coprocessor."),
6526 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6527 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6528 _("Select single-precision MIPS floating-point coprocessor."),
6530 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6531 _("Select double-precision MIPS floating-point coprocessor."),
6533 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6534 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6535 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6536 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6537 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6538 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6539 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6540 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6541 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6542 _("Select MIPS floating-point coprocessor automatically."),
6544 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6545 _("Show current use of MIPS floating-point coprocessor target."),
6548 /* We really would like to have both "0" and "unlimited" work, but
6549 command.c doesn't deal with that. So make it a var_zinteger
6550 because the user can always use "999999" or some such for unlimited. */
6551 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6552 &heuristic_fence_post
, _("\
6553 Set the distance searched for the start of a function."), _("\
6554 Show the distance searched for the start of a function."), _("\
6555 If you are debugging a stripped executable, GDB needs to search through the\n\
6556 program for the start of a function. This command sets the distance of the\n\
6557 search. The only need to set it is when debugging a stripped executable."),
6558 reinit_frame_cache_sfunc
,
6559 NULL
, /* FIXME: i18n: The distance searched for
6560 the start of a function is %s. */
6561 &setlist
, &showlist
);
6563 /* Allow the user to control whether the upper bits of 64-bit
6564 addresses should be zeroed. */
6565 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6566 &mask_address_var
, _("\
6567 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6568 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6569 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
6570 allow GDB to determine the correct value."),
6571 NULL
, show_mask_address
,
6572 &setmipscmdlist
, &showmipscmdlist
);
6574 /* Allow the user to control the size of 32 bit registers within the
6575 raw remote packet. */
6576 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6577 &mips64_transfers_32bit_regs_p
, _("\
6578 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6580 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6582 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6583 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6584 64 bits for others. Use \"off\" to disable compatibility mode"),
6585 set_mips64_transfers_32bit_regs
,
6586 NULL
, /* FIXME: i18n: Compatibility with 64-bit
6587 MIPS target that transfers 32-bit
6588 quantities is %s. */
6589 &setlist
, &showlist
);
6591 /* Debug this files internals. */
6592 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6594 Set mips debugging."), _("\
6595 Show mips debugging."), _("\
6596 When non-zero, mips specific debugging is enabled."),
6598 NULL
, /* FIXME: i18n: Mips debugging is
6600 &setdebuglist
, &showdebuglist
);