1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE
= 4,
72 MIPS_FPU_DOUBLE_REGSIZE
= 8
76 static const char *mips_abi_string
;
78 static const char *mips_abi_strings
[] = {
89 /* Various MIPS ISA options (related to stack analysis) can be
90 overridden dynamically. Establish an enum/array for managing
93 static const char size_auto
[] = "auto";
94 static const char size_32
[] = "32";
95 static const char size_64
[] = "64";
97 static const char *size_enums
[] = {
104 /* Some MIPS boards don't support floating point while others only
105 support single-precision floating-point operations. */
109 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
110 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
111 MIPS_FPU_NONE
/* No floating point. */
114 #ifndef MIPS_DEFAULT_FPU_TYPE
115 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
117 static int mips_fpu_type_auto
= 1;
118 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
120 static int mips_debug
= 0;
122 /* MIPS specific per-architecture information */
125 /* from the elf header */
129 enum mips_abi mips_abi
;
130 enum mips_abi found_abi
;
131 enum mips_fpu_type mips_fpu_type
;
132 int mips_last_arg_regnum
;
133 int mips_last_fp_arg_regnum
;
134 int default_mask_address_p
;
135 /* Is the target using 64-bit raw integer registers but only
136 storing a left-aligned 32-bit value in each? */
137 int mips64_transfers_32bit_regs_p
;
138 /* Indexes for various registers. IRIX and embedded have
139 different values. This contains the "public" fields. Don't
140 add any that do not need to be public. */
141 const struct mips_regnum
*regnum
;
142 /* Register names table for the current register set. */
143 const char **mips_processor_reg_names
;
147 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
153 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
154 They are implemented as a pair of 64bit doubles where the high
155 part holds the result of the operation rounded to double, and
156 the low double holds the difference between the exact result and
157 the rounded result. So "high" + "low" contains the result with
158 added precision. Unfortunately, the floatformat structure used
159 by GDB is not powerful enough to describe this format. As a temporary
160 measure, we define a 128bit floatformat that only uses the high part.
161 We lose a bit of precision but that's probably the best we can do
162 for now with the current infrastructure. */
164 static const struct floatformat floatformat_n32n64_long_double_big
=
166 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
167 floatformat_intbit_no
,
168 "floatformat_ieee_double_big",
169 n32n64_floatformat_always_valid
172 const struct mips_regnum
*
173 mips_regnum (struct gdbarch
*gdbarch
)
175 return gdbarch_tdep (gdbarch
)->regnum
;
179 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
181 return mips_regnum (gdbarch
)->fp0
+ 12;
184 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
185 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
187 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
189 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
191 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
193 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
194 functions to test, set, or clear bit 0 of addresses. */
197 is_mips16_addr (CORE_ADDR addr
)
203 unmake_mips16_addr (CORE_ADDR addr
)
205 return ((addr
) & ~1);
208 /* Return the contents of register REGNUM as a signed integer. */
211 read_signed_register (int regnum
)
214 regcache_cooked_read_signed (current_regcache
, regnum
, &val
);
219 read_signed_register_pid (int regnum
, ptid_t ptid
)
224 if (ptid_equal (ptid
, inferior_ptid
))
225 return read_signed_register (regnum
);
227 save_ptid
= inferior_ptid
;
229 inferior_ptid
= ptid
;
231 retval
= read_signed_register (regnum
);
233 inferior_ptid
= save_ptid
;
238 /* Return the MIPS ABI associated with GDBARCH. */
240 mips_abi (struct gdbarch
*gdbarch
)
242 return gdbarch_tdep (gdbarch
)->mips_abi
;
246 mips_isa_regsize (struct gdbarch
*gdbarch
)
248 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
249 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
252 /* Return the currently configured (or set) saved register size. */
254 static const char *mips_abi_regsize_string
= size_auto
;
257 mips_abi_regsize (struct gdbarch
*gdbarch
)
259 if (mips_abi_regsize_string
== size_auto
)
260 switch (mips_abi (gdbarch
))
262 case MIPS_ABI_EABI32
:
268 case MIPS_ABI_EABI64
:
270 case MIPS_ABI_UNKNOWN
:
273 internal_error (__FILE__
, __LINE__
, "bad switch");
275 else if (mips_abi_regsize_string
== size_64
)
277 else /* if (mips_abi_regsize_string == size_32) */
281 /* Functions for setting and testing a bit in a minimal symbol that
282 marks it as 16-bit function. The MSB of the minimal symbol's
283 "info" field is used for this purpose.
285 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
286 i.e. refers to a 16-bit function, and sets a "special" bit in a
287 minimal symbol to mark it as a 16-bit function
289 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
292 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
294 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
296 MSYMBOL_INFO (msym
) = (char *)
297 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
298 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
303 msymbol_is_special (struct minimal_symbol
*msym
)
305 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
308 /* XFER a value from the big/little/left end of the register.
309 Depending on the size of the value it might occupy the entire
310 register or just part of it. Make an allowance for this, aligning
311 things accordingly. */
314 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
315 enum bfd_endian endian
, bfd_byte
* in
,
316 const bfd_byte
* out
, int buf_offset
)
319 gdb_assert (reg_num
>= NUM_REGS
);
320 /* Need to transfer the left or right part of the register, based on
321 the targets byte order. */
325 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
327 case BFD_ENDIAN_LITTLE
:
330 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
334 internal_error (__FILE__
, __LINE__
, "bad switch");
337 fprintf_unfiltered (gdb_stderr
,
338 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
339 reg_num
, reg_offset
, buf_offset
, length
);
340 if (mips_debug
&& out
!= NULL
)
343 fprintf_unfiltered (gdb_stdlog
, "out ");
344 for (i
= 0; i
< length
; i
++)
345 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
348 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
351 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
353 if (mips_debug
&& in
!= NULL
)
356 fprintf_unfiltered (gdb_stdlog
, "in ");
357 for (i
= 0; i
< length
; i
++)
358 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
361 fprintf_unfiltered (gdb_stdlog
, "\n");
364 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
365 compatiblity mode. A return value of 1 means that we have
366 physical 64-bit registers, but should treat them as 32-bit registers. */
369 mips2_fp_compat (void)
371 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
373 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
378 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
379 in all the places we deal with FP registers. PR gdb/413. */
380 /* Otherwise check the FR bit in the status register - it controls
381 the FP compatiblity mode. If it is clear we are in compatibility
383 if ((read_register (MIPS_PS_REGNUM
) & ST0_FR
) == 0)
390 /* The amount of space reserved on the stack for registers. This is
391 different to MIPS_ABI_REGSIZE as it determines the alignment of
392 data allocated after the registers have run out. */
394 static const char *mips_stack_argsize_string
= size_auto
;
397 mips_stack_argsize (struct gdbarch
*gdbarch
)
399 if (mips_stack_argsize_string
== size_auto
)
400 return mips_abi_regsize (gdbarch
);
401 else if (mips_stack_argsize_string
== size_64
)
403 else /* if (mips_stack_argsize_string == size_32) */
407 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
409 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
411 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
413 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
415 static struct type
*mips_float_register_type (void);
416 static struct type
*mips_double_register_type (void);
418 /* The list of available "set mips " and "show mips " commands */
420 static struct cmd_list_element
*setmipscmdlist
= NULL
;
421 static struct cmd_list_element
*showmipscmdlist
= NULL
;
423 /* Integer registers 0 thru 31 are handled explicitly by
424 mips_register_name(). Processor specific registers 32 and above
425 are listed in the followign tables. */
428 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
432 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
433 "sr", "lo", "hi", "bad", "cause", "pc",
434 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
435 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
436 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
437 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
438 "fsr", "fir", "" /*"fp" */ , "",
439 "", "", "", "", "", "", "", "",
440 "", "", "", "", "", "", "", "",
443 /* Names of IDT R3041 registers. */
445 static const char *mips_r3041_reg_names
[] = {
446 "sr", "lo", "hi", "bad", "cause", "pc",
447 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
448 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
449 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
450 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
451 "fsr", "fir", "", /*"fp" */ "",
452 "", "", "bus", "ccfg", "", "", "", "",
453 "", "", "port", "cmp", "", "", "epc", "prid",
456 /* Names of tx39 registers. */
458 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
459 "sr", "lo", "hi", "bad", "cause", "pc",
460 "", "", "", "", "", "", "", "",
461 "", "", "", "", "", "", "", "",
462 "", "", "", "", "", "", "", "",
463 "", "", "", "", "", "", "", "",
465 "", "", "", "", "", "", "", "",
466 "", "", "config", "cache", "debug", "depc", "epc", ""
469 /* Names of IRIX registers. */
470 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
471 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
472 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
473 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
474 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
475 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
479 /* Return the name of the register corresponding to REGNO. */
481 mips_register_name (int regno
)
483 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
484 /* GPR names for all ABIs other than n32/n64. */
485 static char *mips_gpr_names
[] = {
486 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
487 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
488 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
489 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
492 /* GPR names for n32 and n64 ABIs. */
493 static char *mips_n32_n64_gpr_names
[] = {
494 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
495 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
496 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
497 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
500 enum mips_abi abi
= mips_abi (current_gdbarch
);
502 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
503 don't make the raw register names visible. */
504 int rawnum
= regno
% NUM_REGS
;
505 if (regno
< NUM_REGS
)
508 /* The MIPS integer registers are always mapped from 0 to 31. The
509 names of the registers (which reflects the conventions regarding
510 register use) vary depending on the ABI. */
511 if (0 <= rawnum
&& rawnum
< 32)
513 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
514 return mips_n32_n64_gpr_names
[rawnum
];
516 return mips_gpr_names
[rawnum
];
518 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
520 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
521 return tdep
->mips_processor_reg_names
[rawnum
- 32];
524 internal_error (__FILE__
, __LINE__
,
525 "mips_register_name: bad register number %d", rawnum
);
528 /* Return the groups that a MIPS register can be categorised into. */
531 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
532 struct reggroup
*reggroup
)
537 int rawnum
= regnum
% NUM_REGS
;
538 int pseudo
= regnum
/ NUM_REGS
;
539 if (reggroup
== all_reggroup
)
541 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
542 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
543 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
544 (gdbarch), as not all architectures are multi-arch. */
545 raw_p
= rawnum
< NUM_REGS
;
546 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
548 if (reggroup
== float_reggroup
)
549 return float_p
&& pseudo
;
550 if (reggroup
== vector_reggroup
)
551 return vector_p
&& pseudo
;
552 if (reggroup
== general_reggroup
)
553 return (!vector_p
&& !float_p
) && pseudo
;
554 /* Save the pseudo registers. Need to make certain that any code
555 extracting register values from a saved register cache also uses
557 if (reggroup
== save_reggroup
)
558 return raw_p
&& pseudo
;
559 /* Restore the same pseudo register. */
560 if (reggroup
== restore_reggroup
)
561 return raw_p
&& pseudo
;
565 /* Map the symbol table registers which live in the range [1 *
566 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
567 registers. Take care of alignment and size problems. */
570 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
571 int cookednum
, void *buf
)
573 int rawnum
= cookednum
% NUM_REGS
;
574 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
575 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
576 regcache_raw_read (regcache
, rawnum
, buf
);
577 else if (register_size (gdbarch
, rawnum
) >
578 register_size (gdbarch
, cookednum
))
580 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
581 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
582 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
584 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
587 internal_error (__FILE__
, __LINE__
, "bad register size");
591 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
592 struct regcache
*regcache
, int cookednum
,
595 int rawnum
= cookednum
% NUM_REGS
;
596 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
597 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
598 regcache_raw_write (regcache
, rawnum
, buf
);
599 else if (register_size (gdbarch
, rawnum
) >
600 register_size (gdbarch
, cookednum
))
602 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
603 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
604 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
606 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
609 internal_error (__FILE__
, __LINE__
, "bad register size");
612 /* Table to translate MIPS16 register field to actual register number. */
613 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
615 /* Heuristic_proc_start may hunt through the text section for a long
616 time across a 2400 baud serial line. Allows the user to limit this
619 static unsigned int heuristic_fence_post
= 0;
621 /* Number of bytes of storage in the actual machine representation for
622 register N. NOTE: This defines the pseudo register type so need to
623 rebuild the architecture vector. */
625 static int mips64_transfers_32bit_regs_p
= 0;
628 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
629 struct cmd_list_element
*c
)
631 struct gdbarch_info info
;
632 gdbarch_info_init (&info
);
633 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
634 instead of relying on globals. Doing that would let generic code
635 handle the search for this specific architecture. */
636 if (!gdbarch_update_p (info
))
638 mips64_transfers_32bit_regs_p
= 0;
639 error ("32-bit compatibility mode not supported");
643 /* Convert to/from a register and the corresponding memory value. */
646 mips_convert_register_p (int regnum
, struct type
*type
)
648 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
649 && register_size (current_gdbarch
, regnum
) == 4
650 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
651 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
652 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
656 mips_register_to_value (struct frame_info
*frame
, int regnum
,
657 struct type
*type
, void *to
)
659 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
660 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
664 mips_value_to_register (struct frame_info
*frame
, int regnum
,
665 struct type
*type
, const void *from
)
667 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
668 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
671 /* Return the GDB type object for the "standard" data type of data in
675 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
677 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
678 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
679 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
681 /* The floating-point registers raw, or cooked, always match
682 mips_isa_regsize(), and also map 1:1, byte for byte. */
683 switch (gdbarch_byte_order (gdbarch
))
686 if (mips_isa_regsize (gdbarch
) == 4)
687 return builtin_type_ieee_single_big
;
689 return builtin_type_ieee_double_big
;
690 case BFD_ENDIAN_LITTLE
:
691 if (mips_isa_regsize (gdbarch
) == 4)
692 return builtin_type_ieee_single_little
;
694 return builtin_type_ieee_double_little
;
695 case BFD_ENDIAN_UNKNOWN
:
697 internal_error (__FILE__
, __LINE__
, "bad switch");
700 else if (regnum
< NUM_REGS
)
702 /* The raw or ISA registers. These are all sized according to
704 if (mips_isa_regsize (gdbarch
) == 4)
705 return builtin_type_int32
;
707 return builtin_type_int64
;
711 /* The cooked or ABI registers. These are sized according to
712 the ABI (with a few complications). */
713 if (regnum
>= (NUM_REGS
714 + mips_regnum (current_gdbarch
)->fp_control_status
)
715 && regnum
<= NUM_REGS
+ MIPS_LAST_EMBED_REGNUM
)
716 /* The pseudo/cooked view of the embedded registers is always
717 32-bit. The raw view is handled below. */
718 return builtin_type_int32
;
719 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
720 /* The target, while possibly using a 64-bit register buffer,
721 is only transfering 32-bits of each integer register.
722 Reflect this in the cooked/pseudo (ABI) register value. */
723 return builtin_type_int32
;
724 else if (mips_abi_regsize (gdbarch
) == 4)
725 /* The ABI is restricted to 32-bit registers (the ISA could be
727 return builtin_type_int32
;
730 return builtin_type_int64
;
734 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
739 return read_signed_register (MIPS_SP_REGNUM
);
742 /* Should the upper word of 64-bit addresses be zeroed? */
743 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
746 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
748 switch (mask_address_var
)
750 case AUTO_BOOLEAN_TRUE
:
752 case AUTO_BOOLEAN_FALSE
:
755 case AUTO_BOOLEAN_AUTO
:
756 return tdep
->default_mask_address_p
;
758 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
764 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
766 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
767 switch (mask_address_var
)
769 case AUTO_BOOLEAN_TRUE
:
770 printf_filtered ("The 32 bit mips address mask is enabled\n");
772 case AUTO_BOOLEAN_FALSE
:
773 printf_filtered ("The 32 bit mips address mask is disabled\n");
775 case AUTO_BOOLEAN_AUTO
:
777 ("The 32 bit address mask is set automatically. Currently %s\n",
778 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
781 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
786 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
789 mips_pc_is_mips16 (CORE_ADDR memaddr
)
791 struct minimal_symbol
*sym
;
793 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
794 if (is_mips16_addr (memaddr
))
797 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
798 the high bit of the info field. Use this to decide if the function is
799 MIPS16 or normal MIPS. */
800 sym
= lookup_minimal_symbol_by_pc (memaddr
);
802 return msymbol_is_special (sym
);
807 /* MIPS believes that the PC has a sign extended value. Perhaps the
808 all registers should be sign extended for simplicity? */
811 mips_read_pc (ptid_t ptid
)
813 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
817 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
819 return frame_unwind_register_signed (next_frame
,
820 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
823 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
824 dummy frame. The frame ID's base needs to match the TOS value
825 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
828 static struct frame_id
829 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
831 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
832 frame_pc_unwind (next_frame
));
836 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
838 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
841 /* Fetch and return instruction from the specified location. If the PC
842 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
845 mips_fetch_instruction (CORE_ADDR addr
)
847 char buf
[MIPS_INSN32_SIZE
];
851 if (mips_pc_is_mips16 (addr
))
853 instlen
= MIPS_INSN16_SIZE
;
854 addr
= unmake_mips16_addr (addr
);
857 instlen
= MIPS_INSN32_SIZE
;
858 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
860 memory_error (status
, addr
);
861 return extract_unsigned_integer (buf
, instlen
);
864 /* These the fields of 32 bit mips instructions */
865 #define mips32_op(x) (x >> 26)
866 #define itype_op(x) (x >> 26)
867 #define itype_rs(x) ((x >> 21) & 0x1f)
868 #define itype_rt(x) ((x >> 16) & 0x1f)
869 #define itype_immediate(x) (x & 0xffff)
871 #define jtype_op(x) (x >> 26)
872 #define jtype_target(x) (x & 0x03ffffff)
874 #define rtype_op(x) (x >> 26)
875 #define rtype_rs(x) ((x >> 21) & 0x1f)
876 #define rtype_rt(x) ((x >> 16) & 0x1f)
877 #define rtype_rd(x) ((x >> 11) & 0x1f)
878 #define rtype_shamt(x) ((x >> 6) & 0x1f)
879 #define rtype_funct(x) (x & 0x3f)
882 mips32_relative_offset (ULONGEST inst
)
884 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
887 /* Determine whate to set a single step breakpoint while considering
890 mips32_next_pc (CORE_ADDR pc
)
894 inst
= mips_fetch_instruction (pc
);
895 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
897 if (itype_op (inst
) >> 2 == 5)
898 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
900 op
= (itype_op (inst
) & 0x03);
915 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
916 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
918 int tf
= itype_rt (inst
) & 0x01;
919 int cnum
= itype_rt (inst
) >> 2;
921 read_signed_register (mips_regnum (current_gdbarch
)->
923 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
925 if (((cond
>> cnum
) & 0x01) == tf
)
926 pc
+= mips32_relative_offset (inst
) + 4;
931 pc
+= 4; /* Not a branch, next instruction is easy */
934 { /* This gets way messy */
936 /* Further subdivide into SPECIAL, REGIMM and other */
937 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
939 case 0: /* SPECIAL */
940 op
= rtype_funct (inst
);
945 /* Set PC to that address */
946 pc
= read_signed_register (rtype_rs (inst
));
952 break; /* end SPECIAL */
955 op
= itype_rt (inst
); /* branch condition */
960 case 16: /* BLTZAL */
961 case 18: /* BLTZALL */
963 if (read_signed_register (itype_rs (inst
)) < 0)
964 pc
+= mips32_relative_offset (inst
) + 4;
966 pc
+= 8; /* after the delay slot */
970 case 17: /* BGEZAL */
971 case 19: /* BGEZALL */
972 if (read_signed_register (itype_rs (inst
)) >= 0)
973 pc
+= mips32_relative_offset (inst
) + 4;
975 pc
+= 8; /* after the delay slot */
977 /* All of the other instructions in the REGIMM category */
982 break; /* end REGIMM */
987 reg
= jtype_target (inst
) << 2;
988 /* Upper four bits get never changed... */
989 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
992 /* FIXME case JALX : */
995 reg
= jtype_target (inst
) << 2;
996 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
997 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
999 break; /* The new PC will be alternate mode */
1000 case 4: /* BEQ, BEQL */
1002 if (read_signed_register (itype_rs (inst
)) ==
1003 read_signed_register (itype_rt (inst
)))
1004 pc
+= mips32_relative_offset (inst
) + 4;
1008 case 5: /* BNE, BNEL */
1010 if (read_signed_register (itype_rs (inst
)) !=
1011 read_signed_register (itype_rt (inst
)))
1012 pc
+= mips32_relative_offset (inst
) + 4;
1016 case 6: /* BLEZ, BLEZL */
1017 if (read_signed_register (itype_rs (inst
)) <= 0)
1018 pc
+= mips32_relative_offset (inst
) + 4;
1024 greater_branch
: /* BGTZ, BGTZL */
1025 if (read_signed_register (itype_rs (inst
)) > 0)
1026 pc
+= mips32_relative_offset (inst
) + 4;
1033 } /* mips32_next_pc */
1035 /* Decoding the next place to set a breakpoint is irregular for the
1036 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1037 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1038 We dont want to set a single step instruction on the extend instruction
1042 /* Lots of mips16 instruction formats */
1043 /* Predicting jumps requires itype,ritype,i8type
1044 and their extensions extItype,extritype,extI8type
1046 enum mips16_inst_fmts
1048 itype
, /* 0 immediate 5,10 */
1049 ritype
, /* 1 5,3,8 */
1050 rrtype
, /* 2 5,3,3,5 */
1051 rritype
, /* 3 5,3,3,5 */
1052 rrrtype
, /* 4 5,3,3,3,2 */
1053 rriatype
, /* 5 5,3,3,1,4 */
1054 shifttype
, /* 6 5,3,3,3,2 */
1055 i8type
, /* 7 5,3,8 */
1056 i8movtype
, /* 8 5,3,3,5 */
1057 i8mov32rtype
, /* 9 5,3,5,3 */
1058 i64type
, /* 10 5,3,8 */
1059 ri64type
, /* 11 5,3,3,5 */
1060 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1061 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1062 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1063 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1064 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1065 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1066 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1067 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1068 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1069 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1071 /* I am heaping all the fields of the formats into one structure and
1072 then, only the fields which are involved in instruction extension */
1076 unsigned int regx
; /* Function in i8 type */
1081 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1082 for the bits which make up the immediatate extension. */
1085 extended_offset (unsigned int extension
)
1088 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1090 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1092 value
|= extension
& 0x01f; /* extract 4:0 */
1096 /* Only call this function if you know that this is an extendable
1097 instruction, It wont malfunction, but why make excess remote memory references?
1098 If the immediate operands get sign extended or somthing, do it after
1099 the extension is performed.
1101 /* FIXME: Every one of these cases needs to worry about sign extension
1102 when the offset is to be used in relative addressing */
1106 fetch_mips_16 (CORE_ADDR pc
)
1109 pc
&= 0xfffffffe; /* clear the low order bit */
1110 target_read_memory (pc
, buf
, 2);
1111 return extract_unsigned_integer (buf
, 2);
1115 unpack_mips16 (CORE_ADDR pc
,
1116 unsigned int extension
,
1118 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1123 switch (insn_format
)
1130 value
= extended_offset (extension
);
1131 value
= value
<< 11; /* rom for the original value */
1132 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1136 value
= inst
& 0x7ff;
1137 /* FIXME : Consider sign extension */
1146 { /* A register identifier and an offset */
1147 /* Most of the fields are the same as I type but the
1148 immediate value is of a different length */
1152 value
= extended_offset (extension
);
1153 value
= value
<< 8; /* from the original instruction */
1154 value
|= inst
& 0xff; /* eleven bits from instruction */
1155 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1156 if (value
& 0x4000) /* test the sign bit , bit 26 */
1158 value
&= ~0x3fff; /* remove the sign bit */
1164 value
= inst
& 0xff; /* 8 bits */
1165 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1166 /* FIXME: Do sign extension , this format needs it */
1167 if (value
& 0x80) /* THIS CONFUSES ME */
1169 value
&= 0xef; /* remove the sign bit */
1179 unsigned long value
;
1180 unsigned int nexthalf
;
1181 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1182 value
= value
<< 16;
1183 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1191 internal_error (__FILE__
, __LINE__
, "bad switch");
1193 upk
->offset
= offset
;
1200 add_offset_16 (CORE_ADDR pc
, int offset
)
1202 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1206 extended_mips16_next_pc (CORE_ADDR pc
,
1207 unsigned int extension
, unsigned int insn
)
1209 int op
= (insn
>> 11);
1212 case 2: /* Branch */
1215 struct upk_mips16 upk
;
1216 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1217 offset
= upk
.offset
;
1223 pc
+= (offset
<< 1) + 2;
1226 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1228 struct upk_mips16 upk
;
1229 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1230 pc
= add_offset_16 (pc
, upk
.offset
);
1231 if ((insn
>> 10) & 0x01) /* Exchange mode */
1232 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1239 struct upk_mips16 upk
;
1241 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1242 reg
= read_signed_register (upk
.regx
);
1244 pc
+= (upk
.offset
<< 1) + 2;
1251 struct upk_mips16 upk
;
1253 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1254 reg
= read_signed_register (upk
.regx
);
1256 pc
+= (upk
.offset
<< 1) + 2;
1261 case 12: /* I8 Formats btez btnez */
1263 struct upk_mips16 upk
;
1265 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1266 /* upk.regx contains the opcode */
1267 reg
= read_signed_register (24); /* Test register is 24 */
1268 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1269 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1270 /* pc = add_offset_16(pc,upk.offset) ; */
1271 pc
+= (upk
.offset
<< 1) + 2;
1276 case 29: /* RR Formats JR, JALR, JALR-RA */
1278 struct upk_mips16 upk
;
1279 /* upk.fmt = rrtype; */
1284 upk
.regx
= (insn
>> 8) & 0x07;
1285 upk
.regy
= (insn
>> 5) & 0x07;
1293 break; /* Function return instruction */
1299 break; /* BOGUS Guess */
1301 pc
= read_signed_register (reg
);
1308 /* This is an instruction extension. Fetch the real instruction
1309 (which follows the extension) and decode things based on
1313 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1326 mips16_next_pc (CORE_ADDR pc
)
1328 unsigned int insn
= fetch_mips_16 (pc
);
1329 return extended_mips16_next_pc (pc
, 0, insn
);
1332 /* The mips_next_pc function supports single_step when the remote
1333 target monitor or stub is not developed enough to do a single_step.
1334 It works by decoding the current instruction and predicting where a
1335 branch will go. This isnt hard because all the data is available.
1336 The MIPS32 and MIPS16 variants are quite different */
1338 mips_next_pc (CORE_ADDR pc
)
1341 return mips16_next_pc (pc
);
1343 return mips32_next_pc (pc
);
1346 struct mips_frame_cache
1349 struct trad_frame_saved_reg
*saved_regs
;
1352 /* Set a register's saved stack address in temp_saved_regs. If an
1353 address has already been set for this register, do nothing; this
1354 way we will only recognize the first save of a given register in a
1357 For simplicity, save the address in both [0 .. NUM_REGS) and
1358 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1359 is used as it is only second range (the ABI instead of ISA
1360 registers) that comes into play when finding saved registers in a
1364 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1367 if (this_cache
!= NULL
1368 && this_cache
->saved_regs
[regnum
].addr
== -1)
1370 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
1371 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
1376 /* Fetch the immediate value from a MIPS16 instruction.
1377 If the previous instruction was an EXTEND, use it to extend
1378 the upper bits of the immediate value. This is a helper function
1379 for mips16_scan_prologue. */
1382 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1383 unsigned short inst
, /* current instruction */
1384 int nbits
, /* number of bits in imm field */
1385 int scale
, /* scale factor to be applied to imm */
1386 int is_signed
) /* is the imm field signed? */
1390 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1392 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1393 if (offset
& 0x8000) /* check for negative extend */
1394 offset
= 0 - (0x10000 - (offset
& 0xffff));
1395 return offset
| (inst
& 0x1f);
1399 int max_imm
= 1 << nbits
;
1400 int mask
= max_imm
- 1;
1401 int sign_bit
= max_imm
>> 1;
1403 offset
= inst
& mask
;
1404 if (is_signed
&& (offset
& sign_bit
))
1405 offset
= 0 - (max_imm
- offset
);
1406 return offset
* scale
;
1411 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1412 the associated FRAME_CACHE if not null.
1413 Return the address of the first instruction past the prologue. */
1416 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1417 struct frame_info
*next_frame
,
1418 struct mips_frame_cache
*this_cache
)
1421 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1423 long frame_offset
= 0; /* Size of stack frame. */
1424 long frame_adjust
= 0; /* Offset of FP from SP. */
1425 int frame_reg
= MIPS_SP_REGNUM
;
1426 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1427 unsigned inst
= 0; /* current instruction */
1428 unsigned entry_inst
= 0; /* the entry instruction */
1431 int extend_bytes
= 0;
1432 int prev_extend_bytes
;
1433 CORE_ADDR end_prologue_addr
= 0;
1435 /* Can be called when there's no process, and hence when there's no
1437 if (next_frame
!= NULL
)
1438 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1442 if (limit_pc
> start_pc
+ 200)
1443 limit_pc
= start_pc
+ 200;
1445 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1447 /* Save the previous instruction. If it's an EXTEND, we'll extract
1448 the immediate offset extension from it in mips16_get_imm. */
1451 /* Fetch and decode the instruction. */
1452 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1454 /* Normally we ignore extend instructions. However, if it is
1455 not followed by a valid prologue instruction, then this
1456 instruction is not part of the prologue either. We must
1457 remember in this case to adjust the end_prologue_addr back
1459 if ((inst
& 0xf800) == 0xf000) /* extend */
1461 extend_bytes
= MIPS_INSN16_SIZE
;
1465 prev_extend_bytes
= extend_bytes
;
1468 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1469 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1471 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1472 if (offset
< 0) /* negative stack adjustment? */
1473 frame_offset
-= offset
;
1475 /* Exit loop if a positive stack adjustment is found, which
1476 usually means that the stack cleanup code in the function
1477 epilogue is reached. */
1480 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1482 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1483 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1484 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1486 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1488 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1489 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1490 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1492 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1494 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1495 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1497 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1499 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1500 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1502 else if (inst
== 0x673d) /* move $s1, $sp */
1507 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1509 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1510 frame_addr
= sp
+ offset
;
1512 frame_adjust
= offset
;
1514 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1516 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1517 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1518 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1520 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1522 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1523 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1524 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1526 else if ((inst
& 0xf81f) == 0xe809
1527 && (inst
& 0x700) != 0x700) /* entry */
1528 entry_inst
= inst
; /* save for later processing */
1529 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1530 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1531 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1533 /* This instruction is part of the prologue, but we don't
1534 need to do anything special to handle it. */
1538 /* This instruction is not an instruction typically found
1539 in a prologue, so we must have reached the end of the
1541 if (end_prologue_addr
== 0)
1542 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1546 /* The entry instruction is typically the first instruction in a function,
1547 and it stores registers at offsets relative to the value of the old SP
1548 (before the prologue). But the value of the sp parameter to this
1549 function is the new SP (after the prologue has been executed). So we
1550 can't calculate those offsets until we've seen the entire prologue,
1551 and can calculate what the old SP must have been. */
1552 if (entry_inst
!= 0)
1554 int areg_count
= (entry_inst
>> 8) & 7;
1555 int sreg_count
= (entry_inst
>> 6) & 3;
1557 /* The entry instruction always subtracts 32 from the SP. */
1560 /* Now we can calculate what the SP must have been at the
1561 start of the function prologue. */
1564 /* Check if a0-a3 were saved in the caller's argument save area. */
1565 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1567 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1568 offset
+= mips_abi_regsize (current_gdbarch
);
1571 /* Check if the ra register was pushed on the stack. */
1573 if (entry_inst
& 0x20)
1575 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1576 offset
-= mips_abi_regsize (current_gdbarch
);
1579 /* Check if the s0 and s1 registers were pushed on the stack. */
1580 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1582 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1583 offset
-= mips_abi_regsize (current_gdbarch
);
1587 if (this_cache
!= NULL
)
1590 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1591 + frame_offset
- frame_adjust
);
1592 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1593 be able to get rid of the assignment below, evetually. But it's
1594 still needed for now. */
1595 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1596 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1599 /* If we didn't reach the end of the prologue when scanning the function
1600 instructions, then set end_prologue_addr to the address of the
1601 instruction immediately after the last one we scanned. */
1602 if (end_prologue_addr
== 0)
1603 end_prologue_addr
= cur_pc
;
1605 return end_prologue_addr
;
1608 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1609 Procedures that use the 32-bit instruction set are handled by the
1610 mips_insn32 unwinder. */
1612 static struct mips_frame_cache
*
1613 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1615 struct mips_frame_cache
*cache
;
1617 if ((*this_cache
) != NULL
)
1618 return (*this_cache
);
1619 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1620 (*this_cache
) = cache
;
1621 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1623 /* Analyze the function prologue. */
1625 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1626 CORE_ADDR start_addr
;
1628 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1629 if (start_addr
== 0)
1630 start_addr
= heuristic_proc_start (pc
);
1631 /* We can't analyze the prologue if we couldn't find the begining
1633 if (start_addr
== 0)
1636 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1639 /* SP_REGNUM, contains the value and not the address. */
1640 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1642 return (*this_cache
);
1646 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1647 struct frame_id
*this_id
)
1649 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1651 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1655 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1657 int regnum
, int *optimizedp
,
1658 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1659 int *realnump
, void *valuep
)
1661 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1663 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1664 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1667 static const struct frame_unwind mips_insn16_frame_unwind
=
1670 mips_insn16_frame_this_id
,
1671 mips_insn16_frame_prev_register
1674 static const struct frame_unwind
*
1675 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1677 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1678 if (mips_pc_is_mips16 (pc
))
1679 return &mips_insn16_frame_unwind
;
1684 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1687 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1692 static const struct frame_base mips_insn16_frame_base
=
1694 &mips_insn16_frame_unwind
,
1695 mips_insn16_frame_base_address
,
1696 mips_insn16_frame_base_address
,
1697 mips_insn16_frame_base_address
1700 static const struct frame_base
*
1701 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1703 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1704 return &mips_insn16_frame_base
;
1709 /* Mark all the registers as unset in the saved_regs array
1710 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1713 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1715 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1719 const int num_regs
= NUM_REGS
;
1722 for (i
= 0; i
< num_regs
; i
++)
1724 this_cache
->saved_regs
[i
].addr
= -1;
1729 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1730 the associated FRAME_CACHE if not null.
1731 Return the address of the first instruction past the prologue. */
1734 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1735 struct frame_info
*next_frame
,
1736 struct mips_frame_cache
*this_cache
)
1739 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1742 int frame_reg
= MIPS_SP_REGNUM
;
1744 CORE_ADDR end_prologue_addr
= 0;
1745 int seen_sp_adjust
= 0;
1746 int load_immediate_bytes
= 0;
1748 /* Can be called when there's no process, and hence when there's no
1750 if (next_frame
!= NULL
)
1751 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1755 if (limit_pc
> start_pc
+ 200)
1756 limit_pc
= start_pc
+ 200;
1761 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1763 unsigned long inst
, high_word
, low_word
;
1766 /* Fetch the instruction. */
1767 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1769 /* Save some code by pre-extracting some useful fields. */
1770 high_word
= (inst
>> 16) & 0xffff;
1771 low_word
= inst
& 0xffff;
1772 reg
= high_word
& 0x1f;
1774 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1775 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1776 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1778 if (low_word
& 0x8000) /* negative stack adjustment? */
1779 frame_offset
+= 0x10000 - low_word
;
1781 /* Exit loop if a positive stack adjustment is found, which
1782 usually means that the stack cleanup code in the function
1783 epilogue is reached. */
1787 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1789 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1791 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1793 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1794 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1796 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1798 /* Old gcc frame, r30 is virtual frame pointer. */
1799 if ((long) low_word
!= frame_offset
)
1800 frame_addr
= sp
+ low_word
;
1801 else if (frame_reg
== MIPS_SP_REGNUM
)
1803 unsigned alloca_adjust
;
1806 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
1807 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1808 if (alloca_adjust
> 0)
1810 /* FP > SP + frame_size. This may be because of
1811 an alloca or somethings similar. Fix sp to
1812 "pre-alloca" value, and try again. */
1813 sp
+= alloca_adjust
;
1814 /* Need to reset the status of all registers. Otherwise,
1815 we will hit a guard that prevents the new address
1816 for each register to be recomputed during the second
1818 reset_saved_regs (this_cache
);
1823 /* move $30,$sp. With different versions of gas this will be either
1824 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1825 Accept any one of these. */
1826 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1828 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1829 if (frame_reg
== MIPS_SP_REGNUM
)
1831 unsigned alloca_adjust
;
1834 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
1835 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1836 if (alloca_adjust
> 0)
1838 /* FP > SP + frame_size. This may be because of
1839 an alloca or somethings similar. Fix sp to
1840 "pre-alloca" value, and try again. */
1842 /* Need to reset the status of all registers. Otherwise,
1843 we will hit a guard that prevents the new address
1844 for each register to be recomputed during the second
1846 reset_saved_regs (this_cache
);
1851 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1853 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
1855 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1856 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1857 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1858 || high_word
== 0x3c1c /* lui $gp,n */
1859 || high_word
== 0x279c /* addiu $gp,$gp,n */
1860 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1861 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
1864 /* These instructions are part of the prologue, but we don't
1865 need to do anything special to handle them. */
1867 /* The instructions below load $at or $t0 with an immediate
1868 value in preparation for a stack adjustment via
1869 subu $sp,$sp,[$at,$t0]. These instructions could also
1870 initialize a local variable, so we accept them only before
1871 a stack adjustment instruction was seen. */
1872 else if (!seen_sp_adjust
1873 && (high_word
== 0x3c01 /* lui $at,n */
1874 || high_word
== 0x3c08 /* lui $t0,n */
1875 || high_word
== 0x3421 /* ori $at,$at,n */
1876 || high_word
== 0x3508 /* ori $t0,$t0,n */
1877 || high_word
== 0x3401 /* ori $at,$zero,n */
1878 || high_word
== 0x3408 /* ori $t0,$zero,n */
1881 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
1885 /* This instruction is not an instruction typically found
1886 in a prologue, so we must have reached the end of the
1888 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
1889 loop now? Why would we need to continue scanning the function
1891 if (end_prologue_addr
== 0)
1892 end_prologue_addr
= cur_pc
;
1896 if (this_cache
!= NULL
)
1899 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1901 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
1902 this assignment below, eventually. But it's still needed
1904 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1905 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1908 /* If we didn't reach the end of the prologue when scanning the function
1909 instructions, then set end_prologue_addr to the address of the
1910 instruction immediately after the last one we scanned. */
1911 /* brobecker/2004-10-10: I don't think this would ever happen, but
1912 we may as well be careful and do our best if we have a null
1913 end_prologue_addr. */
1914 if (end_prologue_addr
== 0)
1915 end_prologue_addr
= cur_pc
;
1917 /* In a frameless function, we might have incorrectly
1918 skipped some load immediate instructions. Undo the skipping
1919 if the load immediate was not followed by a stack adjustment. */
1920 if (load_immediate_bytes
&& !seen_sp_adjust
)
1921 end_prologue_addr
-= load_immediate_bytes
;
1923 return end_prologue_addr
;
1926 /* Heuristic unwinder for procedures using 32-bit instructions (covers
1927 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
1928 instructions (a.k.a. MIPS16) are handled by the mips_insn16
1931 static struct mips_frame_cache
*
1932 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1934 struct mips_frame_cache
*cache
;
1936 if ((*this_cache
) != NULL
)
1937 return (*this_cache
);
1939 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1940 (*this_cache
) = cache
;
1941 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1943 /* Analyze the function prologue. */
1945 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1946 CORE_ADDR start_addr
;
1948 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1949 if (start_addr
== 0)
1950 start_addr
= heuristic_proc_start (pc
);
1951 /* We can't analyze the prologue if we couldn't find the begining
1953 if (start_addr
== 0)
1956 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1959 /* SP_REGNUM, contains the value and not the address. */
1960 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1962 return (*this_cache
);
1966 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1967 struct frame_id
*this_id
)
1969 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1971 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1975 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
1977 int regnum
, int *optimizedp
,
1978 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1979 int *realnump
, void *valuep
)
1981 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1983 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1984 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1987 static const struct frame_unwind mips_insn32_frame_unwind
=
1990 mips_insn32_frame_this_id
,
1991 mips_insn32_frame_prev_register
1994 static const struct frame_unwind
*
1995 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
1997 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1998 if (! mips_pc_is_mips16 (pc
))
1999 return &mips_insn32_frame_unwind
;
2004 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2007 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2012 static const struct frame_base mips_insn32_frame_base
=
2014 &mips_insn32_frame_unwind
,
2015 mips_insn32_frame_base_address
,
2016 mips_insn32_frame_base_address
,
2017 mips_insn32_frame_base_address
2020 static const struct frame_base
*
2021 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2023 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2024 return &mips_insn32_frame_base
;
2029 static struct trad_frame_cache
*
2030 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2033 CORE_ADDR start_addr
;
2034 CORE_ADDR stack_addr
;
2035 struct trad_frame_cache
*this_trad_cache
;
2037 if ((*this_cache
) != NULL
)
2038 return (*this_cache
);
2039 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2040 (*this_cache
) = this_trad_cache
;
2042 /* The return address is in the link register. */
2043 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, MIPS_RA_REGNUM
);
2045 /* Frame ID, since it's a frameless / stackless function, no stack
2046 space is allocated and SP on entry is the current SP. */
2047 pc
= frame_pc_unwind (next_frame
);
2048 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2049 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2050 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2052 /* Assume that the frame's base is the same as the
2054 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2056 return this_trad_cache
;
2060 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2061 struct frame_id
*this_id
)
2063 struct trad_frame_cache
*this_trad_cache
2064 = mips_stub_frame_cache (next_frame
, this_cache
);
2065 trad_frame_get_id (this_trad_cache
, this_id
);
2069 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2071 int regnum
, int *optimizedp
,
2072 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2073 int *realnump
, void *valuep
)
2075 struct trad_frame_cache
*this_trad_cache
2076 = mips_stub_frame_cache (next_frame
, this_cache
);
2077 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2078 lvalp
, addrp
, realnump
, valuep
);
2081 static const struct frame_unwind mips_stub_frame_unwind
=
2084 mips_stub_frame_this_id
,
2085 mips_stub_frame_prev_register
2088 static const struct frame_unwind
*
2089 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2091 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2092 if (in_plt_section (pc
, NULL
))
2093 return &mips_stub_frame_unwind
;
2099 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2102 struct trad_frame_cache
*this_trad_cache
2103 = mips_stub_frame_cache (next_frame
, this_cache
);
2104 return trad_frame_get_this_base (this_trad_cache
);
2107 static const struct frame_base mips_stub_frame_base
=
2109 &mips_stub_frame_unwind
,
2110 mips_stub_frame_base_address
,
2111 mips_stub_frame_base_address
,
2112 mips_stub_frame_base_address
2115 static const struct frame_base
*
2116 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2118 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2119 return &mips_stub_frame_base
;
2125 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2127 /* Always a pseudo. */
2128 gdb_assert (regno
>= NUM_REGS
);
2132 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2136 return frame_unwind_register_signed (fi
, regno
);
2140 /* mips_addr_bits_remove - remove useless address bits */
2143 mips_addr_bits_remove (CORE_ADDR addr
)
2145 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2146 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2147 /* This hack is a work-around for existing boards using PMON, the
2148 simulator, and any other 64-bit targets that doesn't have true
2149 64-bit addressing. On these targets, the upper 32 bits of
2150 addresses are ignored by the hardware. Thus, the PC or SP are
2151 likely to have been sign extended to all 1s by instruction
2152 sequences that load 32-bit addresses. For example, a typical
2153 piece of code that loads an address is this:
2155 lui $r2, <upper 16 bits>
2156 ori $r2, <lower 16 bits>
2158 But the lui sign-extends the value such that the upper 32 bits
2159 may be all 1s. The workaround is simply to mask off these
2160 bits. In the future, gcc may be changed to support true 64-bit
2161 addressing, and this masking will have to be disabled. */
2162 return addr
&= 0xffffffffUL
;
2167 /* mips_software_single_step() is called just before we want to resume
2168 the inferior, if we want to single-step it but there is no hardware
2169 or kernel single-step support (MIPS on GNU/Linux for example). We find
2170 the target of the coming instruction and breakpoint it.
2172 single_step is also called just after the inferior stops. If we had
2173 set up a simulated single-step, we undo our damage. */
2176 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2178 static CORE_ADDR next_pc
;
2179 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2180 static binsn_quantum break_mem
;
2183 if (insert_breakpoints_p
)
2185 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2186 next_pc
= mips_next_pc (pc
);
2188 target_insert_breakpoint (next_pc
, break_mem
);
2191 target_remove_breakpoint (next_pc
, break_mem
);
2194 /* Test whether the PC points to the return instruction at the
2195 end of a function. */
2198 mips_about_to_return (CORE_ADDR pc
)
2200 if (mips_pc_is_mips16 (pc
))
2201 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2202 generates a "jr $ra"; other times it generates code to load
2203 the return address from the stack to an accessible register (such
2204 as $a3), then a "jr" using that register. This second case
2205 is almost impossible to distinguish from an indirect jump
2206 used for switch statements, so we don't even try. */
2207 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2209 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2213 /* This fencepost looks highly suspicious to me. Removing it also
2214 seems suspicious as it could affect remote debugging across serial
2218 heuristic_proc_start (CORE_ADDR pc
)
2225 pc
= ADDR_BITS_REMOVE (pc
);
2227 fence
= start_pc
- heuristic_fence_post
;
2231 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2232 fence
= VM_MIN_ADDRESS
;
2234 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2236 /* search back for previous return */
2237 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2238 if (start_pc
< fence
)
2240 /* It's not clear to me why we reach this point when
2241 stop_soon, but with this test, at least we
2242 don't print out warnings for every child forked (eg, on
2243 decstation). 22apr93 rich@cygnus.com. */
2244 if (stop_soon
== NO_STOP_QUIETLY
)
2246 static int blurb_printed
= 0;
2248 warning ("GDB can't find the start of the function at 0x%s.",
2253 /* This actually happens frequently in embedded
2254 development, when you first connect to a board
2255 and your stack pointer and pc are nowhere in
2256 particular. This message needs to give people
2257 in that situation enough information to
2258 determine that it's no big deal. */
2259 printf_filtered ("\n\
2260 GDB is unable to find the start of the function at 0x%s\n\
2261 and thus can't determine the size of that function's stack frame.\n\
2262 This means that GDB may be unable to access that stack frame, or\n\
2263 the frames below it.\n\
2264 This problem is most likely caused by an invalid program counter or\n\
2266 However, if you think GDB should simply search farther back\n\
2267 from 0x%s for code which looks like the beginning of a\n\
2268 function, you can increase the range of the search using the `set\n\
2269 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2276 else if (mips_pc_is_mips16 (start_pc
))
2278 unsigned short inst
;
2280 /* On MIPS16, any one of the following is likely to be the
2281 start of a function:
2285 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2286 inst
= mips_fetch_instruction (start_pc
);
2287 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2288 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2289 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2290 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2292 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2293 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2298 else if (mips_about_to_return (start_pc
))
2300 /* Skip return and its delay slot. */
2301 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2308 struct mips_objfile_private
2314 /* According to the current ABI, should the type be passed in a
2315 floating-point register (assuming that there is space)? When there
2316 is no FPU, FP are not even considered as possibile candidates for
2317 FP registers and, consequently this returns false - forces FP
2318 arguments into integer registers. */
2321 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2323 return ((typecode
== TYPE_CODE_FLT
2325 && (typecode
== TYPE_CODE_STRUCT
2326 || typecode
== TYPE_CODE_UNION
)
2327 && TYPE_NFIELDS (arg_type
) == 1
2328 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2329 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2332 /* On o32, argument passing in GPRs depends on the alignment of the type being
2333 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2336 mips_type_needs_double_align (struct type
*type
)
2338 enum type_code typecode
= TYPE_CODE (type
);
2340 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2342 else if (typecode
== TYPE_CODE_STRUCT
)
2344 if (TYPE_NFIELDS (type
) < 1)
2346 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2348 else if (typecode
== TYPE_CODE_UNION
)
2352 n
= TYPE_NFIELDS (type
);
2353 for (i
= 0; i
< n
; i
++)
2354 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2361 /* Adjust the address downward (direction of stack growth) so that it
2362 is correctly aligned for a new stack frame. */
2364 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2366 return align_down (addr
, 16);
2370 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2371 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2372 int nargs
, struct value
**args
, CORE_ADDR sp
,
2373 int struct_return
, CORE_ADDR struct_addr
)
2379 int stack_offset
= 0;
2380 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2381 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2383 /* For shared libraries, "t9" needs to point at the function
2385 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2387 /* Set the return address register to point to the entry point of
2388 the program, where a breakpoint lies in wait. */
2389 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2391 /* First ensure that the stack and structure return address (if any)
2392 are properly aligned. The stack has to be at least 64-bit
2393 aligned even on 32-bit machines, because doubles must be 64-bit
2394 aligned. For n32 and n64, stack frames need to be 128-bit
2395 aligned, so we round to this widest known alignment. */
2397 sp
= align_down (sp
, 16);
2398 struct_addr
= align_down (struct_addr
, 16);
2400 /* Now make space on the stack for the args. We allocate more
2401 than necessary for EABI, because the first few arguments are
2402 passed in registers, but that's OK. */
2403 for (argnum
= 0; argnum
< nargs
; argnum
++)
2404 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2405 mips_stack_argsize (gdbarch
));
2406 sp
-= align_up (len
, 16);
2409 fprintf_unfiltered (gdb_stdlog
,
2410 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2411 paddr_nz (sp
), (long) align_up (len
, 16));
2413 /* Initialize the integer and float register pointers. */
2414 argreg
= MIPS_A0_REGNUM
;
2415 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2417 /* The struct_return pointer occupies the first parameter-passing reg. */
2421 fprintf_unfiltered (gdb_stdlog
,
2422 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2423 argreg
, paddr_nz (struct_addr
));
2424 write_register (argreg
++, struct_addr
);
2427 /* Now load as many as possible of the first arguments into
2428 registers, and push the rest onto the stack. Loop thru args
2429 from first to last. */
2430 for (argnum
= 0; argnum
< nargs
; argnum
++)
2433 char valbuf
[MAX_REGISTER_SIZE
];
2434 struct value
*arg
= args
[argnum
];
2435 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2436 int len
= TYPE_LENGTH (arg_type
);
2437 enum type_code typecode
= TYPE_CODE (arg_type
);
2440 fprintf_unfiltered (gdb_stdlog
,
2441 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2442 argnum
+ 1, len
, (int) typecode
);
2444 /* The EABI passes structures that do not fit in a register by
2446 if (len
> mips_abi_regsize (gdbarch
)
2447 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2449 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
2450 VALUE_ADDRESS (arg
));
2451 typecode
= TYPE_CODE_PTR
;
2452 len
= mips_abi_regsize (gdbarch
);
2455 fprintf_unfiltered (gdb_stdlog
, " push");
2458 val
= (char *) VALUE_CONTENTS (arg
);
2460 /* 32-bit ABIs always start floating point arguments in an
2461 even-numbered floating point register. Round the FP register
2462 up before the check to see if there are any FP registers
2463 left. Non MIPS_EABI targets also pass the FP in the integer
2464 registers so also round up normal registers. */
2465 if (mips_abi_regsize (gdbarch
) < 8
2466 && fp_register_arg_p (typecode
, arg_type
))
2468 if ((float_argreg
& 1))
2472 /* Floating point arguments passed in registers have to be
2473 treated specially. On 32-bit architectures, doubles
2474 are passed in register pairs; the even register gets
2475 the low word, and the odd register gets the high word.
2476 On non-EABI processors, the first two floating point arguments are
2477 also copied to general registers, because MIPS16 functions
2478 don't use float registers for arguments. This duplication of
2479 arguments in general registers can't hurt non-MIPS16 functions
2480 because those registers are normally skipped. */
2481 /* MIPS_EABI squeezes a struct that contains a single floating
2482 point value into an FP register instead of pushing it onto the
2484 if (fp_register_arg_p (typecode
, arg_type
)
2485 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2487 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
2489 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2490 unsigned long regval
;
2492 /* Write the low word of the double to the even register(s). */
2493 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2495 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2496 float_argreg
, phex (regval
, 4));
2497 write_register (float_argreg
++, regval
);
2499 /* Write the high word of the double to the odd register(s). */
2500 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2502 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2503 float_argreg
, phex (regval
, 4));
2504 write_register (float_argreg
++, regval
);
2508 /* This is a floating point value that fits entirely
2509 in a single register. */
2510 /* On 32 bit ABI's the float_argreg is further adjusted
2511 above to ensure that it is even register aligned. */
2512 LONGEST regval
= extract_unsigned_integer (val
, len
);
2514 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2515 float_argreg
, phex (regval
, len
));
2516 write_register (float_argreg
++, regval
);
2521 /* Copy the argument to general registers or the stack in
2522 register-sized pieces. Large arguments are split between
2523 registers and stack. */
2524 /* Note: structs whose size is not a multiple of
2525 mips_abi_regsize() are treated specially: Irix cc passes
2526 them in registers where gcc sometimes puts them on the
2527 stack. For maximum compatibility, we will put them in
2529 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
2530 && (len
% mips_abi_regsize (gdbarch
) != 0));
2532 /* Note: Floating-point values that didn't fit into an FP
2533 register are only written to memory. */
2536 /* Remember if the argument was written to the stack. */
2537 int stack_used_p
= 0;
2538 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
2539 ? len
: mips_abi_regsize (gdbarch
));
2542 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2545 /* Write this portion of the argument to the stack. */
2546 if (argreg
> MIPS_LAST_ARG_REGNUM
2548 || fp_register_arg_p (typecode
, arg_type
))
2550 /* Should shorter than int integer values be
2551 promoted to int before being stored? */
2552 int longword_offset
= 0;
2555 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2557 if (mips_stack_argsize (gdbarch
) == 8
2558 && (typecode
== TYPE_CODE_INT
2559 || typecode
== TYPE_CODE_PTR
2560 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2561 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2562 else if ((typecode
== TYPE_CODE_STRUCT
2563 || typecode
== TYPE_CODE_UNION
)
2564 && (TYPE_LENGTH (arg_type
)
2565 < mips_stack_argsize (gdbarch
)))
2566 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2571 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2572 paddr_nz (stack_offset
));
2573 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2574 paddr_nz (longword_offset
));
2577 addr
= sp
+ stack_offset
+ longword_offset
;
2582 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2584 for (i
= 0; i
< partial_len
; i
++)
2586 fprintf_unfiltered (gdb_stdlog
, "%02x",
2590 write_memory (addr
, val
, partial_len
);
2593 /* Note!!! This is NOT an else clause. Odd sized
2594 structs may go thru BOTH paths. Floating point
2595 arguments will not. */
2596 /* Write this portion of the argument to a general
2597 purpose register. */
2598 if (argreg
<= MIPS_LAST_ARG_REGNUM
2599 && !fp_register_arg_p (typecode
, arg_type
))
2602 extract_unsigned_integer (val
, partial_len
);
2605 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2608 mips_abi_regsize (gdbarch
)));
2609 write_register (argreg
, regval
);
2616 /* Compute the the offset into the stack at which we
2617 will copy the next parameter.
2619 In the new EABI (and the NABI32), the stack_offset
2620 only needs to be adjusted when it has been used. */
2623 stack_offset
+= align_up (partial_len
,
2624 mips_stack_argsize (gdbarch
));
2628 fprintf_unfiltered (gdb_stdlog
, "\n");
2631 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2633 /* Return adjusted stack pointer. */
2637 /* Determin the return value convention being used. */
2639 static enum return_value_convention
2640 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2641 struct type
*type
, struct regcache
*regcache
,
2642 void *readbuf
, const void *writebuf
)
2644 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2645 return RETURN_VALUE_STRUCT_CONVENTION
;
2647 memset (readbuf
, 0, TYPE_LENGTH (type
));
2648 return RETURN_VALUE_REGISTER_CONVENTION
;
2652 /* N32/N64 ABI stuff. */
2655 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2656 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2657 int nargs
, struct value
**args
, CORE_ADDR sp
,
2658 int struct_return
, CORE_ADDR struct_addr
)
2664 int stack_offset
= 0;
2665 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2666 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2668 /* For shared libraries, "t9" needs to point at the function
2670 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2672 /* Set the return address register to point to the entry point of
2673 the program, where a breakpoint lies in wait. */
2674 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2676 /* First ensure that the stack and structure return address (if any)
2677 are properly aligned. The stack has to be at least 64-bit
2678 aligned even on 32-bit machines, because doubles must be 64-bit
2679 aligned. For n32 and n64, stack frames need to be 128-bit
2680 aligned, so we round to this widest known alignment. */
2682 sp
= align_down (sp
, 16);
2683 struct_addr
= align_down (struct_addr
, 16);
2685 /* Now make space on the stack for the args. */
2686 for (argnum
= 0; argnum
< nargs
; argnum
++)
2687 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2688 mips_stack_argsize (gdbarch
));
2689 sp
-= align_up (len
, 16);
2692 fprintf_unfiltered (gdb_stdlog
,
2693 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2694 paddr_nz (sp
), (long) align_up (len
, 16));
2696 /* Initialize the integer and float register pointers. */
2697 argreg
= MIPS_A0_REGNUM
;
2698 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2700 /* The struct_return pointer occupies the first parameter-passing reg. */
2704 fprintf_unfiltered (gdb_stdlog
,
2705 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2706 argreg
, paddr_nz (struct_addr
));
2707 write_register (argreg
++, struct_addr
);
2710 /* Now load as many as possible of the first arguments into
2711 registers, and push the rest onto the stack. Loop thru args
2712 from first to last. */
2713 for (argnum
= 0; argnum
< nargs
; argnum
++)
2716 struct value
*arg
= args
[argnum
];
2717 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2718 int len
= TYPE_LENGTH (arg_type
);
2719 enum type_code typecode
= TYPE_CODE (arg_type
);
2722 fprintf_unfiltered (gdb_stdlog
,
2723 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2724 argnum
+ 1, len
, (int) typecode
);
2726 val
= (char *) VALUE_CONTENTS (arg
);
2728 if (fp_register_arg_p (typecode
, arg_type
)
2729 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2731 /* This is a floating point value that fits entirely
2732 in a single register. */
2733 /* On 32 bit ABI's the float_argreg is further adjusted
2734 above to ensure that it is even register aligned. */
2735 LONGEST regval
= extract_unsigned_integer (val
, len
);
2737 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2738 float_argreg
, phex (regval
, len
));
2739 write_register (float_argreg
++, regval
);
2742 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2743 argreg
, phex (regval
, len
));
2744 write_register (argreg
, regval
);
2749 /* Copy the argument to general registers or the stack in
2750 register-sized pieces. Large arguments are split between
2751 registers and stack. */
2752 /* Note: structs whose size is not a multiple of
2753 mips_abi_regsize() are treated specially: Irix cc passes
2754 them in registers where gcc sometimes puts them on the
2755 stack. For maximum compatibility, we will put them in
2757 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
2758 && (len
% mips_abi_regsize (gdbarch
) != 0));
2759 /* Note: Floating-point values that didn't fit into an FP
2760 register are only written to memory. */
2763 /* Rememer if the argument was written to the stack. */
2764 int stack_used_p
= 0;
2765 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
2766 ? len
: mips_abi_regsize (gdbarch
));
2769 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2772 /* Write this portion of the argument to the stack. */
2773 if (argreg
> MIPS_LAST_ARG_REGNUM
2775 || fp_register_arg_p (typecode
, arg_type
))
2777 /* Should shorter than int integer values be
2778 promoted to int before being stored? */
2779 int longword_offset
= 0;
2782 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2784 if (mips_stack_argsize (gdbarch
) == 8
2785 && (typecode
== TYPE_CODE_INT
2786 || typecode
== TYPE_CODE_PTR
2787 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2788 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2793 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2794 paddr_nz (stack_offset
));
2795 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2796 paddr_nz (longword_offset
));
2799 addr
= sp
+ stack_offset
+ longword_offset
;
2804 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2806 for (i
= 0; i
< partial_len
; i
++)
2808 fprintf_unfiltered (gdb_stdlog
, "%02x",
2812 write_memory (addr
, val
, partial_len
);
2815 /* Note!!! This is NOT an else clause. Odd sized
2816 structs may go thru BOTH paths. Floating point
2817 arguments will not. */
2818 /* Write this portion of the argument to a general
2819 purpose register. */
2820 if (argreg
<= MIPS_LAST_ARG_REGNUM
2821 && !fp_register_arg_p (typecode
, arg_type
))
2824 extract_unsigned_integer (val
, partial_len
);
2826 /* A non-floating-point argument being passed in a
2827 general register. If a struct or union, and if
2828 the remaining length is smaller than the register
2829 size, we have to adjust the register value on
2832 It does not seem to be necessary to do the
2833 same for integral types.
2835 cagney/2001-07-23: gdb/179: Also, GCC, when
2836 outputting LE O32 with sizeof (struct) <
2837 mips_abi_regsize(), generates a left shift as
2838 part of storing the argument in a register a
2839 register (the left shift isn't generated when
2840 sizeof (struct) >= mips_abi_regsize()). Since
2841 it is quite possible that this is GCC
2842 contradicting the LE/O32 ABI, GDB has not been
2843 adjusted to accommodate this. Either someone
2844 needs to demonstrate that the LE/O32 ABI
2845 specifies such a left shift OR this new ABI gets
2846 identified as such and GDB gets tweaked
2849 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2850 && partial_len
< mips_abi_regsize (gdbarch
)
2851 && (typecode
== TYPE_CODE_STRUCT
||
2852 typecode
== TYPE_CODE_UNION
))
2853 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
2857 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2860 mips_abi_regsize (gdbarch
)));
2861 write_register (argreg
, regval
);
2868 /* Compute the the offset into the stack at which we
2869 will copy the next parameter.
2871 In N32 (N64?), the stack_offset only needs to be
2872 adjusted when it has been used. */
2875 stack_offset
+= align_up (partial_len
,
2876 mips_stack_argsize (gdbarch
));
2880 fprintf_unfiltered (gdb_stdlog
, "\n");
2883 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2885 /* Return adjusted stack pointer. */
2889 static enum return_value_convention
2890 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
2891 struct type
*type
, struct regcache
*regcache
,
2892 void *readbuf
, const void *writebuf
)
2894 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2895 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2896 || TYPE_CODE (type
) == TYPE_CODE_UNION
2897 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
2898 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2899 return RETURN_VALUE_STRUCT_CONVENTION
;
2900 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2901 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2903 /* A floating-point value belongs in the least significant part
2906 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
2907 mips_xfer_register (regcache
,
2908 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
2910 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
2911 return RETURN_VALUE_REGISTER_CONVENTION
;
2913 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2914 && TYPE_NFIELDS (type
) <= 2
2915 && TYPE_NFIELDS (type
) >= 1
2916 && ((TYPE_NFIELDS (type
) == 1
2917 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2919 || (TYPE_NFIELDS (type
) == 2
2920 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2922 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
2924 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2926 /* A struct that contains one or two floats. Each value is part
2927 in the least significant part of their floating point
2931 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
2932 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
2934 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
2937 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
2939 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
2940 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
2941 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
2943 return RETURN_VALUE_REGISTER_CONVENTION
;
2945 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2946 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2948 /* A structure or union. Extract the left justified value,
2949 regardless of the byte order. I.e. DO NOT USE
2953 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
2954 offset
< TYPE_LENGTH (type
);
2955 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
2957 int xfer
= register_size (current_gdbarch
, regnum
);
2958 if (offset
+ xfer
> TYPE_LENGTH (type
))
2959 xfer
= TYPE_LENGTH (type
) - offset
;
2961 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
2962 offset
, xfer
, regnum
);
2963 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
2964 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
2966 return RETURN_VALUE_REGISTER_CONVENTION
;
2970 /* A scalar extract each part but least-significant-byte
2974 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
2975 offset
< TYPE_LENGTH (type
);
2976 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
2978 int xfer
= register_size (current_gdbarch
, regnum
);
2979 if (offset
+ xfer
> TYPE_LENGTH (type
))
2980 xfer
= TYPE_LENGTH (type
) - offset
;
2982 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
2983 offset
, xfer
, regnum
);
2984 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
2985 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
2987 return RETURN_VALUE_REGISTER_CONVENTION
;
2991 /* O32 ABI stuff. */
2994 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2995 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2996 int nargs
, struct value
**args
, CORE_ADDR sp
,
2997 int struct_return
, CORE_ADDR struct_addr
)
3003 int stack_offset
= 0;
3004 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3005 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3007 /* For shared libraries, "t9" needs to point at the function
3009 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3011 /* Set the return address register to point to the entry point of
3012 the program, where a breakpoint lies in wait. */
3013 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3015 /* First ensure that the stack and structure return address (if any)
3016 are properly aligned. The stack has to be at least 64-bit
3017 aligned even on 32-bit machines, because doubles must be 64-bit
3018 aligned. For n32 and n64, stack frames need to be 128-bit
3019 aligned, so we round to this widest known alignment. */
3021 sp
= align_down (sp
, 16);
3022 struct_addr
= align_down (struct_addr
, 16);
3024 /* Now make space on the stack for the args. */
3025 for (argnum
= 0; argnum
< nargs
; argnum
++)
3026 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3027 mips_stack_argsize (gdbarch
));
3028 sp
-= align_up (len
, 16);
3031 fprintf_unfiltered (gdb_stdlog
,
3032 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3033 paddr_nz (sp
), (long) align_up (len
, 16));
3035 /* Initialize the integer and float register pointers. */
3036 argreg
= MIPS_A0_REGNUM
;
3037 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3039 /* The struct_return pointer occupies the first parameter-passing reg. */
3043 fprintf_unfiltered (gdb_stdlog
,
3044 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3045 argreg
, paddr_nz (struct_addr
));
3046 write_register (argreg
++, struct_addr
);
3047 stack_offset
+= mips_stack_argsize (gdbarch
);
3050 /* Now load as many as possible of the first arguments into
3051 registers, and push the rest onto the stack. Loop thru args
3052 from first to last. */
3053 for (argnum
= 0; argnum
< nargs
; argnum
++)
3056 struct value
*arg
= args
[argnum
];
3057 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3058 int len
= TYPE_LENGTH (arg_type
);
3059 enum type_code typecode
= TYPE_CODE (arg_type
);
3062 fprintf_unfiltered (gdb_stdlog
,
3063 "mips_o32_push_dummy_call: %d len=%d type=%d",
3064 argnum
+ 1, len
, (int) typecode
);
3066 val
= (char *) VALUE_CONTENTS (arg
);
3068 /* 32-bit ABIs always start floating point arguments in an
3069 even-numbered floating point register. Round the FP register
3070 up before the check to see if there are any FP registers
3071 left. O32/O64 targets also pass the FP in the integer
3072 registers so also round up normal registers. */
3073 if (mips_abi_regsize (gdbarch
) < 8
3074 && fp_register_arg_p (typecode
, arg_type
))
3076 if ((float_argreg
& 1))
3080 /* Floating point arguments passed in registers have to be
3081 treated specially. On 32-bit architectures, doubles
3082 are passed in register pairs; the even register gets
3083 the low word, and the odd register gets the high word.
3084 On O32/O64, the first two floating point arguments are
3085 also copied to general registers, because MIPS16 functions
3086 don't use float registers for arguments. This duplication of
3087 arguments in general registers can't hurt non-MIPS16 functions
3088 because those registers are normally skipped. */
3090 if (fp_register_arg_p (typecode
, arg_type
)
3091 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3093 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3095 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3096 unsigned long regval
;
3098 /* Write the low word of the double to the even register(s). */
3099 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3101 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3102 float_argreg
, phex (regval
, 4));
3103 write_register (float_argreg
++, regval
);
3105 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3106 argreg
, phex (regval
, 4));
3107 write_register (argreg
++, regval
);
3109 /* Write the high word of the double to the odd register(s). */
3110 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3112 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3113 float_argreg
, phex (regval
, 4));
3114 write_register (float_argreg
++, regval
);
3117 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3118 argreg
, phex (regval
, 4));
3119 write_register (argreg
++, regval
);
3123 /* This is a floating point value that fits entirely
3124 in a single register. */
3125 /* On 32 bit ABI's the float_argreg is further adjusted
3126 above to ensure that it is even register aligned. */
3127 LONGEST regval
= extract_unsigned_integer (val
, len
);
3129 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3130 float_argreg
, phex (regval
, len
));
3131 write_register (float_argreg
++, regval
);
3132 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3133 registers for each argument. The below is (my
3134 guess) to ensure that the corresponding integer
3135 register has reserved the same space. */
3137 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3138 argreg
, phex (regval
, len
));
3139 write_register (argreg
, regval
);
3140 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3142 /* Reserve space for the FP register. */
3143 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3147 /* Copy the argument to general registers or the stack in
3148 register-sized pieces. Large arguments are split between
3149 registers and stack. */
3150 /* Note: structs whose size is not a multiple of
3151 mips_abi_regsize() are treated specially: Irix cc passes
3152 them in registers where gcc sometimes puts them on the
3153 stack. For maximum compatibility, we will put them in
3155 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3156 && (len
% mips_abi_regsize (gdbarch
) != 0));
3157 /* Structures should be aligned to eight bytes (even arg registers)
3158 on MIPS_ABI_O32, if their first member has double precision. */
3159 if (mips_abi_regsize (gdbarch
) < 8
3160 && mips_type_needs_double_align (arg_type
))
3165 /* Note: Floating-point values that didn't fit into an FP
3166 register are only written to memory. */
3169 /* Remember if the argument was written to the stack. */
3170 int stack_used_p
= 0;
3171 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3172 ? len
: mips_abi_regsize (gdbarch
));
3175 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3178 /* Write this portion of the argument to the stack. */
3179 if (argreg
> MIPS_LAST_ARG_REGNUM
3181 || fp_register_arg_p (typecode
, arg_type
))
3183 /* Should shorter than int integer values be
3184 promoted to int before being stored? */
3185 int longword_offset
= 0;
3188 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3190 if (mips_stack_argsize (gdbarch
) == 8
3191 && (typecode
== TYPE_CODE_INT
3192 || typecode
== TYPE_CODE_PTR
3193 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3194 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3199 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3200 paddr_nz (stack_offset
));
3201 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3202 paddr_nz (longword_offset
));
3205 addr
= sp
+ stack_offset
+ longword_offset
;
3210 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3212 for (i
= 0; i
< partial_len
; i
++)
3214 fprintf_unfiltered (gdb_stdlog
, "%02x",
3218 write_memory (addr
, val
, partial_len
);
3221 /* Note!!! This is NOT an else clause. Odd sized
3222 structs may go thru BOTH paths. Floating point
3223 arguments will not. */
3224 /* Write this portion of the argument to a general
3225 purpose register. */
3226 if (argreg
<= MIPS_LAST_ARG_REGNUM
3227 && !fp_register_arg_p (typecode
, arg_type
))
3229 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3230 /* Value may need to be sign extended, because
3231 mips_isa_regsize() != mips_abi_regsize(). */
3233 /* A non-floating-point argument being passed in a
3234 general register. If a struct or union, and if
3235 the remaining length is smaller than the register
3236 size, we have to adjust the register value on
3239 It does not seem to be necessary to do the
3240 same for integral types.
3242 Also don't do this adjustment on O64 binaries.
3244 cagney/2001-07-23: gdb/179: Also, GCC, when
3245 outputting LE O32 with sizeof (struct) <
3246 mips_abi_regsize(), generates a left shift as
3247 part of storing the argument in a register a
3248 register (the left shift isn't generated when
3249 sizeof (struct) >= mips_abi_regsize()). Since
3250 it is quite possible that this is GCC
3251 contradicting the LE/O32 ABI, GDB has not been
3252 adjusted to accommodate this. Either someone
3253 needs to demonstrate that the LE/O32 ABI
3254 specifies such a left shift OR this new ABI gets
3255 identified as such and GDB gets tweaked
3258 if (mips_abi_regsize (gdbarch
) < 8
3259 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3260 && partial_len
< mips_abi_regsize (gdbarch
)
3261 && (typecode
== TYPE_CODE_STRUCT
||
3262 typecode
== TYPE_CODE_UNION
))
3263 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3267 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3270 mips_abi_regsize (gdbarch
)));
3271 write_register (argreg
, regval
);
3274 /* Prevent subsequent floating point arguments from
3275 being passed in floating point registers. */
3276 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3282 /* Compute the the offset into the stack at which we
3283 will copy the next parameter.
3285 In older ABIs, the caller reserved space for
3286 registers that contained arguments. This was loosely
3287 refered to as their "home". Consequently, space is
3288 always allocated. */
3290 stack_offset
+= align_up (partial_len
,
3291 mips_stack_argsize (gdbarch
));
3295 fprintf_unfiltered (gdb_stdlog
, "\n");
3298 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3300 /* Return adjusted stack pointer. */
3304 static enum return_value_convention
3305 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3306 struct regcache
*regcache
,
3307 void *readbuf
, const void *writebuf
)
3309 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3311 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3312 || TYPE_CODE (type
) == TYPE_CODE_UNION
3313 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3314 return RETURN_VALUE_STRUCT_CONVENTION
;
3315 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3316 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3318 /* A single-precision floating-point value. It fits in the
3319 least significant part of FP0. */
3321 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3322 mips_xfer_register (regcache
,
3323 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3325 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3326 return RETURN_VALUE_REGISTER_CONVENTION
;
3328 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3329 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3331 /* A double-precision floating-point value. The most
3332 significant part goes in FP1, and the least significant in
3335 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3336 switch (TARGET_BYTE_ORDER
)
3338 case BFD_ENDIAN_LITTLE
:
3339 mips_xfer_register (regcache
,
3340 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3341 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3342 mips_xfer_register (regcache
,
3343 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3344 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3346 case BFD_ENDIAN_BIG
:
3347 mips_xfer_register (regcache
,
3348 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3349 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3350 mips_xfer_register (regcache
,
3351 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3352 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3355 internal_error (__FILE__
, __LINE__
, "bad switch");
3357 return RETURN_VALUE_REGISTER_CONVENTION
;
3360 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3361 && TYPE_NFIELDS (type
) <= 2
3362 && TYPE_NFIELDS (type
) >= 1
3363 && ((TYPE_NFIELDS (type
) == 1
3364 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3366 || (TYPE_NFIELDS (type
) == 2
3367 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3369 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3371 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3373 /* A struct that contains one or two floats. Each value is part
3374 in the least significant part of their floating point
3376 bfd_byte reg
[MAX_REGISTER_SIZE
];
3379 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3380 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3382 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3385 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3387 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3388 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3389 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3391 return RETURN_VALUE_REGISTER_CONVENTION
;
3395 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3396 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3398 /* A structure or union. Extract the left justified value,
3399 regardless of the byte order. I.e. DO NOT USE
3403 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3404 offset
< TYPE_LENGTH (type
);
3405 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3407 int xfer
= register_size (current_gdbarch
, regnum
);
3408 if (offset
+ xfer
> TYPE_LENGTH (type
))
3409 xfer
= TYPE_LENGTH (type
) - offset
;
3411 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3412 offset
, xfer
, regnum
);
3413 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3414 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3416 return RETURN_VALUE_REGISTER_CONVENTION
;
3421 /* A scalar extract each part but least-significant-byte
3422 justified. o32 thinks registers are 4 byte, regardless of
3423 the ISA. mips_stack_argsize controls this. */
3426 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3427 offset
< TYPE_LENGTH (type
);
3428 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
3430 int xfer
= mips_stack_argsize (gdbarch
);
3431 if (offset
+ xfer
> TYPE_LENGTH (type
))
3432 xfer
= TYPE_LENGTH (type
) - offset
;
3434 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3435 offset
, xfer
, regnum
);
3436 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3437 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3439 return RETURN_VALUE_REGISTER_CONVENTION
;
3443 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3447 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3448 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3450 struct value
**args
, CORE_ADDR sp
,
3451 int struct_return
, CORE_ADDR struct_addr
)
3457 int stack_offset
= 0;
3458 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3459 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3461 /* For shared libraries, "t9" needs to point at the function
3463 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3465 /* Set the return address register to point to the entry point of
3466 the program, where a breakpoint lies in wait. */
3467 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3469 /* First ensure that the stack and structure return address (if any)
3470 are properly aligned. The stack has to be at least 64-bit
3471 aligned even on 32-bit machines, because doubles must be 64-bit
3472 aligned. For n32 and n64, stack frames need to be 128-bit
3473 aligned, so we round to this widest known alignment. */
3475 sp
= align_down (sp
, 16);
3476 struct_addr
= align_down (struct_addr
, 16);
3478 /* Now make space on the stack for the args. */
3479 for (argnum
= 0; argnum
< nargs
; argnum
++)
3480 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3481 mips_stack_argsize (gdbarch
));
3482 sp
-= align_up (len
, 16);
3485 fprintf_unfiltered (gdb_stdlog
,
3486 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3487 paddr_nz (sp
), (long) align_up (len
, 16));
3489 /* Initialize the integer and float register pointers. */
3490 argreg
= MIPS_A0_REGNUM
;
3491 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3493 /* The struct_return pointer occupies the first parameter-passing reg. */
3497 fprintf_unfiltered (gdb_stdlog
,
3498 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3499 argreg
, paddr_nz (struct_addr
));
3500 write_register (argreg
++, struct_addr
);
3501 stack_offset
+= mips_stack_argsize (gdbarch
);
3504 /* Now load as many as possible of the first arguments into
3505 registers, and push the rest onto the stack. Loop thru args
3506 from first to last. */
3507 for (argnum
= 0; argnum
< nargs
; argnum
++)
3510 struct value
*arg
= args
[argnum
];
3511 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3512 int len
= TYPE_LENGTH (arg_type
);
3513 enum type_code typecode
= TYPE_CODE (arg_type
);
3516 fprintf_unfiltered (gdb_stdlog
,
3517 "mips_o64_push_dummy_call: %d len=%d type=%d",
3518 argnum
+ 1, len
, (int) typecode
);
3520 val
= (char *) VALUE_CONTENTS (arg
);
3522 /* 32-bit ABIs always start floating point arguments in an
3523 even-numbered floating point register. Round the FP register
3524 up before the check to see if there are any FP registers
3525 left. O32/O64 targets also pass the FP in the integer
3526 registers so also round up normal registers. */
3527 if (mips_abi_regsize (gdbarch
) < 8
3528 && fp_register_arg_p (typecode
, arg_type
))
3530 if ((float_argreg
& 1))
3534 /* Floating point arguments passed in registers have to be
3535 treated specially. On 32-bit architectures, doubles
3536 are passed in register pairs; the even register gets
3537 the low word, and the odd register gets the high word.
3538 On O32/O64, the first two floating point arguments are
3539 also copied to general registers, because MIPS16 functions
3540 don't use float registers for arguments. This duplication of
3541 arguments in general registers can't hurt non-MIPS16 functions
3542 because those registers are normally skipped. */
3544 if (fp_register_arg_p (typecode
, arg_type
)
3545 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3547 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3549 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3550 unsigned long regval
;
3552 /* Write the low word of the double to the even register(s). */
3553 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3555 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3556 float_argreg
, phex (regval
, 4));
3557 write_register (float_argreg
++, regval
);
3559 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3560 argreg
, phex (regval
, 4));
3561 write_register (argreg
++, regval
);
3563 /* Write the high word of the double to the odd register(s). */
3564 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3566 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3567 float_argreg
, phex (regval
, 4));
3568 write_register (float_argreg
++, regval
);
3571 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3572 argreg
, phex (regval
, 4));
3573 write_register (argreg
++, regval
);
3577 /* This is a floating point value that fits entirely
3578 in a single register. */
3579 /* On 32 bit ABI's the float_argreg is further adjusted
3580 above to ensure that it is even register aligned. */
3581 LONGEST regval
= extract_unsigned_integer (val
, len
);
3583 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3584 float_argreg
, phex (regval
, len
));
3585 write_register (float_argreg
++, regval
);
3586 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3587 registers for each argument. The below is (my
3588 guess) to ensure that the corresponding integer
3589 register has reserved the same space. */
3591 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3592 argreg
, phex (regval
, len
));
3593 write_register (argreg
, regval
);
3594 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3596 /* Reserve space for the FP register. */
3597 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3601 /* Copy the argument to general registers or the stack in
3602 register-sized pieces. Large arguments are split between
3603 registers and stack. */
3604 /* Note: structs whose size is not a multiple of
3605 mips_abi_regsize() are treated specially: Irix cc passes
3606 them in registers where gcc sometimes puts them on the
3607 stack. For maximum compatibility, we will put them in
3609 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3610 && (len
% mips_abi_regsize (gdbarch
) != 0));
3611 /* Structures should be aligned to eight bytes (even arg registers)
3612 on MIPS_ABI_O32, if their first member has double precision. */
3613 if (mips_abi_regsize (gdbarch
) < 8
3614 && mips_type_needs_double_align (arg_type
))
3619 /* Note: Floating-point values that didn't fit into an FP
3620 register are only written to memory. */
3623 /* Remember if the argument was written to the stack. */
3624 int stack_used_p
= 0;
3625 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3626 ? len
: mips_abi_regsize (gdbarch
));
3629 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3632 /* Write this portion of the argument to the stack. */
3633 if (argreg
> MIPS_LAST_ARG_REGNUM
3635 || fp_register_arg_p (typecode
, arg_type
))
3637 /* Should shorter than int integer values be
3638 promoted to int before being stored? */
3639 int longword_offset
= 0;
3642 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3644 if (mips_stack_argsize (gdbarch
) == 8
3645 && (typecode
== TYPE_CODE_INT
3646 || typecode
== TYPE_CODE_PTR
3647 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3648 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3653 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3654 paddr_nz (stack_offset
));
3655 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3656 paddr_nz (longword_offset
));
3659 addr
= sp
+ stack_offset
+ longword_offset
;
3664 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3666 for (i
= 0; i
< partial_len
; i
++)
3668 fprintf_unfiltered (gdb_stdlog
, "%02x",
3672 write_memory (addr
, val
, partial_len
);
3675 /* Note!!! This is NOT an else clause. Odd sized
3676 structs may go thru BOTH paths. Floating point
3677 arguments will not. */
3678 /* Write this portion of the argument to a general
3679 purpose register. */
3680 if (argreg
<= MIPS_LAST_ARG_REGNUM
3681 && !fp_register_arg_p (typecode
, arg_type
))
3683 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3684 /* Value may need to be sign extended, because
3685 mips_isa_regsize() != mips_abi_regsize(). */
3687 /* A non-floating-point argument being passed in a
3688 general register. If a struct or union, and if
3689 the remaining length is smaller than the register
3690 size, we have to adjust the register value on
3693 It does not seem to be necessary to do the
3694 same for integral types.
3696 Also don't do this adjustment on O64 binaries.
3698 cagney/2001-07-23: gdb/179: Also, GCC, when
3699 outputting LE O32 with sizeof (struct) <
3700 mips_abi_regsize(), generates a left shift as
3701 part of storing the argument in a register a
3702 register (the left shift isn't generated when
3703 sizeof (struct) >= mips_abi_regsize()). Since
3704 it is quite possible that this is GCC
3705 contradicting the LE/O32 ABI, GDB has not been
3706 adjusted to accommodate this. Either someone
3707 needs to demonstrate that the LE/O32 ABI
3708 specifies such a left shift OR this new ABI gets
3709 identified as such and GDB gets tweaked
3712 if (mips_abi_regsize (gdbarch
) < 8
3713 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3714 && partial_len
< mips_abi_regsize (gdbarch
)
3715 && (typecode
== TYPE_CODE_STRUCT
||
3716 typecode
== TYPE_CODE_UNION
))
3717 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3721 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3724 mips_abi_regsize (gdbarch
)));
3725 write_register (argreg
, regval
);
3728 /* Prevent subsequent floating point arguments from
3729 being passed in floating point registers. */
3730 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3736 /* Compute the the offset into the stack at which we
3737 will copy the next parameter.
3739 In older ABIs, the caller reserved space for
3740 registers that contained arguments. This was loosely
3741 refered to as their "home". Consequently, space is
3742 always allocated. */
3744 stack_offset
+= align_up (partial_len
,
3745 mips_stack_argsize (gdbarch
));
3749 fprintf_unfiltered (gdb_stdlog
, "\n");
3752 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3754 /* Return adjusted stack pointer. */
3758 static enum return_value_convention
3759 mips_o64_return_value (struct gdbarch
*gdbarch
,
3760 struct type
*type
, struct regcache
*regcache
,
3761 void *readbuf
, const void *writebuf
)
3763 return RETURN_VALUE_STRUCT_CONVENTION
;
3766 /* Floating point register management.
3768 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3769 64bit operations, these early MIPS cpus treat fp register pairs
3770 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3771 registers and offer a compatibility mode that emulates the MIPS2 fp
3772 model. When operating in MIPS2 fp compat mode, later cpu's split
3773 double precision floats into two 32-bit chunks and store them in
3774 consecutive fp regs. To display 64-bit floats stored in this
3775 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3776 Throw in user-configurable endianness and you have a real mess.
3778 The way this works is:
3779 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3780 double-precision value will be split across two logical registers.
3781 The lower-numbered logical register will hold the low-order bits,
3782 regardless of the processor's endianness.
3783 - If we are on a 64-bit processor, and we are looking for a
3784 single-precision value, it will be in the low ordered bits
3785 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3786 save slot in memory.
3787 - If we are in 64-bit mode, everything is straightforward.
3789 Note that this code only deals with "live" registers at the top of the
3790 stack. We will attempt to deal with saved registers later, when
3791 the raw/cooked register interface is in place. (We need a general
3792 interface that can deal with dynamic saved register sizes -- fp
3793 regs could be 32 bits wide in one frame and 64 on the frame above
3796 static struct type
*
3797 mips_float_register_type (void)
3799 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3800 return builtin_type_ieee_single_big
;
3802 return builtin_type_ieee_single_little
;
3805 static struct type
*
3806 mips_double_register_type (void)
3808 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3809 return builtin_type_ieee_double_big
;
3811 return builtin_type_ieee_double_little
;
3814 /* Copy a 32-bit single-precision value from the current frame
3815 into rare_buffer. */
3818 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3821 int raw_size
= register_size (current_gdbarch
, regno
);
3822 char *raw_buffer
= alloca (raw_size
);
3824 if (!frame_register_read (frame
, regno
, raw_buffer
))
3825 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3828 /* We have a 64-bit value for this register. Find the low-order
3832 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3837 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3841 memcpy (rare_buffer
, raw_buffer
, 4);
3845 /* Copy a 64-bit double-precision value from the current frame into
3846 rare_buffer. This may include getting half of it from the next
3850 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
3853 int raw_size
= register_size (current_gdbarch
, regno
);
3855 if (raw_size
== 8 && !mips2_fp_compat ())
3857 /* We have a 64-bit value for this register, and we should use
3859 if (!frame_register_read (frame
, regno
, rare_buffer
))
3860 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3864 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
3865 internal_error (__FILE__
, __LINE__
,
3866 "mips_read_fp_register_double: bad access to "
3867 "odd-numbered FP register");
3869 /* mips_read_fp_register_single will find the correct 32 bits from
3871 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3873 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
3874 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
3878 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
3879 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
3885 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
3887 { /* do values for FP (float) regs */
3889 double doub
, flt1
; /* doubles extracted from raw hex data */
3893 (char *) alloca (2 *
3894 register_size (current_gdbarch
,
3895 mips_regnum (current_gdbarch
)->fp0
));
3897 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
3898 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
3901 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
3903 /* 4-byte registers: Print hex and floating. Also print even
3904 numbered registers as doubles. */
3905 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3906 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3908 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
3911 fprintf_filtered (file
, " flt: ");
3913 fprintf_filtered (file
, " <invalid float> ");
3915 fprintf_filtered (file
, "%-17.9g", flt1
);
3917 if (regnum
% 2 == 0)
3919 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3920 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
3923 fprintf_filtered (file
, " dbl: ");
3925 fprintf_filtered (file
, "<invalid double>");
3927 fprintf_filtered (file
, "%-24.17g", doub
);
3932 /* Eight byte registers: print each one as hex, float and double. */
3933 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3934 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3936 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3937 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
3940 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
3943 fprintf_filtered (file
, " flt: ");
3945 fprintf_filtered (file
, "<invalid float>");
3947 fprintf_filtered (file
, "%-17.9g", flt1
);
3949 fprintf_filtered (file
, " dbl: ");
3951 fprintf_filtered (file
, "<invalid double>");
3953 fprintf_filtered (file
, "%-24.17g", doub
);
3958 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
3959 int regnum
, int all
)
3961 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3962 char raw_buffer
[MAX_REGISTER_SIZE
];
3965 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
3967 mips_print_fp_register (file
, frame
, regnum
);
3971 /* Get the data in raw format. */
3972 if (!frame_register_read (frame
, regnum
, raw_buffer
))
3974 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
3978 fputs_filtered (REGISTER_NAME (regnum
), file
);
3980 /* The problem with printing numeric register names (r26, etc.) is that
3981 the user can't use them on input. Probably the best solution is to
3982 fix it so that either the numeric or the funky (a2, etc.) names
3983 are accepted on input. */
3984 if (regnum
< MIPS_NUMREGS
)
3985 fprintf_filtered (file
, "(r%d): ", regnum
);
3987 fprintf_filtered (file
, ": ");
3989 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3991 register_size (current_gdbarch
,
3992 regnum
) - register_size (current_gdbarch
, regnum
);
3996 print_scalar_formatted (raw_buffer
+ offset
,
3997 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4001 /* Replacement for generic do_registers_info.
4002 Print regs in pretty columns. */
4005 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4008 fprintf_filtered (file
, " ");
4009 mips_print_fp_register (file
, frame
, regnum
);
4010 fprintf_filtered (file
, "\n");
4015 /* Print a row's worth of GP (int) registers, with name labels above */
4018 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4021 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4022 /* do values for GP (int) regs */
4023 char raw_buffer
[MAX_REGISTER_SIZE
];
4024 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4028 /* For GP registers, we print a separate row of names above the vals */
4029 fprintf_filtered (file
, " ");
4030 for (col
= 0, regnum
= start_regnum
;
4031 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4033 if (*REGISTER_NAME (regnum
) == '\0')
4034 continue; /* unused register */
4035 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4037 break; /* end the row: reached FP register */
4038 fprintf_filtered (file
,
4039 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4040 REGISTER_NAME (regnum
));
4043 /* print the R0 to R31 names */
4044 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4045 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4047 fprintf_filtered (file
, "\n ");
4049 /* now print the values in hex, 4 or 8 to the row */
4050 for (col
= 0, regnum
= start_regnum
;
4051 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4053 if (*REGISTER_NAME (regnum
) == '\0')
4054 continue; /* unused register */
4055 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4057 break; /* end row: reached FP register */
4058 /* OK: get the data in raw format. */
4059 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4060 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4061 /* pad small registers */
4063 byte
< (mips_abi_regsize (current_gdbarch
)
4064 - register_size (current_gdbarch
, regnum
)); byte
++)
4065 printf_filtered (" ");
4066 /* Now print the register value in hex, endian order. */
4067 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4069 register_size (current_gdbarch
,
4070 regnum
) - register_size (current_gdbarch
, regnum
);
4071 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4072 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4074 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4076 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4077 fprintf_filtered (file
, " ");
4080 if (col
> 0) /* ie. if we actually printed anything... */
4081 fprintf_filtered (file
, "\n");
4086 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4089 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4090 struct frame_info
*frame
, int regnum
, int all
)
4092 if (regnum
!= -1) /* do one specified register */
4094 gdb_assert (regnum
>= NUM_REGS
);
4095 if (*(REGISTER_NAME (regnum
)) == '\0')
4096 error ("Not a valid register for the current processor type");
4098 mips_print_register (file
, frame
, regnum
, 0);
4099 fprintf_filtered (file
, "\n");
4102 /* do all (or most) registers */
4105 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4107 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4110 if (all
) /* true for "INFO ALL-REGISTERS" command */
4111 regnum
= print_fp_register_row (file
, frame
, regnum
);
4113 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4116 regnum
= print_gp_register_row (file
, frame
, regnum
);
4121 /* Is this a branch with a delay slot? */
4124 is_delayed (unsigned long insn
)
4127 for (i
= 0; i
< NUMOPCODES
; ++i
)
4128 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4129 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4131 return (i
< NUMOPCODES
4132 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4133 | INSN_COND_BRANCH_DELAY
4134 | INSN_COND_BRANCH_LIKELY
)));
4138 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4139 struct frame_info
*frame
)
4141 CORE_ADDR pc
= get_frame_pc (frame
);
4142 char buf
[MIPS_INSN32_SIZE
];
4144 /* There is no branch delay slot on MIPS16. */
4145 if (mips_pc_is_mips16 (pc
))
4148 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4149 /* If error reading memory, guess that it is not a delayed
4152 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4155 /* To skip prologues, I use this predicate. Returns either PC itself
4156 if the code at PC does not look like a function prologue; otherwise
4157 returns an address that (if we're lucky) follows the prologue. If
4158 LENIENT, then we must skip everything which is involved in setting
4159 up the frame (it's OK to skip more, just so long as we don't skip
4160 anything which might clobber the registers which are being saved.
4161 We must skip more in the case where part of the prologue is in the
4162 delay slot of a non-prologue instruction). */
4165 mips_skip_prologue (CORE_ADDR pc
)
4168 CORE_ADDR func_addr
;
4170 /* See if we can determine the end of the prologue via the symbol table.
4171 If so, then return either PC, or the PC after the prologue, whichever
4173 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4175 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4176 if (post_prologue_pc
!= 0)
4177 return max (pc
, post_prologue_pc
);
4180 /* Can't determine prologue from the symbol table, need to examine
4183 /* Find an upper limit on the function prologue using the debug
4184 information. If the debug information could not be used to provide
4185 that bound, then use an arbitrary large number as the upper bound. */
4186 limit_pc
= skip_prologue_using_sal (pc
);
4188 limit_pc
= pc
+ 100; /* Magic. */
4190 if (mips_pc_is_mips16 (pc
))
4191 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4193 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4196 /* Root of all "set mips "/"show mips " commands. This will eventually be
4197 used for all MIPS-specific commands. */
4200 show_mips_command (char *args
, int from_tty
)
4202 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4206 set_mips_command (char *args
, int from_tty
)
4209 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4210 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4213 /* Commands to show/set the MIPS FPU type. */
4216 show_mipsfpu_command (char *args
, int from_tty
)
4219 switch (MIPS_FPU_TYPE
)
4221 case MIPS_FPU_SINGLE
:
4222 fpu
= "single-precision";
4224 case MIPS_FPU_DOUBLE
:
4225 fpu
= "double-precision";
4228 fpu
= "absent (none)";
4231 internal_error (__FILE__
, __LINE__
, "bad switch");
4233 if (mips_fpu_type_auto
)
4235 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4239 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4244 set_mipsfpu_command (char *args
, int from_tty
)
4247 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4248 show_mipsfpu_command (args
, from_tty
);
4252 set_mipsfpu_single_command (char *args
, int from_tty
)
4254 struct gdbarch_info info
;
4255 gdbarch_info_init (&info
);
4256 mips_fpu_type
= MIPS_FPU_SINGLE
;
4257 mips_fpu_type_auto
= 0;
4258 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4259 instead of relying on globals. Doing that would let generic code
4260 handle the search for this specific architecture. */
4261 if (!gdbarch_update_p (info
))
4262 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4266 set_mipsfpu_double_command (char *args
, int from_tty
)
4268 struct gdbarch_info info
;
4269 gdbarch_info_init (&info
);
4270 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4271 mips_fpu_type_auto
= 0;
4272 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4273 instead of relying on globals. Doing that would let generic code
4274 handle the search for this specific architecture. */
4275 if (!gdbarch_update_p (info
))
4276 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4280 set_mipsfpu_none_command (char *args
, int from_tty
)
4282 struct gdbarch_info info
;
4283 gdbarch_info_init (&info
);
4284 mips_fpu_type
= MIPS_FPU_NONE
;
4285 mips_fpu_type_auto
= 0;
4286 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4287 instead of relying on globals. Doing that would let generic code
4288 handle the search for this specific architecture. */
4289 if (!gdbarch_update_p (info
))
4290 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4294 set_mipsfpu_auto_command (char *args
, int from_tty
)
4296 mips_fpu_type_auto
= 1;
4299 /* Attempt to identify the particular processor model by reading the
4300 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4301 the relevant processor still exists (it dates back to '94) and
4302 secondly this is not the way to do this. The processor type should
4303 be set by forcing an architecture change. */
4306 deprecated_mips_set_processor_regs_hack (void)
4308 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4311 prid
= read_register (MIPS_PRID_REGNUM
);
4313 if ((prid
& ~0xf) == 0x700)
4314 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4317 /* Just like reinit_frame_cache, but with the right arguments to be
4318 callable as an sfunc. */
4321 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4322 struct cmd_list_element
*c
)
4324 reinit_frame_cache ();
4328 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4330 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4332 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4333 disassembler needs to be able to locally determine the ISA, and
4334 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4336 if (mips_pc_is_mips16 (memaddr
))
4337 info
->mach
= bfd_mach_mips16
;
4339 /* Round down the instruction address to the appropriate boundary. */
4340 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4342 /* Set the disassembler options. */
4343 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4345 /* Set up the disassembler info, so that we get the right
4346 register names from libopcodes. */
4347 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4348 info
->disassembler_options
= "gpr-names=n32";
4350 info
->disassembler_options
= "gpr-names=64";
4351 info
->flavour
= bfd_target_elf_flavour
;
4354 /* This string is not recognized explicitly by the disassembler,
4355 but it tells the disassembler to not try to guess the ABI from
4356 the bfd elf headers, such that, if the user overrides the ABI
4357 of a program linked as NewABI, the disassembly will follow the
4358 register naming conventions specified by the user. */
4359 info
->disassembler_options
= "gpr-names=32";
4361 /* Call the appropriate disassembler based on the target endian-ness. */
4362 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4363 return print_insn_big_mips (memaddr
, info
);
4365 return print_insn_little_mips (memaddr
, info
);
4368 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4369 counter value to determine whether a 16- or 32-bit breakpoint should be
4370 used. It returns a pointer to a string of bytes that encode a breakpoint
4371 instruction, stores the length of the string to *lenptr, and adjusts pc
4372 (if necessary) to point to the actual memory location where the
4373 breakpoint should be inserted. */
4375 static const unsigned char *
4376 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4378 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4380 if (mips_pc_is_mips16 (*pcptr
))
4382 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4383 *pcptr
= unmake_mips16_addr (*pcptr
);
4384 *lenptr
= sizeof (mips16_big_breakpoint
);
4385 return mips16_big_breakpoint
;
4389 /* The IDT board uses an unusual breakpoint value, and
4390 sometimes gets confused when it sees the usual MIPS
4391 breakpoint instruction. */
4392 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4393 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4394 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4396 *lenptr
= sizeof (big_breakpoint
);
4398 if (strcmp (target_shortname
, "mips") == 0)
4399 return idt_big_breakpoint
;
4400 else if (strcmp (target_shortname
, "ddb") == 0
4401 || strcmp (target_shortname
, "pmon") == 0
4402 || strcmp (target_shortname
, "lsi") == 0)
4403 return pmon_big_breakpoint
;
4405 return big_breakpoint
;
4410 if (mips_pc_is_mips16 (*pcptr
))
4412 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4413 *pcptr
= unmake_mips16_addr (*pcptr
);
4414 *lenptr
= sizeof (mips16_little_breakpoint
);
4415 return mips16_little_breakpoint
;
4419 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4420 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4421 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4423 *lenptr
= sizeof (little_breakpoint
);
4425 if (strcmp (target_shortname
, "mips") == 0)
4426 return idt_little_breakpoint
;
4427 else if (strcmp (target_shortname
, "ddb") == 0
4428 || strcmp (target_shortname
, "pmon") == 0
4429 || strcmp (target_shortname
, "lsi") == 0)
4430 return pmon_little_breakpoint
;
4432 return little_breakpoint
;
4437 /* If PC is in a mips16 call or return stub, return the address of the target
4438 PC, which is either the callee or the caller. There are several
4439 cases which must be handled:
4441 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4442 target PC is in $31 ($ra).
4443 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4444 and the target PC is in $2.
4445 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4446 before the jal instruction, this is effectively a call stub
4447 and the the target PC is in $2. Otherwise this is effectively
4448 a return stub and the target PC is in $18.
4450 See the source code for the stubs in gcc/config/mips/mips16.S for
4454 mips_skip_trampoline_code (CORE_ADDR pc
)
4457 CORE_ADDR start_addr
;
4459 /* Find the starting address and name of the function containing the PC. */
4460 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4463 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4464 target PC is in $31 ($ra). */
4465 if (strcmp (name
, "__mips16_ret_sf") == 0
4466 || strcmp (name
, "__mips16_ret_df") == 0)
4467 return read_signed_register (MIPS_RA_REGNUM
);
4469 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4471 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4472 and the target PC is in $2. */
4473 if (name
[19] >= '0' && name
[19] <= '9')
4474 return read_signed_register (2);
4476 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4477 before the jal instruction, this is effectively a call stub
4478 and the the target PC is in $2. Otherwise this is effectively
4479 a return stub and the target PC is in $18. */
4480 else if (name
[19] == 's' || name
[19] == 'd')
4482 if (pc
== start_addr
)
4484 /* Check if the target of the stub is a compiler-generated
4485 stub. Such a stub for a function bar might have a name
4486 like __fn_stub_bar, and might look like this:
4491 la $1,bar (becomes a lui/addiu pair)
4493 So scan down to the lui/addi and extract the target
4494 address from those two instructions. */
4496 CORE_ADDR target_pc
= read_signed_register (2);
4500 /* See if the name of the target function is __fn_stub_*. */
4501 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4504 if (strncmp (name
, "__fn_stub_", 10) != 0
4505 && strcmp (name
, "etext") != 0
4506 && strcmp (name
, "_etext") != 0)
4509 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4510 The limit on the search is arbitrarily set to 20
4511 instructions. FIXME. */
4512 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
4514 inst
= mips_fetch_instruction (target_pc
);
4515 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4516 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4517 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4518 return pc
| (inst
& 0xffff); /* low word */
4521 /* Couldn't find the lui/addui pair, so return stub address. */
4525 /* This is the 'return' part of a call stub. The return
4526 address is in $r18. */
4527 return read_signed_register (18);
4530 return 0; /* not a stub */
4533 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4534 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4537 mips_stab_reg_to_regnum (int num
)
4540 if (num
>= 0 && num
< 32)
4542 else if (num
>= 38 && num
< 70)
4543 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4545 regnum
= mips_regnum (current_gdbarch
)->hi
;
4547 regnum
= mips_regnum (current_gdbarch
)->lo
;
4549 /* This will hopefully (eventually) provoke a warning. Should
4550 we be calling complaint() here? */
4551 return NUM_REGS
+ NUM_PSEUDO_REGS
;
4552 return NUM_REGS
+ regnum
;
4556 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4557 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4560 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4563 if (num
>= 0 && num
< 32)
4565 else if (num
>= 32 && num
< 64)
4566 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4568 regnum
= mips_regnum (current_gdbarch
)->hi
;
4570 regnum
= mips_regnum (current_gdbarch
)->lo
;
4572 /* This will hopefully (eventually) provoke a warning. Should we
4573 be calling complaint() here? */
4574 return NUM_REGS
+ NUM_PSEUDO_REGS
;
4575 return NUM_REGS
+ regnum
;
4579 mips_register_sim_regno (int regnum
)
4581 /* Only makes sense to supply raw registers. */
4582 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
4583 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4584 decide if it is valid. Should instead define a standard sim/gdb
4585 register numbering scheme. */
4586 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
4587 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
4590 return LEGACY_SIM_REGNO_IGNORE
;
4594 /* Convert an integer into an address. By first converting the value
4595 into a pointer and then extracting it signed, the address is
4596 guarenteed to be correctly sign extended. */
4599 mips_integer_to_address (struct type
*type
, void *buf
)
4601 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
4602 LONGEST val
= unpack_long (type
, buf
);
4603 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
4604 return extract_signed_integer (tmp
,
4605 TYPE_LENGTH (builtin_type_void_data_ptr
));
4609 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4611 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4612 const char *name
= bfd_get_section_name (abfd
, sect
);
4614 if (*abip
!= MIPS_ABI_UNKNOWN
)
4617 if (strncmp (name
, ".mdebug.", 8) != 0)
4620 if (strcmp (name
, ".mdebug.abi32") == 0)
4621 *abip
= MIPS_ABI_O32
;
4622 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4623 *abip
= MIPS_ABI_N32
;
4624 else if (strcmp (name
, ".mdebug.abi64") == 0)
4625 *abip
= MIPS_ABI_N64
;
4626 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4627 *abip
= MIPS_ABI_O64
;
4628 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4629 *abip
= MIPS_ABI_EABI32
;
4630 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4631 *abip
= MIPS_ABI_EABI64
;
4633 warning ("unsupported ABI %s.", name
+ 8);
4636 static enum mips_abi
4637 global_mips_abi (void)
4641 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4642 if (mips_abi_strings
[i
] == mips_abi_string
)
4643 return (enum mips_abi
) i
;
4645 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
4648 static struct gdbarch
*
4649 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4651 struct gdbarch
*gdbarch
;
4652 struct gdbarch_tdep
*tdep
;
4654 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4656 enum mips_fpu_type fpu_type
;
4658 /* First of all, extract the elf_flags, if available. */
4659 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4660 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4661 else if (arches
!= NULL
)
4662 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
4666 fprintf_unfiltered (gdb_stdlog
,
4667 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
4669 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4670 switch ((elf_flags
& EF_MIPS_ABI
))
4672 case E_MIPS_ABI_O32
:
4673 found_abi
= MIPS_ABI_O32
;
4675 case E_MIPS_ABI_O64
:
4676 found_abi
= MIPS_ABI_O64
;
4678 case E_MIPS_ABI_EABI32
:
4679 found_abi
= MIPS_ABI_EABI32
;
4681 case E_MIPS_ABI_EABI64
:
4682 found_abi
= MIPS_ABI_EABI64
;
4685 if ((elf_flags
& EF_MIPS_ABI2
))
4686 found_abi
= MIPS_ABI_N32
;
4688 found_abi
= MIPS_ABI_UNKNOWN
;
4692 /* GCC creates a pseudo-section whose name describes the ABI. */
4693 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4694 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
4696 /* If we have no useful BFD information, use the ABI from the last
4697 MIPS architecture (if there is one). */
4698 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
4699 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
4701 /* Try the architecture for any hint of the correct ABI. */
4702 if (found_abi
== MIPS_ABI_UNKNOWN
4703 && info
.bfd_arch_info
!= NULL
4704 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4706 switch (info
.bfd_arch_info
->mach
)
4708 case bfd_mach_mips3900
:
4709 found_abi
= MIPS_ABI_EABI32
;
4711 case bfd_mach_mips4100
:
4712 case bfd_mach_mips5000
:
4713 found_abi
= MIPS_ABI_EABI64
;
4715 case bfd_mach_mips8000
:
4716 case bfd_mach_mips10000
:
4717 /* On Irix, ELF64 executables use the N64 ABI. The
4718 pseudo-sections which describe the ABI aren't present
4719 on IRIX. (Even for executables created by gcc.) */
4720 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4721 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4722 found_abi
= MIPS_ABI_N64
;
4724 found_abi
= MIPS_ABI_N32
;
4730 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
4733 /* What has the user specified from the command line? */
4734 wanted_abi
= global_mips_abi ();
4736 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
4739 /* Now that we have found what the ABI for this binary would be,
4740 check whether the user is overriding it. */
4741 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
4742 mips_abi
= wanted_abi
;
4743 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
4744 mips_abi
= found_abi
;
4746 mips_abi
= MIPS_ABI_O32
;
4748 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
4751 /* Also used when doing an architecture lookup. */
4753 fprintf_unfiltered (gdb_stdlog
,
4754 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
4755 mips64_transfers_32bit_regs_p
);
4757 /* Determine the MIPS FPU type. */
4758 if (!mips_fpu_type_auto
)
4759 fpu_type
= mips_fpu_type
;
4760 else if (info
.bfd_arch_info
!= NULL
4761 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4762 switch (info
.bfd_arch_info
->mach
)
4764 case bfd_mach_mips3900
:
4765 case bfd_mach_mips4100
:
4766 case bfd_mach_mips4111
:
4767 case bfd_mach_mips4120
:
4768 fpu_type
= MIPS_FPU_NONE
;
4770 case bfd_mach_mips4650
:
4771 fpu_type
= MIPS_FPU_SINGLE
;
4774 fpu_type
= MIPS_FPU_DOUBLE
;
4777 else if (arches
!= NULL
)
4778 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
4780 fpu_type
= MIPS_FPU_DOUBLE
;
4782 fprintf_unfiltered (gdb_stdlog
,
4783 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
4785 /* try to find a pre-existing architecture */
4786 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4788 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4790 /* MIPS needs to be pedantic about which ABI the object is
4792 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4794 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4796 /* Need to be pedantic about which register virtual size is
4798 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
4799 != mips64_transfers_32bit_regs_p
)
4801 /* Be pedantic about which FPU is selected. */
4802 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
4804 return arches
->gdbarch
;
4807 /* Need a new architecture. Fill in a target specific vector. */
4808 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4809 gdbarch
= gdbarch_alloc (&info
, tdep
);
4810 tdep
->elf_flags
= elf_flags
;
4811 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
4812 tdep
->found_abi
= found_abi
;
4813 tdep
->mips_abi
= mips_abi
;
4814 tdep
->mips_fpu_type
= fpu_type
;
4816 /* Initially set everything according to the default ABI/ISA. */
4817 set_gdbarch_short_bit (gdbarch
, 16);
4818 set_gdbarch_int_bit (gdbarch
, 32);
4819 set_gdbarch_float_bit (gdbarch
, 32);
4820 set_gdbarch_double_bit (gdbarch
, 64);
4821 set_gdbarch_long_double_bit (gdbarch
, 64);
4822 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
4823 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
4824 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
4826 set_gdbarch_elf_make_msymbol_special (gdbarch
,
4827 mips_elf_make_msymbol_special
);
4829 /* Fill in the OS dependant register numbers and names. */
4831 const char **reg_names
;
4832 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
4833 struct mips_regnum
);
4834 if (info
.osabi
== GDB_OSABI_IRIX
)
4839 regnum
->badvaddr
= 66;
4842 regnum
->fp_control_status
= 69;
4843 regnum
->fp_implementation_revision
= 70;
4845 reg_names
= mips_irix_reg_names
;
4849 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
4850 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
4851 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
4852 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
4853 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
4854 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
4855 regnum
->fp_control_status
= 70;
4856 regnum
->fp_implementation_revision
= 71;
4858 if (info
.bfd_arch_info
!= NULL
4859 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
4860 reg_names
= mips_tx39_reg_names
;
4862 reg_names
= mips_generic_reg_names
;
4864 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
4865 replaced by read_pc? */
4866 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
4867 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
4868 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
4869 set_gdbarch_num_regs (gdbarch
, num_regs
);
4870 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
4871 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4872 tdep
->mips_processor_reg_names
= reg_names
;
4873 tdep
->regnum
= regnum
;
4879 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
4880 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
4881 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
4882 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
4883 tdep
->default_mask_address_p
= 0;
4884 set_gdbarch_long_bit (gdbarch
, 32);
4885 set_gdbarch_ptr_bit (gdbarch
, 32);
4886 set_gdbarch_long_long_bit (gdbarch
, 64);
4889 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
4890 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
4891 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
4892 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
4893 tdep
->default_mask_address_p
= 0;
4894 set_gdbarch_long_bit (gdbarch
, 32);
4895 set_gdbarch_ptr_bit (gdbarch
, 32);
4896 set_gdbarch_long_long_bit (gdbarch
, 64);
4898 case MIPS_ABI_EABI32
:
4899 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
4900 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
4901 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
4902 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
4903 tdep
->default_mask_address_p
= 0;
4904 set_gdbarch_long_bit (gdbarch
, 32);
4905 set_gdbarch_ptr_bit (gdbarch
, 32);
4906 set_gdbarch_long_long_bit (gdbarch
, 64);
4908 case MIPS_ABI_EABI64
:
4909 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
4910 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
4911 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
4912 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
4913 tdep
->default_mask_address_p
= 0;
4914 set_gdbarch_long_bit (gdbarch
, 64);
4915 set_gdbarch_ptr_bit (gdbarch
, 64);
4916 set_gdbarch_long_long_bit (gdbarch
, 64);
4919 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
4920 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
4921 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
4922 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
4923 tdep
->default_mask_address_p
= 0;
4924 set_gdbarch_long_bit (gdbarch
, 32);
4925 set_gdbarch_ptr_bit (gdbarch
, 32);
4926 set_gdbarch_long_long_bit (gdbarch
, 64);
4927 set_gdbarch_long_double_bit (gdbarch
, 128);
4928 set_gdbarch_long_double_format (gdbarch
,
4929 &floatformat_n32n64_long_double_big
);
4932 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
4933 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
4934 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
4935 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
4936 tdep
->default_mask_address_p
= 0;
4937 set_gdbarch_long_bit (gdbarch
, 64);
4938 set_gdbarch_ptr_bit (gdbarch
, 64);
4939 set_gdbarch_long_long_bit (gdbarch
, 64);
4940 set_gdbarch_long_double_bit (gdbarch
, 128);
4941 set_gdbarch_long_double_format (gdbarch
,
4942 &floatformat_n32n64_long_double_big
);
4945 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
4948 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4949 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4952 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4953 flag in object files because to do so would make it impossible to
4954 link with libraries compiled without "-gp32". This is
4955 unnecessarily restrictive.
4957 We could solve this problem by adding "-gp32" multilibs to gcc,
4958 but to set this flag before gcc is built with such multilibs will
4959 break too many systems.''
4961 But even more unhelpfully, the default linker output target for
4962 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4963 for 64-bit programs - you need to change the ABI to change this,
4964 and not all gcc targets support that currently. Therefore using
4965 this flag to detect 32-bit mode would do the wrong thing given
4966 the current gcc - it would make GDB treat these 64-bit programs
4967 as 32-bit programs by default. */
4969 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
4970 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
4971 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
4973 /* Add/remove bits from an address. The MIPS needs be careful to
4974 ensure that all 32 bit addresses are sign extended to 64 bits. */
4975 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
4977 /* Unwind the frame. */
4978 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
4979 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
4981 /* Map debug register numbers onto internal register numbers. */
4982 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
4983 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
4984 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
4985 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
4986 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
4987 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
4988 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
4989 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
4991 /* MIPS version of CALL_DUMMY */
4993 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
4994 replaced by a command, and all targets will default to on stack
4995 (regardless of the stack's execute status). */
4996 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
4997 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
4999 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5000 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5001 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5003 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5004 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5006 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5008 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5009 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5010 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5012 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5014 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5016 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5018 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5019 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5020 need to all be folded into the target vector. Since they are
5021 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5022 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5024 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5026 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5028 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5030 /* Hook in OS ABI-specific overrides, if they have been registered. */
5031 gdbarch_init_osabi (info
, gdbarch
);
5033 /* Unwind the frame. */
5034 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5035 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5036 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5037 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5038 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5039 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5045 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5047 struct gdbarch_info info
;
5049 /* Force the architecture to update, and (if it's a MIPS architecture)
5050 mips_gdbarch_init will take care of the rest. */
5051 gdbarch_info_init (&info
);
5052 gdbarch_update_p (info
);
5055 /* Print out which MIPS ABI is in use. */
5058 show_mips_abi (char *ignore_args
, int from_tty
)
5060 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5062 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
5065 enum mips_abi global_abi
= global_mips_abi ();
5066 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5067 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5069 if (global_abi
== MIPS_ABI_UNKNOWN
)
5071 ("The MIPS ABI is set automatically (currently \"%s\").\n",
5073 else if (global_abi
== actual_abi
)
5075 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5079 /* Probably shouldn't happen... */
5081 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5082 actual_abi_str
, mips_abi_strings
[global_abi
]);
5088 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5090 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5094 int ef_mips_32bitmode
;
5095 /* determine the ISA */
5096 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5114 /* determine the size of a pointer */
5115 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5116 fprintf_unfiltered (file
,
5117 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5119 fprintf_unfiltered (file
,
5120 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5122 fprintf_unfiltered (file
,
5123 "mips_dump_tdep: ef_mips_arch = %d\n",
5125 fprintf_unfiltered (file
,
5126 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5127 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5128 fprintf_unfiltered (file
,
5129 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5130 mips_mask_address_p (tdep
),
5131 tdep
->default_mask_address_p
);
5133 fprintf_unfiltered (file
,
5134 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5135 MIPS_DEFAULT_FPU_TYPE
,
5136 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5137 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5138 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5140 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5141 fprintf_unfiltered (file
,
5142 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5144 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5145 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5146 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5148 fprintf_unfiltered (file
,
5149 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5150 mips_stack_argsize (current_gdbarch
));
5153 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5156 _initialize_mips_tdep (void)
5158 static struct cmd_list_element
*mipsfpulist
= NULL
;
5159 struct cmd_list_element
*c
;
5161 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5162 if (MIPS_ABI_LAST
+ 1
5163 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5164 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
5166 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5168 mips_pdr_data
= register_objfile_data ();
5170 /* Add root prefix command for all "set mips"/"show mips" commands */
5171 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5172 "Various MIPS specific commands.",
5173 &setmipscmdlist
, "set mips ", 0, &setlist
);
5175 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5176 "Various MIPS specific commands.",
5177 &showmipscmdlist
, "show mips ", 0, &showlist
);
5179 /* Allow the user to override the saved register size. */
5180 add_setshow_enum_cmd ("saved-gpreg-size", class_obscure
,
5181 size_enums
, &mips_abi_regsize_string
, "\
5182 Set size of general purpose registers saved on the stack.\n", "\
5183 Show size of general purpose registers saved on the stack.\n", "\
5184 This option can be set to one of:\n\
5185 32 - Force GDB to treat saved GP registers as 32-bit\n\
5186 64 - Force GDB to treat saved GP registers as 64-bit\n\
5187 auto - Allow GDB to use the target's default setting or autodetect the\n\
5188 saved GP register size from information contained in the executable.\n\
5189 (default: auto)", "\
5190 Size of general purpose registers saved on the stack is %s.\n",
5191 NULL
, NULL
, &setmipscmdlist
, &showmipscmdlist
);
5193 /* Allow the user to override the argument stack size. */
5194 add_setshow_enum_cmd ("stack-arg-size", class_obscure
,
5195 size_enums
, &mips_stack_argsize_string
, "\
5196 Set the amount of stack space reserved for each argument.\n", "\
5197 Show the amount of stack space reserved for each argument.\n", "\
5198 This option can be set to one of:\n\
5199 32 - Force GDB to allocate 32-bit chunks per argument\n\
5200 64 - Force GDB to allocate 64-bit chunks per argument\n\
5201 auto - Allow GDB to determine the correct setting from the current\n\
5202 target and executable (default)", "\
5203 The amount of stack space reserved for each argument is %s.\n",
5204 NULL
, NULL
, &setmipscmdlist
, &showmipscmdlist
);
5206 /* Allow the user to override the ABI. */
5207 c
= add_set_enum_cmd
5208 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
5209 "Set the ABI used by this program.\n"
5210 "This option can be set to one of:\n"
5211 " auto - the default ABI associated with the current binary\n"
5213 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
5214 set_cmd_sfunc (c
, mips_abi_update
);
5215 add_cmd ("abi", class_obscure
, show_mips_abi
,
5216 "Show ABI in use by MIPS target", &showmipscmdlist
);
5218 /* Let the user turn off floating point and set the fence post for
5219 heuristic_proc_start. */
5221 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5222 "Set use of MIPS floating-point coprocessor.",
5223 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5224 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5225 "Select single-precision MIPS floating-point coprocessor.",
5227 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5228 "Select double-precision MIPS floating-point coprocessor.",
5230 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5231 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5232 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5233 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5234 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
5235 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5236 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5237 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5238 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5239 "Select MIPS floating-point coprocessor automatically.",
5241 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5242 "Show current use of MIPS floating-point coprocessor target.",
5245 /* We really would like to have both "0" and "unlimited" work, but
5246 command.c doesn't deal with that. So make it a var_zinteger
5247 because the user can always use "999999" or some such for unlimited. */
5248 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5249 &heuristic_fence_post
, "\
5250 Set the distance searched for the start of a function.\n", "\
5251 Show the distance searched for the start of a function.\n", "\
5252 If you are debugging a stripped executable, GDB needs to search through the\n\
5253 program for the start of a function. This command sets the distance of the\n\
5254 search. The only need to set it is when debugging a stripped executable.", "\
5255 The distance searched for the start of a function is %s.\n",
5256 reinit_frame_cache_sfunc
, NULL
,
5257 &setlist
, &showlist
);
5259 /* Allow the user to control whether the upper bits of 64-bit
5260 addresses should be zeroed. */
5261 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
5262 Set zeroing of upper 32 bits of 64-bit addresses.", "\
5263 Show zeroing of upper 32 bits of 64-bit addresses.", "\
5264 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5265 allow GDB to determine the correct value.\n", "\
5266 Zerroing of upper 32 bits of 64-bit address is %s.",
5267 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
5269 /* Allow the user to control the size of 32 bit registers within the
5270 raw remote packet. */
5271 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
5272 &mips64_transfers_32bit_regs_p
, "\
5273 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
5274 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
5275 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5276 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5277 64 bits for others. Use \"off\" to disable compatibility mode", "\
5278 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
5279 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
5281 /* Debug this files internals. */
5282 add_setshow_zinteger_cmd ("mips", class_maintenance
,
5284 Set mips debugging.\n", "\
5285 Show mips debugging.\n", "\
5286 When non-zero, mips specific debugging is enabled.\n", "\
5287 Mips debugging is currently %s.\n",
5289 &setdebuglist
, &showdebuglist
);