1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_string.h"
25 #include "gdb_assert.h"
37 #include "arch-utils.h"
40 #include "mips-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/mips.h"
47 #include "sim-regno.h"
49 #include "frame-unwind.h"
50 #include "frame-base.h"
51 #include "trad-frame.h"
53 #include "floatformat.h"
55 #include "target-descriptions.h"
56 #include "dwarf2-frame.h"
57 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 static int mips32_instruction_has_delay_slot (struct gdbarch
*, CORE_ADDR
);
66 static int micromips_instruction_has_delay_slot (struct gdbarch
*, CORE_ADDR
,
68 static int mips16_instruction_has_delay_slot (struct gdbarch
*, CORE_ADDR
,
71 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
72 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
73 #define ST0_FR (1 << 26)
75 /* The sizes of floating point registers. */
79 MIPS_FPU_SINGLE_REGSIZE
= 4,
80 MIPS_FPU_DOUBLE_REGSIZE
= 8
89 static const char *mips_abi_string
;
91 static const char *const mips_abi_strings
[] = {
102 /* For backwards compatibility we default to MIPS16. This flag is
103 overridden as soon as unambiguous ELF file flags tell us the
104 compressed ISA encoding used. */
105 static const char mips_compression_mips16
[] = "mips16";
106 static const char mips_compression_micromips
[] = "micromips";
107 static const char *const mips_compression_strings
[] =
109 mips_compression_mips16
,
110 mips_compression_micromips
,
114 static const char *mips_compression_string
= mips_compression_mips16
;
116 /* The standard register names, and all the valid aliases for them. */
117 struct register_alias
123 /* Aliases for o32 and most other ABIs. */
124 const struct register_alias mips_o32_aliases
[] = {
131 /* Aliases for n32 and n64. */
132 const struct register_alias mips_n32_n64_aliases
[] = {
139 /* Aliases for ABI-independent registers. */
140 const struct register_alias mips_register_aliases
[] = {
141 /* The architecture manuals specify these ABI-independent names for
143 #define R(n) { "r" #n, n }
144 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
145 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
146 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
147 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
150 /* k0 and k1 are sometimes called these instead (for "kernel
155 /* This is the traditional GDB name for the CP0 status register. */
156 { "sr", MIPS_PS_REGNUM
},
158 /* This is the traditional GDB name for the CP0 BadVAddr register. */
159 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
161 /* This is the traditional GDB name for the FCSR. */
162 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
165 const struct register_alias mips_numeric_register_aliases
[] = {
166 #define R(n) { #n, n }
167 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
168 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
169 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
170 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
174 #ifndef MIPS_DEFAULT_FPU_TYPE
175 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
177 static int mips_fpu_type_auto
= 1;
178 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
180 static int mips_debug
= 0;
182 /* Properties (for struct target_desc) describing the g/G packet
184 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
185 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
187 struct target_desc
*mips_tdesc_gp32
;
188 struct target_desc
*mips_tdesc_gp64
;
190 const struct mips_regnum
*
191 mips_regnum (struct gdbarch
*gdbarch
)
193 return gdbarch_tdep (gdbarch
)->regnum
;
197 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
199 return mips_regnum (gdbarch
)->fp0
+ 12;
202 /* Return 1 if REGNUM refers to a floating-point general register, raw
203 or cooked. Otherwise return 0. */
206 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
208 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
210 return (rawnum
>= mips_regnum (gdbarch
)->fp0
211 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
214 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
216 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
218 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
219 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
221 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
222 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
224 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
226 /* Return the MIPS ABI associated with GDBARCH. */
228 mips_abi (struct gdbarch
*gdbarch
)
230 return gdbarch_tdep (gdbarch
)->mips_abi
;
234 mips_isa_regsize (struct gdbarch
*gdbarch
)
236 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
238 /* If we know how big the registers are, use that size. */
239 if (tdep
->register_size_valid_p
)
240 return tdep
->register_size
;
242 /* Fall back to the previous behavior. */
243 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
244 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
247 /* Return the currently configured (or set) saved register size. */
250 mips_abi_regsize (struct gdbarch
*gdbarch
)
252 switch (mips_abi (gdbarch
))
254 case MIPS_ABI_EABI32
:
260 case MIPS_ABI_EABI64
:
262 case MIPS_ABI_UNKNOWN
:
265 internal_error (__FILE__
, __LINE__
, _("bad switch"));
269 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
270 are some functions to handle addresses associated with compressed
271 code including but not limited to testing, setting, or clearing
272 bit 0 of such addresses. */
274 /* Return one iff compressed code is the MIPS16 instruction set. */
277 is_mips16_isa (struct gdbarch
*gdbarch
)
279 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
282 /* Return one iff compressed code is the microMIPS instruction set. */
285 is_micromips_isa (struct gdbarch
*gdbarch
)
287 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
290 /* Return one iff ADDR denotes compressed code. */
293 is_compact_addr (CORE_ADDR addr
)
298 /* Return one iff ADDR denotes standard ISA code. */
301 is_mips_addr (CORE_ADDR addr
)
303 return !is_compact_addr (addr
);
306 /* Return one iff ADDR denotes MIPS16 code. */
309 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
311 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
314 /* Return one iff ADDR denotes microMIPS code. */
317 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
319 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
322 /* Strip the ISA (compression) bit off from ADDR. */
325 unmake_compact_addr (CORE_ADDR addr
)
327 return ((addr
) & ~(CORE_ADDR
) 1);
330 /* Add the ISA (compression) bit to ADDR. */
333 make_compact_addr (CORE_ADDR addr
)
335 return ((addr
) | (CORE_ADDR
) 1);
338 /* Functions for setting and testing a bit in a minimal symbol that
339 marks it as MIPS16 or microMIPS function. The MSB of the minimal
340 symbol's "info" field is used for this purpose.
342 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
343 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
344 one of the "special" bits in a minimal symbol to mark it accordingly.
345 The test checks an ELF-private flag that is valid for true function
346 symbols only; in particular synthetic symbols such as for PLT stubs
347 have no ELF-private part at all.
349 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
350 in a minimal symbol. */
353 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
355 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
357 if ((sym
->flags
& BSF_SYNTHETIC
) != 0)
360 if (ELF_ST_IS_MICROMIPS (elfsym
->internal_elf_sym
.st_other
))
361 MSYMBOL_TARGET_FLAG_2 (msym
) = 1;
362 else if (ELF_ST_IS_MIPS16 (elfsym
->internal_elf_sym
.st_other
))
363 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
366 /* Return one iff MSYM refers to standard ISA code. */
369 msymbol_is_mips (struct minimal_symbol
*msym
)
371 return !(MSYMBOL_TARGET_FLAG_1 (msym
) | MSYMBOL_TARGET_FLAG_2 (msym
));
374 /* Return one iff MSYM refers to MIPS16 code. */
377 msymbol_is_mips16 (struct minimal_symbol
*msym
)
379 return MSYMBOL_TARGET_FLAG_1 (msym
);
382 /* Return one iff MSYM refers to microMIPS code. */
385 msymbol_is_micromips (struct minimal_symbol
*msym
)
387 return MSYMBOL_TARGET_FLAG_2 (msym
);
390 /* XFER a value from the big/little/left end of the register.
391 Depending on the size of the value it might occupy the entire
392 register or just part of it. Make an allowance for this, aligning
393 things accordingly. */
396 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
397 int reg_num
, int length
,
398 enum bfd_endian endian
, gdb_byte
*in
,
399 const gdb_byte
*out
, int buf_offset
)
403 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
404 /* Need to transfer the left or right part of the register, based on
405 the targets byte order. */
409 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
411 case BFD_ENDIAN_LITTLE
:
414 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
418 internal_error (__FILE__
, __LINE__
, _("bad switch"));
421 fprintf_unfiltered (gdb_stderr
,
422 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
423 reg_num
, reg_offset
, buf_offset
, length
);
424 if (mips_debug
&& out
!= NULL
)
427 fprintf_unfiltered (gdb_stdlog
, "out ");
428 for (i
= 0; i
< length
; i
++)
429 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
432 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
435 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
437 if (mips_debug
&& in
!= NULL
)
440 fprintf_unfiltered (gdb_stdlog
, "in ");
441 for (i
= 0; i
< length
; i
++)
442 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
445 fprintf_unfiltered (gdb_stdlog
, "\n");
448 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
449 compatiblity mode. A return value of 1 means that we have
450 physical 64-bit registers, but should treat them as 32-bit registers. */
453 mips2_fp_compat (struct frame_info
*frame
)
455 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
456 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
458 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
462 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
463 in all the places we deal with FP registers. PR gdb/413. */
464 /* Otherwise check the FR bit in the status register - it controls
465 the FP compatiblity mode. If it is clear we are in compatibility
467 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
474 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
476 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
478 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
480 /* The list of available "set mips " and "show mips " commands. */
482 static struct cmd_list_element
*setmipscmdlist
= NULL
;
483 static struct cmd_list_element
*showmipscmdlist
= NULL
;
485 /* Integer registers 0 thru 31 are handled explicitly by
486 mips_register_name(). Processor specific registers 32 and above
487 are listed in the following tables. */
490 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
494 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
495 "sr", "lo", "hi", "bad", "cause", "pc",
496 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
497 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
498 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
499 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
503 /* Names of IDT R3041 registers. */
505 static const char *mips_r3041_reg_names
[] = {
506 "sr", "lo", "hi", "bad", "cause", "pc",
507 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
508 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
509 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
510 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
511 "fsr", "fir", "", /*"fp" */ "",
512 "", "", "bus", "ccfg", "", "", "", "",
513 "", "", "port", "cmp", "", "", "epc", "prid",
516 /* Names of tx39 registers. */
518 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
519 "sr", "lo", "hi", "bad", "cause", "pc",
520 "", "", "", "", "", "", "", "",
521 "", "", "", "", "", "", "", "",
522 "", "", "", "", "", "", "", "",
523 "", "", "", "", "", "", "", "",
525 "", "", "", "", "", "", "", "",
526 "", "", "config", "cache", "debug", "depc", "epc",
529 /* Names of IRIX registers. */
530 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
531 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
532 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
533 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
534 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
535 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
538 /* Names of registers with Linux kernels. */
539 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
540 "sr", "lo", "hi", "bad", "cause", "pc",
541 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
542 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
543 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
544 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
549 /* Return the name of the register corresponding to REGNO. */
551 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
553 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
554 /* GPR names for all ABIs other than n32/n64. */
555 static char *mips_gpr_names
[] = {
556 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
557 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
558 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
559 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
562 /* GPR names for n32 and n64 ABIs. */
563 static char *mips_n32_n64_gpr_names
[] = {
564 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
565 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
566 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
567 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
570 enum mips_abi abi
= mips_abi (gdbarch
);
572 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
573 but then don't make the raw register names visible. This (upper)
574 range of user visible register numbers are the pseudo-registers.
576 This approach was adopted accommodate the following scenario:
577 It is possible to debug a 64-bit device using a 32-bit
578 programming model. In such instances, the raw registers are
579 configured to be 64-bits wide, while the pseudo registers are
580 configured to be 32-bits wide. The registers that the user
581 sees - the pseudo registers - match the users expectations
582 given the programming model being used. */
583 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
584 if (regno
< gdbarch_num_regs (gdbarch
))
587 /* The MIPS integer registers are always mapped from 0 to 31. The
588 names of the registers (which reflects the conventions regarding
589 register use) vary depending on the ABI. */
590 if (0 <= rawnum
&& rawnum
< 32)
592 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
593 return mips_n32_n64_gpr_names
[rawnum
];
595 return mips_gpr_names
[rawnum
];
597 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
598 return tdesc_register_name (gdbarch
, rawnum
);
599 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
601 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
602 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
603 return tdep
->mips_processor_reg_names
[rawnum
- 32];
607 internal_error (__FILE__
, __LINE__
,
608 _("mips_register_name: bad register number %d"), rawnum
);
611 /* Return the groups that a MIPS register can be categorised into. */
614 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
615 struct reggroup
*reggroup
)
620 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
621 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
622 if (reggroup
== all_reggroup
)
624 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
625 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
626 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
627 (gdbarch), as not all architectures are multi-arch. */
628 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
629 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
630 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
632 if (reggroup
== float_reggroup
)
633 return float_p
&& pseudo
;
634 if (reggroup
== vector_reggroup
)
635 return vector_p
&& pseudo
;
636 if (reggroup
== general_reggroup
)
637 return (!vector_p
&& !float_p
) && pseudo
;
638 /* Save the pseudo registers. Need to make certain that any code
639 extracting register values from a saved register cache also uses
641 if (reggroup
== save_reggroup
)
642 return raw_p
&& pseudo
;
643 /* Restore the same pseudo register. */
644 if (reggroup
== restore_reggroup
)
645 return raw_p
&& pseudo
;
649 /* Return the groups that a MIPS register can be categorised into.
650 This version is only used if we have a target description which
651 describes real registers (and their groups). */
654 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
655 struct reggroup
*reggroup
)
657 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
658 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
661 /* Only save, restore, and display the pseudo registers. Need to
662 make certain that any code extracting register values from a
663 saved register cache also uses pseudo registers.
665 Note: saving and restoring the pseudo registers is slightly
666 strange; if we have 64 bits, we should save and restore all
667 64 bits. But this is hard and has little benefit. */
671 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
675 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
678 /* Map the symbol table registers which live in the range [1 *
679 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
680 registers. Take care of alignment and size problems. */
682 static enum register_status
683 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
684 int cookednum
, gdb_byte
*buf
)
686 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
687 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
688 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
689 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
690 return regcache_raw_read (regcache
, rawnum
, buf
);
691 else if (register_size (gdbarch
, rawnum
) >
692 register_size (gdbarch
, cookednum
))
694 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
695 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
698 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
700 enum register_status status
;
702 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
703 if (status
== REG_VALID
)
704 store_signed_integer (buf
, 4, byte_order
, regval
);
709 internal_error (__FILE__
, __LINE__
, _("bad register size"));
713 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
714 struct regcache
*regcache
, int cookednum
,
717 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
718 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
719 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
720 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
721 regcache_raw_write (regcache
, rawnum
, buf
);
722 else if (register_size (gdbarch
, rawnum
) >
723 register_size (gdbarch
, cookednum
))
725 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
726 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
729 /* Sign extend the shortened version of the register prior
730 to placing it in the raw register. This is required for
731 some mips64 parts in order to avoid unpredictable behavior. */
732 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
733 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
734 regcache_raw_write_signed (regcache
, rawnum
, regval
);
738 internal_error (__FILE__
, __LINE__
, _("bad register size"));
742 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
743 struct agent_expr
*ax
, int reg
)
745 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
746 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
747 && reg
< 2 * gdbarch_num_regs (gdbarch
));
749 ax_reg_mask (ax
, rawnum
);
755 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
756 struct agent_expr
*ax
, int reg
)
758 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
759 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
760 && reg
< 2 * gdbarch_num_regs (gdbarch
));
761 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
765 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
767 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
768 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
771 ax_simple (ax
, aop_lsh
);
774 ax_simple (ax
, aop_rsh_signed
);
778 internal_error (__FILE__
, __LINE__
, _("bad register size"));
783 /* Table to translate 3-bit register field to actual register number. */
784 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
786 /* Heuristic_proc_start may hunt through the text section for a long
787 time across a 2400 baud serial line. Allows the user to limit this
790 static unsigned int heuristic_fence_post
= 0;
792 /* Number of bytes of storage in the actual machine representation for
793 register N. NOTE: This defines the pseudo register type so need to
794 rebuild the architecture vector. */
796 static int mips64_transfers_32bit_regs_p
= 0;
799 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
800 struct cmd_list_element
*c
)
802 struct gdbarch_info info
;
803 gdbarch_info_init (&info
);
804 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
805 instead of relying on globals. Doing that would let generic code
806 handle the search for this specific architecture. */
807 if (!gdbarch_update_p (info
))
809 mips64_transfers_32bit_regs_p
= 0;
810 error (_("32-bit compatibility mode not supported"));
814 /* Convert to/from a register and the corresponding memory value. */
816 /* This predicate tests for the case of an 8 byte floating point
817 value that is being transferred to or from a pair of floating point
818 registers each of which are (or are considered to be) only 4 bytes
821 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
824 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
825 && register_size (gdbarch
, regnum
) == 4
826 && mips_float_register_p (gdbarch
, regnum
)
827 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
830 /* This predicate tests for the case of a value of less than 8
831 bytes in width that is being transfered to or from an 8 byte
832 general purpose register. */
834 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
837 int num_regs
= gdbarch_num_regs (gdbarch
);
839 return (register_size (gdbarch
, regnum
) == 8
840 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
841 && TYPE_LENGTH (type
) < 8);
845 mips_convert_register_p (struct gdbarch
*gdbarch
,
846 int regnum
, struct type
*type
)
848 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
849 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
853 mips_register_to_value (struct frame_info
*frame
, int regnum
,
854 struct type
*type
, gdb_byte
*to
,
855 int *optimizedp
, int *unavailablep
)
857 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
859 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
861 get_frame_register (frame
, regnum
+ 0, to
+ 4);
862 get_frame_register (frame
, regnum
+ 1, to
+ 0);
864 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
865 optimizedp
, unavailablep
))
868 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
869 optimizedp
, unavailablep
))
871 *optimizedp
= *unavailablep
= 0;
874 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
876 int len
= TYPE_LENGTH (type
);
879 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
880 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
881 optimizedp
, unavailablep
))
884 *optimizedp
= *unavailablep
= 0;
889 internal_error (__FILE__
, __LINE__
,
890 _("mips_register_to_value: unrecognized case"));
895 mips_value_to_register (struct frame_info
*frame
, int regnum
,
896 struct type
*type
, const gdb_byte
*from
)
898 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
900 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
902 put_frame_register (frame
, regnum
+ 0, from
+ 4);
903 put_frame_register (frame
, regnum
+ 1, from
+ 0);
905 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
908 int len
= TYPE_LENGTH (type
);
910 /* Sign extend values, irrespective of type, that are stored to
911 a 64-bit general purpose register. (32-bit unsigned values
912 are stored as signed quantities within a 64-bit register.
913 When performing an operation, in compiled code, that combines
914 a 32-bit unsigned value with a signed 64-bit value, a type
915 conversion is first performed that zeroes out the high 32 bits.) */
916 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
919 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
921 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
922 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
923 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
927 if (from
[len
-1] & 0x80)
928 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
930 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
931 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
932 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
937 internal_error (__FILE__
, __LINE__
,
938 _("mips_value_to_register: unrecognized case"));
942 /* Return the GDB type object for the "standard" data type of data in
946 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
948 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
949 if (mips_float_register_p (gdbarch
, regnum
))
951 /* The floating-point registers raw, or cooked, always match
952 mips_isa_regsize(), and also map 1:1, byte for byte. */
953 if (mips_isa_regsize (gdbarch
) == 4)
954 return builtin_type (gdbarch
)->builtin_float
;
956 return builtin_type (gdbarch
)->builtin_double
;
958 else if (regnum
< gdbarch_num_regs (gdbarch
))
960 /* The raw or ISA registers. These are all sized according to
962 if (mips_isa_regsize (gdbarch
) == 4)
963 return builtin_type (gdbarch
)->builtin_int32
;
965 return builtin_type (gdbarch
)->builtin_int64
;
969 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
971 /* The cooked or ABI registers. These are sized according to
972 the ABI (with a few complications). */
973 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
974 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
975 return builtin_type (gdbarch
)->builtin_int32
;
976 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
977 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
978 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
979 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
980 /* The pseudo/cooked view of the embedded registers is always
981 32-bit. The raw view is handled below. */
982 return builtin_type (gdbarch
)->builtin_int32
;
983 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
984 /* The target, while possibly using a 64-bit register buffer,
985 is only transfering 32-bits of each integer register.
986 Reflect this in the cooked/pseudo (ABI) register value. */
987 return builtin_type (gdbarch
)->builtin_int32
;
988 else if (mips_abi_regsize (gdbarch
) == 4)
989 /* The ABI is restricted to 32-bit registers (the ISA could be
991 return builtin_type (gdbarch
)->builtin_int32
;
994 return builtin_type (gdbarch
)->builtin_int64
;
998 /* Return the GDB type for the pseudo register REGNUM, which is the
999 ABI-level view. This function is only called if there is a target
1000 description which includes registers, so we know precisely the
1001 types of hardware registers. */
1003 static struct type
*
1004 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1006 const int num_regs
= gdbarch_num_regs (gdbarch
);
1007 int rawnum
= regnum
% num_regs
;
1008 struct type
*rawtype
;
1010 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1012 /* Absent registers are still absent. */
1013 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1014 if (TYPE_LENGTH (rawtype
) == 0)
1017 if (mips_float_register_p (gdbarch
, rawnum
))
1018 /* Present the floating point registers however the hardware did;
1019 do not try to convert between FPU layouts. */
1022 /* Use pointer types for registers if we can. For n32 we can not,
1023 since we do not have a 64-bit pointer type. */
1024 if (mips_abi_regsize (gdbarch
)
1025 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1027 if (rawnum
== MIPS_SP_REGNUM
1028 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1029 return builtin_type (gdbarch
)->builtin_data_ptr
;
1030 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1031 return builtin_type (gdbarch
)->builtin_func_ptr
;
1034 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1035 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1036 || rawnum
== mips_regnum (gdbarch
)->lo
1037 || rawnum
== mips_regnum (gdbarch
)->hi
1038 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1039 || rawnum
== mips_regnum (gdbarch
)->cause
1040 || rawnum
== mips_regnum (gdbarch
)->pc
1041 || (mips_regnum (gdbarch
)->dspacc
!= -1
1042 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1043 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1044 return builtin_type (gdbarch
)->builtin_int32
;
1046 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
1047 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1048 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
1049 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1051 /* The pseudo/cooked view of embedded registers is always
1052 32-bit, even if the target transfers 64-bit values for them.
1053 New targets relying on XML descriptions should only transfer
1054 the necessary 32 bits, but older versions of GDB expected 64,
1055 so allow the target to provide 64 bits without interfering
1056 with the displayed type. */
1057 return builtin_type (gdbarch
)->builtin_int32
;
1060 /* For all other registers, pass through the hardware type. */
1064 /* Should the upper word of 64-bit addresses be zeroed? */
1065 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1068 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1070 switch (mask_address_var
)
1072 case AUTO_BOOLEAN_TRUE
:
1074 case AUTO_BOOLEAN_FALSE
:
1077 case AUTO_BOOLEAN_AUTO
:
1078 return tdep
->default_mask_address_p
;
1080 internal_error (__FILE__
, __LINE__
,
1081 _("mips_mask_address_p: bad switch"));
1087 show_mask_address (struct ui_file
*file
, int from_tty
,
1088 struct cmd_list_element
*c
, const char *value
)
1090 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
1092 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1093 switch (mask_address_var
)
1095 case AUTO_BOOLEAN_TRUE
:
1096 printf_filtered ("The 32 bit mips address mask is enabled\n");
1098 case AUTO_BOOLEAN_FALSE
:
1099 printf_filtered ("The 32 bit mips address mask is disabled\n");
1101 case AUTO_BOOLEAN_AUTO
:
1103 ("The 32 bit address mask is set automatically. Currently %s\n",
1104 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1107 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1112 /* Tell if the program counter value in MEMADDR is in a standard ISA
1116 mips_pc_is_mips (CORE_ADDR memaddr
)
1118 struct minimal_symbol
*sym
;
1120 /* Flags indicating that this is a MIPS16 or microMIPS function is
1121 stored by elfread.c in the high bit of the info field. Use this
1122 to decide if the function is standard MIPS. Otherwise if bit 0
1123 of the address is clear, then this is a standard MIPS function. */
1124 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1126 return msymbol_is_mips (sym
);
1128 return is_mips_addr (memaddr
);
1131 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1134 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1136 struct minimal_symbol
*sym
;
1138 /* A flag indicating that this is a MIPS16 function is stored by
1139 elfread.c in the high bit of the info field. Use this to decide
1140 if the function is MIPS16. Otherwise if bit 0 of the address is
1141 set, then ELF file flags will tell if this is a MIPS16 function. */
1142 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1144 return msymbol_is_mips16 (sym
);
1146 return is_mips16_addr (gdbarch
, memaddr
);
1149 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1152 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1154 struct minimal_symbol
*sym
;
1156 /* A flag indicating that this is a microMIPS function is stored by
1157 elfread.c in the high bit of the info field. Use this to decide
1158 if the function is microMIPS. Otherwise if bit 0 of the address
1159 is set, then ELF file flags will tell if this is a microMIPS
1161 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1163 return msymbol_is_micromips (sym
);
1165 return is_micromips_addr (gdbarch
, memaddr
);
1168 /* Tell the ISA type of the function the program counter value in MEMADDR
1171 static enum mips_isa
1172 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1174 struct minimal_symbol
*sym
;
1176 /* A flag indicating that this is a MIPS16 or a microMIPS function
1177 is stored by elfread.c in the high bit of the info field. Use
1178 this to decide if the function is MIPS16 or microMIPS or normal
1179 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1180 flags will tell if this is a MIPS16 or a microMIPS function. */
1181 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1184 if (msymbol_is_micromips (sym
))
1185 return ISA_MICROMIPS
;
1186 else if (msymbol_is_mips16 (sym
))
1193 if (is_mips_addr (memaddr
))
1195 else if (is_micromips_addr (gdbarch
, memaddr
))
1196 return ISA_MICROMIPS
;
1202 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1204 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1205 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1206 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1207 static const char mips_str_call_stub
[] = "__call_stub_";
1208 static const char mips_str_fn_stub
[] = "__fn_stub_";
1210 /* This is used as a PIC thunk prefix. */
1212 static const char mips_str_pic
[] = ".pic.";
1214 /* Return non-zero if the PC is inside a call thunk (aka stub or
1215 trampoline) that should be treated as a temporary frame. */
1218 mips_in_frame_stub (CORE_ADDR pc
)
1220 CORE_ADDR start_addr
;
1223 /* Find the starting address of the function containing the PC. */
1224 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1227 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1228 if (strncmp (name
, mips_str_mips16_call_stub
,
1229 strlen (mips_str_mips16_call_stub
)) == 0)
1231 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1232 if (strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
1234 /* If the PC is in __fn_stub_*, this is a call stub. */
1235 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0)
1238 return 0; /* Not a stub. */
1241 /* MIPS believes that the PC has a sign extended value. Perhaps the
1242 all registers should be sign extended for simplicity? */
1245 mips_read_pc (struct regcache
*regcache
)
1247 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1250 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1251 if (is_compact_addr (pc
))
1252 pc
= unmake_compact_addr (pc
);
1257 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1261 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1262 if (is_compact_addr (pc
))
1263 pc
= unmake_compact_addr (pc
);
1264 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1265 intermediate frames. In this case we can get the caller's address
1266 from $ra, or if $ra contains an address within a thunk as well, then
1267 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1268 and thus the caller's address is in $s2. */
1269 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1271 pc
= frame_unwind_register_signed
1272 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1273 if (is_compact_addr (pc
))
1274 pc
= unmake_compact_addr (pc
);
1275 if (mips_in_frame_stub (pc
))
1277 pc
= frame_unwind_register_signed
1278 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1279 if (is_compact_addr (pc
))
1280 pc
= unmake_compact_addr (pc
);
1287 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1289 return frame_unwind_register_signed
1290 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1293 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1294 dummy frame. The frame ID's base needs to match the TOS value
1295 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1298 static struct frame_id
1299 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1301 return frame_id_build
1302 (get_frame_register_signed (this_frame
,
1303 gdbarch_num_regs (gdbarch
)
1305 get_frame_pc (this_frame
));
1308 /* Implement the "write_pc" gdbarch method. */
1311 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1313 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1315 if (mips_pc_is_mips (pc
))
1316 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1318 regcache_cooked_write_unsigned (regcache
, regnum
, make_compact_addr (pc
));
1321 /* Fetch and return instruction from the specified location. Handle
1322 MIPS16/microMIPS as appropriate. */
1325 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1326 enum mips_isa isa
, CORE_ADDR addr
, int *statusp
)
1328 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1329 gdb_byte buf
[MIPS_INSN32_SIZE
];
1337 instlen
= MIPS_INSN16_SIZE
;
1338 addr
= unmake_compact_addr (addr
);
1341 instlen
= MIPS_INSN32_SIZE
;
1344 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1347 status
= target_read_memory (addr
, buf
, instlen
);
1348 if (statusp
!= NULL
)
1352 if (statusp
== NULL
)
1353 memory_error (status
, addr
);
1356 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1359 /* These are the fields of 32 bit mips instructions. */
1360 #define mips32_op(x) (x >> 26)
1361 #define itype_op(x) (x >> 26)
1362 #define itype_rs(x) ((x >> 21) & 0x1f)
1363 #define itype_rt(x) ((x >> 16) & 0x1f)
1364 #define itype_immediate(x) (x & 0xffff)
1366 #define jtype_op(x) (x >> 26)
1367 #define jtype_target(x) (x & 0x03ffffff)
1369 #define rtype_op(x) (x >> 26)
1370 #define rtype_rs(x) ((x >> 21) & 0x1f)
1371 #define rtype_rt(x) ((x >> 16) & 0x1f)
1372 #define rtype_rd(x) ((x >> 11) & 0x1f)
1373 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1374 #define rtype_funct(x) (x & 0x3f)
1376 /* MicroMIPS instruction fields. */
1377 #define micromips_op(x) ((x) >> 10)
1379 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1380 bit and the size respectively of the field extracted. */
1381 #define b0s4_imm(x) ((x) & 0xf)
1382 #define b0s5_imm(x) ((x) & 0x1f)
1383 #define b0s5_reg(x) ((x) & 0x1f)
1384 #define b0s7_imm(x) ((x) & 0x7f)
1385 #define b0s10_imm(x) ((x) & 0x3ff)
1386 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1387 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1388 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1389 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1390 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1391 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1392 #define b6s4_op(x) (((x) >> 6) & 0xf)
1393 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1395 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1396 respectively of the field extracted. */
1397 #define b0s6_op(x) ((x) & 0x3f)
1398 #define b0s11_op(x) ((x) & 0x7ff)
1399 #define b0s12_imm(x) ((x) & 0xfff)
1400 #define b0s16_imm(x) ((x) & 0xffff)
1401 #define b0s26_imm(x) ((x) & 0x3ffffff)
1402 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1403 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1404 #define b12s4_op(x) (((x) >> 12) & 0xf)
1406 /* Return the size in bytes of the instruction INSN encoded in the ISA
1410 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1415 if (micromips_op (insn
) == 0x1f)
1416 return 3 * MIPS_INSN16_SIZE
;
1417 else if (((micromips_op (insn
) & 0x4) == 0x4)
1418 || ((micromips_op (insn
) & 0x7) == 0x0))
1419 return 2 * MIPS_INSN16_SIZE
;
1421 return MIPS_INSN16_SIZE
;
1423 if ((insn
& 0xf800) == 0xf000)
1424 return 2 * MIPS_INSN16_SIZE
;
1426 return MIPS_INSN16_SIZE
;
1428 return MIPS_INSN32_SIZE
;
1430 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1434 mips32_relative_offset (ULONGEST inst
)
1436 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1439 /* Determine the address of the next instruction executed after the INST
1440 floating condition branch instruction at PC. COUNT specifies the
1441 number of the floating condition bits tested by the branch. */
1444 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1445 ULONGEST inst
, CORE_ADDR pc
, int count
)
1447 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1448 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1449 int tf
= itype_rt (inst
) & 1;
1450 int mask
= (1 << count
) - 1;
1455 /* No way to handle; it'll most likely trap anyway. */
1458 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1459 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1461 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1462 pc
+= mips32_relative_offset (inst
);
1469 /* Determine where to set a single step breakpoint while considering
1470 branch prediction. */
1472 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1474 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1477 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1478 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1481 if (itype_op (inst
) >> 2 == 5)
1482 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1484 op
= (itype_op (inst
) & 0x03);
1494 goto greater_branch
;
1499 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1500 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1501 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1502 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 9
1503 && (itype_rt (inst
) & 2) == 0)
1504 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1505 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1506 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 10
1507 && (itype_rt (inst
) & 2) == 0)
1508 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1509 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1510 else if (itype_op (inst
) == 29)
1512 /* The new PC will be alternate mode. */
1516 reg
= jtype_target (inst
) << 2;
1517 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1518 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1521 pc
+= 4; /* Not a branch, next instruction is easy. */
1524 { /* This gets way messy. */
1526 /* Further subdivide into SPECIAL, REGIMM and other. */
1527 switch (op
= itype_op (inst
) & 0x07) /* Extract bits 28,27,26. */
1529 case 0: /* SPECIAL */
1530 op
= rtype_funct (inst
);
1535 /* Set PC to that address. */
1536 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1538 case 12: /* SYSCALL */
1540 struct gdbarch_tdep
*tdep
;
1542 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1543 if (tdep
->syscall_next_pc
!= NULL
)
1544 pc
= tdep
->syscall_next_pc (frame
);
1553 break; /* end SPECIAL */
1554 case 1: /* REGIMM */
1556 op
= itype_rt (inst
); /* branch condition */
1561 case 16: /* BLTZAL */
1562 case 18: /* BLTZALL */
1564 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1565 pc
+= mips32_relative_offset (inst
) + 4;
1567 pc
+= 8; /* after the delay slot */
1571 case 17: /* BGEZAL */
1572 case 19: /* BGEZALL */
1573 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1574 pc
+= mips32_relative_offset (inst
) + 4;
1576 pc
+= 8; /* after the delay slot */
1578 case 0x1c: /* BPOSGE32 */
1579 case 0x1e: /* BPOSGE64 */
1581 if (itype_rs (inst
) == 0)
1583 unsigned int pos
= (op
& 2) ? 64 : 32;
1584 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1587 /* No way to handle; it'll most likely trap anyway. */
1590 if ((get_frame_register_unsigned (frame
,
1591 dspctl
) & 0x7f) >= pos
)
1592 pc
+= mips32_relative_offset (inst
);
1597 /* All of the other instructions in the REGIMM category */
1602 break; /* end REGIMM */
1607 reg
= jtype_target (inst
) << 2;
1608 /* Upper four bits get never changed... */
1609 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1612 case 4: /* BEQ, BEQL */
1614 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1615 get_frame_register_signed (frame
, itype_rt (inst
)))
1616 pc
+= mips32_relative_offset (inst
) + 4;
1620 case 5: /* BNE, BNEL */
1622 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1623 get_frame_register_signed (frame
, itype_rt (inst
)))
1624 pc
+= mips32_relative_offset (inst
) + 4;
1628 case 6: /* BLEZ, BLEZL */
1629 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1630 pc
+= mips32_relative_offset (inst
) + 4;
1636 greater_branch
: /* BGTZ, BGTZL */
1637 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1638 pc
+= mips32_relative_offset (inst
) + 4;
1645 } /* mips32_next_pc */
1647 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1651 micromips_relative_offset7 (ULONGEST insn
)
1653 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1656 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1660 micromips_relative_offset10 (ULONGEST insn
)
1662 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1665 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1669 micromips_relative_offset16 (ULONGEST insn
)
1671 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1674 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1677 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1681 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1682 return mips_insn_size (ISA_MICROMIPS
, insn
);
1685 /* Calculate the address of the next microMIPS instruction to execute
1686 after the INSN coprocessor 1 conditional branch instruction at the
1687 address PC. COUNT denotes the number of coprocessor condition bits
1688 examined by the branch. */
1691 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1692 ULONGEST insn
, CORE_ADDR pc
, int count
)
1694 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1695 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1696 int tf
= b5s5_op (insn
>> 16) & 1;
1697 int mask
= (1 << count
) - 1;
1702 /* No way to handle; it'll most likely trap anyway. */
1705 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1706 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1708 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1709 pc
+= micromips_relative_offset16 (insn
);
1711 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1716 /* Calculate the address of the next microMIPS instruction to execute
1717 after the instruction at the address PC. */
1720 micromips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1722 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1725 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1726 pc
+= MIPS_INSN16_SIZE
;
1727 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1729 /* 48-bit instructions. */
1730 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
1731 /* No branch or jump instructions in this category. */
1732 pc
+= 2 * MIPS_INSN16_SIZE
;
1735 /* 32-bit instructions. */
1736 case 2 * MIPS_INSN16_SIZE
:
1738 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1739 pc
+= MIPS_INSN16_SIZE
;
1740 switch (micromips_op (insn
>> 16))
1742 case 0x00: /* POOL32A: bits 000000 */
1743 if (b0s6_op (insn
) == 0x3c
1744 /* POOL32Axf: bits 000000 ... 111100 */
1745 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1746 /* JALR, JALR.HB: 000000 000x111100 111100 */
1747 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1748 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
>> 16));
1751 case 0x10: /* POOL32I: bits 010000 */
1752 switch (b5s5_op (insn
>> 16))
1754 case 0x00: /* BLTZ: bits 010000 00000 */
1755 case 0x01: /* BLTZAL: bits 010000 00001 */
1756 case 0x11: /* BLTZALS: bits 010000 10001 */
1757 if (get_frame_register_signed (frame
,
1758 b0s5_reg (insn
>> 16)) < 0)
1759 pc
+= micromips_relative_offset16 (insn
);
1761 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1764 case 0x02: /* BGEZ: bits 010000 00010 */
1765 case 0x03: /* BGEZAL: bits 010000 00011 */
1766 case 0x13: /* BGEZALS: bits 010000 10011 */
1767 if (get_frame_register_signed (frame
,
1768 b0s5_reg (insn
>> 16)) >= 0)
1769 pc
+= micromips_relative_offset16 (insn
);
1771 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1774 case 0x04: /* BLEZ: bits 010000 00100 */
1775 if (get_frame_register_signed (frame
,
1776 b0s5_reg (insn
>> 16)) <= 0)
1777 pc
+= micromips_relative_offset16 (insn
);
1779 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1782 case 0x05: /* BNEZC: bits 010000 00101 */
1783 if (get_frame_register_signed (frame
,
1784 b0s5_reg (insn
>> 16)) != 0)
1785 pc
+= micromips_relative_offset16 (insn
);
1788 case 0x06: /* BGTZ: bits 010000 00110 */
1789 if (get_frame_register_signed (frame
,
1790 b0s5_reg (insn
>> 16)) > 0)
1791 pc
+= micromips_relative_offset16 (insn
);
1793 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1796 case 0x07: /* BEQZC: bits 010000 00111 */
1797 if (get_frame_register_signed (frame
,
1798 b0s5_reg (insn
>> 16)) == 0)
1799 pc
+= micromips_relative_offset16 (insn
);
1802 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1803 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1804 if (((insn
>> 16) & 0x3) == 0x0)
1805 /* BC2F, BC2T: don't know how to handle these. */
1809 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1810 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1812 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1813 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1816 /* No way to handle; it'll most likely trap anyway. */
1819 if ((get_frame_register_unsigned (frame
,
1820 dspctl
) & 0x7f) >= pos
)
1821 pc
+= micromips_relative_offset16 (insn
);
1823 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1827 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1828 /* BC1ANY2F: bits 010000 11100 xxx01 */
1829 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1830 /* BC1ANY2T: bits 010000 11101 xxx01 */
1831 if (((insn
>> 16) & 0x2) == 0x0)
1832 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
,
1833 ((insn
>> 16) & 0x1) + 1);
1836 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1837 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1838 if (((insn
>> 16) & 0x3) == 0x1)
1839 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
, 4);
1844 case 0x1d: /* JALS: bits 011101 */
1845 case 0x35: /* J: bits 110101 */
1846 case 0x3d: /* JAL: bits 111101 */
1847 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
1850 case 0x25: /* BEQ: bits 100101 */
1851 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1852 == get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1853 pc
+= micromips_relative_offset16 (insn
);
1855 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1858 case 0x2d: /* BNE: bits 101101 */
1859 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1860 != get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1861 pc
+= micromips_relative_offset16 (insn
);
1863 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1866 case 0x3c: /* JALX: bits 111100 */
1867 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
1872 /* 16-bit instructions. */
1873 case MIPS_INSN16_SIZE
:
1874 switch (micromips_op (insn
))
1876 case 0x11: /* POOL16C: bits 010001 */
1877 if ((b5s5_op (insn
) & 0x1c) == 0xc)
1878 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
1879 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
));
1880 else if (b5s5_op (insn
) == 0x18)
1881 /* JRADDIUSP: bits 010001 11000 */
1882 pc
= get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
1885 case 0x23: /* BEQZ16: bits 100011 */
1887 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
1889 if (get_frame_register_signed (frame
, rs
) == 0)
1890 pc
+= micromips_relative_offset7 (insn
);
1892 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1896 case 0x2b: /* BNEZ16: bits 101011 */
1898 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
1900 if (get_frame_register_signed (frame
, rs
) != 0)
1901 pc
+= micromips_relative_offset7 (insn
);
1903 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1907 case 0x33: /* B16: bits 110011 */
1908 pc
+= micromips_relative_offset10 (insn
);
1917 /* Decoding the next place to set a breakpoint is irregular for the
1918 mips 16 variant, but fortunately, there fewer instructions. We have
1919 to cope ith extensions for 16 bit instructions and a pair of actual
1920 32 bit instructions. We dont want to set a single step instruction
1921 on the extend instruction either. */
1923 /* Lots of mips16 instruction formats */
1924 /* Predicting jumps requires itype,ritype,i8type
1925 and their extensions extItype,extritype,extI8type. */
1926 enum mips16_inst_fmts
1928 itype
, /* 0 immediate 5,10 */
1929 ritype
, /* 1 5,3,8 */
1930 rrtype
, /* 2 5,3,3,5 */
1931 rritype
, /* 3 5,3,3,5 */
1932 rrrtype
, /* 4 5,3,3,3,2 */
1933 rriatype
, /* 5 5,3,3,1,4 */
1934 shifttype
, /* 6 5,3,3,3,2 */
1935 i8type
, /* 7 5,3,8 */
1936 i8movtype
, /* 8 5,3,3,5 */
1937 i8mov32rtype
, /* 9 5,3,5,3 */
1938 i64type
, /* 10 5,3,8 */
1939 ri64type
, /* 11 5,3,3,5 */
1940 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1941 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1942 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1943 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1944 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1945 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1946 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1947 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1948 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1949 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1951 /* I am heaping all the fields of the formats into one structure and
1952 then, only the fields which are involved in instruction extension. */
1956 unsigned int regx
; /* Function in i8 type. */
1961 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1962 for the bits which make up the immediate extension. */
1965 extended_offset (unsigned int extension
)
1969 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
1971 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
1973 value
|= extension
& 0x1f; /* Extract 4:0. */
1978 /* Only call this function if you know that this is an extendable
1979 instruction. It won't malfunction, but why make excess remote memory
1980 references? If the immediate operands get sign extended or something,
1981 do it after the extension is performed. */
1982 /* FIXME: Every one of these cases needs to worry about sign extension
1983 when the offset is to be used in relative addressing. */
1986 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1988 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1990 pc
&= 0xfffffffe; /* Clear the low order bit. */
1991 target_read_memory (pc
, buf
, 2);
1992 return extract_unsigned_integer (buf
, 2, byte_order
);
1996 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1997 unsigned int extension
,
1999 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2004 switch (insn_format
)
2011 value
= extended_offset ((extension
<< 16) | inst
);
2012 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2016 value
= inst
& 0x7ff;
2017 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2026 { /* A register identifier and an offset. */
2027 /* Most of the fields are the same as I type but the
2028 immediate value is of a different length. */
2032 value
= extended_offset ((extension
<< 16) | inst
);
2033 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2037 value
= inst
& 0xff; /* 8 bits */
2038 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2041 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2047 unsigned long value
;
2048 unsigned int nexthalf
;
2049 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2050 value
= value
<< 16;
2051 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2052 /* Low bit still set. */
2060 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2062 upk
->offset
= offset
;
2069 add_offset_16 (CORE_ADDR pc
, int offset
)
2071 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
2075 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
2076 unsigned int extension
, unsigned int insn
)
2078 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2079 int op
= (insn
>> 11);
2082 case 2: /* Branch */
2084 struct upk_mips16 upk
;
2085 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2086 pc
+= (upk
.offset
<< 1) + 2;
2089 case 3: /* JAL , JALX - Watch out, these are 32 bit
2092 struct upk_mips16 upk
;
2093 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2094 pc
= add_offset_16 (pc
, upk
.offset
);
2095 if ((insn
>> 10) & 0x01) /* Exchange mode */
2096 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2103 struct upk_mips16 upk
;
2105 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2106 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2108 pc
+= (upk
.offset
<< 1) + 2;
2115 struct upk_mips16 upk
;
2117 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2118 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2120 pc
+= (upk
.offset
<< 1) + 2;
2125 case 12: /* I8 Formats btez btnez */
2127 struct upk_mips16 upk
;
2129 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2130 /* upk.regx contains the opcode */
2131 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
2132 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2133 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2134 /* pc = add_offset_16(pc,upk.offset) ; */
2135 pc
+= (upk
.offset
<< 1) + 2;
2140 case 29: /* RR Formats JR, JALR, JALR-RA */
2142 struct upk_mips16 upk
;
2143 /* upk.fmt = rrtype; */
2148 upk
.regx
= (insn
>> 8) & 0x07;
2149 upk
.regy
= (insn
>> 5) & 0x07;
2150 if ((upk
.regy
& 1) == 0)
2151 reg
= mips_reg3_to_reg
[upk
.regx
];
2153 reg
= 31; /* Function return instruction. */
2154 pc
= get_frame_register_signed (frame
, reg
);
2161 /* This is an instruction extension. Fetch the real instruction
2162 (which follows the extension) and decode things based on
2166 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
2167 fetch_mips_16 (gdbarch
, pc
));
2180 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2182 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2183 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2184 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
2187 /* The mips_next_pc function supports single_step when the remote
2188 target monitor or stub is not developed enough to do a single_step.
2189 It works by decoding the current instruction and predicting where a
2190 branch will go. This isnt hard because all the data is available.
2191 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2193 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2195 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2197 if (mips_pc_is_mips16 (gdbarch
, pc
))
2198 return mips16_next_pc (frame
, pc
);
2199 else if (mips_pc_is_micromips (gdbarch
, pc
))
2200 return micromips_next_pc (frame
, pc
);
2202 return mips32_next_pc (frame
, pc
);
2205 struct mips_frame_cache
2208 struct trad_frame_saved_reg
*saved_regs
;
2211 /* Set a register's saved stack address in temp_saved_regs. If an
2212 address has already been set for this register, do nothing; this
2213 way we will only recognize the first save of a given register in a
2216 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2217 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2218 Strictly speaking, only the second range is used as it is only second
2219 range (the ABI instead of ISA registers) that comes into play when finding
2220 saved registers in a frame. */
2223 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2224 int regnum
, CORE_ADDR offset
)
2226 if (this_cache
!= NULL
2227 && this_cache
->saved_regs
[regnum
].addr
== -1)
2229 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2231 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2237 /* Fetch the immediate value from a MIPS16 instruction.
2238 If the previous instruction was an EXTEND, use it to extend
2239 the upper bits of the immediate value. This is a helper function
2240 for mips16_scan_prologue. */
2243 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2244 unsigned short inst
, /* current instruction */
2245 int nbits
, /* number of bits in imm field */
2246 int scale
, /* scale factor to be applied to imm */
2247 int is_signed
) /* is the imm field signed? */
2251 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2253 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2254 if (offset
& 0x8000) /* check for negative extend */
2255 offset
= 0 - (0x10000 - (offset
& 0xffff));
2256 return offset
| (inst
& 0x1f);
2260 int max_imm
= 1 << nbits
;
2261 int mask
= max_imm
- 1;
2262 int sign_bit
= max_imm
>> 1;
2264 offset
= inst
& mask
;
2265 if (is_signed
&& (offset
& sign_bit
))
2266 offset
= 0 - (max_imm
- offset
);
2267 return offset
* scale
;
2272 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2273 the associated FRAME_CACHE if not null.
2274 Return the address of the first instruction past the prologue. */
2277 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2278 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2279 struct frame_info
*this_frame
,
2280 struct mips_frame_cache
*this_cache
)
2283 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2285 long frame_offset
= 0; /* Size of stack frame. */
2286 long frame_adjust
= 0; /* Offset of FP from SP. */
2287 int frame_reg
= MIPS_SP_REGNUM
;
2288 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2289 unsigned inst
= 0; /* current instruction */
2290 unsigned entry_inst
= 0; /* the entry instruction */
2291 unsigned save_inst
= 0; /* the save instruction */
2294 int extend_bytes
= 0;
2295 int prev_extend_bytes
;
2296 CORE_ADDR end_prologue_addr
= 0;
2298 /* Can be called when there's no process, and hence when there's no
2300 if (this_frame
!= NULL
)
2301 sp
= get_frame_register_signed (this_frame
,
2302 gdbarch_num_regs (gdbarch
)
2307 if (limit_pc
> start_pc
+ 200)
2308 limit_pc
= start_pc
+ 200;
2310 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2312 /* Save the previous instruction. If it's an EXTEND, we'll extract
2313 the immediate offset extension from it in mips16_get_imm. */
2316 /* Fetch and decode the instruction. */
2317 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2320 /* Normally we ignore extend instructions. However, if it is
2321 not followed by a valid prologue instruction, then this
2322 instruction is not part of the prologue either. We must
2323 remember in this case to adjust the end_prologue_addr back
2325 if ((inst
& 0xf800) == 0xf000) /* extend */
2327 extend_bytes
= MIPS_INSN16_SIZE
;
2331 prev_extend_bytes
= extend_bytes
;
2334 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2335 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2337 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2338 if (offset
< 0) /* Negative stack adjustment? */
2339 frame_offset
-= offset
;
2341 /* Exit loop if a positive stack adjustment is found, which
2342 usually means that the stack cleanup code in the function
2343 epilogue is reached. */
2346 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2348 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2349 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2350 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2352 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2354 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2355 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2356 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2358 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2360 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2361 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2363 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2365 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2366 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2368 else if (inst
== 0x673d) /* move $s1, $sp */
2373 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2375 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2376 frame_addr
= sp
+ offset
;
2378 frame_adjust
= offset
;
2380 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2382 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2383 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2384 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2386 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2388 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2389 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2390 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2392 else if ((inst
& 0xf81f) == 0xe809
2393 && (inst
& 0x700) != 0x700) /* entry */
2394 entry_inst
= inst
; /* Save for later processing. */
2395 else if ((inst
& 0xff80) == 0x6480) /* save */
2397 save_inst
= inst
; /* Save for later processing. */
2398 if (prev_extend_bytes
) /* extend */
2399 save_inst
|= prev_inst
<< 16;
2401 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2402 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2403 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2405 /* This instruction is part of the prologue, but we don't
2406 need to do anything special to handle it. */
2410 /* This instruction is not an instruction typically found
2411 in a prologue, so we must have reached the end of the
2413 if (end_prologue_addr
== 0)
2414 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
2418 /* The entry instruction is typically the first instruction in a function,
2419 and it stores registers at offsets relative to the value of the old SP
2420 (before the prologue). But the value of the sp parameter to this
2421 function is the new SP (after the prologue has been executed). So we
2422 can't calculate those offsets until we've seen the entire prologue,
2423 and can calculate what the old SP must have been. */
2424 if (entry_inst
!= 0)
2426 int areg_count
= (entry_inst
>> 8) & 7;
2427 int sreg_count
= (entry_inst
>> 6) & 3;
2429 /* The entry instruction always subtracts 32 from the SP. */
2432 /* Now we can calculate what the SP must have been at the
2433 start of the function prologue. */
2436 /* Check if a0-a3 were saved in the caller's argument save area. */
2437 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2439 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2440 offset
+= mips_abi_regsize (gdbarch
);
2443 /* Check if the ra register was pushed on the stack. */
2445 if (entry_inst
& 0x20)
2447 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2448 offset
-= mips_abi_regsize (gdbarch
);
2451 /* Check if the s0 and s1 registers were pushed on the stack. */
2452 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2454 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2455 offset
-= mips_abi_regsize (gdbarch
);
2459 /* The SAVE instruction is similar to ENTRY, except that defined by the
2460 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2461 size of the frame is specified as an immediate field of instruction
2462 and an extended variation exists which lets additional registers and
2463 frame space to be specified. The instruction always treats registers
2464 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2465 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2467 static int args_table
[16] = {
2468 0, 0, 0, 0, 1, 1, 1, 1,
2469 2, 2, 2, 0, 3, 3, 4, -1,
2471 static int astatic_table
[16] = {
2472 0, 1, 2, 3, 0, 1, 2, 3,
2473 0, 1, 2, 4, 0, 1, 0, -1,
2475 int aregs
= (save_inst
>> 16) & 0xf;
2476 int xsregs
= (save_inst
>> 24) & 0x7;
2477 int args
= args_table
[aregs
];
2478 int astatic
= astatic_table
[aregs
];
2483 warning (_("Invalid number of argument registers encoded in SAVE."));
2488 warning (_("Invalid number of static registers encoded in SAVE."));
2492 /* For standard SAVE the frame size of 0 means 128. */
2493 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2494 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2497 frame_offset
+= frame_size
;
2499 /* Now we can calculate what the SP must have been at the
2500 start of the function prologue. */
2503 /* Check if A0-A3 were saved in the caller's argument save area. */
2504 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2506 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2507 offset
+= mips_abi_regsize (gdbarch
);
2512 /* Check if the RA register was pushed on the stack. */
2513 if (save_inst
& 0x40)
2515 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2516 offset
-= mips_abi_regsize (gdbarch
);
2519 /* Check if the S8 register was pushed on the stack. */
2522 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2523 offset
-= mips_abi_regsize (gdbarch
);
2526 /* Check if S2-S7 were pushed on the stack. */
2527 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2529 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2530 offset
-= mips_abi_regsize (gdbarch
);
2533 /* Check if the S1 register was pushed on the stack. */
2534 if (save_inst
& 0x10)
2536 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2537 offset
-= mips_abi_regsize (gdbarch
);
2539 /* Check if the S0 register was pushed on the stack. */
2540 if (save_inst
& 0x20)
2542 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2543 offset
-= mips_abi_regsize (gdbarch
);
2546 /* Check if A0-A3 were pushed on the stack. */
2547 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2549 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2550 offset
-= mips_abi_regsize (gdbarch
);
2554 if (this_cache
!= NULL
)
2557 (get_frame_register_signed (this_frame
,
2558 gdbarch_num_regs (gdbarch
) + frame_reg
)
2559 + frame_offset
- frame_adjust
);
2560 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2561 be able to get rid of the assignment below, evetually. But it's
2562 still needed for now. */
2563 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2564 + mips_regnum (gdbarch
)->pc
]
2565 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2568 /* If we didn't reach the end of the prologue when scanning the function
2569 instructions, then set end_prologue_addr to the address of the
2570 instruction immediately after the last one we scanned. */
2571 if (end_prologue_addr
== 0)
2572 end_prologue_addr
= cur_pc
;
2574 return end_prologue_addr
;
2577 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2578 Procedures that use the 32-bit instruction set are handled by the
2579 mips_insn32 unwinder. */
2581 static struct mips_frame_cache
*
2582 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2584 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2585 struct mips_frame_cache
*cache
;
2587 if ((*this_cache
) != NULL
)
2588 return (*this_cache
);
2589 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2590 (*this_cache
) = cache
;
2591 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2593 /* Analyze the function prologue. */
2595 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2596 CORE_ADDR start_addr
;
2598 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2599 if (start_addr
== 0)
2600 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2601 /* We can't analyze the prologue if we couldn't find the begining
2603 if (start_addr
== 0)
2606 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2609 /* gdbarch_sp_regnum contains the value and not the address. */
2610 trad_frame_set_value (cache
->saved_regs
,
2611 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2614 return (*this_cache
);
2618 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2619 struct frame_id
*this_id
)
2621 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2623 /* This marks the outermost frame. */
2624 if (info
->base
== 0)
2626 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2629 static struct value
*
2630 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2631 void **this_cache
, int regnum
)
2633 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2635 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2639 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2640 struct frame_info
*this_frame
, void **this_cache
)
2642 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2643 CORE_ADDR pc
= get_frame_pc (this_frame
);
2644 if (mips_pc_is_mips16 (gdbarch
, pc
))
2649 static const struct frame_unwind mips_insn16_frame_unwind
=
2652 default_frame_unwind_stop_reason
,
2653 mips_insn16_frame_this_id
,
2654 mips_insn16_frame_prev_register
,
2656 mips_insn16_frame_sniffer
2660 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2663 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2668 static const struct frame_base mips_insn16_frame_base
=
2670 &mips_insn16_frame_unwind
,
2671 mips_insn16_frame_base_address
,
2672 mips_insn16_frame_base_address
,
2673 mips_insn16_frame_base_address
2676 static const struct frame_base
*
2677 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2679 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2680 CORE_ADDR pc
= get_frame_pc (this_frame
);
2681 if (mips_pc_is_mips16 (gdbarch
, pc
))
2682 return &mips_insn16_frame_base
;
2687 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2688 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2689 interpreted directly, and then multiplied by 4. */
2692 micromips_decode_imm9 (int imm
)
2694 imm
= (imm
^ 0x100) - 0x100;
2695 if (imm
> -3 && imm
< 2)
2700 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2701 the address of the first instruction past the prologue. */
2704 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2705 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2706 struct frame_info
*this_frame
,
2707 struct mips_frame_cache
*this_cache
)
2709 CORE_ADDR end_prologue_addr
= 0;
2710 int prev_non_prologue_insn
= 0;
2711 int frame_reg
= MIPS_SP_REGNUM
;
2712 int this_non_prologue_insn
;
2713 int non_prologue_insns
= 0;
2714 long frame_offset
= 0; /* Size of stack frame. */
2715 long frame_adjust
= 0; /* Offset of FP from SP. */
2716 CORE_ADDR frame_addr
= 0; /* Value of $30, used as frame pointer. */
2719 ULONGEST insn
; /* current instruction */
2723 long v1_off
= 0; /* The assumption is LUI will replace it. */
2734 /* Can be called when there's no process, and hence when there's no
2736 if (this_frame
!= NULL
)
2737 sp
= get_frame_register_signed (this_frame
,
2738 gdbarch_num_regs (gdbarch
)
2743 if (limit_pc
> start_pc
+ 200)
2744 limit_pc
= start_pc
+ 200;
2747 /* Permit at most one non-prologue non-control-transfer instruction
2748 in the middle which may have been reordered by the compiler for
2750 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2752 this_non_prologue_insn
= 0;
2755 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2756 loc
+= MIPS_INSN16_SIZE
;
2757 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2759 /* 48-bit instructions. */
2760 case 3 * MIPS_INSN16_SIZE
:
2761 /* No prologue instructions in this category. */
2762 this_non_prologue_insn
= 1;
2763 loc
+= 2 * MIPS_INSN16_SIZE
;
2766 /* 32-bit instructions. */
2767 case 2 * MIPS_INSN16_SIZE
:
2769 insn
|= mips_fetch_instruction (gdbarch
,
2770 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
2771 loc
+= MIPS_INSN16_SIZE
;
2772 switch (micromips_op (insn
>> 16))
2774 /* Record $sp/$fp adjustment. */
2775 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2776 case 0x0: /* POOL32A: bits 000000 */
2777 case 0x16: /* POOL32S: bits 010110 */
2778 op
= b0s11_op (insn
);
2779 sreg
= b0s5_reg (insn
>> 16);
2780 treg
= b5s5_reg (insn
>> 16);
2781 dreg
= b11s5_reg (insn
);
2783 /* SUBU: bits 000000 00111010000 */
2784 /* DSUBU: bits 010110 00111010000 */
2785 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
2787 /* (D)SUBU $sp, $v1 */
2789 else if (op
!= 0x150
2790 /* ADDU: bits 000000 00101010000 */
2791 /* DADDU: bits 010110 00101010000 */
2792 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
2793 this_non_prologue_insn
= 1;
2796 case 0x8: /* POOL32B: bits 001000 */
2797 op
= b12s4_op (insn
);
2798 breg
= b0s5_reg (insn
>> 16);
2799 reglist
= sreg
= b5s5_reg (insn
>> 16);
2800 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
2801 if ((op
== 0x9 || op
== 0xc)
2802 /* SWP: bits 001000 1001 */
2803 /* SDP: bits 001000 1100 */
2804 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
2805 /* S[DW]P reg,offset($sp) */
2807 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
2808 set_reg_offset (gdbarch
, this_cache
,
2810 set_reg_offset (gdbarch
, this_cache
,
2811 sreg
+ 1, sp
+ offset
+ s
);
2813 else if ((op
== 0xd || op
== 0xf)
2814 /* SWM: bits 001000 1101 */
2815 /* SDM: bits 001000 1111 */
2816 && breg
== MIPS_SP_REGNUM
2817 /* SWM reglist,offset($sp) */
2818 && ((reglist
>= 1 && reglist
<= 9)
2819 || (reglist
>= 16 && reglist
<= 25)))
2821 int sreglist
= min(reglist
& 0xf, 8);
2823 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
2824 for (i
= 0; i
< sreglist
; i
++)
2825 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
2826 if ((reglist
& 0xf) > 8)
2827 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
2828 if ((reglist
& 0x10) == 0x10)
2829 set_reg_offset (gdbarch
, this_cache
,
2830 MIPS_RA_REGNUM
, sp
+ s
* i
++);
2833 this_non_prologue_insn
= 1;
2836 /* Record $sp/$fp adjustment. */
2837 /* Discard (D)ADDIU $gp used for PIC code. */
2838 case 0xc: /* ADDIU: bits 001100 */
2839 case 0x17: /* DADDIU: bits 010111 */
2840 sreg
= b0s5_reg (insn
>> 16);
2841 dreg
= b5s5_reg (insn
>> 16);
2842 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
2843 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
2844 /* (D)ADDIU $sp, imm */
2846 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
2847 /* (D)ADDIU $fp, $sp, imm */
2849 frame_addr
= sp
+ offset
;
2850 frame_adjust
= offset
;
2853 else if (sreg
!= 28 || dreg
!= 28)
2854 /* (D)ADDIU $gp, imm */
2855 this_non_prologue_insn
= 1;
2858 /* LUI $v1 is used for larger $sp adjustments. */
2859 /* Discard LUI $gp is used for PIC code. */
2860 case 0x10: /* POOL32I: bits 010000 */
2861 if (b5s5_op (insn
>> 16) == 0xd
2862 /* LUI: bits 010000 001101 */
2863 && b0s5_reg (insn
>> 16) == 3)
2865 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
2866 else if (b5s5_op (insn
>> 16) != 0xd
2867 /* LUI: bits 010000 001101 */
2868 || b0s5_reg (insn
>> 16) != 28)
2870 this_non_prologue_insn
= 1;
2873 /* ORI $v1 is used for larger $sp adjustments. */
2874 case 0x14: /* ORI: bits 010100 */
2875 sreg
= b0s5_reg (insn
>> 16);
2876 dreg
= b5s5_reg (insn
>> 16);
2877 if (sreg
== 3 && dreg
== 3)
2879 v1_off
|= b0s16_imm (insn
);
2881 this_non_prologue_insn
= 1;
2884 case 0x26: /* SWC1: bits 100110 */
2885 case 0x2e: /* SDC1: bits 101110 */
2886 breg
= b0s5_reg (insn
>> 16);
2887 if (breg
!= MIPS_SP_REGNUM
)
2888 /* S[DW]C1 reg,offset($sp) */
2889 this_non_prologue_insn
= 1;
2892 case 0x36: /* SD: bits 110110 */
2893 case 0x3e: /* SW: bits 111110 */
2894 breg
= b0s5_reg (insn
>> 16);
2895 sreg
= b5s5_reg (insn
>> 16);
2896 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
2897 if (breg
== MIPS_SP_REGNUM
)
2898 /* S[DW] reg,offset($sp) */
2899 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
2901 this_non_prologue_insn
= 1;
2905 this_non_prologue_insn
= 1;
2910 /* 16-bit instructions. */
2911 case MIPS_INSN16_SIZE
:
2912 switch (micromips_op (insn
))
2914 case 0x3: /* MOVE: bits 000011 */
2915 sreg
= b0s5_reg (insn
);
2916 dreg
= b5s5_reg (insn
);
2917 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
2923 else if ((sreg
& 0x1c) != 0x4)
2924 /* MOVE reg, $a0-$a3 */
2925 this_non_prologue_insn
= 1;
2928 case 0x11: /* POOL16C: bits 010001 */
2929 if (b6s4_op (insn
) == 0x5)
2930 /* SWM: bits 010001 0101 */
2932 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
2933 reglist
= b4s2_regl (insn
);
2934 for (i
= 0; i
<= reglist
; i
++)
2935 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
2936 set_reg_offset (gdbarch
, this_cache
,
2937 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
2940 this_non_prologue_insn
= 1;
2943 case 0x13: /* POOL16D: bits 010011 */
2944 if ((insn
& 0x1) == 0x1)
2945 /* ADDIUSP: bits 010011 1 */
2946 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
2947 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
2948 /* ADDIUS5: bits 010011 0 */
2949 /* ADDIUS5 $sp, imm */
2950 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
2952 this_non_prologue_insn
= 1;
2955 case 0x32: /* SWSP: bits 110010 */
2956 offset
= b0s5_imm (insn
) << 2;
2957 sreg
= b5s5_reg (insn
);
2958 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
2962 this_non_prologue_insn
= 1;
2968 frame_offset
-= sp_adj
;
2970 non_prologue_insns
+= this_non_prologue_insn
;
2971 /* Enough non-prologue insns seen or positive stack adjustment? */
2972 if (end_prologue_addr
== 0 && (non_prologue_insns
> 1 || sp_adj
> 0))
2974 end_prologue_addr
= prev_non_prologue_insn
? prev_pc
: cur_pc
;
2977 prev_non_prologue_insn
= this_non_prologue_insn
;
2981 if (this_cache
!= NULL
)
2984 (get_frame_register_signed (this_frame
,
2985 gdbarch_num_regs (gdbarch
) + frame_reg
)
2986 + frame_offset
- frame_adjust
);
2987 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2988 be able to get rid of the assignment below, evetually. But it's
2989 still needed for now. */
2990 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2991 + mips_regnum (gdbarch
)->pc
]
2992 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2995 /* If we didn't reach the end of the prologue when scanning the function
2996 instructions, then set end_prologue_addr to the address of the
2997 instruction immediately after the last one we scanned. Unless the
2998 last one looked like a non-prologue instruction (and we looked ahead),
2999 in which case use its address instead. */
3000 if (end_prologue_addr
== 0)
3001 end_prologue_addr
= prev_non_prologue_insn
? prev_pc
: cur_pc
;
3003 return end_prologue_addr
;
3006 /* Heuristic unwinder for procedures using microMIPS instructions.
3007 Procedures that use the 32-bit instruction set are handled by the
3008 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3010 static struct mips_frame_cache
*
3011 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3013 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3014 struct mips_frame_cache
*cache
;
3016 if ((*this_cache
) != NULL
)
3017 return (*this_cache
);
3019 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3020 (*this_cache
) = cache
;
3021 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3023 /* Analyze the function prologue. */
3025 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3026 CORE_ADDR start_addr
;
3028 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3029 if (start_addr
== 0)
3030 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3031 /* We can't analyze the prologue if we couldn't find the begining
3033 if (start_addr
== 0)
3036 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3039 /* gdbarch_sp_regnum contains the value and not the address. */
3040 trad_frame_set_value (cache
->saved_regs
,
3041 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3044 return (*this_cache
);
3048 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3049 struct frame_id
*this_id
)
3051 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3053 /* This marks the outermost frame. */
3054 if (info
->base
== 0)
3056 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3059 static struct value
*
3060 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3061 void **this_cache
, int regnum
)
3063 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3065 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3069 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3070 struct frame_info
*this_frame
, void **this_cache
)
3072 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3073 CORE_ADDR pc
= get_frame_pc (this_frame
);
3075 if (mips_pc_is_micromips (gdbarch
, pc
))
3080 static const struct frame_unwind mips_micro_frame_unwind
=
3083 default_frame_unwind_stop_reason
,
3084 mips_micro_frame_this_id
,
3085 mips_micro_frame_prev_register
,
3087 mips_micro_frame_sniffer
3091 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3094 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3099 static const struct frame_base mips_micro_frame_base
=
3101 &mips_micro_frame_unwind
,
3102 mips_micro_frame_base_address
,
3103 mips_micro_frame_base_address
,
3104 mips_micro_frame_base_address
3107 static const struct frame_base
*
3108 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3110 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3111 CORE_ADDR pc
= get_frame_pc (this_frame
);
3113 if (mips_pc_is_micromips (gdbarch
, pc
))
3114 return &mips_micro_frame_base
;
3119 /* Mark all the registers as unset in the saved_regs array
3120 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3123 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3125 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3129 const int num_regs
= gdbarch_num_regs (gdbarch
);
3132 for (i
= 0; i
< num_regs
; i
++)
3134 this_cache
->saved_regs
[i
].addr
= -1;
3139 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3140 the associated FRAME_CACHE if not null.
3141 Return the address of the first instruction past the prologue. */
3144 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3145 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3146 struct frame_info
*this_frame
,
3147 struct mips_frame_cache
*this_cache
)
3150 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3154 int frame_reg
= MIPS_SP_REGNUM
;
3156 CORE_ADDR end_prologue_addr
= 0;
3157 int seen_sp_adjust
= 0;
3158 int load_immediate_bytes
= 0;
3159 int in_delay_slot
= 0;
3160 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3162 /* Can be called when there's no process, and hence when there's no
3164 if (this_frame
!= NULL
)
3165 sp
= get_frame_register_signed (this_frame
,
3166 gdbarch_num_regs (gdbarch
)
3171 if (limit_pc
> start_pc
+ 200)
3172 limit_pc
= start_pc
+ 200;
3177 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3179 unsigned long inst
, high_word
, low_word
;
3182 /* Fetch the instruction. */
3183 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3186 /* Save some code by pre-extracting some useful fields. */
3187 high_word
= (inst
>> 16) & 0xffff;
3188 low_word
= inst
& 0xffff;
3189 reg
= high_word
& 0x1f;
3191 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3192 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3193 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3195 if (low_word
& 0x8000) /* Negative stack adjustment? */
3196 frame_offset
+= 0x10000 - low_word
;
3198 /* Exit loop if a positive stack adjustment is found, which
3199 usually means that the stack cleanup code in the function
3200 epilogue is reached. */
3204 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3205 && !regsize_is_64_bits
)
3207 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3209 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3210 && regsize_is_64_bits
)
3212 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3213 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3215 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3217 /* Old gcc frame, r30 is virtual frame pointer. */
3218 if ((long) low_word
!= frame_offset
)
3219 frame_addr
= sp
+ low_word
;
3220 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3222 unsigned alloca_adjust
;
3225 frame_addr
= get_frame_register_signed
3226 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3228 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
3229 if (alloca_adjust
> 0)
3231 /* FP > SP + frame_size. This may be because of
3232 an alloca or somethings similar. Fix sp to
3233 "pre-alloca" value, and try again. */
3234 sp
+= alloca_adjust
;
3235 /* Need to reset the status of all registers. Otherwise,
3236 we will hit a guard that prevents the new address
3237 for each register to be recomputed during the second
3239 reset_saved_regs (gdbarch
, this_cache
);
3244 /* move $30,$sp. With different versions of gas this will be either
3245 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3246 Accept any one of these. */
3247 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3249 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3250 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3252 unsigned alloca_adjust
;
3255 frame_addr
= get_frame_register_signed
3256 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3258 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3259 if (alloca_adjust
> 0)
3261 /* FP > SP + frame_size. This may be because of
3262 an alloca or somethings similar. Fix sp to
3263 "pre-alloca" value, and try again. */
3265 /* Need to reset the status of all registers. Otherwise,
3266 we will hit a guard that prevents the new address
3267 for each register to be recomputed during the second
3269 reset_saved_regs (gdbarch
, this_cache
);
3274 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3275 && !regsize_is_64_bits
)
3277 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
3279 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3280 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3281 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3282 || high_word
== 0x3c1c /* lui $gp,n */
3283 || high_word
== 0x279c /* addiu $gp,$gp,n */
3284 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3285 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3288 /* These instructions are part of the prologue, but we don't
3289 need to do anything special to handle them. */
3291 /* The instructions below load $at or $t0 with an immediate
3292 value in preparation for a stack adjustment via
3293 subu $sp,$sp,[$at,$t0]. These instructions could also
3294 initialize a local variable, so we accept them only before
3295 a stack adjustment instruction was seen. */
3296 else if (!seen_sp_adjust
3297 && (high_word
== 0x3c01 /* lui $at,n */
3298 || high_word
== 0x3c08 /* lui $t0,n */
3299 || high_word
== 0x3421 /* ori $at,$at,n */
3300 || high_word
== 0x3508 /* ori $t0,$t0,n */
3301 || high_word
== 0x3401 /* ori $at,$zero,n */
3302 || high_word
== 0x3408 /* ori $t0,$zero,n */
3305 if (end_prologue_addr
== 0)
3306 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3310 /* This instruction is not an instruction typically found
3311 in a prologue, so we must have reached the end of the
3313 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
3314 loop now? Why would we need to continue scanning the function
3316 if (end_prologue_addr
== 0)
3317 end_prologue_addr
= cur_pc
;
3319 /* Check for branches and jumps. For now, only jump to
3320 register are caught (i.e. returns). */
3321 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
3325 /* If the previous instruction was a jump, we must have reached
3326 the end of the prologue by now. Stop scanning so that we do
3327 not go past the function return. */
3332 if (this_cache
!= NULL
)
3335 (get_frame_register_signed (this_frame
,
3336 gdbarch_num_regs (gdbarch
) + frame_reg
)
3338 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3339 this assignment below, eventually. But it's still needed
3341 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3342 + mips_regnum (gdbarch
)->pc
]
3343 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3347 /* If we didn't reach the end of the prologue when scanning the function
3348 instructions, then set end_prologue_addr to the address of the
3349 instruction immediately after the last one we scanned. */
3350 /* brobecker/2004-10-10: I don't think this would ever happen, but
3351 we may as well be careful and do our best if we have a null
3352 end_prologue_addr. */
3353 if (end_prologue_addr
== 0)
3354 end_prologue_addr
= cur_pc
;
3356 /* In a frameless function, we might have incorrectly
3357 skipped some load immediate instructions. Undo the skipping
3358 if the load immediate was not followed by a stack adjustment. */
3359 if (load_immediate_bytes
&& !seen_sp_adjust
)
3360 end_prologue_addr
-= load_immediate_bytes
;
3362 return end_prologue_addr
;
3365 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3366 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3367 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3368 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3370 static struct mips_frame_cache
*
3371 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3373 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3374 struct mips_frame_cache
*cache
;
3376 if ((*this_cache
) != NULL
)
3377 return (*this_cache
);
3379 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3380 (*this_cache
) = cache
;
3381 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3383 /* Analyze the function prologue. */
3385 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3386 CORE_ADDR start_addr
;
3388 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3389 if (start_addr
== 0)
3390 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3391 /* We can't analyze the prologue if we couldn't find the begining
3393 if (start_addr
== 0)
3396 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3399 /* gdbarch_sp_regnum contains the value and not the address. */
3400 trad_frame_set_value (cache
->saved_regs
,
3401 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3404 return (*this_cache
);
3408 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3409 struct frame_id
*this_id
)
3411 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3413 /* This marks the outermost frame. */
3414 if (info
->base
== 0)
3416 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3419 static struct value
*
3420 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3421 void **this_cache
, int regnum
)
3423 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3425 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3429 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3430 struct frame_info
*this_frame
, void **this_cache
)
3432 CORE_ADDR pc
= get_frame_pc (this_frame
);
3433 if (mips_pc_is_mips (pc
))
3438 static const struct frame_unwind mips_insn32_frame_unwind
=
3441 default_frame_unwind_stop_reason
,
3442 mips_insn32_frame_this_id
,
3443 mips_insn32_frame_prev_register
,
3445 mips_insn32_frame_sniffer
3449 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3452 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3457 static const struct frame_base mips_insn32_frame_base
=
3459 &mips_insn32_frame_unwind
,
3460 mips_insn32_frame_base_address
,
3461 mips_insn32_frame_base_address
,
3462 mips_insn32_frame_base_address
3465 static const struct frame_base
*
3466 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3468 CORE_ADDR pc
= get_frame_pc (this_frame
);
3469 if (mips_pc_is_mips (pc
))
3470 return &mips_insn32_frame_base
;
3475 static struct trad_frame_cache
*
3476 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3479 CORE_ADDR start_addr
;
3480 CORE_ADDR stack_addr
;
3481 struct trad_frame_cache
*this_trad_cache
;
3482 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3483 int num_regs
= gdbarch_num_regs (gdbarch
);
3485 if ((*this_cache
) != NULL
)
3486 return (*this_cache
);
3487 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3488 (*this_cache
) = this_trad_cache
;
3490 /* The return address is in the link register. */
3491 trad_frame_set_reg_realreg (this_trad_cache
,
3492 gdbarch_pc_regnum (gdbarch
),
3493 num_regs
+ MIPS_RA_REGNUM
);
3495 /* Frame ID, since it's a frameless / stackless function, no stack
3496 space is allocated and SP on entry is the current SP. */
3497 pc
= get_frame_pc (this_frame
);
3498 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3499 stack_addr
= get_frame_register_signed (this_frame
,
3500 num_regs
+ MIPS_SP_REGNUM
);
3501 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3503 /* Assume that the frame's base is the same as the
3505 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3507 return this_trad_cache
;
3511 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3512 struct frame_id
*this_id
)
3514 struct trad_frame_cache
*this_trad_cache
3515 = mips_stub_frame_cache (this_frame
, this_cache
);
3516 trad_frame_get_id (this_trad_cache
, this_id
);
3519 static struct value
*
3520 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3521 void **this_cache
, int regnum
)
3523 struct trad_frame_cache
*this_trad_cache
3524 = mips_stub_frame_cache (this_frame
, this_cache
);
3525 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3529 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3530 struct frame_info
*this_frame
, void **this_cache
)
3533 struct obj_section
*s
;
3534 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3535 struct minimal_symbol
*msym
;
3537 /* Use the stub unwinder for unreadable code. */
3538 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3541 if (in_plt_section (pc
, NULL
))
3544 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
3545 s
= find_pc_section (pc
);
3548 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
3549 ".MIPS.stubs") == 0)
3552 /* Calling a PIC function from a non-PIC function passes through a
3553 stub. The stub for foo is named ".pic.foo". */
3554 msym
= lookup_minimal_symbol_by_pc (pc
);
3556 && SYMBOL_LINKAGE_NAME (msym
) != NULL
3557 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
3563 static const struct frame_unwind mips_stub_frame_unwind
=
3566 default_frame_unwind_stop_reason
,
3567 mips_stub_frame_this_id
,
3568 mips_stub_frame_prev_register
,
3570 mips_stub_frame_sniffer
3574 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3577 struct trad_frame_cache
*this_trad_cache
3578 = mips_stub_frame_cache (this_frame
, this_cache
);
3579 return trad_frame_get_this_base (this_trad_cache
);
3582 static const struct frame_base mips_stub_frame_base
=
3584 &mips_stub_frame_unwind
,
3585 mips_stub_frame_base_address
,
3586 mips_stub_frame_base_address
,
3587 mips_stub_frame_base_address
3590 static const struct frame_base
*
3591 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3593 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3594 return &mips_stub_frame_base
;
3599 /* mips_addr_bits_remove - remove useless address bits */
3602 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3604 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3606 if (is_compact_addr (addr
))
3607 addr
= unmake_compact_addr (addr
);
3609 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3610 /* This hack is a work-around for existing boards using PMON, the
3611 simulator, and any other 64-bit targets that doesn't have true
3612 64-bit addressing. On these targets, the upper 32 bits of
3613 addresses are ignored by the hardware. Thus, the PC or SP are
3614 likely to have been sign extended to all 1s by instruction
3615 sequences that load 32-bit addresses. For example, a typical
3616 piece of code that loads an address is this:
3618 lui $r2, <upper 16 bits>
3619 ori $r2, <lower 16 bits>
3621 But the lui sign-extends the value such that the upper 32 bits
3622 may be all 1s. The workaround is simply to mask off these
3623 bits. In the future, gcc may be changed to support true 64-bit
3624 addressing, and this masking will have to be disabled. */
3625 return addr
&= 0xffffffffUL
;
3631 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3632 instruction and ending with a SC/SCD instruction. If such a sequence
3633 is found, attempt to step through it. A breakpoint is placed at the end of
3636 /* Instructions used during single-stepping of atomic sequences, standard
3638 #define LL_OPCODE 0x30
3639 #define LLD_OPCODE 0x34
3640 #define SC_OPCODE 0x38
3641 #define SCD_OPCODE 0x3c
3644 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3645 struct address_space
*aspace
, CORE_ADDR pc
)
3647 CORE_ADDR breaks
[2] = {-1, -1};
3649 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3653 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3654 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3656 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3657 /* Assume all atomic sequences start with a ll/lld instruction. */
3658 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3661 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3663 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3666 loc
+= MIPS_INSN32_SIZE
;
3667 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3669 /* Assume that there is at most one branch in the atomic
3670 sequence. If a branch is found, put a breakpoint in its
3671 destination address. */
3672 switch (itype_op (insn
))
3674 case 0: /* SPECIAL */
3675 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3676 return 0; /* fallback to the standard single-step code. */
3678 case 1: /* REGIMM */
3679 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3680 || ((itype_rt (insn
) & 0x1e) == 0
3681 && itype_rs (insn
) == 0)); /* BPOSGE* */
3685 return 0; /* fallback to the standard single-step code. */
3692 case 22: /* BLEZL */
3693 case 23: /* BGTTL */
3697 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3698 && (itype_rt (insn
) & 0x2) == 0);
3699 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3704 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3709 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3710 if (last_breakpoint
>= 1)
3711 return 0; /* More than one branch found, fallback to the
3712 standard single-step code. */
3713 breaks
[1] = branch_bp
;
3717 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3721 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3722 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3725 loc
+= MIPS_INSN32_SIZE
;
3727 /* Insert a breakpoint right after the end of the atomic sequence. */
3730 /* Check for duplicated breakpoints. Check also for a breakpoint
3731 placed (branch instruction's destination) in the atomic sequence. */
3732 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3733 last_breakpoint
= 0;
3735 /* Effectively inserts the breakpoints. */
3736 for (index
= 0; index
<= last_breakpoint
; index
++)
3737 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3743 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3744 struct address_space
*aspace
,
3747 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3748 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3749 CORE_ADDR breaks
[2] = {-1, -1};
3750 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3757 /* Assume all atomic sequences start with a ll/lld instruction. */
3758 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3759 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
3761 loc
+= MIPS_INSN16_SIZE
;
3763 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3764 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
3766 loc
+= MIPS_INSN16_SIZE
;
3768 /* Assume all atomic sequences end with an sc/scd instruction. Assume
3769 that no atomic sequence is longer than "atomic_sequence_length"
3771 for (insn_count
= 0;
3772 !sc_found
&& insn_count
< atomic_sequence_length
;
3777 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3778 loc
+= MIPS_INSN16_SIZE
;
3780 /* Assume that there is at most one conditional branch in the
3781 atomic sequence. If a branch is found, put a breakpoint in
3782 its destination address. */
3783 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3785 /* 48-bit instructions. */
3786 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
3787 loc
+= 2 * MIPS_INSN16_SIZE
;
3790 /* 32-bit instructions. */
3791 case 2 * MIPS_INSN16_SIZE
:
3792 switch (micromips_op (insn
))
3794 case 0x10: /* POOL32I: bits 010000 */
3795 if ((b5s5_op (insn
) & 0x18) != 0x0
3796 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
3797 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
3798 && (b5s5_op (insn
) & 0x1d) != 0x11
3799 /* BLTZALS, BGEZALS: bits 010000 100x1 */
3800 && ((b5s5_op (insn
) & 0x1e) != 0x14
3801 || (insn
& 0x3) != 0x0)
3802 /* BC2F, BC2T: bits 010000 1010x xxx00 */
3803 && (b5s5_op (insn
) & 0x1e) != 0x1a
3804 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
3805 && ((b5s5_op (insn
) & 0x1e) != 0x1c
3806 || (insn
& 0x3) != 0x0)
3807 /* BC1F, BC1T: bits 010000 1110x xxx00 */
3808 && ((b5s5_op (insn
) & 0x1c) != 0x1c
3809 || (insn
& 0x3) != 0x1))
3810 /* BC1ANY*: bits 010000 111xx xxx01 */
3814 case 0x25: /* BEQ: bits 100101 */
3815 case 0x2d: /* BNE: bits 101101 */
3817 insn
|= mips_fetch_instruction (gdbarch
,
3818 ISA_MICROMIPS
, loc
, NULL
);
3819 branch_bp
= (loc
+ MIPS_INSN16_SIZE
3820 + micromips_relative_offset16 (insn
));
3824 case 0x00: /* POOL32A: bits 000000 */
3826 insn
|= mips_fetch_instruction (gdbarch
,
3827 ISA_MICROMIPS
, loc
, NULL
);
3828 if (b0s6_op (insn
) != 0x3c
3829 /* POOL32Axf: bits 000000 ... 111100 */
3830 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
3831 /* JALR, JALR.HB: 000000 000x111100 111100 */
3832 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
3836 case 0x1d: /* JALS: bits 011101 */
3837 case 0x35: /* J: bits 110101 */
3838 case 0x3d: /* JAL: bits 111101 */
3839 case 0x3c: /* JALX: bits 111100 */
3840 return 0; /* Fall back to the standard single-step code. */
3842 case 0x18: /* POOL32C: bits 011000 */
3843 if ((b12s4_op (insn
) & 0xb) == 0xb)
3844 /* SC, SCD: bits 011000 1x11 */
3848 loc
+= MIPS_INSN16_SIZE
;
3851 /* 16-bit instructions. */
3852 case MIPS_INSN16_SIZE
:
3853 switch (micromips_op (insn
))
3855 case 0x23: /* BEQZ16: bits 100011 */
3856 case 0x2b: /* BNEZ16: bits 101011 */
3857 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
3861 case 0x11: /* POOL16C: bits 010001 */
3862 if ((b5s5_op (insn
) & 0x1c) != 0xc
3863 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
3864 && b5s5_op (insn
) != 0x18)
3865 /* JRADDIUSP: bits 010001 11000 */
3867 return 0; /* Fall back to the standard single-step code. */
3869 case 0x33: /* B16: bits 110011 */
3870 return 0; /* Fall back to the standard single-step code. */
3876 if (last_breakpoint
>= 1)
3877 return 0; /* More than one branch found, fallback to the
3878 standard single-step code. */
3879 breaks
[1] = branch_bp
;
3886 /* Insert a breakpoint right after the end of the atomic sequence. */
3889 /* Check for duplicated breakpoints. Check also for a breakpoint
3890 placed (branch instruction's destination) in the atomic sequence */
3891 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3892 last_breakpoint
= 0;
3894 /* Effectively inserts the breakpoints. */
3895 for (index
= 0; index
<= last_breakpoint
; index
++)
3896 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3902 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3903 struct address_space
*aspace
, CORE_ADDR pc
)
3905 if (mips_pc_is_mips (pc
))
3906 return mips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
3907 else if (mips_pc_is_micromips (gdbarch
, pc
))
3908 return micromips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
3913 /* mips_software_single_step() is called just before we want to resume
3914 the inferior, if we want to single-step it but there is no hardware
3915 or kernel single-step support (MIPS on GNU/Linux for example). We find
3916 the target of the coming instruction and breakpoint it. */
3919 mips_software_single_step (struct frame_info
*frame
)
3921 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3922 struct address_space
*aspace
= get_frame_address_space (frame
);
3923 CORE_ADDR pc
, next_pc
;
3925 pc
= get_frame_pc (frame
);
3926 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
3929 next_pc
= mips_next_pc (frame
, pc
);
3931 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
3935 /* Test whether the PC points to the return instruction at the
3936 end of a function. */
3939 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3944 /* This used to check for MIPS16, but this piece of code is never
3945 called for MIPS16 functions. And likewise microMIPS ones. */
3946 gdb_assert (mips_pc_is_mips (pc
));
3948 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
3950 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
3954 /* This fencepost looks highly suspicious to me. Removing it also
3955 seems suspicious as it could affect remote debugging across serial
3959 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3965 struct inferior
*inf
;
3967 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
3969 fence
= start_pc
- heuristic_fence_post
;
3973 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
3974 fence
= VM_MIN_ADDRESS
;
3976 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
3978 inf
= current_inferior ();
3980 /* Search back for previous return. */
3981 for (start_pc
-= instlen
;; start_pc
-= instlen
)
3982 if (start_pc
< fence
)
3984 /* It's not clear to me why we reach this point when
3985 stop_soon, but with this test, at least we
3986 don't print out warnings for every child forked (eg, on
3987 decstation). 22apr93 rich@cygnus.com. */
3988 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
3990 static int blurb_printed
= 0;
3992 warning (_("GDB can't find the start of the function at %s."),
3993 paddress (gdbarch
, pc
));
3997 /* This actually happens frequently in embedded
3998 development, when you first connect to a board
3999 and your stack pointer and pc are nowhere in
4000 particular. This message needs to give people
4001 in that situation enough information to
4002 determine that it's no big deal. */
4003 printf_filtered ("\n\
4004 GDB is unable to find the start of the function at %s\n\
4005 and thus can't determine the size of that function's stack frame.\n\
4006 This means that GDB may be unable to access that stack frame, or\n\
4007 the frames below it.\n\
4008 This problem is most likely caused by an invalid program counter or\n\
4010 However, if you think GDB should simply search farther back\n\
4011 from %s for code which looks like the beginning of a\n\
4012 function, you can increase the range of the search using the `set\n\
4013 heuristic-fence-post' command.\n",
4014 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4021 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4023 unsigned short inst
;
4025 /* On MIPS16, any one of the following is likely to be the
4026 start of a function:
4032 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4033 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4034 if ((inst
& 0xff80) == 0x6480) /* save */
4036 if (start_pc
- instlen
>= fence
)
4038 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4039 start_pc
- instlen
, NULL
);
4040 if ((inst
& 0xf800) == 0xf000) /* extend */
4041 start_pc
-= instlen
;
4045 else if (((inst
& 0xf81f) == 0xe809
4046 && (inst
& 0x700) != 0x700) /* entry */
4047 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4048 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4049 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4051 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4052 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4057 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4065 /* On microMIPS, any one of the following is likely to be the
4066 start of a function:
4070 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4071 switch (micromips_op (insn
))
4073 case 0xc: /* ADDIU: bits 001100 */
4074 case 0x17: /* DADDIU: bits 010111 */
4075 sreg
= b0s5_reg (insn
);
4076 dreg
= b5s5_reg (insn
);
4078 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4079 pc
+ MIPS_INSN16_SIZE
, NULL
);
4080 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4081 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4082 /* (D)ADDIU $sp, imm */
4087 case 0x10: /* POOL32I: bits 010000 */
4088 if (b5s5_op (insn
) == 0xd
4089 /* LUI: bits 010000 001101 */
4090 && b0s5_reg (insn
>> 16) == 28)
4095 case 0x13: /* POOL16D: bits 010011 */
4096 if ((insn
& 0x1) == 0x1)
4097 /* ADDIUSP: bits 010011 1 */
4099 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4105 /* ADDIUS5: bits 010011 0 */
4107 dreg
= b5s5_reg (insn
);
4108 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4109 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4110 /* ADDIUS5 $sp, -imm */
4118 else if (mips_about_to_return (gdbarch
, start_pc
))
4120 /* Skip return and its delay slot. */
4121 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4128 struct mips_objfile_private
4134 /* According to the current ABI, should the type be passed in a
4135 floating-point register (assuming that there is space)? When there
4136 is no FPU, FP are not even considered as possible candidates for
4137 FP registers and, consequently this returns false - forces FP
4138 arguments into integer registers. */
4141 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4142 struct type
*arg_type
)
4144 return ((typecode
== TYPE_CODE_FLT
4145 || (MIPS_EABI (gdbarch
)
4146 && (typecode
== TYPE_CODE_STRUCT
4147 || typecode
== TYPE_CODE_UNION
)
4148 && TYPE_NFIELDS (arg_type
) == 1
4149 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4151 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4154 /* On o32, argument passing in GPRs depends on the alignment of the type being
4155 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4158 mips_type_needs_double_align (struct type
*type
)
4160 enum type_code typecode
= TYPE_CODE (type
);
4162 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4164 else if (typecode
== TYPE_CODE_STRUCT
)
4166 if (TYPE_NFIELDS (type
) < 1)
4168 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4170 else if (typecode
== TYPE_CODE_UNION
)
4174 n
= TYPE_NFIELDS (type
);
4175 for (i
= 0; i
< n
; i
++)
4176 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4183 /* Adjust the address downward (direction of stack growth) so that it
4184 is correctly aligned for a new stack frame. */
4186 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4188 return align_down (addr
, 16);
4191 /* Implement the "push_dummy_code" gdbarch method. */
4194 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4195 CORE_ADDR funaddr
, struct value
**args
,
4196 int nargs
, struct type
*value_type
,
4197 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4198 struct regcache
*regcache
)
4201 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4203 /* Reserve enough room on the stack for our breakpoint instruction. */
4204 *bp_addr
= sp
- sizeof (nop_insn
);
4206 /* The breakpoint layer automatically adjusts the address of
4207 breakpoints inserted in a branch delay slot. With enough
4208 bad luck, the 4 bytes located just before our breakpoint
4209 instruction could look like a branch instruction, and thus
4210 trigger the adjustement, and break the function call entirely.
4211 So, we reserve those 4 bytes and write a nop instruction
4212 to prevent that from happening. */
4213 nop_addr
= *bp_addr
- sizeof (nop_insn
);
4214 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4215 sp
= mips_frame_align (gdbarch
, nop_addr
);
4217 /* Inferior resumes at the function entry point. */
4224 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4225 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4226 int nargs
, struct value
**args
, CORE_ADDR sp
,
4227 int struct_return
, CORE_ADDR struct_addr
)
4233 int stack_offset
= 0;
4234 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4235 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4236 int regsize
= mips_abi_regsize (gdbarch
);
4238 /* For shared libraries, "t9" needs to point at the function
4240 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4242 /* Set the return address register to point to the entry point of
4243 the program, where a breakpoint lies in wait. */
4244 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4246 /* First ensure that the stack and structure return address (if any)
4247 are properly aligned. The stack has to be at least 64-bit
4248 aligned even on 32-bit machines, because doubles must be 64-bit
4249 aligned. For n32 and n64, stack frames need to be 128-bit
4250 aligned, so we round to this widest known alignment. */
4252 sp
= align_down (sp
, 16);
4253 struct_addr
= align_down (struct_addr
, 16);
4255 /* Now make space on the stack for the args. We allocate more
4256 than necessary for EABI, because the first few arguments are
4257 passed in registers, but that's OK. */
4258 for (argnum
= 0; argnum
< nargs
; argnum
++)
4259 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
4260 sp
-= align_up (len
, 16);
4263 fprintf_unfiltered (gdb_stdlog
,
4264 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4265 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4267 /* Initialize the integer and float register pointers. */
4268 argreg
= MIPS_A0_REGNUM
;
4269 float_argreg
= mips_fpa0_regnum (gdbarch
);
4271 /* The struct_return pointer occupies the first parameter-passing reg. */
4275 fprintf_unfiltered (gdb_stdlog
,
4276 "mips_eabi_push_dummy_call: "
4277 "struct_return reg=%d %s\n",
4278 argreg
, paddress (gdbarch
, struct_addr
));
4279 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4282 /* Now load as many as possible of the first arguments into
4283 registers, and push the rest onto the stack. Loop thru args
4284 from first to last. */
4285 for (argnum
= 0; argnum
< nargs
; argnum
++)
4287 const gdb_byte
*val
;
4288 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4289 struct value
*arg
= args
[argnum
];
4290 struct type
*arg_type
= check_typedef (value_type (arg
));
4291 int len
= TYPE_LENGTH (arg_type
);
4292 enum type_code typecode
= TYPE_CODE (arg_type
);
4295 fprintf_unfiltered (gdb_stdlog
,
4296 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4297 argnum
+ 1, len
, (int) typecode
);
4299 /* Function pointer arguments to mips16 code need to be made into
4301 if (typecode
== TYPE_CODE_PTR
4302 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4304 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4306 if (mips_pc_is_mips (addr
))
4307 val
= value_contents (arg
);
4310 store_signed_integer (valbuf
, len
, byte_order
,
4311 make_compact_addr (addr
));
4315 /* The EABI passes structures that do not fit in a register by
4317 else if (len
> regsize
4318 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4320 store_unsigned_integer (valbuf
, regsize
, byte_order
,
4321 value_address (arg
));
4322 typecode
= TYPE_CODE_PTR
;
4326 fprintf_unfiltered (gdb_stdlog
, " push");
4329 val
= value_contents (arg
);
4331 /* 32-bit ABIs always start floating point arguments in an
4332 even-numbered floating point register. Round the FP register
4333 up before the check to see if there are any FP registers
4334 left. Non MIPS_EABI targets also pass the FP in the integer
4335 registers so also round up normal registers. */
4336 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4338 if ((float_argreg
& 1))
4342 /* Floating point arguments passed in registers have to be
4343 treated specially. On 32-bit architectures, doubles
4344 are passed in register pairs; the even register gets
4345 the low word, and the odd register gets the high word.
4346 On non-EABI processors, the first two floating point arguments are
4347 also copied to general registers, because MIPS16 functions
4348 don't use float registers for arguments. This duplication of
4349 arguments in general registers can't hurt non-MIPS16 functions
4350 because those registers are normally skipped. */
4351 /* MIPS_EABI squeezes a struct that contains a single floating
4352 point value into an FP register instead of pushing it onto the
4354 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4355 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4357 /* EABI32 will pass doubles in consecutive registers, even on
4358 64-bit cores. At one time, we used to check the size of
4359 `float_argreg' to determine whether or not to pass doubles
4360 in consecutive registers, but this is not sufficient for
4361 making the ABI determination. */
4362 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4364 int low_offset
= gdbarch_byte_order (gdbarch
)
4365 == BFD_ENDIAN_BIG
? 4 : 0;
4368 /* Write the low word of the double to the even register(s). */
4369 regval
= extract_signed_integer (val
+ low_offset
,
4372 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4373 float_argreg
, phex (regval
, 4));
4374 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4376 /* Write the high word of the double to the odd register(s). */
4377 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4380 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4381 float_argreg
, phex (regval
, 4));
4382 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4386 /* This is a floating point value that fits entirely
4387 in a single register. */
4388 /* On 32 bit ABI's the float_argreg is further adjusted
4389 above to ensure that it is even register aligned. */
4390 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4392 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4393 float_argreg
, phex (regval
, len
));
4394 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4399 /* Copy the argument to general registers or the stack in
4400 register-sized pieces. Large arguments are split between
4401 registers and stack. */
4402 /* Note: structs whose size is not a multiple of regsize
4403 are treated specially: Irix cc passes
4404 them in registers where gcc sometimes puts them on the
4405 stack. For maximum compatibility, we will put them in
4407 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
4409 /* Note: Floating-point values that didn't fit into an FP
4410 register are only written to memory. */
4413 /* Remember if the argument was written to the stack. */
4414 int stack_used_p
= 0;
4415 int partial_len
= (len
< regsize
? len
: regsize
);
4418 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4421 /* Write this portion of the argument to the stack. */
4422 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4424 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4426 /* Should shorter than int integer values be
4427 promoted to int before being stored? */
4428 int longword_offset
= 0;
4431 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4434 && (typecode
== TYPE_CODE_INT
4435 || typecode
== TYPE_CODE_PTR
4436 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4437 longword_offset
= regsize
- len
;
4438 else if ((typecode
== TYPE_CODE_STRUCT
4439 || typecode
== TYPE_CODE_UNION
)
4440 && TYPE_LENGTH (arg_type
) < regsize
)
4441 longword_offset
= regsize
- len
;
4446 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4447 paddress (gdbarch
, stack_offset
));
4448 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4449 paddress (gdbarch
, longword_offset
));
4452 addr
= sp
+ stack_offset
+ longword_offset
;
4457 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4458 paddress (gdbarch
, addr
));
4459 for (i
= 0; i
< partial_len
; i
++)
4461 fprintf_unfiltered (gdb_stdlog
, "%02x",
4465 write_memory (addr
, val
, partial_len
);
4468 /* Note!!! This is NOT an else clause. Odd sized
4469 structs may go thru BOTH paths. Floating point
4470 arguments will not. */
4471 /* Write this portion of the argument to a general
4472 purpose register. */
4473 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4474 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4477 extract_signed_integer (val
, partial_len
, byte_order
);
4480 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4482 phex (regval
, regsize
));
4483 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4490 /* Compute the offset into the stack at which we will
4491 copy the next parameter.
4493 In the new EABI (and the NABI32), the stack_offset
4494 only needs to be adjusted when it has been used. */
4497 stack_offset
+= align_up (partial_len
, regsize
);
4501 fprintf_unfiltered (gdb_stdlog
, "\n");
4504 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4506 /* Return adjusted stack pointer. */
4510 /* Determine the return value convention being used. */
4512 static enum return_value_convention
4513 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4514 struct type
*type
, struct regcache
*regcache
,
4515 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4517 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4518 int fp_return_type
= 0;
4519 int offset
, regnum
, xfer
;
4521 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4522 return RETURN_VALUE_STRUCT_CONVENTION
;
4524 /* Floating point type? */
4525 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4527 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4529 /* Structs with a single field of float type
4530 are returned in a floating point register. */
4531 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4532 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4533 && TYPE_NFIELDS (type
) == 1)
4535 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4537 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4544 /* A floating-point value belongs in the least significant part
4547 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4548 regnum
= mips_regnum (gdbarch
)->fp0
;
4552 /* An integer value goes in V0/V1. */
4554 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4555 regnum
= MIPS_V0_REGNUM
;
4558 offset
< TYPE_LENGTH (type
);
4559 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4561 xfer
= mips_abi_regsize (gdbarch
);
4562 if (offset
+ xfer
> TYPE_LENGTH (type
))
4563 xfer
= TYPE_LENGTH (type
) - offset
;
4564 mips_xfer_register (gdbarch
, regcache
,
4565 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4566 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4570 return RETURN_VALUE_REGISTER_CONVENTION
;
4574 /* N32/N64 ABI stuff. */
4576 /* Search for a naturally aligned double at OFFSET inside a struct
4577 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4581 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4586 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4589 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4592 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4595 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4598 struct type
*field_type
;
4600 /* We're only looking at normal fields. */
4601 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4602 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4605 /* If we have gone past the offset, there is no double to pass. */
4606 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4610 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4612 /* If this field is entirely before the requested offset, go
4613 on to the next one. */
4614 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4617 /* If this is our special aligned double, we can stop. */
4618 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4619 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4622 /* This field starts at or before the requested offset, and
4623 overlaps it. If it is a structure, recurse inwards. */
4624 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4631 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4632 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4633 int nargs
, struct value
**args
, CORE_ADDR sp
,
4634 int struct_return
, CORE_ADDR struct_addr
)
4640 int stack_offset
= 0;
4641 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4642 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4644 /* For shared libraries, "t9" needs to point at the function
4646 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4648 /* Set the return address register to point to the entry point of
4649 the program, where a breakpoint lies in wait. */
4650 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4652 /* First ensure that the stack and structure return address (if any)
4653 are properly aligned. The stack has to be at least 64-bit
4654 aligned even on 32-bit machines, because doubles must be 64-bit
4655 aligned. For n32 and n64, stack frames need to be 128-bit
4656 aligned, so we round to this widest known alignment. */
4658 sp
= align_down (sp
, 16);
4659 struct_addr
= align_down (struct_addr
, 16);
4661 /* Now make space on the stack for the args. */
4662 for (argnum
= 0; argnum
< nargs
; argnum
++)
4663 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4664 sp
-= align_up (len
, 16);
4667 fprintf_unfiltered (gdb_stdlog
,
4668 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4669 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4671 /* Initialize the integer and float register pointers. */
4672 argreg
= MIPS_A0_REGNUM
;
4673 float_argreg
= mips_fpa0_regnum (gdbarch
);
4675 /* The struct_return pointer occupies the first parameter-passing reg. */
4679 fprintf_unfiltered (gdb_stdlog
,
4680 "mips_n32n64_push_dummy_call: "
4681 "struct_return reg=%d %s\n",
4682 argreg
, paddress (gdbarch
, struct_addr
));
4683 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4686 /* Now load as many as possible of the first arguments into
4687 registers, and push the rest onto the stack. Loop thru args
4688 from first to last. */
4689 for (argnum
= 0; argnum
< nargs
; argnum
++)
4691 const gdb_byte
*val
;
4692 struct value
*arg
= args
[argnum
];
4693 struct type
*arg_type
= check_typedef (value_type (arg
));
4694 int len
= TYPE_LENGTH (arg_type
);
4695 enum type_code typecode
= TYPE_CODE (arg_type
);
4698 fprintf_unfiltered (gdb_stdlog
,
4699 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4700 argnum
+ 1, len
, (int) typecode
);
4702 val
= value_contents (arg
);
4704 /* A 128-bit long double value requires an even-odd pair of
4705 floating-point registers. */
4707 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4708 && (float_argreg
& 1))
4714 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4715 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4717 /* This is a floating point value that fits entirely
4718 in a single register or a pair of registers. */
4719 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4720 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4722 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4723 float_argreg
, phex (regval
, reglen
));
4724 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4727 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4728 argreg
, phex (regval
, reglen
));
4729 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4734 regval
= extract_unsigned_integer (val
+ reglen
,
4735 reglen
, byte_order
);
4737 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4738 float_argreg
, phex (regval
, reglen
));
4739 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4742 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4743 argreg
, phex (regval
, reglen
));
4744 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4751 /* Copy the argument to general registers or the stack in
4752 register-sized pieces. Large arguments are split between
4753 registers and stack. */
4754 /* For N32/N64, structs, unions, or other composite types are
4755 treated as a sequence of doublewords, and are passed in integer
4756 or floating point registers as though they were simple scalar
4757 parameters to the extent that they fit, with any excess on the
4758 stack packed according to the normal memory layout of the
4760 The caller does not reserve space for the register arguments;
4761 the callee is responsible for reserving it if required. */
4762 /* Note: Floating-point values that didn't fit into an FP
4763 register are only written to memory. */
4766 /* Remember if the argument was written to the stack. */
4767 int stack_used_p
= 0;
4768 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4771 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4774 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4775 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
4777 /* Write this portion of the argument to the stack. */
4778 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
4780 /* Should shorter than int integer values be
4781 promoted to int before being stored? */
4782 int longword_offset
= 0;
4785 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4787 if ((typecode
== TYPE_CODE_INT
4788 || typecode
== TYPE_CODE_PTR
)
4790 longword_offset
= MIPS64_REGSIZE
- len
;
4795 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4796 paddress (gdbarch
, stack_offset
));
4797 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4798 paddress (gdbarch
, longword_offset
));
4801 addr
= sp
+ stack_offset
+ longword_offset
;
4806 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4807 paddress (gdbarch
, addr
));
4808 for (i
= 0; i
< partial_len
; i
++)
4810 fprintf_unfiltered (gdb_stdlog
, "%02x",
4814 write_memory (addr
, val
, partial_len
);
4817 /* Note!!! This is NOT an else clause. Odd sized
4818 structs may go thru BOTH paths. */
4819 /* Write this portion of the argument to a general
4820 purpose register. */
4821 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4825 /* Sign extend pointers, 32-bit integers and signed
4826 16-bit and 8-bit integers; everything else is taken
4829 if ((partial_len
== 4
4830 && (typecode
== TYPE_CODE_PTR
4831 || typecode
== TYPE_CODE_INT
))
4833 && typecode
== TYPE_CODE_INT
4834 && !TYPE_UNSIGNED (arg_type
)))
4835 regval
= extract_signed_integer (val
, partial_len
,
4838 regval
= extract_unsigned_integer (val
, partial_len
,
4841 /* A non-floating-point argument being passed in a
4842 general register. If a struct or union, and if
4843 the remaining length is smaller than the register
4844 size, we have to adjust the register value on
4847 It does not seem to be necessary to do the
4848 same for integral types. */
4850 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4851 && partial_len
< MIPS64_REGSIZE
4852 && (typecode
== TYPE_CODE_STRUCT
4853 || typecode
== TYPE_CODE_UNION
))
4854 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4858 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4860 phex (regval
, MIPS64_REGSIZE
));
4861 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4863 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
4864 TYPE_LENGTH (arg_type
) - len
))
4867 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
4869 phex (regval
, MIPS64_REGSIZE
));
4870 regcache_cooked_write_unsigned (regcache
, float_argreg
,
4881 /* Compute the offset into the stack at which we will
4882 copy the next parameter.
4884 In N32 (N64?), the stack_offset only needs to be
4885 adjusted when it has been used. */
4888 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4892 fprintf_unfiltered (gdb_stdlog
, "\n");
4895 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4897 /* Return adjusted stack pointer. */
4901 static enum return_value_convention
4902 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4903 struct type
*type
, struct regcache
*regcache
,
4904 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4906 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4908 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
4910 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
4911 if needed), as appropriate for the type. Composite results (struct,
4912 union, or array) are returned in $2/$f0 and $3/$f2 according to the
4915 * A struct with only one or two floating point fields is returned in $f0
4916 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
4919 * Any other composite results of at most 128 bits are returned in
4920 $2 (first 64 bits) and $3 (remainder, if necessary).
4922 * Larger composite results are handled by converting the function to a
4923 procedure with an implicit first parameter, which is a pointer to an area
4924 reserved by the caller to receive the result. [The o32-bit ABI requires
4925 that all composite results be handled by conversion to implicit first
4926 parameters. The MIPS/SGI Fortran implementation has always made a
4927 specific exception to return COMPLEX results in the floating point
4930 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
4931 return RETURN_VALUE_STRUCT_CONVENTION
;
4932 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4933 && TYPE_LENGTH (type
) == 16
4934 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4936 /* A 128-bit floating-point value fills both $f0 and $f2. The
4937 two registers are used in the same as memory order, so the
4938 eight bytes with the lower memory address are in $f0. */
4940 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
4941 mips_xfer_register (gdbarch
, regcache
,
4942 (gdbarch_num_regs (gdbarch
)
4943 + mips_regnum (gdbarch
)->fp0
),
4944 8, gdbarch_byte_order (gdbarch
),
4945 readbuf
, writebuf
, 0);
4946 mips_xfer_register (gdbarch
, regcache
,
4947 (gdbarch_num_regs (gdbarch
)
4948 + mips_regnum (gdbarch
)->fp0
+ 2),
4949 8, gdbarch_byte_order (gdbarch
),
4950 readbuf
? readbuf
+ 8 : readbuf
,
4951 writebuf
? writebuf
+ 8 : writebuf
, 0);
4952 return RETURN_VALUE_REGISTER_CONVENTION
;
4954 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4955 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4957 /* A single or double floating-point value that fits in FP0. */
4959 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4960 mips_xfer_register (gdbarch
, regcache
,
4961 (gdbarch_num_regs (gdbarch
)
4962 + mips_regnum (gdbarch
)->fp0
),
4964 gdbarch_byte_order (gdbarch
),
4965 readbuf
, writebuf
, 0);
4966 return RETURN_VALUE_REGISTER_CONVENTION
;
4968 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4969 && TYPE_NFIELDS (type
) <= 2
4970 && TYPE_NFIELDS (type
) >= 1
4971 && ((TYPE_NFIELDS (type
) == 1
4972 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
4974 || (TYPE_NFIELDS (type
) == 2
4975 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
4977 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
4978 == TYPE_CODE_FLT
))))
4980 /* A struct that contains one or two floats. Each value is part
4981 in the least significant part of their floating point
4982 register (or GPR, for soft float). */
4985 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
4986 ? mips_regnum (gdbarch
)->fp0
4988 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4990 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4993 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4995 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
4997 /* A 16-byte long double field goes in two consecutive
4999 mips_xfer_register (gdbarch
, regcache
,
5000 gdbarch_num_regs (gdbarch
) + regnum
,
5002 gdbarch_byte_order (gdbarch
),
5003 readbuf
, writebuf
, offset
);
5004 mips_xfer_register (gdbarch
, regcache
,
5005 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5007 gdbarch_byte_order (gdbarch
),
5008 readbuf
, writebuf
, offset
+ 8);
5011 mips_xfer_register (gdbarch
, regcache
,
5012 gdbarch_num_regs (gdbarch
) + regnum
,
5013 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5014 gdbarch_byte_order (gdbarch
),
5015 readbuf
, writebuf
, offset
);
5017 return RETURN_VALUE_REGISTER_CONVENTION
;
5019 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5020 || TYPE_CODE (type
) == TYPE_CODE_UNION
5021 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5023 /* A composite type. Extract the left justified value,
5024 regardless of the byte order. I.e. DO NOT USE
5028 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5029 offset
< TYPE_LENGTH (type
);
5030 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5032 int xfer
= register_size (gdbarch
, regnum
);
5033 if (offset
+ xfer
> TYPE_LENGTH (type
))
5034 xfer
= TYPE_LENGTH (type
) - offset
;
5036 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5037 offset
, xfer
, regnum
);
5038 mips_xfer_register (gdbarch
, regcache
,
5039 gdbarch_num_regs (gdbarch
) + regnum
,
5040 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5043 return RETURN_VALUE_REGISTER_CONVENTION
;
5047 /* A scalar extract each part but least-significant-byte
5051 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5052 offset
< TYPE_LENGTH (type
);
5053 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5055 int xfer
= register_size (gdbarch
, regnum
);
5056 if (offset
+ xfer
> TYPE_LENGTH (type
))
5057 xfer
= TYPE_LENGTH (type
) - offset
;
5059 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5060 offset
, xfer
, regnum
);
5061 mips_xfer_register (gdbarch
, regcache
,
5062 gdbarch_num_regs (gdbarch
) + regnum
,
5063 xfer
, gdbarch_byte_order (gdbarch
),
5064 readbuf
, writebuf
, offset
);
5066 return RETURN_VALUE_REGISTER_CONVENTION
;
5070 /* Which registers to use for passing floating-point values between
5071 function calls, one of floating-point, general and both kinds of
5072 registers. O32 and O64 use different register kinds for standard
5073 MIPS and MIPS16 code; to make the handling of cases where we may
5074 not know what kind of code is being used (e.g. no debug information)
5075 easier we sometimes use both kinds. */
5084 /* O32 ABI stuff. */
5087 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5088 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5089 int nargs
, struct value
**args
, CORE_ADDR sp
,
5090 int struct_return
, CORE_ADDR struct_addr
)
5096 int stack_offset
= 0;
5097 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5098 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5100 /* For shared libraries, "t9" needs to point at the function
5102 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5104 /* Set the return address register to point to the entry point of
5105 the program, where a breakpoint lies in wait. */
5106 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5108 /* First ensure that the stack and structure return address (if any)
5109 are properly aligned. The stack has to be at least 64-bit
5110 aligned even on 32-bit machines, because doubles must be 64-bit
5111 aligned. For n32 and n64, stack frames need to be 128-bit
5112 aligned, so we round to this widest known alignment. */
5114 sp
= align_down (sp
, 16);
5115 struct_addr
= align_down (struct_addr
, 16);
5117 /* Now make space on the stack for the args. */
5118 for (argnum
= 0; argnum
< nargs
; argnum
++)
5120 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5121 int arglen
= TYPE_LENGTH (arg_type
);
5123 /* Align to double-word if necessary. */
5124 if (mips_type_needs_double_align (arg_type
))
5125 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5126 /* Allocate space on the stack. */
5127 len
+= align_up (arglen
, MIPS32_REGSIZE
);
5129 sp
-= align_up (len
, 16);
5132 fprintf_unfiltered (gdb_stdlog
,
5133 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5134 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5136 /* Initialize the integer and float register pointers. */
5137 argreg
= MIPS_A0_REGNUM
;
5138 float_argreg
= mips_fpa0_regnum (gdbarch
);
5140 /* The struct_return pointer occupies the first parameter-passing reg. */
5144 fprintf_unfiltered (gdb_stdlog
,
5145 "mips_o32_push_dummy_call: "
5146 "struct_return reg=%d %s\n",
5147 argreg
, paddress (gdbarch
, struct_addr
));
5148 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5149 stack_offset
+= MIPS32_REGSIZE
;
5152 /* Now load as many as possible of the first arguments into
5153 registers, and push the rest onto the stack. Loop thru args
5154 from first to last. */
5155 for (argnum
= 0; argnum
< nargs
; argnum
++)
5157 const gdb_byte
*val
;
5158 struct value
*arg
= args
[argnum
];
5159 struct type
*arg_type
= check_typedef (value_type (arg
));
5160 int len
= TYPE_LENGTH (arg_type
);
5161 enum type_code typecode
= TYPE_CODE (arg_type
);
5164 fprintf_unfiltered (gdb_stdlog
,
5165 "mips_o32_push_dummy_call: %d len=%d type=%d",
5166 argnum
+ 1, len
, (int) typecode
);
5168 val
= value_contents (arg
);
5170 /* 32-bit ABIs always start floating point arguments in an
5171 even-numbered floating point register. Round the FP register
5172 up before the check to see if there are any FP registers
5173 left. O32 targets also pass the FP in the integer registers
5174 so also round up normal registers. */
5175 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5177 if ((float_argreg
& 1))
5181 /* Floating point arguments passed in registers have to be
5182 treated specially. On 32-bit architectures, doubles are
5183 passed in register pairs; the even FP register gets the
5184 low word, and the odd FP register gets the high word.
5185 On O32, the first two floating point arguments are also
5186 copied to general registers, following their memory order,
5187 because MIPS16 functions don't use float registers for
5188 arguments. This duplication of arguments in general
5189 registers can't hurt non-MIPS16 functions, because those
5190 registers are normally skipped. */
5192 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5193 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5195 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5197 int freg_offset
= gdbarch_byte_order (gdbarch
)
5198 == BFD_ENDIAN_BIG
? 1 : 0;
5199 unsigned long regval
;
5202 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5204 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5205 float_argreg
+ freg_offset
,
5207 regcache_cooked_write_unsigned (regcache
,
5208 float_argreg
++ + freg_offset
,
5211 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5212 argreg
, phex (regval
, 4));
5213 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5216 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5218 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5219 float_argreg
- freg_offset
,
5221 regcache_cooked_write_unsigned (regcache
,
5222 float_argreg
++ - freg_offset
,
5225 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5226 argreg
, phex (regval
, 4));
5227 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5231 /* This is a floating point value that fits entirely
5232 in a single register. */
5233 /* On 32 bit ABI's the float_argreg is further adjusted
5234 above to ensure that it is even register aligned. */
5235 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5237 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5238 float_argreg
, phex (regval
, len
));
5239 regcache_cooked_write_unsigned (regcache
,
5240 float_argreg
++, regval
);
5241 /* Although two FP registers are reserved for each
5242 argument, only one corresponding integer register is
5245 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5246 argreg
, phex (regval
, len
));
5247 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5249 /* Reserve space for the FP register. */
5250 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5254 /* Copy the argument to general registers or the stack in
5255 register-sized pieces. Large arguments are split between
5256 registers and stack. */
5257 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5258 are treated specially: Irix cc passes
5259 them in registers where gcc sometimes puts them on the
5260 stack. For maximum compatibility, we will put them in
5262 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5263 && len
% MIPS32_REGSIZE
!= 0);
5264 /* Structures should be aligned to eight bytes (even arg registers)
5265 on MIPS_ABI_O32, if their first member has double precision. */
5266 if (mips_type_needs_double_align (arg_type
))
5271 stack_offset
+= MIPS32_REGSIZE
;
5276 /* Remember if the argument was written to the stack. */
5277 int stack_used_p
= 0;
5278 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5281 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5284 /* Write this portion of the argument to the stack. */
5285 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5286 || odd_sized_struct
)
5288 /* Should shorter than int integer values be
5289 promoted to int before being stored? */
5290 int longword_offset
= 0;
5296 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5297 paddress (gdbarch
, stack_offset
));
5298 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5299 paddress (gdbarch
, longword_offset
));
5302 addr
= sp
+ stack_offset
+ longword_offset
;
5307 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5308 paddress (gdbarch
, addr
));
5309 for (i
= 0; i
< partial_len
; i
++)
5311 fprintf_unfiltered (gdb_stdlog
, "%02x",
5315 write_memory (addr
, val
, partial_len
);
5318 /* Note!!! This is NOT an else clause. Odd sized
5319 structs may go thru BOTH paths. */
5320 /* Write this portion of the argument to a general
5321 purpose register. */
5322 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5324 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5326 /* Value may need to be sign extended, because
5327 mips_isa_regsize() != mips_abi_regsize(). */
5329 /* A non-floating-point argument being passed in a
5330 general register. If a struct or union, and if
5331 the remaining length is smaller than the register
5332 size, we have to adjust the register value on
5335 It does not seem to be necessary to do the
5336 same for integral types.
5338 Also don't do this adjustment on O64 binaries.
5340 cagney/2001-07-23: gdb/179: Also, GCC, when
5341 outputting LE O32 with sizeof (struct) <
5342 mips_abi_regsize(), generates a left shift
5343 as part of storing the argument in a register
5344 (the left shift isn't generated when
5345 sizeof (struct) >= mips_abi_regsize()). Since
5346 it is quite possible that this is GCC
5347 contradicting the LE/O32 ABI, GDB has not been
5348 adjusted to accommodate this. Either someone
5349 needs to demonstrate that the LE/O32 ABI
5350 specifies such a left shift OR this new ABI gets
5351 identified as such and GDB gets tweaked
5354 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5355 && partial_len
< MIPS32_REGSIZE
5356 && (typecode
== TYPE_CODE_STRUCT
5357 || typecode
== TYPE_CODE_UNION
))
5358 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5362 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5364 phex (regval
, MIPS32_REGSIZE
));
5365 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5368 /* Prevent subsequent floating point arguments from
5369 being passed in floating point registers. */
5370 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5376 /* Compute the offset into the stack at which we will
5377 copy the next parameter.
5379 In older ABIs, the caller reserved space for
5380 registers that contained arguments. This was loosely
5381 refered to as their "home". Consequently, space is
5382 always allocated. */
5384 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5388 fprintf_unfiltered (gdb_stdlog
, "\n");
5391 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5393 /* Return adjusted stack pointer. */
5397 static enum return_value_convention
5398 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5399 struct type
*type
, struct regcache
*regcache
,
5400 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5402 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5403 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5404 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5405 enum mips_fval_reg fval_reg
;
5407 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5408 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5409 || TYPE_CODE (type
) == TYPE_CODE_UNION
5410 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5411 return RETURN_VALUE_STRUCT_CONVENTION
;
5412 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5413 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5415 /* A single-precision floating-point value. If reading in or copying,
5416 then we get it from/put it to FP0 for standard MIPS code or GPR2
5417 for MIPS16 code. If writing out only, then we put it to both FP0
5418 and GPR2. We do not support reading in with no function known, if
5419 this safety check ever triggers, then we'll have to try harder. */
5420 gdb_assert (function
|| !readbuf
);
5425 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5428 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5430 case mips_fval_both
:
5431 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5434 if (fval_reg
!= mips_fval_gpr
)
5435 mips_xfer_register (gdbarch
, regcache
,
5436 (gdbarch_num_regs (gdbarch
)
5437 + mips_regnum (gdbarch
)->fp0
),
5439 gdbarch_byte_order (gdbarch
),
5440 readbuf
, writebuf
, 0);
5441 if (fval_reg
!= mips_fval_fpr
)
5442 mips_xfer_register (gdbarch
, regcache
,
5443 gdbarch_num_regs (gdbarch
) + 2,
5445 gdbarch_byte_order (gdbarch
),
5446 readbuf
, writebuf
, 0);
5447 return RETURN_VALUE_REGISTER_CONVENTION
;
5449 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5450 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5452 /* A double-precision floating-point value. If reading in or copying,
5453 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5454 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5455 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5456 no function known, if this safety check ever triggers, then we'll
5457 have to try harder. */
5458 gdb_assert (function
|| !readbuf
);
5463 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5466 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5468 case mips_fval_both
:
5469 fprintf_unfiltered (gdb_stderr
,
5470 "Return float in $fp1/$fp0 and $2/$3\n");
5473 if (fval_reg
!= mips_fval_gpr
)
5475 /* The most significant part goes in FP1, and the least significant
5477 switch (gdbarch_byte_order (gdbarch
))
5479 case BFD_ENDIAN_LITTLE
:
5480 mips_xfer_register (gdbarch
, regcache
,
5481 (gdbarch_num_regs (gdbarch
)
5482 + mips_regnum (gdbarch
)->fp0
+ 0),
5483 4, gdbarch_byte_order (gdbarch
),
5484 readbuf
, writebuf
, 0);
5485 mips_xfer_register (gdbarch
, regcache
,
5486 (gdbarch_num_regs (gdbarch
)
5487 + mips_regnum (gdbarch
)->fp0
+ 1),
5488 4, gdbarch_byte_order (gdbarch
),
5489 readbuf
, writebuf
, 4);
5491 case BFD_ENDIAN_BIG
:
5492 mips_xfer_register (gdbarch
, regcache
,
5493 (gdbarch_num_regs (gdbarch
)
5494 + mips_regnum (gdbarch
)->fp0
+ 1),
5495 4, gdbarch_byte_order (gdbarch
),
5496 readbuf
, writebuf
, 0);
5497 mips_xfer_register (gdbarch
, regcache
,
5498 (gdbarch_num_regs (gdbarch
)
5499 + mips_regnum (gdbarch
)->fp0
+ 0),
5500 4, gdbarch_byte_order (gdbarch
),
5501 readbuf
, writebuf
, 4);
5504 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5507 if (fval_reg
!= mips_fval_fpr
)
5509 /* The two 32-bit parts are always placed in GPR2 and GPR3
5510 following these registers' memory order. */
5511 mips_xfer_register (gdbarch
, regcache
,
5512 gdbarch_num_regs (gdbarch
) + 2,
5513 4, gdbarch_byte_order (gdbarch
),
5514 readbuf
, writebuf
, 0);
5515 mips_xfer_register (gdbarch
, regcache
,
5516 gdbarch_num_regs (gdbarch
) + 3,
5517 4, gdbarch_byte_order (gdbarch
),
5518 readbuf
, writebuf
, 4);
5520 return RETURN_VALUE_REGISTER_CONVENTION
;
5523 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5524 && TYPE_NFIELDS (type
) <= 2
5525 && TYPE_NFIELDS (type
) >= 1
5526 && ((TYPE_NFIELDS (type
) == 1
5527 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5529 || (TYPE_NFIELDS (type
) == 2
5530 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5532 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5534 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5536 /* A struct that contains one or two floats. Each value is part
5537 in the least significant part of their floating point
5539 gdb_byte reg
[MAX_REGISTER_SIZE
];
5542 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5543 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5545 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5548 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5550 mips_xfer_register (gdbarch
, regcache
,
5551 gdbarch_num_regs (gdbarch
) + regnum
,
5552 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5553 gdbarch_byte_order (gdbarch
),
5554 readbuf
, writebuf
, offset
);
5556 return RETURN_VALUE_REGISTER_CONVENTION
;
5560 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5561 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5563 /* A structure or union. Extract the left justified value,
5564 regardless of the byte order. I.e. DO NOT USE
5568 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5569 offset
< TYPE_LENGTH (type
);
5570 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5572 int xfer
= register_size (gdbarch
, regnum
);
5573 if (offset
+ xfer
> TYPE_LENGTH (type
))
5574 xfer
= TYPE_LENGTH (type
) - offset
;
5576 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5577 offset
, xfer
, regnum
);
5578 mips_xfer_register (gdbarch
, regcache
,
5579 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5580 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5582 return RETURN_VALUE_REGISTER_CONVENTION
;
5587 /* A scalar extract each part but least-significant-byte
5588 justified. o32 thinks registers are 4 byte, regardless of
5592 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5593 offset
< TYPE_LENGTH (type
);
5594 offset
+= MIPS32_REGSIZE
, regnum
++)
5596 int xfer
= MIPS32_REGSIZE
;
5597 if (offset
+ xfer
> TYPE_LENGTH (type
))
5598 xfer
= TYPE_LENGTH (type
) - offset
;
5600 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5601 offset
, xfer
, regnum
);
5602 mips_xfer_register (gdbarch
, regcache
,
5603 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5604 gdbarch_byte_order (gdbarch
),
5605 readbuf
, writebuf
, offset
);
5607 return RETURN_VALUE_REGISTER_CONVENTION
;
5611 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5615 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5616 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5618 struct value
**args
, CORE_ADDR sp
,
5619 int struct_return
, CORE_ADDR struct_addr
)
5625 int stack_offset
= 0;
5626 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5627 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5629 /* For shared libraries, "t9" needs to point at the function
5631 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5633 /* Set the return address register to point to the entry point of
5634 the program, where a breakpoint lies in wait. */
5635 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5637 /* First ensure that the stack and structure return address (if any)
5638 are properly aligned. The stack has to be at least 64-bit
5639 aligned even on 32-bit machines, because doubles must be 64-bit
5640 aligned. For n32 and n64, stack frames need to be 128-bit
5641 aligned, so we round to this widest known alignment. */
5643 sp
= align_down (sp
, 16);
5644 struct_addr
= align_down (struct_addr
, 16);
5646 /* Now make space on the stack for the args. */
5647 for (argnum
= 0; argnum
< nargs
; argnum
++)
5649 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5650 int arglen
= TYPE_LENGTH (arg_type
);
5652 /* Allocate space on the stack. */
5653 len
+= align_up (arglen
, MIPS64_REGSIZE
);
5655 sp
-= align_up (len
, 16);
5658 fprintf_unfiltered (gdb_stdlog
,
5659 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5660 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5662 /* Initialize the integer and float register pointers. */
5663 argreg
= MIPS_A0_REGNUM
;
5664 float_argreg
= mips_fpa0_regnum (gdbarch
);
5666 /* The struct_return pointer occupies the first parameter-passing reg. */
5670 fprintf_unfiltered (gdb_stdlog
,
5671 "mips_o64_push_dummy_call: "
5672 "struct_return reg=%d %s\n",
5673 argreg
, paddress (gdbarch
, struct_addr
));
5674 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5675 stack_offset
+= MIPS64_REGSIZE
;
5678 /* Now load as many as possible of the first arguments into
5679 registers, and push the rest onto the stack. Loop thru args
5680 from first to last. */
5681 for (argnum
= 0; argnum
< nargs
; argnum
++)
5683 const gdb_byte
*val
;
5684 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
5685 struct value
*arg
= args
[argnum
];
5686 struct type
*arg_type
= check_typedef (value_type (arg
));
5687 int len
= TYPE_LENGTH (arg_type
);
5688 enum type_code typecode
= TYPE_CODE (arg_type
);
5691 fprintf_unfiltered (gdb_stdlog
,
5692 "mips_o64_push_dummy_call: %d len=%d type=%d",
5693 argnum
+ 1, len
, (int) typecode
);
5695 val
= value_contents (arg
);
5697 /* Function pointer arguments to mips16 code need to be made into
5699 if (typecode
== TYPE_CODE_PTR
5700 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
5702 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
5704 if (!mips_pc_is_mips (addr
))
5706 store_signed_integer (valbuf
, len
, byte_order
,
5707 make_compact_addr (addr
));
5712 /* Floating point arguments passed in registers have to be
5713 treated specially. On 32-bit architectures, doubles are
5714 passed in register pairs; the even FP register gets the
5715 low word, and the odd FP register gets the high word.
5716 On O64, the first two floating point arguments are also
5717 copied to general registers, because MIPS16 functions
5718 don't use float registers for arguments. This duplication
5719 of arguments in general registers can't hurt non-MIPS16
5720 functions because those registers are normally skipped. */
5722 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5723 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5725 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5727 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5728 float_argreg
, phex (regval
, len
));
5729 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5731 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5732 argreg
, phex (regval
, len
));
5733 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5735 /* Reserve space for the FP register. */
5736 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5740 /* Copy the argument to general registers or the stack in
5741 register-sized pieces. Large arguments are split between
5742 registers and stack. */
5743 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5744 are treated specially: Irix cc passes them in registers
5745 where gcc sometimes puts them on the stack. For maximum
5746 compatibility, we will put them in both places. */
5747 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5748 && len
% MIPS64_REGSIZE
!= 0);
5751 /* Remember if the argument was written to the stack. */
5752 int stack_used_p
= 0;
5753 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5756 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5759 /* Write this portion of the argument to the stack. */
5760 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5761 || odd_sized_struct
)
5763 /* Should shorter than int integer values be
5764 promoted to int before being stored? */
5765 int longword_offset
= 0;
5768 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5770 if ((typecode
== TYPE_CODE_INT
5771 || typecode
== TYPE_CODE_PTR
5772 || typecode
== TYPE_CODE_FLT
)
5774 longword_offset
= MIPS64_REGSIZE
- len
;
5779 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5780 paddress (gdbarch
, stack_offset
));
5781 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5782 paddress (gdbarch
, longword_offset
));
5785 addr
= sp
+ stack_offset
+ longword_offset
;
5790 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5791 paddress (gdbarch
, addr
));
5792 for (i
= 0; i
< partial_len
; i
++)
5794 fprintf_unfiltered (gdb_stdlog
, "%02x",
5798 write_memory (addr
, val
, partial_len
);
5801 /* Note!!! This is NOT an else clause. Odd sized
5802 structs may go thru BOTH paths. */
5803 /* Write this portion of the argument to a general
5804 purpose register. */
5805 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5807 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5809 /* Value may need to be sign extended, because
5810 mips_isa_regsize() != mips_abi_regsize(). */
5812 /* A non-floating-point argument being passed in a
5813 general register. If a struct or union, and if
5814 the remaining length is smaller than the register
5815 size, we have to adjust the register value on
5818 It does not seem to be necessary to do the
5819 same for integral types. */
5821 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5822 && partial_len
< MIPS64_REGSIZE
5823 && (typecode
== TYPE_CODE_STRUCT
5824 || typecode
== TYPE_CODE_UNION
))
5825 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5829 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5831 phex (regval
, MIPS64_REGSIZE
));
5832 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5835 /* Prevent subsequent floating point arguments from
5836 being passed in floating point registers. */
5837 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5843 /* Compute the offset into the stack at which we will
5844 copy the next parameter.
5846 In older ABIs, the caller reserved space for
5847 registers that contained arguments. This was loosely
5848 refered to as their "home". Consequently, space is
5849 always allocated. */
5851 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5855 fprintf_unfiltered (gdb_stdlog
, "\n");
5858 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5860 /* Return adjusted stack pointer. */
5864 static enum return_value_convention
5865 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5866 struct type
*type
, struct regcache
*regcache
,
5867 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5869 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5870 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5871 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5872 enum mips_fval_reg fval_reg
;
5874 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5875 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5876 || TYPE_CODE (type
) == TYPE_CODE_UNION
5877 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5878 return RETURN_VALUE_STRUCT_CONVENTION
;
5879 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
5881 /* A floating-point value. If reading in or copying, then we get it
5882 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
5883 If writing out only, then we put it to both FP0 and GPR2. We do
5884 not support reading in with no function known, if this safety
5885 check ever triggers, then we'll have to try harder. */
5886 gdb_assert (function
|| !readbuf
);
5891 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5894 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5896 case mips_fval_both
:
5897 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5900 if (fval_reg
!= mips_fval_gpr
)
5901 mips_xfer_register (gdbarch
, regcache
,
5902 (gdbarch_num_regs (gdbarch
)
5903 + mips_regnum (gdbarch
)->fp0
),
5905 gdbarch_byte_order (gdbarch
),
5906 readbuf
, writebuf
, 0);
5907 if (fval_reg
!= mips_fval_fpr
)
5908 mips_xfer_register (gdbarch
, regcache
,
5909 gdbarch_num_regs (gdbarch
) + 2,
5911 gdbarch_byte_order (gdbarch
),
5912 readbuf
, writebuf
, 0);
5913 return RETURN_VALUE_REGISTER_CONVENTION
;
5917 /* A scalar extract each part but least-significant-byte
5921 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5922 offset
< TYPE_LENGTH (type
);
5923 offset
+= MIPS64_REGSIZE
, regnum
++)
5925 int xfer
= MIPS64_REGSIZE
;
5926 if (offset
+ xfer
> TYPE_LENGTH (type
))
5927 xfer
= TYPE_LENGTH (type
) - offset
;
5929 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5930 offset
, xfer
, regnum
);
5931 mips_xfer_register (gdbarch
, regcache
,
5932 gdbarch_num_regs (gdbarch
) + regnum
,
5933 xfer
, gdbarch_byte_order (gdbarch
),
5934 readbuf
, writebuf
, offset
);
5936 return RETURN_VALUE_REGISTER_CONVENTION
;
5940 /* Floating point register management.
5942 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
5943 64bit operations, these early MIPS cpus treat fp register pairs
5944 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
5945 registers and offer a compatibility mode that emulates the MIPS2 fp
5946 model. When operating in MIPS2 fp compat mode, later cpu's split
5947 double precision floats into two 32-bit chunks and store them in
5948 consecutive fp regs. To display 64-bit floats stored in this
5949 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
5950 Throw in user-configurable endianness and you have a real mess.
5952 The way this works is:
5953 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
5954 double-precision value will be split across two logical registers.
5955 The lower-numbered logical register will hold the low-order bits,
5956 regardless of the processor's endianness.
5957 - If we are on a 64-bit processor, and we are looking for a
5958 single-precision value, it will be in the low ordered bits
5959 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
5960 save slot in memory.
5961 - If we are in 64-bit mode, everything is straightforward.
5963 Note that this code only deals with "live" registers at the top of the
5964 stack. We will attempt to deal with saved registers later, when
5965 the raw/cooked register interface is in place. (We need a general
5966 interface that can deal with dynamic saved register sizes -- fp
5967 regs could be 32 bits wide in one frame and 64 on the frame above
5970 /* Copy a 32-bit single-precision value from the current frame
5971 into rare_buffer. */
5974 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
5975 gdb_byte
*rare_buffer
)
5977 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5978 int raw_size
= register_size (gdbarch
, regno
);
5979 gdb_byte
*raw_buffer
= alloca (raw_size
);
5981 if (!frame_register_read (frame
, regno
, raw_buffer
))
5982 error (_("can't read register %d (%s)"),
5983 regno
, gdbarch_register_name (gdbarch
, regno
));
5986 /* We have a 64-bit value for this register. Find the low-order
5990 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5995 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
5999 memcpy (rare_buffer
, raw_buffer
, 4);
6003 /* Copy a 64-bit double-precision value from the current frame into
6004 rare_buffer. This may include getting half of it from the next
6008 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6009 gdb_byte
*rare_buffer
)
6011 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6012 int raw_size
= register_size (gdbarch
, regno
);
6014 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6016 /* We have a 64-bit value for this register, and we should use
6018 if (!frame_register_read (frame
, regno
, rare_buffer
))
6019 error (_("can't read register %d (%s)"),
6020 regno
, gdbarch_register_name (gdbarch
, regno
));
6024 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6026 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6027 internal_error (__FILE__
, __LINE__
,
6028 _("mips_read_fp_register_double: bad access to "
6029 "odd-numbered FP register"));
6031 /* mips_read_fp_register_single will find the correct 32 bits from
6033 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6035 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6036 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6040 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6041 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6047 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6049 { /* Do values for FP (float) regs. */
6050 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6051 gdb_byte
*raw_buffer
;
6052 double doub
, flt1
; /* Doubles extracted from raw hex data. */
6055 raw_buffer
= alloca (2 * register_size (gdbarch
,
6056 mips_regnum (gdbarch
)->fp0
));
6058 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6059 fprintf_filtered (file
, "%*s",
6060 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6063 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6065 struct value_print_options opts
;
6067 /* 4-byte registers: Print hex and floating. Also print even
6068 numbered registers as doubles. */
6069 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6070 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6073 get_formatted_print_options (&opts
, 'x');
6074 print_scalar_formatted (raw_buffer
,
6075 builtin_type (gdbarch
)->builtin_uint32
,
6078 fprintf_filtered (file
, " flt: ");
6080 fprintf_filtered (file
, " <invalid float> ");
6082 fprintf_filtered (file
, "%-17.9g", flt1
);
6084 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6086 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6087 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6090 fprintf_filtered (file
, " dbl: ");
6092 fprintf_filtered (file
, "<invalid double>");
6094 fprintf_filtered (file
, "%-24.17g", doub
);
6099 struct value_print_options opts
;
6101 /* Eight byte registers: print each one as hex, float and double. */
6102 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6103 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6106 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6107 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6110 get_formatted_print_options (&opts
, 'x');
6111 print_scalar_formatted (raw_buffer
,
6112 builtin_type (gdbarch
)->builtin_uint64
,
6115 fprintf_filtered (file
, " flt: ");
6117 fprintf_filtered (file
, "<invalid float>");
6119 fprintf_filtered (file
, "%-17.9g", flt1
);
6121 fprintf_filtered (file
, " dbl: ");
6123 fprintf_filtered (file
, "<invalid double>");
6125 fprintf_filtered (file
, "%-24.17g", doub
);
6130 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6133 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6134 struct value_print_options opts
;
6137 if (mips_float_register_p (gdbarch
, regnum
))
6139 mips_print_fp_register (file
, frame
, regnum
);
6143 val
= get_frame_register_value (frame
, regnum
);
6144 if (value_optimized_out (val
))
6146 fprintf_filtered (file
, "%s: [Invalid]",
6147 gdbarch_register_name (gdbarch
, regnum
));
6151 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6153 /* The problem with printing numeric register names (r26, etc.) is that
6154 the user can't use them on input. Probably the best solution is to
6155 fix it so that either the numeric or the funky (a2, etc.) names
6156 are accepted on input. */
6157 if (regnum
< MIPS_NUMREGS
)
6158 fprintf_filtered (file
, "(r%d): ", regnum
);
6160 fprintf_filtered (file
, ": ");
6162 get_formatted_print_options (&opts
, 'x');
6163 val_print_scalar_formatted (value_type (val
),
6164 value_contents_for_printing (val
),
6165 value_embedded_offset (val
),
6170 /* Replacement for generic do_registers_info.
6171 Print regs in pretty columns. */
6174 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6177 fprintf_filtered (file
, " ");
6178 mips_print_fp_register (file
, frame
, regnum
);
6179 fprintf_filtered (file
, "\n");
6184 /* Print a row's worth of GP (int) registers, with name labels above. */
6187 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6190 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6191 /* Do values for GP (int) regs. */
6192 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
6193 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6198 /* For GP registers, we print a separate row of names above the vals. */
6199 for (col
= 0, regnum
= start_regnum
;
6200 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6201 + gdbarch_num_pseudo_regs (gdbarch
);
6204 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6205 continue; /* unused register */
6206 if (mips_float_register_p (gdbarch
, regnum
))
6207 break; /* End the row: reached FP register. */
6208 /* Large registers are handled separately. */
6209 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6212 break; /* End the row before this register. */
6214 /* Print this register on a row by itself. */
6215 mips_print_register (file
, frame
, regnum
);
6216 fprintf_filtered (file
, "\n");
6220 fprintf_filtered (file
, " ");
6221 fprintf_filtered (file
,
6222 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6223 gdbarch_register_name (gdbarch
, regnum
));
6230 /* Print the R0 to R31 names. */
6231 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6232 fprintf_filtered (file
, "\n R%-4d",
6233 start_regnum
% gdbarch_num_regs (gdbarch
));
6235 fprintf_filtered (file
, "\n ");
6237 /* Now print the values in hex, 4 or 8 to the row. */
6238 for (col
= 0, regnum
= start_regnum
;
6239 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6240 + gdbarch_num_pseudo_regs (gdbarch
);
6243 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6244 continue; /* unused register */
6245 if (mips_float_register_p (gdbarch
, regnum
))
6246 break; /* End row: reached FP register. */
6247 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6248 break; /* End row: large register. */
6250 /* OK: get the data in raw format. */
6251 if (!frame_register_read (frame
, regnum
, raw_buffer
))
6252 error (_("can't read register %d (%s)"),
6253 regnum
, gdbarch_register_name (gdbarch
, regnum
));
6254 /* pad small registers */
6256 byte
< (mips_abi_regsize (gdbarch
)
6257 - register_size (gdbarch
, regnum
)); byte
++)
6258 printf_filtered (" ");
6259 /* Now print the register value in hex, endian order. */
6260 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6262 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6263 byte
< register_size (gdbarch
, regnum
); byte
++)
6264 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6266 for (byte
= register_size (gdbarch
, regnum
) - 1;
6268 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6269 fprintf_filtered (file
, " ");
6272 if (col
> 0) /* ie. if we actually printed anything... */
6273 fprintf_filtered (file
, "\n");
6278 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6281 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6282 struct frame_info
*frame
, int regnum
, int all
)
6284 if (regnum
!= -1) /* Do one specified register. */
6286 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6287 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6288 error (_("Not a valid register for the current processor type"));
6290 mips_print_register (file
, frame
, regnum
);
6291 fprintf_filtered (file
, "\n");
6294 /* Do all (or most) registers. */
6296 regnum
= gdbarch_num_regs (gdbarch
);
6297 while (regnum
< gdbarch_num_regs (gdbarch
)
6298 + gdbarch_num_pseudo_regs (gdbarch
))
6300 if (mips_float_register_p (gdbarch
, regnum
))
6302 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6303 regnum
= print_fp_register_row (file
, frame
, regnum
);
6305 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6308 regnum
= print_gp_register_row (file
, frame
, regnum
);
6314 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6315 struct frame_info
*frame
)
6317 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6318 CORE_ADDR pc
= get_frame_pc (frame
);
6319 struct address_space
*aspace
;
6325 if ((mips_pc_is_mips (pc
)
6326 && !mips32_instruction_has_delay_slot (gdbarch
, pc
))
6327 || (mips_pc_is_micromips (gdbarch
, pc
)
6328 && !micromips_instruction_has_delay_slot (gdbarch
, pc
, 0))
6329 || (mips_pc_is_mips16 (gdbarch
, pc
)
6330 && !mips16_instruction_has_delay_slot (gdbarch
, pc
, 0)))
6333 isa
= mips_pc_isa (gdbarch
, pc
);
6334 /* _has_delay_slot above will have validated the read. */
6335 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6336 size
= mips_insn_size (isa
, insn
);
6337 aspace
= get_frame_address_space (frame
);
6338 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6341 /* To skip prologues, I use this predicate. Returns either PC itself
6342 if the code at PC does not look like a function prologue; otherwise
6343 returns an address that (if we're lucky) follows the prologue. If
6344 LENIENT, then we must skip everything which is involved in setting
6345 up the frame (it's OK to skip more, just so long as we don't skip
6346 anything which might clobber the registers which are being saved.
6347 We must skip more in the case where part of the prologue is in the
6348 delay slot of a non-prologue instruction). */
6351 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6354 CORE_ADDR func_addr
;
6356 /* See if we can determine the end of the prologue via the symbol table.
6357 If so, then return either PC, or the PC after the prologue, whichever
6359 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6361 CORE_ADDR post_prologue_pc
6362 = skip_prologue_using_sal (gdbarch
, func_addr
);
6363 if (post_prologue_pc
!= 0)
6364 return max (pc
, post_prologue_pc
);
6367 /* Can't determine prologue from the symbol table, need to examine
6370 /* Find an upper limit on the function prologue using the debug
6371 information. If the debug information could not be used to provide
6372 that bound, then use an arbitrary large number as the upper bound. */
6373 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6375 limit_pc
= pc
+ 100; /* Magic. */
6377 if (mips_pc_is_mips16 (gdbarch
, pc
))
6378 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6379 else if (mips_pc_is_micromips (gdbarch
, pc
))
6380 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6382 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6385 /* Check whether the PC is in a function epilogue (32-bit version).
6386 This is a helper function for mips_in_function_epilogue_p. */
6388 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6390 CORE_ADDR func_addr
= 0, func_end
= 0;
6392 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6394 /* The MIPS epilogue is max. 12 bytes long. */
6395 CORE_ADDR addr
= func_end
- 12;
6397 if (addr
< func_addr
+ 4)
6398 addr
= func_addr
+ 4;
6402 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6404 unsigned long high_word
;
6407 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6408 high_word
= (inst
>> 16) & 0xffff;
6410 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6411 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6412 && inst
!= 0x03e00008 /* jr $ra */
6413 && inst
!= 0x00000000) /* nop */
6423 /* Check whether the PC is in a function epilogue (microMIPS version).
6424 This is a helper function for mips_in_function_epilogue_p. */
6427 micromips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6429 CORE_ADDR func_addr
= 0;
6430 CORE_ADDR func_end
= 0;
6438 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6441 /* The microMIPS epilogue is max. 12 bytes long. */
6442 addr
= func_end
- 12;
6444 if (addr
< func_addr
+ 2)
6445 addr
= func_addr
+ 2;
6449 for (; pc
< func_end
; pc
+= loc
)
6452 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6453 loc
+= MIPS_INSN16_SIZE
;
6454 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6456 /* 48-bit instructions. */
6457 case 3 * MIPS_INSN16_SIZE
:
6458 /* No epilogue instructions in this category. */
6461 /* 32-bit instructions. */
6462 case 2 * MIPS_INSN16_SIZE
:
6464 insn
|= mips_fetch_instruction (gdbarch
,
6465 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6466 loc
+= MIPS_INSN16_SIZE
;
6467 switch (micromips_op (insn
>> 16))
6469 case 0xc: /* ADDIU: bits 001100 */
6470 case 0x17: /* DADDIU: bits 010111 */
6471 sreg
= b0s5_reg (insn
>> 16);
6472 dreg
= b5s5_reg (insn
>> 16);
6473 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6474 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6475 /* (D)ADDIU $sp, imm */
6485 /* 16-bit instructions. */
6486 case MIPS_INSN16_SIZE
:
6487 switch (micromips_op (insn
))
6489 case 0x3: /* MOVE: bits 000011 */
6490 sreg
= b0s5_reg (insn
);
6491 dreg
= b5s5_reg (insn
);
6492 if (sreg
== 0 && dreg
== 0)
6493 /* MOVE $zero, $zero aka NOP */
6497 case 0x11: /* POOL16C: bits 010001 */
6498 if (b5s5_op (insn
) == 0x18
6499 /* JRADDIUSP: bits 010011 11000 */
6500 || (b5s5_op (insn
) == 0xd
6501 /* JRC: bits 010011 01101 */
6502 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6507 case 0x13: /* POOL16D: bits 010011 */
6508 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6509 if ((insn
& 0x1) == 0x1
6510 /* ADDIUSP: bits 010011 1 */
6524 /* Check whether the PC is in a function epilogue (16-bit version).
6525 This is a helper function for mips_in_function_epilogue_p. */
6527 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6529 CORE_ADDR func_addr
= 0, func_end
= 0;
6531 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6533 /* The MIPS epilogue is max. 12 bytes long. */
6534 CORE_ADDR addr
= func_end
- 12;
6536 if (addr
< func_addr
+ 4)
6537 addr
= func_addr
+ 4;
6541 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6543 unsigned short inst
;
6545 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6547 if ((inst
& 0xf800) == 0xf000) /* extend */
6550 if (inst
!= 0x6300 /* addiu $sp,offset */
6551 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6552 && inst
!= 0xe820 /* jr $ra */
6553 && inst
!= 0xe8a0 /* jrc $ra */
6554 && inst
!= 0x6500) /* nop */
6564 /* The epilogue is defined here as the area at the end of a function,
6565 after an instruction which destroys the function's stack frame. */
6567 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6569 if (mips_pc_is_mips16 (gdbarch
, pc
))
6570 return mips16_in_function_epilogue_p (gdbarch
, pc
);
6571 else if (mips_pc_is_micromips (gdbarch
, pc
))
6572 return micromips_in_function_epilogue_p (gdbarch
, pc
);
6574 return mips32_in_function_epilogue_p (gdbarch
, pc
);
6577 /* Root of all "set mips "/"show mips " commands. This will eventually be
6578 used for all MIPS-specific commands. */
6581 show_mips_command (char *args
, int from_tty
)
6583 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6587 set_mips_command (char *args
, int from_tty
)
6590 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6591 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6594 /* Commands to show/set the MIPS FPU type. */
6597 show_mipsfpu_command (char *args
, int from_tty
)
6601 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6604 ("The MIPS floating-point coprocessor is unknown "
6605 "because the current architecture is not MIPS.\n");
6609 switch (MIPS_FPU_TYPE (target_gdbarch
))
6611 case MIPS_FPU_SINGLE
:
6612 fpu
= "single-precision";
6614 case MIPS_FPU_DOUBLE
:
6615 fpu
= "double-precision";
6618 fpu
= "absent (none)";
6621 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6623 if (mips_fpu_type_auto
)
6624 printf_unfiltered ("The MIPS floating-point coprocessor "
6625 "is set automatically (currently %s)\n",
6629 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6634 set_mipsfpu_command (char *args
, int from_tty
)
6636 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6637 "\"single\",\"none\" or \"auto\".\n");
6638 show_mipsfpu_command (args
, from_tty
);
6642 set_mipsfpu_single_command (char *args
, int from_tty
)
6644 struct gdbarch_info info
;
6645 gdbarch_info_init (&info
);
6646 mips_fpu_type
= MIPS_FPU_SINGLE
;
6647 mips_fpu_type_auto
= 0;
6648 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6649 instead of relying on globals. Doing that would let generic code
6650 handle the search for this specific architecture. */
6651 if (!gdbarch_update_p (info
))
6652 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6656 set_mipsfpu_double_command (char *args
, int from_tty
)
6658 struct gdbarch_info info
;
6659 gdbarch_info_init (&info
);
6660 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6661 mips_fpu_type_auto
= 0;
6662 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6663 instead of relying on globals. Doing that would let generic code
6664 handle the search for this specific architecture. */
6665 if (!gdbarch_update_p (info
))
6666 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6670 set_mipsfpu_none_command (char *args
, int from_tty
)
6672 struct gdbarch_info info
;
6673 gdbarch_info_init (&info
);
6674 mips_fpu_type
= MIPS_FPU_NONE
;
6675 mips_fpu_type_auto
= 0;
6676 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6677 instead of relying on globals. Doing that would let generic code
6678 handle the search for this specific architecture. */
6679 if (!gdbarch_update_p (info
))
6680 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6684 set_mipsfpu_auto_command (char *args
, int from_tty
)
6686 mips_fpu_type_auto
= 1;
6689 /* Attempt to identify the particular processor model by reading the
6690 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
6691 the relevant processor still exists (it dates back to '94) and
6692 secondly this is not the way to do this. The processor type should
6693 be set by forcing an architecture change. */
6696 deprecated_mips_set_processor_regs_hack (void)
6698 struct regcache
*regcache
= get_current_regcache ();
6699 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6700 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6703 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
6704 if ((prid
& ~0xf) == 0x700)
6705 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
6708 /* Just like reinit_frame_cache, but with the right arguments to be
6709 callable as an sfunc. */
6712 reinit_frame_cache_sfunc (char *args
, int from_tty
,
6713 struct cmd_list_element
*c
)
6715 reinit_frame_cache ();
6719 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6721 struct gdbarch
*gdbarch
= info
->application_data
;
6723 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6724 disassembler needs to be able to locally determine the ISA, and
6725 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6727 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6728 info
->mach
= bfd_mach_mips16
;
6729 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6730 info
->mach
= bfd_mach_mips_micromips
;
6732 /* Round down the instruction address to the appropriate boundary. */
6733 memaddr
&= (info
->mach
== bfd_mach_mips16
6734 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
6736 /* Set the disassembler options. */
6737 if (!info
->disassembler_options
)
6738 /* This string is not recognized explicitly by the disassembler,
6739 but it tells the disassembler to not try to guess the ABI from
6740 the bfd elf headers, such that, if the user overrides the ABI
6741 of a program linked as NewABI, the disassembly will follow the
6742 register naming conventions specified by the user. */
6743 info
->disassembler_options
= "gpr-names=32";
6745 /* Call the appropriate disassembler based on the target endian-ness. */
6746 if (info
->endian
== BFD_ENDIAN_BIG
)
6747 return print_insn_big_mips (memaddr
, info
);
6749 return print_insn_little_mips (memaddr
, info
);
6753 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
6755 /* Set up the disassembler info, so that we get the right
6756 register names from libopcodes. */
6757 info
->disassembler_options
= "gpr-names=n32";
6758 info
->flavour
= bfd_target_elf_flavour
;
6760 return gdb_print_insn_mips (memaddr
, info
);
6764 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
6766 /* Set up the disassembler info, so that we get the right
6767 register names from libopcodes. */
6768 info
->disassembler_options
= "gpr-names=64";
6769 info
->flavour
= bfd_target_elf_flavour
;
6771 return gdb_print_insn_mips (memaddr
, info
);
6774 /* This function implements gdbarch_breakpoint_from_pc. It uses the
6775 program counter value to determine whether a 16- or 32-bit breakpoint
6776 should be used. It returns a pointer to a string of bytes that encode a
6777 breakpoint instruction, stores the length of the string to *lenptr, and
6778 adjusts pc (if necessary) to point to the actual memory location where
6779 the breakpoint should be inserted. */
6781 static const gdb_byte
*
6782 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
6783 CORE_ADDR
*pcptr
, int *lenptr
)
6785 CORE_ADDR pc
= *pcptr
;
6787 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6789 if (mips_pc_is_mips16 (gdbarch
, pc
))
6791 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
6792 *pcptr
= unmake_compact_addr (pc
);
6793 *lenptr
= sizeof (mips16_big_breakpoint
);
6794 return mips16_big_breakpoint
;
6796 else if (mips_pc_is_micromips (gdbarch
, pc
))
6798 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
6799 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
6804 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6806 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6807 *pcptr
= unmake_compact_addr (pc
);
6809 return (size
== 2) ? micromips16_big_breakpoint
6810 : micromips32_big_breakpoint
;
6814 /* The IDT board uses an unusual breakpoint value, and
6815 sometimes gets confused when it sees the usual MIPS
6816 breakpoint instruction. */
6817 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
6818 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
6819 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
6820 /* Likewise, IRIX appears to expect a different breakpoint,
6821 although this is not apparent until you try to use pthreads. */
6822 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
6824 *lenptr
= sizeof (big_breakpoint
);
6826 if (strcmp (target_shortname
, "mips") == 0)
6827 return idt_big_breakpoint
;
6828 else if (strcmp (target_shortname
, "ddb") == 0
6829 || strcmp (target_shortname
, "pmon") == 0
6830 || strcmp (target_shortname
, "lsi") == 0)
6831 return pmon_big_breakpoint
;
6832 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
6833 return irix_big_breakpoint
;
6835 return big_breakpoint
;
6840 if (mips_pc_is_mips16 (gdbarch
, pc
))
6842 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
6843 *pcptr
= unmake_compact_addr (pc
);
6844 *lenptr
= sizeof (mips16_little_breakpoint
);
6845 return mips16_little_breakpoint
;
6847 else if (mips_pc_is_micromips (gdbarch
, pc
))
6849 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
6850 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
6855 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6857 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6858 *pcptr
= unmake_compact_addr (pc
);
6860 return (size
== 2) ? micromips16_little_breakpoint
6861 : micromips32_little_breakpoint
;
6865 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
6866 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
6867 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
6869 *lenptr
= sizeof (little_breakpoint
);
6871 if (strcmp (target_shortname
, "mips") == 0)
6872 return idt_little_breakpoint
;
6873 else if (strcmp (target_shortname
, "ddb") == 0
6874 || strcmp (target_shortname
, "pmon") == 0
6875 || strcmp (target_shortname
, "lsi") == 0)
6876 return pmon_little_breakpoint
;
6878 return little_breakpoint
;
6883 /* Determine the remote breakpoint kind suitable for the PC. The following
6886 * 2 -- 16-bit MIPS16 mode breakpoint,
6888 * 3 -- 16-bit microMIPS mode breakpoint,
6890 * 4 -- 32-bit standard MIPS mode breakpoint,
6892 * 5 -- 32-bit microMIPS mode breakpoint. */
6895 mips_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
6898 CORE_ADDR pc
= *pcptr
;
6900 if (mips_pc_is_mips16 (gdbarch
, pc
))
6902 *pcptr
= unmake_compact_addr (pc
);
6905 else if (mips_pc_is_micromips (gdbarch
, pc
))
6911 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6912 size
= status
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6913 *pcptr
= unmake_compact_addr (pc
);
6914 *kindptr
= size
| 1;
6920 /* Return non-zero if the ADDR instruction has a branch delay slot
6921 (i.e. it is a jump or branch instruction). This function is based
6922 on mips32_next_pc. */
6925 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
6933 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
6937 op
= itype_op (inst
);
6938 if ((inst
& 0xe0000000) != 0)
6940 rs
= itype_rs (inst
);
6941 rt
= itype_rt (inst
);
6942 return (op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
6943 || op
== 29 /* JALX: bits 011101 */
6946 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
6947 || (rs
== 9 && (rt
& 0x2) == 0)
6948 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
6949 || (rs
== 10 && (rt
& 0x2) == 0))));
6950 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
6953 switch (op
& 0x07) /* extract bits 28,27,26 */
6955 case 0: /* SPECIAL */
6956 op
= rtype_funct (inst
);
6957 return (op
== 8 /* JR */
6958 || op
== 9); /* JALR */
6959 break; /* end SPECIAL */
6960 case 1: /* REGIMM */
6961 rs
= itype_rs (inst
);
6962 rt
= itype_rt (inst
); /* branch condition */
6963 return ((rt
& 0xc) == 0
6964 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
6965 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
6966 || ((rt
& 0x1e) == 0x1c && rs
== 0));
6967 /* BPOSGE32, BPOSGE64: bits 1110x */
6968 break; /* end REGIMM */
6969 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
6975 /* Return non-zero if the ADDR instruction, which must be a 32-bit
6976 instruction if MUSTBE32 is set or can be any instruction otherwise,
6977 has a branch delay slot (i.e. it is a non-compact jump instruction). */
6980 micromips_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
6981 CORE_ADDR addr
, int mustbe32
)
6986 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
6990 if (!mustbe32
) /* 16-bit instructions. */
6991 return (micromips_op (insn
) == 0x11
6992 /* POOL16C: bits 010001 */
6993 && (b5s5_op (insn
) == 0xc
6994 /* JR16: bits 010001 01100 */
6995 || (b5s5_op (insn
) & 0x1e) == 0xe))
6996 /* JALR16, JALRS16: bits 010001 0111x */
6997 || (micromips_op (insn
) & 0x37) == 0x23
6998 /* BEQZ16, BNEZ16: bits 10x011 */
6999 || micromips_op (insn
) == 0x33;
7000 /* B16: bits 110011 */
7002 /* 32-bit instructions. */
7003 if (micromips_op (insn
) == 0x0)
7004 /* POOL32A: bits 000000 */
7007 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7010 return b0s6_op (insn
) == 0x3c
7011 /* POOL32Axf: bits 000000 ... 111100 */
7012 && (b6s10_ext (insn
) & 0x2bf) == 0x3c;
7013 /* JALR, JALR.HB: 000000 000x111100 111100 */
7014 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7017 return (micromips_op (insn
) == 0x10
7018 /* POOL32I: bits 010000 */
7019 && ((b5s5_op (insn
) & 0x1c) == 0x0
7020 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7021 || (b5s5_op (insn
) & 0x1d) == 0x4
7022 /* BLEZ, BGTZ: bits 010000 001x0 */
7023 || (b5s5_op (insn
) & 0x1d) == 0x11
7024 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7025 || ((b5s5_op (insn
) & 0x1e) == 0x14
7026 && (insn
& 0x3) == 0x0)
7027 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7028 || (b5s5_op (insn
) & 0x1e) == 0x1a
7029 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7030 || ((b5s5_op (insn
) & 0x1e) == 0x1c
7031 && (insn
& 0x3) == 0x0)
7032 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7033 || ((b5s5_op (insn
) & 0x1c) == 0x1c
7034 && (insn
& 0x3) == 0x1)))
7035 /* BC1ANY*: bits 010000 111xx xxx01 */
7036 || (micromips_op (insn
) & 0x1f) == 0x1d
7037 /* JALS, JAL: bits x11101 */
7038 || (micromips_op (insn
) & 0x37) == 0x25
7039 /* BEQ, BNE: bits 10x101 */
7040 || micromips_op (insn
) == 0x35
7041 /* J: bits 110101 */
7042 || micromips_op (insn
) == 0x3c;
7043 /* JALX: bits 111100 */
7047 mips16_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
7050 unsigned short inst
;
7053 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7058 return (inst
& 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
7059 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7062 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7063 This assumes KSSEG exists. */
7066 mips_segment_boundary (CORE_ADDR bpaddr
)
7068 CORE_ADDR mask
= CORE_ADDR_MAX
;
7071 if (sizeof (CORE_ADDR
) == 8)
7072 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7073 a compiler warning produced where CORE_ADDR is a 32-bit type even
7074 though in that case this is dead code). */
7075 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7078 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7079 segsize
= 29; /* 32-bit compatibility segment */
7081 segsize
= 62; /* xkseg */
7083 case 2: /* xkphys */
7086 default: /* xksseg (1), xkuseg/kuseg (0) */
7090 else if (bpaddr
& 0x80000000) /* kernel segment */
7093 segsize
= 31; /* user segment */
7095 return bpaddr
& mask
;
7098 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7099 it backwards if necessary. Return the address of the new location. */
7102 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7104 CORE_ADDR prev_addr
;
7106 CORE_ADDR func_addr
;
7108 /* If a breakpoint is set on the instruction in a branch delay slot,
7109 GDB gets confused. When the breakpoint is hit, the PC isn't on
7110 the instruction in the branch delay slot, the PC will point to
7111 the branch instruction. Since the PC doesn't match any known
7112 breakpoints, GDB reports a trap exception.
7114 There are two possible fixes for this problem.
7116 1) When the breakpoint gets hit, see if the BD bit is set in the
7117 Cause register (which indicates the last exception occurred in a
7118 branch delay slot). If the BD bit is set, fix the PC to point to
7119 the instruction in the branch delay slot.
7121 2) When the user sets the breakpoint, don't allow him to set the
7122 breakpoint on the instruction in the branch delay slot. Instead
7123 move the breakpoint to the branch instruction (which will have
7126 The problem with the first solution is that if the user then
7127 single-steps the processor, the branch instruction will get
7128 skipped (since GDB thinks the PC is on the instruction in the
7131 So, we'll use the second solution. To do this we need to know if
7132 the instruction we're trying to set the breakpoint on is in the
7133 branch delay slot. */
7135 boundary
= mips_segment_boundary (bpaddr
);
7137 /* Make sure we don't scan back before the beginning of the current
7138 function, since we may fetch constant data or insns that look like
7139 a jump. Of course we might do that anyway if the compiler has
7140 moved constants inline. :-( */
7141 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7142 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7143 boundary
= func_addr
;
7145 if (mips_pc_is_mips (bpaddr
))
7147 if (bpaddr
== boundary
)
7150 /* If the previous instruction has a branch delay slot, we have
7151 to move the breakpoint to the branch instruction. */
7152 prev_addr
= bpaddr
- 4;
7153 if (mips32_instruction_has_delay_slot (gdbarch
, prev_addr
))
7158 int (*instruction_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7159 CORE_ADDR addr
, jmpaddr
;
7162 boundary
= unmake_compact_addr (boundary
);
7164 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7165 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7166 so try for that first, then try the 2 byte JALR/JR.
7167 The microMIPS ASE has a whole range of jumps and branches
7168 with delay slots, some of which take 4 bytes and some take
7169 2 bytes, so the idea is the same.
7170 FIXME: We have to assume that bpaddr is not the second half
7171 of an extended instruction. */
7172 instruction_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7173 ? micromips_instruction_has_delay_slot
7174 : mips16_instruction_has_delay_slot
);
7178 for (i
= 1; i
< 4; i
++)
7180 if (unmake_compact_addr (addr
) == boundary
)
7182 addr
-= MIPS_INSN16_SIZE
;
7183 if (i
== 1 && instruction_has_delay_slot (gdbarch
, addr
, 0))
7184 /* Looks like a JR/JALR at [target-1], but it could be
7185 the second word of a previous JAL/JALX, so record it
7186 and check back one more. */
7188 else if (i
> 1 && instruction_has_delay_slot (gdbarch
, addr
, 1))
7191 /* Looks like a JAL/JALX at [target-2], but it could also
7192 be the second word of a previous JAL/JALX, record it,
7193 and check back one more. */
7196 /* Looks like a JAL/JALX at [target-3], so any previously
7197 recorded JAL/JALX or JR/JALR must be wrong, because:
7200 -2: JAL-ext (can't be JAL/JALX)
7201 -1: bdslot (can't be JR/JALR)
7204 Of course it could be another JAL-ext which looks
7205 like a JAL, but in that case we'd have broken out
7206 of this loop at [target-2]:
7210 -2: bdslot (can't be jmp)
7217 /* Not a jump instruction: if we're at [target-1] this
7218 could be the second word of a JAL/JALX, so continue;
7219 otherwise we're done. */
7232 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7233 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7236 mips_is_stub_suffix (const char *suffix
, int zero
)
7241 return zero
&& suffix
[1] == '\0';
7243 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7248 return suffix
[1] == '\0';
7254 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7255 call stubs, one of sf, df, sc, or dc. */
7258 mips_is_stub_mode (const char *mode
)
7260 return ((mode
[0] == 's' || mode
[0] == 'd')
7261 && (mode
[1] == 'f' || mode
[1] == 'c'));
7264 /* Code at PC is a compiler-generated stub. Such a stub for a function
7265 bar might have a name like __fn_stub_bar, and might look like this:
7272 followed by (or interspersed with):
7279 addiu $25, $25, %lo(bar)
7282 ($1 may be used in old code; for robustness we accept any register)
7285 lui $28, %hi(_gp_disp)
7286 addiu $28, $28, %lo(_gp_disp)
7289 addiu $25, $25, %lo(bar)
7292 In the case of a __call_stub_bar stub, the sequence to set up
7293 arguments might look like this:
7300 followed by (or interspersed with) one of the jump sequences above.
7302 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7303 of J or JR, respectively, followed by:
7309 We are at the beginning of the stub here, and scan down and extract
7310 the target address from the jump immediate instruction or, if a jump
7311 register instruction is used, from the register referred. Return
7312 the value of PC calculated or 0 if inconclusive.
7314 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7317 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7319 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7320 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7321 int addrreg
= MIPS_ZERO_REGNUM
;
7322 CORE_ADDR start_pc
= pc
;
7323 CORE_ADDR target_pc
= 0;
7330 status
== 0 && target_pc
== 0 && i
< 20;
7331 i
++, pc
+= MIPS_INSN32_SIZE
)
7333 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7339 switch (itype_op (inst
))
7341 case 0: /* SPECIAL */
7342 switch (rtype_funct (inst
))
7346 rs
= rtype_rs (inst
);
7347 if (rs
== MIPS_GP_REGNUM
)
7348 target_pc
= gp
; /* Hmm... */
7349 else if (rs
== addrreg
)
7353 case 0x21: /* ADDU */
7354 rt
= rtype_rt (inst
);
7355 rs
= rtype_rs (inst
);
7356 rd
= rtype_rd (inst
);
7357 if (rd
== MIPS_GP_REGNUM
7358 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7359 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7367 target_pc
= jtype_target (inst
) << 2;
7368 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7372 rt
= itype_rt (inst
);
7373 rs
= itype_rs (inst
);
7376 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7377 if (rt
== MIPS_GP_REGNUM
)
7379 else if (rt
== addrreg
)
7385 rt
= itype_rt (inst
);
7386 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7387 if (rt
== MIPS_GP_REGNUM
)
7389 else if (rt
!= MIPS_ZERO_REGNUM
)
7397 rt
= itype_rt (inst
);
7398 rs
= itype_rs (inst
);
7399 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7400 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7404 memset (buf
, 0, sizeof (buf
));
7405 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7407 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7416 /* If PC is in a MIPS16 call or return stub, return the address of the
7417 target PC, which is either the callee or the caller. There are several
7418 cases which must be handled:
7420 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7421 and the target PC is in $31 ($ra).
7422 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7423 and the target PC is in $2.
7424 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7425 i.e. before the JALR instruction, this is effectively a call stub
7426 and the target PC is in $2. Otherwise this is effectively
7427 a return stub and the target PC is in $18.
7428 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7429 JAL or JALR instruction, this is effectively a call stub and the
7430 target PC is buried in the instruction stream. Otherwise this
7431 is effectively a return stub and the target PC is in $18.
7432 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7433 stub and the target PC is buried in the instruction stream.
7435 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7436 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7440 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7442 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7443 CORE_ADDR start_addr
;
7447 /* Find the starting address and name of the function containing the PC. */
7448 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7451 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7452 and the target PC is in $31 ($ra). */
7453 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7454 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7455 && mips_is_stub_mode (name
+ prefixlen
)
7456 && name
[prefixlen
+ 2] == '\0')
7457 return get_frame_register_signed
7458 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7460 /* If the PC is in __mips16_call_stub_*, this is one of the call
7461 call/return stubs. */
7462 prefixlen
= strlen (mips_str_mips16_call_stub
);
7463 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7465 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7466 and the target PC is in $2. */
7467 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7468 return get_frame_register_signed
7469 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7471 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7472 i.e. before the JALR instruction, this is effectively a call stub
7473 and the target PC is in $2. Otherwise this is effectively
7474 a return stub and the target PC is in $18. */
7475 else if (mips_is_stub_mode (name
+ prefixlen
)
7476 && name
[prefixlen
+ 2] == '_'
7477 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7479 if (pc
== start_addr
)
7480 /* This is the 'call' part of a call stub. The return
7481 address is in $2. */
7482 return get_frame_register_signed
7483 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7485 /* This is the 'return' part of a call stub. The return
7486 address is in $18. */
7487 return get_frame_register_signed
7488 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7491 return 0; /* Not a stub. */
7494 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7495 compiler-generated call or call/return stubs. */
7496 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0
7497 || strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
7499 if (pc
== start_addr
)
7500 /* This is the 'call' part of a call stub. Call this helper
7501 to scan through this code for interesting instructions
7502 and determine the final PC. */
7503 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7505 /* This is the 'return' part of a call stub. The return address
7507 return get_frame_register_signed
7508 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7511 return 0; /* Not a stub. */
7514 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7515 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7518 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7520 CORE_ADDR start_addr
;
7523 /* Find the starting address of the function containing the PC. */
7524 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7527 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7528 the start, i.e. after the JALR instruction, this is effectively
7530 prefixlen
= strlen (mips_str_mips16_call_stub
);
7531 if (pc
!= start_addr
7532 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7533 && mips_is_stub_mode (name
+ prefixlen
)
7534 && name
[prefixlen
+ 2] == '_'
7535 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7538 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7539 the JAL or JALR instruction, this is effectively a return stub. */
7540 prefixlen
= strlen (mips_str_call_fp_stub
);
7541 if (pc
!= start_addr
7542 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7545 /* Consume the .pic. prefix of any PIC stub, this function must return
7546 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7547 or the call stub path will trigger in handle_inferior_event causing
7549 prefixlen
= strlen (mips_str_pic
);
7550 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7553 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7554 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7555 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7556 && mips_is_stub_mode (name
+ prefixlen
)
7557 && name
[prefixlen
+ 2] == '\0')
7560 return 0; /* Not a stub. */
7563 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7564 PC of the stub target. The stub just loads $t9 and jumps to it,
7565 so that $t9 has the correct value at function entry. */
7568 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7570 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7571 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7572 struct minimal_symbol
*msym
;
7574 gdb_byte stub_code
[16];
7575 int32_t stub_words
[4];
7577 /* The stub for foo is named ".pic.foo", and is either two
7578 instructions inserted before foo or a three instruction sequence
7579 which jumps to foo. */
7580 msym
= lookup_minimal_symbol_by_pc (pc
);
7582 || SYMBOL_VALUE_ADDRESS (msym
) != pc
7583 || SYMBOL_LINKAGE_NAME (msym
) == NULL
7584 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
7587 /* A two-instruction header. */
7588 if (MSYMBOL_SIZE (msym
) == 8)
7591 /* A three-instruction (plus delay slot) trampoline. */
7592 if (MSYMBOL_SIZE (msym
) == 16)
7594 if (target_read_memory (pc
, stub_code
, 16) != 0)
7596 for (i
= 0; i
< 4; i
++)
7597 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7600 /* A stub contains these instructions:
7603 addiu t9, t9, %lo(target)
7606 This works even for N64, since stubs are only generated with
7608 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7609 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7610 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7611 && stub_words
[3] == 0x00000000)
7612 return ((((stub_words
[0] & 0x0000ffff) << 16)
7613 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7616 /* Not a recognized stub. */
7621 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7623 CORE_ADDR requested_pc
= pc
;
7624 CORE_ADDR target_pc
;
7631 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7635 if (is_compact_addr (pc
))
7636 pc
= unmake_compact_addr (pc
);
7639 new_pc
= find_solib_trampoline_target (frame
, pc
);
7643 if (is_compact_addr (pc
))
7644 pc
= unmake_compact_addr (pc
);
7647 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7651 if (is_compact_addr (pc
))
7652 pc
= unmake_compact_addr (pc
);
7655 while (pc
!= target_pc
);
7657 return pc
!= requested_pc
? pc
: 0;
7660 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7661 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7664 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7667 if (num
>= 0 && num
< 32)
7669 else if (num
>= 38 && num
< 70)
7670 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7672 regnum
= mips_regnum (gdbarch
)->hi
;
7674 regnum
= mips_regnum (gdbarch
)->lo
;
7675 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7676 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7678 /* This will hopefully (eventually) provoke a warning. Should
7679 we be calling complaint() here? */
7680 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7681 return gdbarch_num_regs (gdbarch
) + regnum
;
7685 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7686 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7689 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7692 if (num
>= 0 && num
< 32)
7694 else if (num
>= 32 && num
< 64)
7695 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7697 regnum
= mips_regnum (gdbarch
)->hi
;
7699 regnum
= mips_regnum (gdbarch
)->lo
;
7700 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7701 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7703 /* This will hopefully (eventually) provoke a warning. Should we
7704 be calling complaint() here? */
7705 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7706 return gdbarch_num_regs (gdbarch
) + regnum
;
7710 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7712 /* Only makes sense to supply raw registers. */
7713 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7714 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7715 decide if it is valid. Should instead define a standard sim/gdb
7716 register numbering scheme. */
7717 if (gdbarch_register_name (gdbarch
,
7718 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7719 && gdbarch_register_name (gdbarch
,
7720 gdbarch_num_regs (gdbarch
)
7721 + regnum
)[0] != '\0')
7724 return LEGACY_SIM_REGNO_IGNORE
;
7728 /* Convert an integer into an address. Extracting the value signed
7729 guarantees a correctly sign extended address. */
7732 mips_integer_to_address (struct gdbarch
*gdbarch
,
7733 struct type
*type
, const gdb_byte
*buf
)
7735 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7736 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7739 /* Dummy virtual frame pointer method. This is no more or less accurate
7740 than most other architectures; we just need to be explicit about it,
7741 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7742 an assertion failure. */
7745 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7746 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7748 *reg
= MIPS_SP_REGNUM
;
7753 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7755 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7756 const char *name
= bfd_get_section_name (abfd
, sect
);
7758 if (*abip
!= MIPS_ABI_UNKNOWN
)
7761 if (strncmp (name
, ".mdebug.", 8) != 0)
7764 if (strcmp (name
, ".mdebug.abi32") == 0)
7765 *abip
= MIPS_ABI_O32
;
7766 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7767 *abip
= MIPS_ABI_N32
;
7768 else if (strcmp (name
, ".mdebug.abi64") == 0)
7769 *abip
= MIPS_ABI_N64
;
7770 else if (strcmp (name
, ".mdebug.abiO64") == 0)
7771 *abip
= MIPS_ABI_O64
;
7772 else if (strcmp (name
, ".mdebug.eabi32") == 0)
7773 *abip
= MIPS_ABI_EABI32
;
7774 else if (strcmp (name
, ".mdebug.eabi64") == 0)
7775 *abip
= MIPS_ABI_EABI64
;
7777 warning (_("unsupported ABI %s."), name
+ 8);
7781 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
7783 int *lbp
= (int *) obj
;
7784 const char *name
= bfd_get_section_name (abfd
, sect
);
7786 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
7788 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
7790 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
7791 warning (_("unrecognized .gcc_compiled_longXX"));
7794 static enum mips_abi
7795 global_mips_abi (void)
7799 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
7800 if (mips_abi_strings
[i
] == mips_abi_string
)
7801 return (enum mips_abi
) i
;
7803 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
7806 /* Return the default compressed instruction set, either of MIPS16
7807 or microMIPS, selected when none could have been determined from
7808 the ELF header of the binary being executed (or no binary has been
7811 static enum mips_isa
7812 global_mips_compression (void)
7816 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
7817 if (mips_compression_strings
[i
] == mips_compression_string
)
7818 return (enum mips_isa
) i
;
7820 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
7824 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
7826 /* If the size matches the set of 32-bit or 64-bit integer registers,
7827 assume that's what we've got. */
7828 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
7829 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
7831 /* If the size matches the full set of registers GDB traditionally
7832 knows about, including floating point, for either 32-bit or
7833 64-bit, assume that's what we've got. */
7834 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
7835 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
7837 /* Otherwise we don't have a useful guess. */
7840 static struct value
*
7841 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
7843 const int *reg_p
= baton
;
7844 return value_of_register (*reg_p
, frame
);
7847 static struct gdbarch
*
7848 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7850 struct gdbarch
*gdbarch
;
7851 struct gdbarch_tdep
*tdep
;
7853 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
7855 enum mips_fpu_type fpu_type
;
7856 struct tdesc_arch_data
*tdesc_data
= NULL
;
7857 int elf_fpu_type
= 0;
7858 const char **reg_names
;
7859 struct mips_regnum mips_regnum
, *regnum
;
7860 enum mips_isa mips_isa
;
7864 /* Fill in the OS dependent register numbers and names. */
7865 if (info
.osabi
== GDB_OSABI_IRIX
)
7867 mips_regnum
.fp0
= 32;
7868 mips_regnum
.pc
= 64;
7869 mips_regnum
.cause
= 65;
7870 mips_regnum
.badvaddr
= 66;
7871 mips_regnum
.hi
= 67;
7872 mips_regnum
.lo
= 68;
7873 mips_regnum
.fp_control_status
= 69;
7874 mips_regnum
.fp_implementation_revision
= 70;
7875 mips_regnum
.dspacc
= dspacc
= -1;
7876 mips_regnum
.dspctl
= dspctl
= -1;
7878 reg_names
= mips_irix_reg_names
;
7880 else if (info
.osabi
== GDB_OSABI_LINUX
)
7882 mips_regnum
.fp0
= 38;
7883 mips_regnum
.pc
= 37;
7884 mips_regnum
.cause
= 36;
7885 mips_regnum
.badvaddr
= 35;
7886 mips_regnum
.hi
= 34;
7887 mips_regnum
.lo
= 33;
7888 mips_regnum
.fp_control_status
= 70;
7889 mips_regnum
.fp_implementation_revision
= 71;
7890 mips_regnum
.dspacc
= -1;
7891 mips_regnum
.dspctl
= -1;
7895 reg_names
= mips_linux_reg_names
;
7899 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
7900 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
7901 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
7902 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
7903 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
7904 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
7905 mips_regnum
.fp_control_status
= 70;
7906 mips_regnum
.fp_implementation_revision
= 71;
7907 mips_regnum
.dspacc
= dspacc
= -1;
7908 mips_regnum
.dspctl
= dspctl
= -1;
7909 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
7910 if (info
.bfd_arch_info
!= NULL
7911 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
7912 reg_names
= mips_tx39_reg_names
;
7914 reg_names
= mips_generic_reg_names
;
7917 /* Check any target description for validity. */
7918 if (tdesc_has_registers (info
.target_desc
))
7920 static const char *const mips_gprs
[] = {
7921 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7922 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7923 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
7924 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
7926 static const char *const mips_fprs
[] = {
7927 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
7928 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
7929 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
7930 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
7933 const struct tdesc_feature
*feature
;
7936 feature
= tdesc_find_feature (info
.target_desc
,
7937 "org.gnu.gdb.mips.cpu");
7938 if (feature
== NULL
)
7941 tdesc_data
= tdesc_data_alloc ();
7944 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
7945 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
7949 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7950 mips_regnum
.lo
, "lo");
7951 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7952 mips_regnum
.hi
, "hi");
7953 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7954 mips_regnum
.pc
, "pc");
7958 tdesc_data_cleanup (tdesc_data
);
7962 feature
= tdesc_find_feature (info
.target_desc
,
7963 "org.gnu.gdb.mips.cp0");
7964 if (feature
== NULL
)
7966 tdesc_data_cleanup (tdesc_data
);
7971 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7972 mips_regnum
.badvaddr
, "badvaddr");
7973 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7974 MIPS_PS_REGNUM
, "status");
7975 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7976 mips_regnum
.cause
, "cause");
7980 tdesc_data_cleanup (tdesc_data
);
7984 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
7985 backend is not prepared for that, though. */
7986 feature
= tdesc_find_feature (info
.target_desc
,
7987 "org.gnu.gdb.mips.fpu");
7988 if (feature
== NULL
)
7990 tdesc_data_cleanup (tdesc_data
);
7995 for (i
= 0; i
< 32; i
++)
7996 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7997 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
7999 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8000 mips_regnum
.fp_control_status
,
8003 &= tdesc_numbered_register (feature
, tdesc_data
,
8004 mips_regnum
.fp_implementation_revision
,
8009 tdesc_data_cleanup (tdesc_data
);
8015 feature
= tdesc_find_feature (info
.target_desc
,
8016 "org.gnu.gdb.mips.dsp");
8017 /* The DSP registers are optional; it's OK if they are absent. */
8018 if (feature
!= NULL
)
8022 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8023 dspacc
+ i
++, "hi1");
8024 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8025 dspacc
+ i
++, "lo1");
8026 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8027 dspacc
+ i
++, "hi2");
8028 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8029 dspacc
+ i
++, "lo2");
8030 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8031 dspacc
+ i
++, "hi3");
8032 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8033 dspacc
+ i
++, "lo3");
8035 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8040 tdesc_data_cleanup (tdesc_data
);
8044 mips_regnum
.dspacc
= dspacc
;
8045 mips_regnum
.dspctl
= dspctl
;
8049 /* It would be nice to detect an attempt to use a 64-bit ABI
8050 when only 32-bit registers are provided. */
8054 /* First of all, extract the elf_flags, if available. */
8055 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8056 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8057 else if (arches
!= NULL
)
8058 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8062 fprintf_unfiltered (gdb_stdlog
,
8063 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8065 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8066 switch ((elf_flags
& EF_MIPS_ABI
))
8068 case E_MIPS_ABI_O32
:
8069 found_abi
= MIPS_ABI_O32
;
8071 case E_MIPS_ABI_O64
:
8072 found_abi
= MIPS_ABI_O64
;
8074 case E_MIPS_ABI_EABI32
:
8075 found_abi
= MIPS_ABI_EABI32
;
8077 case E_MIPS_ABI_EABI64
:
8078 found_abi
= MIPS_ABI_EABI64
;
8081 if ((elf_flags
& EF_MIPS_ABI2
))
8082 found_abi
= MIPS_ABI_N32
;
8084 found_abi
= MIPS_ABI_UNKNOWN
;
8088 /* GCC creates a pseudo-section whose name describes the ABI. */
8089 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8090 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8092 /* If we have no useful BFD information, use the ABI from the last
8093 MIPS architecture (if there is one). */
8094 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8095 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8097 /* Try the architecture for any hint of the correct ABI. */
8098 if (found_abi
== MIPS_ABI_UNKNOWN
8099 && info
.bfd_arch_info
!= NULL
8100 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8102 switch (info
.bfd_arch_info
->mach
)
8104 case bfd_mach_mips3900
:
8105 found_abi
= MIPS_ABI_EABI32
;
8107 case bfd_mach_mips4100
:
8108 case bfd_mach_mips5000
:
8109 found_abi
= MIPS_ABI_EABI64
;
8111 case bfd_mach_mips8000
:
8112 case bfd_mach_mips10000
:
8113 /* On Irix, ELF64 executables use the N64 ABI. The
8114 pseudo-sections which describe the ABI aren't present
8115 on IRIX. (Even for executables created by gcc.) */
8116 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8117 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8118 found_abi
= MIPS_ABI_N64
;
8120 found_abi
= MIPS_ABI_N32
;
8125 /* Default 64-bit objects to N64 instead of O32. */
8126 if (found_abi
== MIPS_ABI_UNKNOWN
8127 && info
.abfd
!= NULL
8128 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8129 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8130 found_abi
= MIPS_ABI_N64
;
8133 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8136 /* What has the user specified from the command line? */
8137 wanted_abi
= global_mips_abi ();
8139 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8142 /* Now that we have found what the ABI for this binary would be,
8143 check whether the user is overriding it. */
8144 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8145 mips_abi
= wanted_abi
;
8146 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8147 mips_abi
= found_abi
;
8149 mips_abi
= MIPS_ABI_O32
;
8151 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8154 /* Determine the default compressed ISA. */
8155 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8156 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8157 mips_isa
= ISA_MICROMIPS
;
8158 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8159 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8160 mips_isa
= ISA_MIPS16
;
8162 mips_isa
= global_mips_compression ();
8163 mips_compression_string
= mips_compression_strings
[mips_isa
];
8165 /* Also used when doing an architecture lookup. */
8167 fprintf_unfiltered (gdb_stdlog
,
8168 "mips_gdbarch_init: "
8169 "mips64_transfers_32bit_regs_p = %d\n",
8170 mips64_transfers_32bit_regs_p
);
8172 /* Determine the MIPS FPU type. */
8175 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8176 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8177 Tag_GNU_MIPS_ABI_FP
);
8178 #endif /* HAVE_ELF */
8180 if (!mips_fpu_type_auto
)
8181 fpu_type
= mips_fpu_type
;
8182 else if (elf_fpu_type
!= 0)
8184 switch (elf_fpu_type
)
8187 fpu_type
= MIPS_FPU_DOUBLE
;
8190 fpu_type
= MIPS_FPU_SINGLE
;
8194 /* Soft float or unknown. */
8195 fpu_type
= MIPS_FPU_NONE
;
8199 else if (info
.bfd_arch_info
!= NULL
8200 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8201 switch (info
.bfd_arch_info
->mach
)
8203 case bfd_mach_mips3900
:
8204 case bfd_mach_mips4100
:
8205 case bfd_mach_mips4111
:
8206 case bfd_mach_mips4120
:
8207 fpu_type
= MIPS_FPU_NONE
;
8209 case bfd_mach_mips4650
:
8210 fpu_type
= MIPS_FPU_SINGLE
;
8213 fpu_type
= MIPS_FPU_DOUBLE
;
8216 else if (arches
!= NULL
)
8217 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
8219 fpu_type
= MIPS_FPU_DOUBLE
;
8221 fprintf_unfiltered (gdb_stdlog
,
8222 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8224 /* Check for blatant incompatibilities. */
8226 /* If we have only 32-bit registers, then we can't debug a 64-bit
8228 if (info
.target_desc
8229 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8230 && mips_abi
!= MIPS_ABI_EABI32
8231 && mips_abi
!= MIPS_ABI_O32
)
8233 if (tdesc_data
!= NULL
)
8234 tdesc_data_cleanup (tdesc_data
);
8238 /* Try to find a pre-existing architecture. */
8239 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8241 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8243 /* MIPS needs to be pedantic about which ABI the object is
8245 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8247 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8249 /* Need to be pedantic about which register virtual size is
8251 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8252 != mips64_transfers_32bit_regs_p
)
8254 /* Be pedantic about which FPU is selected. */
8255 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
8258 if (tdesc_data
!= NULL
)
8259 tdesc_data_cleanup (tdesc_data
);
8260 return arches
->gdbarch
;
8263 /* Need a new architecture. Fill in a target specific vector. */
8264 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
8265 gdbarch
= gdbarch_alloc (&info
, tdep
);
8266 tdep
->elf_flags
= elf_flags
;
8267 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8268 tdep
->found_abi
= found_abi
;
8269 tdep
->mips_abi
= mips_abi
;
8270 tdep
->mips_isa
= mips_isa
;
8271 tdep
->mips_fpu_type
= fpu_type
;
8272 tdep
->register_size_valid_p
= 0;
8273 tdep
->register_size
= 0;
8274 tdep
->gregset
= NULL
;
8275 tdep
->gregset64
= NULL
;
8276 tdep
->fpregset
= NULL
;
8277 tdep
->fpregset64
= NULL
;
8279 if (info
.target_desc
)
8281 /* Some useful properties can be inferred from the target. */
8282 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8284 tdep
->register_size_valid_p
= 1;
8285 tdep
->register_size
= 4;
8287 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8289 tdep
->register_size_valid_p
= 1;
8290 tdep
->register_size
= 8;
8294 /* Initially set everything according to the default ABI/ISA. */
8295 set_gdbarch_short_bit (gdbarch
, 16);
8296 set_gdbarch_int_bit (gdbarch
, 32);
8297 set_gdbarch_float_bit (gdbarch
, 32);
8298 set_gdbarch_double_bit (gdbarch
, 64);
8299 set_gdbarch_long_double_bit (gdbarch
, 64);
8300 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8301 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8302 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8304 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8305 mips_ax_pseudo_register_collect
);
8306 set_gdbarch_ax_pseudo_register_push_stack
8307 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8309 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8310 mips_elf_make_msymbol_special
);
8312 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8313 *regnum
= mips_regnum
;
8314 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8315 set_gdbarch_num_regs (gdbarch
, num_regs
);
8316 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8317 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8318 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8319 tdep
->mips_processor_reg_names
= reg_names
;
8320 tdep
->regnum
= regnum
;
8325 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8326 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8327 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8328 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8329 tdep
->default_mask_address_p
= 0;
8330 set_gdbarch_long_bit (gdbarch
, 32);
8331 set_gdbarch_ptr_bit (gdbarch
, 32);
8332 set_gdbarch_long_long_bit (gdbarch
, 64);
8335 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8336 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8337 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8338 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8339 tdep
->default_mask_address_p
= 0;
8340 set_gdbarch_long_bit (gdbarch
, 32);
8341 set_gdbarch_ptr_bit (gdbarch
, 32);
8342 set_gdbarch_long_long_bit (gdbarch
, 64);
8344 case MIPS_ABI_EABI32
:
8345 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8346 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8347 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8348 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8349 tdep
->default_mask_address_p
= 0;
8350 set_gdbarch_long_bit (gdbarch
, 32);
8351 set_gdbarch_ptr_bit (gdbarch
, 32);
8352 set_gdbarch_long_long_bit (gdbarch
, 64);
8354 case MIPS_ABI_EABI64
:
8355 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8356 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8357 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8358 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8359 tdep
->default_mask_address_p
= 0;
8360 set_gdbarch_long_bit (gdbarch
, 64);
8361 set_gdbarch_ptr_bit (gdbarch
, 64);
8362 set_gdbarch_long_long_bit (gdbarch
, 64);
8365 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8366 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8367 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8368 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8369 tdep
->default_mask_address_p
= 0;
8370 set_gdbarch_long_bit (gdbarch
, 32);
8371 set_gdbarch_ptr_bit (gdbarch
, 32);
8372 set_gdbarch_long_long_bit (gdbarch
, 64);
8373 set_gdbarch_long_double_bit (gdbarch
, 128);
8374 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8377 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8378 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8379 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8380 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8381 tdep
->default_mask_address_p
= 0;
8382 set_gdbarch_long_bit (gdbarch
, 64);
8383 set_gdbarch_ptr_bit (gdbarch
, 64);
8384 set_gdbarch_long_long_bit (gdbarch
, 64);
8385 set_gdbarch_long_double_bit (gdbarch
, 128);
8386 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8389 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8392 /* GCC creates a pseudo-section whose name specifies the size of
8393 longs, since -mlong32 or -mlong64 may be used independent of
8394 other options. How those options affect pointer sizes is ABI and
8395 architecture dependent, so use them to override the default sizes
8396 set by the ABI. This table shows the relationship between ABI,
8397 -mlongXX, and size of pointers:
8399 ABI -mlongXX ptr bits
8400 --- -------- --------
8414 Note that for o32 and eabi32, pointers are always 32 bits
8415 regardless of any -mlongXX option. For all others, pointers and
8416 longs are the same, as set by -mlongXX or set by defaults. */
8418 if (info
.abfd
!= NULL
)
8422 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8425 set_gdbarch_long_bit (gdbarch
, long_bit
);
8429 case MIPS_ABI_EABI32
:
8434 case MIPS_ABI_EABI64
:
8435 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8438 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8443 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8444 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8447 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8448 flag in object files because to do so would make it impossible to
8449 link with libraries compiled without "-gp32". This is
8450 unnecessarily restrictive.
8452 We could solve this problem by adding "-gp32" multilibs to gcc,
8453 but to set this flag before gcc is built with such multilibs will
8454 break too many systems.''
8456 But even more unhelpfully, the default linker output target for
8457 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8458 for 64-bit programs - you need to change the ABI to change this,
8459 and not all gcc targets support that currently. Therefore using
8460 this flag to detect 32-bit mode would do the wrong thing given
8461 the current gcc - it would make GDB treat these 64-bit programs
8462 as 32-bit programs by default. */
8464 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8465 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8467 /* Add/remove bits from an address. The MIPS needs be careful to
8468 ensure that all 32 bit addresses are sign extended to 64 bits. */
8469 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8471 /* Unwind the frame. */
8472 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8473 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8474 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8476 /* Map debug register numbers onto internal register numbers. */
8477 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8478 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8479 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8480 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8481 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8482 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8484 /* MIPS version of CALL_DUMMY. */
8486 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8487 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8488 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8490 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8491 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8492 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8494 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8495 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
8496 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
8497 mips_remote_breakpoint_from_pc
);
8498 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8499 mips_adjust_breakpoint_address
);
8501 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8503 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
8505 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8506 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8507 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8509 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8511 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8513 if (mips_abi
== MIPS_ABI_N32
)
8514 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8515 else if (mips_abi
== MIPS_ABI_N64
)
8516 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8518 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8520 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8521 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8522 need to all be folded into the target vector. Since they are
8523 being used as guards for target_stopped_by_watchpoint, why not have
8524 target_stopped_by_watchpoint return the type of watchpoint that the code
8526 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8528 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8530 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8531 to support MIPS16. This is a bad thing. Make sure not to do it
8532 if we have an OS ABI that actually supports shared libraries, since
8533 shared library support is more important. If we have an OS someday
8534 that supports both shared libraries and MIPS16, we'll have to find
8535 a better place for these.
8536 macro/2012-04-25: But that applies to return trampolines only and
8537 currently no MIPS OS ABI uses shared libraries that have them. */
8538 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8540 set_gdbarch_single_step_through_delay (gdbarch
,
8541 mips_single_step_through_delay
);
8543 /* Virtual tables. */
8544 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8546 mips_register_g_packet_guesses (gdbarch
);
8548 /* Hook in OS ABI-specific overrides, if they have been registered. */
8549 info
.tdep_info
= (void *) tdesc_data
;
8550 gdbarch_init_osabi (info
, gdbarch
);
8552 /* The hook may have adjusted num_regs, fetch the final value and
8553 set pc_regnum and sp_regnum now that it has been fixed. */
8554 num_regs
= gdbarch_num_regs (gdbarch
);
8555 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8556 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8558 /* Unwind the frame. */
8559 dwarf2_append_unwinders (gdbarch
);
8560 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8561 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8562 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8563 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8564 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8565 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8566 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8567 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8568 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8572 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8573 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8575 /* Override the normal target description methods to handle our
8576 dual real and pseudo registers. */
8577 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8578 set_gdbarch_register_reggroup_p (gdbarch
,
8579 mips_tdesc_register_reggroup_p
);
8581 num_regs
= gdbarch_num_regs (gdbarch
);
8582 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8583 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8584 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8587 /* Add ABI-specific aliases for the registers. */
8588 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8589 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8590 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8591 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8593 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8594 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8595 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8597 /* Add some other standard aliases. */
8598 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8599 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8600 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8602 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8603 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8604 value_of_mips_user_reg
,
8605 &mips_numeric_register_aliases
[i
].regnum
);
8611 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
8613 struct gdbarch_info info
;
8615 /* Force the architecture to update, and (if it's a MIPS architecture)
8616 mips_gdbarch_init will take care of the rest. */
8617 gdbarch_info_init (&info
);
8618 gdbarch_update_p (info
);
8621 /* Print out which MIPS ABI is in use. */
8624 show_mips_abi (struct ui_file
*file
,
8626 struct cmd_list_element
*ignored_cmd
,
8627 const char *ignored_value
)
8629 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
8632 "The MIPS ABI is unknown because the current architecture "
8636 enum mips_abi global_abi
= global_mips_abi ();
8637 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
8638 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8640 if (global_abi
== MIPS_ABI_UNKNOWN
)
8643 "The MIPS ABI is set automatically (currently \"%s\").\n",
8645 else if (global_abi
== actual_abi
)
8648 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8652 /* Probably shouldn't happen... */
8653 fprintf_filtered (file
,
8654 "The (auto detected) MIPS ABI \"%s\" is in use "
8655 "even though the user setting was \"%s\".\n",
8656 actual_abi_str
, mips_abi_strings
[global_abi
]);
8661 /* Print out which MIPS compressed ISA encoding is used. */
8664 show_mips_compression (struct ui_file
*file
, int from_tty
,
8665 struct cmd_list_element
*c
, const char *value
)
8667 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8672 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8674 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8678 int ef_mips_32bitmode
;
8679 /* Determine the ISA. */
8680 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8698 /* Determine the size of a pointer. */
8699 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8700 fprintf_unfiltered (file
,
8701 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8703 fprintf_unfiltered (file
,
8704 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8706 fprintf_unfiltered (file
,
8707 "mips_dump_tdep: ef_mips_arch = %d\n",
8709 fprintf_unfiltered (file
,
8710 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8711 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8712 fprintf_unfiltered (file
,
8714 "mips_mask_address_p() %d (default %d)\n",
8715 mips_mask_address_p (tdep
),
8716 tdep
->default_mask_address_p
);
8718 fprintf_unfiltered (file
,
8719 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8720 MIPS_DEFAULT_FPU_TYPE
,
8721 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
8722 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
8723 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
8725 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8726 MIPS_EABI (gdbarch
));
8727 fprintf_unfiltered (file
,
8728 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8729 MIPS_FPU_TYPE (gdbarch
),
8730 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
8731 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
8732 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
8736 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
8739 _initialize_mips_tdep (void)
8741 static struct cmd_list_element
*mipsfpulist
= NULL
;
8742 struct cmd_list_element
*c
;
8744 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8745 if (MIPS_ABI_LAST
+ 1
8746 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8747 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8749 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8751 mips_pdr_data
= register_objfile_data ();
8753 /* Create feature sets with the appropriate properties. The values
8754 are not important. */
8755 mips_tdesc_gp32
= allocate_target_description ();
8756 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8758 mips_tdesc_gp64
= allocate_target_description ();
8759 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8761 /* Add root prefix command for all "set mips"/"show mips" commands. */
8762 add_prefix_cmd ("mips", no_class
, set_mips_command
,
8763 _("Various MIPS specific commands."),
8764 &setmipscmdlist
, "set mips ", 0, &setlist
);
8766 add_prefix_cmd ("mips", no_class
, show_mips_command
,
8767 _("Various MIPS specific commands."),
8768 &showmipscmdlist
, "show mips ", 0, &showlist
);
8770 /* Allow the user to override the ABI. */
8771 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
8772 &mips_abi_string
, _("\
8773 Set the MIPS ABI used by this program."), _("\
8774 Show the MIPS ABI used by this program."), _("\
8775 This option can be set to one of:\n\
8776 auto - the default ABI associated with the current binary\n\
8785 &setmipscmdlist
, &showmipscmdlist
);
8787 /* Allow the user to set the ISA to assume for compressed code if ELF
8788 file flags don't tell or there is no program file selected. This
8789 setting is updated whenever unambiguous ELF file flags are interpreted,
8790 and carried over to subsequent sessions. */
8791 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
8792 &mips_compression_string
, _("\
8793 Set the compressed ISA encoding used by MIPS code."), _("\
8794 Show the compressed ISA encoding used by MIPS code."), _("\
8795 Select the compressed ISA encoding used in functions that have no symbol\n\
8796 information available. The encoding can be set to either of:\n\
8799 and is updated automatically from ELF file flags if available."),
8801 show_mips_compression
,
8802 &setmipscmdlist
, &showmipscmdlist
);
8804 /* Let the user turn off floating point and set the fence post for
8805 heuristic_proc_start. */
8807 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
8808 _("Set use of MIPS floating-point coprocessor."),
8809 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
8810 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
8811 _("Select single-precision MIPS floating-point coprocessor."),
8813 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
8814 _("Select double-precision MIPS floating-point coprocessor."),
8816 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
8817 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
8818 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
8819 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
8820 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
8821 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
8822 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
8823 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
8824 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
8825 _("Select MIPS floating-point coprocessor automatically."),
8827 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
8828 _("Show current use of MIPS floating-point coprocessor target."),
8831 /* We really would like to have both "0" and "unlimited" work, but
8832 command.c doesn't deal with that. So make it a var_zinteger
8833 because the user can always use "999999" or some such for unlimited. */
8834 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
8835 &heuristic_fence_post
, _("\
8836 Set the distance searched for the start of a function."), _("\
8837 Show the distance searched for the start of a function."), _("\
8838 If you are debugging a stripped executable, GDB needs to search through the\n\
8839 program for the start of a function. This command sets the distance of the\n\
8840 search. The only need to set it is when debugging a stripped executable."),
8841 reinit_frame_cache_sfunc
,
8842 NULL
, /* FIXME: i18n: The distance searched for
8843 the start of a function is %s. */
8844 &setlist
, &showlist
);
8846 /* Allow the user to control whether the upper bits of 64-bit
8847 addresses should be zeroed. */
8848 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
8849 &mask_address_var
, _("\
8850 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
8851 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
8852 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
8853 allow GDB to determine the correct value."),
8854 NULL
, show_mask_address
,
8855 &setmipscmdlist
, &showmipscmdlist
);
8857 /* Allow the user to control the size of 32 bit registers within the
8858 raw remote packet. */
8859 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
8860 &mips64_transfers_32bit_regs_p
, _("\
8861 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
8863 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
8865 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
8866 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
8867 64 bits for others. Use \"off\" to disable compatibility mode"),
8868 set_mips64_transfers_32bit_regs
,
8869 NULL
, /* FIXME: i18n: Compatibility with 64-bit
8870 MIPS target that transfers 32-bit
8871 quantities is %s. */
8872 &setlist
, &showlist
);
8874 /* Debug this files internals. */
8875 add_setshow_zinteger_cmd ("mips", class_maintenance
,
8877 Set mips debugging."), _("\
8878 Show mips debugging."), _("\
8879 When non-zero, mips specific debugging is enabled."),
8881 NULL
, /* FIXME: i18n: Mips debugging is
8883 &setdebuglist
, &showdebuglist
);