1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
41 #include "opcode/mips.h"
46 /* The sizes of floating point registers. */
50 MIPS_FPU_SINGLE_REGSIZE
= 4,
51 MIPS_FPU_DOUBLE_REGSIZE
= 8
54 /* All the possible MIPS ABIs. */
66 struct frame_extra_info
68 mips_extra_func_info_t proc_desc
;
72 /* Various MIPS ISA options (related to stack analysis) can be
73 overridden dynamically. Establish an enum/array for managing
76 static const char size_auto
[] = "auto";
77 static const char size_32
[] = "32";
78 static const char size_64
[] = "64";
80 static const char *size_enums
[] = {
87 /* Some MIPS boards don't support floating point while others only
88 support single-precision floating-point operations. See also
89 FP_REGISTER_DOUBLE. */
93 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
94 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
95 MIPS_FPU_NONE
/* No floating point. */
98 #ifndef MIPS_DEFAULT_FPU_TYPE
99 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
101 static int mips_fpu_type_auto
= 1;
102 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
103 #define MIPS_FPU_TYPE mips_fpu_type
105 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
106 #ifndef FP_REGISTER_DOUBLE
107 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
110 static int mips_debug
= 0;
112 /* MIPS specific per-architecture information */
115 /* from the elf header */
118 enum mips_abi mips_abi
;
119 enum mips_fpu_type mips_fpu_type
;
120 int mips_last_arg_regnum
;
121 int mips_last_fp_arg_regnum
;
122 int mips_default_saved_regsize
;
123 int mips_fp_register_double
;
124 int mips_regs_have_home_p
;
125 int mips_default_stack_argsize
;
126 int gdb_target_is_mips64
;
127 int default_mask_address_p
;
132 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
133 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
137 #undef MIPS_LAST_FP_ARG_REGNUM
138 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
142 #undef MIPS_LAST_ARG_REGNUM
143 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
148 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
151 /* Return the currently configured (or set) saved register size. */
154 #undef MIPS_DEFAULT_SAVED_REGSIZE
155 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
156 #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE)
157 #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
160 static const char *mips_saved_regsize_string
= size_auto
;
162 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
165 mips_saved_regsize ()
167 if (mips_saved_regsize_string
== size_auto
)
168 return MIPS_DEFAULT_SAVED_REGSIZE
;
169 else if (mips_saved_regsize_string
== size_64
)
171 else /* if (mips_saved_regsize_string == size_32) */
175 /* Indicate that the ABI makes use of double-precision registers
176 provided by the FPU (rather than combining pairs of registers to
177 form double-precision values). Do not use "TARGET_IS_MIPS64" to
178 determine if the ABI is using double-precision registers. See also
181 #undef FP_REGISTER_DOUBLE
182 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
185 /* Does the caller allocate a ``home'' for each register used in the
186 function call? The N32 ABI and MIPS_EABI do not, the others do. */
189 #undef MIPS_REGS_HAVE_HOME_P
190 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
191 #elif !defined (MIPS_REGS_HAVE_HOME_P)
192 #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI)
195 /* The amount of space reserved on the stack for registers. This is
196 different to MIPS_SAVED_REGSIZE as it determines the alignment of
197 data allocated after the registers have run out. */
200 #undef MIPS_DEFAULT_STACK_ARGSIZE
201 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
202 #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE)
203 #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE)
206 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
208 static const char *mips_stack_argsize_string
= size_auto
;
211 mips_stack_argsize (void)
213 if (mips_stack_argsize_string
== size_auto
)
214 return MIPS_DEFAULT_STACK_ARGSIZE
;
215 else if (mips_stack_argsize_string
== size_64
)
217 else /* if (mips_stack_argsize_string == size_32) */
222 #undef GDB_TARGET_IS_MIPS64
223 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
226 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
229 static int mips_in_lenient_prologue (CORE_ADDR
, CORE_ADDR
);
232 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
234 static void mips_print_register (int, int);
236 static mips_extra_func_info_t
237 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*);
239 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
241 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
243 int mips_set_processor_type (char *);
245 static void mips_show_processor_type_command (char *, int);
247 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
249 static mips_extra_func_info_t
250 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
);
252 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
253 mips_extra_func_info_t proc_desc
);
255 /* This value is the model of MIPS in use. It is derived from the value
256 of the PrID register. */
258 char *mips_processor_type
;
260 char *tmp_mips_processor_type
;
262 /* A set of original names, to be used when restoring back to generic
263 registers from a specific set. */
265 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
266 char **mips_processor_reg_names
= mips_generic_reg_names
;
268 /* The list of available "set mips " and "show mips " commands */
269 static struct cmd_list_element
*setmipscmdlist
= NULL
;
270 static struct cmd_list_element
*showmipscmdlist
= NULL
;
273 mips_register_name (i
)
276 return mips_processor_reg_names
[i
];
279 /* Names of IDT R3041 registers. */
281 char *mips_r3041_reg_names
[] = {
282 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
283 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
284 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
285 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
286 "sr", "lo", "hi", "bad", "cause","pc",
287 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
288 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
289 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
290 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
291 "fsr", "fir", "fp", "",
292 "", "", "bus", "ccfg", "", "", "", "",
293 "", "", "port", "cmp", "", "", "epc", "prid",
296 /* Names of IDT R3051 registers. */
298 char *mips_r3051_reg_names
[] = {
299 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
300 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
301 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
302 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
303 "sr", "lo", "hi", "bad", "cause","pc",
304 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
305 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
306 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
307 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
308 "fsr", "fir", "fp", "",
309 "inx", "rand", "elo", "", "ctxt", "", "", "",
310 "", "", "ehi", "", "", "", "epc", "prid",
313 /* Names of IDT R3081 registers. */
315 char *mips_r3081_reg_names
[] = {
316 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
317 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
318 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
319 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
320 "sr", "lo", "hi", "bad", "cause","pc",
321 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
322 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
323 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
324 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
325 "fsr", "fir", "fp", "",
326 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
327 "", "", "ehi", "", "", "", "epc", "prid",
330 /* Names of LSI 33k registers. */
332 char *mips_lsi33k_reg_names
[] = {
333 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
334 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
335 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
336 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
337 "epc", "hi", "lo", "sr", "cause","badvaddr",
338 "dcic", "bpc", "bda", "", "", "", "", "",
339 "", "", "", "", "", "", "", "",
340 "", "", "", "", "", "", "", "",
341 "", "", "", "", "", "", "", "",
343 "", "", "", "", "", "", "", "",
344 "", "", "", "", "", "", "", "",
350 } mips_processor_type_table
[] = {
351 { "generic", mips_generic_reg_names
},
352 { "r3041", mips_r3041_reg_names
},
353 { "r3051", mips_r3051_reg_names
},
354 { "r3071", mips_r3081_reg_names
},
355 { "r3081", mips_r3081_reg_names
},
356 { "lsi33k", mips_lsi33k_reg_names
},
364 /* Table to translate MIPS16 register field to actual register number. */
365 static int mips16_to_32_reg
[8] =
366 {16, 17, 2, 3, 4, 5, 6, 7};
368 /* Heuristic_proc_start may hunt through the text section for a long
369 time across a 2400 baud serial line. Allows the user to limit this
372 static unsigned int heuristic_fence_post
= 0;
374 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
375 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
376 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
377 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
378 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
379 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
380 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
381 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
382 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
383 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
384 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
385 #define _PROC_MAGIC_ 0x0F0F0F0F
386 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
387 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
389 struct linked_proc_info
391 struct mips_extra_func_info info
;
392 struct linked_proc_info
*next
;
394 *linked_proc_desc_table
= NULL
;
397 mips_print_extra_frame_info (fi
)
398 struct frame_info
*fi
;
402 && fi
->extra_info
->proc_desc
403 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
404 printf_filtered (" frame pointer is at %s+%s\n",
405 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
406 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
409 /* Convert between RAW and VIRTUAL registers. The RAW register size
410 defines the remote-gdb packet. */
412 static int mips64_transfers_32bit_regs_p
= 0;
415 mips_register_raw_size (reg_nr
)
418 if (mips64_transfers_32bit_regs_p
)
419 return REGISTER_VIRTUAL_SIZE (reg_nr
);
425 mips_register_convertible (reg_nr
)
428 if (mips64_transfers_32bit_regs_p
)
431 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
435 mips_register_convert_to_virtual (n
, virtual_type
, raw_buf
, virt_buf
)
437 struct type
*virtual_type
;
441 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
443 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
444 TYPE_LENGTH (virtual_type
));
448 TYPE_LENGTH (virtual_type
));
452 mips_register_convert_to_raw (virtual_type
, n
, virt_buf
, raw_buf
)
453 struct type
*virtual_type
;
458 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
459 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
460 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
462 TYPE_LENGTH (virtual_type
));
466 TYPE_LENGTH (virtual_type
));
469 /* Should the upper word of 64-bit addresses be zeroed? */
470 enum cmd_auto_boolean mask_address_var
= CMD_AUTO_BOOLEAN_AUTO
;
473 mips_mask_address_p (void)
475 switch (mask_address_var
)
477 case CMD_AUTO_BOOLEAN_TRUE
:
479 case CMD_AUTO_BOOLEAN_FALSE
:
482 case CMD_AUTO_BOOLEAN_AUTO
:
483 return gdbarch_tdep (current_gdbarch
)->default_mask_address_p
;
485 internal_error ("mips_mask_address_p: bad switch");
491 show_mask_address (char *cmd
, int from_tty
)
493 switch (mask_address_var
)
495 case CMD_AUTO_BOOLEAN_TRUE
:
496 printf_filtered ("The 32 bit mips address mask is enabled\n");
498 case CMD_AUTO_BOOLEAN_FALSE
:
499 printf_filtered ("The 32 bit mips address mask is disabled\n");
501 case CMD_AUTO_BOOLEAN_AUTO
:
502 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
503 mips_mask_address_p () ? "enabled" : "disabled");
506 internal_error ("show_mask_address: bad switch");
511 /* Should call_function allocate stack space for a struct return? */
513 mips_use_struct_convention (gcc_p
, type
)
518 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
520 return 1; /* Structures are returned by ref in extra arg0 */
523 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
526 pc_is_mips16 (bfd_vma memaddr
)
528 struct minimal_symbol
*sym
;
530 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
531 if (IS_MIPS16_ADDR (memaddr
))
534 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
535 the high bit of the info field. Use this to decide if the function is
536 MIPS16 or normal MIPS. */
537 sym
= lookup_minimal_symbol_by_pc (memaddr
);
539 return MSYMBOL_IS_SPECIAL (sym
);
545 /* This returns the PC of the first inst after the prologue. If we can't
546 find the prologue, then return 0. */
549 after_prologue (pc
, proc_desc
)
551 mips_extra_func_info_t proc_desc
;
553 struct symtab_and_line sal
;
554 CORE_ADDR func_addr
, func_end
;
557 proc_desc
= find_proc_desc (pc
, NULL
);
561 /* If function is frameless, then we need to do it the hard way. I
562 strongly suspect that frameless always means prologueless... */
563 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
564 && PROC_FRAME_OFFSET (proc_desc
) == 0)
568 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
569 return 0; /* Unknown */
571 sal
= find_pc_line (func_addr
, 0);
573 if (sal
.end
< func_end
)
576 /* The line after the prologue is after the end of the function. In this
577 case, tell the caller to find the prologue the hard way. */
582 /* Decode a MIPS32 instruction that saves a register in the stack, and
583 set the appropriate bit in the general register mask or float register mask
584 to indicate which register is saved. This is a helper function
585 for mips_find_saved_regs. */
588 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
590 unsigned long *gen_mask
;
591 unsigned long *float_mask
;
595 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
596 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
597 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
599 /* It might be possible to use the instruction to
600 find the offset, rather than the code below which
601 is based on things being in a certain order in the
602 frame, but figuring out what the instruction's offset
603 is relative to might be a little tricky. */
604 reg
= (inst
& 0x001f0000) >> 16;
605 *gen_mask
|= (1 << reg
);
607 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
608 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
609 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
612 reg
= ((inst
& 0x001f0000) >> 16);
613 *float_mask
|= (1 << reg
);
617 /* Decode a MIPS16 instruction that saves a register in the stack, and
618 set the appropriate bit in the general register or float register mask
619 to indicate which register is saved. This is a helper function
620 for mips_find_saved_regs. */
623 mips16_decode_reg_save (inst
, gen_mask
)
625 unsigned long *gen_mask
;
627 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
629 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
630 *gen_mask
|= (1 << reg
);
632 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
634 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
635 *gen_mask
|= (1 << reg
);
637 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
638 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
639 *gen_mask
|= (1 << RA_REGNUM
);
643 /* Fetch and return instruction from the specified location. If the PC
644 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
647 mips_fetch_instruction (addr
)
650 char buf
[MIPS_INSTLEN
];
654 if (pc_is_mips16 (addr
))
656 instlen
= MIPS16_INSTLEN
;
657 addr
= UNMAKE_MIPS16_ADDR (addr
);
660 instlen
= MIPS_INSTLEN
;
661 status
= read_memory_nobpt (addr
, buf
, instlen
);
663 memory_error (status
, addr
);
664 return extract_unsigned_integer (buf
, instlen
);
668 /* These the fields of 32 bit mips instructions */
669 #define mips32_op(x) (x >> 25)
670 #define itype_op(x) (x >> 25)
671 #define itype_rs(x) ((x >> 21)& 0x1f)
672 #define itype_rt(x) ((x >> 16) & 0x1f)
673 #define itype_immediate(x) ( x & 0xffff)
675 #define jtype_op(x) (x >> 25)
676 #define jtype_target(x) ( x & 0x03fffff)
678 #define rtype_op(x) (x >>25)
679 #define rtype_rs(x) ((x>>21) & 0x1f)
680 #define rtype_rt(x) ((x>>16) & 0x1f)
681 #define rtype_rd(x) ((x>>11) & 0x1f)
682 #define rtype_shamt(x) ((x>>6) & 0x1f)
683 #define rtype_funct(x) (x & 0x3f )
686 mips32_relative_offset (unsigned long inst
)
689 x
= itype_immediate (inst
);
690 if (x
& 0x8000) /* sign bit set */
692 x
|= 0xffff0000; /* sign extension */
698 /* Determine whate to set a single step breakpoint while considering
701 mips32_next_pc (CORE_ADDR pc
)
705 inst
= mips_fetch_instruction (pc
);
706 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
708 if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
710 op
= ((inst
>> 25) & 0x03);
714 goto equal_branch
; /* BEQL */
716 goto neq_branch
; /* BNEZ */
718 goto less_branch
; /* BLEZ */
720 goto greater_branch
; /* BGTZ */
726 pc
+= 4; /* Not a branch, next instruction is easy */
729 { /* This gets way messy */
731 /* Further subdivide into SPECIAL, REGIMM and other */
732 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
734 case 0: /* SPECIAL */
735 op
= rtype_funct (inst
);
740 pc
= read_register (rtype_rs (inst
)); /* Set PC to that address */
746 break; /* end special */
749 op
= jtype_op (inst
); /* branch condition */
750 switch (jtype_op (inst
))
754 case 16: /* BLTZALL */
755 case 18: /* BLTZALL */
757 if (read_register (itype_rs (inst
)) < 0)
758 pc
+= mips32_relative_offset (inst
) + 4;
760 pc
+= 8; /* after the delay slot */
764 case 17: /* BGEZAL */
765 case 19: /* BGEZALL */
766 greater_equal_branch
:
767 if (read_register (itype_rs (inst
)) >= 0)
768 pc
+= mips32_relative_offset (inst
) + 4;
770 pc
+= 8; /* after the delay slot */
772 /* All of the other intructions in the REGIMM catagory */
777 break; /* end REGIMM */
782 reg
= jtype_target (inst
) << 2;
783 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
784 /* Whats this mysterious 0xf000000 adjustment ??? */
787 /* FIXME case JALX : */
790 reg
= jtype_target (inst
) << 2;
791 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
792 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
794 break; /* The new PC will be alternate mode */
795 case 4: /* BEQ , BEQL */
797 if (read_register (itype_rs (inst
)) ==
798 read_register (itype_rt (inst
)))
799 pc
+= mips32_relative_offset (inst
) + 4;
803 case 5: /* BNE , BNEL */
805 if (read_register (itype_rs (inst
)) !=
806 read_register (itype_rs (inst
)))
807 pc
+= mips32_relative_offset (inst
) + 4;
811 case 6: /* BLEZ , BLEZL */
813 if (read_register (itype_rs (inst
) <= 0))
814 pc
+= mips32_relative_offset (inst
) + 4;
819 greater_branch
: /* BGTZ BGTZL */
820 if (read_register (itype_rs (inst
) > 0))
821 pc
+= mips32_relative_offset (inst
) + 4;
830 } /* mips32_next_pc */
832 /* Decoding the next place to set a breakpoint is irregular for the
833 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
834 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
835 We dont want to set a single step instruction on the extend instruction
839 /* Lots of mips16 instruction formats */
840 /* Predicting jumps requires itype,ritype,i8type
841 and their extensions extItype,extritype,extI8type
843 enum mips16_inst_fmts
845 itype
, /* 0 immediate 5,10 */
846 ritype
, /* 1 5,3,8 */
847 rrtype
, /* 2 5,3,3,5 */
848 rritype
, /* 3 5,3,3,5 */
849 rrrtype
, /* 4 5,3,3,3,2 */
850 rriatype
, /* 5 5,3,3,1,4 */
851 shifttype
, /* 6 5,3,3,3,2 */
852 i8type
, /* 7 5,3,8 */
853 i8movtype
, /* 8 5,3,3,5 */
854 i8mov32rtype
, /* 9 5,3,5,3 */
855 i64type
, /* 10 5,3,8 */
856 ri64type
, /* 11 5,3,3,5 */
857 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
858 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
859 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
860 extRRItype
, /* 15 5,5,5,5,3,3,5 */
861 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
862 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
863 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
864 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
865 extRi64type
, /* 20 5,6,5,5,3,3,5 */
866 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
868 /* I am heaping all the fields of the formats into one structure and then,
869 only the fields which are involved in instruction extension */
873 enum mips16_inst_fmts fmt
;
874 unsigned long offset
;
875 unsigned int regx
; /* Function in i8 type */
882 print_unpack (char *comment
,
883 struct upk_mips16
*u
)
885 printf ("%s %04x ,f(%d) off(%s) (x(%x) y(%x)\n",
886 comment
, u
->inst
, u
->fmt
, paddr (u
->offset
), u
->regx
, u
->regy
);
889 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
890 format for the bits which make up the immediatate extension.
893 extended_offset (unsigned long extension
)
896 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
898 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
900 value
|= extension
& 0x01f; /* extract 4:0 */
904 /* Only call this function if you know that this is an extendable
905 instruction, It wont malfunction, but why make excess remote memory references?
906 If the immediate operands get sign extended or somthing, do it after
907 the extension is performed.
909 /* FIXME: Every one of these cases needs to worry about sign extension
910 when the offset is to be used in relative addressing */
913 static unsigned short
914 fetch_mips_16 (CORE_ADDR pc
)
917 pc
&= 0xfffffffe; /* clear the low order bit */
918 target_read_memory (pc
, buf
, 2);
919 return extract_unsigned_integer (buf
, 2);
923 unpack_mips16 (CORE_ADDR pc
,
924 struct upk_mips16
*upk
)
927 unsigned long extension
;
929 extpc
= (pc
- 4) & ~0x01; /* Extensions are 32 bit instructions */
930 /* Decrement to previous address and loose the 16bit mode flag */
931 /* return if the instruction was extendable, but not actually extended */
932 extended
= ((mips32_op (extension
) == 30) ? 1 : 0);
935 extension
= mips_fetch_instruction (extpc
);
944 value
= extended_offset (extension
);
945 value
= value
<< 11; /* rom for the original value */
946 value
|= upk
->inst
& 0x7ff; /* eleven bits from instruction */
950 value
= upk
->inst
& 0x7ff;
951 /* FIXME : Consider sign extension */
958 { /* A register identifier and an offset */
959 /* Most of the fields are the same as I type but the
960 immediate value is of a different length */
964 value
= extended_offset (extension
);
965 value
= value
<< 8; /* from the original instruction */
966 value
|= upk
->inst
& 0xff; /* eleven bits from instruction */
967 upk
->regx
= (extension
>> 8) & 0x07; /* or i8 funct */
968 if (value
& 0x4000) /* test the sign bit , bit 26 */
970 value
&= ~0x3fff; /* remove the sign bit */
976 value
= upk
->inst
& 0xff; /* 8 bits */
977 upk
->regx
= (upk
->inst
>> 8) & 0x07; /* or i8 funct */
978 /* FIXME: Do sign extension , this format needs it */
979 if (value
& 0x80) /* THIS CONFUSES ME */
981 value
&= 0xef; /* remove the sign bit */
992 unsigned short nexthalf
;
993 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f);
995 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1001 printf_filtered ("Decoding unimplemented instruction format type\n");
1004 /* print_unpack("UPK",upk) ; */
1008 #define mips16_op(x) (x >> 11)
1010 /* This is a map of the opcodes which ae known to perform branches */
1011 static unsigned char map16
[32] =
1012 {0, 0, 1, 1, 1, 1, 0, 0,
1013 0, 0, 0, 0, 1, 0, 0, 0,
1014 0, 0, 0, 0, 0, 0, 0, 0,
1015 0, 0, 0, 0, 0, 1, 1, 0
1019 add_offset_16 (CORE_ADDR pc
, int offset
)
1021 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1027 static struct upk_mips16 upk
;
1030 mips16_next_pc (CORE_ADDR pc
)
1034 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
1035 inst
= fetch_mips_16 (pc
);
1037 op
= mips16_op (upk
.inst
);
1043 case 2: /* Branch */
1045 unpack_mips16 (pc
, &upk
);
1048 offset
= upk
.offset
;
1054 pc
+= (offset
<< 1) + 2;
1057 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1059 unpack_mips16 (pc
, &upk
);
1060 pc
= add_offset_16 (pc
, upk
.offset
);
1061 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
1062 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1068 unpack_mips16 (pc
, &upk
);
1069 reg
= read_register (upk
.regx
);
1071 pc
+= (upk
.offset
<< 1) + 2;
1077 unpack_mips16 (pc
, &upk
);
1078 reg
= read_register (upk
.regx
);
1080 pc
+= (upk
.offset
<< 1) + 2;
1084 case 12: /* I8 Formats btez btnez */
1086 unpack_mips16 (pc
, &upk
);
1087 /* upk.regx contains the opcode */
1088 reg
= read_register (24); /* Test register is 24 */
1089 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1090 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1091 /* pc = add_offset_16(pc,upk.offset) ; */
1092 pc
+= (upk
.offset
<< 1) + 2;
1096 case 29: /* RR Formats JR, JALR, JALR-RA */
1098 op
= upk
.inst
& 0x1f;
1101 upk
.regx
= (upk
.inst
>> 8) & 0x07;
1102 upk
.regy
= (upk
.inst
>> 5) & 0x07;
1110 break; /* Function return instruction */
1116 break; /* BOGUS Guess */
1118 pc
= read_register (reg
);
1123 case 30: /* This is an extend instruction */
1124 pc
+= 4; /* Dont be setting breakpints on the second half */
1127 printf ("Filtered - next PC probably incorrrect due to jump inst\n");
1133 pc
+= 2; /* just a good old instruction */
1134 /* See if we CAN actually break on the next instruction */
1135 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
1137 } /* mips16_next_pc */
1139 /* The mips_next_pc function supports single_tep when the remote target monitor or
1140 stub is not developed enough to so a single_step.
1141 It works by decoding the current instruction and predicting where a branch
1142 will go. This isnt hard because all the data is available.
1143 The MIPS32 and MIPS16 variants are quite different
1146 mips_next_pc (CORE_ADDR pc
)
1149 /* inst = mips_fetch_instruction(pc) ; */
1150 /* if (pc_is_mips16) <----- This is failing */
1152 return mips16_next_pc (pc
);
1154 return mips32_next_pc (pc
);
1155 } /* mips_next_pc */
1157 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1161 mips_find_saved_regs (fci
)
1162 struct frame_info
*fci
;
1165 CORE_ADDR reg_position
;
1166 /* r0 bit means kernel trap */
1168 /* What registers have been saved? Bitmasks. */
1169 unsigned long gen_mask
, float_mask
;
1170 mips_extra_func_info_t proc_desc
;
1173 frame_saved_regs_zalloc (fci
);
1175 /* If it is the frame for sigtramp, the saved registers are located
1176 in a sigcontext structure somewhere on the stack.
1177 If the stack layout for sigtramp changes we might have to change these
1178 constants and the companion fixup_sigtramp in mdebugread.c */
1179 #ifndef SIGFRAME_BASE
1180 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1181 above the sigtramp frame. */
1182 #define SIGFRAME_BASE MIPS_REGSIZE
1183 /* FIXME! Are these correct?? */
1184 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1185 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1186 #define SIGFRAME_FPREGSAVE_OFF \
1187 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1189 #ifndef SIGFRAME_REG_SIZE
1190 /* FIXME! Is this correct?? */
1191 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1193 if (fci
->signal_handler_caller
)
1195 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1197 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1198 + ireg
* SIGFRAME_REG_SIZE
;
1199 fci
->saved_regs
[ireg
] = reg_position
;
1201 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1203 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1204 + ireg
* SIGFRAME_REG_SIZE
;
1205 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1207 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1211 proc_desc
= fci
->extra_info
->proc_desc
;
1212 if (proc_desc
== NULL
)
1213 /* I'm not sure how/whether this can happen. Normally when we can't
1214 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1215 and set the saved_regs right away. */
1218 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1219 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1220 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1222 if ( /* In any frame other than the innermost or a frame interrupted by
1223 a signal, we assume that all registers have been saved.
1224 This assumes that all register saves in a function happen before
1225 the first function call. */
1226 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1228 /* In a dummy frame we know exactly where things are saved. */
1229 && !PROC_DESC_IS_DUMMY (proc_desc
)
1231 /* Don't bother unless we are inside a function prologue. Outside the
1232 prologue, we know where everything is. */
1234 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1236 /* Not sure exactly what kernel_trap means, but if it means
1237 the kernel saves the registers without a prologue doing it,
1238 we better not examine the prologue to see whether registers
1239 have been saved yet. */
1242 /* We need to figure out whether the registers that the proc_desc
1243 claims are saved have been saved yet. */
1247 /* Bitmasks; set if we have found a save for the register. */
1248 unsigned long gen_save_found
= 0;
1249 unsigned long float_save_found
= 0;
1252 /* If the address is odd, assume this is MIPS16 code. */
1253 addr
= PROC_LOW_ADDR (proc_desc
);
1254 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1256 /* Scan through this function's instructions preceding the current
1257 PC, and look for those that save registers. */
1258 while (addr
< fci
->pc
)
1260 inst
= mips_fetch_instruction (addr
);
1261 if (pc_is_mips16 (addr
))
1262 mips16_decode_reg_save (inst
, &gen_save_found
);
1264 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1267 gen_mask
= gen_save_found
;
1268 float_mask
= float_save_found
;
1271 /* Fill in the offsets for the registers which gen_mask says
1273 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1274 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1275 if (gen_mask
& 0x80000000)
1277 fci
->saved_regs
[ireg
] = reg_position
;
1278 reg_position
-= MIPS_SAVED_REGSIZE
;
1281 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1282 of that normally used by gcc. Therefore, we have to fetch the first
1283 instruction of the function, and if it's an entry instruction that
1284 saves $s0 or $s1, correct their saved addresses. */
1285 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1287 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1288 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1291 int sreg_count
= (inst
>> 6) & 3;
1293 /* Check if the ra register was pushed on the stack. */
1294 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1296 reg_position
-= MIPS_SAVED_REGSIZE
;
1298 /* Check if the s0 and s1 registers were pushed on the stack. */
1299 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1301 fci
->saved_regs
[reg
] = reg_position
;
1302 reg_position
-= MIPS_SAVED_REGSIZE
;
1307 /* Fill in the offsets for the registers which float_mask says
1309 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1311 /* The freg_offset points to where the first *double* register
1312 is saved. So skip to the high-order word. */
1313 if (!GDB_TARGET_IS_MIPS64
)
1314 reg_position
+= MIPS_SAVED_REGSIZE
;
1316 /* Fill in the offsets for the float registers which float_mask says
1318 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1319 if (float_mask
& 0x80000000)
1321 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1322 reg_position
-= MIPS_SAVED_REGSIZE
;
1325 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1329 read_next_frame_reg (fi
, regno
)
1330 struct frame_info
*fi
;
1333 for (; fi
; fi
= fi
->next
)
1335 /* We have to get the saved sp from the sigcontext
1336 if it is a signal handler frame. */
1337 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1341 if (fi
->saved_regs
== NULL
)
1342 mips_find_saved_regs (fi
);
1343 if (fi
->saved_regs
[regno
])
1344 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1347 return read_register (regno
);
1350 /* mips_addr_bits_remove - remove useless address bits */
1353 mips_addr_bits_remove (addr
)
1356 if (GDB_TARGET_IS_MIPS64
)
1358 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1360 /* This hack is a work-around for existing boards using
1361 PMON, the simulator, and any other 64-bit targets that
1362 doesn't have true 64-bit addressing. On these targets,
1363 the upper 32 bits of addresses are ignored by the
1364 hardware. Thus, the PC or SP are likely to have been
1365 sign extended to all 1s by instruction sequences that
1366 load 32-bit addresses. For example, a typical piece of
1367 code that loads an address is this:
1368 lui $r2, <upper 16 bits>
1369 ori $r2, <lower 16 bits>
1370 But the lui sign-extends the value such that the upper 32
1371 bits may be all 1s. The workaround is simply to mask off
1372 these bits. In the future, gcc may be changed to support
1373 true 64-bit addressing, and this masking will have to be
1375 addr
&= (CORE_ADDR
) 0xffffffff;
1378 else if (mips_mask_address_p ())
1380 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1381 masking off bits, instead, the actual target should be asking
1382 for the address to be converted to a valid pointer. */
1383 /* Even when GDB is configured for some 32-bit targets
1384 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1385 so CORE_ADDR is 64 bits. So we still have to mask off
1386 useless bits from addresses. */
1387 addr
&= (CORE_ADDR
) 0xffffffff;
1393 mips_init_frame_pc_first (fromleaf
, prev
)
1395 struct frame_info
*prev
;
1399 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1400 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1401 tmp
= mips_skip_stub (pc
);
1402 prev
->pc
= tmp
? tmp
: pc
;
1407 mips_frame_saved_pc (frame
)
1408 struct frame_info
*frame
;
1411 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1412 /* We have to get the saved pc from the sigcontext
1413 if it is a signal handler frame. */
1414 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1415 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1417 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1418 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1420 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1422 return ADDR_BITS_REMOVE (saved_pc
);
1425 static struct mips_extra_func_info temp_proc_desc
;
1426 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1428 /* Set a register's saved stack address in temp_saved_regs. If an address
1429 has already been set for this register, do nothing; this way we will
1430 only recognize the first save of a given register in a function prologue.
1431 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1434 set_reg_offset (regno
, offset
)
1438 if (temp_saved_regs
[regno
] == 0)
1439 temp_saved_regs
[regno
] = offset
;
1443 /* Test whether the PC points to the return instruction at the
1444 end of a function. */
1447 mips_about_to_return (pc
)
1450 if (pc_is_mips16 (pc
))
1451 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1452 generates a "jr $ra"; other times it generates code to load
1453 the return address from the stack to an accessible register (such
1454 as $a3), then a "jr" using that register. This second case
1455 is almost impossible to distinguish from an indirect jump
1456 used for switch statements, so we don't even try. */
1457 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1459 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1463 /* This fencepost looks highly suspicious to me. Removing it also
1464 seems suspicious as it could affect remote debugging across serial
1468 heuristic_proc_start (pc
)
1476 pc
= ADDR_BITS_REMOVE (pc
);
1478 fence
= start_pc
- heuristic_fence_post
;
1482 if (heuristic_fence_post
== UINT_MAX
1483 || fence
< VM_MIN_ADDRESS
)
1484 fence
= VM_MIN_ADDRESS
;
1486 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1488 /* search back for previous return */
1489 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1490 if (start_pc
< fence
)
1492 /* It's not clear to me why we reach this point when
1493 stop_soon_quietly, but with this test, at least we
1494 don't print out warnings for every child forked (eg, on
1495 decstation). 22apr93 rich@cygnus.com. */
1496 if (!stop_soon_quietly
)
1498 static int blurb_printed
= 0;
1500 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1505 /* This actually happens frequently in embedded
1506 development, when you first connect to a board
1507 and your stack pointer and pc are nowhere in
1508 particular. This message needs to give people
1509 in that situation enough information to
1510 determine that it's no big deal. */
1511 printf_filtered ("\n\
1512 GDB is unable to find the start of the function at 0x%s\n\
1513 and thus can't determine the size of that function's stack frame.\n\
1514 This means that GDB may be unable to access that stack frame, or\n\
1515 the frames below it.\n\
1516 This problem is most likely caused by an invalid program counter or\n\
1518 However, if you think GDB should simply search farther back\n\
1519 from 0x%s for code which looks like the beginning of a\n\
1520 function, you can increase the range of the search using the `set\n\
1521 heuristic-fence-post' command.\n",
1522 paddr_nz (pc
), paddr_nz (pc
));
1529 else if (pc_is_mips16 (start_pc
))
1531 unsigned short inst
;
1533 /* On MIPS16, any one of the following is likely to be the
1534 start of a function:
1538 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1539 inst
= mips_fetch_instruction (start_pc
);
1540 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1541 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1542 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1543 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1545 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1546 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1551 else if (mips_about_to_return (start_pc
))
1553 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1558 /* skip nops (usually 1) 0 - is this */
1559 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1560 start_pc
+= MIPS_INSTLEN
;
1565 /* Fetch the immediate value from a MIPS16 instruction.
1566 If the previous instruction was an EXTEND, use it to extend
1567 the upper bits of the immediate value. This is a helper function
1568 for mips16_heuristic_proc_desc. */
1571 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1572 unsigned short prev_inst
; /* previous instruction */
1573 unsigned short inst
; /* current instruction */
1574 int nbits
; /* number of bits in imm field */
1575 int scale
; /* scale factor to be applied to imm */
1576 int is_signed
; /* is the imm field signed? */
1580 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1582 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1583 if (offset
& 0x8000) /* check for negative extend */
1584 offset
= 0 - (0x10000 - (offset
& 0xffff));
1585 return offset
| (inst
& 0x1f);
1589 int max_imm
= 1 << nbits
;
1590 int mask
= max_imm
- 1;
1591 int sign_bit
= max_imm
>> 1;
1593 offset
= inst
& mask
;
1594 if (is_signed
&& (offset
& sign_bit
))
1595 offset
= 0 - (max_imm
- offset
);
1596 return offset
* scale
;
1601 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1602 stream from start_pc to limit_pc. */
1605 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1606 CORE_ADDR start_pc
, limit_pc
;
1607 struct frame_info
*next_frame
;
1611 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1612 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1613 unsigned inst
= 0; /* current instruction */
1614 unsigned entry_inst
= 0; /* the entry instruction */
1617 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1618 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1620 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1622 /* Save the previous instruction. If it's an EXTEND, we'll extract
1623 the immediate offset extension from it in mips16_get_imm. */
1626 /* Fetch and decode the instruction. */
1627 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1628 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1629 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1631 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1632 if (offset
< 0) /* negative stack adjustment? */
1633 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1635 /* Exit loop if a positive stack adjustment is found, which
1636 usually means that the stack cleanup code in the function
1637 epilogue is reached. */
1640 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1642 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1643 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1644 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1645 set_reg_offset (reg
, sp
+ offset
);
1647 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1649 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1650 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1651 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1652 set_reg_offset (reg
, sp
+ offset
);
1654 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1656 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1657 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1658 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1660 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1662 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1663 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1664 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1666 else if (inst
== 0x673d) /* move $s1, $sp */
1669 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1671 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1673 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1674 frame_addr
= sp
+ offset
;
1675 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1676 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1678 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1680 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1681 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1682 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1683 set_reg_offset (reg
, frame_addr
+ offset
);
1685 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1687 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1688 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1689 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1690 set_reg_offset (reg
, frame_addr
+ offset
);
1692 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1693 entry_inst
= inst
; /* save for later processing */
1694 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1695 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1698 /* The entry instruction is typically the first instruction in a function,
1699 and it stores registers at offsets relative to the value of the old SP
1700 (before the prologue). But the value of the sp parameter to this
1701 function is the new SP (after the prologue has been executed). So we
1702 can't calculate those offsets until we've seen the entire prologue,
1703 and can calculate what the old SP must have been. */
1704 if (entry_inst
!= 0)
1706 int areg_count
= (entry_inst
>> 8) & 7;
1707 int sreg_count
= (entry_inst
>> 6) & 3;
1709 /* The entry instruction always subtracts 32 from the SP. */
1710 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1712 /* Now we can calculate what the SP must have been at the
1713 start of the function prologue. */
1714 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1716 /* Check if a0-a3 were saved in the caller's argument save area. */
1717 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1719 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1720 set_reg_offset (reg
, sp
+ offset
);
1721 offset
+= MIPS_SAVED_REGSIZE
;
1724 /* Check if the ra register was pushed on the stack. */
1726 if (entry_inst
& 0x20)
1728 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1729 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1730 offset
-= MIPS_SAVED_REGSIZE
;
1733 /* Check if the s0 and s1 registers were pushed on the stack. */
1734 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1736 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1737 set_reg_offset (reg
, sp
+ offset
);
1738 offset
-= MIPS_SAVED_REGSIZE
;
1744 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1745 CORE_ADDR start_pc
, limit_pc
;
1746 struct frame_info
*next_frame
;
1750 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1752 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1753 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1754 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1755 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1757 unsigned long inst
, high_word
, low_word
;
1760 /* Fetch the instruction. */
1761 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1763 /* Save some code by pre-extracting some useful fields. */
1764 high_word
= (inst
>> 16) & 0xffff;
1765 low_word
= inst
& 0xffff;
1766 reg
= high_word
& 0x1f;
1768 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1769 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1770 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1772 if (low_word
& 0x8000) /* negative stack adjustment? */
1773 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1775 /* Exit loop if a positive stack adjustment is found, which
1776 usually means that the stack cleanup code in the function
1777 epilogue is reached. */
1780 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1782 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1783 set_reg_offset (reg
, sp
+ low_word
);
1785 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1787 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1788 but the register size used is only 32 bits. Make the address
1789 for the saved register point to the lower 32 bits. */
1790 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1791 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1793 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1795 /* Old gcc frame, r30 is virtual frame pointer. */
1796 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1797 frame_addr
= sp
+ low_word
;
1798 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1800 unsigned alloca_adjust
;
1801 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1802 frame_addr
= read_next_frame_reg (next_frame
, 30);
1803 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1804 if (alloca_adjust
> 0)
1806 /* FP > SP + frame_size. This may be because
1807 * of an alloca or somethings similar.
1808 * Fix sp to "pre-alloca" value, and try again.
1810 sp
+= alloca_adjust
;
1815 /* move $30,$sp. With different versions of gas this will be either
1816 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1817 Accept any one of these. */
1818 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1820 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1821 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1823 unsigned alloca_adjust
;
1824 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1825 frame_addr
= read_next_frame_reg (next_frame
, 30);
1826 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1827 if (alloca_adjust
> 0)
1829 /* FP > SP + frame_size. This may be because
1830 * of an alloca or somethings similar.
1831 * Fix sp to "pre-alloca" value, and try again.
1833 sp
+= alloca_adjust
;
1838 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1840 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1841 set_reg_offset (reg
, frame_addr
+ low_word
);
1846 static mips_extra_func_info_t
1847 heuristic_proc_desc (start_pc
, limit_pc
, next_frame
)
1848 CORE_ADDR start_pc
, limit_pc
;
1849 struct frame_info
*next_frame
;
1851 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1855 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1856 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1857 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1858 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1859 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1861 if (start_pc
+ 200 < limit_pc
)
1862 limit_pc
= start_pc
+ 200;
1863 if (pc_is_mips16 (start_pc
))
1864 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1866 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1867 return &temp_proc_desc
;
1870 static mips_extra_func_info_t
1871 non_heuristic_proc_desc (pc
, addrptr
)
1875 CORE_ADDR startaddr
;
1876 mips_extra_func_info_t proc_desc
;
1877 struct block
*b
= block_for_pc (pc
);
1880 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1882 *addrptr
= startaddr
;
1883 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1887 if (startaddr
> BLOCK_START (b
))
1888 /* This is the "pathological" case referred to in a comment in
1889 print_frame_info. It might be better to move this check into
1893 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1896 /* If we never found a PDR for this function in symbol reading, then
1897 examine prologues to find the information. */
1900 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1901 if (PROC_FRAME_REG (proc_desc
) == -1)
1911 static mips_extra_func_info_t
1912 find_proc_desc (pc
, next_frame
)
1914 struct frame_info
*next_frame
;
1916 mips_extra_func_info_t proc_desc
;
1917 CORE_ADDR startaddr
;
1919 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1923 /* IF this is the topmost frame AND
1924 * (this proc does not have debugging information OR
1925 * the PC is in the procedure prologue)
1926 * THEN create a "heuristic" proc_desc (by analyzing
1927 * the actual code) to replace the "official" proc_desc.
1929 if (next_frame
== NULL
)
1931 struct symtab_and_line val
;
1932 struct symbol
*proc_symbol
=
1933 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1937 val
= find_pc_line (BLOCK_START
1938 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1940 val
.pc
= val
.end
? val
.end
: pc
;
1942 if (!proc_symbol
|| pc
< val
.pc
)
1944 mips_extra_func_info_t found_heuristic
=
1945 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1947 if (found_heuristic
)
1948 proc_desc
= found_heuristic
;
1954 /* Is linked_proc_desc_table really necessary? It only seems to be used
1955 by procedure call dummys. However, the procedures being called ought
1956 to have their own proc_descs, and even if they don't,
1957 heuristic_proc_desc knows how to create them! */
1959 register struct linked_proc_info
*link
;
1961 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1962 if (PROC_LOW_ADDR (&link
->info
) <= pc
1963 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1967 startaddr
= heuristic_proc_start (pc
);
1970 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1976 get_frame_pointer (frame
, proc_desc
)
1977 struct frame_info
*frame
;
1978 mips_extra_func_info_t proc_desc
;
1980 return ADDR_BITS_REMOVE (
1981 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1982 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1985 mips_extra_func_info_t cached_proc_desc
;
1988 mips_frame_chain (frame
)
1989 struct frame_info
*frame
;
1991 mips_extra_func_info_t proc_desc
;
1993 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
1995 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1998 /* Check if the PC is inside a call stub. If it is, fetch the
1999 PC of the caller of that stub. */
2000 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
2003 /* Look up the procedure descriptor for this PC. */
2004 proc_desc
= find_proc_desc (saved_pc
, frame
);
2008 cached_proc_desc
= proc_desc
;
2010 /* If no frame pointer and frame size is zero, we must be at end
2011 of stack (or otherwise hosed). If we don't check frame size,
2012 we loop forever if we see a zero size frame. */
2013 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2014 && PROC_FRAME_OFFSET (proc_desc
) == 0
2015 /* The previous frame from a sigtramp frame might be frameless
2016 and have frame size zero. */
2017 && !frame
->signal_handler_caller
)
2020 return get_frame_pointer (frame
, proc_desc
);
2024 mips_init_extra_frame_info (fromleaf
, fci
)
2026 struct frame_info
*fci
;
2030 /* Use proc_desc calculated in frame_chain */
2031 mips_extra_func_info_t proc_desc
=
2032 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
2034 fci
->extra_info
= (struct frame_extra_info
*)
2035 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2037 fci
->saved_regs
= NULL
;
2038 fci
->extra_info
->proc_desc
=
2039 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2042 /* Fixup frame-pointer - only needed for top frame */
2043 /* This may not be quite right, if proc has a real frame register.
2044 Get the value of the frame relative sp, procedure might have been
2045 interrupted by a signal at it's very start. */
2046 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2047 && !PROC_DESC_IS_DUMMY (proc_desc
))
2048 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2050 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2052 if (proc_desc
== &temp_proc_desc
)
2056 /* Do not set the saved registers for a sigtramp frame,
2057 mips_find_saved_registers will do that for us.
2058 We can't use fci->signal_handler_caller, it is not yet set. */
2059 find_pc_partial_function (fci
->pc
, &name
,
2060 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2061 if (!IN_SIGTRAMP (fci
->pc
, name
))
2063 frame_saved_regs_zalloc (fci
);
2064 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2065 fci
->saved_regs
[PC_REGNUM
]
2066 = fci
->saved_regs
[RA_REGNUM
];
2070 /* hack: if argument regs are saved, guess these contain args */
2071 /* assume we can't tell how many args for now */
2072 fci
->extra_info
->num_args
= -1;
2073 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2075 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2077 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2084 /* MIPS stack frames are almost impenetrable. When execution stops,
2085 we basically have to look at symbol information for the function
2086 that we stopped in, which tells us *which* register (if any) is
2087 the base of the frame pointer, and what offset from that register
2088 the frame itself is at.
2090 This presents a problem when trying to examine a stack in memory
2091 (that isn't executing at the moment), using the "frame" command. We
2092 don't have a PC, nor do we have any registers except SP.
2094 This routine takes two arguments, SP and PC, and tries to make the
2095 cached frames look as if these two arguments defined a frame on the
2096 cache. This allows the rest of info frame to extract the important
2097 arguments without difficulty. */
2100 setup_arbitrary_frame (argc
, argv
)
2105 error ("MIPS frame specifications require two arguments: sp and pc");
2107 return create_new_frame (argv
[0], argv
[1]);
2110 /* According to the current ABI, should the type be passed in a
2111 floating-point register (assuming that there is space)? When there
2112 is no FPU, FP are not even considered as possibile candidates for
2113 FP registers and, consequently this returns false - forces FP
2114 arguments into integer registers. */
2117 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2119 return ((typecode
== TYPE_CODE_FLT
2121 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2122 && TYPE_NFIELDS (arg_type
) == 1
2123 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2124 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2128 mips_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
2133 CORE_ADDR struct_addr
;
2139 int stack_offset
= 0;
2141 /* Macros to round N up or down to the next A boundary; A must be
2143 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2144 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2146 /* First ensure that the stack and structure return address (if any)
2147 are properly aligned. The stack has to be at least 64-bit aligned
2148 even on 32-bit machines, because doubles must be 64-bit aligned.
2149 On at least one MIPS variant, stack frames need to be 128-bit
2150 aligned, so we round to this widest known alignment. */
2151 sp
= ROUND_DOWN (sp
, 16);
2152 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2154 /* Now make space on the stack for the args. We allocate more
2155 than necessary for EABI, because the first few arguments are
2156 passed in registers, but that's OK. */
2157 for (argnum
= 0; argnum
< nargs
; argnum
++)
2158 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_STACK_ARGSIZE
);
2159 sp
-= ROUND_UP (len
, 16);
2162 fprintf_unfiltered (gdb_stdlog
, "mips_push_arguments: sp=0x%lx allocated %d\n",
2163 (long) sp
, ROUND_UP (len
, 16));
2165 /* Initialize the integer and float register pointers. */
2167 float_argreg
= FPA0_REGNUM
;
2169 /* the struct_return pointer occupies the first parameter-passing reg */
2173 fprintf_unfiltered (gdb_stdlog
,
2174 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2175 argreg
, (long) struct_addr
);
2176 write_register (argreg
++, struct_addr
);
2177 if (MIPS_REGS_HAVE_HOME_P
)
2178 stack_offset
+= MIPS_STACK_ARGSIZE
;
2181 /* Now load as many as possible of the first arguments into
2182 registers, and push the rest onto the stack. Loop thru args
2183 from first to last. */
2184 for (argnum
= 0; argnum
< nargs
; argnum
++)
2187 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2188 value_ptr arg
= args
[argnum
];
2189 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2190 int len
= TYPE_LENGTH (arg_type
);
2191 enum type_code typecode
= TYPE_CODE (arg_type
);
2194 fprintf_unfiltered (gdb_stdlog
,
2195 "mips_push_arguments: %d len=%d type=%d",
2196 argnum
, len
, (int) typecode
);
2198 /* The EABI passes structures that do not fit in a register by
2199 reference. In all other cases, pass the structure by value. */
2201 && len
> MIPS_SAVED_REGSIZE
2202 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2204 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2205 typecode
= TYPE_CODE_PTR
;
2206 len
= MIPS_SAVED_REGSIZE
;
2209 fprintf_unfiltered (gdb_stdlog
, " push");
2212 val
= (char *) VALUE_CONTENTS (arg
);
2214 /* 32-bit ABIs always start floating point arguments in an
2215 even-numbered floating point register. */
2216 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
2217 && (float_argreg
& 1))
2220 /* Floating point arguments passed in registers have to be
2221 treated specially. On 32-bit architectures, doubles
2222 are passed in register pairs; the even register gets
2223 the low word, and the odd register gets the high word.
2224 On non-EABI processors, the first two floating point arguments are
2225 also copied to general registers, because MIPS16 functions
2226 don't use float registers for arguments. This duplication of
2227 arguments in general registers can't hurt non-MIPS16 functions
2228 because those registers are normally skipped. */
2229 /* MIPS_EABI squeeses a struct that contains a single floating
2230 point value into an FP register instead of pusing it onto the
2232 if (fp_register_arg_p (typecode
, arg_type
)
2233 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2235 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2237 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2238 unsigned long regval
;
2240 /* Write the low word of the double to the even register(s). */
2241 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2243 fprintf_unfiltered (gdb_stdlog
, " fpreg=%d val=%s",
2244 float_argreg
, phex (regval
, 4));
2245 write_register (float_argreg
++, regval
);
2249 fprintf_unfiltered (gdb_stdlog
, " reg=%d val=%s",
2250 argreg
, phex (regval
, 4));
2251 write_register (argreg
++, regval
);
2254 /* Write the high word of the double to the odd register(s). */
2255 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2257 fprintf_unfiltered (gdb_stdlog
, " fpreg=%d val=%s",
2258 float_argreg
, phex (regval
, 4));
2259 write_register (float_argreg
++, regval
);
2263 fprintf_unfiltered (gdb_stdlog
, " reg=%d val=%s",
2264 argreg
, phex (regval
, 4));
2265 write_register (argreg
++, regval
);
2271 /* This is a floating point value that fits entirely
2272 in a single register. */
2273 /* On 32 bit ABI's the float_argreg is further adjusted
2274 above to ensure that it is even register aligned. */
2275 LONGEST regval
= extract_unsigned_integer (val
, len
);
2277 fprintf_unfiltered (gdb_stdlog
, " fpreg=%d val=%s",
2278 float_argreg
, phex (regval
, len
));
2279 write_register (float_argreg
++, regval
);
2282 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2283 registers for each argument. The below is (my
2284 guess) to ensure that the corresponding integer
2285 register has reserved the same space. */
2287 fprintf_unfiltered (gdb_stdlog
, " reg=%d val=%s",
2288 argreg
, phex (regval
, len
));
2289 write_register (argreg
, regval
);
2290 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2293 /* Reserve space for the FP register. */
2294 if (MIPS_REGS_HAVE_HOME_P
)
2295 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
2299 /* Copy the argument to general registers or the stack in
2300 register-sized pieces. Large arguments are split between
2301 registers and stack. */
2302 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2303 are treated specially: Irix cc passes them in registers
2304 where gcc sometimes puts them on the stack. For maximum
2305 compatibility, we will put them in both places. */
2306 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2307 (len
% MIPS_SAVED_REGSIZE
!= 0));
2308 /* Note: Floating-point values that didn't fit into an FP
2309 register are only written to memory. */
2312 /* Rememer if the argument was written to the stack. */
2313 int stack_used_p
= 0;
2314 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2316 /* Write this portion of the argument to the stack. */
2317 if (argreg
> MIPS_LAST_ARG_REGNUM
2319 || fp_register_arg_p (typecode
, arg_type
))
2321 /* Should shorter than int integer values be
2322 promoted to int before being stored? */
2323 int longword_offset
= 0;
2326 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2328 if (MIPS_STACK_ARGSIZE
== 8 &&
2329 (typecode
== TYPE_CODE_INT
||
2330 typecode
== TYPE_CODE_PTR
||
2331 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2332 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2333 else if ((typecode
== TYPE_CODE_STRUCT
||
2334 typecode
== TYPE_CODE_UNION
) &&
2335 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2336 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2341 fprintf_unfiltered (gdb_stdlog
, " stack_offset=0x%lx",
2342 (long) stack_offset
);
2343 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%lx",
2344 (long) longword_offset
);
2347 addr
= sp
+ stack_offset
+ longword_offset
;
2352 fprintf_unfiltered (gdb_stdlog
, " @0x%lx ", (long) addr
);
2353 for (i
= 0; i
< partial_len
; i
++)
2355 fprintf_unfiltered (gdb_stdlog
, "%02x", val
[i
] & 0xff);
2358 write_memory (addr
, val
, partial_len
);
2361 /* Note!!! This is NOT an else clause. Odd sized
2362 structs may go thru BOTH paths. Floating point
2363 arguments will not. */
2364 /* Write this portion of the argument to a general
2365 purpose register. */
2366 if (argreg
<= MIPS_LAST_ARG_REGNUM
2367 && !fp_register_arg_p (typecode
, arg_type
))
2369 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2371 /* A non-floating-point argument being passed in a
2372 general register. If a struct or union, and if
2373 the remaining length is smaller than the register
2374 size, we have to adjust the register value on
2377 It does not seem to be necessary to do the
2378 same for integral types.
2380 Also don't do this adjustment on EABI and O64
2384 && MIPS_SAVED_REGSIZE
< 8
2385 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2386 && partial_len
< MIPS_SAVED_REGSIZE
2387 && (typecode
== TYPE_CODE_STRUCT
||
2388 typecode
== TYPE_CODE_UNION
))
2389 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2393 fprintf_filtered (gdb_stdlog
, " reg=%d val=%s",
2395 phex (regval
, MIPS_SAVED_REGSIZE
));
2396 write_register (argreg
, regval
);
2399 /* If this is the old ABI, prevent subsequent floating
2400 point arguments from being passed in floating point
2403 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2409 /* Compute the the offset into the stack at which we
2410 will copy the next parameter.
2412 In older ABIs, the caller reserved space for
2413 registers that contained arguments. This was loosely
2414 refered to as their "home". Consequently, space is
2417 In the new EABI (and the NABI32), the stack_offset
2418 only needs to be adjusted when it has been used.. */
2420 if (MIPS_REGS_HAVE_HOME_P
|| stack_used_p
)
2421 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2425 fprintf_unfiltered (gdb_stdlog
, "\n");
2428 /* Return adjusted stack pointer. */
2433 mips_push_return_address (pc
, sp
)
2437 /* Set the return address register to point to the entry
2438 point of the program, where a breakpoint lies in wait. */
2439 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2444 mips_push_register (CORE_ADDR
* sp
, int regno
)
2446 char buffer
[MAX_REGISTER_RAW_SIZE
];
2449 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2451 regsize
= MIPS_SAVED_REGSIZE
;
2452 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2453 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2458 regsize
= REGISTER_RAW_SIZE (regno
);
2462 read_register_gen (regno
, buffer
);
2463 write_memory (*sp
, buffer
+ offset
, regsize
);
2466 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2467 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2470 mips_push_dummy_frame ()
2473 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2474 xmalloc (sizeof (struct linked_proc_info
));
2475 mips_extra_func_info_t proc_desc
= &link
->info
;
2476 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2477 CORE_ADDR old_sp
= sp
;
2478 link
->next
= linked_proc_desc_table
;
2479 linked_proc_desc_table
= link
;
2481 /* FIXME! are these correct ? */
2482 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2483 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2484 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2485 #define FLOAT_SINGLE_REG_SAVE_MASK \
2486 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2488 * The registers we must save are all those not preserved across
2489 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2490 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2491 * and FP Control/Status registers.
2494 * Dummy frame layout:
2497 * Saved MMHI, MMLO, FPC_CSR
2502 * Saved D18 (i.e. F19, F18)
2504 * Saved D0 (i.e. F1, F0)
2505 * Argument build area and stack arguments written via mips_push_arguments
2509 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2510 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2511 PROC_FRAME_OFFSET (proc_desc
) = 0;
2512 PROC_FRAME_ADJUST (proc_desc
) = 0;
2513 mips_push_register (&sp
, PC_REGNUM
);
2514 mips_push_register (&sp
, HI_REGNUM
);
2515 mips_push_register (&sp
, LO_REGNUM
);
2516 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2518 /* Save general CPU registers */
2519 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2520 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2521 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2522 for (ireg
= 32; --ireg
>= 0;)
2523 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2524 mips_push_register (&sp
, ireg
);
2526 /* Save floating point registers starting with high order word */
2527 PROC_FREG_MASK (proc_desc
) =
2528 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2529 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2530 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2532 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2533 for (ireg
= 32; --ireg
>= 0;)
2534 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2535 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2537 /* Update the frame pointer for the call dummy and the stack pointer.
2538 Set the procedure's starting and ending addresses to point to the
2539 call dummy address at the entry point. */
2540 write_register (PUSH_FP_REGNUM
, old_sp
);
2541 write_register (SP_REGNUM
, sp
);
2542 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2543 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2544 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2545 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2551 register int regnum
;
2552 struct frame_info
*frame
= get_current_frame ();
2553 CORE_ADDR new_sp
= FRAME_FP (frame
);
2555 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2557 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2558 if (frame
->saved_regs
== NULL
)
2559 mips_find_saved_regs (frame
);
2560 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2562 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2563 && frame
->saved_regs
[regnum
])
2564 write_register (regnum
,
2565 read_memory_integer (frame
->saved_regs
[regnum
],
2566 MIPS_SAVED_REGSIZE
));
2568 write_register (SP_REGNUM
, new_sp
);
2569 flush_cached_frames ();
2571 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2573 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2575 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2577 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2579 if (&pi_ptr
->info
== proc_desc
)
2584 error ("Can't locate dummy extra frame info\n");
2586 if (prev_ptr
!= NULL
)
2587 prev_ptr
->next
= pi_ptr
->next
;
2589 linked_proc_desc_table
= pi_ptr
->next
;
2593 write_register (HI_REGNUM
,
2594 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2595 MIPS_SAVED_REGSIZE
));
2596 write_register (LO_REGNUM
,
2597 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2598 MIPS_SAVED_REGSIZE
));
2599 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2600 write_register (FCRCS_REGNUM
,
2601 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2602 MIPS_SAVED_REGSIZE
));
2607 mips_print_register (regnum
, all
)
2610 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2612 /* Get the data in raw format. */
2613 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2615 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2619 /* If an even floating point register, also print as double. */
2620 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2621 && !((regnum
- FP0_REGNUM
) & 1))
2622 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2624 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2626 read_relative_register_raw_bytes (regnum
, dbuffer
);
2627 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2628 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2630 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2631 val_print (builtin_type_double
, dbuffer
, 0, 0,
2632 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2633 printf_filtered ("); ");
2635 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2637 /* The problem with printing numeric register names (r26, etc.) is that
2638 the user can't use them on input. Probably the best solution is to
2639 fix it so that either the numeric or the funky (a2, etc.) names
2640 are accepted on input. */
2641 if (regnum
< MIPS_NUMREGS
)
2642 printf_filtered ("(r%d): ", regnum
);
2644 printf_filtered (": ");
2646 /* If virtual format is floating, print it that way. */
2647 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2648 if (FP_REGISTER_DOUBLE
)
2649 { /* show 8-byte floats as float AND double: */
2650 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2652 printf_filtered (" (float) ");
2653 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2654 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2655 printf_filtered (", (double) ");
2656 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2657 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2660 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2661 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2662 /* Else print as integer in hex. */
2667 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2668 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2672 print_scalar_formatted (raw_buffer
+ offset
,
2673 REGISTER_VIRTUAL_TYPE (regnum
),
2674 'x', 0, gdb_stdout
);
2678 /* Replacement for generic do_registers_info.
2679 Print regs in pretty columns. */
2682 do_fp_register_row (regnum
)
2684 { /* do values for FP (float) regs */
2685 char *raw_buffer
[2];
2687 /* use HI and LO to control the order of combining two flt regs */
2688 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2689 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2690 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2691 int inv1
, inv2
, inv3
;
2693 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2694 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2695 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2697 /* Get the data in raw format. */
2698 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2699 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2700 if (REGISTER_RAW_SIZE (regnum
) == 4)
2702 /* 4-byte registers: we can fit two registers per row. */
2703 /* Also print every pair of 4-byte regs as an 8-byte double. */
2704 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2705 error ("can't read register %d (%s)",
2706 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2708 /* copy the two floats into one double, and unpack both */
2709 memcpy (dbl_buffer
, raw_buffer
, 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2710 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2711 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2712 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2714 printf_filtered (inv1
? " %-5s: <invalid float>" :
2715 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2716 printf_filtered (inv2
? " %-5s: <invalid float>" :
2717 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2718 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2719 " dbl: %-24.17g\n", doub
);
2720 /* may want to do hex display here (future enhancement) */
2724 { /* eight byte registers: print each one as float AND as double. */
2725 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2727 memcpy (dbl_buffer
, raw_buffer
[HI
], 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2728 flt1
= unpack_double (builtin_type_float
,
2729 &raw_buffer
[HI
][offset
], &inv1
);
2730 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2732 printf_filtered (inv1
? " %-5s: <invalid float>" :
2733 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2734 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2735 " dbl: %-24.17g\n", doub
);
2736 /* may want to do hex display here (future enhancement) */
2742 /* Print a row's worth of GP (int) registers, with name labels above */
2745 do_gp_register_row (regnum
)
2748 /* do values for GP (int) regs */
2749 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2750 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2752 int start_regnum
= regnum
;
2753 int numregs
= NUM_REGS
;
2756 /* For GP registers, we print a separate row of names above the vals */
2757 printf_filtered (" ");
2758 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2760 if (*REGISTER_NAME (regnum
) == '\0')
2761 continue; /* unused register */
2762 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2763 break; /* end the row: reached FP register */
2764 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2765 REGISTER_NAME (regnum
));
2768 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2769 start_regnum
); /* print the R0 to R31 names */
2771 regnum
= start_regnum
; /* go back to start of row */
2772 /* now print the values in hex, 4 or 8 to the row */
2773 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2775 if (*REGISTER_NAME (regnum
) == '\0')
2776 continue; /* unused register */
2777 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2778 break; /* end row: reached FP register */
2779 /* OK: get the data in raw format. */
2780 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2781 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2782 /* pad small registers */
2783 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
2784 printf_filtered (" ");
2785 /* Now print the register value in hex, endian order. */
2786 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2787 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2788 byte
< REGISTER_RAW_SIZE (regnum
);
2790 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2792 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
2795 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2796 printf_filtered (" ");
2799 if (col
> 0) /* ie. if we actually printed anything... */
2800 printf_filtered ("\n");
2805 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2808 mips_do_registers_info (regnum
, fpregs
)
2812 if (regnum
!= -1) /* do one specified register */
2814 if (*(REGISTER_NAME (regnum
)) == '\0')
2815 error ("Not a valid register for the current processor type");
2817 mips_print_register (regnum
, 0);
2818 printf_filtered ("\n");
2821 /* do all (or most) registers */
2824 while (regnum
< NUM_REGS
)
2826 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2827 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2828 regnum
= do_fp_register_row (regnum
); /* FP regs */
2830 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2832 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2837 /* Return number of args passed to a frame. described by FIP.
2838 Can return -1, meaning no way to tell. */
2841 mips_frame_num_args (frame
)
2842 struct frame_info
*frame
;
2844 #if 0 /* FIXME Use or lose this! */
2845 struct chain_info_t
*p
;
2847 p
= mips_find_cached_frame (FRAME_FP (frame
));
2849 return p
->the_info
.numargs
;
2854 /* Is this a branch with a delay slot? */
2856 static int is_delayed (unsigned long);
2863 for (i
= 0; i
< NUMOPCODES
; ++i
)
2864 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2865 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2867 return (i
< NUMOPCODES
2868 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2869 | INSN_COND_BRANCH_DELAY
2870 | INSN_COND_BRANCH_LIKELY
)));
2874 mips_step_skips_delay (pc
)
2877 char buf
[MIPS_INSTLEN
];
2879 /* There is no branch delay slot on MIPS16. */
2880 if (pc_is_mips16 (pc
))
2883 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2884 /* If error reading memory, guess that it is not a delayed branch. */
2886 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2890 /* Skip the PC past function prologue instructions (32-bit version).
2891 This is a helper function for mips_skip_prologue. */
2894 mips32_skip_prologue (CORE_ADDR pc
)
2898 int seen_sp_adjust
= 0;
2899 int load_immediate_bytes
= 0;
2901 /* Skip the typical prologue instructions. These are the stack adjustment
2902 instruction and the instructions that save registers on the stack
2903 or in the gcc frame. */
2904 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2906 unsigned long high_word
;
2908 inst
= mips_fetch_instruction (pc
);
2909 high_word
= (inst
>> 16) & 0xffff;
2912 if (lenient
&& is_delayed (inst
))
2916 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2917 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2919 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2920 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2922 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2923 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2924 && (inst
& 0x001F0000)) /* reg != $zero */
2927 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2929 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2931 continue; /* reg != $zero */
2933 /* move $s8,$sp. With different versions of gas this will be either
2934 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2935 Accept any one of these. */
2936 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2939 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2941 else if (high_word
== 0x3c1c) /* lui $gp,n */
2943 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2945 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2946 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2948 /* The following instructions load $at or $t0 with an immediate
2949 value in preparation for a stack adjustment via
2950 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2951 a local variable, so we accept them only before a stack adjustment
2952 instruction was seen. */
2953 else if (!seen_sp_adjust
)
2955 if (high_word
== 0x3c01 || /* lui $at,n */
2956 high_word
== 0x3c08) /* lui $t0,n */
2958 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2961 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2962 high_word
== 0x3508 || /* ori $t0,$t0,n */
2963 high_word
== 0x3401 || /* ori $at,$zero,n */
2964 high_word
== 0x3408) /* ori $t0,$zero,n */
2966 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2976 /* In a frameless function, we might have incorrectly
2977 skipped some load immediate instructions. Undo the skipping
2978 if the load immediate was not followed by a stack adjustment. */
2979 if (load_immediate_bytes
&& !seen_sp_adjust
)
2980 pc
-= load_immediate_bytes
;
2984 /* Skip the PC past function prologue instructions (16-bit version).
2985 This is a helper function for mips_skip_prologue. */
2988 mips16_skip_prologue (CORE_ADDR pc
)
2991 int extend_bytes
= 0;
2992 int prev_extend_bytes
;
2994 /* Table of instructions likely to be found in a function prologue. */
2997 unsigned short inst
;
2998 unsigned short mask
;
3005 , /* addiu $sp,offset */
3009 , /* daddiu $sp,offset */
3013 , /* sw reg,n($sp) */
3017 , /* sd reg,n($sp) */
3021 , /* sw $ra,n($sp) */
3025 , /* sd $ra,n($sp) */
3033 , /* sw $a0-$a3,n($s1) */
3037 , /* move reg,$a0-$a3 */
3041 , /* entry pseudo-op */
3045 , /* addiu $s1,$sp,n */
3048 } /* end of table marker */
3051 /* Skip the typical prologue instructions. These are the stack adjustment
3052 instruction and the instructions that save registers on the stack
3053 or in the gcc frame. */
3054 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
3056 unsigned short inst
;
3059 inst
= mips_fetch_instruction (pc
);
3061 /* Normally we ignore an extend instruction. However, if it is
3062 not followed by a valid prologue instruction, we must adjust
3063 the pc back over the extend so that it won't be considered
3064 part of the prologue. */
3065 if ((inst
& 0xf800) == 0xf000) /* extend */
3067 extend_bytes
= MIPS16_INSTLEN
;
3070 prev_extend_bytes
= extend_bytes
;
3073 /* Check for other valid prologue instructions besides extend. */
3074 for (i
= 0; table
[i
].mask
!= 0; i
++)
3075 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
3077 if (table
[i
].mask
!= 0) /* it was in table? */
3078 continue; /* ignore it */
3082 /* Return the current pc, adjusted backwards by 2 if
3083 the previous instruction was an extend. */
3084 return pc
- prev_extend_bytes
;
3090 /* To skip prologues, I use this predicate. Returns either PC itself
3091 if the code at PC does not look like a function prologue; otherwise
3092 returns an address that (if we're lucky) follows the prologue. If
3093 LENIENT, then we must skip everything which is involved in setting
3094 up the frame (it's OK to skip more, just so long as we don't skip
3095 anything which might clobber the registers which are being saved.
3096 We must skip more in the case where part of the prologue is in the
3097 delay slot of a non-prologue instruction). */
3100 mips_skip_prologue (CORE_ADDR pc
)
3102 /* See if we can determine the end of the prologue via the symbol table.
3103 If so, then return either PC, or the PC after the prologue, whichever
3106 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
3108 if (post_prologue_pc
!= 0)
3109 return max (pc
, post_prologue_pc
);
3111 /* Can't determine prologue from the symbol table, need to examine
3114 if (pc_is_mips16 (pc
))
3115 return mips16_skip_prologue (pc
);
3117 return mips32_skip_prologue (pc
);
3120 /* Determine how a return value is stored within the MIPS register
3121 file, given the return type `valtype'. */
3123 struct return_value_word
3131 static void return_value_location (struct type
*, struct return_value_word
*,
3132 struct return_value_word
*);
3135 return_value_location (valtype
, hi
, lo
)
3136 struct type
*valtype
;
3137 struct return_value_word
*hi
;
3138 struct return_value_word
*lo
;
3140 int len
= TYPE_LENGTH (valtype
);
3142 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3143 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3144 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3146 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3148 /* We need to break a 64bit float in two 32 bit halves and
3149 spread them across a floating-point register pair. */
3150 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
3151 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
3152 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3153 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3155 hi
->reg_offset
= lo
->reg_offset
;
3156 lo
->reg
= FP0_REGNUM
+ 0;
3157 hi
->reg
= FP0_REGNUM
+ 1;
3163 /* The floating point value fits in a single floating-point
3165 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3166 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3169 lo
->reg
= FP0_REGNUM
;
3180 /* Locate a result possibly spread across two registers. */
3182 lo
->reg
= regnum
+ 0;
3183 hi
->reg
= regnum
+ 1;
3184 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3185 && len
< MIPS_SAVED_REGSIZE
)
3187 /* "un-left-justify" the value in the low register */
3188 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3193 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3194 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3195 && len
< MIPS_SAVED_REGSIZE
* 2
3196 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3197 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3199 /* "un-left-justify" the value spread across two registers. */
3200 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3201 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3203 hi
->len
= len
- lo
->len
;
3207 /* Only perform a partial copy of the second register. */
3210 if (len
> MIPS_SAVED_REGSIZE
)
3212 lo
->len
= MIPS_SAVED_REGSIZE
;
3213 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3221 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3222 && REGISTER_RAW_SIZE (regnum
) == 8
3223 && MIPS_SAVED_REGSIZE
== 4)
3225 /* Account for the fact that only the least-signficant part
3226 of the register is being used */
3227 lo
->reg_offset
+= 4;
3228 hi
->reg_offset
+= 4;
3231 hi
->buf_offset
= lo
->len
;
3235 /* Given a return value in `regbuf' with a type `valtype', extract and
3236 copy its value into `valbuf'. */
3239 mips_extract_return_value (valtype
, regbuf
, valbuf
)
3240 struct type
*valtype
;
3241 char regbuf
[REGISTER_BYTES
];
3244 struct return_value_word lo
;
3245 struct return_value_word hi
;
3246 return_value_location (valtype
, &lo
, &hi
);
3248 memcpy (valbuf
+ lo
.buf_offset
,
3249 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3253 memcpy (valbuf
+ hi
.buf_offset
,
3254 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3260 int len
= TYPE_LENGTH (valtype
);
3263 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3264 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3265 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3266 && len
<= MIPS_FPU_SINGLE_REGSIZE
)))
3267 regnum
= FP0_REGNUM
;
3269 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3270 { /* "un-left-justify" the value from the register */
3271 if (len
< REGISTER_RAW_SIZE (regnum
))
3272 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3273 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3274 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3275 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3276 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3277 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3279 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
3280 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
3284 /* Given a return value in `valbuf' with a type `valtype', write it's
3285 value into the appropriate register. */
3288 mips_store_return_value (valtype
, valbuf
)
3289 struct type
*valtype
;
3292 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3293 struct return_value_word lo
;
3294 struct return_value_word hi
;
3295 return_value_location (valtype
, &lo
, &hi
);
3297 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3298 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3299 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3301 REGISTER_RAW_SIZE (lo
.reg
));
3305 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3306 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3307 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3309 REGISTER_RAW_SIZE (hi
.reg
));
3315 int len
= TYPE_LENGTH (valtype
);
3316 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3319 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3320 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3321 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3322 && len
<= MIPS_REGSIZE
)))
3323 regnum
= FP0_REGNUM
;
3325 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3326 { /* "left-justify" the value in the register */
3327 if (len
< REGISTER_RAW_SIZE (regnum
))
3328 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3329 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3330 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3331 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3332 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3333 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3335 memcpy (raw_buffer
+ offset
, valbuf
, len
);
3336 REGISTER_CONVERT_FROM_TYPE (regnum
, valtype
, raw_buffer
);
3337 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
,
3338 len
> REGISTER_RAW_SIZE (regnum
) ?
3339 len
: REGISTER_RAW_SIZE (regnum
));
3343 /* Exported procedure: Is PC in the signal trampoline code */
3346 in_sigtramp (pc
, ignore
)
3348 char *ignore
; /* function name */
3350 if (sigtramp_address
== 0)
3352 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3355 /* Root of all "set mips "/"show mips " commands. This will eventually be
3356 used for all MIPS-specific commands. */
3358 static void show_mips_command (char *, int);
3360 show_mips_command (args
, from_tty
)
3364 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3367 static void set_mips_command (char *, int);
3369 set_mips_command (args
, from_tty
)
3373 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3374 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3377 /* Commands to show/set the MIPS FPU type. */
3379 static void show_mipsfpu_command (char *, int);
3381 show_mipsfpu_command (args
, from_tty
)
3387 switch (MIPS_FPU_TYPE
)
3389 case MIPS_FPU_SINGLE
:
3390 fpu
= "single-precision";
3392 case MIPS_FPU_DOUBLE
:
3393 fpu
= "double-precision";
3396 fpu
= "absent (none)";
3399 if (mips_fpu_type_auto
)
3400 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3403 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3408 static void set_mipsfpu_command (char *, int);
3410 set_mipsfpu_command (args
, from_tty
)
3414 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3415 show_mipsfpu_command (args
, from_tty
);
3418 static void set_mipsfpu_single_command (char *, int);
3420 set_mipsfpu_single_command (args
, from_tty
)
3424 mips_fpu_type
= MIPS_FPU_SINGLE
;
3425 mips_fpu_type_auto
= 0;
3428 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3432 static void set_mipsfpu_double_command (char *, int);
3434 set_mipsfpu_double_command (args
, from_tty
)
3438 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3439 mips_fpu_type_auto
= 0;
3442 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3446 static void set_mipsfpu_none_command (char *, int);
3448 set_mipsfpu_none_command (args
, from_tty
)
3452 mips_fpu_type
= MIPS_FPU_NONE
;
3453 mips_fpu_type_auto
= 0;
3456 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3460 static void set_mipsfpu_auto_command (char *, int);
3462 set_mipsfpu_auto_command (args
, from_tty
)
3466 mips_fpu_type_auto
= 1;
3469 /* Command to set the processor type. */
3472 mips_set_processor_type_command (args
, from_tty
)
3478 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3480 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3481 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3482 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3484 /* Restore the value. */
3485 tmp_mips_processor_type
= strsave (mips_processor_type
);
3490 if (!mips_set_processor_type (tmp_mips_processor_type
))
3492 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3493 /* Restore its value. */
3494 tmp_mips_processor_type
= strsave (mips_processor_type
);
3499 mips_show_processor_type_command (args
, from_tty
)
3505 /* Modify the actual processor type. */
3508 mips_set_processor_type (str
)
3516 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3518 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3520 mips_processor_type
= str
;
3521 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3523 /* FIXME tweak fpu flag too */
3530 /* Attempt to identify the particular processor model by reading the
3534 mips_read_processor_type ()
3538 prid
= read_register (PRID_REGNUM
);
3540 if ((prid
& ~0xf) == 0x700)
3541 return savestring ("r3041", strlen ("r3041"));
3546 /* Just like reinit_frame_cache, but with the right arguments to be
3547 callable as an sfunc. */
3550 reinit_frame_cache_sfunc (args
, from_tty
, c
)
3553 struct cmd_list_element
*c
;
3555 reinit_frame_cache ();
3559 gdb_print_insn_mips (memaddr
, info
)
3561 disassemble_info
*info
;
3563 mips_extra_func_info_t proc_desc
;
3565 /* Search for the function containing this address. Set the low bit
3566 of the address when searching, in case we were given an even address
3567 that is the start of a 16-bit function. If we didn't do this,
3568 the search would fail because the symbol table says the function
3569 starts at an odd address, i.e. 1 byte past the given address. */
3570 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3571 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3573 /* Make an attempt to determine if this is a 16-bit function. If
3574 the procedure descriptor exists and the address therein is odd,
3575 it's definitely a 16-bit function. Otherwise, we have to just
3576 guess that if the address passed in is odd, it's 16-bits. */
3578 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
3579 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3581 info
->mach
= pc_is_mips16 (memaddr
) ?
3582 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3584 /* Round down the instruction address to the appropriate boundary. */
3585 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
3587 /* Call the appropriate disassembler based on the target endian-ness. */
3588 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3589 return print_insn_big_mips (memaddr
, info
);
3591 return print_insn_little_mips (memaddr
, info
);
3594 /* Old-style breakpoint macros.
3595 The IDT board uses an unusual breakpoint value, and sometimes gets
3596 confused when it sees the usual MIPS breakpoint instruction. */
3598 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3599 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3600 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3601 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3602 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3603 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3604 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3605 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3607 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3608 counter value to determine whether a 16- or 32-bit breakpoint should be
3609 used. It returns a pointer to a string of bytes that encode a breakpoint
3610 instruction, stores the length of the string to *lenptr, and adjusts pc
3611 (if necessary) to point to the actual memory location where the
3612 breakpoint should be inserted. */
3615 mips_breakpoint_from_pc (pcptr
, lenptr
)
3619 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3621 if (pc_is_mips16 (*pcptr
))
3623 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3624 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3625 *lenptr
= sizeof (mips16_big_breakpoint
);
3626 return mips16_big_breakpoint
;
3630 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3631 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3632 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3634 *lenptr
= sizeof (big_breakpoint
);
3636 if (strcmp (target_shortname
, "mips") == 0)
3637 return idt_big_breakpoint
;
3638 else if (strcmp (target_shortname
, "ddb") == 0
3639 || strcmp (target_shortname
, "pmon") == 0
3640 || strcmp (target_shortname
, "lsi") == 0)
3641 return pmon_big_breakpoint
;
3643 return big_breakpoint
;
3648 if (pc_is_mips16 (*pcptr
))
3650 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3651 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3652 *lenptr
= sizeof (mips16_little_breakpoint
);
3653 return mips16_little_breakpoint
;
3657 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3658 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3659 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3661 *lenptr
= sizeof (little_breakpoint
);
3663 if (strcmp (target_shortname
, "mips") == 0)
3664 return idt_little_breakpoint
;
3665 else if (strcmp (target_shortname
, "ddb") == 0
3666 || strcmp (target_shortname
, "pmon") == 0
3667 || strcmp (target_shortname
, "lsi") == 0)
3668 return pmon_little_breakpoint
;
3670 return little_breakpoint
;
3675 /* If PC is in a mips16 call or return stub, return the address of the target
3676 PC, which is either the callee or the caller. There are several
3677 cases which must be handled:
3679 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3680 target PC is in $31 ($ra).
3681 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3682 and the target PC is in $2.
3683 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3684 before the jal instruction, this is effectively a call stub
3685 and the the target PC is in $2. Otherwise this is effectively
3686 a return stub and the target PC is in $18.
3688 See the source code for the stubs in gcc/config/mips/mips16.S for
3691 This function implements the SKIP_TRAMPOLINE_CODE macro.
3699 CORE_ADDR start_addr
;
3701 /* Find the starting address and name of the function containing the PC. */
3702 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3705 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3706 target PC is in $31 ($ra). */
3707 if (strcmp (name
, "__mips16_ret_sf") == 0
3708 || strcmp (name
, "__mips16_ret_df") == 0)
3709 return read_register (RA_REGNUM
);
3711 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3713 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3714 and the target PC is in $2. */
3715 if (name
[19] >= '0' && name
[19] <= '9')
3716 return read_register (2);
3718 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3719 before the jal instruction, this is effectively a call stub
3720 and the the target PC is in $2. Otherwise this is effectively
3721 a return stub and the target PC is in $18. */
3722 else if (name
[19] == 's' || name
[19] == 'd')
3724 if (pc
== start_addr
)
3726 /* Check if the target of the stub is a compiler-generated
3727 stub. Such a stub for a function bar might have a name
3728 like __fn_stub_bar, and might look like this:
3733 la $1,bar (becomes a lui/addiu pair)
3735 So scan down to the lui/addi and extract the target
3736 address from those two instructions. */
3738 CORE_ADDR target_pc
= read_register (2);
3742 /* See if the name of the target function is __fn_stub_*. */
3743 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3745 if (strncmp (name
, "__fn_stub_", 10) != 0
3746 && strcmp (name
, "etext") != 0
3747 && strcmp (name
, "_etext") != 0)
3750 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3751 The limit on the search is arbitrarily set to 20
3752 instructions. FIXME. */
3753 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3755 inst
= mips_fetch_instruction (target_pc
);
3756 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3757 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3758 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3759 return pc
| (inst
& 0xffff); /* low word */
3762 /* Couldn't find the lui/addui pair, so return stub address. */
3766 /* This is the 'return' part of a call stub. The return
3767 address is in $r18. */
3768 return read_register (18);
3771 return 0; /* not a stub */
3775 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3776 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3779 mips_in_call_stub (pc
, name
)
3783 CORE_ADDR start_addr
;
3785 /* Find the starting address of the function containing the PC. If the
3786 caller didn't give us a name, look it up at the same time. */
3787 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3790 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3792 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3793 if (name
[19] >= '0' && name
[19] <= '9')
3795 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3796 before the jal instruction, this is effectively a call stub. */
3797 else if (name
[19] == 's' || name
[19] == 'd')
3798 return pc
== start_addr
;
3801 return 0; /* not a stub */
3805 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3806 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3809 mips_in_return_stub (pc
, name
)
3813 CORE_ADDR start_addr
;
3815 /* Find the starting address of the function containing the PC. */
3816 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3819 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3820 if (strcmp (name
, "__mips16_ret_sf") == 0
3821 || strcmp (name
, "__mips16_ret_df") == 0)
3824 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3825 i.e. after the jal instruction, this is effectively a return stub. */
3826 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3827 && (name
[19] == 's' || name
[19] == 'd')
3828 && pc
!= start_addr
)
3831 return 0; /* not a stub */
3835 /* Return non-zero if the PC is in a library helper function that should
3836 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3839 mips_ignore_helper (pc
)
3844 /* Find the starting address and name of the function containing the PC. */
3845 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3848 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3849 that we want to ignore. */
3850 return (strcmp (name
, "__mips16_ret_sf") == 0
3851 || strcmp (name
, "__mips16_ret_df") == 0);
3855 /* Return a location where we can set a breakpoint that will be hit
3856 when an inferior function call returns. This is normally the
3857 program's entry point. Executables that don't have an entry
3858 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3859 whose address is the location where the breakpoint should be placed. */
3862 mips_call_dummy_address ()
3864 struct minimal_symbol
*sym
;
3866 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3868 return SYMBOL_VALUE_ADDRESS (sym
);
3870 return entry_point_address ();
3874 /* If the current gcc for for this target does not produce correct debugging
3875 information for float parameters, both prototyped and unprototyped, then
3876 define this macro. This forces gdb to always assume that floats are
3877 passed as doubles and then converted in the callee.
3879 For the mips chip, it appears that the debug info marks the parameters as
3880 floats regardless of whether the function is prototyped, but the actual
3881 values are passed as doubles for the non-prototyped case and floats for
3882 the prototyped case. Thus we choose to make the non-prototyped case work
3883 for C and break the prototyped case, since the non-prototyped case is
3884 probably much more common. (FIXME). */
3887 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
3889 return current_language
->la_language
== language_c
;
3892 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
3893 the register stored on the stack (32) is different to its real raw
3894 size (64). The below ensures that registers are fetched from the
3895 stack using their ABI size and then stored into the RAW_BUFFER
3896 using their raw size.
3898 The alternative to adding this function would be to add an ABI
3899 macro - REGISTER_STACK_SIZE(). */
3902 mips_get_saved_register (raw_buffer
, optimized
, addrp
, frame
, regnum
, lval
)
3906 struct frame_info
*frame
;
3908 enum lval_type
*lval
;
3912 if (!target_has_registers
)
3913 error ("No registers.");
3915 /* Normal systems don't optimize out things with register numbers. */
3916 if (optimized
!= NULL
)
3918 addr
= find_saved_register (frame
, regnum
);
3922 *lval
= lval_memory
;
3923 if (regnum
== SP_REGNUM
)
3925 if (raw_buffer
!= NULL
)
3927 /* Put it back in target format. */
3928 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
3935 if (raw_buffer
!= NULL
)
3939 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
3941 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
3943 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
3944 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
3950 *lval
= lval_register
;
3951 addr
= REGISTER_BYTE (regnum
);
3952 if (raw_buffer
!= NULL
)
3953 read_register_gen (regnum
, raw_buffer
);
3959 /* Immediately after a function call, return the saved pc.
3960 Can't always go through the frames for this because on some machines
3961 the new frame is not set up until the new function executes
3962 some instructions. */
3965 mips_saved_pc_after_call (struct frame_info
*frame
)
3968 return read_register (RA_REGNUM
);
3972 static gdbarch_init_ftype mips_gdbarch_init
;
3973 static struct gdbarch
*
3974 mips_gdbarch_init (info
, arches
)
3975 struct gdbarch_info info
;
3976 struct gdbarch_list
*arches
;
3978 static LONGEST mips_call_dummy_words
[] =
3980 struct gdbarch
*gdbarch
;
3981 struct gdbarch_tdep
*tdep
;
3984 int ef_mips_bitptrs
;
3989 enum mips_abi mips_abi
;
3991 /* Extract the elf_flags if available */
3992 if (info
.abfd
!= NULL
3993 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
3994 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3998 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
3999 switch ((elf_flags
& EF_MIPS_ABI
))
4001 case E_MIPS_ABI_O32
:
4002 mips_abi
= MIPS_ABI_O32
;
4004 case E_MIPS_ABI_O64
:
4005 mips_abi
= MIPS_ABI_O64
;
4007 case E_MIPS_ABI_EABI32
:
4008 mips_abi
= MIPS_ABI_EABI32
;
4010 case E_MIPS_ABI_EABI64
:
4011 mips_abi
= MIPS_ABI_EABI64
;
4014 mips_abi
= MIPS_ABI_UNKNOWN
;
4017 /* Try the architecture for any hint of the corect ABI */
4018 if (mips_abi
== MIPS_ABI_UNKNOWN
4019 && info
.bfd_arch_info
!= NULL
4020 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4022 switch (info
.bfd_arch_info
->mach
)
4024 case bfd_mach_mips3900
:
4025 mips_abi
= MIPS_ABI_EABI32
;
4027 case bfd_mach_mips4100
:
4028 case bfd_mach_mips5000
:
4029 mips_abi
= MIPS_ABI_EABI64
;
4033 #ifdef MIPS_DEFAULT_ABI
4034 if (mips_abi
== MIPS_ABI_UNKNOWN
)
4035 mips_abi
= MIPS_DEFAULT_ABI
;
4040 fprintf_unfiltered (gdb_stdlog
,
4041 "mips_gdbarch_init: elf_flags = 0x%08x\n",
4044 fprintf_unfiltered (gdb_stdlog
,
4045 "mips_gdbarch_init: ef_mips_arch = %d\n",
4049 fprintf_unfiltered (gdb_stdlog
,
4050 "mips_gdbarch_init: ef_mips_bitptrs = %d\n",
4053 fprintf_unfiltered (gdb_stdlog
,
4054 "mips_gdbarch_init: mips_abi = %d\n",
4058 /* try to find a pre-existing architecture */
4059 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4061 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4063 /* MIPS needs to be pedantic about which ABI the object is
4065 if (gdbarch_tdep (current_gdbarch
)->elf_flags
!= elf_flags
)
4067 if (gdbarch_tdep (current_gdbarch
)->mips_abi
!= mips_abi
)
4069 return arches
->gdbarch
;
4072 /* Need a new architecture. Fill in a target specific vector. */
4073 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4074 gdbarch
= gdbarch_alloc (&info
, tdep
);
4075 tdep
->elf_flags
= elf_flags
;
4077 /* Initially set everything according to the ABI. */
4078 set_gdbarch_short_bit (gdbarch
, 16);
4079 set_gdbarch_int_bit (gdbarch
, 32);
4080 set_gdbarch_float_bit (gdbarch
, 32);
4081 set_gdbarch_double_bit (gdbarch
, 64);
4082 set_gdbarch_long_double_bit (gdbarch
, 64);
4083 tdep
->mips_abi
= mips_abi
;
4087 tdep
->mips_default_saved_regsize
= 4;
4088 tdep
->mips_default_stack_argsize
= 4;
4089 tdep
->mips_fp_register_double
= 0;
4090 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 7;
4091 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 15;
4092 tdep
->mips_regs_have_home_p
= 1;
4093 tdep
->gdb_target_is_mips64
= 0;
4094 tdep
->default_mask_address_p
= 0;
4095 set_gdbarch_long_bit (gdbarch
, 32);
4096 set_gdbarch_ptr_bit (gdbarch
, 32);
4097 set_gdbarch_long_long_bit (gdbarch
, 64);
4100 tdep
->mips_default_saved_regsize
= 8;
4101 tdep
->mips_default_stack_argsize
= 8;
4102 tdep
->mips_fp_register_double
= 1;
4103 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 7;
4104 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 15;
4105 tdep
->mips_regs_have_home_p
= 1;
4106 tdep
->gdb_target_is_mips64
= 1;
4107 tdep
->default_mask_address_p
= 0;
4108 set_gdbarch_long_bit (gdbarch
, 32);
4109 set_gdbarch_ptr_bit (gdbarch
, 32);
4110 set_gdbarch_long_long_bit (gdbarch
, 64);
4112 case MIPS_ABI_EABI32
:
4113 tdep
->mips_default_saved_regsize
= 4;
4114 tdep
->mips_default_stack_argsize
= 4;
4115 tdep
->mips_fp_register_double
= 0;
4116 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
4117 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
4118 tdep
->mips_regs_have_home_p
= 0;
4119 tdep
->gdb_target_is_mips64
= 0;
4120 tdep
->default_mask_address_p
= 0;
4121 set_gdbarch_long_bit (gdbarch
, 32);
4122 set_gdbarch_ptr_bit (gdbarch
, 32);
4123 set_gdbarch_long_long_bit (gdbarch
, 64);
4125 case MIPS_ABI_EABI64
:
4126 tdep
->mips_default_saved_regsize
= 8;
4127 tdep
->mips_default_stack_argsize
= 8;
4128 tdep
->mips_fp_register_double
= 1;
4129 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
4130 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
4131 tdep
->mips_regs_have_home_p
= 0;
4132 tdep
->gdb_target_is_mips64
= 1;
4133 tdep
->default_mask_address_p
= 0;
4134 set_gdbarch_long_bit (gdbarch
, 64);
4135 set_gdbarch_ptr_bit (gdbarch
, 64);
4136 set_gdbarch_long_long_bit (gdbarch
, 64);
4139 tdep
->mips_default_saved_regsize
= 4;
4140 tdep
->mips_default_stack_argsize
= 8;
4141 tdep
->mips_fp_register_double
= 1;
4142 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
4143 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
4144 tdep
->mips_regs_have_home_p
= 0;
4145 tdep
->gdb_target_is_mips64
= 0;
4146 tdep
->default_mask_address_p
= 0;
4147 set_gdbarch_long_bit (gdbarch
, 32);
4148 set_gdbarch_ptr_bit (gdbarch
, 32);
4149 set_gdbarch_long_long_bit (gdbarch
, 64);
4152 tdep
->mips_default_saved_regsize
= MIPS_REGSIZE
;
4153 tdep
->mips_default_stack_argsize
= MIPS_REGSIZE
;
4154 tdep
->mips_fp_register_double
= (REGISTER_VIRTUAL_SIZE (FP0_REGNUM
) == 8);
4155 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
4156 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
4157 tdep
->mips_regs_have_home_p
= 1;
4158 tdep
->gdb_target_is_mips64
= 0;
4159 tdep
->default_mask_address_p
= 0;
4160 set_gdbarch_long_bit (gdbarch
, 32);
4161 set_gdbarch_ptr_bit (gdbarch
, 32);
4162 set_gdbarch_long_long_bit (gdbarch
, 64);
4166 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4167 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4170 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4171 flag in object files because to do so would make it impossible to
4172 link with libraries compiled without "-gp32". This is
4173 unnecessarily restrictive.
4175 We could solve this problem by adding "-gp32" multilibs to gcc,
4176 but to set this flag before gcc is built with such multilibs will
4177 break too many systems.''
4179 But even more unhelpfully, the default linker output target for
4180 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4181 for 64-bit programs - you need to change the ABI to change this,
4182 and not all gcc targets support that currently. Therefore using
4183 this flag to detect 32-bit mode would do the wrong thing given
4184 the current gcc - it would make GDB treat these 64-bit programs
4185 as 32-bit programs by default. */
4188 /* determine the ISA */
4189 switch (elf_flags
& EF_MIPS_ARCH
)
4209 /* determine the size of a pointer */
4210 if ((elf_flags
& EF_MIPS_32BITPTRS
))
4212 ef_mips_bitptrs
= 32;
4214 else if ((elf_flags
& EF_MIPS_64BITPTRS
))
4216 ef_mips_bitptrs
= 64;
4220 ef_mips_bitptrs
= 0;
4224 /* enable/disable the MIPS FPU */
4225 if (!mips_fpu_type_auto
)
4226 tdep
->mips_fpu_type
= mips_fpu_type
;
4227 else if (info
.bfd_arch_info
!= NULL
4228 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4229 switch (info
.bfd_arch_info
->mach
)
4231 case bfd_mach_mips3900
:
4232 case bfd_mach_mips4100
:
4233 case bfd_mach_mips4111
:
4234 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
4236 case bfd_mach_mips4650
:
4237 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
4240 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4244 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4246 /* MIPS version of register names. NOTE: At present the MIPS
4247 register name management is part way between the old -
4248 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4249 Further work on it is required. */
4250 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4251 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
4252 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4253 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4254 set_gdbarch_write_fp (gdbarch
, generic_target_write_fp
);
4255 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4256 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4258 /* Initialize a frame */
4259 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
4261 /* MIPS version of CALL_DUMMY */
4263 set_gdbarch_call_dummy_p (gdbarch
, 1);
4264 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4265 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
4266 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4267 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4268 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4269 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4270 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4271 set_gdbarch_call_dummy_length (gdbarch
, 0);
4272 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4273 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4274 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4275 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4276 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4277 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4278 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4280 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4281 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
4283 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4284 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
4285 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4286 set_gdbarch_ieee_float (gdbarch
, 1);
4288 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
4289 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
4295 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4297 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4300 fprintf_unfiltered (file
,
4301 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4303 fprintf_unfiltered (file
,
4304 "mips_dump_tdep: tdep->mips_abi = %d\n",
4306 fprintf_unfiltered (file
,
4307 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4308 mips_mask_address_p (),
4309 tdep
->default_mask_address_p
);
4311 fprintf_unfiltered (file
,
4312 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4313 FP_REGISTER_DOUBLE
);
4314 fprintf_unfiltered (file
,
4315 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4316 MIPS_DEFAULT_FPU_TYPE
,
4317 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4318 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4319 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4321 fprintf_unfiltered (file
,
4322 "mips_dump_tdep: MIPS_EABI = %d\n",
4324 fprintf_unfiltered (file
,
4325 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d\n",
4326 MIPS_LAST_FP_ARG_REGNUM
);
4327 fprintf_unfiltered (file
,
4328 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4330 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4331 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4332 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4334 fprintf_unfiltered (file
,
4335 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4336 MIPS_DEFAULT_SAVED_REGSIZE
);
4337 fprintf_unfiltered (file
,
4338 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4339 FP_REGISTER_DOUBLE
);
4340 fprintf_unfiltered (file
,
4341 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4342 MIPS_REGS_HAVE_HOME_P
);
4343 fprintf_unfiltered (file
,
4344 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4345 MIPS_DEFAULT_STACK_ARGSIZE
);
4346 fprintf_unfiltered (file
,
4347 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4348 MIPS_STACK_ARGSIZE
);
4349 fprintf_unfiltered (file
,
4350 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4352 fprintf_unfiltered (file
,
4353 "mips_dump_tdep: A0_REGNUM = %d\n",
4355 fprintf_unfiltered (file
,
4356 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4357 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
4358 fprintf_unfiltered (file
,
4359 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4360 XSTRING (ATTACH_DETACH
));
4361 fprintf_unfiltered (file
,
4362 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4364 fprintf_unfiltered (file
,
4365 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4366 fprintf_unfiltered (file
,
4367 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4369 fprintf_unfiltered (file
,
4370 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4372 fprintf_unfiltered (file
,
4373 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4375 fprintf_unfiltered (file
,
4376 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4377 XSTRING (DO_REGISTERS_INFO
));
4378 fprintf_unfiltered (file
,
4379 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4380 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
4381 fprintf_unfiltered (file
,
4382 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4383 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
4384 fprintf_unfiltered (file
,
4385 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4386 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
4387 fprintf_unfiltered (file
,
4388 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4390 fprintf_unfiltered (file
,
4391 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4393 fprintf_unfiltered (file
,
4394 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4395 FIRST_EMBED_REGNUM
);
4396 fprintf_unfiltered (file
,
4397 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4399 fprintf_unfiltered (file
,
4400 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4401 GDB_TARGET_IS_MIPS64
);
4402 fprintf_unfiltered (file
,
4403 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4404 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
4405 fprintf_unfiltered (file
,
4406 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4407 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
4408 fprintf_unfiltered (file
,
4409 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4411 fprintf_unfiltered (file
,
4412 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4413 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
4414 fprintf_unfiltered (file
,
4415 "mips_dump_tdep: HI_REGNUM = %d\n",
4417 fprintf_unfiltered (file
,
4418 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4419 fprintf_unfiltered (file
,
4420 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4421 fprintf_unfiltered (file
,
4422 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4423 XSTRING (IGNORE_HELPER_CALL (PC
)));
4424 fprintf_unfiltered (file
,
4425 "mips_dump_tdep: INIT_FRAME_PC # %s\n",
4426 XSTRING (INIT_FRAME_PC (FROMLEAF
, PREV
)));
4427 fprintf_unfiltered (file
,
4428 "mips_dump_tdep: INIT_FRAME_PC_FIRST # %s\n",
4429 XSTRING (INIT_FRAME_PC_FIRST (FROMLEAF
, PREV
)));
4430 fprintf_unfiltered (file
,
4431 "mips_dump_tdep: IN_SIGTRAMP # %s\n",
4432 XSTRING (IN_SIGTRAMP (PC
, NAME
)));
4433 fprintf_unfiltered (file
,
4434 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4435 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
4436 fprintf_unfiltered (file
,
4437 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4438 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
4439 fprintf_unfiltered (file
,
4440 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4441 fprintf_unfiltered (file
,
4442 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4444 fprintf_unfiltered (file
,
4445 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4446 fprintf_unfiltered (file
,
4447 "mips_dump_tdep: LO_REGNUM = %d\n",
4449 #ifdef MACHINE_CPROC_FP_OFFSET
4450 fprintf_unfiltered (file
,
4451 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4452 MACHINE_CPROC_FP_OFFSET
);
4454 #ifdef MACHINE_CPROC_PC_OFFSET
4455 fprintf_unfiltered (file
,
4456 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4457 MACHINE_CPROC_PC_OFFSET
);
4459 #ifdef MACHINE_CPROC_SP_OFFSET
4460 fprintf_unfiltered (file
,
4461 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4462 MACHINE_CPROC_SP_OFFSET
);
4464 fprintf_unfiltered (file
,
4465 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4466 fprintf_unfiltered (file
,
4467 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4468 fprintf_unfiltered (file
,
4469 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4471 fprintf_unfiltered (file
,
4472 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4473 fprintf_unfiltered (file
,
4474 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4475 fprintf_unfiltered (file
,
4476 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4477 fprintf_unfiltered (file
,
4478 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4480 fprintf_unfiltered (file
,
4481 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d\n",
4482 MIPS_LAST_ARG_REGNUM
);
4483 fprintf_unfiltered (file
,
4484 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4486 fprintf_unfiltered (file
,
4487 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4488 fprintf_unfiltered (file
,
4489 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4490 MIPS_SAVED_REGSIZE
);
4491 fprintf_unfiltered (file
,
4492 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4493 fprintf_unfiltered (file
,
4494 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4495 XSTRING (MSYMBOL_SIZE (MSYM
)));
4496 fprintf_unfiltered (file
,
4497 "mips_dump_tdep: OP_LDFPR = used?\n");
4498 fprintf_unfiltered (file
,
4499 "mips_dump_tdep: OP_LDGPR = used?\n");
4500 fprintf_unfiltered (file
,
4501 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4502 fprintf_unfiltered (file
,
4503 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4504 fprintf_unfiltered (file
,
4505 "mips_dump_tdep: PRID_REGNUM = %d\n",
4507 fprintf_unfiltered (file
,
4508 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4509 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
4510 fprintf_unfiltered (file
,
4511 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4512 fprintf_unfiltered (file
,
4513 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4514 fprintf_unfiltered (file
,
4515 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4516 fprintf_unfiltered (file
,
4517 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4518 fprintf_unfiltered (file
,
4519 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4520 fprintf_unfiltered (file
,
4521 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4522 fprintf_unfiltered (file
,
4523 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4524 fprintf_unfiltered (file
,
4525 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4526 fprintf_unfiltered (file
,
4527 "mips_dump_tdep: PROC_PC_REG = function?\n");
4528 fprintf_unfiltered (file
,
4529 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4530 fprintf_unfiltered (file
,
4531 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4532 fprintf_unfiltered (file
,
4533 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4534 fprintf_unfiltered (file
,
4535 "mips_dump_tdep: PS_REGNUM = %d\n",
4537 fprintf_unfiltered (file
,
4538 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4540 fprintf_unfiltered (file
,
4541 "mips_dump_tdep: RA_REGNUM = %d\n",
4543 fprintf_unfiltered (file
,
4544 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4545 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4546 fprintf_unfiltered (file
,
4547 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4548 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4549 fprintf_unfiltered (file
,
4550 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4551 fprintf_unfiltered (file
,
4552 "mips_dump_tdep: ROUND_DOWN = function?\n");
4553 fprintf_unfiltered (file
,
4554 "mips_dump_tdep: ROUND_UP = function?\n");
4556 fprintf_unfiltered (file
,
4557 "mips_dump_tdep: SAVED_BYTES = %d\n",
4561 fprintf_unfiltered (file
,
4562 "mips_dump_tdep: SAVED_FP = %d\n",
4566 fprintf_unfiltered (file
,
4567 "mips_dump_tdep: SAVED_PC = %d\n",
4570 fprintf_unfiltered (file
,
4571 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
4572 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
4573 fprintf_unfiltered (file
,
4574 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
4575 fprintf_unfiltered (file
,
4576 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
4578 fprintf_unfiltered (file
,
4579 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
4580 SIGFRAME_FPREGSAVE_OFF
);
4581 fprintf_unfiltered (file
,
4582 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
4584 fprintf_unfiltered (file
,
4585 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
4586 SIGFRAME_REGSAVE_OFF
);
4587 fprintf_unfiltered (file
,
4588 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
4590 fprintf_unfiltered (file
,
4591 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
4592 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
4593 fprintf_unfiltered (file
,
4594 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
4595 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
4596 fprintf_unfiltered (file
,
4597 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n",
4598 SOFTWARE_SINGLE_STEP_P
);
4599 fprintf_unfiltered (file
,
4600 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n",
4601 SOFTWARE_SINGLE_STEP_P
);
4602 fprintf_unfiltered (file
,
4603 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
4604 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
4605 #ifdef STACK_END_ADDR
4606 fprintf_unfiltered (file
,
4607 "mips_dump_tdep: STACK_END_ADDR = %d\n",
4610 fprintf_unfiltered (file
,
4611 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
4612 XSTRING (STEP_SKIPS_DELAY (PC
)));
4613 fprintf_unfiltered (file
,
4614 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
4615 STEP_SKIPS_DELAY_P
);
4616 fprintf_unfiltered (file
,
4617 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
4618 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
4619 fprintf_unfiltered (file
,
4620 "mips_dump_tdep: T9_REGNUM = %d\n",
4622 fprintf_unfiltered (file
,
4623 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
4624 fprintf_unfiltered (file
,
4625 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
4626 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
4627 fprintf_unfiltered (file
,
4628 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
4629 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
4630 fprintf_unfiltered (file
,
4631 "mips_dump_tdep: TARGET_MIPS = used?\n");
4632 fprintf_unfiltered (file
,
4633 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
4634 XSTRING (TM_PRINT_INSN_MACH
));
4636 fprintf_unfiltered (file
,
4637 "mips_dump_tdep: TRACE_CLEAR # %s\n",
4638 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
4641 fprintf_unfiltered (file
,
4642 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
4645 #ifdef TRACE_FLAVOR_SIZE
4646 fprintf_unfiltered (file
,
4647 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
4651 fprintf_unfiltered (file
,
4652 "mips_dump_tdep: TRACE_SET # %s\n",
4653 XSTRING (TRACE_SET (X
,STATE
)));
4655 fprintf_unfiltered (file
,
4656 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
4657 #ifdef UNUSED_REGNUM
4658 fprintf_unfiltered (file
,
4659 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
4662 fprintf_unfiltered (file
,
4663 "mips_dump_tdep: V0_REGNUM = %d\n",
4665 fprintf_unfiltered (file
,
4666 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
4667 (long) VM_MIN_ADDRESS
);
4669 fprintf_unfiltered (file
,
4670 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
4673 fprintf_unfiltered (file
,
4674 "mips_dump_tdep: ZERO_REGNUM = %d\n",
4676 fprintf_unfiltered (file
,
4677 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
4682 _initialize_mips_tdep ()
4684 static struct cmd_list_element
*mipsfpulist
= NULL
;
4685 struct cmd_list_element
*c
;
4687 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
4688 if (!tm_print_insn
) /* Someone may have already set it */
4689 tm_print_insn
= gdb_print_insn_mips
;
4691 /* Add root prefix command for all "set mips"/"show mips" commands */
4692 add_prefix_cmd ("mips", no_class
, set_mips_command
,
4693 "Various MIPS specific commands.",
4694 &setmipscmdlist
, "set mips ", 0, &setlist
);
4696 add_prefix_cmd ("mips", no_class
, show_mips_command
,
4697 "Various MIPS specific commands.",
4698 &showmipscmdlist
, "show mips ", 0, &showlist
);
4700 /* Allow the user to override the saved register size. */
4701 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
4704 &mips_saved_regsize_string
, "\
4705 Set size of general purpose registers saved on the stack.\n\
4706 This option can be set to one of:\n\
4707 32 - Force GDB to treat saved GP registers as 32-bit\n\
4708 64 - Force GDB to treat saved GP registers as 64-bit\n\
4709 auto - Allow GDB to use the target's default setting or autodetect the\n\
4710 saved GP register size from information contained in the executable.\n\
4715 /* Allow the user to override the argument stack size. */
4716 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
4719 &mips_stack_argsize_string
, "\
4720 Set the amount of stack space reserved for each argument.\n\
4721 This option can be set to one of:\n\
4722 32 - Force GDB to allocate 32-bit chunks per argument\n\
4723 64 - Force GDB to allocate 64-bit chunks per argument\n\
4724 auto - Allow GDB to determine the correct setting from the current\n\
4725 target and executable (default)",
4729 /* Let the user turn off floating point and set the fence post for
4730 heuristic_proc_start. */
4732 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
4733 "Set use of MIPS floating-point coprocessor.",
4734 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
4735 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
4736 "Select single-precision MIPS floating-point coprocessor.",
4738 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
4739 "Select double-precision MIPS floating-point coprocessor .",
4741 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
4742 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
4743 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
4744 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
4745 "Select no MIPS floating-point coprocessor.",
4747 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
4748 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
4749 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
4750 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
4751 "Select MIPS floating-point coprocessor automatically.",
4753 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
4754 "Show current use of MIPS floating-point coprocessor target.",
4758 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
4759 (char *) &tmp_mips_processor_type
,
4760 "Set the type of MIPS processor in use.\n\
4761 Set this to be able to access processor-type-specific registers.\n\
4764 c
->function
.cfunc
= mips_set_processor_type_command
;
4765 c
= add_show_from_set (c
, &showlist
);
4766 c
->function
.cfunc
= mips_show_processor_type_command
;
4768 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
4769 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
4772 /* We really would like to have both "0" and "unlimited" work, but
4773 command.c doesn't deal with that. So make it a var_zinteger
4774 because the user can always use "999999" or some such for unlimited. */
4775 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
4776 (char *) &heuristic_fence_post
,
4778 Set the distance searched for the start of a function.\n\
4779 If you are debugging a stripped executable, GDB needs to search through the\n\
4780 program for the start of a function. This command sets the distance of the\n\
4781 search. The only need to set it is when debugging a stripped executable.",
4783 /* We need to throw away the frame cache when we set this, since it
4784 might change our ability to get backtraces. */
4785 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
4786 add_show_from_set (c
, &showlist
);
4788 /* Allow the user to control whether the upper bits of 64-bit
4789 addresses should be zeroed. */
4790 c
= add_set_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
,
4791 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
4792 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\
4793 the correct value.\n",
4795 add_cmd ("mask-address", no_class
, show_mask_address
,
4796 "Show current mask-address value", &showmipscmdlist
);
4798 /* Allow the user to control the size of 32 bit registers within the
4799 raw remote packet. */
4800 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
4803 (char *)&mips64_transfers_32bit_regs_p
, "\
4804 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
4805 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
4806 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
4807 64 bits for others. Use \"off\" to disable compatibility mode",
4811 /* Debug this files internals. */
4812 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
4813 &mips_debug
, "Set mips debugging.\n\
4814 When non-zero, mips specific debugging is enabled.", &setdebuglist
),