1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 /* A useful bit in the CP0 status register (PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE
= 4,
72 MIPS_FPU_DOUBLE_REGSIZE
= 8
76 static const char *mips_abi_string
;
78 static const char *mips_abi_strings
[] = {
89 struct frame_extra_info
91 mips_extra_func_info_t proc_desc
;
95 /* Various MIPS ISA options (related to stack analysis) can be
96 overridden dynamically. Establish an enum/array for managing
99 static const char size_auto
[] = "auto";
100 static const char size_32
[] = "32";
101 static const char size_64
[] = "64";
103 static const char *size_enums
[] = {
110 /* Some MIPS boards don't support floating point while others only
111 support single-precision floating-point operations. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int default_mask_address_p
;
141 /* Is the target using 64-bit raw integer registers but only
142 storing a left-aligned 32-bit value in each? */
143 int mips64_transfers_32bit_regs_p
;
144 /* Indexes for various registers. IRIX and embedded have
145 different values. This contains the "public" fields. Don't
146 add any that do not need to be public. */
147 const struct mips_regnum
*regnum
;
148 /* Register names table for the current register set. */
149 const char **mips_processor_reg_names
;
153 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
159 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
160 They are implemented as a pair of 64bit doubles where the high
161 part holds the result of the operation rounded to double, and
162 the low double holds the difference between the exact result and
163 the rounded result. So "high" + "low" contains the result with
164 added precision. Unfortunately, the floatformat structure used
165 by GDB is not powerful enough to describe this format. As a temporary
166 measure, we define a 128bit floatformat that only uses the high part.
167 We lose a bit of precision but that's probably the best we can do
168 for now with the current infrastructure. */
170 static const struct floatformat floatformat_n32n64_long_double_big
=
172 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
173 floatformat_intbit_no
,
174 "floatformat_ieee_double_big",
175 n32n64_floatformat_always_valid
178 const struct mips_regnum
*
179 mips_regnum (struct gdbarch
*gdbarch
)
181 return gdbarch_tdep (gdbarch
)->regnum
;
185 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
187 return mips_regnum (gdbarch
)->fp0
+ 12;
190 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
191 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
193 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
195 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
197 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
199 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
200 functions to test, set, or clear bit 0 of addresses. */
203 is_mips16_addr (CORE_ADDR addr
)
209 make_mips16_addr (CORE_ADDR addr
)
215 unmake_mips16_addr (CORE_ADDR addr
)
217 return ((addr
) & ~1);
220 /* Return the contents of register REGNUM as a signed integer. */
223 read_signed_register (int regnum
)
225 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
226 deprecated_read_register_gen (regnum
, buf
);
227 return (extract_signed_integer
228 (buf
, register_size (current_gdbarch
, regnum
)));
232 read_signed_register_pid (int regnum
, ptid_t ptid
)
237 if (ptid_equal (ptid
, inferior_ptid
))
238 return read_signed_register (regnum
);
240 save_ptid
= inferior_ptid
;
242 inferior_ptid
= ptid
;
244 retval
= read_signed_register (regnum
);
246 inferior_ptid
= save_ptid
;
251 /* Return the MIPS ABI associated with GDBARCH. */
253 mips_abi (struct gdbarch
*gdbarch
)
255 return gdbarch_tdep (gdbarch
)->mips_abi
;
259 mips_isa_regsize (struct gdbarch
*gdbarch
)
261 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
262 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
265 /* Return the currently configured (or set) saved register size. */
267 static const char *mips_abi_regsize_string
= size_auto
;
270 mips_abi_regsize (struct gdbarch
*gdbarch
)
272 if (mips_abi_regsize_string
== size_auto
)
273 switch (mips_abi (gdbarch
))
275 case MIPS_ABI_EABI32
:
281 case MIPS_ABI_EABI64
:
283 case MIPS_ABI_UNKNOWN
:
286 internal_error (__FILE__
, __LINE__
, "bad switch");
288 else if (mips_abi_regsize_string
== size_64
)
290 else /* if (mips_abi_regsize_string == size_32) */
294 /* Functions for setting and testing a bit in a minimal symbol that
295 marks it as 16-bit function. The MSB of the minimal symbol's
296 "info" field is used for this purpose.
298 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
299 i.e. refers to a 16-bit function, and sets a "special" bit in a
300 minimal symbol to mark it as a 16-bit function
302 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
305 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
307 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
309 MSYMBOL_INFO (msym
) = (char *)
310 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
311 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
316 msymbol_is_special (struct minimal_symbol
*msym
)
318 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
321 /* XFER a value from the big/little/left end of the register.
322 Depending on the size of the value it might occupy the entire
323 register or just part of it. Make an allowance for this, aligning
324 things accordingly. */
327 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
328 enum bfd_endian endian
, bfd_byte
* in
,
329 const bfd_byte
* out
, int buf_offset
)
332 gdb_assert (reg_num
>= NUM_REGS
);
333 /* Need to transfer the left or right part of the register, based on
334 the targets byte order. */
338 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
340 case BFD_ENDIAN_LITTLE
:
343 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
347 internal_error (__FILE__
, __LINE__
, "bad switch");
350 fprintf_unfiltered (gdb_stderr
,
351 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
352 reg_num
, reg_offset
, buf_offset
, length
);
353 if (mips_debug
&& out
!= NULL
)
356 fprintf_unfiltered (gdb_stdlog
, "out ");
357 for (i
= 0; i
< length
; i
++)
358 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
361 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
364 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
366 if (mips_debug
&& in
!= NULL
)
369 fprintf_unfiltered (gdb_stdlog
, "in ");
370 for (i
= 0; i
< length
; i
++)
371 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
374 fprintf_unfiltered (gdb_stdlog
, "\n");
377 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
378 compatiblity mode. A return value of 1 means that we have
379 physical 64-bit registers, but should treat them as 32-bit registers. */
382 mips2_fp_compat (void)
384 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
386 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
391 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
392 in all the places we deal with FP registers. PR gdb/413. */
393 /* Otherwise check the FR bit in the status register - it controls
394 the FP compatiblity mode. If it is clear we are in compatibility
396 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
403 /* The amount of space reserved on the stack for registers. This is
404 different to MIPS_ABI_REGSIZE as it determines the alignment of
405 data allocated after the registers have run out. */
407 static const char *mips_stack_argsize_string
= size_auto
;
410 mips_stack_argsize (struct gdbarch
*gdbarch
)
412 if (mips_stack_argsize_string
== size_auto
)
413 return mips_abi_regsize (gdbarch
);
414 else if (mips_stack_argsize_string
== size_64
)
416 else /* if (mips_stack_argsize_string == size_32) */
420 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
422 struct mips_frame_cache
;
423 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
425 struct mips_frame_cache
*);
426 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
429 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
431 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
433 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
435 static CORE_ADDR
after_prologue (CORE_ADDR pc
);
437 static struct type
*mips_float_register_type (void);
438 static struct type
*mips_double_register_type (void);
440 /* The list of available "set mips " and "show mips " commands */
442 static struct cmd_list_element
*setmipscmdlist
= NULL
;
443 static struct cmd_list_element
*showmipscmdlist
= NULL
;
445 /* Integer registers 0 thru 31 are handled explicitly by
446 mips_register_name(). Processor specific registers 32 and above
447 are listed in the followign tables. */
450 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
454 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
455 "sr", "lo", "hi", "bad", "cause", "pc",
456 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
457 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
458 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
459 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
460 "fsr", "fir", "" /*"fp" */ , "",
461 "", "", "", "", "", "", "", "",
462 "", "", "", "", "", "", "", "",
465 /* Names of IDT R3041 registers. */
467 static const char *mips_r3041_reg_names
[] = {
468 "sr", "lo", "hi", "bad", "cause", "pc",
469 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
470 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
471 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
472 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
473 "fsr", "fir", "", /*"fp" */ "",
474 "", "", "bus", "ccfg", "", "", "", "",
475 "", "", "port", "cmp", "", "", "epc", "prid",
478 /* Names of tx39 registers. */
480 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
481 "sr", "lo", "hi", "bad", "cause", "pc",
482 "", "", "", "", "", "", "", "",
483 "", "", "", "", "", "", "", "",
484 "", "", "", "", "", "", "", "",
485 "", "", "", "", "", "", "", "",
487 "", "", "", "", "", "", "", "",
488 "", "", "config", "cache", "debug", "depc", "epc", ""
491 /* Names of IRIX registers. */
492 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
493 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
494 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
495 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
496 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
497 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
501 /* Return the name of the register corresponding to REGNO. */
503 mips_register_name (int regno
)
505 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
506 /* GPR names for all ABIs other than n32/n64. */
507 static char *mips_gpr_names
[] = {
508 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
509 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
510 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
511 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
514 /* GPR names for n32 and n64 ABIs. */
515 static char *mips_n32_n64_gpr_names
[] = {
516 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
517 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
518 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
519 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
522 enum mips_abi abi
= mips_abi (current_gdbarch
);
524 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
525 don't make the raw register names visible. */
526 int rawnum
= regno
% NUM_REGS
;
527 if (regno
< NUM_REGS
)
530 /* The MIPS integer registers are always mapped from 0 to 31. The
531 names of the registers (which reflects the conventions regarding
532 register use) vary depending on the ABI. */
533 if (0 <= rawnum
&& rawnum
< 32)
535 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
536 return mips_n32_n64_gpr_names
[rawnum
];
538 return mips_gpr_names
[rawnum
];
540 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
542 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
543 return tdep
->mips_processor_reg_names
[rawnum
- 32];
546 internal_error (__FILE__
, __LINE__
,
547 "mips_register_name: bad register number %d", rawnum
);
550 /* Return the groups that a MIPS register can be categorised into. */
553 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
554 struct reggroup
*reggroup
)
559 int rawnum
= regnum
% NUM_REGS
;
560 int pseudo
= regnum
/ NUM_REGS
;
561 if (reggroup
== all_reggroup
)
563 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
564 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
565 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
566 (gdbarch), as not all architectures are multi-arch. */
567 raw_p
= rawnum
< NUM_REGS
;
568 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
570 if (reggroup
== float_reggroup
)
571 return float_p
&& pseudo
;
572 if (reggroup
== vector_reggroup
)
573 return vector_p
&& pseudo
;
574 if (reggroup
== general_reggroup
)
575 return (!vector_p
&& !float_p
) && pseudo
;
576 /* Save the pseudo registers. Need to make certain that any code
577 extracting register values from a saved register cache also uses
579 if (reggroup
== save_reggroup
)
580 return raw_p
&& pseudo
;
581 /* Restore the same pseudo register. */
582 if (reggroup
== restore_reggroup
)
583 return raw_p
&& pseudo
;
587 /* Map the symbol table registers which live in the range [1 *
588 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
589 registers. Take care of alignment and size problems. */
592 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
593 int cookednum
, void *buf
)
595 int rawnum
= cookednum
% NUM_REGS
;
596 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
597 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
598 regcache_raw_read (regcache
, rawnum
, buf
);
599 else if (register_size (gdbarch
, rawnum
) >
600 register_size (gdbarch
, cookednum
))
602 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
603 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
604 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
606 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
609 internal_error (__FILE__
, __LINE__
, "bad register size");
613 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
614 struct regcache
*regcache
, int cookednum
,
617 int rawnum
= cookednum
% NUM_REGS
;
618 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
619 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
620 regcache_raw_write (regcache
, rawnum
, buf
);
621 else if (register_size (gdbarch
, rawnum
) >
622 register_size (gdbarch
, cookednum
))
624 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
625 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
626 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
628 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
631 internal_error (__FILE__
, __LINE__
, "bad register size");
634 /* Table to translate MIPS16 register field to actual register number. */
635 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
637 /* Heuristic_proc_start may hunt through the text section for a long
638 time across a 2400 baud serial line. Allows the user to limit this
641 static unsigned int heuristic_fence_post
= 0;
643 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
644 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
645 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
646 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
647 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
648 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
649 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
650 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
651 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
652 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
653 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
654 this will corrupt pdr.iline. Fortunately we don't use it. */
655 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
656 #define _PROC_MAGIC_ 0x0F0F0F0F
658 /* Number of bytes of storage in the actual machine representation for
659 register N. NOTE: This defines the pseudo register type so need to
660 rebuild the architecture vector. */
662 static int mips64_transfers_32bit_regs_p
= 0;
665 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
666 struct cmd_list_element
*c
)
668 struct gdbarch_info info
;
669 gdbarch_info_init (&info
);
670 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
671 instead of relying on globals. Doing that would let generic code
672 handle the search for this specific architecture. */
673 if (!gdbarch_update_p (info
))
675 mips64_transfers_32bit_regs_p
= 0;
676 error ("32-bit compatibility mode not supported");
680 /* Convert to/from a register and the corresponding memory value. */
683 mips_convert_register_p (int regnum
, struct type
*type
)
685 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
686 && register_size (current_gdbarch
, regnum
) == 4
687 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
688 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
689 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
693 mips_register_to_value (struct frame_info
*frame
, int regnum
,
694 struct type
*type
, void *to
)
696 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
697 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
701 mips_value_to_register (struct frame_info
*frame
, int regnum
,
702 struct type
*type
, const void *from
)
704 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
705 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
708 /* Return the GDB type object for the "standard" data type of data in
712 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
714 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
715 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
716 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
718 /* The floating-point registers raw, or cooked, always match
719 mips_isa_regsize(), and also map 1:1, byte for byte. */
720 switch (gdbarch_byte_order (gdbarch
))
723 if (mips_isa_regsize (gdbarch
) == 4)
724 return builtin_type_ieee_single_big
;
726 return builtin_type_ieee_double_big
;
727 case BFD_ENDIAN_LITTLE
:
728 if (mips_isa_regsize (gdbarch
) == 4)
729 return builtin_type_ieee_single_little
;
731 return builtin_type_ieee_double_little
;
732 case BFD_ENDIAN_UNKNOWN
:
734 internal_error (__FILE__
, __LINE__
, "bad switch");
737 else if (regnum
< NUM_REGS
)
739 /* The raw or ISA registers. These are all sized according to
741 if (mips_isa_regsize (gdbarch
) == 4)
742 return builtin_type_int32
;
744 return builtin_type_int64
;
748 /* The cooked or ABI registers. These are sized according to
749 the ABI (with a few complications). */
750 if (regnum
>= (NUM_REGS
751 + mips_regnum (current_gdbarch
)->fp_control_status
)
752 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
753 /* The pseudo/cooked view of the embedded registers is always
754 32-bit. The raw view is handled below. */
755 return builtin_type_int32
;
756 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
757 /* The target, while possibly using a 64-bit register buffer,
758 is only transfering 32-bits of each integer register.
759 Reflect this in the cooked/pseudo (ABI) register value. */
760 return builtin_type_int32
;
761 else if (mips_abi_regsize (gdbarch
) == 4)
762 /* The ABI is restricted to 32-bit registers (the ISA could be
764 return builtin_type_int32
;
767 return builtin_type_int64
;
771 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
776 return read_signed_register (MIPS_SP_REGNUM
);
779 /* Should the upper word of 64-bit addresses be zeroed? */
780 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
783 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
785 switch (mask_address_var
)
787 case AUTO_BOOLEAN_TRUE
:
789 case AUTO_BOOLEAN_FALSE
:
792 case AUTO_BOOLEAN_AUTO
:
793 return tdep
->default_mask_address_p
;
795 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
801 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
803 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
804 switch (mask_address_var
)
806 case AUTO_BOOLEAN_TRUE
:
807 printf_filtered ("The 32 bit mips address mask is enabled\n");
809 case AUTO_BOOLEAN_FALSE
:
810 printf_filtered ("The 32 bit mips address mask is disabled\n");
812 case AUTO_BOOLEAN_AUTO
:
814 ("The 32 bit address mask is set automatically. Currently %s\n",
815 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
818 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
823 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
826 pc_is_mips16 (bfd_vma memaddr
)
828 struct minimal_symbol
*sym
;
830 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
831 if (is_mips16_addr (memaddr
))
834 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
835 the high bit of the info field. Use this to decide if the function is
836 MIPS16 or normal MIPS. */
837 sym
= lookup_minimal_symbol_by_pc (memaddr
);
839 return msymbol_is_special (sym
);
844 /* MIPS believes that the PC has a sign extended value. Perhaps the
845 all registers should be sign extended for simplicity? */
848 mips_read_pc (ptid_t ptid
)
850 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
854 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
856 return frame_unwind_register_signed (next_frame
,
857 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
860 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
861 dummy frame. The frame ID's base needs to match the TOS value
862 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
865 static struct frame_id
866 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
868 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
869 frame_pc_unwind (next_frame
));
873 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
875 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
878 /* This returns the PC of the first inst after the prologue. If we can't
879 find the prologue, then return 0. */
882 after_prologue (CORE_ADDR pc
)
884 mips_extra_func_info_t proc_desc
;
885 struct symtab_and_line sal
;
886 CORE_ADDR func_addr
, func_end
;
887 CORE_ADDR startaddr
= 0;
889 /* Pass a NULL next_frame to heuristic_proc_desc. We should not
890 attempt to read the stack pointer from the current machine state,
891 because the current machine state has nothing to do with the
892 information we need from the proc_desc; and the process may or
893 may not exist right now. */
894 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
897 /* IF this is the topmost frame AND (this proc does not have
898 debugging information OR the PC is in the procedure prologue)
899 THEN create a "heuristic" proc_desc (by analyzing the actual
900 code) to replace the "official" proc_desc. */
901 struct symtab_and_line val
;
902 if (PROC_SYMBOL (proc_desc
))
904 val
= find_pc_line (BLOCK_START
905 (SYMBOL_BLOCK_VALUE (PROC_SYMBOL (proc_desc
))),
907 val
.pc
= val
.end
? val
.end
: pc
;
909 if (!PROC_SYMBOL (proc_desc
) || pc
< val
.pc
)
911 mips_extra_func_info_t found_heuristic
=
912 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
), pc
, NULL
, NULL
);
914 proc_desc
= found_heuristic
;
920 startaddr
= heuristic_proc_start (pc
);
922 proc_desc
= heuristic_proc_desc (startaddr
, pc
, NULL
, NULL
);
927 /* If function is frameless, then we need to do it the hard way. I
928 strongly suspect that frameless always means prologueless... */
929 if (PROC_FRAME_REG (proc_desc
) == MIPS_SP_REGNUM
930 && PROC_FRAME_OFFSET (proc_desc
) == 0)
934 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
935 return 0; /* Unknown */
937 sal
= find_pc_line (func_addr
, 0);
939 if (sal
.end
< func_end
)
942 /* The line after the prologue is after the end of the function. In this
943 case, tell the caller to find the prologue the hard way. */
948 /* Fetch and return instruction from the specified location. If the PC
949 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
952 mips_fetch_instruction (CORE_ADDR addr
)
954 char buf
[MIPS_INSTLEN
];
958 if (pc_is_mips16 (addr
))
960 instlen
= MIPS16_INSTLEN
;
961 addr
= unmake_mips16_addr (addr
);
964 instlen
= MIPS_INSTLEN
;
965 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
967 memory_error (status
, addr
);
968 return extract_unsigned_integer (buf
, instlen
);
972 mips16_fetch_instruction (CORE_ADDR addr
)
974 char buf
[MIPS_INSTLEN
];
978 instlen
= MIPS16_INSTLEN
;
979 addr
= unmake_mips16_addr (addr
);
980 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
982 memory_error (status
, addr
);
983 return extract_unsigned_integer (buf
, instlen
);
986 /* These the fields of 32 bit mips instructions */
987 #define mips32_op(x) (x >> 26)
988 #define itype_op(x) (x >> 26)
989 #define itype_rs(x) ((x >> 21) & 0x1f)
990 #define itype_rt(x) ((x >> 16) & 0x1f)
991 #define itype_immediate(x) (x & 0xffff)
993 #define jtype_op(x) (x >> 26)
994 #define jtype_target(x) (x & 0x03ffffff)
996 #define rtype_op(x) (x >> 26)
997 #define rtype_rs(x) ((x >> 21) & 0x1f)
998 #define rtype_rt(x) ((x >> 16) & 0x1f)
999 #define rtype_rd(x) ((x >> 11) & 0x1f)
1000 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1001 #define rtype_funct(x) (x & 0x3f)
1004 mips32_relative_offset (unsigned long inst
)
1007 x
= itype_immediate (inst
);
1008 if (x
& 0x8000) /* sign bit set */
1010 x
|= 0xffff0000; /* sign extension */
1016 /* Determine whate to set a single step breakpoint while considering
1017 branch prediction */
1019 mips32_next_pc (CORE_ADDR pc
)
1023 inst
= mips_fetch_instruction (pc
);
1024 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1026 if (itype_op (inst
) >> 2 == 5)
1027 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1029 op
= (itype_op (inst
) & 0x03);
1039 goto greater_branch
;
1044 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1045 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1047 int tf
= itype_rt (inst
) & 0x01;
1048 int cnum
= itype_rt (inst
) >> 2;
1050 read_signed_register (mips_regnum (current_gdbarch
)->
1052 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1054 if (((cond
>> cnum
) & 0x01) == tf
)
1055 pc
+= mips32_relative_offset (inst
) + 4;
1060 pc
+= 4; /* Not a branch, next instruction is easy */
1063 { /* This gets way messy */
1065 /* Further subdivide into SPECIAL, REGIMM and other */
1066 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1068 case 0: /* SPECIAL */
1069 op
= rtype_funct (inst
);
1074 /* Set PC to that address */
1075 pc
= read_signed_register (rtype_rs (inst
));
1081 break; /* end SPECIAL */
1082 case 1: /* REGIMM */
1084 op
= itype_rt (inst
); /* branch condition */
1089 case 16: /* BLTZAL */
1090 case 18: /* BLTZALL */
1092 if (read_signed_register (itype_rs (inst
)) < 0)
1093 pc
+= mips32_relative_offset (inst
) + 4;
1095 pc
+= 8; /* after the delay slot */
1099 case 17: /* BGEZAL */
1100 case 19: /* BGEZALL */
1101 if (read_signed_register (itype_rs (inst
)) >= 0)
1102 pc
+= mips32_relative_offset (inst
) + 4;
1104 pc
+= 8; /* after the delay slot */
1106 /* All of the other instructions in the REGIMM category */
1111 break; /* end REGIMM */
1116 reg
= jtype_target (inst
) << 2;
1117 /* Upper four bits get never changed... */
1118 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1121 /* FIXME case JALX : */
1124 reg
= jtype_target (inst
) << 2;
1125 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1126 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1128 break; /* The new PC will be alternate mode */
1129 case 4: /* BEQ, BEQL */
1131 if (read_signed_register (itype_rs (inst
)) ==
1132 read_signed_register (itype_rt (inst
)))
1133 pc
+= mips32_relative_offset (inst
) + 4;
1137 case 5: /* BNE, BNEL */
1139 if (read_signed_register (itype_rs (inst
)) !=
1140 read_signed_register (itype_rt (inst
)))
1141 pc
+= mips32_relative_offset (inst
) + 4;
1145 case 6: /* BLEZ, BLEZL */
1146 if (read_signed_register (itype_rs (inst
)) <= 0)
1147 pc
+= mips32_relative_offset (inst
) + 4;
1153 greater_branch
: /* BGTZ, BGTZL */
1154 if (read_signed_register (itype_rs (inst
)) > 0)
1155 pc
+= mips32_relative_offset (inst
) + 4;
1162 } /* mips32_next_pc */
1164 /* Decoding the next place to set a breakpoint is irregular for the
1165 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1166 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1167 We dont want to set a single step instruction on the extend instruction
1171 /* Lots of mips16 instruction formats */
1172 /* Predicting jumps requires itype,ritype,i8type
1173 and their extensions extItype,extritype,extI8type
1175 enum mips16_inst_fmts
1177 itype
, /* 0 immediate 5,10 */
1178 ritype
, /* 1 5,3,8 */
1179 rrtype
, /* 2 5,3,3,5 */
1180 rritype
, /* 3 5,3,3,5 */
1181 rrrtype
, /* 4 5,3,3,3,2 */
1182 rriatype
, /* 5 5,3,3,1,4 */
1183 shifttype
, /* 6 5,3,3,3,2 */
1184 i8type
, /* 7 5,3,8 */
1185 i8movtype
, /* 8 5,3,3,5 */
1186 i8mov32rtype
, /* 9 5,3,5,3 */
1187 i64type
, /* 10 5,3,8 */
1188 ri64type
, /* 11 5,3,3,5 */
1189 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1190 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1191 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1192 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1193 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1194 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1195 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1196 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1197 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1198 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1200 /* I am heaping all the fields of the formats into one structure and
1201 then, only the fields which are involved in instruction extension */
1205 unsigned int regx
; /* Function in i8 type */
1210 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1211 for the bits which make up the immediatate extension. */
1214 extended_offset (unsigned int extension
)
1217 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1219 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1221 value
|= extension
& 0x01f; /* extract 4:0 */
1225 /* Only call this function if you know that this is an extendable
1226 instruction, It wont malfunction, but why make excess remote memory references?
1227 If the immediate operands get sign extended or somthing, do it after
1228 the extension is performed.
1230 /* FIXME: Every one of these cases needs to worry about sign extension
1231 when the offset is to be used in relative addressing */
1235 fetch_mips_16 (CORE_ADDR pc
)
1238 pc
&= 0xfffffffe; /* clear the low order bit */
1239 target_read_memory (pc
, buf
, 2);
1240 return extract_unsigned_integer (buf
, 2);
1244 unpack_mips16 (CORE_ADDR pc
,
1245 unsigned int extension
,
1247 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1252 switch (insn_format
)
1259 value
= extended_offset (extension
);
1260 value
= value
<< 11; /* rom for the original value */
1261 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1265 value
= inst
& 0x7ff;
1266 /* FIXME : Consider sign extension */
1275 { /* A register identifier and an offset */
1276 /* Most of the fields are the same as I type but the
1277 immediate value is of a different length */
1281 value
= extended_offset (extension
);
1282 value
= value
<< 8; /* from the original instruction */
1283 value
|= inst
& 0xff; /* eleven bits from instruction */
1284 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1285 if (value
& 0x4000) /* test the sign bit , bit 26 */
1287 value
&= ~0x3fff; /* remove the sign bit */
1293 value
= inst
& 0xff; /* 8 bits */
1294 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1295 /* FIXME: Do sign extension , this format needs it */
1296 if (value
& 0x80) /* THIS CONFUSES ME */
1298 value
&= 0xef; /* remove the sign bit */
1308 unsigned long value
;
1309 unsigned int nexthalf
;
1310 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1311 value
= value
<< 16;
1312 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1320 internal_error (__FILE__
, __LINE__
, "bad switch");
1322 upk
->offset
= offset
;
1329 add_offset_16 (CORE_ADDR pc
, int offset
)
1331 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1335 extended_mips16_next_pc (CORE_ADDR pc
,
1336 unsigned int extension
, unsigned int insn
)
1338 int op
= (insn
>> 11);
1341 case 2: /* Branch */
1344 struct upk_mips16 upk
;
1345 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1346 offset
= upk
.offset
;
1352 pc
+= (offset
<< 1) + 2;
1355 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1357 struct upk_mips16 upk
;
1358 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1359 pc
= add_offset_16 (pc
, upk
.offset
);
1360 if ((insn
>> 10) & 0x01) /* Exchange mode */
1361 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1368 struct upk_mips16 upk
;
1370 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1371 reg
= read_signed_register (upk
.regx
);
1373 pc
+= (upk
.offset
<< 1) + 2;
1380 struct upk_mips16 upk
;
1382 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1383 reg
= read_signed_register (upk
.regx
);
1385 pc
+= (upk
.offset
<< 1) + 2;
1390 case 12: /* I8 Formats btez btnez */
1392 struct upk_mips16 upk
;
1394 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1395 /* upk.regx contains the opcode */
1396 reg
= read_signed_register (24); /* Test register is 24 */
1397 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1398 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1399 /* pc = add_offset_16(pc,upk.offset) ; */
1400 pc
+= (upk
.offset
<< 1) + 2;
1405 case 29: /* RR Formats JR, JALR, JALR-RA */
1407 struct upk_mips16 upk
;
1408 /* upk.fmt = rrtype; */
1413 upk
.regx
= (insn
>> 8) & 0x07;
1414 upk
.regy
= (insn
>> 5) & 0x07;
1422 break; /* Function return instruction */
1428 break; /* BOGUS Guess */
1430 pc
= read_signed_register (reg
);
1437 /* This is an instruction extension. Fetch the real instruction
1438 (which follows the extension) and decode things based on
1442 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1455 mips16_next_pc (CORE_ADDR pc
)
1457 unsigned int insn
= fetch_mips_16 (pc
);
1458 return extended_mips16_next_pc (pc
, 0, insn
);
1461 /* The mips_next_pc function supports single_step when the remote
1462 target monitor or stub is not developed enough to do a single_step.
1463 It works by decoding the current instruction and predicting where a
1464 branch will go. This isnt hard because all the data is available.
1465 The MIPS32 and MIPS16 variants are quite different */
1467 mips_next_pc (CORE_ADDR pc
)
1470 return mips16_next_pc (pc
);
1472 return mips32_next_pc (pc
);
1475 struct mips_frame_cache
1478 struct trad_frame_saved_reg
*saved_regs
;
1482 static struct mips_frame_cache
*
1483 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1485 CORE_ADDR startaddr
= 0;
1486 mips_extra_func_info_t proc_desc
;
1487 struct mips_frame_cache
*cache
;
1488 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1489 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1490 /* r0 bit means kernel trap */
1492 /* What registers have been saved? Bitmasks. */
1493 unsigned long gen_mask
, float_mask
;
1495 if ((*this_cache
) != NULL
)
1496 return (*this_cache
);
1497 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1498 (*this_cache
) = cache
;
1499 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1501 /* Get the mdebug proc descriptor. */
1502 proc_desc
= non_heuristic_proc_desc (frame_pc_unwind (next_frame
),
1504 /* Must be true. This is only called when the sniffer detected a
1506 gdb_assert (proc_desc
!= NULL
);
1508 /* Extract the frame's base. */
1509 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1510 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1512 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1513 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1514 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1516 /* Must be true. The in_prologue case is left for the heuristic
1517 unwinder. This is always used on kernel traps. */
1518 gdb_assert (!in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1521 /* Fill in the offsets for the registers which gen_mask says were
1524 CORE_ADDR reg_position
= (cache
->base
+ PROC_REG_OFFSET (proc_desc
));
1527 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1528 if (gen_mask
& 0x80000000)
1530 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1531 reg_position
-= mips_abi_regsize (gdbarch
);
1535 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1536 order of that normally used by gcc. Therefore, we have to fetch
1537 the first instruction of the function, and if it's an entry
1538 instruction that saves $s0 or $s1, correct their saved addresses. */
1539 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1541 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1542 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1546 int sreg_count
= (inst
>> 6) & 3;
1548 /* Check if the ra register was pushed on the stack. */
1549 CORE_ADDR reg_position
= (cache
->base
1550 + PROC_REG_OFFSET (proc_desc
));
1552 reg_position
-= mips_abi_regsize (gdbarch
);
1554 /* Check if the s0 and s1 registers were pushed on the
1556 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1558 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1560 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1561 reg_position
-= mips_abi_regsize (gdbarch
);
1566 /* Fill in the offsets for the registers which float_mask says were
1569 CORE_ADDR reg_position
= (cache
->base
1570 + PROC_FREG_OFFSET (proc_desc
));
1572 /* Fill in the offsets for the float registers which float_mask
1574 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1575 if (float_mask
& 0x80000000)
1577 if (mips_abi_regsize (gdbarch
) == 4
1578 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1580 /* On a big endian 32 bit ABI, floating point registers
1581 are paired to form doubles such that the most
1582 significant part is in $f[N+1] and the least
1583 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1584 registers are also spilled as a pair and stored as a
1587 When little-endian the least significant part is
1588 stored first leading to the memory order $f[N] and
1591 Unfortunately, when big-endian the most significant
1592 part of the double is stored first, and the least
1593 significant is stored second. This leads to the
1594 registers being ordered in memory as firt $f[N+1] and
1597 For the big-endian case make certain that the
1598 addresses point at the correct (swapped) locations
1599 $f[N] and $f[N+1] pair (keep in mind that
1600 reg_position is decremented each time through the
1603 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1604 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1606 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1607 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1610 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1611 .addr
= reg_position
;
1612 reg_position
-= mips_abi_regsize (gdbarch
);
1615 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1616 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1619 /* SP_REGNUM, contains the value and not the address. */
1620 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1622 return (*this_cache
);
1626 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1627 struct frame_id
*this_id
)
1629 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1631 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1635 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1637 int regnum
, int *optimizedp
,
1638 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1639 int *realnump
, void *valuep
)
1641 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1643 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1644 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1647 static const struct frame_unwind mips_mdebug_frame_unwind
=
1650 mips_mdebug_frame_this_id
,
1651 mips_mdebug_frame_prev_register
1654 static const struct frame_unwind
*
1655 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1657 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1658 CORE_ADDR startaddr
= 0;
1659 mips_extra_func_info_t proc_desc
;
1662 /* Only use the mdebug frame unwinder on mdebug frames where all the
1663 registers have been saved. Leave hard cases such as no mdebug or
1664 in prologue for the heuristic unwinders. */
1666 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1667 if (proc_desc
== NULL
)
1670 /* Not sure exactly what kernel_trap means, but if it means the
1671 kernel saves the registers without a prologue doing it, we better
1672 not examine the prologue to see whether registers have been saved
1674 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1676 return &mips_mdebug_frame_unwind
;
1678 /* In any frame other than the innermost or a frame interrupted by a
1679 signal, we assume that all registers have been saved. This
1680 assumes that all register saves in a function happen before the
1681 first function call. */
1682 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1683 return &mips_mdebug_frame_unwind
;
1689 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1692 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1697 static const struct frame_base mips_mdebug_frame_base
= {
1698 &mips_mdebug_frame_unwind
,
1699 mips_mdebug_frame_base_address
,
1700 mips_mdebug_frame_base_address
,
1701 mips_mdebug_frame_base_address
1704 static const struct frame_base
*
1705 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1707 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1708 return &mips_mdebug_frame_base
;
1713 /* Set a register's saved stack address in temp_saved_regs. If an
1714 address has already been set for this register, do nothing; this
1715 way we will only recognize the first save of a given register in a
1718 For simplicity, save the address in both [0 .. NUM_REGS) and
1719 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1720 is used as it is only second range (the ABI instead of ISA
1721 registers) that comes into play when finding saved registers in a
1725 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1728 if (this_cache
!= NULL
1729 && this_cache
->saved_regs
[regnum
].addr
== -1)
1731 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
1732 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
1737 /* Fetch the immediate value from a MIPS16 instruction.
1738 If the previous instruction was an EXTEND, use it to extend
1739 the upper bits of the immediate value. This is a helper function
1740 for mips16_scan_prologue. */
1743 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1744 unsigned short inst
, /* current instruction */
1745 int nbits
, /* number of bits in imm field */
1746 int scale
, /* scale factor to be applied to imm */
1747 int is_signed
) /* is the imm field signed? */
1751 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1753 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1754 if (offset
& 0x8000) /* check for negative extend */
1755 offset
= 0 - (0x10000 - (offset
& 0xffff));
1756 return offset
| (inst
& 0x1f);
1760 int max_imm
= 1 << nbits
;
1761 int mask
= max_imm
- 1;
1762 int sign_bit
= max_imm
>> 1;
1764 offset
= inst
& mask
;
1765 if (is_signed
&& (offset
& sign_bit
))
1766 offset
= 0 - (max_imm
- offset
);
1767 return offset
* scale
;
1772 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1773 the associated FRAME_CACHE if not null.
1774 Return the address of the first instruction past the prologue. */
1777 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1778 struct frame_info
*next_frame
,
1779 struct mips_frame_cache
*this_cache
)
1782 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1784 long frame_offset
= 0; /* Size of stack frame. */
1785 long frame_adjust
= 0; /* Offset of FP from SP. */
1786 int frame_reg
= MIPS_SP_REGNUM
;
1787 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1788 unsigned inst
= 0; /* current instruction */
1789 unsigned entry_inst
= 0; /* the entry instruction */
1792 int extend_bytes
= 0;
1793 int prev_extend_bytes
;
1794 CORE_ADDR end_prologue_addr
= 0;
1796 /* Can be called when there's no process, and hence when there's no
1798 if (next_frame
!= NULL
)
1799 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1803 if (limit_pc
> start_pc
+ 200)
1804 limit_pc
= start_pc
+ 200;
1806 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1808 /* Save the previous instruction. If it's an EXTEND, we'll extract
1809 the immediate offset extension from it in mips16_get_imm. */
1812 /* Fetch and decode the instruction. */
1813 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1815 /* Normally we ignore extend instructions. However, if it is
1816 not followed by a valid prologue instruction, then this
1817 instruction is not part of the prologue either. We must
1818 remember in this case to adjust the end_prologue_addr back
1820 if ((inst
& 0xf800) == 0xf000) /* extend */
1822 extend_bytes
= MIPS16_INSTLEN
;
1826 prev_extend_bytes
= extend_bytes
;
1829 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1830 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1832 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1833 if (offset
< 0) /* negative stack adjustment? */
1834 frame_offset
-= offset
;
1836 /* Exit loop if a positive stack adjustment is found, which
1837 usually means that the stack cleanup code in the function
1838 epilogue is reached. */
1841 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1843 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1844 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1845 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1847 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1849 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1850 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1851 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1853 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1855 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1856 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
1858 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1860 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1861 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
1863 else if (inst
== 0x673d) /* move $s1, $sp */
1868 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1870 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1871 frame_addr
= sp
+ offset
;
1873 frame_adjust
= offset
;
1875 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1877 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1878 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1879 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1881 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1883 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1884 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1885 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1887 else if ((inst
& 0xf81f) == 0xe809
1888 && (inst
& 0x700) != 0x700) /* entry */
1889 entry_inst
= inst
; /* save for later processing */
1890 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1891 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1892 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1894 /* This instruction is part of the prologue, but we don't
1895 need to do anything special to handle it. */
1899 /* This instruction is not an instruction typically found
1900 in a prologue, so we must have reached the end of the
1902 if (end_prologue_addr
== 0)
1903 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1907 /* The entry instruction is typically the first instruction in a function,
1908 and it stores registers at offsets relative to the value of the old SP
1909 (before the prologue). But the value of the sp parameter to this
1910 function is the new SP (after the prologue has been executed). So we
1911 can't calculate those offsets until we've seen the entire prologue,
1912 and can calculate what the old SP must have been. */
1913 if (entry_inst
!= 0)
1915 int areg_count
= (entry_inst
>> 8) & 7;
1916 int sreg_count
= (entry_inst
>> 6) & 3;
1918 /* The entry instruction always subtracts 32 from the SP. */
1921 /* Now we can calculate what the SP must have been at the
1922 start of the function prologue. */
1925 /* Check if a0-a3 were saved in the caller's argument save area. */
1926 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1928 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1929 offset
+= mips_abi_regsize (current_gdbarch
);
1932 /* Check if the ra register was pushed on the stack. */
1934 if (entry_inst
& 0x20)
1936 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
1937 offset
-= mips_abi_regsize (current_gdbarch
);
1940 /* Check if the s0 and s1 registers were pushed on the stack. */
1941 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1943 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1944 offset
-= mips_abi_regsize (current_gdbarch
);
1948 if (this_cache
!= NULL
)
1951 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1952 + frame_offset
- frame_adjust
);
1953 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1954 be able to get rid of the assignment below, evetually. But it's
1955 still needed for now. */
1956 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1957 = this_cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1960 /* If we didn't reach the end of the prologue when scanning the function
1961 instructions, then set end_prologue_addr to the address of the
1962 instruction immediately after the last one we scanned. */
1963 if (end_prologue_addr
== 0)
1964 end_prologue_addr
= cur_pc
;
1966 return end_prologue_addr
;
1969 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1970 Procedures that use the 32-bit instruction set are handled by the
1971 mips_insn32 unwinder. */
1973 static struct mips_frame_cache
*
1974 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1976 struct mips_frame_cache
*cache
;
1978 if ((*this_cache
) != NULL
)
1979 return (*this_cache
);
1980 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1981 (*this_cache
) = cache
;
1982 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1984 /* Analyze the function prologue. */
1986 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1987 CORE_ADDR start_addr
;
1989 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1990 if (start_addr
== 0)
1991 start_addr
= heuristic_proc_start (pc
);
1992 /* We can't analyze the prologue if we couldn't find the begining
1994 if (start_addr
== 0)
1997 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
2000 /* SP_REGNUM, contains the value and not the address. */
2001 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2003 return (*this_cache
);
2007 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2008 struct frame_id
*this_id
)
2010 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2012 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2016 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
2018 int regnum
, int *optimizedp
,
2019 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2020 int *realnump
, void *valuep
)
2022 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2024 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2025 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2028 static const struct frame_unwind mips_insn16_frame_unwind
=
2031 mips_insn16_frame_this_id
,
2032 mips_insn16_frame_prev_register
2035 static const struct frame_unwind
*
2036 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
2038 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2039 if (pc_is_mips16 (pc
))
2040 return &mips_insn16_frame_unwind
;
2045 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
2048 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2053 static const struct frame_base mips_insn16_frame_base
=
2055 &mips_insn16_frame_unwind
,
2056 mips_insn16_frame_base_address
,
2057 mips_insn16_frame_base_address
,
2058 mips_insn16_frame_base_address
2061 static const struct frame_base
*
2062 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
2064 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
2065 return &mips_insn16_frame_base
;
2070 /* Mark all the registers as unset in the saved_regs array
2071 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2074 reset_saved_regs (struct mips_frame_cache
*this_cache
)
2076 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2080 const int num_regs
= NUM_REGS
;
2083 for (i
= 0; i
< num_regs
; i
++)
2085 this_cache
->saved_regs
[i
].addr
= -1;
2090 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2091 the associated FRAME_CACHE if not null.
2092 Return the address of the first instruction past the prologue. */
2095 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2096 struct frame_info
*next_frame
,
2097 struct mips_frame_cache
*this_cache
)
2100 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2103 int frame_reg
= MIPS_SP_REGNUM
;
2105 CORE_ADDR end_prologue_addr
= 0;
2106 int seen_sp_adjust
= 0;
2107 int load_immediate_bytes
= 0;
2109 /* Can be called when there's no process, and hence when there's no
2111 if (next_frame
!= NULL
)
2112 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2116 if (limit_pc
> start_pc
+ 200)
2117 limit_pc
= start_pc
+ 200;
2122 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2124 unsigned long inst
, high_word
, low_word
;
2127 /* Fetch the instruction. */
2128 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2130 /* Save some code by pre-extracting some useful fields. */
2131 high_word
= (inst
>> 16) & 0xffff;
2132 low_word
= inst
& 0xffff;
2133 reg
= high_word
& 0x1f;
2135 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2136 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2137 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2139 if (low_word
& 0x8000) /* negative stack adjustment? */
2140 frame_offset
+= 0x10000 - low_word
;
2142 /* Exit loop if a positive stack adjustment is found, which
2143 usually means that the stack cleanup code in the function
2144 epilogue is reached. */
2148 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2150 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2152 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2154 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2155 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2157 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2159 /* Old gcc frame, r30 is virtual frame pointer. */
2160 if ((long) low_word
!= frame_offset
)
2161 frame_addr
= sp
+ low_word
;
2162 else if (frame_reg
== MIPS_SP_REGNUM
)
2164 unsigned alloca_adjust
;
2167 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2168 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2169 if (alloca_adjust
> 0)
2171 /* FP > SP + frame_size. This may be because of
2172 an alloca or somethings similar. Fix sp to
2173 "pre-alloca" value, and try again. */
2174 sp
+= alloca_adjust
;
2175 /* Need to reset the status of all registers. Otherwise,
2176 we will hit a guard that prevents the new address
2177 for each register to be recomputed during the second
2179 reset_saved_regs (this_cache
);
2184 /* move $30,$sp. With different versions of gas this will be either
2185 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2186 Accept any one of these. */
2187 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2189 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2190 if (frame_reg
== MIPS_SP_REGNUM
)
2192 unsigned alloca_adjust
;
2195 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2196 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2197 if (alloca_adjust
> 0)
2199 /* FP > SP + frame_size. This may be because of
2200 an alloca or somethings similar. Fix sp to
2201 "pre-alloca" value, and try again. */
2203 /* Need to reset the status of all registers. Otherwise,
2204 we will hit a guard that prevents the new address
2205 for each register to be recomputed during the second
2207 reset_saved_regs (this_cache
);
2212 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2214 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
2216 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2217 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2218 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2219 || high_word
== 0x3c1c /* lui $gp,n */
2220 || high_word
== 0x279c /* addiu $gp,$gp,n */
2221 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2222 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2225 /* These instructions are part of the prologue, but we don't
2226 need to do anything special to handle them. */
2228 /* The instructions below load $at or $t0 with an immediate
2229 value in preparation for a stack adjustment via
2230 subu $sp,$sp,[$at,$t0]. These instructions could also
2231 initialize a local variable, so we accept them only before
2232 a stack adjustment instruction was seen. */
2233 else if (!seen_sp_adjust
2234 && (high_word
== 0x3c01 /* lui $at,n */
2235 || high_word
== 0x3c08 /* lui $t0,n */
2236 || high_word
== 0x3421 /* ori $at,$at,n */
2237 || high_word
== 0x3508 /* ori $t0,$t0,n */
2238 || high_word
== 0x3401 /* ori $at,$zero,n */
2239 || high_word
== 0x3408 /* ori $t0,$zero,n */
2242 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2246 /* This instruction is not an instruction typically found
2247 in a prologue, so we must have reached the end of the
2249 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2250 loop now? Why would we need to continue scanning the function
2252 if (end_prologue_addr
== 0)
2253 end_prologue_addr
= cur_pc
;
2257 if (this_cache
!= NULL
)
2260 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
2262 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2263 this assignment below, eventually. But it's still needed
2265 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2266 = this_cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2269 /* If we didn't reach the end of the prologue when scanning the function
2270 instructions, then set end_prologue_addr to the address of the
2271 instruction immediately after the last one we scanned. */
2272 /* brobecker/2004-10-10: I don't think this would ever happen, but
2273 we may as well be careful and do our best if we have a null
2274 end_prologue_addr. */
2275 if (end_prologue_addr
== 0)
2276 end_prologue_addr
= cur_pc
;
2278 /* In a frameless function, we might have incorrectly
2279 skipped some load immediate instructions. Undo the skipping
2280 if the load immediate was not followed by a stack adjustment. */
2281 if (load_immediate_bytes
&& !seen_sp_adjust
)
2282 end_prologue_addr
-= load_immediate_bytes
;
2284 return end_prologue_addr
;
2287 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2288 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2289 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2292 static struct mips_frame_cache
*
2293 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2295 struct mips_frame_cache
*cache
;
2297 if ((*this_cache
) != NULL
)
2298 return (*this_cache
);
2300 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2301 (*this_cache
) = cache
;
2302 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2304 /* Analyze the function prologue. */
2306 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2307 CORE_ADDR start_addr
;
2309 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2310 if (start_addr
== 0)
2311 start_addr
= heuristic_proc_start (pc
);
2312 /* We can't analyze the prologue if we couldn't find the begining
2314 if (start_addr
== 0)
2317 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
2320 /* SP_REGNUM, contains the value and not the address. */
2321 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2323 return (*this_cache
);
2327 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2328 struct frame_id
*this_id
)
2330 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2332 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2336 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2338 int regnum
, int *optimizedp
,
2339 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2340 int *realnump
, void *valuep
)
2342 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2344 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2345 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2348 static const struct frame_unwind mips_insn32_frame_unwind
=
2351 mips_insn32_frame_this_id
,
2352 mips_insn32_frame_prev_register
2355 static const struct frame_unwind
*
2356 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2358 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2359 if (! pc_is_mips16 (pc
))
2360 return &mips_insn32_frame_unwind
;
2365 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2368 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2373 static const struct frame_base mips_insn32_frame_base
=
2375 &mips_insn32_frame_unwind
,
2376 mips_insn32_frame_base_address
,
2377 mips_insn32_frame_base_address
,
2378 mips_insn32_frame_base_address
2381 static const struct frame_base
*
2382 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2384 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2385 return &mips_insn32_frame_base
;
2390 static struct trad_frame_cache
*
2391 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2394 CORE_ADDR start_addr
;
2395 CORE_ADDR stack_addr
;
2396 struct trad_frame_cache
*this_trad_cache
;
2398 if ((*this_cache
) != NULL
)
2399 return (*this_cache
);
2400 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2401 (*this_cache
) = this_trad_cache
;
2403 /* The return address is in the link register. */
2404 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, RA_REGNUM
);
2406 /* Frame ID, since it's a frameless / stackless function, no stack
2407 space is allocated and SP on entry is the current SP. */
2408 pc
= frame_pc_unwind (next_frame
);
2409 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2410 stack_addr
= frame_unwind_register_signed (next_frame
, SP_REGNUM
);
2411 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2413 /* Assume that the frame's base is the same as the
2415 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2417 return this_trad_cache
;
2421 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2422 struct frame_id
*this_id
)
2424 struct trad_frame_cache
*this_trad_cache
2425 = mips_stub_frame_cache (next_frame
, this_cache
);
2426 trad_frame_get_id (this_trad_cache
, this_id
);
2430 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2432 int regnum
, int *optimizedp
,
2433 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2434 int *realnump
, void *valuep
)
2436 struct trad_frame_cache
*this_trad_cache
2437 = mips_stub_frame_cache (next_frame
, this_cache
);
2438 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2439 lvalp
, addrp
, realnump
, valuep
);
2442 static const struct frame_unwind mips_stub_frame_unwind
=
2445 mips_stub_frame_this_id
,
2446 mips_stub_frame_prev_register
2449 static const struct frame_unwind
*
2450 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2452 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2453 if (in_plt_section (pc
, NULL
))
2454 return &mips_stub_frame_unwind
;
2460 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2463 struct trad_frame_cache
*this_trad_cache
2464 = mips_stub_frame_cache (next_frame
, this_cache
);
2465 return trad_frame_get_this_base (this_trad_cache
);
2468 static const struct frame_base mips_stub_frame_base
=
2470 &mips_stub_frame_unwind
,
2471 mips_stub_frame_base_address
,
2472 mips_stub_frame_base_address
,
2473 mips_stub_frame_base_address
2476 static const struct frame_base
*
2477 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2479 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2480 return &mips_stub_frame_base
;
2486 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2488 /* Always a pseudo. */
2489 gdb_assert (regno
>= NUM_REGS
);
2493 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2497 return frame_unwind_register_signed (fi
, regno
);
2501 /* mips_addr_bits_remove - remove useless address bits */
2504 mips_addr_bits_remove (CORE_ADDR addr
)
2506 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2507 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2508 /* This hack is a work-around for existing boards using PMON, the
2509 simulator, and any other 64-bit targets that doesn't have true
2510 64-bit addressing. On these targets, the upper 32 bits of
2511 addresses are ignored by the hardware. Thus, the PC or SP are
2512 likely to have been sign extended to all 1s by instruction
2513 sequences that load 32-bit addresses. For example, a typical
2514 piece of code that loads an address is this:
2516 lui $r2, <upper 16 bits>
2517 ori $r2, <lower 16 bits>
2519 But the lui sign-extends the value such that the upper 32 bits
2520 may be all 1s. The workaround is simply to mask off these
2521 bits. In the future, gcc may be changed to support true 64-bit
2522 addressing, and this masking will have to be disabled. */
2523 return addr
&= 0xffffffffUL
;
2528 /* mips_software_single_step() is called just before we want to resume
2529 the inferior, if we want to single-step it but there is no hardware
2530 or kernel single-step support (MIPS on GNU/Linux for example). We find
2531 the target of the coming instruction and breakpoint it.
2533 single_step is also called just after the inferior stops. If we had
2534 set up a simulated single-step, we undo our damage. */
2537 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2539 static CORE_ADDR next_pc
;
2540 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2541 static binsn_quantum break_mem
;
2544 if (insert_breakpoints_p
)
2546 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2547 next_pc
= mips_next_pc (pc
);
2549 target_insert_breakpoint (next_pc
, break_mem
);
2552 target_remove_breakpoint (next_pc
, break_mem
);
2555 static struct mips_extra_func_info temp_proc_desc
;
2557 /* Test whether the PC points to the return instruction at the
2558 end of a function. */
2561 mips_about_to_return (CORE_ADDR pc
)
2563 if (pc_is_mips16 (pc
))
2564 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2565 generates a "jr $ra"; other times it generates code to load
2566 the return address from the stack to an accessible register (such
2567 as $a3), then a "jr" using that register. This second case
2568 is almost impossible to distinguish from an indirect jump
2569 used for switch statements, so we don't even try. */
2570 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2572 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2576 /* This fencepost looks highly suspicious to me. Removing it also
2577 seems suspicious as it could affect remote debugging across serial
2581 heuristic_proc_start (CORE_ADDR pc
)
2588 pc
= ADDR_BITS_REMOVE (pc
);
2590 fence
= start_pc
- heuristic_fence_post
;
2594 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2595 fence
= VM_MIN_ADDRESS
;
2597 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
2599 /* search back for previous return */
2600 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2601 if (start_pc
< fence
)
2603 /* It's not clear to me why we reach this point when
2604 stop_soon, but with this test, at least we
2605 don't print out warnings for every child forked (eg, on
2606 decstation). 22apr93 rich@cygnus.com. */
2607 if (stop_soon
== NO_STOP_QUIETLY
)
2609 static int blurb_printed
= 0;
2611 warning ("GDB can't find the start of the function at 0x%s.",
2616 /* This actually happens frequently in embedded
2617 development, when you first connect to a board
2618 and your stack pointer and pc are nowhere in
2619 particular. This message needs to give people
2620 in that situation enough information to
2621 determine that it's no big deal. */
2622 printf_filtered ("\n\
2623 GDB is unable to find the start of the function at 0x%s\n\
2624 and thus can't determine the size of that function's stack frame.\n\
2625 This means that GDB may be unable to access that stack frame, or\n\
2626 the frames below it.\n\
2627 This problem is most likely caused by an invalid program counter or\n\
2629 However, if you think GDB should simply search farther back\n\
2630 from 0x%s for code which looks like the beginning of a\n\
2631 function, you can increase the range of the search using the `set\n\
2632 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2639 else if (pc_is_mips16 (start_pc
))
2641 unsigned short inst
;
2643 /* On MIPS16, any one of the following is likely to be the
2644 start of a function:
2648 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2649 inst
= mips_fetch_instruction (start_pc
);
2650 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2651 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2652 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2653 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2655 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2656 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2661 else if (mips_about_to_return (start_pc
))
2663 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2670 static mips_extra_func_info_t
2671 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2672 struct frame_info
*next_frame
,
2673 struct mips_frame_cache
*this_cache
)
2678 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2679 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2680 PROC_FRAME_REG (&temp_proc_desc
) = MIPS_SP_REGNUM
;
2681 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2683 if (pc_is_mips16 (start_pc
))
2684 mips16_scan_prologue (start_pc
, limit_pc
, next_frame
, this_cache
);
2686 mips32_scan_prologue (start_pc
, limit_pc
, next_frame
, this_cache
);
2688 return &temp_proc_desc
;
2691 struct mips_objfile_private
2697 /* Global used to communicate between non_heuristic_proc_desc and
2698 compare_pdr_entries within qsort (). */
2699 static bfd
*the_bfd
;
2702 compare_pdr_entries (const void *a
, const void *b
)
2704 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2705 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2709 else if (lhs
== rhs
)
2715 static mips_extra_func_info_t
2716 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2718 CORE_ADDR startaddr
;
2719 mips_extra_func_info_t proc_desc
;
2720 struct block
*b
= block_for_pc (pc
);
2722 struct obj_section
*sec
;
2723 struct mips_objfile_private
*priv
;
2725 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2727 *addrptr
= startaddr
;
2731 sec
= find_pc_section (pc
);
2734 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2736 /* Search the ".pdr" section generated by GAS. This includes most of
2737 the information normally found in ECOFF PDRs. */
2739 the_bfd
= sec
->objfile
->obfd
;
2741 && (the_bfd
->format
== bfd_object
2742 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2743 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2745 /* Right now GAS only outputs the address as a four-byte sequence.
2746 This means that we should not bother with this method on 64-bit
2747 targets (until that is fixed). */
2749 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2750 sizeof (struct mips_objfile_private
));
2752 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2754 else if (priv
== NULL
)
2758 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2759 sizeof (struct mips_objfile_private
));
2761 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2764 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2765 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2767 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2768 priv
->contents
, 0, priv
->size
);
2770 /* In general, the .pdr section is sorted. However, in the
2771 presence of multiple code sections (and other corner cases)
2772 it can become unsorted. Sort it so that we can use a faster
2774 qsort (priv
->contents
, priv
->size
/ 32, 32,
2775 compare_pdr_entries
);
2780 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2784 if (priv
->size
!= 0)
2791 high
= priv
->size
/ 32;
2793 /* We've found a .pdr section describing this objfile. We want to
2794 find the entry which describes this code address. The .pdr
2795 information is not very descriptive; we have only a function
2796 start address. We have to look for the closest entry, because
2797 the local symbol at the beginning of this function may have
2798 been stripped - so if we ask the symbol table for the start
2799 address we may get a preceding global function. */
2801 /* First, find the last .pdr entry starting at or before PC. */
2804 mid
= (low
+ high
) / 2;
2806 ptr
= priv
->contents
+ mid
* 32;
2807 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2808 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2809 SECT_OFF_TEXT (sec
->objfile
));
2816 while (low
!= high
);
2818 /* Both low and high point one past the PDR of interest. If
2819 both are zero, that means this PC is before any region
2820 covered by a PDR, i.e. pdr_pc for the first PDR entry is
2824 ptr
= priv
->contents
+ (low
- 1) * 32;
2825 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2826 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2827 SECT_OFF_TEXT (sec
->objfile
));
2830 /* We don't have a range, so we have no way to know for sure
2831 whether we're in the correct PDR or a PDR for a preceding
2832 function and the current function was a stripped local
2833 symbol. But if the PDR's PC is at least as great as the
2834 best guess from the symbol table, assume that it does cover
2835 the right area; if a .pdr section is present at all then
2836 nearly every function will have an entry. The biggest exception
2837 will be the dynamic linker stubs; conveniently these are
2838 placed before .text instead of after. */
2840 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
2842 struct symbol
*sym
= find_pc_function (pc
);
2847 /* Fill in what we need of the proc_desc. */
2848 proc_desc
= (mips_extra_func_info_t
)
2849 obstack_alloc (&sec
->objfile
->objfile_obstack
,
2850 sizeof (struct mips_extra_func_info
));
2851 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
2853 /* Only used for dummy frames. */
2854 PROC_HIGH_ADDR (proc_desc
) = 0;
2856 PROC_FRAME_OFFSET (proc_desc
)
2857 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2858 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2860 PROC_FRAME_ADJUST (proc_desc
) = 0;
2861 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2863 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2865 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2867 PROC_FREG_OFFSET (proc_desc
)
2868 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2869 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2871 proc_desc
->pdr
.isym
= (long) sym
;
2881 if (startaddr
> BLOCK_START (b
))
2883 /* This is the "pathological" case referred to in a comment in
2884 print_frame_info. It might be better to move this check into
2889 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2891 /* If we never found a PDR for this function in symbol reading, then
2892 examine prologues to find the information. */
2895 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2896 if (PROC_FRAME_REG (proc_desc
) == -1)
2905 /* MIPS stack frames are almost impenetrable. When execution stops,
2906 we basically have to look at symbol information for the function
2907 that we stopped in, which tells us *which* register (if any) is
2908 the base of the frame pointer, and what offset from that register
2909 the frame itself is at.
2911 This presents a problem when trying to examine a stack in memory
2912 (that isn't executing at the moment), using the "frame" command. We
2913 don't have a PC, nor do we have any registers except SP.
2915 This routine takes two arguments, SP and PC, and tries to make the
2916 cached frames look as if these two arguments defined a frame on the
2917 cache. This allows the rest of info frame to extract the important
2918 arguments without difficulty. */
2921 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2924 error ("MIPS frame specifications require two arguments: sp and pc");
2926 return create_new_frame (argv
[0], argv
[1]);
2929 /* According to the current ABI, should the type be passed in a
2930 floating-point register (assuming that there is space)? When there
2931 is no FPU, FP are not even considered as possibile candidates for
2932 FP registers and, consequently this returns false - forces FP
2933 arguments into integer registers. */
2936 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2938 return ((typecode
== TYPE_CODE_FLT
2940 && (typecode
== TYPE_CODE_STRUCT
2941 || typecode
== TYPE_CODE_UNION
)
2942 && TYPE_NFIELDS (arg_type
) == 1
2943 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2944 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2947 /* On o32, argument passing in GPRs depends on the alignment of the type being
2948 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2951 mips_type_needs_double_align (struct type
*type
)
2953 enum type_code typecode
= TYPE_CODE (type
);
2955 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2957 else if (typecode
== TYPE_CODE_STRUCT
)
2959 if (TYPE_NFIELDS (type
) < 1)
2961 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2963 else if (typecode
== TYPE_CODE_UNION
)
2967 n
= TYPE_NFIELDS (type
);
2968 for (i
= 0; i
< n
; i
++)
2969 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2976 /* Adjust the address downward (direction of stack growth) so that it
2977 is correctly aligned for a new stack frame. */
2979 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2981 return align_down (addr
, 16);
2984 /* Determine how a return value is stored within the MIPS register
2985 file, given the return type `valtype'. */
2987 struct return_value_word
2996 return_value_location (struct type
*valtype
,
2997 struct return_value_word
*hi
,
2998 struct return_value_word
*lo
)
3000 int len
= TYPE_LENGTH (valtype
);
3001 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3003 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3004 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3005 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3007 if (mips_abi_regsize (current_gdbarch
) < 8 && len
== 8)
3009 /* We need to break a 64bit float in two 32 bit halves and
3010 spread them across a floating-point register pair. */
3011 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3012 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3013 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3014 && register_size (current_gdbarch
,
3015 mips_regnum (current_gdbarch
)->
3016 fp0
) == 8) ? 4 : 0);
3017 hi
->reg_offset
= lo
->reg_offset
;
3018 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
3019 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
3025 /* The floating point value fits in a single floating-point
3027 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3028 && register_size (current_gdbarch
,
3029 mips_regnum (current_gdbarch
)->
3031 && len
== 4) ? 4 : 0);
3032 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
3043 /* Locate a result possibly spread across two registers. */
3045 lo
->reg
= regnum
+ 0;
3046 hi
->reg
= regnum
+ 1;
3047 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3048 && len
< mips_abi_regsize (current_gdbarch
))
3050 /* "un-left-justify" the value in the low register */
3051 lo
->reg_offset
= mips_abi_regsize (current_gdbarch
) - len
;
3056 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (current_gdbarch
) /* odd-size structs */
3057 && len
< mips_abi_regsize (current_gdbarch
) * 2
3058 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3059 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3061 /* "un-left-justify" the value spread across two registers. */
3062 lo
->reg_offset
= 2 * mips_abi_regsize (current_gdbarch
) - len
;
3063 lo
->len
= mips_abi_regsize (current_gdbarch
) - lo
->reg_offset
;
3065 hi
->len
= len
- lo
->len
;
3069 /* Only perform a partial copy of the second register. */
3072 if (len
> mips_abi_regsize (current_gdbarch
))
3074 lo
->len
= mips_abi_regsize (current_gdbarch
);
3075 hi
->len
= len
- mips_abi_regsize (current_gdbarch
);
3083 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3084 && register_size (current_gdbarch
, regnum
) == 8
3085 && mips_abi_regsize (current_gdbarch
) == 4)
3087 /* Account for the fact that only the least-signficant part
3088 of the register is being used */
3089 lo
->reg_offset
+= 4;
3090 hi
->reg_offset
+= 4;
3093 hi
->buf_offset
= lo
->len
;
3097 /* Should call_function allocate stack space for a struct return? */
3100 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
3102 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3103 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (current_gdbarch
));
3106 /* Should call_function pass struct by reference?
3107 For each architecture, structs are passed either by
3108 value or by reference, depending on their size. */
3111 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
3113 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
3114 int len
= TYPE_LENGTH (check_typedef (type
));
3115 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3117 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
3118 return (len
> mips_abi_regsize (current_gdbarch
));
3124 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3125 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3126 int nargs
, struct value
**args
, CORE_ADDR sp
,
3127 int struct_return
, CORE_ADDR struct_addr
)
3133 int stack_offset
= 0;
3134 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3135 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3137 /* For shared libraries, "t9" needs to point at the function
3139 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3141 /* Set the return address register to point to the entry point of
3142 the program, where a breakpoint lies in wait. */
3143 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3145 /* First ensure that the stack and structure return address (if any)
3146 are properly aligned. The stack has to be at least 64-bit
3147 aligned even on 32-bit machines, because doubles must be 64-bit
3148 aligned. For n32 and n64, stack frames need to be 128-bit
3149 aligned, so we round to this widest known alignment. */
3151 sp
= align_down (sp
, 16);
3152 struct_addr
= align_down (struct_addr
, 16);
3154 /* Now make space on the stack for the args. We allocate more
3155 than necessary for EABI, because the first few arguments are
3156 passed in registers, but that's OK. */
3157 for (argnum
= 0; argnum
< nargs
; argnum
++)
3158 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3159 mips_stack_argsize (gdbarch
));
3160 sp
-= align_up (len
, 16);
3163 fprintf_unfiltered (gdb_stdlog
,
3164 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
3165 paddr_nz (sp
), (long) align_up (len
, 16));
3167 /* Initialize the integer and float register pointers. */
3169 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3171 /* The struct_return pointer occupies the first parameter-passing reg. */
3175 fprintf_unfiltered (gdb_stdlog
,
3176 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
3177 argreg
, paddr_nz (struct_addr
));
3178 write_register (argreg
++, struct_addr
);
3181 /* Now load as many as possible of the first arguments into
3182 registers, and push the rest onto the stack. Loop thru args
3183 from first to last. */
3184 for (argnum
= 0; argnum
< nargs
; argnum
++)
3187 char valbuf
[MAX_REGISTER_SIZE
];
3188 struct value
*arg
= args
[argnum
];
3189 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3190 int len
= TYPE_LENGTH (arg_type
);
3191 enum type_code typecode
= TYPE_CODE (arg_type
);
3194 fprintf_unfiltered (gdb_stdlog
,
3195 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3196 argnum
+ 1, len
, (int) typecode
);
3198 /* The EABI passes structures that do not fit in a register by
3200 if (len
> mips_abi_regsize (gdbarch
)
3201 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3203 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
3204 VALUE_ADDRESS (arg
));
3205 typecode
= TYPE_CODE_PTR
;
3206 len
= mips_abi_regsize (gdbarch
);
3209 fprintf_unfiltered (gdb_stdlog
, " push");
3212 val
= (char *) VALUE_CONTENTS (arg
);
3214 /* 32-bit ABIs always start floating point arguments in an
3215 even-numbered floating point register. Round the FP register
3216 up before the check to see if there are any FP registers
3217 left. Non MIPS_EABI targets also pass the FP in the integer
3218 registers so also round up normal registers. */
3219 if (mips_abi_regsize (gdbarch
) < 8
3220 && fp_register_arg_p (typecode
, arg_type
))
3222 if ((float_argreg
& 1))
3226 /* Floating point arguments passed in registers have to be
3227 treated specially. On 32-bit architectures, doubles
3228 are passed in register pairs; the even register gets
3229 the low word, and the odd register gets the high word.
3230 On non-EABI processors, the first two floating point arguments are
3231 also copied to general registers, because MIPS16 functions
3232 don't use float registers for arguments. This duplication of
3233 arguments in general registers can't hurt non-MIPS16 functions
3234 because those registers are normally skipped. */
3235 /* MIPS_EABI squeezes a struct that contains a single floating
3236 point value into an FP register instead of pushing it onto the
3238 if (fp_register_arg_p (typecode
, arg_type
)
3239 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3241 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3243 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3244 unsigned long regval
;
3246 /* Write the low word of the double to the even register(s). */
3247 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3249 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3250 float_argreg
, phex (regval
, 4));
3251 write_register (float_argreg
++, regval
);
3253 /* Write the high word of the double to the odd register(s). */
3254 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3256 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3257 float_argreg
, phex (regval
, 4));
3258 write_register (float_argreg
++, regval
);
3262 /* This is a floating point value that fits entirely
3263 in a single register. */
3264 /* On 32 bit ABI's the float_argreg is further adjusted
3265 above to ensure that it is even register aligned. */
3266 LONGEST regval
= extract_unsigned_integer (val
, len
);
3268 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3269 float_argreg
, phex (regval
, len
));
3270 write_register (float_argreg
++, regval
);
3275 /* Copy the argument to general registers or the stack in
3276 register-sized pieces. Large arguments are split between
3277 registers and stack. */
3278 /* Note: structs whose size is not a multiple of
3279 mips_abi_regsize() are treated specially: Irix cc passes
3280 them in registers where gcc sometimes puts them on the
3281 stack. For maximum compatibility, we will put them in
3283 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3284 && (len
% mips_abi_regsize (gdbarch
) != 0));
3286 /* Note: Floating-point values that didn't fit into an FP
3287 register are only written to memory. */
3290 /* Remember if the argument was written to the stack. */
3291 int stack_used_p
= 0;
3292 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3293 ? len
: mips_abi_regsize (gdbarch
));
3296 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3299 /* Write this portion of the argument to the stack. */
3300 if (argreg
> MIPS_LAST_ARG_REGNUM
3302 || fp_register_arg_p (typecode
, arg_type
))
3304 /* Should shorter than int integer values be
3305 promoted to int before being stored? */
3306 int longword_offset
= 0;
3309 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3311 if (mips_stack_argsize (gdbarch
) == 8
3312 && (typecode
== TYPE_CODE_INT
3313 || typecode
== TYPE_CODE_PTR
3314 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3315 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3316 else if ((typecode
== TYPE_CODE_STRUCT
3317 || typecode
== TYPE_CODE_UNION
)
3318 && (TYPE_LENGTH (arg_type
)
3319 < mips_stack_argsize (gdbarch
)))
3320 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3325 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3326 paddr_nz (stack_offset
));
3327 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3328 paddr_nz (longword_offset
));
3331 addr
= sp
+ stack_offset
+ longword_offset
;
3336 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3338 for (i
= 0; i
< partial_len
; i
++)
3340 fprintf_unfiltered (gdb_stdlog
, "%02x",
3344 write_memory (addr
, val
, partial_len
);
3347 /* Note!!! This is NOT an else clause. Odd sized
3348 structs may go thru BOTH paths. Floating point
3349 arguments will not. */
3350 /* Write this portion of the argument to a general
3351 purpose register. */
3352 if (argreg
<= MIPS_LAST_ARG_REGNUM
3353 && !fp_register_arg_p (typecode
, arg_type
))
3356 extract_unsigned_integer (val
, partial_len
);
3359 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3362 mips_abi_regsize (gdbarch
)));
3363 write_register (argreg
, regval
);
3370 /* Compute the the offset into the stack at which we
3371 will copy the next parameter.
3373 In the new EABI (and the NABI32), the stack_offset
3374 only needs to be adjusted when it has been used. */
3377 stack_offset
+= align_up (partial_len
,
3378 mips_stack_argsize (gdbarch
));
3382 fprintf_unfiltered (gdb_stdlog
, "\n");
3385 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3387 /* Return adjusted stack pointer. */
3391 /* Given a return value in `regbuf' with a type `valtype', extract and
3392 copy its value into `valbuf'. */
3395 mips_eabi_extract_return_value (struct type
*valtype
,
3396 char regbuf
[], char *valbuf
)
3398 struct return_value_word lo
;
3399 struct return_value_word hi
;
3400 return_value_location (valtype
, &hi
, &lo
);
3402 memcpy (valbuf
+ lo
.buf_offset
,
3403 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3404 lo
.reg_offset
, lo
.len
);
3407 memcpy (valbuf
+ hi
.buf_offset
,
3408 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3409 hi
.reg_offset
, hi
.len
);
3412 /* Given a return value in `valbuf' with a type `valtype', write it's
3413 value into the appropriate register. */
3416 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3418 char raw_buffer
[MAX_REGISTER_SIZE
];
3419 struct return_value_word lo
;
3420 struct return_value_word hi
;
3421 return_value_location (valtype
, &hi
, &lo
);
3423 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3424 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3425 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3426 raw_buffer
, register_size (current_gdbarch
,
3431 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3432 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3433 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3435 register_size (current_gdbarch
,
3440 /* N32/N64 ABI stuff. */
3443 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3444 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3445 int nargs
, struct value
**args
, CORE_ADDR sp
,
3446 int struct_return
, CORE_ADDR struct_addr
)
3452 int stack_offset
= 0;
3453 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3454 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3456 /* For shared libraries, "t9" needs to point at the function
3458 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3460 /* Set the return address register to point to the entry point of
3461 the program, where a breakpoint lies in wait. */
3462 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3464 /* First ensure that the stack and structure return address (if any)
3465 are properly aligned. The stack has to be at least 64-bit
3466 aligned even on 32-bit machines, because doubles must be 64-bit
3467 aligned. For n32 and n64, stack frames need to be 128-bit
3468 aligned, so we round to this widest known alignment. */
3470 sp
= align_down (sp
, 16);
3471 struct_addr
= align_down (struct_addr
, 16);
3473 /* Now make space on the stack for the args. */
3474 for (argnum
= 0; argnum
< nargs
; argnum
++)
3475 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3476 mips_stack_argsize (gdbarch
));
3477 sp
-= align_up (len
, 16);
3480 fprintf_unfiltered (gdb_stdlog
,
3481 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3482 paddr_nz (sp
), (long) align_up (len
, 16));
3484 /* Initialize the integer and float register pointers. */
3486 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3488 /* The struct_return pointer occupies the first parameter-passing reg. */
3492 fprintf_unfiltered (gdb_stdlog
,
3493 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3494 argreg
, paddr_nz (struct_addr
));
3495 write_register (argreg
++, struct_addr
);
3498 /* Now load as many as possible of the first arguments into
3499 registers, and push the rest onto the stack. Loop thru args
3500 from first to last. */
3501 for (argnum
= 0; argnum
< nargs
; argnum
++)
3504 struct value
*arg
= args
[argnum
];
3505 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3506 int len
= TYPE_LENGTH (arg_type
);
3507 enum type_code typecode
= TYPE_CODE (arg_type
);
3510 fprintf_unfiltered (gdb_stdlog
,
3511 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3512 argnum
+ 1, len
, (int) typecode
);
3514 val
= (char *) VALUE_CONTENTS (arg
);
3516 if (fp_register_arg_p (typecode
, arg_type
)
3517 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3519 /* This is a floating point value that fits entirely
3520 in a single register. */
3521 /* On 32 bit ABI's the float_argreg is further adjusted
3522 above to ensure that it is even register aligned. */
3523 LONGEST regval
= extract_unsigned_integer (val
, len
);
3525 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3526 float_argreg
, phex (regval
, len
));
3527 write_register (float_argreg
++, regval
);
3530 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3531 argreg
, phex (regval
, len
));
3532 write_register (argreg
, regval
);
3537 /* Copy the argument to general registers or the stack in
3538 register-sized pieces. Large arguments are split between
3539 registers and stack. */
3540 /* Note: structs whose size is not a multiple of
3541 mips_abi_regsize() are treated specially: Irix cc passes
3542 them in registers where gcc sometimes puts them on the
3543 stack. For maximum compatibility, we will put them in
3545 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3546 && (len
% mips_abi_regsize (gdbarch
) != 0));
3547 /* Note: Floating-point values that didn't fit into an FP
3548 register are only written to memory. */
3551 /* Rememer if the argument was written to the stack. */
3552 int stack_used_p
= 0;
3553 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3554 ? len
: mips_abi_regsize (gdbarch
));
3557 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3560 /* Write this portion of the argument to the stack. */
3561 if (argreg
> MIPS_LAST_ARG_REGNUM
3563 || fp_register_arg_p (typecode
, arg_type
))
3565 /* Should shorter than int integer values be
3566 promoted to int before being stored? */
3567 int longword_offset
= 0;
3570 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3572 if (mips_stack_argsize (gdbarch
) == 8
3573 && (typecode
== TYPE_CODE_INT
3574 || typecode
== TYPE_CODE_PTR
3575 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3576 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3581 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3582 paddr_nz (stack_offset
));
3583 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3584 paddr_nz (longword_offset
));
3587 addr
= sp
+ stack_offset
+ longword_offset
;
3592 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3594 for (i
= 0; i
< partial_len
; i
++)
3596 fprintf_unfiltered (gdb_stdlog
, "%02x",
3600 write_memory (addr
, val
, partial_len
);
3603 /* Note!!! This is NOT an else clause. Odd sized
3604 structs may go thru BOTH paths. Floating point
3605 arguments will not. */
3606 /* Write this portion of the argument to a general
3607 purpose register. */
3608 if (argreg
<= MIPS_LAST_ARG_REGNUM
3609 && !fp_register_arg_p (typecode
, arg_type
))
3612 extract_unsigned_integer (val
, partial_len
);
3614 /* A non-floating-point argument being passed in a
3615 general register. If a struct or union, and if
3616 the remaining length is smaller than the register
3617 size, we have to adjust the register value on
3620 It does not seem to be necessary to do the
3621 same for integral types.
3623 cagney/2001-07-23: gdb/179: Also, GCC, when
3624 outputting LE O32 with sizeof (struct) <
3625 mips_abi_regsize(), generates a left shift as
3626 part of storing the argument in a register a
3627 register (the left shift isn't generated when
3628 sizeof (struct) >= mips_abi_regsize()). Since
3629 it is quite possible that this is GCC
3630 contradicting the LE/O32 ABI, GDB has not been
3631 adjusted to accommodate this. Either someone
3632 needs to demonstrate that the LE/O32 ABI
3633 specifies such a left shift OR this new ABI gets
3634 identified as such and GDB gets tweaked
3637 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3638 && partial_len
< mips_abi_regsize (gdbarch
)
3639 && (typecode
== TYPE_CODE_STRUCT
||
3640 typecode
== TYPE_CODE_UNION
))
3641 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3645 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3648 mips_abi_regsize (gdbarch
)));
3649 write_register (argreg
, regval
);
3656 /* Compute the the offset into the stack at which we
3657 will copy the next parameter.
3659 In N32 (N64?), the stack_offset only needs to be
3660 adjusted when it has been used. */
3663 stack_offset
+= align_up (partial_len
,
3664 mips_stack_argsize (gdbarch
));
3668 fprintf_unfiltered (gdb_stdlog
, "\n");
3671 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3673 /* Return adjusted stack pointer. */
3677 static enum return_value_convention
3678 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3679 struct type
*type
, struct regcache
*regcache
,
3680 void *readbuf
, const void *writebuf
)
3682 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3683 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3684 || TYPE_CODE (type
) == TYPE_CODE_UNION
3685 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3686 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3687 return RETURN_VALUE_STRUCT_CONVENTION
;
3688 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3689 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3691 /* A floating-point value belongs in the least significant part
3694 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3695 mips_xfer_register (regcache
,
3696 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3698 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3699 return RETURN_VALUE_REGISTER_CONVENTION
;
3701 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3702 && TYPE_NFIELDS (type
) <= 2
3703 && TYPE_NFIELDS (type
) >= 1
3704 && ((TYPE_NFIELDS (type
) == 1
3705 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3707 || (TYPE_NFIELDS (type
) == 2
3708 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3710 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3712 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3714 /* A struct that contains one or two floats. Each value is part
3715 in the least significant part of their floating point
3719 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3720 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3722 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3725 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3727 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3728 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3729 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3731 return RETURN_VALUE_REGISTER_CONVENTION
;
3733 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3734 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3736 /* A structure or union. Extract the left justified value,
3737 regardless of the byte order. I.e. DO NOT USE
3741 for (offset
= 0, regnum
= V0_REGNUM
;
3742 offset
< TYPE_LENGTH (type
);
3743 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3745 int xfer
= register_size (current_gdbarch
, regnum
);
3746 if (offset
+ xfer
> TYPE_LENGTH (type
))
3747 xfer
= TYPE_LENGTH (type
) - offset
;
3749 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3750 offset
, xfer
, regnum
);
3751 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3752 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3754 return RETURN_VALUE_REGISTER_CONVENTION
;
3758 /* A scalar extract each part but least-significant-byte
3762 for (offset
= 0, regnum
= V0_REGNUM
;
3763 offset
< TYPE_LENGTH (type
);
3764 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3766 int xfer
= register_size (current_gdbarch
, regnum
);
3767 if (offset
+ xfer
> TYPE_LENGTH (type
))
3768 xfer
= TYPE_LENGTH (type
) - offset
;
3770 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3771 offset
, xfer
, regnum
);
3772 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3773 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3775 return RETURN_VALUE_REGISTER_CONVENTION
;
3779 /* O32 ABI stuff. */
3782 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3783 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3784 int nargs
, struct value
**args
, CORE_ADDR sp
,
3785 int struct_return
, CORE_ADDR struct_addr
)
3791 int stack_offset
= 0;
3792 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3793 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3795 /* For shared libraries, "t9" needs to point at the function
3797 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3799 /* Set the return address register to point to the entry point of
3800 the program, where a breakpoint lies in wait. */
3801 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3803 /* First ensure that the stack and structure return address (if any)
3804 are properly aligned. The stack has to be at least 64-bit
3805 aligned even on 32-bit machines, because doubles must be 64-bit
3806 aligned. For n32 and n64, stack frames need to be 128-bit
3807 aligned, so we round to this widest known alignment. */
3809 sp
= align_down (sp
, 16);
3810 struct_addr
= align_down (struct_addr
, 16);
3812 /* Now make space on the stack for the args. */
3813 for (argnum
= 0; argnum
< nargs
; argnum
++)
3814 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3815 mips_stack_argsize (gdbarch
));
3816 sp
-= align_up (len
, 16);
3819 fprintf_unfiltered (gdb_stdlog
,
3820 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3821 paddr_nz (sp
), (long) align_up (len
, 16));
3823 /* Initialize the integer and float register pointers. */
3825 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3827 /* The struct_return pointer occupies the first parameter-passing reg. */
3831 fprintf_unfiltered (gdb_stdlog
,
3832 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3833 argreg
, paddr_nz (struct_addr
));
3834 write_register (argreg
++, struct_addr
);
3835 stack_offset
+= mips_stack_argsize (gdbarch
);
3838 /* Now load as many as possible of the first arguments into
3839 registers, and push the rest onto the stack. Loop thru args
3840 from first to last. */
3841 for (argnum
= 0; argnum
< nargs
; argnum
++)
3844 struct value
*arg
= args
[argnum
];
3845 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3846 int len
= TYPE_LENGTH (arg_type
);
3847 enum type_code typecode
= TYPE_CODE (arg_type
);
3850 fprintf_unfiltered (gdb_stdlog
,
3851 "mips_o32_push_dummy_call: %d len=%d type=%d",
3852 argnum
+ 1, len
, (int) typecode
);
3854 val
= (char *) VALUE_CONTENTS (arg
);
3856 /* 32-bit ABIs always start floating point arguments in an
3857 even-numbered floating point register. Round the FP register
3858 up before the check to see if there are any FP registers
3859 left. O32/O64 targets also pass the FP in the integer
3860 registers so also round up normal registers. */
3861 if (mips_abi_regsize (gdbarch
) < 8
3862 && fp_register_arg_p (typecode
, arg_type
))
3864 if ((float_argreg
& 1))
3868 /* Floating point arguments passed in registers have to be
3869 treated specially. On 32-bit architectures, doubles
3870 are passed in register pairs; the even register gets
3871 the low word, and the odd register gets the high word.
3872 On O32/O64, the first two floating point arguments are
3873 also copied to general registers, because MIPS16 functions
3874 don't use float registers for arguments. This duplication of
3875 arguments in general registers can't hurt non-MIPS16 functions
3876 because those registers are normally skipped. */
3878 if (fp_register_arg_p (typecode
, arg_type
)
3879 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3881 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3883 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3884 unsigned long regval
;
3886 /* Write the low word of the double to the even register(s). */
3887 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3889 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3890 float_argreg
, phex (regval
, 4));
3891 write_register (float_argreg
++, regval
);
3893 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3894 argreg
, phex (regval
, 4));
3895 write_register (argreg
++, regval
);
3897 /* Write the high word of the double to the odd register(s). */
3898 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3900 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3901 float_argreg
, phex (regval
, 4));
3902 write_register (float_argreg
++, regval
);
3905 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3906 argreg
, phex (regval
, 4));
3907 write_register (argreg
++, regval
);
3911 /* This is a floating point value that fits entirely
3912 in a single register. */
3913 /* On 32 bit ABI's the float_argreg is further adjusted
3914 above to ensure that it is even register aligned. */
3915 LONGEST regval
= extract_unsigned_integer (val
, len
);
3917 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3918 float_argreg
, phex (regval
, len
));
3919 write_register (float_argreg
++, regval
);
3920 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3921 registers for each argument. The below is (my
3922 guess) to ensure that the corresponding integer
3923 register has reserved the same space. */
3925 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3926 argreg
, phex (regval
, len
));
3927 write_register (argreg
, regval
);
3928 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3930 /* Reserve space for the FP register. */
3931 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3935 /* Copy the argument to general registers or the stack in
3936 register-sized pieces. Large arguments are split between
3937 registers and stack. */
3938 /* Note: structs whose size is not a multiple of
3939 mips_abi_regsize() are treated specially: Irix cc passes
3940 them in registers where gcc sometimes puts them on the
3941 stack. For maximum compatibility, we will put them in
3943 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3944 && (len
% mips_abi_regsize (gdbarch
) != 0));
3945 /* Structures should be aligned to eight bytes (even arg registers)
3946 on MIPS_ABI_O32, if their first member has double precision. */
3947 if (mips_abi_regsize (gdbarch
) < 8
3948 && mips_type_needs_double_align (arg_type
))
3953 /* Note: Floating-point values that didn't fit into an FP
3954 register are only written to memory. */
3957 /* Remember if the argument was written to the stack. */
3958 int stack_used_p
= 0;
3959 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3960 ? len
: mips_abi_regsize (gdbarch
));
3963 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3966 /* Write this portion of the argument to the stack. */
3967 if (argreg
> MIPS_LAST_ARG_REGNUM
3969 || fp_register_arg_p (typecode
, arg_type
))
3971 /* Should shorter than int integer values be
3972 promoted to int before being stored? */
3973 int longword_offset
= 0;
3976 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3978 if (mips_stack_argsize (gdbarch
) == 8
3979 && (typecode
== TYPE_CODE_INT
3980 || typecode
== TYPE_CODE_PTR
3981 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3982 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3987 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3988 paddr_nz (stack_offset
));
3989 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3990 paddr_nz (longword_offset
));
3993 addr
= sp
+ stack_offset
+ longword_offset
;
3998 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4000 for (i
= 0; i
< partial_len
; i
++)
4002 fprintf_unfiltered (gdb_stdlog
, "%02x",
4006 write_memory (addr
, val
, partial_len
);
4009 /* Note!!! This is NOT an else clause. Odd sized
4010 structs may go thru BOTH paths. Floating point
4011 arguments will not. */
4012 /* Write this portion of the argument to a general
4013 purpose register. */
4014 if (argreg
<= MIPS_LAST_ARG_REGNUM
4015 && !fp_register_arg_p (typecode
, arg_type
))
4017 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4018 /* Value may need to be sign extended, because
4019 mips_isa_regsize() != mips_abi_regsize(). */
4021 /* A non-floating-point argument being passed in a
4022 general register. If a struct or union, and if
4023 the remaining length is smaller than the register
4024 size, we have to adjust the register value on
4027 It does not seem to be necessary to do the
4028 same for integral types.
4030 Also don't do this adjustment on O64 binaries.
4032 cagney/2001-07-23: gdb/179: Also, GCC, when
4033 outputting LE O32 with sizeof (struct) <
4034 mips_abi_regsize(), generates a left shift as
4035 part of storing the argument in a register a
4036 register (the left shift isn't generated when
4037 sizeof (struct) >= mips_abi_regsize()). Since
4038 it is quite possible that this is GCC
4039 contradicting the LE/O32 ABI, GDB has not been
4040 adjusted to accommodate this. Either someone
4041 needs to demonstrate that the LE/O32 ABI
4042 specifies such a left shift OR this new ABI gets
4043 identified as such and GDB gets tweaked
4046 if (mips_abi_regsize (gdbarch
) < 8
4047 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4048 && partial_len
< mips_abi_regsize (gdbarch
)
4049 && (typecode
== TYPE_CODE_STRUCT
||
4050 typecode
== TYPE_CODE_UNION
))
4051 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4055 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4058 mips_abi_regsize (gdbarch
)));
4059 write_register (argreg
, regval
);
4062 /* Prevent subsequent floating point arguments from
4063 being passed in floating point registers. */
4064 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4070 /* Compute the the offset into the stack at which we
4071 will copy the next parameter.
4073 In older ABIs, the caller reserved space for
4074 registers that contained arguments. This was loosely
4075 refered to as their "home". Consequently, space is
4076 always allocated. */
4078 stack_offset
+= align_up (partial_len
,
4079 mips_stack_argsize (gdbarch
));
4083 fprintf_unfiltered (gdb_stdlog
, "\n");
4086 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4088 /* Return adjusted stack pointer. */
4092 static enum return_value_convention
4093 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4094 struct regcache
*regcache
,
4095 void *readbuf
, const void *writebuf
)
4097 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4099 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4100 || TYPE_CODE (type
) == TYPE_CODE_UNION
4101 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4102 return RETURN_VALUE_STRUCT_CONVENTION
;
4103 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4104 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4106 /* A single-precision floating-point value. It fits in the
4107 least significant part of FP0. */
4109 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4110 mips_xfer_register (regcache
,
4111 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4113 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4114 return RETURN_VALUE_REGISTER_CONVENTION
;
4116 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4117 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4119 /* A double-precision floating-point value. The most
4120 significant part goes in FP1, and the least significant in
4123 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4124 switch (TARGET_BYTE_ORDER
)
4126 case BFD_ENDIAN_LITTLE
:
4127 mips_xfer_register (regcache
,
4128 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4129 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4130 mips_xfer_register (regcache
,
4131 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4132 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4134 case BFD_ENDIAN_BIG
:
4135 mips_xfer_register (regcache
,
4136 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4137 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4138 mips_xfer_register (regcache
,
4139 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4140 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4143 internal_error (__FILE__
, __LINE__
, "bad switch");
4145 return RETURN_VALUE_REGISTER_CONVENTION
;
4148 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4149 && TYPE_NFIELDS (type
) <= 2
4150 && TYPE_NFIELDS (type
) >= 1
4151 && ((TYPE_NFIELDS (type
) == 1
4152 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4154 || (TYPE_NFIELDS (type
) == 2
4155 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4157 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4159 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4161 /* A struct that contains one or two floats. Each value is part
4162 in the least significant part of their floating point
4164 bfd_byte reg
[MAX_REGISTER_SIZE
];
4167 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4168 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4170 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4173 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4175 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4176 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4177 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4179 return RETURN_VALUE_REGISTER_CONVENTION
;
4183 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4184 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4186 /* A structure or union. Extract the left justified value,
4187 regardless of the byte order. I.e. DO NOT USE
4191 for (offset
= 0, regnum
= V0_REGNUM
;
4192 offset
< TYPE_LENGTH (type
);
4193 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4195 int xfer
= register_size (current_gdbarch
, regnum
);
4196 if (offset
+ xfer
> TYPE_LENGTH (type
))
4197 xfer
= TYPE_LENGTH (type
) - offset
;
4199 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4200 offset
, xfer
, regnum
);
4201 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4202 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4204 return RETURN_VALUE_REGISTER_CONVENTION
;
4209 /* A scalar extract each part but least-significant-byte
4210 justified. o32 thinks registers are 4 byte, regardless of
4211 the ISA. mips_stack_argsize controls this. */
4214 for (offset
= 0, regnum
= V0_REGNUM
;
4215 offset
< TYPE_LENGTH (type
);
4216 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
4218 int xfer
= mips_stack_argsize (gdbarch
);
4219 if (offset
+ xfer
> TYPE_LENGTH (type
))
4220 xfer
= TYPE_LENGTH (type
) - offset
;
4222 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4223 offset
, xfer
, regnum
);
4224 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4225 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4227 return RETURN_VALUE_REGISTER_CONVENTION
;
4231 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4235 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4236 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4238 struct value
**args
, CORE_ADDR sp
,
4239 int struct_return
, CORE_ADDR struct_addr
)
4245 int stack_offset
= 0;
4246 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4247 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4249 /* For shared libraries, "t9" needs to point at the function
4251 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4253 /* Set the return address register to point to the entry point of
4254 the program, where a breakpoint lies in wait. */
4255 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4257 /* First ensure that the stack and structure return address (if any)
4258 are properly aligned. The stack has to be at least 64-bit
4259 aligned even on 32-bit machines, because doubles must be 64-bit
4260 aligned. For n32 and n64, stack frames need to be 128-bit
4261 aligned, so we round to this widest known alignment. */
4263 sp
= align_down (sp
, 16);
4264 struct_addr
= align_down (struct_addr
, 16);
4266 /* Now make space on the stack for the args. */
4267 for (argnum
= 0; argnum
< nargs
; argnum
++)
4268 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4269 mips_stack_argsize (gdbarch
));
4270 sp
-= align_up (len
, 16);
4273 fprintf_unfiltered (gdb_stdlog
,
4274 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4275 paddr_nz (sp
), (long) align_up (len
, 16));
4277 /* Initialize the integer and float register pointers. */
4279 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4281 /* The struct_return pointer occupies the first parameter-passing reg. */
4285 fprintf_unfiltered (gdb_stdlog
,
4286 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4287 argreg
, paddr_nz (struct_addr
));
4288 write_register (argreg
++, struct_addr
);
4289 stack_offset
+= mips_stack_argsize (gdbarch
);
4292 /* Now load as many as possible of the first arguments into
4293 registers, and push the rest onto the stack. Loop thru args
4294 from first to last. */
4295 for (argnum
= 0; argnum
< nargs
; argnum
++)
4298 struct value
*arg
= args
[argnum
];
4299 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4300 int len
= TYPE_LENGTH (arg_type
);
4301 enum type_code typecode
= TYPE_CODE (arg_type
);
4304 fprintf_unfiltered (gdb_stdlog
,
4305 "mips_o64_push_dummy_call: %d len=%d type=%d",
4306 argnum
+ 1, len
, (int) typecode
);
4308 val
= (char *) VALUE_CONTENTS (arg
);
4310 /* 32-bit ABIs always start floating point arguments in an
4311 even-numbered floating point register. Round the FP register
4312 up before the check to see if there are any FP registers
4313 left. O32/O64 targets also pass the FP in the integer
4314 registers so also round up normal registers. */
4315 if (mips_abi_regsize (gdbarch
) < 8
4316 && fp_register_arg_p (typecode
, arg_type
))
4318 if ((float_argreg
& 1))
4322 /* Floating point arguments passed in registers have to be
4323 treated specially. On 32-bit architectures, doubles
4324 are passed in register pairs; the even register gets
4325 the low word, and the odd register gets the high word.
4326 On O32/O64, the first two floating point arguments are
4327 also copied to general registers, because MIPS16 functions
4328 don't use float registers for arguments. This duplication of
4329 arguments in general registers can't hurt non-MIPS16 functions
4330 because those registers are normally skipped. */
4332 if (fp_register_arg_p (typecode
, arg_type
)
4333 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4335 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4337 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4338 unsigned long regval
;
4340 /* Write the low word of the double to the even register(s). */
4341 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4343 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4344 float_argreg
, phex (regval
, 4));
4345 write_register (float_argreg
++, regval
);
4347 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4348 argreg
, phex (regval
, 4));
4349 write_register (argreg
++, regval
);
4351 /* Write the high word of the double to the odd register(s). */
4352 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4354 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4355 float_argreg
, phex (regval
, 4));
4356 write_register (float_argreg
++, regval
);
4359 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4360 argreg
, phex (regval
, 4));
4361 write_register (argreg
++, regval
);
4365 /* This is a floating point value that fits entirely
4366 in a single register. */
4367 /* On 32 bit ABI's the float_argreg is further adjusted
4368 above to ensure that it is even register aligned. */
4369 LONGEST regval
= extract_unsigned_integer (val
, len
);
4371 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4372 float_argreg
, phex (regval
, len
));
4373 write_register (float_argreg
++, regval
);
4374 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4375 registers for each argument. The below is (my
4376 guess) to ensure that the corresponding integer
4377 register has reserved the same space. */
4379 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4380 argreg
, phex (regval
, len
));
4381 write_register (argreg
, regval
);
4382 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4384 /* Reserve space for the FP register. */
4385 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4389 /* Copy the argument to general registers or the stack in
4390 register-sized pieces. Large arguments are split between
4391 registers and stack. */
4392 /* Note: structs whose size is not a multiple of
4393 mips_abi_regsize() are treated specially: Irix cc passes
4394 them in registers where gcc sometimes puts them on the
4395 stack. For maximum compatibility, we will put them in
4397 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4398 && (len
% mips_abi_regsize (gdbarch
) != 0));
4399 /* Structures should be aligned to eight bytes (even arg registers)
4400 on MIPS_ABI_O32, if their first member has double precision. */
4401 if (mips_abi_regsize (gdbarch
) < 8
4402 && mips_type_needs_double_align (arg_type
))
4407 /* Note: Floating-point values that didn't fit into an FP
4408 register are only written to memory. */
4411 /* Remember if the argument was written to the stack. */
4412 int stack_used_p
= 0;
4413 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4414 ? len
: mips_abi_regsize (gdbarch
));
4417 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4420 /* Write this portion of the argument to the stack. */
4421 if (argreg
> MIPS_LAST_ARG_REGNUM
4423 || fp_register_arg_p (typecode
, arg_type
))
4425 /* Should shorter than int integer values be
4426 promoted to int before being stored? */
4427 int longword_offset
= 0;
4430 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4432 if (mips_stack_argsize (gdbarch
) == 8
4433 && (typecode
== TYPE_CODE_INT
4434 || typecode
== TYPE_CODE_PTR
4435 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4436 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4441 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4442 paddr_nz (stack_offset
));
4443 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4444 paddr_nz (longword_offset
));
4447 addr
= sp
+ stack_offset
+ longword_offset
;
4452 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4454 for (i
= 0; i
< partial_len
; i
++)
4456 fprintf_unfiltered (gdb_stdlog
, "%02x",
4460 write_memory (addr
, val
, partial_len
);
4463 /* Note!!! This is NOT an else clause. Odd sized
4464 structs may go thru BOTH paths. Floating point
4465 arguments will not. */
4466 /* Write this portion of the argument to a general
4467 purpose register. */
4468 if (argreg
<= MIPS_LAST_ARG_REGNUM
4469 && !fp_register_arg_p (typecode
, arg_type
))
4471 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4472 /* Value may need to be sign extended, because
4473 mips_isa_regsize() != mips_abi_regsize(). */
4475 /* A non-floating-point argument being passed in a
4476 general register. If a struct or union, and if
4477 the remaining length is smaller than the register
4478 size, we have to adjust the register value on
4481 It does not seem to be necessary to do the
4482 same for integral types.
4484 Also don't do this adjustment on O64 binaries.
4486 cagney/2001-07-23: gdb/179: Also, GCC, when
4487 outputting LE O32 with sizeof (struct) <
4488 mips_abi_regsize(), generates a left shift as
4489 part of storing the argument in a register a
4490 register (the left shift isn't generated when
4491 sizeof (struct) >= mips_abi_regsize()). Since
4492 it is quite possible that this is GCC
4493 contradicting the LE/O32 ABI, GDB has not been
4494 adjusted to accommodate this. Either someone
4495 needs to demonstrate that the LE/O32 ABI
4496 specifies such a left shift OR this new ABI gets
4497 identified as such and GDB gets tweaked
4500 if (mips_abi_regsize (gdbarch
) < 8
4501 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4502 && partial_len
< mips_abi_regsize (gdbarch
)
4503 && (typecode
== TYPE_CODE_STRUCT
||
4504 typecode
== TYPE_CODE_UNION
))
4505 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4509 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4512 mips_abi_regsize (gdbarch
)));
4513 write_register (argreg
, regval
);
4516 /* Prevent subsequent floating point arguments from
4517 being passed in floating point registers. */
4518 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4524 /* Compute the the offset into the stack at which we
4525 will copy the next parameter.
4527 In older ABIs, the caller reserved space for
4528 registers that contained arguments. This was loosely
4529 refered to as their "home". Consequently, space is
4530 always allocated. */
4532 stack_offset
+= align_up (partial_len
,
4533 mips_stack_argsize (gdbarch
));
4537 fprintf_unfiltered (gdb_stdlog
, "\n");
4540 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4542 /* Return adjusted stack pointer. */
4547 mips_o64_extract_return_value (struct type
*valtype
,
4548 char regbuf
[], char *valbuf
)
4550 struct return_value_word lo
;
4551 struct return_value_word hi
;
4552 return_value_location (valtype
, &hi
, &lo
);
4554 memcpy (valbuf
+ lo
.buf_offset
,
4555 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4556 lo
.reg_offset
, lo
.len
);
4559 memcpy (valbuf
+ hi
.buf_offset
,
4560 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4561 hi
.reg_offset
, hi
.len
);
4565 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4567 char raw_buffer
[MAX_REGISTER_SIZE
];
4568 struct return_value_word lo
;
4569 struct return_value_word hi
;
4570 return_value_location (valtype
, &hi
, &lo
);
4572 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4573 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4574 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4575 raw_buffer
, register_size (current_gdbarch
,
4580 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4581 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4582 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4584 register_size (current_gdbarch
,
4589 /* Floating point register management.
4591 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4592 64bit operations, these early MIPS cpus treat fp register pairs
4593 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4594 registers and offer a compatibility mode that emulates the MIPS2 fp
4595 model. When operating in MIPS2 fp compat mode, later cpu's split
4596 double precision floats into two 32-bit chunks and store them in
4597 consecutive fp regs. To display 64-bit floats stored in this
4598 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4599 Throw in user-configurable endianness and you have a real mess.
4601 The way this works is:
4602 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4603 double-precision value will be split across two logical registers.
4604 The lower-numbered logical register will hold the low-order bits,
4605 regardless of the processor's endianness.
4606 - If we are on a 64-bit processor, and we are looking for a
4607 single-precision value, it will be in the low ordered bits
4608 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4609 save slot in memory.
4610 - If we are in 64-bit mode, everything is straightforward.
4612 Note that this code only deals with "live" registers at the top of the
4613 stack. We will attempt to deal with saved registers later, when
4614 the raw/cooked register interface is in place. (We need a general
4615 interface that can deal with dynamic saved register sizes -- fp
4616 regs could be 32 bits wide in one frame and 64 on the frame above
4619 static struct type
*
4620 mips_float_register_type (void)
4622 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4623 return builtin_type_ieee_single_big
;
4625 return builtin_type_ieee_single_little
;
4628 static struct type
*
4629 mips_double_register_type (void)
4631 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4632 return builtin_type_ieee_double_big
;
4634 return builtin_type_ieee_double_little
;
4637 /* Copy a 32-bit single-precision value from the current frame
4638 into rare_buffer. */
4641 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4644 int raw_size
= register_size (current_gdbarch
, regno
);
4645 char *raw_buffer
= alloca (raw_size
);
4647 if (!frame_register_read (frame
, regno
, raw_buffer
))
4648 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4651 /* We have a 64-bit value for this register. Find the low-order
4655 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4660 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4664 memcpy (rare_buffer
, raw_buffer
, 4);
4668 /* Copy a 64-bit double-precision value from the current frame into
4669 rare_buffer. This may include getting half of it from the next
4673 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4676 int raw_size
= register_size (current_gdbarch
, regno
);
4678 if (raw_size
== 8 && !mips2_fp_compat ())
4680 /* We have a 64-bit value for this register, and we should use
4682 if (!frame_register_read (frame
, regno
, rare_buffer
))
4683 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4687 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4688 internal_error (__FILE__
, __LINE__
,
4689 "mips_read_fp_register_double: bad access to "
4690 "odd-numbered FP register");
4692 /* mips_read_fp_register_single will find the correct 32 bits from
4694 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4696 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4697 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4701 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4702 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4708 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4710 { /* do values for FP (float) regs */
4712 double doub
, flt1
; /* doubles extracted from raw hex data */
4716 (char *) alloca (2 *
4717 register_size (current_gdbarch
,
4718 mips_regnum (current_gdbarch
)->fp0
));
4720 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4721 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4724 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4726 /* 4-byte registers: Print hex and floating. Also print even
4727 numbered registers as doubles. */
4728 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4729 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4731 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4734 fprintf_filtered (file
, " flt: ");
4736 fprintf_filtered (file
, " <invalid float> ");
4738 fprintf_filtered (file
, "%-17.9g", flt1
);
4740 if (regnum
% 2 == 0)
4742 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4743 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4746 fprintf_filtered (file
, " dbl: ");
4748 fprintf_filtered (file
, "<invalid double>");
4750 fprintf_filtered (file
, "%-24.17g", doub
);
4755 /* Eight byte registers: print each one as hex, float and double. */
4756 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4757 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4759 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4760 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4763 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4766 fprintf_filtered (file
, " flt: ");
4768 fprintf_filtered (file
, "<invalid float>");
4770 fprintf_filtered (file
, "%-17.9g", flt1
);
4772 fprintf_filtered (file
, " dbl: ");
4774 fprintf_filtered (file
, "<invalid double>");
4776 fprintf_filtered (file
, "%-24.17g", doub
);
4781 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4782 int regnum
, int all
)
4784 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4785 char raw_buffer
[MAX_REGISTER_SIZE
];
4788 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4790 mips_print_fp_register (file
, frame
, regnum
);
4794 /* Get the data in raw format. */
4795 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4797 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4801 fputs_filtered (REGISTER_NAME (regnum
), file
);
4803 /* The problem with printing numeric register names (r26, etc.) is that
4804 the user can't use them on input. Probably the best solution is to
4805 fix it so that either the numeric or the funky (a2, etc.) names
4806 are accepted on input. */
4807 if (regnum
< MIPS_NUMREGS
)
4808 fprintf_filtered (file
, "(r%d): ", regnum
);
4810 fprintf_filtered (file
, ": ");
4812 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4814 register_size (current_gdbarch
,
4815 regnum
) - register_size (current_gdbarch
, regnum
);
4819 print_scalar_formatted (raw_buffer
+ offset
,
4820 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4824 /* Replacement for generic do_registers_info.
4825 Print regs in pretty columns. */
4828 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4831 fprintf_filtered (file
, " ");
4832 mips_print_fp_register (file
, frame
, regnum
);
4833 fprintf_filtered (file
, "\n");
4838 /* Print a row's worth of GP (int) registers, with name labels above */
4841 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4844 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4845 /* do values for GP (int) regs */
4846 char raw_buffer
[MAX_REGISTER_SIZE
];
4847 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4851 /* For GP registers, we print a separate row of names above the vals */
4852 fprintf_filtered (file
, " ");
4853 for (col
= 0, regnum
= start_regnum
;
4854 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4856 if (*REGISTER_NAME (regnum
) == '\0')
4857 continue; /* unused register */
4858 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4860 break; /* end the row: reached FP register */
4861 fprintf_filtered (file
,
4862 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4863 REGISTER_NAME (regnum
));
4866 /* print the R0 to R31 names */
4867 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4868 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4870 fprintf_filtered (file
, "\n ");
4872 /* now print the values in hex, 4 or 8 to the row */
4873 for (col
= 0, regnum
= start_regnum
;
4874 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4876 if (*REGISTER_NAME (regnum
) == '\0')
4877 continue; /* unused register */
4878 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4880 break; /* end row: reached FP register */
4881 /* OK: get the data in raw format. */
4882 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4883 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4884 /* pad small registers */
4886 byte
< (mips_abi_regsize (current_gdbarch
)
4887 - register_size (current_gdbarch
, regnum
)); byte
++)
4888 printf_filtered (" ");
4889 /* Now print the register value in hex, endian order. */
4890 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4892 register_size (current_gdbarch
,
4893 regnum
) - register_size (current_gdbarch
, regnum
);
4894 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4895 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4897 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4899 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4900 fprintf_filtered (file
, " ");
4903 if (col
> 0) /* ie. if we actually printed anything... */
4904 fprintf_filtered (file
, "\n");
4909 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4912 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4913 struct frame_info
*frame
, int regnum
, int all
)
4915 if (regnum
!= -1) /* do one specified register */
4917 gdb_assert (regnum
>= NUM_REGS
);
4918 if (*(REGISTER_NAME (regnum
)) == '\0')
4919 error ("Not a valid register for the current processor type");
4921 mips_print_register (file
, frame
, regnum
, 0);
4922 fprintf_filtered (file
, "\n");
4925 /* do all (or most) registers */
4928 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4930 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4933 if (all
) /* true for "INFO ALL-REGISTERS" command */
4934 regnum
= print_fp_register_row (file
, frame
, regnum
);
4936 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4939 regnum
= print_gp_register_row (file
, frame
, regnum
);
4944 /* Is this a branch with a delay slot? */
4946 static int is_delayed (unsigned long);
4949 is_delayed (unsigned long insn
)
4952 for (i
= 0; i
< NUMOPCODES
; ++i
)
4953 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4954 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4956 return (i
< NUMOPCODES
4957 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4958 | INSN_COND_BRANCH_DELAY
4959 | INSN_COND_BRANCH_LIKELY
)));
4963 mips_step_skips_delay (CORE_ADDR pc
)
4965 char buf
[MIPS_INSTLEN
];
4967 /* There is no branch delay slot on MIPS16. */
4968 if (pc_is_mips16 (pc
))
4971 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4972 /* If error reading memory, guess that it is not a delayed branch. */
4974 return is_delayed ((unsigned long)
4975 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4978 /* To skip prologues, I use this predicate. Returns either PC itself
4979 if the code at PC does not look like a function prologue; otherwise
4980 returns an address that (if we're lucky) follows the prologue. If
4981 LENIENT, then we must skip everything which is involved in setting
4982 up the frame (it's OK to skip more, just so long as we don't skip
4983 anything which might clobber the registers which are being saved.
4984 We must skip more in the case where part of the prologue is in the
4985 delay slot of a non-prologue instruction). */
4988 mips_skip_prologue (CORE_ADDR pc
)
4990 /* See if we can determine the end of the prologue via the symbol table.
4991 If so, then return either PC, or the PC after the prologue, whichever
4994 CORE_ADDR post_prologue_pc
= after_prologue (pc
);
4997 if (post_prologue_pc
!= 0)
4998 return max (pc
, post_prologue_pc
);
5000 /* Can't determine prologue from the symbol table, need to examine
5003 /* Find an upper limit on the function prologue using the debug
5004 information. If the debug information could not be used to provide
5005 that bound, then use an arbitrary large number as the upper bound. */
5006 limit_pc
= skip_prologue_using_sal (pc
);
5008 limit_pc
= pc
+ 100; /* Magic. */
5010 if (pc_is_mips16 (pc
))
5011 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
5013 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
5016 /* Root of all "set mips "/"show mips " commands. This will eventually be
5017 used for all MIPS-specific commands. */
5020 show_mips_command (char *args
, int from_tty
)
5022 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5026 set_mips_command (char *args
, int from_tty
)
5029 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5030 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5033 /* Commands to show/set the MIPS FPU type. */
5036 show_mipsfpu_command (char *args
, int from_tty
)
5039 switch (MIPS_FPU_TYPE
)
5041 case MIPS_FPU_SINGLE
:
5042 fpu
= "single-precision";
5044 case MIPS_FPU_DOUBLE
:
5045 fpu
= "double-precision";
5048 fpu
= "absent (none)";
5051 internal_error (__FILE__
, __LINE__
, "bad switch");
5053 if (mips_fpu_type_auto
)
5055 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5059 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5064 set_mipsfpu_command (char *args
, int from_tty
)
5067 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5068 show_mipsfpu_command (args
, from_tty
);
5072 set_mipsfpu_single_command (char *args
, int from_tty
)
5074 struct gdbarch_info info
;
5075 gdbarch_info_init (&info
);
5076 mips_fpu_type
= MIPS_FPU_SINGLE
;
5077 mips_fpu_type_auto
= 0;
5078 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5079 instead of relying on globals. Doing that would let generic code
5080 handle the search for this specific architecture. */
5081 if (!gdbarch_update_p (info
))
5082 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5086 set_mipsfpu_double_command (char *args
, int from_tty
)
5088 struct gdbarch_info info
;
5089 gdbarch_info_init (&info
);
5090 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5091 mips_fpu_type_auto
= 0;
5092 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5093 instead of relying on globals. Doing that would let generic code
5094 handle the search for this specific architecture. */
5095 if (!gdbarch_update_p (info
))
5096 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5100 set_mipsfpu_none_command (char *args
, int from_tty
)
5102 struct gdbarch_info info
;
5103 gdbarch_info_init (&info
);
5104 mips_fpu_type
= MIPS_FPU_NONE
;
5105 mips_fpu_type_auto
= 0;
5106 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5107 instead of relying on globals. Doing that would let generic code
5108 handle the search for this specific architecture. */
5109 if (!gdbarch_update_p (info
))
5110 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5114 set_mipsfpu_auto_command (char *args
, int from_tty
)
5116 mips_fpu_type_auto
= 1;
5119 /* Attempt to identify the particular processor model by reading the
5120 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5121 the relevant processor still exists (it dates back to '94) and
5122 secondly this is not the way to do this. The processor type should
5123 be set by forcing an architecture change. */
5126 deprecated_mips_set_processor_regs_hack (void)
5128 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5131 prid
= read_register (PRID_REGNUM
);
5133 if ((prid
& ~0xf) == 0x700)
5134 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5137 /* Just like reinit_frame_cache, but with the right arguments to be
5138 callable as an sfunc. */
5141 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5142 struct cmd_list_element
*c
)
5144 reinit_frame_cache ();
5148 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5150 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5151 mips_extra_func_info_t proc_desc
;
5153 /* Search for the function containing this address. Set the low bit
5154 of the address when searching, in case we were given an even address
5155 that is the start of a 16-bit function. If we didn't do this,
5156 the search would fail because the symbol table says the function
5157 starts at an odd address, i.e. 1 byte past the given address. */
5158 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5159 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5161 /* Make an attempt to determine if this is a 16-bit function. If
5162 the procedure descriptor exists and the address therein is odd,
5163 it's definitely a 16-bit function. Otherwise, we have to just
5164 guess that if the address passed in is odd, it's 16-bits. */
5165 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5166 disassembler needs to be able to locally determine the ISA, and
5167 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5171 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5172 info
->mach
= bfd_mach_mips16
;
5176 if (pc_is_mips16 (memaddr
))
5177 info
->mach
= bfd_mach_mips16
;
5180 /* Round down the instruction address to the appropriate boundary. */
5181 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5183 /* Set the disassembler options. */
5184 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5186 /* Set up the disassembler info, so that we get the right
5187 register names from libopcodes. */
5188 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5189 info
->disassembler_options
= "gpr-names=n32";
5191 info
->disassembler_options
= "gpr-names=64";
5192 info
->flavour
= bfd_target_elf_flavour
;
5195 /* This string is not recognized explicitly by the disassembler,
5196 but it tells the disassembler to not try to guess the ABI from
5197 the bfd elf headers, such that, if the user overrides the ABI
5198 of a program linked as NewABI, the disassembly will follow the
5199 register naming conventions specified by the user. */
5200 info
->disassembler_options
= "gpr-names=32";
5202 /* Call the appropriate disassembler based on the target endian-ness. */
5203 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5204 return print_insn_big_mips (memaddr
, info
);
5206 return print_insn_little_mips (memaddr
, info
);
5209 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5210 counter value to determine whether a 16- or 32-bit breakpoint should be
5211 used. It returns a pointer to a string of bytes that encode a breakpoint
5212 instruction, stores the length of the string to *lenptr, and adjusts pc
5213 (if necessary) to point to the actual memory location where the
5214 breakpoint should be inserted. */
5216 static const unsigned char *
5217 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5219 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5221 if (pc_is_mips16 (*pcptr
))
5223 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5224 *pcptr
= unmake_mips16_addr (*pcptr
);
5225 *lenptr
= sizeof (mips16_big_breakpoint
);
5226 return mips16_big_breakpoint
;
5230 /* The IDT board uses an unusual breakpoint value, and
5231 sometimes gets confused when it sees the usual MIPS
5232 breakpoint instruction. */
5233 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5234 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5235 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5237 *lenptr
= sizeof (big_breakpoint
);
5239 if (strcmp (target_shortname
, "mips") == 0)
5240 return idt_big_breakpoint
;
5241 else if (strcmp (target_shortname
, "ddb") == 0
5242 || strcmp (target_shortname
, "pmon") == 0
5243 || strcmp (target_shortname
, "lsi") == 0)
5244 return pmon_big_breakpoint
;
5246 return big_breakpoint
;
5251 if (pc_is_mips16 (*pcptr
))
5253 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5254 *pcptr
= unmake_mips16_addr (*pcptr
);
5255 *lenptr
= sizeof (mips16_little_breakpoint
);
5256 return mips16_little_breakpoint
;
5260 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5261 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5262 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5264 *lenptr
= sizeof (little_breakpoint
);
5266 if (strcmp (target_shortname
, "mips") == 0)
5267 return idt_little_breakpoint
;
5268 else if (strcmp (target_shortname
, "ddb") == 0
5269 || strcmp (target_shortname
, "pmon") == 0
5270 || strcmp (target_shortname
, "lsi") == 0)
5271 return pmon_little_breakpoint
;
5273 return little_breakpoint
;
5278 /* If PC is in a mips16 call or return stub, return the address of the target
5279 PC, which is either the callee or the caller. There are several
5280 cases which must be handled:
5282 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5283 target PC is in $31 ($ra).
5284 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5285 and the target PC is in $2.
5286 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5287 before the jal instruction, this is effectively a call stub
5288 and the the target PC is in $2. Otherwise this is effectively
5289 a return stub and the target PC is in $18.
5291 See the source code for the stubs in gcc/config/mips/mips16.S for
5294 This function implements the SKIP_TRAMPOLINE_CODE macro.
5298 mips_skip_stub (CORE_ADDR pc
)
5301 CORE_ADDR start_addr
;
5303 /* Find the starting address and name of the function containing the PC. */
5304 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5307 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5308 target PC is in $31 ($ra). */
5309 if (strcmp (name
, "__mips16_ret_sf") == 0
5310 || strcmp (name
, "__mips16_ret_df") == 0)
5311 return read_signed_register (RA_REGNUM
);
5313 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5315 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5316 and the target PC is in $2. */
5317 if (name
[19] >= '0' && name
[19] <= '9')
5318 return read_signed_register (2);
5320 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5321 before the jal instruction, this is effectively a call stub
5322 and the the target PC is in $2. Otherwise this is effectively
5323 a return stub and the target PC is in $18. */
5324 else if (name
[19] == 's' || name
[19] == 'd')
5326 if (pc
== start_addr
)
5328 /* Check if the target of the stub is a compiler-generated
5329 stub. Such a stub for a function bar might have a name
5330 like __fn_stub_bar, and might look like this:
5335 la $1,bar (becomes a lui/addiu pair)
5337 So scan down to the lui/addi and extract the target
5338 address from those two instructions. */
5340 CORE_ADDR target_pc
= read_signed_register (2);
5344 /* See if the name of the target function is __fn_stub_*. */
5345 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5348 if (strncmp (name
, "__fn_stub_", 10) != 0
5349 && strcmp (name
, "etext") != 0
5350 && strcmp (name
, "_etext") != 0)
5353 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5354 The limit on the search is arbitrarily set to 20
5355 instructions. FIXME. */
5356 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5358 inst
= mips_fetch_instruction (target_pc
);
5359 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5360 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5361 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5362 return pc
| (inst
& 0xffff); /* low word */
5365 /* Couldn't find the lui/addui pair, so return stub address. */
5369 /* This is the 'return' part of a call stub. The return
5370 address is in $r18. */
5371 return read_signed_register (18);
5374 return 0; /* not a stub */
5378 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5379 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5382 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5384 CORE_ADDR start_addr
;
5386 /* Find the starting address of the function containing the PC. If the
5387 caller didn't give us a name, look it up at the same time. */
5388 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5392 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5394 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5395 if (name
[19] >= '0' && name
[19] <= '9')
5397 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5398 before the jal instruction, this is effectively a call stub. */
5399 else if (name
[19] == 's' || name
[19] == 'd')
5400 return pc
== start_addr
;
5403 return 0; /* not a stub */
5407 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5408 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5411 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5413 CORE_ADDR start_addr
;
5415 /* Find the starting address of the function containing the PC. */
5416 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5419 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5420 if (strcmp (name
, "__mips16_ret_sf") == 0
5421 || strcmp (name
, "__mips16_ret_df") == 0)
5424 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5425 i.e. after the jal instruction, this is effectively a return stub. */
5426 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5427 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5430 return 0; /* not a stub */
5434 /* Return non-zero if the PC is in a library helper function that
5435 should be ignored. This implements the
5436 DEPRECATED_IGNORE_HELPER_CALL macro. */
5439 mips_ignore_helper (CORE_ADDR pc
)
5443 /* Find the starting address and name of the function containing the PC. */
5444 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5447 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5448 that we want to ignore. */
5449 return (strcmp (name
, "__mips16_ret_sf") == 0
5450 || strcmp (name
, "__mips16_ret_df") == 0);
5454 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5455 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5458 mips_stab_reg_to_regnum (int num
)
5461 if (num
>= 0 && num
< 32)
5463 else if (num
>= 38 && num
< 70)
5464 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5466 regnum
= mips_regnum (current_gdbarch
)->hi
;
5468 regnum
= mips_regnum (current_gdbarch
)->lo
;
5470 /* This will hopefully (eventually) provoke a warning. Should
5471 we be calling complaint() here? */
5472 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5473 return NUM_REGS
+ regnum
;
5477 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5478 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5481 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5484 if (num
>= 0 && num
< 32)
5486 else if (num
>= 32 && num
< 64)
5487 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5489 regnum
= mips_regnum (current_gdbarch
)->hi
;
5491 regnum
= mips_regnum (current_gdbarch
)->lo
;
5493 /* This will hopefully (eventually) provoke a warning. Should we
5494 be calling complaint() here? */
5495 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5496 return NUM_REGS
+ regnum
;
5500 mips_register_sim_regno (int regnum
)
5502 /* Only makes sense to supply raw registers. */
5503 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5504 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5505 decide if it is valid. Should instead define a standard sim/gdb
5506 register numbering scheme. */
5507 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5508 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5511 return LEGACY_SIM_REGNO_IGNORE
;
5515 /* Convert an integer into an address. By first converting the value
5516 into a pointer and then extracting it signed, the address is
5517 guarenteed to be correctly sign extended. */
5520 mips_integer_to_address (struct type
*type
, void *buf
)
5522 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5523 LONGEST val
= unpack_long (type
, buf
);
5524 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5525 return extract_signed_integer (tmp
,
5526 TYPE_LENGTH (builtin_type_void_data_ptr
));
5530 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5532 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5533 const char *name
= bfd_get_section_name (abfd
, sect
);
5535 if (*abip
!= MIPS_ABI_UNKNOWN
)
5538 if (strncmp (name
, ".mdebug.", 8) != 0)
5541 if (strcmp (name
, ".mdebug.abi32") == 0)
5542 *abip
= MIPS_ABI_O32
;
5543 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5544 *abip
= MIPS_ABI_N32
;
5545 else if (strcmp (name
, ".mdebug.abi64") == 0)
5546 *abip
= MIPS_ABI_N64
;
5547 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5548 *abip
= MIPS_ABI_O64
;
5549 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5550 *abip
= MIPS_ABI_EABI32
;
5551 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5552 *abip
= MIPS_ABI_EABI64
;
5554 warning ("unsupported ABI %s.", name
+ 8);
5557 static enum mips_abi
5558 global_mips_abi (void)
5562 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5563 if (mips_abi_strings
[i
] == mips_abi_string
)
5564 return (enum mips_abi
) i
;
5566 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5569 static struct gdbarch
*
5570 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5572 struct gdbarch
*gdbarch
;
5573 struct gdbarch_tdep
*tdep
;
5575 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5577 enum mips_fpu_type fpu_type
;
5579 /* First of all, extract the elf_flags, if available. */
5580 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5581 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5582 else if (arches
!= NULL
)
5583 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5587 fprintf_unfiltered (gdb_stdlog
,
5588 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5590 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5591 switch ((elf_flags
& EF_MIPS_ABI
))
5593 case E_MIPS_ABI_O32
:
5594 found_abi
= MIPS_ABI_O32
;
5596 case E_MIPS_ABI_O64
:
5597 found_abi
= MIPS_ABI_O64
;
5599 case E_MIPS_ABI_EABI32
:
5600 found_abi
= MIPS_ABI_EABI32
;
5602 case E_MIPS_ABI_EABI64
:
5603 found_abi
= MIPS_ABI_EABI64
;
5606 if ((elf_flags
& EF_MIPS_ABI2
))
5607 found_abi
= MIPS_ABI_N32
;
5609 found_abi
= MIPS_ABI_UNKNOWN
;
5613 /* GCC creates a pseudo-section whose name describes the ABI. */
5614 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5615 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5617 /* If we have no useful BFD information, use the ABI from the last
5618 MIPS architecture (if there is one). */
5619 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5620 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5622 /* Try the architecture for any hint of the correct ABI. */
5623 if (found_abi
== MIPS_ABI_UNKNOWN
5624 && info
.bfd_arch_info
!= NULL
5625 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5627 switch (info
.bfd_arch_info
->mach
)
5629 case bfd_mach_mips3900
:
5630 found_abi
= MIPS_ABI_EABI32
;
5632 case bfd_mach_mips4100
:
5633 case bfd_mach_mips5000
:
5634 found_abi
= MIPS_ABI_EABI64
;
5636 case bfd_mach_mips8000
:
5637 case bfd_mach_mips10000
:
5638 /* On Irix, ELF64 executables use the N64 ABI. The
5639 pseudo-sections which describe the ABI aren't present
5640 on IRIX. (Even for executables created by gcc.) */
5641 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5642 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5643 found_abi
= MIPS_ABI_N64
;
5645 found_abi
= MIPS_ABI_N32
;
5651 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5654 /* What has the user specified from the command line? */
5655 wanted_abi
= global_mips_abi ();
5657 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5660 /* Now that we have found what the ABI for this binary would be,
5661 check whether the user is overriding it. */
5662 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5663 mips_abi
= wanted_abi
;
5664 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5665 mips_abi
= found_abi
;
5667 mips_abi
= MIPS_ABI_O32
;
5669 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5672 /* Also used when doing an architecture lookup. */
5674 fprintf_unfiltered (gdb_stdlog
,
5675 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5676 mips64_transfers_32bit_regs_p
);
5678 /* Determine the MIPS FPU type. */
5679 if (!mips_fpu_type_auto
)
5680 fpu_type
= mips_fpu_type
;
5681 else if (info
.bfd_arch_info
!= NULL
5682 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5683 switch (info
.bfd_arch_info
->mach
)
5685 case bfd_mach_mips3900
:
5686 case bfd_mach_mips4100
:
5687 case bfd_mach_mips4111
:
5688 case bfd_mach_mips4120
:
5689 fpu_type
= MIPS_FPU_NONE
;
5691 case bfd_mach_mips4650
:
5692 fpu_type
= MIPS_FPU_SINGLE
;
5695 fpu_type
= MIPS_FPU_DOUBLE
;
5698 else if (arches
!= NULL
)
5699 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5701 fpu_type
= MIPS_FPU_DOUBLE
;
5703 fprintf_unfiltered (gdb_stdlog
,
5704 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5706 /* try to find a pre-existing architecture */
5707 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5709 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5711 /* MIPS needs to be pedantic about which ABI the object is
5713 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5715 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5717 /* Need to be pedantic about which register virtual size is
5719 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5720 != mips64_transfers_32bit_regs_p
)
5722 /* Be pedantic about which FPU is selected. */
5723 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5725 return arches
->gdbarch
;
5728 /* Need a new architecture. Fill in a target specific vector. */
5729 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5730 gdbarch
= gdbarch_alloc (&info
, tdep
);
5731 tdep
->elf_flags
= elf_flags
;
5732 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5733 tdep
->found_abi
= found_abi
;
5734 tdep
->mips_abi
= mips_abi
;
5735 tdep
->mips_fpu_type
= fpu_type
;
5737 /* Initially set everything according to the default ABI/ISA. */
5738 set_gdbarch_short_bit (gdbarch
, 16);
5739 set_gdbarch_int_bit (gdbarch
, 32);
5740 set_gdbarch_float_bit (gdbarch
, 32);
5741 set_gdbarch_double_bit (gdbarch
, 64);
5742 set_gdbarch_long_double_bit (gdbarch
, 64);
5743 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5744 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5745 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5747 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5748 mips_elf_make_msymbol_special
);
5750 /* Fill in the OS dependant register numbers and names. */
5752 const char **reg_names
;
5753 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5754 struct mips_regnum
);
5755 if (info
.osabi
== GDB_OSABI_IRIX
)
5760 regnum
->badvaddr
= 66;
5763 regnum
->fp_control_status
= 69;
5764 regnum
->fp_implementation_revision
= 70;
5766 reg_names
= mips_irix_reg_names
;
5770 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5771 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5772 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5773 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5774 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5775 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5776 regnum
->fp_control_status
= 70;
5777 regnum
->fp_implementation_revision
= 71;
5779 if (info
.bfd_arch_info
!= NULL
5780 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5781 reg_names
= mips_tx39_reg_names
;
5783 reg_names
= mips_generic_reg_names
;
5785 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5786 replaced by read_pc? */
5787 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5788 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5789 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5790 set_gdbarch_num_regs (gdbarch
, num_regs
);
5791 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5792 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5793 tdep
->mips_processor_reg_names
= reg_names
;
5794 tdep
->regnum
= regnum
;
5800 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5801 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5802 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5803 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5804 tdep
->default_mask_address_p
= 0;
5805 set_gdbarch_long_bit (gdbarch
, 32);
5806 set_gdbarch_ptr_bit (gdbarch
, 32);
5807 set_gdbarch_long_long_bit (gdbarch
, 64);
5810 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5811 set_gdbarch_deprecated_store_return_value (gdbarch
,
5812 mips_o64_store_return_value
);
5813 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5814 mips_o64_extract_return_value
);
5815 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5816 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5817 tdep
->default_mask_address_p
= 0;
5818 set_gdbarch_long_bit (gdbarch
, 32);
5819 set_gdbarch_ptr_bit (gdbarch
, 32);
5820 set_gdbarch_long_long_bit (gdbarch
, 64);
5821 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
5823 case MIPS_ABI_EABI32
:
5824 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5825 set_gdbarch_deprecated_store_return_value (gdbarch
,
5826 mips_eabi_store_return_value
);
5827 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5828 mips_eabi_extract_return_value
);
5829 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5830 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5831 tdep
->default_mask_address_p
= 0;
5832 set_gdbarch_long_bit (gdbarch
, 32);
5833 set_gdbarch_ptr_bit (gdbarch
, 32);
5834 set_gdbarch_long_long_bit (gdbarch
, 64);
5835 set_gdbarch_deprecated_reg_struct_has_addr
5836 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5837 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
5839 case MIPS_ABI_EABI64
:
5840 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5841 set_gdbarch_deprecated_store_return_value (gdbarch
,
5842 mips_eabi_store_return_value
);
5843 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5844 mips_eabi_extract_return_value
);
5845 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5846 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5847 tdep
->default_mask_address_p
= 0;
5848 set_gdbarch_long_bit (gdbarch
, 64);
5849 set_gdbarch_ptr_bit (gdbarch
, 64);
5850 set_gdbarch_long_long_bit (gdbarch
, 64);
5851 set_gdbarch_deprecated_reg_struct_has_addr
5852 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5853 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
5856 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5857 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5858 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5859 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5860 tdep
->default_mask_address_p
= 0;
5861 set_gdbarch_long_bit (gdbarch
, 32);
5862 set_gdbarch_ptr_bit (gdbarch
, 32);
5863 set_gdbarch_long_long_bit (gdbarch
, 64);
5864 set_gdbarch_long_double_bit (gdbarch
, 128);
5865 set_gdbarch_long_double_format (gdbarch
,
5866 &floatformat_n32n64_long_double_big
);
5869 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5870 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5871 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5872 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5873 tdep
->default_mask_address_p
= 0;
5874 set_gdbarch_long_bit (gdbarch
, 64);
5875 set_gdbarch_ptr_bit (gdbarch
, 64);
5876 set_gdbarch_long_long_bit (gdbarch
, 64);
5877 set_gdbarch_long_double_bit (gdbarch
, 128);
5878 set_gdbarch_long_double_format (gdbarch
,
5879 &floatformat_n32n64_long_double_big
);
5882 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
5885 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5886 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5889 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5890 flag in object files because to do so would make it impossible to
5891 link with libraries compiled without "-gp32". This is
5892 unnecessarily restrictive.
5894 We could solve this problem by adding "-gp32" multilibs to gcc,
5895 but to set this flag before gcc is built with such multilibs will
5896 break too many systems.''
5898 But even more unhelpfully, the default linker output target for
5899 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5900 for 64-bit programs - you need to change the ABI to change this,
5901 and not all gcc targets support that currently. Therefore using
5902 this flag to detect 32-bit mode would do the wrong thing given
5903 the current gcc - it would make GDB treat these 64-bit programs
5904 as 32-bit programs by default. */
5906 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5907 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5908 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5910 /* Add/remove bits from an address. The MIPS needs be careful to
5911 ensure that all 32 bit addresses are sign extended to 64 bits. */
5912 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5914 /* Unwind the frame. */
5915 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5916 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5918 /* Map debug register numbers onto internal register numbers. */
5919 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5920 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5921 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5922 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5923 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5924 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5925 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5926 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5928 /* MIPS version of CALL_DUMMY */
5930 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5931 replaced by a command, and all targets will default to on stack
5932 (regardless of the stack's execute status). */
5933 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5934 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5936 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5937 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5938 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5940 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5941 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5943 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5945 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5946 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5947 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5949 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5951 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5953 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5955 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5956 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5957 need to all be folded into the target vector. Since they are
5958 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5959 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5961 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5963 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
5965 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
5966 to support MIPS16. This is a bad thing. Make sure not to do it
5967 if we have an OS ABI that actually supports shared libraries, since
5968 shared library support is more important. If we have an OS someday
5969 that supports both shared libraries and MIPS16, we'll have to find
5970 a better place for these. */
5971 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
5973 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
5974 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
5977 /* Hook in OS ABI-specific overrides, if they have been registered. */
5978 gdbarch_init_osabi (info
, gdbarch
);
5980 /* Unwind the frame. */
5981 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5982 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
5983 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5984 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5985 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5986 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
5987 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5988 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5994 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5996 struct gdbarch_info info
;
5998 /* Force the architecture to update, and (if it's a MIPS architecture)
5999 mips_gdbarch_init will take care of the rest. */
6000 gdbarch_info_init (&info
);
6001 gdbarch_update_p (info
);
6004 /* Print out which MIPS ABI is in use. */
6007 show_mips_abi (char *ignore_args
, int from_tty
)
6009 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6011 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6014 enum mips_abi global_abi
= global_mips_abi ();
6015 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6016 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6018 if (global_abi
== MIPS_ABI_UNKNOWN
)
6020 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6022 else if (global_abi
== actual_abi
)
6024 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6028 /* Probably shouldn't happen... */
6030 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6031 actual_abi_str
, mips_abi_strings
[global_abi
]);
6037 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6039 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6043 int ef_mips_32bitmode
;
6044 /* determine the ISA */
6045 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6063 /* determine the size of a pointer */
6064 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6065 fprintf_unfiltered (file
,
6066 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6068 fprintf_unfiltered (file
,
6069 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6071 fprintf_unfiltered (file
,
6072 "mips_dump_tdep: ef_mips_arch = %d\n",
6074 fprintf_unfiltered (file
,
6075 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6076 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6077 fprintf_unfiltered (file
,
6078 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6079 mips_mask_address_p (tdep
),
6080 tdep
->default_mask_address_p
);
6082 fprintf_unfiltered (file
,
6083 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6084 MIPS_DEFAULT_FPU_TYPE
,
6085 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6086 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6087 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6089 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6090 fprintf_unfiltered (file
,
6091 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6093 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6094 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6095 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6097 fprintf_unfiltered (file
,
6098 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6099 mips_stack_argsize (current_gdbarch
));
6100 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6101 fprintf_unfiltered (file
,
6102 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6103 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6104 fprintf_unfiltered (file
,
6105 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6106 XSTRING (ATTACH_DETACH
));
6107 fprintf_unfiltered (file
,
6108 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6109 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6110 fprintf_unfiltered (file
,
6111 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6112 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6113 fprintf_unfiltered (file
,
6114 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6115 FIRST_EMBED_REGNUM
);
6116 fprintf_unfiltered (file
,
6117 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
6118 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
6119 fprintf_unfiltered (file
,
6120 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6121 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6122 fprintf_unfiltered (file
,
6123 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6124 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6125 fprintf_unfiltered (file
,
6126 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6128 #ifdef MACHINE_CPROC_FP_OFFSET
6129 fprintf_unfiltered (file
,
6130 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6131 MACHINE_CPROC_FP_OFFSET
);
6133 #ifdef MACHINE_CPROC_PC_OFFSET
6134 fprintf_unfiltered (file
,
6135 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6136 MACHINE_CPROC_PC_OFFSET
);
6138 #ifdef MACHINE_CPROC_SP_OFFSET
6139 fprintf_unfiltered (file
,
6140 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6141 MACHINE_CPROC_SP_OFFSET
);
6143 fprintf_unfiltered (file
,
6144 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6146 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6147 fprintf_unfiltered (file
,
6148 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6149 fprintf_unfiltered (file
,
6150 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6151 fprintf_unfiltered (file
,
6152 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6153 MIPS_LAST_ARG_REGNUM
,
6154 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6155 fprintf_unfiltered (file
,
6156 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6157 fprintf_unfiltered (file
,
6158 "mips_dump_tdep: mips_abi_regsize() = %d\n",
6159 mips_abi_regsize (current_gdbarch
));
6160 fprintf_unfiltered (file
,
6161 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6162 fprintf_unfiltered (file
,
6163 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6164 fprintf_unfiltered (file
,
6165 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6166 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6167 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6168 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6169 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6170 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6171 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6172 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6173 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6174 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6175 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6176 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6178 fprintf_unfiltered (file
,
6179 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6182 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6185 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6187 fprintf_unfiltered (file
,
6188 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6189 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6190 fprintf_unfiltered (file
,
6191 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6192 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6193 fprintf_unfiltered (file
,
6194 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6195 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6196 fprintf_unfiltered (file
,
6197 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6198 SOFTWARE_SINGLE_STEP_P ());
6199 fprintf_unfiltered (file
,
6200 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6201 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6202 #ifdef STACK_END_ADDR
6203 fprintf_unfiltered (file
,
6204 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6207 fprintf_unfiltered (file
,
6208 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6209 XSTRING (STEP_SKIPS_DELAY (PC
)));
6210 fprintf_unfiltered (file
,
6211 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6212 STEP_SKIPS_DELAY_P
);
6213 fprintf_unfiltered (file
,
6214 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6215 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6216 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6217 fprintf_unfiltered (file
,
6218 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6219 fprintf_unfiltered (file
,
6220 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6221 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6222 (TYPE
, CNT
, OTHERTYPE
)));
6224 fprintf_unfiltered (file
,
6225 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6226 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6229 fprintf_unfiltered (file
,
6230 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6232 #ifdef TRACE_FLAVOR_SIZE
6233 fprintf_unfiltered (file
,
6234 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6238 fprintf_unfiltered (file
,
6239 "mips_dump_tdep: TRACE_SET # %s\n",
6240 XSTRING (TRACE_SET (X
, STATE
)));
6242 #ifdef UNUSED_REGNUM
6243 fprintf_unfiltered (file
,
6244 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6246 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6247 fprintf_unfiltered (file
,
6248 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6249 (long) VM_MIN_ADDRESS
);
6250 fprintf_unfiltered (file
,
6251 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6254 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6257 _initialize_mips_tdep (void)
6259 static struct cmd_list_element
*mipsfpulist
= NULL
;
6260 struct cmd_list_element
*c
;
6262 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6263 if (MIPS_ABI_LAST
+ 1
6264 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6265 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6267 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6269 mips_pdr_data
= register_objfile_data ();
6271 /* Add root prefix command for all "set mips"/"show mips" commands */
6272 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6273 "Various MIPS specific commands.",
6274 &setmipscmdlist
, "set mips ", 0, &setlist
);
6276 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6277 "Various MIPS specific commands.",
6278 &showmipscmdlist
, "show mips ", 0, &showlist
);
6280 /* Allow the user to override the saved register size. */
6281 deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6284 &mips_abi_regsize_string
, "\
6285 Set size of general purpose registers saved on the stack.\n\
6286 This option can be set to one of:\n\
6287 32 - Force GDB to treat saved GP registers as 32-bit\n\
6288 64 - Force GDB to treat saved GP registers as 64-bit\n\
6289 auto - Allow GDB to use the target's default setting or autodetect the\n\
6290 saved GP register size from information contained in the executable.\n\
6291 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6293 /* Allow the user to override the argument stack size. */
6294 deprecated_add_show_from_set
6295 (add_set_enum_cmd ("stack-arg-size",
6298 &mips_stack_argsize_string
, "\
6299 Set the amount of stack space reserved for each argument.\n\
6300 This option can be set to one of:\n\
6301 32 - Force GDB to allocate 32-bit chunks per argument\n\
6302 64 - Force GDB to allocate 64-bit chunks per argument\n\
6303 auto - Allow GDB to determine the correct setting from the current\n\
6304 target and executable (default)", &setmipscmdlist
),
6307 /* Allow the user to override the ABI. */
6308 c
= add_set_enum_cmd
6309 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6310 "Set the ABI used by this program.\n"
6311 "This option can be set to one of:\n"
6312 " auto - the default ABI associated with the current binary\n"
6314 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6315 set_cmd_sfunc (c
, mips_abi_update
);
6316 add_cmd ("abi", class_obscure
, show_mips_abi
,
6317 "Show ABI in use by MIPS target", &showmipscmdlist
);
6319 /* Let the user turn off floating point and set the fence post for
6320 heuristic_proc_start. */
6322 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6323 "Set use of MIPS floating-point coprocessor.",
6324 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6325 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6326 "Select single-precision MIPS floating-point coprocessor.",
6328 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6329 "Select double-precision MIPS floating-point coprocessor.",
6331 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6332 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6333 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6334 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6335 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6336 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6337 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6338 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6339 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6340 "Select MIPS floating-point coprocessor automatically.",
6342 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6343 "Show current use of MIPS floating-point coprocessor target.",
6346 /* We really would like to have both "0" and "unlimited" work, but
6347 command.c doesn't deal with that. So make it a var_zinteger
6348 because the user can always use "999999" or some such for unlimited. */
6349 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6350 (char *) &heuristic_fence_post
, "\
6351 Set the distance searched for the start of a function.\n\
6352 If you are debugging a stripped executable, GDB needs to search through the\n\
6353 program for the start of a function. This command sets the distance of the\n\
6354 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6355 /* We need to throw away the frame cache when we set this, since it
6356 might change our ability to get backtraces. */
6357 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6358 deprecated_add_show_from_set (c
, &showlist
);
6360 /* Allow the user to control whether the upper bits of 64-bit
6361 addresses should be zeroed. */
6362 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6363 Set zeroing of upper 32 bits of 64-bit addresses.", "\
6364 Show zeroing of upper 32 bits of 64-bit addresses.", "\
6365 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6366 allow GDB to determine the correct value.\n", "\
6367 Zerroing of upper 32 bits of 64-bit address is %s.",
6368 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6370 /* Allow the user to control the size of 32 bit registers within the
6371 raw remote packet. */
6372 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6373 &mips64_transfers_32bit_regs_p
, "\
6374 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6375 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6376 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6377 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6378 64 bits for others. Use \"off\" to disable compatibility mode", "\
6379 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6380 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6382 /* Debug this files internals. */
6383 deprecated_add_show_from_set
6384 (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6385 &mips_debug
, "Set mips debugging.\n\
6386 When non-zero, mips specific debugging is enabled.", &setdebuglist
),