1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
41 /* FIXME: Put this declaration in frame.h. */
42 extern struct obstack frame_cache_obstack
;
45 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
48 static int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
50 static void mips_print_register
PARAMS ((int, int));
52 static mips_extra_func_info_t
53 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
55 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
57 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
59 static void mips_set_fpu_command
PARAMS ((char *, int,
60 struct cmd_list_element
*));
62 static void mips_show_fpu_command
PARAMS ((char *, int,
63 struct cmd_list_element
*));
65 void mips_set_processor_type_command
PARAMS ((char *, int));
67 int mips_set_processor_type
PARAMS ((char *));
69 static void mips_show_processor_type_command
PARAMS ((char *, int));
71 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
72 struct cmd_list_element
*));
74 static mips_extra_func_info_t
75 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
*next_frame
));
77 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
78 mips_extra_func_info_t proc_desc
));
80 /* This value is the model of MIPS in use. It is derived from the value
81 of the PrID register. */
83 char *mips_processor_type
;
85 char *tmp_mips_processor_type
;
87 /* Some MIPS boards don't support floating point, so we permit the
88 user to turn it off. */
90 enum mips_fpu_type mips_fpu
;
92 static char *mips_fpu_string
;
94 /* A set of original names, to be used when restoring back to generic
95 registers from a specific set. */
97 char *mips_generic_reg_names
[] = REGISTER_NAMES
;
99 /* Names of IDT R3041 registers. */
101 char *mips_r3041_reg_names
[] = {
102 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
103 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
104 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
105 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
106 "sr", "lo", "hi", "bad", "cause","pc",
107 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
108 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
109 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
110 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
111 "fsr", "fir", "fp", "",
112 "", "", "bus", "ccfg", "", "", "", "",
113 "", "", "port", "cmp", "", "", "epc", "prid",
116 /* Names of IDT R3051 registers. */
118 char *mips_r3051_reg_names
[] = {
119 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
120 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
121 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
122 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
123 "sr", "lo", "hi", "bad", "cause","pc",
124 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
125 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
126 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
127 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
128 "fsr", "fir", "fp", "",
129 "inx", "rand", "elo", "", "ctxt", "", "", "",
130 "", "", "ehi", "", "", "", "epc", "prid",
133 /* Names of IDT R3081 registers. */
135 char *mips_r3081_reg_names
[] = {
136 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
137 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
138 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
139 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
140 "sr", "lo", "hi", "bad", "cause","pc",
141 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
142 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
143 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
144 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
145 "fsr", "fir", "fp", "",
146 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
147 "", "", "ehi", "", "", "", "epc", "prid",
150 /* Names of LSI 33k registers. */
152 char *mips_lsi33k_reg_names
[] = {
153 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
154 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
155 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
156 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
157 "epc", "hi", "lo", "sr", "cause","badvaddr",
158 "dcic", "bpc", "bda", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "",
163 "", "", "", "", "", "", "", "",
164 "", "", "", "", "", "", "", "",
170 } mips_processor_type_table
[] = {
171 { "generic", mips_generic_reg_names
},
172 { "r3041", mips_r3041_reg_names
},
173 { "r3051", mips_r3051_reg_names
},
174 { "r3071", mips_r3081_reg_names
},
175 { "r3081", mips_r3081_reg_names
},
176 { "lsi33k", mips_lsi33k_reg_names
},
180 /* Table to translate MIPS16 register field to actual register number. */
181 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
183 /* Heuristic_proc_start may hunt through the text section for a long
184 time across a 2400 baud serial line. Allows the user to limit this
187 static unsigned int heuristic_fence_post
= 0;
189 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
190 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
191 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
192 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
193 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
194 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
195 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
196 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
197 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
198 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
199 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
200 #define _PROC_MAGIC_ 0x0F0F0F0F
201 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
202 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
204 struct linked_proc_info
206 struct mips_extra_func_info info
;
207 struct linked_proc_info
*next
;
208 } *linked_proc_desc_table
= NULL
;
211 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
214 pc_is_mips16 (bfd_vma memaddr
)
216 struct minimal_symbol
*sym
;
218 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
219 if (IS_MIPS16_ADDR (memaddr
))
222 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
223 the high bit of the info field. Use this to decide if the function is
224 MIPS16 or normal MIPS. */
225 sym
= lookup_minimal_symbol_by_pc (memaddr
);
227 return MSYMBOL_IS_SPECIAL (sym
);
233 /* This returns the PC of the first inst after the prologue. If we can't
234 find the prologue, then return 0. */
237 after_prologue (pc
, proc_desc
)
239 mips_extra_func_info_t proc_desc
;
241 struct symtab_and_line sal
;
242 CORE_ADDR func_addr
, func_end
;
245 proc_desc
= find_proc_desc (pc
, NULL
);
249 /* If function is frameless, then we need to do it the hard way. I
250 strongly suspect that frameless always means prologueless... */
251 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
252 && PROC_FRAME_OFFSET (proc_desc
) == 0)
256 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
257 return 0; /* Unknown */
259 sal
= find_pc_line (func_addr
, 0);
261 if (sal
.end
< func_end
)
264 /* The line after the prologue is after the end of the function. In this
265 case, tell the caller to find the prologue the hard way. */
270 /* Decode a MIPS32 instruction that saves a register in the stack, and
271 set the appropriate bit in the general register mask or float register mask
272 to indicate which register is saved. This is a helper function
273 for mips_find_saved_regs. */
276 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
278 unsigned long *gen_mask
;
279 unsigned long *float_mask
;
283 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
284 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
285 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
287 /* It might be possible to use the instruction to
288 find the offset, rather than the code below which
289 is based on things being in a certain order in the
290 frame, but figuring out what the instruction's offset
291 is relative to might be a little tricky. */
292 reg
= (inst
& 0x001f0000) >> 16;
293 *gen_mask
|= (1 << reg
);
295 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
296 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
297 || (inst
& 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */
300 reg
= ((inst
& 0x001f0000) >> 16);
301 *float_mask
|= (1 << reg
);
305 /* Decode a MIPS16 instruction that saves a register in the stack, and
306 set the appropriate bit in the general register or float register mask
307 to indicate which register is saved. This is a helper function
308 for mips_find_saved_regs. */
311 mips16_decode_reg_save (inst
, gen_mask
)
313 unsigned long *gen_mask
;
315 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
317 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
318 *gen_mask
|= (1 << reg
);
320 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
322 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
323 *gen_mask
|= (1 << reg
);
325 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
326 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
327 *gen_mask
|= (1 << RA_REGNUM
);
331 /* Fetch and return instruction from the specified location. If the PC
332 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
335 mips_fetch_instruction (addr
)
338 char buf
[MIPS_INSTLEN
];
342 if (pc_is_mips16 (addr
))
344 instlen
= MIPS16_INSTLEN
;
345 addr
= UNMAKE_MIPS16_ADDR (addr
);
348 instlen
= MIPS_INSTLEN
;
349 status
= read_memory_nobpt (addr
, buf
, instlen
);
351 memory_error (status
, addr
);
352 return extract_unsigned_integer (buf
, instlen
);
356 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
360 mips_find_saved_regs (fci
)
361 struct frame_info
*fci
;
364 CORE_ADDR reg_position
;
365 /* r0 bit means kernel trap */
367 /* What registers have been saved? Bitmasks. */
368 unsigned long gen_mask
, float_mask
;
369 mips_extra_func_info_t proc_desc
;
372 fci
->saved_regs
= (struct frame_saved_regs
*)
373 obstack_alloc (&frame_cache_obstack
, sizeof(struct frame_saved_regs
));
374 memset (fci
->saved_regs
, 0, sizeof (struct frame_saved_regs
));
376 /* If it is the frame for sigtramp, the saved registers are located
377 in a sigcontext structure somewhere on the stack.
378 If the stack layout for sigtramp changes we might have to change these
379 constants and the companion fixup_sigtramp in mdebugread.c */
380 #ifndef SIGFRAME_BASE
381 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
382 above the sigtramp frame. */
383 #define SIGFRAME_BASE MIPS_REGSIZE
384 /* FIXME! Are these correct?? */
385 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
386 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
387 #define SIGFRAME_FPREGSAVE_OFF \
388 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
390 #ifndef SIGFRAME_REG_SIZE
391 /* FIXME! Is this correct?? */
392 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
394 if (fci
->signal_handler_caller
)
396 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
398 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
399 + ireg
* SIGFRAME_REG_SIZE
;
400 fci
->saved_regs
->regs
[ireg
] = reg_position
;
402 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
404 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
405 + ireg
* SIGFRAME_REG_SIZE
;
406 fci
->saved_regs
->regs
[FP0_REGNUM
+ ireg
] = reg_position
;
408 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
412 proc_desc
= fci
->proc_desc
;
413 if (proc_desc
== NULL
)
414 /* I'm not sure how/whether this can happen. Normally when we can't
415 find a proc_desc, we "synthesize" one using heuristic_proc_desc
416 and set the saved_regs right away. */
419 kernel_trap
= PROC_REG_MASK(proc_desc
) & 1;
420 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK(proc_desc
);
421 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc
);
423 if (/* In any frame other than the innermost or a frame interrupted by
424 a signal, we assume that all registers have been saved.
425 This assumes that all register saves in a function happen before
426 the first function call. */
427 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
429 /* In a dummy frame we know exactly where things are saved. */
430 && !PROC_DESC_IS_DUMMY (proc_desc
)
432 /* Don't bother unless we are inside a function prologue. Outside the
433 prologue, we know where everything is. */
435 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
437 /* Not sure exactly what kernel_trap means, but if it means
438 the kernel saves the registers without a prologue doing it,
439 we better not examine the prologue to see whether registers
440 have been saved yet. */
443 /* We need to figure out whether the registers that the proc_desc
444 claims are saved have been saved yet. */
448 /* Bitmasks; set if we have found a save for the register. */
449 unsigned long gen_save_found
= 0;
450 unsigned long float_save_found
= 0;
453 /* If the address is odd, assume this is MIPS16 code. */
454 addr
= PROC_LOW_ADDR (proc_desc
);
455 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
457 /* Scan through this function's instructions preceding the current
458 PC, and look for those that save registers. */
459 while (addr
< fci
->pc
)
461 inst
= mips_fetch_instruction (addr
);
462 if (pc_is_mips16 (addr
))
463 mips16_decode_reg_save (inst
, &gen_save_found
);
465 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
468 gen_mask
= gen_save_found
;
469 float_mask
= float_save_found
;
472 /* Fill in the offsets for the registers which gen_mask says
474 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
475 for (ireg
= MIPS_NUMREGS
-1; gen_mask
; --ireg
, gen_mask
<<= 1)
476 if (gen_mask
& 0x80000000)
478 fci
->saved_regs
->regs
[ireg
] = reg_position
;
479 reg_position
-= MIPS_REGSIZE
;
482 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
483 of that normally used by gcc. Therefore, we have to fetch the first
484 instruction of the function, and if it's an entry instruction that
485 saves $s0 or $s1, correct their saved addresses. */
486 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
488 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
489 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
492 int sreg_count
= (inst
>> 6) & 3;
494 /* Check if the ra register was pushed on the stack. */
495 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
497 reg_position
-= MIPS_REGSIZE
;
499 /* Check if the s0 and s1 registers were pushed on the stack. */
500 for (reg
= 16; reg
< sreg_count
+16; reg
++)
502 fci
->saved_regs
->regs
[reg
] = reg_position
;
503 reg_position
-= MIPS_REGSIZE
;
508 /* Fill in the offsets for the registers which float_mask says
510 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
512 /* The freg_offset points to where the first *double* register
513 is saved. So skip to the high-order word. */
514 if (! GDB_TARGET_IS_MIPS64
)
515 reg_position
+= MIPS_REGSIZE
;
517 /* Fill in the offsets for the float registers which float_mask says
519 for (ireg
= MIPS_NUMREGS
-1; float_mask
; --ireg
, float_mask
<<= 1)
520 if (float_mask
& 0x80000000)
522 fci
->saved_regs
->regs
[FP0_REGNUM
+ireg
] = reg_position
;
523 reg_position
-= MIPS_REGSIZE
;
526 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->saved_regs
->regs
[RA_REGNUM
];
530 read_next_frame_reg(fi
, regno
)
531 struct frame_info
*fi
;
534 for (; fi
; fi
= fi
->next
)
536 /* We have to get the saved sp from the sigcontext
537 if it is a signal handler frame. */
538 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
542 if (fi
->saved_regs
== NULL
)
543 mips_find_saved_regs (fi
);
544 if (fi
->saved_regs
->regs
[regno
])
545 return read_memory_integer(fi
->saved_regs
->regs
[regno
], MIPS_REGSIZE
);
548 return read_register (regno
);
551 /* mips_addr_bits_remove - remove useless address bits */
554 mips_addr_bits_remove (addr
)
557 #if GDB_TARGET_IS_MIPS64
558 if ((addr
>> 32 == (CORE_ADDR
)0xffffffff)
559 && (strcmp (target_shortname
,"pmon")==0
560 || strcmp (target_shortname
,"ddb")==0
561 || strcmp (target_shortname
,"sim")==0))
563 /* This hack is a work-around for existing boards using PMON,
564 the simulator, and any other 64-bit targets that doesn't have
565 true 64-bit addressing. On these targets, the upper 32 bits
566 of addresses are ignored by the hardware. Thus, the PC or SP
567 are likely to have been sign extended to all 1s by instruction
568 sequences that load 32-bit addresses. For example, a typical
569 piece of code that loads an address is this:
570 lui $r2, <upper 16 bits>
571 ori $r2, <lower 16 bits>
572 But the lui sign-extends the value such that the upper 32 bits
573 may be all 1s. The workaround is simply to mask off these bits.
574 In the future, gcc may be changed to support true 64-bit
575 addressing, and this masking will have to be disabled. */
576 addr
&= (CORE_ADDR
)0xffffffff;
579 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
580 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
581 So we still have to mask off useless bits from addresses. */
582 addr
&= (CORE_ADDR
)0xffffffff;
589 mips_init_frame_pc_first (fromleaf
, prev
)
591 struct frame_info
*prev
;
595 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
596 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
597 tmp
= mips_skip_stub (pc
);
598 prev
->pc
= tmp
? tmp
: pc
;
603 mips_frame_saved_pc(frame
)
604 struct frame_info
*frame
;
607 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
608 /* We have to get the saved pc from the sigcontext
609 if it is a signal handler frame. */
610 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
611 : (proc_desc
? PROC_PC_REG(proc_desc
) : RA_REGNUM
);
613 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
614 saved_pc
= read_memory_integer(frame
->frame
- MIPS_REGSIZE
, MIPS_REGSIZE
);
616 saved_pc
= read_next_frame_reg(frame
, pcreg
);
618 return ADDR_BITS_REMOVE (saved_pc
);
621 static struct mips_extra_func_info temp_proc_desc
;
622 static struct frame_saved_regs temp_saved_regs
;
624 /* Set a register's saved stack address in temp_saved_regs. If an address
625 has already been set for this register, do nothing; this way we will
626 only recognize the first save of a given register in a function prologue.
627 This is a helper function for mips{16,32}_heuristic_proc_desc. */
630 set_reg_offset (regno
, offset
)
634 if (temp_saved_regs
.regs
[regno
] == 0)
635 temp_saved_regs
.regs
[regno
] = offset
;
639 /* This fencepost looks highly suspicious to me. Removing it also
640 seems suspicious as it could affect remote debugging across serial
644 heuristic_proc_start(pc
)
652 pc
= ADDR_BITS_REMOVE (pc
);
654 fence
= start_pc
- heuristic_fence_post
;
655 if (start_pc
== 0) return 0;
657 if (heuristic_fence_post
== UINT_MAX
658 || fence
< VM_MIN_ADDRESS
)
659 fence
= VM_MIN_ADDRESS
;
661 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
663 /* search back for previous return */
664 for (start_pc
-= instlen
; ; start_pc
-= instlen
)
665 if (start_pc
< fence
)
667 /* It's not clear to me why we reach this point when
668 stop_soon_quietly, but with this test, at least we
669 don't print out warnings for every child forked (eg, on
670 decstation). 22apr93 rich@cygnus.com. */
671 if (!stop_soon_quietly
)
673 static int blurb_printed
= 0;
675 if (fence
== VM_MIN_ADDRESS
)
676 warning("Hit beginning of text section without finding");
678 warning("Hit heuristic-fence-post without finding");
680 warning("enclosing function for address 0x%s", paddr_nz (pc
));
684 This warning occurs if you are debugging a function without any symbols\n\
685 (for example, in a stripped executable). In that case, you may wish to\n\
686 increase the size of the search with the `set heuristic-fence-post' command.\n\
688 Otherwise, you told GDB there was a function where there isn't one, or\n\
689 (more likely) you have encountered a bug in GDB.\n");
696 else if (pc_is_mips16 (start_pc
))
700 /* On MIPS16, any one of the following is likely to be the
705 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
706 inst
= mips_fetch_instruction (start_pc
);
707 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
708 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
709 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
710 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
712 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
713 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
718 else if (ABOUT_TO_RETURN(start_pc
))
720 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
725 /* skip nops (usually 1) 0 - is this */
726 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
727 start_pc
+= MIPS_INSTLEN
;
732 /* Fetch the immediate value from a MIPS16 instruction.
733 If the previous instruction was an EXTEND, use it to extend
734 the upper bits of the immediate value. This is a helper function
735 for mips16_heuristic_proc_desc. */
738 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
739 unsigned short prev_inst
; /* previous instruction */
740 unsigned short inst
; /* current instruction */
741 int nbits
; /* number of bits in imm field */
742 int scale
; /* scale factor to be applied to imm */
743 int is_signed
; /* is the imm field signed? */
747 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
749 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
750 if (offset
& 0x8000) /* check for negative extend */
751 offset
= 0 - (0x10000 - (offset
& 0xffff));
752 return offset
| (inst
& 0x1f);
756 int max_imm
= 1 << nbits
;
757 int mask
= max_imm
- 1;
758 int sign_bit
= max_imm
>> 1;
760 offset
= inst
& mask
;
761 if (is_signed
&& (offset
& sign_bit
))
762 offset
= 0 - (max_imm
- offset
);
763 return offset
* scale
;
768 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
769 stream from start_pc to limit_pc. */
772 mips16_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
773 CORE_ADDR start_pc
, limit_pc
;
774 struct frame_info
*next_frame
;
778 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
779 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
780 unsigned inst
= 0; /* current instruction */
781 unsigned entry_inst
= 0; /* the entry instruction */
784 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0; /* size of stack frame */
785 PROC_FRAME_ADJUST(&temp_proc_desc
) = 0; /* offset of FP from SP */
787 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
789 /* Save the previous instruction. If it's an EXTEND, we'll extract
790 the immediate offset extension from it in mips16_get_imm. */
793 /* Fetch and decode the instruction. */
794 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
795 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
796 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
798 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
799 if (offset
< 0) /* negative stack adjustment? */
800 PROC_FRAME_OFFSET(&temp_proc_desc
) -= offset
;
802 /* Exit loop if a positive stack adjustment is found, which
803 usually means that the stack cleanup code in the function
804 epilogue is reached. */
807 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
809 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
810 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
811 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
812 set_reg_offset (reg
, sp
+ offset
);
814 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
816 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
817 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
818 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
819 set_reg_offset (reg
, sp
+ offset
);
821 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
823 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
824 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
825 set_reg_offset (RA_REGNUM
, sp
+ offset
);
827 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
829 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
830 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
831 set_reg_offset (RA_REGNUM
, sp
+ offset
);
833 else if (inst
== 0x673d) /* move $s1, $sp */
836 PROC_FRAME_REG (&temp_proc_desc
) = 17;
838 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
840 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
841 frame_addr
= sp
+ offset
;
842 PROC_FRAME_REG (&temp_proc_desc
) = 17;
843 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
845 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
847 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
848 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
849 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
850 set_reg_offset (reg
, frame_addr
+ offset
);
852 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
854 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
855 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
856 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
857 set_reg_offset (reg
, frame_addr
+ offset
);
859 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
860 entry_inst
= inst
; /* save for later processing */
861 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
862 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
865 /* The entry instruction is typically the first instruction in a function,
866 and it stores registers at offsets relative to the value of the old SP
867 (before the prologue). But the value of the sp parameter to this
868 function is the new SP (after the prologue has been executed). So we
869 can't calculate those offsets until we've seen the entire prologue,
870 and can calculate what the old SP must have been. */
873 int areg_count
= (entry_inst
>> 8) & 7;
874 int sreg_count
= (entry_inst
>> 6) & 3;
876 /* The entry instruction always subtracts 32 from the SP. */
877 PROC_FRAME_OFFSET(&temp_proc_desc
) += 32;
879 /* Now we can calculate what the SP must have been at the
880 start of the function prologue. */
881 sp
+= PROC_FRAME_OFFSET(&temp_proc_desc
);
883 /* Check if a0-a3 were saved in the caller's argument save area. */
884 for (reg
= 4, offset
= 0; reg
< areg_count
+4; reg
++)
886 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
887 set_reg_offset (reg
, sp
+ offset
);
888 offset
+= MIPS_REGSIZE
;
891 /* Check if the ra register was pushed on the stack. */
893 if (entry_inst
& 0x20)
895 PROC_REG_MASK(&temp_proc_desc
) |= 1 << RA_REGNUM
;
896 set_reg_offset (RA_REGNUM
, sp
+ offset
);
897 offset
-= MIPS_REGSIZE
;
900 /* Check if the s0 and s1 registers were pushed on the stack. */
901 for (reg
= 16; reg
< sreg_count
+16; reg
++)
903 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
904 set_reg_offset (reg
, sp
+ offset
);
905 offset
-= MIPS_REGSIZE
;
911 mips32_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
912 CORE_ADDR start_pc
, limit_pc
;
913 struct frame_info
*next_frame
;
917 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
919 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
920 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
921 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
923 unsigned long inst
, high_word
, low_word
;
926 /* Fetch the instruction. */
927 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
929 /* Save some code by pre-extracting some useful fields. */
930 high_word
= (inst
>> 16) & 0xffff;
931 low_word
= inst
& 0xffff;
932 reg
= high_word
& 0x1f;
934 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
935 || high_word
== 0x23bd /* addi $sp,$sp,-i */
936 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
938 if (low_word
& 0x8000) /* negative stack adjustment? */
939 PROC_FRAME_OFFSET(&temp_proc_desc
) += 0x10000 - low_word
;
941 /* Exit loop if a positive stack adjustment is found, which
942 usually means that the stack cleanup code in the function
943 epilogue is reached. */
946 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
948 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
949 set_reg_offset (reg
, sp
+ low_word
);
951 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
953 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
954 but the register size used is only 32 bits. Make the address
955 for the saved register point to the lower 32 bits. */
956 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
957 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
959 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
961 /* Old gcc frame, r30 is virtual frame pointer. */
962 if ((long)low_word
!= PROC_FRAME_OFFSET(&temp_proc_desc
))
963 frame_addr
= sp
+ low_word
;
964 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
966 unsigned alloca_adjust
;
967 PROC_FRAME_REG (&temp_proc_desc
) = 30;
968 frame_addr
= read_next_frame_reg(next_frame
, 30);
969 alloca_adjust
= (unsigned)(frame_addr
- (sp
+ low_word
));
970 if (alloca_adjust
> 0)
972 /* FP > SP + frame_size. This may be because
973 * of an alloca or somethings similar.
974 * Fix sp to "pre-alloca" value, and try again.
981 /* move $30,$sp. With different versions of gas this will be either
982 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
983 Accept any one of these. */
984 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
986 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
987 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
989 unsigned alloca_adjust
;
990 PROC_FRAME_REG (&temp_proc_desc
) = 30;
991 frame_addr
= read_next_frame_reg(next_frame
, 30);
992 alloca_adjust
= (unsigned)(frame_addr
- sp
);
993 if (alloca_adjust
> 0)
995 /* FP > SP + frame_size. This may be because
996 * of an alloca or somethings similar.
997 * Fix sp to "pre-alloca" value, and try again.
1004 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1006 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1007 set_reg_offset (reg
, frame_addr
+ low_word
);
1012 static mips_extra_func_info_t
1013 heuristic_proc_desc(start_pc
, limit_pc
, next_frame
)
1014 CORE_ADDR start_pc
, limit_pc
;
1015 struct frame_info
*next_frame
;
1017 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1019 if (start_pc
== 0) return NULL
;
1020 memset (&temp_proc_desc
, '\0', sizeof(temp_proc_desc
));
1021 memset (&temp_saved_regs
, '\0', sizeof(struct frame_saved_regs
));
1022 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1023 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1024 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1026 if (start_pc
+ 200 < limit_pc
)
1027 limit_pc
= start_pc
+ 200;
1028 if (pc_is_mips16 (start_pc
))
1029 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1031 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1032 return &temp_proc_desc
;
1035 static mips_extra_func_info_t
1036 non_heuristic_proc_desc (pc
, addrptr
)
1040 CORE_ADDR startaddr
;
1041 mips_extra_func_info_t proc_desc
;
1042 struct block
*b
= block_for_pc(pc
);
1045 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1047 *addrptr
= startaddr
;
1048 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1052 if (startaddr
> BLOCK_START (b
))
1053 /* This is the "pathological" case referred to in a comment in
1054 print_frame_info. It might be better to move this check into
1058 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1061 /* If we never found a PDR for this function in symbol reading, then
1062 examine prologues to find the information. */
1065 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1066 if (PROC_FRAME_REG (proc_desc
) == -1)
1076 static mips_extra_func_info_t
1077 find_proc_desc (pc
, next_frame
)
1079 struct frame_info
*next_frame
;
1081 mips_extra_func_info_t proc_desc
;
1082 CORE_ADDR startaddr
;
1084 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1088 /* IF this is the topmost frame AND
1089 * (this proc does not have debugging information OR
1090 * the PC is in the procedure prologue)
1091 * THEN create a "heuristic" proc_desc (by analyzing
1092 * the actual code) to replace the "official" proc_desc.
1094 if (next_frame
== NULL
)
1096 struct symtab_and_line val
;
1097 struct symbol
*proc_symbol
=
1098 PROC_DESC_IS_DUMMY(proc_desc
) ? 0 : PROC_SYMBOL(proc_desc
);
1102 val
= find_pc_line (BLOCK_START
1103 (SYMBOL_BLOCK_VALUE(proc_symbol
)),
1105 val
.pc
= val
.end
? val
.end
: pc
;
1107 if (!proc_symbol
|| pc
< val
.pc
)
1109 mips_extra_func_info_t found_heuristic
=
1110 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1112 if (found_heuristic
)
1113 proc_desc
= found_heuristic
;
1119 /* Is linked_proc_desc_table really necessary? It only seems to be used
1120 by procedure call dummys. However, the procedures being called ought
1121 to have their own proc_descs, and even if they don't,
1122 heuristic_proc_desc knows how to create them! */
1124 register struct linked_proc_info
*link
;
1126 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1127 if (PROC_LOW_ADDR(&link
->info
) <= pc
1128 && PROC_HIGH_ADDR(&link
->info
) > pc
)
1132 startaddr
= heuristic_proc_start (pc
);
1135 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1141 get_frame_pointer(frame
, proc_desc
)
1142 struct frame_info
*frame
;
1143 mips_extra_func_info_t proc_desc
;
1145 return ADDR_BITS_REMOVE (
1146 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1147 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1150 mips_extra_func_info_t cached_proc_desc
;
1153 mips_frame_chain(frame
)
1154 struct frame_info
*frame
;
1156 mips_extra_func_info_t proc_desc
;
1158 CORE_ADDR saved_pc
= FRAME_SAVED_PC(frame
);
1160 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1163 /* Check if the PC is inside a call stub. If it is, fetch the
1164 PC of the caller of that stub. */
1165 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1168 /* Look up the procedure descriptor for this PC. */
1169 proc_desc
= find_proc_desc(saved_pc
, frame
);
1173 cached_proc_desc
= proc_desc
;
1175 /* If no frame pointer and frame size is zero, we must be at end
1176 of stack (or otherwise hosed). If we don't check frame size,
1177 we loop forever if we see a zero size frame. */
1178 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1179 && PROC_FRAME_OFFSET (proc_desc
) == 0
1180 /* The previous frame from a sigtramp frame might be frameless
1181 and have frame size zero. */
1182 && !frame
->signal_handler_caller
)
1185 return get_frame_pointer (frame
, proc_desc
);
1189 init_extra_frame_info(fci
)
1190 struct frame_info
*fci
;
1194 /* Use proc_desc calculated in frame_chain */
1195 mips_extra_func_info_t proc_desc
=
1196 fci
->next
? cached_proc_desc
: find_proc_desc(fci
->pc
, fci
->next
);
1198 fci
->saved_regs
= NULL
;
1200 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1203 /* Fixup frame-pointer - only needed for top frame */
1204 /* This may not be quite right, if proc has a real frame register.
1205 Get the value of the frame relative sp, procedure might have been
1206 interrupted by a signal at it's very start. */
1207 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1208 && !PROC_DESC_IS_DUMMY (proc_desc
))
1209 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1211 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1213 if (proc_desc
== &temp_proc_desc
)
1217 /* Do not set the saved registers for a sigtramp frame,
1218 mips_find_saved_registers will do that for us.
1219 We can't use fci->signal_handler_caller, it is not yet set. */
1220 find_pc_partial_function (fci
->pc
, &name
,
1221 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
1222 if (!IN_SIGTRAMP (fci
->pc
, name
))
1224 fci
->saved_regs
= (struct frame_saved_regs
*)
1225 obstack_alloc (&frame_cache_obstack
,
1226 sizeof (struct frame_saved_regs
));
1227 *fci
->saved_regs
= temp_saved_regs
;
1228 fci
->saved_regs
->regs
[PC_REGNUM
]
1229 = fci
->saved_regs
->regs
[RA_REGNUM
];
1233 /* hack: if argument regs are saved, guess these contain args */
1234 fci
->num_args
= -1; /* assume we can't tell how many args for now */
1235 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1237 if (PROC_REG_MASK(proc_desc
) & (1 << regnum
))
1239 fci
->num_args
= regnum
- A0_REGNUM
+ 1;
1246 /* MIPS stack frames are almost impenetrable. When execution stops,
1247 we basically have to look at symbol information for the function
1248 that we stopped in, which tells us *which* register (if any) is
1249 the base of the frame pointer, and what offset from that register
1250 the frame itself is at.
1252 This presents a problem when trying to examine a stack in memory
1253 (that isn't executing at the moment), using the "frame" command. We
1254 don't have a PC, nor do we have any registers except SP.
1256 This routine takes two arguments, SP and PC, and tries to make the
1257 cached frames look as if these two arguments defined a frame on the
1258 cache. This allows the rest of info frame to extract the important
1259 arguments without difficulty. */
1262 setup_arbitrary_frame (argc
, argv
)
1267 error ("MIPS frame specifications require two arguments: sp and pc");
1269 return create_new_frame (argv
[0], argv
[1]);
1273 mips_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
1278 CORE_ADDR struct_addr
;
1284 int stack_offset
= 0;
1286 /* Macros to round N up or down to the next A boundary; A must be
1288 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1289 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1291 /* First ensure that the stack and structure return address (if any)
1292 are properly aligned. The stack has to be 64-bit aligned even
1293 on 32-bit machines, because doubles must be 64-bit aligned. */
1294 sp
= ROUND_DOWN (sp
, 8);
1295 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_REGSIZE
);
1297 /* Now make space on the stack for the args. We allocate more
1298 than necessary for EABI, because the first few arguments are
1299 passed in registers, but that's OK. */
1300 for (argnum
= 0; argnum
< nargs
; argnum
++)
1301 len
+= ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args
[argnum
])), MIPS_REGSIZE
);
1302 sp
-= ROUND_UP (len
, 8);
1304 /* Initialize the integer and float register pointers. */
1306 float_argreg
= FPA0_REGNUM
;
1308 /* the struct_return pointer occupies the first parameter-passing reg */
1310 write_register (argreg
++, struct_addr
);
1312 /* Now load as many as possible of the first arguments into
1313 registers, and push the rest onto the stack. Loop thru args
1314 from first to last. */
1315 for (argnum
= 0; argnum
< nargs
; argnum
++)
1318 char valbuf
[REGISTER_RAW_SIZE(A0_REGNUM
)];
1319 value_ptr arg
= args
[argnum
];
1320 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1321 int len
= TYPE_LENGTH (arg_type
);
1322 enum type_code typecode
= TYPE_CODE (arg_type
);
1324 /* The EABI passes structures that do not fit in a register by
1325 reference. In all other cases, pass the structure by value. */
1326 if (MIPS_EABI
&& len
> MIPS_REGSIZE
&&
1327 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1329 store_address (valbuf
, MIPS_REGSIZE
, VALUE_ADDRESS (arg
));
1330 typecode
= TYPE_CODE_PTR
;
1335 val
= (char *)VALUE_CONTENTS (arg
);
1337 /* 32-bit ABIs always start floating point arguments in an
1338 even-numbered floating point register. */
1339 if (!GDB_TARGET_IS_MIPS64
&& typecode
== TYPE_CODE_FLT
1340 && (float_argreg
& 1))
1343 /* Floating point arguments passed in registers have to be
1344 treated specially. On 32-bit architectures, doubles
1345 are passed in register pairs; the even register gets
1346 the low word, and the odd register gets the high word.
1347 On non-EABI processors, the first two floating point arguments are
1348 also copied to general registers, because MIPS16 functions
1349 don't use float registers for arguments. This duplication of
1350 arguments in general registers can't hurt non-MIPS16 functions
1351 because those registers are normally skipped. */
1352 if (typecode
== TYPE_CODE_FLT
1353 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
1354 && mips_fpu
!= MIPS_FPU_NONE
)
1356 if (!GDB_TARGET_IS_MIPS64
&& len
== 8)
1358 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
1359 unsigned long regval
;
1361 /* Write the low word of the double to the even register(s). */
1362 regval
= extract_unsigned_integer (val
+low_offset
, 4);
1363 write_register (float_argreg
++, regval
);
1365 write_register (argreg
+1, regval
);
1367 /* Write the high word of the double to the odd register(s). */
1368 regval
= extract_unsigned_integer (val
+4-low_offset
, 4);
1369 write_register (float_argreg
++, regval
);
1372 write_register (argreg
, regval
);
1379 /* This is a floating point value that fits entirely
1380 in a single register. */
1381 CORE_ADDR regval
= extract_address (val
, len
);
1382 write_register (float_argreg
++, regval
);
1385 write_register (argreg
, regval
);
1386 argreg
+= GDB_TARGET_IS_MIPS64
? 1 : 2;
1392 /* Copy the argument to general registers or the stack in
1393 register-sized pieces. Large arguments are split between
1394 registers and stack. */
1395 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
1396 are treated specially: Irix cc passes them in registers
1397 where gcc sometimes puts them on the stack. For maximum
1398 compatibility, we will put them in both places. */
1400 int odd_sized_struct
= ((len
> MIPS_REGSIZE
) &&
1401 (len
% MIPS_REGSIZE
!= 0));
1404 int partial_len
= len
< MIPS_REGSIZE
? len
: MIPS_REGSIZE
;
1406 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
1408 /* Write this portion of the argument to the stack. */
1409 int longword_offset
;
1411 longword_offset
= 0;
1412 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1413 if (MIPS_REGSIZE
== 8 &&
1414 (typecode
== TYPE_CODE_INT
||
1415 typecode
== TYPE_CODE_PTR
||
1416 typecode
== TYPE_CODE_FLT
) && len
<= 4)
1417 longword_offset
= 4;
1418 else if ((typecode
== TYPE_CODE_STRUCT
||
1419 typecode
== TYPE_CODE_UNION
) &&
1420 TYPE_LENGTH (arg_type
) < MIPS_REGSIZE
)
1421 longword_offset
= MIPS_REGSIZE
- len
;
1423 write_memory (sp
+ stack_offset
+ longword_offset
,
1427 /* Note!!! This is NOT an else clause.
1428 Odd sized structs may go thru BOTH paths. */
1429 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
1431 CORE_ADDR regval
= extract_address (val
, partial_len
);
1433 /* A non-floating-point argument being passed in a
1434 general register. If a struct or union, and if
1435 the remaining length is smaller than the register
1436 size, we have to adjust the register value on
1439 It does not seem to be necessary to do the
1440 same for integral types.
1442 Also don't do this adjustment on EABI targets. */
1445 TARGET_BYTE_ORDER
== BIG_ENDIAN
&&
1446 partial_len
< MIPS_REGSIZE
&&
1447 (typecode
== TYPE_CODE_STRUCT
||
1448 typecode
== TYPE_CODE_UNION
))
1449 regval
<<= ((MIPS_REGSIZE
- partial_len
) *
1452 write_register (argreg
, regval
);
1455 /* If this is the old ABI, prevent subsequent floating
1456 point arguments from being passed in floating point
1459 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
1465 /* The offset onto the stack at which we will start
1466 copying parameters (after the registers are used up)
1467 begins at (4 * MIPS_REGSIZE) in the old ABI. This
1468 leaves room for the "home" area for register parameters.
1470 In the new EABI, the 8 register parameters do not
1471 have "home" stack space reserved for them, so the
1472 stack offset does not get incremented until after
1473 we have used up the 8 parameter registers. */
1474 if (!(MIPS_EABI
&& argnum
< 8))
1475 stack_offset
+= ROUND_UP (partial_len
, MIPS_REGSIZE
);
1480 /* Set the return address register to point to the entry
1481 point of the program, where a breakpoint lies in wait. */
1482 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS());
1484 /* Return adjusted stack pointer. */
1489 mips_push_register(CORE_ADDR
*sp
, int regno
)
1491 char buffer
[MAX_REGISTER_RAW_SIZE
];
1492 int regsize
= REGISTER_RAW_SIZE (regno
);
1495 read_register_gen (regno
, buffer
);
1496 write_memory (*sp
, buffer
, regsize
);
1499 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
1500 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
1503 mips_push_dummy_frame()
1506 struct linked_proc_info
*link
= (struct linked_proc_info
*)
1507 xmalloc(sizeof(struct linked_proc_info
));
1508 mips_extra_func_info_t proc_desc
= &link
->info
;
1509 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
1510 CORE_ADDR old_sp
= sp
;
1511 link
->next
= linked_proc_desc_table
;
1512 linked_proc_desc_table
= link
;
1514 /* FIXME! are these correct ? */
1515 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
1516 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
1517 #define FLOAT_REG_SAVE_MASK MASK(0,19)
1518 #define FLOAT_SINGLE_REG_SAVE_MASK \
1519 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
1521 * The registers we must save are all those not preserved across
1522 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
1523 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
1524 * and FP Control/Status registers.
1527 * Dummy frame layout:
1530 * Saved MMHI, MMLO, FPC_CSR
1535 * Saved D18 (i.e. F19, F18)
1537 * Saved D0 (i.e. F1, F0)
1538 * Argument build area and stack arguments written via mips_push_arguments
1542 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
1543 PROC_FRAME_REG(proc_desc
) = PUSH_FP_REGNUM
;
1544 PROC_FRAME_OFFSET(proc_desc
) = 0;
1545 PROC_FRAME_ADJUST(proc_desc
) = 0;
1546 mips_push_register (&sp
, PC_REGNUM
);
1547 mips_push_register (&sp
, HI_REGNUM
);
1548 mips_push_register (&sp
, LO_REGNUM
);
1549 mips_push_register (&sp
, mips_fpu
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
1551 /* Save general CPU registers */
1552 PROC_REG_MASK(proc_desc
) = GEN_REG_SAVE_MASK
;
1553 PROC_REG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved R31) from FP */
1554 for (ireg
= 32; --ireg
>= 0; )
1555 if (PROC_REG_MASK(proc_desc
) & (1 << ireg
))
1556 mips_push_register (&sp
, ireg
);
1558 /* Save floating point registers starting with high order word */
1559 PROC_FREG_MASK(proc_desc
) =
1560 mips_fpu
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
1561 : mips_fpu
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
1562 PROC_FREG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved D18) from FP */
1563 for (ireg
= 32; --ireg
>= 0; )
1564 if (PROC_FREG_MASK(proc_desc
) & (1 << ireg
))
1565 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
1567 /* Update the frame pointer for the call dummy and the stack pointer.
1568 Set the procedure's starting and ending addresses to point to the
1569 call dummy address at the entry point. */
1570 write_register (PUSH_FP_REGNUM
, old_sp
);
1571 write_register (SP_REGNUM
, sp
);
1572 PROC_LOW_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS();
1573 PROC_HIGH_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS() + 4;
1574 SET_PROC_DESC_IS_DUMMY(proc_desc
);
1575 PROC_PC_REG(proc_desc
) = RA_REGNUM
;
1581 register int regnum
;
1582 struct frame_info
*frame
= get_current_frame ();
1583 CORE_ADDR new_sp
= FRAME_FP (frame
);
1585 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
1587 write_register (PC_REGNUM
, FRAME_SAVED_PC(frame
));
1588 if (frame
->saved_regs
== NULL
)
1589 mips_find_saved_regs (frame
);
1590 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1592 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
1593 && frame
->saved_regs
->regs
[regnum
])
1594 write_register (regnum
,
1595 read_memory_integer (frame
->saved_regs
->regs
[regnum
],
1598 write_register (SP_REGNUM
, new_sp
);
1599 flush_cached_frames ();
1601 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
1603 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
1605 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
1607 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
1609 if (&pi_ptr
->info
== proc_desc
)
1614 error ("Can't locate dummy extra frame info\n");
1616 if (prev_ptr
!= NULL
)
1617 prev_ptr
->next
= pi_ptr
->next
;
1619 linked_proc_desc_table
= pi_ptr
->next
;
1623 write_register (HI_REGNUM
,
1624 read_memory_integer (new_sp
- 2*MIPS_REGSIZE
, MIPS_REGSIZE
));
1625 write_register (LO_REGNUM
,
1626 read_memory_integer (new_sp
- 3*MIPS_REGSIZE
, MIPS_REGSIZE
));
1627 if (mips_fpu
!= MIPS_FPU_NONE
)
1628 write_register (FCRCS_REGNUM
,
1629 read_memory_integer (new_sp
- 4*MIPS_REGSIZE
, MIPS_REGSIZE
));
1634 mips_print_register (regnum
, all
)
1637 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
1639 /* Get the data in raw format. */
1640 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
1642 printf_filtered ("%s: [Invalid]", reg_names
[regnum
]);
1646 /* If an even floating point register, also print as double. */
1647 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
1648 && !((regnum
-FP0_REGNUM
) & 1))
1649 if (REGISTER_RAW_SIZE(regnum
) == 4) /* this would be silly on MIPS64 */
1651 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
1653 read_relative_register_raw_bytes (regnum
, dbuffer
);
1654 read_relative_register_raw_bytes (regnum
+1, dbuffer
+MIPS_REGSIZE
);
1655 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
1657 printf_filtered ("(d%d: ", regnum
-FP0_REGNUM
);
1658 val_print (builtin_type_double
, dbuffer
, 0,
1659 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1660 printf_filtered ("); ");
1662 fputs_filtered (reg_names
[regnum
], gdb_stdout
);
1664 /* The problem with printing numeric register names (r26, etc.) is that
1665 the user can't use them on input. Probably the best solution is to
1666 fix it so that either the numeric or the funky (a2, etc.) names
1667 are accepted on input. */
1668 if (regnum
< MIPS_NUMREGS
)
1669 printf_filtered ("(r%d): ", regnum
);
1671 printf_filtered (": ");
1673 /* If virtual format is floating, print it that way. */
1674 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1675 if (REGISTER_RAW_SIZE(regnum
) == 8)
1676 { /* show 8-byte floats as float AND double: */
1677 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
1679 printf_filtered (" (float) ");
1680 val_print (builtin_type_float
, raw_buffer
+ offset
, 0,
1681 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1682 printf_filtered (", (double) ");
1683 val_print (builtin_type_double
, raw_buffer
, 0,
1684 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1687 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0,
1688 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1689 /* Else print as integer in hex. */
1691 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
1692 'x', 0, gdb_stdout
);
1695 /* Replacement for generic do_registers_info.
1696 Print regs in pretty columns. */
1699 do_fp_register_row (regnum
)
1701 { /* do values for FP (float) regs */
1702 char raw_buffer
[2] [REGISTER_RAW_SIZE(FP0_REGNUM
)];
1703 char dbl_buffer
[2 * REGISTER_RAW_SIZE(FP0_REGNUM
)];
1704 /* use HI and LO to control the order of combining two flt regs */
1705 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
1706 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
1707 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
1708 int inv1
, inv2
, inv3
;
1710 /* Get the data in raw format. */
1711 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
1712 error ("can't read register %d (%s)", regnum
, reg_names
[regnum
]);
1713 if (REGISTER_RAW_SIZE(regnum
) == 4)
1715 /* 4-byte registers: we can fit two registers per row. */
1716 /* Also print every pair of 4-byte regs as an 8-byte double. */
1717 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
1718 error ("can't read register %d (%s)",
1719 regnum
+ 1, reg_names
[regnum
+ 1]);
1721 /* copy the two floats into one double, and unpack both */
1722 memcpy (dbl_buffer
, raw_buffer
, sizeof(dbl_buffer
));
1723 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
1724 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
1725 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
1727 printf_filtered (inv1
? " %-5s: <invalid float>" :
1728 " %-5s%-17.9g", reg_names
[regnum
], flt1
);
1729 printf_filtered (inv2
? " %-5s: <invalid float>" :
1730 " %-5s%-17.9g", reg_names
[regnum
+ 1], flt2
);
1731 printf_filtered (inv3
? " dbl: <invalid double>\n" :
1732 " dbl: %-24.17g\n", doub
);
1733 /* may want to do hex display here (future enhancement) */
1737 { /* eight byte registers: print each one as float AND as double. */
1738 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
1740 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof(dbl_buffer
));
1741 flt1
= unpack_double (builtin_type_float
,
1742 &raw_buffer
[HI
][offset
], &inv1
);
1743 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
1745 printf_filtered (inv1
? " %-5s: <invalid float>" :
1746 " %-5s flt: %-17.9g", reg_names
[regnum
], flt1
);
1747 printf_filtered (inv3
? " dbl: <invalid double>\n" :
1748 " dbl: %-24.17g\n", doub
);
1749 /* may want to do hex display here (future enhancement) */
1755 /* Print a row's worth of GP (int) registers, with name labels above */
1758 do_gp_register_row (regnum
)
1760 { /* do values for GP (int) regs */
1761 char raw_buffer
[REGISTER_RAW_SIZE(0)];
1762 int ncols
= MIPS_REGSIZE
== 8 ? 4 : 8; /* display cols per row */
1763 int col
, byte
, start_regnum
= regnum
;
1765 /* For GP registers, we print a separate row of names above the vals */
1766 printf_filtered (" ");
1767 for (col
= 0; col
< ncols
&& regnum
< NUM_REGS
; regnum
++)
1769 if (*reg_names
[regnum
] == '\0')
1770 continue; /* unused register */
1771 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1772 break; /* end the row: reached FP register */
1773 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
1777 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
1778 start_regnum
); /* print the R0 to R31 names */
1780 regnum
= start_regnum
; /* go back to start of row */
1781 /* now print the values in hex, 4 or 8 to the row */
1782 for (col
= 0; col
< ncols
&& regnum
< NUM_REGS
; regnum
++)
1784 if (*reg_names
[regnum
] == '\0')
1785 continue; /* unused register */
1786 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1787 break; /* end row: reached FP register */
1788 /* OK: get the data in raw format. */
1789 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
1790 error ("can't read register %d (%s)", regnum
, reg_names
[regnum
]);
1791 /* Now print the register value in hex, endian order. */
1792 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1793 for (byte
= 0; byte
< REGISTER_RAW_SIZE (regnum
); byte
++)
1794 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
1796 for (byte
= REGISTER_RAW_SIZE (regnum
) - 1; byte
>= 0; byte
--)
1797 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
1798 printf_filtered (" ");
1801 if (col
> 0) /* ie. if we actually printed anything... */
1802 printf_filtered ("\n");
1807 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
1810 mips_do_registers_info (regnum
, fpregs
)
1814 if (regnum
!= -1) /* do one specified register */
1816 if (*(reg_names
[regnum
]) == '\0')
1817 error ("Not a valid register for the current processor type");
1819 mips_print_register (regnum
, 0);
1820 printf_filtered ("\n");
1822 else /* do all (or most) registers */
1825 while (regnum
< NUM_REGS
)
1826 if (TYPE_CODE(REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1827 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
1828 regnum
= do_fp_register_row (regnum
); /* FP regs */
1830 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
1832 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
1836 /* Return number of args passed to a frame. described by FIP.
1837 Can return -1, meaning no way to tell. */
1840 mips_frame_num_args (frame
)
1841 struct frame_info
*frame
;
1843 #if 0 /* FIXME Use or lose this! */
1844 struct chain_info_t
*p
;
1846 p
= mips_find_cached_frame (FRAME_FP (frame
));
1848 return p
->the_info
.numargs
;
1853 /* Is this a branch with a delay slot? */
1855 static int is_delayed
PARAMS ((unsigned long));
1862 for (i
= 0; i
< NUMOPCODES
; ++i
)
1863 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
1864 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
1866 return (i
< NUMOPCODES
1867 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
1868 | INSN_COND_BRANCH_DELAY
1869 | INSN_COND_BRANCH_LIKELY
)));
1873 mips_step_skips_delay (pc
)
1876 char buf
[MIPS_INSTLEN
];
1878 /* There is no branch delay slot on MIPS16. */
1879 if (pc_is_mips16 (pc
))
1882 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
1883 /* If error reading memory, guess that it is not a delayed branch. */
1885 return is_delayed ((unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
));
1889 /* Skip the PC past function prologue instructions (32-bit version).
1890 This is a helper function for mips_skip_prologue. */
1893 mips32_skip_prologue (pc
, lenient
)
1894 CORE_ADDR pc
; /* starting PC to search from */
1899 int seen_sp_adjust
= 0;
1900 int load_immediate_bytes
= 0;
1902 /* Skip the typical prologue instructions. These are the stack adjustment
1903 instruction and the instructions that save registers on the stack
1904 or in the gcc frame. */
1905 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
1907 unsigned long high_word
;
1909 inst
= mips_fetch_instruction (pc
);
1910 high_word
= (inst
>> 16) & 0xffff;
1913 if (lenient
&& is_delayed (inst
))
1917 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
1918 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
1920 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
1921 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
1923 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
1924 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
1925 && (inst
& 0x001F0000)) /* reg != $zero */
1928 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
1930 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
1932 continue; /* reg != $zero */
1934 /* move $s8,$sp. With different versions of gas this will be either
1935 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
1936 Accept any one of these. */
1937 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1940 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
1942 else if (high_word
== 0x3c1c) /* lui $gp,n */
1944 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
1946 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1947 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
1949 /* The following instructions load $at or $t0 with an immediate
1950 value in preparation for a stack adjustment via
1951 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
1952 a local variable, so we accept them only before a stack adjustment
1953 instruction was seen. */
1954 else if (!seen_sp_adjust
)
1956 if (high_word
== 0x3c01 || /* lui $at,n */
1957 high_word
== 0x3c08) /* lui $t0,n */
1959 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
1962 else if (high_word
== 0x3421 || /* ori $at,$at,n */
1963 high_word
== 0x3508 || /* ori $t0,$t0,n */
1964 high_word
== 0x3401 || /* ori $at,$zero,n */
1965 high_word
== 0x3408) /* ori $t0,$zero,n */
1967 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
1977 /* In a frameless function, we might have incorrectly
1978 skipped some load immediate instructions. Undo the skipping
1979 if the load immediate was not followed by a stack adjustment. */
1980 if (load_immediate_bytes
&& !seen_sp_adjust
)
1981 pc
-= load_immediate_bytes
;
1985 /* Skip the PC past function prologue instructions (16-bit version).
1986 This is a helper function for mips_skip_prologue. */
1989 mips16_skip_prologue (pc
, lenient
)
1990 CORE_ADDR pc
; /* starting PC to search from */
1994 int extend_bytes
= 0;
1995 int prev_extend_bytes
;
1997 /* Table of instructions likely to be found in a function prologue. */
2000 unsigned short inst
;
2001 unsigned short mask
;
2004 { 0x6300, 0xff00 }, /* addiu $sp,offset */
2005 { 0xfb00, 0xff00 }, /* daddiu $sp,offset */
2006 { 0xd000, 0xf800 }, /* sw reg,n($sp) */
2007 { 0xf900, 0xff00 }, /* sd reg,n($sp) */
2008 { 0x6200, 0xff00 }, /* sw $ra,n($sp) */
2009 { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */
2010 { 0x673d, 0xffff }, /* move $s1,sp */
2011 { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */
2012 { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */
2013 { 0xe809, 0xf81f }, /* entry pseudo-op */
2014 { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */
2015 { 0, 0 } /* end of table marker */
2018 /* Skip the typical prologue instructions. These are the stack adjustment
2019 instruction and the instructions that save registers on the stack
2020 or in the gcc frame. */
2021 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2023 unsigned short inst
;
2026 inst
= mips_fetch_instruction (pc
);
2028 /* Normally we ignore an extend instruction. However, if it is
2029 not followed by a valid prologue instruction, we must adjust
2030 the pc back over the extend so that it won't be considered
2031 part of the prologue. */
2032 if ((inst
& 0xf800) == 0xf000) /* extend */
2034 extend_bytes
= MIPS16_INSTLEN
;
2037 prev_extend_bytes
= extend_bytes
;
2040 /* Check for other valid prologue instructions besides extend. */
2041 for (i
= 0; table
[i
].mask
!= 0; i
++)
2042 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2044 if (table
[i
].mask
!= 0) /* it was in table? */
2045 continue; /* ignore it */
2046 else /* non-prologue */
2048 /* Return the current pc, adjusted backwards by 2 if
2049 the previous instruction was an extend. */
2050 return pc
- prev_extend_bytes
;
2056 /* To skip prologues, I use this predicate. Returns either PC itself
2057 if the code at PC does not look like a function prologue; otherwise
2058 returns an address that (if we're lucky) follows the prologue. If
2059 LENIENT, then we must skip everything which is involved in setting
2060 up the frame (it's OK to skip more, just so long as we don't skip
2061 anything which might clobber the registers which are being saved.
2062 We must skip more in the case where part of the prologue is in the
2063 delay slot of a non-prologue instruction). */
2066 mips_skip_prologue (pc
, lenient
)
2070 /* See if we can determine the end of the prologue via the symbol table.
2071 If so, then return either PC, or the PC after the prologue, whichever
2074 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2076 if (post_prologue_pc
!= 0)
2077 return max (pc
, post_prologue_pc
);
2079 /* Can't determine prologue from the symbol table, need to examine
2082 if (pc_is_mips16 (pc
))
2083 return mips16_skip_prologue (pc
, lenient
);
2085 return mips32_skip_prologue (pc
, lenient
);
2089 /* The lenient prologue stuff should be superseded by the code in
2090 init_extra_frame_info which looks to see whether the stores mentioned
2091 in the proc_desc have actually taken place. */
2093 /* Is address PC in the prologue (loosely defined) for function at
2097 mips_in_lenient_prologue (startaddr
, pc
)
2098 CORE_ADDR startaddr
;
2101 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2102 return pc
>= startaddr
&& pc
< end_prologue
;
2106 /* Given a return value in `regbuf' with a type `valtype',
2107 extract and copy its value into `valbuf'. */
2109 mips_extract_return_value (valtype
, regbuf
, valbuf
)
2110 struct type
*valtype
;
2111 char regbuf
[REGISTER_BYTES
];
2116 int len
= TYPE_LENGTH (valtype
);
2119 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2120 && (mips_fpu
== MIPS_FPU_DOUBLE
2121 || (mips_fpu
== MIPS_FPU_SINGLE
&& len
<= MIPS_REGSIZE
)))
2122 regnum
= FP0_REGNUM
;
2124 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2125 { /* "un-left-justify" the value from the register */
2126 if (len
< REGISTER_RAW_SIZE (regnum
))
2127 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2128 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2129 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2130 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2131 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2132 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2134 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
2135 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
2138 /* Given a return value in `regbuf' with a type `valtype',
2139 write it's value into the appropriate register. */
2141 mips_store_return_value (valtype
, valbuf
)
2142 struct type
*valtype
;
2147 int len
= TYPE_LENGTH (valtype
);
2148 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2151 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2152 && (mips_fpu
== MIPS_FPU_DOUBLE
2153 || (mips_fpu
== MIPS_FPU_SINGLE
&& len
<= MIPS_REGSIZE
)))
2154 regnum
= FP0_REGNUM
;
2156 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2157 { /* "left-justify" the value in the register */
2158 if (len
< REGISTER_RAW_SIZE (regnum
))
2159 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2160 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2161 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2162 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2163 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2164 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2166 memcpy(raw_buffer
+ offset
, valbuf
, len
);
2167 REGISTER_CONVERT_FROM_TYPE(regnum
, valtype
, raw_buffer
);
2168 write_register_bytes(REGISTER_BYTE (regnum
), raw_buffer
,
2169 len
> REGISTER_RAW_SIZE (regnum
) ?
2170 len
: REGISTER_RAW_SIZE (regnum
));
2173 /* Exported procedure: Is PC in the signal trampoline code */
2176 in_sigtramp (pc
, ignore
)
2178 char *ignore
; /* function name */
2180 if (sigtramp_address
== 0)
2182 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
2185 /* Command to set FPU type. mips_fpu_string will have been set to the
2186 user's argument. Set mips_fpu based on mips_fpu_string, and then
2187 canonicalize mips_fpu_string. */
2191 mips_set_fpu_command (args
, from_tty
, c
)
2194 struct cmd_list_element
*c
;
2198 if (mips_fpu_string
== NULL
|| *mips_fpu_string
== '\0')
2199 mips_fpu
= MIPS_FPU_DOUBLE
;
2200 else if (strcasecmp (mips_fpu_string
, "double") == 0
2201 || strcasecmp (mips_fpu_string
, "on") == 0
2202 || strcasecmp (mips_fpu_string
, "1") == 0
2203 || strcasecmp (mips_fpu_string
, "yes") == 0)
2204 mips_fpu
= MIPS_FPU_DOUBLE
;
2205 else if (strcasecmp (mips_fpu_string
, "none") == 0
2206 || strcasecmp (mips_fpu_string
, "off") == 0
2207 || strcasecmp (mips_fpu_string
, "0") == 0
2208 || strcasecmp (mips_fpu_string
, "no") == 0)
2209 mips_fpu
= MIPS_FPU_NONE
;
2210 else if (strcasecmp (mips_fpu_string
, "single") == 0)
2211 mips_fpu
= MIPS_FPU_SINGLE
;
2213 err
= strsave (mips_fpu_string
);
2215 if (mips_fpu_string
!= NULL
)
2216 free (mips_fpu_string
);
2220 case MIPS_FPU_DOUBLE
:
2221 mips_fpu_string
= strsave ("double");
2223 case MIPS_FPU_SINGLE
:
2224 mips_fpu_string
= strsave ("single");
2227 mips_fpu_string
= strsave ("none");
2233 struct cleanup
*cleanups
= make_cleanup (free
, err
);
2234 error ("Unknown FPU type `%s'. Use `double', `none', or `single'.",
2236 do_cleanups (cleanups
);
2241 mips_show_fpu_command (args
, from_tty
, c
)
2244 struct cmd_list_element
*c
;
2248 /* Command to set the processor type. */
2251 mips_set_processor_type_command (args
, from_tty
)
2257 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
2259 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
2260 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2261 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
2263 /* Restore the value. */
2264 tmp_mips_processor_type
= strsave (mips_processor_type
);
2269 if (!mips_set_processor_type (tmp_mips_processor_type
))
2271 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
2272 /* Restore its value. */
2273 tmp_mips_processor_type
= strsave (mips_processor_type
);
2278 mips_show_processor_type_command (args
, from_tty
)
2284 /* Modify the actual processor type. */
2287 mips_set_processor_type (str
)
2295 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2297 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
2299 mips_processor_type
= str
;
2301 for (j
= 0; j
< NUM_REGS
; ++j
)
2302 reg_names
[j
] = mips_processor_type_table
[i
].regnames
[j
];
2306 /* FIXME tweak fpu flag too */
2313 /* Attempt to identify the particular processor model by reading the
2317 mips_read_processor_type ()
2321 prid
= read_register (PRID_REGNUM
);
2323 if ((prid
& ~0xf) == 0x700)
2324 return savestring ("r3041", strlen("r3041"));
2329 /* Just like reinit_frame_cache, but with the right arguments to be
2330 callable as an sfunc. */
2333 reinit_frame_cache_sfunc (args
, from_tty
, c
)
2336 struct cmd_list_element
*c
;
2338 reinit_frame_cache ();
2342 gdb_print_insn_mips (memaddr
, info
)
2344 disassemble_info
*info
;
2346 mips_extra_func_info_t proc_desc
;
2348 /* Search for the function containing this address. Set the low bit
2349 of the address when searching, in case we were given an even address
2350 that is the start of a 16-bit function. If we didn't do this,
2351 the search would fail because the symbol table says the function
2352 starts at an odd address, i.e. 1 byte past the given address. */
2353 memaddr
= ADDR_BITS_REMOVE (memaddr
);
2354 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
2356 /* Make an attempt to determine if this is a 16-bit function. If
2357 the procedure descriptor exists and the address therein is odd,
2358 it's definitely a 16-bit function. Otherwise, we have to just
2359 guess that if the address passed in is odd, it's 16-bits. */
2361 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : 0;
2363 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : 0;
2365 /* Round down the instruction address to the appropriate boundary. */
2366 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
2368 /* Call the appropriate disassembler based on the target endian-ness. */
2369 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2370 return print_insn_big_mips (memaddr
, info
);
2372 return print_insn_little_mips (memaddr
, info
);
2375 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
2376 counter value to determine whether a 16- or 32-bit breakpoint should be
2377 used. It returns a pointer to a string of bytes that encode a breakpoint
2378 instruction, stores the length of the string to *lenptr, and adjusts pc
2379 (if necessary) to point to the actual memory location where the
2380 breakpoint should be inserted. */
2382 unsigned char *mips_breakpoint_from_pc (pcptr
, lenptr
)
2386 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2388 if (pc_is_mips16 (*pcptr
))
2390 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
2391 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2392 *lenptr
= sizeof(mips16_big_breakpoint
);
2393 return mips16_big_breakpoint
;
2397 static char big_breakpoint
[] = BIG_BREAKPOINT
;
2398 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
2399 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
2401 *lenptr
= sizeof(big_breakpoint
);
2403 if (strcmp (target_shortname
, "mips") == 0)
2404 return idt_big_breakpoint
;
2405 else if (strcmp (target_shortname
, "ddb") == 0
2406 || strcmp (target_shortname
, "pmon") == 0
2407 || strcmp (target_shortname
, "lsi") == 0)
2408 return pmon_big_breakpoint
;
2410 return big_breakpoint
;
2415 if (pc_is_mips16 (*pcptr
))
2417 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
2418 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2419 *lenptr
= sizeof(mips16_little_breakpoint
);
2420 return mips16_little_breakpoint
;
2424 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
2425 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
2426 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
2428 *lenptr
= sizeof(little_breakpoint
);
2430 if (strcmp (target_shortname
, "mips") == 0)
2431 return idt_little_breakpoint
;
2432 else if (strcmp (target_shortname
, "ddb") == 0
2433 || strcmp (target_shortname
, "pmon") == 0
2434 || strcmp (target_shortname
, "lsi") == 0)
2435 return pmon_little_breakpoint
;
2437 return little_breakpoint
;
2442 /* Test whether the PC points to the return instruction at the
2443 end of a function. This implements the ABOUT_TO_RETURN macro. */
2446 mips_about_to_return (pc
)
2449 if (pc_is_mips16 (pc
))
2450 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2451 generates a "jr $ra"; other times it generates code to load
2452 the return address from the stack to an accessible register (such
2453 as $a3), then a "jr" using that register. This second case
2454 is almost impossible to distinguish from an indirect jump
2455 used for switch statements, so we don't even try. */
2456 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2458 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2462 /* If PC is in a mips16 call or return stub, return the address of the target
2463 PC, which is either the callee or the caller. There are several
2464 cases which must be handled:
2466 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
2467 target PC is in $31 ($ra).
2468 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
2469 and the target PC is in $2.
2470 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2471 before the jal instruction, this is effectively a call stub
2472 and the the target PC is in $2. Otherwise this is effectively
2473 a return stub and the target PC is in $18.
2475 See the source code for the stubs in gcc/config/mips/mips16.S for
2478 This function implements the SKIP_TRAMPOLINE_CODE macro.
2486 CORE_ADDR start_addr
;
2488 /* Find the starting address and name of the function containing the PC. */
2489 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2492 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
2493 target PC is in $31 ($ra). */
2494 if (strcmp (name
, "__mips16_ret_sf") == 0
2495 || strcmp (name
, "__mips16_ret_df") == 0)
2496 return read_register (RA_REGNUM
);
2498 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
2500 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
2501 and the target PC is in $2. */
2502 if (name
[19] >= '0' && name
[19] <= '9')
2503 return read_register (2);
2505 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2506 before the jal instruction, this is effectively a call stub
2507 and the the target PC is in $2. Otherwise this is effectively
2508 a return stub and the target PC is in $18. */
2509 else if (name
[19] == 's' || name
[19] == 'd')
2511 if (pc
== start_addr
)
2513 /* Check if the target of the stub is a compiler-generated
2514 stub. Such a stub for a function bar might have a name
2515 like __fn_stub_bar, and might look like this:
2520 la $1,bar (becomes a lui/addiu pair)
2522 So scan down to the lui/addi and extract the target
2523 address from those two instructions. */
2525 CORE_ADDR target_pc
= read_register (2);
2529 /* See if the name of the target function is __fn_stub_*. */
2530 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
2532 if (strncmp (name
, "__fn_stub_", 10) != 0
2533 && strcmp (name
, "etext") != 0
2534 && strcmp (name
, "_etext") != 0)
2537 /* Scan through this _fn_stub_ code for the lui/addiu pair.
2538 The limit on the search is arbitrarily set to 20
2539 instructions. FIXME. */
2540 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
2542 inst
= mips_fetch_instruction (target_pc
);
2543 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
2544 pc
= (inst
<< 16) & 0xffff0000; /* high word */
2545 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
2546 return pc
| (inst
& 0xffff); /* low word */
2549 /* Couldn't find the lui/addui pair, so return stub address. */
2553 /* This is the 'return' part of a call stub. The return
2554 address is in $r18. */
2555 return read_register (18);
2558 return 0; /* not a stub */
2562 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
2563 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
2566 mips_in_call_stub (pc
, name
)
2570 CORE_ADDR start_addr
;
2572 /* Find the starting address of the function containing the PC. If the
2573 caller didn't give us a name, look it up at the same time. */
2574 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
2577 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
2579 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
2580 if (name
[19] >= '0' && name
[19] <= '9')
2582 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2583 before the jal instruction, this is effectively a call stub. */
2584 else if (name
[19] == 's' || name
[19] == 'd')
2585 return pc
== start_addr
;
2588 return 0; /* not a stub */
2592 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
2593 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
2596 mips_in_return_stub (pc
, name
)
2600 CORE_ADDR start_addr
;
2602 /* Find the starting address of the function containing the PC. */
2603 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
2606 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
2607 if (strcmp (name
, "__mips16_ret_sf") == 0
2608 || strcmp (name
, "__mips16_ret_df") == 0)
2611 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
2612 i.e. after the jal instruction, this is effectively a return stub. */
2613 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
2614 && (name
[19] == 's' || name
[19] == 'd')
2615 && pc
!= start_addr
)
2618 return 0; /* not a stub */
2622 /* Return non-zero if the PC is in a library helper function that should
2623 be ignored. This implements the IGNORE_HELPER_CALL macro. */
2626 mips_ignore_helper (pc
)
2631 /* Find the starting address and name of the function containing the PC. */
2632 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
2635 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
2636 that we want to ignore. */
2637 return (strcmp (name
, "__mips16_ret_sf") == 0
2638 || strcmp (name
, "__mips16_ret_df") == 0);
2643 _initialize_mips_tdep ()
2645 struct cmd_list_element
*c
;
2647 tm_print_insn
= gdb_print_insn_mips
;
2649 /* Let the user turn off floating point and set the fence post for
2650 heuristic_proc_start. */
2652 c
= add_set_cmd ("mipsfpu", class_support
, var_string_noescape
,
2653 (char *) &mips_fpu_string
,
2654 "Set use of floating point coprocessor.\n\
2655 Set to `none' to avoid using floating point instructions when calling\n\
2656 functions or dealing with return values. Set to `single' to use only\n\
2657 single precision floating point as on the R4650. Set to `double' for\n\
2658 normal floating point support.",
2660 c
->function
.sfunc
= mips_set_fpu_command
;
2661 c
= add_show_from_set (c
, &showlist
);
2662 c
->function
.sfunc
= mips_show_fpu_command
;
2664 #ifndef MIPS_DEFAULT_FPU_TYPE
2665 mips_fpu
= MIPS_FPU_DOUBLE
;
2666 mips_fpu_string
= strsave ("double");
2668 mips_fpu
= MIPS_DEFAULT_FPU_TYPE
;
2671 case MIPS_FPU_DOUBLE
: mips_fpu_string
= strsave ("double"); break;
2672 case MIPS_FPU_SINGLE
: mips_fpu_string
= strsave ("single"); break;
2673 case MIPS_FPU_NONE
: mips_fpu_string
= strsave ("none"); break;
2677 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
2678 (char *) &tmp_mips_processor_type
,
2679 "Set the type of MIPS processor in use.\n\
2680 Set this to be able to access processor-type-specific registers.\n\
2683 c
->function
.cfunc
= mips_set_processor_type_command
;
2684 c
= add_show_from_set (c
, &showlist
);
2685 c
->function
.cfunc
= mips_show_processor_type_command
;
2687 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
2688 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
2690 /* We really would like to have both "0" and "unlimited" work, but
2691 command.c doesn't deal with that. So make it a var_zinteger
2692 because the user can always use "999999" or some such for unlimited. */
2693 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
2694 (char *) &heuristic_fence_post
,
2696 Set the distance searched for the start of a function.\n\
2697 If you are debugging a stripped executable, GDB needs to search through the\n\
2698 program for the start of a function. This command sets the distance of the\n\
2699 search. The only need to set it is when debugging a stripped executable.",
2701 /* We need to throw away the frame cache when we set this, since it
2702 might change our ability to get backtraces. */
2703 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
2704 add_show_from_set (c
, &showlist
);