1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 /* Some MIPS boards don't support floating point while others only
146 support single-precision floating-point operations. */
150 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
151 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
152 MIPS_FPU_NONE
/* No floating point. */
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto
= 1;
159 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
161 static int mips_debug
= 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc
*mips_tdesc_gp32
;
169 struct target_desc
*mips_tdesc_gp64
;
171 /* MIPS specific per-architecture information */
174 /* from the elf header */
178 enum mips_abi mips_abi
;
179 enum mips_abi found_abi
;
180 enum mips_fpu_type mips_fpu_type
;
181 int mips_last_arg_regnum
;
182 int mips_last_fp_arg_regnum
;
183 int default_mask_address_p
;
184 /* Is the target using 64-bit raw integer registers but only
185 storing a left-aligned 32-bit value in each? */
186 int mips64_transfers_32bit_regs_p
;
187 /* Indexes for various registers. IRIX and embedded have
188 different values. This contains the "public" fields. Don't
189 add any that do not need to be public. */
190 const struct mips_regnum
*regnum
;
191 /* Register names table for the current register set. */
192 const char **mips_processor_reg_names
;
194 /* The size of register data available from the target, if known.
195 This doesn't quite obsolete the manual
196 mips64_transfers_32bit_regs_p, since that is documented to force
197 left alignment even for big endian (very strange). */
198 int register_size_valid_p
;
202 const struct mips_regnum
*
203 mips_regnum (struct gdbarch
*gdbarch
)
205 return gdbarch_tdep (gdbarch
)->regnum
;
209 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
211 return mips_regnum (gdbarch
)->fp0
+ 12;
214 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
215 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
217 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
219 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
221 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
223 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
224 functions to test, set, or clear bit 0 of addresses. */
227 is_mips16_addr (CORE_ADDR addr
)
233 unmake_mips16_addr (CORE_ADDR addr
)
235 return ((addr
) & ~(CORE_ADDR
) 1);
238 /* Return the MIPS ABI associated with GDBARCH. */
240 mips_abi (struct gdbarch
*gdbarch
)
242 return gdbarch_tdep (gdbarch
)->mips_abi
;
246 mips_isa_regsize (struct gdbarch
*gdbarch
)
248 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
250 /* If we know how big the registers are, use that size. */
251 if (tdep
->register_size_valid_p
)
252 return tdep
->register_size
;
254 /* Fall back to the previous behavior. */
255 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
256 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
259 /* Return the currently configured (or set) saved register size. */
262 mips_abi_regsize (struct gdbarch
*gdbarch
)
264 switch (mips_abi (gdbarch
))
266 case MIPS_ABI_EABI32
:
272 case MIPS_ABI_EABI64
:
274 case MIPS_ABI_UNKNOWN
:
277 internal_error (__FILE__
, __LINE__
, _("bad switch"));
281 /* Functions for setting and testing a bit in a minimal symbol that
282 marks it as 16-bit function. The MSB of the minimal symbol's
283 "info" field is used for this purpose.
285 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
286 i.e. refers to a 16-bit function, and sets a "special" bit in a
287 minimal symbol to mark it as a 16-bit function
289 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
292 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
294 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
296 MSYMBOL_INFO (msym
) = (char *)
297 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
298 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
303 msymbol_is_special (struct minimal_symbol
*msym
)
305 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
308 /* XFER a value from the big/little/left end of the register.
309 Depending on the size of the value it might occupy the entire
310 register or just part of it. Make an allowance for this, aligning
311 things accordingly. */
314 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
315 int reg_num
, int length
,
316 enum bfd_endian endian
, gdb_byte
*in
,
317 const gdb_byte
*out
, int buf_offset
)
321 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
322 /* Need to transfer the left or right part of the register, based on
323 the targets byte order. */
327 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
329 case BFD_ENDIAN_LITTLE
:
332 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
336 internal_error (__FILE__
, __LINE__
, _("bad switch"));
339 fprintf_unfiltered (gdb_stderr
,
340 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
341 reg_num
, reg_offset
, buf_offset
, length
);
342 if (mips_debug
&& out
!= NULL
)
345 fprintf_unfiltered (gdb_stdlog
, "out ");
346 for (i
= 0; i
< length
; i
++)
347 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
350 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
353 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
355 if (mips_debug
&& in
!= NULL
)
358 fprintf_unfiltered (gdb_stdlog
, "in ");
359 for (i
= 0; i
< length
; i
++)
360 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
363 fprintf_unfiltered (gdb_stdlog
, "\n");
366 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
367 compatiblity mode. A return value of 1 means that we have
368 physical 64-bit registers, but should treat them as 32-bit registers. */
371 mips2_fp_compat (struct frame_info
*frame
)
373 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
374 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
376 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
380 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
381 in all the places we deal with FP registers. PR gdb/413. */
382 /* Otherwise check the FR bit in the status register - it controls
383 the FP compatiblity mode. If it is clear we are in compatibility
385 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
392 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
394 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
396 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
398 static struct type
*mips_float_register_type (void);
399 static struct type
*mips_double_register_type (void);
401 /* The list of available "set mips " and "show mips " commands */
403 static struct cmd_list_element
*setmipscmdlist
= NULL
;
404 static struct cmd_list_element
*showmipscmdlist
= NULL
;
406 /* Integer registers 0 thru 31 are handled explicitly by
407 mips_register_name(). Processor specific registers 32 and above
408 are listed in the following tables. */
411 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
415 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
416 "sr", "lo", "hi", "bad", "cause", "pc",
417 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
418 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
419 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
420 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
421 "fsr", "fir", "" /*"fp" */ , "",
422 "", "", "", "", "", "", "", "",
423 "", "", "", "", "", "", "", "",
426 /* Names of IDT R3041 registers. */
428 static const char *mips_r3041_reg_names
[] = {
429 "sr", "lo", "hi", "bad", "cause", "pc",
430 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
431 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
432 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
433 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
434 "fsr", "fir", "", /*"fp" */ "",
435 "", "", "bus", "ccfg", "", "", "", "",
436 "", "", "port", "cmp", "", "", "epc", "prid",
439 /* Names of tx39 registers. */
441 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
442 "sr", "lo", "hi", "bad", "cause", "pc",
443 "", "", "", "", "", "", "", "",
444 "", "", "", "", "", "", "", "",
445 "", "", "", "", "", "", "", "",
446 "", "", "", "", "", "", "", "",
448 "", "", "", "", "", "", "", "",
449 "", "", "config", "cache", "debug", "depc", "epc", ""
452 /* Names of IRIX registers. */
453 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
454 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
455 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
456 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
457 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
458 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
462 /* Return the name of the register corresponding to REGNO. */
464 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
466 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
467 /* GPR names for all ABIs other than n32/n64. */
468 static char *mips_gpr_names
[] = {
469 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
470 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
471 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
472 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
475 /* GPR names for n32 and n64 ABIs. */
476 static char *mips_n32_n64_gpr_names
[] = {
477 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
478 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
479 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
480 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
483 enum mips_abi abi
= mips_abi (gdbarch
);
485 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
486 but then don't make the raw register names visible. */
487 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
488 if (regno
< gdbarch_num_regs (gdbarch
))
491 /* The MIPS integer registers are always mapped from 0 to 31. The
492 names of the registers (which reflects the conventions regarding
493 register use) vary depending on the ABI. */
494 if (0 <= rawnum
&& rawnum
< 32)
496 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
497 return mips_n32_n64_gpr_names
[rawnum
];
499 return mips_gpr_names
[rawnum
];
501 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
502 return tdesc_register_name (gdbarch
, rawnum
);
503 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
505 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
506 return tdep
->mips_processor_reg_names
[rawnum
- 32];
509 internal_error (__FILE__
, __LINE__
,
510 _("mips_register_name: bad register number %d"), rawnum
);
513 /* Return the groups that a MIPS register can be categorised into. */
516 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
517 struct reggroup
*reggroup
)
522 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
523 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
524 if (reggroup
== all_reggroup
)
526 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
527 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
528 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
529 (gdbarch), as not all architectures are multi-arch. */
530 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
531 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
532 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
534 if (reggroup
== float_reggroup
)
535 return float_p
&& pseudo
;
536 if (reggroup
== vector_reggroup
)
537 return vector_p
&& pseudo
;
538 if (reggroup
== general_reggroup
)
539 return (!vector_p
&& !float_p
) && pseudo
;
540 /* Save the pseudo registers. Need to make certain that any code
541 extracting register values from a saved register cache also uses
543 if (reggroup
== save_reggroup
)
544 return raw_p
&& pseudo
;
545 /* Restore the same pseudo register. */
546 if (reggroup
== restore_reggroup
)
547 return raw_p
&& pseudo
;
551 /* Return the groups that a MIPS register can be categorised into.
552 This version is only used if we have a target description which
553 describes real registers (and their groups). */
556 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
557 struct reggroup
*reggroup
)
559 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
560 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
563 /* Only save, restore, and display the pseudo registers. Need to
564 make certain that any code extracting register values from a
565 saved register cache also uses pseudo registers.
567 Note: saving and restoring the pseudo registers is slightly
568 strange; if we have 64 bits, we should save and restore all
569 64 bits. But this is hard and has little benefit. */
573 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
577 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
580 /* Map the symbol table registers which live in the range [1 *
581 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
582 registers. Take care of alignment and size problems. */
585 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
586 int cookednum
, gdb_byte
*buf
)
588 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
589 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
590 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
591 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
592 regcache_raw_read (regcache
, rawnum
, buf
);
593 else if (register_size (gdbarch
, rawnum
) >
594 register_size (gdbarch
, cookednum
))
596 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
597 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
598 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
600 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
603 internal_error (__FILE__
, __LINE__
, _("bad register size"));
607 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
608 struct regcache
*regcache
, int cookednum
,
611 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
612 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
613 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
614 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
615 regcache_raw_write (regcache
, rawnum
, buf
);
616 else if (register_size (gdbarch
, rawnum
) >
617 register_size (gdbarch
, cookednum
))
619 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
620 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
621 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
623 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
626 internal_error (__FILE__
, __LINE__
, _("bad register size"));
629 /* Table to translate MIPS16 register field to actual register number. */
630 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
632 /* Heuristic_proc_start may hunt through the text section for a long
633 time across a 2400 baud serial line. Allows the user to limit this
636 static unsigned int heuristic_fence_post
= 0;
638 /* Number of bytes of storage in the actual machine representation for
639 register N. NOTE: This defines the pseudo register type so need to
640 rebuild the architecture vector. */
642 static int mips64_transfers_32bit_regs_p
= 0;
645 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
646 struct cmd_list_element
*c
)
648 struct gdbarch_info info
;
649 gdbarch_info_init (&info
);
650 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
651 instead of relying on globals. Doing that would let generic code
652 handle the search for this specific architecture. */
653 if (!gdbarch_update_p (info
))
655 mips64_transfers_32bit_regs_p
= 0;
656 error (_("32-bit compatibility mode not supported"));
660 /* Convert to/from a register and the corresponding memory value. */
663 mips_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
665 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
666 && register_size (gdbarch
, regnum
) == 4
667 && (regnum
% gdbarch_num_regs (gdbarch
))
668 >= mips_regnum (gdbarch
)->fp0
669 && (regnum
% gdbarch_num_regs (gdbarch
))
670 < mips_regnum (gdbarch
)->fp0
+ 32
671 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
675 mips_register_to_value (struct frame_info
*frame
, int regnum
,
676 struct type
*type
, gdb_byte
*to
)
678 get_frame_register (frame
, regnum
+ 0, to
+ 4);
679 get_frame_register (frame
, regnum
+ 1, to
+ 0);
683 mips_value_to_register (struct frame_info
*frame
, int regnum
,
684 struct type
*type
, const gdb_byte
*from
)
686 put_frame_register (frame
, regnum
+ 0, from
+ 4);
687 put_frame_register (frame
, regnum
+ 1, from
+ 0);
690 /* Return the GDB type object for the "standard" data type of data in
694 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
696 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
697 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
698 && (regnum
% gdbarch_num_regs (gdbarch
))
699 < mips_regnum (gdbarch
)->fp0
+ 32)
701 /* The floating-point registers raw, or cooked, always match
702 mips_isa_regsize(), and also map 1:1, byte for byte. */
703 if (mips_isa_regsize (gdbarch
) == 4)
704 return builtin_type_ieee_single
;
706 return builtin_type_ieee_double
;
708 else if (regnum
< gdbarch_num_regs (gdbarch
))
710 /* The raw or ISA registers. These are all sized according to
712 if (mips_isa_regsize (gdbarch
) == 4)
713 return builtin_type_int32
;
715 return builtin_type_int64
;
719 /* The cooked or ABI registers. These are sized according to
720 the ABI (with a few complications). */
721 if (regnum
>= (gdbarch_num_regs (gdbarch
)
722 + mips_regnum (gdbarch
)->fp_control_status
)
723 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
724 /* The pseudo/cooked view of the embedded registers is always
725 32-bit. The raw view is handled below. */
726 return builtin_type_int32
;
727 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
728 /* The target, while possibly using a 64-bit register buffer,
729 is only transfering 32-bits of each integer register.
730 Reflect this in the cooked/pseudo (ABI) register value. */
731 return builtin_type_int32
;
732 else if (mips_abi_regsize (gdbarch
) == 4)
733 /* The ABI is restricted to 32-bit registers (the ISA could be
735 return builtin_type_int32
;
738 return builtin_type_int64
;
742 /* Return the GDB type for the pseudo register REGNUM, which is the
743 ABI-level view. This function is only called if there is a target
744 description which includes registers, so we know precisely the
745 types of hardware registers. */
748 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
750 const int num_regs
= gdbarch_num_regs (gdbarch
);
751 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
752 int rawnum
= regnum
% num_regs
;
753 struct type
*rawtype
;
755 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
757 /* Absent registers are still absent. */
758 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
759 if (TYPE_LENGTH (rawtype
) == 0)
762 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
763 /* Present the floating point registers however the hardware did;
764 do not try to convert between FPU layouts. */
767 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
769 /* The pseudo/cooked view of embedded registers is always
770 32-bit, even if the target transfers 64-bit values for them.
771 New targets relying on XML descriptions should only transfer
772 the necessary 32 bits, but older versions of GDB expected 64,
773 so allow the target to provide 64 bits without interfering
774 with the displayed type. */
775 return builtin_type_int32
;
778 /* Use pointer types for registers if we can. For n32 we can not,
779 since we do not have a 64-bit pointer type. */
780 if (mips_abi_regsize (gdbarch
) == TYPE_LENGTH (builtin_type_void_data_ptr
))
782 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
783 return builtin_type_void_data_ptr
;
784 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
785 return builtin_type_void_func_ptr
;
788 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
789 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
790 return builtin_type_int32
;
792 /* For all other registers, pass through the hardware type. */
796 /* Should the upper word of 64-bit addresses be zeroed? */
797 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
800 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
802 switch (mask_address_var
)
804 case AUTO_BOOLEAN_TRUE
:
806 case AUTO_BOOLEAN_FALSE
:
809 case AUTO_BOOLEAN_AUTO
:
810 return tdep
->default_mask_address_p
;
812 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
818 show_mask_address (struct ui_file
*file
, int from_tty
,
819 struct cmd_list_element
*c
, const char *value
)
821 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
823 deprecated_show_value_hack (file
, from_tty
, c
, value
);
824 switch (mask_address_var
)
826 case AUTO_BOOLEAN_TRUE
:
827 printf_filtered ("The 32 bit mips address mask is enabled\n");
829 case AUTO_BOOLEAN_FALSE
:
830 printf_filtered ("The 32 bit mips address mask is disabled\n");
832 case AUTO_BOOLEAN_AUTO
:
834 ("The 32 bit address mask is set automatically. Currently %s\n",
835 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
838 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
843 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
846 mips_pc_is_mips16 (CORE_ADDR memaddr
)
848 struct minimal_symbol
*sym
;
850 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
851 if (is_mips16_addr (memaddr
))
854 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
855 the high bit of the info field. Use this to decide if the function is
856 MIPS16 or normal MIPS. */
857 sym
= lookup_minimal_symbol_by_pc (memaddr
);
859 return msymbol_is_special (sym
);
864 /* MIPS believes that the PC has a sign extended value. Perhaps the
865 all registers should be sign extended for simplicity? */
868 mips_read_pc (struct regcache
*regcache
)
871 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
872 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
877 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
879 return frame_unwind_register_signed
880 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
884 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
886 return frame_unwind_register_signed
887 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
890 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
891 dummy frame. The frame ID's base needs to match the TOS value
892 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
895 static struct frame_id
896 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
898 return frame_id_build
899 (get_frame_register_signed (this_frame
,
900 gdbarch_num_regs (gdbarch
)
902 get_frame_pc (this_frame
));
906 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
908 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
909 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
912 /* Fetch and return instruction from the specified location. If the PC
913 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
916 mips_fetch_instruction (CORE_ADDR addr
)
918 gdb_byte buf
[MIPS_INSN32_SIZE
];
922 if (mips_pc_is_mips16 (addr
))
924 instlen
= MIPS_INSN16_SIZE
;
925 addr
= unmake_mips16_addr (addr
);
928 instlen
= MIPS_INSN32_SIZE
;
929 status
= target_read_memory (addr
, buf
, instlen
);
931 memory_error (status
, addr
);
932 return extract_unsigned_integer (buf
, instlen
);
935 /* These the fields of 32 bit mips instructions */
936 #define mips32_op(x) (x >> 26)
937 #define itype_op(x) (x >> 26)
938 #define itype_rs(x) ((x >> 21) & 0x1f)
939 #define itype_rt(x) ((x >> 16) & 0x1f)
940 #define itype_immediate(x) (x & 0xffff)
942 #define jtype_op(x) (x >> 26)
943 #define jtype_target(x) (x & 0x03ffffff)
945 #define rtype_op(x) (x >> 26)
946 #define rtype_rs(x) ((x >> 21) & 0x1f)
947 #define rtype_rt(x) ((x >> 16) & 0x1f)
948 #define rtype_rd(x) ((x >> 11) & 0x1f)
949 #define rtype_shamt(x) ((x >> 6) & 0x1f)
950 #define rtype_funct(x) (x & 0x3f)
953 mips32_relative_offset (ULONGEST inst
)
955 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
958 /* Determine where to set a single step breakpoint while considering
959 branch prediction. */
961 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
965 inst
= mips_fetch_instruction (pc
);
966 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
968 if (itype_op (inst
) >> 2 == 5)
969 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
971 op
= (itype_op (inst
) & 0x03);
986 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
987 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
989 int tf
= itype_rt (inst
) & 0x01;
990 int cnum
= itype_rt (inst
) >> 2;
992 get_frame_register_signed (frame
,
993 mips_regnum (get_frame_arch (frame
))->
995 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
997 if (((cond
>> cnum
) & 0x01) == tf
)
998 pc
+= mips32_relative_offset (inst
) + 4;
1003 pc
+= 4; /* Not a branch, next instruction is easy */
1006 { /* This gets way messy */
1008 /* Further subdivide into SPECIAL, REGIMM and other */
1009 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1011 case 0: /* SPECIAL */
1012 op
= rtype_funct (inst
);
1017 /* Set PC to that address */
1018 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1024 break; /* end SPECIAL */
1025 case 1: /* REGIMM */
1027 op
= itype_rt (inst
); /* branch condition */
1032 case 16: /* BLTZAL */
1033 case 18: /* BLTZALL */
1035 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1036 pc
+= mips32_relative_offset (inst
) + 4;
1038 pc
+= 8; /* after the delay slot */
1042 case 17: /* BGEZAL */
1043 case 19: /* BGEZALL */
1044 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1045 pc
+= mips32_relative_offset (inst
) + 4;
1047 pc
+= 8; /* after the delay slot */
1049 /* All of the other instructions in the REGIMM category */
1054 break; /* end REGIMM */
1059 reg
= jtype_target (inst
) << 2;
1060 /* Upper four bits get never changed... */
1061 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1064 /* FIXME case JALX : */
1067 reg
= jtype_target (inst
) << 2;
1068 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1069 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1071 break; /* The new PC will be alternate mode */
1072 case 4: /* BEQ, BEQL */
1074 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1075 get_frame_register_signed (frame
, itype_rt (inst
)))
1076 pc
+= mips32_relative_offset (inst
) + 4;
1080 case 5: /* BNE, BNEL */
1082 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1083 get_frame_register_signed (frame
, itype_rt (inst
)))
1084 pc
+= mips32_relative_offset (inst
) + 4;
1088 case 6: /* BLEZ, BLEZL */
1089 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1090 pc
+= mips32_relative_offset (inst
) + 4;
1096 greater_branch
: /* BGTZ, BGTZL */
1097 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1098 pc
+= mips32_relative_offset (inst
) + 4;
1105 } /* mips32_next_pc */
1107 /* Decoding the next place to set a breakpoint is irregular for the
1108 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1109 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1110 We dont want to set a single step instruction on the extend instruction
1114 /* Lots of mips16 instruction formats */
1115 /* Predicting jumps requires itype,ritype,i8type
1116 and their extensions extItype,extritype,extI8type
1118 enum mips16_inst_fmts
1120 itype
, /* 0 immediate 5,10 */
1121 ritype
, /* 1 5,3,8 */
1122 rrtype
, /* 2 5,3,3,5 */
1123 rritype
, /* 3 5,3,3,5 */
1124 rrrtype
, /* 4 5,3,3,3,2 */
1125 rriatype
, /* 5 5,3,3,1,4 */
1126 shifttype
, /* 6 5,3,3,3,2 */
1127 i8type
, /* 7 5,3,8 */
1128 i8movtype
, /* 8 5,3,3,5 */
1129 i8mov32rtype
, /* 9 5,3,5,3 */
1130 i64type
, /* 10 5,3,8 */
1131 ri64type
, /* 11 5,3,3,5 */
1132 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1133 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1134 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1135 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1136 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1137 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1138 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1139 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1140 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1141 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1143 /* I am heaping all the fields of the formats into one structure and
1144 then, only the fields which are involved in instruction extension */
1148 unsigned int regx
; /* Function in i8 type */
1153 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1154 for the bits which make up the immediate extension. */
1157 extended_offset (unsigned int extension
)
1160 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1162 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1164 value
|= extension
& 0x01f; /* extract 4:0 */
1168 /* Only call this function if you know that this is an extendable
1169 instruction. It won't malfunction, but why make excess remote memory
1170 references? If the immediate operands get sign extended or something,
1171 do it after the extension is performed. */
1172 /* FIXME: Every one of these cases needs to worry about sign extension
1173 when the offset is to be used in relative addressing. */
1176 fetch_mips_16 (CORE_ADDR pc
)
1179 pc
&= 0xfffffffe; /* clear the low order bit */
1180 target_read_memory (pc
, buf
, 2);
1181 return extract_unsigned_integer (buf
, 2);
1185 unpack_mips16 (CORE_ADDR pc
,
1186 unsigned int extension
,
1188 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1193 switch (insn_format
)
1200 value
= extended_offset (extension
);
1201 value
= value
<< 11; /* rom for the original value */
1202 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1206 value
= inst
& 0x7ff;
1207 /* FIXME : Consider sign extension */
1216 { /* A register identifier and an offset */
1217 /* Most of the fields are the same as I type but the
1218 immediate value is of a different length */
1222 value
= extended_offset (extension
);
1223 value
= value
<< 8; /* from the original instruction */
1224 value
|= inst
& 0xff; /* eleven bits from instruction */
1225 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1226 if (value
& 0x4000) /* test the sign bit , bit 26 */
1228 value
&= ~0x3fff; /* remove the sign bit */
1234 value
= inst
& 0xff; /* 8 bits */
1235 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1236 /* FIXME: Do sign extension , this format needs it */
1237 if (value
& 0x80) /* THIS CONFUSES ME */
1239 value
&= 0xef; /* remove the sign bit */
1249 unsigned long value
;
1250 unsigned int nexthalf
;
1251 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1252 value
= value
<< 16;
1253 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1261 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1263 upk
->offset
= offset
;
1270 add_offset_16 (CORE_ADDR pc
, int offset
)
1272 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1276 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1277 unsigned int extension
, unsigned int insn
)
1279 int op
= (insn
>> 11);
1282 case 2: /* Branch */
1285 struct upk_mips16 upk
;
1286 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1287 offset
= upk
.offset
;
1293 pc
+= (offset
<< 1) + 2;
1296 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1298 struct upk_mips16 upk
;
1299 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1300 pc
= add_offset_16 (pc
, upk
.offset
);
1301 if ((insn
>> 10) & 0x01) /* Exchange mode */
1302 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1309 struct upk_mips16 upk
;
1311 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1312 reg
= get_frame_register_signed (frame
, upk
.regx
);
1314 pc
+= (upk
.offset
<< 1) + 2;
1321 struct upk_mips16 upk
;
1323 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1324 reg
= get_frame_register_signed (frame
, upk
.regx
);
1326 pc
+= (upk
.offset
<< 1) + 2;
1331 case 12: /* I8 Formats btez btnez */
1333 struct upk_mips16 upk
;
1335 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1336 /* upk.regx contains the opcode */
1337 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1338 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1339 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1340 /* pc = add_offset_16(pc,upk.offset) ; */
1341 pc
+= (upk
.offset
<< 1) + 2;
1346 case 29: /* RR Formats JR, JALR, JALR-RA */
1348 struct upk_mips16 upk
;
1349 /* upk.fmt = rrtype; */
1354 upk
.regx
= (insn
>> 8) & 0x07;
1355 upk
.regy
= (insn
>> 5) & 0x07;
1363 break; /* Function return instruction */
1369 break; /* BOGUS Guess */
1371 pc
= get_frame_register_signed (frame
, reg
);
1378 /* This is an instruction extension. Fetch the real instruction
1379 (which follows the extension) and decode things based on
1383 pc
= extended_mips16_next_pc (frame
, pc
, insn
, fetch_mips_16 (pc
));
1396 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1398 unsigned int insn
= fetch_mips_16 (pc
);
1399 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1402 /* The mips_next_pc function supports single_step when the remote
1403 target monitor or stub is not developed enough to do a single_step.
1404 It works by decoding the current instruction and predicting where a
1405 branch will go. This isnt hard because all the data is available.
1406 The MIPS32 and MIPS16 variants are quite different. */
1408 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1410 if (is_mips16_addr (pc
))
1411 return mips16_next_pc (frame
, pc
);
1413 return mips32_next_pc (frame
, pc
);
1416 struct mips_frame_cache
1419 struct trad_frame_saved_reg
*saved_regs
;
1422 /* Set a register's saved stack address in temp_saved_regs. If an
1423 address has already been set for this register, do nothing; this
1424 way we will only recognize the first save of a given register in a
1427 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1428 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1429 Strictly speaking, only the second range is used as it is only second
1430 range (the ABI instead of ISA registers) that comes into play when finding
1431 saved registers in a frame. */
1434 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1437 if (this_cache
!= NULL
1438 && this_cache
->saved_regs
[regnum
].addr
== -1)
1440 this_cache
->saved_regs
[regnum
1441 + 0 * gdbarch_num_regs (current_gdbarch
)].addr
1443 this_cache
->saved_regs
[regnum
1444 + 1 * gdbarch_num_regs (current_gdbarch
)].addr
1450 /* Fetch the immediate value from a MIPS16 instruction.
1451 If the previous instruction was an EXTEND, use it to extend
1452 the upper bits of the immediate value. This is a helper function
1453 for mips16_scan_prologue. */
1456 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1457 unsigned short inst
, /* current instruction */
1458 int nbits
, /* number of bits in imm field */
1459 int scale
, /* scale factor to be applied to imm */
1460 int is_signed
) /* is the imm field signed? */
1464 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1466 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1467 if (offset
& 0x8000) /* check for negative extend */
1468 offset
= 0 - (0x10000 - (offset
& 0xffff));
1469 return offset
| (inst
& 0x1f);
1473 int max_imm
= 1 << nbits
;
1474 int mask
= max_imm
- 1;
1475 int sign_bit
= max_imm
>> 1;
1477 offset
= inst
& mask
;
1478 if (is_signed
&& (offset
& sign_bit
))
1479 offset
= 0 - (max_imm
- offset
);
1480 return offset
* scale
;
1485 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1486 the associated FRAME_CACHE if not null.
1487 Return the address of the first instruction past the prologue. */
1490 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1491 struct frame_info
*this_frame
,
1492 struct mips_frame_cache
*this_cache
)
1495 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1497 long frame_offset
= 0; /* Size of stack frame. */
1498 long frame_adjust
= 0; /* Offset of FP from SP. */
1499 int frame_reg
= MIPS_SP_REGNUM
;
1500 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1501 unsigned inst
= 0; /* current instruction */
1502 unsigned entry_inst
= 0; /* the entry instruction */
1503 unsigned save_inst
= 0; /* the save instruction */
1506 int extend_bytes
= 0;
1507 int prev_extend_bytes
;
1508 CORE_ADDR end_prologue_addr
= 0;
1509 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1511 /* Can be called when there's no process, and hence when there's no
1513 if (this_frame
!= NULL
)
1514 sp
= get_frame_register_signed (this_frame
,
1515 gdbarch_num_regs (gdbarch
)
1520 if (limit_pc
> start_pc
+ 200)
1521 limit_pc
= start_pc
+ 200;
1523 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1525 /* Save the previous instruction. If it's an EXTEND, we'll extract
1526 the immediate offset extension from it in mips16_get_imm. */
1529 /* Fetch and decode the instruction. */
1530 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1532 /* Normally we ignore extend instructions. However, if it is
1533 not followed by a valid prologue instruction, then this
1534 instruction is not part of the prologue either. We must
1535 remember in this case to adjust the end_prologue_addr back
1537 if ((inst
& 0xf800) == 0xf000) /* extend */
1539 extend_bytes
= MIPS_INSN16_SIZE
;
1543 prev_extend_bytes
= extend_bytes
;
1546 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1547 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1549 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1550 if (offset
< 0) /* negative stack adjustment? */
1551 frame_offset
-= offset
;
1553 /* Exit loop if a positive stack adjustment is found, which
1554 usually means that the stack cleanup code in the function
1555 epilogue is reached. */
1558 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1560 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1561 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1562 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1564 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1566 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1567 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1568 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1570 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1572 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1573 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1575 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1577 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1578 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1580 else if (inst
== 0x673d) /* move $s1, $sp */
1585 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1587 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1588 frame_addr
= sp
+ offset
;
1590 frame_adjust
= offset
;
1592 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1594 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1595 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1596 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1598 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1600 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1601 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1602 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1604 else if ((inst
& 0xf81f) == 0xe809
1605 && (inst
& 0x700) != 0x700) /* entry */
1606 entry_inst
= inst
; /* save for later processing */
1607 else if ((inst
& 0xff80) == 0x6480) /* save */
1609 save_inst
= inst
; /* save for later processing */
1610 if (prev_extend_bytes
) /* extend */
1611 save_inst
|= prev_inst
<< 16;
1613 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1614 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1615 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1617 /* This instruction is part of the prologue, but we don't
1618 need to do anything special to handle it. */
1622 /* This instruction is not an instruction typically found
1623 in a prologue, so we must have reached the end of the
1625 if (end_prologue_addr
== 0)
1626 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1630 /* The entry instruction is typically the first instruction in a function,
1631 and it stores registers at offsets relative to the value of the old SP
1632 (before the prologue). But the value of the sp parameter to this
1633 function is the new SP (after the prologue has been executed). So we
1634 can't calculate those offsets until we've seen the entire prologue,
1635 and can calculate what the old SP must have been. */
1636 if (entry_inst
!= 0)
1638 int areg_count
= (entry_inst
>> 8) & 7;
1639 int sreg_count
= (entry_inst
>> 6) & 3;
1641 /* The entry instruction always subtracts 32 from the SP. */
1644 /* Now we can calculate what the SP must have been at the
1645 start of the function prologue. */
1648 /* Check if a0-a3 were saved in the caller's argument save area. */
1649 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1651 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1652 offset
+= mips_abi_regsize (gdbarch
);
1655 /* Check if the ra register was pushed on the stack. */
1657 if (entry_inst
& 0x20)
1659 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1660 offset
-= mips_abi_regsize (gdbarch
);
1663 /* Check if the s0 and s1 registers were pushed on the stack. */
1664 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1666 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1667 offset
-= mips_abi_regsize (gdbarch
);
1671 /* The SAVE instruction is similar to ENTRY, except that defined by the
1672 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1673 size of the frame is specified as an immediate field of instruction
1674 and an extended variation exists which lets additional registers and
1675 frame space to be specified. The instruction always treats registers
1676 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1677 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1679 static int args_table
[16] = {
1680 0, 0, 0, 0, 1, 1, 1, 1,
1681 2, 2, 2, 0, 3, 3, 4, -1,
1683 static int astatic_table
[16] = {
1684 0, 1, 2, 3, 0, 1, 2, 3,
1685 0, 1, 2, 4, 0, 1, 0, -1,
1687 int aregs
= (save_inst
>> 16) & 0xf;
1688 int xsregs
= (save_inst
>> 24) & 0x7;
1689 int args
= args_table
[aregs
];
1690 int astatic
= astatic_table
[aregs
];
1695 warning (_("Invalid number of argument registers encoded in SAVE."));
1700 warning (_("Invalid number of static registers encoded in SAVE."));
1704 /* For standard SAVE the frame size of 0 means 128. */
1705 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1706 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1709 frame_offset
+= frame_size
;
1711 /* Now we can calculate what the SP must have been at the
1712 start of the function prologue. */
1715 /* Check if A0-A3 were saved in the caller's argument save area. */
1716 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1718 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1719 offset
+= mips_abi_regsize (gdbarch
);
1724 /* Check if the RA register was pushed on the stack. */
1725 if (save_inst
& 0x40)
1727 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1728 offset
-= mips_abi_regsize (gdbarch
);
1731 /* Check if the S8 register was pushed on the stack. */
1734 set_reg_offset (this_cache
, 30, sp
+ offset
);
1735 offset
-= mips_abi_regsize (gdbarch
);
1738 /* Check if S2-S7 were pushed on the stack. */
1739 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1741 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1742 offset
-= mips_abi_regsize (gdbarch
);
1745 /* Check if the S1 register was pushed on the stack. */
1746 if (save_inst
& 0x10)
1748 set_reg_offset (this_cache
, 17, sp
+ offset
);
1749 offset
-= mips_abi_regsize (gdbarch
);
1751 /* Check if the S0 register was pushed on the stack. */
1752 if (save_inst
& 0x20)
1754 set_reg_offset (this_cache
, 16, sp
+ offset
);
1755 offset
-= mips_abi_regsize (gdbarch
);
1758 /* Check if A0-A3 were pushed on the stack. */
1759 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1761 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1762 offset
-= mips_abi_regsize (gdbarch
);
1766 if (this_cache
!= NULL
)
1769 (get_frame_register_signed (this_frame
,
1770 gdbarch_num_regs (gdbarch
) + frame_reg
)
1771 + frame_offset
- frame_adjust
);
1772 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1773 be able to get rid of the assignment below, evetually. But it's
1774 still needed for now. */
1775 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1776 + mips_regnum (gdbarch
)->pc
]
1777 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1780 /* If we didn't reach the end of the prologue when scanning the function
1781 instructions, then set end_prologue_addr to the address of the
1782 instruction immediately after the last one we scanned. */
1783 if (end_prologue_addr
== 0)
1784 end_prologue_addr
= cur_pc
;
1786 return end_prologue_addr
;
1789 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1790 Procedures that use the 32-bit instruction set are handled by the
1791 mips_insn32 unwinder. */
1793 static struct mips_frame_cache
*
1794 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1796 struct mips_frame_cache
*cache
;
1798 if ((*this_cache
) != NULL
)
1799 return (*this_cache
);
1800 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1801 (*this_cache
) = cache
;
1802 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1804 /* Analyze the function prologue. */
1806 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1807 CORE_ADDR start_addr
;
1809 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1810 if (start_addr
== 0)
1811 start_addr
= heuristic_proc_start (pc
);
1812 /* We can't analyze the prologue if we couldn't find the begining
1814 if (start_addr
== 0)
1817 mips16_scan_prologue (start_addr
, pc
, this_frame
, *this_cache
);
1820 /* gdbarch_sp_regnum contains the value and not the address. */
1821 trad_frame_set_value (cache
->saved_regs
,
1822 gdbarch_num_regs (get_frame_arch (this_frame
))
1826 return (*this_cache
);
1830 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1831 struct frame_id
*this_id
)
1833 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1835 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
1838 static struct value
*
1839 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
1840 void **this_cache
, int regnum
)
1842 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1844 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1848 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
1849 struct frame_info
*this_frame
, void **this_cache
)
1851 CORE_ADDR pc
= get_frame_pc (this_frame
);
1852 if (mips_pc_is_mips16 (pc
))
1857 static const struct frame_unwind mips_insn16_frame_unwind
=
1860 mips_insn16_frame_this_id
,
1861 mips_insn16_frame_prev_register
,
1863 mips_insn16_frame_sniffer
1867 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
1870 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1875 static const struct frame_base mips_insn16_frame_base
=
1877 &mips_insn16_frame_unwind
,
1878 mips_insn16_frame_base_address
,
1879 mips_insn16_frame_base_address
,
1880 mips_insn16_frame_base_address
1883 static const struct frame_base
*
1884 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
1886 CORE_ADDR pc
= get_frame_pc (this_frame
);
1887 if (mips_pc_is_mips16 (pc
))
1888 return &mips_insn16_frame_base
;
1893 /* Mark all the registers as unset in the saved_regs array
1894 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1897 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1899 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1903 const int num_regs
= gdbarch_num_regs (current_gdbarch
);
1906 for (i
= 0; i
< num_regs
; i
++)
1908 this_cache
->saved_regs
[i
].addr
= -1;
1913 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1914 the associated FRAME_CACHE if not null.
1915 Return the address of the first instruction past the prologue. */
1918 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1919 struct frame_info
*this_frame
,
1920 struct mips_frame_cache
*this_cache
)
1923 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1926 int frame_reg
= MIPS_SP_REGNUM
;
1928 CORE_ADDR end_prologue_addr
= 0;
1929 int seen_sp_adjust
= 0;
1930 int load_immediate_bytes
= 0;
1931 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1932 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
1934 /* Can be called when there's no process, and hence when there's no
1936 if (this_frame
!= NULL
)
1937 sp
= get_frame_register_signed (this_frame
,
1938 gdbarch_num_regs (gdbarch
)
1943 if (limit_pc
> start_pc
+ 200)
1944 limit_pc
= start_pc
+ 200;
1949 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1951 unsigned long inst
, high_word
, low_word
;
1954 /* Fetch the instruction. */
1955 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1957 /* Save some code by pre-extracting some useful fields. */
1958 high_word
= (inst
>> 16) & 0xffff;
1959 low_word
= inst
& 0xffff;
1960 reg
= high_word
& 0x1f;
1962 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1963 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1964 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1966 if (low_word
& 0x8000) /* negative stack adjustment? */
1967 frame_offset
+= 0x10000 - low_word
;
1969 /* Exit loop if a positive stack adjustment is found, which
1970 usually means that the stack cleanup code in the function
1971 epilogue is reached. */
1975 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1976 && !regsize_is_64_bits
)
1978 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1980 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1981 && regsize_is_64_bits
)
1983 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1984 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1986 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1988 /* Old gcc frame, r30 is virtual frame pointer. */
1989 if ((long) low_word
!= frame_offset
)
1990 frame_addr
= sp
+ low_word
;
1991 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1993 unsigned alloca_adjust
;
1996 frame_addr
= get_frame_register_signed
1997 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
1999 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2000 if (alloca_adjust
> 0)
2002 /* FP > SP + frame_size. This may be because of
2003 an alloca or somethings similar. Fix sp to
2004 "pre-alloca" value, and try again. */
2005 sp
+= alloca_adjust
;
2006 /* Need to reset the status of all registers. Otherwise,
2007 we will hit a guard that prevents the new address
2008 for each register to be recomputed during the second
2010 reset_saved_regs (this_cache
);
2015 /* move $30,$sp. With different versions of gas this will be either
2016 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2017 Accept any one of these. */
2018 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2020 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2021 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2023 unsigned alloca_adjust
;
2026 frame_addr
= get_frame_register_signed
2027 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2029 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2030 if (alloca_adjust
> 0)
2032 /* FP > SP + frame_size. This may be because of
2033 an alloca or somethings similar. Fix sp to
2034 "pre-alloca" value, and try again. */
2036 /* Need to reset the status of all registers. Otherwise,
2037 we will hit a guard that prevents the new address
2038 for each register to be recomputed during the second
2040 reset_saved_regs (this_cache
);
2045 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2046 && !regsize_is_64_bits
)
2048 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
2050 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2051 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2052 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2053 || high_word
== 0x3c1c /* lui $gp,n */
2054 || high_word
== 0x279c /* addiu $gp,$gp,n */
2055 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2056 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2059 /* These instructions are part of the prologue, but we don't
2060 need to do anything special to handle them. */
2062 /* The instructions below load $at or $t0 with an immediate
2063 value in preparation for a stack adjustment via
2064 subu $sp,$sp,[$at,$t0]. These instructions could also
2065 initialize a local variable, so we accept them only before
2066 a stack adjustment instruction was seen. */
2067 else if (!seen_sp_adjust
2068 && (high_word
== 0x3c01 /* lui $at,n */
2069 || high_word
== 0x3c08 /* lui $t0,n */
2070 || high_word
== 0x3421 /* ori $at,$at,n */
2071 || high_word
== 0x3508 /* ori $t0,$t0,n */
2072 || high_word
== 0x3401 /* ori $at,$zero,n */
2073 || high_word
== 0x3408 /* ori $t0,$zero,n */
2076 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2080 /* This instruction is not an instruction typically found
2081 in a prologue, so we must have reached the end of the
2083 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2084 loop now? Why would we need to continue scanning the function
2086 if (end_prologue_addr
== 0)
2087 end_prologue_addr
= cur_pc
;
2091 if (this_cache
!= NULL
)
2094 (get_frame_register_signed (this_frame
,
2095 gdbarch_num_regs (gdbarch
) + frame_reg
)
2097 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2098 this assignment below, eventually. But it's still needed
2100 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2101 + mips_regnum (gdbarch
)->pc
]
2102 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2106 /* If we didn't reach the end of the prologue when scanning the function
2107 instructions, then set end_prologue_addr to the address of the
2108 instruction immediately after the last one we scanned. */
2109 /* brobecker/2004-10-10: I don't think this would ever happen, but
2110 we may as well be careful and do our best if we have a null
2111 end_prologue_addr. */
2112 if (end_prologue_addr
== 0)
2113 end_prologue_addr
= cur_pc
;
2115 /* In a frameless function, we might have incorrectly
2116 skipped some load immediate instructions. Undo the skipping
2117 if the load immediate was not followed by a stack adjustment. */
2118 if (load_immediate_bytes
&& !seen_sp_adjust
)
2119 end_prologue_addr
-= load_immediate_bytes
;
2121 return end_prologue_addr
;
2124 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2125 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2126 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2129 static struct mips_frame_cache
*
2130 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2132 struct mips_frame_cache
*cache
;
2134 if ((*this_cache
) != NULL
)
2135 return (*this_cache
);
2137 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2138 (*this_cache
) = cache
;
2139 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2141 /* Analyze the function prologue. */
2143 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2144 CORE_ADDR start_addr
;
2146 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2147 if (start_addr
== 0)
2148 start_addr
= heuristic_proc_start (pc
);
2149 /* We can't analyze the prologue if we couldn't find the begining
2151 if (start_addr
== 0)
2154 mips32_scan_prologue (start_addr
, pc
, this_frame
, *this_cache
);
2157 /* gdbarch_sp_regnum contains the value and not the address. */
2158 trad_frame_set_value (cache
->saved_regs
,
2159 gdbarch_num_regs (get_frame_arch (this_frame
))
2163 return (*this_cache
);
2167 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2168 struct frame_id
*this_id
)
2170 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2172 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2175 static struct value
*
2176 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2177 void **this_cache
, int regnum
)
2179 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2181 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2185 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2186 struct frame_info
*this_frame
, void **this_cache
)
2188 CORE_ADDR pc
= get_frame_pc (this_frame
);
2189 if (! mips_pc_is_mips16 (pc
))
2194 static const struct frame_unwind mips_insn32_frame_unwind
=
2197 mips_insn32_frame_this_id
,
2198 mips_insn32_frame_prev_register
,
2200 mips_insn32_frame_sniffer
2204 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2207 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2212 static const struct frame_base mips_insn32_frame_base
=
2214 &mips_insn32_frame_unwind
,
2215 mips_insn32_frame_base_address
,
2216 mips_insn32_frame_base_address
,
2217 mips_insn32_frame_base_address
2220 static const struct frame_base
*
2221 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2223 CORE_ADDR pc
= get_frame_pc (this_frame
);
2224 if (! mips_pc_is_mips16 (pc
))
2225 return &mips_insn32_frame_base
;
2230 static struct trad_frame_cache
*
2231 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2234 CORE_ADDR start_addr
;
2235 CORE_ADDR stack_addr
;
2236 struct trad_frame_cache
*this_trad_cache
;
2237 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2238 int num_regs
= gdbarch_num_regs (gdbarch
);
2240 if ((*this_cache
) != NULL
)
2241 return (*this_cache
);
2242 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2243 (*this_cache
) = this_trad_cache
;
2245 /* The return address is in the link register. */
2246 trad_frame_set_reg_realreg (this_trad_cache
,
2247 gdbarch_pc_regnum (gdbarch
),
2248 num_regs
+ MIPS_RA_REGNUM
);
2250 /* Frame ID, since it's a frameless / stackless function, no stack
2251 space is allocated and SP on entry is the current SP. */
2252 pc
= get_frame_pc (this_frame
);
2253 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2254 stack_addr
= get_frame_register_signed (this_frame
,
2255 num_regs
+ MIPS_SP_REGNUM
);
2256 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2258 /* Assume that the frame's base is the same as the
2260 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2262 return this_trad_cache
;
2266 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2267 struct frame_id
*this_id
)
2269 struct trad_frame_cache
*this_trad_cache
2270 = mips_stub_frame_cache (this_frame
, this_cache
);
2271 trad_frame_get_id (this_trad_cache
, this_id
);
2274 static struct value
*
2275 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2276 void **this_cache
, int regnum
)
2278 struct trad_frame_cache
*this_trad_cache
2279 = mips_stub_frame_cache (this_frame
, this_cache
);
2280 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2284 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2285 struct frame_info
*this_frame
, void **this_cache
)
2288 struct obj_section
*s
;
2289 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2291 /* Use the stub unwinder for unreadable code. */
2292 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2295 if (in_plt_section (pc
, NULL
))
2298 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2299 s
= find_pc_section (pc
);
2302 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2303 ".MIPS.stubs") == 0)
2309 static const struct frame_unwind mips_stub_frame_unwind
=
2312 mips_stub_frame_this_id
,
2313 mips_stub_frame_prev_register
,
2315 mips_stub_frame_sniffer
2319 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2322 struct trad_frame_cache
*this_trad_cache
2323 = mips_stub_frame_cache (this_frame
, this_cache
);
2324 return trad_frame_get_this_base (this_trad_cache
);
2327 static const struct frame_base mips_stub_frame_base
=
2329 &mips_stub_frame_unwind
,
2330 mips_stub_frame_base_address
,
2331 mips_stub_frame_base_address
,
2332 mips_stub_frame_base_address
2335 static const struct frame_base
*
2336 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2338 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2339 return &mips_stub_frame_base
;
2344 /* mips_addr_bits_remove - remove useless address bits */
2347 mips_addr_bits_remove (CORE_ADDR addr
)
2349 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2350 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2351 /* This hack is a work-around for existing boards using PMON, the
2352 simulator, and any other 64-bit targets that doesn't have true
2353 64-bit addressing. On these targets, the upper 32 bits of
2354 addresses are ignored by the hardware. Thus, the PC or SP are
2355 likely to have been sign extended to all 1s by instruction
2356 sequences that load 32-bit addresses. For example, a typical
2357 piece of code that loads an address is this:
2359 lui $r2, <upper 16 bits>
2360 ori $r2, <lower 16 bits>
2362 But the lui sign-extends the value such that the upper 32 bits
2363 may be all 1s. The workaround is simply to mask off these
2364 bits. In the future, gcc may be changed to support true 64-bit
2365 addressing, and this masking will have to be disabled. */
2366 return addr
&= 0xffffffffUL
;
2371 /* Instructions used during single-stepping of atomic sequences. */
2372 #define LL_OPCODE 0x30
2373 #define LLD_OPCODE 0x34
2374 #define SC_OPCODE 0x38
2375 #define SCD_OPCODE 0x3c
2377 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2378 instruction and ending with a SC/SCD instruction. If such a sequence
2379 is found, attempt to step through it. A breakpoint is placed at the end of
2383 deal_with_atomic_sequence (CORE_ADDR pc
)
2385 CORE_ADDR breaks
[2] = {-1, -1};
2387 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2391 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2392 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2397 insn
= mips_fetch_instruction (loc
);
2398 /* Assume all atomic sequences start with a ll/lld instruction. */
2399 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2402 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2404 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2407 loc
+= MIPS_INSN32_SIZE
;
2408 insn
= mips_fetch_instruction (loc
);
2410 /* Assume that there is at most one branch in the atomic
2411 sequence. If a branch is found, put a breakpoint in its
2412 destination address. */
2413 switch (itype_op (insn
))
2415 case 0: /* SPECIAL */
2416 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2417 return 0; /* fallback to the standard single-step code. */
2419 case 1: /* REGIMM */
2420 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2424 return 0; /* fallback to the standard single-step code. */
2431 case 22: /* BLEZL */
2432 case 23: /* BGTTL */
2438 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2443 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2444 if (last_breakpoint
>= 1)
2445 return 0; /* More than one branch found, fallback to the
2446 standard single-step code. */
2447 breaks
[1] = branch_bp
;
2451 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2455 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2456 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2459 loc
+= MIPS_INSN32_SIZE
;
2461 /* Insert a breakpoint right after the end of the atomic sequence. */
2464 /* Check for duplicated breakpoints. Check also for a breakpoint
2465 placed (branch instruction's destination) in the atomic sequence */
2466 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2467 last_breakpoint
= 0;
2469 /* Effectively inserts the breakpoints. */
2470 for (index
= 0; index
<= last_breakpoint
; index
++)
2471 insert_single_step_breakpoint (breaks
[index
]);
2476 /* mips_software_single_step() is called just before we want to resume
2477 the inferior, if we want to single-step it but there is no hardware
2478 or kernel single-step support (MIPS on GNU/Linux for example). We find
2479 the target of the coming instruction and breakpoint it. */
2482 mips_software_single_step (struct frame_info
*frame
)
2484 CORE_ADDR pc
, next_pc
;
2486 pc
= get_frame_pc (frame
);
2487 if (deal_with_atomic_sequence (pc
))
2490 next_pc
= mips_next_pc (frame
, pc
);
2492 insert_single_step_breakpoint (next_pc
);
2496 /* Test whether the PC points to the return instruction at the
2497 end of a function. */
2500 mips_about_to_return (CORE_ADDR pc
)
2502 if (mips_pc_is_mips16 (pc
))
2503 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2504 generates a "jr $ra"; other times it generates code to load
2505 the return address from the stack to an accessible register (such
2506 as $a3), then a "jr" using that register. This second case
2507 is almost impossible to distinguish from an indirect jump
2508 used for switch statements, so we don't even try. */
2509 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2511 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2515 /* This fencepost looks highly suspicious to me. Removing it also
2516 seems suspicious as it could affect remote debugging across serial
2520 heuristic_proc_start (CORE_ADDR pc
)
2527 pc
= gdbarch_addr_bits_remove (current_gdbarch
, pc
);
2529 fence
= start_pc
- heuristic_fence_post
;
2533 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2534 fence
= VM_MIN_ADDRESS
;
2536 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2538 /* search back for previous return */
2539 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2540 if (start_pc
< fence
)
2542 /* It's not clear to me why we reach this point when
2543 stop_soon, but with this test, at least we
2544 don't print out warnings for every child forked (eg, on
2545 decstation). 22apr93 rich@cygnus.com. */
2546 if (stop_soon
== NO_STOP_QUIETLY
)
2548 static int blurb_printed
= 0;
2550 warning (_("GDB can't find the start of the function at 0x%s."),
2555 /* This actually happens frequently in embedded
2556 development, when you first connect to a board
2557 and your stack pointer and pc are nowhere in
2558 particular. This message needs to give people
2559 in that situation enough information to
2560 determine that it's no big deal. */
2561 printf_filtered ("\n\
2562 GDB is unable to find the start of the function at 0x%s\n\
2563 and thus can't determine the size of that function's stack frame.\n\
2564 This means that GDB may be unable to access that stack frame, or\n\
2565 the frames below it.\n\
2566 This problem is most likely caused by an invalid program counter or\n\
2568 However, if you think GDB should simply search farther back\n\
2569 from 0x%s for code which looks like the beginning of a\n\
2570 function, you can increase the range of the search using the `set\n\
2571 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2578 else if (mips_pc_is_mips16 (start_pc
))
2580 unsigned short inst
;
2582 /* On MIPS16, any one of the following is likely to be the
2583 start of a function:
2589 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2590 inst
= mips_fetch_instruction (start_pc
);
2591 if ((inst
& 0xff80) == 0x6480) /* save */
2593 if (start_pc
- instlen
>= fence
)
2595 inst
= mips_fetch_instruction (start_pc
- instlen
);
2596 if ((inst
& 0xf800) == 0xf000) /* extend */
2597 start_pc
-= instlen
;
2601 else if (((inst
& 0xf81f) == 0xe809
2602 && (inst
& 0x700) != 0x700) /* entry */
2603 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2604 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2605 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2607 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2608 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2613 else if (mips_about_to_return (start_pc
))
2615 /* Skip return and its delay slot. */
2616 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2623 struct mips_objfile_private
2629 /* According to the current ABI, should the type be passed in a
2630 floating-point register (assuming that there is space)? When there
2631 is no FPU, FP are not even considered as possible candidates for
2632 FP registers and, consequently this returns false - forces FP
2633 arguments into integer registers. */
2636 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2638 return ((typecode
== TYPE_CODE_FLT
2640 && (typecode
== TYPE_CODE_STRUCT
2641 || typecode
== TYPE_CODE_UNION
)
2642 && TYPE_NFIELDS (arg_type
) == 1
2643 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2645 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2648 /* On o32, argument passing in GPRs depends on the alignment of the type being
2649 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2652 mips_type_needs_double_align (struct type
*type
)
2654 enum type_code typecode
= TYPE_CODE (type
);
2656 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2658 else if (typecode
== TYPE_CODE_STRUCT
)
2660 if (TYPE_NFIELDS (type
) < 1)
2662 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2664 else if (typecode
== TYPE_CODE_UNION
)
2668 n
= TYPE_NFIELDS (type
);
2669 for (i
= 0; i
< n
; i
++)
2670 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2677 /* Adjust the address downward (direction of stack growth) so that it
2678 is correctly aligned for a new stack frame. */
2680 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2682 return align_down (addr
, 16);
2686 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2687 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2688 int nargs
, struct value
**args
, CORE_ADDR sp
,
2689 int struct_return
, CORE_ADDR struct_addr
)
2695 int stack_offset
= 0;
2696 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2697 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2698 int regsize
= mips_abi_regsize (gdbarch
);
2700 /* For shared libraries, "t9" needs to point at the function
2702 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2704 /* Set the return address register to point to the entry point of
2705 the program, where a breakpoint lies in wait. */
2706 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2708 /* First ensure that the stack and structure return address (if any)
2709 are properly aligned. The stack has to be at least 64-bit
2710 aligned even on 32-bit machines, because doubles must be 64-bit
2711 aligned. For n32 and n64, stack frames need to be 128-bit
2712 aligned, so we round to this widest known alignment. */
2714 sp
= align_down (sp
, 16);
2715 struct_addr
= align_down (struct_addr
, 16);
2717 /* Now make space on the stack for the args. We allocate more
2718 than necessary for EABI, because the first few arguments are
2719 passed in registers, but that's OK. */
2720 for (argnum
= 0; argnum
< nargs
; argnum
++)
2721 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2722 sp
-= align_up (len
, 16);
2725 fprintf_unfiltered (gdb_stdlog
,
2726 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2727 paddr_nz (sp
), (long) align_up (len
, 16));
2729 /* Initialize the integer and float register pointers. */
2730 argreg
= MIPS_A0_REGNUM
;
2731 float_argreg
= mips_fpa0_regnum (gdbarch
);
2733 /* The struct_return pointer occupies the first parameter-passing reg. */
2737 fprintf_unfiltered (gdb_stdlog
,
2738 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2739 argreg
, paddr_nz (struct_addr
));
2740 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2743 /* Now load as many as possible of the first arguments into
2744 registers, and push the rest onto the stack. Loop thru args
2745 from first to last. */
2746 for (argnum
= 0; argnum
< nargs
; argnum
++)
2748 const gdb_byte
*val
;
2749 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2750 struct value
*arg
= args
[argnum
];
2751 struct type
*arg_type
= check_typedef (value_type (arg
));
2752 int len
= TYPE_LENGTH (arg_type
);
2753 enum type_code typecode
= TYPE_CODE (arg_type
);
2756 fprintf_unfiltered (gdb_stdlog
,
2757 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2758 argnum
+ 1, len
, (int) typecode
);
2760 /* The EABI passes structures that do not fit in a register by
2763 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2765 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2766 typecode
= TYPE_CODE_PTR
;
2770 fprintf_unfiltered (gdb_stdlog
, " push");
2773 val
= value_contents (arg
);
2775 /* 32-bit ABIs always start floating point arguments in an
2776 even-numbered floating point register. Round the FP register
2777 up before the check to see if there are any FP registers
2778 left. Non MIPS_EABI targets also pass the FP in the integer
2779 registers so also round up normal registers. */
2780 if (regsize
< 8 && fp_register_arg_p (typecode
, arg_type
))
2782 if ((float_argreg
& 1))
2786 /* Floating point arguments passed in registers have to be
2787 treated specially. On 32-bit architectures, doubles
2788 are passed in register pairs; the even register gets
2789 the low word, and the odd register gets the high word.
2790 On non-EABI processors, the first two floating point arguments are
2791 also copied to general registers, because MIPS16 functions
2792 don't use float registers for arguments. This duplication of
2793 arguments in general registers can't hurt non-MIPS16 functions
2794 because those registers are normally skipped. */
2795 /* MIPS_EABI squeezes a struct that contains a single floating
2796 point value into an FP register instead of pushing it onto the
2798 if (fp_register_arg_p (typecode
, arg_type
)
2799 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2801 /* EABI32 will pass doubles in consecutive registers, even on
2802 64-bit cores. At one time, we used to check the size of
2803 `float_argreg' to determine whether or not to pass doubles
2804 in consecutive registers, but this is not sufficient for
2805 making the ABI determination. */
2806 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2808 int low_offset
= gdbarch_byte_order (gdbarch
)
2809 == BFD_ENDIAN_BIG
? 4 : 0;
2810 unsigned long regval
;
2812 /* Write the low word of the double to the even register(s). */
2813 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2815 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2816 float_argreg
, phex (regval
, 4));
2817 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2819 /* Write the high word of the double to the odd register(s). */
2820 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2822 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2823 float_argreg
, phex (regval
, 4));
2824 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2828 /* This is a floating point value that fits entirely
2829 in a single register. */
2830 /* On 32 bit ABI's the float_argreg is further adjusted
2831 above to ensure that it is even register aligned. */
2832 LONGEST regval
= extract_unsigned_integer (val
, len
);
2834 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2835 float_argreg
, phex (regval
, len
));
2836 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2841 /* Copy the argument to general registers or the stack in
2842 register-sized pieces. Large arguments are split between
2843 registers and stack. */
2844 /* Note: structs whose size is not a multiple of regsize
2845 are treated specially: Irix cc passes
2846 them in registers where gcc sometimes puts them on the
2847 stack. For maximum compatibility, we will put them in
2849 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2851 /* Note: Floating-point values that didn't fit into an FP
2852 register are only written to memory. */
2855 /* Remember if the argument was written to the stack. */
2856 int stack_used_p
= 0;
2857 int partial_len
= (len
< regsize
? len
: regsize
);
2860 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2863 /* Write this portion of the argument to the stack. */
2864 if (argreg
> MIPS_LAST_ARG_REGNUM
2866 || fp_register_arg_p (typecode
, arg_type
))
2868 /* Should shorter than int integer values be
2869 promoted to int before being stored? */
2870 int longword_offset
= 0;
2873 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2876 && (typecode
== TYPE_CODE_INT
2877 || typecode
== TYPE_CODE_PTR
2878 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2879 longword_offset
= regsize
- len
;
2880 else if ((typecode
== TYPE_CODE_STRUCT
2881 || typecode
== TYPE_CODE_UNION
)
2882 && TYPE_LENGTH (arg_type
) < regsize
)
2883 longword_offset
= regsize
- len
;
2888 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2889 paddr_nz (stack_offset
));
2890 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2891 paddr_nz (longword_offset
));
2894 addr
= sp
+ stack_offset
+ longword_offset
;
2899 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2901 for (i
= 0; i
< partial_len
; i
++)
2903 fprintf_unfiltered (gdb_stdlog
, "%02x",
2907 write_memory (addr
, val
, partial_len
);
2910 /* Note!!! This is NOT an else clause. Odd sized
2911 structs may go thru BOTH paths. Floating point
2912 arguments will not. */
2913 /* Write this portion of the argument to a general
2914 purpose register. */
2915 if (argreg
<= MIPS_LAST_ARG_REGNUM
2916 && !fp_register_arg_p (typecode
, arg_type
))
2919 extract_unsigned_integer (val
, partial_len
);
2922 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2924 phex (regval
, regsize
));
2925 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2932 /* Compute the the offset into the stack at which we
2933 will copy the next parameter.
2935 In the new EABI (and the NABI32), the stack_offset
2936 only needs to be adjusted when it has been used. */
2939 stack_offset
+= align_up (partial_len
, regsize
);
2943 fprintf_unfiltered (gdb_stdlog
, "\n");
2946 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2948 /* Return adjusted stack pointer. */
2952 /* Determine the return value convention being used. */
2954 static enum return_value_convention
2955 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2956 struct type
*type
, struct regcache
*regcache
,
2957 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2959 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2960 return RETURN_VALUE_STRUCT_CONVENTION
;
2962 memset (readbuf
, 0, TYPE_LENGTH (type
));
2963 return RETURN_VALUE_REGISTER_CONVENTION
;
2967 /* N32/N64 ABI stuff. */
2969 /* Search for a naturally aligned double at OFFSET inside a struct
2970 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
2974 mips_n32n64_fp_arg_chunk_p (struct type
*arg_type
, int offset
)
2978 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
2981 if (MIPS_FPU_TYPE
!= MIPS_FPU_DOUBLE
)
2984 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
2987 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
2990 struct type
*field_type
;
2992 /* We're only looking at normal fields. */
2993 if (TYPE_FIELD_STATIC (arg_type
, i
)
2994 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
2997 /* If we have gone past the offset, there is no double to pass. */
2998 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3002 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3004 /* If this field is entirely before the requested offset, go
3005 on to the next one. */
3006 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3009 /* If this is our special aligned double, we can stop. */
3010 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3011 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3014 /* This field starts at or before the requested offset, and
3015 overlaps it. If it is a structure, recurse inwards. */
3016 return mips_n32n64_fp_arg_chunk_p (field_type
, offset
- pos
);
3023 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3024 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3025 int nargs
, struct value
**args
, CORE_ADDR sp
,
3026 int struct_return
, CORE_ADDR struct_addr
)
3032 int stack_offset
= 0;
3033 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3034 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3036 /* For shared libraries, "t9" needs to point at the function
3038 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3040 /* Set the return address register to point to the entry point of
3041 the program, where a breakpoint lies in wait. */
3042 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3044 /* First ensure that the stack and structure return address (if any)
3045 are properly aligned. The stack has to be at least 64-bit
3046 aligned even on 32-bit machines, because doubles must be 64-bit
3047 aligned. For n32 and n64, stack frames need to be 128-bit
3048 aligned, so we round to this widest known alignment. */
3050 sp
= align_down (sp
, 16);
3051 struct_addr
= align_down (struct_addr
, 16);
3053 /* Now make space on the stack for the args. */
3054 for (argnum
= 0; argnum
< nargs
; argnum
++)
3055 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3056 sp
-= align_up (len
, 16);
3059 fprintf_unfiltered (gdb_stdlog
,
3060 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3061 paddr_nz (sp
), (long) align_up (len
, 16));
3063 /* Initialize the integer and float register pointers. */
3064 argreg
= MIPS_A0_REGNUM
;
3065 float_argreg
= mips_fpa0_regnum (gdbarch
);
3067 /* The struct_return pointer occupies the first parameter-passing reg. */
3071 fprintf_unfiltered (gdb_stdlog
,
3072 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3073 argreg
, paddr_nz (struct_addr
));
3074 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3077 /* Now load as many as possible of the first arguments into
3078 registers, and push the rest onto the stack. Loop thru args
3079 from first to last. */
3080 for (argnum
= 0; argnum
< nargs
; argnum
++)
3082 const gdb_byte
*val
;
3083 struct value
*arg
= args
[argnum
];
3084 struct type
*arg_type
= check_typedef (value_type (arg
));
3085 int len
= TYPE_LENGTH (arg_type
);
3086 enum type_code typecode
= TYPE_CODE (arg_type
);
3089 fprintf_unfiltered (gdb_stdlog
,
3090 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3091 argnum
+ 1, len
, (int) typecode
);
3093 val
= value_contents (arg
);
3095 if (fp_register_arg_p (typecode
, arg_type
)
3096 && argreg
<= MIPS_LAST_ARG_REGNUM
)
3098 /* This is a floating point value that fits entirely
3099 in a single register. */
3100 LONGEST regval
= extract_unsigned_integer (val
, len
);
3102 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3103 float_argreg
, phex (regval
, len
));
3104 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3107 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3108 argreg
, phex (regval
, len
));
3109 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3115 /* Copy the argument to general registers or the stack in
3116 register-sized pieces. Large arguments are split between
3117 registers and stack. */
3118 /* For N32/N64, structs, unions, or other composite types are
3119 treated as a sequence of doublewords, and are passed in integer
3120 or floating point registers as though they were simple scalar
3121 parameters to the extent that they fit, with any excess on the
3122 stack packed according to the normal memory layout of the
3124 The caller does not reserve space for the register arguments;
3125 the callee is responsible for reserving it if required. */
3126 /* Note: Floating-point values that didn't fit into an FP
3127 register are only written to memory. */
3130 /* Remember if the argument was written to the stack. */
3131 int stack_used_p
= 0;
3132 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3135 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3138 if (fp_register_arg_p (typecode
, arg_type
))
3139 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM
);
3141 /* Write this portion of the argument to the stack. */
3142 if (argreg
> MIPS_LAST_ARG_REGNUM
)
3144 /* Should shorter than int integer values be
3145 promoted to int before being stored? */
3146 int longword_offset
= 0;
3149 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3151 if ((typecode
== TYPE_CODE_INT
3152 || typecode
== TYPE_CODE_PTR
3153 || typecode
== TYPE_CODE_FLT
)
3155 longword_offset
= MIPS64_REGSIZE
- len
;
3160 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3161 paddr_nz (stack_offset
));
3162 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3163 paddr_nz (longword_offset
));
3166 addr
= sp
+ stack_offset
+ longword_offset
;
3171 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3173 for (i
= 0; i
< partial_len
; i
++)
3175 fprintf_unfiltered (gdb_stdlog
, "%02x",
3179 write_memory (addr
, val
, partial_len
);
3182 /* Note!!! This is NOT an else clause. Odd sized
3183 structs may go thru BOTH paths. */
3184 /* Write this portion of the argument to a general
3185 purpose register. */
3186 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3190 /* Sign extend pointers, 32-bit integers and signed
3191 16-bit and 8-bit integers; everything else is taken
3194 if ((partial_len
== 4
3195 && (typecode
== TYPE_CODE_PTR
3196 || typecode
== TYPE_CODE_INT
))
3198 && typecode
== TYPE_CODE_INT
3199 && !TYPE_UNSIGNED (arg_type
)))
3200 regval
= extract_signed_integer (val
, partial_len
);
3202 regval
= extract_unsigned_integer (val
, partial_len
);
3204 /* A non-floating-point argument being passed in a
3205 general register. If a struct or union, and if
3206 the remaining length is smaller than the register
3207 size, we have to adjust the register value on
3210 It does not seem to be necessary to do the
3211 same for integral types. */
3213 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3214 && partial_len
< MIPS64_REGSIZE
3215 && (typecode
== TYPE_CODE_STRUCT
3216 || typecode
== TYPE_CODE_UNION
))
3217 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3221 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3223 phex (regval
, MIPS64_REGSIZE
));
3224 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3226 if (mips_n32n64_fp_arg_chunk_p (arg_type
,
3227 TYPE_LENGTH (arg_type
) - len
))
3230 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3232 phex (regval
, MIPS64_REGSIZE
));
3233 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3244 /* Compute the the offset into the stack at which we
3245 will copy the next parameter.
3247 In N32 (N64?), the stack_offset only needs to be
3248 adjusted when it has been used. */
3251 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3255 fprintf_unfiltered (gdb_stdlog
, "\n");
3258 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3260 /* Return adjusted stack pointer. */
3264 static enum return_value_convention
3265 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3266 struct type
*type
, struct regcache
*regcache
,
3267 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3269 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3271 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3273 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3274 if needed), as appropriate for the type. Composite results (struct,
3275 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3278 * A struct with only one or two floating point fields is returned in $f0
3279 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3282 * Any other struct or union results of at most 128 bits are returned in
3283 $2 (first 64 bits) and $3 (remainder, if necessary).
3285 * Larger composite results are handled by converting the function to a
3286 procedure with an implicit first parameter, which is a pointer to an area
3287 reserved by the caller to receive the result. [The o32-bit ABI requires
3288 that all composite results be handled by conversion to implicit first
3289 parameters. The MIPS/SGI Fortran implementation has always made a
3290 specific exception to return COMPLEX results in the floating point
3293 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
3294 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3295 return RETURN_VALUE_STRUCT_CONVENTION
;
3296 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3297 && TYPE_LENGTH (type
) == 16
3298 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3300 /* A 128-bit floating-point value fills both $f0 and $f2. The
3301 two registers are used in the same as memory order, so the
3302 eight bytes with the lower memory address are in $f0. */
3304 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3305 mips_xfer_register (gdbarch
, regcache
,
3306 gdbarch_num_regs (gdbarch
)
3307 + mips_regnum (gdbarch
)->fp0
,
3308 8, gdbarch_byte_order (gdbarch
),
3309 readbuf
, writebuf
, 0);
3310 mips_xfer_register (gdbarch
, regcache
,
3311 gdbarch_num_regs (gdbarch
)
3312 + mips_regnum (gdbarch
)->fp0
+ 2,
3313 8, gdbarch_byte_order (gdbarch
),
3314 readbuf
? readbuf
+ 8 : readbuf
,
3315 writebuf
? writebuf
+ 8 : writebuf
, 0);
3316 return RETURN_VALUE_REGISTER_CONVENTION
;
3318 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3319 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3321 /* A single or double floating-point value that fits in FP0. */
3323 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3324 mips_xfer_register (gdbarch
, regcache
,
3325 gdbarch_num_regs (gdbarch
)
3326 + mips_regnum (gdbarch
)->fp0
,
3328 gdbarch_byte_order (gdbarch
),
3329 readbuf
, writebuf
, 0);
3330 return RETURN_VALUE_REGISTER_CONVENTION
;
3332 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3333 && TYPE_NFIELDS (type
) <= 2
3334 && TYPE_NFIELDS (type
) >= 1
3335 && ((TYPE_NFIELDS (type
) == 1
3336 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3338 || (TYPE_NFIELDS (type
) == 2
3339 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3341 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3343 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3345 /* A struct that contains one or two floats. Each value is part
3346 in the least significant part of their floating point
3350 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3351 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3353 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3356 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3358 mips_xfer_register (gdbarch
, regcache
,
3359 gdbarch_num_regs (gdbarch
) + regnum
,
3360 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3361 gdbarch_byte_order (gdbarch
),
3362 readbuf
, writebuf
, offset
);
3364 return RETURN_VALUE_REGISTER_CONVENTION
;
3366 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3367 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3369 /* A structure or union. Extract the left justified value,
3370 regardless of the byte order. I.e. DO NOT USE
3374 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3375 offset
< TYPE_LENGTH (type
);
3376 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3378 int xfer
= register_size (gdbarch
, regnum
);
3379 if (offset
+ xfer
> TYPE_LENGTH (type
))
3380 xfer
= TYPE_LENGTH (type
) - offset
;
3382 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3383 offset
, xfer
, regnum
);
3384 mips_xfer_register (gdbarch
, regcache
,
3385 gdbarch_num_regs (gdbarch
) + regnum
,
3386 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3389 return RETURN_VALUE_REGISTER_CONVENTION
;
3393 /* A scalar extract each part but least-significant-byte
3397 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3398 offset
< TYPE_LENGTH (type
);
3399 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3401 int xfer
= register_size (gdbarch
, regnum
);
3402 if (offset
+ xfer
> TYPE_LENGTH (type
))
3403 xfer
= TYPE_LENGTH (type
) - offset
;
3405 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3406 offset
, xfer
, regnum
);
3407 mips_xfer_register (gdbarch
, regcache
,
3408 gdbarch_num_regs (gdbarch
) + regnum
,
3409 xfer
, gdbarch_byte_order (gdbarch
),
3410 readbuf
, writebuf
, offset
);
3412 return RETURN_VALUE_REGISTER_CONVENTION
;
3416 /* O32 ABI stuff. */
3419 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3420 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3421 int nargs
, struct value
**args
, CORE_ADDR sp
,
3422 int struct_return
, CORE_ADDR struct_addr
)
3428 int stack_offset
= 0;
3429 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3430 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3432 /* For shared libraries, "t9" needs to point at the function
3434 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3436 /* Set the return address register to point to the entry point of
3437 the program, where a breakpoint lies in wait. */
3438 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3440 /* First ensure that the stack and structure return address (if any)
3441 are properly aligned. The stack has to be at least 64-bit
3442 aligned even on 32-bit machines, because doubles must be 64-bit
3443 aligned. For n32 and n64, stack frames need to be 128-bit
3444 aligned, so we round to this widest known alignment. */
3446 sp
= align_down (sp
, 16);
3447 struct_addr
= align_down (struct_addr
, 16);
3449 /* Now make space on the stack for the args. */
3450 for (argnum
= 0; argnum
< nargs
; argnum
++)
3452 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3453 int arglen
= TYPE_LENGTH (arg_type
);
3455 /* Align to double-word if necessary. */
3456 if (mips_type_needs_double_align (arg_type
))
3457 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3458 /* Allocate space on the stack. */
3459 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3461 sp
-= align_up (len
, 16);
3464 fprintf_unfiltered (gdb_stdlog
,
3465 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3466 paddr_nz (sp
), (long) align_up (len
, 16));
3468 /* Initialize the integer and float register pointers. */
3469 argreg
= MIPS_A0_REGNUM
;
3470 float_argreg
= mips_fpa0_regnum (gdbarch
);
3472 /* The struct_return pointer occupies the first parameter-passing reg. */
3476 fprintf_unfiltered (gdb_stdlog
,
3477 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3478 argreg
, paddr_nz (struct_addr
));
3479 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3480 stack_offset
+= MIPS32_REGSIZE
;
3483 /* Now load as many as possible of the first arguments into
3484 registers, and push the rest onto the stack. Loop thru args
3485 from first to last. */
3486 for (argnum
= 0; argnum
< nargs
; argnum
++)
3488 const gdb_byte
*val
;
3489 struct value
*arg
= args
[argnum
];
3490 struct type
*arg_type
= check_typedef (value_type (arg
));
3491 int len
= TYPE_LENGTH (arg_type
);
3492 enum type_code typecode
= TYPE_CODE (arg_type
);
3495 fprintf_unfiltered (gdb_stdlog
,
3496 "mips_o32_push_dummy_call: %d len=%d type=%d",
3497 argnum
+ 1, len
, (int) typecode
);
3499 val
= value_contents (arg
);
3501 /* 32-bit ABIs always start floating point arguments in an
3502 even-numbered floating point register. Round the FP register
3503 up before the check to see if there are any FP registers
3504 left. O32/O64 targets also pass the FP in the integer
3505 registers so also round up normal registers. */
3506 if (fp_register_arg_p (typecode
, arg_type
))
3508 if ((float_argreg
& 1))
3512 /* Floating point arguments passed in registers have to be
3513 treated specially. On 32-bit architectures, doubles
3514 are passed in register pairs; the even register gets
3515 the low word, and the odd register gets the high word.
3516 On O32/O64, the first two floating point arguments are
3517 also copied to general registers, because MIPS16 functions
3518 don't use float registers for arguments. This duplication of
3519 arguments in general registers can't hurt non-MIPS16 functions
3520 because those registers are normally skipped. */
3522 if (fp_register_arg_p (typecode
, arg_type
)
3523 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3525 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3527 int low_offset
= gdbarch_byte_order (gdbarch
)
3528 == BFD_ENDIAN_BIG
? 4 : 0;
3529 unsigned long regval
;
3531 /* Write the low word of the double to the even register(s). */
3532 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3534 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3535 float_argreg
, phex (regval
, 4));
3536 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3538 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3539 argreg
, phex (regval
, 4));
3540 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3542 /* Write the high word of the double to the odd register(s). */
3543 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3545 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3546 float_argreg
, phex (regval
, 4));
3547 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3550 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3551 argreg
, phex (regval
, 4));
3552 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3556 /* This is a floating point value that fits entirely
3557 in a single register. */
3558 /* On 32 bit ABI's the float_argreg is further adjusted
3559 above to ensure that it is even register aligned. */
3560 LONGEST regval
= extract_unsigned_integer (val
, len
);
3562 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3563 float_argreg
, phex (regval
, len
));
3564 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3565 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3566 registers for each argument. The below is (my
3567 guess) to ensure that the corresponding integer
3568 register has reserved the same space. */
3570 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3571 argreg
, phex (regval
, len
));
3572 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3575 /* Reserve space for the FP register. */
3576 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3580 /* Copy the argument to general registers or the stack in
3581 register-sized pieces. Large arguments are split between
3582 registers and stack. */
3583 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3584 are treated specially: Irix cc passes
3585 them in registers where gcc sometimes puts them on the
3586 stack. For maximum compatibility, we will put them in
3588 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3589 && len
% MIPS32_REGSIZE
!= 0);
3590 /* Structures should be aligned to eight bytes (even arg registers)
3591 on MIPS_ABI_O32, if their first member has double precision. */
3592 if (mips_type_needs_double_align (arg_type
))
3597 stack_offset
+= MIPS32_REGSIZE
;
3602 /* Remember if the argument was written to the stack. */
3603 int stack_used_p
= 0;
3604 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3607 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3610 /* Write this portion of the argument to the stack. */
3611 if (argreg
> MIPS_LAST_ARG_REGNUM
3612 || odd_sized_struct
)
3614 /* Should shorter than int integer values be
3615 promoted to int before being stored? */
3616 int longword_offset
= 0;
3622 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3623 paddr_nz (stack_offset
));
3624 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3625 paddr_nz (longword_offset
));
3628 addr
= sp
+ stack_offset
+ longword_offset
;
3633 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3635 for (i
= 0; i
< partial_len
; i
++)
3637 fprintf_unfiltered (gdb_stdlog
, "%02x",
3641 write_memory (addr
, val
, partial_len
);
3644 /* Note!!! This is NOT an else clause. Odd sized
3645 structs may go thru BOTH paths. */
3646 /* Write this portion of the argument to a general
3647 purpose register. */
3648 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3650 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3651 /* Value may need to be sign extended, because
3652 mips_isa_regsize() != mips_abi_regsize(). */
3654 /* A non-floating-point argument being passed in a
3655 general register. If a struct or union, and if
3656 the remaining length is smaller than the register
3657 size, we have to adjust the register value on
3660 It does not seem to be necessary to do the
3661 same for integral types.
3663 Also don't do this adjustment on O64 binaries.
3665 cagney/2001-07-23: gdb/179: Also, GCC, when
3666 outputting LE O32 with sizeof (struct) <
3667 mips_abi_regsize(), generates a left shift
3668 as part of storing the argument in a register
3669 (the left shift isn't generated when
3670 sizeof (struct) >= mips_abi_regsize()). Since
3671 it is quite possible that this is GCC
3672 contradicting the LE/O32 ABI, GDB has not been
3673 adjusted to accommodate this. Either someone
3674 needs to demonstrate that the LE/O32 ABI
3675 specifies such a left shift OR this new ABI gets
3676 identified as such and GDB gets tweaked
3679 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3680 && partial_len
< MIPS32_REGSIZE
3681 && (typecode
== TYPE_CODE_STRUCT
3682 || typecode
== TYPE_CODE_UNION
))
3683 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3687 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3689 phex (regval
, MIPS32_REGSIZE
));
3690 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3693 /* Prevent subsequent floating point arguments from
3694 being passed in floating point registers. */
3695 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3701 /* Compute the the offset into the stack at which we
3702 will copy the next parameter.
3704 In older ABIs, the caller reserved space for
3705 registers that contained arguments. This was loosely
3706 refered to as their "home". Consequently, space is
3707 always allocated. */
3709 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3713 fprintf_unfiltered (gdb_stdlog
, "\n");
3716 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3718 /* Return adjusted stack pointer. */
3722 static enum return_value_convention
3723 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3724 struct type
*type
, struct regcache
*regcache
,
3725 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3727 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3729 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3730 || TYPE_CODE (type
) == TYPE_CODE_UNION
3731 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3732 return RETURN_VALUE_STRUCT_CONVENTION
;
3733 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3734 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3736 /* A single-precision floating-point value. It fits in the
3737 least significant part of FP0. */
3739 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3740 mips_xfer_register (gdbarch
, regcache
,
3741 gdbarch_num_regs (gdbarch
)
3742 + mips_regnum (gdbarch
)->fp0
,
3744 gdbarch_byte_order (gdbarch
),
3745 readbuf
, writebuf
, 0);
3746 return RETURN_VALUE_REGISTER_CONVENTION
;
3748 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3749 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3751 /* A double-precision floating-point value. The most
3752 significant part goes in FP1, and the least significant in
3755 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3756 switch (gdbarch_byte_order (gdbarch
))
3758 case BFD_ENDIAN_LITTLE
:
3759 mips_xfer_register (gdbarch
, regcache
,
3760 gdbarch_num_regs (gdbarch
)
3761 + mips_regnum (gdbarch
)->fp0
+
3762 0, 4, gdbarch_byte_order (gdbarch
),
3763 readbuf
, writebuf
, 0);
3764 mips_xfer_register (gdbarch
, regcache
,
3765 gdbarch_num_regs (gdbarch
)
3766 + mips_regnum (gdbarch
)->fp0
+ 1,
3767 4, gdbarch_byte_order (gdbarch
),
3768 readbuf
, writebuf
, 4);
3770 case BFD_ENDIAN_BIG
:
3771 mips_xfer_register (gdbarch
, regcache
,
3772 gdbarch_num_regs (gdbarch
)
3773 + mips_regnum (gdbarch
)->fp0
+ 1,
3774 4, gdbarch_byte_order (gdbarch
),
3775 readbuf
, writebuf
, 0);
3776 mips_xfer_register (gdbarch
, regcache
,
3777 gdbarch_num_regs (gdbarch
)
3778 + mips_regnum (gdbarch
)->fp0
+ 0,
3779 4, gdbarch_byte_order (gdbarch
),
3780 readbuf
, writebuf
, 4);
3783 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3785 return RETURN_VALUE_REGISTER_CONVENTION
;
3788 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3789 && TYPE_NFIELDS (type
) <= 2
3790 && TYPE_NFIELDS (type
) >= 1
3791 && ((TYPE_NFIELDS (type
) == 1
3792 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3794 || (TYPE_NFIELDS (type
) == 2
3795 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3797 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3799 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3801 /* A struct that contains one or two floats. Each value is part
3802 in the least significant part of their floating point
3804 gdb_byte reg
[MAX_REGISTER_SIZE
];
3807 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3808 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3810 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3813 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3815 mips_xfer_register (gdbarch
, regcache
,
3816 gdbarch_num_regs (gdbarch
) + regnum
,
3817 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3818 gdbarch_byte_order (gdbarch
),
3819 readbuf
, writebuf
, offset
);
3821 return RETURN_VALUE_REGISTER_CONVENTION
;
3825 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3826 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3828 /* A structure or union. Extract the left justified value,
3829 regardless of the byte order. I.e. DO NOT USE
3833 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3834 offset
< TYPE_LENGTH (type
);
3835 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3837 int xfer
= register_size (gdbarch
, regnum
);
3838 if (offset
+ xfer
> TYPE_LENGTH (type
))
3839 xfer
= TYPE_LENGTH (type
) - offset
;
3841 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3842 offset
, xfer
, regnum
);
3843 mips_xfer_register (gdbarch
, regcache
,
3844 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3845 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3847 return RETURN_VALUE_REGISTER_CONVENTION
;
3852 /* A scalar extract each part but least-significant-byte
3853 justified. o32 thinks registers are 4 byte, regardless of
3857 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3858 offset
< TYPE_LENGTH (type
);
3859 offset
+= MIPS32_REGSIZE
, regnum
++)
3861 int xfer
= MIPS32_REGSIZE
;
3862 if (offset
+ xfer
> TYPE_LENGTH (type
))
3863 xfer
= TYPE_LENGTH (type
) - offset
;
3865 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3866 offset
, xfer
, regnum
);
3867 mips_xfer_register (gdbarch
, regcache
,
3868 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3869 gdbarch_byte_order (gdbarch
),
3870 readbuf
, writebuf
, offset
);
3872 return RETURN_VALUE_REGISTER_CONVENTION
;
3876 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3880 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3881 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3883 struct value
**args
, CORE_ADDR sp
,
3884 int struct_return
, CORE_ADDR struct_addr
)
3890 int stack_offset
= 0;
3891 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3892 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3894 /* For shared libraries, "t9" needs to point at the function
3896 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3898 /* Set the return address register to point to the entry point of
3899 the program, where a breakpoint lies in wait. */
3900 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3902 /* First ensure that the stack and structure return address (if any)
3903 are properly aligned. The stack has to be at least 64-bit
3904 aligned even on 32-bit machines, because doubles must be 64-bit
3905 aligned. For n32 and n64, stack frames need to be 128-bit
3906 aligned, so we round to this widest known alignment. */
3908 sp
= align_down (sp
, 16);
3909 struct_addr
= align_down (struct_addr
, 16);
3911 /* Now make space on the stack for the args. */
3912 for (argnum
= 0; argnum
< nargs
; argnum
++)
3914 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3915 int arglen
= TYPE_LENGTH (arg_type
);
3917 /* Allocate space on the stack. */
3918 len
+= align_up (arglen
, MIPS64_REGSIZE
);
3920 sp
-= align_up (len
, 16);
3923 fprintf_unfiltered (gdb_stdlog
,
3924 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3925 paddr_nz (sp
), (long) align_up (len
, 16));
3927 /* Initialize the integer and float register pointers. */
3928 argreg
= MIPS_A0_REGNUM
;
3929 float_argreg
= mips_fpa0_regnum (gdbarch
);
3931 /* The struct_return pointer occupies the first parameter-passing reg. */
3935 fprintf_unfiltered (gdb_stdlog
,
3936 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3937 argreg
, paddr_nz (struct_addr
));
3938 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3939 stack_offset
+= MIPS64_REGSIZE
;
3942 /* Now load as many as possible of the first arguments into
3943 registers, and push the rest onto the stack. Loop thru args
3944 from first to last. */
3945 for (argnum
= 0; argnum
< nargs
; argnum
++)
3947 const gdb_byte
*val
;
3948 struct value
*arg
= args
[argnum
];
3949 struct type
*arg_type
= check_typedef (value_type (arg
));
3950 int len
= TYPE_LENGTH (arg_type
);
3951 enum type_code typecode
= TYPE_CODE (arg_type
);
3954 fprintf_unfiltered (gdb_stdlog
,
3955 "mips_o64_push_dummy_call: %d len=%d type=%d",
3956 argnum
+ 1, len
, (int) typecode
);
3958 val
= value_contents (arg
);
3960 /* Floating point arguments passed in registers have to be
3961 treated specially. On 32-bit architectures, doubles
3962 are passed in register pairs; the even register gets
3963 the low word, and the odd register gets the high word.
3964 On O32/O64, the first two floating point arguments are
3965 also copied to general registers, because MIPS16 functions
3966 don't use float registers for arguments. This duplication of
3967 arguments in general registers can't hurt non-MIPS16 functions
3968 because those registers are normally skipped. */
3970 if (fp_register_arg_p (typecode
, arg_type
)
3971 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3973 LONGEST regval
= extract_unsigned_integer (val
, len
);
3975 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3976 float_argreg
, phex (regval
, len
));
3977 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3979 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3980 argreg
, phex (regval
, len
));
3981 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3983 /* Reserve space for the FP register. */
3984 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
3988 /* Copy the argument to general registers or the stack in
3989 register-sized pieces. Large arguments are split between
3990 registers and stack. */
3991 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
3992 are treated specially: Irix cc passes them in registers
3993 where gcc sometimes puts them on the stack. For maximum
3994 compatibility, we will put them in both places. */
3995 int odd_sized_struct
= (len
> MIPS64_REGSIZE
3996 && len
% MIPS64_REGSIZE
!= 0);
3999 /* Remember if the argument was written to the stack. */
4000 int stack_used_p
= 0;
4001 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4004 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4007 /* Write this portion of the argument to the stack. */
4008 if (argreg
> MIPS_LAST_ARG_REGNUM
4009 || odd_sized_struct
)
4011 /* Should shorter than int integer values be
4012 promoted to int before being stored? */
4013 int longword_offset
= 0;
4016 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4018 if ((typecode
== TYPE_CODE_INT
4019 || typecode
== TYPE_CODE_PTR
4020 || typecode
== TYPE_CODE_FLT
)
4022 longword_offset
= MIPS64_REGSIZE
- len
;
4027 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4028 paddr_nz (stack_offset
));
4029 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4030 paddr_nz (longword_offset
));
4033 addr
= sp
+ stack_offset
+ longword_offset
;
4038 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4040 for (i
= 0; i
< partial_len
; i
++)
4042 fprintf_unfiltered (gdb_stdlog
, "%02x",
4046 write_memory (addr
, val
, partial_len
);
4049 /* Note!!! This is NOT an else clause. Odd sized
4050 structs may go thru BOTH paths. */
4051 /* Write this portion of the argument to a general
4052 purpose register. */
4053 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
4055 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4056 /* Value may need to be sign extended, because
4057 mips_isa_regsize() != mips_abi_regsize(). */
4059 /* A non-floating-point argument being passed in a
4060 general register. If a struct or union, and if
4061 the remaining length is smaller than the register
4062 size, we have to adjust the register value on
4065 It does not seem to be necessary to do the
4066 same for integral types. */
4068 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4069 && partial_len
< MIPS64_REGSIZE
4070 && (typecode
== TYPE_CODE_STRUCT
4071 || typecode
== TYPE_CODE_UNION
))
4072 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4076 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4078 phex (regval
, MIPS64_REGSIZE
));
4079 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4082 /* Prevent subsequent floating point arguments from
4083 being passed in floating point registers. */
4084 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4090 /* Compute the the offset into the stack at which we
4091 will copy the next parameter.
4093 In older ABIs, the caller reserved space for
4094 registers that contained arguments. This was loosely
4095 refered to as their "home". Consequently, space is
4096 always allocated. */
4098 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4102 fprintf_unfiltered (gdb_stdlog
, "\n");
4105 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4107 /* Return adjusted stack pointer. */
4111 static enum return_value_convention
4112 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4113 struct type
*type
, struct regcache
*regcache
,
4114 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4116 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4118 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4119 || TYPE_CODE (type
) == TYPE_CODE_UNION
4120 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4121 return RETURN_VALUE_STRUCT_CONVENTION
;
4122 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
4124 /* A floating-point value. It fits in the least significant
4127 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4128 mips_xfer_register (gdbarch
, regcache
,
4129 gdbarch_num_regs (gdbarch
)
4130 + mips_regnum (gdbarch
)->fp0
,
4132 gdbarch_byte_order (gdbarch
),
4133 readbuf
, writebuf
, 0);
4134 return RETURN_VALUE_REGISTER_CONVENTION
;
4138 /* A scalar extract each part but least-significant-byte
4142 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4143 offset
< TYPE_LENGTH (type
);
4144 offset
+= MIPS64_REGSIZE
, regnum
++)
4146 int xfer
= MIPS64_REGSIZE
;
4147 if (offset
+ xfer
> TYPE_LENGTH (type
))
4148 xfer
= TYPE_LENGTH (type
) - offset
;
4150 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4151 offset
, xfer
, regnum
);
4152 mips_xfer_register (gdbarch
, regcache
,
4153 gdbarch_num_regs (gdbarch
) + regnum
,
4154 xfer
, gdbarch_byte_order (gdbarch
),
4155 readbuf
, writebuf
, offset
);
4157 return RETURN_VALUE_REGISTER_CONVENTION
;
4161 /* Floating point register management.
4163 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4164 64bit operations, these early MIPS cpus treat fp register pairs
4165 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4166 registers and offer a compatibility mode that emulates the MIPS2 fp
4167 model. When operating in MIPS2 fp compat mode, later cpu's split
4168 double precision floats into two 32-bit chunks and store them in
4169 consecutive fp regs. To display 64-bit floats stored in this
4170 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4171 Throw in user-configurable endianness and you have a real mess.
4173 The way this works is:
4174 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4175 double-precision value will be split across two logical registers.
4176 The lower-numbered logical register will hold the low-order bits,
4177 regardless of the processor's endianness.
4178 - If we are on a 64-bit processor, and we are looking for a
4179 single-precision value, it will be in the low ordered bits
4180 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4181 save slot in memory.
4182 - If we are in 64-bit mode, everything is straightforward.
4184 Note that this code only deals with "live" registers at the top of the
4185 stack. We will attempt to deal with saved registers later, when
4186 the raw/cooked register interface is in place. (We need a general
4187 interface that can deal with dynamic saved register sizes -- fp
4188 regs could be 32 bits wide in one frame and 64 on the frame above
4191 static struct type
*
4192 mips_float_register_type (void)
4194 return builtin_type_ieee_single
;
4197 static struct type
*
4198 mips_double_register_type (void)
4200 return builtin_type_ieee_double
;
4203 /* Copy a 32-bit single-precision value from the current frame
4204 into rare_buffer. */
4207 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4208 gdb_byte
*rare_buffer
)
4210 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4211 int raw_size
= register_size (gdbarch
, regno
);
4212 gdb_byte
*raw_buffer
= alloca (raw_size
);
4214 if (!frame_register_read (frame
, regno
, raw_buffer
))
4215 error (_("can't read register %d (%s)"),
4216 regno
, gdbarch_register_name (gdbarch
, regno
));
4219 /* We have a 64-bit value for this register. Find the low-order
4223 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4228 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4232 memcpy (rare_buffer
, raw_buffer
, 4);
4236 /* Copy a 64-bit double-precision value from the current frame into
4237 rare_buffer. This may include getting half of it from the next
4241 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4242 gdb_byte
*rare_buffer
)
4244 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4245 int raw_size
= register_size (gdbarch
, regno
);
4247 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4249 /* We have a 64-bit value for this register, and we should use
4251 if (!frame_register_read (frame
, regno
, rare_buffer
))
4252 error (_("can't read register %d (%s)"),
4253 regno
, gdbarch_register_name (gdbarch
, regno
));
4257 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4259 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4260 internal_error (__FILE__
, __LINE__
,
4261 _("mips_read_fp_register_double: bad access to "
4262 "odd-numbered FP register"));
4264 /* mips_read_fp_register_single will find the correct 32 bits from
4266 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4268 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4269 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4273 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4274 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4280 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4282 { /* do values for FP (float) regs */
4283 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4284 gdb_byte
*raw_buffer
;
4285 double doub
, flt1
; /* doubles extracted from raw hex data */
4288 raw_buffer
= alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
));
4290 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4291 fprintf_filtered (file
, "%*s",
4292 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4295 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4297 /* 4-byte registers: Print hex and floating. Also print even
4298 numbered registers as doubles. */
4299 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4300 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4302 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4305 fprintf_filtered (file
, " flt: ");
4307 fprintf_filtered (file
, " <invalid float> ");
4309 fprintf_filtered (file
, "%-17.9g", flt1
);
4311 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4313 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4314 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4317 fprintf_filtered (file
, " dbl: ");
4319 fprintf_filtered (file
, "<invalid double>");
4321 fprintf_filtered (file
, "%-24.17g", doub
);
4326 /* Eight byte registers: print each one as hex, float and double. */
4327 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4328 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4330 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4331 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4334 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4337 fprintf_filtered (file
, " flt: ");
4339 fprintf_filtered (file
, "<invalid float>");
4341 fprintf_filtered (file
, "%-17.9g", flt1
);
4343 fprintf_filtered (file
, " dbl: ");
4345 fprintf_filtered (file
, "<invalid double>");
4347 fprintf_filtered (file
, "%-24.17g", doub
);
4352 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4355 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4356 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4359 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4361 mips_print_fp_register (file
, frame
, regnum
);
4365 /* Get the data in raw format. */
4366 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4368 fprintf_filtered (file
, "%s: [Invalid]",
4369 gdbarch_register_name (gdbarch
, regnum
));
4373 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4375 /* The problem with printing numeric register names (r26, etc.) is that
4376 the user can't use them on input. Probably the best solution is to
4377 fix it so that either the numeric or the funky (a2, etc.) names
4378 are accepted on input. */
4379 if (regnum
< MIPS_NUMREGS
)
4380 fprintf_filtered (file
, "(r%d): ", regnum
);
4382 fprintf_filtered (file
, ": ");
4384 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4386 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4390 print_scalar_formatted (raw_buffer
+ offset
,
4391 register_type (gdbarch
, regnum
), 'x', 0,
4395 /* Replacement for generic do_registers_info.
4396 Print regs in pretty columns. */
4399 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4402 fprintf_filtered (file
, " ");
4403 mips_print_fp_register (file
, frame
, regnum
);
4404 fprintf_filtered (file
, "\n");
4409 /* Print a row's worth of GP (int) registers, with name labels above */
4412 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4415 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4416 /* do values for GP (int) regs */
4417 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4418 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4422 /* For GP registers, we print a separate row of names above the vals */
4423 for (col
= 0, regnum
= start_regnum
;
4424 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4425 + gdbarch_num_pseudo_regs (gdbarch
);
4428 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4429 continue; /* unused register */
4430 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4432 break; /* end the row: reached FP register */
4433 /* Large registers are handled separately. */
4434 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4437 break; /* End the row before this register. */
4439 /* Print this register on a row by itself. */
4440 mips_print_register (file
, frame
, regnum
);
4441 fprintf_filtered (file
, "\n");
4445 fprintf_filtered (file
, " ");
4446 fprintf_filtered (file
,
4447 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4448 gdbarch_register_name (gdbarch
, regnum
));
4455 /* print the R0 to R31 names */
4456 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4457 fprintf_filtered (file
, "\n R%-4d",
4458 start_regnum
% gdbarch_num_regs (gdbarch
));
4460 fprintf_filtered (file
, "\n ");
4462 /* now print the values in hex, 4 or 8 to the row */
4463 for (col
= 0, regnum
= start_regnum
;
4464 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4465 + gdbarch_num_pseudo_regs (gdbarch
);
4468 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4469 continue; /* unused register */
4470 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4472 break; /* end row: reached FP register */
4473 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4474 break; /* End row: large register. */
4476 /* OK: get the data in raw format. */
4477 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4478 error (_("can't read register %d (%s)"),
4479 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4480 /* pad small registers */
4482 byte
< (mips_abi_regsize (gdbarch
)
4483 - register_size (gdbarch
, regnum
)); byte
++)
4484 printf_filtered (" ");
4485 /* Now print the register value in hex, endian order. */
4486 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4488 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4489 byte
< register_size (gdbarch
, regnum
); byte
++)
4490 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4492 for (byte
= register_size (gdbarch
, regnum
) - 1;
4494 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4495 fprintf_filtered (file
, " ");
4498 if (col
> 0) /* ie. if we actually printed anything... */
4499 fprintf_filtered (file
, "\n");
4504 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4507 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4508 struct frame_info
*frame
, int regnum
, int all
)
4510 if (regnum
!= -1) /* do one specified register */
4512 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4513 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4514 error (_("Not a valid register for the current processor type"));
4516 mips_print_register (file
, frame
, regnum
);
4517 fprintf_filtered (file
, "\n");
4520 /* do all (or most) registers */
4522 regnum
= gdbarch_num_regs (gdbarch
);
4523 while (regnum
< gdbarch_num_regs (gdbarch
)
4524 + gdbarch_num_pseudo_regs (gdbarch
))
4526 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4529 if (all
) /* true for "INFO ALL-REGISTERS" command */
4530 regnum
= print_fp_register_row (file
, frame
, regnum
);
4532 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4535 regnum
= print_gp_register_row (file
, frame
, regnum
);
4540 /* Is this a branch with a delay slot? */
4543 is_delayed (unsigned long insn
)
4546 for (i
= 0; i
< NUMOPCODES
; ++i
)
4547 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4548 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4550 return (i
< NUMOPCODES
4551 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4552 | INSN_COND_BRANCH_DELAY
4553 | INSN_COND_BRANCH_LIKELY
)));
4557 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4558 struct frame_info
*frame
)
4560 CORE_ADDR pc
= get_frame_pc (frame
);
4561 gdb_byte buf
[MIPS_INSN32_SIZE
];
4563 /* There is no branch delay slot on MIPS16. */
4564 if (mips_pc_is_mips16 (pc
))
4567 if (!breakpoint_here_p (pc
+ 4))
4570 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4571 /* If error reading memory, guess that it is not a delayed
4574 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4577 /* To skip prologues, I use this predicate. Returns either PC itself
4578 if the code at PC does not look like a function prologue; otherwise
4579 returns an address that (if we're lucky) follows the prologue. If
4580 LENIENT, then we must skip everything which is involved in setting
4581 up the frame (it's OK to skip more, just so long as we don't skip
4582 anything which might clobber the registers which are being saved.
4583 We must skip more in the case where part of the prologue is in the
4584 delay slot of a non-prologue instruction). */
4587 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4590 CORE_ADDR func_addr
;
4592 /* See if we can determine the end of the prologue via the symbol table.
4593 If so, then return either PC, or the PC after the prologue, whichever
4595 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4597 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4598 if (post_prologue_pc
!= 0)
4599 return max (pc
, post_prologue_pc
);
4602 /* Can't determine prologue from the symbol table, need to examine
4605 /* Find an upper limit on the function prologue using the debug
4606 information. If the debug information could not be used to provide
4607 that bound, then use an arbitrary large number as the upper bound. */
4608 limit_pc
= skip_prologue_using_sal (pc
);
4610 limit_pc
= pc
+ 100; /* Magic. */
4612 if (mips_pc_is_mips16 (pc
))
4613 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4615 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4618 /* Check whether the PC is in a function epilogue (32-bit version).
4619 This is a helper function for mips_in_function_epilogue_p. */
4621 mips32_in_function_epilogue_p (CORE_ADDR pc
)
4623 CORE_ADDR func_addr
= 0, func_end
= 0;
4625 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4627 /* The MIPS epilogue is max. 12 bytes long. */
4628 CORE_ADDR addr
= func_end
- 12;
4630 if (addr
< func_addr
+ 4)
4631 addr
= func_addr
+ 4;
4635 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4637 unsigned long high_word
;
4640 inst
= mips_fetch_instruction (pc
);
4641 high_word
= (inst
>> 16) & 0xffff;
4643 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4644 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4645 && inst
!= 0x03e00008 /* jr $ra */
4646 && inst
!= 0x00000000) /* nop */
4656 /* Check whether the PC is in a function epilogue (16-bit version).
4657 This is a helper function for mips_in_function_epilogue_p. */
4659 mips16_in_function_epilogue_p (CORE_ADDR pc
)
4661 CORE_ADDR func_addr
= 0, func_end
= 0;
4663 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4665 /* The MIPS epilogue is max. 12 bytes long. */
4666 CORE_ADDR addr
= func_end
- 12;
4668 if (addr
< func_addr
+ 4)
4669 addr
= func_addr
+ 4;
4673 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4675 unsigned short inst
;
4677 inst
= mips_fetch_instruction (pc
);
4679 if ((inst
& 0xf800) == 0xf000) /* extend */
4682 if (inst
!= 0x6300 /* addiu $sp,offset */
4683 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
4684 && inst
!= 0xe820 /* jr $ra */
4685 && inst
!= 0xe8a0 /* jrc $ra */
4686 && inst
!= 0x6500) /* nop */
4696 /* The epilogue is defined here as the area at the end of a function,
4697 after an instruction which destroys the function's stack frame. */
4699 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4701 if (mips_pc_is_mips16 (pc
))
4702 return mips16_in_function_epilogue_p (pc
);
4704 return mips32_in_function_epilogue_p (pc
);
4707 /* Root of all "set mips "/"show mips " commands. This will eventually be
4708 used for all MIPS-specific commands. */
4711 show_mips_command (char *args
, int from_tty
)
4713 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4717 set_mips_command (char *args
, int from_tty
)
4720 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4721 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4724 /* Commands to show/set the MIPS FPU type. */
4727 show_mipsfpu_command (char *args
, int from_tty
)
4731 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
4734 ("The MIPS floating-point coprocessor is unknown "
4735 "because the current architecture is not MIPS.\n");
4739 switch (MIPS_FPU_TYPE
)
4741 case MIPS_FPU_SINGLE
:
4742 fpu
= "single-precision";
4744 case MIPS_FPU_DOUBLE
:
4745 fpu
= "double-precision";
4748 fpu
= "absent (none)";
4751 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4753 if (mips_fpu_type_auto
)
4755 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4759 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4764 set_mipsfpu_command (char *args
, int from_tty
)
4767 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4768 show_mipsfpu_command (args
, from_tty
);
4772 set_mipsfpu_single_command (char *args
, int from_tty
)
4774 struct gdbarch_info info
;
4775 gdbarch_info_init (&info
);
4776 mips_fpu_type
= MIPS_FPU_SINGLE
;
4777 mips_fpu_type_auto
= 0;
4778 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4779 instead of relying on globals. Doing that would let generic code
4780 handle the search for this specific architecture. */
4781 if (!gdbarch_update_p (info
))
4782 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4786 set_mipsfpu_double_command (char *args
, int from_tty
)
4788 struct gdbarch_info info
;
4789 gdbarch_info_init (&info
);
4790 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4791 mips_fpu_type_auto
= 0;
4792 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4793 instead of relying on globals. Doing that would let generic code
4794 handle the search for this specific architecture. */
4795 if (!gdbarch_update_p (info
))
4796 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4800 set_mipsfpu_none_command (char *args
, int from_tty
)
4802 struct gdbarch_info info
;
4803 gdbarch_info_init (&info
);
4804 mips_fpu_type
= MIPS_FPU_NONE
;
4805 mips_fpu_type_auto
= 0;
4806 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4807 instead of relying on globals. Doing that would let generic code
4808 handle the search for this specific architecture. */
4809 if (!gdbarch_update_p (info
))
4810 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4814 set_mipsfpu_auto_command (char *args
, int from_tty
)
4816 mips_fpu_type_auto
= 1;
4819 /* Attempt to identify the particular processor model by reading the
4820 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4821 the relevant processor still exists (it dates back to '94) and
4822 secondly this is not the way to do this. The processor type should
4823 be set by forcing an architecture change. */
4826 deprecated_mips_set_processor_regs_hack (void)
4828 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4831 regcache_cooked_read_unsigned (get_current_regcache (),
4832 MIPS_PRID_REGNUM
, &prid
);
4833 if ((prid
& ~0xf) == 0x700)
4834 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4837 /* Just like reinit_frame_cache, but with the right arguments to be
4838 callable as an sfunc. */
4841 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4842 struct cmd_list_element
*c
)
4844 reinit_frame_cache ();
4848 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4850 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4852 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4853 disassembler needs to be able to locally determine the ISA, and
4854 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4856 if (mips_pc_is_mips16 (memaddr
))
4857 info
->mach
= bfd_mach_mips16
;
4859 /* Round down the instruction address to the appropriate boundary. */
4860 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4862 /* Set the disassembler options. */
4863 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4865 /* Set up the disassembler info, so that we get the right
4866 register names from libopcodes. */
4867 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4868 info
->disassembler_options
= "gpr-names=n32";
4870 info
->disassembler_options
= "gpr-names=64";
4871 info
->flavour
= bfd_target_elf_flavour
;
4874 /* This string is not recognized explicitly by the disassembler,
4875 but it tells the disassembler to not try to guess the ABI from
4876 the bfd elf headers, such that, if the user overrides the ABI
4877 of a program linked as NewABI, the disassembly will follow the
4878 register naming conventions specified by the user. */
4879 info
->disassembler_options
= "gpr-names=32";
4881 /* Call the appropriate disassembler based on the target endian-ness. */
4882 if (info
->endian
== BFD_ENDIAN_BIG
)
4883 return print_insn_big_mips (memaddr
, info
);
4885 return print_insn_little_mips (memaddr
, info
);
4888 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4889 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4890 It returns a pointer to a string of bytes that encode a breakpoint
4891 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4892 necessary) to point to the actual memory location where the breakpoint
4893 should be inserted. */
4895 static const gdb_byte
*
4896 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
4898 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4900 if (mips_pc_is_mips16 (*pcptr
))
4902 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4903 *pcptr
= unmake_mips16_addr (*pcptr
);
4904 *lenptr
= sizeof (mips16_big_breakpoint
);
4905 return mips16_big_breakpoint
;
4909 /* The IDT board uses an unusual breakpoint value, and
4910 sometimes gets confused when it sees the usual MIPS
4911 breakpoint instruction. */
4912 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4913 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4914 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4916 *lenptr
= sizeof (big_breakpoint
);
4918 if (strcmp (target_shortname
, "mips") == 0)
4919 return idt_big_breakpoint
;
4920 else if (strcmp (target_shortname
, "ddb") == 0
4921 || strcmp (target_shortname
, "pmon") == 0
4922 || strcmp (target_shortname
, "lsi") == 0)
4923 return pmon_big_breakpoint
;
4925 return big_breakpoint
;
4930 if (mips_pc_is_mips16 (*pcptr
))
4932 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4933 *pcptr
= unmake_mips16_addr (*pcptr
);
4934 *lenptr
= sizeof (mips16_little_breakpoint
);
4935 return mips16_little_breakpoint
;
4939 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4940 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4941 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4943 *lenptr
= sizeof (little_breakpoint
);
4945 if (strcmp (target_shortname
, "mips") == 0)
4946 return idt_little_breakpoint
;
4947 else if (strcmp (target_shortname
, "ddb") == 0
4948 || strcmp (target_shortname
, "pmon") == 0
4949 || strcmp (target_shortname
, "lsi") == 0)
4950 return pmon_little_breakpoint
;
4952 return little_breakpoint
;
4957 /* If PC is in a mips16 call or return stub, return the address of the target
4958 PC, which is either the callee or the caller. There are several
4959 cases which must be handled:
4961 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4962 target PC is in $31 ($ra).
4963 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4964 and the target PC is in $2.
4965 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4966 before the jal instruction, this is effectively a call stub
4967 and the the target PC is in $2. Otherwise this is effectively
4968 a return stub and the target PC is in $18.
4970 See the source code for the stubs in gcc/config/mips/mips16.S for
4974 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
4977 CORE_ADDR start_addr
;
4979 /* Find the starting address and name of the function containing the PC. */
4980 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4983 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4984 target PC is in $31 ($ra). */
4985 if (strcmp (name
, "__mips16_ret_sf") == 0
4986 || strcmp (name
, "__mips16_ret_df") == 0)
4987 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
4989 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4991 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4992 and the target PC is in $2. */
4993 if (name
[19] >= '0' && name
[19] <= '9')
4994 return get_frame_register_signed (frame
, 2);
4996 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4997 before the jal instruction, this is effectively a call stub
4998 and the the target PC is in $2. Otherwise this is effectively
4999 a return stub and the target PC is in $18. */
5000 else if (name
[19] == 's' || name
[19] == 'd')
5002 if (pc
== start_addr
)
5004 /* Check if the target of the stub is a compiler-generated
5005 stub. Such a stub for a function bar might have a name
5006 like __fn_stub_bar, and might look like this:
5011 la $1,bar (becomes a lui/addiu pair)
5013 So scan down to the lui/addi and extract the target
5014 address from those two instructions. */
5016 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5020 /* See if the name of the target function is __fn_stub_*. */
5021 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5024 if (strncmp (name
, "__fn_stub_", 10) != 0
5025 && strcmp (name
, "etext") != 0
5026 && strcmp (name
, "_etext") != 0)
5029 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5030 The limit on the search is arbitrarily set to 20
5031 instructions. FIXME. */
5032 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5034 inst
= mips_fetch_instruction (target_pc
);
5035 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5036 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5037 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5038 return pc
| (inst
& 0xffff); /* low word */
5041 /* Couldn't find the lui/addui pair, so return stub address. */
5045 /* This is the 'return' part of a call stub. The return
5046 address is in $r18. */
5047 return get_frame_register_signed (frame
, 18);
5050 return 0; /* not a stub */
5053 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5054 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5057 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5060 if (num
>= 0 && num
< 32)
5062 else if (num
>= 38 && num
< 70)
5063 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5065 regnum
= mips_regnum (gdbarch
)->hi
;
5067 regnum
= mips_regnum (gdbarch
)->lo
;
5069 /* This will hopefully (eventually) provoke a warning. Should
5070 we be calling complaint() here? */
5071 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5072 return gdbarch_num_regs (gdbarch
) + regnum
;
5076 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5077 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5080 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5083 if (num
>= 0 && num
< 32)
5085 else if (num
>= 32 && num
< 64)
5086 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5088 regnum
= mips_regnum (gdbarch
)->hi
;
5090 regnum
= mips_regnum (gdbarch
)->lo
;
5092 /* This will hopefully (eventually) provoke a warning. Should we
5093 be calling complaint() here? */
5094 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5095 return gdbarch_num_regs (gdbarch
) + regnum
;
5099 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5101 /* Only makes sense to supply raw registers. */
5102 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5103 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5104 decide if it is valid. Should instead define a standard sim/gdb
5105 register numbering scheme. */
5106 if (gdbarch_register_name (gdbarch
,
5107 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5108 && gdbarch_register_name (gdbarch
,
5109 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
5112 return LEGACY_SIM_REGNO_IGNORE
;
5116 /* Convert an integer into an address. Extracting the value signed
5117 guarantees a correctly sign extended address. */
5120 mips_integer_to_address (struct gdbarch
*gdbarch
,
5121 struct type
*type
, const gdb_byte
*buf
)
5123 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
5126 /* Dummy virtual frame pointer method. This is no more or less accurate
5127 than most other architectures; we just need to be explicit about it,
5128 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5129 an assertion failure. */
5132 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5133 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5135 *reg
= MIPS_SP_REGNUM
;
5140 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5142 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5143 const char *name
= bfd_get_section_name (abfd
, sect
);
5145 if (*abip
!= MIPS_ABI_UNKNOWN
)
5148 if (strncmp (name
, ".mdebug.", 8) != 0)
5151 if (strcmp (name
, ".mdebug.abi32") == 0)
5152 *abip
= MIPS_ABI_O32
;
5153 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5154 *abip
= MIPS_ABI_N32
;
5155 else if (strcmp (name
, ".mdebug.abi64") == 0)
5156 *abip
= MIPS_ABI_N64
;
5157 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5158 *abip
= MIPS_ABI_O64
;
5159 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5160 *abip
= MIPS_ABI_EABI32
;
5161 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5162 *abip
= MIPS_ABI_EABI64
;
5164 warning (_("unsupported ABI %s."), name
+ 8);
5168 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5170 int *lbp
= (int *) obj
;
5171 const char *name
= bfd_get_section_name (abfd
, sect
);
5173 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5175 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5177 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5178 warning (_("unrecognized .gcc_compiled_longXX"));
5181 static enum mips_abi
5182 global_mips_abi (void)
5186 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5187 if (mips_abi_strings
[i
] == mips_abi_string
)
5188 return (enum mips_abi
) i
;
5190 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5194 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5196 /* If the size matches the set of 32-bit or 64-bit integer registers,
5197 assume that's what we've got. */
5198 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5199 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5201 /* If the size matches the full set of registers GDB traditionally
5202 knows about, including floating point, for either 32-bit or
5203 64-bit, assume that's what we've got. */
5204 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5205 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5207 /* Otherwise we don't have a useful guess. */
5210 static struct value
*
5211 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5213 const int *reg_p
= baton
;
5214 return value_of_register (*reg_p
, frame
);
5217 static struct gdbarch
*
5218 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5220 struct gdbarch
*gdbarch
;
5221 struct gdbarch_tdep
*tdep
;
5223 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5225 enum mips_fpu_type fpu_type
;
5226 struct tdesc_arch_data
*tdesc_data
= NULL
;
5227 int elf_fpu_type
= 0;
5229 /* Check any target description for validity. */
5230 if (tdesc_has_registers (info
.target_desc
))
5232 static const char *const mips_gprs
[] = {
5233 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5234 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5235 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5236 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5238 static const char *const mips_fprs
[] = {
5239 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5240 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5241 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5242 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5245 const struct tdesc_feature
*feature
;
5248 feature
= tdesc_find_feature (info
.target_desc
,
5249 "org.gnu.gdb.mips.cpu");
5250 if (feature
== NULL
)
5253 tdesc_data
= tdesc_data_alloc ();
5256 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5257 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5261 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5262 MIPS_EMBED_LO_REGNUM
, "lo");
5263 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5264 MIPS_EMBED_HI_REGNUM
, "hi");
5265 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5266 MIPS_EMBED_PC_REGNUM
, "pc");
5270 tdesc_data_cleanup (tdesc_data
);
5274 feature
= tdesc_find_feature (info
.target_desc
,
5275 "org.gnu.gdb.mips.cp0");
5276 if (feature
== NULL
)
5278 tdesc_data_cleanup (tdesc_data
);
5283 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5284 MIPS_EMBED_BADVADDR_REGNUM
,
5286 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5287 MIPS_PS_REGNUM
, "status");
5288 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5289 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5293 tdesc_data_cleanup (tdesc_data
);
5297 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5298 backend is not prepared for that, though. */
5299 feature
= tdesc_find_feature (info
.target_desc
,
5300 "org.gnu.gdb.mips.fpu");
5301 if (feature
== NULL
)
5303 tdesc_data_cleanup (tdesc_data
);
5308 for (i
= 0; i
< 32; i
++)
5309 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5310 i
+ MIPS_EMBED_FP0_REGNUM
,
5313 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5314 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5315 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5316 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5320 tdesc_data_cleanup (tdesc_data
);
5324 /* It would be nice to detect an attempt to use a 64-bit ABI
5325 when only 32-bit registers are provided. */
5328 /* First of all, extract the elf_flags, if available. */
5329 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5330 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5331 else if (arches
!= NULL
)
5332 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5336 fprintf_unfiltered (gdb_stdlog
,
5337 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5339 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5340 switch ((elf_flags
& EF_MIPS_ABI
))
5342 case E_MIPS_ABI_O32
:
5343 found_abi
= MIPS_ABI_O32
;
5345 case E_MIPS_ABI_O64
:
5346 found_abi
= MIPS_ABI_O64
;
5348 case E_MIPS_ABI_EABI32
:
5349 found_abi
= MIPS_ABI_EABI32
;
5351 case E_MIPS_ABI_EABI64
:
5352 found_abi
= MIPS_ABI_EABI64
;
5355 if ((elf_flags
& EF_MIPS_ABI2
))
5356 found_abi
= MIPS_ABI_N32
;
5358 found_abi
= MIPS_ABI_UNKNOWN
;
5362 /* GCC creates a pseudo-section whose name describes the ABI. */
5363 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5364 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5366 /* If we have no useful BFD information, use the ABI from the last
5367 MIPS architecture (if there is one). */
5368 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5369 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5371 /* Try the architecture for any hint of the correct ABI. */
5372 if (found_abi
== MIPS_ABI_UNKNOWN
5373 && info
.bfd_arch_info
!= NULL
5374 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5376 switch (info
.bfd_arch_info
->mach
)
5378 case bfd_mach_mips3900
:
5379 found_abi
= MIPS_ABI_EABI32
;
5381 case bfd_mach_mips4100
:
5382 case bfd_mach_mips5000
:
5383 found_abi
= MIPS_ABI_EABI64
;
5385 case bfd_mach_mips8000
:
5386 case bfd_mach_mips10000
:
5387 /* On Irix, ELF64 executables use the N64 ABI. The
5388 pseudo-sections which describe the ABI aren't present
5389 on IRIX. (Even for executables created by gcc.) */
5390 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5391 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5392 found_abi
= MIPS_ABI_N64
;
5394 found_abi
= MIPS_ABI_N32
;
5399 /* Default 64-bit objects to N64 instead of O32. */
5400 if (found_abi
== MIPS_ABI_UNKNOWN
5401 && info
.abfd
!= NULL
5402 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5403 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5404 found_abi
= MIPS_ABI_N64
;
5407 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5410 /* What has the user specified from the command line? */
5411 wanted_abi
= global_mips_abi ();
5413 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5416 /* Now that we have found what the ABI for this binary would be,
5417 check whether the user is overriding it. */
5418 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5419 mips_abi
= wanted_abi
;
5420 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5421 mips_abi
= found_abi
;
5423 mips_abi
= MIPS_ABI_O32
;
5425 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5428 /* Also used when doing an architecture lookup. */
5430 fprintf_unfiltered (gdb_stdlog
,
5431 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5432 mips64_transfers_32bit_regs_p
);
5434 /* Determine the MIPS FPU type. */
5437 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5438 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5439 Tag_GNU_MIPS_ABI_FP
);
5440 #endif /* HAVE_ELF */
5442 if (!mips_fpu_type_auto
)
5443 fpu_type
= mips_fpu_type
;
5444 else if (elf_fpu_type
!= 0)
5446 switch (elf_fpu_type
)
5449 fpu_type
= MIPS_FPU_DOUBLE
;
5452 fpu_type
= MIPS_FPU_SINGLE
;
5456 /* Soft float or unknown. */
5457 fpu_type
= MIPS_FPU_NONE
;
5461 else if (info
.bfd_arch_info
!= NULL
5462 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5463 switch (info
.bfd_arch_info
->mach
)
5465 case bfd_mach_mips3900
:
5466 case bfd_mach_mips4100
:
5467 case bfd_mach_mips4111
:
5468 case bfd_mach_mips4120
:
5469 fpu_type
= MIPS_FPU_NONE
;
5471 case bfd_mach_mips4650
:
5472 fpu_type
= MIPS_FPU_SINGLE
;
5475 fpu_type
= MIPS_FPU_DOUBLE
;
5478 else if (arches
!= NULL
)
5479 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5481 fpu_type
= MIPS_FPU_DOUBLE
;
5483 fprintf_unfiltered (gdb_stdlog
,
5484 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5486 /* Check for blatant incompatibilities. */
5488 /* If we have only 32-bit registers, then we can't debug a 64-bit
5490 if (info
.target_desc
5491 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5492 && mips_abi
!= MIPS_ABI_EABI32
5493 && mips_abi
!= MIPS_ABI_O32
)
5495 if (tdesc_data
!= NULL
)
5496 tdesc_data_cleanup (tdesc_data
);
5500 /* try to find a pre-existing architecture */
5501 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5503 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5505 /* MIPS needs to be pedantic about which ABI the object is
5507 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5509 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5511 /* Need to be pedantic about which register virtual size is
5513 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5514 != mips64_transfers_32bit_regs_p
)
5516 /* Be pedantic about which FPU is selected. */
5517 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5520 if (tdesc_data
!= NULL
)
5521 tdesc_data_cleanup (tdesc_data
);
5522 return arches
->gdbarch
;
5525 /* Need a new architecture. Fill in a target specific vector. */
5526 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5527 gdbarch
= gdbarch_alloc (&info
, tdep
);
5528 tdep
->elf_flags
= elf_flags
;
5529 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5530 tdep
->found_abi
= found_abi
;
5531 tdep
->mips_abi
= mips_abi
;
5532 tdep
->mips_fpu_type
= fpu_type
;
5533 tdep
->register_size_valid_p
= 0;
5534 tdep
->register_size
= 0;
5536 if (info
.target_desc
)
5538 /* Some useful properties can be inferred from the target. */
5539 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5541 tdep
->register_size_valid_p
= 1;
5542 tdep
->register_size
= 4;
5544 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5546 tdep
->register_size_valid_p
= 1;
5547 tdep
->register_size
= 8;
5551 /* Initially set everything according to the default ABI/ISA. */
5552 set_gdbarch_short_bit (gdbarch
, 16);
5553 set_gdbarch_int_bit (gdbarch
, 32);
5554 set_gdbarch_float_bit (gdbarch
, 32);
5555 set_gdbarch_double_bit (gdbarch
, 64);
5556 set_gdbarch_long_double_bit (gdbarch
, 64);
5557 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5558 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5559 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5561 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5562 mips_elf_make_msymbol_special
);
5564 /* Fill in the OS dependant register numbers and names. */
5566 const char **reg_names
;
5567 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5568 struct mips_regnum
);
5569 if (tdesc_has_registers (info
.target_desc
))
5571 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5572 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5573 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5574 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5575 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5576 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5577 regnum
->fp_control_status
= 70;
5578 regnum
->fp_implementation_revision
= 71;
5579 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5582 else if (info
.osabi
== GDB_OSABI_IRIX
)
5587 regnum
->badvaddr
= 66;
5590 regnum
->fp_control_status
= 69;
5591 regnum
->fp_implementation_revision
= 70;
5593 reg_names
= mips_irix_reg_names
;
5597 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5598 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5599 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5600 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5601 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5602 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5603 regnum
->fp_control_status
= 70;
5604 regnum
->fp_implementation_revision
= 71;
5606 if (info
.bfd_arch_info
!= NULL
5607 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5608 reg_names
= mips_tx39_reg_names
;
5610 reg_names
= mips_generic_reg_names
;
5612 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5613 replaced by read_pc? */
5614 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5615 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5616 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5617 set_gdbarch_num_regs (gdbarch
, num_regs
);
5618 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5619 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5620 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
5621 tdep
->mips_processor_reg_names
= reg_names
;
5622 tdep
->regnum
= regnum
;
5628 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5629 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5630 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5631 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5632 tdep
->default_mask_address_p
= 0;
5633 set_gdbarch_long_bit (gdbarch
, 32);
5634 set_gdbarch_ptr_bit (gdbarch
, 32);
5635 set_gdbarch_long_long_bit (gdbarch
, 64);
5638 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5639 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5640 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5641 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5642 tdep
->default_mask_address_p
= 0;
5643 set_gdbarch_long_bit (gdbarch
, 32);
5644 set_gdbarch_ptr_bit (gdbarch
, 32);
5645 set_gdbarch_long_long_bit (gdbarch
, 64);
5647 case MIPS_ABI_EABI32
:
5648 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5649 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5650 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5651 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5652 tdep
->default_mask_address_p
= 0;
5653 set_gdbarch_long_bit (gdbarch
, 32);
5654 set_gdbarch_ptr_bit (gdbarch
, 32);
5655 set_gdbarch_long_long_bit (gdbarch
, 64);
5657 case MIPS_ABI_EABI64
:
5658 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5659 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5660 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5661 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5662 tdep
->default_mask_address_p
= 0;
5663 set_gdbarch_long_bit (gdbarch
, 64);
5664 set_gdbarch_ptr_bit (gdbarch
, 64);
5665 set_gdbarch_long_long_bit (gdbarch
, 64);
5668 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5669 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5670 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5671 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5672 tdep
->default_mask_address_p
= 0;
5673 set_gdbarch_long_bit (gdbarch
, 32);
5674 set_gdbarch_ptr_bit (gdbarch
, 32);
5675 set_gdbarch_long_long_bit (gdbarch
, 64);
5676 set_gdbarch_long_double_bit (gdbarch
, 128);
5677 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5680 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5681 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5682 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5683 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5684 tdep
->default_mask_address_p
= 0;
5685 set_gdbarch_long_bit (gdbarch
, 64);
5686 set_gdbarch_ptr_bit (gdbarch
, 64);
5687 set_gdbarch_long_long_bit (gdbarch
, 64);
5688 set_gdbarch_long_double_bit (gdbarch
, 128);
5689 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5692 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5695 /* GCC creates a pseudo-section whose name specifies the size of
5696 longs, since -mlong32 or -mlong64 may be used independent of
5697 other options. How those options affect pointer sizes is ABI and
5698 architecture dependent, so use them to override the default sizes
5699 set by the ABI. This table shows the relationship between ABI,
5700 -mlongXX, and size of pointers:
5702 ABI -mlongXX ptr bits
5703 --- -------- --------
5717 Note that for o32 and eabi32, pointers are always 32 bits
5718 regardless of any -mlongXX option. For all others, pointers and
5719 longs are the same, as set by -mlongXX or set by defaults.
5722 if (info
.abfd
!= NULL
)
5726 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5729 set_gdbarch_long_bit (gdbarch
, long_bit
);
5733 case MIPS_ABI_EABI32
:
5738 case MIPS_ABI_EABI64
:
5739 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5742 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5747 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5748 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5751 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5752 flag in object files because to do so would make it impossible to
5753 link with libraries compiled without "-gp32". This is
5754 unnecessarily restrictive.
5756 We could solve this problem by adding "-gp32" multilibs to gcc,
5757 but to set this flag before gcc is built with such multilibs will
5758 break too many systems.''
5760 But even more unhelpfully, the default linker output target for
5761 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5762 for 64-bit programs - you need to change the ABI to change this,
5763 and not all gcc targets support that currently. Therefore using
5764 this flag to detect 32-bit mode would do the wrong thing given
5765 the current gcc - it would make GDB treat these 64-bit programs
5766 as 32-bit programs by default. */
5768 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5769 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5771 /* Add/remove bits from an address. The MIPS needs be careful to
5772 ensure that all 32 bit addresses are sign extended to 64 bits. */
5773 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5775 /* Unwind the frame. */
5776 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5777 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5778 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
5780 /* Map debug register numbers onto internal register numbers. */
5781 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5782 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5783 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5784 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5785 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5786 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5788 /* MIPS version of CALL_DUMMY */
5790 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5791 replaced by a command, and all targets will default to on stack
5792 (regardless of the stack's execute status). */
5793 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5794 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5796 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5797 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5798 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5800 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5801 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5803 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5805 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
5807 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5808 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5809 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5811 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5813 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5815 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5817 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5818 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5819 need to all be folded into the target vector. Since they are
5820 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5821 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5823 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5825 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5827 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5829 /* Virtual tables. */
5830 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5832 mips_register_g_packet_guesses (gdbarch
);
5834 /* Hook in OS ABI-specific overrides, if they have been registered. */
5835 info
.tdep_info
= (void *) tdesc_data
;
5836 gdbarch_init_osabi (info
, gdbarch
);
5838 /* Unwind the frame. */
5839 dwarf2_append_unwinders (gdbarch
);
5840 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
5841 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
5842 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
5843 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
5844 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5845 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5846 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5850 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
5851 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
5853 /* Override the normal target description methods to handle our
5854 dual real and pseudo registers. */
5855 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5856 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
5858 num_regs
= gdbarch_num_regs (gdbarch
);
5859 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5860 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
5861 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5864 /* Add ABI-specific aliases for the registers. */
5865 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
5866 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
5867 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
5868 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
5870 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
5871 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
5872 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
5874 /* Add some other standard aliases. */
5875 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
5876 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
5877 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
5883 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5885 struct gdbarch_info info
;
5887 /* Force the architecture to update, and (if it's a MIPS architecture)
5888 mips_gdbarch_init will take care of the rest. */
5889 gdbarch_info_init (&info
);
5890 gdbarch_update_p (info
);
5893 /* Print out which MIPS ABI is in use. */
5896 show_mips_abi (struct ui_file
*file
,
5898 struct cmd_list_element
*ignored_cmd
,
5899 const char *ignored_value
)
5901 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5904 "The MIPS ABI is unknown because the current architecture "
5908 enum mips_abi global_abi
= global_mips_abi ();
5909 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5910 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5912 if (global_abi
== MIPS_ABI_UNKNOWN
)
5915 "The MIPS ABI is set automatically (currently \"%s\").\n",
5917 else if (global_abi
== actual_abi
)
5920 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5924 /* Probably shouldn't happen... */
5927 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5928 actual_abi_str
, mips_abi_strings
[global_abi
]);
5934 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
5936 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5940 int ef_mips_32bitmode
;
5941 /* Determine the ISA. */
5942 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5960 /* Determine the size of a pointer. */
5961 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5962 fprintf_unfiltered (file
,
5963 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5965 fprintf_unfiltered (file
,
5966 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5968 fprintf_unfiltered (file
,
5969 "mips_dump_tdep: ef_mips_arch = %d\n",
5971 fprintf_unfiltered (file
,
5972 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5973 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5974 fprintf_unfiltered (file
,
5975 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5976 mips_mask_address_p (tdep
),
5977 tdep
->default_mask_address_p
);
5979 fprintf_unfiltered (file
,
5980 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5981 MIPS_DEFAULT_FPU_TYPE
,
5982 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5983 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5984 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5986 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5987 fprintf_unfiltered (file
,
5988 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5990 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5991 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5992 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5996 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5999 _initialize_mips_tdep (void)
6001 static struct cmd_list_element
*mipsfpulist
= NULL
;
6002 struct cmd_list_element
*c
;
6004 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6005 if (MIPS_ABI_LAST
+ 1
6006 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6007 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6009 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6011 mips_pdr_data
= register_objfile_data ();
6013 /* Create feature sets with the appropriate properties. The values
6014 are not important. */
6015 mips_tdesc_gp32
= allocate_target_description ();
6016 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6018 mips_tdesc_gp64
= allocate_target_description ();
6019 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6021 /* Add root prefix command for all "set mips"/"show mips" commands */
6022 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6023 _("Various MIPS specific commands."),
6024 &setmipscmdlist
, "set mips ", 0, &setlist
);
6026 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6027 _("Various MIPS specific commands."),
6028 &showmipscmdlist
, "show mips ", 0, &showlist
);
6030 /* Allow the user to override the ABI. */
6031 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6032 &mips_abi_string
, _("\
6033 Set the MIPS ABI used by this program."), _("\
6034 Show the MIPS ABI used by this program."), _("\
6035 This option can be set to one of:\n\
6036 auto - the default ABI associated with the current binary\n\
6045 &setmipscmdlist
, &showmipscmdlist
);
6047 /* Let the user turn off floating point and set the fence post for
6048 heuristic_proc_start. */
6050 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6051 _("Set use of MIPS floating-point coprocessor."),
6052 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6053 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6054 _("Select single-precision MIPS floating-point coprocessor."),
6056 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6057 _("Select double-precision MIPS floating-point coprocessor."),
6059 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6060 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6061 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6062 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6063 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6064 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6065 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6066 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6067 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6068 _("Select MIPS floating-point coprocessor automatically."),
6070 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6071 _("Show current use of MIPS floating-point coprocessor target."),
6074 /* We really would like to have both "0" and "unlimited" work, but
6075 command.c doesn't deal with that. So make it a var_zinteger
6076 because the user can always use "999999" or some such for unlimited. */
6077 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6078 &heuristic_fence_post
, _("\
6079 Set the distance searched for the start of a function."), _("\
6080 Show the distance searched for the start of a function."), _("\
6081 If you are debugging a stripped executable, GDB needs to search through the\n\
6082 program for the start of a function. This command sets the distance of the\n\
6083 search. The only need to set it is when debugging a stripped executable."),
6084 reinit_frame_cache_sfunc
,
6085 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
6086 &setlist
, &showlist
);
6088 /* Allow the user to control whether the upper bits of 64-bit
6089 addresses should be zeroed. */
6090 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6091 &mask_address_var
, _("\
6092 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6093 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6094 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6095 allow GDB to determine the correct value."),
6096 NULL
, show_mask_address
,
6097 &setmipscmdlist
, &showmipscmdlist
);
6099 /* Allow the user to control the size of 32 bit registers within the
6100 raw remote packet. */
6101 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6102 &mips64_transfers_32bit_regs_p
, _("\
6103 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6105 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6107 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6108 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6109 64 bits for others. Use \"off\" to disable compatibility mode"),
6110 set_mips64_transfers_32bit_regs
,
6111 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6112 &setlist
, &showlist
);
6114 /* Debug this files internals. */
6115 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6117 Set mips debugging."), _("\
6118 Show mips debugging."), _("\
6119 When non-zero, mips specific debugging is enabled."),
6121 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
6122 &setdebuglist
, &showdebuglist
);