1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
47 #include "frame-unwind.h"
48 #include "frame-base.h"
49 #include "trad-frame.h"
51 #include "floatformat.h"
53 #include "target-descriptions.h"
54 #include "dwarf2-frame.h"
55 #include "user-regs.h"
60 static const struct objfile_data
*mips_pdr_data
;
62 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
64 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
66 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
67 static int mips16_instruction_has_delay_slot (unsigned short inst
,
70 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
73 CORE_ADDR addr
, int mustbe32
);
74 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
75 CORE_ADDR addr
, int mustbe32
);
77 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
78 struct frame_info
*, const char *);
80 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
81 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
82 #define ST0_FR (1 << 26)
84 /* The sizes of floating point registers. */
88 MIPS_FPU_SINGLE_REGSIZE
= 4,
89 MIPS_FPU_DOUBLE_REGSIZE
= 8
98 static const char *mips_abi_string
;
100 static const char *const mips_abi_strings
[] = {
111 /* Enum describing the different kinds of breakpoints. */
113 enum mips_breakpoint_kind
115 /* 16-bit MIPS16 mode breakpoint. */
116 MIPS_BP_KIND_MIPS16
= 2,
118 /* 16-bit microMIPS mode breakpoint. */
119 MIPS_BP_KIND_MICROMIPS16
= 3,
121 /* 32-bit standard MIPS mode breakpoint. */
122 MIPS_BP_KIND_MIPS32
= 4,
124 /* 32-bit microMIPS mode breakpoint. */
125 MIPS_BP_KIND_MICROMIPS32
= 5,
128 /* For backwards compatibility we default to MIPS16. This flag is
129 overridden as soon as unambiguous ELF file flags tell us the
130 compressed ISA encoding used. */
131 static const char mips_compression_mips16
[] = "mips16";
132 static const char mips_compression_micromips
[] = "micromips";
133 static const char *const mips_compression_strings
[] =
135 mips_compression_mips16
,
136 mips_compression_micromips
,
140 static const char *mips_compression_string
= mips_compression_mips16
;
142 /* The standard register names, and all the valid aliases for them. */
143 struct register_alias
149 /* Aliases for o32 and most other ABIs. */
150 const struct register_alias mips_o32_aliases
[] = {
157 /* Aliases for n32 and n64. */
158 const struct register_alias mips_n32_n64_aliases
[] = {
165 /* Aliases for ABI-independent registers. */
166 const struct register_alias mips_register_aliases
[] = {
167 /* The architecture manuals specify these ABI-independent names for
169 #define R(n) { "r" #n, n }
170 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
171 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
172 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
173 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
176 /* k0 and k1 are sometimes called these instead (for "kernel
181 /* This is the traditional GDB name for the CP0 status register. */
182 { "sr", MIPS_PS_REGNUM
},
184 /* This is the traditional GDB name for the CP0 BadVAddr register. */
185 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
187 /* This is the traditional GDB name for the FCSR. */
188 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
191 const struct register_alias mips_numeric_register_aliases
[] = {
192 #define R(n) { #n, n }
193 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
194 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
195 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
196 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
200 #ifndef MIPS_DEFAULT_FPU_TYPE
201 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
203 static int mips_fpu_type_auto
= 1;
204 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
206 static unsigned int mips_debug
= 0;
208 /* Properties (for struct target_desc) describing the g/G packet
210 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
211 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
213 struct target_desc
*mips_tdesc_gp32
;
214 struct target_desc
*mips_tdesc_gp64
;
216 const struct mips_regnum
*
217 mips_regnum (struct gdbarch
*gdbarch
)
219 return gdbarch_tdep (gdbarch
)->regnum
;
223 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
225 return mips_regnum (gdbarch
)->fp0
+ 12;
228 /* Return 1 if REGNUM refers to a floating-point general register, raw
229 or cooked. Otherwise return 0. */
232 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
234 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
236 return (rawnum
>= mips_regnum (gdbarch
)->fp0
237 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
240 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
242 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
244 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
245 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
247 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
248 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
250 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
252 /* Return the MIPS ABI associated with GDBARCH. */
254 mips_abi (struct gdbarch
*gdbarch
)
256 return gdbarch_tdep (gdbarch
)->mips_abi
;
260 mips_isa_regsize (struct gdbarch
*gdbarch
)
262 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
264 /* If we know how big the registers are, use that size. */
265 if (tdep
->register_size_valid_p
)
266 return tdep
->register_size
;
268 /* Fall back to the previous behavior. */
269 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
270 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
273 /* Return the currently configured (or set) saved register size. */
276 mips_abi_regsize (struct gdbarch
*gdbarch
)
278 switch (mips_abi (gdbarch
))
280 case MIPS_ABI_EABI32
:
286 case MIPS_ABI_EABI64
:
288 case MIPS_ABI_UNKNOWN
:
291 internal_error (__FILE__
, __LINE__
, _("bad switch"));
295 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
296 are some functions to handle addresses associated with compressed
297 code including but not limited to testing, setting, or clearing
298 bit 0 of such addresses. */
300 /* Return one iff compressed code is the MIPS16 instruction set. */
303 is_mips16_isa (struct gdbarch
*gdbarch
)
305 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
308 /* Return one iff compressed code is the microMIPS instruction set. */
311 is_micromips_isa (struct gdbarch
*gdbarch
)
313 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
316 /* Return one iff ADDR denotes compressed code. */
319 is_compact_addr (CORE_ADDR addr
)
324 /* Return one iff ADDR denotes standard ISA code. */
327 is_mips_addr (CORE_ADDR addr
)
329 return !is_compact_addr (addr
);
332 /* Return one iff ADDR denotes MIPS16 code. */
335 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
337 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
340 /* Return one iff ADDR denotes microMIPS code. */
343 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
345 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
348 /* Strip the ISA (compression) bit off from ADDR. */
351 unmake_compact_addr (CORE_ADDR addr
)
353 return ((addr
) & ~(CORE_ADDR
) 1);
356 /* Add the ISA (compression) bit to ADDR. */
359 make_compact_addr (CORE_ADDR addr
)
361 return ((addr
) | (CORE_ADDR
) 1);
364 /* Extern version of unmake_compact_addr; we use a separate function
365 so that unmake_compact_addr can be inlined throughout this file. */
368 mips_unmake_compact_addr (CORE_ADDR addr
)
370 return unmake_compact_addr (addr
);
373 /* Functions for setting and testing a bit in a minimal symbol that
374 marks it as MIPS16 or microMIPS function. The MSB of the minimal
375 symbol's "info" field is used for this purpose.
377 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
378 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
379 one of the "special" bits in a minimal symbol to mark it accordingly.
380 The test checks an ELF-private flag that is valid for true function
381 symbols only; for synthetic symbols such as for PLT stubs that have
382 no ELF-private part at all the MIPS BFD backend arranges for this
383 information to be carried in the asymbol's udata field instead.
385 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
386 in a minimal symbol. */
389 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
391 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
392 unsigned char st_other
;
394 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
395 st_other
= elfsym
->internal_elf_sym
.st_other
;
396 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
397 st_other
= sym
->udata
.i
;
401 if (ELF_ST_IS_MICROMIPS (st_other
))
403 MSYMBOL_TARGET_FLAG_MICROMIPS (msym
) = 1;
404 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
406 else if (ELF_ST_IS_MIPS16 (st_other
))
408 MSYMBOL_TARGET_FLAG_MIPS16 (msym
) = 1;
409 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
413 /* Return one iff MSYM refers to standard ISA code. */
416 msymbol_is_mips (struct minimal_symbol
*msym
)
418 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
419 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
422 /* Return one iff MSYM refers to MIPS16 code. */
425 msymbol_is_mips16 (struct minimal_symbol
*msym
)
427 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
430 /* Return one iff MSYM refers to microMIPS code. */
433 msymbol_is_micromips (struct minimal_symbol
*msym
)
435 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
438 /* Set the ISA bit in the main symbol too, complementing the corresponding
439 minimal symbol setting and reflecting the run-time value of the symbol.
440 The need for comes from the ISA bit having been cleared as code in
441 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
442 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
443 of symbols referring to compressed code different in GDB to the values
444 used by actual code. That in turn makes them evaluate incorrectly in
445 expressions, producing results different to what the same expressions
446 yield when compiled into the program being debugged. */
449 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
451 if (SYMBOL_CLASS (sym
) == LOC_BLOCK
)
453 /* We are in symbol reading so it is OK to cast away constness. */
454 struct block
*block
= (struct block
*) SYMBOL_BLOCK_VALUE (sym
);
455 CORE_ADDR compact_block_start
;
456 struct bound_minimal_symbol msym
;
458 compact_block_start
= BLOCK_START (block
) | 1;
459 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
460 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
462 BLOCK_START (block
) = compact_block_start
;
467 /* XFER a value from the big/little/left end of the register.
468 Depending on the size of the value it might occupy the entire
469 register or just part of it. Make an allowance for this, aligning
470 things accordingly. */
473 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
474 int reg_num
, int length
,
475 enum bfd_endian endian
, gdb_byte
*in
,
476 const gdb_byte
*out
, int buf_offset
)
480 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
481 /* Need to transfer the left or right part of the register, based on
482 the targets byte order. */
486 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
488 case BFD_ENDIAN_LITTLE
:
491 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
495 internal_error (__FILE__
, __LINE__
, _("bad switch"));
498 fprintf_unfiltered (gdb_stderr
,
499 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
500 reg_num
, reg_offset
, buf_offset
, length
);
501 if (mips_debug
&& out
!= NULL
)
504 fprintf_unfiltered (gdb_stdlog
, "out ");
505 for (i
= 0; i
< length
; i
++)
506 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
509 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
512 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
514 if (mips_debug
&& in
!= NULL
)
517 fprintf_unfiltered (gdb_stdlog
, "in ");
518 for (i
= 0; i
< length
; i
++)
519 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
522 fprintf_unfiltered (gdb_stdlog
, "\n");
525 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
526 compatiblity mode. A return value of 1 means that we have
527 physical 64-bit registers, but should treat them as 32-bit registers. */
530 mips2_fp_compat (struct frame_info
*frame
)
532 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
533 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
535 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
539 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
540 in all the places we deal with FP registers. PR gdb/413. */
541 /* Otherwise check the FR bit in the status register - it controls
542 the FP compatiblity mode. If it is clear we are in compatibility
544 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
551 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
553 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
555 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
557 /* The list of available "set mips " and "show mips " commands. */
559 static struct cmd_list_element
*setmipscmdlist
= NULL
;
560 static struct cmd_list_element
*showmipscmdlist
= NULL
;
562 /* Integer registers 0 thru 31 are handled explicitly by
563 mips_register_name(). Processor specific registers 32 and above
564 are listed in the following tables. */
567 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
571 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
572 "sr", "lo", "hi", "bad", "cause", "pc",
573 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
574 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
575 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
576 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
580 /* Names of tx39 registers. */
582 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
583 "sr", "lo", "hi", "bad", "cause", "pc",
584 "", "", "", "", "", "", "", "",
585 "", "", "", "", "", "", "", "",
586 "", "", "", "", "", "", "", "",
587 "", "", "", "", "", "", "", "",
589 "", "", "", "", "", "", "", "",
590 "", "", "config", "cache", "debug", "depc", "epc",
593 /* Names of registers with Linux kernels. */
594 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
595 "sr", "lo", "hi", "bad", "cause", "pc",
596 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
597 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
598 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
599 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
604 /* Return the name of the register corresponding to REGNO. */
606 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
608 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
609 /* GPR names for all ABIs other than n32/n64. */
610 static char *mips_gpr_names
[] = {
611 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
612 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
613 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
614 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
617 /* GPR names for n32 and n64 ABIs. */
618 static char *mips_n32_n64_gpr_names
[] = {
619 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
620 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
621 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
622 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
625 enum mips_abi abi
= mips_abi (gdbarch
);
627 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
628 but then don't make the raw register names visible. This (upper)
629 range of user visible register numbers are the pseudo-registers.
631 This approach was adopted accommodate the following scenario:
632 It is possible to debug a 64-bit device using a 32-bit
633 programming model. In such instances, the raw registers are
634 configured to be 64-bits wide, while the pseudo registers are
635 configured to be 32-bits wide. The registers that the user
636 sees - the pseudo registers - match the users expectations
637 given the programming model being used. */
638 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
639 if (regno
< gdbarch_num_regs (gdbarch
))
642 /* The MIPS integer registers are always mapped from 0 to 31. The
643 names of the registers (which reflects the conventions regarding
644 register use) vary depending on the ABI. */
645 if (0 <= rawnum
&& rawnum
< 32)
647 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
648 return mips_n32_n64_gpr_names
[rawnum
];
650 return mips_gpr_names
[rawnum
];
652 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
653 return tdesc_register_name (gdbarch
, rawnum
);
654 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
656 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
657 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
658 return tdep
->mips_processor_reg_names
[rawnum
- 32];
662 internal_error (__FILE__
, __LINE__
,
663 _("mips_register_name: bad register number %d"), rawnum
);
666 /* Return the groups that a MIPS register can be categorised into. */
669 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
670 struct reggroup
*reggroup
)
675 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
676 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
677 if (reggroup
== all_reggroup
)
679 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
680 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
681 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
682 (gdbarch), as not all architectures are multi-arch. */
683 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
684 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
685 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
687 if (reggroup
== float_reggroup
)
688 return float_p
&& pseudo
;
689 if (reggroup
== vector_reggroup
)
690 return vector_p
&& pseudo
;
691 if (reggroup
== general_reggroup
)
692 return (!vector_p
&& !float_p
) && pseudo
;
693 /* Save the pseudo registers. Need to make certain that any code
694 extracting register values from a saved register cache also uses
696 if (reggroup
== save_reggroup
)
697 return raw_p
&& pseudo
;
698 /* Restore the same pseudo register. */
699 if (reggroup
== restore_reggroup
)
700 return raw_p
&& pseudo
;
704 /* Return the groups that a MIPS register can be categorised into.
705 This version is only used if we have a target description which
706 describes real registers (and their groups). */
709 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
710 struct reggroup
*reggroup
)
712 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
713 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
716 /* Only save, restore, and display the pseudo registers. Need to
717 make certain that any code extracting register values from a
718 saved register cache also uses pseudo registers.
720 Note: saving and restoring the pseudo registers is slightly
721 strange; if we have 64 bits, we should save and restore all
722 64 bits. But this is hard and has little benefit. */
726 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
730 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
733 /* Map the symbol table registers which live in the range [1 *
734 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
735 registers. Take care of alignment and size problems. */
737 static enum register_status
738 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
739 int cookednum
, gdb_byte
*buf
)
741 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
742 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
743 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
744 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
745 return regcache_raw_read (regcache
, rawnum
, buf
);
746 else if (register_size (gdbarch
, rawnum
) >
747 register_size (gdbarch
, cookednum
))
749 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
750 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
753 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
755 enum register_status status
;
757 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
758 if (status
== REG_VALID
)
759 store_signed_integer (buf
, 4, byte_order
, regval
);
764 internal_error (__FILE__
, __LINE__
, _("bad register size"));
768 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
769 struct regcache
*regcache
, int cookednum
,
772 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
773 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
774 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
775 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
776 regcache_raw_write (regcache
, rawnum
, buf
);
777 else if (register_size (gdbarch
, rawnum
) >
778 register_size (gdbarch
, cookednum
))
780 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
781 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
784 /* Sign extend the shortened version of the register prior
785 to placing it in the raw register. This is required for
786 some mips64 parts in order to avoid unpredictable behavior. */
787 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
788 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
789 regcache_raw_write_signed (regcache
, rawnum
, regval
);
793 internal_error (__FILE__
, __LINE__
, _("bad register size"));
797 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
798 struct agent_expr
*ax
, int reg
)
800 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
801 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
802 && reg
< 2 * gdbarch_num_regs (gdbarch
));
804 ax_reg_mask (ax
, rawnum
);
810 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
811 struct agent_expr
*ax
, int reg
)
813 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
814 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
815 && reg
< 2 * gdbarch_num_regs (gdbarch
));
816 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
820 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
822 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
823 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
826 ax_simple (ax
, aop_lsh
);
829 ax_simple (ax
, aop_rsh_signed
);
833 internal_error (__FILE__
, __LINE__
, _("bad register size"));
838 /* Table to translate 3-bit register field to actual register number. */
839 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
841 /* Heuristic_proc_start may hunt through the text section for a long
842 time across a 2400 baud serial line. Allows the user to limit this
845 static int heuristic_fence_post
= 0;
847 /* Number of bytes of storage in the actual machine representation for
848 register N. NOTE: This defines the pseudo register type so need to
849 rebuild the architecture vector. */
851 static int mips64_transfers_32bit_regs_p
= 0;
854 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
855 struct cmd_list_element
*c
)
857 struct gdbarch_info info
;
858 gdbarch_info_init (&info
);
859 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
860 instead of relying on globals. Doing that would let generic code
861 handle the search for this specific architecture. */
862 if (!gdbarch_update_p (info
))
864 mips64_transfers_32bit_regs_p
= 0;
865 error (_("32-bit compatibility mode not supported"));
869 /* Convert to/from a register and the corresponding memory value. */
871 /* This predicate tests for the case of an 8 byte floating point
872 value that is being transferred to or from a pair of floating point
873 registers each of which are (or are considered to be) only 4 bytes
876 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
879 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
880 && register_size (gdbarch
, regnum
) == 4
881 && mips_float_register_p (gdbarch
, regnum
)
882 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
885 /* This predicate tests for the case of a value of less than 8
886 bytes in width that is being transfered to or from an 8 byte
887 general purpose register. */
889 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
892 int num_regs
= gdbarch_num_regs (gdbarch
);
894 return (register_size (gdbarch
, regnum
) == 8
895 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
896 && TYPE_LENGTH (type
) < 8);
900 mips_convert_register_p (struct gdbarch
*gdbarch
,
901 int regnum
, struct type
*type
)
903 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
904 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
908 mips_register_to_value (struct frame_info
*frame
, int regnum
,
909 struct type
*type
, gdb_byte
*to
,
910 int *optimizedp
, int *unavailablep
)
912 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
914 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
916 get_frame_register (frame
, regnum
+ 0, to
+ 4);
917 get_frame_register (frame
, regnum
+ 1, to
+ 0);
919 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
920 optimizedp
, unavailablep
))
923 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
924 optimizedp
, unavailablep
))
926 *optimizedp
= *unavailablep
= 0;
929 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
931 int len
= TYPE_LENGTH (type
);
934 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
935 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
936 optimizedp
, unavailablep
))
939 *optimizedp
= *unavailablep
= 0;
944 internal_error (__FILE__
, __LINE__
,
945 _("mips_register_to_value: unrecognized case"));
950 mips_value_to_register (struct frame_info
*frame
, int regnum
,
951 struct type
*type
, const gdb_byte
*from
)
953 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
955 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
957 put_frame_register (frame
, regnum
+ 0, from
+ 4);
958 put_frame_register (frame
, regnum
+ 1, from
+ 0);
960 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
963 int len
= TYPE_LENGTH (type
);
965 /* Sign extend values, irrespective of type, that are stored to
966 a 64-bit general purpose register. (32-bit unsigned values
967 are stored as signed quantities within a 64-bit register.
968 When performing an operation, in compiled code, that combines
969 a 32-bit unsigned value with a signed 64-bit value, a type
970 conversion is first performed that zeroes out the high 32 bits.) */
971 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
974 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
976 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
977 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
978 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
982 if (from
[len
-1] & 0x80)
983 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
985 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
986 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
987 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
992 internal_error (__FILE__
, __LINE__
,
993 _("mips_value_to_register: unrecognized case"));
997 /* Return the GDB type object for the "standard" data type of data in
1000 static struct type
*
1001 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1003 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1004 if (mips_float_register_p (gdbarch
, regnum
))
1006 /* The floating-point registers raw, or cooked, always match
1007 mips_isa_regsize(), and also map 1:1, byte for byte. */
1008 if (mips_isa_regsize (gdbarch
) == 4)
1009 return builtin_type (gdbarch
)->builtin_float
;
1011 return builtin_type (gdbarch
)->builtin_double
;
1013 else if (regnum
< gdbarch_num_regs (gdbarch
))
1015 /* The raw or ISA registers. These are all sized according to
1017 if (mips_isa_regsize (gdbarch
) == 4)
1018 return builtin_type (gdbarch
)->builtin_int32
;
1020 return builtin_type (gdbarch
)->builtin_int64
;
1024 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1026 /* The cooked or ABI registers. These are sized according to
1027 the ABI (with a few complications). */
1028 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1029 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1030 return builtin_type (gdbarch
)->builtin_int32
;
1031 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1032 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1033 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1034 /* The pseudo/cooked view of the embedded registers is always
1035 32-bit. The raw view is handled below. */
1036 return builtin_type (gdbarch
)->builtin_int32
;
1037 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
1038 /* The target, while possibly using a 64-bit register buffer,
1039 is only transfering 32-bits of each integer register.
1040 Reflect this in the cooked/pseudo (ABI) register value. */
1041 return builtin_type (gdbarch
)->builtin_int32
;
1042 else if (mips_abi_regsize (gdbarch
) == 4)
1043 /* The ABI is restricted to 32-bit registers (the ISA could be
1045 return builtin_type (gdbarch
)->builtin_int32
;
1048 return builtin_type (gdbarch
)->builtin_int64
;
1052 /* Return the GDB type for the pseudo register REGNUM, which is the
1053 ABI-level view. This function is only called if there is a target
1054 description which includes registers, so we know precisely the
1055 types of hardware registers. */
1057 static struct type
*
1058 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1060 const int num_regs
= gdbarch_num_regs (gdbarch
);
1061 int rawnum
= regnum
% num_regs
;
1062 struct type
*rawtype
;
1064 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1066 /* Absent registers are still absent. */
1067 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1068 if (TYPE_LENGTH (rawtype
) == 0)
1071 /* Present the floating point registers however the hardware did;
1072 do not try to convert between FPU layouts. */
1073 if (mips_float_register_p (gdbarch
, rawnum
))
1076 /* Floating-point control registers are always 32-bit even though for
1077 backwards compatibility reasons 64-bit targets will transfer them
1078 as 64-bit quantities even if using XML descriptions. */
1079 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1080 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1081 return builtin_type (gdbarch
)->builtin_int32
;
1083 /* Use pointer types for registers if we can. For n32 we can not,
1084 since we do not have a 64-bit pointer type. */
1085 if (mips_abi_regsize (gdbarch
)
1086 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1088 if (rawnum
== MIPS_SP_REGNUM
1089 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1090 return builtin_type (gdbarch
)->builtin_data_ptr
;
1091 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1092 return builtin_type (gdbarch
)->builtin_func_ptr
;
1095 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1096 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1097 || rawnum
== mips_regnum (gdbarch
)->lo
1098 || rawnum
== mips_regnum (gdbarch
)->hi
1099 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1100 || rawnum
== mips_regnum (gdbarch
)->cause
1101 || rawnum
== mips_regnum (gdbarch
)->pc
1102 || (mips_regnum (gdbarch
)->dspacc
!= -1
1103 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1104 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1105 return builtin_type (gdbarch
)->builtin_int32
;
1107 /* The pseudo/cooked view of embedded registers is always
1108 32-bit, even if the target transfers 64-bit values for them.
1109 New targets relying on XML descriptions should only transfer
1110 the necessary 32 bits, but older versions of GDB expected 64,
1111 so allow the target to provide 64 bits without interfering
1112 with the displayed type. */
1113 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1114 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1115 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1116 return builtin_type (gdbarch
)->builtin_int32
;
1118 /* For all other registers, pass through the hardware type. */
1122 /* Should the upper word of 64-bit addresses be zeroed? */
1123 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1126 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1128 switch (mask_address_var
)
1130 case AUTO_BOOLEAN_TRUE
:
1132 case AUTO_BOOLEAN_FALSE
:
1135 case AUTO_BOOLEAN_AUTO
:
1136 return tdep
->default_mask_address_p
;
1138 internal_error (__FILE__
, __LINE__
,
1139 _("mips_mask_address_p: bad switch"));
1145 show_mask_address (struct ui_file
*file
, int from_tty
,
1146 struct cmd_list_element
*c
, const char *value
)
1148 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1150 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1151 switch (mask_address_var
)
1153 case AUTO_BOOLEAN_TRUE
:
1154 printf_filtered ("The 32 bit mips address mask is enabled\n");
1156 case AUTO_BOOLEAN_FALSE
:
1157 printf_filtered ("The 32 bit mips address mask is disabled\n");
1159 case AUTO_BOOLEAN_AUTO
:
1161 ("The 32 bit address mask is set automatically. Currently %s\n",
1162 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1165 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1170 /* Tell if the program counter value in MEMADDR is in a standard ISA
1174 mips_pc_is_mips (CORE_ADDR memaddr
)
1176 struct bound_minimal_symbol sym
;
1178 /* Flags indicating that this is a MIPS16 or microMIPS function is
1179 stored by elfread.c in the high bit of the info field. Use this
1180 to decide if the function is standard MIPS. Otherwise if bit 0
1181 of the address is clear, then this is a standard MIPS function. */
1182 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1184 return msymbol_is_mips (sym
.minsym
);
1186 return is_mips_addr (memaddr
);
1189 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1192 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1194 struct bound_minimal_symbol sym
;
1196 /* A flag indicating that this is a MIPS16 function is stored by
1197 elfread.c in the high bit of the info field. Use this to decide
1198 if the function is MIPS16. Otherwise if bit 0 of the address is
1199 set, then ELF file flags will tell if this is a MIPS16 function. */
1200 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1202 return msymbol_is_mips16 (sym
.minsym
);
1204 return is_mips16_addr (gdbarch
, memaddr
);
1207 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1210 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1212 struct bound_minimal_symbol sym
;
1214 /* A flag indicating that this is a microMIPS function is stored by
1215 elfread.c in the high bit of the info field. Use this to decide
1216 if the function is microMIPS. Otherwise if bit 0 of the address
1217 is set, then ELF file flags will tell if this is a microMIPS
1219 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1221 return msymbol_is_micromips (sym
.minsym
);
1223 return is_micromips_addr (gdbarch
, memaddr
);
1226 /* Tell the ISA type of the function the program counter value in MEMADDR
1229 static enum mips_isa
1230 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1232 struct bound_minimal_symbol sym
;
1234 /* A flag indicating that this is a MIPS16 or a microMIPS function
1235 is stored by elfread.c in the high bit of the info field. Use
1236 this to decide if the function is MIPS16 or microMIPS or normal
1237 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1238 flags will tell if this is a MIPS16 or a microMIPS function. */
1239 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1242 if (msymbol_is_micromips (sym
.minsym
))
1243 return ISA_MICROMIPS
;
1244 else if (msymbol_is_mips16 (sym
.minsym
))
1251 if (is_mips_addr (memaddr
))
1253 else if (is_micromips_addr (gdbarch
, memaddr
))
1254 return ISA_MICROMIPS
;
1260 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1261 The need for comes from the ISA bit having been cleared, making
1262 addresses in FDE, range records, etc. referring to compressed code
1263 different to those in line information, the symbol table and finally
1264 the PC register. That in turn confuses many operations. */
1267 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1269 pc
= unmake_compact_addr (pc
);
1270 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1273 /* Recalculate the line record requested so that the resulting PC has
1274 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1275 this adjustment comes from some records associated with compressed
1276 code having the ISA bit cleared, most notably at function prologue
1277 ends. The ISA bit is in this context retrieved from the minimal
1278 symbol covering the address requested, which in turn has been
1279 constructed from the binary's symbol table rather than DWARF-2
1280 information. The correct setting of the ISA bit is required for
1281 breakpoint addresses to correctly match against the stop PC.
1283 As line entries can specify relative address adjustments we need to
1284 keep track of the absolute value of the last line address recorded
1285 in line information, so that we can calculate the actual address to
1286 apply the ISA bit adjustment to. We use PC for this tracking and
1287 keep the original address there.
1289 As such relative address adjustments can be odd within compressed
1290 code we need to keep track of the last line address with the ISA
1291 bit adjustment applied too, as the original address may or may not
1292 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1293 the adjusted address there.
1295 For relative address adjustments we then use these variables to
1296 calculate the address intended by line information, which will be
1297 PC-relative, and return an updated adjustment carrying ISA bit
1298 information, which will be ADJ_PC-relative. For absolute address
1299 adjustments we just return the same address that we store in ADJ_PC
1302 As the first line entry can be relative to an implied address value
1303 of 0 we need to have the initial address set up that we store in PC
1304 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1305 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1308 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1310 static CORE_ADDR adj_pc
;
1311 static CORE_ADDR pc
;
1314 pc
= rel
? pc
+ addr
: addr
;
1315 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1316 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1321 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1323 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1324 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1325 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1326 static const char mips_str_call_stub
[] = "__call_stub_";
1327 static const char mips_str_fn_stub
[] = "__fn_stub_";
1329 /* This is used as a PIC thunk prefix. */
1331 static const char mips_str_pic
[] = ".pic.";
1333 /* Return non-zero if the PC is inside a call thunk (aka stub or
1334 trampoline) that should be treated as a temporary frame. */
1337 mips_in_frame_stub (CORE_ADDR pc
)
1339 CORE_ADDR start_addr
;
1342 /* Find the starting address of the function containing the PC. */
1343 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1346 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1347 if (startswith (name
, mips_str_mips16_call_stub
))
1349 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1350 if (startswith (name
, mips_str_call_stub
))
1352 /* If the PC is in __fn_stub_*, this is a call stub. */
1353 if (startswith (name
, mips_str_fn_stub
))
1356 return 0; /* Not a stub. */
1359 /* MIPS believes that the PC has a sign extended value. Perhaps the
1360 all registers should be sign extended for simplicity? */
1363 mips_read_pc (struct regcache
*regcache
)
1365 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1368 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1373 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1377 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1378 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1379 intermediate frames. In this case we can get the caller's address
1380 from $ra, or if $ra contains an address within a thunk as well, then
1381 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1382 and thus the caller's address is in $s2. */
1383 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1385 pc
= frame_unwind_register_signed
1386 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1387 if (mips_in_frame_stub (pc
))
1388 pc
= frame_unwind_register_signed
1389 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1395 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1397 return frame_unwind_register_signed
1398 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1401 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1402 dummy frame. The frame ID's base needs to match the TOS value
1403 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1406 static struct frame_id
1407 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1409 return frame_id_build
1410 (get_frame_register_signed (this_frame
,
1411 gdbarch_num_regs (gdbarch
)
1413 get_frame_pc (this_frame
));
1416 /* Implement the "write_pc" gdbarch method. */
1419 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1421 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1423 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1426 /* Fetch and return instruction from the specified location. Handle
1427 MIPS16/microMIPS as appropriate. */
1430 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1431 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1433 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1434 gdb_byte buf
[MIPS_INSN32_SIZE
];
1442 instlen
= MIPS_INSN16_SIZE
;
1443 addr
= unmake_compact_addr (addr
);
1446 instlen
= MIPS_INSN32_SIZE
;
1449 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1452 err
= target_read_memory (addr
, buf
, instlen
);
1458 memory_error (TARGET_XFER_E_IO
, addr
);
1461 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1464 /* These are the fields of 32 bit mips instructions. */
1465 #define mips32_op(x) (x >> 26)
1466 #define itype_op(x) (x >> 26)
1467 #define itype_rs(x) ((x >> 21) & 0x1f)
1468 #define itype_rt(x) ((x >> 16) & 0x1f)
1469 #define itype_immediate(x) (x & 0xffff)
1471 #define jtype_op(x) (x >> 26)
1472 #define jtype_target(x) (x & 0x03ffffff)
1474 #define rtype_op(x) (x >> 26)
1475 #define rtype_rs(x) ((x >> 21) & 0x1f)
1476 #define rtype_rt(x) ((x >> 16) & 0x1f)
1477 #define rtype_rd(x) ((x >> 11) & 0x1f)
1478 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1479 #define rtype_funct(x) (x & 0x3f)
1481 /* MicroMIPS instruction fields. */
1482 #define micromips_op(x) ((x) >> 10)
1484 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1485 bit and the size respectively of the field extracted. */
1486 #define b0s4_imm(x) ((x) & 0xf)
1487 #define b0s5_imm(x) ((x) & 0x1f)
1488 #define b0s5_reg(x) ((x) & 0x1f)
1489 #define b0s7_imm(x) ((x) & 0x7f)
1490 #define b0s10_imm(x) ((x) & 0x3ff)
1491 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1492 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1493 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1494 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1495 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1496 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1497 #define b6s4_op(x) (((x) >> 6) & 0xf)
1498 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1500 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1501 respectively of the field extracted. */
1502 #define b0s6_op(x) ((x) & 0x3f)
1503 #define b0s11_op(x) ((x) & 0x7ff)
1504 #define b0s12_imm(x) ((x) & 0xfff)
1505 #define b0s16_imm(x) ((x) & 0xffff)
1506 #define b0s26_imm(x) ((x) & 0x3ffffff)
1507 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1508 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1509 #define b12s4_op(x) (((x) >> 12) & 0xf)
1511 /* Return the size in bytes of the instruction INSN encoded in the ISA
1515 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1520 if ((micromips_op (insn
) & 0x4) == 0x4
1521 || (micromips_op (insn
) & 0x7) == 0x0)
1522 return 2 * MIPS_INSN16_SIZE
;
1524 return MIPS_INSN16_SIZE
;
1526 if ((insn
& 0xf800) == 0xf000)
1527 return 2 * MIPS_INSN16_SIZE
;
1529 return MIPS_INSN16_SIZE
;
1531 return MIPS_INSN32_SIZE
;
1533 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1537 mips32_relative_offset (ULONGEST inst
)
1539 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1542 /* Determine the address of the next instruction executed after the INST
1543 floating condition branch instruction at PC. COUNT specifies the
1544 number of the floating condition bits tested by the branch. */
1547 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1548 ULONGEST inst
, CORE_ADDR pc
, int count
)
1550 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1551 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1552 int tf
= itype_rt (inst
) & 1;
1553 int mask
= (1 << count
) - 1;
1558 /* No way to handle; it'll most likely trap anyway. */
1561 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1562 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1564 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1565 pc
+= mips32_relative_offset (inst
);
1572 /* Return nonzero if the gdbarch is an Octeon series. */
1575 is_octeon (struct gdbarch
*gdbarch
)
1577 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1579 return (info
->mach
== bfd_mach_mips_octeon
1580 || info
->mach
== bfd_mach_mips_octeonp
1581 || info
->mach
== bfd_mach_mips_octeon2
);
1584 /* Return true if the OP represents the Octeon's BBIT instruction. */
1587 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1589 if (!is_octeon (gdbarch
))
1591 /* BBIT0 is encoded as LWC2: 110 010. */
1592 /* BBIT032 is encoded as LDC2: 110 110. */
1593 /* BBIT1 is encoded as SWC2: 111 010. */
1594 /* BBIT132 is encoded as SDC2: 111 110. */
1595 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1601 /* Determine where to set a single step breakpoint while considering
1602 branch prediction. */
1605 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1607 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1610 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1611 op
= itype_op (inst
);
1612 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1616 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1627 goto greater_branch
;
1632 else if (op
== 17 && itype_rs (inst
) == 8)
1633 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1634 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1635 else if (op
== 17 && itype_rs (inst
) == 9
1636 && (itype_rt (inst
) & 2) == 0)
1637 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1638 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1639 else if (op
== 17 && itype_rs (inst
) == 10
1640 && (itype_rt (inst
) & 2) == 0)
1641 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1642 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1645 /* The new PC will be alternate mode. */
1649 reg
= jtype_target (inst
) << 2;
1650 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1651 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1653 else if (is_octeon_bbit_op (op
, gdbarch
))
1657 branch_if
= op
== 58 || op
== 62;
1658 bit
= itype_rt (inst
);
1660 /* Take into account the *32 instructions. */
1661 if (op
== 54 || op
== 62)
1664 if (((get_frame_register_signed (frame
,
1665 itype_rs (inst
)) >> bit
) & 1)
1667 pc
+= mips32_relative_offset (inst
) + 4;
1669 pc
+= 8; /* After the delay slot. */
1673 pc
+= 4; /* Not a branch, next instruction is easy. */
1676 { /* This gets way messy. */
1678 /* Further subdivide into SPECIAL, REGIMM and other. */
1679 switch (op
& 0x07) /* Extract bits 28,27,26. */
1681 case 0: /* SPECIAL */
1682 op
= rtype_funct (inst
);
1687 /* Set PC to that address. */
1688 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1690 case 12: /* SYSCALL */
1692 struct gdbarch_tdep
*tdep
;
1694 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1695 if (tdep
->syscall_next_pc
!= NULL
)
1696 pc
= tdep
->syscall_next_pc (frame
);
1705 break; /* end SPECIAL */
1706 case 1: /* REGIMM */
1708 op
= itype_rt (inst
); /* branch condition */
1713 case 16: /* BLTZAL */
1714 case 18: /* BLTZALL */
1716 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1717 pc
+= mips32_relative_offset (inst
) + 4;
1719 pc
+= 8; /* after the delay slot */
1723 case 17: /* BGEZAL */
1724 case 19: /* BGEZALL */
1725 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1726 pc
+= mips32_relative_offset (inst
) + 4;
1728 pc
+= 8; /* after the delay slot */
1730 case 0x1c: /* BPOSGE32 */
1731 case 0x1e: /* BPOSGE64 */
1733 if (itype_rs (inst
) == 0)
1735 unsigned int pos
= (op
& 2) ? 64 : 32;
1736 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1739 /* No way to handle; it'll most likely trap anyway. */
1742 if ((get_frame_register_unsigned (frame
,
1743 dspctl
) & 0x7f) >= pos
)
1744 pc
+= mips32_relative_offset (inst
);
1749 /* All of the other instructions in the REGIMM category */
1754 break; /* end REGIMM */
1759 reg
= jtype_target (inst
) << 2;
1760 /* Upper four bits get never changed... */
1761 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1764 case 4: /* BEQ, BEQL */
1766 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1767 get_frame_register_signed (frame
, itype_rt (inst
)))
1768 pc
+= mips32_relative_offset (inst
) + 4;
1772 case 5: /* BNE, BNEL */
1774 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1775 get_frame_register_signed (frame
, itype_rt (inst
)))
1776 pc
+= mips32_relative_offset (inst
) + 4;
1780 case 6: /* BLEZ, BLEZL */
1781 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1782 pc
+= mips32_relative_offset (inst
) + 4;
1788 greater_branch
: /* BGTZ, BGTZL */
1789 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1790 pc
+= mips32_relative_offset (inst
) + 4;
1797 } /* mips32_next_pc */
1799 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1803 micromips_relative_offset7 (ULONGEST insn
)
1805 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1808 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1812 micromips_relative_offset10 (ULONGEST insn
)
1814 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1817 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1821 micromips_relative_offset16 (ULONGEST insn
)
1823 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1826 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1829 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1833 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1834 return mips_insn_size (ISA_MICROMIPS
, insn
);
1837 /* Calculate the address of the next microMIPS instruction to execute
1838 after the INSN coprocessor 1 conditional branch instruction at the
1839 address PC. COUNT denotes the number of coprocessor condition bits
1840 examined by the branch. */
1843 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1844 ULONGEST insn
, CORE_ADDR pc
, int count
)
1846 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1847 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1848 int tf
= b5s5_op (insn
>> 16) & 1;
1849 int mask
= (1 << count
) - 1;
1854 /* No way to handle; it'll most likely trap anyway. */
1857 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1858 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1860 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1861 pc
+= micromips_relative_offset16 (insn
);
1863 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1868 /* Calculate the address of the next microMIPS instruction to execute
1869 after the instruction at the address PC. */
1872 micromips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1874 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1877 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1878 pc
+= MIPS_INSN16_SIZE
;
1879 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1881 /* 32-bit instructions. */
1882 case 2 * MIPS_INSN16_SIZE
:
1884 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1885 pc
+= MIPS_INSN16_SIZE
;
1886 switch (micromips_op (insn
>> 16))
1888 case 0x00: /* POOL32A: bits 000000 */
1889 if (b0s6_op (insn
) == 0x3c
1890 /* POOL32Axf: bits 000000 ... 111100 */
1891 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1892 /* JALR, JALR.HB: 000000 000x111100 111100 */
1893 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1894 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
>> 16));
1897 case 0x10: /* POOL32I: bits 010000 */
1898 switch (b5s5_op (insn
>> 16))
1900 case 0x00: /* BLTZ: bits 010000 00000 */
1901 case 0x01: /* BLTZAL: bits 010000 00001 */
1902 case 0x11: /* BLTZALS: bits 010000 10001 */
1903 if (get_frame_register_signed (frame
,
1904 b0s5_reg (insn
>> 16)) < 0)
1905 pc
+= micromips_relative_offset16 (insn
);
1907 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1910 case 0x02: /* BGEZ: bits 010000 00010 */
1911 case 0x03: /* BGEZAL: bits 010000 00011 */
1912 case 0x13: /* BGEZALS: bits 010000 10011 */
1913 if (get_frame_register_signed (frame
,
1914 b0s5_reg (insn
>> 16)) >= 0)
1915 pc
+= micromips_relative_offset16 (insn
);
1917 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1920 case 0x04: /* BLEZ: bits 010000 00100 */
1921 if (get_frame_register_signed (frame
,
1922 b0s5_reg (insn
>> 16)) <= 0)
1923 pc
+= micromips_relative_offset16 (insn
);
1925 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1928 case 0x05: /* BNEZC: bits 010000 00101 */
1929 if (get_frame_register_signed (frame
,
1930 b0s5_reg (insn
>> 16)) != 0)
1931 pc
+= micromips_relative_offset16 (insn
);
1934 case 0x06: /* BGTZ: bits 010000 00110 */
1935 if (get_frame_register_signed (frame
,
1936 b0s5_reg (insn
>> 16)) > 0)
1937 pc
+= micromips_relative_offset16 (insn
);
1939 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1942 case 0x07: /* BEQZC: bits 010000 00111 */
1943 if (get_frame_register_signed (frame
,
1944 b0s5_reg (insn
>> 16)) == 0)
1945 pc
+= micromips_relative_offset16 (insn
);
1948 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1949 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1950 if (((insn
>> 16) & 0x3) == 0x0)
1951 /* BC2F, BC2T: don't know how to handle these. */
1955 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1956 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1958 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1959 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1962 /* No way to handle; it'll most likely trap anyway. */
1965 if ((get_frame_register_unsigned (frame
,
1966 dspctl
) & 0x7f) >= pos
)
1967 pc
+= micromips_relative_offset16 (insn
);
1969 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1973 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1974 /* BC1ANY2F: bits 010000 11100 xxx01 */
1975 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1976 /* BC1ANY2T: bits 010000 11101 xxx01 */
1977 if (((insn
>> 16) & 0x2) == 0x0)
1978 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
,
1979 ((insn
>> 16) & 0x1) + 1);
1982 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1983 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1984 if (((insn
>> 16) & 0x3) == 0x1)
1985 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
, 4);
1990 case 0x1d: /* JALS: bits 011101 */
1991 case 0x35: /* J: bits 110101 */
1992 case 0x3d: /* JAL: bits 111101 */
1993 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
1996 case 0x25: /* BEQ: bits 100101 */
1997 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1998 == get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1999 pc
+= micromips_relative_offset16 (insn
);
2001 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2004 case 0x2d: /* BNE: bits 101101 */
2005 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
2006 != get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
2007 pc
+= micromips_relative_offset16 (insn
);
2009 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2012 case 0x3c: /* JALX: bits 111100 */
2013 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2018 /* 16-bit instructions. */
2019 case MIPS_INSN16_SIZE
:
2020 switch (micromips_op (insn
))
2022 case 0x11: /* POOL16C: bits 010001 */
2023 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2024 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2025 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
));
2026 else if (b5s5_op (insn
) == 0x18)
2027 /* JRADDIUSP: bits 010001 11000 */
2028 pc
= get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
2031 case 0x23: /* BEQZ16: bits 100011 */
2033 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2035 if (get_frame_register_signed (frame
, rs
) == 0)
2036 pc
+= micromips_relative_offset7 (insn
);
2038 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2042 case 0x2b: /* BNEZ16: bits 101011 */
2044 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2046 if (get_frame_register_signed (frame
, rs
) != 0)
2047 pc
+= micromips_relative_offset7 (insn
);
2049 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2053 case 0x33: /* B16: bits 110011 */
2054 pc
+= micromips_relative_offset10 (insn
);
2063 /* Decoding the next place to set a breakpoint is irregular for the
2064 mips 16 variant, but fortunately, there fewer instructions. We have
2065 to cope ith extensions for 16 bit instructions and a pair of actual
2066 32 bit instructions. We dont want to set a single step instruction
2067 on the extend instruction either. */
2069 /* Lots of mips16 instruction formats */
2070 /* Predicting jumps requires itype,ritype,i8type
2071 and their extensions extItype,extritype,extI8type. */
2072 enum mips16_inst_fmts
2074 itype
, /* 0 immediate 5,10 */
2075 ritype
, /* 1 5,3,8 */
2076 rrtype
, /* 2 5,3,3,5 */
2077 rritype
, /* 3 5,3,3,5 */
2078 rrrtype
, /* 4 5,3,3,3,2 */
2079 rriatype
, /* 5 5,3,3,1,4 */
2080 shifttype
, /* 6 5,3,3,3,2 */
2081 i8type
, /* 7 5,3,8 */
2082 i8movtype
, /* 8 5,3,3,5 */
2083 i8mov32rtype
, /* 9 5,3,5,3 */
2084 i64type
, /* 10 5,3,8 */
2085 ri64type
, /* 11 5,3,3,5 */
2086 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2087 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2088 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2089 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2090 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2091 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2092 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2093 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2094 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2095 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2097 /* I am heaping all the fields of the formats into one structure and
2098 then, only the fields which are involved in instruction extension. */
2102 unsigned int regx
; /* Function in i8 type. */
2107 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2108 for the bits which make up the immediate extension. */
2111 extended_offset (unsigned int extension
)
2115 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2117 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2119 value
|= extension
& 0x1f; /* Extract 4:0. */
2124 /* Only call this function if you know that this is an extendable
2125 instruction. It won't malfunction, but why make excess remote memory
2126 references? If the immediate operands get sign extended or something,
2127 do it after the extension is performed. */
2128 /* FIXME: Every one of these cases needs to worry about sign extension
2129 when the offset is to be used in relative addressing. */
2132 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2134 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2137 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2138 target_read_memory (pc
, buf
, 2);
2139 return extract_unsigned_integer (buf
, 2, byte_order
);
2143 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2144 unsigned int extension
,
2146 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2151 switch (insn_format
)
2158 value
= extended_offset ((extension
<< 16) | inst
);
2159 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2163 value
= inst
& 0x7ff;
2164 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2173 { /* A register identifier and an offset. */
2174 /* Most of the fields are the same as I type but the
2175 immediate value is of a different length. */
2179 value
= extended_offset ((extension
<< 16) | inst
);
2180 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2184 value
= inst
& 0xff; /* 8 bits */
2185 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2188 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2194 unsigned long value
;
2195 unsigned int nexthalf
;
2196 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2197 value
= value
<< 16;
2198 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2199 /* Low bit still set. */
2207 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2209 upk
->offset
= offset
;
2215 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2216 and having a signed 16-bit OFFSET. */
2219 add_offset_16 (CORE_ADDR pc
, int offset
)
2221 return pc
+ (offset
<< 1) + 2;
2225 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
2226 unsigned int extension
, unsigned int insn
)
2228 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2229 int op
= (insn
>> 11);
2232 case 2: /* Branch */
2234 struct upk_mips16 upk
;
2235 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2236 pc
= add_offset_16 (pc
, upk
.offset
);
2239 case 3: /* JAL , JALX - Watch out, these are 32 bit
2242 struct upk_mips16 upk
;
2243 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2244 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2245 if ((insn
>> 10) & 0x01) /* Exchange mode */
2246 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2253 struct upk_mips16 upk
;
2255 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2256 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2258 pc
= add_offset_16 (pc
, upk
.offset
);
2265 struct upk_mips16 upk
;
2267 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2268 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2270 pc
= add_offset_16 (pc
, upk
.offset
);
2275 case 12: /* I8 Formats btez btnez */
2277 struct upk_mips16 upk
;
2279 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2280 /* upk.regx contains the opcode */
2281 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
2282 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2283 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2284 pc
= add_offset_16 (pc
, upk
.offset
);
2289 case 29: /* RR Formats JR, JALR, JALR-RA */
2291 struct upk_mips16 upk
;
2292 /* upk.fmt = rrtype; */
2297 upk
.regx
= (insn
>> 8) & 0x07;
2298 upk
.regy
= (insn
>> 5) & 0x07;
2299 if ((upk
.regy
& 1) == 0)
2300 reg
= mips_reg3_to_reg
[upk
.regx
];
2302 reg
= 31; /* Function return instruction. */
2303 pc
= get_frame_register_signed (frame
, reg
);
2310 /* This is an instruction extension. Fetch the real instruction
2311 (which follows the extension) and decode things based on
2315 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
2316 fetch_mips_16 (gdbarch
, pc
));
2329 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2331 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2332 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2333 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
2336 /* The mips_next_pc function supports single_step when the remote
2337 target monitor or stub is not developed enough to do a single_step.
2338 It works by decoding the current instruction and predicting where a
2339 branch will go. This isn't hard because all the data is available.
2340 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2342 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2344 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2346 if (mips_pc_is_mips16 (gdbarch
, pc
))
2347 return mips16_next_pc (frame
, pc
);
2348 else if (mips_pc_is_micromips (gdbarch
, pc
))
2349 return micromips_next_pc (frame
, pc
);
2351 return mips32_next_pc (frame
, pc
);
2354 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2358 mips16_instruction_is_compact_branch (unsigned short insn
)
2360 switch (insn
& 0xf800)
2363 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2365 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2366 case 0x2800: /* BNEZ */
2367 case 0x2000: /* BEQZ */
2368 case 0x1000: /* B */
2375 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2379 micromips_instruction_is_compact_branch (unsigned short insn
)
2381 switch (micromips_op (insn
))
2383 case 0x11: /* POOL16C: bits 010001 */
2384 return (b5s5_op (insn
) == 0x18
2385 /* JRADDIUSP: bits 010001 11000 */
2386 || b5s5_op (insn
) == 0xd);
2387 /* JRC: bits 010011 01101 */
2388 case 0x10: /* POOL32I: bits 010000 */
2389 return (b5s5_op (insn
) & 0x1d) == 0x5;
2390 /* BEQZC/BNEZC: bits 010000 001x1 */
2396 struct mips_frame_cache
2399 struct trad_frame_saved_reg
*saved_regs
;
2402 /* Set a register's saved stack address in temp_saved_regs. If an
2403 address has already been set for this register, do nothing; this
2404 way we will only recognize the first save of a given register in a
2407 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2408 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2409 Strictly speaking, only the second range is used as it is only second
2410 range (the ABI instead of ISA registers) that comes into play when finding
2411 saved registers in a frame. */
2414 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2415 int regnum
, CORE_ADDR offset
)
2417 if (this_cache
!= NULL
2418 && this_cache
->saved_regs
[regnum
].addr
== -1)
2420 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2422 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2428 /* Fetch the immediate value from a MIPS16 instruction.
2429 If the previous instruction was an EXTEND, use it to extend
2430 the upper bits of the immediate value. This is a helper function
2431 for mips16_scan_prologue. */
2434 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2435 unsigned short inst
, /* current instruction */
2436 int nbits
, /* number of bits in imm field */
2437 int scale
, /* scale factor to be applied to imm */
2438 int is_signed
) /* is the imm field signed? */
2442 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2444 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2445 if (offset
& 0x8000) /* check for negative extend */
2446 offset
= 0 - (0x10000 - (offset
& 0xffff));
2447 return offset
| (inst
& 0x1f);
2451 int max_imm
= 1 << nbits
;
2452 int mask
= max_imm
- 1;
2453 int sign_bit
= max_imm
>> 1;
2455 offset
= inst
& mask
;
2456 if (is_signed
&& (offset
& sign_bit
))
2457 offset
= 0 - (max_imm
- offset
);
2458 return offset
* scale
;
2463 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2464 the associated FRAME_CACHE if not null.
2465 Return the address of the first instruction past the prologue. */
2468 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2469 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2470 struct frame_info
*this_frame
,
2471 struct mips_frame_cache
*this_cache
)
2473 int prev_non_prologue_insn
= 0;
2474 int this_non_prologue_insn
;
2475 int non_prologue_insns
= 0;
2478 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2480 long frame_offset
= 0; /* Size of stack frame. */
2481 long frame_adjust
= 0; /* Offset of FP from SP. */
2482 int frame_reg
= MIPS_SP_REGNUM
;
2483 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2484 unsigned inst
= 0; /* current instruction */
2485 unsigned entry_inst
= 0; /* the entry instruction */
2486 unsigned save_inst
= 0; /* the save instruction */
2487 int prev_delay_slot
= 0;
2491 int extend_bytes
= 0;
2492 int prev_extend_bytes
= 0;
2493 CORE_ADDR end_prologue_addr
;
2495 /* Can be called when there's no process, and hence when there's no
2497 if (this_frame
!= NULL
)
2498 sp
= get_frame_register_signed (this_frame
,
2499 gdbarch_num_regs (gdbarch
)
2504 if (limit_pc
> start_pc
+ 200)
2505 limit_pc
= start_pc
+ 200;
2508 /* Permit at most one non-prologue non-control-transfer instruction
2509 in the middle which may have been reordered by the compiler for
2511 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2513 this_non_prologue_insn
= 0;
2516 /* Save the previous instruction. If it's an EXTEND, we'll extract
2517 the immediate offset extension from it in mips16_get_imm. */
2520 /* Fetch and decode the instruction. */
2521 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2524 /* Normally we ignore extend instructions. However, if it is
2525 not followed by a valid prologue instruction, then this
2526 instruction is not part of the prologue either. We must
2527 remember in this case to adjust the end_prologue_addr back
2529 if ((inst
& 0xf800) == 0xf000) /* extend */
2531 extend_bytes
= MIPS_INSN16_SIZE
;
2535 prev_extend_bytes
= extend_bytes
;
2538 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2539 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2541 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2542 if (offset
< 0) /* Negative stack adjustment? */
2543 frame_offset
-= offset
;
2545 /* Exit loop if a positive stack adjustment is found, which
2546 usually means that the stack cleanup code in the function
2547 epilogue is reached. */
2550 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2552 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2553 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2554 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2556 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2558 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2559 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2560 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2562 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2564 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2565 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2567 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2569 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2570 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2572 else if (inst
== 0x673d) /* move $s1, $sp */
2577 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2579 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2580 frame_addr
= sp
+ offset
;
2582 frame_adjust
= offset
;
2584 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2586 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2587 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2588 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2590 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2592 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2593 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2594 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2596 else if ((inst
& 0xf81f) == 0xe809
2597 && (inst
& 0x700) != 0x700) /* entry */
2598 entry_inst
= inst
; /* Save for later processing. */
2599 else if ((inst
& 0xff80) == 0x6480) /* save */
2601 save_inst
= inst
; /* Save for later processing. */
2602 if (prev_extend_bytes
) /* extend */
2603 save_inst
|= prev_inst
<< 16;
2605 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2607 /* This instruction is part of the prologue, but we don't
2608 need to do anything special to handle it. */
2610 else if (mips16_instruction_has_delay_slot (inst
, 0))
2611 /* JAL/JALR/JALX/JR */
2613 /* The instruction in the delay slot can be a part
2614 of the prologue, so move forward once more. */
2616 if (mips16_instruction_has_delay_slot (inst
, 1))
2619 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2620 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2625 this_non_prologue_insn
= 1;
2628 non_prologue_insns
+= this_non_prologue_insn
;
2630 /* A jump or branch, or enough non-prologue insns seen? If so,
2631 then we must have reached the end of the prologue by now. */
2632 if (prev_delay_slot
|| non_prologue_insns
> 1
2633 || mips16_instruction_is_compact_branch (inst
))
2636 prev_non_prologue_insn
= this_non_prologue_insn
;
2637 prev_delay_slot
= in_delay_slot
;
2638 prev_pc
= cur_pc
- prev_extend_bytes
;
2641 /* The entry instruction is typically the first instruction in a function,
2642 and it stores registers at offsets relative to the value of the old SP
2643 (before the prologue). But the value of the sp parameter to this
2644 function is the new SP (after the prologue has been executed). So we
2645 can't calculate those offsets until we've seen the entire prologue,
2646 and can calculate what the old SP must have been. */
2647 if (entry_inst
!= 0)
2649 int areg_count
= (entry_inst
>> 8) & 7;
2650 int sreg_count
= (entry_inst
>> 6) & 3;
2652 /* The entry instruction always subtracts 32 from the SP. */
2655 /* Now we can calculate what the SP must have been at the
2656 start of the function prologue. */
2659 /* Check if a0-a3 were saved in the caller's argument save area. */
2660 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2662 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2663 offset
+= mips_abi_regsize (gdbarch
);
2666 /* Check if the ra register was pushed on the stack. */
2668 if (entry_inst
& 0x20)
2670 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2671 offset
-= mips_abi_regsize (gdbarch
);
2674 /* Check if the s0 and s1 registers were pushed on the stack. */
2675 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2677 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2678 offset
-= mips_abi_regsize (gdbarch
);
2682 /* The SAVE instruction is similar to ENTRY, except that defined by the
2683 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2684 size of the frame is specified as an immediate field of instruction
2685 and an extended variation exists which lets additional registers and
2686 frame space to be specified. The instruction always treats registers
2687 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2688 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2690 static int args_table
[16] = {
2691 0, 0, 0, 0, 1, 1, 1, 1,
2692 2, 2, 2, 0, 3, 3, 4, -1,
2694 static int astatic_table
[16] = {
2695 0, 1, 2, 3, 0, 1, 2, 3,
2696 0, 1, 2, 4, 0, 1, 0, -1,
2698 int aregs
= (save_inst
>> 16) & 0xf;
2699 int xsregs
= (save_inst
>> 24) & 0x7;
2700 int args
= args_table
[aregs
];
2701 int astatic
= astatic_table
[aregs
];
2706 warning (_("Invalid number of argument registers encoded in SAVE."));
2711 warning (_("Invalid number of static registers encoded in SAVE."));
2715 /* For standard SAVE the frame size of 0 means 128. */
2716 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2717 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2720 frame_offset
+= frame_size
;
2722 /* Now we can calculate what the SP must have been at the
2723 start of the function prologue. */
2726 /* Check if A0-A3 were saved in the caller's argument save area. */
2727 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2729 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2730 offset
+= mips_abi_regsize (gdbarch
);
2735 /* Check if the RA register was pushed on the stack. */
2736 if (save_inst
& 0x40)
2738 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2739 offset
-= mips_abi_regsize (gdbarch
);
2742 /* Check if the S8 register was pushed on the stack. */
2745 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2746 offset
-= mips_abi_regsize (gdbarch
);
2749 /* Check if S2-S7 were pushed on the stack. */
2750 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2752 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2753 offset
-= mips_abi_regsize (gdbarch
);
2756 /* Check if the S1 register was pushed on the stack. */
2757 if (save_inst
& 0x10)
2759 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2760 offset
-= mips_abi_regsize (gdbarch
);
2762 /* Check if the S0 register was pushed on the stack. */
2763 if (save_inst
& 0x20)
2765 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2766 offset
-= mips_abi_regsize (gdbarch
);
2769 /* Check if A0-A3 were pushed on the stack. */
2770 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2772 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2773 offset
-= mips_abi_regsize (gdbarch
);
2777 if (this_cache
!= NULL
)
2780 (get_frame_register_signed (this_frame
,
2781 gdbarch_num_regs (gdbarch
) + frame_reg
)
2782 + frame_offset
- frame_adjust
);
2783 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2784 be able to get rid of the assignment below, evetually. But it's
2785 still needed for now. */
2786 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2787 + mips_regnum (gdbarch
)->pc
]
2788 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2791 /* Set end_prologue_addr to the address of the instruction immediately
2792 after the last one we scanned. Unless the last one looked like a
2793 non-prologue instruction (and we looked ahead), in which case use
2794 its address instead. */
2795 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2796 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2798 return end_prologue_addr
;
2801 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2802 Procedures that use the 32-bit instruction set are handled by the
2803 mips_insn32 unwinder. */
2805 static struct mips_frame_cache
*
2806 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2808 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2809 struct mips_frame_cache
*cache
;
2811 if ((*this_cache
) != NULL
)
2812 return (struct mips_frame_cache
*) (*this_cache
);
2813 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2814 (*this_cache
) = cache
;
2815 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2817 /* Analyze the function prologue. */
2819 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2820 CORE_ADDR start_addr
;
2822 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2823 if (start_addr
== 0)
2824 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2825 /* We can't analyze the prologue if we couldn't find the begining
2827 if (start_addr
== 0)
2830 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2831 (struct mips_frame_cache
*) *this_cache
);
2834 /* gdbarch_sp_regnum contains the value and not the address. */
2835 trad_frame_set_value (cache
->saved_regs
,
2836 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2839 return (struct mips_frame_cache
*) (*this_cache
);
2843 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2844 struct frame_id
*this_id
)
2846 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2848 /* This marks the outermost frame. */
2849 if (info
->base
== 0)
2851 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2854 static struct value
*
2855 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2856 void **this_cache
, int regnum
)
2858 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2860 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2864 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2865 struct frame_info
*this_frame
, void **this_cache
)
2867 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2868 CORE_ADDR pc
= get_frame_pc (this_frame
);
2869 if (mips_pc_is_mips16 (gdbarch
, pc
))
2874 static const struct frame_unwind mips_insn16_frame_unwind
=
2877 default_frame_unwind_stop_reason
,
2878 mips_insn16_frame_this_id
,
2879 mips_insn16_frame_prev_register
,
2881 mips_insn16_frame_sniffer
2885 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2888 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2893 static const struct frame_base mips_insn16_frame_base
=
2895 &mips_insn16_frame_unwind
,
2896 mips_insn16_frame_base_address
,
2897 mips_insn16_frame_base_address
,
2898 mips_insn16_frame_base_address
2901 static const struct frame_base
*
2902 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2904 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2905 CORE_ADDR pc
= get_frame_pc (this_frame
);
2906 if (mips_pc_is_mips16 (gdbarch
, pc
))
2907 return &mips_insn16_frame_base
;
2912 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2913 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2914 interpreted directly, and then multiplied by 4. */
2917 micromips_decode_imm9 (int imm
)
2919 imm
= (imm
^ 0x100) - 0x100;
2920 if (imm
> -3 && imm
< 2)
2925 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2926 the address of the first instruction past the prologue. */
2929 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2930 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2931 struct frame_info
*this_frame
,
2932 struct mips_frame_cache
*this_cache
)
2934 CORE_ADDR end_prologue_addr
;
2935 int prev_non_prologue_insn
= 0;
2936 int frame_reg
= MIPS_SP_REGNUM
;
2937 int this_non_prologue_insn
;
2938 int non_prologue_insns
= 0;
2939 long frame_offset
= 0; /* Size of stack frame. */
2940 long frame_adjust
= 0; /* Offset of FP from SP. */
2941 int prev_delay_slot
= 0;
2945 ULONGEST insn
; /* current instruction */
2949 long v1_off
= 0; /* The assumption is LUI will replace it. */
2960 /* Can be called when there's no process, and hence when there's no
2962 if (this_frame
!= NULL
)
2963 sp
= get_frame_register_signed (this_frame
,
2964 gdbarch_num_regs (gdbarch
)
2969 if (limit_pc
> start_pc
+ 200)
2970 limit_pc
= start_pc
+ 200;
2973 /* Permit at most one non-prologue non-control-transfer instruction
2974 in the middle which may have been reordered by the compiler for
2976 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2978 this_non_prologue_insn
= 0;
2982 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2983 loc
+= MIPS_INSN16_SIZE
;
2984 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2986 /* 32-bit instructions. */
2987 case 2 * MIPS_INSN16_SIZE
:
2989 insn
|= mips_fetch_instruction (gdbarch
,
2990 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
2991 loc
+= MIPS_INSN16_SIZE
;
2992 switch (micromips_op (insn
>> 16))
2994 /* Record $sp/$fp adjustment. */
2995 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2996 case 0x0: /* POOL32A: bits 000000 */
2997 case 0x16: /* POOL32S: bits 010110 */
2998 op
= b0s11_op (insn
);
2999 sreg
= b0s5_reg (insn
>> 16);
3000 treg
= b5s5_reg (insn
>> 16);
3001 dreg
= b11s5_reg (insn
);
3003 /* SUBU: bits 000000 00111010000 */
3004 /* DSUBU: bits 010110 00111010000 */
3005 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3007 /* (D)SUBU $sp, $v1 */
3009 else if (op
!= 0x150
3010 /* ADDU: bits 000000 00101010000 */
3011 /* DADDU: bits 010110 00101010000 */
3012 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3013 this_non_prologue_insn
= 1;
3016 case 0x8: /* POOL32B: bits 001000 */
3017 op
= b12s4_op (insn
);
3018 breg
= b0s5_reg (insn
>> 16);
3019 reglist
= sreg
= b5s5_reg (insn
>> 16);
3020 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3021 if ((op
== 0x9 || op
== 0xc)
3022 /* SWP: bits 001000 1001 */
3023 /* SDP: bits 001000 1100 */
3024 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3025 /* S[DW]P reg,offset($sp) */
3027 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3028 set_reg_offset (gdbarch
, this_cache
,
3030 set_reg_offset (gdbarch
, this_cache
,
3031 sreg
+ 1, sp
+ offset
+ s
);
3033 else if ((op
== 0xd || op
== 0xf)
3034 /* SWM: bits 001000 1101 */
3035 /* SDM: bits 001000 1111 */
3036 && breg
== MIPS_SP_REGNUM
3037 /* SWM reglist,offset($sp) */
3038 && ((reglist
>= 1 && reglist
<= 9)
3039 || (reglist
>= 16 && reglist
<= 25)))
3041 int sreglist
= std::min(reglist
& 0xf, 8);
3043 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3044 for (i
= 0; i
< sreglist
; i
++)
3045 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3046 if ((reglist
& 0xf) > 8)
3047 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3048 if ((reglist
& 0x10) == 0x10)
3049 set_reg_offset (gdbarch
, this_cache
,
3050 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3053 this_non_prologue_insn
= 1;
3056 /* Record $sp/$fp adjustment. */
3057 /* Discard (D)ADDIU $gp used for PIC code. */
3058 case 0xc: /* ADDIU: bits 001100 */
3059 case 0x17: /* DADDIU: bits 010111 */
3060 sreg
= b0s5_reg (insn
>> 16);
3061 dreg
= b5s5_reg (insn
>> 16);
3062 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3063 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3064 /* (D)ADDIU $sp, imm */
3066 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3067 /* (D)ADDIU $fp, $sp, imm */
3069 frame_adjust
= offset
;
3072 else if (sreg
!= 28 || dreg
!= 28)
3073 /* (D)ADDIU $gp, imm */
3074 this_non_prologue_insn
= 1;
3077 /* LUI $v1 is used for larger $sp adjustments. */
3078 /* Discard LUI $gp used for PIC code. */
3079 case 0x10: /* POOL32I: bits 010000 */
3080 if (b5s5_op (insn
>> 16) == 0xd
3081 /* LUI: bits 010000 001101 */
3082 && b0s5_reg (insn
>> 16) == 3)
3084 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3085 else if (b5s5_op (insn
>> 16) != 0xd
3086 /* LUI: bits 010000 001101 */
3087 || b0s5_reg (insn
>> 16) != 28)
3089 this_non_prologue_insn
= 1;
3092 /* ORI $v1 is used for larger $sp adjustments. */
3093 case 0x14: /* ORI: bits 010100 */
3094 sreg
= b0s5_reg (insn
>> 16);
3095 dreg
= b5s5_reg (insn
>> 16);
3096 if (sreg
== 3 && dreg
== 3)
3098 v1_off
|= b0s16_imm (insn
);
3100 this_non_prologue_insn
= 1;
3103 case 0x26: /* SWC1: bits 100110 */
3104 case 0x2e: /* SDC1: bits 101110 */
3105 breg
= b0s5_reg (insn
>> 16);
3106 if (breg
!= MIPS_SP_REGNUM
)
3107 /* S[DW]C1 reg,offset($sp) */
3108 this_non_prologue_insn
= 1;
3111 case 0x36: /* SD: bits 110110 */
3112 case 0x3e: /* SW: bits 111110 */
3113 breg
= b0s5_reg (insn
>> 16);
3114 sreg
= b5s5_reg (insn
>> 16);
3115 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3116 if (breg
== MIPS_SP_REGNUM
)
3117 /* S[DW] reg,offset($sp) */
3118 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3120 this_non_prologue_insn
= 1;
3124 /* The instruction in the delay slot can be a part
3125 of the prologue, so move forward once more. */
3126 if (micromips_instruction_has_delay_slot (insn
, 0))
3129 this_non_prologue_insn
= 1;
3135 /* 16-bit instructions. */
3136 case MIPS_INSN16_SIZE
:
3137 switch (micromips_op (insn
))
3139 case 0x3: /* MOVE: bits 000011 */
3140 sreg
= b0s5_reg (insn
);
3141 dreg
= b5s5_reg (insn
);
3142 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3145 else if ((sreg
& 0x1c) != 0x4)
3146 /* MOVE reg, $a0-$a3 */
3147 this_non_prologue_insn
= 1;
3150 case 0x11: /* POOL16C: bits 010001 */
3151 if (b6s4_op (insn
) == 0x5)
3152 /* SWM: bits 010001 0101 */
3154 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3155 reglist
= b4s2_regl (insn
);
3156 for (i
= 0; i
<= reglist
; i
++)
3157 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3158 set_reg_offset (gdbarch
, this_cache
,
3159 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3162 this_non_prologue_insn
= 1;
3165 case 0x13: /* POOL16D: bits 010011 */
3166 if ((insn
& 0x1) == 0x1)
3167 /* ADDIUSP: bits 010011 1 */
3168 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3169 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3170 /* ADDIUS5: bits 010011 0 */
3171 /* ADDIUS5 $sp, imm */
3172 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3174 this_non_prologue_insn
= 1;
3177 case 0x32: /* SWSP: bits 110010 */
3178 offset
= b0s5_imm (insn
) << 2;
3179 sreg
= b5s5_reg (insn
);
3180 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3184 /* The instruction in the delay slot can be a part
3185 of the prologue, so move forward once more. */
3186 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3189 this_non_prologue_insn
= 1;
3195 frame_offset
-= sp_adj
;
3197 non_prologue_insns
+= this_non_prologue_insn
;
3199 /* A jump or branch, enough non-prologue insns seen or positive
3200 stack adjustment? If so, then we must have reached the end
3201 of the prologue by now. */
3202 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3203 || micromips_instruction_is_compact_branch (insn
))
3206 prev_non_prologue_insn
= this_non_prologue_insn
;
3207 prev_delay_slot
= in_delay_slot
;
3211 if (this_cache
!= NULL
)
3214 (get_frame_register_signed (this_frame
,
3215 gdbarch_num_regs (gdbarch
) + frame_reg
)
3216 + frame_offset
- frame_adjust
);
3217 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3218 be able to get rid of the assignment below, evetually. But it's
3219 still needed for now. */
3220 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3221 + mips_regnum (gdbarch
)->pc
]
3222 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3225 /* Set end_prologue_addr to the address of the instruction immediately
3226 after the last one we scanned. Unless the last one looked like a
3227 non-prologue instruction (and we looked ahead), in which case use
3228 its address instead. */
3230 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3232 return end_prologue_addr
;
3235 /* Heuristic unwinder for procedures using microMIPS instructions.
3236 Procedures that use the 32-bit instruction set are handled by the
3237 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3239 static struct mips_frame_cache
*
3240 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3242 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3243 struct mips_frame_cache
*cache
;
3245 if ((*this_cache
) != NULL
)
3246 return (struct mips_frame_cache
*) (*this_cache
);
3248 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3249 (*this_cache
) = cache
;
3250 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3252 /* Analyze the function prologue. */
3254 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3255 CORE_ADDR start_addr
;
3257 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3258 if (start_addr
== 0)
3259 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3260 /* We can't analyze the prologue if we couldn't find the begining
3262 if (start_addr
== 0)
3265 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3266 (struct mips_frame_cache
*) *this_cache
);
3269 /* gdbarch_sp_regnum contains the value and not the address. */
3270 trad_frame_set_value (cache
->saved_regs
,
3271 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3274 return (struct mips_frame_cache
*) (*this_cache
);
3278 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3279 struct frame_id
*this_id
)
3281 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3283 /* This marks the outermost frame. */
3284 if (info
->base
== 0)
3286 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3289 static struct value
*
3290 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3291 void **this_cache
, int regnum
)
3293 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3295 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3299 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3300 struct frame_info
*this_frame
, void **this_cache
)
3302 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3303 CORE_ADDR pc
= get_frame_pc (this_frame
);
3305 if (mips_pc_is_micromips (gdbarch
, pc
))
3310 static const struct frame_unwind mips_micro_frame_unwind
=
3313 default_frame_unwind_stop_reason
,
3314 mips_micro_frame_this_id
,
3315 mips_micro_frame_prev_register
,
3317 mips_micro_frame_sniffer
3321 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3324 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3329 static const struct frame_base mips_micro_frame_base
=
3331 &mips_micro_frame_unwind
,
3332 mips_micro_frame_base_address
,
3333 mips_micro_frame_base_address
,
3334 mips_micro_frame_base_address
3337 static const struct frame_base
*
3338 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3340 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3341 CORE_ADDR pc
= get_frame_pc (this_frame
);
3343 if (mips_pc_is_micromips (gdbarch
, pc
))
3344 return &mips_micro_frame_base
;
3349 /* Mark all the registers as unset in the saved_regs array
3350 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3353 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3355 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3359 const int num_regs
= gdbarch_num_regs (gdbarch
);
3362 for (i
= 0; i
< num_regs
; i
++)
3364 this_cache
->saved_regs
[i
].addr
= -1;
3369 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3370 the associated FRAME_CACHE if not null.
3371 Return the address of the first instruction past the prologue. */
3374 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3375 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3376 struct frame_info
*this_frame
,
3377 struct mips_frame_cache
*this_cache
)
3379 int prev_non_prologue_insn
;
3380 int this_non_prologue_insn
;
3381 int non_prologue_insns
;
3382 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3384 int prev_delay_slot
;
3389 int frame_reg
= MIPS_SP_REGNUM
;
3391 CORE_ADDR end_prologue_addr
;
3392 int seen_sp_adjust
= 0;
3393 int load_immediate_bytes
= 0;
3395 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3397 /* Can be called when there's no process, and hence when there's no
3399 if (this_frame
!= NULL
)
3400 sp
= get_frame_register_signed (this_frame
,
3401 gdbarch_num_regs (gdbarch
)
3406 if (limit_pc
> start_pc
+ 200)
3407 limit_pc
= start_pc
+ 200;
3410 prev_non_prologue_insn
= 0;
3411 non_prologue_insns
= 0;
3412 prev_delay_slot
= 0;
3415 /* Permit at most one non-prologue non-control-transfer instruction
3416 in the middle which may have been reordered by the compiler for
3419 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3421 unsigned long inst
, high_word
;
3425 this_non_prologue_insn
= 0;
3428 /* Fetch the instruction. */
3429 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3432 /* Save some code by pre-extracting some useful fields. */
3433 high_word
= (inst
>> 16) & 0xffff;
3434 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3435 reg
= high_word
& 0x1f;
3437 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3438 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3439 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3441 if (offset
< 0) /* Negative stack adjustment? */
3442 frame_offset
-= offset
;
3444 /* Exit loop if a positive stack adjustment is found, which
3445 usually means that the stack cleanup code in the function
3446 epilogue is reached. */
3450 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3451 && !regsize_is_64_bits
)
3453 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3455 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3456 && regsize_is_64_bits
)
3458 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3459 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3461 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3463 /* Old gcc frame, r30 is virtual frame pointer. */
3464 if (offset
!= frame_offset
)
3465 frame_addr
= sp
+ offset
;
3466 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3468 unsigned alloca_adjust
;
3471 frame_addr
= get_frame_register_signed
3472 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3475 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3476 if (alloca_adjust
> 0)
3478 /* FP > SP + frame_size. This may be because of
3479 an alloca or somethings similar. Fix sp to
3480 "pre-alloca" value, and try again. */
3481 sp
+= alloca_adjust
;
3482 /* Need to reset the status of all registers. Otherwise,
3483 we will hit a guard that prevents the new address
3484 for each register to be recomputed during the second
3486 reset_saved_regs (gdbarch
, this_cache
);
3491 /* move $30,$sp. With different versions of gas this will be either
3492 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3493 Accept any one of these. */
3494 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3496 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3497 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3499 unsigned alloca_adjust
;
3502 frame_addr
= get_frame_register_signed
3503 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3505 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3506 if (alloca_adjust
> 0)
3508 /* FP > SP + frame_size. This may be because of
3509 an alloca or somethings similar. Fix sp to
3510 "pre-alloca" value, and try again. */
3512 /* Need to reset the status of all registers. Otherwise,
3513 we will hit a guard that prevents the new address
3514 for each register to be recomputed during the second
3516 reset_saved_regs (gdbarch
, this_cache
);
3521 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3522 && !regsize_is_64_bits
)
3524 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3526 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3527 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3528 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3529 || high_word
== 0x3c1c /* lui $gp,n */
3530 || high_word
== 0x279c /* addiu $gp,$gp,n */
3531 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3532 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3535 /* These instructions are part of the prologue, but we don't
3536 need to do anything special to handle them. */
3538 /* The instructions below load $at or $t0 with an immediate
3539 value in preparation for a stack adjustment via
3540 subu $sp,$sp,[$at,$t0]. These instructions could also
3541 initialize a local variable, so we accept them only before
3542 a stack adjustment instruction was seen. */
3543 else if (!seen_sp_adjust
3545 && (high_word
== 0x3c01 /* lui $at,n */
3546 || high_word
== 0x3c08 /* lui $t0,n */
3547 || high_word
== 0x3421 /* ori $at,$at,n */
3548 || high_word
== 0x3508 /* ori $t0,$t0,n */
3549 || high_word
== 0x3401 /* ori $at,$zero,n */
3550 || high_word
== 0x3408 /* ori $t0,$zero,n */
3553 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3555 /* Check for branches and jumps. The instruction in the delay
3556 slot can be a part of the prologue, so move forward once more. */
3557 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3561 /* This instruction is not an instruction typically found
3562 in a prologue, so we must have reached the end of the
3566 this_non_prologue_insn
= 1;
3569 non_prologue_insns
+= this_non_prologue_insn
;
3571 /* A jump or branch, or enough non-prologue insns seen? If so,
3572 then we must have reached the end of the prologue by now. */
3573 if (prev_delay_slot
|| non_prologue_insns
> 1)
3576 prev_non_prologue_insn
= this_non_prologue_insn
;
3577 prev_delay_slot
= in_delay_slot
;
3581 if (this_cache
!= NULL
)
3584 (get_frame_register_signed (this_frame
,
3585 gdbarch_num_regs (gdbarch
) + frame_reg
)
3587 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3588 this assignment below, eventually. But it's still needed
3590 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3591 + mips_regnum (gdbarch
)->pc
]
3592 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3596 /* Set end_prologue_addr to the address of the instruction immediately
3597 after the last one we scanned. Unless the last one looked like a
3598 non-prologue instruction (and we looked ahead), in which case use
3599 its address instead. */
3601 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3603 /* In a frameless function, we might have incorrectly
3604 skipped some load immediate instructions. Undo the skipping
3605 if the load immediate was not followed by a stack adjustment. */
3606 if (load_immediate_bytes
&& !seen_sp_adjust
)
3607 end_prologue_addr
-= load_immediate_bytes
;
3609 return end_prologue_addr
;
3612 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3613 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3614 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3615 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3617 static struct mips_frame_cache
*
3618 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3620 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3621 struct mips_frame_cache
*cache
;
3623 if ((*this_cache
) != NULL
)
3624 return (struct mips_frame_cache
*) (*this_cache
);
3626 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3627 (*this_cache
) = cache
;
3628 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3630 /* Analyze the function prologue. */
3632 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3633 CORE_ADDR start_addr
;
3635 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3636 if (start_addr
== 0)
3637 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3638 /* We can't analyze the prologue if we couldn't find the begining
3640 if (start_addr
== 0)
3643 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3644 (struct mips_frame_cache
*) *this_cache
);
3647 /* gdbarch_sp_regnum contains the value and not the address. */
3648 trad_frame_set_value (cache
->saved_regs
,
3649 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3652 return (struct mips_frame_cache
*) (*this_cache
);
3656 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3657 struct frame_id
*this_id
)
3659 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3661 /* This marks the outermost frame. */
3662 if (info
->base
== 0)
3664 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3667 static struct value
*
3668 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3669 void **this_cache
, int regnum
)
3671 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3673 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3677 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3678 struct frame_info
*this_frame
, void **this_cache
)
3680 CORE_ADDR pc
= get_frame_pc (this_frame
);
3681 if (mips_pc_is_mips (pc
))
3686 static const struct frame_unwind mips_insn32_frame_unwind
=
3689 default_frame_unwind_stop_reason
,
3690 mips_insn32_frame_this_id
,
3691 mips_insn32_frame_prev_register
,
3693 mips_insn32_frame_sniffer
3697 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3700 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3705 static const struct frame_base mips_insn32_frame_base
=
3707 &mips_insn32_frame_unwind
,
3708 mips_insn32_frame_base_address
,
3709 mips_insn32_frame_base_address
,
3710 mips_insn32_frame_base_address
3713 static const struct frame_base
*
3714 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3716 CORE_ADDR pc
= get_frame_pc (this_frame
);
3717 if (mips_pc_is_mips (pc
))
3718 return &mips_insn32_frame_base
;
3723 static struct trad_frame_cache
*
3724 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3727 CORE_ADDR start_addr
;
3728 CORE_ADDR stack_addr
;
3729 struct trad_frame_cache
*this_trad_cache
;
3730 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3731 int num_regs
= gdbarch_num_regs (gdbarch
);
3733 if ((*this_cache
) != NULL
)
3734 return (struct trad_frame_cache
*) (*this_cache
);
3735 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3736 (*this_cache
) = this_trad_cache
;
3738 /* The return address is in the link register. */
3739 trad_frame_set_reg_realreg (this_trad_cache
,
3740 gdbarch_pc_regnum (gdbarch
),
3741 num_regs
+ MIPS_RA_REGNUM
);
3743 /* Frame ID, since it's a frameless / stackless function, no stack
3744 space is allocated and SP on entry is the current SP. */
3745 pc
= get_frame_pc (this_frame
);
3746 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3747 stack_addr
= get_frame_register_signed (this_frame
,
3748 num_regs
+ MIPS_SP_REGNUM
);
3749 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3751 /* Assume that the frame's base is the same as the
3753 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3755 return this_trad_cache
;
3759 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3760 struct frame_id
*this_id
)
3762 struct trad_frame_cache
*this_trad_cache
3763 = mips_stub_frame_cache (this_frame
, this_cache
);
3764 trad_frame_get_id (this_trad_cache
, this_id
);
3767 static struct value
*
3768 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3769 void **this_cache
, int regnum
)
3771 struct trad_frame_cache
*this_trad_cache
3772 = mips_stub_frame_cache (this_frame
, this_cache
);
3773 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3777 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3778 struct frame_info
*this_frame
, void **this_cache
)
3781 struct obj_section
*s
;
3782 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3783 struct bound_minimal_symbol msym
;
3785 /* Use the stub unwinder for unreadable code. */
3786 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3789 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3792 /* Calling a PIC function from a non-PIC function passes through a
3793 stub. The stub for foo is named ".pic.foo". */
3794 msym
= lookup_minimal_symbol_by_pc (pc
);
3795 if (msym
.minsym
!= NULL
3796 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
3797 && startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
3803 static const struct frame_unwind mips_stub_frame_unwind
=
3806 default_frame_unwind_stop_reason
,
3807 mips_stub_frame_this_id
,
3808 mips_stub_frame_prev_register
,
3810 mips_stub_frame_sniffer
3814 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3817 struct trad_frame_cache
*this_trad_cache
3818 = mips_stub_frame_cache (this_frame
, this_cache
);
3819 return trad_frame_get_this_base (this_trad_cache
);
3822 static const struct frame_base mips_stub_frame_base
=
3824 &mips_stub_frame_unwind
,
3825 mips_stub_frame_base_address
,
3826 mips_stub_frame_base_address
,
3827 mips_stub_frame_base_address
3830 static const struct frame_base
*
3831 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3833 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3834 return &mips_stub_frame_base
;
3839 /* mips_addr_bits_remove - remove useless address bits */
3842 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3844 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3846 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3847 /* This hack is a work-around for existing boards using PMON, the
3848 simulator, and any other 64-bit targets that doesn't have true
3849 64-bit addressing. On these targets, the upper 32 bits of
3850 addresses are ignored by the hardware. Thus, the PC or SP are
3851 likely to have been sign extended to all 1s by instruction
3852 sequences that load 32-bit addresses. For example, a typical
3853 piece of code that loads an address is this:
3855 lui $r2, <upper 16 bits>
3856 ori $r2, <lower 16 bits>
3858 But the lui sign-extends the value such that the upper 32 bits
3859 may be all 1s. The workaround is simply to mask off these
3860 bits. In the future, gcc may be changed to support true 64-bit
3861 addressing, and this masking will have to be disabled. */
3862 return addr
&= 0xffffffffUL
;
3868 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3869 instruction and ending with a SC/SCD instruction. If such a sequence
3870 is found, attempt to step through it. A breakpoint is placed at the end of
3873 /* Instructions used during single-stepping of atomic sequences, standard
3875 #define LL_OPCODE 0x30
3876 #define LLD_OPCODE 0x34
3877 #define SC_OPCODE 0x38
3878 #define SCD_OPCODE 0x3c
3881 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3882 struct address_space
*aspace
, CORE_ADDR pc
)
3884 CORE_ADDR breaks
[2] = {-1, -1};
3886 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3890 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3891 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3893 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3894 /* Assume all atomic sequences start with a ll/lld instruction. */
3895 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3898 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3900 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3903 loc
+= MIPS_INSN32_SIZE
;
3904 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3906 /* Assume that there is at most one branch in the atomic
3907 sequence. If a branch is found, put a breakpoint in its
3908 destination address. */
3909 switch (itype_op (insn
))
3911 case 0: /* SPECIAL */
3912 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3913 return 0; /* fallback to the standard single-step code. */
3915 case 1: /* REGIMM */
3916 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3917 || ((itype_rt (insn
) & 0x1e) == 0
3918 && itype_rs (insn
) == 0)); /* BPOSGE* */
3922 return 0; /* fallback to the standard single-step code. */
3929 case 22: /* BLEZL */
3930 case 23: /* BGTTL */
3934 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3935 && (itype_rt (insn
) & 0x2) == 0);
3936 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3941 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3946 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3947 if (last_breakpoint
>= 1)
3948 return 0; /* More than one branch found, fallback to the
3949 standard single-step code. */
3950 breaks
[1] = branch_bp
;
3954 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3958 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3959 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3962 loc
+= MIPS_INSN32_SIZE
;
3964 /* Insert a breakpoint right after the end of the atomic sequence. */
3967 /* Check for duplicated breakpoints. Check also for a breakpoint
3968 placed (branch instruction's destination) in the atomic sequence. */
3969 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3970 last_breakpoint
= 0;
3972 /* Effectively inserts the breakpoints. */
3973 for (index
= 0; index
<= last_breakpoint
; index
++)
3974 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3980 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3981 struct address_space
*aspace
,
3984 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3985 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3986 CORE_ADDR breaks
[2] = {-1, -1};
3987 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
3995 /* Assume all atomic sequences start with a ll/lld instruction. */
3996 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3997 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
3999 loc
+= MIPS_INSN16_SIZE
;
4001 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4002 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4004 loc
+= MIPS_INSN16_SIZE
;
4006 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4007 that no atomic sequence is longer than "atomic_sequence_length"
4009 for (insn_count
= 0;
4010 !sc_found
&& insn_count
< atomic_sequence_length
;
4015 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4016 loc
+= MIPS_INSN16_SIZE
;
4018 /* Assume that there is at most one conditional branch in the
4019 atomic sequence. If a branch is found, put a breakpoint in
4020 its destination address. */
4021 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4023 /* 32-bit instructions. */
4024 case 2 * MIPS_INSN16_SIZE
:
4025 switch (micromips_op (insn
))
4027 case 0x10: /* POOL32I: bits 010000 */
4028 if ((b5s5_op (insn
) & 0x18) != 0x0
4029 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4030 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4031 && (b5s5_op (insn
) & 0x1d) != 0x11
4032 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4033 && ((b5s5_op (insn
) & 0x1e) != 0x14
4034 || (insn
& 0x3) != 0x0)
4035 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4036 && (b5s5_op (insn
) & 0x1e) != 0x1a
4037 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4038 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4039 || (insn
& 0x3) != 0x0)
4040 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4041 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4042 || (insn
& 0x3) != 0x1))
4043 /* BC1ANY*: bits 010000 111xx xxx01 */
4047 case 0x25: /* BEQ: bits 100101 */
4048 case 0x2d: /* BNE: bits 101101 */
4050 insn
|= mips_fetch_instruction (gdbarch
,
4051 ISA_MICROMIPS
, loc
, NULL
);
4052 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4053 + micromips_relative_offset16 (insn
));
4057 case 0x00: /* POOL32A: bits 000000 */
4059 insn
|= mips_fetch_instruction (gdbarch
,
4060 ISA_MICROMIPS
, loc
, NULL
);
4061 if (b0s6_op (insn
) != 0x3c
4062 /* POOL32Axf: bits 000000 ... 111100 */
4063 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4064 /* JALR, JALR.HB: 000000 000x111100 111100 */
4065 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4069 case 0x1d: /* JALS: bits 011101 */
4070 case 0x35: /* J: bits 110101 */
4071 case 0x3d: /* JAL: bits 111101 */
4072 case 0x3c: /* JALX: bits 111100 */
4073 return 0; /* Fall back to the standard single-step code. */
4075 case 0x18: /* POOL32C: bits 011000 */
4076 if ((b12s4_op (insn
) & 0xb) == 0xb)
4077 /* SC, SCD: bits 011000 1x11 */
4081 loc
+= MIPS_INSN16_SIZE
;
4084 /* 16-bit instructions. */
4085 case MIPS_INSN16_SIZE
:
4086 switch (micromips_op (insn
))
4088 case 0x23: /* BEQZ16: bits 100011 */
4089 case 0x2b: /* BNEZ16: bits 101011 */
4090 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4094 case 0x11: /* POOL16C: bits 010001 */
4095 if ((b5s5_op (insn
) & 0x1c) != 0xc
4096 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4097 && b5s5_op (insn
) != 0x18)
4098 /* JRADDIUSP: bits 010001 11000 */
4100 return 0; /* Fall back to the standard single-step code. */
4102 case 0x33: /* B16: bits 110011 */
4103 return 0; /* Fall back to the standard single-step code. */
4109 if (last_breakpoint
>= 1)
4110 return 0; /* More than one branch found, fallback to the
4111 standard single-step code. */
4112 breaks
[1] = branch_bp
;
4119 /* Insert a breakpoint right after the end of the atomic sequence. */
4122 /* Check for duplicated breakpoints. Check also for a breakpoint
4123 placed (branch instruction's destination) in the atomic sequence */
4124 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4125 last_breakpoint
= 0;
4127 /* Effectively inserts the breakpoints. */
4128 for (index
= 0; index
<= last_breakpoint
; index
++)
4129 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
4135 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4136 struct address_space
*aspace
, CORE_ADDR pc
)
4138 if (mips_pc_is_mips (pc
))
4139 return mips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4140 else if (mips_pc_is_micromips (gdbarch
, pc
))
4141 return micromips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4146 /* mips_software_single_step() is called just before we want to resume
4147 the inferior, if we want to single-step it but there is no hardware
4148 or kernel single-step support (MIPS on GNU/Linux for example). We find
4149 the target of the coming instruction and breakpoint it. */
4152 mips_software_single_step (struct frame_info
*frame
)
4154 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4155 struct address_space
*aspace
= get_frame_address_space (frame
);
4156 CORE_ADDR pc
, next_pc
;
4158 pc
= get_frame_pc (frame
);
4159 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
4162 next_pc
= mips_next_pc (frame
, pc
);
4164 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
4168 /* Test whether the PC points to the return instruction at the
4169 end of a function. */
4172 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4177 /* This used to check for MIPS16, but this piece of code is never
4178 called for MIPS16 functions. And likewise microMIPS ones. */
4179 gdb_assert (mips_pc_is_mips (pc
));
4181 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4183 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4187 /* This fencepost looks highly suspicious to me. Removing it also
4188 seems suspicious as it could affect remote debugging across serial
4192 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4198 struct inferior
*inf
;
4200 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4202 fence
= start_pc
- heuristic_fence_post
;
4206 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4207 fence
= VM_MIN_ADDRESS
;
4209 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4211 inf
= current_inferior ();
4213 /* Search back for previous return. */
4214 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4215 if (start_pc
< fence
)
4217 /* It's not clear to me why we reach this point when
4218 stop_soon, but with this test, at least we
4219 don't print out warnings for every child forked (eg, on
4220 decstation). 22apr93 rich@cygnus.com. */
4221 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4223 static int blurb_printed
= 0;
4225 warning (_("GDB can't find the start of the function at %s."),
4226 paddress (gdbarch
, pc
));
4230 /* This actually happens frequently in embedded
4231 development, when you first connect to a board
4232 and your stack pointer and pc are nowhere in
4233 particular. This message needs to give people
4234 in that situation enough information to
4235 determine that it's no big deal. */
4236 printf_filtered ("\n\
4237 GDB is unable to find the start of the function at %s\n\
4238 and thus can't determine the size of that function's stack frame.\n\
4239 This means that GDB may be unable to access that stack frame, or\n\
4240 the frames below it.\n\
4241 This problem is most likely caused by an invalid program counter or\n\
4243 However, if you think GDB should simply search farther back\n\
4244 from %s for code which looks like the beginning of a\n\
4245 function, you can increase the range of the search using the `set\n\
4246 heuristic-fence-post' command.\n",
4247 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4254 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4256 unsigned short inst
;
4258 /* On MIPS16, any one of the following is likely to be the
4259 start of a function:
4265 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4266 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4267 if ((inst
& 0xff80) == 0x6480) /* save */
4269 if (start_pc
- instlen
>= fence
)
4271 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4272 start_pc
- instlen
, NULL
);
4273 if ((inst
& 0xf800) == 0xf000) /* extend */
4274 start_pc
-= instlen
;
4278 else if (((inst
& 0xf81f) == 0xe809
4279 && (inst
& 0x700) != 0x700) /* entry */
4280 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4281 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4282 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4284 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4285 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4290 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4298 /* On microMIPS, any one of the following is likely to be the
4299 start of a function:
4303 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4304 switch (micromips_op (insn
))
4306 case 0xc: /* ADDIU: bits 001100 */
4307 case 0x17: /* DADDIU: bits 010111 */
4308 sreg
= b0s5_reg (insn
);
4309 dreg
= b5s5_reg (insn
);
4311 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4312 pc
+ MIPS_INSN16_SIZE
, NULL
);
4313 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4314 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4315 /* (D)ADDIU $sp, imm */
4320 case 0x10: /* POOL32I: bits 010000 */
4321 if (b5s5_op (insn
) == 0xd
4322 /* LUI: bits 010000 001101 */
4323 && b0s5_reg (insn
>> 16) == 28)
4328 case 0x13: /* POOL16D: bits 010011 */
4329 if ((insn
& 0x1) == 0x1)
4330 /* ADDIUSP: bits 010011 1 */
4332 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4338 /* ADDIUS5: bits 010011 0 */
4340 dreg
= b5s5_reg (insn
);
4341 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4342 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4343 /* ADDIUS5 $sp, -imm */
4351 else if (mips_about_to_return (gdbarch
, start_pc
))
4353 /* Skip return and its delay slot. */
4354 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4361 struct mips_objfile_private
4367 /* According to the current ABI, should the type be passed in a
4368 floating-point register (assuming that there is space)? When there
4369 is no FPU, FP are not even considered as possible candidates for
4370 FP registers and, consequently this returns false - forces FP
4371 arguments into integer registers. */
4374 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4375 struct type
*arg_type
)
4377 return ((typecode
== TYPE_CODE_FLT
4378 || (MIPS_EABI (gdbarch
)
4379 && (typecode
== TYPE_CODE_STRUCT
4380 || typecode
== TYPE_CODE_UNION
)
4381 && TYPE_NFIELDS (arg_type
) == 1
4382 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4384 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4387 /* On o32, argument passing in GPRs depends on the alignment of the type being
4388 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4391 mips_type_needs_double_align (struct type
*type
)
4393 enum type_code typecode
= TYPE_CODE (type
);
4395 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4397 else if (typecode
== TYPE_CODE_STRUCT
)
4399 if (TYPE_NFIELDS (type
) < 1)
4401 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4403 else if (typecode
== TYPE_CODE_UNION
)
4407 n
= TYPE_NFIELDS (type
);
4408 for (i
= 0; i
< n
; i
++)
4409 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4416 /* Adjust the address downward (direction of stack growth) so that it
4417 is correctly aligned for a new stack frame. */
4419 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4421 return align_down (addr
, 16);
4424 /* Implement the "push_dummy_code" gdbarch method. */
4427 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4428 CORE_ADDR funaddr
, struct value
**args
,
4429 int nargs
, struct type
*value_type
,
4430 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4431 struct regcache
*regcache
)
4433 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4437 /* Reserve enough room on the stack for our breakpoint instruction. */
4438 bp_slot
= sp
- sizeof (nop_insn
);
4440 /* Return to microMIPS mode if calling microMIPS code to avoid
4441 triggering an address error exception on processors that only
4442 support microMIPS execution. */
4443 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4444 ? make_compact_addr (bp_slot
) : bp_slot
);
4446 /* The breakpoint layer automatically adjusts the address of
4447 breakpoints inserted in a branch delay slot. With enough
4448 bad luck, the 4 bytes located just before our breakpoint
4449 instruction could look like a branch instruction, and thus
4450 trigger the adjustement, and break the function call entirely.
4451 So, we reserve those 4 bytes and write a nop instruction
4452 to prevent that from happening. */
4453 nop_addr
= bp_slot
- sizeof (nop_insn
);
4454 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4455 sp
= mips_frame_align (gdbarch
, nop_addr
);
4457 /* Inferior resumes at the function entry point. */
4464 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4465 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4466 int nargs
, struct value
**args
, CORE_ADDR sp
,
4467 int struct_return
, CORE_ADDR struct_addr
)
4473 int stack_offset
= 0;
4474 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4475 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4476 int regsize
= mips_abi_regsize (gdbarch
);
4478 /* For shared libraries, "t9" needs to point at the function
4480 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4482 /* Set the return address register to point to the entry point of
4483 the program, where a breakpoint lies in wait. */
4484 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4486 /* First ensure that the stack and structure return address (if any)
4487 are properly aligned. The stack has to be at least 64-bit
4488 aligned even on 32-bit machines, because doubles must be 64-bit
4489 aligned. For n32 and n64, stack frames need to be 128-bit
4490 aligned, so we round to this widest known alignment. */
4492 sp
= align_down (sp
, 16);
4493 struct_addr
= align_down (struct_addr
, 16);
4495 /* Now make space on the stack for the args. We allocate more
4496 than necessary for EABI, because the first few arguments are
4497 passed in registers, but that's OK. */
4498 for (argnum
= 0; argnum
< nargs
; argnum
++)
4499 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
4500 sp
-= align_up (len
, 16);
4503 fprintf_unfiltered (gdb_stdlog
,
4504 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4505 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4507 /* Initialize the integer and float register pointers. */
4508 argreg
= MIPS_A0_REGNUM
;
4509 float_argreg
= mips_fpa0_regnum (gdbarch
);
4511 /* The struct_return pointer occupies the first parameter-passing reg. */
4515 fprintf_unfiltered (gdb_stdlog
,
4516 "mips_eabi_push_dummy_call: "
4517 "struct_return reg=%d %s\n",
4518 argreg
, paddress (gdbarch
, struct_addr
));
4519 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4522 /* Now load as many as possible of the first arguments into
4523 registers, and push the rest onto the stack. Loop thru args
4524 from first to last. */
4525 for (argnum
= 0; argnum
< nargs
; argnum
++)
4527 const gdb_byte
*val
;
4528 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4529 struct value
*arg
= args
[argnum
];
4530 struct type
*arg_type
= check_typedef (value_type (arg
));
4531 int len
= TYPE_LENGTH (arg_type
);
4532 enum type_code typecode
= TYPE_CODE (arg_type
);
4535 fprintf_unfiltered (gdb_stdlog
,
4536 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4537 argnum
+ 1, len
, (int) typecode
);
4539 /* The EABI passes structures that do not fit in a register by
4542 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4544 store_unsigned_integer (valbuf
, regsize
, byte_order
,
4545 value_address (arg
));
4546 typecode
= TYPE_CODE_PTR
;
4550 fprintf_unfiltered (gdb_stdlog
, " push");
4553 val
= value_contents (arg
);
4555 /* 32-bit ABIs always start floating point arguments in an
4556 even-numbered floating point register. Round the FP register
4557 up before the check to see if there are any FP registers
4558 left. Non MIPS_EABI targets also pass the FP in the integer
4559 registers so also round up normal registers. */
4560 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4562 if ((float_argreg
& 1))
4566 /* Floating point arguments passed in registers have to be
4567 treated specially. On 32-bit architectures, doubles
4568 are passed in register pairs; the even register gets
4569 the low word, and the odd register gets the high word.
4570 On non-EABI processors, the first two floating point arguments are
4571 also copied to general registers, because MIPS16 functions
4572 don't use float registers for arguments. This duplication of
4573 arguments in general registers can't hurt non-MIPS16 functions
4574 because those registers are normally skipped. */
4575 /* MIPS_EABI squeezes a struct that contains a single floating
4576 point value into an FP register instead of pushing it onto the
4578 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4579 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4581 /* EABI32 will pass doubles in consecutive registers, even on
4582 64-bit cores. At one time, we used to check the size of
4583 `float_argreg' to determine whether or not to pass doubles
4584 in consecutive registers, but this is not sufficient for
4585 making the ABI determination. */
4586 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4588 int low_offset
= gdbarch_byte_order (gdbarch
)
4589 == BFD_ENDIAN_BIG
? 4 : 0;
4592 /* Write the low word of the double to the even register(s). */
4593 regval
= extract_signed_integer (val
+ low_offset
,
4596 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4597 float_argreg
, phex (regval
, 4));
4598 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4600 /* Write the high word of the double to the odd register(s). */
4601 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4604 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4605 float_argreg
, phex (regval
, 4));
4606 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4610 /* This is a floating point value that fits entirely
4611 in a single register. */
4612 /* On 32 bit ABI's the float_argreg is further adjusted
4613 above to ensure that it is even register aligned. */
4614 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4616 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4617 float_argreg
, phex (regval
, len
));
4618 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4623 /* Copy the argument to general registers or the stack in
4624 register-sized pieces. Large arguments are split between
4625 registers and stack. */
4626 /* Note: structs whose size is not a multiple of regsize
4627 are treated specially: Irix cc passes
4628 them in registers where gcc sometimes puts them on the
4629 stack. For maximum compatibility, we will put them in
4631 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
4633 /* Note: Floating-point values that didn't fit into an FP
4634 register are only written to memory. */
4637 /* Remember if the argument was written to the stack. */
4638 int stack_used_p
= 0;
4639 int partial_len
= (len
< regsize
? len
: regsize
);
4642 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4645 /* Write this portion of the argument to the stack. */
4646 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4648 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4650 /* Should shorter than int integer values be
4651 promoted to int before being stored? */
4652 int longword_offset
= 0;
4655 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4658 && (typecode
== TYPE_CODE_INT
4659 || typecode
== TYPE_CODE_PTR
4660 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4661 longword_offset
= regsize
- len
;
4662 else if ((typecode
== TYPE_CODE_STRUCT
4663 || typecode
== TYPE_CODE_UNION
)
4664 && TYPE_LENGTH (arg_type
) < regsize
)
4665 longword_offset
= regsize
- len
;
4670 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4671 paddress (gdbarch
, stack_offset
));
4672 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4673 paddress (gdbarch
, longword_offset
));
4676 addr
= sp
+ stack_offset
+ longword_offset
;
4681 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4682 paddress (gdbarch
, addr
));
4683 for (i
= 0; i
< partial_len
; i
++)
4685 fprintf_unfiltered (gdb_stdlog
, "%02x",
4689 write_memory (addr
, val
, partial_len
);
4692 /* Note!!! This is NOT an else clause. Odd sized
4693 structs may go thru BOTH paths. Floating point
4694 arguments will not. */
4695 /* Write this portion of the argument to a general
4696 purpose register. */
4697 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4698 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4701 extract_signed_integer (val
, partial_len
, byte_order
);
4704 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4706 phex (regval
, regsize
));
4707 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4714 /* Compute the offset into the stack at which we will
4715 copy the next parameter.
4717 In the new EABI (and the NABI32), the stack_offset
4718 only needs to be adjusted when it has been used. */
4721 stack_offset
+= align_up (partial_len
, regsize
);
4725 fprintf_unfiltered (gdb_stdlog
, "\n");
4728 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4730 /* Return adjusted stack pointer. */
4734 /* Determine the return value convention being used. */
4736 static enum return_value_convention
4737 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4738 struct type
*type
, struct regcache
*regcache
,
4739 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4741 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4742 int fp_return_type
= 0;
4743 int offset
, regnum
, xfer
;
4745 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4746 return RETURN_VALUE_STRUCT_CONVENTION
;
4748 /* Floating point type? */
4749 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4751 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4753 /* Structs with a single field of float type
4754 are returned in a floating point register. */
4755 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4756 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4757 && TYPE_NFIELDS (type
) == 1)
4759 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4761 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4768 /* A floating-point value belongs in the least significant part
4771 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4772 regnum
= mips_regnum (gdbarch
)->fp0
;
4776 /* An integer value goes in V0/V1. */
4778 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4779 regnum
= MIPS_V0_REGNUM
;
4782 offset
< TYPE_LENGTH (type
);
4783 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4785 xfer
= mips_abi_regsize (gdbarch
);
4786 if (offset
+ xfer
> TYPE_LENGTH (type
))
4787 xfer
= TYPE_LENGTH (type
) - offset
;
4788 mips_xfer_register (gdbarch
, regcache
,
4789 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4790 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4794 return RETURN_VALUE_REGISTER_CONVENTION
;
4798 /* N32/N64 ABI stuff. */
4800 /* Search for a naturally aligned double at OFFSET inside a struct
4801 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4805 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4810 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4813 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4816 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4819 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4822 struct type
*field_type
;
4824 /* We're only looking at normal fields. */
4825 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4826 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4829 /* If we have gone past the offset, there is no double to pass. */
4830 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4834 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4836 /* If this field is entirely before the requested offset, go
4837 on to the next one. */
4838 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4841 /* If this is our special aligned double, we can stop. */
4842 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4843 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4846 /* This field starts at or before the requested offset, and
4847 overlaps it. If it is a structure, recurse inwards. */
4848 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4855 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4856 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4857 int nargs
, struct value
**args
, CORE_ADDR sp
,
4858 int struct_return
, CORE_ADDR struct_addr
)
4864 int stack_offset
= 0;
4865 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4866 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4868 /* For shared libraries, "t9" needs to point at the function
4870 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4872 /* Set the return address register to point to the entry point of
4873 the program, where a breakpoint lies in wait. */
4874 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4876 /* First ensure that the stack and structure return address (if any)
4877 are properly aligned. The stack has to be at least 64-bit
4878 aligned even on 32-bit machines, because doubles must be 64-bit
4879 aligned. For n32 and n64, stack frames need to be 128-bit
4880 aligned, so we round to this widest known alignment. */
4882 sp
= align_down (sp
, 16);
4883 struct_addr
= align_down (struct_addr
, 16);
4885 /* Now make space on the stack for the args. */
4886 for (argnum
= 0; argnum
< nargs
; argnum
++)
4887 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4888 sp
-= align_up (len
, 16);
4891 fprintf_unfiltered (gdb_stdlog
,
4892 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4893 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4895 /* Initialize the integer and float register pointers. */
4896 argreg
= MIPS_A0_REGNUM
;
4897 float_argreg
= mips_fpa0_regnum (gdbarch
);
4899 /* The struct_return pointer occupies the first parameter-passing reg. */
4903 fprintf_unfiltered (gdb_stdlog
,
4904 "mips_n32n64_push_dummy_call: "
4905 "struct_return reg=%d %s\n",
4906 argreg
, paddress (gdbarch
, struct_addr
));
4907 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4910 /* Now load as many as possible of the first arguments into
4911 registers, and push the rest onto the stack. Loop thru args
4912 from first to last. */
4913 for (argnum
= 0; argnum
< nargs
; argnum
++)
4915 const gdb_byte
*val
;
4916 struct value
*arg
= args
[argnum
];
4917 struct type
*arg_type
= check_typedef (value_type (arg
));
4918 int len
= TYPE_LENGTH (arg_type
);
4919 enum type_code typecode
= TYPE_CODE (arg_type
);
4922 fprintf_unfiltered (gdb_stdlog
,
4923 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4924 argnum
+ 1, len
, (int) typecode
);
4926 val
= value_contents (arg
);
4928 /* A 128-bit long double value requires an even-odd pair of
4929 floating-point registers. */
4931 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4932 && (float_argreg
& 1))
4938 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4939 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4941 /* This is a floating point value that fits entirely
4942 in a single register or a pair of registers. */
4943 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4944 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4946 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4947 float_argreg
, phex (regval
, reglen
));
4948 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4951 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4952 argreg
, phex (regval
, reglen
));
4953 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4958 regval
= extract_unsigned_integer (val
+ reglen
,
4959 reglen
, byte_order
);
4961 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4962 float_argreg
, phex (regval
, reglen
));
4963 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4966 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4967 argreg
, phex (regval
, reglen
));
4968 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4975 /* Copy the argument to general registers or the stack in
4976 register-sized pieces. Large arguments are split between
4977 registers and stack. */
4978 /* For N32/N64, structs, unions, or other composite types are
4979 treated as a sequence of doublewords, and are passed in integer
4980 or floating point registers as though they were simple scalar
4981 parameters to the extent that they fit, with any excess on the
4982 stack packed according to the normal memory layout of the
4984 The caller does not reserve space for the register arguments;
4985 the callee is responsible for reserving it if required. */
4986 /* Note: Floating-point values that didn't fit into an FP
4987 register are only written to memory. */
4990 /* Remember if the argument was written to the stack. */
4991 int stack_used_p
= 0;
4992 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4995 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4998 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4999 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
5001 /* Write this portion of the argument to the stack. */
5002 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
5004 /* Should shorter than int integer values be
5005 promoted to int before being stored? */
5006 int longword_offset
= 0;
5009 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5011 if ((typecode
== TYPE_CODE_INT
5012 || typecode
== TYPE_CODE_PTR
)
5014 longword_offset
= MIPS64_REGSIZE
- len
;
5019 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5020 paddress (gdbarch
, stack_offset
));
5021 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5022 paddress (gdbarch
, longword_offset
));
5025 addr
= sp
+ stack_offset
+ longword_offset
;
5030 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5031 paddress (gdbarch
, addr
));
5032 for (i
= 0; i
< partial_len
; i
++)
5034 fprintf_unfiltered (gdb_stdlog
, "%02x",
5038 write_memory (addr
, val
, partial_len
);
5041 /* Note!!! This is NOT an else clause. Odd sized
5042 structs may go thru BOTH paths. */
5043 /* Write this portion of the argument to a general
5044 purpose register. */
5045 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5049 /* Sign extend pointers, 32-bit integers and signed
5050 16-bit and 8-bit integers; everything else is taken
5053 if ((partial_len
== 4
5054 && (typecode
== TYPE_CODE_PTR
5055 || typecode
== TYPE_CODE_INT
))
5057 && typecode
== TYPE_CODE_INT
5058 && !TYPE_UNSIGNED (arg_type
)))
5059 regval
= extract_signed_integer (val
, partial_len
,
5062 regval
= extract_unsigned_integer (val
, partial_len
,
5065 /* A non-floating-point argument being passed in a
5066 general register. If a struct or union, and if
5067 the remaining length is smaller than the register
5068 size, we have to adjust the register value on
5071 It does not seem to be necessary to do the
5072 same for integral types. */
5074 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5075 && partial_len
< MIPS64_REGSIZE
5076 && (typecode
== TYPE_CODE_STRUCT
5077 || typecode
== TYPE_CODE_UNION
))
5078 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5082 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5084 phex (regval
, MIPS64_REGSIZE
));
5085 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5087 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5088 TYPE_LENGTH (arg_type
) - len
))
5091 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5093 phex (regval
, MIPS64_REGSIZE
));
5094 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5105 /* Compute the offset into the stack at which we will
5106 copy the next parameter.
5108 In N32 (N64?), the stack_offset only needs to be
5109 adjusted when it has been used. */
5112 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5116 fprintf_unfiltered (gdb_stdlog
, "\n");
5119 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5121 /* Return adjusted stack pointer. */
5125 static enum return_value_convention
5126 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5127 struct type
*type
, struct regcache
*regcache
,
5128 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5130 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5132 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5134 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5135 if needed), as appropriate for the type. Composite results (struct,
5136 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5139 * A struct with only one or two floating point fields is returned in $f0
5140 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5143 * Any other composite results of at most 128 bits are returned in
5144 $2 (first 64 bits) and $3 (remainder, if necessary).
5146 * Larger composite results are handled by converting the function to a
5147 procedure with an implicit first parameter, which is a pointer to an area
5148 reserved by the caller to receive the result. [The o32-bit ABI requires
5149 that all composite results be handled by conversion to implicit first
5150 parameters. The MIPS/SGI Fortran implementation has always made a
5151 specific exception to return COMPLEX results in the floating point
5154 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5155 return RETURN_VALUE_STRUCT_CONVENTION
;
5156 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5157 && TYPE_LENGTH (type
) == 16
5158 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5160 /* A 128-bit floating-point value fills both $f0 and $f2. The
5161 two registers are used in the same as memory order, so the
5162 eight bytes with the lower memory address are in $f0. */
5164 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5165 mips_xfer_register (gdbarch
, regcache
,
5166 (gdbarch_num_regs (gdbarch
)
5167 + mips_regnum (gdbarch
)->fp0
),
5168 8, gdbarch_byte_order (gdbarch
),
5169 readbuf
, writebuf
, 0);
5170 mips_xfer_register (gdbarch
, regcache
,
5171 (gdbarch_num_regs (gdbarch
)
5172 + mips_regnum (gdbarch
)->fp0
+ 2),
5173 8, gdbarch_byte_order (gdbarch
),
5174 readbuf
? readbuf
+ 8 : readbuf
,
5175 writebuf
? writebuf
+ 8 : writebuf
, 0);
5176 return RETURN_VALUE_REGISTER_CONVENTION
;
5178 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5179 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5181 /* A single or double floating-point value that fits in FP0. */
5183 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5184 mips_xfer_register (gdbarch
, regcache
,
5185 (gdbarch_num_regs (gdbarch
)
5186 + mips_regnum (gdbarch
)->fp0
),
5188 gdbarch_byte_order (gdbarch
),
5189 readbuf
, writebuf
, 0);
5190 return RETURN_VALUE_REGISTER_CONVENTION
;
5192 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5193 && TYPE_NFIELDS (type
) <= 2
5194 && TYPE_NFIELDS (type
) >= 1
5195 && ((TYPE_NFIELDS (type
) == 1
5196 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5198 || (TYPE_NFIELDS (type
) == 2
5199 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5201 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
5202 == TYPE_CODE_FLT
))))
5204 /* A struct that contains one or two floats. Each value is part
5205 in the least significant part of their floating point
5206 register (or GPR, for soft float). */
5209 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5210 ? mips_regnum (gdbarch
)->fp0
5212 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5214 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5217 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5219 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5221 /* A 16-byte long double field goes in two consecutive
5223 mips_xfer_register (gdbarch
, regcache
,
5224 gdbarch_num_regs (gdbarch
) + regnum
,
5226 gdbarch_byte_order (gdbarch
),
5227 readbuf
, writebuf
, offset
);
5228 mips_xfer_register (gdbarch
, regcache
,
5229 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5231 gdbarch_byte_order (gdbarch
),
5232 readbuf
, writebuf
, offset
+ 8);
5235 mips_xfer_register (gdbarch
, regcache
,
5236 gdbarch_num_regs (gdbarch
) + regnum
,
5237 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5238 gdbarch_byte_order (gdbarch
),
5239 readbuf
, writebuf
, offset
);
5241 return RETURN_VALUE_REGISTER_CONVENTION
;
5243 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5244 || TYPE_CODE (type
) == TYPE_CODE_UNION
5245 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5247 /* A composite type. Extract the left justified value,
5248 regardless of the byte order. I.e. DO NOT USE
5252 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5253 offset
< TYPE_LENGTH (type
);
5254 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5256 int xfer
= register_size (gdbarch
, regnum
);
5257 if (offset
+ xfer
> TYPE_LENGTH (type
))
5258 xfer
= TYPE_LENGTH (type
) - offset
;
5260 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5261 offset
, xfer
, regnum
);
5262 mips_xfer_register (gdbarch
, regcache
,
5263 gdbarch_num_regs (gdbarch
) + regnum
,
5264 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5267 return RETURN_VALUE_REGISTER_CONVENTION
;
5271 /* A scalar extract each part but least-significant-byte
5275 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5276 offset
< TYPE_LENGTH (type
);
5277 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5279 int xfer
= register_size (gdbarch
, regnum
);
5280 if (offset
+ xfer
> TYPE_LENGTH (type
))
5281 xfer
= TYPE_LENGTH (type
) - offset
;
5283 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5284 offset
, xfer
, regnum
);
5285 mips_xfer_register (gdbarch
, regcache
,
5286 gdbarch_num_regs (gdbarch
) + regnum
,
5287 xfer
, gdbarch_byte_order (gdbarch
),
5288 readbuf
, writebuf
, offset
);
5290 return RETURN_VALUE_REGISTER_CONVENTION
;
5294 /* Which registers to use for passing floating-point values between
5295 function calls, one of floating-point, general and both kinds of
5296 registers. O32 and O64 use different register kinds for standard
5297 MIPS and MIPS16 code; to make the handling of cases where we may
5298 not know what kind of code is being used (e.g. no debug information)
5299 easier we sometimes use both kinds. */
5308 /* O32 ABI stuff. */
5311 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5312 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5313 int nargs
, struct value
**args
, CORE_ADDR sp
,
5314 int struct_return
, CORE_ADDR struct_addr
)
5320 int stack_offset
= 0;
5321 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5322 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5324 /* For shared libraries, "t9" needs to point at the function
5326 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5328 /* Set the return address register to point to the entry point of
5329 the program, where a breakpoint lies in wait. */
5330 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5332 /* First ensure that the stack and structure return address (if any)
5333 are properly aligned. The stack has to be at least 64-bit
5334 aligned even on 32-bit machines, because doubles must be 64-bit
5335 aligned. For n32 and n64, stack frames need to be 128-bit
5336 aligned, so we round to this widest known alignment. */
5338 sp
= align_down (sp
, 16);
5339 struct_addr
= align_down (struct_addr
, 16);
5341 /* Now make space on the stack for the args. */
5342 for (argnum
= 0; argnum
< nargs
; argnum
++)
5344 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5346 /* Align to double-word if necessary. */
5347 if (mips_type_needs_double_align (arg_type
))
5348 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5349 /* Allocate space on the stack. */
5350 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5352 sp
-= align_up (len
, 16);
5355 fprintf_unfiltered (gdb_stdlog
,
5356 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5357 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5359 /* Initialize the integer and float register pointers. */
5360 argreg
= MIPS_A0_REGNUM
;
5361 float_argreg
= mips_fpa0_regnum (gdbarch
);
5363 /* The struct_return pointer occupies the first parameter-passing reg. */
5367 fprintf_unfiltered (gdb_stdlog
,
5368 "mips_o32_push_dummy_call: "
5369 "struct_return reg=%d %s\n",
5370 argreg
, paddress (gdbarch
, struct_addr
));
5371 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5372 stack_offset
+= MIPS32_REGSIZE
;
5375 /* Now load as many as possible of the first arguments into
5376 registers, and push the rest onto the stack. Loop thru args
5377 from first to last. */
5378 for (argnum
= 0; argnum
< nargs
; argnum
++)
5380 const gdb_byte
*val
;
5381 struct value
*arg
= args
[argnum
];
5382 struct type
*arg_type
= check_typedef (value_type (arg
));
5383 int len
= TYPE_LENGTH (arg_type
);
5384 enum type_code typecode
= TYPE_CODE (arg_type
);
5387 fprintf_unfiltered (gdb_stdlog
,
5388 "mips_o32_push_dummy_call: %d len=%d type=%d",
5389 argnum
+ 1, len
, (int) typecode
);
5391 val
= value_contents (arg
);
5393 /* 32-bit ABIs always start floating point arguments in an
5394 even-numbered floating point register. Round the FP register
5395 up before the check to see if there are any FP registers
5396 left. O32 targets also pass the FP in the integer registers
5397 so also round up normal registers. */
5398 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5400 if ((float_argreg
& 1))
5404 /* Floating point arguments passed in registers have to be
5405 treated specially. On 32-bit architectures, doubles are
5406 passed in register pairs; the even FP register gets the
5407 low word, and the odd FP register gets the high word.
5408 On O32, the first two floating point arguments are also
5409 copied to general registers, following their memory order,
5410 because MIPS16 functions don't use float registers for
5411 arguments. This duplication of arguments in general
5412 registers can't hurt non-MIPS16 functions, because those
5413 registers are normally skipped. */
5415 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5416 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5418 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5420 int freg_offset
= gdbarch_byte_order (gdbarch
)
5421 == BFD_ENDIAN_BIG
? 1 : 0;
5422 unsigned long regval
;
5425 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5427 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5428 float_argreg
+ freg_offset
,
5430 regcache_cooked_write_unsigned (regcache
,
5431 float_argreg
++ + freg_offset
,
5434 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5435 argreg
, phex (regval
, 4));
5436 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5439 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5441 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5442 float_argreg
- freg_offset
,
5444 regcache_cooked_write_unsigned (regcache
,
5445 float_argreg
++ - freg_offset
,
5448 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5449 argreg
, phex (regval
, 4));
5450 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5454 /* This is a floating point value that fits entirely
5455 in a single register. */
5456 /* On 32 bit ABI's the float_argreg is further adjusted
5457 above to ensure that it is even register aligned. */
5458 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5460 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5461 float_argreg
, phex (regval
, len
));
5462 regcache_cooked_write_unsigned (regcache
,
5463 float_argreg
++, regval
);
5464 /* Although two FP registers are reserved for each
5465 argument, only one corresponding integer register is
5468 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5469 argreg
, phex (regval
, len
));
5470 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5472 /* Reserve space for the FP register. */
5473 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5477 /* Copy the argument to general registers or the stack in
5478 register-sized pieces. Large arguments are split between
5479 registers and stack. */
5480 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5481 are treated specially: Irix cc passes
5482 them in registers where gcc sometimes puts them on the
5483 stack. For maximum compatibility, we will put them in
5485 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5486 && len
% MIPS32_REGSIZE
!= 0);
5487 /* Structures should be aligned to eight bytes (even arg registers)
5488 on MIPS_ABI_O32, if their first member has double precision. */
5489 if (mips_type_needs_double_align (arg_type
))
5494 stack_offset
+= MIPS32_REGSIZE
;
5499 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5502 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5505 /* Write this portion of the argument to the stack. */
5506 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5507 || odd_sized_struct
)
5509 /* Should shorter than int integer values be
5510 promoted to int before being stored? */
5511 int longword_offset
= 0;
5516 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5517 paddress (gdbarch
, stack_offset
));
5518 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5519 paddress (gdbarch
, longword_offset
));
5522 addr
= sp
+ stack_offset
+ longword_offset
;
5527 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5528 paddress (gdbarch
, addr
));
5529 for (i
= 0; i
< partial_len
; i
++)
5531 fprintf_unfiltered (gdb_stdlog
, "%02x",
5535 write_memory (addr
, val
, partial_len
);
5538 /* Note!!! This is NOT an else clause. Odd sized
5539 structs may go thru BOTH paths. */
5540 /* Write this portion of the argument to a general
5541 purpose register. */
5542 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5544 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5546 /* Value may need to be sign extended, because
5547 mips_isa_regsize() != mips_abi_regsize(). */
5549 /* A non-floating-point argument being passed in a
5550 general register. If a struct or union, and if
5551 the remaining length is smaller than the register
5552 size, we have to adjust the register value on
5555 It does not seem to be necessary to do the
5556 same for integral types.
5558 Also don't do this adjustment on O64 binaries.
5560 cagney/2001-07-23: gdb/179: Also, GCC, when
5561 outputting LE O32 with sizeof (struct) <
5562 mips_abi_regsize(), generates a left shift
5563 as part of storing the argument in a register
5564 (the left shift isn't generated when
5565 sizeof (struct) >= mips_abi_regsize()). Since
5566 it is quite possible that this is GCC
5567 contradicting the LE/O32 ABI, GDB has not been
5568 adjusted to accommodate this. Either someone
5569 needs to demonstrate that the LE/O32 ABI
5570 specifies such a left shift OR this new ABI gets
5571 identified as such and GDB gets tweaked
5574 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5575 && partial_len
< MIPS32_REGSIZE
5576 && (typecode
== TYPE_CODE_STRUCT
5577 || typecode
== TYPE_CODE_UNION
))
5578 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5582 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5584 phex (regval
, MIPS32_REGSIZE
));
5585 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5588 /* Prevent subsequent floating point arguments from
5589 being passed in floating point registers. */
5590 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5596 /* Compute the offset into the stack at which we will
5597 copy the next parameter.
5599 In older ABIs, the caller reserved space for
5600 registers that contained arguments. This was loosely
5601 refered to as their "home". Consequently, space is
5602 always allocated. */
5604 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5608 fprintf_unfiltered (gdb_stdlog
, "\n");
5611 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5613 /* Return adjusted stack pointer. */
5617 static enum return_value_convention
5618 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5619 struct type
*type
, struct regcache
*regcache
,
5620 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5622 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5623 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5624 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5625 enum mips_fval_reg fval_reg
;
5627 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5628 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5629 || TYPE_CODE (type
) == TYPE_CODE_UNION
5630 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5631 return RETURN_VALUE_STRUCT_CONVENTION
;
5632 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5633 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5635 /* A single-precision floating-point value. If reading in or copying,
5636 then we get it from/put it to FP0 for standard MIPS code or GPR2
5637 for MIPS16 code. If writing out only, then we put it to both FP0
5638 and GPR2. We do not support reading in with no function known, if
5639 this safety check ever triggers, then we'll have to try harder. */
5640 gdb_assert (function
|| !readbuf
);
5645 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5648 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5650 case mips_fval_both
:
5651 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5654 if (fval_reg
!= mips_fval_gpr
)
5655 mips_xfer_register (gdbarch
, regcache
,
5656 (gdbarch_num_regs (gdbarch
)
5657 + mips_regnum (gdbarch
)->fp0
),
5659 gdbarch_byte_order (gdbarch
),
5660 readbuf
, writebuf
, 0);
5661 if (fval_reg
!= mips_fval_fpr
)
5662 mips_xfer_register (gdbarch
, regcache
,
5663 gdbarch_num_regs (gdbarch
) + 2,
5665 gdbarch_byte_order (gdbarch
),
5666 readbuf
, writebuf
, 0);
5667 return RETURN_VALUE_REGISTER_CONVENTION
;
5669 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5670 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5672 /* A double-precision floating-point value. If reading in or copying,
5673 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5674 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5675 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5676 no function known, if this safety check ever triggers, then we'll
5677 have to try harder. */
5678 gdb_assert (function
|| !readbuf
);
5683 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5686 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5688 case mips_fval_both
:
5689 fprintf_unfiltered (gdb_stderr
,
5690 "Return float in $fp1/$fp0 and $2/$3\n");
5693 if (fval_reg
!= mips_fval_gpr
)
5695 /* The most significant part goes in FP1, and the least significant
5697 switch (gdbarch_byte_order (gdbarch
))
5699 case BFD_ENDIAN_LITTLE
:
5700 mips_xfer_register (gdbarch
, regcache
,
5701 (gdbarch_num_regs (gdbarch
)
5702 + mips_regnum (gdbarch
)->fp0
+ 0),
5703 4, gdbarch_byte_order (gdbarch
),
5704 readbuf
, writebuf
, 0);
5705 mips_xfer_register (gdbarch
, regcache
,
5706 (gdbarch_num_regs (gdbarch
)
5707 + mips_regnum (gdbarch
)->fp0
+ 1),
5708 4, gdbarch_byte_order (gdbarch
),
5709 readbuf
, writebuf
, 4);
5711 case BFD_ENDIAN_BIG
:
5712 mips_xfer_register (gdbarch
, regcache
,
5713 (gdbarch_num_regs (gdbarch
)
5714 + mips_regnum (gdbarch
)->fp0
+ 1),
5715 4, gdbarch_byte_order (gdbarch
),
5716 readbuf
, writebuf
, 0);
5717 mips_xfer_register (gdbarch
, regcache
,
5718 (gdbarch_num_regs (gdbarch
)
5719 + mips_regnum (gdbarch
)->fp0
+ 0),
5720 4, gdbarch_byte_order (gdbarch
),
5721 readbuf
, writebuf
, 4);
5724 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5727 if (fval_reg
!= mips_fval_fpr
)
5729 /* The two 32-bit parts are always placed in GPR2 and GPR3
5730 following these registers' memory order. */
5731 mips_xfer_register (gdbarch
, regcache
,
5732 gdbarch_num_regs (gdbarch
) + 2,
5733 4, gdbarch_byte_order (gdbarch
),
5734 readbuf
, writebuf
, 0);
5735 mips_xfer_register (gdbarch
, regcache
,
5736 gdbarch_num_regs (gdbarch
) + 3,
5737 4, gdbarch_byte_order (gdbarch
),
5738 readbuf
, writebuf
, 4);
5740 return RETURN_VALUE_REGISTER_CONVENTION
;
5743 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5744 && TYPE_NFIELDS (type
) <= 2
5745 && TYPE_NFIELDS (type
) >= 1
5746 && ((TYPE_NFIELDS (type
) == 1
5747 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5749 || (TYPE_NFIELDS (type
) == 2
5750 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5752 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5754 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5756 /* A struct that contains one or two floats. Each value is part
5757 in the least significant part of their floating point
5759 gdb_byte reg
[MAX_REGISTER_SIZE
];
5762 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5763 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5765 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5768 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5770 mips_xfer_register (gdbarch
, regcache
,
5771 gdbarch_num_regs (gdbarch
) + regnum
,
5772 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5773 gdbarch_byte_order (gdbarch
),
5774 readbuf
, writebuf
, offset
);
5776 return RETURN_VALUE_REGISTER_CONVENTION
;
5780 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5781 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5783 /* A structure or union. Extract the left justified value,
5784 regardless of the byte order. I.e. DO NOT USE
5788 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5789 offset
< TYPE_LENGTH (type
);
5790 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5792 int xfer
= register_size (gdbarch
, regnum
);
5793 if (offset
+ xfer
> TYPE_LENGTH (type
))
5794 xfer
= TYPE_LENGTH (type
) - offset
;
5796 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5797 offset
, xfer
, regnum
);
5798 mips_xfer_register (gdbarch
, regcache
,
5799 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5800 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5802 return RETURN_VALUE_REGISTER_CONVENTION
;
5807 /* A scalar extract each part but least-significant-byte
5808 justified. o32 thinks registers are 4 byte, regardless of
5812 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5813 offset
< TYPE_LENGTH (type
);
5814 offset
+= MIPS32_REGSIZE
, regnum
++)
5816 int xfer
= MIPS32_REGSIZE
;
5817 if (offset
+ xfer
> TYPE_LENGTH (type
))
5818 xfer
= TYPE_LENGTH (type
) - offset
;
5820 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5821 offset
, xfer
, regnum
);
5822 mips_xfer_register (gdbarch
, regcache
,
5823 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5824 gdbarch_byte_order (gdbarch
),
5825 readbuf
, writebuf
, offset
);
5827 return RETURN_VALUE_REGISTER_CONVENTION
;
5831 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5835 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5836 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5838 struct value
**args
, CORE_ADDR sp
,
5839 int struct_return
, CORE_ADDR struct_addr
)
5845 int stack_offset
= 0;
5846 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5847 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5849 /* For shared libraries, "t9" needs to point at the function
5851 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5853 /* Set the return address register to point to the entry point of
5854 the program, where a breakpoint lies in wait. */
5855 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5857 /* First ensure that the stack and structure return address (if any)
5858 are properly aligned. The stack has to be at least 64-bit
5859 aligned even on 32-bit machines, because doubles must be 64-bit
5860 aligned. For n32 and n64, stack frames need to be 128-bit
5861 aligned, so we round to this widest known alignment. */
5863 sp
= align_down (sp
, 16);
5864 struct_addr
= align_down (struct_addr
, 16);
5866 /* Now make space on the stack for the args. */
5867 for (argnum
= 0; argnum
< nargs
; argnum
++)
5869 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5871 /* Allocate space on the stack. */
5872 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5874 sp
-= align_up (len
, 16);
5877 fprintf_unfiltered (gdb_stdlog
,
5878 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5879 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5881 /* Initialize the integer and float register pointers. */
5882 argreg
= MIPS_A0_REGNUM
;
5883 float_argreg
= mips_fpa0_regnum (gdbarch
);
5885 /* The struct_return pointer occupies the first parameter-passing reg. */
5889 fprintf_unfiltered (gdb_stdlog
,
5890 "mips_o64_push_dummy_call: "
5891 "struct_return reg=%d %s\n",
5892 argreg
, paddress (gdbarch
, struct_addr
));
5893 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5894 stack_offset
+= MIPS64_REGSIZE
;
5897 /* Now load as many as possible of the first arguments into
5898 registers, and push the rest onto the stack. Loop thru args
5899 from first to last. */
5900 for (argnum
= 0; argnum
< nargs
; argnum
++)
5902 const gdb_byte
*val
;
5903 struct value
*arg
= args
[argnum
];
5904 struct type
*arg_type
= check_typedef (value_type (arg
));
5905 int len
= TYPE_LENGTH (arg_type
);
5906 enum type_code typecode
= TYPE_CODE (arg_type
);
5909 fprintf_unfiltered (gdb_stdlog
,
5910 "mips_o64_push_dummy_call: %d len=%d type=%d",
5911 argnum
+ 1, len
, (int) typecode
);
5913 val
= value_contents (arg
);
5915 /* Floating point arguments passed in registers have to be
5916 treated specially. On 32-bit architectures, doubles are
5917 passed in register pairs; the even FP register gets the
5918 low word, and the odd FP register gets the high word.
5919 On O64, the first two floating point arguments are also
5920 copied to general registers, because MIPS16 functions
5921 don't use float registers for arguments. This duplication
5922 of arguments in general registers can't hurt non-MIPS16
5923 functions because those registers are normally skipped. */
5925 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5926 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5928 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5930 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5931 float_argreg
, phex (regval
, len
));
5932 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5934 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5935 argreg
, phex (regval
, len
));
5936 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5938 /* Reserve space for the FP register. */
5939 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5943 /* Copy the argument to general registers or the stack in
5944 register-sized pieces. Large arguments are split between
5945 registers and stack. */
5946 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5947 are treated specially: Irix cc passes them in registers
5948 where gcc sometimes puts them on the stack. For maximum
5949 compatibility, we will put them in both places. */
5950 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5951 && len
% MIPS64_REGSIZE
!= 0);
5954 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5957 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5960 /* Write this portion of the argument to the stack. */
5961 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5962 || odd_sized_struct
)
5964 /* Should shorter than int integer values be
5965 promoted to int before being stored? */
5966 int longword_offset
= 0;
5968 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5970 if ((typecode
== TYPE_CODE_INT
5971 || typecode
== TYPE_CODE_PTR
5972 || typecode
== TYPE_CODE_FLT
)
5974 longword_offset
= MIPS64_REGSIZE
- len
;
5979 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5980 paddress (gdbarch
, stack_offset
));
5981 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5982 paddress (gdbarch
, longword_offset
));
5985 addr
= sp
+ stack_offset
+ longword_offset
;
5990 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5991 paddress (gdbarch
, addr
));
5992 for (i
= 0; i
< partial_len
; i
++)
5994 fprintf_unfiltered (gdb_stdlog
, "%02x",
5998 write_memory (addr
, val
, partial_len
);
6001 /* Note!!! This is NOT an else clause. Odd sized
6002 structs may go thru BOTH paths. */
6003 /* Write this portion of the argument to a general
6004 purpose register. */
6005 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
6007 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6009 /* Value may need to be sign extended, because
6010 mips_isa_regsize() != mips_abi_regsize(). */
6012 /* A non-floating-point argument being passed in a
6013 general register. If a struct or union, and if
6014 the remaining length is smaller than the register
6015 size, we have to adjust the register value on
6018 It does not seem to be necessary to do the
6019 same for integral types. */
6021 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6022 && partial_len
< MIPS64_REGSIZE
6023 && (typecode
== TYPE_CODE_STRUCT
6024 || typecode
== TYPE_CODE_UNION
))
6025 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6029 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
6031 phex (regval
, MIPS64_REGSIZE
));
6032 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6035 /* Prevent subsequent floating point arguments from
6036 being passed in floating point registers. */
6037 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
6043 /* Compute the offset into the stack at which we will
6044 copy the next parameter.
6046 In older ABIs, the caller reserved space for
6047 registers that contained arguments. This was loosely
6048 refered to as their "home". Consequently, space is
6049 always allocated. */
6051 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6055 fprintf_unfiltered (gdb_stdlog
, "\n");
6058 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6060 /* Return adjusted stack pointer. */
6064 static enum return_value_convention
6065 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6066 struct type
*type
, struct regcache
*regcache
,
6067 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6069 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6070 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6071 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6072 enum mips_fval_reg fval_reg
;
6074 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6075 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
6076 || TYPE_CODE (type
) == TYPE_CODE_UNION
6077 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
6078 return RETURN_VALUE_STRUCT_CONVENTION
;
6079 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
6081 /* A floating-point value. If reading in or copying, then we get it
6082 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6083 If writing out only, then we put it to both FP0 and GPR2. We do
6084 not support reading in with no function known, if this safety
6085 check ever triggers, then we'll have to try harder. */
6086 gdb_assert (function
|| !readbuf
);
6091 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6094 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6096 case mips_fval_both
:
6097 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6100 if (fval_reg
!= mips_fval_gpr
)
6101 mips_xfer_register (gdbarch
, regcache
,
6102 (gdbarch_num_regs (gdbarch
)
6103 + mips_regnum (gdbarch
)->fp0
),
6105 gdbarch_byte_order (gdbarch
),
6106 readbuf
, writebuf
, 0);
6107 if (fval_reg
!= mips_fval_fpr
)
6108 mips_xfer_register (gdbarch
, regcache
,
6109 gdbarch_num_regs (gdbarch
) + 2,
6111 gdbarch_byte_order (gdbarch
),
6112 readbuf
, writebuf
, 0);
6113 return RETURN_VALUE_REGISTER_CONVENTION
;
6117 /* A scalar extract each part but least-significant-byte
6121 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6122 offset
< TYPE_LENGTH (type
);
6123 offset
+= MIPS64_REGSIZE
, regnum
++)
6125 int xfer
= MIPS64_REGSIZE
;
6126 if (offset
+ xfer
> TYPE_LENGTH (type
))
6127 xfer
= TYPE_LENGTH (type
) - offset
;
6129 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6130 offset
, xfer
, regnum
);
6131 mips_xfer_register (gdbarch
, regcache
,
6132 gdbarch_num_regs (gdbarch
) + regnum
,
6133 xfer
, gdbarch_byte_order (gdbarch
),
6134 readbuf
, writebuf
, offset
);
6136 return RETURN_VALUE_REGISTER_CONVENTION
;
6140 /* Floating point register management.
6142 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6143 64bit operations, these early MIPS cpus treat fp register pairs
6144 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6145 registers and offer a compatibility mode that emulates the MIPS2 fp
6146 model. When operating in MIPS2 fp compat mode, later cpu's split
6147 double precision floats into two 32-bit chunks and store them in
6148 consecutive fp regs. To display 64-bit floats stored in this
6149 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6150 Throw in user-configurable endianness and you have a real mess.
6152 The way this works is:
6153 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6154 double-precision value will be split across two logical registers.
6155 The lower-numbered logical register will hold the low-order bits,
6156 regardless of the processor's endianness.
6157 - If we are on a 64-bit processor, and we are looking for a
6158 single-precision value, it will be in the low ordered bits
6159 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6160 save slot in memory.
6161 - If we are in 64-bit mode, everything is straightforward.
6163 Note that this code only deals with "live" registers at the top of the
6164 stack. We will attempt to deal with saved registers later, when
6165 the raw/cooked register interface is in place. (We need a general
6166 interface that can deal with dynamic saved register sizes -- fp
6167 regs could be 32 bits wide in one frame and 64 on the frame above
6170 /* Copy a 32-bit single-precision value from the current frame
6171 into rare_buffer. */
6174 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6175 gdb_byte
*rare_buffer
)
6177 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6178 int raw_size
= register_size (gdbarch
, regno
);
6179 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6181 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6182 error (_("can't read register %d (%s)"),
6183 regno
, gdbarch_register_name (gdbarch
, regno
));
6186 /* We have a 64-bit value for this register. Find the low-order
6190 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6195 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6199 memcpy (rare_buffer
, raw_buffer
, 4);
6203 /* Copy a 64-bit double-precision value from the current frame into
6204 rare_buffer. This may include getting half of it from the next
6208 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6209 gdb_byte
*rare_buffer
)
6211 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6212 int raw_size
= register_size (gdbarch
, regno
);
6214 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6216 /* We have a 64-bit value for this register, and we should use
6218 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6219 error (_("can't read register %d (%s)"),
6220 regno
, gdbarch_register_name (gdbarch
, regno
));
6224 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6226 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6227 internal_error (__FILE__
, __LINE__
,
6228 _("mips_read_fp_register_double: bad access to "
6229 "odd-numbered FP register"));
6231 /* mips_read_fp_register_single will find the correct 32 bits from
6233 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6235 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6236 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6240 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6241 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6247 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6249 { /* Do values for FP (float) regs. */
6250 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6251 gdb_byte
*raw_buffer
;
6252 double doub
, flt1
; /* Doubles extracted from raw hex data. */
6257 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6259 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6260 fprintf_filtered (file
, "%*s",
6261 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6264 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6266 struct value_print_options opts
;
6268 /* 4-byte registers: Print hex and floating. Also print even
6269 numbered registers as doubles. */
6270 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6271 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6274 get_formatted_print_options (&opts
, 'x');
6275 print_scalar_formatted (raw_buffer
,
6276 builtin_type (gdbarch
)->builtin_uint32
,
6279 fprintf_filtered (file
, " flt: ");
6281 fprintf_filtered (file
, " <invalid float> ");
6283 fprintf_filtered (file
, "%-17.9g", flt1
);
6285 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6287 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6288 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6291 fprintf_filtered (file
, " dbl: ");
6293 fprintf_filtered (file
, "<invalid double>");
6295 fprintf_filtered (file
, "%-24.17g", doub
);
6300 struct value_print_options opts
;
6302 /* Eight byte registers: print each one as hex, float and double. */
6303 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6304 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6307 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6308 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6311 get_formatted_print_options (&opts
, 'x');
6312 print_scalar_formatted (raw_buffer
,
6313 builtin_type (gdbarch
)->builtin_uint64
,
6316 fprintf_filtered (file
, " flt: ");
6318 fprintf_filtered (file
, "<invalid float>");
6320 fprintf_filtered (file
, "%-17.9g", flt1
);
6322 fprintf_filtered (file
, " dbl: ");
6324 fprintf_filtered (file
, "<invalid double>");
6326 fprintf_filtered (file
, "%-24.17g", doub
);
6331 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6334 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6335 struct value_print_options opts
;
6338 if (mips_float_register_p (gdbarch
, regnum
))
6340 mips_print_fp_register (file
, frame
, regnum
);
6344 val
= get_frame_register_value (frame
, regnum
);
6346 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6348 /* The problem with printing numeric register names (r26, etc.) is that
6349 the user can't use them on input. Probably the best solution is to
6350 fix it so that either the numeric or the funky (a2, etc.) names
6351 are accepted on input. */
6352 if (regnum
< MIPS_NUMREGS
)
6353 fprintf_filtered (file
, "(r%d): ", regnum
);
6355 fprintf_filtered (file
, ": ");
6357 get_formatted_print_options (&opts
, 'x');
6358 val_print_scalar_formatted (value_type (val
),
6359 value_contents_for_printing (val
),
6360 value_embedded_offset (val
),
6365 /* Print IEEE exception condition bits in FLAGS. */
6368 print_fpu_flags (struct ui_file
*file
, int flags
)
6370 if (flags
& (1 << 0))
6371 fputs_filtered (" inexact", file
);
6372 if (flags
& (1 << 1))
6373 fputs_filtered (" uflow", file
);
6374 if (flags
& (1 << 2))
6375 fputs_filtered (" oflow", file
);
6376 if (flags
& (1 << 3))
6377 fputs_filtered (" div0", file
);
6378 if (flags
& (1 << 4))
6379 fputs_filtered (" inval", file
);
6380 if (flags
& (1 << 5))
6381 fputs_filtered (" unimp", file
);
6382 fputc_filtered ('\n', file
);
6385 /* Print interesting information about the floating point processor
6386 (if present) or emulator. */
6389 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6390 struct frame_info
*frame
, const char *args
)
6392 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6393 enum mips_fpu_type type
= MIPS_FPU_TYPE (gdbarch
);
6397 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6398 type
= MIPS_FPU_NONE
;
6400 fprintf_filtered (file
, "fpu type: %s\n",
6401 type
== MIPS_FPU_DOUBLE
? "double-precision"
6402 : type
== MIPS_FPU_SINGLE
? "single-precision"
6405 if (type
== MIPS_FPU_NONE
)
6408 fprintf_filtered (file
, "reg size: %d bits\n",
6409 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6411 fputs_filtered ("cond :", file
);
6412 if (fcs
& (1 << 23))
6413 fputs_filtered (" 0", file
);
6414 for (i
= 1; i
<= 7; i
++)
6415 if (fcs
& (1 << (24 + i
)))
6416 fprintf_filtered (file
, " %d", i
);
6417 fputc_filtered ('\n', file
);
6419 fputs_filtered ("cause :", file
);
6420 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6421 fputs ("mask :", stdout
);
6422 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6423 fputs ("flags :", stdout
);
6424 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6426 fputs_filtered ("rounding: ", file
);
6429 case 0: fputs_filtered ("nearest\n", file
); break;
6430 case 1: fputs_filtered ("zero\n", file
); break;
6431 case 2: fputs_filtered ("+inf\n", file
); break;
6432 case 3: fputs_filtered ("-inf\n", file
); break;
6435 fputs_filtered ("flush :", file
);
6436 if (fcs
& (1 << 21))
6437 fputs_filtered (" nearest", file
);
6438 if (fcs
& (1 << 22))
6439 fputs_filtered (" override", file
);
6440 if (fcs
& (1 << 24))
6441 fputs_filtered (" zero", file
);
6442 if ((fcs
& (0xb << 21)) == 0)
6443 fputs_filtered (" no", file
);
6444 fputc_filtered ('\n', file
);
6446 fprintf_filtered (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6447 fprintf_filtered (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6448 fputc_filtered ('\n', file
);
6450 default_print_float_info (gdbarch
, file
, frame
, args
);
6453 /* Replacement for generic do_registers_info.
6454 Print regs in pretty columns. */
6457 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6460 fprintf_filtered (file
, " ");
6461 mips_print_fp_register (file
, frame
, regnum
);
6462 fprintf_filtered (file
, "\n");
6467 /* Print a row's worth of GP (int) registers, with name labels above. */
6470 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6473 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6474 /* Do values for GP (int) regs. */
6475 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
6476 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6481 /* For GP registers, we print a separate row of names above the vals. */
6482 for (col
= 0, regnum
= start_regnum
;
6483 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6484 + gdbarch_num_pseudo_regs (gdbarch
);
6487 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6488 continue; /* unused register */
6489 if (mips_float_register_p (gdbarch
, regnum
))
6490 break; /* End the row: reached FP register. */
6491 /* Large registers are handled separately. */
6492 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6495 break; /* End the row before this register. */
6497 /* Print this register on a row by itself. */
6498 mips_print_register (file
, frame
, regnum
);
6499 fprintf_filtered (file
, "\n");
6503 fprintf_filtered (file
, " ");
6504 fprintf_filtered (file
,
6505 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6506 gdbarch_register_name (gdbarch
, regnum
));
6513 /* Print the R0 to R31 names. */
6514 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6515 fprintf_filtered (file
, "\n R%-4d",
6516 start_regnum
% gdbarch_num_regs (gdbarch
));
6518 fprintf_filtered (file
, "\n ");
6520 /* Now print the values in hex, 4 or 8 to the row. */
6521 for (col
= 0, regnum
= start_regnum
;
6522 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6523 + gdbarch_num_pseudo_regs (gdbarch
);
6526 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6527 continue; /* unused register */
6528 if (mips_float_register_p (gdbarch
, regnum
))
6529 break; /* End row: reached FP register. */
6530 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6531 break; /* End row: large register. */
6533 /* OK: get the data in raw format. */
6534 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
6535 error (_("can't read register %d (%s)"),
6536 regnum
, gdbarch_register_name (gdbarch
, regnum
));
6537 /* pad small registers */
6539 byte
< (mips_abi_regsize (gdbarch
)
6540 - register_size (gdbarch
, regnum
)); byte
++)
6541 printf_filtered (" ");
6542 /* Now print the register value in hex, endian order. */
6543 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6545 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6546 byte
< register_size (gdbarch
, regnum
); byte
++)
6547 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6549 for (byte
= register_size (gdbarch
, regnum
) - 1;
6551 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6552 fprintf_filtered (file
, " ");
6555 if (col
> 0) /* ie. if we actually printed anything... */
6556 fprintf_filtered (file
, "\n");
6561 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6564 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6565 struct frame_info
*frame
, int regnum
, int all
)
6567 if (regnum
!= -1) /* Do one specified register. */
6569 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6570 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6571 error (_("Not a valid register for the current processor type"));
6573 mips_print_register (file
, frame
, regnum
);
6574 fprintf_filtered (file
, "\n");
6577 /* Do all (or most) registers. */
6579 regnum
= gdbarch_num_regs (gdbarch
);
6580 while (regnum
< gdbarch_num_regs (gdbarch
)
6581 + gdbarch_num_pseudo_regs (gdbarch
))
6583 if (mips_float_register_p (gdbarch
, regnum
))
6585 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6586 regnum
= print_fp_register_row (file
, frame
, regnum
);
6588 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6591 regnum
= print_gp_register_row (file
, frame
, regnum
);
6597 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6598 struct frame_info
*frame
)
6600 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6601 CORE_ADDR pc
= get_frame_pc (frame
);
6602 struct address_space
*aspace
;
6608 if ((mips_pc_is_mips (pc
)
6609 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6610 || (mips_pc_is_micromips (gdbarch
, pc
)
6611 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6612 || (mips_pc_is_mips16 (gdbarch
, pc
)
6613 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6616 isa
= mips_pc_isa (gdbarch
, pc
);
6617 /* _has_delay_slot above will have validated the read. */
6618 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6619 size
= mips_insn_size (isa
, insn
);
6620 aspace
= get_frame_address_space (frame
);
6621 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6624 /* To skip prologues, I use this predicate. Returns either PC itself
6625 if the code at PC does not look like a function prologue; otherwise
6626 returns an address that (if we're lucky) follows the prologue. If
6627 LENIENT, then we must skip everything which is involved in setting
6628 up the frame (it's OK to skip more, just so long as we don't skip
6629 anything which might clobber the registers which are being saved.
6630 We must skip more in the case where part of the prologue is in the
6631 delay slot of a non-prologue instruction). */
6634 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6637 CORE_ADDR func_addr
;
6639 /* See if we can determine the end of the prologue via the symbol table.
6640 If so, then return either PC, or the PC after the prologue, whichever
6642 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6644 CORE_ADDR post_prologue_pc
6645 = skip_prologue_using_sal (gdbarch
, func_addr
);
6646 if (post_prologue_pc
!= 0)
6647 return std::max (pc
, post_prologue_pc
);
6650 /* Can't determine prologue from the symbol table, need to examine
6653 /* Find an upper limit on the function prologue using the debug
6654 information. If the debug information could not be used to provide
6655 that bound, then use an arbitrary large number as the upper bound. */
6656 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6658 limit_pc
= pc
+ 100; /* Magic. */
6660 if (mips_pc_is_mips16 (gdbarch
, pc
))
6661 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6662 else if (mips_pc_is_micromips (gdbarch
, pc
))
6663 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6665 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6668 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6669 This is a helper function for mips_stack_frame_destroyed_p. */
6672 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6674 CORE_ADDR func_addr
= 0, func_end
= 0;
6676 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6678 /* The MIPS epilogue is max. 12 bytes long. */
6679 CORE_ADDR addr
= func_end
- 12;
6681 if (addr
< func_addr
+ 4)
6682 addr
= func_addr
+ 4;
6686 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6688 unsigned long high_word
;
6691 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6692 high_word
= (inst
>> 16) & 0xffff;
6694 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6695 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6696 && inst
!= 0x03e00008 /* jr $ra */
6697 && inst
!= 0x00000000) /* nop */
6707 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6708 This is a helper function for mips_stack_frame_destroyed_p. */
6711 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6713 CORE_ADDR func_addr
= 0;
6714 CORE_ADDR func_end
= 0;
6722 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6725 /* The microMIPS epilogue is max. 12 bytes long. */
6726 addr
= func_end
- 12;
6728 if (addr
< func_addr
+ 2)
6729 addr
= func_addr
+ 2;
6733 for (; pc
< func_end
; pc
+= loc
)
6736 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6737 loc
+= MIPS_INSN16_SIZE
;
6738 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6740 /* 32-bit instructions. */
6741 case 2 * MIPS_INSN16_SIZE
:
6743 insn
|= mips_fetch_instruction (gdbarch
,
6744 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6745 loc
+= MIPS_INSN16_SIZE
;
6746 switch (micromips_op (insn
>> 16))
6748 case 0xc: /* ADDIU: bits 001100 */
6749 case 0x17: /* DADDIU: bits 010111 */
6750 sreg
= b0s5_reg (insn
>> 16);
6751 dreg
= b5s5_reg (insn
>> 16);
6752 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6753 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6754 /* (D)ADDIU $sp, imm */
6764 /* 16-bit instructions. */
6765 case MIPS_INSN16_SIZE
:
6766 switch (micromips_op (insn
))
6768 case 0x3: /* MOVE: bits 000011 */
6769 sreg
= b0s5_reg (insn
);
6770 dreg
= b5s5_reg (insn
);
6771 if (sreg
== 0 && dreg
== 0)
6772 /* MOVE $zero, $zero aka NOP */
6776 case 0x11: /* POOL16C: bits 010001 */
6777 if (b5s5_op (insn
) == 0x18
6778 /* JRADDIUSP: bits 010011 11000 */
6779 || (b5s5_op (insn
) == 0xd
6780 /* JRC: bits 010011 01101 */
6781 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6786 case 0x13: /* POOL16D: bits 010011 */
6787 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6788 if ((insn
& 0x1) == 0x1
6789 /* ADDIUSP: bits 010011 1 */
6803 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6804 This is a helper function for mips_stack_frame_destroyed_p. */
6807 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6809 CORE_ADDR func_addr
= 0, func_end
= 0;
6811 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6813 /* The MIPS epilogue is max. 12 bytes long. */
6814 CORE_ADDR addr
= func_end
- 12;
6816 if (addr
< func_addr
+ 4)
6817 addr
= func_addr
+ 4;
6821 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6823 unsigned short inst
;
6825 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6827 if ((inst
& 0xf800) == 0xf000) /* extend */
6830 if (inst
!= 0x6300 /* addiu $sp,offset */
6831 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6832 && inst
!= 0xe820 /* jr $ra */
6833 && inst
!= 0xe8a0 /* jrc $ra */
6834 && inst
!= 0x6500) /* nop */
6844 /* Implement the stack_frame_destroyed_p gdbarch method.
6846 The epilogue is defined here as the area at the end of a function,
6847 after an instruction which destroys the function's stack frame. */
6850 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6852 if (mips_pc_is_mips16 (gdbarch
, pc
))
6853 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6854 else if (mips_pc_is_micromips (gdbarch
, pc
))
6855 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6857 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6860 /* Root of all "set mips "/"show mips " commands. This will eventually be
6861 used for all MIPS-specific commands. */
6864 show_mips_command (char *args
, int from_tty
)
6866 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6870 set_mips_command (char *args
, int from_tty
)
6873 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6874 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6877 /* Commands to show/set the MIPS FPU type. */
6880 show_mipsfpu_command (char *args
, int from_tty
)
6884 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6887 ("The MIPS floating-point coprocessor is unknown "
6888 "because the current architecture is not MIPS.\n");
6892 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6894 case MIPS_FPU_SINGLE
:
6895 fpu
= "single-precision";
6897 case MIPS_FPU_DOUBLE
:
6898 fpu
= "double-precision";
6901 fpu
= "absent (none)";
6904 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6906 if (mips_fpu_type_auto
)
6907 printf_unfiltered ("The MIPS floating-point coprocessor "
6908 "is set automatically (currently %s)\n",
6912 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6917 set_mipsfpu_command (char *args
, int from_tty
)
6919 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6920 "\"single\",\"none\" or \"auto\".\n");
6921 show_mipsfpu_command (args
, from_tty
);
6925 set_mipsfpu_single_command (char *args
, int from_tty
)
6927 struct gdbarch_info info
;
6928 gdbarch_info_init (&info
);
6929 mips_fpu_type
= MIPS_FPU_SINGLE
;
6930 mips_fpu_type_auto
= 0;
6931 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6932 instead of relying on globals. Doing that would let generic code
6933 handle the search for this specific architecture. */
6934 if (!gdbarch_update_p (info
))
6935 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6939 set_mipsfpu_double_command (char *args
, int from_tty
)
6941 struct gdbarch_info info
;
6942 gdbarch_info_init (&info
);
6943 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6944 mips_fpu_type_auto
= 0;
6945 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6946 instead of relying on globals. Doing that would let generic code
6947 handle the search for this specific architecture. */
6948 if (!gdbarch_update_p (info
))
6949 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6953 set_mipsfpu_none_command (char *args
, int from_tty
)
6955 struct gdbarch_info info
;
6956 gdbarch_info_init (&info
);
6957 mips_fpu_type
= MIPS_FPU_NONE
;
6958 mips_fpu_type_auto
= 0;
6959 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6960 instead of relying on globals. Doing that would let generic code
6961 handle the search for this specific architecture. */
6962 if (!gdbarch_update_p (info
))
6963 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6967 set_mipsfpu_auto_command (char *args
, int from_tty
)
6969 mips_fpu_type_auto
= 1;
6972 /* Just like reinit_frame_cache, but with the right arguments to be
6973 callable as an sfunc. */
6976 reinit_frame_cache_sfunc (char *args
, int from_tty
,
6977 struct cmd_list_element
*c
)
6979 reinit_frame_cache ();
6983 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6985 struct gdbarch
*gdbarch
= (struct gdbarch
*) info
->application_data
;
6987 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6988 disassembler needs to be able to locally determine the ISA, and
6989 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6991 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6992 info
->mach
= bfd_mach_mips16
;
6993 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6994 info
->mach
= bfd_mach_mips_micromips
;
6996 /* Round down the instruction address to the appropriate boundary. */
6997 memaddr
&= (info
->mach
== bfd_mach_mips16
6998 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7000 /* Set the disassembler options. */
7001 if (!info
->disassembler_options
)
7002 /* This string is not recognized explicitly by the disassembler,
7003 but it tells the disassembler to not try to guess the ABI from
7004 the bfd elf headers, such that, if the user overrides the ABI
7005 of a program linked as NewABI, the disassembly will follow the
7006 register naming conventions specified by the user. */
7007 info
->disassembler_options
= "gpr-names=32";
7009 /* Call the appropriate disassembler based on the target endian-ness. */
7010 if (info
->endian
== BFD_ENDIAN_BIG
)
7011 return print_insn_big_mips (memaddr
, info
);
7013 return print_insn_little_mips (memaddr
, info
);
7017 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
7019 /* Set up the disassembler info, so that we get the right
7020 register names from libopcodes. */
7021 info
->disassembler_options
= "gpr-names=n32";
7022 info
->flavour
= bfd_target_elf_flavour
;
7024 return gdb_print_insn_mips (memaddr
, info
);
7028 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
7030 /* Set up the disassembler info, so that we get the right
7031 register names from libopcodes. */
7032 info
->disassembler_options
= "gpr-names=64";
7033 info
->flavour
= bfd_target_elf_flavour
;
7035 return gdb_print_insn_mips (memaddr
, info
);
7038 /* This function implements gdbarch_breakpoint_from_pc. It uses the
7039 program counter value to determine whether a 16- or 32-bit breakpoint
7040 should be used. It returns a pointer to a string of bytes that encode a
7041 breakpoint instruction, stores the length of the string to *lenptr, and
7042 adjusts pc (if necessary) to point to the actual memory location where
7043 the breakpoint should be inserted. */
7045 static const gdb_byte
*
7046 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
7047 CORE_ADDR
*pcptr
, int *lenptr
)
7049 CORE_ADDR pc
= *pcptr
;
7051 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
7053 if (mips_pc_is_mips16 (gdbarch
, pc
))
7055 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7056 *pcptr
= unmake_compact_addr (pc
);
7057 *lenptr
= sizeof (mips16_big_breakpoint
);
7058 return mips16_big_breakpoint
;
7060 else if (mips_pc_is_micromips (gdbarch
, pc
))
7062 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7063 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7068 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &err
);
7069 size
= err
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
);
7070 *pcptr
= unmake_compact_addr (pc
);
7072 return (size
== 2) ? micromips16_big_breakpoint
7073 : micromips32_big_breakpoint
;
7077 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7079 *lenptr
= sizeof (big_breakpoint
);
7080 return big_breakpoint
;
7085 if (mips_pc_is_mips16 (gdbarch
, pc
))
7087 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7088 *pcptr
= unmake_compact_addr (pc
);
7089 *lenptr
= sizeof (mips16_little_breakpoint
);
7090 return mips16_little_breakpoint
;
7092 else if (mips_pc_is_micromips (gdbarch
, pc
))
7094 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7095 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7100 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &err
);
7101 size
= err
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
);
7102 *pcptr
= unmake_compact_addr (pc
);
7104 return (size
== 2) ? micromips16_little_breakpoint
7105 : micromips32_little_breakpoint
;
7109 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7111 *lenptr
= sizeof (little_breakpoint
);
7112 return little_breakpoint
;
7117 /* Determine the remote breakpoint kind suitable for the PC. */
7120 mips_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
7123 CORE_ADDR pc
= *pcptr
;
7125 if (mips_pc_is_mips16 (gdbarch
, pc
))
7127 *pcptr
= unmake_compact_addr (pc
);
7128 *kindptr
= MIPS_BP_KIND_MIPS16
;
7130 else if (mips_pc_is_micromips (gdbarch
, pc
))
7135 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7136 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7137 *kindptr
= MIPS_BP_KIND_MICROMIPS16
;
7139 *kindptr
= MIPS_BP_KIND_MICROMIPS32
;
7141 *pcptr
= unmake_compact_addr (pc
);
7144 *kindptr
= MIPS_BP_KIND_MIPS32
;
7147 /* Return non-zero if the standard MIPS instruction INST has a branch
7148 delay slot (i.e. it is a jump or branch instruction). This function
7149 is based on mips32_next_pc. */
7152 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7158 op
= itype_op (inst
);
7159 if ((inst
& 0xe0000000) != 0)
7161 rs
= itype_rs (inst
);
7162 rt
= itype_rt (inst
);
7163 return (is_octeon_bbit_op (op
, gdbarch
)
7164 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7165 || op
== 29 /* JALX: bits 011101 */
7168 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7169 || (rs
== 9 && (rt
& 0x2) == 0)
7170 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7171 || (rs
== 10 && (rt
& 0x2) == 0))));
7172 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7175 switch (op
& 0x07) /* extract bits 28,27,26 */
7177 case 0: /* SPECIAL */
7178 op
= rtype_funct (inst
);
7179 return (op
== 8 /* JR */
7180 || op
== 9); /* JALR */
7181 break; /* end SPECIAL */
7182 case 1: /* REGIMM */
7183 rs
= itype_rs (inst
);
7184 rt
= itype_rt (inst
); /* branch condition */
7185 return ((rt
& 0xc) == 0
7186 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7187 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7188 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7189 /* BPOSGE32, BPOSGE64: bits 1110x */
7190 break; /* end REGIMM */
7191 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7197 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7198 delay slot (i.e. it is a jump or branch instruction). */
7201 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7206 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7210 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7213 /* Return non-zero if the microMIPS instruction INSN, comprising the
7214 16-bit major opcode word in the high 16 bits and any second word
7215 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7216 jump or branch instruction). The instruction must be 32-bit if
7217 MUSTBE32 is set or can be any instruction otherwise. */
7220 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7222 ULONGEST major
= insn
>> 16;
7224 switch (micromips_op (major
))
7226 /* 16-bit instructions. */
7227 case 0x33: /* B16: bits 110011 */
7228 case 0x2b: /* BNEZ16: bits 101011 */
7229 case 0x23: /* BEQZ16: bits 100011 */
7231 case 0x11: /* POOL16C: bits 010001 */
7233 && ((b5s5_op (major
) == 0xc
7234 /* JR16: bits 010001 01100 */
7235 || (b5s5_op (major
) & 0x1e) == 0xe)));
7236 /* JALR16, JALRS16: bits 010001 0111x */
7237 /* 32-bit instructions. */
7238 case 0x3d: /* JAL: bits 111101 */
7239 case 0x3c: /* JALX: bits 111100 */
7240 case 0x35: /* J: bits 110101 */
7241 case 0x2d: /* BNE: bits 101101 */
7242 case 0x25: /* BEQ: bits 100101 */
7243 case 0x1d: /* JALS: bits 011101 */
7245 case 0x10: /* POOL32I: bits 010000 */
7246 return ((b5s5_op (major
) & 0x1c) == 0x0
7247 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7248 || (b5s5_op (major
) & 0x1d) == 0x4
7249 /* BLEZ, BGTZ: bits 010000 001x0 */
7250 || (b5s5_op (major
) & 0x1d) == 0x11
7251 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7252 || ((b5s5_op (major
) & 0x1e) == 0x14
7253 && (major
& 0x3) == 0x0)
7254 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7255 || (b5s5_op (major
) & 0x1e) == 0x1a
7256 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7257 || ((b5s5_op (major
) & 0x1e) == 0x1c
7258 && (major
& 0x3) == 0x0)
7259 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7260 || ((b5s5_op (major
) & 0x1c) == 0x1c
7261 && (major
& 0x3) == 0x1));
7262 /* BC1ANY*: bits 010000 111xx xxx01 */
7263 case 0x0: /* POOL32A: bits 000000 */
7264 return (b0s6_op (insn
) == 0x3c
7265 /* POOL32Axf: bits 000000 ... 111100 */
7266 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7267 /* JALR, JALR.HB: 000000 000x111100 111100 */
7268 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7274 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7275 slot (i.e. it is a non-compact jump instruction). The instruction
7276 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7279 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7280 CORE_ADDR addr
, int mustbe32
)
7286 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7289 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7291 if (size
== 2 * MIPS_INSN16_SIZE
)
7293 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7298 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7301 /* Return non-zero if the MIPS16 instruction INST, which must be
7302 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7303 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7304 instruction). This function is based on mips16_next_pc. */
7307 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7309 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7311 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7314 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7315 slot (i.e. it is a non-compact jump instruction). The instruction
7316 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7319 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7320 CORE_ADDR addr
, int mustbe32
)
7322 unsigned short insn
;
7325 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7329 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7332 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7333 This assumes KSSEG exists. */
7336 mips_segment_boundary (CORE_ADDR bpaddr
)
7338 CORE_ADDR mask
= CORE_ADDR_MAX
;
7341 if (sizeof (CORE_ADDR
) == 8)
7342 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7343 a compiler warning produced where CORE_ADDR is a 32-bit type even
7344 though in that case this is dead code). */
7345 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7348 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7349 segsize
= 29; /* 32-bit compatibility segment */
7351 segsize
= 62; /* xkseg */
7353 case 2: /* xkphys */
7356 default: /* xksseg (1), xkuseg/kuseg (0) */
7360 else if (bpaddr
& 0x80000000) /* kernel segment */
7363 segsize
= 31; /* user segment */
7365 return bpaddr
& mask
;
7368 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7369 it backwards if necessary. Return the address of the new location. */
7372 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7374 CORE_ADDR prev_addr
;
7376 CORE_ADDR func_addr
;
7378 /* If a breakpoint is set on the instruction in a branch delay slot,
7379 GDB gets confused. When the breakpoint is hit, the PC isn't on
7380 the instruction in the branch delay slot, the PC will point to
7381 the branch instruction. Since the PC doesn't match any known
7382 breakpoints, GDB reports a trap exception.
7384 There are two possible fixes for this problem.
7386 1) When the breakpoint gets hit, see if the BD bit is set in the
7387 Cause register (which indicates the last exception occurred in a
7388 branch delay slot). If the BD bit is set, fix the PC to point to
7389 the instruction in the branch delay slot.
7391 2) When the user sets the breakpoint, don't allow him to set the
7392 breakpoint on the instruction in the branch delay slot. Instead
7393 move the breakpoint to the branch instruction (which will have
7396 The problem with the first solution is that if the user then
7397 single-steps the processor, the branch instruction will get
7398 skipped (since GDB thinks the PC is on the instruction in the
7401 So, we'll use the second solution. To do this we need to know if
7402 the instruction we're trying to set the breakpoint on is in the
7403 branch delay slot. */
7405 boundary
= mips_segment_boundary (bpaddr
);
7407 /* Make sure we don't scan back before the beginning of the current
7408 function, since we may fetch constant data or insns that look like
7409 a jump. Of course we might do that anyway if the compiler has
7410 moved constants inline. :-( */
7411 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7412 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7413 boundary
= func_addr
;
7415 if (mips_pc_is_mips (bpaddr
))
7417 if (bpaddr
== boundary
)
7420 /* If the previous instruction has a branch delay slot, we have
7421 to move the breakpoint to the branch instruction. */
7422 prev_addr
= bpaddr
- 4;
7423 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7428 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7429 CORE_ADDR addr
, jmpaddr
;
7432 boundary
= unmake_compact_addr (boundary
);
7434 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7435 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7436 so try for that first, then try the 2 byte JALR/JR.
7437 The microMIPS ASE has a whole range of jumps and branches
7438 with delay slots, some of which take 4 bytes and some take
7439 2 bytes, so the idea is the same.
7440 FIXME: We have to assume that bpaddr is not the second half
7441 of an extended instruction. */
7442 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7443 ? micromips_insn_at_pc_has_delay_slot
7444 : mips16_insn_at_pc_has_delay_slot
);
7448 for (i
= 1; i
< 4; i
++)
7450 if (unmake_compact_addr (addr
) == boundary
)
7452 addr
-= MIPS_INSN16_SIZE
;
7453 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7454 /* Looks like a JR/JALR at [target-1], but it could be
7455 the second word of a previous JAL/JALX, so record it
7456 and check back one more. */
7458 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7461 /* Looks like a JAL/JALX at [target-2], but it could also
7462 be the second word of a previous JAL/JALX, record it,
7463 and check back one more. */
7466 /* Looks like a JAL/JALX at [target-3], so any previously
7467 recorded JAL/JALX or JR/JALR must be wrong, because:
7470 -2: JAL-ext (can't be JAL/JALX)
7471 -1: bdslot (can't be JR/JALR)
7474 Of course it could be another JAL-ext which looks
7475 like a JAL, but in that case we'd have broken out
7476 of this loop at [target-2]:
7480 -2: bdslot (can't be jmp)
7487 /* Not a jump instruction: if we're at [target-1] this
7488 could be the second word of a JAL/JALX, so continue;
7489 otherwise we're done. */
7502 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7503 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7506 mips_is_stub_suffix (const char *suffix
, int zero
)
7511 return zero
&& suffix
[1] == '\0';
7513 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7518 return suffix
[1] == '\0';
7524 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7525 call stubs, one of sf, df, sc, or dc. */
7528 mips_is_stub_mode (const char *mode
)
7530 return ((mode
[0] == 's' || mode
[0] == 'd')
7531 && (mode
[1] == 'f' || mode
[1] == 'c'));
7534 /* Code at PC is a compiler-generated stub. Such a stub for a function
7535 bar might have a name like __fn_stub_bar, and might look like this:
7542 followed by (or interspersed with):
7549 addiu $25, $25, %lo(bar)
7552 ($1 may be used in old code; for robustness we accept any register)
7555 lui $28, %hi(_gp_disp)
7556 addiu $28, $28, %lo(_gp_disp)
7559 addiu $25, $25, %lo(bar)
7562 In the case of a __call_stub_bar stub, the sequence to set up
7563 arguments might look like this:
7570 followed by (or interspersed with) one of the jump sequences above.
7572 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7573 of J or JR, respectively, followed by:
7579 We are at the beginning of the stub here, and scan down and extract
7580 the target address from the jump immediate instruction or, if a jump
7581 register instruction is used, from the register referred. Return
7582 the value of PC calculated or 0 if inconclusive.
7584 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7587 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7589 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7590 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7591 int addrreg
= MIPS_ZERO_REGNUM
;
7592 CORE_ADDR start_pc
= pc
;
7593 CORE_ADDR target_pc
= 0;
7600 status
== 0 && target_pc
== 0 && i
< 20;
7601 i
++, pc
+= MIPS_INSN32_SIZE
)
7603 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7609 switch (itype_op (inst
))
7611 case 0: /* SPECIAL */
7612 switch (rtype_funct (inst
))
7616 rs
= rtype_rs (inst
);
7617 if (rs
== MIPS_GP_REGNUM
)
7618 target_pc
= gp
; /* Hmm... */
7619 else if (rs
== addrreg
)
7623 case 0x21: /* ADDU */
7624 rt
= rtype_rt (inst
);
7625 rs
= rtype_rs (inst
);
7626 rd
= rtype_rd (inst
);
7627 if (rd
== MIPS_GP_REGNUM
7628 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7629 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7637 target_pc
= jtype_target (inst
) << 2;
7638 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7642 rt
= itype_rt (inst
);
7643 rs
= itype_rs (inst
);
7646 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7647 if (rt
== MIPS_GP_REGNUM
)
7649 else if (rt
== addrreg
)
7655 rt
= itype_rt (inst
);
7656 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7657 if (rt
== MIPS_GP_REGNUM
)
7659 else if (rt
!= MIPS_ZERO_REGNUM
)
7667 rt
= itype_rt (inst
);
7668 rs
= itype_rs (inst
);
7669 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7670 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7674 memset (buf
, 0, sizeof (buf
));
7675 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7677 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7686 /* If PC is in a MIPS16 call or return stub, return the address of the
7687 target PC, which is either the callee or the caller. There are several
7688 cases which must be handled:
7690 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7691 and the target PC is in $31 ($ra).
7692 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7693 and the target PC is in $2.
7694 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7695 i.e. before the JALR instruction, this is effectively a call stub
7696 and the target PC is in $2. Otherwise this is effectively
7697 a return stub and the target PC is in $18.
7698 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7699 JAL or JALR instruction, this is effectively a call stub and the
7700 target PC is buried in the instruction stream. Otherwise this
7701 is effectively a return stub and the target PC is in $18.
7702 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7703 stub and the target PC is buried in the instruction stream.
7705 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7706 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7710 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7712 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7713 CORE_ADDR start_addr
;
7717 /* Find the starting address and name of the function containing the PC. */
7718 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7721 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7722 and the target PC is in $31 ($ra). */
7723 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7724 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7725 && mips_is_stub_mode (name
+ prefixlen
)
7726 && name
[prefixlen
+ 2] == '\0')
7727 return get_frame_register_signed
7728 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7730 /* If the PC is in __mips16_call_stub_*, this is one of the call
7731 call/return stubs. */
7732 prefixlen
= strlen (mips_str_mips16_call_stub
);
7733 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7735 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7736 and the target PC is in $2. */
7737 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7738 return get_frame_register_signed
7739 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7741 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7742 i.e. before the JALR instruction, this is effectively a call stub
7743 and the target PC is in $2. Otherwise this is effectively
7744 a return stub and the target PC is in $18. */
7745 else if (mips_is_stub_mode (name
+ prefixlen
)
7746 && name
[prefixlen
+ 2] == '_'
7747 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7749 if (pc
== start_addr
)
7750 /* This is the 'call' part of a call stub. The return
7751 address is in $2. */
7752 return get_frame_register_signed
7753 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7755 /* This is the 'return' part of a call stub. The return
7756 address is in $18. */
7757 return get_frame_register_signed
7758 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7761 return 0; /* Not a stub. */
7764 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7765 compiler-generated call or call/return stubs. */
7766 if (startswith (name
, mips_str_fn_stub
)
7767 || startswith (name
, mips_str_call_stub
))
7769 if (pc
== start_addr
)
7770 /* This is the 'call' part of a call stub. Call this helper
7771 to scan through this code for interesting instructions
7772 and determine the final PC. */
7773 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7775 /* This is the 'return' part of a call stub. The return address
7777 return get_frame_register_signed
7778 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7781 return 0; /* Not a stub. */
7784 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7785 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7788 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7790 CORE_ADDR start_addr
;
7793 /* Find the starting address of the function containing the PC. */
7794 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7797 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7798 the start, i.e. after the JALR instruction, this is effectively
7800 prefixlen
= strlen (mips_str_mips16_call_stub
);
7801 if (pc
!= start_addr
7802 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7803 && mips_is_stub_mode (name
+ prefixlen
)
7804 && name
[prefixlen
+ 2] == '_'
7805 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7808 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7809 the JAL or JALR instruction, this is effectively a return stub. */
7810 prefixlen
= strlen (mips_str_call_fp_stub
);
7811 if (pc
!= start_addr
7812 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7815 /* Consume the .pic. prefix of any PIC stub, this function must return
7816 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7817 or the call stub path will trigger in handle_inferior_event causing
7819 prefixlen
= strlen (mips_str_pic
);
7820 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7823 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7824 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7825 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7826 && mips_is_stub_mode (name
+ prefixlen
)
7827 && name
[prefixlen
+ 2] == '\0')
7830 return 0; /* Not a stub. */
7833 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7834 PC of the stub target. The stub just loads $t9 and jumps to it,
7835 so that $t9 has the correct value at function entry. */
7838 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7840 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7841 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7842 struct bound_minimal_symbol msym
;
7844 gdb_byte stub_code
[16];
7845 int32_t stub_words
[4];
7847 /* The stub for foo is named ".pic.foo", and is either two
7848 instructions inserted before foo or a three instruction sequence
7849 which jumps to foo. */
7850 msym
= lookup_minimal_symbol_by_pc (pc
);
7851 if (msym
.minsym
== NULL
7852 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7853 || MSYMBOL_LINKAGE_NAME (msym
.minsym
) == NULL
7854 || !startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
7857 /* A two-instruction header. */
7858 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7861 /* A three-instruction (plus delay slot) trampoline. */
7862 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7864 if (target_read_memory (pc
, stub_code
, 16) != 0)
7866 for (i
= 0; i
< 4; i
++)
7867 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7870 /* A stub contains these instructions:
7873 addiu t9, t9, %lo(target)
7876 This works even for N64, since stubs are only generated with
7878 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7879 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7880 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7881 && stub_words
[3] == 0x00000000)
7882 return ((((stub_words
[0] & 0x0000ffff) << 16)
7883 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7886 /* Not a recognized stub. */
7891 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7893 CORE_ADDR requested_pc
= pc
;
7894 CORE_ADDR target_pc
;
7901 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7905 new_pc
= find_solib_trampoline_target (frame
, pc
);
7909 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7913 while (pc
!= target_pc
);
7915 return pc
!= requested_pc
? pc
: 0;
7918 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7919 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7922 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7925 if (num
>= 0 && num
< 32)
7927 else if (num
>= 38 && num
< 70)
7928 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7930 regnum
= mips_regnum (gdbarch
)->hi
;
7932 regnum
= mips_regnum (gdbarch
)->lo
;
7933 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7934 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7937 return gdbarch_num_regs (gdbarch
) + regnum
;
7941 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7942 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7945 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7948 if (num
>= 0 && num
< 32)
7950 else if (num
>= 32 && num
< 64)
7951 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7953 regnum
= mips_regnum (gdbarch
)->hi
;
7955 regnum
= mips_regnum (gdbarch
)->lo
;
7956 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7957 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7960 return gdbarch_num_regs (gdbarch
) + regnum
;
7964 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7966 /* Only makes sense to supply raw registers. */
7967 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7968 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7969 decide if it is valid. Should instead define a standard sim/gdb
7970 register numbering scheme. */
7971 if (gdbarch_register_name (gdbarch
,
7972 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7973 && gdbarch_register_name (gdbarch
,
7974 gdbarch_num_regs (gdbarch
)
7975 + regnum
)[0] != '\0')
7978 return LEGACY_SIM_REGNO_IGNORE
;
7982 /* Convert an integer into an address. Extracting the value signed
7983 guarantees a correctly sign extended address. */
7986 mips_integer_to_address (struct gdbarch
*gdbarch
,
7987 struct type
*type
, const gdb_byte
*buf
)
7989 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7990 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7993 /* Dummy virtual frame pointer method. This is no more or less accurate
7994 than most other architectures; we just need to be explicit about it,
7995 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7996 an assertion failure. */
7999 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
8000 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
8002 *reg
= MIPS_SP_REGNUM
;
8007 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
8009 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
8010 const char *name
= bfd_get_section_name (abfd
, sect
);
8012 if (*abip
!= MIPS_ABI_UNKNOWN
)
8015 if (!startswith (name
, ".mdebug."))
8018 if (strcmp (name
, ".mdebug.abi32") == 0)
8019 *abip
= MIPS_ABI_O32
;
8020 else if (strcmp (name
, ".mdebug.abiN32") == 0)
8021 *abip
= MIPS_ABI_N32
;
8022 else if (strcmp (name
, ".mdebug.abi64") == 0)
8023 *abip
= MIPS_ABI_N64
;
8024 else if (strcmp (name
, ".mdebug.abiO64") == 0)
8025 *abip
= MIPS_ABI_O64
;
8026 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8027 *abip
= MIPS_ABI_EABI32
;
8028 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8029 *abip
= MIPS_ABI_EABI64
;
8031 warning (_("unsupported ABI %s."), name
+ 8);
8035 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8037 int *lbp
= (int *) obj
;
8038 const char *name
= bfd_get_section_name (abfd
, sect
);
8040 if (startswith (name
, ".gcc_compiled_long32"))
8042 else if (startswith (name
, ".gcc_compiled_long64"))
8044 else if (startswith (name
, ".gcc_compiled_long"))
8045 warning (_("unrecognized .gcc_compiled_longXX"));
8048 static enum mips_abi
8049 global_mips_abi (void)
8053 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8054 if (mips_abi_strings
[i
] == mips_abi_string
)
8055 return (enum mips_abi
) i
;
8057 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8060 /* Return the default compressed instruction set, either of MIPS16
8061 or microMIPS, selected when none could have been determined from
8062 the ELF header of the binary being executed (or no binary has been
8065 static enum mips_isa
8066 global_mips_compression (void)
8070 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8071 if (mips_compression_strings
[i
] == mips_compression_string
)
8072 return (enum mips_isa
) i
;
8074 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8078 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8080 /* If the size matches the set of 32-bit or 64-bit integer registers,
8081 assume that's what we've got. */
8082 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8083 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8085 /* If the size matches the full set of registers GDB traditionally
8086 knows about, including floating point, for either 32-bit or
8087 64-bit, assume that's what we've got. */
8088 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8089 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8091 /* Otherwise we don't have a useful guess. */
8094 static struct value
*
8095 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8097 const int *reg_p
= (const int *) baton
;
8098 return value_of_register (*reg_p
, frame
);
8101 static struct gdbarch
*
8102 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8104 struct gdbarch
*gdbarch
;
8105 struct gdbarch_tdep
*tdep
;
8107 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8109 enum mips_fpu_type fpu_type
;
8110 struct tdesc_arch_data
*tdesc_data
= NULL
;
8111 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8112 const char **reg_names
;
8113 struct mips_regnum mips_regnum
, *regnum
;
8114 enum mips_isa mips_isa
;
8118 /* Fill in the OS dependent register numbers and names. */
8119 if (info
.osabi
== GDB_OSABI_LINUX
)
8121 mips_regnum
.fp0
= 38;
8122 mips_regnum
.pc
= 37;
8123 mips_regnum
.cause
= 36;
8124 mips_regnum
.badvaddr
= 35;
8125 mips_regnum
.hi
= 34;
8126 mips_regnum
.lo
= 33;
8127 mips_regnum
.fp_control_status
= 70;
8128 mips_regnum
.fp_implementation_revision
= 71;
8129 mips_regnum
.dspacc
= -1;
8130 mips_regnum
.dspctl
= -1;
8134 reg_names
= mips_linux_reg_names
;
8138 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8139 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8140 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8141 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8142 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8143 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8144 mips_regnum
.fp_control_status
= 70;
8145 mips_regnum
.fp_implementation_revision
= 71;
8146 mips_regnum
.dspacc
= dspacc
= -1;
8147 mips_regnum
.dspctl
= dspctl
= -1;
8148 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8149 if (info
.bfd_arch_info
!= NULL
8150 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8151 reg_names
= mips_tx39_reg_names
;
8153 reg_names
= mips_generic_reg_names
;
8156 /* Check any target description for validity. */
8157 if (tdesc_has_registers (info
.target_desc
))
8159 static const char *const mips_gprs
[] = {
8160 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8161 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8162 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8163 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8165 static const char *const mips_fprs
[] = {
8166 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8167 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8168 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8169 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8172 const struct tdesc_feature
*feature
;
8175 feature
= tdesc_find_feature (info
.target_desc
,
8176 "org.gnu.gdb.mips.cpu");
8177 if (feature
== NULL
)
8180 tdesc_data
= tdesc_data_alloc ();
8183 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8184 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
8188 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8189 mips_regnum
.lo
, "lo");
8190 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8191 mips_regnum
.hi
, "hi");
8192 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8193 mips_regnum
.pc
, "pc");
8197 tdesc_data_cleanup (tdesc_data
);
8201 feature
= tdesc_find_feature (info
.target_desc
,
8202 "org.gnu.gdb.mips.cp0");
8203 if (feature
== NULL
)
8205 tdesc_data_cleanup (tdesc_data
);
8210 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8211 mips_regnum
.badvaddr
, "badvaddr");
8212 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8213 MIPS_PS_REGNUM
, "status");
8214 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8215 mips_regnum
.cause
, "cause");
8219 tdesc_data_cleanup (tdesc_data
);
8223 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8224 backend is not prepared for that, though. */
8225 feature
= tdesc_find_feature (info
.target_desc
,
8226 "org.gnu.gdb.mips.fpu");
8227 if (feature
== NULL
)
8229 tdesc_data_cleanup (tdesc_data
);
8234 for (i
= 0; i
< 32; i
++)
8235 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8236 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8238 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8239 mips_regnum
.fp_control_status
,
8242 &= tdesc_numbered_register (feature
, tdesc_data
,
8243 mips_regnum
.fp_implementation_revision
,
8248 tdesc_data_cleanup (tdesc_data
);
8252 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8256 feature
= tdesc_find_feature (info
.target_desc
,
8257 "org.gnu.gdb.mips.dsp");
8258 /* The DSP registers are optional; it's OK if they are absent. */
8259 if (feature
!= NULL
)
8263 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8264 dspacc
+ i
++, "hi1");
8265 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8266 dspacc
+ i
++, "lo1");
8267 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8268 dspacc
+ i
++, "hi2");
8269 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8270 dspacc
+ i
++, "lo2");
8271 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8272 dspacc
+ i
++, "hi3");
8273 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8274 dspacc
+ i
++, "lo3");
8276 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8281 tdesc_data_cleanup (tdesc_data
);
8285 mips_regnum
.dspacc
= dspacc
;
8286 mips_regnum
.dspctl
= dspctl
;
8288 num_regs
= mips_regnum
.dspctl
+ 1;
8292 /* It would be nice to detect an attempt to use a 64-bit ABI
8293 when only 32-bit registers are provided. */
8297 /* First of all, extract the elf_flags, if available. */
8298 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8299 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8300 else if (arches
!= NULL
)
8301 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8305 fprintf_unfiltered (gdb_stdlog
,
8306 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8308 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8309 switch ((elf_flags
& EF_MIPS_ABI
))
8311 case E_MIPS_ABI_O32
:
8312 found_abi
= MIPS_ABI_O32
;
8314 case E_MIPS_ABI_O64
:
8315 found_abi
= MIPS_ABI_O64
;
8317 case E_MIPS_ABI_EABI32
:
8318 found_abi
= MIPS_ABI_EABI32
;
8320 case E_MIPS_ABI_EABI64
:
8321 found_abi
= MIPS_ABI_EABI64
;
8324 if ((elf_flags
& EF_MIPS_ABI2
))
8325 found_abi
= MIPS_ABI_N32
;
8327 found_abi
= MIPS_ABI_UNKNOWN
;
8331 /* GCC creates a pseudo-section whose name describes the ABI. */
8332 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8333 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8335 /* If we have no useful BFD information, use the ABI from the last
8336 MIPS architecture (if there is one). */
8337 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8338 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8340 /* Try the architecture for any hint of the correct ABI. */
8341 if (found_abi
== MIPS_ABI_UNKNOWN
8342 && info
.bfd_arch_info
!= NULL
8343 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8345 switch (info
.bfd_arch_info
->mach
)
8347 case bfd_mach_mips3900
:
8348 found_abi
= MIPS_ABI_EABI32
;
8350 case bfd_mach_mips4100
:
8351 case bfd_mach_mips5000
:
8352 found_abi
= MIPS_ABI_EABI64
;
8354 case bfd_mach_mips8000
:
8355 case bfd_mach_mips10000
:
8356 /* On Irix, ELF64 executables use the N64 ABI. The
8357 pseudo-sections which describe the ABI aren't present
8358 on IRIX. (Even for executables created by gcc.) */
8359 if (info
.abfd
!= NULL
8360 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8361 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8362 found_abi
= MIPS_ABI_N64
;
8364 found_abi
= MIPS_ABI_N32
;
8369 /* Default 64-bit objects to N64 instead of O32. */
8370 if (found_abi
== MIPS_ABI_UNKNOWN
8371 && info
.abfd
!= NULL
8372 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8373 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8374 found_abi
= MIPS_ABI_N64
;
8377 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8380 /* What has the user specified from the command line? */
8381 wanted_abi
= global_mips_abi ();
8383 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8386 /* Now that we have found what the ABI for this binary would be,
8387 check whether the user is overriding it. */
8388 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8389 mips_abi
= wanted_abi
;
8390 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8391 mips_abi
= found_abi
;
8393 mips_abi
= MIPS_ABI_O32
;
8395 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8398 /* Determine the default compressed ISA. */
8399 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8400 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8401 mips_isa
= ISA_MICROMIPS
;
8402 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8403 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8404 mips_isa
= ISA_MIPS16
;
8406 mips_isa
= global_mips_compression ();
8407 mips_compression_string
= mips_compression_strings
[mips_isa
];
8409 /* Also used when doing an architecture lookup. */
8411 fprintf_unfiltered (gdb_stdlog
,
8412 "mips_gdbarch_init: "
8413 "mips64_transfers_32bit_regs_p = %d\n",
8414 mips64_transfers_32bit_regs_p
);
8416 /* Determine the MIPS FPU type. */
8419 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8420 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8421 Tag_GNU_MIPS_ABI_FP
);
8422 #endif /* HAVE_ELF */
8424 if (!mips_fpu_type_auto
)
8425 fpu_type
= mips_fpu_type
;
8426 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8428 switch (elf_fpu_type
)
8430 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8431 fpu_type
= MIPS_FPU_DOUBLE
;
8433 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8434 fpu_type
= MIPS_FPU_SINGLE
;
8436 case Val_GNU_MIPS_ABI_FP_SOFT
:
8438 /* Soft float or unknown. */
8439 fpu_type
= MIPS_FPU_NONE
;
8443 else if (info
.bfd_arch_info
!= NULL
8444 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8445 switch (info
.bfd_arch_info
->mach
)
8447 case bfd_mach_mips3900
:
8448 case bfd_mach_mips4100
:
8449 case bfd_mach_mips4111
:
8450 case bfd_mach_mips4120
:
8451 fpu_type
= MIPS_FPU_NONE
;
8453 case bfd_mach_mips4650
:
8454 fpu_type
= MIPS_FPU_SINGLE
;
8457 fpu_type
= MIPS_FPU_DOUBLE
;
8460 else if (arches
!= NULL
)
8461 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
8463 fpu_type
= MIPS_FPU_DOUBLE
;
8465 fprintf_unfiltered (gdb_stdlog
,
8466 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8468 /* Check for blatant incompatibilities. */
8470 /* If we have only 32-bit registers, then we can't debug a 64-bit
8472 if (info
.target_desc
8473 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8474 && mips_abi
!= MIPS_ABI_EABI32
8475 && mips_abi
!= MIPS_ABI_O32
)
8477 if (tdesc_data
!= NULL
)
8478 tdesc_data_cleanup (tdesc_data
);
8482 /* Try to find a pre-existing architecture. */
8483 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8485 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8487 /* MIPS needs to be pedantic about which ABI and the compressed
8488 ISA variation the object is using. */
8489 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8491 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8493 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8495 /* Need to be pedantic about which register virtual size is
8497 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8498 != mips64_transfers_32bit_regs_p
)
8500 /* Be pedantic about which FPU is selected. */
8501 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
8504 if (tdesc_data
!= NULL
)
8505 tdesc_data_cleanup (tdesc_data
);
8506 return arches
->gdbarch
;
8509 /* Need a new architecture. Fill in a target specific vector. */
8510 tdep
= XNEW (struct gdbarch_tdep
);
8511 gdbarch
= gdbarch_alloc (&info
, tdep
);
8512 tdep
->elf_flags
= elf_flags
;
8513 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8514 tdep
->found_abi
= found_abi
;
8515 tdep
->mips_abi
= mips_abi
;
8516 tdep
->mips_isa
= mips_isa
;
8517 tdep
->mips_fpu_type
= fpu_type
;
8518 tdep
->register_size_valid_p
= 0;
8519 tdep
->register_size
= 0;
8521 if (info
.target_desc
)
8523 /* Some useful properties can be inferred from the target. */
8524 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8526 tdep
->register_size_valid_p
= 1;
8527 tdep
->register_size
= 4;
8529 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8531 tdep
->register_size_valid_p
= 1;
8532 tdep
->register_size
= 8;
8536 /* Initially set everything according to the default ABI/ISA. */
8537 set_gdbarch_short_bit (gdbarch
, 16);
8538 set_gdbarch_int_bit (gdbarch
, 32);
8539 set_gdbarch_float_bit (gdbarch
, 32);
8540 set_gdbarch_double_bit (gdbarch
, 64);
8541 set_gdbarch_long_double_bit (gdbarch
, 64);
8542 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8543 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8544 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8546 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8547 mips_ax_pseudo_register_collect
);
8548 set_gdbarch_ax_pseudo_register_push_stack
8549 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8551 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8552 mips_elf_make_msymbol_special
);
8553 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8554 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8555 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8557 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8558 *regnum
= mips_regnum
;
8559 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8560 set_gdbarch_num_regs (gdbarch
, num_regs
);
8561 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8562 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8563 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8564 tdep
->mips_processor_reg_names
= reg_names
;
8565 tdep
->regnum
= regnum
;
8570 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8571 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8572 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8573 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8574 tdep
->default_mask_address_p
= 0;
8575 set_gdbarch_long_bit (gdbarch
, 32);
8576 set_gdbarch_ptr_bit (gdbarch
, 32);
8577 set_gdbarch_long_long_bit (gdbarch
, 64);
8580 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8581 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8582 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8583 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8584 tdep
->default_mask_address_p
= 0;
8585 set_gdbarch_long_bit (gdbarch
, 32);
8586 set_gdbarch_ptr_bit (gdbarch
, 32);
8587 set_gdbarch_long_long_bit (gdbarch
, 64);
8589 case MIPS_ABI_EABI32
:
8590 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8591 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8592 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8593 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8594 tdep
->default_mask_address_p
= 0;
8595 set_gdbarch_long_bit (gdbarch
, 32);
8596 set_gdbarch_ptr_bit (gdbarch
, 32);
8597 set_gdbarch_long_long_bit (gdbarch
, 64);
8599 case MIPS_ABI_EABI64
:
8600 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8601 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8602 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8603 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8604 tdep
->default_mask_address_p
= 0;
8605 set_gdbarch_long_bit (gdbarch
, 64);
8606 set_gdbarch_ptr_bit (gdbarch
, 64);
8607 set_gdbarch_long_long_bit (gdbarch
, 64);
8610 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8611 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8612 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8613 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8614 tdep
->default_mask_address_p
= 0;
8615 set_gdbarch_long_bit (gdbarch
, 32);
8616 set_gdbarch_ptr_bit (gdbarch
, 32);
8617 set_gdbarch_long_long_bit (gdbarch
, 64);
8618 set_gdbarch_long_double_bit (gdbarch
, 128);
8619 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8622 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8623 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8624 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8625 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8626 tdep
->default_mask_address_p
= 0;
8627 set_gdbarch_long_bit (gdbarch
, 64);
8628 set_gdbarch_ptr_bit (gdbarch
, 64);
8629 set_gdbarch_long_long_bit (gdbarch
, 64);
8630 set_gdbarch_long_double_bit (gdbarch
, 128);
8631 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8634 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8637 /* GCC creates a pseudo-section whose name specifies the size of
8638 longs, since -mlong32 or -mlong64 may be used independent of
8639 other options. How those options affect pointer sizes is ABI and
8640 architecture dependent, so use them to override the default sizes
8641 set by the ABI. This table shows the relationship between ABI,
8642 -mlongXX, and size of pointers:
8644 ABI -mlongXX ptr bits
8645 --- -------- --------
8659 Note that for o32 and eabi32, pointers are always 32 bits
8660 regardless of any -mlongXX option. For all others, pointers and
8661 longs are the same, as set by -mlongXX or set by defaults. */
8663 if (info
.abfd
!= NULL
)
8667 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8670 set_gdbarch_long_bit (gdbarch
, long_bit
);
8674 case MIPS_ABI_EABI32
:
8679 case MIPS_ABI_EABI64
:
8680 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8683 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8688 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8689 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8692 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8693 flag in object files because to do so would make it impossible to
8694 link with libraries compiled without "-gp32". This is
8695 unnecessarily restrictive.
8697 We could solve this problem by adding "-gp32" multilibs to gcc,
8698 but to set this flag before gcc is built with such multilibs will
8699 break too many systems.''
8701 But even more unhelpfully, the default linker output target for
8702 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8703 for 64-bit programs - you need to change the ABI to change this,
8704 and not all gcc targets support that currently. Therefore using
8705 this flag to detect 32-bit mode would do the wrong thing given
8706 the current gcc - it would make GDB treat these 64-bit programs
8707 as 32-bit programs by default. */
8709 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8710 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8712 /* Add/remove bits from an address. The MIPS needs be careful to
8713 ensure that all 32 bit addresses are sign extended to 64 bits. */
8714 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8716 /* Unwind the frame. */
8717 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8718 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8719 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8721 /* Map debug register numbers onto internal register numbers. */
8722 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8723 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8724 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8725 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8726 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8727 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8729 /* MIPS version of CALL_DUMMY. */
8731 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8732 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8733 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8735 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8737 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8738 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8739 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8741 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8742 SET_GDBARCH_BREAKPOINT_MANIPULATION (mips
);
8743 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
8744 mips_remote_breakpoint_from_pc
);
8745 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8746 mips_adjust_breakpoint_address
);
8748 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8750 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8752 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8753 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8754 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8756 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8758 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8760 if (mips_abi
== MIPS_ABI_N32
)
8761 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8762 else if (mips_abi
== MIPS_ABI_N64
)
8763 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8765 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8767 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8768 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8769 need to all be folded into the target vector. Since they are
8770 being used as guards for target_stopped_by_watchpoint, why not have
8771 target_stopped_by_watchpoint return the type of watchpoint that the code
8773 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8775 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8777 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8778 to support MIPS16. This is a bad thing. Make sure not to do it
8779 if we have an OS ABI that actually supports shared libraries, since
8780 shared library support is more important. If we have an OS someday
8781 that supports both shared libraries and MIPS16, we'll have to find
8782 a better place for these.
8783 macro/2012-04-25: But that applies to return trampolines only and
8784 currently no MIPS OS ABI uses shared libraries that have them. */
8785 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8787 set_gdbarch_single_step_through_delay (gdbarch
,
8788 mips_single_step_through_delay
);
8790 /* Virtual tables. */
8791 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8793 mips_register_g_packet_guesses (gdbarch
);
8795 /* Hook in OS ABI-specific overrides, if they have been registered. */
8796 info
.tdep_info
= tdesc_data
;
8797 gdbarch_init_osabi (info
, gdbarch
);
8799 /* The hook may have adjusted num_regs, fetch the final value and
8800 set pc_regnum and sp_regnum now that it has been fixed. */
8801 num_regs
= gdbarch_num_regs (gdbarch
);
8802 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8803 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8805 /* Unwind the frame. */
8806 dwarf2_append_unwinders (gdbarch
);
8807 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8808 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8809 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8810 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8811 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8812 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8813 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8814 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8815 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8819 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8820 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8822 /* Override the normal target description methods to handle our
8823 dual real and pseudo registers. */
8824 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8825 set_gdbarch_register_reggroup_p (gdbarch
,
8826 mips_tdesc_register_reggroup_p
);
8828 num_regs
= gdbarch_num_regs (gdbarch
);
8829 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8830 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8831 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8834 /* Add ABI-specific aliases for the registers. */
8835 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8836 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8837 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8838 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8840 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8841 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8842 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8844 /* Add some other standard aliases. */
8845 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8846 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8847 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8849 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8850 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8851 value_of_mips_user_reg
,
8852 &mips_numeric_register_aliases
[i
].regnum
);
8858 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
8860 struct gdbarch_info info
;
8862 /* Force the architecture to update, and (if it's a MIPS architecture)
8863 mips_gdbarch_init will take care of the rest. */
8864 gdbarch_info_init (&info
);
8865 gdbarch_update_p (info
);
8868 /* Print out which MIPS ABI is in use. */
8871 show_mips_abi (struct ui_file
*file
,
8873 struct cmd_list_element
*ignored_cmd
,
8874 const char *ignored_value
)
8876 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8879 "The MIPS ABI is unknown because the current architecture "
8883 enum mips_abi global_abi
= global_mips_abi ();
8884 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8885 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8887 if (global_abi
== MIPS_ABI_UNKNOWN
)
8890 "The MIPS ABI is set automatically (currently \"%s\").\n",
8892 else if (global_abi
== actual_abi
)
8895 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8899 /* Probably shouldn't happen... */
8900 fprintf_filtered (file
,
8901 "The (auto detected) MIPS ABI \"%s\" is in use "
8902 "even though the user setting was \"%s\".\n",
8903 actual_abi_str
, mips_abi_strings
[global_abi
]);
8908 /* Print out which MIPS compressed ISA encoding is used. */
8911 show_mips_compression (struct ui_file
*file
, int from_tty
,
8912 struct cmd_list_element
*c
, const char *value
)
8914 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8919 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8921 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8925 int ef_mips_32bitmode
;
8926 /* Determine the ISA. */
8927 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8945 /* Determine the size of a pointer. */
8946 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8947 fprintf_unfiltered (file
,
8948 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8950 fprintf_unfiltered (file
,
8951 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8953 fprintf_unfiltered (file
,
8954 "mips_dump_tdep: ef_mips_arch = %d\n",
8956 fprintf_unfiltered (file
,
8957 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8958 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8959 fprintf_unfiltered (file
,
8961 "mips_mask_address_p() %d (default %d)\n",
8962 mips_mask_address_p (tdep
),
8963 tdep
->default_mask_address_p
);
8965 fprintf_unfiltered (file
,
8966 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8967 MIPS_DEFAULT_FPU_TYPE
,
8968 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
8969 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
8970 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
8972 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8973 MIPS_EABI (gdbarch
));
8974 fprintf_unfiltered (file
,
8975 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8976 MIPS_FPU_TYPE (gdbarch
),
8977 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
8978 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
8979 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
8983 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
8986 _initialize_mips_tdep (void)
8988 static struct cmd_list_element
*mipsfpulist
= NULL
;
8989 struct cmd_list_element
*c
;
8991 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8992 if (MIPS_ABI_LAST
+ 1
8993 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8994 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8996 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8998 mips_pdr_data
= register_objfile_data ();
9000 /* Create feature sets with the appropriate properties. The values
9001 are not important. */
9002 mips_tdesc_gp32
= allocate_target_description ();
9003 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
9005 mips_tdesc_gp64
= allocate_target_description ();
9006 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
9008 /* Add root prefix command for all "set mips"/"show mips" commands. */
9009 add_prefix_cmd ("mips", no_class
, set_mips_command
,
9010 _("Various MIPS specific commands."),
9011 &setmipscmdlist
, "set mips ", 0, &setlist
);
9013 add_prefix_cmd ("mips", no_class
, show_mips_command
,
9014 _("Various MIPS specific commands."),
9015 &showmipscmdlist
, "show mips ", 0, &showlist
);
9017 /* Allow the user to override the ABI. */
9018 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9019 &mips_abi_string
, _("\
9020 Set the MIPS ABI used by this program."), _("\
9021 Show the MIPS ABI used by this program."), _("\
9022 This option can be set to one of:\n\
9023 auto - the default ABI associated with the current binary\n\
9032 &setmipscmdlist
, &showmipscmdlist
);
9034 /* Allow the user to set the ISA to assume for compressed code if ELF
9035 file flags don't tell or there is no program file selected. This
9036 setting is updated whenever unambiguous ELF file flags are interpreted,
9037 and carried over to subsequent sessions. */
9038 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9039 &mips_compression_string
, _("\
9040 Set the compressed ISA encoding used by MIPS code."), _("\
9041 Show the compressed ISA encoding used by MIPS code."), _("\
9042 Select the compressed ISA encoding used in functions that have no symbol\n\
9043 information available. The encoding can be set to either of:\n\
9046 and is updated automatically from ELF file flags if available."),
9048 show_mips_compression
,
9049 &setmipscmdlist
, &showmipscmdlist
);
9051 /* Let the user turn off floating point and set the fence post for
9052 heuristic_proc_start. */
9054 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
9055 _("Set use of MIPS floating-point coprocessor."),
9056 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
9057 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9058 _("Select single-precision MIPS floating-point coprocessor."),
9060 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9061 _("Select double-precision MIPS floating-point coprocessor."),
9063 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
9064 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
9065 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
9066 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9067 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9068 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
9069 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
9070 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
9071 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9072 _("Select MIPS floating-point coprocessor automatically."),
9074 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9075 _("Show current use of MIPS floating-point coprocessor target."),
9078 /* We really would like to have both "0" and "unlimited" work, but
9079 command.c doesn't deal with that. So make it a var_zinteger
9080 because the user can always use "999999" or some such for unlimited. */
9081 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9082 &heuristic_fence_post
, _("\
9083 Set the distance searched for the start of a function."), _("\
9084 Show the distance searched for the start of a function."), _("\
9085 If you are debugging a stripped executable, GDB needs to search through the\n\
9086 program for the start of a function. This command sets the distance of the\n\
9087 search. The only need to set it is when debugging a stripped executable."),
9088 reinit_frame_cache_sfunc
,
9089 NULL
, /* FIXME: i18n: The distance searched for
9090 the start of a function is %s. */
9091 &setlist
, &showlist
);
9093 /* Allow the user to control whether the upper bits of 64-bit
9094 addresses should be zeroed. */
9095 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9096 &mask_address_var
, _("\
9097 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9098 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9099 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9100 allow GDB to determine the correct value."),
9101 NULL
, show_mask_address
,
9102 &setmipscmdlist
, &showmipscmdlist
);
9104 /* Allow the user to control the size of 32 bit registers within the
9105 raw remote packet. */
9106 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9107 &mips64_transfers_32bit_regs_p
, _("\
9108 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9110 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9112 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9113 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9114 64 bits for others. Use \"off\" to disable compatibility mode"),
9115 set_mips64_transfers_32bit_regs
,
9116 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9117 MIPS target that transfers 32-bit
9118 quantities is %s. */
9119 &setlist
, &showlist
);
9121 /* Debug this files internals. */
9122 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9124 Set mips debugging."), _("\
9125 Show mips debugging."), _("\
9126 When non-zero, mips specific debugging is enabled."),
9128 NULL
, /* FIXME: i18n: Mips debugging is
9130 &setdebuglist
, &showdebuglist
);