1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
62 static const struct objfile_data
*mips_pdr_data
;
64 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
66 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
67 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
68 #define ST0_FR (1 << 26)
70 /* The sizes of floating point registers. */
74 MIPS_FPU_SINGLE_REGSIZE
= 4,
75 MIPS_FPU_DOUBLE_REGSIZE
= 8
84 static const char *mips_abi_string
;
86 static const char *mips_abi_strings
[] = {
97 /* The standard register names, and all the valid aliases for them. */
104 /* Aliases for o32 and most other ABIs. */
105 const struct register_alias mips_o32_aliases
[] = {
112 /* Aliases for n32 and n64. */
113 const struct register_alias mips_n32_n64_aliases
[] = {
120 /* Aliases for ABI-independent registers. */
121 const struct register_alias mips_register_aliases
[] = {
122 /* The architecture manuals specify these ABI-independent names for
124 #define R(n) { "r" #n, n }
125 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
126 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
127 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
128 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
131 /* k0 and k1 are sometimes called these instead (for "kernel
136 /* This is the traditional GDB name for the CP0 status register. */
137 { "sr", MIPS_PS_REGNUM
},
139 /* This is the traditional GDB name for the CP0 BadVAddr register. */
140 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
142 /* This is the traditional GDB name for the FCSR. */
143 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
146 const struct register_alias mips_numeric_register_aliases
[] = {
147 #define R(n) { #n, n }
148 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
149 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
150 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
151 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto
= 1;
159 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
161 static int mips_debug
= 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc
*mips_tdesc_gp32
;
169 struct target_desc
*mips_tdesc_gp64
;
171 const struct mips_regnum
*
172 mips_regnum (struct gdbarch
*gdbarch
)
174 return gdbarch_tdep (gdbarch
)->regnum
;
178 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
180 return mips_regnum (gdbarch
)->fp0
+ 12;
183 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
185 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
187 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
189 #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
191 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
193 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
194 functions to test, set, or clear bit 0 of addresses. */
197 is_mips16_addr (CORE_ADDR addr
)
203 unmake_mips16_addr (CORE_ADDR addr
)
205 return ((addr
) & ~(CORE_ADDR
) 1);
208 /* Return the MIPS ABI associated with GDBARCH. */
210 mips_abi (struct gdbarch
*gdbarch
)
212 return gdbarch_tdep (gdbarch
)->mips_abi
;
216 mips_isa_regsize (struct gdbarch
*gdbarch
)
218 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
220 /* If we know how big the registers are, use that size. */
221 if (tdep
->register_size_valid_p
)
222 return tdep
->register_size
;
224 /* Fall back to the previous behavior. */
225 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
226 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
229 /* Return the currently configured (or set) saved register size. */
232 mips_abi_regsize (struct gdbarch
*gdbarch
)
234 switch (mips_abi (gdbarch
))
236 case MIPS_ABI_EABI32
:
242 case MIPS_ABI_EABI64
:
244 case MIPS_ABI_UNKNOWN
:
247 internal_error (__FILE__
, __LINE__
, _("bad switch"));
251 /* Functions for setting and testing a bit in a minimal symbol that
252 marks it as 16-bit function. The MSB of the minimal symbol's
253 "info" field is used for this purpose.
255 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
256 i.e. refers to a 16-bit function, and sets a "special" bit in a
257 minimal symbol to mark it as a 16-bit function
259 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
262 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
264 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
266 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
267 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
272 msymbol_is_special (struct minimal_symbol
*msym
)
274 return MSYMBOL_TARGET_FLAG_1 (msym
);
277 /* XFER a value from the big/little/left end of the register.
278 Depending on the size of the value it might occupy the entire
279 register or just part of it. Make an allowance for this, aligning
280 things accordingly. */
283 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
284 int reg_num
, int length
,
285 enum bfd_endian endian
, gdb_byte
*in
,
286 const gdb_byte
*out
, int buf_offset
)
290 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
291 /* Need to transfer the left or right part of the register, based on
292 the targets byte order. */
296 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
298 case BFD_ENDIAN_LITTLE
:
301 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
305 internal_error (__FILE__
, __LINE__
, _("bad switch"));
308 fprintf_unfiltered (gdb_stderr
,
309 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
310 reg_num
, reg_offset
, buf_offset
, length
);
311 if (mips_debug
&& out
!= NULL
)
314 fprintf_unfiltered (gdb_stdlog
, "out ");
315 for (i
= 0; i
< length
; i
++)
316 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
319 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
322 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
324 if (mips_debug
&& in
!= NULL
)
327 fprintf_unfiltered (gdb_stdlog
, "in ");
328 for (i
= 0; i
< length
; i
++)
329 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
332 fprintf_unfiltered (gdb_stdlog
, "\n");
335 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
336 compatiblity mode. A return value of 1 means that we have
337 physical 64-bit registers, but should treat them as 32-bit registers. */
340 mips2_fp_compat (struct frame_info
*frame
)
342 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
343 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
345 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
349 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
350 in all the places we deal with FP registers. PR gdb/413. */
351 /* Otherwise check the FR bit in the status register - it controls
352 the FP compatiblity mode. If it is clear we are in compatibility
354 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
361 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
363 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
365 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
367 static struct type
*mips_float_register_type (void);
368 static struct type
*mips_double_register_type (void);
370 /* The list of available "set mips " and "show mips " commands */
372 static struct cmd_list_element
*setmipscmdlist
= NULL
;
373 static struct cmd_list_element
*showmipscmdlist
= NULL
;
375 /* Integer registers 0 thru 31 are handled explicitly by
376 mips_register_name(). Processor specific registers 32 and above
377 are listed in the following tables. */
380 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
384 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
385 "sr", "lo", "hi", "bad", "cause", "pc",
386 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
387 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
388 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
389 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
390 "fsr", "fir", "" /*"fp" */ , "",
391 "", "", "", "", "", "", "", "",
392 "", "", "", "", "", "", "", "",
395 /* Names of IDT R3041 registers. */
397 static const char *mips_r3041_reg_names
[] = {
398 "sr", "lo", "hi", "bad", "cause", "pc",
399 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
400 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
401 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
402 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
403 "fsr", "fir", "", /*"fp" */ "",
404 "", "", "bus", "ccfg", "", "", "", "",
405 "", "", "port", "cmp", "", "", "epc", "prid",
408 /* Names of tx39 registers. */
410 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
411 "sr", "lo", "hi", "bad", "cause", "pc",
412 "", "", "", "", "", "", "", "",
413 "", "", "", "", "", "", "", "",
414 "", "", "", "", "", "", "", "",
415 "", "", "", "", "", "", "", "",
417 "", "", "", "", "", "", "", "",
418 "", "", "config", "cache", "debug", "depc", "epc", ""
421 /* Names of IRIX registers. */
422 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
423 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
424 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
425 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
426 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
427 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
431 /* Return the name of the register corresponding to REGNO. */
433 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
435 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
436 /* GPR names for all ABIs other than n32/n64. */
437 static char *mips_gpr_names
[] = {
438 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
439 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
440 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
441 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
444 /* GPR names for n32 and n64 ABIs. */
445 static char *mips_n32_n64_gpr_names
[] = {
446 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
447 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
448 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
449 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
452 enum mips_abi abi
= mips_abi (gdbarch
);
454 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
455 but then don't make the raw register names visible. */
456 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
457 if (regno
< gdbarch_num_regs (gdbarch
))
460 /* The MIPS integer registers are always mapped from 0 to 31. The
461 names of the registers (which reflects the conventions regarding
462 register use) vary depending on the ABI. */
463 if (0 <= rawnum
&& rawnum
< 32)
465 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
466 return mips_n32_n64_gpr_names
[rawnum
];
468 return mips_gpr_names
[rawnum
];
470 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
471 return tdesc_register_name (gdbarch
, rawnum
);
472 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
474 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
475 return tdep
->mips_processor_reg_names
[rawnum
- 32];
478 internal_error (__FILE__
, __LINE__
,
479 _("mips_register_name: bad register number %d"), rawnum
);
482 /* Return the groups that a MIPS register can be categorised into. */
485 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
486 struct reggroup
*reggroup
)
491 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
492 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
493 if (reggroup
== all_reggroup
)
495 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
496 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
497 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
498 (gdbarch), as not all architectures are multi-arch. */
499 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
500 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
501 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
503 if (reggroup
== float_reggroup
)
504 return float_p
&& pseudo
;
505 if (reggroup
== vector_reggroup
)
506 return vector_p
&& pseudo
;
507 if (reggroup
== general_reggroup
)
508 return (!vector_p
&& !float_p
) && pseudo
;
509 /* Save the pseudo registers. Need to make certain that any code
510 extracting register values from a saved register cache also uses
512 if (reggroup
== save_reggroup
)
513 return raw_p
&& pseudo
;
514 /* Restore the same pseudo register. */
515 if (reggroup
== restore_reggroup
)
516 return raw_p
&& pseudo
;
520 /* Return the groups that a MIPS register can be categorised into.
521 This version is only used if we have a target description which
522 describes real registers (and their groups). */
525 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
526 struct reggroup
*reggroup
)
528 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
529 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
532 /* Only save, restore, and display the pseudo registers. Need to
533 make certain that any code extracting register values from a
534 saved register cache also uses pseudo registers.
536 Note: saving and restoring the pseudo registers is slightly
537 strange; if we have 64 bits, we should save and restore all
538 64 bits. But this is hard and has little benefit. */
542 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
546 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
549 /* Map the symbol table registers which live in the range [1 *
550 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
551 registers. Take care of alignment and size problems. */
554 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
555 int cookednum
, gdb_byte
*buf
)
557 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
558 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
559 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
560 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
561 regcache_raw_read (regcache
, rawnum
, buf
);
562 else if (register_size (gdbarch
, rawnum
) >
563 register_size (gdbarch
, cookednum
))
565 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
566 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
567 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
569 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
572 internal_error (__FILE__
, __LINE__
, _("bad register size"));
576 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
577 struct regcache
*regcache
, int cookednum
,
580 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
581 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
582 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
583 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
584 regcache_raw_write (regcache
, rawnum
, buf
);
585 else if (register_size (gdbarch
, rawnum
) >
586 register_size (gdbarch
, cookednum
))
588 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
589 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
590 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
592 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
595 internal_error (__FILE__
, __LINE__
, _("bad register size"));
598 /* Table to translate MIPS16 register field to actual register number. */
599 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
601 /* Heuristic_proc_start may hunt through the text section for a long
602 time across a 2400 baud serial line. Allows the user to limit this
605 static unsigned int heuristic_fence_post
= 0;
607 /* Number of bytes of storage in the actual machine representation for
608 register N. NOTE: This defines the pseudo register type so need to
609 rebuild the architecture vector. */
611 static int mips64_transfers_32bit_regs_p
= 0;
614 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
615 struct cmd_list_element
*c
)
617 struct gdbarch_info info
;
618 gdbarch_info_init (&info
);
619 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
620 instead of relying on globals. Doing that would let generic code
621 handle the search for this specific architecture. */
622 if (!gdbarch_update_p (info
))
624 mips64_transfers_32bit_regs_p
= 0;
625 error (_("32-bit compatibility mode not supported"));
629 /* Convert to/from a register and the corresponding memory value. */
632 mips_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
634 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
635 && register_size (gdbarch
, regnum
) == 4
636 && (regnum
% gdbarch_num_regs (gdbarch
))
637 >= mips_regnum (gdbarch
)->fp0
638 && (regnum
% gdbarch_num_regs (gdbarch
))
639 < mips_regnum (gdbarch
)->fp0
+ 32
640 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
644 mips_register_to_value (struct frame_info
*frame
, int regnum
,
645 struct type
*type
, gdb_byte
*to
)
647 get_frame_register (frame
, regnum
+ 0, to
+ 4);
648 get_frame_register (frame
, regnum
+ 1, to
+ 0);
652 mips_value_to_register (struct frame_info
*frame
, int regnum
,
653 struct type
*type
, const gdb_byte
*from
)
655 put_frame_register (frame
, regnum
+ 0, from
+ 4);
656 put_frame_register (frame
, regnum
+ 1, from
+ 0);
659 /* Return the GDB type object for the "standard" data type of data in
663 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
665 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
666 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
667 && (regnum
% gdbarch_num_regs (gdbarch
))
668 < mips_regnum (gdbarch
)->fp0
+ 32)
670 /* The floating-point registers raw, or cooked, always match
671 mips_isa_regsize(), and also map 1:1, byte for byte. */
672 if (mips_isa_regsize (gdbarch
) == 4)
673 return builtin_type_ieee_single
;
675 return builtin_type_ieee_double
;
677 else if (regnum
< gdbarch_num_regs (gdbarch
))
679 /* The raw or ISA registers. These are all sized according to
681 if (mips_isa_regsize (gdbarch
) == 4)
682 return builtin_type_int32
;
684 return builtin_type_int64
;
688 /* The cooked or ABI registers. These are sized according to
689 the ABI (with a few complications). */
690 if (regnum
>= (gdbarch_num_regs (gdbarch
)
691 + mips_regnum (gdbarch
)->fp_control_status
)
692 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
693 /* The pseudo/cooked view of the embedded registers is always
694 32-bit. The raw view is handled below. */
695 return builtin_type_int32
;
696 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
697 /* The target, while possibly using a 64-bit register buffer,
698 is only transfering 32-bits of each integer register.
699 Reflect this in the cooked/pseudo (ABI) register value. */
700 return builtin_type_int32
;
701 else if (mips_abi_regsize (gdbarch
) == 4)
702 /* The ABI is restricted to 32-bit registers (the ISA could be
704 return builtin_type_int32
;
707 return builtin_type_int64
;
711 /* Return the GDB type for the pseudo register REGNUM, which is the
712 ABI-level view. This function is only called if there is a target
713 description which includes registers, so we know precisely the
714 types of hardware registers. */
717 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
719 const int num_regs
= gdbarch_num_regs (gdbarch
);
720 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
721 int rawnum
= regnum
% num_regs
;
722 struct type
*rawtype
;
724 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
726 /* Absent registers are still absent. */
727 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
728 if (TYPE_LENGTH (rawtype
) == 0)
731 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
732 /* Present the floating point registers however the hardware did;
733 do not try to convert between FPU layouts. */
736 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
738 /* The pseudo/cooked view of embedded registers is always
739 32-bit, even if the target transfers 64-bit values for them.
740 New targets relying on XML descriptions should only transfer
741 the necessary 32 bits, but older versions of GDB expected 64,
742 so allow the target to provide 64 bits without interfering
743 with the displayed type. */
744 return builtin_type_int32
;
747 /* Use pointer types for registers if we can. For n32 we can not,
748 since we do not have a 64-bit pointer type. */
749 if (mips_abi_regsize (gdbarch
)
750 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
752 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
753 return builtin_type (gdbarch
)->builtin_data_ptr
;
754 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
755 return builtin_type (gdbarch
)->builtin_func_ptr
;
758 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
759 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
760 return builtin_type_int32
;
762 /* For all other registers, pass through the hardware type. */
766 /* Should the upper word of 64-bit addresses be zeroed? */
767 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
770 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
772 switch (mask_address_var
)
774 case AUTO_BOOLEAN_TRUE
:
776 case AUTO_BOOLEAN_FALSE
:
779 case AUTO_BOOLEAN_AUTO
:
780 return tdep
->default_mask_address_p
;
782 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
788 show_mask_address (struct ui_file
*file
, int from_tty
,
789 struct cmd_list_element
*c
, const char *value
)
791 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
793 deprecated_show_value_hack (file
, from_tty
, c
, value
);
794 switch (mask_address_var
)
796 case AUTO_BOOLEAN_TRUE
:
797 printf_filtered ("The 32 bit mips address mask is enabled\n");
799 case AUTO_BOOLEAN_FALSE
:
800 printf_filtered ("The 32 bit mips address mask is disabled\n");
802 case AUTO_BOOLEAN_AUTO
:
804 ("The 32 bit address mask is set automatically. Currently %s\n",
805 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
808 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
813 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
816 mips_pc_is_mips16 (CORE_ADDR memaddr
)
818 struct minimal_symbol
*sym
;
820 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
821 if (is_mips16_addr (memaddr
))
824 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
825 the high bit of the info field. Use this to decide if the function is
826 MIPS16 or normal MIPS. */
827 sym
= lookup_minimal_symbol_by_pc (memaddr
);
829 return msymbol_is_special (sym
);
834 /* MIPS believes that the PC has a sign extended value. Perhaps the
835 all registers should be sign extended for simplicity? */
838 mips_read_pc (struct regcache
*regcache
)
841 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
842 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
847 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
849 return frame_unwind_register_signed
850 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
854 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
856 return frame_unwind_register_signed
857 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
860 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
861 dummy frame. The frame ID's base needs to match the TOS value
862 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
865 static struct frame_id
866 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
868 return frame_id_build
869 (get_frame_register_signed (this_frame
,
870 gdbarch_num_regs (gdbarch
)
872 get_frame_pc (this_frame
));
876 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
878 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
879 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
882 /* Fetch and return instruction from the specified location. If the PC
883 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
886 mips_fetch_instruction (CORE_ADDR addr
)
888 gdb_byte buf
[MIPS_INSN32_SIZE
];
892 if (mips_pc_is_mips16 (addr
))
894 instlen
= MIPS_INSN16_SIZE
;
895 addr
= unmake_mips16_addr (addr
);
898 instlen
= MIPS_INSN32_SIZE
;
899 status
= target_read_memory (addr
, buf
, instlen
);
901 memory_error (status
, addr
);
902 return extract_unsigned_integer (buf
, instlen
);
905 /* These the fields of 32 bit mips instructions */
906 #define mips32_op(x) (x >> 26)
907 #define itype_op(x) (x >> 26)
908 #define itype_rs(x) ((x >> 21) & 0x1f)
909 #define itype_rt(x) ((x >> 16) & 0x1f)
910 #define itype_immediate(x) (x & 0xffff)
912 #define jtype_op(x) (x >> 26)
913 #define jtype_target(x) (x & 0x03ffffff)
915 #define rtype_op(x) (x >> 26)
916 #define rtype_rs(x) ((x >> 21) & 0x1f)
917 #define rtype_rt(x) ((x >> 16) & 0x1f)
918 #define rtype_rd(x) ((x >> 11) & 0x1f)
919 #define rtype_shamt(x) ((x >> 6) & 0x1f)
920 #define rtype_funct(x) (x & 0x3f)
923 mips32_relative_offset (ULONGEST inst
)
925 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
928 /* Determine where to set a single step breakpoint while considering
929 branch prediction. */
931 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
935 inst
= mips_fetch_instruction (pc
);
936 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
938 if (itype_op (inst
) >> 2 == 5)
939 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
941 op
= (itype_op (inst
) & 0x03);
956 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
957 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
959 int tf
= itype_rt (inst
) & 0x01;
960 int cnum
= itype_rt (inst
) >> 2;
962 get_frame_register_signed (frame
,
963 mips_regnum (get_frame_arch (frame
))->
965 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
967 if (((cond
>> cnum
) & 0x01) == tf
)
968 pc
+= mips32_relative_offset (inst
) + 4;
973 pc
+= 4; /* Not a branch, next instruction is easy */
976 { /* This gets way messy */
978 /* Further subdivide into SPECIAL, REGIMM and other */
979 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
981 case 0: /* SPECIAL */
982 op
= rtype_funct (inst
);
987 /* Set PC to that address */
988 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
990 case 12: /* SYSCALL */
992 struct gdbarch_tdep
*tdep
;
994 tdep
= gdbarch_tdep (get_frame_arch (frame
));
995 if (tdep
->syscall_next_pc
!= NULL
)
996 pc
= tdep
->syscall_next_pc (frame
);
1005 break; /* end SPECIAL */
1006 case 1: /* REGIMM */
1008 op
= itype_rt (inst
); /* branch condition */
1013 case 16: /* BLTZAL */
1014 case 18: /* BLTZALL */
1016 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1017 pc
+= mips32_relative_offset (inst
) + 4;
1019 pc
+= 8; /* after the delay slot */
1023 case 17: /* BGEZAL */
1024 case 19: /* BGEZALL */
1025 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1026 pc
+= mips32_relative_offset (inst
) + 4;
1028 pc
+= 8; /* after the delay slot */
1030 /* All of the other instructions in the REGIMM category */
1035 break; /* end REGIMM */
1040 reg
= jtype_target (inst
) << 2;
1041 /* Upper four bits get never changed... */
1042 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1045 /* FIXME case JALX : */
1048 reg
= jtype_target (inst
) << 2;
1049 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1050 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1052 break; /* The new PC will be alternate mode */
1053 case 4: /* BEQ, BEQL */
1055 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1056 get_frame_register_signed (frame
, itype_rt (inst
)))
1057 pc
+= mips32_relative_offset (inst
) + 4;
1061 case 5: /* BNE, BNEL */
1063 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1064 get_frame_register_signed (frame
, itype_rt (inst
)))
1065 pc
+= mips32_relative_offset (inst
) + 4;
1069 case 6: /* BLEZ, BLEZL */
1070 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1071 pc
+= mips32_relative_offset (inst
) + 4;
1077 greater_branch
: /* BGTZ, BGTZL */
1078 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1079 pc
+= mips32_relative_offset (inst
) + 4;
1086 } /* mips32_next_pc */
1088 /* Decoding the next place to set a breakpoint is irregular for the
1089 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1090 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1091 We dont want to set a single step instruction on the extend instruction
1095 /* Lots of mips16 instruction formats */
1096 /* Predicting jumps requires itype,ritype,i8type
1097 and their extensions extItype,extritype,extI8type
1099 enum mips16_inst_fmts
1101 itype
, /* 0 immediate 5,10 */
1102 ritype
, /* 1 5,3,8 */
1103 rrtype
, /* 2 5,3,3,5 */
1104 rritype
, /* 3 5,3,3,5 */
1105 rrrtype
, /* 4 5,3,3,3,2 */
1106 rriatype
, /* 5 5,3,3,1,4 */
1107 shifttype
, /* 6 5,3,3,3,2 */
1108 i8type
, /* 7 5,3,8 */
1109 i8movtype
, /* 8 5,3,3,5 */
1110 i8mov32rtype
, /* 9 5,3,5,3 */
1111 i64type
, /* 10 5,3,8 */
1112 ri64type
, /* 11 5,3,3,5 */
1113 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1114 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1115 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1116 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1117 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1118 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1119 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1120 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1121 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1122 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1124 /* I am heaping all the fields of the formats into one structure and
1125 then, only the fields which are involved in instruction extension */
1129 unsigned int regx
; /* Function in i8 type */
1134 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1135 for the bits which make up the immediate extension. */
1138 extended_offset (unsigned int extension
)
1141 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1143 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1145 value
|= extension
& 0x01f; /* extract 4:0 */
1149 /* Only call this function if you know that this is an extendable
1150 instruction. It won't malfunction, but why make excess remote memory
1151 references? If the immediate operands get sign extended or something,
1152 do it after the extension is performed. */
1153 /* FIXME: Every one of these cases needs to worry about sign extension
1154 when the offset is to be used in relative addressing. */
1157 fetch_mips_16 (CORE_ADDR pc
)
1160 pc
&= 0xfffffffe; /* clear the low order bit */
1161 target_read_memory (pc
, buf
, 2);
1162 return extract_unsigned_integer (buf
, 2);
1166 unpack_mips16 (CORE_ADDR pc
,
1167 unsigned int extension
,
1169 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1174 switch (insn_format
)
1181 value
= extended_offset (extension
);
1182 value
= value
<< 11; /* rom for the original value */
1183 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1187 value
= inst
& 0x7ff;
1188 /* FIXME : Consider sign extension */
1197 { /* A register identifier and an offset */
1198 /* Most of the fields are the same as I type but the
1199 immediate value is of a different length */
1203 value
= extended_offset (extension
);
1204 value
= value
<< 8; /* from the original instruction */
1205 value
|= inst
& 0xff; /* eleven bits from instruction */
1206 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1207 if (value
& 0x4000) /* test the sign bit , bit 26 */
1209 value
&= ~0x3fff; /* remove the sign bit */
1215 value
= inst
& 0xff; /* 8 bits */
1216 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1217 /* FIXME: Do sign extension , this format needs it */
1218 if (value
& 0x80) /* THIS CONFUSES ME */
1220 value
&= 0xef; /* remove the sign bit */
1230 unsigned long value
;
1231 unsigned int nexthalf
;
1232 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1233 value
= value
<< 16;
1234 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1242 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1244 upk
->offset
= offset
;
1251 add_offset_16 (CORE_ADDR pc
, int offset
)
1253 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1257 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1258 unsigned int extension
, unsigned int insn
)
1260 int op
= (insn
>> 11);
1263 case 2: /* Branch */
1266 struct upk_mips16 upk
;
1267 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1268 offset
= upk
.offset
;
1274 pc
+= (offset
<< 1) + 2;
1277 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1279 struct upk_mips16 upk
;
1280 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1281 pc
= add_offset_16 (pc
, upk
.offset
);
1282 if ((insn
>> 10) & 0x01) /* Exchange mode */
1283 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1290 struct upk_mips16 upk
;
1292 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1293 reg
= get_frame_register_signed (frame
, upk
.regx
);
1295 pc
+= (upk
.offset
<< 1) + 2;
1302 struct upk_mips16 upk
;
1304 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1305 reg
= get_frame_register_signed (frame
, upk
.regx
);
1307 pc
+= (upk
.offset
<< 1) + 2;
1312 case 12: /* I8 Formats btez btnez */
1314 struct upk_mips16 upk
;
1316 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1317 /* upk.regx contains the opcode */
1318 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1319 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1320 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1321 /* pc = add_offset_16(pc,upk.offset) ; */
1322 pc
+= (upk
.offset
<< 1) + 2;
1327 case 29: /* RR Formats JR, JALR, JALR-RA */
1329 struct upk_mips16 upk
;
1330 /* upk.fmt = rrtype; */
1335 upk
.regx
= (insn
>> 8) & 0x07;
1336 upk
.regy
= (insn
>> 5) & 0x07;
1344 break; /* Function return instruction */
1350 break; /* BOGUS Guess */
1352 pc
= get_frame_register_signed (frame
, reg
);
1359 /* This is an instruction extension. Fetch the real instruction
1360 (which follows the extension) and decode things based on
1364 pc
= extended_mips16_next_pc (frame
, pc
, insn
, fetch_mips_16 (pc
));
1377 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1379 unsigned int insn
= fetch_mips_16 (pc
);
1380 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1383 /* The mips_next_pc function supports single_step when the remote
1384 target monitor or stub is not developed enough to do a single_step.
1385 It works by decoding the current instruction and predicting where a
1386 branch will go. This isnt hard because all the data is available.
1387 The MIPS32 and MIPS16 variants are quite different. */
1389 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1391 if (is_mips16_addr (pc
))
1392 return mips16_next_pc (frame
, pc
);
1394 return mips32_next_pc (frame
, pc
);
1397 struct mips_frame_cache
1400 struct trad_frame_saved_reg
*saved_regs
;
1403 /* Set a register's saved stack address in temp_saved_regs. If an
1404 address has already been set for this register, do nothing; this
1405 way we will only recognize the first save of a given register in a
1408 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1409 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1410 Strictly speaking, only the second range is used as it is only second
1411 range (the ABI instead of ISA registers) that comes into play when finding
1412 saved registers in a frame. */
1415 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1416 int regnum
, CORE_ADDR offset
)
1418 if (this_cache
!= NULL
1419 && this_cache
->saved_regs
[regnum
].addr
== -1)
1421 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1423 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1429 /* Fetch the immediate value from a MIPS16 instruction.
1430 If the previous instruction was an EXTEND, use it to extend
1431 the upper bits of the immediate value. This is a helper function
1432 for mips16_scan_prologue. */
1435 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1436 unsigned short inst
, /* current instruction */
1437 int nbits
, /* number of bits in imm field */
1438 int scale
, /* scale factor to be applied to imm */
1439 int is_signed
) /* is the imm field signed? */
1443 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1445 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1446 if (offset
& 0x8000) /* check for negative extend */
1447 offset
= 0 - (0x10000 - (offset
& 0xffff));
1448 return offset
| (inst
& 0x1f);
1452 int max_imm
= 1 << nbits
;
1453 int mask
= max_imm
- 1;
1454 int sign_bit
= max_imm
>> 1;
1456 offset
= inst
& mask
;
1457 if (is_signed
&& (offset
& sign_bit
))
1458 offset
= 0 - (max_imm
- offset
);
1459 return offset
* scale
;
1464 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1465 the associated FRAME_CACHE if not null.
1466 Return the address of the first instruction past the prologue. */
1469 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1470 struct frame_info
*this_frame
,
1471 struct mips_frame_cache
*this_cache
)
1474 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1476 long frame_offset
= 0; /* Size of stack frame. */
1477 long frame_adjust
= 0; /* Offset of FP from SP. */
1478 int frame_reg
= MIPS_SP_REGNUM
;
1479 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1480 unsigned inst
= 0; /* current instruction */
1481 unsigned entry_inst
= 0; /* the entry instruction */
1482 unsigned save_inst
= 0; /* the save instruction */
1485 int extend_bytes
= 0;
1486 int prev_extend_bytes
;
1487 CORE_ADDR end_prologue_addr
= 0;
1488 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1490 /* Can be called when there's no process, and hence when there's no
1492 if (this_frame
!= NULL
)
1493 sp
= get_frame_register_signed (this_frame
,
1494 gdbarch_num_regs (gdbarch
)
1499 if (limit_pc
> start_pc
+ 200)
1500 limit_pc
= start_pc
+ 200;
1502 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1504 /* Save the previous instruction. If it's an EXTEND, we'll extract
1505 the immediate offset extension from it in mips16_get_imm. */
1508 /* Fetch and decode the instruction. */
1509 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1511 /* Normally we ignore extend instructions. However, if it is
1512 not followed by a valid prologue instruction, then this
1513 instruction is not part of the prologue either. We must
1514 remember in this case to adjust the end_prologue_addr back
1516 if ((inst
& 0xf800) == 0xf000) /* extend */
1518 extend_bytes
= MIPS_INSN16_SIZE
;
1522 prev_extend_bytes
= extend_bytes
;
1525 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1526 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1528 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1529 if (offset
< 0) /* negative stack adjustment? */
1530 frame_offset
-= offset
;
1532 /* Exit loop if a positive stack adjustment is found, which
1533 usually means that the stack cleanup code in the function
1534 epilogue is reached. */
1537 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1539 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1540 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1541 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1543 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1545 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1546 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1547 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1549 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1551 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1552 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1554 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1556 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1557 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1559 else if (inst
== 0x673d) /* move $s1, $sp */
1564 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1566 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1567 frame_addr
= sp
+ offset
;
1569 frame_adjust
= offset
;
1571 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1573 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1574 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1575 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1577 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1579 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1580 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1581 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1583 else if ((inst
& 0xf81f) == 0xe809
1584 && (inst
& 0x700) != 0x700) /* entry */
1585 entry_inst
= inst
; /* save for later processing */
1586 else if ((inst
& 0xff80) == 0x6480) /* save */
1588 save_inst
= inst
; /* save for later processing */
1589 if (prev_extend_bytes
) /* extend */
1590 save_inst
|= prev_inst
<< 16;
1592 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1593 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1594 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1596 /* This instruction is part of the prologue, but we don't
1597 need to do anything special to handle it. */
1601 /* This instruction is not an instruction typically found
1602 in a prologue, so we must have reached the end of the
1604 if (end_prologue_addr
== 0)
1605 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1609 /* The entry instruction is typically the first instruction in a function,
1610 and it stores registers at offsets relative to the value of the old SP
1611 (before the prologue). But the value of the sp parameter to this
1612 function is the new SP (after the prologue has been executed). So we
1613 can't calculate those offsets until we've seen the entire prologue,
1614 and can calculate what the old SP must have been. */
1615 if (entry_inst
!= 0)
1617 int areg_count
= (entry_inst
>> 8) & 7;
1618 int sreg_count
= (entry_inst
>> 6) & 3;
1620 /* The entry instruction always subtracts 32 from the SP. */
1623 /* Now we can calculate what the SP must have been at the
1624 start of the function prologue. */
1627 /* Check if a0-a3 were saved in the caller's argument save area. */
1628 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1630 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1631 offset
+= mips_abi_regsize (gdbarch
);
1634 /* Check if the ra register was pushed on the stack. */
1636 if (entry_inst
& 0x20)
1638 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1639 offset
-= mips_abi_regsize (gdbarch
);
1642 /* Check if the s0 and s1 registers were pushed on the stack. */
1643 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1645 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1646 offset
-= mips_abi_regsize (gdbarch
);
1650 /* The SAVE instruction is similar to ENTRY, except that defined by the
1651 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1652 size of the frame is specified as an immediate field of instruction
1653 and an extended variation exists which lets additional registers and
1654 frame space to be specified. The instruction always treats registers
1655 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1656 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1658 static int args_table
[16] = {
1659 0, 0, 0, 0, 1, 1, 1, 1,
1660 2, 2, 2, 0, 3, 3, 4, -1,
1662 static int astatic_table
[16] = {
1663 0, 1, 2, 3, 0, 1, 2, 3,
1664 0, 1, 2, 4, 0, 1, 0, -1,
1666 int aregs
= (save_inst
>> 16) & 0xf;
1667 int xsregs
= (save_inst
>> 24) & 0x7;
1668 int args
= args_table
[aregs
];
1669 int astatic
= astatic_table
[aregs
];
1674 warning (_("Invalid number of argument registers encoded in SAVE."));
1679 warning (_("Invalid number of static registers encoded in SAVE."));
1683 /* For standard SAVE the frame size of 0 means 128. */
1684 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1685 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1688 frame_offset
+= frame_size
;
1690 /* Now we can calculate what the SP must have been at the
1691 start of the function prologue. */
1694 /* Check if A0-A3 were saved in the caller's argument save area. */
1695 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1697 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1698 offset
+= mips_abi_regsize (gdbarch
);
1703 /* Check if the RA register was pushed on the stack. */
1704 if (save_inst
& 0x40)
1706 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1707 offset
-= mips_abi_regsize (gdbarch
);
1710 /* Check if the S8 register was pushed on the stack. */
1713 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1714 offset
-= mips_abi_regsize (gdbarch
);
1717 /* Check if S2-S7 were pushed on the stack. */
1718 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1720 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1721 offset
-= mips_abi_regsize (gdbarch
);
1724 /* Check if the S1 register was pushed on the stack. */
1725 if (save_inst
& 0x10)
1727 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1728 offset
-= mips_abi_regsize (gdbarch
);
1730 /* Check if the S0 register was pushed on the stack. */
1731 if (save_inst
& 0x20)
1733 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1734 offset
-= mips_abi_regsize (gdbarch
);
1737 /* Check if A0-A3 were pushed on the stack. */
1738 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1740 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1741 offset
-= mips_abi_regsize (gdbarch
);
1745 if (this_cache
!= NULL
)
1748 (get_frame_register_signed (this_frame
,
1749 gdbarch_num_regs (gdbarch
) + frame_reg
)
1750 + frame_offset
- frame_adjust
);
1751 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1752 be able to get rid of the assignment below, evetually. But it's
1753 still needed for now. */
1754 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1755 + mips_regnum (gdbarch
)->pc
]
1756 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1759 /* If we didn't reach the end of the prologue when scanning the function
1760 instructions, then set end_prologue_addr to the address of the
1761 instruction immediately after the last one we scanned. */
1762 if (end_prologue_addr
== 0)
1763 end_prologue_addr
= cur_pc
;
1765 return end_prologue_addr
;
1768 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1769 Procedures that use the 32-bit instruction set are handled by the
1770 mips_insn32 unwinder. */
1772 static struct mips_frame_cache
*
1773 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1775 struct mips_frame_cache
*cache
;
1777 if ((*this_cache
) != NULL
)
1778 return (*this_cache
);
1779 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1780 (*this_cache
) = cache
;
1781 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1783 /* Analyze the function prologue. */
1785 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1786 CORE_ADDR start_addr
;
1788 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1789 if (start_addr
== 0)
1790 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
1791 /* We can't analyze the prologue if we couldn't find the begining
1793 if (start_addr
== 0)
1796 mips16_scan_prologue (start_addr
, pc
, this_frame
, *this_cache
);
1799 /* gdbarch_sp_regnum contains the value and not the address. */
1800 trad_frame_set_value (cache
->saved_regs
,
1801 gdbarch_num_regs (get_frame_arch (this_frame
))
1805 return (*this_cache
);
1809 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1810 struct frame_id
*this_id
)
1812 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1814 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
1817 static struct value
*
1818 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
1819 void **this_cache
, int regnum
)
1821 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1823 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1827 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
1828 struct frame_info
*this_frame
, void **this_cache
)
1830 CORE_ADDR pc
= get_frame_pc (this_frame
);
1831 if (mips_pc_is_mips16 (pc
))
1836 static const struct frame_unwind mips_insn16_frame_unwind
=
1839 mips_insn16_frame_this_id
,
1840 mips_insn16_frame_prev_register
,
1842 mips_insn16_frame_sniffer
1846 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
1849 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1854 static const struct frame_base mips_insn16_frame_base
=
1856 &mips_insn16_frame_unwind
,
1857 mips_insn16_frame_base_address
,
1858 mips_insn16_frame_base_address
,
1859 mips_insn16_frame_base_address
1862 static const struct frame_base
*
1863 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
1865 CORE_ADDR pc
= get_frame_pc (this_frame
);
1866 if (mips_pc_is_mips16 (pc
))
1867 return &mips_insn16_frame_base
;
1872 /* Mark all the registers as unset in the saved_regs array
1873 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1876 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
1878 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1882 const int num_regs
= gdbarch_num_regs (gdbarch
);
1885 for (i
= 0; i
< num_regs
; i
++)
1887 this_cache
->saved_regs
[i
].addr
= -1;
1892 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1893 the associated FRAME_CACHE if not null.
1894 Return the address of the first instruction past the prologue. */
1897 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1898 struct frame_info
*this_frame
,
1899 struct mips_frame_cache
*this_cache
)
1902 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1905 int frame_reg
= MIPS_SP_REGNUM
;
1907 CORE_ADDR end_prologue_addr
= 0;
1908 int seen_sp_adjust
= 0;
1909 int load_immediate_bytes
= 0;
1910 int in_delay_slot
= 0;
1911 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1912 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
1914 /* Can be called when there's no process, and hence when there's no
1916 if (this_frame
!= NULL
)
1917 sp
= get_frame_register_signed (this_frame
,
1918 gdbarch_num_regs (gdbarch
)
1923 if (limit_pc
> start_pc
+ 200)
1924 limit_pc
= start_pc
+ 200;
1929 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1931 unsigned long inst
, high_word
, low_word
;
1934 /* Fetch the instruction. */
1935 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1937 /* Save some code by pre-extracting some useful fields. */
1938 high_word
= (inst
>> 16) & 0xffff;
1939 low_word
= inst
& 0xffff;
1940 reg
= high_word
& 0x1f;
1942 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1943 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1944 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1946 if (low_word
& 0x8000) /* negative stack adjustment? */
1947 frame_offset
+= 0x10000 - low_word
;
1949 /* Exit loop if a positive stack adjustment is found, which
1950 usually means that the stack cleanup code in the function
1951 epilogue is reached. */
1955 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1956 && !regsize_is_64_bits
)
1958 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
1960 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1961 && regsize_is_64_bits
)
1963 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1964 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
1966 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1968 /* Old gcc frame, r30 is virtual frame pointer. */
1969 if ((long) low_word
!= frame_offset
)
1970 frame_addr
= sp
+ low_word
;
1971 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1973 unsigned alloca_adjust
;
1976 frame_addr
= get_frame_register_signed
1977 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
1979 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1980 if (alloca_adjust
> 0)
1982 /* FP > SP + frame_size. This may be because of
1983 an alloca or somethings similar. Fix sp to
1984 "pre-alloca" value, and try again. */
1985 sp
+= alloca_adjust
;
1986 /* Need to reset the status of all registers. Otherwise,
1987 we will hit a guard that prevents the new address
1988 for each register to be recomputed during the second
1990 reset_saved_regs (gdbarch
, this_cache
);
1995 /* move $30,$sp. With different versions of gas this will be either
1996 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1997 Accept any one of these. */
1998 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2000 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2001 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2003 unsigned alloca_adjust
;
2006 frame_addr
= get_frame_register_signed
2007 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2009 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2010 if (alloca_adjust
> 0)
2012 /* FP > SP + frame_size. This may be because of
2013 an alloca or somethings similar. Fix sp to
2014 "pre-alloca" value, and try again. */
2016 /* Need to reset the status of all registers. Otherwise,
2017 we will hit a guard that prevents the new address
2018 for each register to be recomputed during the second
2020 reset_saved_regs (gdbarch
, this_cache
);
2025 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2026 && !regsize_is_64_bits
)
2028 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2030 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2031 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2032 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2033 || high_word
== 0x3c1c /* lui $gp,n */
2034 || high_word
== 0x279c /* addiu $gp,$gp,n */
2035 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2036 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2039 /* These instructions are part of the prologue, but we don't
2040 need to do anything special to handle them. */
2042 /* The instructions below load $at or $t0 with an immediate
2043 value in preparation for a stack adjustment via
2044 subu $sp,$sp,[$at,$t0]. These instructions could also
2045 initialize a local variable, so we accept them only before
2046 a stack adjustment instruction was seen. */
2047 else if (!seen_sp_adjust
2048 && (high_word
== 0x3c01 /* lui $at,n */
2049 || high_word
== 0x3c08 /* lui $t0,n */
2050 || high_word
== 0x3421 /* ori $at,$at,n */
2051 || high_word
== 0x3508 /* ori $t0,$t0,n */
2052 || high_word
== 0x3401 /* ori $at,$zero,n */
2053 || high_word
== 0x3408 /* ori $t0,$zero,n */
2056 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2060 /* This instruction is not an instruction typically found
2061 in a prologue, so we must have reached the end of the
2063 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2064 loop now? Why would we need to continue scanning the function
2066 if (end_prologue_addr
== 0)
2067 end_prologue_addr
= cur_pc
;
2069 /* Check for branches and jumps. For now, only jump to
2070 register are caught (i.e. returns). */
2071 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2075 /* If the previous instruction was a jump, we must have reached
2076 the end of the prologue by now. Stop scanning so that we do
2077 not go past the function return. */
2082 if (this_cache
!= NULL
)
2085 (get_frame_register_signed (this_frame
,
2086 gdbarch_num_regs (gdbarch
) + frame_reg
)
2088 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2089 this assignment below, eventually. But it's still needed
2091 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2092 + mips_regnum (gdbarch
)->pc
]
2093 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2097 /* If we didn't reach the end of the prologue when scanning the function
2098 instructions, then set end_prologue_addr to the address of the
2099 instruction immediately after the last one we scanned. */
2100 /* brobecker/2004-10-10: I don't think this would ever happen, but
2101 we may as well be careful and do our best if we have a null
2102 end_prologue_addr. */
2103 if (end_prologue_addr
== 0)
2104 end_prologue_addr
= cur_pc
;
2106 /* In a frameless function, we might have incorrectly
2107 skipped some load immediate instructions. Undo the skipping
2108 if the load immediate was not followed by a stack adjustment. */
2109 if (load_immediate_bytes
&& !seen_sp_adjust
)
2110 end_prologue_addr
-= load_immediate_bytes
;
2112 return end_prologue_addr
;
2115 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2116 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2117 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2120 static struct mips_frame_cache
*
2121 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2123 struct mips_frame_cache
*cache
;
2125 if ((*this_cache
) != NULL
)
2126 return (*this_cache
);
2128 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2129 (*this_cache
) = cache
;
2130 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2132 /* Analyze the function prologue. */
2134 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2135 CORE_ADDR start_addr
;
2137 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2138 if (start_addr
== 0)
2139 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
2140 /* We can't analyze the prologue if we couldn't find the begining
2142 if (start_addr
== 0)
2145 mips32_scan_prologue (start_addr
, pc
, this_frame
, *this_cache
);
2148 /* gdbarch_sp_regnum contains the value and not the address. */
2149 trad_frame_set_value (cache
->saved_regs
,
2150 gdbarch_num_regs (get_frame_arch (this_frame
))
2154 return (*this_cache
);
2158 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2159 struct frame_id
*this_id
)
2161 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2163 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2166 static struct value
*
2167 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2168 void **this_cache
, int regnum
)
2170 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2172 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2176 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2177 struct frame_info
*this_frame
, void **this_cache
)
2179 CORE_ADDR pc
= get_frame_pc (this_frame
);
2180 if (! mips_pc_is_mips16 (pc
))
2185 static const struct frame_unwind mips_insn32_frame_unwind
=
2188 mips_insn32_frame_this_id
,
2189 mips_insn32_frame_prev_register
,
2191 mips_insn32_frame_sniffer
2195 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2198 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2203 static const struct frame_base mips_insn32_frame_base
=
2205 &mips_insn32_frame_unwind
,
2206 mips_insn32_frame_base_address
,
2207 mips_insn32_frame_base_address
,
2208 mips_insn32_frame_base_address
2211 static const struct frame_base
*
2212 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2214 CORE_ADDR pc
= get_frame_pc (this_frame
);
2215 if (! mips_pc_is_mips16 (pc
))
2216 return &mips_insn32_frame_base
;
2221 static struct trad_frame_cache
*
2222 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2225 CORE_ADDR start_addr
;
2226 CORE_ADDR stack_addr
;
2227 struct trad_frame_cache
*this_trad_cache
;
2228 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2229 int num_regs
= gdbarch_num_regs (gdbarch
);
2231 if ((*this_cache
) != NULL
)
2232 return (*this_cache
);
2233 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2234 (*this_cache
) = this_trad_cache
;
2236 /* The return address is in the link register. */
2237 trad_frame_set_reg_realreg (this_trad_cache
,
2238 gdbarch_pc_regnum (gdbarch
),
2239 num_regs
+ MIPS_RA_REGNUM
);
2241 /* Frame ID, since it's a frameless / stackless function, no stack
2242 space is allocated and SP on entry is the current SP. */
2243 pc
= get_frame_pc (this_frame
);
2244 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2245 stack_addr
= get_frame_register_signed (this_frame
,
2246 num_regs
+ MIPS_SP_REGNUM
);
2247 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2249 /* Assume that the frame's base is the same as the
2251 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2253 return this_trad_cache
;
2257 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2258 struct frame_id
*this_id
)
2260 struct trad_frame_cache
*this_trad_cache
2261 = mips_stub_frame_cache (this_frame
, this_cache
);
2262 trad_frame_get_id (this_trad_cache
, this_id
);
2265 static struct value
*
2266 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2267 void **this_cache
, int regnum
)
2269 struct trad_frame_cache
*this_trad_cache
2270 = mips_stub_frame_cache (this_frame
, this_cache
);
2271 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2275 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2276 struct frame_info
*this_frame
, void **this_cache
)
2279 struct obj_section
*s
;
2280 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2281 struct minimal_symbol
*msym
;
2283 /* Use the stub unwinder for unreadable code. */
2284 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2287 if (in_plt_section (pc
, NULL
))
2290 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2291 s
= find_pc_section (pc
);
2294 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2295 ".MIPS.stubs") == 0)
2298 /* Calling a PIC function from a non-PIC function passes through a
2299 stub. The stub for foo is named ".pic.foo". */
2300 msym
= lookup_minimal_symbol_by_pc (pc
);
2302 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2303 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2309 static const struct frame_unwind mips_stub_frame_unwind
=
2312 mips_stub_frame_this_id
,
2313 mips_stub_frame_prev_register
,
2315 mips_stub_frame_sniffer
2319 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2322 struct trad_frame_cache
*this_trad_cache
2323 = mips_stub_frame_cache (this_frame
, this_cache
);
2324 return trad_frame_get_this_base (this_trad_cache
);
2327 static const struct frame_base mips_stub_frame_base
=
2329 &mips_stub_frame_unwind
,
2330 mips_stub_frame_base_address
,
2331 mips_stub_frame_base_address
,
2332 mips_stub_frame_base_address
2335 static const struct frame_base
*
2336 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2338 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2339 return &mips_stub_frame_base
;
2344 /* mips_addr_bits_remove - remove useless address bits */
2347 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2349 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2350 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2351 /* This hack is a work-around for existing boards using PMON, the
2352 simulator, and any other 64-bit targets that doesn't have true
2353 64-bit addressing. On these targets, the upper 32 bits of
2354 addresses are ignored by the hardware. Thus, the PC or SP are
2355 likely to have been sign extended to all 1s by instruction
2356 sequences that load 32-bit addresses. For example, a typical
2357 piece of code that loads an address is this:
2359 lui $r2, <upper 16 bits>
2360 ori $r2, <lower 16 bits>
2362 But the lui sign-extends the value such that the upper 32 bits
2363 may be all 1s. The workaround is simply to mask off these
2364 bits. In the future, gcc may be changed to support true 64-bit
2365 addressing, and this masking will have to be disabled. */
2366 return addr
&= 0xffffffffUL
;
2371 /* Instructions used during single-stepping of atomic sequences. */
2372 #define LL_OPCODE 0x30
2373 #define LLD_OPCODE 0x34
2374 #define SC_OPCODE 0x38
2375 #define SCD_OPCODE 0x3c
2377 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2378 instruction and ending with a SC/SCD instruction. If such a sequence
2379 is found, attempt to step through it. A breakpoint is placed at the end of
2383 deal_with_atomic_sequence (CORE_ADDR pc
)
2385 CORE_ADDR breaks
[2] = {-1, -1};
2387 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2391 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2392 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2397 insn
= mips_fetch_instruction (loc
);
2398 /* Assume all atomic sequences start with a ll/lld instruction. */
2399 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2402 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2404 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2407 loc
+= MIPS_INSN32_SIZE
;
2408 insn
= mips_fetch_instruction (loc
);
2410 /* Assume that there is at most one branch in the atomic
2411 sequence. If a branch is found, put a breakpoint in its
2412 destination address. */
2413 switch (itype_op (insn
))
2415 case 0: /* SPECIAL */
2416 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2417 return 0; /* fallback to the standard single-step code. */
2419 case 1: /* REGIMM */
2420 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2424 return 0; /* fallback to the standard single-step code. */
2431 case 22: /* BLEZL */
2432 case 23: /* BGTTL */
2438 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2443 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2444 if (last_breakpoint
>= 1)
2445 return 0; /* More than one branch found, fallback to the
2446 standard single-step code. */
2447 breaks
[1] = branch_bp
;
2451 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2455 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2456 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2459 loc
+= MIPS_INSN32_SIZE
;
2461 /* Insert a breakpoint right after the end of the atomic sequence. */
2464 /* Check for duplicated breakpoints. Check also for a breakpoint
2465 placed (branch instruction's destination) in the atomic sequence */
2466 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2467 last_breakpoint
= 0;
2469 /* Effectively inserts the breakpoints. */
2470 for (index
= 0; index
<= last_breakpoint
; index
++)
2471 insert_single_step_breakpoint (breaks
[index
]);
2476 /* mips_software_single_step() is called just before we want to resume
2477 the inferior, if we want to single-step it but there is no hardware
2478 or kernel single-step support (MIPS on GNU/Linux for example). We find
2479 the target of the coming instruction and breakpoint it. */
2482 mips_software_single_step (struct frame_info
*frame
)
2484 CORE_ADDR pc
, next_pc
;
2486 pc
= get_frame_pc (frame
);
2487 if (deal_with_atomic_sequence (pc
))
2490 next_pc
= mips_next_pc (frame
, pc
);
2492 insert_single_step_breakpoint (next_pc
);
2496 /* Test whether the PC points to the return instruction at the
2497 end of a function. */
2500 mips_about_to_return (CORE_ADDR pc
)
2502 if (mips_pc_is_mips16 (pc
))
2503 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2504 generates a "jr $ra"; other times it generates code to load
2505 the return address from the stack to an accessible register (such
2506 as $a3), then a "jr" using that register. This second case
2507 is almost impossible to distinguish from an indirect jump
2508 used for switch statements, so we don't even try. */
2509 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2511 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2515 /* This fencepost looks highly suspicious to me. Removing it also
2516 seems suspicious as it could affect remote debugging across serial
2520 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2526 struct inferior
*inf
;
2528 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2530 fence
= start_pc
- heuristic_fence_post
;
2534 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2535 fence
= VM_MIN_ADDRESS
;
2537 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2539 inf
= current_inferior ();
2541 /* search back for previous return */
2542 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2543 if (start_pc
< fence
)
2545 /* It's not clear to me why we reach this point when
2546 stop_soon, but with this test, at least we
2547 don't print out warnings for every child forked (eg, on
2548 decstation). 22apr93 rich@cygnus.com. */
2549 if (inf
->stop_soon
== NO_STOP_QUIETLY
)
2551 static int blurb_printed
= 0;
2553 warning (_("GDB can't find the start of the function at 0x%s."),
2558 /* This actually happens frequently in embedded
2559 development, when you first connect to a board
2560 and your stack pointer and pc are nowhere in
2561 particular. This message needs to give people
2562 in that situation enough information to
2563 determine that it's no big deal. */
2564 printf_filtered ("\n\
2565 GDB is unable to find the start of the function at 0x%s\n\
2566 and thus can't determine the size of that function's stack frame.\n\
2567 This means that GDB may be unable to access that stack frame, or\n\
2568 the frames below it.\n\
2569 This problem is most likely caused by an invalid program counter or\n\
2571 However, if you think GDB should simply search farther back\n\
2572 from 0x%s for code which looks like the beginning of a\n\
2573 function, you can increase the range of the search using the `set\n\
2574 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2581 else if (mips_pc_is_mips16 (start_pc
))
2583 unsigned short inst
;
2585 /* On MIPS16, any one of the following is likely to be the
2586 start of a function:
2592 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2593 inst
= mips_fetch_instruction (start_pc
);
2594 if ((inst
& 0xff80) == 0x6480) /* save */
2596 if (start_pc
- instlen
>= fence
)
2598 inst
= mips_fetch_instruction (start_pc
- instlen
);
2599 if ((inst
& 0xf800) == 0xf000) /* extend */
2600 start_pc
-= instlen
;
2604 else if (((inst
& 0xf81f) == 0xe809
2605 && (inst
& 0x700) != 0x700) /* entry */
2606 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2607 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2608 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2610 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2611 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2616 else if (mips_about_to_return (start_pc
))
2618 /* Skip return and its delay slot. */
2619 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2626 struct mips_objfile_private
2632 /* According to the current ABI, should the type be passed in a
2633 floating-point register (assuming that there is space)? When there
2634 is no FPU, FP are not even considered as possible candidates for
2635 FP registers and, consequently this returns false - forces FP
2636 arguments into integer registers. */
2639 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2640 struct type
*arg_type
)
2642 return ((typecode
== TYPE_CODE_FLT
2643 || (MIPS_EABI (gdbarch
)
2644 && (typecode
== TYPE_CODE_STRUCT
2645 || typecode
== TYPE_CODE_UNION
)
2646 && TYPE_NFIELDS (arg_type
) == 1
2647 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2649 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2652 /* On o32, argument passing in GPRs depends on the alignment of the type being
2653 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2656 mips_type_needs_double_align (struct type
*type
)
2658 enum type_code typecode
= TYPE_CODE (type
);
2660 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2662 else if (typecode
== TYPE_CODE_STRUCT
)
2664 if (TYPE_NFIELDS (type
) < 1)
2666 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2668 else if (typecode
== TYPE_CODE_UNION
)
2672 n
= TYPE_NFIELDS (type
);
2673 for (i
= 0; i
< n
; i
++)
2674 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2681 /* Adjust the address downward (direction of stack growth) so that it
2682 is correctly aligned for a new stack frame. */
2684 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2686 return align_down (addr
, 16);
2690 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2691 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2692 int nargs
, struct value
**args
, CORE_ADDR sp
,
2693 int struct_return
, CORE_ADDR struct_addr
)
2699 int stack_offset
= 0;
2700 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2701 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2702 int regsize
= mips_abi_regsize (gdbarch
);
2704 /* For shared libraries, "t9" needs to point at the function
2706 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2708 /* Set the return address register to point to the entry point of
2709 the program, where a breakpoint lies in wait. */
2710 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2712 /* First ensure that the stack and structure return address (if any)
2713 are properly aligned. The stack has to be at least 64-bit
2714 aligned even on 32-bit machines, because doubles must be 64-bit
2715 aligned. For n32 and n64, stack frames need to be 128-bit
2716 aligned, so we round to this widest known alignment. */
2718 sp
= align_down (sp
, 16);
2719 struct_addr
= align_down (struct_addr
, 16);
2721 /* Now make space on the stack for the args. We allocate more
2722 than necessary for EABI, because the first few arguments are
2723 passed in registers, but that's OK. */
2724 for (argnum
= 0; argnum
< nargs
; argnum
++)
2725 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2726 sp
-= align_up (len
, 16);
2729 fprintf_unfiltered (gdb_stdlog
,
2730 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2731 paddr_nz (sp
), (long) align_up (len
, 16));
2733 /* Initialize the integer and float register pointers. */
2734 argreg
= MIPS_A0_REGNUM
;
2735 float_argreg
= mips_fpa0_regnum (gdbarch
);
2737 /* The struct_return pointer occupies the first parameter-passing reg. */
2741 fprintf_unfiltered (gdb_stdlog
,
2742 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2743 argreg
, paddr_nz (struct_addr
));
2744 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2747 /* Now load as many as possible of the first arguments into
2748 registers, and push the rest onto the stack. Loop thru args
2749 from first to last. */
2750 for (argnum
= 0; argnum
< nargs
; argnum
++)
2752 const gdb_byte
*val
;
2753 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2754 struct value
*arg
= args
[argnum
];
2755 struct type
*arg_type
= check_typedef (value_type (arg
));
2756 int len
= TYPE_LENGTH (arg_type
);
2757 enum type_code typecode
= TYPE_CODE (arg_type
);
2760 fprintf_unfiltered (gdb_stdlog
,
2761 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2762 argnum
+ 1, len
, (int) typecode
);
2764 /* The EABI passes structures that do not fit in a register by
2767 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2769 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2770 typecode
= TYPE_CODE_PTR
;
2774 fprintf_unfiltered (gdb_stdlog
, " push");
2777 val
= value_contents (arg
);
2779 /* 32-bit ABIs always start floating point arguments in an
2780 even-numbered floating point register. Round the FP register
2781 up before the check to see if there are any FP registers
2782 left. Non MIPS_EABI targets also pass the FP in the integer
2783 registers so also round up normal registers. */
2784 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2786 if ((float_argreg
& 1))
2790 /* Floating point arguments passed in registers have to be
2791 treated specially. On 32-bit architectures, doubles
2792 are passed in register pairs; the even register gets
2793 the low word, and the odd register gets the high word.
2794 On non-EABI processors, the first two floating point arguments are
2795 also copied to general registers, because MIPS16 functions
2796 don't use float registers for arguments. This duplication of
2797 arguments in general registers can't hurt non-MIPS16 functions
2798 because those registers are normally skipped. */
2799 /* MIPS_EABI squeezes a struct that contains a single floating
2800 point value into an FP register instead of pushing it onto the
2802 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
2803 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
2805 /* EABI32 will pass doubles in consecutive registers, even on
2806 64-bit cores. At one time, we used to check the size of
2807 `float_argreg' to determine whether or not to pass doubles
2808 in consecutive registers, but this is not sufficient for
2809 making the ABI determination. */
2810 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2812 int low_offset
= gdbarch_byte_order (gdbarch
)
2813 == BFD_ENDIAN_BIG
? 4 : 0;
2814 unsigned long regval
;
2816 /* Write the low word of the double to the even register(s). */
2817 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2819 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2820 float_argreg
, phex (regval
, 4));
2821 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2823 /* Write the high word of the double to the odd register(s). */
2824 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2826 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2827 float_argreg
, phex (regval
, 4));
2828 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2832 /* This is a floating point value that fits entirely
2833 in a single register. */
2834 /* On 32 bit ABI's the float_argreg is further adjusted
2835 above to ensure that it is even register aligned. */
2836 LONGEST regval
= extract_unsigned_integer (val
, len
);
2838 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2839 float_argreg
, phex (regval
, len
));
2840 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2845 /* Copy the argument to general registers or the stack in
2846 register-sized pieces. Large arguments are split between
2847 registers and stack. */
2848 /* Note: structs whose size is not a multiple of regsize
2849 are treated specially: Irix cc passes
2850 them in registers where gcc sometimes puts them on the
2851 stack. For maximum compatibility, we will put them in
2853 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2855 /* Note: Floating-point values that didn't fit into an FP
2856 register are only written to memory. */
2859 /* Remember if the argument was written to the stack. */
2860 int stack_used_p
= 0;
2861 int partial_len
= (len
< regsize
? len
: regsize
);
2864 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2867 /* Write this portion of the argument to the stack. */
2868 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
2870 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2872 /* Should shorter than int integer values be
2873 promoted to int before being stored? */
2874 int longword_offset
= 0;
2877 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2880 && (typecode
== TYPE_CODE_INT
2881 || typecode
== TYPE_CODE_PTR
2882 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2883 longword_offset
= regsize
- len
;
2884 else if ((typecode
== TYPE_CODE_STRUCT
2885 || typecode
== TYPE_CODE_UNION
)
2886 && TYPE_LENGTH (arg_type
) < regsize
)
2887 longword_offset
= regsize
- len
;
2892 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2893 paddr_nz (stack_offset
));
2894 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2895 paddr_nz (longword_offset
));
2898 addr
= sp
+ stack_offset
+ longword_offset
;
2903 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2905 for (i
= 0; i
< partial_len
; i
++)
2907 fprintf_unfiltered (gdb_stdlog
, "%02x",
2911 write_memory (addr
, val
, partial_len
);
2914 /* Note!!! This is NOT an else clause. Odd sized
2915 structs may go thru BOTH paths. Floating point
2916 arguments will not. */
2917 /* Write this portion of the argument to a general
2918 purpose register. */
2919 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
2920 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2923 extract_unsigned_integer (val
, partial_len
);
2926 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2928 phex (regval
, regsize
));
2929 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2936 /* Compute the the offset into the stack at which we
2937 will copy the next parameter.
2939 In the new EABI (and the NABI32), the stack_offset
2940 only needs to be adjusted when it has been used. */
2943 stack_offset
+= align_up (partial_len
, regsize
);
2947 fprintf_unfiltered (gdb_stdlog
, "\n");
2950 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2952 /* Return adjusted stack pointer. */
2956 /* Determine the return value convention being used. */
2958 static enum return_value_convention
2959 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2960 struct type
*type
, struct regcache
*regcache
,
2961 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2963 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2964 int fp_return_type
= 0;
2965 int offset
, regnum
, xfer
;
2967 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2968 return RETURN_VALUE_STRUCT_CONVENTION
;
2970 /* Floating point type? */
2971 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2973 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2975 /* Structs with a single field of float type
2976 are returned in a floating point register. */
2977 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
2978 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2979 && TYPE_NFIELDS (type
) == 1)
2981 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
2983 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
2990 /* A floating-point value belongs in the least significant part
2993 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
2994 regnum
= mips_regnum (gdbarch
)->fp0
;
2998 /* An integer value goes in V0/V1. */
3000 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3001 regnum
= MIPS_V0_REGNUM
;
3004 offset
< TYPE_LENGTH (type
);
3005 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3007 xfer
= mips_abi_regsize (gdbarch
);
3008 if (offset
+ xfer
> TYPE_LENGTH (type
))
3009 xfer
= TYPE_LENGTH (type
) - offset
;
3010 mips_xfer_register (gdbarch
, regcache
,
3011 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3012 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3016 return RETURN_VALUE_REGISTER_CONVENTION
;
3020 /* N32/N64 ABI stuff. */
3022 /* Search for a naturally aligned double at OFFSET inside a struct
3023 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3027 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3032 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3035 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3038 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3041 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3044 struct type
*field_type
;
3046 /* We're only looking at normal fields. */
3047 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3048 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3051 /* If we have gone past the offset, there is no double to pass. */
3052 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3056 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3058 /* If this field is entirely before the requested offset, go
3059 on to the next one. */
3060 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3063 /* If this is our special aligned double, we can stop. */
3064 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3065 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3068 /* This field starts at or before the requested offset, and
3069 overlaps it. If it is a structure, recurse inwards. */
3070 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3077 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3078 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3079 int nargs
, struct value
**args
, CORE_ADDR sp
,
3080 int struct_return
, CORE_ADDR struct_addr
)
3086 int stack_offset
= 0;
3087 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3088 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3090 /* For shared libraries, "t9" needs to point at the function
3092 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3094 /* Set the return address register to point to the entry point of
3095 the program, where a breakpoint lies in wait. */
3096 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3098 /* First ensure that the stack and structure return address (if any)
3099 are properly aligned. The stack has to be at least 64-bit
3100 aligned even on 32-bit machines, because doubles must be 64-bit
3101 aligned. For n32 and n64, stack frames need to be 128-bit
3102 aligned, so we round to this widest known alignment. */
3104 sp
= align_down (sp
, 16);
3105 struct_addr
= align_down (struct_addr
, 16);
3107 /* Now make space on the stack for the args. */
3108 for (argnum
= 0; argnum
< nargs
; argnum
++)
3109 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3110 sp
-= align_up (len
, 16);
3113 fprintf_unfiltered (gdb_stdlog
,
3114 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3115 paddr_nz (sp
), (long) align_up (len
, 16));
3117 /* Initialize the integer and float register pointers. */
3118 argreg
= MIPS_A0_REGNUM
;
3119 float_argreg
= mips_fpa0_regnum (gdbarch
);
3121 /* The struct_return pointer occupies the first parameter-passing reg. */
3125 fprintf_unfiltered (gdb_stdlog
,
3126 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3127 argreg
, paddr_nz (struct_addr
));
3128 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3131 /* Now load as many as possible of the first arguments into
3132 registers, and push the rest onto the stack. Loop thru args
3133 from first to last. */
3134 for (argnum
= 0; argnum
< nargs
; argnum
++)
3136 const gdb_byte
*val
;
3137 struct value
*arg
= args
[argnum
];
3138 struct type
*arg_type
= check_typedef (value_type (arg
));
3139 int len
= TYPE_LENGTH (arg_type
);
3140 enum type_code typecode
= TYPE_CODE (arg_type
);
3143 fprintf_unfiltered (gdb_stdlog
,
3144 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3145 argnum
+ 1, len
, (int) typecode
);
3147 val
= value_contents (arg
);
3149 /* A 128-bit long double value requires an even-odd pair of
3150 floating-point registers. */
3152 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3153 && (float_argreg
& 1))
3159 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3160 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3162 /* This is a floating point value that fits entirely
3163 in a single register or a pair of registers. */
3164 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3165 LONGEST regval
= extract_unsigned_integer (val
, reglen
);
3167 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3168 float_argreg
, phex (regval
, reglen
));
3169 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3172 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3173 argreg
, phex (regval
, reglen
));
3174 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3179 regval
= extract_unsigned_integer (val
+ reglen
, reglen
);
3181 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3182 float_argreg
, phex (regval
, reglen
));
3183 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3186 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3187 argreg
, phex (regval
, reglen
));
3188 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3195 /* Copy the argument to general registers or the stack in
3196 register-sized pieces. Large arguments are split between
3197 registers and stack. */
3198 /* For N32/N64, structs, unions, or other composite types are
3199 treated as a sequence of doublewords, and are passed in integer
3200 or floating point registers as though they were simple scalar
3201 parameters to the extent that they fit, with any excess on the
3202 stack packed according to the normal memory layout of the
3204 The caller does not reserve space for the register arguments;
3205 the callee is responsible for reserving it if required. */
3206 /* Note: Floating-point values that didn't fit into an FP
3207 register are only written to memory. */
3210 /* Remember if the argument was written to the stack. */
3211 int stack_used_p
= 0;
3212 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3215 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3218 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3219 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3221 /* Write this portion of the argument to the stack. */
3222 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3224 /* Should shorter than int integer values be
3225 promoted to int before being stored? */
3226 int longword_offset
= 0;
3229 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3231 if ((typecode
== TYPE_CODE_INT
3232 || typecode
== TYPE_CODE_PTR
)
3234 longword_offset
= MIPS64_REGSIZE
- len
;
3239 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3240 paddr_nz (stack_offset
));
3241 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3242 paddr_nz (longword_offset
));
3245 addr
= sp
+ stack_offset
+ longword_offset
;
3250 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3252 for (i
= 0; i
< partial_len
; i
++)
3254 fprintf_unfiltered (gdb_stdlog
, "%02x",
3258 write_memory (addr
, val
, partial_len
);
3261 /* Note!!! This is NOT an else clause. Odd sized
3262 structs may go thru BOTH paths. */
3263 /* Write this portion of the argument to a general
3264 purpose register. */
3265 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3269 /* Sign extend pointers, 32-bit integers and signed
3270 16-bit and 8-bit integers; everything else is taken
3273 if ((partial_len
== 4
3274 && (typecode
== TYPE_CODE_PTR
3275 || typecode
== TYPE_CODE_INT
))
3277 && typecode
== TYPE_CODE_INT
3278 && !TYPE_UNSIGNED (arg_type
)))
3279 regval
= extract_signed_integer (val
, partial_len
);
3281 regval
= extract_unsigned_integer (val
, partial_len
);
3283 /* A non-floating-point argument being passed in a
3284 general register. If a struct or union, and if
3285 the remaining length is smaller than the register
3286 size, we have to adjust the register value on
3289 It does not seem to be necessary to do the
3290 same for integral types. */
3292 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3293 && partial_len
< MIPS64_REGSIZE
3294 && (typecode
== TYPE_CODE_STRUCT
3295 || typecode
== TYPE_CODE_UNION
))
3296 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3300 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3302 phex (regval
, MIPS64_REGSIZE
));
3303 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3305 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3306 TYPE_LENGTH (arg_type
) - len
))
3309 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3311 phex (regval
, MIPS64_REGSIZE
));
3312 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3323 /* Compute the the offset into the stack at which we
3324 will copy the next parameter.
3326 In N32 (N64?), the stack_offset only needs to be
3327 adjusted when it has been used. */
3330 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3334 fprintf_unfiltered (gdb_stdlog
, "\n");
3337 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3339 /* Return adjusted stack pointer. */
3343 static enum return_value_convention
3344 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3345 struct type
*type
, struct regcache
*regcache
,
3346 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3348 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3350 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3352 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3353 if needed), as appropriate for the type. Composite results (struct,
3354 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3357 * A struct with only one or two floating point fields is returned in $f0
3358 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3361 * Any other struct or union results of at most 128 bits are returned in
3362 $2 (first 64 bits) and $3 (remainder, if necessary).
3364 * Larger composite results are handled by converting the function to a
3365 procedure with an implicit first parameter, which is a pointer to an area
3366 reserved by the caller to receive the result. [The o32-bit ABI requires
3367 that all composite results be handled by conversion to implicit first
3368 parameters. The MIPS/SGI Fortran implementation has always made a
3369 specific exception to return COMPLEX results in the floating point
3372 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
3373 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3374 return RETURN_VALUE_STRUCT_CONVENTION
;
3375 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3376 && TYPE_LENGTH (type
) == 16
3377 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3379 /* A 128-bit floating-point value fills both $f0 and $f2. The
3380 two registers are used in the same as memory order, so the
3381 eight bytes with the lower memory address are in $f0. */
3383 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3384 mips_xfer_register (gdbarch
, regcache
,
3385 gdbarch_num_regs (gdbarch
)
3386 + mips_regnum (gdbarch
)->fp0
,
3387 8, gdbarch_byte_order (gdbarch
),
3388 readbuf
, writebuf
, 0);
3389 mips_xfer_register (gdbarch
, regcache
,
3390 gdbarch_num_regs (gdbarch
)
3391 + mips_regnum (gdbarch
)->fp0
+ 2,
3392 8, gdbarch_byte_order (gdbarch
),
3393 readbuf
? readbuf
+ 8 : readbuf
,
3394 writebuf
? writebuf
+ 8 : writebuf
, 0);
3395 return RETURN_VALUE_REGISTER_CONVENTION
;
3397 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3398 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3400 /* A single or double floating-point value that fits in FP0. */
3402 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3403 mips_xfer_register (gdbarch
, regcache
,
3404 gdbarch_num_regs (gdbarch
)
3405 + mips_regnum (gdbarch
)->fp0
,
3407 gdbarch_byte_order (gdbarch
),
3408 readbuf
, writebuf
, 0);
3409 return RETURN_VALUE_REGISTER_CONVENTION
;
3411 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3412 && TYPE_NFIELDS (type
) <= 2
3413 && TYPE_NFIELDS (type
) >= 1
3414 && ((TYPE_NFIELDS (type
) == 1
3415 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3417 || (TYPE_NFIELDS (type
) == 2
3418 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3420 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3421 == TYPE_CODE_FLT
))))
3423 /* A struct that contains one or two floats. Each value is part
3424 in the least significant part of their floating point
3425 register (or GPR, for soft float). */
3428 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3429 ? mips_regnum (gdbarch
)->fp0
3431 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3433 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3436 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3438 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3440 /* A 16-byte long double field goes in two consecutive
3442 mips_xfer_register (gdbarch
, regcache
,
3443 gdbarch_num_regs (gdbarch
) + regnum
,
3445 gdbarch_byte_order (gdbarch
),
3446 readbuf
, writebuf
, offset
);
3447 mips_xfer_register (gdbarch
, regcache
,
3448 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3450 gdbarch_byte_order (gdbarch
),
3451 readbuf
, writebuf
, offset
+ 8);
3454 mips_xfer_register (gdbarch
, regcache
,
3455 gdbarch_num_regs (gdbarch
) + regnum
,
3456 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3457 gdbarch_byte_order (gdbarch
),
3458 readbuf
, writebuf
, offset
);
3460 return RETURN_VALUE_REGISTER_CONVENTION
;
3462 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3463 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3465 /* A structure or union. Extract the left justified value,
3466 regardless of the byte order. I.e. DO NOT USE
3470 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3471 offset
< TYPE_LENGTH (type
);
3472 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3474 int xfer
= register_size (gdbarch
, regnum
);
3475 if (offset
+ xfer
> TYPE_LENGTH (type
))
3476 xfer
= TYPE_LENGTH (type
) - offset
;
3478 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3479 offset
, xfer
, regnum
);
3480 mips_xfer_register (gdbarch
, regcache
,
3481 gdbarch_num_regs (gdbarch
) + regnum
,
3482 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3485 return RETURN_VALUE_REGISTER_CONVENTION
;
3489 /* A scalar extract each part but least-significant-byte
3493 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3494 offset
< TYPE_LENGTH (type
);
3495 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3497 int xfer
= register_size (gdbarch
, regnum
);
3498 if (offset
+ xfer
> TYPE_LENGTH (type
))
3499 xfer
= TYPE_LENGTH (type
) - offset
;
3501 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3502 offset
, xfer
, regnum
);
3503 mips_xfer_register (gdbarch
, regcache
,
3504 gdbarch_num_regs (gdbarch
) + regnum
,
3505 xfer
, gdbarch_byte_order (gdbarch
),
3506 readbuf
, writebuf
, offset
);
3508 return RETURN_VALUE_REGISTER_CONVENTION
;
3512 /* O32 ABI stuff. */
3515 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3516 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3517 int nargs
, struct value
**args
, CORE_ADDR sp
,
3518 int struct_return
, CORE_ADDR struct_addr
)
3524 int stack_offset
= 0;
3525 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3526 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3528 /* For shared libraries, "t9" needs to point at the function
3530 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3532 /* Set the return address register to point to the entry point of
3533 the program, where a breakpoint lies in wait. */
3534 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3536 /* First ensure that the stack and structure return address (if any)
3537 are properly aligned. The stack has to be at least 64-bit
3538 aligned even on 32-bit machines, because doubles must be 64-bit
3539 aligned. For n32 and n64, stack frames need to be 128-bit
3540 aligned, so we round to this widest known alignment. */
3542 sp
= align_down (sp
, 16);
3543 struct_addr
= align_down (struct_addr
, 16);
3545 /* Now make space on the stack for the args. */
3546 for (argnum
= 0; argnum
< nargs
; argnum
++)
3548 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3549 int arglen
= TYPE_LENGTH (arg_type
);
3551 /* Align to double-word if necessary. */
3552 if (mips_type_needs_double_align (arg_type
))
3553 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3554 /* Allocate space on the stack. */
3555 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3557 sp
-= align_up (len
, 16);
3560 fprintf_unfiltered (gdb_stdlog
,
3561 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3562 paddr_nz (sp
), (long) align_up (len
, 16));
3564 /* Initialize the integer and float register pointers. */
3565 argreg
= MIPS_A0_REGNUM
;
3566 float_argreg
= mips_fpa0_regnum (gdbarch
);
3568 /* The struct_return pointer occupies the first parameter-passing reg. */
3572 fprintf_unfiltered (gdb_stdlog
,
3573 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3574 argreg
, paddr_nz (struct_addr
));
3575 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3576 stack_offset
+= MIPS32_REGSIZE
;
3579 /* Now load as many as possible of the first arguments into
3580 registers, and push the rest onto the stack. Loop thru args
3581 from first to last. */
3582 for (argnum
= 0; argnum
< nargs
; argnum
++)
3584 const gdb_byte
*val
;
3585 struct value
*arg
= args
[argnum
];
3586 struct type
*arg_type
= check_typedef (value_type (arg
));
3587 int len
= TYPE_LENGTH (arg_type
);
3588 enum type_code typecode
= TYPE_CODE (arg_type
);
3591 fprintf_unfiltered (gdb_stdlog
,
3592 "mips_o32_push_dummy_call: %d len=%d type=%d",
3593 argnum
+ 1, len
, (int) typecode
);
3595 val
= value_contents (arg
);
3597 /* 32-bit ABIs always start floating point arguments in an
3598 even-numbered floating point register. Round the FP register
3599 up before the check to see if there are any FP registers
3600 left. O32/O64 targets also pass the FP in the integer
3601 registers so also round up normal registers. */
3602 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3604 if ((float_argreg
& 1))
3608 /* Floating point arguments passed in registers have to be
3609 treated specially. On 32-bit architectures, doubles
3610 are passed in register pairs; the even register gets
3611 the low word, and the odd register gets the high word.
3612 On O32/O64, the first two floating point arguments are
3613 also copied to general registers, because MIPS16 functions
3614 don't use float registers for arguments. This duplication of
3615 arguments in general registers can't hurt non-MIPS16 functions
3616 because those registers are normally skipped. */
3618 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3619 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3621 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3623 int low_offset
= gdbarch_byte_order (gdbarch
)
3624 == BFD_ENDIAN_BIG
? 4 : 0;
3625 unsigned long regval
;
3627 /* Write the low word of the double to the even register(s). */
3628 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3630 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3631 float_argreg
, phex (regval
, 4));
3632 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3634 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3635 argreg
, phex (regval
, 4));
3636 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3638 /* Write the high word of the double to the odd register(s). */
3639 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3641 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3642 float_argreg
, phex (regval
, 4));
3643 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3646 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3647 argreg
, phex (regval
, 4));
3648 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3652 /* This is a floating point value that fits entirely
3653 in a single register. */
3654 /* On 32 bit ABI's the float_argreg is further adjusted
3655 above to ensure that it is even register aligned. */
3656 LONGEST regval
= extract_unsigned_integer (val
, len
);
3658 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3659 float_argreg
, phex (regval
, len
));
3660 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3661 /* Although two FP registers are reserved for each
3662 argument, only one corresponding integer register is
3665 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3666 argreg
, phex (regval
, len
));
3667 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3669 /* Reserve space for the FP register. */
3670 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3674 /* Copy the argument to general registers or the stack in
3675 register-sized pieces. Large arguments are split between
3676 registers and stack. */
3677 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3678 are treated specially: Irix cc passes
3679 them in registers where gcc sometimes puts them on the
3680 stack. For maximum compatibility, we will put them in
3682 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3683 && len
% MIPS32_REGSIZE
!= 0);
3684 /* Structures should be aligned to eight bytes (even arg registers)
3685 on MIPS_ABI_O32, if their first member has double precision. */
3686 if (mips_type_needs_double_align (arg_type
))
3691 stack_offset
+= MIPS32_REGSIZE
;
3696 /* Remember if the argument was written to the stack. */
3697 int stack_used_p
= 0;
3698 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3701 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3704 /* Write this portion of the argument to the stack. */
3705 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3706 || odd_sized_struct
)
3708 /* Should shorter than int integer values be
3709 promoted to int before being stored? */
3710 int longword_offset
= 0;
3716 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3717 paddr_nz (stack_offset
));
3718 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3719 paddr_nz (longword_offset
));
3722 addr
= sp
+ stack_offset
+ longword_offset
;
3727 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3729 for (i
= 0; i
< partial_len
; i
++)
3731 fprintf_unfiltered (gdb_stdlog
, "%02x",
3735 write_memory (addr
, val
, partial_len
);
3738 /* Note!!! This is NOT an else clause. Odd sized
3739 structs may go thru BOTH paths. */
3740 /* Write this portion of the argument to a general
3741 purpose register. */
3742 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3744 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3745 /* Value may need to be sign extended, because
3746 mips_isa_regsize() != mips_abi_regsize(). */
3748 /* A non-floating-point argument being passed in a
3749 general register. If a struct or union, and if
3750 the remaining length is smaller than the register
3751 size, we have to adjust the register value on
3754 It does not seem to be necessary to do the
3755 same for integral types.
3757 Also don't do this adjustment on O64 binaries.
3759 cagney/2001-07-23: gdb/179: Also, GCC, when
3760 outputting LE O32 with sizeof (struct) <
3761 mips_abi_regsize(), generates a left shift
3762 as part of storing the argument in a register
3763 (the left shift isn't generated when
3764 sizeof (struct) >= mips_abi_regsize()). Since
3765 it is quite possible that this is GCC
3766 contradicting the LE/O32 ABI, GDB has not been
3767 adjusted to accommodate this. Either someone
3768 needs to demonstrate that the LE/O32 ABI
3769 specifies such a left shift OR this new ABI gets
3770 identified as such and GDB gets tweaked
3773 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3774 && partial_len
< MIPS32_REGSIZE
3775 && (typecode
== TYPE_CODE_STRUCT
3776 || typecode
== TYPE_CODE_UNION
))
3777 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3781 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3783 phex (regval
, MIPS32_REGSIZE
));
3784 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3787 /* Prevent subsequent floating point arguments from
3788 being passed in floating point registers. */
3789 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
3795 /* Compute the the offset into the stack at which we
3796 will copy the next parameter.
3798 In older ABIs, the caller reserved space for
3799 registers that contained arguments. This was loosely
3800 refered to as their "home". Consequently, space is
3801 always allocated. */
3803 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3807 fprintf_unfiltered (gdb_stdlog
, "\n");
3810 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3812 /* Return adjusted stack pointer. */
3816 static enum return_value_convention
3817 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3818 struct type
*type
, struct regcache
*regcache
,
3819 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3821 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3823 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3824 || TYPE_CODE (type
) == TYPE_CODE_UNION
3825 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3826 return RETURN_VALUE_STRUCT_CONVENTION
;
3827 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3828 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3830 /* A single-precision floating-point value. It fits in the
3831 least significant part of FP0. */
3833 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3834 mips_xfer_register (gdbarch
, regcache
,
3835 gdbarch_num_regs (gdbarch
)
3836 + mips_regnum (gdbarch
)->fp0
,
3838 gdbarch_byte_order (gdbarch
),
3839 readbuf
, writebuf
, 0);
3840 return RETURN_VALUE_REGISTER_CONVENTION
;
3842 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3843 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3845 /* A double-precision floating-point value. The most
3846 significant part goes in FP1, and the least significant in
3849 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3850 switch (gdbarch_byte_order (gdbarch
))
3852 case BFD_ENDIAN_LITTLE
:
3853 mips_xfer_register (gdbarch
, regcache
,
3854 gdbarch_num_regs (gdbarch
)
3855 + mips_regnum (gdbarch
)->fp0
+
3856 0, 4, gdbarch_byte_order (gdbarch
),
3857 readbuf
, writebuf
, 0);
3858 mips_xfer_register (gdbarch
, regcache
,
3859 gdbarch_num_regs (gdbarch
)
3860 + mips_regnum (gdbarch
)->fp0
+ 1,
3861 4, gdbarch_byte_order (gdbarch
),
3862 readbuf
, writebuf
, 4);
3864 case BFD_ENDIAN_BIG
:
3865 mips_xfer_register (gdbarch
, regcache
,
3866 gdbarch_num_regs (gdbarch
)
3867 + mips_regnum (gdbarch
)->fp0
+ 1,
3868 4, gdbarch_byte_order (gdbarch
),
3869 readbuf
, writebuf
, 0);
3870 mips_xfer_register (gdbarch
, regcache
,
3871 gdbarch_num_regs (gdbarch
)
3872 + mips_regnum (gdbarch
)->fp0
+ 0,
3873 4, gdbarch_byte_order (gdbarch
),
3874 readbuf
, writebuf
, 4);
3877 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3879 return RETURN_VALUE_REGISTER_CONVENTION
;
3882 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3883 && TYPE_NFIELDS (type
) <= 2
3884 && TYPE_NFIELDS (type
) >= 1
3885 && ((TYPE_NFIELDS (type
) == 1
3886 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3888 || (TYPE_NFIELDS (type
) == 2
3889 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3891 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3893 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3895 /* A struct that contains one or two floats. Each value is part
3896 in the least significant part of their floating point
3898 gdb_byte reg
[MAX_REGISTER_SIZE
];
3901 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3902 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3904 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3907 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3909 mips_xfer_register (gdbarch
, regcache
,
3910 gdbarch_num_regs (gdbarch
) + regnum
,
3911 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3912 gdbarch_byte_order (gdbarch
),
3913 readbuf
, writebuf
, offset
);
3915 return RETURN_VALUE_REGISTER_CONVENTION
;
3919 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3920 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3922 /* A structure or union. Extract the left justified value,
3923 regardless of the byte order. I.e. DO NOT USE
3927 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3928 offset
< TYPE_LENGTH (type
);
3929 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3931 int xfer
= register_size (gdbarch
, regnum
);
3932 if (offset
+ xfer
> TYPE_LENGTH (type
))
3933 xfer
= TYPE_LENGTH (type
) - offset
;
3935 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3936 offset
, xfer
, regnum
);
3937 mips_xfer_register (gdbarch
, regcache
,
3938 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3939 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3941 return RETURN_VALUE_REGISTER_CONVENTION
;
3946 /* A scalar extract each part but least-significant-byte
3947 justified. o32 thinks registers are 4 byte, regardless of
3951 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3952 offset
< TYPE_LENGTH (type
);
3953 offset
+= MIPS32_REGSIZE
, regnum
++)
3955 int xfer
= MIPS32_REGSIZE
;
3956 if (offset
+ xfer
> TYPE_LENGTH (type
))
3957 xfer
= TYPE_LENGTH (type
) - offset
;
3959 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3960 offset
, xfer
, regnum
);
3961 mips_xfer_register (gdbarch
, regcache
,
3962 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3963 gdbarch_byte_order (gdbarch
),
3964 readbuf
, writebuf
, offset
);
3966 return RETURN_VALUE_REGISTER_CONVENTION
;
3970 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3974 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3975 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3977 struct value
**args
, CORE_ADDR sp
,
3978 int struct_return
, CORE_ADDR struct_addr
)
3984 int stack_offset
= 0;
3985 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3986 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3988 /* For shared libraries, "t9" needs to point at the function
3990 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3992 /* Set the return address register to point to the entry point of
3993 the program, where a breakpoint lies in wait. */
3994 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3996 /* First ensure that the stack and structure return address (if any)
3997 are properly aligned. The stack has to be at least 64-bit
3998 aligned even on 32-bit machines, because doubles must be 64-bit
3999 aligned. For n32 and n64, stack frames need to be 128-bit
4000 aligned, so we round to this widest known alignment. */
4002 sp
= align_down (sp
, 16);
4003 struct_addr
= align_down (struct_addr
, 16);
4005 /* Now make space on the stack for the args. */
4006 for (argnum
= 0; argnum
< nargs
; argnum
++)
4008 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4009 int arglen
= TYPE_LENGTH (arg_type
);
4011 /* Allocate space on the stack. */
4012 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4014 sp
-= align_up (len
, 16);
4017 fprintf_unfiltered (gdb_stdlog
,
4018 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4019 paddr_nz (sp
), (long) align_up (len
, 16));
4021 /* Initialize the integer and float register pointers. */
4022 argreg
= MIPS_A0_REGNUM
;
4023 float_argreg
= mips_fpa0_regnum (gdbarch
);
4025 /* The struct_return pointer occupies the first parameter-passing reg. */
4029 fprintf_unfiltered (gdb_stdlog
,
4030 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4031 argreg
, paddr_nz (struct_addr
));
4032 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4033 stack_offset
+= MIPS64_REGSIZE
;
4036 /* Now load as many as possible of the first arguments into
4037 registers, and push the rest onto the stack. Loop thru args
4038 from first to last. */
4039 for (argnum
= 0; argnum
< nargs
; argnum
++)
4041 const gdb_byte
*val
;
4042 struct value
*arg
= args
[argnum
];
4043 struct type
*arg_type
= check_typedef (value_type (arg
));
4044 int len
= TYPE_LENGTH (arg_type
);
4045 enum type_code typecode
= TYPE_CODE (arg_type
);
4048 fprintf_unfiltered (gdb_stdlog
,
4049 "mips_o64_push_dummy_call: %d len=%d type=%d",
4050 argnum
+ 1, len
, (int) typecode
);
4052 val
= value_contents (arg
);
4054 /* Floating point arguments passed in registers have to be
4055 treated specially. On 32-bit architectures, doubles
4056 are passed in register pairs; the even register gets
4057 the low word, and the odd register gets the high word.
4058 On O32/O64, the first two floating point arguments are
4059 also copied to general registers, because MIPS16 functions
4060 don't use float registers for arguments. This duplication of
4061 arguments in general registers can't hurt non-MIPS16 functions
4062 because those registers are normally skipped. */
4064 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4065 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4067 LONGEST regval
= extract_unsigned_integer (val
, len
);
4069 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4070 float_argreg
, phex (regval
, len
));
4071 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4073 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4074 argreg
, phex (regval
, len
));
4075 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4077 /* Reserve space for the FP register. */
4078 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4082 /* Copy the argument to general registers or the stack in
4083 register-sized pieces. Large arguments are split between
4084 registers and stack. */
4085 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4086 are treated specially: Irix cc passes them in registers
4087 where gcc sometimes puts them on the stack. For maximum
4088 compatibility, we will put them in both places. */
4089 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4090 && len
% MIPS64_REGSIZE
!= 0);
4093 /* Remember if the argument was written to the stack. */
4094 int stack_used_p
= 0;
4095 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4098 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4101 /* Write this portion of the argument to the stack. */
4102 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4103 || odd_sized_struct
)
4105 /* Should shorter than int integer values be
4106 promoted to int before being stored? */
4107 int longword_offset
= 0;
4110 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4112 if ((typecode
== TYPE_CODE_INT
4113 || typecode
== TYPE_CODE_PTR
4114 || typecode
== TYPE_CODE_FLT
)
4116 longword_offset
= MIPS64_REGSIZE
- len
;
4121 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4122 paddr_nz (stack_offset
));
4123 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4124 paddr_nz (longword_offset
));
4127 addr
= sp
+ stack_offset
+ longword_offset
;
4132 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4134 for (i
= 0; i
< partial_len
; i
++)
4136 fprintf_unfiltered (gdb_stdlog
, "%02x",
4140 write_memory (addr
, val
, partial_len
);
4143 /* Note!!! This is NOT an else clause. Odd sized
4144 structs may go thru BOTH paths. */
4145 /* Write this portion of the argument to a general
4146 purpose register. */
4147 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4149 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4150 /* Value may need to be sign extended, because
4151 mips_isa_regsize() != mips_abi_regsize(). */
4153 /* A non-floating-point argument being passed in a
4154 general register. If a struct or union, and if
4155 the remaining length is smaller than the register
4156 size, we have to adjust the register value on
4159 It does not seem to be necessary to do the
4160 same for integral types. */
4162 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4163 && partial_len
< MIPS64_REGSIZE
4164 && (typecode
== TYPE_CODE_STRUCT
4165 || typecode
== TYPE_CODE_UNION
))
4166 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4170 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4172 phex (regval
, MIPS64_REGSIZE
));
4173 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4176 /* Prevent subsequent floating point arguments from
4177 being passed in floating point registers. */
4178 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4184 /* Compute the the offset into the stack at which we
4185 will copy the next parameter.
4187 In older ABIs, the caller reserved space for
4188 registers that contained arguments. This was loosely
4189 refered to as their "home". Consequently, space is
4190 always allocated. */
4192 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4196 fprintf_unfiltered (gdb_stdlog
, "\n");
4199 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4201 /* Return adjusted stack pointer. */
4205 static enum return_value_convention
4206 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4207 struct type
*type
, struct regcache
*regcache
,
4208 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4210 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4212 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4213 || TYPE_CODE (type
) == TYPE_CODE_UNION
4214 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4215 return RETURN_VALUE_STRUCT_CONVENTION
;
4216 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4218 /* A floating-point value. It fits in the least significant
4221 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4222 mips_xfer_register (gdbarch
, regcache
,
4223 gdbarch_num_regs (gdbarch
)
4224 + mips_regnum (gdbarch
)->fp0
,
4226 gdbarch_byte_order (gdbarch
),
4227 readbuf
, writebuf
, 0);
4228 return RETURN_VALUE_REGISTER_CONVENTION
;
4232 /* A scalar extract each part but least-significant-byte
4236 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4237 offset
< TYPE_LENGTH (type
);
4238 offset
+= MIPS64_REGSIZE
, regnum
++)
4240 int xfer
= MIPS64_REGSIZE
;
4241 if (offset
+ xfer
> TYPE_LENGTH (type
))
4242 xfer
= TYPE_LENGTH (type
) - offset
;
4244 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4245 offset
, xfer
, regnum
);
4246 mips_xfer_register (gdbarch
, regcache
,
4247 gdbarch_num_regs (gdbarch
) + regnum
,
4248 xfer
, gdbarch_byte_order (gdbarch
),
4249 readbuf
, writebuf
, offset
);
4251 return RETURN_VALUE_REGISTER_CONVENTION
;
4255 /* Floating point register management.
4257 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4258 64bit operations, these early MIPS cpus treat fp register pairs
4259 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4260 registers and offer a compatibility mode that emulates the MIPS2 fp
4261 model. When operating in MIPS2 fp compat mode, later cpu's split
4262 double precision floats into two 32-bit chunks and store them in
4263 consecutive fp regs. To display 64-bit floats stored in this
4264 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4265 Throw in user-configurable endianness and you have a real mess.
4267 The way this works is:
4268 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4269 double-precision value will be split across two logical registers.
4270 The lower-numbered logical register will hold the low-order bits,
4271 regardless of the processor's endianness.
4272 - If we are on a 64-bit processor, and we are looking for a
4273 single-precision value, it will be in the low ordered bits
4274 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4275 save slot in memory.
4276 - If we are in 64-bit mode, everything is straightforward.
4278 Note that this code only deals with "live" registers at the top of the
4279 stack. We will attempt to deal with saved registers later, when
4280 the raw/cooked register interface is in place. (We need a general
4281 interface that can deal with dynamic saved register sizes -- fp
4282 regs could be 32 bits wide in one frame and 64 on the frame above
4285 static struct type
*
4286 mips_float_register_type (void)
4288 return builtin_type_ieee_single
;
4291 static struct type
*
4292 mips_double_register_type (void)
4294 return builtin_type_ieee_double
;
4297 /* Copy a 32-bit single-precision value from the current frame
4298 into rare_buffer. */
4301 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4302 gdb_byte
*rare_buffer
)
4304 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4305 int raw_size
= register_size (gdbarch
, regno
);
4306 gdb_byte
*raw_buffer
= alloca (raw_size
);
4308 if (!frame_register_read (frame
, regno
, raw_buffer
))
4309 error (_("can't read register %d (%s)"),
4310 regno
, gdbarch_register_name (gdbarch
, regno
));
4313 /* We have a 64-bit value for this register. Find the low-order
4317 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4322 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4326 memcpy (rare_buffer
, raw_buffer
, 4);
4330 /* Copy a 64-bit double-precision value from the current frame into
4331 rare_buffer. This may include getting half of it from the next
4335 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4336 gdb_byte
*rare_buffer
)
4338 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4339 int raw_size
= register_size (gdbarch
, regno
);
4341 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4343 /* We have a 64-bit value for this register, and we should use
4345 if (!frame_register_read (frame
, regno
, rare_buffer
))
4346 error (_("can't read register %d (%s)"),
4347 regno
, gdbarch_register_name (gdbarch
, regno
));
4351 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4353 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4354 internal_error (__FILE__
, __LINE__
,
4355 _("mips_read_fp_register_double: bad access to "
4356 "odd-numbered FP register"));
4358 /* mips_read_fp_register_single will find the correct 32 bits from
4360 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4362 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4363 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4367 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4368 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4374 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4376 { /* do values for FP (float) regs */
4377 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4378 gdb_byte
*raw_buffer
;
4379 double doub
, flt1
; /* doubles extracted from raw hex data */
4382 raw_buffer
= alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
));
4384 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4385 fprintf_filtered (file
, "%*s",
4386 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4389 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4391 struct value_print_options opts
;
4393 /* 4-byte registers: Print hex and floating. Also print even
4394 numbered registers as doubles. */
4395 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4396 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4398 get_formatted_print_options (&opts
, 'x');
4399 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, &opts
, 'w',
4402 fprintf_filtered (file
, " flt: ");
4404 fprintf_filtered (file
, " <invalid float> ");
4406 fprintf_filtered (file
, "%-17.9g", flt1
);
4408 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4410 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4411 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4414 fprintf_filtered (file
, " dbl: ");
4416 fprintf_filtered (file
, "<invalid double>");
4418 fprintf_filtered (file
, "%-24.17g", doub
);
4423 struct value_print_options opts
;
4425 /* Eight byte registers: print each one as hex, float and double. */
4426 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4427 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4429 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4430 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4432 get_formatted_print_options (&opts
, 'x');
4433 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, &opts
, 'g',
4436 fprintf_filtered (file
, " flt: ");
4438 fprintf_filtered (file
, "<invalid float>");
4440 fprintf_filtered (file
, "%-17.9g", flt1
);
4442 fprintf_filtered (file
, " dbl: ");
4444 fprintf_filtered (file
, "<invalid double>");
4446 fprintf_filtered (file
, "%-24.17g", doub
);
4451 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4454 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4455 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4457 struct value_print_options opts
;
4459 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4461 mips_print_fp_register (file
, frame
, regnum
);
4465 /* Get the data in raw format. */
4466 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4468 fprintf_filtered (file
, "%s: [Invalid]",
4469 gdbarch_register_name (gdbarch
, regnum
));
4473 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4475 /* The problem with printing numeric register names (r26, etc.) is that
4476 the user can't use them on input. Probably the best solution is to
4477 fix it so that either the numeric or the funky (a2, etc.) names
4478 are accepted on input. */
4479 if (regnum
< MIPS_NUMREGS
)
4480 fprintf_filtered (file
, "(r%d): ", regnum
);
4482 fprintf_filtered (file
, ": ");
4484 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4486 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4490 get_formatted_print_options (&opts
, 'x');
4491 print_scalar_formatted (raw_buffer
+ offset
,
4492 register_type (gdbarch
, regnum
), &opts
, 0,
4496 /* Replacement for generic do_registers_info.
4497 Print regs in pretty columns. */
4500 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4503 fprintf_filtered (file
, " ");
4504 mips_print_fp_register (file
, frame
, regnum
);
4505 fprintf_filtered (file
, "\n");
4510 /* Print a row's worth of GP (int) registers, with name labels above */
4513 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4516 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4517 /* do values for GP (int) regs */
4518 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4519 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4523 /* For GP registers, we print a separate row of names above the vals */
4524 for (col
= 0, regnum
= start_regnum
;
4525 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4526 + gdbarch_num_pseudo_regs (gdbarch
);
4529 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4530 continue; /* unused register */
4531 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4533 break; /* end the row: reached FP register */
4534 /* Large registers are handled separately. */
4535 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4538 break; /* End the row before this register. */
4540 /* Print this register on a row by itself. */
4541 mips_print_register (file
, frame
, regnum
);
4542 fprintf_filtered (file
, "\n");
4546 fprintf_filtered (file
, " ");
4547 fprintf_filtered (file
,
4548 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4549 gdbarch_register_name (gdbarch
, regnum
));
4556 /* print the R0 to R31 names */
4557 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4558 fprintf_filtered (file
, "\n R%-4d",
4559 start_regnum
% gdbarch_num_regs (gdbarch
));
4561 fprintf_filtered (file
, "\n ");
4563 /* now print the values in hex, 4 or 8 to the row */
4564 for (col
= 0, regnum
= start_regnum
;
4565 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4566 + gdbarch_num_pseudo_regs (gdbarch
);
4569 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4570 continue; /* unused register */
4571 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4573 break; /* end row: reached FP register */
4574 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4575 break; /* End row: large register. */
4577 /* OK: get the data in raw format. */
4578 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4579 error (_("can't read register %d (%s)"),
4580 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4581 /* pad small registers */
4583 byte
< (mips_abi_regsize (gdbarch
)
4584 - register_size (gdbarch
, regnum
)); byte
++)
4585 printf_filtered (" ");
4586 /* Now print the register value in hex, endian order. */
4587 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4589 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4590 byte
< register_size (gdbarch
, regnum
); byte
++)
4591 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4593 for (byte
= register_size (gdbarch
, regnum
) - 1;
4595 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4596 fprintf_filtered (file
, " ");
4599 if (col
> 0) /* ie. if we actually printed anything... */
4600 fprintf_filtered (file
, "\n");
4605 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4608 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4609 struct frame_info
*frame
, int regnum
, int all
)
4611 if (regnum
!= -1) /* do one specified register */
4613 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4614 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4615 error (_("Not a valid register for the current processor type"));
4617 mips_print_register (file
, frame
, regnum
);
4618 fprintf_filtered (file
, "\n");
4621 /* do all (or most) registers */
4623 regnum
= gdbarch_num_regs (gdbarch
);
4624 while (regnum
< gdbarch_num_regs (gdbarch
)
4625 + gdbarch_num_pseudo_regs (gdbarch
))
4627 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4630 if (all
) /* true for "INFO ALL-REGISTERS" command */
4631 regnum
= print_fp_register_row (file
, frame
, regnum
);
4633 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4636 regnum
= print_gp_register_row (file
, frame
, regnum
);
4641 /* Is this a branch with a delay slot? */
4644 is_delayed (unsigned long insn
)
4647 for (i
= 0; i
< NUMOPCODES
; ++i
)
4648 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4649 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4651 return (i
< NUMOPCODES
4652 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4653 | INSN_COND_BRANCH_DELAY
4654 | INSN_COND_BRANCH_LIKELY
)));
4658 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4659 struct frame_info
*frame
)
4661 CORE_ADDR pc
= get_frame_pc (frame
);
4662 gdb_byte buf
[MIPS_INSN32_SIZE
];
4664 /* There is no branch delay slot on MIPS16. */
4665 if (mips_pc_is_mips16 (pc
))
4668 if (!breakpoint_here_p (pc
+ 4))
4671 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4672 /* If error reading memory, guess that it is not a delayed
4675 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4678 /* To skip prologues, I use this predicate. Returns either PC itself
4679 if the code at PC does not look like a function prologue; otherwise
4680 returns an address that (if we're lucky) follows the prologue. If
4681 LENIENT, then we must skip everything which is involved in setting
4682 up the frame (it's OK to skip more, just so long as we don't skip
4683 anything which might clobber the registers which are being saved.
4684 We must skip more in the case where part of the prologue is in the
4685 delay slot of a non-prologue instruction). */
4688 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4691 CORE_ADDR func_addr
;
4693 /* See if we can determine the end of the prologue via the symbol table.
4694 If so, then return either PC, or the PC after the prologue, whichever
4696 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4698 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4699 if (post_prologue_pc
!= 0)
4700 return max (pc
, post_prologue_pc
);
4703 /* Can't determine prologue from the symbol table, need to examine
4706 /* Find an upper limit on the function prologue using the debug
4707 information. If the debug information could not be used to provide
4708 that bound, then use an arbitrary large number as the upper bound. */
4709 limit_pc
= skip_prologue_using_sal (pc
);
4711 limit_pc
= pc
+ 100; /* Magic. */
4713 if (mips_pc_is_mips16 (pc
))
4714 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4716 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4719 /* Check whether the PC is in a function epilogue (32-bit version).
4720 This is a helper function for mips_in_function_epilogue_p. */
4722 mips32_in_function_epilogue_p (CORE_ADDR pc
)
4724 CORE_ADDR func_addr
= 0, func_end
= 0;
4726 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4728 /* The MIPS epilogue is max. 12 bytes long. */
4729 CORE_ADDR addr
= func_end
- 12;
4731 if (addr
< func_addr
+ 4)
4732 addr
= func_addr
+ 4;
4736 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4738 unsigned long high_word
;
4741 inst
= mips_fetch_instruction (pc
);
4742 high_word
= (inst
>> 16) & 0xffff;
4744 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4745 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4746 && inst
!= 0x03e00008 /* jr $ra */
4747 && inst
!= 0x00000000) /* nop */
4757 /* Check whether the PC is in a function epilogue (16-bit version).
4758 This is a helper function for mips_in_function_epilogue_p. */
4760 mips16_in_function_epilogue_p (CORE_ADDR pc
)
4762 CORE_ADDR func_addr
= 0, func_end
= 0;
4764 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4766 /* The MIPS epilogue is max. 12 bytes long. */
4767 CORE_ADDR addr
= func_end
- 12;
4769 if (addr
< func_addr
+ 4)
4770 addr
= func_addr
+ 4;
4774 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4776 unsigned short inst
;
4778 inst
= mips_fetch_instruction (pc
);
4780 if ((inst
& 0xf800) == 0xf000) /* extend */
4783 if (inst
!= 0x6300 /* addiu $sp,offset */
4784 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
4785 && inst
!= 0xe820 /* jr $ra */
4786 && inst
!= 0xe8a0 /* jrc $ra */
4787 && inst
!= 0x6500) /* nop */
4797 /* The epilogue is defined here as the area at the end of a function,
4798 after an instruction which destroys the function's stack frame. */
4800 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4802 if (mips_pc_is_mips16 (pc
))
4803 return mips16_in_function_epilogue_p (pc
);
4805 return mips32_in_function_epilogue_p (pc
);
4808 /* Root of all "set mips "/"show mips " commands. This will eventually be
4809 used for all MIPS-specific commands. */
4812 show_mips_command (char *args
, int from_tty
)
4814 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4818 set_mips_command (char *args
, int from_tty
)
4821 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4822 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4825 /* Commands to show/set the MIPS FPU type. */
4828 show_mipsfpu_command (char *args
, int from_tty
)
4832 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
4835 ("The MIPS floating-point coprocessor is unknown "
4836 "because the current architecture is not MIPS.\n");
4840 switch (MIPS_FPU_TYPE (target_gdbarch
))
4842 case MIPS_FPU_SINGLE
:
4843 fpu
= "single-precision";
4845 case MIPS_FPU_DOUBLE
:
4846 fpu
= "double-precision";
4849 fpu
= "absent (none)";
4852 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4854 if (mips_fpu_type_auto
)
4856 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4860 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4865 set_mipsfpu_command (char *args
, int from_tty
)
4868 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4869 show_mipsfpu_command (args
, from_tty
);
4873 set_mipsfpu_single_command (char *args
, int from_tty
)
4875 struct gdbarch_info info
;
4876 gdbarch_info_init (&info
);
4877 mips_fpu_type
= MIPS_FPU_SINGLE
;
4878 mips_fpu_type_auto
= 0;
4879 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4880 instead of relying on globals. Doing that would let generic code
4881 handle the search for this specific architecture. */
4882 if (!gdbarch_update_p (info
))
4883 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4887 set_mipsfpu_double_command (char *args
, int from_tty
)
4889 struct gdbarch_info info
;
4890 gdbarch_info_init (&info
);
4891 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4892 mips_fpu_type_auto
= 0;
4893 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4894 instead of relying on globals. Doing that would let generic code
4895 handle the search for this specific architecture. */
4896 if (!gdbarch_update_p (info
))
4897 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4901 set_mipsfpu_none_command (char *args
, int from_tty
)
4903 struct gdbarch_info info
;
4904 gdbarch_info_init (&info
);
4905 mips_fpu_type
= MIPS_FPU_NONE
;
4906 mips_fpu_type_auto
= 0;
4907 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4908 instead of relying on globals. Doing that would let generic code
4909 handle the search for this specific architecture. */
4910 if (!gdbarch_update_p (info
))
4911 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4915 set_mipsfpu_auto_command (char *args
, int from_tty
)
4917 mips_fpu_type_auto
= 1;
4920 /* Attempt to identify the particular processor model by reading the
4921 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4922 the relevant processor still exists (it dates back to '94) and
4923 secondly this is not the way to do this. The processor type should
4924 be set by forcing an architecture change. */
4927 deprecated_mips_set_processor_regs_hack (void)
4929 struct regcache
*regcache
= get_current_regcache ();
4930 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
4931 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4934 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
4935 if ((prid
& ~0xf) == 0x700)
4936 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4939 /* Just like reinit_frame_cache, but with the right arguments to be
4940 callable as an sfunc. */
4943 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4944 struct cmd_list_element
*c
)
4946 reinit_frame_cache ();
4950 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4952 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4953 disassembler needs to be able to locally determine the ISA, and
4954 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4956 if (mips_pc_is_mips16 (memaddr
))
4957 info
->mach
= bfd_mach_mips16
;
4959 /* Round down the instruction address to the appropriate boundary. */
4960 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4962 /* Set the disassembler options. */
4963 if (!info
->disassembler_options
)
4964 /* This string is not recognized explicitly by the disassembler,
4965 but it tells the disassembler to not try to guess the ABI from
4966 the bfd elf headers, such that, if the user overrides the ABI
4967 of a program linked as NewABI, the disassembly will follow the
4968 register naming conventions specified by the user. */
4969 info
->disassembler_options
= "gpr-names=32";
4971 /* Call the appropriate disassembler based on the target endian-ness. */
4972 if (info
->endian
== BFD_ENDIAN_BIG
)
4973 return print_insn_big_mips (memaddr
, info
);
4975 return print_insn_little_mips (memaddr
, info
);
4979 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
4981 /* Set up the disassembler info, so that we get the right
4982 register names from libopcodes. */
4983 info
->disassembler_options
= "gpr-names=n32";
4984 info
->flavour
= bfd_target_elf_flavour
;
4986 return gdb_print_insn_mips (memaddr
, info
);
4990 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
4992 /* Set up the disassembler info, so that we get the right
4993 register names from libopcodes. */
4994 info
->disassembler_options
= "gpr-names=64";
4995 info
->flavour
= bfd_target_elf_flavour
;
4997 return gdb_print_insn_mips (memaddr
, info
);
5000 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
5001 counter value to determine whether a 16- or 32-bit breakpoint should be used.
5002 It returns a pointer to a string of bytes that encode a breakpoint
5003 instruction, stores the length of the string to *lenptr, and adjusts pc (if
5004 necessary) to point to the actual memory location where the breakpoint
5005 should be inserted. */
5007 static const gdb_byte
*
5008 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
5010 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5012 if (mips_pc_is_mips16 (*pcptr
))
5014 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5015 *pcptr
= unmake_mips16_addr (*pcptr
);
5016 *lenptr
= sizeof (mips16_big_breakpoint
);
5017 return mips16_big_breakpoint
;
5021 /* The IDT board uses an unusual breakpoint value, and
5022 sometimes gets confused when it sees the usual MIPS
5023 breakpoint instruction. */
5024 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5025 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5026 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5028 *lenptr
= sizeof (big_breakpoint
);
5030 if (strcmp (target_shortname
, "mips") == 0)
5031 return idt_big_breakpoint
;
5032 else if (strcmp (target_shortname
, "ddb") == 0
5033 || strcmp (target_shortname
, "pmon") == 0
5034 || strcmp (target_shortname
, "lsi") == 0)
5035 return pmon_big_breakpoint
;
5037 return big_breakpoint
;
5042 if (mips_pc_is_mips16 (*pcptr
))
5044 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5045 *pcptr
= unmake_mips16_addr (*pcptr
);
5046 *lenptr
= sizeof (mips16_little_breakpoint
);
5047 return mips16_little_breakpoint
;
5051 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5052 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5053 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5055 *lenptr
= sizeof (little_breakpoint
);
5057 if (strcmp (target_shortname
, "mips") == 0)
5058 return idt_little_breakpoint
;
5059 else if (strcmp (target_shortname
, "ddb") == 0
5060 || strcmp (target_shortname
, "pmon") == 0
5061 || strcmp (target_shortname
, "lsi") == 0)
5062 return pmon_little_breakpoint
;
5064 return little_breakpoint
;
5069 /* If PC is in a mips16 call or return stub, return the address of the target
5070 PC, which is either the callee or the caller. There are several
5071 cases which must be handled:
5073 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5074 target PC is in $31 ($ra).
5075 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5076 and the target PC is in $2.
5077 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5078 before the jal instruction, this is effectively a call stub
5079 and the the target PC is in $2. Otherwise this is effectively
5080 a return stub and the target PC is in $18.
5082 See the source code for the stubs in gcc/config/mips/mips16.S for
5086 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5089 CORE_ADDR start_addr
;
5091 /* Find the starting address and name of the function containing the PC. */
5092 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5095 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5096 target PC is in $31 ($ra). */
5097 if (strcmp (name
, "__mips16_ret_sf") == 0
5098 || strcmp (name
, "__mips16_ret_df") == 0)
5099 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5101 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5103 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5104 and the target PC is in $2. */
5105 if (name
[19] >= '0' && name
[19] <= '9')
5106 return get_frame_register_signed (frame
, 2);
5108 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5109 before the jal instruction, this is effectively a call stub
5110 and the the target PC is in $2. Otherwise this is effectively
5111 a return stub and the target PC is in $18. */
5112 else if (name
[19] == 's' || name
[19] == 'd')
5114 if (pc
== start_addr
)
5116 /* Check if the target of the stub is a compiler-generated
5117 stub. Such a stub for a function bar might have a name
5118 like __fn_stub_bar, and might look like this:
5123 la $1,bar (becomes a lui/addiu pair)
5125 So scan down to the lui/addi and extract the target
5126 address from those two instructions. */
5128 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5132 /* See if the name of the target function is __fn_stub_*. */
5133 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5136 if (strncmp (name
, "__fn_stub_", 10) != 0
5137 && strcmp (name
, "etext") != 0
5138 && strcmp (name
, "_etext") != 0)
5141 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5142 The limit on the search is arbitrarily set to 20
5143 instructions. FIXME. */
5144 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5146 inst
= mips_fetch_instruction (target_pc
);
5147 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5148 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5149 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5150 return pc
| (inst
& 0xffff); /* low word */
5153 /* Couldn't find the lui/addui pair, so return stub address. */
5157 /* This is the 'return' part of a call stub. The return
5158 address is in $r18. */
5159 return get_frame_register_signed (frame
, 18);
5162 return 0; /* not a stub */
5165 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5166 PC of the stub target. The stub just loads $t9 and jumps to it,
5167 so that $t9 has the correct value at function entry. */
5170 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5172 struct minimal_symbol
*msym
;
5174 gdb_byte stub_code
[16];
5175 int32_t stub_words
[4];
5177 /* The stub for foo is named ".pic.foo", and is either two
5178 instructions inserted before foo or a three instruction sequence
5179 which jumps to foo. */
5180 msym
= lookup_minimal_symbol_by_pc (pc
);
5182 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5183 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5184 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5187 /* A two-instruction header. */
5188 if (MSYMBOL_SIZE (msym
) == 8)
5191 /* A three-instruction (plus delay slot) trampoline. */
5192 if (MSYMBOL_SIZE (msym
) == 16)
5194 if (target_read_memory (pc
, stub_code
, 16) != 0)
5196 for (i
= 0; i
< 4; i
++)
5197 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4, 4);
5199 /* A stub contains these instructions:
5202 addiu t9, t9, %lo(target)
5205 This works even for N64, since stubs are only generated with
5207 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5208 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5209 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5210 && stub_words
[3] == 0x00000000)
5211 return (((stub_words
[0] & 0x0000ffff) << 16)
5212 + (stub_words
[2] & 0x0000ffff));
5215 /* Not a recognized stub. */
5220 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5222 CORE_ADDR target_pc
;
5224 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5228 target_pc
= find_solib_trampoline_target (frame
, pc
);
5232 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5239 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5240 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5243 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5246 if (num
>= 0 && num
< 32)
5248 else if (num
>= 38 && num
< 70)
5249 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5251 regnum
= mips_regnum (gdbarch
)->hi
;
5253 regnum
= mips_regnum (gdbarch
)->lo
;
5255 /* This will hopefully (eventually) provoke a warning. Should
5256 we be calling complaint() here? */
5257 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5258 return gdbarch_num_regs (gdbarch
) + regnum
;
5262 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5263 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5266 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5269 if (num
>= 0 && num
< 32)
5271 else if (num
>= 32 && num
< 64)
5272 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5274 regnum
= mips_regnum (gdbarch
)->hi
;
5276 regnum
= mips_regnum (gdbarch
)->lo
;
5278 /* This will hopefully (eventually) provoke a warning. Should we
5279 be calling complaint() here? */
5280 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5281 return gdbarch_num_regs (gdbarch
) + regnum
;
5285 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5287 /* Only makes sense to supply raw registers. */
5288 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5289 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5290 decide if it is valid. Should instead define a standard sim/gdb
5291 register numbering scheme. */
5292 if (gdbarch_register_name (gdbarch
,
5293 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5294 && gdbarch_register_name (gdbarch
,
5295 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
5298 return LEGACY_SIM_REGNO_IGNORE
;
5302 /* Convert an integer into an address. Extracting the value signed
5303 guarantees a correctly sign extended address. */
5306 mips_integer_to_address (struct gdbarch
*gdbarch
,
5307 struct type
*type
, const gdb_byte
*buf
)
5309 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
5312 /* Dummy virtual frame pointer method. This is no more or less accurate
5313 than most other architectures; we just need to be explicit about it,
5314 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5315 an assertion failure. */
5318 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5319 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5321 *reg
= MIPS_SP_REGNUM
;
5326 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5328 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5329 const char *name
= bfd_get_section_name (abfd
, sect
);
5331 if (*abip
!= MIPS_ABI_UNKNOWN
)
5334 if (strncmp (name
, ".mdebug.", 8) != 0)
5337 if (strcmp (name
, ".mdebug.abi32") == 0)
5338 *abip
= MIPS_ABI_O32
;
5339 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5340 *abip
= MIPS_ABI_N32
;
5341 else if (strcmp (name
, ".mdebug.abi64") == 0)
5342 *abip
= MIPS_ABI_N64
;
5343 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5344 *abip
= MIPS_ABI_O64
;
5345 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5346 *abip
= MIPS_ABI_EABI32
;
5347 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5348 *abip
= MIPS_ABI_EABI64
;
5350 warning (_("unsupported ABI %s."), name
+ 8);
5354 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5356 int *lbp
= (int *) obj
;
5357 const char *name
= bfd_get_section_name (abfd
, sect
);
5359 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5361 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5363 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5364 warning (_("unrecognized .gcc_compiled_longXX"));
5367 static enum mips_abi
5368 global_mips_abi (void)
5372 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5373 if (mips_abi_strings
[i
] == mips_abi_string
)
5374 return (enum mips_abi
) i
;
5376 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5380 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5382 /* If the size matches the set of 32-bit or 64-bit integer registers,
5383 assume that's what we've got. */
5384 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5385 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5387 /* If the size matches the full set of registers GDB traditionally
5388 knows about, including floating point, for either 32-bit or
5389 64-bit, assume that's what we've got. */
5390 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5391 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5393 /* Otherwise we don't have a useful guess. */
5396 static struct value
*
5397 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5399 const int *reg_p
= baton
;
5400 return value_of_register (*reg_p
, frame
);
5403 static struct gdbarch
*
5404 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5406 struct gdbarch
*gdbarch
;
5407 struct gdbarch_tdep
*tdep
;
5409 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5411 enum mips_fpu_type fpu_type
;
5412 struct tdesc_arch_data
*tdesc_data
= NULL
;
5413 int elf_fpu_type
= 0;
5415 /* Check any target description for validity. */
5416 if (tdesc_has_registers (info
.target_desc
))
5418 static const char *const mips_gprs
[] = {
5419 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5420 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5421 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5422 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5424 static const char *const mips_fprs
[] = {
5425 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5426 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5427 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5428 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5431 const struct tdesc_feature
*feature
;
5434 feature
= tdesc_find_feature (info
.target_desc
,
5435 "org.gnu.gdb.mips.cpu");
5436 if (feature
== NULL
)
5439 tdesc_data
= tdesc_data_alloc ();
5442 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5443 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5447 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5448 MIPS_EMBED_LO_REGNUM
, "lo");
5449 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5450 MIPS_EMBED_HI_REGNUM
, "hi");
5451 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5452 MIPS_EMBED_PC_REGNUM
, "pc");
5456 tdesc_data_cleanup (tdesc_data
);
5460 feature
= tdesc_find_feature (info
.target_desc
,
5461 "org.gnu.gdb.mips.cp0");
5462 if (feature
== NULL
)
5464 tdesc_data_cleanup (tdesc_data
);
5469 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5470 MIPS_EMBED_BADVADDR_REGNUM
,
5472 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5473 MIPS_PS_REGNUM
, "status");
5474 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5475 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5479 tdesc_data_cleanup (tdesc_data
);
5483 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5484 backend is not prepared for that, though. */
5485 feature
= tdesc_find_feature (info
.target_desc
,
5486 "org.gnu.gdb.mips.fpu");
5487 if (feature
== NULL
)
5489 tdesc_data_cleanup (tdesc_data
);
5494 for (i
= 0; i
< 32; i
++)
5495 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5496 i
+ MIPS_EMBED_FP0_REGNUM
,
5499 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5500 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5501 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5502 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5506 tdesc_data_cleanup (tdesc_data
);
5510 /* It would be nice to detect an attempt to use a 64-bit ABI
5511 when only 32-bit registers are provided. */
5514 /* First of all, extract the elf_flags, if available. */
5515 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5516 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5517 else if (arches
!= NULL
)
5518 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5522 fprintf_unfiltered (gdb_stdlog
,
5523 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5525 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5526 switch ((elf_flags
& EF_MIPS_ABI
))
5528 case E_MIPS_ABI_O32
:
5529 found_abi
= MIPS_ABI_O32
;
5531 case E_MIPS_ABI_O64
:
5532 found_abi
= MIPS_ABI_O64
;
5534 case E_MIPS_ABI_EABI32
:
5535 found_abi
= MIPS_ABI_EABI32
;
5537 case E_MIPS_ABI_EABI64
:
5538 found_abi
= MIPS_ABI_EABI64
;
5541 if ((elf_flags
& EF_MIPS_ABI2
))
5542 found_abi
= MIPS_ABI_N32
;
5544 found_abi
= MIPS_ABI_UNKNOWN
;
5548 /* GCC creates a pseudo-section whose name describes the ABI. */
5549 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5550 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5552 /* If we have no useful BFD information, use the ABI from the last
5553 MIPS architecture (if there is one). */
5554 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5555 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5557 /* Try the architecture for any hint of the correct ABI. */
5558 if (found_abi
== MIPS_ABI_UNKNOWN
5559 && info
.bfd_arch_info
!= NULL
5560 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5562 switch (info
.bfd_arch_info
->mach
)
5564 case bfd_mach_mips3900
:
5565 found_abi
= MIPS_ABI_EABI32
;
5567 case bfd_mach_mips4100
:
5568 case bfd_mach_mips5000
:
5569 found_abi
= MIPS_ABI_EABI64
;
5571 case bfd_mach_mips8000
:
5572 case bfd_mach_mips10000
:
5573 /* On Irix, ELF64 executables use the N64 ABI. The
5574 pseudo-sections which describe the ABI aren't present
5575 on IRIX. (Even for executables created by gcc.) */
5576 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5577 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5578 found_abi
= MIPS_ABI_N64
;
5580 found_abi
= MIPS_ABI_N32
;
5585 /* Default 64-bit objects to N64 instead of O32. */
5586 if (found_abi
== MIPS_ABI_UNKNOWN
5587 && info
.abfd
!= NULL
5588 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5589 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5590 found_abi
= MIPS_ABI_N64
;
5593 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5596 /* What has the user specified from the command line? */
5597 wanted_abi
= global_mips_abi ();
5599 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5602 /* Now that we have found what the ABI for this binary would be,
5603 check whether the user is overriding it. */
5604 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5605 mips_abi
= wanted_abi
;
5606 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5607 mips_abi
= found_abi
;
5609 mips_abi
= MIPS_ABI_O32
;
5611 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5614 /* Also used when doing an architecture lookup. */
5616 fprintf_unfiltered (gdb_stdlog
,
5617 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5618 mips64_transfers_32bit_regs_p
);
5620 /* Determine the MIPS FPU type. */
5623 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5624 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5625 Tag_GNU_MIPS_ABI_FP
);
5626 #endif /* HAVE_ELF */
5628 if (!mips_fpu_type_auto
)
5629 fpu_type
= mips_fpu_type
;
5630 else if (elf_fpu_type
!= 0)
5632 switch (elf_fpu_type
)
5635 fpu_type
= MIPS_FPU_DOUBLE
;
5638 fpu_type
= MIPS_FPU_SINGLE
;
5642 /* Soft float or unknown. */
5643 fpu_type
= MIPS_FPU_NONE
;
5647 else if (info
.bfd_arch_info
!= NULL
5648 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5649 switch (info
.bfd_arch_info
->mach
)
5651 case bfd_mach_mips3900
:
5652 case bfd_mach_mips4100
:
5653 case bfd_mach_mips4111
:
5654 case bfd_mach_mips4120
:
5655 fpu_type
= MIPS_FPU_NONE
;
5657 case bfd_mach_mips4650
:
5658 fpu_type
= MIPS_FPU_SINGLE
;
5661 fpu_type
= MIPS_FPU_DOUBLE
;
5664 else if (arches
!= NULL
)
5665 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5667 fpu_type
= MIPS_FPU_DOUBLE
;
5669 fprintf_unfiltered (gdb_stdlog
,
5670 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5672 /* Check for blatant incompatibilities. */
5674 /* If we have only 32-bit registers, then we can't debug a 64-bit
5676 if (info
.target_desc
5677 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5678 && mips_abi
!= MIPS_ABI_EABI32
5679 && mips_abi
!= MIPS_ABI_O32
)
5681 if (tdesc_data
!= NULL
)
5682 tdesc_data_cleanup (tdesc_data
);
5686 /* try to find a pre-existing architecture */
5687 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5689 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5691 /* MIPS needs to be pedantic about which ABI the object is
5693 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5695 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5697 /* Need to be pedantic about which register virtual size is
5699 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5700 != mips64_transfers_32bit_regs_p
)
5702 /* Be pedantic about which FPU is selected. */
5703 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5706 if (tdesc_data
!= NULL
)
5707 tdesc_data_cleanup (tdesc_data
);
5708 return arches
->gdbarch
;
5711 /* Need a new architecture. Fill in a target specific vector. */
5712 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5713 gdbarch
= gdbarch_alloc (&info
, tdep
);
5714 tdep
->elf_flags
= elf_flags
;
5715 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5716 tdep
->found_abi
= found_abi
;
5717 tdep
->mips_abi
= mips_abi
;
5718 tdep
->mips_fpu_type
= fpu_type
;
5719 tdep
->register_size_valid_p
= 0;
5720 tdep
->register_size
= 0;
5722 if (info
.target_desc
)
5724 /* Some useful properties can be inferred from the target. */
5725 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5727 tdep
->register_size_valid_p
= 1;
5728 tdep
->register_size
= 4;
5730 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5732 tdep
->register_size_valid_p
= 1;
5733 tdep
->register_size
= 8;
5737 /* Initially set everything according to the default ABI/ISA. */
5738 set_gdbarch_short_bit (gdbarch
, 16);
5739 set_gdbarch_int_bit (gdbarch
, 32);
5740 set_gdbarch_float_bit (gdbarch
, 32);
5741 set_gdbarch_double_bit (gdbarch
, 64);
5742 set_gdbarch_long_double_bit (gdbarch
, 64);
5743 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5744 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5745 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5747 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5748 mips_elf_make_msymbol_special
);
5750 /* Fill in the OS dependant register numbers and names. */
5752 const char **reg_names
;
5753 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5754 struct mips_regnum
);
5755 if (tdesc_has_registers (info
.target_desc
))
5757 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5758 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5759 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5760 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5761 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5762 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5763 regnum
->fp_control_status
= 70;
5764 regnum
->fp_implementation_revision
= 71;
5765 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5768 else if (info
.osabi
== GDB_OSABI_IRIX
)
5773 regnum
->badvaddr
= 66;
5776 regnum
->fp_control_status
= 69;
5777 regnum
->fp_implementation_revision
= 70;
5779 reg_names
= mips_irix_reg_names
;
5783 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5784 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5785 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5786 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5787 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5788 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5789 regnum
->fp_control_status
= 70;
5790 regnum
->fp_implementation_revision
= 71;
5792 if (info
.bfd_arch_info
!= NULL
5793 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5794 reg_names
= mips_tx39_reg_names
;
5796 reg_names
= mips_generic_reg_names
;
5798 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5799 replaced by gdbarch_read_pc? */
5800 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5801 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5802 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5803 set_gdbarch_num_regs (gdbarch
, num_regs
);
5804 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5805 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5806 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
5807 tdep
->mips_processor_reg_names
= reg_names
;
5808 tdep
->regnum
= regnum
;
5814 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5815 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5816 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5817 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5818 tdep
->default_mask_address_p
= 0;
5819 set_gdbarch_long_bit (gdbarch
, 32);
5820 set_gdbarch_ptr_bit (gdbarch
, 32);
5821 set_gdbarch_long_long_bit (gdbarch
, 64);
5824 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5825 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5826 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5827 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5828 tdep
->default_mask_address_p
= 0;
5829 set_gdbarch_long_bit (gdbarch
, 32);
5830 set_gdbarch_ptr_bit (gdbarch
, 32);
5831 set_gdbarch_long_long_bit (gdbarch
, 64);
5833 case MIPS_ABI_EABI32
:
5834 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5835 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5836 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5837 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5838 tdep
->default_mask_address_p
= 0;
5839 set_gdbarch_long_bit (gdbarch
, 32);
5840 set_gdbarch_ptr_bit (gdbarch
, 32);
5841 set_gdbarch_long_long_bit (gdbarch
, 64);
5843 case MIPS_ABI_EABI64
:
5844 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5845 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5846 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5847 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5848 tdep
->default_mask_address_p
= 0;
5849 set_gdbarch_long_bit (gdbarch
, 64);
5850 set_gdbarch_ptr_bit (gdbarch
, 64);
5851 set_gdbarch_long_long_bit (gdbarch
, 64);
5854 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5855 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5856 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5857 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5858 tdep
->default_mask_address_p
= 0;
5859 set_gdbarch_long_bit (gdbarch
, 32);
5860 set_gdbarch_ptr_bit (gdbarch
, 32);
5861 set_gdbarch_long_long_bit (gdbarch
, 64);
5862 set_gdbarch_long_double_bit (gdbarch
, 128);
5863 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5866 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5867 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5868 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5869 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5870 tdep
->default_mask_address_p
= 0;
5871 set_gdbarch_long_bit (gdbarch
, 64);
5872 set_gdbarch_ptr_bit (gdbarch
, 64);
5873 set_gdbarch_long_long_bit (gdbarch
, 64);
5874 set_gdbarch_long_double_bit (gdbarch
, 128);
5875 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5878 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5881 /* GCC creates a pseudo-section whose name specifies the size of
5882 longs, since -mlong32 or -mlong64 may be used independent of
5883 other options. How those options affect pointer sizes is ABI and
5884 architecture dependent, so use them to override the default sizes
5885 set by the ABI. This table shows the relationship between ABI,
5886 -mlongXX, and size of pointers:
5888 ABI -mlongXX ptr bits
5889 --- -------- --------
5903 Note that for o32 and eabi32, pointers are always 32 bits
5904 regardless of any -mlongXX option. For all others, pointers and
5905 longs are the same, as set by -mlongXX or set by defaults.
5908 if (info
.abfd
!= NULL
)
5912 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5915 set_gdbarch_long_bit (gdbarch
, long_bit
);
5919 case MIPS_ABI_EABI32
:
5924 case MIPS_ABI_EABI64
:
5925 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5928 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5933 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5934 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5937 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5938 flag in object files because to do so would make it impossible to
5939 link with libraries compiled without "-gp32". This is
5940 unnecessarily restrictive.
5942 We could solve this problem by adding "-gp32" multilibs to gcc,
5943 but to set this flag before gcc is built with such multilibs will
5944 break too many systems.''
5946 But even more unhelpfully, the default linker output target for
5947 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5948 for 64-bit programs - you need to change the ABI to change this,
5949 and not all gcc targets support that currently. Therefore using
5950 this flag to detect 32-bit mode would do the wrong thing given
5951 the current gcc - it would make GDB treat these 64-bit programs
5952 as 32-bit programs by default. */
5954 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5955 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5957 /* Add/remove bits from an address. The MIPS needs be careful to
5958 ensure that all 32 bit addresses are sign extended to 64 bits. */
5959 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5961 /* Unwind the frame. */
5962 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5963 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5964 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
5966 /* Map debug register numbers onto internal register numbers. */
5967 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5968 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5969 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5970 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5971 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5972 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5974 /* MIPS version of CALL_DUMMY */
5976 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5977 replaced by a command, and all targets will default to on stack
5978 (regardless of the stack's execute status). */
5979 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5980 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5982 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5983 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5984 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5986 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5987 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5989 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5991 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
5993 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5994 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5995 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5997 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5999 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6001 if (mips_abi
== MIPS_ABI_N32
)
6002 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6003 else if (mips_abi
== MIPS_ABI_N64
)
6004 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6006 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6008 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6009 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6010 need to all be folded into the target vector. Since they are
6011 being used as guards for target_stopped_by_watchpoint, why not have
6012 target_stopped_by_watchpoint return the type of watchpoint that the code
6014 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6016 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6018 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
6020 /* Virtual tables. */
6021 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6023 mips_register_g_packet_guesses (gdbarch
);
6025 /* Hook in OS ABI-specific overrides, if they have been registered. */
6026 info
.tdep_info
= (void *) tdesc_data
;
6027 gdbarch_init_osabi (info
, gdbarch
);
6029 /* Unwind the frame. */
6030 dwarf2_append_unwinders (gdbarch
);
6031 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6032 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6033 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6034 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6035 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6036 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6037 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6041 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6042 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6044 /* Override the normal target description methods to handle our
6045 dual real and pseudo registers. */
6046 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6047 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
6049 num_regs
= gdbarch_num_regs (gdbarch
);
6050 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6051 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6052 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6055 /* Add ABI-specific aliases for the registers. */
6056 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6057 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6058 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6059 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6061 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6062 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6063 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6065 /* Add some other standard aliases. */
6066 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6067 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6068 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6070 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6071 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6072 value_of_mips_user_reg
,
6073 &mips_numeric_register_aliases
[i
].regnum
);
6079 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6081 struct gdbarch_info info
;
6083 /* Force the architecture to update, and (if it's a MIPS architecture)
6084 mips_gdbarch_init will take care of the rest. */
6085 gdbarch_info_init (&info
);
6086 gdbarch_update_p (info
);
6089 /* Print out which MIPS ABI is in use. */
6092 show_mips_abi (struct ui_file
*file
,
6094 struct cmd_list_element
*ignored_cmd
,
6095 const char *ignored_value
)
6097 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6100 "The MIPS ABI is unknown because the current architecture "
6104 enum mips_abi global_abi
= global_mips_abi ();
6105 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6106 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6108 if (global_abi
== MIPS_ABI_UNKNOWN
)
6111 "The MIPS ABI is set automatically (currently \"%s\").\n",
6113 else if (global_abi
== actual_abi
)
6116 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6120 /* Probably shouldn't happen... */
6123 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6124 actual_abi_str
, mips_abi_strings
[global_abi
]);
6130 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6132 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6136 int ef_mips_32bitmode
;
6137 /* Determine the ISA. */
6138 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6156 /* Determine the size of a pointer. */
6157 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6158 fprintf_unfiltered (file
,
6159 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6161 fprintf_unfiltered (file
,
6162 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6164 fprintf_unfiltered (file
,
6165 "mips_dump_tdep: ef_mips_arch = %d\n",
6167 fprintf_unfiltered (file
,
6168 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6169 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6170 fprintf_unfiltered (file
,
6171 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6172 mips_mask_address_p (tdep
),
6173 tdep
->default_mask_address_p
);
6175 fprintf_unfiltered (file
,
6176 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6177 MIPS_DEFAULT_FPU_TYPE
,
6178 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6179 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6180 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6182 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6183 MIPS_EABI (gdbarch
));
6184 fprintf_unfiltered (file
,
6185 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6186 MIPS_FPU_TYPE (gdbarch
),
6187 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6188 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6189 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6193 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6196 _initialize_mips_tdep (void)
6198 static struct cmd_list_element
*mipsfpulist
= NULL
;
6199 struct cmd_list_element
*c
;
6201 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6202 if (MIPS_ABI_LAST
+ 1
6203 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6204 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6206 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6208 mips_pdr_data
= register_objfile_data ();
6210 /* Create feature sets with the appropriate properties. The values
6211 are not important. */
6212 mips_tdesc_gp32
= allocate_target_description ();
6213 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6215 mips_tdesc_gp64
= allocate_target_description ();
6216 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6218 /* Add root prefix command for all "set mips"/"show mips" commands */
6219 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6220 _("Various MIPS specific commands."),
6221 &setmipscmdlist
, "set mips ", 0, &setlist
);
6223 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6224 _("Various MIPS specific commands."),
6225 &showmipscmdlist
, "show mips ", 0, &showlist
);
6227 /* Allow the user to override the ABI. */
6228 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6229 &mips_abi_string
, _("\
6230 Set the MIPS ABI used by this program."), _("\
6231 Show the MIPS ABI used by this program."), _("\
6232 This option can be set to one of:\n\
6233 auto - the default ABI associated with the current binary\n\
6242 &setmipscmdlist
, &showmipscmdlist
);
6244 /* Let the user turn off floating point and set the fence post for
6245 heuristic_proc_start. */
6247 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6248 _("Set use of MIPS floating-point coprocessor."),
6249 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6250 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6251 _("Select single-precision MIPS floating-point coprocessor."),
6253 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6254 _("Select double-precision MIPS floating-point coprocessor."),
6256 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6257 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6258 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6259 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6260 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6261 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6262 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6263 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6264 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6265 _("Select MIPS floating-point coprocessor automatically."),
6267 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6268 _("Show current use of MIPS floating-point coprocessor target."),
6271 /* We really would like to have both "0" and "unlimited" work, but
6272 command.c doesn't deal with that. So make it a var_zinteger
6273 because the user can always use "999999" or some such for unlimited. */
6274 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6275 &heuristic_fence_post
, _("\
6276 Set the distance searched for the start of a function."), _("\
6277 Show the distance searched for the start of a function."), _("\
6278 If you are debugging a stripped executable, GDB needs to search through the\n\
6279 program for the start of a function. This command sets the distance of the\n\
6280 search. The only need to set it is when debugging a stripped executable."),
6281 reinit_frame_cache_sfunc
,
6282 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
6283 &setlist
, &showlist
);
6285 /* Allow the user to control whether the upper bits of 64-bit
6286 addresses should be zeroed. */
6287 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6288 &mask_address_var
, _("\
6289 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6290 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6291 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6292 allow GDB to determine the correct value."),
6293 NULL
, show_mask_address
,
6294 &setmipscmdlist
, &showmipscmdlist
);
6296 /* Allow the user to control the size of 32 bit registers within the
6297 raw remote packet. */
6298 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6299 &mips64_transfers_32bit_regs_p
, _("\
6300 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6302 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6304 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6305 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6306 64 bits for others. Use \"off\" to disable compatibility mode"),
6307 set_mips64_transfers_32bit_regs
,
6308 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6309 &setlist
, &showlist
);
6311 /* Debug this files internals. */
6312 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6314 Set mips debugging."), _("\
6315 Show mips debugging."), _("\
6316 When non-zero, mips specific debugging is enabled."),
6318 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
6319 &setdebuglist
, &showdebuglist
);