1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
41 #include "opcode/mips.h"
46 /* The sizes of floating point registers. */
50 MIPS_FPU_SINGLE_REGSIZE
= 4,
51 MIPS_FPU_DOUBLE_REGSIZE
= 8
54 /* All the possible MIPS ABIs. */
66 struct frame_extra_info
68 mips_extra_func_info_t proc_desc
;
72 /* Various MIPS ISA options (related to stack analysis) can be
73 overridden dynamically. Establish an enum/array for managing
76 static const char size_auto
[] = "auto";
77 static const char size_32
[] = "32";
78 static const char size_64
[] = "64";
80 static const char *size_enums
[] = {
87 /* Some MIPS boards don't support floating point while others only
88 support single-precision floating-point operations. See also
89 FP_REGISTER_DOUBLE. */
93 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
94 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
95 MIPS_FPU_NONE
/* No floating point. */
98 #ifndef MIPS_DEFAULT_FPU_TYPE
99 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
101 static int mips_fpu_type_auto
= 1;
102 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
103 #define MIPS_FPU_TYPE mips_fpu_type
105 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
106 #ifndef FP_REGISTER_DOUBLE
107 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
110 static int mips_debug
= 0;
112 /* MIPS specific per-architecture information */
115 /* from the elf header */
118 enum mips_abi mips_abi
;
119 enum mips_fpu_type mips_fpu_type
;
120 int mips_last_arg_regnum
;
121 int mips_last_fp_arg_regnum
;
122 int mips_default_saved_regsize
;
123 int mips_fp_register_double
;
124 int mips_regs_have_home_p
;
125 int mips_default_stack_argsize
;
126 int gdb_target_is_mips64
;
131 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
132 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
136 #undef MIPS_LAST_FP_ARG_REGNUM
137 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
141 #undef MIPS_LAST_ARG_REGNUM
142 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
147 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
150 /* Return the currently configured (or set) saved register size. */
153 #undef MIPS_DEFAULT_SAVED_REGSIZE
154 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
155 #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE)
156 #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
159 static const char *mips_saved_regsize_string
= size_auto
;
161 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
164 mips_saved_regsize ()
166 if (mips_saved_regsize_string
== size_auto
)
167 return MIPS_DEFAULT_SAVED_REGSIZE
;
168 else if (mips_saved_regsize_string
== size_64
)
170 else /* if (mips_saved_regsize_string == size_32) */
174 /* Indicate that the ABI makes use of double-precision registers
175 provided by the FPU (rather than combining pairs of registers to
176 form double-precision values). Do not use "TARGET_IS_MIPS64" to
177 determine if the ABI is using double-precision registers. See also
180 #undef FP_REGISTER_DOUBLE
181 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
184 /* Does the caller allocate a ``home'' for each register used in the
185 function call? The N32 ABI and MIPS_EABI do not, the others do. */
188 #undef MIPS_REGS_HAVE_HOME_P
189 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
190 #elif !defined (MIPS_REGS_HAVE_HOME_P)
191 #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI)
194 /* The amount of space reserved on the stack for registers. This is
195 different to MIPS_SAVED_REGSIZE as it determines the alignment of
196 data allocated after the registers have run out. */
199 #undef MIPS_DEFAULT_STACK_ARGSIZE
200 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
201 #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE)
202 #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE)
205 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
207 static const char *mips_stack_argsize_string
= size_auto
;
210 mips_stack_argsize (void)
212 if (mips_stack_argsize_string
== size_auto
)
213 return MIPS_DEFAULT_STACK_ARGSIZE
;
214 else if (mips_stack_argsize_string
== size_64
)
216 else /* if (mips_stack_argsize_string == size_32) */
221 #undef GDB_TARGET_IS_MIPS64
222 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
225 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
228 static int mips_in_lenient_prologue (CORE_ADDR
, CORE_ADDR
);
231 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
233 static void mips_print_register (int, int);
235 static mips_extra_func_info_t
236 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*);
238 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
240 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
242 int mips_set_processor_type (char *);
244 static void mips_show_processor_type_command (char *, int);
246 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
248 static mips_extra_func_info_t
249 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
);
251 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
252 mips_extra_func_info_t proc_desc
);
254 /* This value is the model of MIPS in use. It is derived from the value
255 of the PrID register. */
257 char *mips_processor_type
;
259 char *tmp_mips_processor_type
;
261 /* A set of original names, to be used when restoring back to generic
262 registers from a specific set. */
264 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
265 char **mips_processor_reg_names
= mips_generic_reg_names
;
267 /* The list of available "set mips " and "show mips " commands */
268 static struct cmd_list_element
*setmipscmdlist
= NULL
;
269 static struct cmd_list_element
*showmipscmdlist
= NULL
;
272 mips_register_name (i
)
275 return mips_processor_reg_names
[i
];
278 /* Names of IDT R3041 registers. */
280 char *mips_r3041_reg_names
[] = {
281 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
282 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
283 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
284 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
285 "sr", "lo", "hi", "bad", "cause","pc",
286 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
287 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
288 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
289 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
290 "fsr", "fir", "fp", "",
291 "", "", "bus", "ccfg", "", "", "", "",
292 "", "", "port", "cmp", "", "", "epc", "prid",
295 /* Names of IDT R3051 registers. */
297 char *mips_r3051_reg_names
[] = {
298 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
299 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
300 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
301 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
302 "sr", "lo", "hi", "bad", "cause","pc",
303 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
304 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
305 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
306 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
307 "fsr", "fir", "fp", "",
308 "inx", "rand", "elo", "", "ctxt", "", "", "",
309 "", "", "ehi", "", "", "", "epc", "prid",
312 /* Names of IDT R3081 registers. */
314 char *mips_r3081_reg_names
[] = {
315 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
316 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
317 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
318 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
319 "sr", "lo", "hi", "bad", "cause","pc",
320 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
321 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
322 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
323 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
324 "fsr", "fir", "fp", "",
325 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
326 "", "", "ehi", "", "", "", "epc", "prid",
329 /* Names of LSI 33k registers. */
331 char *mips_lsi33k_reg_names
[] = {
332 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
333 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
334 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
335 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
336 "epc", "hi", "lo", "sr", "cause","badvaddr",
337 "dcic", "bpc", "bda", "", "", "", "", "",
338 "", "", "", "", "", "", "", "",
339 "", "", "", "", "", "", "", "",
340 "", "", "", "", "", "", "", "",
342 "", "", "", "", "", "", "", "",
343 "", "", "", "", "", "", "", "",
349 } mips_processor_type_table
[] = {
350 { "generic", mips_generic_reg_names
},
351 { "r3041", mips_r3041_reg_names
},
352 { "r3051", mips_r3051_reg_names
},
353 { "r3071", mips_r3081_reg_names
},
354 { "r3081", mips_r3081_reg_names
},
355 { "lsi33k", mips_lsi33k_reg_names
},
363 /* Table to translate MIPS16 register field to actual register number. */
364 static int mips16_to_32_reg
[8] =
365 {16, 17, 2, 3, 4, 5, 6, 7};
367 /* Heuristic_proc_start may hunt through the text section for a long
368 time across a 2400 baud serial line. Allows the user to limit this
371 static unsigned int heuristic_fence_post
= 0;
373 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
374 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
375 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
376 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
377 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
378 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
379 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
380 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
381 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
382 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
383 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
384 #define _PROC_MAGIC_ 0x0F0F0F0F
385 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
386 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
388 struct linked_proc_info
390 struct mips_extra_func_info info
;
391 struct linked_proc_info
*next
;
393 *linked_proc_desc_table
= NULL
;
396 mips_print_extra_frame_info (fi
)
397 struct frame_info
*fi
;
401 && fi
->extra_info
->proc_desc
402 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
403 printf_filtered (" frame pointer is at %s+%s\n",
404 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
405 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
408 /* Convert between RAW and VIRTUAL registers. The RAW register size
409 defines the remote-gdb packet. */
411 static int mips64_transfers_32bit_regs_p
= 0;
414 mips_register_raw_size (reg_nr
)
417 if (mips64_transfers_32bit_regs_p
)
418 return REGISTER_VIRTUAL_SIZE (reg_nr
);
424 mips_register_convertible (reg_nr
)
427 if (mips64_transfers_32bit_regs_p
)
430 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
434 mips_register_convert_to_virtual (n
, virtual_type
, raw_buf
, virt_buf
)
436 struct type
*virtual_type
;
440 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
442 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
443 TYPE_LENGTH (virtual_type
));
447 TYPE_LENGTH (virtual_type
));
451 mips_register_convert_to_raw (virtual_type
, n
, virt_buf
, raw_buf
)
452 struct type
*virtual_type
;
457 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
458 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
459 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
461 TYPE_LENGTH (virtual_type
));
465 TYPE_LENGTH (virtual_type
));
468 /* Should the upper word of 64-bit addresses be zeroed? */
469 static int mask_address_p
= 1;
471 /* Should call_function allocate stack space for a struct return? */
473 mips_use_struct_convention (gcc_p
, type
)
478 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
480 return 1; /* Structures are returned by ref in extra arg0 */
483 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
486 pc_is_mips16 (bfd_vma memaddr
)
488 struct minimal_symbol
*sym
;
490 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
491 if (IS_MIPS16_ADDR (memaddr
))
494 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
495 the high bit of the info field. Use this to decide if the function is
496 MIPS16 or normal MIPS. */
497 sym
= lookup_minimal_symbol_by_pc (memaddr
);
499 return MSYMBOL_IS_SPECIAL (sym
);
505 /* This returns the PC of the first inst after the prologue. If we can't
506 find the prologue, then return 0. */
509 after_prologue (pc
, proc_desc
)
511 mips_extra_func_info_t proc_desc
;
513 struct symtab_and_line sal
;
514 CORE_ADDR func_addr
, func_end
;
517 proc_desc
= find_proc_desc (pc
, NULL
);
521 /* If function is frameless, then we need to do it the hard way. I
522 strongly suspect that frameless always means prologueless... */
523 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
524 && PROC_FRAME_OFFSET (proc_desc
) == 0)
528 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
529 return 0; /* Unknown */
531 sal
= find_pc_line (func_addr
, 0);
533 if (sal
.end
< func_end
)
536 /* The line after the prologue is after the end of the function. In this
537 case, tell the caller to find the prologue the hard way. */
542 /* Decode a MIPS32 instruction that saves a register in the stack, and
543 set the appropriate bit in the general register mask or float register mask
544 to indicate which register is saved. This is a helper function
545 for mips_find_saved_regs. */
548 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
550 unsigned long *gen_mask
;
551 unsigned long *float_mask
;
555 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
556 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
557 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
559 /* It might be possible to use the instruction to
560 find the offset, rather than the code below which
561 is based on things being in a certain order in the
562 frame, but figuring out what the instruction's offset
563 is relative to might be a little tricky. */
564 reg
= (inst
& 0x001f0000) >> 16;
565 *gen_mask
|= (1 << reg
);
567 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
568 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
569 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
572 reg
= ((inst
& 0x001f0000) >> 16);
573 *float_mask
|= (1 << reg
);
577 /* Decode a MIPS16 instruction that saves a register in the stack, and
578 set the appropriate bit in the general register or float register mask
579 to indicate which register is saved. This is a helper function
580 for mips_find_saved_regs. */
583 mips16_decode_reg_save (inst
, gen_mask
)
585 unsigned long *gen_mask
;
587 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
589 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
590 *gen_mask
|= (1 << reg
);
592 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
594 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
595 *gen_mask
|= (1 << reg
);
597 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
598 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
599 *gen_mask
|= (1 << RA_REGNUM
);
603 /* Fetch and return instruction from the specified location. If the PC
604 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
607 mips_fetch_instruction (addr
)
610 char buf
[MIPS_INSTLEN
];
614 if (pc_is_mips16 (addr
))
616 instlen
= MIPS16_INSTLEN
;
617 addr
= UNMAKE_MIPS16_ADDR (addr
);
620 instlen
= MIPS_INSTLEN
;
621 status
= read_memory_nobpt (addr
, buf
, instlen
);
623 memory_error (status
, addr
);
624 return extract_unsigned_integer (buf
, instlen
);
628 /* These the fields of 32 bit mips instructions */
629 #define mips32_op(x) (x >> 25)
630 #define itype_op(x) (x >> 25)
631 #define itype_rs(x) ((x >> 21)& 0x1f)
632 #define itype_rt(x) ((x >> 16) & 0x1f)
633 #define itype_immediate(x) ( x & 0xffff)
635 #define jtype_op(x) (x >> 25)
636 #define jtype_target(x) ( x & 0x03fffff)
638 #define rtype_op(x) (x >>25)
639 #define rtype_rs(x) ((x>>21) & 0x1f)
640 #define rtype_rt(x) ((x>>16) & 0x1f)
641 #define rtype_rd(x) ((x>>11) & 0x1f)
642 #define rtype_shamt(x) ((x>>6) & 0x1f)
643 #define rtype_funct(x) (x & 0x3f )
646 mips32_relative_offset (unsigned long inst
)
649 x
= itype_immediate (inst
);
650 if (x
& 0x8000) /* sign bit set */
652 x
|= 0xffff0000; /* sign extension */
658 /* Determine whate to set a single step breakpoint while considering
661 mips32_next_pc (CORE_ADDR pc
)
665 inst
= mips_fetch_instruction (pc
);
666 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
668 if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
670 op
= ((inst
>> 25) & 0x03);
674 goto equal_branch
; /* BEQL */
676 goto neq_branch
; /* BNEZ */
678 goto less_branch
; /* BLEZ */
680 goto greater_branch
; /* BGTZ */
686 pc
+= 4; /* Not a branch, next instruction is easy */
689 { /* This gets way messy */
691 /* Further subdivide into SPECIAL, REGIMM and other */
692 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
694 case 0: /* SPECIAL */
695 op
= rtype_funct (inst
);
700 pc
= read_register (rtype_rs (inst
)); /* Set PC to that address */
706 break; /* end special */
709 op
= jtype_op (inst
); /* branch condition */
710 switch (jtype_op (inst
))
714 case 16: /* BLTZALL */
715 case 18: /* BLTZALL */
717 if (read_register (itype_rs (inst
)) < 0)
718 pc
+= mips32_relative_offset (inst
) + 4;
720 pc
+= 8; /* after the delay slot */
724 case 17: /* BGEZAL */
725 case 19: /* BGEZALL */
726 greater_equal_branch
:
727 if (read_register (itype_rs (inst
)) >= 0)
728 pc
+= mips32_relative_offset (inst
) + 4;
730 pc
+= 8; /* after the delay slot */
732 /* All of the other intructions in the REGIMM catagory */
737 break; /* end REGIMM */
742 reg
= jtype_target (inst
) << 2;
743 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
744 /* Whats this mysterious 0xf000000 adjustment ??? */
747 /* FIXME case JALX : */
750 reg
= jtype_target (inst
) << 2;
751 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
752 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
754 break; /* The new PC will be alternate mode */
755 case 4: /* BEQ , BEQL */
757 if (read_register (itype_rs (inst
)) ==
758 read_register (itype_rt (inst
)))
759 pc
+= mips32_relative_offset (inst
) + 4;
763 case 5: /* BNE , BNEL */
765 if (read_register (itype_rs (inst
)) !=
766 read_register (itype_rs (inst
)))
767 pc
+= mips32_relative_offset (inst
) + 4;
771 case 6: /* BLEZ , BLEZL */
773 if (read_register (itype_rs (inst
) <= 0))
774 pc
+= mips32_relative_offset (inst
) + 4;
779 greater_branch
: /* BGTZ BGTZL */
780 if (read_register (itype_rs (inst
) > 0))
781 pc
+= mips32_relative_offset (inst
) + 4;
790 } /* mips32_next_pc */
792 /* Decoding the next place to set a breakpoint is irregular for the
793 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
794 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
795 We dont want to set a single step instruction on the extend instruction
799 /* Lots of mips16 instruction formats */
800 /* Predicting jumps requires itype,ritype,i8type
801 and their extensions extItype,extritype,extI8type
803 enum mips16_inst_fmts
805 itype
, /* 0 immediate 5,10 */
806 ritype
, /* 1 5,3,8 */
807 rrtype
, /* 2 5,3,3,5 */
808 rritype
, /* 3 5,3,3,5 */
809 rrrtype
, /* 4 5,3,3,3,2 */
810 rriatype
, /* 5 5,3,3,1,4 */
811 shifttype
, /* 6 5,3,3,3,2 */
812 i8type
, /* 7 5,3,8 */
813 i8movtype
, /* 8 5,3,3,5 */
814 i8mov32rtype
, /* 9 5,3,5,3 */
815 i64type
, /* 10 5,3,8 */
816 ri64type
, /* 11 5,3,3,5 */
817 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
818 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
819 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
820 extRRItype
, /* 15 5,5,5,5,3,3,5 */
821 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
822 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
823 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
824 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
825 extRi64type
, /* 20 5,6,5,5,3,3,5 */
826 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
828 /* I am heaping all the fields of the formats into one structure and then,
829 only the fields which are involved in instruction extension */
833 enum mips16_inst_fmts fmt
;
834 unsigned long offset
;
835 unsigned int regx
; /* Function in i8 type */
842 print_unpack (char *comment
,
843 struct upk_mips16
*u
)
845 printf ("%s %04x ,f(%d) off(%s) (x(%x) y(%x)\n",
846 comment
, u
->inst
, u
->fmt
, paddr (u
->offset
), u
->regx
, u
->regy
);
849 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
850 format for the bits which make up the immediatate extension.
853 extended_offset (unsigned long extension
)
856 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
858 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
860 value
|= extension
& 0x01f; /* extract 4:0 */
864 /* Only call this function if you know that this is an extendable
865 instruction, It wont malfunction, but why make excess remote memory references?
866 If the immediate operands get sign extended or somthing, do it after
867 the extension is performed.
869 /* FIXME: Every one of these cases needs to worry about sign extension
870 when the offset is to be used in relative addressing */
873 static unsigned short
874 fetch_mips_16 (CORE_ADDR pc
)
877 pc
&= 0xfffffffe; /* clear the low order bit */
878 target_read_memory (pc
, buf
, 2);
879 return extract_unsigned_integer (buf
, 2);
883 unpack_mips16 (CORE_ADDR pc
,
884 struct upk_mips16
*upk
)
887 unsigned long extension
;
889 extpc
= (pc
- 4) & ~0x01; /* Extensions are 32 bit instructions */
890 /* Decrement to previous address and loose the 16bit mode flag */
891 /* return if the instruction was extendable, but not actually extended */
892 extended
= ((mips32_op (extension
) == 30) ? 1 : 0);
895 extension
= mips_fetch_instruction (extpc
);
904 value
= extended_offset (extension
);
905 value
= value
<< 11; /* rom for the original value */
906 value
|= upk
->inst
& 0x7ff; /* eleven bits from instruction */
910 value
= upk
->inst
& 0x7ff;
911 /* FIXME : Consider sign extension */
918 { /* A register identifier and an offset */
919 /* Most of the fields are the same as I type but the
920 immediate value is of a different length */
924 value
= extended_offset (extension
);
925 value
= value
<< 8; /* from the original instruction */
926 value
|= upk
->inst
& 0xff; /* eleven bits from instruction */
927 upk
->regx
= (extension
>> 8) & 0x07; /* or i8 funct */
928 if (value
& 0x4000) /* test the sign bit , bit 26 */
930 value
&= ~0x3fff; /* remove the sign bit */
936 value
= upk
->inst
& 0xff; /* 8 bits */
937 upk
->regx
= (upk
->inst
>> 8) & 0x07; /* or i8 funct */
938 /* FIXME: Do sign extension , this format needs it */
939 if (value
& 0x80) /* THIS CONFUSES ME */
941 value
&= 0xef; /* remove the sign bit */
952 unsigned short nexthalf
;
953 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f);
955 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
961 printf_filtered ("Decoding unimplemented instruction format type\n");
964 /* print_unpack("UPK",upk) ; */
968 #define mips16_op(x) (x >> 11)
970 /* This is a map of the opcodes which ae known to perform branches */
971 static unsigned char map16
[32] =
972 {0, 0, 1, 1, 1, 1, 0, 0,
973 0, 0, 0, 0, 1, 0, 0, 0,
974 0, 0, 0, 0, 0, 0, 0, 0,
975 0, 0, 0, 0, 0, 1, 1, 0
979 add_offset_16 (CORE_ADDR pc
, int offset
)
981 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
987 static struct upk_mips16 upk
;
990 mips16_next_pc (CORE_ADDR pc
)
994 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
995 inst
= fetch_mips_16 (pc
);
997 op
= mips16_op (upk
.inst
);
1003 case 2: /* Branch */
1005 unpack_mips16 (pc
, &upk
);
1008 offset
= upk
.offset
;
1014 pc
+= (offset
<< 1) + 2;
1017 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1019 unpack_mips16 (pc
, &upk
);
1020 pc
= add_offset_16 (pc
, upk
.offset
);
1021 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
1022 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1028 unpack_mips16 (pc
, &upk
);
1029 reg
= read_register (upk
.regx
);
1031 pc
+= (upk
.offset
<< 1) + 2;
1037 unpack_mips16 (pc
, &upk
);
1038 reg
= read_register (upk
.regx
);
1040 pc
+= (upk
.offset
<< 1) + 2;
1044 case 12: /* I8 Formats btez btnez */
1046 unpack_mips16 (pc
, &upk
);
1047 /* upk.regx contains the opcode */
1048 reg
= read_register (24); /* Test register is 24 */
1049 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1050 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1051 /* pc = add_offset_16(pc,upk.offset) ; */
1052 pc
+= (upk
.offset
<< 1) + 2;
1056 case 29: /* RR Formats JR, JALR, JALR-RA */
1058 op
= upk
.inst
& 0x1f;
1061 upk
.regx
= (upk
.inst
>> 8) & 0x07;
1062 upk
.regy
= (upk
.inst
>> 5) & 0x07;
1070 break; /* Function return instruction */
1076 break; /* BOGUS Guess */
1078 pc
= read_register (reg
);
1083 case 30: /* This is an extend instruction */
1084 pc
+= 4; /* Dont be setting breakpints on the second half */
1087 printf ("Filtered - next PC probably incorrrect due to jump inst\n");
1093 pc
+= 2; /* just a good old instruction */
1094 /* See if we CAN actually break on the next instruction */
1095 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
1097 } /* mips16_next_pc */
1099 /* The mips_next_pc function supports single_tep when the remote target monitor or
1100 stub is not developed enough to so a single_step.
1101 It works by decoding the current instruction and predicting where a branch
1102 will go. This isnt hard because all the data is available.
1103 The MIPS32 and MIPS16 variants are quite different
1106 mips_next_pc (CORE_ADDR pc
)
1109 /* inst = mips_fetch_instruction(pc) ; */
1110 /* if (pc_is_mips16) <----- This is failing */
1112 return mips16_next_pc (pc
);
1114 return mips32_next_pc (pc
);
1115 } /* mips_next_pc */
1117 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1121 mips_find_saved_regs (fci
)
1122 struct frame_info
*fci
;
1125 CORE_ADDR reg_position
;
1126 /* r0 bit means kernel trap */
1128 /* What registers have been saved? Bitmasks. */
1129 unsigned long gen_mask
, float_mask
;
1130 mips_extra_func_info_t proc_desc
;
1133 frame_saved_regs_zalloc (fci
);
1135 /* If it is the frame for sigtramp, the saved registers are located
1136 in a sigcontext structure somewhere on the stack.
1137 If the stack layout for sigtramp changes we might have to change these
1138 constants and the companion fixup_sigtramp in mdebugread.c */
1139 #ifndef SIGFRAME_BASE
1140 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1141 above the sigtramp frame. */
1142 #define SIGFRAME_BASE MIPS_REGSIZE
1143 /* FIXME! Are these correct?? */
1144 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1145 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1146 #define SIGFRAME_FPREGSAVE_OFF \
1147 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1149 #ifndef SIGFRAME_REG_SIZE
1150 /* FIXME! Is this correct?? */
1151 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1153 if (fci
->signal_handler_caller
)
1155 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1157 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1158 + ireg
* SIGFRAME_REG_SIZE
;
1159 fci
->saved_regs
[ireg
] = reg_position
;
1161 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1163 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1164 + ireg
* SIGFRAME_REG_SIZE
;
1165 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1167 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1171 proc_desc
= fci
->extra_info
->proc_desc
;
1172 if (proc_desc
== NULL
)
1173 /* I'm not sure how/whether this can happen. Normally when we can't
1174 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1175 and set the saved_regs right away. */
1178 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1179 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1180 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1182 if ( /* In any frame other than the innermost or a frame interrupted by
1183 a signal, we assume that all registers have been saved.
1184 This assumes that all register saves in a function happen before
1185 the first function call. */
1186 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1188 /* In a dummy frame we know exactly where things are saved. */
1189 && !PROC_DESC_IS_DUMMY (proc_desc
)
1191 /* Don't bother unless we are inside a function prologue. Outside the
1192 prologue, we know where everything is. */
1194 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1196 /* Not sure exactly what kernel_trap means, but if it means
1197 the kernel saves the registers without a prologue doing it,
1198 we better not examine the prologue to see whether registers
1199 have been saved yet. */
1202 /* We need to figure out whether the registers that the proc_desc
1203 claims are saved have been saved yet. */
1207 /* Bitmasks; set if we have found a save for the register. */
1208 unsigned long gen_save_found
= 0;
1209 unsigned long float_save_found
= 0;
1212 /* If the address is odd, assume this is MIPS16 code. */
1213 addr
= PROC_LOW_ADDR (proc_desc
);
1214 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1216 /* Scan through this function's instructions preceding the current
1217 PC, and look for those that save registers. */
1218 while (addr
< fci
->pc
)
1220 inst
= mips_fetch_instruction (addr
);
1221 if (pc_is_mips16 (addr
))
1222 mips16_decode_reg_save (inst
, &gen_save_found
);
1224 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1227 gen_mask
= gen_save_found
;
1228 float_mask
= float_save_found
;
1231 /* Fill in the offsets for the registers which gen_mask says
1233 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1234 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1235 if (gen_mask
& 0x80000000)
1237 fci
->saved_regs
[ireg
] = reg_position
;
1238 reg_position
-= MIPS_SAVED_REGSIZE
;
1241 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1242 of that normally used by gcc. Therefore, we have to fetch the first
1243 instruction of the function, and if it's an entry instruction that
1244 saves $s0 or $s1, correct their saved addresses. */
1245 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1247 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1248 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1251 int sreg_count
= (inst
>> 6) & 3;
1253 /* Check if the ra register was pushed on the stack. */
1254 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1256 reg_position
-= MIPS_SAVED_REGSIZE
;
1258 /* Check if the s0 and s1 registers were pushed on the stack. */
1259 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1261 fci
->saved_regs
[reg
] = reg_position
;
1262 reg_position
-= MIPS_SAVED_REGSIZE
;
1267 /* Fill in the offsets for the registers which float_mask says
1269 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1271 /* The freg_offset points to where the first *double* register
1272 is saved. So skip to the high-order word. */
1273 if (!GDB_TARGET_IS_MIPS64
)
1274 reg_position
+= MIPS_SAVED_REGSIZE
;
1276 /* Fill in the offsets for the float registers which float_mask says
1278 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1279 if (float_mask
& 0x80000000)
1281 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1282 reg_position
-= MIPS_SAVED_REGSIZE
;
1285 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1289 read_next_frame_reg (fi
, regno
)
1290 struct frame_info
*fi
;
1293 for (; fi
; fi
= fi
->next
)
1295 /* We have to get the saved sp from the sigcontext
1296 if it is a signal handler frame. */
1297 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1301 if (fi
->saved_regs
== NULL
)
1302 mips_find_saved_regs (fi
);
1303 if (fi
->saved_regs
[regno
])
1304 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1307 return read_register (regno
);
1310 /* mips_addr_bits_remove - remove useless address bits */
1313 mips_addr_bits_remove (addr
)
1316 if (GDB_TARGET_IS_MIPS64
)
1318 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1320 /* This hack is a work-around for existing boards using
1321 PMON, the simulator, and any other 64-bit targets that
1322 doesn't have true 64-bit addressing. On these targets,
1323 the upper 32 bits of addresses are ignored by the
1324 hardware. Thus, the PC or SP are likely to have been
1325 sign extended to all 1s by instruction sequences that
1326 load 32-bit addresses. For example, a typical piece of
1327 code that loads an address is this: lui $r2, <upper 16
1328 bits> ori $r2, <lower 16 bits> But the lui sign-extends
1329 the value such that the upper 32 bits may be all 1s. The
1330 workaround is simply to mask off these bits. In the
1331 future, gcc may be changed to support true 64-bit
1332 addressing, and this masking will have to be disabled. */
1333 addr
&= (CORE_ADDR
) 0xffffffff;
1338 /* Even when GDB is configured for some 32-bit targets
1339 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1340 so CORE_ADDR is 64 bits. So we still have to mask off
1341 useless bits from addresses. */
1342 addr
&= (CORE_ADDR
) 0xffffffff;
1348 mips_init_frame_pc_first (fromleaf
, prev
)
1350 struct frame_info
*prev
;
1354 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1355 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1356 tmp
= mips_skip_stub (pc
);
1357 prev
->pc
= tmp
? tmp
: pc
;
1362 mips_frame_saved_pc (frame
)
1363 struct frame_info
*frame
;
1366 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1367 /* We have to get the saved pc from the sigcontext
1368 if it is a signal handler frame. */
1369 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1370 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1372 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1373 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1375 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1377 return ADDR_BITS_REMOVE (saved_pc
);
1380 static struct mips_extra_func_info temp_proc_desc
;
1381 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1383 /* Set a register's saved stack address in temp_saved_regs. If an address
1384 has already been set for this register, do nothing; this way we will
1385 only recognize the first save of a given register in a function prologue.
1386 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1389 set_reg_offset (regno
, offset
)
1393 if (temp_saved_regs
[regno
] == 0)
1394 temp_saved_regs
[regno
] = offset
;
1398 /* Test whether the PC points to the return instruction at the
1399 end of a function. */
1402 mips_about_to_return (pc
)
1405 if (pc_is_mips16 (pc
))
1406 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1407 generates a "jr $ra"; other times it generates code to load
1408 the return address from the stack to an accessible register (such
1409 as $a3), then a "jr" using that register. This second case
1410 is almost impossible to distinguish from an indirect jump
1411 used for switch statements, so we don't even try. */
1412 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1414 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1418 /* This fencepost looks highly suspicious to me. Removing it also
1419 seems suspicious as it could affect remote debugging across serial
1423 heuristic_proc_start (pc
)
1431 pc
= ADDR_BITS_REMOVE (pc
);
1433 fence
= start_pc
- heuristic_fence_post
;
1437 if (heuristic_fence_post
== UINT_MAX
1438 || fence
< VM_MIN_ADDRESS
)
1439 fence
= VM_MIN_ADDRESS
;
1441 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1443 /* search back for previous return */
1444 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1445 if (start_pc
< fence
)
1447 /* It's not clear to me why we reach this point when
1448 stop_soon_quietly, but with this test, at least we
1449 don't print out warnings for every child forked (eg, on
1450 decstation). 22apr93 rich@cygnus.com. */
1451 if (!stop_soon_quietly
)
1453 static int blurb_printed
= 0;
1455 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1460 /* This actually happens frequently in embedded
1461 development, when you first connect to a board
1462 and your stack pointer and pc are nowhere in
1463 particular. This message needs to give people
1464 in that situation enough information to
1465 determine that it's no big deal. */
1466 printf_filtered ("\n\
1467 GDB is unable to find the start of the function at 0x%s\n\
1468 and thus can't determine the size of that function's stack frame.\n\
1469 This means that GDB may be unable to access that stack frame, or\n\
1470 the frames below it.\n\
1471 This problem is most likely caused by an invalid program counter or\n\
1473 However, if you think GDB should simply search farther back\n\
1474 from 0x%s for code which looks like the beginning of a\n\
1475 function, you can increase the range of the search using the `set\n\
1476 heuristic-fence-post' command.\n",
1477 paddr_nz (pc
), paddr_nz (pc
));
1484 else if (pc_is_mips16 (start_pc
))
1486 unsigned short inst
;
1488 /* On MIPS16, any one of the following is likely to be the
1489 start of a function:
1493 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1494 inst
= mips_fetch_instruction (start_pc
);
1495 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1496 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1497 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1498 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1500 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1501 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1506 else if (mips_about_to_return (start_pc
))
1508 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1513 /* skip nops (usually 1) 0 - is this */
1514 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1515 start_pc
+= MIPS_INSTLEN
;
1520 /* Fetch the immediate value from a MIPS16 instruction.
1521 If the previous instruction was an EXTEND, use it to extend
1522 the upper bits of the immediate value. This is a helper function
1523 for mips16_heuristic_proc_desc. */
1526 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1527 unsigned short prev_inst
; /* previous instruction */
1528 unsigned short inst
; /* current instruction */
1529 int nbits
; /* number of bits in imm field */
1530 int scale
; /* scale factor to be applied to imm */
1531 int is_signed
; /* is the imm field signed? */
1535 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1537 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1538 if (offset
& 0x8000) /* check for negative extend */
1539 offset
= 0 - (0x10000 - (offset
& 0xffff));
1540 return offset
| (inst
& 0x1f);
1544 int max_imm
= 1 << nbits
;
1545 int mask
= max_imm
- 1;
1546 int sign_bit
= max_imm
>> 1;
1548 offset
= inst
& mask
;
1549 if (is_signed
&& (offset
& sign_bit
))
1550 offset
= 0 - (max_imm
- offset
);
1551 return offset
* scale
;
1556 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1557 stream from start_pc to limit_pc. */
1560 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1561 CORE_ADDR start_pc
, limit_pc
;
1562 struct frame_info
*next_frame
;
1566 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1567 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1568 unsigned inst
= 0; /* current instruction */
1569 unsigned entry_inst
= 0; /* the entry instruction */
1572 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1573 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1575 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1577 /* Save the previous instruction. If it's an EXTEND, we'll extract
1578 the immediate offset extension from it in mips16_get_imm. */
1581 /* Fetch and decode the instruction. */
1582 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1583 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1584 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1586 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1587 if (offset
< 0) /* negative stack adjustment? */
1588 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1590 /* Exit loop if a positive stack adjustment is found, which
1591 usually means that the stack cleanup code in the function
1592 epilogue is reached. */
1595 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1597 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1598 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1599 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1600 set_reg_offset (reg
, sp
+ offset
);
1602 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1604 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1605 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1606 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1607 set_reg_offset (reg
, sp
+ offset
);
1609 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1611 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1612 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1613 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1615 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1617 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1618 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1619 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1621 else if (inst
== 0x673d) /* move $s1, $sp */
1624 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1626 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1628 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1629 frame_addr
= sp
+ offset
;
1630 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1631 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1633 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1635 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1636 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1637 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1638 set_reg_offset (reg
, frame_addr
+ offset
);
1640 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1642 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1643 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1644 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1645 set_reg_offset (reg
, frame_addr
+ offset
);
1647 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1648 entry_inst
= inst
; /* save for later processing */
1649 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1650 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1653 /* The entry instruction is typically the first instruction in a function,
1654 and it stores registers at offsets relative to the value of the old SP
1655 (before the prologue). But the value of the sp parameter to this
1656 function is the new SP (after the prologue has been executed). So we
1657 can't calculate those offsets until we've seen the entire prologue,
1658 and can calculate what the old SP must have been. */
1659 if (entry_inst
!= 0)
1661 int areg_count
= (entry_inst
>> 8) & 7;
1662 int sreg_count
= (entry_inst
>> 6) & 3;
1664 /* The entry instruction always subtracts 32 from the SP. */
1665 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1667 /* Now we can calculate what the SP must have been at the
1668 start of the function prologue. */
1669 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1671 /* Check if a0-a3 were saved in the caller's argument save area. */
1672 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1674 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1675 set_reg_offset (reg
, sp
+ offset
);
1676 offset
+= MIPS_SAVED_REGSIZE
;
1679 /* Check if the ra register was pushed on the stack. */
1681 if (entry_inst
& 0x20)
1683 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1684 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1685 offset
-= MIPS_SAVED_REGSIZE
;
1688 /* Check if the s0 and s1 registers were pushed on the stack. */
1689 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1691 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1692 set_reg_offset (reg
, sp
+ offset
);
1693 offset
-= MIPS_SAVED_REGSIZE
;
1699 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1700 CORE_ADDR start_pc
, limit_pc
;
1701 struct frame_info
*next_frame
;
1705 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1707 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1708 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1709 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1710 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1712 unsigned long inst
, high_word
, low_word
;
1715 /* Fetch the instruction. */
1716 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1718 /* Save some code by pre-extracting some useful fields. */
1719 high_word
= (inst
>> 16) & 0xffff;
1720 low_word
= inst
& 0xffff;
1721 reg
= high_word
& 0x1f;
1723 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1724 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1725 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1727 if (low_word
& 0x8000) /* negative stack adjustment? */
1728 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1730 /* Exit loop if a positive stack adjustment is found, which
1731 usually means that the stack cleanup code in the function
1732 epilogue is reached. */
1735 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1737 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1738 set_reg_offset (reg
, sp
+ low_word
);
1740 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1742 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1743 but the register size used is only 32 bits. Make the address
1744 for the saved register point to the lower 32 bits. */
1745 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1746 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1748 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1750 /* Old gcc frame, r30 is virtual frame pointer. */
1751 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1752 frame_addr
= sp
+ low_word
;
1753 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1755 unsigned alloca_adjust
;
1756 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1757 frame_addr
= read_next_frame_reg (next_frame
, 30);
1758 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1759 if (alloca_adjust
> 0)
1761 /* FP > SP + frame_size. This may be because
1762 * of an alloca or somethings similar.
1763 * Fix sp to "pre-alloca" value, and try again.
1765 sp
+= alloca_adjust
;
1770 /* move $30,$sp. With different versions of gas this will be either
1771 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1772 Accept any one of these. */
1773 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1775 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1776 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1778 unsigned alloca_adjust
;
1779 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1780 frame_addr
= read_next_frame_reg (next_frame
, 30);
1781 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1782 if (alloca_adjust
> 0)
1784 /* FP > SP + frame_size. This may be because
1785 * of an alloca or somethings similar.
1786 * Fix sp to "pre-alloca" value, and try again.
1788 sp
+= alloca_adjust
;
1793 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1795 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1796 set_reg_offset (reg
, frame_addr
+ low_word
);
1801 static mips_extra_func_info_t
1802 heuristic_proc_desc (start_pc
, limit_pc
, next_frame
)
1803 CORE_ADDR start_pc
, limit_pc
;
1804 struct frame_info
*next_frame
;
1806 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1810 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1811 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1812 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1813 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1814 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1816 if (start_pc
+ 200 < limit_pc
)
1817 limit_pc
= start_pc
+ 200;
1818 if (pc_is_mips16 (start_pc
))
1819 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1821 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1822 return &temp_proc_desc
;
1825 static mips_extra_func_info_t
1826 non_heuristic_proc_desc (pc
, addrptr
)
1830 CORE_ADDR startaddr
;
1831 mips_extra_func_info_t proc_desc
;
1832 struct block
*b
= block_for_pc (pc
);
1835 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1837 *addrptr
= startaddr
;
1838 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1842 if (startaddr
> BLOCK_START (b
))
1843 /* This is the "pathological" case referred to in a comment in
1844 print_frame_info. It might be better to move this check into
1848 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1851 /* If we never found a PDR for this function in symbol reading, then
1852 examine prologues to find the information. */
1855 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1856 if (PROC_FRAME_REG (proc_desc
) == -1)
1866 static mips_extra_func_info_t
1867 find_proc_desc (pc
, next_frame
)
1869 struct frame_info
*next_frame
;
1871 mips_extra_func_info_t proc_desc
;
1872 CORE_ADDR startaddr
;
1874 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1878 /* IF this is the topmost frame AND
1879 * (this proc does not have debugging information OR
1880 * the PC is in the procedure prologue)
1881 * THEN create a "heuristic" proc_desc (by analyzing
1882 * the actual code) to replace the "official" proc_desc.
1884 if (next_frame
== NULL
)
1886 struct symtab_and_line val
;
1887 struct symbol
*proc_symbol
=
1888 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1892 val
= find_pc_line (BLOCK_START
1893 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1895 val
.pc
= val
.end
? val
.end
: pc
;
1897 if (!proc_symbol
|| pc
< val
.pc
)
1899 mips_extra_func_info_t found_heuristic
=
1900 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1902 if (found_heuristic
)
1903 proc_desc
= found_heuristic
;
1909 /* Is linked_proc_desc_table really necessary? It only seems to be used
1910 by procedure call dummys. However, the procedures being called ought
1911 to have their own proc_descs, and even if they don't,
1912 heuristic_proc_desc knows how to create them! */
1914 register struct linked_proc_info
*link
;
1916 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1917 if (PROC_LOW_ADDR (&link
->info
) <= pc
1918 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1922 startaddr
= heuristic_proc_start (pc
);
1925 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1931 get_frame_pointer (frame
, proc_desc
)
1932 struct frame_info
*frame
;
1933 mips_extra_func_info_t proc_desc
;
1935 return ADDR_BITS_REMOVE (
1936 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1937 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1940 mips_extra_func_info_t cached_proc_desc
;
1943 mips_frame_chain (frame
)
1944 struct frame_info
*frame
;
1946 mips_extra_func_info_t proc_desc
;
1948 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
1950 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1953 /* Check if the PC is inside a call stub. If it is, fetch the
1954 PC of the caller of that stub. */
1955 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1958 /* Look up the procedure descriptor for this PC. */
1959 proc_desc
= find_proc_desc (saved_pc
, frame
);
1963 cached_proc_desc
= proc_desc
;
1965 /* If no frame pointer and frame size is zero, we must be at end
1966 of stack (or otherwise hosed). If we don't check frame size,
1967 we loop forever if we see a zero size frame. */
1968 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1969 && PROC_FRAME_OFFSET (proc_desc
) == 0
1970 /* The previous frame from a sigtramp frame might be frameless
1971 and have frame size zero. */
1972 && !frame
->signal_handler_caller
)
1975 return get_frame_pointer (frame
, proc_desc
);
1979 mips_init_extra_frame_info (fromleaf
, fci
)
1981 struct frame_info
*fci
;
1985 /* Use proc_desc calculated in frame_chain */
1986 mips_extra_func_info_t proc_desc
=
1987 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
1989 fci
->extra_info
= (struct frame_extra_info
*)
1990 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1992 fci
->saved_regs
= NULL
;
1993 fci
->extra_info
->proc_desc
=
1994 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1997 /* Fixup frame-pointer - only needed for top frame */
1998 /* This may not be quite right, if proc has a real frame register.
1999 Get the value of the frame relative sp, procedure might have been
2000 interrupted by a signal at it's very start. */
2001 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2002 && !PROC_DESC_IS_DUMMY (proc_desc
))
2003 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2005 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2007 if (proc_desc
== &temp_proc_desc
)
2011 /* Do not set the saved registers for a sigtramp frame,
2012 mips_find_saved_registers will do that for us.
2013 We can't use fci->signal_handler_caller, it is not yet set. */
2014 find_pc_partial_function (fci
->pc
, &name
,
2015 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2016 if (!IN_SIGTRAMP (fci
->pc
, name
))
2018 frame_saved_regs_zalloc (fci
);
2019 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2020 fci
->saved_regs
[PC_REGNUM
]
2021 = fci
->saved_regs
[RA_REGNUM
];
2025 /* hack: if argument regs are saved, guess these contain args */
2026 /* assume we can't tell how many args for now */
2027 fci
->extra_info
->num_args
= -1;
2028 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2030 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2032 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2039 /* MIPS stack frames are almost impenetrable. When execution stops,
2040 we basically have to look at symbol information for the function
2041 that we stopped in, which tells us *which* register (if any) is
2042 the base of the frame pointer, and what offset from that register
2043 the frame itself is at.
2045 This presents a problem when trying to examine a stack in memory
2046 (that isn't executing at the moment), using the "frame" command. We
2047 don't have a PC, nor do we have any registers except SP.
2049 This routine takes two arguments, SP and PC, and tries to make the
2050 cached frames look as if these two arguments defined a frame on the
2051 cache. This allows the rest of info frame to extract the important
2052 arguments without difficulty. */
2055 setup_arbitrary_frame (argc
, argv
)
2060 error ("MIPS frame specifications require two arguments: sp and pc");
2062 return create_new_frame (argv
[0], argv
[1]);
2065 /* According to the current ABI, should the type be passed in a
2066 floating-point register (assuming that there is space)? When there
2067 is no FPU, FP are not even considered as possibile candidates for
2068 FP registers and, consequently this returns false - forces FP
2069 arguments into integer registers. */
2072 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2074 return ((typecode
== TYPE_CODE_FLT
2076 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2077 && TYPE_NFIELDS (arg_type
) == 1
2078 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2079 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2083 mips_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
2088 CORE_ADDR struct_addr
;
2094 int stack_offset
= 0;
2096 /* Macros to round N up or down to the next A boundary; A must be
2098 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2099 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2101 /* First ensure that the stack and structure return address (if any)
2102 are properly aligned. The stack has to be at least 64-bit aligned
2103 even on 32-bit machines, because doubles must be 64-bit aligned.
2104 On at least one MIPS variant, stack frames need to be 128-bit
2105 aligned, so we round to this widest known alignment. */
2106 sp
= ROUND_DOWN (sp
, 16);
2107 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2109 /* Now make space on the stack for the args. We allocate more
2110 than necessary for EABI, because the first few arguments are
2111 passed in registers, but that's OK. */
2112 for (argnum
= 0; argnum
< nargs
; argnum
++)
2113 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_STACK_ARGSIZE
);
2114 sp
-= ROUND_UP (len
, 16);
2117 fprintf_unfiltered (gdb_stdlog
, "mips_push_arguments: sp=0x%lx allocated %d\n",
2118 (long) sp
, ROUND_UP (len
, 16));
2120 /* Initialize the integer and float register pointers. */
2122 float_argreg
= FPA0_REGNUM
;
2124 /* the struct_return pointer occupies the first parameter-passing reg */
2128 fprintf_unfiltered (gdb_stdlog
,
2129 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2130 argreg
, (long) struct_addr
);
2131 write_register (argreg
++, struct_addr
);
2132 if (MIPS_REGS_HAVE_HOME_P
)
2133 stack_offset
+= MIPS_STACK_ARGSIZE
;
2136 /* Now load as many as possible of the first arguments into
2137 registers, and push the rest onto the stack. Loop thru args
2138 from first to last. */
2139 for (argnum
= 0; argnum
< nargs
; argnum
++)
2142 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2143 value_ptr arg
= args
[argnum
];
2144 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2145 int len
= TYPE_LENGTH (arg_type
);
2146 enum type_code typecode
= TYPE_CODE (arg_type
);
2149 fprintf_unfiltered (gdb_stdlog
,
2150 "mips_push_arguments: %d len=%d type=%d",
2151 argnum
, len
, (int) typecode
);
2153 /* The EABI passes structures that do not fit in a register by
2154 reference. In all other cases, pass the structure by value. */
2156 && len
> MIPS_SAVED_REGSIZE
2157 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2159 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2160 typecode
= TYPE_CODE_PTR
;
2161 len
= MIPS_SAVED_REGSIZE
;
2164 fprintf_unfiltered (gdb_stdlog
, " push");
2167 val
= (char *) VALUE_CONTENTS (arg
);
2169 /* 32-bit ABIs always start floating point arguments in an
2170 even-numbered floating point register. */
2171 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
2172 && (float_argreg
& 1))
2175 /* Floating point arguments passed in registers have to be
2176 treated specially. On 32-bit architectures, doubles
2177 are passed in register pairs; the even register gets
2178 the low word, and the odd register gets the high word.
2179 On non-EABI processors, the first two floating point arguments are
2180 also copied to general registers, because MIPS16 functions
2181 don't use float registers for arguments. This duplication of
2182 arguments in general registers can't hurt non-MIPS16 functions
2183 because those registers are normally skipped. */
2184 /* MIPS_EABI squeeses a struct that contains a single floating
2185 point value into an FP register instead of pusing it onto the
2187 if (fp_register_arg_p (typecode
, arg_type
)
2188 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2190 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2192 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2193 unsigned long regval
;
2195 /* Write the low word of the double to the even register(s). */
2196 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2198 fprintf_unfiltered (gdb_stdlog
, " fpreg=%d val=%s",
2199 float_argreg
, phex (regval
, 4));
2200 write_register (float_argreg
++, regval
);
2204 fprintf_unfiltered (gdb_stdlog
, " reg=%d val=%s",
2205 argreg
, phex (regval
, 4));
2206 write_register (argreg
++, regval
);
2209 /* Write the high word of the double to the odd register(s). */
2210 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2212 fprintf_unfiltered (gdb_stdlog
, " fpreg=%d val=%s",
2213 float_argreg
, phex (regval
, 4));
2214 write_register (float_argreg
++, regval
);
2218 fprintf_unfiltered (gdb_stdlog
, " reg=%d val=%s",
2219 argreg
, phex (regval
, 4));
2220 write_register (argreg
++, regval
);
2226 /* This is a floating point value that fits entirely
2227 in a single register. */
2228 /* On 32 bit ABI's the float_argreg is further adjusted
2229 above to ensure that it is even register aligned. */
2230 LONGEST regval
= extract_unsigned_integer (val
, len
);
2232 fprintf_unfiltered (gdb_stdlog
, " fpreg=%d val=%s",
2233 float_argreg
, phex (regval
, len
));
2234 write_register (float_argreg
++, regval
);
2237 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2238 registers for each argument. The below is (my
2239 guess) to ensure that the corresponding integer
2240 register has reserved the same space. */
2242 fprintf_unfiltered (gdb_stdlog
, " reg=%d val=%s",
2243 argreg
, phex (regval
, len
));
2244 write_register (argreg
, regval
);
2245 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2248 /* Reserve space for the FP register. */
2249 if (MIPS_REGS_HAVE_HOME_P
)
2250 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
2254 /* Copy the argument to general registers or the stack in
2255 register-sized pieces. Large arguments are split between
2256 registers and stack. */
2257 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2258 are treated specially: Irix cc passes them in registers
2259 where gcc sometimes puts them on the stack. For maximum
2260 compatibility, we will put them in both places. */
2261 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2262 (len
% MIPS_SAVED_REGSIZE
!= 0));
2263 /* Note: Floating-point values that didn't fit into an FP
2264 register are only written to memory. */
2267 /* Rememer if the argument was written to the stack. */
2268 int stack_used_p
= 0;
2269 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2271 /* Write this portion of the argument to the stack. */
2272 if (argreg
> MIPS_LAST_ARG_REGNUM
2274 || fp_register_arg_p (typecode
, arg_type
))
2276 /* Should shorter than int integer values be
2277 promoted to int before being stored? */
2278 int longword_offset
= 0;
2281 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2283 if (MIPS_STACK_ARGSIZE
== 8 &&
2284 (typecode
== TYPE_CODE_INT
||
2285 typecode
== TYPE_CODE_PTR
||
2286 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2287 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2288 else if ((typecode
== TYPE_CODE_STRUCT
||
2289 typecode
== TYPE_CODE_UNION
) &&
2290 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2291 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2296 fprintf_unfiltered (gdb_stdlog
, " stack_offset=0x%lx",
2297 (long) stack_offset
);
2298 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%lx",
2299 (long) longword_offset
);
2302 addr
= sp
+ stack_offset
+ longword_offset
;
2307 fprintf_unfiltered (gdb_stdlog
, " @0x%lx ", (long) addr
);
2308 for (i
= 0; i
< partial_len
; i
++)
2310 fprintf_unfiltered (gdb_stdlog
, "%02x", val
[i
] & 0xff);
2313 write_memory (addr
, val
, partial_len
);
2316 /* Note!!! This is NOT an else clause. Odd sized
2317 structs may go thru BOTH paths. Floating point
2318 arguments will not. */
2319 /* Write this portion of the argument to a general
2320 purpose register. */
2321 if (argreg
<= MIPS_LAST_ARG_REGNUM
2322 && !fp_register_arg_p (typecode
, arg_type
))
2324 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2326 /* A non-floating-point argument being passed in a
2327 general register. If a struct or union, and if
2328 the remaining length is smaller than the register
2329 size, we have to adjust the register value on
2332 It does not seem to be necessary to do the
2333 same for integral types.
2335 Also don't do this adjustment on EABI and O64
2339 && MIPS_SAVED_REGSIZE
< 8
2340 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2341 && partial_len
< MIPS_SAVED_REGSIZE
2342 && (typecode
== TYPE_CODE_STRUCT
||
2343 typecode
== TYPE_CODE_UNION
))
2344 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2348 fprintf_filtered (gdb_stdlog
, " reg=%d val=%s",
2350 phex (regval
, MIPS_SAVED_REGSIZE
));
2351 write_register (argreg
, regval
);
2354 /* If this is the old ABI, prevent subsequent floating
2355 point arguments from being passed in floating point
2358 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2364 /* Compute the the offset into the stack at which we
2365 will copy the next parameter.
2367 In older ABIs, the caller reserved space for
2368 registers that contained arguments. This was loosely
2369 refered to as their "home". Consequently, space is
2372 In the new EABI (and the NABI32), the stack_offset
2373 only needs to be adjusted when it has been used.. */
2375 if (MIPS_REGS_HAVE_HOME_P
|| stack_used_p
)
2376 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2380 fprintf_unfiltered (gdb_stdlog
, "\n");
2383 /* Return adjusted stack pointer. */
2388 mips_push_return_address (pc
, sp
)
2392 /* Set the return address register to point to the entry
2393 point of the program, where a breakpoint lies in wait. */
2394 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2399 mips_push_register (CORE_ADDR
* sp
, int regno
)
2401 char buffer
[MAX_REGISTER_RAW_SIZE
];
2404 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2406 regsize
= MIPS_SAVED_REGSIZE
;
2407 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2408 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2413 regsize
= REGISTER_RAW_SIZE (regno
);
2417 read_register_gen (regno
, buffer
);
2418 write_memory (*sp
, buffer
+ offset
, regsize
);
2421 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2422 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2425 mips_push_dummy_frame ()
2428 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2429 xmalloc (sizeof (struct linked_proc_info
));
2430 mips_extra_func_info_t proc_desc
= &link
->info
;
2431 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2432 CORE_ADDR old_sp
= sp
;
2433 link
->next
= linked_proc_desc_table
;
2434 linked_proc_desc_table
= link
;
2436 /* FIXME! are these correct ? */
2437 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2438 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2439 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2440 #define FLOAT_SINGLE_REG_SAVE_MASK \
2441 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2443 * The registers we must save are all those not preserved across
2444 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2445 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2446 * and FP Control/Status registers.
2449 * Dummy frame layout:
2452 * Saved MMHI, MMLO, FPC_CSR
2457 * Saved D18 (i.e. F19, F18)
2459 * Saved D0 (i.e. F1, F0)
2460 * Argument build area and stack arguments written via mips_push_arguments
2464 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2465 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2466 PROC_FRAME_OFFSET (proc_desc
) = 0;
2467 PROC_FRAME_ADJUST (proc_desc
) = 0;
2468 mips_push_register (&sp
, PC_REGNUM
);
2469 mips_push_register (&sp
, HI_REGNUM
);
2470 mips_push_register (&sp
, LO_REGNUM
);
2471 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2473 /* Save general CPU registers */
2474 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2475 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2476 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2477 for (ireg
= 32; --ireg
>= 0;)
2478 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2479 mips_push_register (&sp
, ireg
);
2481 /* Save floating point registers starting with high order word */
2482 PROC_FREG_MASK (proc_desc
) =
2483 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2484 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2485 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2487 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2488 for (ireg
= 32; --ireg
>= 0;)
2489 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2490 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2492 /* Update the frame pointer for the call dummy and the stack pointer.
2493 Set the procedure's starting and ending addresses to point to the
2494 call dummy address at the entry point. */
2495 write_register (PUSH_FP_REGNUM
, old_sp
);
2496 write_register (SP_REGNUM
, sp
);
2497 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2498 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2499 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2500 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2506 register int regnum
;
2507 struct frame_info
*frame
= get_current_frame ();
2508 CORE_ADDR new_sp
= FRAME_FP (frame
);
2510 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2512 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2513 if (frame
->saved_regs
== NULL
)
2514 mips_find_saved_regs (frame
);
2515 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2517 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2518 && frame
->saved_regs
[regnum
])
2519 write_register (regnum
,
2520 read_memory_integer (frame
->saved_regs
[regnum
],
2521 MIPS_SAVED_REGSIZE
));
2523 write_register (SP_REGNUM
, new_sp
);
2524 flush_cached_frames ();
2526 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2528 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2530 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2532 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2534 if (&pi_ptr
->info
== proc_desc
)
2539 error ("Can't locate dummy extra frame info\n");
2541 if (prev_ptr
!= NULL
)
2542 prev_ptr
->next
= pi_ptr
->next
;
2544 linked_proc_desc_table
= pi_ptr
->next
;
2548 write_register (HI_REGNUM
,
2549 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2550 MIPS_SAVED_REGSIZE
));
2551 write_register (LO_REGNUM
,
2552 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2553 MIPS_SAVED_REGSIZE
));
2554 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2555 write_register (FCRCS_REGNUM
,
2556 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2557 MIPS_SAVED_REGSIZE
));
2562 mips_print_register (regnum
, all
)
2565 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2567 /* Get the data in raw format. */
2568 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2570 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2574 /* If an even floating point register, also print as double. */
2575 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2576 && !((regnum
- FP0_REGNUM
) & 1))
2577 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2579 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2581 read_relative_register_raw_bytes (regnum
, dbuffer
);
2582 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2583 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2585 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2586 val_print (builtin_type_double
, dbuffer
, 0, 0,
2587 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2588 printf_filtered ("); ");
2590 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2592 /* The problem with printing numeric register names (r26, etc.) is that
2593 the user can't use them on input. Probably the best solution is to
2594 fix it so that either the numeric or the funky (a2, etc.) names
2595 are accepted on input. */
2596 if (regnum
< MIPS_NUMREGS
)
2597 printf_filtered ("(r%d): ", regnum
);
2599 printf_filtered (": ");
2601 /* If virtual format is floating, print it that way. */
2602 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2603 if (FP_REGISTER_DOUBLE
)
2604 { /* show 8-byte floats as float AND double: */
2605 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2607 printf_filtered (" (float) ");
2608 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2609 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2610 printf_filtered (", (double) ");
2611 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2612 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2615 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2616 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2617 /* Else print as integer in hex. */
2622 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2623 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2627 print_scalar_formatted (raw_buffer
+ offset
,
2628 REGISTER_VIRTUAL_TYPE (regnum
),
2629 'x', 0, gdb_stdout
);
2633 /* Replacement for generic do_registers_info.
2634 Print regs in pretty columns. */
2637 do_fp_register_row (regnum
)
2639 { /* do values for FP (float) regs */
2640 char *raw_buffer
[2];
2642 /* use HI and LO to control the order of combining two flt regs */
2643 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2644 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2645 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2646 int inv1
, inv2
, inv3
;
2648 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2649 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2650 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2652 /* Get the data in raw format. */
2653 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2654 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2655 if (REGISTER_RAW_SIZE (regnum
) == 4)
2657 /* 4-byte registers: we can fit two registers per row. */
2658 /* Also print every pair of 4-byte regs as an 8-byte double. */
2659 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2660 error ("can't read register %d (%s)",
2661 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2663 /* copy the two floats into one double, and unpack both */
2664 memcpy (dbl_buffer
, raw_buffer
, 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2665 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2666 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2667 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2669 printf_filtered (inv1
? " %-5s: <invalid float>" :
2670 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2671 printf_filtered (inv2
? " %-5s: <invalid float>" :
2672 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2673 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2674 " dbl: %-24.17g\n", doub
);
2675 /* may want to do hex display here (future enhancement) */
2679 { /* eight byte registers: print each one as float AND as double. */
2680 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2682 memcpy (dbl_buffer
, raw_buffer
[HI
], 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2683 flt1
= unpack_double (builtin_type_float
,
2684 &raw_buffer
[HI
][offset
], &inv1
);
2685 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2687 printf_filtered (inv1
? " %-5s: <invalid float>" :
2688 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2689 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2690 " dbl: %-24.17g\n", doub
);
2691 /* may want to do hex display here (future enhancement) */
2697 /* Print a row's worth of GP (int) registers, with name labels above */
2700 do_gp_register_row (regnum
)
2703 /* do values for GP (int) regs */
2704 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2705 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2707 int start_regnum
= regnum
;
2708 int numregs
= NUM_REGS
;
2711 /* For GP registers, we print a separate row of names above the vals */
2712 printf_filtered (" ");
2713 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2715 if (*REGISTER_NAME (regnum
) == '\0')
2716 continue; /* unused register */
2717 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2718 break; /* end the row: reached FP register */
2719 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2720 REGISTER_NAME (regnum
));
2723 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2724 start_regnum
); /* print the R0 to R31 names */
2726 regnum
= start_regnum
; /* go back to start of row */
2727 /* now print the values in hex, 4 or 8 to the row */
2728 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2730 if (*REGISTER_NAME (regnum
) == '\0')
2731 continue; /* unused register */
2732 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2733 break; /* end row: reached FP register */
2734 /* OK: get the data in raw format. */
2735 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2736 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2737 /* pad small registers */
2738 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
2739 printf_filtered (" ");
2740 /* Now print the register value in hex, endian order. */
2741 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2742 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2743 byte
< REGISTER_RAW_SIZE (regnum
);
2745 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2747 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
2750 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2751 printf_filtered (" ");
2754 if (col
> 0) /* ie. if we actually printed anything... */
2755 printf_filtered ("\n");
2760 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2763 mips_do_registers_info (regnum
, fpregs
)
2767 if (regnum
!= -1) /* do one specified register */
2769 if (*(REGISTER_NAME (regnum
)) == '\0')
2770 error ("Not a valid register for the current processor type");
2772 mips_print_register (regnum
, 0);
2773 printf_filtered ("\n");
2776 /* do all (or most) registers */
2779 while (regnum
< NUM_REGS
)
2781 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2782 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2783 regnum
= do_fp_register_row (regnum
); /* FP regs */
2785 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2787 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2792 /* Return number of args passed to a frame. described by FIP.
2793 Can return -1, meaning no way to tell. */
2796 mips_frame_num_args (frame
)
2797 struct frame_info
*frame
;
2799 #if 0 /* FIXME Use or lose this! */
2800 struct chain_info_t
*p
;
2802 p
= mips_find_cached_frame (FRAME_FP (frame
));
2804 return p
->the_info
.numargs
;
2809 /* Is this a branch with a delay slot? */
2811 static int is_delayed (unsigned long);
2818 for (i
= 0; i
< NUMOPCODES
; ++i
)
2819 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2820 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2822 return (i
< NUMOPCODES
2823 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2824 | INSN_COND_BRANCH_DELAY
2825 | INSN_COND_BRANCH_LIKELY
)));
2829 mips_step_skips_delay (pc
)
2832 char buf
[MIPS_INSTLEN
];
2834 /* There is no branch delay slot on MIPS16. */
2835 if (pc_is_mips16 (pc
))
2838 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2839 /* If error reading memory, guess that it is not a delayed branch. */
2841 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2845 /* Skip the PC past function prologue instructions (32-bit version).
2846 This is a helper function for mips_skip_prologue. */
2849 mips32_skip_prologue (CORE_ADDR pc
)
2853 int seen_sp_adjust
= 0;
2854 int load_immediate_bytes
= 0;
2856 /* Skip the typical prologue instructions. These are the stack adjustment
2857 instruction and the instructions that save registers on the stack
2858 or in the gcc frame. */
2859 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2861 unsigned long high_word
;
2863 inst
= mips_fetch_instruction (pc
);
2864 high_word
= (inst
>> 16) & 0xffff;
2867 if (lenient
&& is_delayed (inst
))
2871 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2872 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2874 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2875 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2877 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2878 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2879 && (inst
& 0x001F0000)) /* reg != $zero */
2882 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2884 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2886 continue; /* reg != $zero */
2888 /* move $s8,$sp. With different versions of gas this will be either
2889 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2890 Accept any one of these. */
2891 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2894 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2896 else if (high_word
== 0x3c1c) /* lui $gp,n */
2898 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2900 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2901 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2903 /* The following instructions load $at or $t0 with an immediate
2904 value in preparation for a stack adjustment via
2905 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2906 a local variable, so we accept them only before a stack adjustment
2907 instruction was seen. */
2908 else if (!seen_sp_adjust
)
2910 if (high_word
== 0x3c01 || /* lui $at,n */
2911 high_word
== 0x3c08) /* lui $t0,n */
2913 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2916 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2917 high_word
== 0x3508 || /* ori $t0,$t0,n */
2918 high_word
== 0x3401 || /* ori $at,$zero,n */
2919 high_word
== 0x3408) /* ori $t0,$zero,n */
2921 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2931 /* In a frameless function, we might have incorrectly
2932 skipped some load immediate instructions. Undo the skipping
2933 if the load immediate was not followed by a stack adjustment. */
2934 if (load_immediate_bytes
&& !seen_sp_adjust
)
2935 pc
-= load_immediate_bytes
;
2939 /* Skip the PC past function prologue instructions (16-bit version).
2940 This is a helper function for mips_skip_prologue. */
2943 mips16_skip_prologue (CORE_ADDR pc
)
2946 int extend_bytes
= 0;
2947 int prev_extend_bytes
;
2949 /* Table of instructions likely to be found in a function prologue. */
2952 unsigned short inst
;
2953 unsigned short mask
;
2960 , /* addiu $sp,offset */
2964 , /* daddiu $sp,offset */
2968 , /* sw reg,n($sp) */
2972 , /* sd reg,n($sp) */
2976 , /* sw $ra,n($sp) */
2980 , /* sd $ra,n($sp) */
2988 , /* sw $a0-$a3,n($s1) */
2992 , /* move reg,$a0-$a3 */
2996 , /* entry pseudo-op */
3000 , /* addiu $s1,$sp,n */
3003 } /* end of table marker */
3006 /* Skip the typical prologue instructions. These are the stack adjustment
3007 instruction and the instructions that save registers on the stack
3008 or in the gcc frame. */
3009 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
3011 unsigned short inst
;
3014 inst
= mips_fetch_instruction (pc
);
3016 /* Normally we ignore an extend instruction. However, if it is
3017 not followed by a valid prologue instruction, we must adjust
3018 the pc back over the extend so that it won't be considered
3019 part of the prologue. */
3020 if ((inst
& 0xf800) == 0xf000) /* extend */
3022 extend_bytes
= MIPS16_INSTLEN
;
3025 prev_extend_bytes
= extend_bytes
;
3028 /* Check for other valid prologue instructions besides extend. */
3029 for (i
= 0; table
[i
].mask
!= 0; i
++)
3030 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
3032 if (table
[i
].mask
!= 0) /* it was in table? */
3033 continue; /* ignore it */
3037 /* Return the current pc, adjusted backwards by 2 if
3038 the previous instruction was an extend. */
3039 return pc
- prev_extend_bytes
;
3045 /* To skip prologues, I use this predicate. Returns either PC itself
3046 if the code at PC does not look like a function prologue; otherwise
3047 returns an address that (if we're lucky) follows the prologue. If
3048 LENIENT, then we must skip everything which is involved in setting
3049 up the frame (it's OK to skip more, just so long as we don't skip
3050 anything which might clobber the registers which are being saved.
3051 We must skip more in the case where part of the prologue is in the
3052 delay slot of a non-prologue instruction). */
3055 mips_skip_prologue (CORE_ADDR pc
)
3057 /* See if we can determine the end of the prologue via the symbol table.
3058 If so, then return either PC, or the PC after the prologue, whichever
3061 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
3063 if (post_prologue_pc
!= 0)
3064 return max (pc
, post_prologue_pc
);
3066 /* Can't determine prologue from the symbol table, need to examine
3069 if (pc_is_mips16 (pc
))
3070 return mips16_skip_prologue (pc
);
3072 return mips32_skip_prologue (pc
);
3075 /* Determine how a return value is stored within the MIPS register
3076 file, given the return type `valtype'. */
3078 struct return_value_word
3086 static void return_value_location (struct type
*, struct return_value_word
*,
3087 struct return_value_word
*);
3090 return_value_location (valtype
, hi
, lo
)
3091 struct type
*valtype
;
3092 struct return_value_word
*hi
;
3093 struct return_value_word
*lo
;
3095 int len
= TYPE_LENGTH (valtype
);
3097 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3098 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3099 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3101 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3103 /* We need to break a 64bit float in two 32 bit halves and
3104 spread them across a floating-point register pair. */
3105 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
3106 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
3107 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3108 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3110 hi
->reg_offset
= lo
->reg_offset
;
3111 lo
->reg
= FP0_REGNUM
+ 0;
3112 hi
->reg
= FP0_REGNUM
+ 1;
3118 /* The floating point value fits in a single floating-point
3120 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3121 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3124 lo
->reg
= FP0_REGNUM
;
3135 /* Locate a result possibly spread across two registers. */
3137 lo
->reg
= regnum
+ 0;
3138 hi
->reg
= regnum
+ 1;
3139 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3140 && len
< MIPS_SAVED_REGSIZE
)
3142 /* "un-left-justify" the value in the low register */
3143 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3148 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3149 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3150 && len
< MIPS_SAVED_REGSIZE
* 2
3151 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3152 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3154 /* "un-left-justify" the value spread across two registers. */
3155 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3156 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3158 hi
->len
= len
- lo
->len
;
3162 /* Only perform a partial copy of the second register. */
3165 if (len
> MIPS_SAVED_REGSIZE
)
3167 lo
->len
= MIPS_SAVED_REGSIZE
;
3168 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3176 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3177 && REGISTER_RAW_SIZE (regnum
) == 8
3178 && MIPS_SAVED_REGSIZE
== 4)
3180 /* Account for the fact that only the least-signficant part
3181 of the register is being used */
3182 lo
->reg_offset
+= 4;
3183 hi
->reg_offset
+= 4;
3186 hi
->buf_offset
= lo
->len
;
3190 /* Given a return value in `regbuf' with a type `valtype', extract and
3191 copy its value into `valbuf'. */
3194 mips_extract_return_value (valtype
, regbuf
, valbuf
)
3195 struct type
*valtype
;
3196 char regbuf
[REGISTER_BYTES
];
3199 struct return_value_word lo
;
3200 struct return_value_word hi
;
3201 return_value_location (valtype
, &lo
, &hi
);
3203 memcpy (valbuf
+ lo
.buf_offset
,
3204 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3208 memcpy (valbuf
+ hi
.buf_offset
,
3209 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3215 int len
= TYPE_LENGTH (valtype
);
3218 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3219 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3220 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3221 && len
<= MIPS_FPU_SINGLE_REGSIZE
)))
3222 regnum
= FP0_REGNUM
;
3224 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3225 { /* "un-left-justify" the value from the register */
3226 if (len
< REGISTER_RAW_SIZE (regnum
))
3227 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3228 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3229 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3230 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3231 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3232 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3234 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
3235 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
3239 /* Given a return value in `valbuf' with a type `valtype', write it's
3240 value into the appropriate register. */
3243 mips_store_return_value (valtype
, valbuf
)
3244 struct type
*valtype
;
3247 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3248 struct return_value_word lo
;
3249 struct return_value_word hi
;
3250 return_value_location (valtype
, &lo
, &hi
);
3252 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3253 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3254 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3256 REGISTER_RAW_SIZE (lo
.reg
));
3260 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3261 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3262 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3264 REGISTER_RAW_SIZE (hi
.reg
));
3270 int len
= TYPE_LENGTH (valtype
);
3271 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3274 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3275 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3276 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3277 && len
<= MIPS_REGSIZE
)))
3278 regnum
= FP0_REGNUM
;
3280 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3281 { /* "left-justify" the value in the register */
3282 if (len
< REGISTER_RAW_SIZE (regnum
))
3283 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3284 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3285 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3286 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3287 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3288 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3290 memcpy (raw_buffer
+ offset
, valbuf
, len
);
3291 REGISTER_CONVERT_FROM_TYPE (regnum
, valtype
, raw_buffer
);
3292 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
,
3293 len
> REGISTER_RAW_SIZE (regnum
) ?
3294 len
: REGISTER_RAW_SIZE (regnum
));
3298 /* Exported procedure: Is PC in the signal trampoline code */
3301 in_sigtramp (pc
, ignore
)
3303 char *ignore
; /* function name */
3305 if (sigtramp_address
== 0)
3307 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3310 /* Root of all "set mips "/"show mips " commands. This will eventually be
3311 used for all MIPS-specific commands. */
3313 static void show_mips_command (char *, int);
3315 show_mips_command (args
, from_tty
)
3319 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3322 static void set_mips_command (char *, int);
3324 set_mips_command (args
, from_tty
)
3328 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3329 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3332 /* Commands to show/set the MIPS FPU type. */
3334 static void show_mipsfpu_command (char *, int);
3336 show_mipsfpu_command (args
, from_tty
)
3342 switch (MIPS_FPU_TYPE
)
3344 case MIPS_FPU_SINGLE
:
3345 fpu
= "single-precision";
3347 case MIPS_FPU_DOUBLE
:
3348 fpu
= "double-precision";
3351 fpu
= "absent (none)";
3354 if (mips_fpu_type_auto
)
3355 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3358 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3363 static void set_mipsfpu_command (char *, int);
3365 set_mipsfpu_command (args
, from_tty
)
3369 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3370 show_mipsfpu_command (args
, from_tty
);
3373 static void set_mipsfpu_single_command (char *, int);
3375 set_mipsfpu_single_command (args
, from_tty
)
3379 mips_fpu_type
= MIPS_FPU_SINGLE
;
3380 mips_fpu_type_auto
= 0;
3383 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3387 static void set_mipsfpu_double_command (char *, int);
3389 set_mipsfpu_double_command (args
, from_tty
)
3393 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3394 mips_fpu_type_auto
= 0;
3397 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3401 static void set_mipsfpu_none_command (char *, int);
3403 set_mipsfpu_none_command (args
, from_tty
)
3407 mips_fpu_type
= MIPS_FPU_NONE
;
3408 mips_fpu_type_auto
= 0;
3411 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3415 static void set_mipsfpu_auto_command (char *, int);
3417 set_mipsfpu_auto_command (args
, from_tty
)
3421 mips_fpu_type_auto
= 1;
3424 /* Command to set the processor type. */
3427 mips_set_processor_type_command (args
, from_tty
)
3433 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3435 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3436 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3437 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3439 /* Restore the value. */
3440 tmp_mips_processor_type
= strsave (mips_processor_type
);
3445 if (!mips_set_processor_type (tmp_mips_processor_type
))
3447 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3448 /* Restore its value. */
3449 tmp_mips_processor_type
= strsave (mips_processor_type
);
3454 mips_show_processor_type_command (args
, from_tty
)
3460 /* Modify the actual processor type. */
3463 mips_set_processor_type (str
)
3471 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3473 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3475 mips_processor_type
= str
;
3476 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3478 /* FIXME tweak fpu flag too */
3485 /* Attempt to identify the particular processor model by reading the
3489 mips_read_processor_type ()
3493 prid
= read_register (PRID_REGNUM
);
3495 if ((prid
& ~0xf) == 0x700)
3496 return savestring ("r3041", strlen ("r3041"));
3501 /* Just like reinit_frame_cache, but with the right arguments to be
3502 callable as an sfunc. */
3505 reinit_frame_cache_sfunc (args
, from_tty
, c
)
3508 struct cmd_list_element
*c
;
3510 reinit_frame_cache ();
3514 gdb_print_insn_mips (memaddr
, info
)
3516 disassemble_info
*info
;
3518 mips_extra_func_info_t proc_desc
;
3520 /* Search for the function containing this address. Set the low bit
3521 of the address when searching, in case we were given an even address
3522 that is the start of a 16-bit function. If we didn't do this,
3523 the search would fail because the symbol table says the function
3524 starts at an odd address, i.e. 1 byte past the given address. */
3525 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3526 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3528 /* Make an attempt to determine if this is a 16-bit function. If
3529 the procedure descriptor exists and the address therein is odd,
3530 it's definitely a 16-bit function. Otherwise, we have to just
3531 guess that if the address passed in is odd, it's 16-bits. */
3533 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
3534 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3536 info
->mach
= pc_is_mips16 (memaddr
) ?
3537 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3539 /* Round down the instruction address to the appropriate boundary. */
3540 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
3542 /* Call the appropriate disassembler based on the target endian-ness. */
3543 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3544 return print_insn_big_mips (memaddr
, info
);
3546 return print_insn_little_mips (memaddr
, info
);
3549 /* Old-style breakpoint macros.
3550 The IDT board uses an unusual breakpoint value, and sometimes gets
3551 confused when it sees the usual MIPS breakpoint instruction. */
3553 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3554 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3555 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3556 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3557 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3558 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3559 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3560 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3562 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3563 counter value to determine whether a 16- or 32-bit breakpoint should be
3564 used. It returns a pointer to a string of bytes that encode a breakpoint
3565 instruction, stores the length of the string to *lenptr, and adjusts pc
3566 (if necessary) to point to the actual memory location where the
3567 breakpoint should be inserted. */
3570 mips_breakpoint_from_pc (pcptr
, lenptr
)
3574 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3576 if (pc_is_mips16 (*pcptr
))
3578 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3579 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3580 *lenptr
= sizeof (mips16_big_breakpoint
);
3581 return mips16_big_breakpoint
;
3585 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3586 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3587 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3589 *lenptr
= sizeof (big_breakpoint
);
3591 if (strcmp (target_shortname
, "mips") == 0)
3592 return idt_big_breakpoint
;
3593 else if (strcmp (target_shortname
, "ddb") == 0
3594 || strcmp (target_shortname
, "pmon") == 0
3595 || strcmp (target_shortname
, "lsi") == 0)
3596 return pmon_big_breakpoint
;
3598 return big_breakpoint
;
3603 if (pc_is_mips16 (*pcptr
))
3605 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3606 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3607 *lenptr
= sizeof (mips16_little_breakpoint
);
3608 return mips16_little_breakpoint
;
3612 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3613 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3614 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3616 *lenptr
= sizeof (little_breakpoint
);
3618 if (strcmp (target_shortname
, "mips") == 0)
3619 return idt_little_breakpoint
;
3620 else if (strcmp (target_shortname
, "ddb") == 0
3621 || strcmp (target_shortname
, "pmon") == 0
3622 || strcmp (target_shortname
, "lsi") == 0)
3623 return pmon_little_breakpoint
;
3625 return little_breakpoint
;
3630 /* If PC is in a mips16 call or return stub, return the address of the target
3631 PC, which is either the callee or the caller. There are several
3632 cases which must be handled:
3634 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3635 target PC is in $31 ($ra).
3636 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3637 and the target PC is in $2.
3638 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3639 before the jal instruction, this is effectively a call stub
3640 and the the target PC is in $2. Otherwise this is effectively
3641 a return stub and the target PC is in $18.
3643 See the source code for the stubs in gcc/config/mips/mips16.S for
3646 This function implements the SKIP_TRAMPOLINE_CODE macro.
3654 CORE_ADDR start_addr
;
3656 /* Find the starting address and name of the function containing the PC. */
3657 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3660 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3661 target PC is in $31 ($ra). */
3662 if (strcmp (name
, "__mips16_ret_sf") == 0
3663 || strcmp (name
, "__mips16_ret_df") == 0)
3664 return read_register (RA_REGNUM
);
3666 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3668 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3669 and the target PC is in $2. */
3670 if (name
[19] >= '0' && name
[19] <= '9')
3671 return read_register (2);
3673 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3674 before the jal instruction, this is effectively a call stub
3675 and the the target PC is in $2. Otherwise this is effectively
3676 a return stub and the target PC is in $18. */
3677 else if (name
[19] == 's' || name
[19] == 'd')
3679 if (pc
== start_addr
)
3681 /* Check if the target of the stub is a compiler-generated
3682 stub. Such a stub for a function bar might have a name
3683 like __fn_stub_bar, and might look like this:
3688 la $1,bar (becomes a lui/addiu pair)
3690 So scan down to the lui/addi and extract the target
3691 address from those two instructions. */
3693 CORE_ADDR target_pc
= read_register (2);
3697 /* See if the name of the target function is __fn_stub_*. */
3698 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3700 if (strncmp (name
, "__fn_stub_", 10) != 0
3701 && strcmp (name
, "etext") != 0
3702 && strcmp (name
, "_etext") != 0)
3705 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3706 The limit on the search is arbitrarily set to 20
3707 instructions. FIXME. */
3708 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3710 inst
= mips_fetch_instruction (target_pc
);
3711 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3712 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3713 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3714 return pc
| (inst
& 0xffff); /* low word */
3717 /* Couldn't find the lui/addui pair, so return stub address. */
3721 /* This is the 'return' part of a call stub. The return
3722 address is in $r18. */
3723 return read_register (18);
3726 return 0; /* not a stub */
3730 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3731 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3734 mips_in_call_stub (pc
, name
)
3738 CORE_ADDR start_addr
;
3740 /* Find the starting address of the function containing the PC. If the
3741 caller didn't give us a name, look it up at the same time. */
3742 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3745 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3747 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3748 if (name
[19] >= '0' && name
[19] <= '9')
3750 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3751 before the jal instruction, this is effectively a call stub. */
3752 else if (name
[19] == 's' || name
[19] == 'd')
3753 return pc
== start_addr
;
3756 return 0; /* not a stub */
3760 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3761 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3764 mips_in_return_stub (pc
, name
)
3768 CORE_ADDR start_addr
;
3770 /* Find the starting address of the function containing the PC. */
3771 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3774 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3775 if (strcmp (name
, "__mips16_ret_sf") == 0
3776 || strcmp (name
, "__mips16_ret_df") == 0)
3779 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3780 i.e. after the jal instruction, this is effectively a return stub. */
3781 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3782 && (name
[19] == 's' || name
[19] == 'd')
3783 && pc
!= start_addr
)
3786 return 0; /* not a stub */
3790 /* Return non-zero if the PC is in a library helper function that should
3791 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3794 mips_ignore_helper (pc
)
3799 /* Find the starting address and name of the function containing the PC. */
3800 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3803 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3804 that we want to ignore. */
3805 return (strcmp (name
, "__mips16_ret_sf") == 0
3806 || strcmp (name
, "__mips16_ret_df") == 0);
3810 /* Return a location where we can set a breakpoint that will be hit
3811 when an inferior function call returns. This is normally the
3812 program's entry point. Executables that don't have an entry
3813 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3814 whose address is the location where the breakpoint should be placed. */
3817 mips_call_dummy_address ()
3819 struct minimal_symbol
*sym
;
3821 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3823 return SYMBOL_VALUE_ADDRESS (sym
);
3825 return entry_point_address ();
3829 /* If the current gcc for for this target does not produce correct debugging
3830 information for float parameters, both prototyped and unprototyped, then
3831 define this macro. This forces gdb to always assume that floats are
3832 passed as doubles and then converted in the callee.
3834 For the mips chip, it appears that the debug info marks the parameters as
3835 floats regardless of whether the function is prototyped, but the actual
3836 values are passed as doubles for the non-prototyped case and floats for
3837 the prototyped case. Thus we choose to make the non-prototyped case work
3838 for C and break the prototyped case, since the non-prototyped case is
3839 probably much more common. (FIXME). */
3842 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
3844 return current_language
->la_language
== language_c
;
3847 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
3848 the register stored on the stack (32) is different to its real raw
3849 size (64). The below ensures that registers are fetched from the
3850 stack using their ABI size and then stored into the RAW_BUFFER
3851 using their raw size.
3853 The alternative to adding this function would be to add an ABI
3854 macro - REGISTER_STACK_SIZE(). */
3857 mips_get_saved_register (raw_buffer
, optimized
, addrp
, frame
, regnum
, lval
)
3861 struct frame_info
*frame
;
3863 enum lval_type
*lval
;
3867 if (!target_has_registers
)
3868 error ("No registers.");
3870 /* Normal systems don't optimize out things with register numbers. */
3871 if (optimized
!= NULL
)
3873 addr
= find_saved_register (frame
, regnum
);
3877 *lval
= lval_memory
;
3878 if (regnum
== SP_REGNUM
)
3880 if (raw_buffer
!= NULL
)
3882 /* Put it back in target format. */
3883 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
3890 if (raw_buffer
!= NULL
)
3894 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
3896 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
3898 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
3899 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
3905 *lval
= lval_register
;
3906 addr
= REGISTER_BYTE (regnum
);
3907 if (raw_buffer
!= NULL
)
3908 read_register_gen (regnum
, raw_buffer
);
3914 /* Immediately after a function call, return the saved pc.
3915 Can't always go through the frames for this because on some machines
3916 the new frame is not set up until the new function executes
3917 some instructions. */
3920 mips_saved_pc_after_call (struct frame_info
*frame
)
3923 return read_register (RA_REGNUM
);
3927 static gdbarch_init_ftype mips_gdbarch_init
;
3928 static struct gdbarch
*
3929 mips_gdbarch_init (info
, arches
)
3930 struct gdbarch_info info
;
3931 struct gdbarch_list
*arches
;
3933 static LONGEST mips_call_dummy_words
[] =
3935 struct gdbarch
*gdbarch
;
3936 struct gdbarch_tdep
*tdep
;
3939 int ef_mips_bitptrs
;
3944 enum mips_abi mips_abi
;
3946 /* Extract the elf_flags if available */
3947 if (info
.abfd
!= NULL
3948 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
3949 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3953 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
3954 switch ((elf_flags
& EF_MIPS_ABI
))
3956 case E_MIPS_ABI_O32
:
3957 mips_abi
= MIPS_ABI_O32
;
3959 case E_MIPS_ABI_O64
:
3960 mips_abi
= MIPS_ABI_O64
;
3962 case E_MIPS_ABI_EABI32
:
3963 mips_abi
= MIPS_ABI_EABI32
;
3965 case E_MIPS_ABI_EABI64
:
3966 mips_abi
= MIPS_ABI_EABI64
;
3969 mips_abi
= MIPS_ABI_UNKNOWN
;
3972 /* Try the architecture for any hint of the corect ABI */
3973 if (mips_abi
== MIPS_ABI_UNKNOWN
3974 && info
.bfd_arch_info
!= NULL
3975 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
3977 switch (info
.bfd_arch_info
->mach
)
3979 case bfd_mach_mips3900
:
3980 mips_abi
= MIPS_ABI_EABI32
;
3982 case bfd_mach_mips4100
:
3983 case bfd_mach_mips5000
:
3984 mips_abi
= MIPS_ABI_EABI64
;
3988 #ifdef MIPS_DEFAULT_ABI
3989 if (mips_abi
== MIPS_ABI_UNKNOWN
)
3990 mips_abi
= MIPS_DEFAULT_ABI
;
3995 fprintf_unfiltered (gdb_stdlog
,
3996 "mips_gdbarch_init: elf_flags = 0x%08x\n",
3999 fprintf_unfiltered (gdb_stdlog
,
4000 "mips_gdbarch_init: ef_mips_arch = %d\n",
4004 fprintf_unfiltered (gdb_stdlog
,
4005 "mips_gdbarch_init: ef_mips_bitptrs = %d\n",
4008 fprintf_unfiltered (gdb_stdlog
,
4009 "mips_gdbarch_init: mips_abi = %d\n",
4013 /* try to find a pre-existing architecture */
4014 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4016 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4018 /* MIPS needs to be pedantic about which ABI the object is
4020 if (gdbarch_tdep (current_gdbarch
)->elf_flags
!= elf_flags
)
4022 if (gdbarch_tdep (current_gdbarch
)->mips_abi
!= mips_abi
)
4024 return arches
->gdbarch
;
4027 /* Need a new architecture. Fill in a target specific vector. */
4028 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4029 gdbarch
= gdbarch_alloc (&info
, tdep
);
4030 tdep
->elf_flags
= elf_flags
;
4032 /* Initially set everything according to the ABI. */
4033 set_gdbarch_short_bit (gdbarch
, 16);
4034 set_gdbarch_int_bit (gdbarch
, 32);
4035 set_gdbarch_float_bit (gdbarch
, 32);
4036 set_gdbarch_double_bit (gdbarch
, 64);
4037 set_gdbarch_long_double_bit (gdbarch
, 64);
4038 tdep
->mips_abi
= mips_abi
;
4042 tdep
->mips_default_saved_regsize
= 4;
4043 tdep
->mips_default_stack_argsize
= 4;
4044 tdep
->mips_fp_register_double
= 0;
4045 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 7;
4046 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 15;
4047 tdep
->mips_regs_have_home_p
= 1;
4048 tdep
->gdb_target_is_mips64
= 0;
4049 set_gdbarch_long_bit (gdbarch
, 32);
4050 set_gdbarch_ptr_bit (gdbarch
, 32);
4051 set_gdbarch_long_long_bit (gdbarch
, 64);
4054 tdep
->mips_default_saved_regsize
= 8;
4055 tdep
->mips_default_stack_argsize
= 8;
4056 tdep
->mips_fp_register_double
= 1;
4057 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 7;
4058 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 15;
4059 tdep
->mips_regs_have_home_p
= 1;
4060 tdep
->gdb_target_is_mips64
= 1;
4061 set_gdbarch_long_bit (gdbarch
, 32);
4062 set_gdbarch_ptr_bit (gdbarch
, 32);
4063 set_gdbarch_long_long_bit (gdbarch
, 64);
4065 case MIPS_ABI_EABI32
:
4066 tdep
->mips_default_saved_regsize
= 4;
4067 tdep
->mips_default_stack_argsize
= 4;
4068 tdep
->mips_fp_register_double
= 0;
4069 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
4070 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
4071 tdep
->mips_regs_have_home_p
= 0;
4072 tdep
->gdb_target_is_mips64
= 0;
4073 set_gdbarch_long_bit (gdbarch
, 32);
4074 set_gdbarch_ptr_bit (gdbarch
, 32);
4075 set_gdbarch_long_long_bit (gdbarch
, 64);
4077 case MIPS_ABI_EABI64
:
4078 tdep
->mips_default_saved_regsize
= 8;
4079 tdep
->mips_default_stack_argsize
= 8;
4080 tdep
->mips_fp_register_double
= 1;
4081 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
4082 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
4083 tdep
->mips_regs_have_home_p
= 0;
4084 tdep
->gdb_target_is_mips64
= 1;
4085 set_gdbarch_long_bit (gdbarch
, 64);
4086 set_gdbarch_ptr_bit (gdbarch
, 64);
4087 set_gdbarch_long_long_bit (gdbarch
, 64);
4090 tdep
->mips_default_saved_regsize
= 4;
4091 tdep
->mips_default_stack_argsize
= 8;
4092 tdep
->mips_fp_register_double
= 1;
4093 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
4094 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
4095 tdep
->mips_regs_have_home_p
= 0;
4096 tdep
->gdb_target_is_mips64
= 0;
4097 set_gdbarch_long_bit (gdbarch
, 32);
4098 set_gdbarch_ptr_bit (gdbarch
, 32);
4099 set_gdbarch_long_long_bit (gdbarch
, 64);
4102 tdep
->mips_default_saved_regsize
= MIPS_REGSIZE
;
4103 tdep
->mips_default_stack_argsize
= MIPS_REGSIZE
;
4104 tdep
->mips_fp_register_double
= (REGISTER_VIRTUAL_SIZE (FP0_REGNUM
) == 8);
4105 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
4106 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
4107 tdep
->mips_regs_have_home_p
= 1;
4108 tdep
->gdb_target_is_mips64
= 0;
4109 set_gdbarch_long_bit (gdbarch
, 32);
4110 set_gdbarch_ptr_bit (gdbarch
, 32);
4111 set_gdbarch_long_long_bit (gdbarch
, 64);
4115 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4116 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4119 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4120 flag in object files because to do so would make it impossible to
4121 link with libraries compiled without "-gp32". This is
4122 unnecessarily restrictive.
4124 We could solve this problem by adding "-gp32" multilibs to gcc,
4125 but to set this flag before gcc is built with such multilibs will
4126 break too many systems.''
4128 But even more unhelpfully, the default linker output target for
4129 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4130 for 64-bit programs - you need to change the ABI to change this,
4131 and not all gcc targets support that currently. Therefore using
4132 this flag to detect 32-bit mode would do the wrong thing given
4133 the current gcc - it would make GDB treat these 64-bit programs
4134 as 32-bit programs by default. */
4137 /* determine the ISA */
4138 switch (elf_flags
& EF_MIPS_ARCH
)
4158 /* determine the size of a pointer */
4159 if ((elf_flags
& EF_MIPS_32BITPTRS
))
4161 ef_mips_bitptrs
= 32;
4163 else if ((elf_flags
& EF_MIPS_64BITPTRS
))
4165 ef_mips_bitptrs
= 64;
4169 ef_mips_bitptrs
= 0;
4173 /* enable/disable the MIPS FPU */
4174 if (!mips_fpu_type_auto
)
4175 tdep
->mips_fpu_type
= mips_fpu_type
;
4176 else if (info
.bfd_arch_info
!= NULL
4177 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4178 switch (info
.bfd_arch_info
->mach
)
4180 case bfd_mach_mips3900
:
4181 case bfd_mach_mips4100
:
4182 case bfd_mach_mips4111
:
4183 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
4185 case bfd_mach_mips4650
:
4186 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
4189 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4193 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4195 /* MIPS version of register names. NOTE: At present the MIPS
4196 register name management is part way between the old -
4197 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4198 Further work on it is required. */
4199 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4200 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
4201 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4202 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4203 set_gdbarch_write_fp (gdbarch
, generic_target_write_fp
);
4204 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4205 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4207 /* Initialize a frame */
4208 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
4210 /* MIPS version of CALL_DUMMY */
4212 set_gdbarch_call_dummy_p (gdbarch
, 1);
4213 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4214 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
4215 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4216 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4217 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4218 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4219 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4220 set_gdbarch_call_dummy_length (gdbarch
, 0);
4221 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4222 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4223 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4224 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4225 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4226 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4227 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4229 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4230 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
4232 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4233 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
4234 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4235 set_gdbarch_ieee_float (gdbarch
, 1);
4237 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
4238 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
4244 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4246 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4249 fprintf_unfiltered (file
,
4250 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4252 fprintf_unfiltered (file
,
4253 "mips_dump_tdep: tdep->mips_abi = %d\n",
4256 fprintf_unfiltered (file
,
4257 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4258 FP_REGISTER_DOUBLE
);
4259 fprintf_unfiltered (file
,
4260 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4261 MIPS_DEFAULT_FPU_TYPE
,
4262 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4263 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4264 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4266 fprintf_unfiltered (file
,
4267 "mips_dump_tdep: MIPS_EABI = %d\n",
4269 fprintf_unfiltered (file
,
4270 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d\n",
4271 MIPS_LAST_FP_ARG_REGNUM
);
4272 fprintf_unfiltered (file
,
4273 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4275 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4276 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4277 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4279 fprintf_unfiltered (file
,
4280 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4281 MIPS_DEFAULT_SAVED_REGSIZE
);
4282 fprintf_unfiltered (file
,
4283 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4284 FP_REGISTER_DOUBLE
);
4285 fprintf_unfiltered (file
,
4286 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4287 MIPS_REGS_HAVE_HOME_P
);
4288 fprintf_unfiltered (file
,
4289 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4290 MIPS_DEFAULT_STACK_ARGSIZE
);
4291 fprintf_unfiltered (file
,
4292 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4293 MIPS_STACK_ARGSIZE
);
4294 fprintf_unfiltered (file
,
4295 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4297 fprintf_unfiltered (file
,
4298 "mips_dump_tdep: A0_REGNUM = %d\n",
4300 fprintf_unfiltered (file
,
4301 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4302 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
4303 fprintf_unfiltered (file
,
4304 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4305 XSTRING (ATTACH_DETACH
));
4306 fprintf_unfiltered (file
,
4307 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4309 fprintf_unfiltered (file
,
4310 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4311 fprintf_unfiltered (file
,
4312 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4314 fprintf_unfiltered (file
,
4315 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4317 fprintf_unfiltered (file
,
4318 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4320 fprintf_unfiltered (file
,
4321 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4322 XSTRING (DO_REGISTERS_INFO
));
4323 fprintf_unfiltered (file
,
4324 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4325 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
4326 fprintf_unfiltered (file
,
4327 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4328 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
4329 fprintf_unfiltered (file
,
4330 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4331 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
4332 fprintf_unfiltered (file
,
4333 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4335 fprintf_unfiltered (file
,
4336 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4338 fprintf_unfiltered (file
,
4339 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4340 FIRST_EMBED_REGNUM
);
4341 fprintf_unfiltered (file
,
4342 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4344 fprintf_unfiltered (file
,
4345 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4346 GDB_TARGET_IS_MIPS64
);
4347 fprintf_unfiltered (file
,
4348 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4349 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
4350 fprintf_unfiltered (file
,
4351 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4352 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
4353 fprintf_unfiltered (file
,
4354 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4356 fprintf_unfiltered (file
,
4357 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4358 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
4359 fprintf_unfiltered (file
,
4360 "mips_dump_tdep: HI_REGNUM = %d\n",
4362 fprintf_unfiltered (file
,
4363 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4364 fprintf_unfiltered (file
,
4365 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4366 fprintf_unfiltered (file
,
4367 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4368 XSTRING (IGNORE_HELPER_CALL (PC
)));
4369 fprintf_unfiltered (file
,
4370 "mips_dump_tdep: INIT_FRAME_PC # %s\n",
4371 XSTRING (INIT_FRAME_PC (FROMLEAF
, PREV
)));
4372 fprintf_unfiltered (file
,
4373 "mips_dump_tdep: INIT_FRAME_PC_FIRST # %s\n",
4374 XSTRING (INIT_FRAME_PC_FIRST (FROMLEAF
, PREV
)));
4375 fprintf_unfiltered (file
,
4376 "mips_dump_tdep: IN_SIGTRAMP # %s\n",
4377 XSTRING (IN_SIGTRAMP (PC
, NAME
)));
4378 fprintf_unfiltered (file
,
4379 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4380 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
4381 fprintf_unfiltered (file
,
4382 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4383 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
4384 fprintf_unfiltered (file
,
4385 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4386 fprintf_unfiltered (file
,
4387 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4389 fprintf_unfiltered (file
,
4390 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4391 fprintf_unfiltered (file
,
4392 "mips_dump_tdep: LO_REGNUM = %d\n",
4394 #ifdef MACHINE_CPROC_FP_OFFSET
4395 fprintf_unfiltered (file
,
4396 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4397 MACHINE_CPROC_FP_OFFSET
);
4399 #ifdef MACHINE_CPROC_PC_OFFSET
4400 fprintf_unfiltered (file
,
4401 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4402 MACHINE_CPROC_PC_OFFSET
);
4404 #ifdef MACHINE_CPROC_SP_OFFSET
4405 fprintf_unfiltered (file
,
4406 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4407 MACHINE_CPROC_SP_OFFSET
);
4409 fprintf_unfiltered (file
,
4410 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4411 fprintf_unfiltered (file
,
4412 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4413 fprintf_unfiltered (file
,
4414 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4416 fprintf_unfiltered (file
,
4417 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4418 fprintf_unfiltered (file
,
4419 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4420 fprintf_unfiltered (file
,
4421 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4422 fprintf_unfiltered (file
,
4423 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4425 fprintf_unfiltered (file
,
4426 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d\n",
4427 MIPS_LAST_ARG_REGNUM
);
4428 fprintf_unfiltered (file
,
4429 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4431 fprintf_unfiltered (file
,
4432 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4433 fprintf_unfiltered (file
,
4434 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4435 MIPS_SAVED_REGSIZE
);
4436 fprintf_unfiltered (file
,
4437 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4438 fprintf_unfiltered (file
,
4439 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4440 XSTRING (MSYMBOL_SIZE (MSYM
)));
4441 fprintf_unfiltered (file
,
4442 "mips_dump_tdep: OP_LDFPR = used?\n");
4443 fprintf_unfiltered (file
,
4444 "mips_dump_tdep: OP_LDGPR = used?\n");
4445 fprintf_unfiltered (file
,
4446 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4447 fprintf_unfiltered (file
,
4448 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4449 fprintf_unfiltered (file
,
4450 "mips_dump_tdep: PRID_REGNUM = %d\n",
4452 fprintf_unfiltered (file
,
4453 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4454 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
4455 fprintf_unfiltered (file
,
4456 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4457 fprintf_unfiltered (file
,
4458 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4459 fprintf_unfiltered (file
,
4460 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4461 fprintf_unfiltered (file
,
4462 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4463 fprintf_unfiltered (file
,
4464 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4465 fprintf_unfiltered (file
,
4466 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4467 fprintf_unfiltered (file
,
4468 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4469 fprintf_unfiltered (file
,
4470 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4471 fprintf_unfiltered (file
,
4472 "mips_dump_tdep: PROC_PC_REG = function?\n");
4473 fprintf_unfiltered (file
,
4474 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4475 fprintf_unfiltered (file
,
4476 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4477 fprintf_unfiltered (file
,
4478 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4479 fprintf_unfiltered (file
,
4480 "mips_dump_tdep: PS_REGNUM = %d\n",
4482 fprintf_unfiltered (file
,
4483 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4485 fprintf_unfiltered (file
,
4486 "mips_dump_tdep: RA_REGNUM = %d\n",
4488 fprintf_unfiltered (file
,
4489 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4490 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4491 fprintf_unfiltered (file
,
4492 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4493 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4494 fprintf_unfiltered (file
,
4495 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4496 fprintf_unfiltered (file
,
4497 "mips_dump_tdep: ROUND_DOWN = function?\n");
4498 fprintf_unfiltered (file
,
4499 "mips_dump_tdep: ROUND_UP = function?\n");
4501 fprintf_unfiltered (file
,
4502 "mips_dump_tdep: SAVED_BYTES = %d\n",
4506 fprintf_unfiltered (file
,
4507 "mips_dump_tdep: SAVED_FP = %d\n",
4511 fprintf_unfiltered (file
,
4512 "mips_dump_tdep: SAVED_PC = %d\n",
4515 fprintf_unfiltered (file
,
4516 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
4517 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
4518 fprintf_unfiltered (file
,
4519 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
4520 fprintf_unfiltered (file
,
4521 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
4523 fprintf_unfiltered (file
,
4524 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
4525 SIGFRAME_FPREGSAVE_OFF
);
4526 fprintf_unfiltered (file
,
4527 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
4529 fprintf_unfiltered (file
,
4530 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
4531 SIGFRAME_REGSAVE_OFF
);
4532 fprintf_unfiltered (file
,
4533 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
4535 fprintf_unfiltered (file
,
4536 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
4537 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
4538 fprintf_unfiltered (file
,
4539 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
4540 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
4541 fprintf_unfiltered (file
,
4542 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n",
4543 SOFTWARE_SINGLE_STEP_P
);
4544 fprintf_unfiltered (file
,
4545 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n",
4546 SOFTWARE_SINGLE_STEP_P
);
4547 fprintf_unfiltered (file
,
4548 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
4549 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
4550 #ifdef STACK_END_ADDR
4551 fprintf_unfiltered (file
,
4552 "mips_dump_tdep: STACK_END_ADDR = %d\n",
4555 fprintf_unfiltered (file
,
4556 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
4557 XSTRING (STEP_SKIPS_DELAY (PC
)));
4558 fprintf_unfiltered (file
,
4559 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
4560 STEP_SKIPS_DELAY_P
);
4561 fprintf_unfiltered (file
,
4562 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
4563 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
4564 fprintf_unfiltered (file
,
4565 "mips_dump_tdep: T9_REGNUM = %d\n",
4567 fprintf_unfiltered (file
,
4568 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
4569 fprintf_unfiltered (file
,
4570 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
4571 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
4572 fprintf_unfiltered (file
,
4573 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
4574 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
4575 fprintf_unfiltered (file
,
4576 "mips_dump_tdep: TARGET_MIPS = used?\n");
4577 fprintf_unfiltered (file
,
4578 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
4579 XSTRING (TM_PRINT_INSN_MACH
));
4581 fprintf_unfiltered (file
,
4582 "mips_dump_tdep: TRACE_CLEAR # %s\n",
4583 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
4586 fprintf_unfiltered (file
,
4587 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
4590 #ifdef TRACE_FLAVOR_SIZE
4591 fprintf_unfiltered (file
,
4592 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
4596 fprintf_unfiltered (file
,
4597 "mips_dump_tdep: TRACE_SET # %s\n",
4598 XSTRING (TRACE_SET (X
,STATE
)));
4600 fprintf_unfiltered (file
,
4601 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
4602 #ifdef UNUSED_REGNUM
4603 fprintf_unfiltered (file
,
4604 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
4607 fprintf_unfiltered (file
,
4608 "mips_dump_tdep: V0_REGNUM = %d\n",
4610 fprintf_unfiltered (file
,
4611 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
4612 (long) VM_MIN_ADDRESS
);
4614 fprintf_unfiltered (file
,
4615 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
4618 fprintf_unfiltered (file
,
4619 "mips_dump_tdep: ZERO_REGNUM = %d\n",
4621 fprintf_unfiltered (file
,
4622 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
4627 _initialize_mips_tdep ()
4629 static struct cmd_list_element
*mipsfpulist
= NULL
;
4630 struct cmd_list_element
*c
;
4632 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
4633 if (!tm_print_insn
) /* Someone may have already set it */
4634 tm_print_insn
= gdb_print_insn_mips
;
4636 /* Add root prefix command for all "set mips"/"show mips" commands */
4637 add_prefix_cmd ("mips", no_class
, set_mips_command
,
4638 "Various MIPS specific commands.",
4639 &setmipscmdlist
, "set mips ", 0, &setlist
);
4641 add_prefix_cmd ("mips", no_class
, show_mips_command
,
4642 "Various MIPS specific commands.",
4643 &showmipscmdlist
, "show mips ", 0, &showlist
);
4645 /* Allow the user to override the saved register size. */
4646 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
4649 &mips_saved_regsize_string
, "\
4650 Set size of general purpose registers saved on the stack.\n\
4651 This option can be set to one of:\n\
4652 32 - Force GDB to treat saved GP registers as 32-bit\n\
4653 64 - Force GDB to treat saved GP registers as 64-bit\n\
4654 auto - Allow GDB to use the target's default setting or autodetect the\n\
4655 saved GP register size from information contained in the executable.\n\
4660 /* Allow the user to override the argument stack size. */
4661 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
4664 &mips_stack_argsize_string
, "\
4665 Set the amount of stack space reserved for each argument.\n\
4666 This option can be set to one of:\n\
4667 32 - Force GDB to allocate 32-bit chunks per argument\n\
4668 64 - Force GDB to allocate 64-bit chunks per argument\n\
4669 auto - Allow GDB to determine the correct setting from the current\n\
4670 target and executable (default)",
4674 /* Let the user turn off floating point and set the fence post for
4675 heuristic_proc_start. */
4677 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
4678 "Set use of MIPS floating-point coprocessor.",
4679 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
4680 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
4681 "Select single-precision MIPS floating-point coprocessor.",
4683 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
4684 "Select double-precision MIPS floating-point coprocessor .",
4686 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
4687 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
4688 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
4689 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
4690 "Select no MIPS floating-point coprocessor.",
4692 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
4693 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
4694 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
4695 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
4696 "Select MIPS floating-point coprocessor automatically.",
4698 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
4699 "Show current use of MIPS floating-point coprocessor target.",
4703 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
4704 (char *) &tmp_mips_processor_type
,
4705 "Set the type of MIPS processor in use.\n\
4706 Set this to be able to access processor-type-specific registers.\n\
4709 c
->function
.cfunc
= mips_set_processor_type_command
;
4710 c
= add_show_from_set (c
, &showlist
);
4711 c
->function
.cfunc
= mips_show_processor_type_command
;
4713 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
4714 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
4717 /* We really would like to have both "0" and "unlimited" work, but
4718 command.c doesn't deal with that. So make it a var_zinteger
4719 because the user can always use "999999" or some such for unlimited. */
4720 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
4721 (char *) &heuristic_fence_post
,
4723 Set the distance searched for the start of a function.\n\
4724 If you are debugging a stripped executable, GDB needs to search through the\n\
4725 program for the start of a function. This command sets the distance of the\n\
4726 search. The only need to set it is when debugging a stripped executable.",
4728 /* We need to throw away the frame cache when we set this, since it
4729 might change our ability to get backtraces. */
4730 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
4731 add_show_from_set (c
, &showlist
);
4733 /* Allow the user to control whether the upper bits of 64-bit
4734 addresses should be zeroed. */
4736 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *) &mask_address_p
,
4737 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
4738 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
4739 Without an argument, zeroing of upper address bits is enabled.", &setlist
),
4742 /* Allow the user to control the size of 32 bit registers within the
4743 raw remote packet. */
4744 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
4747 (char *)&mips64_transfers_32bit_regs_p
, "\
4748 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
4749 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
4750 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
4751 64 bits for others. Use \"off\" to disable compatibility mode",
4755 /* Debug this files internals. */
4756 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
4757 &mips_debug
, "Set mips debugging.\n\
4758 When non-zero, mips specific debugging is enabled.", &setdebuglist
),