1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
41 /* FIXME: Put this declaration in frame.h. */
42 extern struct obstack frame_cache_obstack
;
45 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
48 static int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
50 static void mips_print_register
PARAMS ((int, int));
52 static mips_extra_func_info_t
53 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
55 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
57 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
59 static void mips_set_fpu_command
PARAMS ((char *, int,
60 struct cmd_list_element
*));
62 static void mips_show_fpu_command
PARAMS ((char *, int,
63 struct cmd_list_element
*));
65 void mips_set_processor_type_command
PARAMS ((char *, int));
67 int mips_set_processor_type
PARAMS ((char *));
69 static void mips_show_processor_type_command
PARAMS ((char *, int));
71 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
72 struct cmd_list_element
*));
74 static mips_extra_func_info_t
75 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
*next_frame
));
77 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
78 mips_extra_func_info_t proc_desc
));
80 /* This value is the model of MIPS in use. It is derived from the value
81 of the PrID register. */
83 char *mips_processor_type
;
85 char *tmp_mips_processor_type
;
87 /* Some MIPS boards don't support floating point, so we permit the
88 user to turn it off. */
90 enum mips_fpu_type mips_fpu
;
92 static char *mips_fpu_string
;
94 /* A set of original names, to be used when restoring back to generic
95 registers from a specific set. */
97 char *mips_generic_reg_names
[] = REGISTER_NAMES
;
99 /* Names of IDT R3041 registers. */
101 char *mips_r3041_reg_names
[] = {
102 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
103 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
104 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
105 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
106 "sr", "lo", "hi", "bad", "cause","pc",
107 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
108 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
109 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
110 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
111 "fsr", "fir", "fp", "",
112 "", "", "bus", "ccfg", "", "", "", "",
113 "", "", "port", "cmp", "", "", "epc", "prid",
116 /* Names of IDT R3051 registers. */
118 char *mips_r3051_reg_names
[] = {
119 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
120 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
121 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
122 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
123 "sr", "lo", "hi", "bad", "cause","pc",
124 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
125 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
126 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
127 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
128 "fsr", "fir", "fp", "",
129 "inx", "rand", "elo", "", "ctxt", "", "", "",
130 "", "", "ehi", "", "", "", "epc", "prid",
133 /* Names of IDT R3081 registers. */
135 char *mips_r3081_reg_names
[] = {
136 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
137 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
138 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
139 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
140 "sr", "lo", "hi", "bad", "cause","pc",
141 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
142 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
143 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
144 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
145 "fsr", "fir", "fp", "",
146 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
147 "", "", "ehi", "", "", "", "epc", "prid",
150 /* Names of LSI 33k registers. */
152 char *mips_lsi33k_reg_names
[] = {
153 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
154 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
155 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
156 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
157 "epc", "hi", "lo", "sr", "cause","badvaddr",
158 "dcic", "bpc", "bda", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "",
163 "", "", "", "", "", "", "", "",
164 "", "", "", "", "", "", "", "",
170 } mips_processor_type_table
[] = {
171 { "generic", mips_generic_reg_names
},
172 { "r3041", mips_r3041_reg_names
},
173 { "r3051", mips_r3051_reg_names
},
174 { "r3071", mips_r3081_reg_names
},
175 { "r3081", mips_r3081_reg_names
},
176 { "lsi33k", mips_lsi33k_reg_names
},
180 /* Table to translate MIPS16 register field to actual register number. */
181 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
183 /* Heuristic_proc_start may hunt through the text section for a long
184 time across a 2400 baud serial line. Allows the user to limit this
187 static unsigned int heuristic_fence_post
= 0;
189 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
190 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
191 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
192 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
193 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
194 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
195 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
196 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
197 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
198 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
199 #define _PROC_MAGIC_ 0x0F0F0F0F
200 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
201 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
203 struct linked_proc_info
205 struct mips_extra_func_info info
;
206 struct linked_proc_info
*next
;
207 } *linked_proc_desc_table
= NULL
;
210 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
213 pc_is_mips16 (bfd_vma memaddr
)
215 struct minimal_symbol
*sym
;
217 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
218 if (IS_MIPS16_ADDR (memaddr
))
221 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
222 the high bit of the info field. Use this to decide if the function is
223 MIPS16 or normal MIPS. */
224 sym
= lookup_minimal_symbol_by_pc (memaddr
);
226 return MSYMBOL_IS_SPECIAL (sym
);
232 /* This returns the PC of the first inst after the prologue. If we can't
233 find the prologue, then return 0. */
236 after_prologue (pc
, proc_desc
)
238 mips_extra_func_info_t proc_desc
;
240 struct symtab_and_line sal
;
241 CORE_ADDR func_addr
, func_end
;
244 proc_desc
= find_proc_desc (pc
, NULL
);
248 /* If function is frameless, then we need to do it the hard way. I
249 strongly suspect that frameless always means prologueless... */
250 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
251 && PROC_FRAME_OFFSET (proc_desc
) == 0)
255 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
256 return 0; /* Unknown */
258 sal
= find_pc_line (func_addr
, 0);
260 if (sal
.end
< func_end
)
263 /* The line after the prologue is after the end of the function. In this
264 case, tell the caller to find the prologue the hard way. */
269 /* Decode a MIPS32 instruction that saves a register in the stack, and
270 set the appropriate bit in the general register mask or float register mask
271 to indicate which register is saved. This is a helper function
272 for mips_find_saved_regs. */
275 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
277 unsigned long *gen_mask
;
278 unsigned long *float_mask
;
282 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
283 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
284 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
286 /* It might be possible to use the instruction to
287 find the offset, rather than the code below which
288 is based on things being in a certain order in the
289 frame, but figuring out what the instruction's offset
290 is relative to might be a little tricky. */
291 reg
= (inst
& 0x001f0000) >> 16;
292 *gen_mask
|= (1 << reg
);
294 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
295 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
296 || (inst
& 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */
299 reg
= ((inst
& 0x001f0000) >> 16);
300 *float_mask
|= (1 << reg
);
304 /* Decode a MIPS16 instruction that saves a register in the stack, and
305 set the appropriate bit in the general register or float register mask
306 to indicate which register is saved. This is a helper function
307 for mips_find_saved_regs. */
310 mips16_decode_reg_save (inst
, gen_mask
)
312 unsigned long *gen_mask
;
314 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
316 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
317 *gen_mask
|= (1 << reg
);
319 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
321 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
322 *gen_mask
|= (1 << reg
);
324 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
325 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
326 *gen_mask
|= (1 << 31);
330 /* Fetch and return instruction from the specified location. If the PC
331 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
334 mips_fetch_instruction (addr
)
337 char buf
[MIPS_INSTLEN
];
341 if (pc_is_mips16 (addr
))
343 instlen
= MIPS16_INSTLEN
;
344 addr
= UNMAKE_MIPS16_ADDR (addr
);
347 instlen
= MIPS_INSTLEN
;
348 status
= read_memory_nobpt (addr
, buf
, instlen
);
350 memory_error (status
, addr
);
351 return extract_unsigned_integer (buf
, instlen
);
355 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
359 mips_find_saved_regs (fci
)
360 struct frame_info
*fci
;
363 CORE_ADDR reg_position
;
364 /* r0 bit means kernel trap */
366 /* What registers have been saved? Bitmasks. */
367 unsigned long gen_mask
, float_mask
;
368 mips_extra_func_info_t proc_desc
;
371 fci
->saved_regs
= (struct frame_saved_regs
*)
372 obstack_alloc (&frame_cache_obstack
, sizeof(struct frame_saved_regs
));
373 memset (fci
->saved_regs
, 0, sizeof (struct frame_saved_regs
));
375 /* If it is the frame for sigtramp, the saved registers are located
376 in a sigcontext structure somewhere on the stack.
377 If the stack layout for sigtramp changes we might have to change these
378 constants and the companion fixup_sigtramp in mdebugread.c */
379 #ifndef SIGFRAME_BASE
380 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
381 above the sigtramp frame. */
382 #define SIGFRAME_BASE MIPS_REGSIZE
383 /* FIXME! Are these correct?? */
384 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
385 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
386 #define SIGFRAME_FPREGSAVE_OFF \
387 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
389 #ifndef SIGFRAME_REG_SIZE
390 /* FIXME! Is this correct?? */
391 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
393 if (fci
->signal_handler_caller
)
395 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
397 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
398 + ireg
* SIGFRAME_REG_SIZE
;
399 fci
->saved_regs
->regs
[ireg
] = reg_position
;
401 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
403 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
404 + ireg
* SIGFRAME_REG_SIZE
;
405 fci
->saved_regs
->regs
[FP0_REGNUM
+ ireg
] = reg_position
;
407 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
411 proc_desc
= fci
->proc_desc
;
412 if (proc_desc
== NULL
)
413 /* I'm not sure how/whether this can happen. Normally when we can't
414 find a proc_desc, we "synthesize" one using heuristic_proc_desc
415 and set the saved_regs right away. */
418 kernel_trap
= PROC_REG_MASK(proc_desc
) & 1;
419 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK(proc_desc
);
420 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc
);
422 if (/* In any frame other than the innermost or a frame interrupted by
423 a signal, we assume that all registers have been saved.
424 This assumes that all register saves in a function happen before
425 the first function call. */
426 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
428 /* In a dummy frame we know exactly where things are saved. */
429 && !PROC_DESC_IS_DUMMY (proc_desc
)
431 /* Don't bother unless we are inside a function prologue. Outside the
432 prologue, we know where everything is. */
434 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
436 /* Not sure exactly what kernel_trap means, but if it means
437 the kernel saves the registers without a prologue doing it,
438 we better not examine the prologue to see whether registers
439 have been saved yet. */
442 /* We need to figure out whether the registers that the proc_desc
443 claims are saved have been saved yet. */
447 /* Bitmasks; set if we have found a save for the register. */
448 unsigned long gen_save_found
= 0;
449 unsigned long float_save_found
= 0;
452 /* If the address is odd, assume this is MIPS16 code. */
453 addr
= PROC_LOW_ADDR (proc_desc
);
454 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
456 /* Scan through this function's instructions preceding the current
457 PC, and look for those that save registers. */
458 while (addr
< fci
->pc
)
460 inst
= mips_fetch_instruction (addr
);
461 if (pc_is_mips16 (addr
))
462 mips16_decode_reg_save (inst
, &gen_save_found
);
464 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
467 gen_mask
= gen_save_found
;
468 float_mask
= float_save_found
;
471 /* Fill in the offsets for the registers which gen_mask says
473 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
474 for (ireg
= MIPS_NUMREGS
-1; gen_mask
; --ireg
, gen_mask
<<= 1)
475 if (gen_mask
& 0x80000000)
477 fci
->saved_regs
->regs
[ireg
] = reg_position
;
478 reg_position
-= MIPS_REGSIZE
;
481 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
482 of that normally used by gcc. Therefore, we have to fetch the first
483 instruction of the function, and if it's an entry instruction that
484 saves $s0 or $s1, correct their saved addresses. */
485 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
487 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
488 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
491 int sreg_count
= (inst
>> 6) & 3;
493 /* Check if the ra register was pushed on the stack. */
494 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
496 reg_position
-= MIPS_REGSIZE
;
498 /* Check if the s0 and s1 registers were pushed on the stack. */
499 for (reg
= 16; reg
< sreg_count
+16; reg
++)
501 fci
->saved_regs
->regs
[reg
] = reg_position
;
502 reg_position
-= MIPS_REGSIZE
;
507 /* Fill in the offsets for the registers which float_mask says
509 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
511 /* The freg_offset points to where the first *double* register
512 is saved. So skip to the high-order word. */
513 if (! GDB_TARGET_IS_MIPS64
)
514 reg_position
+= MIPS_REGSIZE
;
516 /* Fill in the offsets for the float registers which float_mask says
518 for (ireg
= MIPS_NUMREGS
-1; float_mask
; --ireg
, float_mask
<<= 1)
519 if (float_mask
& 0x80000000)
521 fci
->saved_regs
->regs
[FP0_REGNUM
+ireg
] = reg_position
;
522 reg_position
-= MIPS_REGSIZE
;
525 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->saved_regs
->regs
[RA_REGNUM
];
529 read_next_frame_reg(fi
, regno
)
530 struct frame_info
*fi
;
533 for (; fi
; fi
= fi
->next
)
535 /* We have to get the saved sp from the sigcontext
536 if it is a signal handler frame. */
537 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
541 if (fi
->saved_regs
== NULL
)
542 mips_find_saved_regs (fi
);
543 if (fi
->saved_regs
->regs
[regno
])
544 return read_memory_integer(fi
->saved_regs
->regs
[regno
], MIPS_REGSIZE
);
547 return read_register (regno
);
550 /* mips_addr_bits_remove - remove useless address bits */
553 mips_addr_bits_remove (addr
)
556 #if GDB_TARGET_IS_MIPS64
557 if ((addr
>> 32 == (CORE_ADDR
)0xffffffff)
558 && (strcmp (target_shortname
,"pmon")==0
559 || strcmp (target_shortname
,"ddb")==0
560 || strcmp (target_shortname
,"sim")==0))
562 /* This hack is a work-around for existing boards using PMON,
563 the simulator, and any other 64-bit targets that doesn't have
564 true 64-bit addressing. On these targets, the upper 32 bits
565 of addresses are ignored by the hardware. Thus, the PC or SP
566 are likely to have been sign extended to all 1s by instruction
567 sequences that load 32-bit addresses. For example, a typical
568 piece of code that loads an address is this:
569 lui $r2, <upper 16 bits>
570 ori $r2, <lower 16 bits>
571 But the lui sign-extends the value such that the upper 32 bits
572 may be all 1s. The workaround is simply to mask off these bits.
573 In the future, gcc may be changed to support true 64-bit
574 addressing, and this masking will have to be disabled. */
575 addr
&= (CORE_ADDR
)0xffffffff;
578 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
579 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
580 So we still have to mask off useless bits from addresses. */
581 addr
&= (CORE_ADDR
)0xffffffff;
588 mips_init_frame_pc_first (fromleaf
, prev
)
590 struct frame_info
*prev
;
594 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
595 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
596 tmp
= mips_skip_stub (pc
);
597 prev
->pc
= tmp
? tmp
: pc
;
602 mips_frame_saved_pc(frame
)
603 struct frame_info
*frame
;
606 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
607 /* We have to get the saved pc from the sigcontext
608 if it is a signal handler frame. */
609 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
610 : (proc_desc
? PROC_PC_REG(proc_desc
) : RA_REGNUM
);
612 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
613 saved_pc
= read_memory_integer(frame
->frame
- MIPS_REGSIZE
, MIPS_REGSIZE
);
615 saved_pc
= read_next_frame_reg(frame
, pcreg
);
617 return ADDR_BITS_REMOVE (saved_pc
);
620 static struct mips_extra_func_info temp_proc_desc
;
621 static struct frame_saved_regs temp_saved_regs
;
623 /* This fencepost looks highly suspicious to me. Removing it also
624 seems suspicious as it could affect remote debugging across serial
628 heuristic_proc_start(pc
)
636 pc
= ADDR_BITS_REMOVE (pc
);
638 fence
= start_pc
- heuristic_fence_post
;
639 if (start_pc
== 0) return 0;
641 if (heuristic_fence_post
== UINT_MAX
642 || fence
< VM_MIN_ADDRESS
)
643 fence
= VM_MIN_ADDRESS
;
645 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
647 /* search back for previous return */
648 for (start_pc
-= instlen
; ; start_pc
-= instlen
)
649 if (start_pc
< fence
)
651 /* It's not clear to me why we reach this point when
652 stop_soon_quietly, but with this test, at least we
653 don't print out warnings for every child forked (eg, on
654 decstation). 22apr93 rich@cygnus.com. */
655 if (!stop_soon_quietly
)
657 static int blurb_printed
= 0;
659 if (fence
== VM_MIN_ADDRESS
)
660 warning("Hit beginning of text section without finding");
662 warning("Hit heuristic-fence-post without finding");
664 warning("enclosing function for address 0x%s", paddr_nz (pc
));
668 This warning occurs if you are debugging a function without any symbols\n\
669 (for example, in a stripped executable). In that case, you may wish to\n\
670 increase the size of the search with the `set heuristic-fence-post' command.\n\
672 Otherwise, you told GDB there was a function where there isn't one, or\n\
673 (more likely) you have encountered a bug in GDB.\n");
680 else if (pc_is_mips16 (start_pc
))
684 /* On MIPS16, any one of the following is likely to be the
689 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
690 inst
= mips_fetch_instruction (start_pc
);
691 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
692 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
693 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
694 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
696 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
697 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
702 else if (ABOUT_TO_RETURN(start_pc
))
704 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
709 /* skip nops (usually 1) 0 - is this */
710 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
711 start_pc
+= MIPS_INSTLEN
;
716 /* Fetch the immediate value from a MIPS16 instruction.
717 If the previous instruction was an EXTEND, use it to extend
718 the upper bits of the immediate value. This is a helper function
719 for mips16_heuristic_proc_desc. */
722 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
723 unsigned short prev_inst
; /* previous instruction */
724 unsigned short inst
; /* current current instruction */
725 int nbits
; /* number of bits in imm field */
726 int scale
; /* scale factor to be applied to imm */
727 int is_signed
; /* is the imm field signed? */
731 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
733 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
734 if (offset
& 0x8000) /* check for negative extend */
735 offset
= 0 - (0x10000 - (offset
& 0xffff));
736 return offset
| (inst
& 0x1f);
740 int max_imm
= 1 << nbits
;
741 int mask
= max_imm
- 1;
742 int sign_bit
= max_imm
>> 1;
744 offset
= inst
& mask
;
745 if (is_signed
&& (offset
& sign_bit
))
746 offset
= 0 - (max_imm
- offset
);
747 return offset
* scale
;
752 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
753 stream from start_pc to limit_pc. */
756 mips16_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
757 CORE_ADDR start_pc
, limit_pc
;
758 struct frame_info
*next_frame
;
762 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
763 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
764 unsigned inst
= 0; /* current instruction */
766 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
768 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
772 /* Save the previous instruction. If it's an EXTEND, we'll extract
773 the immediate offset extension from it in mips16_get_imm. */
776 /* Fetch and decode the instruction. */
777 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
778 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
779 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
781 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
782 if (offset
< 0) /* negative stack adjustment? */
783 PROC_FRAME_OFFSET(&temp_proc_desc
) -= offset
;
785 /* Exit loop if a positive stack adjustment is found, which
786 usually means that the stack cleanup code in the function
787 epilogue is reached. */
790 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
792 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
793 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
794 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
795 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
797 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
799 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
800 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
801 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
802 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
804 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
806 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
807 PROC_REG_MASK(&temp_proc_desc
) |= (1 << 31);
808 temp_saved_regs
.regs
[31] = sp
+ offset
;
810 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
812 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
813 PROC_REG_MASK(&temp_proc_desc
) |= (1 << 31);
814 temp_saved_regs
.regs
[31] = sp
+ offset
;
816 else if (inst
== 0x673d) /* move $s1, $sp */
818 frame_addr
= read_next_frame_reg(next_frame
, 30);
819 PROC_FRAME_REG (&temp_proc_desc
) = 17;
821 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
823 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
824 frame_addr
= sp
+ offset
;
825 PROC_FRAME_REG (&temp_proc_desc
) = 17;
827 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
829 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
830 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
831 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
832 temp_saved_regs
.regs
[reg
] = frame_addr
+ offset
;
834 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
836 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
837 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
838 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
839 temp_saved_regs
.regs
[reg
] = frame_addr
+ offset
;
841 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
843 int areg_count
= (inst
>> 8) & 7;
844 int sreg_count
= (inst
>> 6) & 3;
846 /* The entry instruction always subtracts 32 from the SP. */
847 PROC_FRAME_OFFSET(&temp_proc_desc
) += 32;
849 /* Check if a0-a3 were saved in the caller's argument save area. */
850 for (reg
= 4, offset
= 32; reg
< areg_count
+4; reg
++)
852 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
853 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
854 offset
-= MIPS_REGSIZE
;
857 /* Check if the ra register was pushed on the stack. */
861 PROC_REG_MASK(&temp_proc_desc
) |= 1 << 31;
862 temp_saved_regs
.regs
[31] = sp
+ offset
;
863 offset
-= MIPS_REGSIZE
;
866 /* Check if the s0 and s1 registers were pushed on the stack. */
867 for (reg
= 16; reg
< sreg_count
+16; reg
++)
869 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
870 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
871 offset
-= MIPS_REGSIZE
;
874 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
875 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
880 mips32_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
881 CORE_ADDR start_pc
, limit_pc
;
882 struct frame_info
*next_frame
;
886 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
888 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
889 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
891 unsigned long inst
, high_word
, low_word
;
894 /* Fetch the instruction. */
895 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
897 /* Save some code by pre-extracting some useful fields. */
898 high_word
= (inst
>> 16) & 0xffff;
899 low_word
= inst
& 0xffff;
900 reg
= high_word
& 0x1f;
902 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
903 || high_word
== 0x23bd /* addi $sp,$sp,-i */
904 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
906 if (low_word
& 0x8000) /* negative stack adjustment? */
907 PROC_FRAME_OFFSET(&temp_proc_desc
) += 0x10000 - low_word
;
909 /* Exit loop if a positive stack adjustment is found, which
910 usually means that the stack cleanup code in the function
911 epilogue is reached. */
914 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
916 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
917 temp_saved_regs
.regs
[reg
] = sp
+ low_word
;
919 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
921 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
922 but the register size used is only 32 bits. Make the address
923 for the saved register point to the lower 32 bits. */
924 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
925 temp_saved_regs
.regs
[reg
] = sp
+ low_word
+ 8 - MIPS_REGSIZE
;
927 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
929 /* Old gcc frame, r30 is virtual frame pointer. */
930 if ((long)low_word
!= PROC_FRAME_OFFSET(&temp_proc_desc
))
931 frame_addr
= sp
+ low_word
;
932 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
934 unsigned alloca_adjust
;
935 PROC_FRAME_REG (&temp_proc_desc
) = 30;
936 frame_addr
= read_next_frame_reg(next_frame
, 30);
937 alloca_adjust
= (unsigned)(frame_addr
- (sp
+ low_word
));
938 if (alloca_adjust
> 0)
940 /* FP > SP + frame_size. This may be because
941 * of an alloca or somethings similar.
942 * Fix sp to "pre-alloca" value, and try again.
949 /* move $30,$sp. With different versions of gas this will be either
950 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
951 Accept any one of these. */
952 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
954 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
955 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
957 unsigned alloca_adjust
;
958 PROC_FRAME_REG (&temp_proc_desc
) = 30;
959 frame_addr
= read_next_frame_reg(next_frame
, 30);
960 alloca_adjust
= (unsigned)(frame_addr
- sp
);
961 if (alloca_adjust
> 0)
963 /* FP > SP + frame_size. This may be because
964 * of an alloca or somethings similar.
965 * Fix sp to "pre-alloca" value, and try again.
972 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
974 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
975 temp_saved_regs
.regs
[reg
] = frame_addr
+ low_word
;
980 static mips_extra_func_info_t
981 heuristic_proc_desc(start_pc
, limit_pc
, next_frame
)
982 CORE_ADDR start_pc
, limit_pc
;
983 struct frame_info
*next_frame
;
985 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
987 if (start_pc
== 0) return NULL
;
988 memset (&temp_proc_desc
, '\0', sizeof(temp_proc_desc
));
989 memset (&temp_saved_regs
, '\0', sizeof(struct frame_saved_regs
));
990 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
991 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
992 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
994 if (start_pc
+ 200 < limit_pc
)
995 limit_pc
= start_pc
+ 200;
996 if (pc_is_mips16 (start_pc
))
997 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
999 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1000 return &temp_proc_desc
;
1003 static mips_extra_func_info_t
1004 non_heuristic_proc_desc (pc
, addrptr
)
1008 CORE_ADDR startaddr
;
1009 mips_extra_func_info_t proc_desc
;
1010 struct block
*b
= block_for_pc(pc
);
1013 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1015 *addrptr
= startaddr
;
1016 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1020 if (startaddr
> BLOCK_START (b
))
1021 /* This is the "pathological" case referred to in a comment in
1022 print_frame_info. It might be better to move this check into
1026 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1029 /* If we never found a PDR for this function in symbol reading, then
1030 examine prologues to find the information. */
1033 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1034 if (PROC_FRAME_REG (proc_desc
) == -1)
1044 static mips_extra_func_info_t
1045 find_proc_desc (pc
, next_frame
)
1047 struct frame_info
*next_frame
;
1049 mips_extra_func_info_t proc_desc
;
1050 CORE_ADDR startaddr
;
1052 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1056 /* IF this is the topmost frame AND
1057 * (this proc does not have debugging information OR
1058 * the PC is in the procedure prologue)
1059 * THEN create a "heuristic" proc_desc (by analyzing
1060 * the actual code) to replace the "official" proc_desc.
1062 if (next_frame
== NULL
)
1064 struct symtab_and_line val
;
1065 struct symbol
*proc_symbol
=
1066 PROC_DESC_IS_DUMMY(proc_desc
) ? 0 : PROC_SYMBOL(proc_desc
);
1070 val
= find_pc_line (BLOCK_START
1071 (SYMBOL_BLOCK_VALUE(proc_symbol
)),
1073 val
.pc
= val
.end
? val
.end
: pc
;
1075 if (!proc_symbol
|| pc
< val
.pc
)
1077 mips_extra_func_info_t found_heuristic
=
1078 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1080 if (found_heuristic
)
1081 proc_desc
= found_heuristic
;
1087 /* Is linked_proc_desc_table really necessary? It only seems to be used
1088 by procedure call dummys. However, the procedures being called ought
1089 to have their own proc_descs, and even if they don't,
1090 heuristic_proc_desc knows how to create them! */
1092 register struct linked_proc_info
*link
;
1094 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1095 if (PROC_LOW_ADDR(&link
->info
) <= pc
1096 && PROC_HIGH_ADDR(&link
->info
) > pc
)
1100 startaddr
= heuristic_proc_start (pc
);
1103 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1109 get_frame_pointer(frame
, proc_desc
)
1110 struct frame_info
*frame
;
1111 mips_extra_func_info_t proc_desc
;
1113 return ADDR_BITS_REMOVE (read_next_frame_reg (frame
,
1114 PROC_FRAME_REG(proc_desc
)) + PROC_FRAME_OFFSET(proc_desc
));
1117 mips_extra_func_info_t cached_proc_desc
;
1120 mips_frame_chain(frame
)
1121 struct frame_info
*frame
;
1123 mips_extra_func_info_t proc_desc
;
1125 CORE_ADDR saved_pc
= FRAME_SAVED_PC(frame
);
1127 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1130 /* Check if the PC is inside a call stub. If it is, fetch the
1131 PC of the caller of that stub. */
1132 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1135 /* Look up the procedure descriptor for this PC. */
1136 proc_desc
= find_proc_desc(saved_pc
, frame
);
1140 cached_proc_desc
= proc_desc
;
1142 /* If no frame pointer and frame size is zero, we must be at end
1143 of stack (or otherwise hosed). If we don't check frame size,
1144 we loop forever if we see a zero size frame. */
1145 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1146 && PROC_FRAME_OFFSET (proc_desc
) == 0
1147 /* The previous frame from a sigtramp frame might be frameless
1148 and have frame size zero. */
1149 && !frame
->signal_handler_caller
)
1152 return get_frame_pointer (frame
, proc_desc
);
1156 init_extra_frame_info(fci
)
1157 struct frame_info
*fci
;
1161 /* Use proc_desc calculated in frame_chain */
1162 mips_extra_func_info_t proc_desc
=
1163 fci
->next
? cached_proc_desc
: find_proc_desc(fci
->pc
, fci
->next
);
1165 fci
->saved_regs
= NULL
;
1167 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1170 /* Fixup frame-pointer - only needed for top frame */
1171 /* This may not be quite right, if proc has a real frame register.
1172 Get the value of the frame relative sp, procedure might have been
1173 interrupted by a signal at it's very start. */
1174 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1175 && !PROC_DESC_IS_DUMMY (proc_desc
))
1176 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1178 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1180 if (proc_desc
== &temp_proc_desc
)
1184 /* Do not set the saved registers for a sigtramp frame,
1185 mips_find_saved_registers will do that for us.
1186 We can't use fci->signal_handler_caller, it is not yet set. */
1187 find_pc_partial_function (fci
->pc
, &name
,
1188 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
1189 if (!IN_SIGTRAMP (fci
->pc
, name
))
1191 fci
->saved_regs
= (struct frame_saved_regs
*)
1192 obstack_alloc (&frame_cache_obstack
,
1193 sizeof (struct frame_saved_regs
));
1194 *fci
->saved_regs
= temp_saved_regs
;
1195 fci
->saved_regs
->regs
[PC_REGNUM
]
1196 = fci
->saved_regs
->regs
[RA_REGNUM
];
1200 /* hack: if argument regs are saved, guess these contain args */
1201 fci
->num_args
= -1; /* assume we can't tell how many args for now */
1202 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1204 if (PROC_REG_MASK(proc_desc
) & (1 << regnum
))
1206 fci
->num_args
= regnum
- A0_REGNUM
+ 1;
1213 /* MIPS stack frames are almost impenetrable. When execution stops,
1214 we basically have to look at symbol information for the function
1215 that we stopped in, which tells us *which* register (if any) is
1216 the base of the frame pointer, and what offset from that register
1217 the frame itself is at.
1219 This presents a problem when trying to examine a stack in memory
1220 (that isn't executing at the moment), using the "frame" command. We
1221 don't have a PC, nor do we have any registers except SP.
1223 This routine takes two arguments, SP and PC, and tries to make the
1224 cached frames look as if these two arguments defined a frame on the
1225 cache. This allows the rest of info frame to extract the important
1226 arguments without difficulty. */
1229 setup_arbitrary_frame (argc
, argv
)
1234 error ("MIPS frame specifications require two arguments: sp and pc");
1236 return create_new_frame (argv
[0], argv
[1]);
1240 mips_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
1245 CORE_ADDR struct_addr
;
1251 int stack_offset
= 0;
1253 /* Macros to round N up or down to the next A boundary; A must be
1255 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1256 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1258 /* First ensure that the stack and structure return address (if any)
1259 are properly aligned. The stack has to be 64-bit aligned even
1260 on 32-bit machines, because doubles must be 64-bit aligned. */
1261 sp
= ROUND_DOWN (sp
, 8);
1262 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_REGSIZE
);
1264 /* Now make space on the stack for the args. We allocate more
1265 than necessary for EABI, because the first few arguments are
1266 passed in registers, but that's OK. */
1267 for (argnum
= 0; argnum
< nargs
; argnum
++)
1268 len
+= ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args
[argnum
])), MIPS_REGSIZE
);
1269 sp
-= ROUND_UP (len
, 8);
1271 /* Initialize the integer and float register pointers. */
1273 float_argreg
= FPA0_REGNUM
;
1275 /* the struct_return pointer occupies the first parameter-passing reg */
1277 write_register (argreg
++, struct_addr
);
1279 /* Now load as many as possible of the first arguments into
1280 registers, and push the rest onto the stack. Loop thru args
1281 from first to last. */
1282 for (argnum
= 0; argnum
< nargs
; argnum
++)
1285 char valbuf
[REGISTER_RAW_SIZE(A0_REGNUM
)];
1286 value_ptr arg
= args
[argnum
];
1287 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1288 int len
= TYPE_LENGTH (arg_type
);
1289 enum type_code typecode
= TYPE_CODE (arg_type
);
1291 /* The EABI passes structures that do not fit in a register by
1292 reference. In all other cases, pass the structure by value. */
1293 if (MIPS_EABI
&& len
> MIPS_REGSIZE
&&
1294 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1296 store_address (valbuf
, MIPS_REGSIZE
, VALUE_ADDRESS (arg
));
1297 typecode
= TYPE_CODE_PTR
;
1302 val
= (char *)VALUE_CONTENTS (arg
);
1304 /* 32-bit ABIs always start floating point arguments in an
1305 even-numbered floating point register. */
1306 if (!GDB_TARGET_IS_MIPS64
&& typecode
== TYPE_CODE_FLT
1307 && (float_argreg
& 1))
1310 /* Floating point arguments passed in registers have to be
1311 treated specially. On 32-bit architectures, doubles
1312 are passed in register pairs; the even register gets
1313 the low word, and the odd register gets the high word.
1314 On non-EABI processors, the first two floating point arguments are
1315 also copied to general registers, because MIPS16 functions
1316 don't use float registers for arguments. This duplication of
1317 arguments in general registers can't hurt non-MIPS16 functions
1318 because those registers are normally skipped. */
1319 if (typecode
== TYPE_CODE_FLT
1320 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
1321 && mips_fpu
!= MIPS_FPU_NONE
)
1323 if (!GDB_TARGET_IS_MIPS64
&& len
== 8)
1325 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
1326 unsigned long regval
;
1328 /* Write the low word of the double to the even register(s). */
1329 regval
= extract_unsigned_integer (val
+low_offset
, 4);
1330 write_register (float_argreg
++, regval
);
1332 write_register (argreg
+1, regval
);
1334 /* Write the high word of the double to the odd register(s). */
1335 regval
= extract_unsigned_integer (val
+4-low_offset
, 4);
1336 write_register (float_argreg
++, regval
);
1339 write_register (argreg
, regval
);
1346 /* This is a floating point value that fits entirely
1347 in a single register. */
1348 CORE_ADDR regval
= extract_address (val
, len
);
1349 write_register (float_argreg
++, regval
);
1352 write_register (argreg
, regval
);
1353 argreg
+= GDB_TARGET_IS_MIPS64
? 1 : 2;
1359 /* Copy the argument to general registers or the stack in
1360 register-sized pieces. Large arguments are split between
1361 registers and stack. */
1362 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
1363 are treated specially: Irix cc passes them in registers
1364 where gcc sometimes puts them on the stack. For maximum
1365 compatibility, we will put them in both places. */
1367 int odd_sized_struct
= ((len
> MIPS_REGSIZE
) &&
1368 (len
% MIPS_REGSIZE
!= 0));
1371 int partial_len
= len
< MIPS_REGSIZE
? len
: MIPS_REGSIZE
;
1373 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
1375 /* Write this portion of the argument to the stack. */
1376 int longword_offset
;
1378 longword_offset
= 0;
1379 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1380 if (MIPS_REGSIZE
== 8 &&
1381 (typecode
== TYPE_CODE_INT
||
1382 typecode
== TYPE_CODE_PTR
||
1383 typecode
== TYPE_CODE_FLT
) && len
<= 4)
1384 longword_offset
= 4;
1385 else if ((typecode
== TYPE_CODE_STRUCT
||
1386 typecode
== TYPE_CODE_UNION
) &&
1387 TYPE_LENGTH (arg_type
) < MIPS_REGSIZE
)
1388 longword_offset
= MIPS_REGSIZE
- len
;
1390 write_memory (sp
+ stack_offset
+ longword_offset
,
1394 /* Note!!! This is NOT an else clause.
1395 Odd sized structs may go thru BOTH paths. */
1396 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
1398 CORE_ADDR regval
= extract_address (val
, partial_len
);
1400 /* A non-floating-point argument being passed in a
1401 general register. If a struct or union, and if
1402 the remaining length is smaller than the register
1403 size, we have to adjust the register value on
1406 It does not seem to be necessary to do the
1407 same for integral types.
1409 Also don't do this adjustment on EABI targets. */
1412 TARGET_BYTE_ORDER
== BIG_ENDIAN
&&
1413 partial_len
< MIPS_REGSIZE
&&
1414 (typecode
== TYPE_CODE_STRUCT
||
1415 typecode
== TYPE_CODE_UNION
))
1416 regval
<<= ((MIPS_REGSIZE
- partial_len
) *
1419 write_register (argreg
, regval
);
1422 /* If this is the old ABI, prevent subsequent floating
1423 point arguments from being passed in floating point
1426 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
1432 /* The offset onto the stack at which we will start
1433 copying parameters (after the registers are used up)
1434 begins at (4 * MIPS_REGSIZE) in the old ABI. This
1435 leaves room for the "home" area for register parameters.
1437 In the new EABI, the 8 register parameters do not
1438 have "home" stack space reserved for them, so the
1439 stack offset does not get incremented until after
1440 we have used up the 8 parameter registers. */
1441 if (!(MIPS_EABI
&& argnum
< 8))
1442 stack_offset
+= ROUND_UP (partial_len
, MIPS_REGSIZE
);
1447 /* Set the return address register to point to the entry
1448 point of the program, where a breakpoint lies in wait. */
1449 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS());
1451 /* Return adjusted stack pointer. */
1456 mips_push_register(CORE_ADDR
*sp
, int regno
)
1458 char buffer
[MAX_REGISTER_RAW_SIZE
];
1459 int regsize
= REGISTER_RAW_SIZE (regno
);
1462 read_register_gen (regno
, buffer
);
1463 write_memory (*sp
, buffer
, regsize
);
1466 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
1467 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
1470 mips_push_dummy_frame()
1473 struct linked_proc_info
*link
= (struct linked_proc_info
*)
1474 xmalloc(sizeof(struct linked_proc_info
));
1475 mips_extra_func_info_t proc_desc
= &link
->info
;
1476 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
1477 CORE_ADDR old_sp
= sp
;
1478 link
->next
= linked_proc_desc_table
;
1479 linked_proc_desc_table
= link
;
1481 /* FIXME! are these correct ? */
1482 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
1483 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
1484 #define FLOAT_REG_SAVE_MASK MASK(0,19)
1485 #define FLOAT_SINGLE_REG_SAVE_MASK \
1486 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
1488 * The registers we must save are all those not preserved across
1489 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
1490 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
1491 * and FP Control/Status registers.
1494 * Dummy frame layout:
1497 * Saved MMHI, MMLO, FPC_CSR
1502 * Saved D18 (i.e. F19, F18)
1504 * Saved D0 (i.e. F1, F0)
1505 * Argument build area and stack arguments written via mips_push_arguments
1509 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
1510 PROC_FRAME_REG(proc_desc
) = PUSH_FP_REGNUM
;
1511 PROC_FRAME_OFFSET(proc_desc
) = 0;
1512 mips_push_register (&sp
, PC_REGNUM
);
1513 mips_push_register (&sp
, HI_REGNUM
);
1514 mips_push_register (&sp
, LO_REGNUM
);
1515 mips_push_register (&sp
, mips_fpu
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
1517 /* Save general CPU registers */
1518 PROC_REG_MASK(proc_desc
) = GEN_REG_SAVE_MASK
;
1519 PROC_REG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved R31) from FP */
1520 for (ireg
= 32; --ireg
>= 0; )
1521 if (PROC_REG_MASK(proc_desc
) & (1 << ireg
))
1522 mips_push_register (&sp
, ireg
);
1524 /* Save floating point registers starting with high order word */
1525 PROC_FREG_MASK(proc_desc
) =
1526 mips_fpu
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
1527 : mips_fpu
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
1528 PROC_FREG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved D18) from FP */
1529 for (ireg
= 32; --ireg
>= 0; )
1530 if (PROC_FREG_MASK(proc_desc
) & (1 << ireg
))
1531 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
1533 /* Update the frame pointer for the call dummy and the stack pointer.
1534 Set the procedure's starting and ending addresses to point to the
1535 call dummy address at the entry point. */
1536 write_register (PUSH_FP_REGNUM
, old_sp
);
1537 write_register (SP_REGNUM
, sp
);
1538 PROC_LOW_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS();
1539 PROC_HIGH_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS() + 4;
1540 SET_PROC_DESC_IS_DUMMY(proc_desc
);
1541 PROC_PC_REG(proc_desc
) = RA_REGNUM
;
1547 register int regnum
;
1548 struct frame_info
*frame
= get_current_frame ();
1549 CORE_ADDR new_sp
= FRAME_FP (frame
);
1551 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
1553 write_register (PC_REGNUM
, FRAME_SAVED_PC(frame
));
1554 if (frame
->saved_regs
== NULL
)
1555 mips_find_saved_regs (frame
);
1556 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1558 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
1559 && frame
->saved_regs
->regs
[regnum
])
1560 write_register (regnum
,
1561 read_memory_integer (frame
->saved_regs
->regs
[regnum
],
1564 write_register (SP_REGNUM
, new_sp
);
1565 flush_cached_frames ();
1567 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
1569 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
1571 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
1573 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
1575 if (&pi_ptr
->info
== proc_desc
)
1580 error ("Can't locate dummy extra frame info\n");
1582 if (prev_ptr
!= NULL
)
1583 prev_ptr
->next
= pi_ptr
->next
;
1585 linked_proc_desc_table
= pi_ptr
->next
;
1589 write_register (HI_REGNUM
,
1590 read_memory_integer (new_sp
- 2*MIPS_REGSIZE
, MIPS_REGSIZE
));
1591 write_register (LO_REGNUM
,
1592 read_memory_integer (new_sp
- 3*MIPS_REGSIZE
, MIPS_REGSIZE
));
1593 if (mips_fpu
!= MIPS_FPU_NONE
)
1594 write_register (FCRCS_REGNUM
,
1595 read_memory_integer (new_sp
- 4*MIPS_REGSIZE
, MIPS_REGSIZE
));
1600 mips_print_register (regnum
, all
)
1603 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
1605 /* Get the data in raw format. */
1606 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
1608 printf_filtered ("%s: [Invalid]", reg_names
[regnum
]);
1612 /* If an even floating point register, also print as double. */
1613 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
1614 && !((regnum
-FP0_REGNUM
) & 1))
1615 if (REGISTER_RAW_SIZE(regnum
) == 4) /* this would be silly on MIPS64 */
1617 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
1619 read_relative_register_raw_bytes (regnum
, dbuffer
);
1620 read_relative_register_raw_bytes (regnum
+1, dbuffer
+MIPS_REGSIZE
);
1621 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
1623 printf_filtered ("(d%d: ", regnum
-FP0_REGNUM
);
1624 val_print (builtin_type_double
, dbuffer
, 0,
1625 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1626 printf_filtered ("); ");
1628 fputs_filtered (reg_names
[regnum
], gdb_stdout
);
1630 /* The problem with printing numeric register names (r26, etc.) is that
1631 the user can't use them on input. Probably the best solution is to
1632 fix it so that either the numeric or the funky (a2, etc.) names
1633 are accepted on input. */
1634 if (regnum
< MIPS_NUMREGS
)
1635 printf_filtered ("(r%d): ", regnum
);
1637 printf_filtered (": ");
1639 /* If virtual format is floating, print it that way. */
1640 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1641 if (REGISTER_RAW_SIZE(regnum
) == 8)
1642 { /* show 8-byte floats as float AND double: */
1643 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
1645 printf_filtered (" (float) ");
1646 val_print (builtin_type_float
, raw_buffer
+ offset
, 0,
1647 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1648 printf_filtered (", (double) ");
1649 val_print (builtin_type_double
, raw_buffer
, 0,
1650 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1653 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0,
1654 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1655 /* Else print as integer in hex. */
1657 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
1658 'x', 0, gdb_stdout
);
1661 /* Replacement for generic do_registers_info.
1662 Print regs in pretty columns. */
1665 do_fp_register_row (regnum
)
1667 { /* do values for FP (float) regs */
1668 char raw_buffer
[2] [REGISTER_RAW_SIZE(FP0_REGNUM
)];
1669 char dbl_buffer
[2 * REGISTER_RAW_SIZE(FP0_REGNUM
)];
1670 /* use HI and LO to control the order of combining two flt regs */
1671 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
1672 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
1673 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
1674 int inv1
, inv2
, inv3
;
1676 /* Get the data in raw format. */
1677 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
1678 error ("can't read register %d (%s)", regnum
, reg_names
[regnum
]);
1679 if (REGISTER_RAW_SIZE(regnum
) == 4)
1681 /* 4-byte registers: we can fit two registers per row. */
1682 /* Also print every pair of 4-byte regs as an 8-byte double. */
1683 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
1684 error ("can't read register %d (%s)",
1685 regnum
+ 1, reg_names
[regnum
+ 1]);
1687 /* copy the two floats into one double, and unpack both */
1688 memcpy (dbl_buffer
, raw_buffer
, sizeof(dbl_buffer
));
1689 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
1690 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
1691 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
1693 printf_filtered (inv1
? " %-5s: <invalid float>" :
1694 " %-5s%-17.9g", reg_names
[regnum
], flt1
);
1695 printf_filtered (inv2
? " %-5s: <invalid float>" :
1696 " %-5s%-17.9g", reg_names
[regnum
+ 1], flt2
);
1697 printf_filtered (inv3
? " dbl: <invalid double>\n" :
1698 " dbl: %-24.17g\n", doub
);
1699 /* may want to do hex display here (future enhancement) */
1703 { /* eight byte registers: print each one as float AND as double. */
1704 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
1706 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof(dbl_buffer
));
1707 flt1
= unpack_double (builtin_type_float
,
1708 &raw_buffer
[HI
][offset
], &inv1
);
1709 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
1711 printf_filtered (inv1
? " %-5s: <invalid float>" :
1712 " %-5s flt: %-17.9g", reg_names
[regnum
], flt1
);
1713 printf_filtered (inv3
? " dbl: <invalid double>\n" :
1714 " dbl: %-24.17g\n", doub
);
1715 /* may want to do hex display here (future enhancement) */
1721 /* Print a row's worth of GP (int) registers, with name labels above */
1724 do_gp_register_row (regnum
)
1726 { /* do values for GP (int) regs */
1727 char raw_buffer
[REGISTER_RAW_SIZE(0)];
1728 int ncols
= MIPS_REGSIZE
== 8 ? 4 : 8; /* display cols per row */
1729 int col
, byte
, start_regnum
= regnum
;
1731 /* For GP registers, we print a separate row of names above the vals */
1732 printf_filtered (" ");
1733 for (col
= 0; col
< ncols
&& regnum
< NUM_REGS
; regnum
++)
1735 if (*reg_names
[regnum
] == '\0')
1736 continue; /* unused register */
1737 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1738 break; /* end the row: reached FP register */
1739 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
1743 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
1744 start_regnum
); /* print the R0 to R31 names */
1746 regnum
= start_regnum
; /* go back to start of row */
1747 /* now print the values in hex, 4 or 8 to the row */
1748 for (col
= 0; col
< ncols
&& regnum
< NUM_REGS
; regnum
++)
1750 if (*reg_names
[regnum
] == '\0')
1751 continue; /* unused register */
1752 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1753 break; /* end row: reached FP register */
1754 /* OK: get the data in raw format. */
1755 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
1756 error ("can't read register %d (%s)", regnum
, reg_names
[regnum
]);
1757 /* Now print the register value in hex, endian order. */
1758 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1759 for (byte
= 0; byte
< REGISTER_RAW_SIZE (regnum
); byte
++)
1760 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
1762 for (byte
= REGISTER_RAW_SIZE (regnum
) - 1; byte
>= 0; byte
--)
1763 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
1764 printf_filtered (" ");
1767 if (col
> 0) /* ie. if we actually printed anything... */
1768 printf_filtered ("\n");
1773 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
1776 mips_do_registers_info (regnum
, fpregs
)
1780 if (regnum
!= -1) /* do one specified register */
1782 if (*(reg_names
[regnum
]) == '\0')
1783 error ("Not a valid register for the current processor type");
1785 mips_print_register (regnum
, 0);
1786 printf_filtered ("\n");
1788 else /* do all (or most) registers */
1791 while (regnum
< NUM_REGS
)
1792 if (TYPE_CODE(REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1793 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
1794 regnum
= do_fp_register_row (regnum
); /* FP regs */
1796 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
1798 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
1802 /* Return number of args passed to a frame. described by FIP.
1803 Can return -1, meaning no way to tell. */
1806 mips_frame_num_args (frame
)
1807 struct frame_info
*frame
;
1809 #if 0 /* FIXME Use or lose this! */
1810 struct chain_info_t
*p
;
1812 p
= mips_find_cached_frame (FRAME_FP (frame
));
1814 return p
->the_info
.numargs
;
1819 /* Is this a branch with a delay slot? */
1821 static int is_delayed
PARAMS ((unsigned long));
1828 for (i
= 0; i
< NUMOPCODES
; ++i
)
1829 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
1830 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
1832 return (i
< NUMOPCODES
1833 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
1834 | INSN_COND_BRANCH_DELAY
1835 | INSN_COND_BRANCH_LIKELY
)));
1839 mips_step_skips_delay (pc
)
1842 char buf
[MIPS_INSTLEN
];
1844 /* There is no branch delay slot on MIPS16. */
1845 if (pc_is_mips16 (pc
))
1848 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
1849 /* If error reading memory, guess that it is not a delayed branch. */
1851 return is_delayed ((unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
));
1855 /* Skip the PC past function prologue instructions (32-bit version).
1856 This is a helper function for mips_skip_prologue. */
1859 mips32_skip_prologue (pc
, lenient
)
1860 CORE_ADDR pc
; /* starting PC to search from */
1865 int seen_sp_adjust
= 0;
1866 int load_immediate_bytes
= 0;
1868 /* Skip the typical prologue instructions. These are the stack adjustment
1869 instruction and the instructions that save registers on the stack
1870 or in the gcc frame. */
1871 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
1873 unsigned long high_word
;
1875 inst
= mips_fetch_instruction (pc
);
1876 high_word
= (inst
>> 16) & 0xffff;
1879 if (lenient
&& is_delayed (inst
))
1883 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
1884 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
1886 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
1887 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
1889 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
1890 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
1891 && (inst
& 0x001F0000)) /* reg != $zero */
1894 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
1896 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
1898 continue; /* reg != $zero */
1900 /* move $s8,$sp. With different versions of gas this will be either
1901 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
1902 Accept any one of these. */
1903 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1906 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
1908 else if (high_word
== 0x3c1c) /* lui $gp,n */
1910 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
1912 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1913 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
1915 /* The following instructions load $at or $t0 with an immediate
1916 value in preparation for a stack adjustment via
1917 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
1918 a local variable, so we accept them only before a stack adjustment
1919 instruction was seen. */
1920 else if (!seen_sp_adjust
)
1922 if (high_word
== 0x3c01 || /* lui $at,n */
1923 high_word
== 0x3c08) /* lui $t0,n */
1925 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
1928 else if (high_word
== 0x3421 || /* ori $at,$at,n */
1929 high_word
== 0x3508 || /* ori $t0,$t0,n */
1930 high_word
== 0x3401 || /* ori $at,$zero,n */
1931 high_word
== 0x3408) /* ori $t0,$zero,n */
1933 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
1943 /* In a frameless function, we might have incorrectly
1944 skipped some load immediate instructions. Undo the skipping
1945 if the load immediate was not followed by a stack adjustment. */
1946 if (load_immediate_bytes
&& !seen_sp_adjust
)
1947 pc
-= load_immediate_bytes
;
1951 /* Skip the PC past function prologue instructions (16-bit version).
1952 This is a helper function for mips_skip_prologue. */
1955 mips16_skip_prologue (pc
, lenient
)
1956 CORE_ADDR pc
; /* starting PC to search from */
1960 int extend_bytes
= 0;
1961 int prev_extend_bytes
;
1963 /* Table of instructions likely to be found in a function prologue. */
1966 unsigned short inst
;
1967 unsigned short mask
;
1970 { 0x6300, 0xff00 }, /* addiu $sp,offset */
1971 { 0xfb00, 0xff00 }, /* daddiu $sp,offset */
1972 { 0xd000, 0xf800 }, /* sw reg,n($sp) */
1973 { 0xf900, 0xff00 }, /* sd reg,n($sp) */
1974 { 0x6200, 0xff00 }, /* sw $ra,n($sp) */
1975 { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */
1976 { 0x673d, 0xffff }, /* move $s1,sp */
1977 { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */
1978 { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */
1979 { 0xe809, 0xf81f }, /* entry pseudo-op */
1980 { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */
1981 { 0, 0 } /* end of table marker */
1984 /* Skip the typical prologue instructions. These are the stack adjustment
1985 instruction and the instructions that save registers on the stack
1986 or in the gcc frame. */
1987 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
1989 unsigned short inst
;
1992 inst
= mips_fetch_instruction (pc
);
1994 /* Normally we ignore an extend instruction. However, if it is
1995 not followed by a valid prologue instruction, we must adjust
1996 the pc back over the extend so that it won't be considered
1997 part of the prologue. */
1998 if ((inst
& 0xf800) == 0xf000) /* extend */
2000 extend_bytes
= MIPS16_INSTLEN
;
2003 prev_extend_bytes
= extend_bytes
;
2006 /* Check for other valid prologue instructions besides extend. */
2007 for (i
= 0; table
[i
].mask
!= 0; i
++)
2008 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2010 if (table
[i
].mask
!= 0) /* it was in table? */
2011 continue; /* ignore it */
2012 else /* non-prologue */
2014 /* Return the current pc, adjusted backwards by 2 if
2015 the previous instruction was an extend. */
2016 return pc
- prev_extend_bytes
;
2022 /* To skip prologues, I use this predicate. Returns either PC itself
2023 if the code at PC does not look like a function prologue; otherwise
2024 returns an address that (if we're lucky) follows the prologue. If
2025 LENIENT, then we must skip everything which is involved in setting
2026 up the frame (it's OK to skip more, just so long as we don't skip
2027 anything which might clobber the registers which are being saved.
2028 We must skip more in the case where part of the prologue is in the
2029 delay slot of a non-prologue instruction). */
2032 mips_skip_prologue (pc
, lenient
)
2036 /* See if we can determine the end of the prologue via the symbol table.
2037 If so, then return either PC, or the PC after the prologue, whichever
2040 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2042 if (post_prologue_pc
!= 0)
2043 return max (pc
, post_prologue_pc
);
2045 /* Can't determine prologue from the symbol table, need to examine
2048 if (pc_is_mips16 (pc
))
2049 return mips16_skip_prologue (pc
, lenient
);
2051 return mips32_skip_prologue (pc
, lenient
);
2055 /* The lenient prologue stuff should be superseded by the code in
2056 init_extra_frame_info which looks to see whether the stores mentioned
2057 in the proc_desc have actually taken place. */
2059 /* Is address PC in the prologue (loosely defined) for function at
2063 mips_in_lenient_prologue (startaddr
, pc
)
2064 CORE_ADDR startaddr
;
2067 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2068 return pc
>= startaddr
&& pc
< end_prologue
;
2072 /* Given a return value in `regbuf' with a type `valtype',
2073 extract and copy its value into `valbuf'. */
2075 mips_extract_return_value (valtype
, regbuf
, valbuf
)
2076 struct type
*valtype
;
2077 char regbuf
[REGISTER_BYTES
];
2082 int len
= TYPE_LENGTH (valtype
);
2085 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2086 && (mips_fpu
== MIPS_FPU_DOUBLE
2087 || (mips_fpu
== MIPS_FPU_SINGLE
&& len
<= MIPS_REGSIZE
)))
2088 regnum
= FP0_REGNUM
;
2090 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2091 { /* "un-left-justify" the value from the register */
2092 if (len
< REGISTER_RAW_SIZE (regnum
))
2093 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2094 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2095 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2096 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2097 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2098 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2100 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
2101 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
2104 /* Given a return value in `regbuf' with a type `valtype',
2105 write it's value into the appropriate register. */
2107 mips_store_return_value (valtype
, valbuf
)
2108 struct type
*valtype
;
2113 int len
= TYPE_LENGTH (valtype
);
2114 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2117 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2118 && (mips_fpu
== MIPS_FPU_DOUBLE
2119 || (mips_fpu
== MIPS_FPU_SINGLE
&& len
<= MIPS_REGSIZE
)))
2120 regnum
= FP0_REGNUM
;
2122 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2123 { /* "left-justify" the value in the register */
2124 if (len
< REGISTER_RAW_SIZE (regnum
))
2125 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2126 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2127 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2128 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2129 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2130 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2132 memcpy(raw_buffer
+ offset
, valbuf
, len
);
2133 REGISTER_CONVERT_FROM_TYPE(regnum
, valtype
, raw_buffer
);
2134 write_register_bytes(REGISTER_BYTE (regnum
), raw_buffer
,
2135 len
> REGISTER_RAW_SIZE (regnum
) ?
2136 len
: REGISTER_RAW_SIZE (regnum
));
2139 /* Exported procedure: Is PC in the signal trampoline code */
2142 in_sigtramp (pc
, ignore
)
2144 char *ignore
; /* function name */
2146 if (sigtramp_address
== 0)
2148 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
2151 /* Command to set FPU type. mips_fpu_string will have been set to the
2152 user's argument. Set mips_fpu based on mips_fpu_string, and then
2153 canonicalize mips_fpu_string. */
2157 mips_set_fpu_command (args
, from_tty
, c
)
2160 struct cmd_list_element
*c
;
2164 if (mips_fpu_string
== NULL
|| *mips_fpu_string
== '\0')
2165 mips_fpu
= MIPS_FPU_DOUBLE
;
2166 else if (strcasecmp (mips_fpu_string
, "double") == 0
2167 || strcasecmp (mips_fpu_string
, "on") == 0
2168 || strcasecmp (mips_fpu_string
, "1") == 0
2169 || strcasecmp (mips_fpu_string
, "yes") == 0)
2170 mips_fpu
= MIPS_FPU_DOUBLE
;
2171 else if (strcasecmp (mips_fpu_string
, "none") == 0
2172 || strcasecmp (mips_fpu_string
, "off") == 0
2173 || strcasecmp (mips_fpu_string
, "0") == 0
2174 || strcasecmp (mips_fpu_string
, "no") == 0)
2175 mips_fpu
= MIPS_FPU_NONE
;
2176 else if (strcasecmp (mips_fpu_string
, "single") == 0)
2177 mips_fpu
= MIPS_FPU_SINGLE
;
2179 err
= strsave (mips_fpu_string
);
2181 if (mips_fpu_string
!= NULL
)
2182 free (mips_fpu_string
);
2186 case MIPS_FPU_DOUBLE
:
2187 mips_fpu_string
= strsave ("double");
2189 case MIPS_FPU_SINGLE
:
2190 mips_fpu_string
= strsave ("single");
2193 mips_fpu_string
= strsave ("none");
2199 struct cleanup
*cleanups
= make_cleanup (free
, err
);
2200 error ("Unknown FPU type `%s'. Use `double', `none', or `single'.",
2202 do_cleanups (cleanups
);
2207 mips_show_fpu_command (args
, from_tty
, c
)
2210 struct cmd_list_element
*c
;
2214 /* Command to set the processor type. */
2217 mips_set_processor_type_command (args
, from_tty
)
2223 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
2225 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
2226 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2227 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
2229 /* Restore the value. */
2230 tmp_mips_processor_type
= strsave (mips_processor_type
);
2235 if (!mips_set_processor_type (tmp_mips_processor_type
))
2237 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
2238 /* Restore its value. */
2239 tmp_mips_processor_type
= strsave (mips_processor_type
);
2244 mips_show_processor_type_command (args
, from_tty
)
2250 /* Modify the actual processor type. */
2253 mips_set_processor_type (str
)
2261 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2263 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
2265 mips_processor_type
= str
;
2267 for (j
= 0; j
< NUM_REGS
; ++j
)
2268 reg_names
[j
] = mips_processor_type_table
[i
].regnames
[j
];
2272 /* FIXME tweak fpu flag too */
2279 /* Attempt to identify the particular processor model by reading the
2283 mips_read_processor_type ()
2287 prid
= read_register (PRID_REGNUM
);
2289 if ((prid
& ~0xf) == 0x700)
2290 return savestring ("r3041", strlen("r3041"));
2295 /* Just like reinit_frame_cache, but with the right arguments to be
2296 callable as an sfunc. */
2299 reinit_frame_cache_sfunc (args
, from_tty
, c
)
2302 struct cmd_list_element
*c
;
2304 reinit_frame_cache ();
2308 gdb_print_insn_mips (memaddr
, info
)
2310 disassemble_info
*info
;
2312 mips_extra_func_info_t proc_desc
;
2314 /* Search for the function containing this address. Set the low bit
2315 of the address when searching, in case we were given an even address
2316 that is the start of a 16-bit function. If we didn't do this,
2317 the search would fail because the symbol table says the function
2318 starts at an odd address, i.e. 1 byte past the given address. */
2319 memaddr
= ADDR_BITS_REMOVE (memaddr
);
2320 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
2322 /* Make an attempt to determine if this is a 16-bit function. If
2323 the procedure descriptor exists and the address therein is odd,
2324 it's definitely a 16-bit function. Otherwise, we have to just
2325 guess that if the address passed in is odd, it's 16-bits. */
2327 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : 0;
2329 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : 0;
2331 /* Round down the instruction address to the appropriate boundary. */
2332 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
2334 /* Call the appropriate disassembler based on the target endian-ness. */
2335 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2336 return print_insn_big_mips (memaddr
, info
);
2338 return print_insn_little_mips (memaddr
, info
);
2341 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
2342 counter value to determine whether a 16- or 32-bit breakpoint should be
2343 used. It returns a pointer to a string of bytes that encode a breakpoint
2344 instruction, stores the length of the string to *lenptr, and adjusts pc
2345 (if necessary) to point to the actual memory location where the
2346 breakpoint should be inserted. */
2348 unsigned char *mips_breakpoint_from_pc (pcptr
, lenptr
)
2352 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2354 if (pc_is_mips16 (*pcptr
))
2356 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
2357 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2358 *lenptr
= sizeof(mips16_big_breakpoint
);
2359 return mips16_big_breakpoint
;
2363 static char big_breakpoint
[] = BIG_BREAKPOINT
;
2364 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
2365 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
2367 *lenptr
= sizeof(big_breakpoint
);
2369 if (strcmp (target_shortname
, "mips") == 0)
2370 return idt_big_breakpoint
;
2371 else if (strcmp (target_shortname
, "ddb") == 0
2372 || strcmp (target_shortname
, "pmon") == 0
2373 || strcmp (target_shortname
, "lsi") == 0)
2374 return pmon_big_breakpoint
;
2376 return big_breakpoint
;
2381 if (pc_is_mips16 (*pcptr
))
2383 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
2384 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2385 *lenptr
= sizeof(mips16_little_breakpoint
);
2386 return mips16_little_breakpoint
;
2390 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
2391 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
2392 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
2394 *lenptr
= sizeof(little_breakpoint
);
2396 if (strcmp (target_shortname
, "mips") == 0)
2397 return idt_little_breakpoint
;
2398 else if (strcmp (target_shortname
, "ddb") == 0
2399 || strcmp (target_shortname
, "pmon") == 0
2400 || strcmp (target_shortname
, "lsi") == 0)
2401 return pmon_little_breakpoint
;
2403 return little_breakpoint
;
2408 /* Test whether the PC points to the return instruction at the
2409 end of a function. This implements the ABOUT_TO_RETURN macro. */
2412 mips_about_to_return (pc
)
2415 if (pc_is_mips16 (pc
))
2416 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2417 generates a "jr $ra"; other times it generates code to load
2418 the return address from the stack to an accessible register (such
2419 as $a3), then a "jr" using that register. This second case
2420 is almost impossible to distinguish from an indirect jump
2421 used for switch statements, so we don't even try. */
2422 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2424 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2428 /* If PC is in a mips16 call or return stub, return the address of the target
2429 PC, which is either the callee or the caller. There are several
2430 cases which must be handled:
2432 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
2433 target PC is in $31 ($ra).
2434 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
2435 and the target PC is in $2.
2436 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2437 before the jal instruction, this is effectively a call stub
2438 and the the target PC is in $2. Otherwise this is effectively
2439 a return stub and the target PC is in $18.
2441 See the source code for the stubs in gcc/config/mips/mips16.S for
2444 This function implements the SKIP_TRAMPOLINE_CODE macro.
2452 CORE_ADDR start_addr
;
2454 /* Find the starting address and name of the function containing the PC. */
2455 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2458 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
2459 target PC is in $31 ($ra). */
2460 if (strcmp (name
, "__mips16_ret_sf") == 0
2461 || strcmp (name
, "__mips16_ret_df") == 0)
2462 return read_register (RA_REGNUM
);
2464 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
2466 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
2467 and the target PC is in $2. */
2468 if (name
[19] >= '0' && name
[19] <= '9')
2469 return read_register (2);
2471 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2472 before the jal instruction, this is effectively a call stub
2473 and the the target PC is in $2. Otherwise this is effectively
2474 a return stub and the target PC is in $18. */
2475 else if (name
[19] == 's' || name
[19] == 'd')
2477 if (pc
== start_addr
)
2479 /* Check if the target of the stub is a compiler-generated
2480 stub. Such a stub for a function bar might have a name
2481 like __fn_stub_bar, and might look like this:
2486 la $1,bar (becomes a lui/addiu pair)
2488 So scan down to the lui/addi and extract the target
2489 address from those two instructions. */
2491 CORE_ADDR target_pc
= read_register (2);
2495 /* See if the name of the target function is __fn_stub_*. */
2496 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
2498 if (strncmp (name
, "__fn_stub_", 10) != 0
2499 && strcmp (name
, "etext") != 0
2500 && strcmp (name
, "_etext") != 0)
2503 /* Scan through this _fn_stub_ code for the lui/addiu pair.
2504 The limit on the search is arbitrarily set to 20
2505 instructions. FIXME. */
2506 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
2508 inst
= mips_fetch_instruction (target_pc
);
2509 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
2510 pc
= (inst
<< 16) & 0xffff0000; /* high word */
2511 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
2512 return pc
| (inst
& 0xffff); /* low word */
2515 /* Couldn't find the lui/addui pair, so return stub address. */
2519 /* This is the 'return' part of a call stub. The return
2520 address is in $r18. */
2521 return read_register (18);
2524 return 0; /* not a stub */
2528 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
2529 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
2532 mips_in_call_stub (pc
, name
)
2536 CORE_ADDR start_addr
;
2538 /* Find the starting address of the function containing the PC. If the
2539 caller didn't give us a name, look it up at the same time. */
2540 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
2543 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
2545 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
2546 if (name
[19] >= '0' && name
[19] <= '9')
2548 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2549 before the jal instruction, this is effectively a call stub. */
2550 else if (name
[19] == 's' || name
[19] == 'd')
2551 return pc
== start_addr
;
2554 return 0; /* not a stub */
2558 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
2559 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
2562 mips_in_return_stub (pc
, name
)
2566 CORE_ADDR start_addr
;
2568 /* Find the starting address of the function containing the PC. */
2569 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
2572 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
2573 if (strcmp (name
, "__mips16_ret_sf") == 0
2574 || strcmp (name
, "__mips16_ret_df") == 0)
2577 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
2578 i.e. after the jal instruction, this is effectively a return stub. */
2579 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
2580 && (name
[19] == 's' || name
[19] == 'd')
2581 && pc
!= start_addr
)
2584 return 0; /* not a stub */
2588 /* Return non-zero if the PC is in a library helper function that should
2589 be ignored. This implements the IGNORE_HELPER_CALL macro. */
2592 mips_ignore_helper (pc
)
2597 /* Find the starting address and name of the function containing the PC. */
2598 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
2601 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
2602 that we want to ignore. */
2603 return (strcmp (name
, "__mips16_ret_sf") == 0
2604 || strcmp (name
, "__mips16_ret_df") == 0);
2609 _initialize_mips_tdep ()
2611 struct cmd_list_element
*c
;
2613 tm_print_insn
= gdb_print_insn_mips
;
2615 /* Let the user turn off floating point and set the fence post for
2616 heuristic_proc_start. */
2618 c
= add_set_cmd ("mipsfpu", class_support
, var_string_noescape
,
2619 (char *) &mips_fpu_string
,
2620 "Set use of floating point coprocessor.\n\
2621 Set to `none' to avoid using floating point instructions when calling\n\
2622 functions or dealing with return values. Set to `single' to use only\n\
2623 single precision floating point as on the R4650. Set to `double' for\n\
2624 normal floating point support.",
2626 c
->function
.sfunc
= mips_set_fpu_command
;
2627 c
= add_show_from_set (c
, &showlist
);
2628 c
->function
.sfunc
= mips_show_fpu_command
;
2630 #ifndef MIPS_DEFAULT_FPU_TYPE
2631 mips_fpu
= MIPS_FPU_DOUBLE
;
2632 mips_fpu_string
= strsave ("double");
2634 mips_fpu
= MIPS_DEFAULT_FPU_TYPE
;
2637 case MIPS_FPU_DOUBLE
: mips_fpu_string
= strsave ("double"); break;
2638 case MIPS_FPU_SINGLE
: mips_fpu_string
= strsave ("single"); break;
2639 case MIPS_FPU_NONE
: mips_fpu_string
= strsave ("none"); break;
2643 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
2644 (char *) &tmp_mips_processor_type
,
2645 "Set the type of MIPS processor in use.\n\
2646 Set this to be able to access processor-type-specific registers.\n\
2649 c
->function
.cfunc
= mips_set_processor_type_command
;
2650 c
= add_show_from_set (c
, &showlist
);
2651 c
->function
.cfunc
= mips_show_processor_type_command
;
2653 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
2654 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
2656 /* We really would like to have both "0" and "unlimited" work, but
2657 command.c doesn't deal with that. So make it a var_zinteger
2658 because the user can always use "999999" or some such for unlimited. */
2659 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
2660 (char *) &heuristic_fence_post
,
2662 Set the distance searched for the start of a function.\n\
2663 If you are debugging a stripped executable, GDB needs to search through the\n\
2664 program for the start of a function. This command sets the distance of the\n\
2665 search. The only need to set it is when debugging a stripped executable.",
2667 /* We need to throw away the frame cache when we set this, since it
2668 might change our ability to get backtraces. */
2669 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
2670 add_show_from_set (c
, &showlist
);