1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 static const struct objfile_data
*mips_pdr_data
;
59 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
60 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
62 /* A useful bit in the CP0 status register (PS_REGNUM). */
63 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
64 #define ST0_FR (1 << 26)
66 /* The sizes of floating point registers. */
70 MIPS_FPU_SINGLE_REGSIZE
= 4,
71 MIPS_FPU_DOUBLE_REGSIZE
= 8
75 static const char *mips_abi_string
;
77 static const char *mips_abi_strings
[] = {
88 struct frame_extra_info
90 mips_extra_func_info_t proc_desc
;
94 /* Various MIPS ISA options (related to stack analysis) can be
95 overridden dynamically. Establish an enum/array for managing
98 static const char size_auto
[] = "auto";
99 static const char size_32
[] = "32";
100 static const char size_64
[] = "64";
102 static const char *size_enums
[] = {
109 /* Some MIPS boards don't support floating point while others only
110 support single-precision floating-point operations. */
114 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
115 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
116 MIPS_FPU_NONE
/* No floating point. */
119 #ifndef MIPS_DEFAULT_FPU_TYPE
120 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
122 static int mips_fpu_type_auto
= 1;
123 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
125 static int mips_debug
= 0;
127 /* MIPS specific per-architecture information */
130 /* from the elf header */
134 enum mips_abi mips_abi
;
135 enum mips_abi found_abi
;
136 enum mips_fpu_type mips_fpu_type
;
137 int mips_last_arg_regnum
;
138 int mips_last_fp_arg_regnum
;
139 int default_mask_address_p
;
140 /* Is the target using 64-bit raw integer registers but only
141 storing a left-aligned 32-bit value in each? */
142 int mips64_transfers_32bit_regs_p
;
143 /* Indexes for various registers. IRIX and embedded have
144 different values. This contains the "public" fields. Don't
145 add any that do not need to be public. */
146 const struct mips_regnum
*regnum
;
147 /* Register names table for the current register set. */
148 const char **mips_processor_reg_names
;
151 const struct mips_regnum
*
152 mips_regnum (struct gdbarch
*gdbarch
)
154 return gdbarch_tdep (gdbarch
)->regnum
;
158 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
160 return mips_regnum (gdbarch
)->fp0
+ 12;
163 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
164 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
166 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
168 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
170 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
172 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
173 functions to test, set, or clear bit 0 of addresses. */
176 is_mips16_addr (CORE_ADDR addr
)
182 make_mips16_addr (CORE_ADDR addr
)
188 unmake_mips16_addr (CORE_ADDR addr
)
190 return ((addr
) & ~1);
193 /* Return the contents of register REGNUM as a signed integer. */
196 read_signed_register (int regnum
)
198 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
199 deprecated_read_register_gen (regnum
, buf
);
200 return (extract_signed_integer
201 (buf
, register_size (current_gdbarch
, regnum
)));
205 read_signed_register_pid (int regnum
, ptid_t ptid
)
210 if (ptid_equal (ptid
, inferior_ptid
))
211 return read_signed_register (regnum
);
213 save_ptid
= inferior_ptid
;
215 inferior_ptid
= ptid
;
217 retval
= read_signed_register (regnum
);
219 inferior_ptid
= save_ptid
;
224 /* Return the MIPS ABI associated with GDBARCH. */
226 mips_abi (struct gdbarch
*gdbarch
)
228 return gdbarch_tdep (gdbarch
)->mips_abi
;
232 mips_isa_regsize (struct gdbarch
*gdbarch
)
234 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
235 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
238 /* Return the currently configured (or set) saved register size. */
240 static const char *mips_abi_regsize_string
= size_auto
;
243 mips_abi_regsize (struct gdbarch
*gdbarch
)
245 if (mips_abi_regsize_string
== size_auto
)
246 switch (mips_abi (gdbarch
))
248 case MIPS_ABI_EABI32
:
254 case MIPS_ABI_EABI64
:
256 case MIPS_ABI_UNKNOWN
:
259 internal_error (__FILE__
, __LINE__
, "bad switch");
261 else if (mips_abi_regsize_string
== size_64
)
263 else /* if (mips_abi_regsize_string == size_32) */
267 /* Functions for setting and testing a bit in a minimal symbol that
268 marks it as 16-bit function. The MSB of the minimal symbol's
269 "info" field is used for this purpose.
271 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
272 i.e. refers to a 16-bit function, and sets a "special" bit in a
273 minimal symbol to mark it as a 16-bit function
275 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
278 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
280 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
282 MSYMBOL_INFO (msym
) = (char *)
283 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
284 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
289 msymbol_is_special (struct minimal_symbol
*msym
)
291 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
294 /* XFER a value from the big/little/left end of the register.
295 Depending on the size of the value it might occupy the entire
296 register or just part of it. Make an allowance for this, aligning
297 things accordingly. */
300 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
301 enum bfd_endian endian
, bfd_byte
* in
,
302 const bfd_byte
* out
, int buf_offset
)
305 gdb_assert (reg_num
>= NUM_REGS
);
306 /* Need to transfer the left or right part of the register, based on
307 the targets byte order. */
311 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
313 case BFD_ENDIAN_LITTLE
:
316 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
320 internal_error (__FILE__
, __LINE__
, "bad switch");
323 fprintf_unfiltered (gdb_stderr
,
324 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
325 reg_num
, reg_offset
, buf_offset
, length
);
326 if (mips_debug
&& out
!= NULL
)
329 fprintf_unfiltered (gdb_stdlog
, "out ");
330 for (i
= 0; i
< length
; i
++)
331 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
334 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
337 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
339 if (mips_debug
&& in
!= NULL
)
342 fprintf_unfiltered (gdb_stdlog
, "in ");
343 for (i
= 0; i
< length
; i
++)
344 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
347 fprintf_unfiltered (gdb_stdlog
, "\n");
350 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
351 compatiblity mode. A return value of 1 means that we have
352 physical 64-bit registers, but should treat them as 32-bit registers. */
355 mips2_fp_compat (void)
357 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
359 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
364 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
365 in all the places we deal with FP registers. PR gdb/413. */
366 /* Otherwise check the FR bit in the status register - it controls
367 the FP compatiblity mode. If it is clear we are in compatibility
369 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
376 /* The amount of space reserved on the stack for registers. This is
377 different to MIPS_ABI_REGSIZE as it determines the alignment of
378 data allocated after the registers have run out. */
380 static const char *mips_stack_argsize_string
= size_auto
;
383 mips_stack_argsize (struct gdbarch
*gdbarch
)
385 if (mips_stack_argsize_string
== size_auto
)
386 return mips_abi_regsize (gdbarch
);
387 else if (mips_stack_argsize_string
== size_64
)
389 else /* if (mips_stack_argsize_string == size_32) */
393 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
395 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
396 struct frame_info
*, int);
398 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
400 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
402 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
404 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
405 struct frame_info
*next_frame
,
408 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
409 mips_extra_func_info_t proc_desc
);
411 static struct type
*mips_float_register_type (void);
412 static struct type
*mips_double_register_type (void);
414 /* The list of available "set mips " and "show mips " commands */
416 static struct cmd_list_element
*setmipscmdlist
= NULL
;
417 static struct cmd_list_element
*showmipscmdlist
= NULL
;
419 /* Integer registers 0 thru 31 are handled explicitly by
420 mips_register_name(). Processor specific registers 32 and above
421 are listed in the followign tables. */
424 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
428 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
429 "sr", "lo", "hi", "bad", "cause", "pc",
430 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
431 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
432 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
433 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
434 "fsr", "fir", "" /*"fp" */ , "",
435 "", "", "", "", "", "", "", "",
436 "", "", "", "", "", "", "", "",
439 /* Names of IDT R3041 registers. */
441 static const char *mips_r3041_reg_names
[] = {
442 "sr", "lo", "hi", "bad", "cause", "pc",
443 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
444 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
445 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
446 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
447 "fsr", "fir", "", /*"fp" */ "",
448 "", "", "bus", "ccfg", "", "", "", "",
449 "", "", "port", "cmp", "", "", "epc", "prid",
452 /* Names of tx39 registers. */
454 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
455 "sr", "lo", "hi", "bad", "cause", "pc",
456 "", "", "", "", "", "", "", "",
457 "", "", "", "", "", "", "", "",
458 "", "", "", "", "", "", "", "",
459 "", "", "", "", "", "", "", "",
461 "", "", "", "", "", "", "", "",
462 "", "", "config", "cache", "debug", "depc", "epc", ""
465 /* Names of IRIX registers. */
466 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
467 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
468 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
469 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
470 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
471 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
475 /* Return the name of the register corresponding to REGNO. */
477 mips_register_name (int regno
)
479 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
480 /* GPR names for all ABIs other than n32/n64. */
481 static char *mips_gpr_names
[] = {
482 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
483 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
484 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
485 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
488 /* GPR names for n32 and n64 ABIs. */
489 static char *mips_n32_n64_gpr_names
[] = {
490 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
491 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
492 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
493 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
496 enum mips_abi abi
= mips_abi (current_gdbarch
);
498 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
499 don't make the raw register names visible. */
500 int rawnum
= regno
% NUM_REGS
;
501 if (regno
< NUM_REGS
)
504 /* The MIPS integer registers are always mapped from 0 to 31. The
505 names of the registers (which reflects the conventions regarding
506 register use) vary depending on the ABI. */
507 if (0 <= rawnum
&& rawnum
< 32)
509 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
510 return mips_n32_n64_gpr_names
[rawnum
];
512 return mips_gpr_names
[rawnum
];
514 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
516 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
517 return tdep
->mips_processor_reg_names
[rawnum
- 32];
520 internal_error (__FILE__
, __LINE__
,
521 "mips_register_name: bad register number %d", rawnum
);
524 /* Return the groups that a MIPS register can be categorised into. */
527 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
528 struct reggroup
*reggroup
)
533 int rawnum
= regnum
% NUM_REGS
;
534 int pseudo
= regnum
/ NUM_REGS
;
535 if (reggroup
== all_reggroup
)
537 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
538 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
539 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
540 (gdbarch), as not all architectures are multi-arch. */
541 raw_p
= rawnum
< NUM_REGS
;
542 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
544 if (reggroup
== float_reggroup
)
545 return float_p
&& pseudo
;
546 if (reggroup
== vector_reggroup
)
547 return vector_p
&& pseudo
;
548 if (reggroup
== general_reggroup
)
549 return (!vector_p
&& !float_p
) && pseudo
;
550 /* Save the pseudo registers. Need to make certain that any code
551 extracting register values from a saved register cache also uses
553 if (reggroup
== save_reggroup
)
554 return raw_p
&& pseudo
;
555 /* Restore the same pseudo register. */
556 if (reggroup
== restore_reggroup
)
557 return raw_p
&& pseudo
;
561 /* Map the symbol table registers which live in the range [1 *
562 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
563 registers. Take care of alignment and size problems. */
566 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
567 int cookednum
, void *buf
)
569 int rawnum
= cookednum
% NUM_REGS
;
570 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
571 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
572 regcache_raw_read (regcache
, rawnum
, buf
);
573 else if (register_size (gdbarch
, rawnum
) >
574 register_size (gdbarch
, cookednum
))
576 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
577 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
578 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
580 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
583 internal_error (__FILE__
, __LINE__
, "bad register size");
587 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
588 struct regcache
*regcache
, int cookednum
,
591 int rawnum
= cookednum
% NUM_REGS
;
592 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
593 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
594 regcache_raw_write (regcache
, rawnum
, buf
);
595 else if (register_size (gdbarch
, rawnum
) >
596 register_size (gdbarch
, cookednum
))
598 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
599 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
600 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
602 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
605 internal_error (__FILE__
, __LINE__
, "bad register size");
608 /* Table to translate MIPS16 register field to actual register number. */
609 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
611 /* Heuristic_proc_start may hunt through the text section for a long
612 time across a 2400 baud serial line. Allows the user to limit this
615 static unsigned int heuristic_fence_post
= 0;
617 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
618 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
619 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
620 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
621 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
622 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
623 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
624 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
625 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
626 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
627 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
628 this will corrupt pdr.iline. Fortunately we don't use it. */
629 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
630 #define _PROC_MAGIC_ 0x0F0F0F0F
631 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
632 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
634 struct linked_proc_info
636 struct mips_extra_func_info info
;
637 struct linked_proc_info
*next
;
639 *linked_proc_desc_table
= NULL
;
641 /* Number of bytes of storage in the actual machine representation for
642 register N. NOTE: This defines the pseudo register type so need to
643 rebuild the architecture vector. */
645 static int mips64_transfers_32bit_regs_p
= 0;
648 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
649 struct cmd_list_element
*c
)
651 struct gdbarch_info info
;
652 gdbarch_info_init (&info
);
653 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
654 instead of relying on globals. Doing that would let generic code
655 handle the search for this specific architecture. */
656 if (!gdbarch_update_p (info
))
658 mips64_transfers_32bit_regs_p
= 0;
659 error ("32-bit compatibility mode not supported");
663 /* Convert to/from a register and the corresponding memory value. */
666 mips_convert_register_p (int regnum
, struct type
*type
)
668 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
669 && register_size (current_gdbarch
, regnum
) == 4
670 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
671 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
672 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
676 mips_register_to_value (struct frame_info
*frame
, int regnum
,
677 struct type
*type
, void *to
)
679 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
680 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
684 mips_value_to_register (struct frame_info
*frame
, int regnum
,
685 struct type
*type
, const void *from
)
687 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
688 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
691 /* Return the GDB type object for the "standard" data type of data in
695 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
697 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
698 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
699 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
701 /* The floating-point registers raw, or cooked, always match
702 mips_isa_regsize(), and also map 1:1, byte for byte. */
703 switch (gdbarch_byte_order (gdbarch
))
706 if (mips_isa_regsize (gdbarch
) == 4)
707 return builtin_type_ieee_single_big
;
709 return builtin_type_ieee_double_big
;
710 case BFD_ENDIAN_LITTLE
:
711 if (mips_isa_regsize (gdbarch
) == 4)
712 return builtin_type_ieee_single_little
;
714 return builtin_type_ieee_double_little
;
715 case BFD_ENDIAN_UNKNOWN
:
717 internal_error (__FILE__
, __LINE__
, "bad switch");
720 else if (regnum
< NUM_REGS
)
722 /* The raw or ISA registers. These are all sized according to
724 if (mips_isa_regsize (gdbarch
) == 4)
725 return builtin_type_int32
;
727 return builtin_type_int64
;
731 /* The cooked or ABI registers. These are sized according to
732 the ABI (with a few complications). */
733 if (regnum
>= (NUM_REGS
734 + mips_regnum (current_gdbarch
)->fp_control_status
)
735 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
736 /* The pseudo/cooked view of the embedded registers is always
737 32-bit. The raw view is handled below. */
738 return builtin_type_int32
;
739 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
740 /* The target, while possibly using a 64-bit register buffer,
741 is only transfering 32-bits of each integer register.
742 Reflect this in the cooked/pseudo (ABI) register value. */
743 return builtin_type_int32
;
744 else if (mips_abi_regsize (gdbarch
) == 4)
745 /* The ABI is restricted to 32-bit registers (the ISA could be
747 return builtin_type_int32
;
750 return builtin_type_int64
;
754 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
759 return read_signed_register (SP_REGNUM
);
762 /* Should the upper word of 64-bit addresses be zeroed? */
763 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
766 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
768 switch (mask_address_var
)
770 case AUTO_BOOLEAN_TRUE
:
772 case AUTO_BOOLEAN_FALSE
:
775 case AUTO_BOOLEAN_AUTO
:
776 return tdep
->default_mask_address_p
;
778 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
784 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
786 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
787 switch (mask_address_var
)
789 case AUTO_BOOLEAN_TRUE
:
790 printf_filtered ("The 32 bit mips address mask is enabled\n");
792 case AUTO_BOOLEAN_FALSE
:
793 printf_filtered ("The 32 bit mips address mask is disabled\n");
795 case AUTO_BOOLEAN_AUTO
:
797 ("The 32 bit address mask is set automatically. Currently %s\n",
798 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
801 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
806 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
809 pc_is_mips16 (bfd_vma memaddr
)
811 struct minimal_symbol
*sym
;
813 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
814 if (is_mips16_addr (memaddr
))
817 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
818 the high bit of the info field. Use this to decide if the function is
819 MIPS16 or normal MIPS. */
820 sym
= lookup_minimal_symbol_by_pc (memaddr
);
822 return msymbol_is_special (sym
);
827 /* MIPS believes that the PC has a sign extended value. Perhaphs the
828 all registers should be sign extended for simplicity? */
831 mips_read_pc (ptid_t ptid
)
833 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
837 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
839 return frame_unwind_register_signed (next_frame
,
840 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
843 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
844 dummy frame. The frame ID's base needs to match the TOS value
845 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
848 static struct frame_id
849 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
851 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ SP_REGNUM
),
852 frame_pc_unwind (next_frame
));
856 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
858 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
861 /* This returns the PC of the first inst after the prologue. If we can't
862 find the prologue, then return 0. */
865 after_prologue (CORE_ADDR pc
, mips_extra_func_info_t proc_desc
)
867 struct symtab_and_line sal
;
868 CORE_ADDR func_addr
, func_end
;
870 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
871 to read the stack pointer from the current machine state, because
872 the current machine state has nothing to do with the information
873 we need from the proc_desc; and the process may or may not exist
876 proc_desc
= find_proc_desc (pc
, NULL
, 0);
880 /* If function is frameless, then we need to do it the hard way. I
881 strongly suspect that frameless always means prologueless... */
882 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
883 && PROC_FRAME_OFFSET (proc_desc
) == 0)
887 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
888 return 0; /* Unknown */
890 sal
= find_pc_line (func_addr
, 0);
892 if (sal
.end
< func_end
)
895 /* The line after the prologue is after the end of the function. In this
896 case, tell the caller to find the prologue the hard way. */
901 /* Decode a MIPS32 instruction that saves a register in the stack, and
902 set the appropriate bit in the general register mask or float register mask
903 to indicate which register is saved. This is a helper function
904 for mips_find_saved_regs. */
907 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
908 unsigned long *float_mask
)
912 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
913 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
914 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
916 /* It might be possible to use the instruction to
917 find the offset, rather than the code below which
918 is based on things being in a certain order in the
919 frame, but figuring out what the instruction's offset
920 is relative to might be a little tricky. */
921 reg
= (inst
& 0x001f0000) >> 16;
922 *gen_mask
|= (1 << reg
);
924 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
925 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
926 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
929 reg
= ((inst
& 0x001f0000) >> 16);
930 *float_mask
|= (1 << reg
);
934 /* Decode a MIPS16 instruction that saves a register in the stack, and
935 set the appropriate bit in the general register or float register mask
936 to indicate which register is saved. This is a helper function
937 for mips_find_saved_regs. */
940 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
942 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
944 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
945 *gen_mask
|= (1 << reg
);
947 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
949 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
950 *gen_mask
|= (1 << reg
);
952 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
953 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
954 *gen_mask
|= (1 << RA_REGNUM
);
958 /* Fetch and return instruction from the specified location. If the PC
959 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
962 mips_fetch_instruction (CORE_ADDR addr
)
964 char buf
[MIPS_INSTLEN
];
968 if (pc_is_mips16 (addr
))
970 instlen
= MIPS16_INSTLEN
;
971 addr
= unmake_mips16_addr (addr
);
974 instlen
= MIPS_INSTLEN
;
975 status
= read_memory_nobpt (addr
, buf
, instlen
);
977 memory_error (status
, addr
);
978 return extract_unsigned_integer (buf
, instlen
);
982 mips16_fetch_instruction (CORE_ADDR addr
)
984 char buf
[MIPS_INSTLEN
];
988 instlen
= MIPS16_INSTLEN
;
989 addr
= unmake_mips16_addr (addr
);
990 status
= read_memory_nobpt (addr
, buf
, instlen
);
992 memory_error (status
, addr
);
993 return extract_unsigned_integer (buf
, instlen
);
997 mips32_fetch_instruction (CORE_ADDR addr
)
999 char buf
[MIPS_INSTLEN
];
1002 instlen
= MIPS_INSTLEN
;
1003 status
= read_memory_nobpt (addr
, buf
, instlen
);
1005 memory_error (status
, addr
);
1006 return extract_unsigned_integer (buf
, instlen
);
1010 /* These the fields of 32 bit mips instructions */
1011 #define mips32_op(x) (x >> 26)
1012 #define itype_op(x) (x >> 26)
1013 #define itype_rs(x) ((x >> 21) & 0x1f)
1014 #define itype_rt(x) ((x >> 16) & 0x1f)
1015 #define itype_immediate(x) (x & 0xffff)
1017 #define jtype_op(x) (x >> 26)
1018 #define jtype_target(x) (x & 0x03ffffff)
1020 #define rtype_op(x) (x >> 26)
1021 #define rtype_rs(x) ((x >> 21) & 0x1f)
1022 #define rtype_rt(x) ((x >> 16) & 0x1f)
1023 #define rtype_rd(x) ((x >> 11) & 0x1f)
1024 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1025 #define rtype_funct(x) (x & 0x3f)
1028 mips32_relative_offset (unsigned long inst
)
1031 x
= itype_immediate (inst
);
1032 if (x
& 0x8000) /* sign bit set */
1034 x
|= 0xffff0000; /* sign extension */
1040 /* Determine whate to set a single step breakpoint while considering
1041 branch prediction */
1043 mips32_next_pc (CORE_ADDR pc
)
1047 inst
= mips_fetch_instruction (pc
);
1048 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1050 if (itype_op (inst
) >> 2 == 5)
1051 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1053 op
= (itype_op (inst
) & 0x03);
1063 goto greater_branch
;
1068 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1069 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1071 int tf
= itype_rt (inst
) & 0x01;
1072 int cnum
= itype_rt (inst
) >> 2;
1074 read_signed_register (mips_regnum (current_gdbarch
)->
1076 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1078 if (((cond
>> cnum
) & 0x01) == tf
)
1079 pc
+= mips32_relative_offset (inst
) + 4;
1084 pc
+= 4; /* Not a branch, next instruction is easy */
1087 { /* This gets way messy */
1089 /* Further subdivide into SPECIAL, REGIMM and other */
1090 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1092 case 0: /* SPECIAL */
1093 op
= rtype_funct (inst
);
1098 /* Set PC to that address */
1099 pc
= read_signed_register (rtype_rs (inst
));
1105 break; /* end SPECIAL */
1106 case 1: /* REGIMM */
1108 op
= itype_rt (inst
); /* branch condition */
1113 case 16: /* BLTZAL */
1114 case 18: /* BLTZALL */
1116 if (read_signed_register (itype_rs (inst
)) < 0)
1117 pc
+= mips32_relative_offset (inst
) + 4;
1119 pc
+= 8; /* after the delay slot */
1123 case 17: /* BGEZAL */
1124 case 19: /* BGEZALL */
1125 if (read_signed_register (itype_rs (inst
)) >= 0)
1126 pc
+= mips32_relative_offset (inst
) + 4;
1128 pc
+= 8; /* after the delay slot */
1130 /* All of the other instructions in the REGIMM category */
1135 break; /* end REGIMM */
1140 reg
= jtype_target (inst
) << 2;
1141 /* Upper four bits get never changed... */
1142 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1145 /* FIXME case JALX : */
1148 reg
= jtype_target (inst
) << 2;
1149 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1150 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1152 break; /* The new PC will be alternate mode */
1153 case 4: /* BEQ, BEQL */
1155 if (read_signed_register (itype_rs (inst
)) ==
1156 read_signed_register (itype_rt (inst
)))
1157 pc
+= mips32_relative_offset (inst
) + 4;
1161 case 5: /* BNE, BNEL */
1163 if (read_signed_register (itype_rs (inst
)) !=
1164 read_signed_register (itype_rt (inst
)))
1165 pc
+= mips32_relative_offset (inst
) + 4;
1169 case 6: /* BLEZ, BLEZL */
1170 if (read_signed_register (itype_rs (inst
) <= 0))
1171 pc
+= mips32_relative_offset (inst
) + 4;
1177 greater_branch
: /* BGTZ, BGTZL */
1178 if (read_signed_register (itype_rs (inst
) > 0))
1179 pc
+= mips32_relative_offset (inst
) + 4;
1186 } /* mips32_next_pc */
1188 /* Decoding the next place to set a breakpoint is irregular for the
1189 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1190 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1191 We dont want to set a single step instruction on the extend instruction
1195 /* Lots of mips16 instruction formats */
1196 /* Predicting jumps requires itype,ritype,i8type
1197 and their extensions extItype,extritype,extI8type
1199 enum mips16_inst_fmts
1201 itype
, /* 0 immediate 5,10 */
1202 ritype
, /* 1 5,3,8 */
1203 rrtype
, /* 2 5,3,3,5 */
1204 rritype
, /* 3 5,3,3,5 */
1205 rrrtype
, /* 4 5,3,3,3,2 */
1206 rriatype
, /* 5 5,3,3,1,4 */
1207 shifttype
, /* 6 5,3,3,3,2 */
1208 i8type
, /* 7 5,3,8 */
1209 i8movtype
, /* 8 5,3,3,5 */
1210 i8mov32rtype
, /* 9 5,3,5,3 */
1211 i64type
, /* 10 5,3,8 */
1212 ri64type
, /* 11 5,3,3,5 */
1213 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1214 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1215 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1216 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1217 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1218 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1219 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1220 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1221 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1222 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1224 /* I am heaping all the fields of the formats into one structure and
1225 then, only the fields which are involved in instruction extension */
1229 unsigned int regx
; /* Function in i8 type */
1234 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1235 for the bits which make up the immediatate extension. */
1238 extended_offset (unsigned int extension
)
1241 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1243 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1245 value
|= extension
& 0x01f; /* extract 4:0 */
1249 /* Only call this function if you know that this is an extendable
1250 instruction, It wont malfunction, but why make excess remote memory references?
1251 If the immediate operands get sign extended or somthing, do it after
1252 the extension is performed.
1254 /* FIXME: Every one of these cases needs to worry about sign extension
1255 when the offset is to be used in relative addressing */
1259 fetch_mips_16 (CORE_ADDR pc
)
1262 pc
&= 0xfffffffe; /* clear the low order bit */
1263 target_read_memory (pc
, buf
, 2);
1264 return extract_unsigned_integer (buf
, 2);
1268 unpack_mips16 (CORE_ADDR pc
,
1269 unsigned int extension
,
1271 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1276 switch (insn_format
)
1283 value
= extended_offset (extension
);
1284 value
= value
<< 11; /* rom for the original value */
1285 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1289 value
= inst
& 0x7ff;
1290 /* FIXME : Consider sign extension */
1299 { /* A register identifier and an offset */
1300 /* Most of the fields are the same as I type but the
1301 immediate value is of a different length */
1305 value
= extended_offset (extension
);
1306 value
= value
<< 8; /* from the original instruction */
1307 value
|= inst
& 0xff; /* eleven bits from instruction */
1308 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1309 if (value
& 0x4000) /* test the sign bit , bit 26 */
1311 value
&= ~0x3fff; /* remove the sign bit */
1317 value
= inst
& 0xff; /* 8 bits */
1318 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1319 /* FIXME: Do sign extension , this format needs it */
1320 if (value
& 0x80) /* THIS CONFUSES ME */
1322 value
&= 0xef; /* remove the sign bit */
1332 unsigned long value
;
1333 unsigned int nexthalf
;
1334 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1335 value
= value
<< 16;
1336 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1344 internal_error (__FILE__
, __LINE__
, "bad switch");
1346 upk
->offset
= offset
;
1353 add_offset_16 (CORE_ADDR pc
, int offset
)
1355 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1359 extended_mips16_next_pc (CORE_ADDR pc
,
1360 unsigned int extension
, unsigned int insn
)
1362 int op
= (insn
>> 11);
1365 case 2: /* Branch */
1368 struct upk_mips16 upk
;
1369 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1370 offset
= upk
.offset
;
1376 pc
+= (offset
<< 1) + 2;
1379 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1381 struct upk_mips16 upk
;
1382 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1383 pc
= add_offset_16 (pc
, upk
.offset
);
1384 if ((insn
>> 10) & 0x01) /* Exchange mode */
1385 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1392 struct upk_mips16 upk
;
1394 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1395 reg
= read_signed_register (upk
.regx
);
1397 pc
+= (upk
.offset
<< 1) + 2;
1404 struct upk_mips16 upk
;
1406 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1407 reg
= read_signed_register (upk
.regx
);
1409 pc
+= (upk
.offset
<< 1) + 2;
1414 case 12: /* I8 Formats btez btnez */
1416 struct upk_mips16 upk
;
1418 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1419 /* upk.regx contains the opcode */
1420 reg
= read_signed_register (24); /* Test register is 24 */
1421 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1422 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1423 /* pc = add_offset_16(pc,upk.offset) ; */
1424 pc
+= (upk
.offset
<< 1) + 2;
1429 case 29: /* RR Formats JR, JALR, JALR-RA */
1431 struct upk_mips16 upk
;
1432 /* upk.fmt = rrtype; */
1437 upk
.regx
= (insn
>> 8) & 0x07;
1438 upk
.regy
= (insn
>> 5) & 0x07;
1446 break; /* Function return instruction */
1452 break; /* BOGUS Guess */
1454 pc
= read_signed_register (reg
);
1461 /* This is an instruction extension. Fetch the real instruction
1462 (which follows the extension) and decode things based on
1466 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1479 mips16_next_pc (CORE_ADDR pc
)
1481 unsigned int insn
= fetch_mips_16 (pc
);
1482 return extended_mips16_next_pc (pc
, 0, insn
);
1485 /* The mips_next_pc function supports single_step when the remote
1486 target monitor or stub is not developed enough to do a single_step.
1487 It works by decoding the current instruction and predicting where a
1488 branch will go. This isnt hard because all the data is available.
1489 The MIPS32 and MIPS16 variants are quite different */
1491 mips_next_pc (CORE_ADDR pc
)
1494 return mips16_next_pc (pc
);
1496 return mips32_next_pc (pc
);
1499 struct mips_frame_cache
1502 struct trad_frame_saved_reg
*saved_regs
;
1506 static struct mips_frame_cache
*
1507 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1509 mips_extra_func_info_t proc_desc
;
1510 struct mips_frame_cache
*cache
;
1511 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1512 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1513 /* r0 bit means kernel trap */
1515 /* What registers have been saved? Bitmasks. */
1516 unsigned long gen_mask
, float_mask
;
1518 if ((*this_cache
) != NULL
)
1519 return (*this_cache
);
1520 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1521 (*this_cache
) = cache
;
1522 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1524 /* Get the mdebug proc descriptor. */
1525 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
, 1);
1526 if (proc_desc
== NULL
)
1527 /* I'm not sure how/whether this can happen. Normally when we
1528 can't find a proc_desc, we "synthesize" one using
1529 heuristic_proc_desc and set the saved_regs right away. */
1532 /* Extract the frame's base. */
1533 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1534 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1536 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1537 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1538 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1540 /* In any frame other than the innermost or a frame interrupted by a
1541 signal, we assume that all registers have been saved. This
1542 assumes that all register saves in a function happen before the
1543 first function call. */
1544 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1545 /* Not sure exactly what kernel_trap means, but if it means the
1546 kernel saves the registers without a prologue doing it, we
1547 better not examine the prologue to see whether registers
1548 have been saved yet. */
1551 /* We need to figure out whether the registers that the
1552 proc_desc claims are saved have been saved yet. */
1556 /* Bitmasks; set if we have found a save for the register. */
1557 unsigned long gen_save_found
= 0;
1558 unsigned long float_save_found
= 0;
1561 /* If the address is odd, assume this is MIPS16 code. */
1562 addr
= PROC_LOW_ADDR (proc_desc
);
1563 mips16
= pc_is_mips16 (addr
);
1565 /* Scan through this function's instructions preceding the
1566 current PC, and look for those that save registers. */
1567 while (addr
< frame_pc_unwind (next_frame
))
1571 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1573 addr
+= MIPS16_INSTLEN
;
1577 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1578 &gen_save_found
, &float_save_found
);
1579 addr
+= MIPS_INSTLEN
;
1582 gen_mask
= gen_save_found
;
1583 float_mask
= float_save_found
;
1586 /* Fill in the offsets for the registers which gen_mask says were
1589 CORE_ADDR reg_position
= (cache
->base
1590 + PROC_REG_OFFSET (proc_desc
));
1592 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1593 if (gen_mask
& 0x80000000)
1595 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1596 reg_position
-= mips_abi_regsize (gdbarch
);
1600 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1601 order of that normally used by gcc. Therefore, we have to fetch
1602 the first instruction of the function, and if it's an entry
1603 instruction that saves $s0 or $s1, correct their saved addresses. */
1604 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1606 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1607 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1611 int sreg_count
= (inst
>> 6) & 3;
1613 /* Check if the ra register was pushed on the stack. */
1614 CORE_ADDR reg_position
= (cache
->base
1615 + PROC_REG_OFFSET (proc_desc
));
1617 reg_position
-= mips_abi_regsize (gdbarch
);
1619 /* Check if the s0 and s1 registers were pushed on the
1621 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1623 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1625 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1626 reg_position
-= mips_abi_regsize (gdbarch
);
1631 /* Fill in the offsets for the registers which float_mask says were
1634 CORE_ADDR reg_position
= (cache
->base
1635 + PROC_FREG_OFFSET (proc_desc
));
1637 /* Fill in the offsets for the float registers which float_mask
1639 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1640 if (float_mask
& 0x80000000)
1642 if (mips_abi_regsize (gdbarch
) == 4
1643 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1645 /* On a big endian 32 bit ABI, floating point registers
1646 are paired to form doubles such that the most
1647 significant part is in $f[N+1] and the least
1648 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1649 registers are also spilled as a pair and stored as a
1652 When little-endian the least significant part is
1653 stored first leading to the memory order $f[N] and
1656 Unfortunately, when big-endian the most significant
1657 part of the double is stored first, and the least
1658 significant is stored second. This leads to the
1659 registers being ordered in memory as firt $f[N+1] and
1662 For the big-endian case make certain that the
1663 addresses point at the correct (swapped) locations
1664 $f[N] and $f[N+1] pair (keep in mind that
1665 reg_position is decremented each time through the
1668 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1669 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1671 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1672 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1675 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1676 .addr
= reg_position
;
1677 reg_position
-= mips_abi_regsize (gdbarch
);
1680 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1681 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1684 /* SP_REGNUM, contains the value and not the address. */
1685 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ SP_REGNUM
, cache
->base
);
1687 return (*this_cache
);
1691 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1692 struct frame_id
*this_id
)
1694 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1696 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1700 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1702 int regnum
, int *optimizedp
,
1703 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1704 int *realnump
, void *valuep
)
1706 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1708 trad_frame_prev_register (next_frame
, info
->saved_regs
, regnum
,
1709 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1712 static const struct frame_unwind mips_mdebug_frame_unwind
=
1715 mips_mdebug_frame_this_id
,
1716 mips_mdebug_frame_prev_register
1719 static const struct frame_unwind
*
1720 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1722 return &mips_mdebug_frame_unwind
;
1726 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1729 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1734 static const struct frame_base mips_mdebug_frame_base
= {
1735 &mips_mdebug_frame_unwind
,
1736 mips_mdebug_frame_base_address
,
1737 mips_mdebug_frame_base_address
,
1738 mips_mdebug_frame_base_address
1741 static const struct frame_base
*
1742 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1744 return &mips_mdebug_frame_base
;
1748 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1750 /* Always a pseudo. */
1751 gdb_assert (regno
>= NUM_REGS
);
1755 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1758 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1759 /* The SP_REGNUM is special, its value is stored in saved_regs.
1760 In fact, it is so special that it can even only be fetched
1761 using a raw register number! Once this code as been converted
1762 to frame-unwind the problem goes away. */
1763 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1765 return frame_unwind_register_signed (fi
, regno
);
1769 /* mips_addr_bits_remove - remove useless address bits */
1772 mips_addr_bits_remove (CORE_ADDR addr
)
1774 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1775 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
1776 /* This hack is a work-around for existing boards using PMON, the
1777 simulator, and any other 64-bit targets that doesn't have true
1778 64-bit addressing. On these targets, the upper 32 bits of
1779 addresses are ignored by the hardware. Thus, the PC or SP are
1780 likely to have been sign extended to all 1s by instruction
1781 sequences that load 32-bit addresses. For example, a typical
1782 piece of code that loads an address is this:
1784 lui $r2, <upper 16 bits>
1785 ori $r2, <lower 16 bits>
1787 But the lui sign-extends the value such that the upper 32 bits
1788 may be all 1s. The workaround is simply to mask off these
1789 bits. In the future, gcc may be changed to support true 64-bit
1790 addressing, and this masking will have to be disabled. */
1791 return addr
&= 0xffffffffUL
;
1796 /* mips_software_single_step() is called just before we want to resume
1797 the inferior, if we want to single-step it but there is no hardware
1798 or kernel single-step support (MIPS on GNU/Linux for example). We find
1799 the target of the coming instruction and breakpoint it.
1801 single_step is also called just after the inferior stops. If we had
1802 set up a simulated single-step, we undo our damage. */
1805 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1807 static CORE_ADDR next_pc
;
1808 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1809 static binsn_quantum break_mem
;
1812 if (insert_breakpoints_p
)
1814 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
1815 next_pc
= mips_next_pc (pc
);
1817 target_insert_breakpoint (next_pc
, break_mem
);
1820 target_remove_breakpoint (next_pc
, break_mem
);
1823 static struct mips_extra_func_info temp_proc_desc
;
1825 /* This hack will go away once the get_prev_frame() code has been
1826 modified to set the frame's type first. That is BEFORE init extra
1827 frame info et.al. is called. This is because it will become
1828 possible to skip the init extra info call for sigtramp and dummy
1830 static CORE_ADDR
*temp_saved_regs
;
1832 /* Set a register's saved stack address in temp_saved_regs. If an
1833 address has already been set for this register, do nothing; this
1834 way we will only recognize the first save of a given register in a
1837 For simplicity, save the address in both [0 .. NUM_REGS) and
1838 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1839 is used as it is only second range (the ABI instead of ISA
1840 registers) that comes into play when finding saved registers in a
1844 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
1846 if (saved_regs
[regno
] == 0)
1848 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
1849 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
1854 /* Test whether the PC points to the return instruction at the
1855 end of a function. */
1858 mips_about_to_return (CORE_ADDR pc
)
1860 if (pc_is_mips16 (pc
))
1861 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1862 generates a "jr $ra"; other times it generates code to load
1863 the return address from the stack to an accessible register (such
1864 as $a3), then a "jr" using that register. This second case
1865 is almost impossible to distinguish from an indirect jump
1866 used for switch statements, so we don't even try. */
1867 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1869 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1873 /* This fencepost looks highly suspicious to me. Removing it also
1874 seems suspicious as it could affect remote debugging across serial
1878 heuristic_proc_start (CORE_ADDR pc
)
1885 pc
= ADDR_BITS_REMOVE (pc
);
1887 fence
= start_pc
- heuristic_fence_post
;
1891 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
1892 fence
= VM_MIN_ADDRESS
;
1894 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1896 /* search back for previous return */
1897 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1898 if (start_pc
< fence
)
1900 /* It's not clear to me why we reach this point when
1901 stop_soon, but with this test, at least we
1902 don't print out warnings for every child forked (eg, on
1903 decstation). 22apr93 rich@cygnus.com. */
1904 if (stop_soon
== NO_STOP_QUIETLY
)
1906 static int blurb_printed
= 0;
1909 ("GDB can't find the start of the function at 0x%s.",
1914 /* This actually happens frequently in embedded
1915 development, when you first connect to a board
1916 and your stack pointer and pc are nowhere in
1917 particular. This message needs to give people
1918 in that situation enough information to
1919 determine that it's no big deal. */
1920 printf_filtered ("\n\
1921 GDB is unable to find the start of the function at 0x%s\n\
1922 and thus can't determine the size of that function's stack frame.\n\
1923 This means that GDB may be unable to access that stack frame, or\n\
1924 the frames below it.\n\
1925 This problem is most likely caused by an invalid program counter or\n\
1927 However, if you think GDB should simply search farther back\n\
1928 from 0x%s for code which looks like the beginning of a\n\
1929 function, you can increase the range of the search using the `set\n\
1930 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
1937 else if (pc_is_mips16 (start_pc
))
1939 unsigned short inst
;
1941 /* On MIPS16, any one of the following is likely to be the
1942 start of a function:
1946 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1947 inst
= mips_fetch_instruction (start_pc
);
1948 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1949 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1950 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1951 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1953 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1954 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1959 else if (mips_about_to_return (start_pc
))
1961 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1968 /* Fetch the immediate value from a MIPS16 instruction.
1969 If the previous instruction was an EXTEND, use it to extend
1970 the upper bits of the immediate value. This is a helper function
1971 for mips16_heuristic_proc_desc. */
1974 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1975 unsigned short inst
, /* current instruction */
1976 int nbits
, /* number of bits in imm field */
1977 int scale
, /* scale factor to be applied to imm */
1978 int is_signed
) /* is the imm field signed? */
1982 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1984 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1985 if (offset
& 0x8000) /* check for negative extend */
1986 offset
= 0 - (0x10000 - (offset
& 0xffff));
1987 return offset
| (inst
& 0x1f);
1991 int max_imm
= 1 << nbits
;
1992 int mask
= max_imm
- 1;
1993 int sign_bit
= max_imm
>> 1;
1995 offset
= inst
& mask
;
1996 if (is_signed
&& (offset
& sign_bit
))
1997 offset
= 0 - (max_imm
- offset
);
1998 return offset
* scale
;
2003 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2004 stream from start_pc to limit_pc. */
2007 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2008 struct frame_info
*next_frame
, CORE_ADDR sp
)
2011 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2012 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2013 unsigned inst
= 0; /* current instruction */
2014 unsigned entry_inst
= 0; /* the entry instruction */
2016 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2018 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2019 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2021 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2023 /* Save the previous instruction. If it's an EXTEND, we'll extract
2024 the immediate offset extension from it in mips16_get_imm. */
2027 /* Fetch and decode the instruction. */
2028 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2029 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2030 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2032 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2033 if (offset
< 0) /* negative stack adjustment? */
2034 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2036 /* Exit loop if a positive stack adjustment is found, which
2037 usually means that the stack cleanup code in the function
2038 epilogue is reached. */
2041 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2043 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2044 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2045 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2046 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2048 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2050 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2051 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2052 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2053 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2055 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2057 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2058 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2059 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2061 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2063 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2064 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2065 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2067 else if (inst
== 0x673d) /* move $s1, $sp */
2070 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2072 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2074 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2075 frame_addr
= sp
+ offset
;
2076 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2077 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2079 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2081 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2082 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2083 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2084 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2086 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2088 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2089 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2090 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2091 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2093 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2094 entry_inst
= inst
; /* save for later processing */
2095 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2096 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2099 /* The entry instruction is typically the first instruction in a function,
2100 and it stores registers at offsets relative to the value of the old SP
2101 (before the prologue). But the value of the sp parameter to this
2102 function is the new SP (after the prologue has been executed). So we
2103 can't calculate those offsets until we've seen the entire prologue,
2104 and can calculate what the old SP must have been. */
2105 if (entry_inst
!= 0)
2107 int areg_count
= (entry_inst
>> 8) & 7;
2108 int sreg_count
= (entry_inst
>> 6) & 3;
2110 /* The entry instruction always subtracts 32 from the SP. */
2111 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2113 /* Now we can calculate what the SP must have been at the
2114 start of the function prologue. */
2115 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2117 /* Check if a0-a3 were saved in the caller's argument save area. */
2118 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2120 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2121 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2122 offset
+= mips_abi_regsize (current_gdbarch
);
2125 /* Check if the ra register was pushed on the stack. */
2127 if (entry_inst
& 0x20)
2129 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2130 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2131 offset
-= mips_abi_regsize (current_gdbarch
);
2134 /* Check if the s0 and s1 registers were pushed on the stack. */
2135 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2137 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2138 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2139 offset
-= mips_abi_regsize (current_gdbarch
);
2145 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2146 struct frame_info
*next_frame
, CORE_ADDR sp
)
2149 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2151 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2152 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2153 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2154 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2155 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2157 unsigned long inst
, high_word
, low_word
;
2160 /* Fetch the instruction. */
2161 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2163 /* Save some code by pre-extracting some useful fields. */
2164 high_word
= (inst
>> 16) & 0xffff;
2165 low_word
= inst
& 0xffff;
2166 reg
= high_word
& 0x1f;
2168 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2169 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2170 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2172 if (low_word
& 0x8000) /* negative stack adjustment? */
2173 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2175 /* Exit loop if a positive stack adjustment is found, which
2176 usually means that the stack cleanup code in the function
2177 epilogue is reached. */
2180 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2182 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2183 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2185 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2187 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and
2189 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2190 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2192 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2194 /* Old gcc frame, r30 is virtual frame pointer. */
2195 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2196 frame_addr
= sp
+ low_word
;
2197 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2199 unsigned alloca_adjust
;
2200 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2201 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2202 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2203 if (alloca_adjust
> 0)
2205 /* FP > SP + frame_size. This may be because
2206 * of an alloca or somethings similar.
2207 * Fix sp to "pre-alloca" value, and try again.
2209 sp
+= alloca_adjust
;
2214 /* move $30,$sp. With different versions of gas this will be either
2215 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2216 Accept any one of these. */
2217 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2219 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2220 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2222 unsigned alloca_adjust
;
2223 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2224 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2225 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2226 if (alloca_adjust
> 0)
2228 /* FP > SP + frame_size. This may be because
2229 * of an alloca or somethings similar.
2230 * Fix sp to "pre-alloca" value, and try again.
2232 sp
+= alloca_adjust
;
2237 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2239 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2240 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2245 static mips_extra_func_info_t
2246 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2247 struct frame_info
*next_frame
, int cur_frame
)
2252 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2258 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2259 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2260 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2261 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2262 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2263 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2265 if (start_pc
+ 200 < limit_pc
)
2266 limit_pc
= start_pc
+ 200;
2267 if (pc_is_mips16 (start_pc
))
2268 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2270 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2271 return &temp_proc_desc
;
2274 struct mips_objfile_private
2280 /* Global used to communicate between non_heuristic_proc_desc and
2281 compare_pdr_entries within qsort (). */
2282 static bfd
*the_bfd
;
2285 compare_pdr_entries (const void *a
, const void *b
)
2287 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2288 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2292 else if (lhs
== rhs
)
2298 static mips_extra_func_info_t
2299 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2301 CORE_ADDR startaddr
;
2302 mips_extra_func_info_t proc_desc
;
2303 struct block
*b
= block_for_pc (pc
);
2305 struct obj_section
*sec
;
2306 struct mips_objfile_private
*priv
;
2308 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2311 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2313 *addrptr
= startaddr
;
2317 sec
= find_pc_section (pc
);
2320 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2322 /* Search the ".pdr" section generated by GAS. This includes most of
2323 the information normally found in ECOFF PDRs. */
2325 the_bfd
= sec
->objfile
->obfd
;
2327 && (the_bfd
->format
== bfd_object
2328 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2329 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2331 /* Right now GAS only outputs the address as a four-byte sequence.
2332 This means that we should not bother with this method on 64-bit
2333 targets (until that is fixed). */
2335 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2336 sizeof (struct mips_objfile_private
));
2338 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2340 else if (priv
== NULL
)
2344 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2345 sizeof (struct mips_objfile_private
));
2347 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2350 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2351 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2353 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2354 priv
->contents
, 0, priv
->size
);
2356 /* In general, the .pdr section is sorted. However, in the
2357 presence of multiple code sections (and other corner cases)
2358 it can become unsorted. Sort it so that we can use a faster
2360 qsort (priv
->contents
, priv
->size
/ 32, 32,
2361 compare_pdr_entries
);
2366 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2370 if (priv
->size
!= 0)
2377 high
= priv
->size
/ 32;
2379 /* We've found a .pdr section describing this objfile. We want to
2380 find the entry which describes this code address. The .pdr
2381 information is not very descriptive; we have only a function
2382 start address. We have to look for the closest entry, because
2383 the local symbol at the beginning of this function may have
2384 been stripped - so if we ask the symbol table for the start
2385 address we may get a preceding global function. */
2387 /* First, find the last .pdr entry starting at or before PC. */
2390 mid
= (low
+ high
) / 2;
2392 ptr
= priv
->contents
+ mid
* 32;
2393 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2394 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2395 SECT_OFF_TEXT (sec
->objfile
));
2402 while (low
!= high
);
2404 /* Both low and high point one past the PDR of interest. If
2405 both are zero, that means this PC is before any region
2406 covered by a PDR, i.e. pdr_pc for the first PDR entry is
2410 ptr
= priv
->contents
+ (low
- 1) * 32;
2411 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2412 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2413 SECT_OFF_TEXT (sec
->objfile
));
2416 /* We don't have a range, so we have no way to know for sure
2417 whether we're in the correct PDR or a PDR for a preceding
2418 function and the current function was a stripped local
2419 symbol. But if the PDR's PC is at least as great as the
2420 best guess from the symbol table, assume that it does cover
2421 the right area; if a .pdr section is present at all then
2422 nearly every function will have an entry. The biggest exception
2423 will be the dynamic linker stubs; conveniently these are
2424 placed before .text instead of after. */
2426 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
2428 struct symbol
*sym
= find_pc_function (pc
);
2433 /* Fill in what we need of the proc_desc. */
2434 proc_desc
= (mips_extra_func_info_t
)
2435 obstack_alloc (&sec
->objfile
->objfile_obstack
,
2436 sizeof (struct mips_extra_func_info
));
2437 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
2439 /* Only used for dummy frames. */
2440 PROC_HIGH_ADDR (proc_desc
) = 0;
2442 PROC_FRAME_OFFSET (proc_desc
)
2443 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2444 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2446 PROC_FRAME_ADJUST (proc_desc
) = 0;
2447 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2449 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2451 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2453 PROC_FREG_OFFSET (proc_desc
)
2454 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2455 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2457 proc_desc
->pdr
.isym
= (long) sym
;
2467 if (startaddr
> BLOCK_START (b
))
2469 /* This is the "pathological" case referred to in a comment in
2470 print_frame_info. It might be better to move this check into
2475 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2477 /* If we never found a PDR for this function in symbol reading, then
2478 examine prologues to find the information. */
2481 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2482 if (PROC_FRAME_REG (proc_desc
) == -1)
2492 static mips_extra_func_info_t
2493 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2495 mips_extra_func_info_t proc_desc
;
2496 CORE_ADDR startaddr
= 0;
2498 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2502 /* IF this is the topmost frame AND
2503 * (this proc does not have debugging information OR
2504 * the PC is in the procedure prologue)
2505 * THEN create a "heuristic" proc_desc (by analyzing
2506 * the actual code) to replace the "official" proc_desc.
2508 if (next_frame
== NULL
)
2510 struct symtab_and_line val
;
2511 struct symbol
*proc_symbol
=
2512 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2516 val
= find_pc_line (BLOCK_START
2517 (SYMBOL_BLOCK_VALUE (proc_symbol
)), 0);
2518 val
.pc
= val
.end
? val
.end
: pc
;
2520 if (!proc_symbol
|| pc
< val
.pc
)
2522 mips_extra_func_info_t found_heuristic
=
2523 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2524 pc
, next_frame
, cur_frame
);
2525 if (found_heuristic
)
2526 proc_desc
= found_heuristic
;
2532 /* Is linked_proc_desc_table really necessary? It only seems to be used
2533 by procedure call dummys. However, the procedures being called ought
2534 to have their own proc_descs, and even if they don't,
2535 heuristic_proc_desc knows how to create them! */
2537 struct linked_proc_info
*link
;
2539 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2540 if (PROC_LOW_ADDR (&link
->info
) <= pc
2541 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2545 startaddr
= heuristic_proc_start (pc
);
2547 proc_desc
= heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2552 /* MIPS stack frames are almost impenetrable. When execution stops,
2553 we basically have to look at symbol information for the function
2554 that we stopped in, which tells us *which* register (if any) is
2555 the base of the frame pointer, and what offset from that register
2556 the frame itself is at.
2558 This presents a problem when trying to examine a stack in memory
2559 (that isn't executing at the moment), using the "frame" command. We
2560 don't have a PC, nor do we have any registers except SP.
2562 This routine takes two arguments, SP and PC, and tries to make the
2563 cached frames look as if these two arguments defined a frame on the
2564 cache. This allows the rest of info frame to extract the important
2565 arguments without difficulty. */
2568 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2571 error ("MIPS frame specifications require two arguments: sp and pc");
2573 return create_new_frame (argv
[0], argv
[1]);
2576 /* According to the current ABI, should the type be passed in a
2577 floating-point register (assuming that there is space)? When there
2578 is no FPU, FP are not even considered as possibile candidates for
2579 FP registers and, consequently this returns false - forces FP
2580 arguments into integer registers. */
2583 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2585 return ((typecode
== TYPE_CODE_FLT
2587 && (typecode
== TYPE_CODE_STRUCT
2588 || typecode
== TYPE_CODE_UNION
)
2589 && TYPE_NFIELDS (arg_type
) == 1
2590 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2591 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2594 /* On o32, argument passing in GPRs depends on the alignment of the type being
2595 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2598 mips_type_needs_double_align (struct type
*type
)
2600 enum type_code typecode
= TYPE_CODE (type
);
2602 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2604 else if (typecode
== TYPE_CODE_STRUCT
)
2606 if (TYPE_NFIELDS (type
) < 1)
2608 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2610 else if (typecode
== TYPE_CODE_UNION
)
2614 n
= TYPE_NFIELDS (type
);
2615 for (i
= 0; i
< n
; i
++)
2616 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2623 /* Adjust the address downward (direction of stack growth) so that it
2624 is correctly aligned for a new stack frame. */
2626 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2628 return align_down (addr
, 16);
2631 /* Determine how a return value is stored within the MIPS register
2632 file, given the return type `valtype'. */
2634 struct return_value_word
2643 return_value_location (struct type
*valtype
,
2644 struct return_value_word
*hi
,
2645 struct return_value_word
*lo
)
2647 int len
= TYPE_LENGTH (valtype
);
2648 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2650 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2651 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2652 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2654 if (mips_abi_regsize (current_gdbarch
) < 8 && len
== 8)
2656 /* We need to break a 64bit float in two 32 bit halves and
2657 spread them across a floating-point register pair. */
2658 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2659 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
2660 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2661 && register_size (current_gdbarch
,
2662 mips_regnum (current_gdbarch
)->
2663 fp0
) == 8) ? 4 : 0);
2664 hi
->reg_offset
= lo
->reg_offset
;
2665 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
2666 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
2672 /* The floating point value fits in a single floating-point
2674 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2675 && register_size (current_gdbarch
,
2676 mips_regnum (current_gdbarch
)->
2678 && len
== 4) ? 4 : 0);
2679 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
2690 /* Locate a result possibly spread across two registers. */
2692 lo
->reg
= regnum
+ 0;
2693 hi
->reg
= regnum
+ 1;
2694 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2695 && len
< mips_abi_regsize (current_gdbarch
))
2697 /* "un-left-justify" the value in the low register */
2698 lo
->reg_offset
= mips_abi_regsize (current_gdbarch
) - len
;
2703 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (current_gdbarch
) /* odd-size structs */
2704 && len
< mips_abi_regsize (current_gdbarch
) * 2
2705 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2706 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2708 /* "un-left-justify" the value spread across two registers. */
2709 lo
->reg_offset
= 2 * mips_abi_regsize (current_gdbarch
) - len
;
2710 lo
->len
= mips_abi_regsize (current_gdbarch
) - lo
->reg_offset
;
2712 hi
->len
= len
- lo
->len
;
2716 /* Only perform a partial copy of the second register. */
2719 if (len
> mips_abi_regsize (current_gdbarch
))
2721 lo
->len
= mips_abi_regsize (current_gdbarch
);
2722 hi
->len
= len
- mips_abi_regsize (current_gdbarch
);
2730 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2731 && register_size (current_gdbarch
, regnum
) == 8
2732 && mips_abi_regsize (current_gdbarch
) == 4)
2734 /* Account for the fact that only the least-signficant part
2735 of the register is being used */
2736 lo
->reg_offset
+= 4;
2737 hi
->reg_offset
+= 4;
2740 hi
->buf_offset
= lo
->len
;
2744 /* Should call_function allocate stack space for a struct return? */
2747 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
2749 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2750 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (current_gdbarch
));
2753 /* Should call_function pass struct by reference?
2754 For each architecture, structs are passed either by
2755 value or by reference, depending on their size. */
2758 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
2760 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
2761 int len
= TYPE_LENGTH (check_typedef (type
));
2762 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2764 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2765 return (len
> mips_abi_regsize (current_gdbarch
));
2771 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2772 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2773 int nargs
, struct value
**args
, CORE_ADDR sp
,
2774 int struct_return
, CORE_ADDR struct_addr
)
2780 int stack_offset
= 0;
2781 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2783 /* For shared libraries, "t9" needs to point at the function
2785 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2787 /* Set the return address register to point to the entry point of
2788 the program, where a breakpoint lies in wait. */
2789 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2791 /* First ensure that the stack and structure return address (if any)
2792 are properly aligned. The stack has to be at least 64-bit
2793 aligned even on 32-bit machines, because doubles must be 64-bit
2794 aligned. For n32 and n64, stack frames need to be 128-bit
2795 aligned, so we round to this widest known alignment. */
2797 sp
= align_down (sp
, 16);
2798 struct_addr
= align_down (struct_addr
, 16);
2800 /* Now make space on the stack for the args. We allocate more
2801 than necessary for EABI, because the first few arguments are
2802 passed in registers, but that's OK. */
2803 for (argnum
= 0; argnum
< nargs
; argnum
++)
2804 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2805 mips_stack_argsize (gdbarch
));
2806 sp
-= align_up (len
, 16);
2809 fprintf_unfiltered (gdb_stdlog
,
2810 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2811 paddr_nz (sp
), (long) align_up (len
, 16));
2813 /* Initialize the integer and float register pointers. */
2815 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2817 /* The struct_return pointer occupies the first parameter-passing reg. */
2821 fprintf_unfiltered (gdb_stdlog
,
2822 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2823 argreg
, paddr_nz (struct_addr
));
2824 write_register (argreg
++, struct_addr
);
2827 /* Now load as many as possible of the first arguments into
2828 registers, and push the rest onto the stack. Loop thru args
2829 from first to last. */
2830 for (argnum
= 0; argnum
< nargs
; argnum
++)
2833 char valbuf
[MAX_REGISTER_SIZE
];
2834 struct value
*arg
= args
[argnum
];
2835 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2836 int len
= TYPE_LENGTH (arg_type
);
2837 enum type_code typecode
= TYPE_CODE (arg_type
);
2840 fprintf_unfiltered (gdb_stdlog
,
2841 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2842 argnum
+ 1, len
, (int) typecode
);
2844 /* The EABI passes structures that do not fit in a register by
2846 if (len
> mips_abi_regsize (gdbarch
)
2847 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2849 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
2850 VALUE_ADDRESS (arg
));
2851 typecode
= TYPE_CODE_PTR
;
2852 len
= mips_abi_regsize (gdbarch
);
2855 fprintf_unfiltered (gdb_stdlog
, " push");
2858 val
= (char *) VALUE_CONTENTS (arg
);
2860 /* 32-bit ABIs always start floating point arguments in an
2861 even-numbered floating point register. Round the FP register
2862 up before the check to see if there are any FP registers
2863 left. Non MIPS_EABI targets also pass the FP in the integer
2864 registers so also round up normal registers. */
2865 if (mips_abi_regsize (gdbarch
) < 8
2866 && fp_register_arg_p (typecode
, arg_type
))
2868 if ((float_argreg
& 1))
2872 /* Floating point arguments passed in registers have to be
2873 treated specially. On 32-bit architectures, doubles
2874 are passed in register pairs; the even register gets
2875 the low word, and the odd register gets the high word.
2876 On non-EABI processors, the first two floating point arguments are
2877 also copied to general registers, because MIPS16 functions
2878 don't use float registers for arguments. This duplication of
2879 arguments in general registers can't hurt non-MIPS16 functions
2880 because those registers are normally skipped. */
2881 /* MIPS_EABI squeezes a struct that contains a single floating
2882 point value into an FP register instead of pushing it onto the
2884 if (fp_register_arg_p (typecode
, arg_type
)
2885 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2887 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
2889 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2890 unsigned long regval
;
2892 /* Write the low word of the double to the even register(s). */
2893 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2895 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2896 float_argreg
, phex (regval
, 4));
2897 write_register (float_argreg
++, regval
);
2899 /* Write the high word of the double to the odd register(s). */
2900 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2902 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2903 float_argreg
, phex (regval
, 4));
2904 write_register (float_argreg
++, regval
);
2908 /* This is a floating point value that fits entirely
2909 in a single register. */
2910 /* On 32 bit ABI's the float_argreg is further adjusted
2911 above to ensure that it is even register aligned. */
2912 LONGEST regval
= extract_unsigned_integer (val
, len
);
2914 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2915 float_argreg
, phex (regval
, len
));
2916 write_register (float_argreg
++, regval
);
2921 /* Copy the argument to general registers or the stack in
2922 register-sized pieces. Large arguments are split between
2923 registers and stack. */
2924 /* Note: structs whose size is not a multiple of
2925 mips_abi_regsize() are treated specially: Irix cc passes
2926 them in registers where gcc sometimes puts them on the
2927 stack. For maximum compatibility, we will put them in
2929 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
2930 && (len
% mips_abi_regsize (gdbarch
) != 0));
2932 /* Note: Floating-point values that didn't fit into an FP
2933 register are only written to memory. */
2936 /* Remember if the argument was written to the stack. */
2937 int stack_used_p
= 0;
2938 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
2939 ? len
: mips_abi_regsize (gdbarch
));
2942 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2945 /* Write this portion of the argument to the stack. */
2946 if (argreg
> MIPS_LAST_ARG_REGNUM
2948 || fp_register_arg_p (typecode
, arg_type
))
2950 /* Should shorter than int integer values be
2951 promoted to int before being stored? */
2952 int longword_offset
= 0;
2955 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2957 if (mips_stack_argsize (gdbarch
) == 8
2958 && (typecode
== TYPE_CODE_INT
2959 || typecode
== TYPE_CODE_PTR
2960 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2961 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2962 else if ((typecode
== TYPE_CODE_STRUCT
2963 || typecode
== TYPE_CODE_UNION
)
2964 && (TYPE_LENGTH (arg_type
)
2965 < mips_stack_argsize (gdbarch
)))
2966 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2971 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2972 paddr_nz (stack_offset
));
2973 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2974 paddr_nz (longword_offset
));
2977 addr
= sp
+ stack_offset
+ longword_offset
;
2982 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2984 for (i
= 0; i
< partial_len
; i
++)
2986 fprintf_unfiltered (gdb_stdlog
, "%02x",
2990 write_memory (addr
, val
, partial_len
);
2993 /* Note!!! This is NOT an else clause. Odd sized
2994 structs may go thru BOTH paths. Floating point
2995 arguments will not. */
2996 /* Write this portion of the argument to a general
2997 purpose register. */
2998 if (argreg
<= MIPS_LAST_ARG_REGNUM
2999 && !fp_register_arg_p (typecode
, arg_type
))
3002 extract_unsigned_integer (val
, partial_len
);
3005 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3008 mips_abi_regsize (gdbarch
)));
3009 write_register (argreg
, regval
);
3016 /* Compute the the offset into the stack at which we
3017 will copy the next parameter.
3019 In the new EABI (and the NABI32), the stack_offset
3020 only needs to be adjusted when it has been used. */
3023 stack_offset
+= align_up (partial_len
,
3024 mips_stack_argsize (gdbarch
));
3028 fprintf_unfiltered (gdb_stdlog
, "\n");
3031 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3033 /* Return adjusted stack pointer. */
3037 /* Given a return value in `regbuf' with a type `valtype', extract and
3038 copy its value into `valbuf'. */
3041 mips_eabi_extract_return_value (struct type
*valtype
,
3042 char regbuf
[], char *valbuf
)
3044 struct return_value_word lo
;
3045 struct return_value_word hi
;
3046 return_value_location (valtype
, &hi
, &lo
);
3048 memcpy (valbuf
+ lo
.buf_offset
,
3049 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3050 lo
.reg_offset
, lo
.len
);
3053 memcpy (valbuf
+ hi
.buf_offset
,
3054 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3055 hi
.reg_offset
, hi
.len
);
3058 /* Given a return value in `valbuf' with a type `valtype', write it's
3059 value into the appropriate register. */
3062 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3064 char raw_buffer
[MAX_REGISTER_SIZE
];
3065 struct return_value_word lo
;
3066 struct return_value_word hi
;
3067 return_value_location (valtype
, &hi
, &lo
);
3069 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3070 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3071 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3072 raw_buffer
, register_size (current_gdbarch
,
3077 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3078 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3079 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3081 register_size (current_gdbarch
,
3086 /* N32/N64 ABI stuff. */
3089 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3090 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3091 int nargs
, struct value
**args
, CORE_ADDR sp
,
3092 int struct_return
, CORE_ADDR struct_addr
)
3098 int stack_offset
= 0;
3099 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3101 /* For shared libraries, "t9" needs to point at the function
3103 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3105 /* Set the return address register to point to the entry point of
3106 the program, where a breakpoint lies in wait. */
3107 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3109 /* First ensure that the stack and structure return address (if any)
3110 are properly aligned. The stack has to be at least 64-bit
3111 aligned even on 32-bit machines, because doubles must be 64-bit
3112 aligned. For n32 and n64, stack frames need to be 128-bit
3113 aligned, so we round to this widest known alignment. */
3115 sp
= align_down (sp
, 16);
3116 struct_addr
= align_down (struct_addr
, 16);
3118 /* Now make space on the stack for the args. */
3119 for (argnum
= 0; argnum
< nargs
; argnum
++)
3120 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3121 mips_stack_argsize (gdbarch
));
3122 sp
-= align_up (len
, 16);
3125 fprintf_unfiltered (gdb_stdlog
,
3126 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3127 paddr_nz (sp
), (long) align_up (len
, 16));
3129 /* Initialize the integer and float register pointers. */
3131 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3133 /* The struct_return pointer occupies the first parameter-passing reg. */
3137 fprintf_unfiltered (gdb_stdlog
,
3138 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3139 argreg
, paddr_nz (struct_addr
));
3140 write_register (argreg
++, struct_addr
);
3143 /* Now load as many as possible of the first arguments into
3144 registers, and push the rest onto the stack. Loop thru args
3145 from first to last. */
3146 for (argnum
= 0; argnum
< nargs
; argnum
++)
3149 struct value
*arg
= args
[argnum
];
3150 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3151 int len
= TYPE_LENGTH (arg_type
);
3152 enum type_code typecode
= TYPE_CODE (arg_type
);
3155 fprintf_unfiltered (gdb_stdlog
,
3156 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3157 argnum
+ 1, len
, (int) typecode
);
3159 val
= (char *) VALUE_CONTENTS (arg
);
3161 if (fp_register_arg_p (typecode
, arg_type
)
3162 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3164 /* This is a floating point value that fits entirely
3165 in a single register. */
3166 /* On 32 bit ABI's the float_argreg is further adjusted
3167 above to ensure that it is even register aligned. */
3168 LONGEST regval
= extract_unsigned_integer (val
, len
);
3170 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3171 float_argreg
, phex (regval
, len
));
3172 write_register (float_argreg
++, regval
);
3175 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3176 argreg
, phex (regval
, len
));
3177 write_register (argreg
, regval
);
3182 /* Copy the argument to general registers or the stack in
3183 register-sized pieces. Large arguments are split between
3184 registers and stack. */
3185 /* Note: structs whose size is not a multiple of
3186 mips_abi_regsize() are treated specially: Irix cc passes
3187 them in registers where gcc sometimes puts them on the
3188 stack. For maximum compatibility, we will put them in
3190 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3191 && (len
% mips_abi_regsize (gdbarch
) != 0));
3192 /* Note: Floating-point values that didn't fit into an FP
3193 register are only written to memory. */
3196 /* Rememer if the argument was written to the stack. */
3197 int stack_used_p
= 0;
3198 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3199 ? len
: mips_abi_regsize (gdbarch
));
3202 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3205 /* Write this portion of the argument to the stack. */
3206 if (argreg
> MIPS_LAST_ARG_REGNUM
3208 || fp_register_arg_p (typecode
, arg_type
))
3210 /* Should shorter than int integer values be
3211 promoted to int before being stored? */
3212 int longword_offset
= 0;
3215 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3217 if (mips_stack_argsize (gdbarch
) == 8
3218 && (typecode
== TYPE_CODE_INT
3219 || typecode
== TYPE_CODE_PTR
3220 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3221 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3226 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3227 paddr_nz (stack_offset
));
3228 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3229 paddr_nz (longword_offset
));
3232 addr
= sp
+ stack_offset
+ longword_offset
;
3237 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3239 for (i
= 0; i
< partial_len
; i
++)
3241 fprintf_unfiltered (gdb_stdlog
, "%02x",
3245 write_memory (addr
, val
, partial_len
);
3248 /* Note!!! This is NOT an else clause. Odd sized
3249 structs may go thru BOTH paths. Floating point
3250 arguments will not. */
3251 /* Write this portion of the argument to a general
3252 purpose register. */
3253 if (argreg
<= MIPS_LAST_ARG_REGNUM
3254 && !fp_register_arg_p (typecode
, arg_type
))
3257 extract_unsigned_integer (val
, partial_len
);
3259 /* A non-floating-point argument being passed in a
3260 general register. If a struct or union, and if
3261 the remaining length is smaller than the register
3262 size, we have to adjust the register value on
3265 It does not seem to be necessary to do the
3266 same for integral types.
3268 cagney/2001-07-23: gdb/179: Also, GCC, when
3269 outputting LE O32 with sizeof (struct) <
3270 mips_abi_regsize(), generates a left shift as
3271 part of storing the argument in a register a
3272 register (the left shift isn't generated when
3273 sizeof (struct) >= mips_abi_regsize()). Since
3274 it is quite possible that this is GCC
3275 contradicting the LE/O32 ABI, GDB has not been
3276 adjusted to accommodate this. Either someone
3277 needs to demonstrate that the LE/O32 ABI
3278 specifies such a left shift OR this new ABI gets
3279 identified as such and GDB gets tweaked
3282 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3283 && partial_len
< mips_abi_regsize (gdbarch
)
3284 && (typecode
== TYPE_CODE_STRUCT
||
3285 typecode
== TYPE_CODE_UNION
))
3286 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3290 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3293 mips_abi_regsize (gdbarch
)));
3294 write_register (argreg
, regval
);
3301 /* Compute the the offset into the stack at which we
3302 will copy the next parameter.
3304 In N32 (N64?), the stack_offset only needs to be
3305 adjusted when it has been used. */
3308 stack_offset
+= align_up (partial_len
,
3309 mips_stack_argsize (gdbarch
));
3313 fprintf_unfiltered (gdb_stdlog
, "\n");
3316 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3318 /* Return adjusted stack pointer. */
3322 static enum return_value_convention
3323 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3324 struct type
*type
, struct regcache
*regcache
,
3325 void *readbuf
, const void *writebuf
)
3327 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3328 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3329 || TYPE_CODE (type
) == TYPE_CODE_UNION
3330 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3331 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3332 return RETURN_VALUE_STRUCT_CONVENTION
;
3333 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3334 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3336 /* A floating-point value belongs in the least significant part
3339 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3340 mips_xfer_register (regcache
,
3341 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3343 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3344 return RETURN_VALUE_REGISTER_CONVENTION
;
3346 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3347 && TYPE_NFIELDS (type
) <= 2
3348 && TYPE_NFIELDS (type
) >= 1
3349 && ((TYPE_NFIELDS (type
) == 1
3350 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3352 || (TYPE_NFIELDS (type
) == 2
3353 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3355 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3357 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3359 /* A struct that contains one or two floats. Each value is part
3360 in the least significant part of their floating point
3364 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3365 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3367 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3370 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3372 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3373 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3374 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3376 return RETURN_VALUE_REGISTER_CONVENTION
;
3378 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3379 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3381 /* A structure or union. Extract the left justified value,
3382 regardless of the byte order. I.e. DO NOT USE
3386 for (offset
= 0, regnum
= V0_REGNUM
;
3387 offset
< TYPE_LENGTH (type
);
3388 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3390 int xfer
= register_size (current_gdbarch
, regnum
);
3391 if (offset
+ xfer
> TYPE_LENGTH (type
))
3392 xfer
= TYPE_LENGTH (type
) - offset
;
3394 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3395 offset
, xfer
, regnum
);
3396 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3397 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3399 return RETURN_VALUE_REGISTER_CONVENTION
;
3403 /* A scalar extract each part but least-significant-byte
3407 for (offset
= 0, regnum
= V0_REGNUM
;
3408 offset
< TYPE_LENGTH (type
);
3409 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3411 int xfer
= register_size (current_gdbarch
, regnum
);
3412 if (offset
+ xfer
> TYPE_LENGTH (type
))
3413 xfer
= TYPE_LENGTH (type
) - offset
;
3415 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3416 offset
, xfer
, regnum
);
3417 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3418 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3420 return RETURN_VALUE_REGISTER_CONVENTION
;
3424 /* O32 ABI stuff. */
3427 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3428 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3429 int nargs
, struct value
**args
, CORE_ADDR sp
,
3430 int struct_return
, CORE_ADDR struct_addr
)
3436 int stack_offset
= 0;
3437 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3439 /* For shared libraries, "t9" needs to point at the function
3441 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3443 /* Set the return address register to point to the entry point of
3444 the program, where a breakpoint lies in wait. */
3445 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3447 /* First ensure that the stack and structure return address (if any)
3448 are properly aligned. The stack has to be at least 64-bit
3449 aligned even on 32-bit machines, because doubles must be 64-bit
3450 aligned. For n32 and n64, stack frames need to be 128-bit
3451 aligned, so we round to this widest known alignment. */
3453 sp
= align_down (sp
, 16);
3454 struct_addr
= align_down (struct_addr
, 16);
3456 /* Now make space on the stack for the args. */
3457 for (argnum
= 0; argnum
< nargs
; argnum
++)
3458 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3459 mips_stack_argsize (gdbarch
));
3460 sp
-= align_up (len
, 16);
3463 fprintf_unfiltered (gdb_stdlog
,
3464 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3465 paddr_nz (sp
), (long) align_up (len
, 16));
3467 /* Initialize the integer and float register pointers. */
3469 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3471 /* The struct_return pointer occupies the first parameter-passing reg. */
3475 fprintf_unfiltered (gdb_stdlog
,
3476 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3477 argreg
, paddr_nz (struct_addr
));
3478 write_register (argreg
++, struct_addr
);
3479 stack_offset
+= mips_stack_argsize (gdbarch
);
3482 /* Now load as many as possible of the first arguments into
3483 registers, and push the rest onto the stack. Loop thru args
3484 from first to last. */
3485 for (argnum
= 0; argnum
< nargs
; argnum
++)
3488 struct value
*arg
= args
[argnum
];
3489 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3490 int len
= TYPE_LENGTH (arg_type
);
3491 enum type_code typecode
= TYPE_CODE (arg_type
);
3494 fprintf_unfiltered (gdb_stdlog
,
3495 "mips_o32_push_dummy_call: %d len=%d type=%d",
3496 argnum
+ 1, len
, (int) typecode
);
3498 val
= (char *) VALUE_CONTENTS (arg
);
3500 /* 32-bit ABIs always start floating point arguments in an
3501 even-numbered floating point register. Round the FP register
3502 up before the check to see if there are any FP registers
3503 left. O32/O64 targets also pass the FP in the integer
3504 registers so also round up normal registers. */
3505 if (mips_abi_regsize (gdbarch
) < 8
3506 && fp_register_arg_p (typecode
, arg_type
))
3508 if ((float_argreg
& 1))
3512 /* Floating point arguments passed in registers have to be
3513 treated specially. On 32-bit architectures, doubles
3514 are passed in register pairs; the even register gets
3515 the low word, and the odd register gets the high word.
3516 On O32/O64, the first two floating point arguments are
3517 also copied to general registers, because MIPS16 functions
3518 don't use float registers for arguments. This duplication of
3519 arguments in general registers can't hurt non-MIPS16 functions
3520 because those registers are normally skipped. */
3522 if (fp_register_arg_p (typecode
, arg_type
)
3523 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3525 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3527 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3528 unsigned long regval
;
3530 /* Write the low word of the double to the even register(s). */
3531 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3533 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3534 float_argreg
, phex (regval
, 4));
3535 write_register (float_argreg
++, regval
);
3537 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3538 argreg
, phex (regval
, 4));
3539 write_register (argreg
++, regval
);
3541 /* Write the high word of the double to the odd register(s). */
3542 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3544 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3545 float_argreg
, phex (regval
, 4));
3546 write_register (float_argreg
++, regval
);
3549 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3550 argreg
, phex (regval
, 4));
3551 write_register (argreg
++, regval
);
3555 /* This is a floating point value that fits entirely
3556 in a single register. */
3557 /* On 32 bit ABI's the float_argreg is further adjusted
3558 above to ensure that it is even register aligned. */
3559 LONGEST regval
= extract_unsigned_integer (val
, len
);
3561 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3562 float_argreg
, phex (regval
, len
));
3563 write_register (float_argreg
++, regval
);
3564 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3565 registers for each argument. The below is (my
3566 guess) to ensure that the corresponding integer
3567 register has reserved the same space. */
3569 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3570 argreg
, phex (regval
, len
));
3571 write_register (argreg
, regval
);
3572 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3574 /* Reserve space for the FP register. */
3575 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3579 /* Copy the argument to general registers or the stack in
3580 register-sized pieces. Large arguments are split between
3581 registers and stack. */
3582 /* Note: structs whose size is not a multiple of
3583 mips_abi_regsize() are treated specially: Irix cc passes
3584 them in registers where gcc sometimes puts them on the
3585 stack. For maximum compatibility, we will put them in
3587 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3588 && (len
% mips_abi_regsize (gdbarch
) != 0));
3589 /* Structures should be aligned to eight bytes (even arg registers)
3590 on MIPS_ABI_O32, if their first member has double precision. */
3591 if (mips_abi_regsize (gdbarch
) < 8
3592 && mips_type_needs_double_align (arg_type
))
3597 /* Note: Floating-point values that didn't fit into an FP
3598 register are only written to memory. */
3601 /* Remember if the argument was written to the stack. */
3602 int stack_used_p
= 0;
3603 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3604 ? len
: mips_abi_regsize (gdbarch
));
3607 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3610 /* Write this portion of the argument to the stack. */
3611 if (argreg
> MIPS_LAST_ARG_REGNUM
3613 || fp_register_arg_p (typecode
, arg_type
))
3615 /* Should shorter than int integer values be
3616 promoted to int before being stored? */
3617 int longword_offset
= 0;
3620 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3622 if (mips_stack_argsize (gdbarch
) == 8
3623 && (typecode
== TYPE_CODE_INT
3624 || typecode
== TYPE_CODE_PTR
3625 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3626 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3631 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3632 paddr_nz (stack_offset
));
3633 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3634 paddr_nz (longword_offset
));
3637 addr
= sp
+ stack_offset
+ longword_offset
;
3642 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3644 for (i
= 0; i
< partial_len
; i
++)
3646 fprintf_unfiltered (gdb_stdlog
, "%02x",
3650 write_memory (addr
, val
, partial_len
);
3653 /* Note!!! This is NOT an else clause. Odd sized
3654 structs may go thru BOTH paths. Floating point
3655 arguments will not. */
3656 /* Write this portion of the argument to a general
3657 purpose register. */
3658 if (argreg
<= MIPS_LAST_ARG_REGNUM
3659 && !fp_register_arg_p (typecode
, arg_type
))
3661 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3662 /* Value may need to be sign extended, because
3663 mips_isa_regsize() != mips_abi_regsize(). */
3665 /* A non-floating-point argument being passed in a
3666 general register. If a struct or union, and if
3667 the remaining length is smaller than the register
3668 size, we have to adjust the register value on
3671 It does not seem to be necessary to do the
3672 same for integral types.
3674 Also don't do this adjustment on O64 binaries.
3676 cagney/2001-07-23: gdb/179: Also, GCC, when
3677 outputting LE O32 with sizeof (struct) <
3678 mips_abi_regsize(), generates a left shift as
3679 part of storing the argument in a register a
3680 register (the left shift isn't generated when
3681 sizeof (struct) >= mips_abi_regsize()). Since
3682 it is quite possible that this is GCC
3683 contradicting the LE/O32 ABI, GDB has not been
3684 adjusted to accommodate this. Either someone
3685 needs to demonstrate that the LE/O32 ABI
3686 specifies such a left shift OR this new ABI gets
3687 identified as such and GDB gets tweaked
3690 if (mips_abi_regsize (gdbarch
) < 8
3691 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3692 && partial_len
< mips_abi_regsize (gdbarch
)
3693 && (typecode
== TYPE_CODE_STRUCT
||
3694 typecode
== TYPE_CODE_UNION
))
3695 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3699 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3702 mips_abi_regsize (gdbarch
)));
3703 write_register (argreg
, regval
);
3706 /* Prevent subsequent floating point arguments from
3707 being passed in floating point registers. */
3708 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3714 /* Compute the the offset into the stack at which we
3715 will copy the next parameter.
3717 In older ABIs, the caller reserved space for
3718 registers that contained arguments. This was loosely
3719 refered to as their "home". Consequently, space is
3720 always allocated. */
3722 stack_offset
+= align_up (partial_len
,
3723 mips_stack_argsize (gdbarch
));
3727 fprintf_unfiltered (gdb_stdlog
, "\n");
3730 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3732 /* Return adjusted stack pointer. */
3736 static enum return_value_convention
3737 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3738 struct regcache
*regcache
,
3739 void *readbuf
, const void *writebuf
)
3741 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3743 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3744 || TYPE_CODE (type
) == TYPE_CODE_UNION
3745 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3746 return RETURN_VALUE_STRUCT_CONVENTION
;
3747 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3748 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3750 /* A single-precision floating-point value. It fits in the
3751 least significant part of FP0. */
3753 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3754 mips_xfer_register (regcache
,
3755 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3757 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3758 return RETURN_VALUE_REGISTER_CONVENTION
;
3760 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3761 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3763 /* A double-precision floating-point value. The most
3764 significant part goes in FP1, and the least significant in
3767 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3768 switch (TARGET_BYTE_ORDER
)
3770 case BFD_ENDIAN_LITTLE
:
3771 mips_xfer_register (regcache
,
3772 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3773 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3774 mips_xfer_register (regcache
,
3775 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3776 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3778 case BFD_ENDIAN_BIG
:
3779 mips_xfer_register (regcache
,
3780 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3781 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3782 mips_xfer_register (regcache
,
3783 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3784 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3787 internal_error (__FILE__
, __LINE__
, "bad switch");
3789 return RETURN_VALUE_REGISTER_CONVENTION
;
3792 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3793 && TYPE_NFIELDS (type
) <= 2
3794 && TYPE_NFIELDS (type
) >= 1
3795 && ((TYPE_NFIELDS (type
) == 1
3796 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3798 || (TYPE_NFIELDS (type
) == 2
3799 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3801 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3803 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3805 /* A struct that contains one or two floats. Each value is part
3806 in the least significant part of their floating point
3808 bfd_byte reg
[MAX_REGISTER_SIZE
];
3811 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3812 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3814 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3817 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3819 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3820 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3821 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3823 return RETURN_VALUE_REGISTER_CONVENTION
;
3827 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3828 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3830 /* A structure or union. Extract the left justified value,
3831 regardless of the byte order. I.e. DO NOT USE
3835 for (offset
= 0, regnum
= V0_REGNUM
;
3836 offset
< TYPE_LENGTH (type
);
3837 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3839 int xfer
= register_size (current_gdbarch
, regnum
);
3840 if (offset
+ xfer
> TYPE_LENGTH (type
))
3841 xfer
= TYPE_LENGTH (type
) - offset
;
3843 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3844 offset
, xfer
, regnum
);
3845 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3846 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3848 return RETURN_VALUE_REGISTER_CONVENTION
;
3853 /* A scalar extract each part but least-significant-byte
3854 justified. o32 thinks registers are 4 byte, regardless of
3855 the ISA. mips_stack_argsize controls this. */
3858 for (offset
= 0, regnum
= V0_REGNUM
;
3859 offset
< TYPE_LENGTH (type
);
3860 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
3862 int xfer
= mips_stack_argsize (gdbarch
);
3863 if (offset
+ xfer
> TYPE_LENGTH (type
))
3864 xfer
= TYPE_LENGTH (type
) - offset
;
3866 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3867 offset
, xfer
, regnum
);
3868 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3869 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3871 return RETURN_VALUE_REGISTER_CONVENTION
;
3875 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3879 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3880 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3882 struct value
**args
, CORE_ADDR sp
,
3883 int struct_return
, CORE_ADDR struct_addr
)
3889 int stack_offset
= 0;
3890 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3892 /* For shared libraries, "t9" needs to point at the function
3894 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3896 /* Set the return address register to point to the entry point of
3897 the program, where a breakpoint lies in wait. */
3898 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3900 /* First ensure that the stack and structure return address (if any)
3901 are properly aligned. The stack has to be at least 64-bit
3902 aligned even on 32-bit machines, because doubles must be 64-bit
3903 aligned. For n32 and n64, stack frames need to be 128-bit
3904 aligned, so we round to this widest known alignment. */
3906 sp
= align_down (sp
, 16);
3907 struct_addr
= align_down (struct_addr
, 16);
3909 /* Now make space on the stack for the args. */
3910 for (argnum
= 0; argnum
< nargs
; argnum
++)
3911 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3912 mips_stack_argsize (gdbarch
));
3913 sp
-= align_up (len
, 16);
3916 fprintf_unfiltered (gdb_stdlog
,
3917 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3918 paddr_nz (sp
), (long) align_up (len
, 16));
3920 /* Initialize the integer and float register pointers. */
3922 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3924 /* The struct_return pointer occupies the first parameter-passing reg. */
3928 fprintf_unfiltered (gdb_stdlog
,
3929 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3930 argreg
, paddr_nz (struct_addr
));
3931 write_register (argreg
++, struct_addr
);
3932 stack_offset
+= mips_stack_argsize (gdbarch
);
3935 /* Now load as many as possible of the first arguments into
3936 registers, and push the rest onto the stack. Loop thru args
3937 from first to last. */
3938 for (argnum
= 0; argnum
< nargs
; argnum
++)
3941 struct value
*arg
= args
[argnum
];
3942 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3943 int len
= TYPE_LENGTH (arg_type
);
3944 enum type_code typecode
= TYPE_CODE (arg_type
);
3947 fprintf_unfiltered (gdb_stdlog
,
3948 "mips_o64_push_dummy_call: %d len=%d type=%d",
3949 argnum
+ 1, len
, (int) typecode
);
3951 val
= (char *) VALUE_CONTENTS (arg
);
3953 /* 32-bit ABIs always start floating point arguments in an
3954 even-numbered floating point register. Round the FP register
3955 up before the check to see if there are any FP registers
3956 left. O32/O64 targets also pass the FP in the integer
3957 registers so also round up normal registers. */
3958 if (mips_abi_regsize (gdbarch
) < 8
3959 && fp_register_arg_p (typecode
, arg_type
))
3961 if ((float_argreg
& 1))
3965 /* Floating point arguments passed in registers have to be
3966 treated specially. On 32-bit architectures, doubles
3967 are passed in register pairs; the even register gets
3968 the low word, and the odd register gets the high word.
3969 On O32/O64, the first two floating point arguments are
3970 also copied to general registers, because MIPS16 functions
3971 don't use float registers for arguments. This duplication of
3972 arguments in general registers can't hurt non-MIPS16 functions
3973 because those registers are normally skipped. */
3975 if (fp_register_arg_p (typecode
, arg_type
)
3976 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3978 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3980 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3981 unsigned long regval
;
3983 /* Write the low word of the double to the even register(s). */
3984 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3986 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3987 float_argreg
, phex (regval
, 4));
3988 write_register (float_argreg
++, regval
);
3990 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3991 argreg
, phex (regval
, 4));
3992 write_register (argreg
++, regval
);
3994 /* Write the high word of the double to the odd register(s). */
3995 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3997 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3998 float_argreg
, phex (regval
, 4));
3999 write_register (float_argreg
++, regval
);
4002 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4003 argreg
, phex (regval
, 4));
4004 write_register (argreg
++, regval
);
4008 /* This is a floating point value that fits entirely
4009 in a single register. */
4010 /* On 32 bit ABI's the float_argreg is further adjusted
4011 above to ensure that it is even register aligned. */
4012 LONGEST regval
= extract_unsigned_integer (val
, len
);
4014 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4015 float_argreg
, phex (regval
, len
));
4016 write_register (float_argreg
++, regval
);
4017 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4018 registers for each argument. The below is (my
4019 guess) to ensure that the corresponding integer
4020 register has reserved the same space. */
4022 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4023 argreg
, phex (regval
, len
));
4024 write_register (argreg
, regval
);
4025 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4027 /* Reserve space for the FP register. */
4028 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4032 /* Copy the argument to general registers or the stack in
4033 register-sized pieces. Large arguments are split between
4034 registers and stack. */
4035 /* Note: structs whose size is not a multiple of
4036 mips_abi_regsize() are treated specially: Irix cc passes
4037 them in registers where gcc sometimes puts them on the
4038 stack. For maximum compatibility, we will put them in
4040 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4041 && (len
% mips_abi_regsize (gdbarch
) != 0));
4042 /* Structures should be aligned to eight bytes (even arg registers)
4043 on MIPS_ABI_O32, if their first member has double precision. */
4044 if (mips_abi_regsize (gdbarch
) < 8
4045 && mips_type_needs_double_align (arg_type
))
4050 /* Note: Floating-point values that didn't fit into an FP
4051 register are only written to memory. */
4054 /* Remember if the argument was written to the stack. */
4055 int stack_used_p
= 0;
4056 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4057 ? len
: mips_abi_regsize (gdbarch
));
4060 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4063 /* Write this portion of the argument to the stack. */
4064 if (argreg
> MIPS_LAST_ARG_REGNUM
4066 || fp_register_arg_p (typecode
, arg_type
))
4068 /* Should shorter than int integer values be
4069 promoted to int before being stored? */
4070 int longword_offset
= 0;
4073 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4075 if (mips_stack_argsize (gdbarch
) == 8
4076 && (typecode
== TYPE_CODE_INT
4077 || typecode
== TYPE_CODE_PTR
4078 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4079 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4084 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4085 paddr_nz (stack_offset
));
4086 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4087 paddr_nz (longword_offset
));
4090 addr
= sp
+ stack_offset
+ longword_offset
;
4095 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4097 for (i
= 0; i
< partial_len
; i
++)
4099 fprintf_unfiltered (gdb_stdlog
, "%02x",
4103 write_memory (addr
, val
, partial_len
);
4106 /* Note!!! This is NOT an else clause. Odd sized
4107 structs may go thru BOTH paths. Floating point
4108 arguments will not. */
4109 /* Write this portion of the argument to a general
4110 purpose register. */
4111 if (argreg
<= MIPS_LAST_ARG_REGNUM
4112 && !fp_register_arg_p (typecode
, arg_type
))
4114 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4115 /* Value may need to be sign extended, because
4116 mips_isa_regsize() != mips_abi_regsize(). */
4118 /* A non-floating-point argument being passed in a
4119 general register. If a struct or union, and if
4120 the remaining length is smaller than the register
4121 size, we have to adjust the register value on
4124 It does not seem to be necessary to do the
4125 same for integral types.
4127 Also don't do this adjustment on O64 binaries.
4129 cagney/2001-07-23: gdb/179: Also, GCC, when
4130 outputting LE O32 with sizeof (struct) <
4131 mips_abi_regsize(), generates a left shift as
4132 part of storing the argument in a register a
4133 register (the left shift isn't generated when
4134 sizeof (struct) >= mips_abi_regsize()). Since
4135 it is quite possible that this is GCC
4136 contradicting the LE/O32 ABI, GDB has not been
4137 adjusted to accommodate this. Either someone
4138 needs to demonstrate that the LE/O32 ABI
4139 specifies such a left shift OR this new ABI gets
4140 identified as such and GDB gets tweaked
4143 if (mips_abi_regsize (gdbarch
) < 8
4144 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4145 && partial_len
< mips_abi_regsize (gdbarch
)
4146 && (typecode
== TYPE_CODE_STRUCT
||
4147 typecode
== TYPE_CODE_UNION
))
4148 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4152 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4155 mips_abi_regsize (gdbarch
)));
4156 write_register (argreg
, regval
);
4159 /* Prevent subsequent floating point arguments from
4160 being passed in floating point registers. */
4161 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4167 /* Compute the the offset into the stack at which we
4168 will copy the next parameter.
4170 In older ABIs, the caller reserved space for
4171 registers that contained arguments. This was loosely
4172 refered to as their "home". Consequently, space is
4173 always allocated. */
4175 stack_offset
+= align_up (partial_len
,
4176 mips_stack_argsize (gdbarch
));
4180 fprintf_unfiltered (gdb_stdlog
, "\n");
4183 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
4185 /* Return adjusted stack pointer. */
4190 mips_o64_extract_return_value (struct type
*valtype
,
4191 char regbuf
[], char *valbuf
)
4193 struct return_value_word lo
;
4194 struct return_value_word hi
;
4195 return_value_location (valtype
, &hi
, &lo
);
4197 memcpy (valbuf
+ lo
.buf_offset
,
4198 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4199 lo
.reg_offset
, lo
.len
);
4202 memcpy (valbuf
+ hi
.buf_offset
,
4203 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4204 hi
.reg_offset
, hi
.len
);
4208 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4210 char raw_buffer
[MAX_REGISTER_SIZE
];
4211 struct return_value_word lo
;
4212 struct return_value_word hi
;
4213 return_value_location (valtype
, &hi
, &lo
);
4215 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4216 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4217 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4218 raw_buffer
, register_size (current_gdbarch
,
4223 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4224 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4225 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4227 register_size (current_gdbarch
,
4232 /* Floating point register management.
4234 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4235 64bit operations, these early MIPS cpus treat fp register pairs
4236 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4237 registers and offer a compatibility mode that emulates the MIPS2 fp
4238 model. When operating in MIPS2 fp compat mode, later cpu's split
4239 double precision floats into two 32-bit chunks and store them in
4240 consecutive fp regs. To display 64-bit floats stored in this
4241 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4242 Throw in user-configurable endianness and you have a real mess.
4244 The way this works is:
4245 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4246 double-precision value will be split across two logical registers.
4247 The lower-numbered logical register will hold the low-order bits,
4248 regardless of the processor's endianness.
4249 - If we are on a 64-bit processor, and we are looking for a
4250 single-precision value, it will be in the low ordered bits
4251 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4252 save slot in memory.
4253 - If we are in 64-bit mode, everything is straightforward.
4255 Note that this code only deals with "live" registers at the top of the
4256 stack. We will attempt to deal with saved registers later, when
4257 the raw/cooked register interface is in place. (We need a general
4258 interface that can deal with dynamic saved register sizes -- fp
4259 regs could be 32 bits wide in one frame and 64 on the frame above
4262 static struct type
*
4263 mips_float_register_type (void)
4265 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4266 return builtin_type_ieee_single_big
;
4268 return builtin_type_ieee_single_little
;
4271 static struct type
*
4272 mips_double_register_type (void)
4274 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4275 return builtin_type_ieee_double_big
;
4277 return builtin_type_ieee_double_little
;
4280 /* Copy a 32-bit single-precision value from the current frame
4281 into rare_buffer. */
4284 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4287 int raw_size
= register_size (current_gdbarch
, regno
);
4288 char *raw_buffer
= alloca (raw_size
);
4290 if (!frame_register_read (frame
, regno
, raw_buffer
))
4291 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4294 /* We have a 64-bit value for this register. Find the low-order
4298 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4303 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4307 memcpy (rare_buffer
, raw_buffer
, 4);
4311 /* Copy a 64-bit double-precision value from the current frame into
4312 rare_buffer. This may include getting half of it from the next
4316 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4319 int raw_size
= register_size (current_gdbarch
, regno
);
4321 if (raw_size
== 8 && !mips2_fp_compat ())
4323 /* We have a 64-bit value for this register, and we should use
4325 if (!frame_register_read (frame
, regno
, rare_buffer
))
4326 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4330 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4331 internal_error (__FILE__
, __LINE__
,
4332 "mips_read_fp_register_double: bad access to "
4333 "odd-numbered FP register");
4335 /* mips_read_fp_register_single will find the correct 32 bits from
4337 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4339 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4340 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4344 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4345 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4351 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4353 { /* do values for FP (float) regs */
4355 double doub
, flt1
; /* doubles extracted from raw hex data */
4359 (char *) alloca (2 *
4360 register_size (current_gdbarch
,
4361 mips_regnum (current_gdbarch
)->fp0
));
4363 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4364 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4367 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4369 /* 4-byte registers: Print hex and floating. Also print even
4370 numbered registers as doubles. */
4371 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4372 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4374 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4377 fprintf_filtered (file
, " flt: ");
4379 fprintf_filtered (file
, " <invalid float> ");
4381 fprintf_filtered (file
, "%-17.9g", flt1
);
4383 if (regnum
% 2 == 0)
4385 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4386 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4389 fprintf_filtered (file
, " dbl: ");
4391 fprintf_filtered (file
, "<invalid double>");
4393 fprintf_filtered (file
, "%-24.17g", doub
);
4398 /* Eight byte registers: print each one as hex, float and double. */
4399 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4400 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4402 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4403 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4406 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4409 fprintf_filtered (file
, " flt: ");
4411 fprintf_filtered (file
, "<invalid float>");
4413 fprintf_filtered (file
, "%-17.9g", flt1
);
4415 fprintf_filtered (file
, " dbl: ");
4417 fprintf_filtered (file
, "<invalid double>");
4419 fprintf_filtered (file
, "%-24.17g", doub
);
4424 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4425 int regnum
, int all
)
4427 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4428 char raw_buffer
[MAX_REGISTER_SIZE
];
4431 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4433 mips_print_fp_register (file
, frame
, regnum
);
4437 /* Get the data in raw format. */
4438 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4440 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4444 fputs_filtered (REGISTER_NAME (regnum
), file
);
4446 /* The problem with printing numeric register names (r26, etc.) is that
4447 the user can't use them on input. Probably the best solution is to
4448 fix it so that either the numeric or the funky (a2, etc.) names
4449 are accepted on input. */
4450 if (regnum
< MIPS_NUMREGS
)
4451 fprintf_filtered (file
, "(r%d): ", regnum
);
4453 fprintf_filtered (file
, ": ");
4455 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4457 register_size (current_gdbarch
,
4458 regnum
) - register_size (current_gdbarch
, regnum
);
4462 print_scalar_formatted (raw_buffer
+ offset
,
4463 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4467 /* Replacement for generic do_registers_info.
4468 Print regs in pretty columns. */
4471 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4474 fprintf_filtered (file
, " ");
4475 mips_print_fp_register (file
, frame
, regnum
);
4476 fprintf_filtered (file
, "\n");
4481 /* Print a row's worth of GP (int) registers, with name labels above */
4484 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4487 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4488 /* do values for GP (int) regs */
4489 char raw_buffer
[MAX_REGISTER_SIZE
];
4490 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4494 /* For GP registers, we print a separate row of names above the vals */
4495 fprintf_filtered (file
, " ");
4496 for (col
= 0, regnum
= start_regnum
;
4497 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4499 if (*REGISTER_NAME (regnum
) == '\0')
4500 continue; /* unused register */
4501 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4503 break; /* end the row: reached FP register */
4504 fprintf_filtered (file
,
4505 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4506 REGISTER_NAME (regnum
));
4509 /* print the R0 to R31 names */
4510 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4511 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4513 fprintf_filtered (file
, "\n ");
4515 /* now print the values in hex, 4 or 8 to the row */
4516 for (col
= 0, regnum
= start_regnum
;
4517 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4519 if (*REGISTER_NAME (regnum
) == '\0')
4520 continue; /* unused register */
4521 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4523 break; /* end row: reached FP register */
4524 /* OK: get the data in raw format. */
4525 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4526 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4527 /* pad small registers */
4529 byte
< (mips_abi_regsize (current_gdbarch
)
4530 - register_size (current_gdbarch
, regnum
)); byte
++)
4531 printf_filtered (" ");
4532 /* Now print the register value in hex, endian order. */
4533 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4535 register_size (current_gdbarch
,
4536 regnum
) - register_size (current_gdbarch
, regnum
);
4537 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4538 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4540 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4542 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4543 fprintf_filtered (file
, " ");
4546 if (col
> 0) /* ie. if we actually printed anything... */
4547 fprintf_filtered (file
, "\n");
4552 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4555 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4556 struct frame_info
*frame
, int regnum
, int all
)
4558 if (regnum
!= -1) /* do one specified register */
4560 gdb_assert (regnum
>= NUM_REGS
);
4561 if (*(REGISTER_NAME (regnum
)) == '\0')
4562 error ("Not a valid register for the current processor type");
4564 mips_print_register (file
, frame
, regnum
, 0);
4565 fprintf_filtered (file
, "\n");
4568 /* do all (or most) registers */
4571 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4573 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4576 if (all
) /* true for "INFO ALL-REGISTERS" command */
4577 regnum
= print_fp_register_row (file
, frame
, regnum
);
4579 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4582 regnum
= print_gp_register_row (file
, frame
, regnum
);
4587 /* Is this a branch with a delay slot? */
4589 static int is_delayed (unsigned long);
4592 is_delayed (unsigned long insn
)
4595 for (i
= 0; i
< NUMOPCODES
; ++i
)
4596 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4597 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4599 return (i
< NUMOPCODES
4600 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4601 | INSN_COND_BRANCH_DELAY
4602 | INSN_COND_BRANCH_LIKELY
)));
4606 mips_step_skips_delay (CORE_ADDR pc
)
4608 char buf
[MIPS_INSTLEN
];
4610 /* There is no branch delay slot on MIPS16. */
4611 if (pc_is_mips16 (pc
))
4614 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4615 /* If error reading memory, guess that it is not a delayed branch. */
4617 return is_delayed ((unsigned long)
4618 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4621 /* Skip the PC past function prologue instructions (32-bit version).
4622 This is a helper function for mips_skip_prologue. */
4625 mips32_skip_prologue (CORE_ADDR pc
)
4629 int seen_sp_adjust
= 0;
4630 int load_immediate_bytes
= 0;
4632 /* Find an upper bound on the prologue. */
4633 end_pc
= skip_prologue_using_sal (pc
);
4635 end_pc
= pc
+ 100; /* Magic. */
4637 /* Skip the typical prologue instructions. These are the stack adjustment
4638 instruction and the instructions that save registers on the stack
4639 or in the gcc frame. */
4640 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4642 unsigned long high_word
;
4644 inst
= mips_fetch_instruction (pc
);
4645 high_word
= (inst
>> 16) & 0xffff;
4647 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4648 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4650 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4651 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4653 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4654 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4655 && (inst
& 0x001F0000)) /* reg != $zero */
4658 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4660 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4662 continue; /* reg != $zero */
4664 /* move $s8,$sp. With different versions of gas this will be either
4665 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4666 Accept any one of these. */
4667 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4670 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4672 else if (high_word
== 0x3c1c) /* lui $gp,n */
4674 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4676 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4677 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4679 /* The following instructions load $at or $t0 with an immediate
4680 value in preparation for a stack adjustment via
4681 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4682 a local variable, so we accept them only before a stack adjustment
4683 instruction was seen. */
4684 else if (!seen_sp_adjust
)
4686 if (high_word
== 0x3c01 || /* lui $at,n */
4687 high_word
== 0x3c08) /* lui $t0,n */
4689 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4692 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4693 high_word
== 0x3508 || /* ori $t0,$t0,n */
4694 high_word
== 0x3401 || /* ori $at,$zero,n */
4695 high_word
== 0x3408) /* ori $t0,$zero,n */
4697 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4707 /* In a frameless function, we might have incorrectly
4708 skipped some load immediate instructions. Undo the skipping
4709 if the load immediate was not followed by a stack adjustment. */
4710 if (load_immediate_bytes
&& !seen_sp_adjust
)
4711 pc
-= load_immediate_bytes
;
4715 /* Skip the PC past function prologue instructions (16-bit version).
4716 This is a helper function for mips_skip_prologue. */
4719 mips16_skip_prologue (CORE_ADDR pc
)
4722 int extend_bytes
= 0;
4723 int prev_extend_bytes
;
4725 /* Table of instructions likely to be found in a function prologue. */
4728 unsigned short inst
;
4729 unsigned short mask
;
4735 , /* addiu $sp,offset */
4738 , /* daddiu $sp,offset */
4741 , /* sw reg,n($sp) */
4744 , /* sd reg,n($sp) */
4747 , /* sw $ra,n($sp) */
4750 , /* sd $ra,n($sp) */
4756 , /* sw $a0-$a3,n($s1) */
4759 , /* move reg,$a0-$a3 */
4762 , /* entry pseudo-op */
4765 , /* addiu $s1,$sp,n */
4767 0, 0} /* end of table marker */
4770 /* Find an upper bound on the prologue. */
4771 end_pc
= skip_prologue_using_sal (pc
);
4773 end_pc
= pc
+ 100; /* Magic. */
4775 /* Skip the typical prologue instructions. These are the stack adjustment
4776 instruction and the instructions that save registers on the stack
4777 or in the gcc frame. */
4778 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4780 unsigned short inst
;
4783 inst
= mips_fetch_instruction (pc
);
4785 /* Normally we ignore an extend instruction. However, if it is
4786 not followed by a valid prologue instruction, we must adjust
4787 the pc back over the extend so that it won't be considered
4788 part of the prologue. */
4789 if ((inst
& 0xf800) == 0xf000) /* extend */
4791 extend_bytes
= MIPS16_INSTLEN
;
4794 prev_extend_bytes
= extend_bytes
;
4797 /* Check for other valid prologue instructions besides extend. */
4798 for (i
= 0; table
[i
].mask
!= 0; i
++)
4799 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4801 if (table
[i
].mask
!= 0) /* it was in table? */
4802 continue; /* ignore it */
4806 /* Return the current pc, adjusted backwards by 2 if
4807 the previous instruction was an extend. */
4808 return pc
- prev_extend_bytes
;
4814 /* To skip prologues, I use this predicate. Returns either PC itself
4815 if the code at PC does not look like a function prologue; otherwise
4816 returns an address that (if we're lucky) follows the prologue. If
4817 LENIENT, then we must skip everything which is involved in setting
4818 up the frame (it's OK to skip more, just so long as we don't skip
4819 anything which might clobber the registers which are being saved.
4820 We must skip more in the case where part of the prologue is in the
4821 delay slot of a non-prologue instruction). */
4824 mips_skip_prologue (CORE_ADDR pc
)
4826 /* See if we can determine the end of the prologue via the symbol table.
4827 If so, then return either PC, or the PC after the prologue, whichever
4830 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4832 if (post_prologue_pc
!= 0)
4833 return max (pc
, post_prologue_pc
);
4835 /* Can't determine prologue from the symbol table, need to examine
4838 if (pc_is_mips16 (pc
))
4839 return mips16_skip_prologue (pc
);
4841 return mips32_skip_prologue (pc
);
4844 /* Exported procedure: Is PC in the signal trampoline code */
4847 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
4849 if (sigtramp_address
== 0)
4851 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
4854 /* Root of all "set mips "/"show mips " commands. This will eventually be
4855 used for all MIPS-specific commands. */
4858 show_mips_command (char *args
, int from_tty
)
4860 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4864 set_mips_command (char *args
, int from_tty
)
4867 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4868 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4871 /* Commands to show/set the MIPS FPU type. */
4874 show_mipsfpu_command (char *args
, int from_tty
)
4877 switch (MIPS_FPU_TYPE
)
4879 case MIPS_FPU_SINGLE
:
4880 fpu
= "single-precision";
4882 case MIPS_FPU_DOUBLE
:
4883 fpu
= "double-precision";
4886 fpu
= "absent (none)";
4889 internal_error (__FILE__
, __LINE__
, "bad switch");
4891 if (mips_fpu_type_auto
)
4893 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4897 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4902 set_mipsfpu_command (char *args
, int from_tty
)
4905 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4906 show_mipsfpu_command (args
, from_tty
);
4910 set_mipsfpu_single_command (char *args
, int from_tty
)
4912 struct gdbarch_info info
;
4913 gdbarch_info_init (&info
);
4914 mips_fpu_type
= MIPS_FPU_SINGLE
;
4915 mips_fpu_type_auto
= 0;
4916 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4917 instead of relying on globals. Doing that would let generic code
4918 handle the search for this specific architecture. */
4919 if (!gdbarch_update_p (info
))
4920 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4924 set_mipsfpu_double_command (char *args
, int from_tty
)
4926 struct gdbarch_info info
;
4927 gdbarch_info_init (&info
);
4928 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4929 mips_fpu_type_auto
= 0;
4930 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4931 instead of relying on globals. Doing that would let generic code
4932 handle the search for this specific architecture. */
4933 if (!gdbarch_update_p (info
))
4934 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4938 set_mipsfpu_none_command (char *args
, int from_tty
)
4940 struct gdbarch_info info
;
4941 gdbarch_info_init (&info
);
4942 mips_fpu_type
= MIPS_FPU_NONE
;
4943 mips_fpu_type_auto
= 0;
4944 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4945 instead of relying on globals. Doing that would let generic code
4946 handle the search for this specific architecture. */
4947 if (!gdbarch_update_p (info
))
4948 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4952 set_mipsfpu_auto_command (char *args
, int from_tty
)
4954 mips_fpu_type_auto
= 1;
4957 /* Attempt to identify the particular processor model by reading the
4958 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4959 the relevant processor still exists (it dates back to '94) and
4960 secondly this is not the way to do this. The processor type should
4961 be set by forcing an architecture change. */
4964 deprecated_mips_set_processor_regs_hack (void)
4966 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4969 prid
= read_register (PRID_REGNUM
);
4971 if ((prid
& ~0xf) == 0x700)
4972 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4975 /* Just like reinit_frame_cache, but with the right arguments to be
4976 callable as an sfunc. */
4979 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4980 struct cmd_list_element
*c
)
4982 reinit_frame_cache ();
4986 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4988 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4989 mips_extra_func_info_t proc_desc
;
4991 /* Search for the function containing this address. Set the low bit
4992 of the address when searching, in case we were given an even address
4993 that is the start of a 16-bit function. If we didn't do this,
4994 the search would fail because the symbol table says the function
4995 starts at an odd address, i.e. 1 byte past the given address. */
4996 memaddr
= ADDR_BITS_REMOVE (memaddr
);
4997 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
4999 /* Make an attempt to determine if this is a 16-bit function. If
5000 the procedure descriptor exists and the address therein is odd,
5001 it's definitely a 16-bit function. Otherwise, we have to just
5002 guess that if the address passed in is odd, it's 16-bits. */
5003 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5004 disassembler needs to be able to locally determine the ISA, and
5005 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5009 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5010 info
->mach
= bfd_mach_mips16
;
5014 if (pc_is_mips16 (memaddr
))
5015 info
->mach
= bfd_mach_mips16
;
5018 /* Round down the instruction address to the appropriate boundary. */
5019 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5021 /* Set the disassembler options. */
5022 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5024 /* Set up the disassembler info, so that we get the right
5025 register names from libopcodes. */
5026 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5027 info
->disassembler_options
= "gpr-names=n32";
5029 info
->disassembler_options
= "gpr-names=64";
5030 info
->flavour
= bfd_target_elf_flavour
;
5033 /* This string is not recognized explicitly by the disassembler,
5034 but it tells the disassembler to not try to guess the ABI from
5035 the bfd elf headers, such that, if the user overrides the ABI
5036 of a program linked as NewABI, the disassembly will follow the
5037 register naming conventions specified by the user. */
5038 info
->disassembler_options
= "gpr-names=32";
5040 /* Call the appropriate disassembler based on the target endian-ness. */
5041 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5042 return print_insn_big_mips (memaddr
, info
);
5044 return print_insn_little_mips (memaddr
, info
);
5047 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5048 counter value to determine whether a 16- or 32-bit breakpoint should be
5049 used. It returns a pointer to a string of bytes that encode a breakpoint
5050 instruction, stores the length of the string to *lenptr, and adjusts pc
5051 (if necessary) to point to the actual memory location where the
5052 breakpoint should be inserted. */
5054 static const unsigned char *
5055 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5057 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5059 if (pc_is_mips16 (*pcptr
))
5061 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5062 *pcptr
= unmake_mips16_addr (*pcptr
);
5063 *lenptr
= sizeof (mips16_big_breakpoint
);
5064 return mips16_big_breakpoint
;
5068 /* The IDT board uses an unusual breakpoint value, and
5069 sometimes gets confused when it sees the usual MIPS
5070 breakpoint instruction. */
5071 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5072 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5073 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5075 *lenptr
= sizeof (big_breakpoint
);
5077 if (strcmp (target_shortname
, "mips") == 0)
5078 return idt_big_breakpoint
;
5079 else if (strcmp (target_shortname
, "ddb") == 0
5080 || strcmp (target_shortname
, "pmon") == 0
5081 || strcmp (target_shortname
, "lsi") == 0)
5082 return pmon_big_breakpoint
;
5084 return big_breakpoint
;
5089 if (pc_is_mips16 (*pcptr
))
5091 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5092 *pcptr
= unmake_mips16_addr (*pcptr
);
5093 *lenptr
= sizeof (mips16_little_breakpoint
);
5094 return mips16_little_breakpoint
;
5098 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5099 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5100 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5102 *lenptr
= sizeof (little_breakpoint
);
5104 if (strcmp (target_shortname
, "mips") == 0)
5105 return idt_little_breakpoint
;
5106 else if (strcmp (target_shortname
, "ddb") == 0
5107 || strcmp (target_shortname
, "pmon") == 0
5108 || strcmp (target_shortname
, "lsi") == 0)
5109 return pmon_little_breakpoint
;
5111 return little_breakpoint
;
5116 /* If PC is in a mips16 call or return stub, return the address of the target
5117 PC, which is either the callee or the caller. There are several
5118 cases which must be handled:
5120 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5121 target PC is in $31 ($ra).
5122 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5123 and the target PC is in $2.
5124 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5125 before the jal instruction, this is effectively a call stub
5126 and the the target PC is in $2. Otherwise this is effectively
5127 a return stub and the target PC is in $18.
5129 See the source code for the stubs in gcc/config/mips/mips16.S for
5132 This function implements the SKIP_TRAMPOLINE_CODE macro.
5136 mips_skip_stub (CORE_ADDR pc
)
5139 CORE_ADDR start_addr
;
5141 /* Find the starting address and name of the function containing the PC. */
5142 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5145 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5146 target PC is in $31 ($ra). */
5147 if (strcmp (name
, "__mips16_ret_sf") == 0
5148 || strcmp (name
, "__mips16_ret_df") == 0)
5149 return read_signed_register (RA_REGNUM
);
5151 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5153 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5154 and the target PC is in $2. */
5155 if (name
[19] >= '0' && name
[19] <= '9')
5156 return read_signed_register (2);
5158 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5159 before the jal instruction, this is effectively a call stub
5160 and the the target PC is in $2. Otherwise this is effectively
5161 a return stub and the target PC is in $18. */
5162 else if (name
[19] == 's' || name
[19] == 'd')
5164 if (pc
== start_addr
)
5166 /* Check if the target of the stub is a compiler-generated
5167 stub. Such a stub for a function bar might have a name
5168 like __fn_stub_bar, and might look like this:
5173 la $1,bar (becomes a lui/addiu pair)
5175 So scan down to the lui/addi and extract the target
5176 address from those two instructions. */
5178 CORE_ADDR target_pc
= read_signed_register (2);
5182 /* See if the name of the target function is __fn_stub_*. */
5183 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5186 if (strncmp (name
, "__fn_stub_", 10) != 0
5187 && strcmp (name
, "etext") != 0
5188 && strcmp (name
, "_etext") != 0)
5191 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5192 The limit on the search is arbitrarily set to 20
5193 instructions. FIXME. */
5194 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5196 inst
= mips_fetch_instruction (target_pc
);
5197 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5198 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5199 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5200 return pc
| (inst
& 0xffff); /* low word */
5203 /* Couldn't find the lui/addui pair, so return stub address. */
5207 /* This is the 'return' part of a call stub. The return
5208 address is in $r18. */
5209 return read_signed_register (18);
5212 return 0; /* not a stub */
5216 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5217 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5220 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5222 CORE_ADDR start_addr
;
5224 /* Find the starting address of the function containing the PC. If the
5225 caller didn't give us a name, look it up at the same time. */
5226 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5230 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5232 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5233 if (name
[19] >= '0' && name
[19] <= '9')
5235 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5236 before the jal instruction, this is effectively a call stub. */
5237 else if (name
[19] == 's' || name
[19] == 'd')
5238 return pc
== start_addr
;
5241 return 0; /* not a stub */
5245 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5246 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5249 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5251 CORE_ADDR start_addr
;
5253 /* Find the starting address of the function containing the PC. */
5254 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5257 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5258 if (strcmp (name
, "__mips16_ret_sf") == 0
5259 || strcmp (name
, "__mips16_ret_df") == 0)
5262 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5263 i.e. after the jal instruction, this is effectively a return stub. */
5264 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5265 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5268 return 0; /* not a stub */
5272 /* Return non-zero if the PC is in a library helper function that should
5273 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5276 mips_ignore_helper (CORE_ADDR pc
)
5280 /* Find the starting address and name of the function containing the PC. */
5281 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5284 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5285 that we want to ignore. */
5286 return (strcmp (name
, "__mips16_ret_sf") == 0
5287 || strcmp (name
, "__mips16_ret_df") == 0);
5291 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5292 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5295 mips_stab_reg_to_regnum (int num
)
5298 if (num
>= 0 && num
< 32)
5300 else if (num
>= 38 && num
< 70)
5301 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5303 regnum
= mips_regnum (current_gdbarch
)->hi
;
5305 regnum
= mips_regnum (current_gdbarch
)->lo
;
5307 /* This will hopefully (eventually) provoke a warning. Should
5308 we be calling complaint() here? */
5309 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5310 return NUM_REGS
+ regnum
;
5314 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5315 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5318 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5321 if (num
>= 0 && num
< 32)
5323 else if (num
>= 32 && num
< 64)
5324 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5326 regnum
= mips_regnum (current_gdbarch
)->hi
;
5328 regnum
= mips_regnum (current_gdbarch
)->lo
;
5330 /* This will hopefully (eventually) provoke a warning. Should we
5331 be calling complaint() here? */
5332 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5333 return NUM_REGS
+ regnum
;
5337 mips_register_sim_regno (int regnum
)
5339 /* Only makes sense to supply raw registers. */
5340 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5341 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5342 decide if it is valid. Should instead define a standard sim/gdb
5343 register numbering scheme. */
5344 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5345 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5348 return LEGACY_SIM_REGNO_IGNORE
;
5352 /* Convert an integer into an address. By first converting the value
5353 into a pointer and then extracting it signed, the address is
5354 guarenteed to be correctly sign extended. */
5357 mips_integer_to_address (struct type
*type
, void *buf
)
5359 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5360 LONGEST val
= unpack_long (type
, buf
);
5361 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5362 return extract_signed_integer (tmp
,
5363 TYPE_LENGTH (builtin_type_void_data_ptr
));
5367 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5369 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5370 const char *name
= bfd_get_section_name (abfd
, sect
);
5372 if (*abip
!= MIPS_ABI_UNKNOWN
)
5375 if (strncmp (name
, ".mdebug.", 8) != 0)
5378 if (strcmp (name
, ".mdebug.abi32") == 0)
5379 *abip
= MIPS_ABI_O32
;
5380 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5381 *abip
= MIPS_ABI_N32
;
5382 else if (strcmp (name
, ".mdebug.abi64") == 0)
5383 *abip
= MIPS_ABI_N64
;
5384 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5385 *abip
= MIPS_ABI_O64
;
5386 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5387 *abip
= MIPS_ABI_EABI32
;
5388 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5389 *abip
= MIPS_ABI_EABI64
;
5391 warning ("unsupported ABI %s.", name
+ 8);
5394 static enum mips_abi
5395 global_mips_abi (void)
5399 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5400 if (mips_abi_strings
[i
] == mips_abi_string
)
5401 return (enum mips_abi
) i
;
5403 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5406 static struct gdbarch
*
5407 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5409 struct gdbarch
*gdbarch
;
5410 struct gdbarch_tdep
*tdep
;
5412 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5414 enum mips_fpu_type fpu_type
;
5416 /* First of all, extract the elf_flags, if available. */
5417 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5418 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5419 else if (arches
!= NULL
)
5420 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5424 fprintf_unfiltered (gdb_stdlog
,
5425 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5427 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5428 switch ((elf_flags
& EF_MIPS_ABI
))
5430 case E_MIPS_ABI_O32
:
5431 found_abi
= MIPS_ABI_O32
;
5433 case E_MIPS_ABI_O64
:
5434 found_abi
= MIPS_ABI_O64
;
5436 case E_MIPS_ABI_EABI32
:
5437 found_abi
= MIPS_ABI_EABI32
;
5439 case E_MIPS_ABI_EABI64
:
5440 found_abi
= MIPS_ABI_EABI64
;
5443 if ((elf_flags
& EF_MIPS_ABI2
))
5444 found_abi
= MIPS_ABI_N32
;
5446 found_abi
= MIPS_ABI_UNKNOWN
;
5450 /* GCC creates a pseudo-section whose name describes the ABI. */
5451 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5452 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5454 /* If we have no usefu BFD information, use the ABI from the last
5455 MIPS architecture (if there is one). */
5456 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5457 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5459 /* Try the architecture for any hint of the correct ABI. */
5460 if (found_abi
== MIPS_ABI_UNKNOWN
5461 && info
.bfd_arch_info
!= NULL
5462 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5464 switch (info
.bfd_arch_info
->mach
)
5466 case bfd_mach_mips3900
:
5467 found_abi
= MIPS_ABI_EABI32
;
5469 case bfd_mach_mips4100
:
5470 case bfd_mach_mips5000
:
5471 found_abi
= MIPS_ABI_EABI64
;
5473 case bfd_mach_mips8000
:
5474 case bfd_mach_mips10000
:
5475 /* On Irix, ELF64 executables use the N64 ABI. The
5476 pseudo-sections which describe the ABI aren't present
5477 on IRIX. (Even for executables created by gcc.) */
5478 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5479 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5480 found_abi
= MIPS_ABI_N64
;
5482 found_abi
= MIPS_ABI_N32
;
5488 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5491 /* What has the user specified from the command line? */
5492 wanted_abi
= global_mips_abi ();
5494 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5497 /* Now that we have found what the ABI for this binary would be,
5498 check whether the user is overriding it. */
5499 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5500 mips_abi
= wanted_abi
;
5501 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5502 mips_abi
= found_abi
;
5504 mips_abi
= MIPS_ABI_O32
;
5506 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5509 /* Also used when doing an architecture lookup. */
5511 fprintf_unfiltered (gdb_stdlog
,
5512 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5513 mips64_transfers_32bit_regs_p
);
5515 /* Determine the MIPS FPU type. */
5516 if (!mips_fpu_type_auto
)
5517 fpu_type
= mips_fpu_type
;
5518 else if (info
.bfd_arch_info
!= NULL
5519 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5520 switch (info
.bfd_arch_info
->mach
)
5522 case bfd_mach_mips3900
:
5523 case bfd_mach_mips4100
:
5524 case bfd_mach_mips4111
:
5525 fpu_type
= MIPS_FPU_NONE
;
5527 case bfd_mach_mips4650
:
5528 fpu_type
= MIPS_FPU_SINGLE
;
5531 fpu_type
= MIPS_FPU_DOUBLE
;
5534 else if (arches
!= NULL
)
5535 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5537 fpu_type
= MIPS_FPU_DOUBLE
;
5539 fprintf_unfiltered (gdb_stdlog
,
5540 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5542 /* try to find a pre-existing architecture */
5543 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5545 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5547 /* MIPS needs to be pedantic about which ABI the object is
5549 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5551 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5553 /* Need to be pedantic about which register virtual size is
5555 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5556 != mips64_transfers_32bit_regs_p
)
5558 /* Be pedantic about which FPU is selected. */
5559 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5561 return arches
->gdbarch
;
5564 /* Need a new architecture. Fill in a target specific vector. */
5565 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5566 gdbarch
= gdbarch_alloc (&info
, tdep
);
5567 tdep
->elf_flags
= elf_flags
;
5568 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5569 tdep
->found_abi
= found_abi
;
5570 tdep
->mips_abi
= mips_abi
;
5571 tdep
->mips_fpu_type
= fpu_type
;
5573 /* Initially set everything according to the default ABI/ISA. */
5574 set_gdbarch_short_bit (gdbarch
, 16);
5575 set_gdbarch_int_bit (gdbarch
, 32);
5576 set_gdbarch_float_bit (gdbarch
, 32);
5577 set_gdbarch_double_bit (gdbarch
, 64);
5578 set_gdbarch_long_double_bit (gdbarch
, 64);
5579 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5580 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5581 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5583 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5584 mips_elf_make_msymbol_special
);
5586 /* Fill in the OS dependant register numbers and names. */
5588 const char **reg_names
;
5589 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5590 struct mips_regnum
);
5591 if (info
.osabi
== GDB_OSABI_IRIX
)
5596 regnum
->badvaddr
= 66;
5599 regnum
->fp_control_status
= 69;
5600 regnum
->fp_implementation_revision
= 70;
5602 reg_names
= mips_irix_reg_names
;
5606 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5607 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5608 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5609 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5610 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5611 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5612 regnum
->fp_control_status
= 70;
5613 regnum
->fp_implementation_revision
= 71;
5615 if (info
.bfd_arch_info
!= NULL
5616 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5617 reg_names
= mips_tx39_reg_names
;
5619 reg_names
= mips_generic_reg_names
;
5621 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5622 replaced by read_pc? */
5623 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
);
5624 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5625 set_gdbarch_num_regs (gdbarch
, num_regs
);
5626 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5627 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5628 tdep
->mips_processor_reg_names
= reg_names
;
5629 tdep
->regnum
= regnum
;
5635 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5636 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5637 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5638 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5639 tdep
->default_mask_address_p
= 0;
5640 set_gdbarch_long_bit (gdbarch
, 32);
5641 set_gdbarch_ptr_bit (gdbarch
, 32);
5642 set_gdbarch_long_long_bit (gdbarch
, 64);
5645 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5646 set_gdbarch_deprecated_store_return_value (gdbarch
,
5647 mips_o64_store_return_value
);
5648 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5649 mips_o64_extract_return_value
);
5650 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5651 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5652 tdep
->default_mask_address_p
= 0;
5653 set_gdbarch_long_bit (gdbarch
, 32);
5654 set_gdbarch_ptr_bit (gdbarch
, 32);
5655 set_gdbarch_long_long_bit (gdbarch
, 64);
5656 set_gdbarch_use_struct_convention (gdbarch
,
5657 always_use_struct_convention
);
5659 case MIPS_ABI_EABI32
:
5660 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5661 set_gdbarch_deprecated_store_return_value (gdbarch
,
5662 mips_eabi_store_return_value
);
5663 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5664 mips_eabi_extract_return_value
);
5665 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5666 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5667 tdep
->default_mask_address_p
= 0;
5668 set_gdbarch_long_bit (gdbarch
, 32);
5669 set_gdbarch_ptr_bit (gdbarch
, 32);
5670 set_gdbarch_long_long_bit (gdbarch
, 64);
5671 set_gdbarch_deprecated_reg_struct_has_addr
5672 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5673 set_gdbarch_use_struct_convention (gdbarch
,
5674 mips_eabi_use_struct_convention
);
5676 case MIPS_ABI_EABI64
:
5677 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5678 set_gdbarch_deprecated_store_return_value (gdbarch
,
5679 mips_eabi_store_return_value
);
5680 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5681 mips_eabi_extract_return_value
);
5682 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5683 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5684 tdep
->default_mask_address_p
= 0;
5685 set_gdbarch_long_bit (gdbarch
, 64);
5686 set_gdbarch_ptr_bit (gdbarch
, 64);
5687 set_gdbarch_long_long_bit (gdbarch
, 64);
5688 set_gdbarch_deprecated_reg_struct_has_addr
5689 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5690 set_gdbarch_use_struct_convention (gdbarch
,
5691 mips_eabi_use_struct_convention
);
5694 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5695 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5696 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5697 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5698 tdep
->default_mask_address_p
= 0;
5699 set_gdbarch_long_bit (gdbarch
, 32);
5700 set_gdbarch_ptr_bit (gdbarch
, 32);
5701 set_gdbarch_long_long_bit (gdbarch
, 64);
5704 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5705 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5706 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5707 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5708 tdep
->default_mask_address_p
= 0;
5709 set_gdbarch_long_bit (gdbarch
, 64);
5710 set_gdbarch_ptr_bit (gdbarch
, 64);
5711 set_gdbarch_long_long_bit (gdbarch
, 64);
5714 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
5717 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5718 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5721 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5722 flag in object files because to do so would make it impossible to
5723 link with libraries compiled without "-gp32". This is
5724 unnecessarily restrictive.
5726 We could solve this problem by adding "-gp32" multilibs to gcc,
5727 but to set this flag before gcc is built with such multilibs will
5728 break too many systems.''
5730 But even more unhelpfully, the default linker output target for
5731 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5732 for 64-bit programs - you need to change the ABI to change this,
5733 and not all gcc targets support that currently. Therefore using
5734 this flag to detect 32-bit mode would do the wrong thing given
5735 the current gcc - it would make GDB treat these 64-bit programs
5736 as 32-bit programs by default. */
5738 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5739 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5740 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5742 /* Add/remove bits from an address. The MIPS needs be careful to
5743 ensure that all 32 bit addresses are sign extended to 64 bits. */
5744 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5746 /* Unwind the frame. */
5747 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5748 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5750 /* Map debug register numbers onto internal register numbers. */
5751 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5752 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5753 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5754 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5755 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5756 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5757 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5758 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5760 /* MIPS version of CALL_DUMMY */
5762 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5763 replaced by a command, and all targets will default to on stack
5764 (regardless of the stack's execute status). */
5765 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5766 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5768 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5769 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5770 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5772 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5773 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5775 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5777 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5778 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5779 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5781 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5783 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5784 set_gdbarch_deprecated_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
5786 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5788 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5789 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5790 need to all be folded into the target vector. Since they are
5791 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5792 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5794 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5796 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
5798 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
5799 to support MIPS16. This is a bad thing. Make sure not to do it
5800 if we have an OS ABI that actually supports shared libraries, since
5801 shared library support is more important. If we have an OS someday
5802 that supports both shared libraries and MIPS16, we'll have to find
5803 a better place for these. */
5804 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
5806 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
5807 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
5810 /* Hook in OS ABI-specific overrides, if they have been registered. */
5811 gdbarch_init_osabi (info
, gdbarch
);
5813 /* Unwind the frame. */
5814 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
5815 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
5821 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5823 struct gdbarch_info info
;
5825 /* Force the architecture to update, and (if it's a MIPS architecture)
5826 mips_gdbarch_init will take care of the rest. */
5827 gdbarch_info_init (&info
);
5828 gdbarch_update_p (info
);
5831 /* Print out which MIPS ABI is in use. */
5834 show_mips_abi (char *ignore_args
, int from_tty
)
5836 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5838 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
5841 enum mips_abi global_abi
= global_mips_abi ();
5842 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5843 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5845 if (global_abi
== MIPS_ABI_UNKNOWN
)
5847 ("The MIPS ABI is set automatically (currently \"%s\").\n",
5849 else if (global_abi
== actual_abi
)
5851 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5855 /* Probably shouldn't happen... */
5857 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5858 actual_abi_str
, mips_abi_strings
[global_abi
]);
5864 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5866 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5870 int ef_mips_32bitmode
;
5871 /* determine the ISA */
5872 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5890 /* determine the size of a pointer */
5891 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5892 fprintf_unfiltered (file
,
5893 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5895 fprintf_unfiltered (file
,
5896 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5898 fprintf_unfiltered (file
,
5899 "mips_dump_tdep: ef_mips_arch = %d\n",
5901 fprintf_unfiltered (file
,
5902 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5903 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5904 fprintf_unfiltered (file
,
5905 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5906 mips_mask_address_p (tdep
),
5907 tdep
->default_mask_address_p
);
5909 fprintf_unfiltered (file
,
5910 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5911 MIPS_DEFAULT_FPU_TYPE
,
5912 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5913 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5914 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5916 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5917 fprintf_unfiltered (file
,
5918 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5920 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5921 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5922 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5924 fprintf_unfiltered (file
,
5925 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5926 mips_stack_argsize (current_gdbarch
));
5927 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
5928 fprintf_unfiltered (file
,
5929 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
5930 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
5931 fprintf_unfiltered (file
,
5932 "mips_dump_tdep: ATTACH_DETACH # %s\n",
5933 XSTRING (ATTACH_DETACH
));
5934 fprintf_unfiltered (file
,
5935 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
5936 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
5937 fprintf_unfiltered (file
,
5938 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
5939 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
5940 fprintf_unfiltered (file
,
5941 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
5942 FIRST_EMBED_REGNUM
);
5943 fprintf_unfiltered (file
,
5944 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
5945 XSTRING (IGNORE_HELPER_CALL (PC
)));
5946 fprintf_unfiltered (file
,
5947 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
5948 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
5949 fprintf_unfiltered (file
,
5950 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
5951 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
5952 fprintf_unfiltered (file
,
5953 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
5955 #ifdef MACHINE_CPROC_FP_OFFSET
5956 fprintf_unfiltered (file
,
5957 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
5958 MACHINE_CPROC_FP_OFFSET
);
5960 #ifdef MACHINE_CPROC_PC_OFFSET
5961 fprintf_unfiltered (file
,
5962 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
5963 MACHINE_CPROC_PC_OFFSET
);
5965 #ifdef MACHINE_CPROC_SP_OFFSET
5966 fprintf_unfiltered (file
,
5967 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
5968 MACHINE_CPROC_SP_OFFSET
);
5970 fprintf_unfiltered (file
,
5971 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
5973 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
5974 fprintf_unfiltered (file
,
5975 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
5976 fprintf_unfiltered (file
,
5977 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
5978 fprintf_unfiltered (file
,
5979 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
5980 MIPS_LAST_ARG_REGNUM
,
5981 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
5982 fprintf_unfiltered (file
,
5983 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
5984 fprintf_unfiltered (file
,
5985 "mips_dump_tdep: mips_abi_regsize() = %d\n",
5986 mips_abi_regsize (current_gdbarch
));
5987 fprintf_unfiltered (file
,
5988 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
5989 fprintf_unfiltered (file
,
5990 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
5991 fprintf_unfiltered (file
,
5992 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
5993 fprintf_unfiltered (file
,
5994 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
5995 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
5996 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
5997 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
5998 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
5999 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6000 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6001 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6002 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6003 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6004 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6005 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6007 fprintf_unfiltered (file
,
6008 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6011 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6014 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6016 fprintf_unfiltered (file
,
6017 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6018 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6019 fprintf_unfiltered (file
,
6020 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6021 fprintf_unfiltered (file
,
6022 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6023 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6024 fprintf_unfiltered (file
,
6025 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6026 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6027 fprintf_unfiltered (file
,
6028 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6029 SOFTWARE_SINGLE_STEP_P ());
6030 fprintf_unfiltered (file
,
6031 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6032 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6033 #ifdef STACK_END_ADDR
6034 fprintf_unfiltered (file
,
6035 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6038 fprintf_unfiltered (file
,
6039 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6040 XSTRING (STEP_SKIPS_DELAY (PC
)));
6041 fprintf_unfiltered (file
,
6042 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6043 STEP_SKIPS_DELAY_P
);
6044 fprintf_unfiltered (file
,
6045 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6046 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6047 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6048 fprintf_unfiltered (file
,
6049 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6050 fprintf_unfiltered (file
,
6051 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6052 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6053 (TYPE
, CNT
, OTHERTYPE
)));
6054 fprintf_unfiltered (file
,
6055 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6056 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6058 fprintf_unfiltered (file
,
6059 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6060 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6063 fprintf_unfiltered (file
,
6064 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6066 #ifdef TRACE_FLAVOR_SIZE
6067 fprintf_unfiltered (file
,
6068 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6072 fprintf_unfiltered (file
,
6073 "mips_dump_tdep: TRACE_SET # %s\n",
6074 XSTRING (TRACE_SET (X
, STATE
)));
6076 #ifdef UNUSED_REGNUM
6077 fprintf_unfiltered (file
,
6078 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6080 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6081 fprintf_unfiltered (file
,
6082 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6083 (long) VM_MIN_ADDRESS
);
6084 fprintf_unfiltered (file
,
6085 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6086 fprintf_unfiltered (file
,
6087 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_
);
6090 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6093 _initialize_mips_tdep (void)
6095 static struct cmd_list_element
*mipsfpulist
= NULL
;
6096 struct cmd_list_element
*c
;
6098 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6099 if (MIPS_ABI_LAST
+ 1
6100 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6101 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6103 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6105 mips_pdr_data
= register_objfile_data ();
6107 /* Add root prefix command for all "set mips"/"show mips" commands */
6108 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6109 "Various MIPS specific commands.",
6110 &setmipscmdlist
, "set mips ", 0, &setlist
);
6112 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6113 "Various MIPS specific commands.",
6114 &showmipscmdlist
, "show mips ", 0, &showlist
);
6116 /* Allow the user to override the saved register size. */
6117 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6120 &mips_abi_regsize_string
, "\
6121 Set size of general purpose registers saved on the stack.\n\
6122 This option can be set to one of:\n\
6123 32 - Force GDB to treat saved GP registers as 32-bit\n\
6124 64 - Force GDB to treat saved GP registers as 64-bit\n\
6125 auto - Allow GDB to use the target's default setting or autodetect the\n\
6126 saved GP register size from information contained in the executable.\n\
6127 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6129 /* Allow the user to override the argument stack size. */
6130 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6133 &mips_stack_argsize_string
, "\
6134 Set the amount of stack space reserved for each argument.\n\
6135 This option can be set to one of:\n\
6136 32 - Force GDB to allocate 32-bit chunks per argument\n\
6137 64 - Force GDB to allocate 64-bit chunks per argument\n\
6138 auto - Allow GDB to determine the correct setting from the current\n\
6139 target and executable (default)", &setmipscmdlist
), &showmipscmdlist
);
6141 /* Allow the user to override the ABI. */
6142 c
= add_set_enum_cmd
6143 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6144 "Set the ABI used by this program.\n"
6145 "This option can be set to one of:\n"
6146 " auto - the default ABI associated with the current binary\n"
6148 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6149 set_cmd_sfunc (c
, mips_abi_update
);
6150 add_cmd ("abi", class_obscure
, show_mips_abi
,
6151 "Show ABI in use by MIPS target", &showmipscmdlist
);
6153 /* Let the user turn off floating point and set the fence post for
6154 heuristic_proc_start. */
6156 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6157 "Set use of MIPS floating-point coprocessor.",
6158 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6159 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6160 "Select single-precision MIPS floating-point coprocessor.",
6162 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6163 "Select double-precision MIPS floating-point coprocessor.",
6165 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6166 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6167 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6168 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6169 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6170 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6171 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6172 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6173 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6174 "Select MIPS floating-point coprocessor automatically.",
6176 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6177 "Show current use of MIPS floating-point coprocessor target.",
6180 /* We really would like to have both "0" and "unlimited" work, but
6181 command.c doesn't deal with that. So make it a var_zinteger
6182 because the user can always use "999999" or some such for unlimited. */
6183 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6184 (char *) &heuristic_fence_post
, "\
6185 Set the distance searched for the start of a function.\n\
6186 If you are debugging a stripped executable, GDB needs to search through the\n\
6187 program for the start of a function. This command sets the distance of the\n\
6188 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6189 /* We need to throw away the frame cache when we set this, since it
6190 might change our ability to get backtraces. */
6191 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6192 add_show_from_set (c
, &showlist
);
6194 /* Allow the user to control whether the upper bits of 64-bit
6195 addresses should be zeroed. */
6196 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6197 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6198 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6199 allow GDB to determine the correct value.\n", "\
6200 Show zeroing of upper 32 bits of 64-bit addresses.",
6201 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6203 /* Allow the user to control the size of 32 bit registers within the
6204 raw remote packet. */
6205 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6206 var_boolean
, &mips64_transfers_32bit_regs_p
, "\
6207 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6208 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6209 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6210 64 bits for others. Use \"off\" to disable compatibility mode", "\
6211 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6212 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6213 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6214 64 bits for others. Use \"off\" to disable compatibility mode", set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6216 /* Debug this files internals. */
6217 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6218 &mips_debug
, "Set mips debugging.\n\
6219 When non-zero, mips specific debugging is enabled.", &setdebuglist
), &showdebuglist
);