1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 /* Some MIPS boards don't support floating point while others only
146 support single-precision floating-point operations. */
150 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
151 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
152 MIPS_FPU_NONE
/* No floating point. */
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto
= 1;
159 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
161 static int mips_debug
= 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc
*mips_tdesc_gp32
;
169 struct target_desc
*mips_tdesc_gp64
;
171 /* MIPS specific per-architecture information */
174 /* from the elf header */
178 enum mips_abi mips_abi
;
179 enum mips_abi found_abi
;
180 enum mips_fpu_type mips_fpu_type
;
181 int mips_last_arg_regnum
;
182 int mips_last_fp_arg_regnum
;
183 int default_mask_address_p
;
184 /* Is the target using 64-bit raw integer registers but only
185 storing a left-aligned 32-bit value in each? */
186 int mips64_transfers_32bit_regs_p
;
187 /* Indexes for various registers. IRIX and embedded have
188 different values. This contains the "public" fields. Don't
189 add any that do not need to be public. */
190 const struct mips_regnum
*regnum
;
191 /* Register names table for the current register set. */
192 const char **mips_processor_reg_names
;
194 /* The size of register data available from the target, if known.
195 This doesn't quite obsolete the manual
196 mips64_transfers_32bit_regs_p, since that is documented to force
197 left alignment even for big endian (very strange). */
198 int register_size_valid_p
;
202 const struct mips_regnum
*
203 mips_regnum (struct gdbarch
*gdbarch
)
205 return gdbarch_tdep (gdbarch
)->regnum
;
209 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
211 return mips_regnum (gdbarch
)->fp0
+ 12;
214 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
216 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
218 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
220 #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
222 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
224 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
225 functions to test, set, or clear bit 0 of addresses. */
228 is_mips16_addr (CORE_ADDR addr
)
234 unmake_mips16_addr (CORE_ADDR addr
)
236 return ((addr
) & ~(CORE_ADDR
) 1);
239 /* Return the MIPS ABI associated with GDBARCH. */
241 mips_abi (struct gdbarch
*gdbarch
)
243 return gdbarch_tdep (gdbarch
)->mips_abi
;
247 mips_isa_regsize (struct gdbarch
*gdbarch
)
249 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
251 /* If we know how big the registers are, use that size. */
252 if (tdep
->register_size_valid_p
)
253 return tdep
->register_size
;
255 /* Fall back to the previous behavior. */
256 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
257 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
260 /* Return the currently configured (or set) saved register size. */
263 mips_abi_regsize (struct gdbarch
*gdbarch
)
265 switch (mips_abi (gdbarch
))
267 case MIPS_ABI_EABI32
:
273 case MIPS_ABI_EABI64
:
275 case MIPS_ABI_UNKNOWN
:
278 internal_error (__FILE__
, __LINE__
, _("bad switch"));
282 /* Functions for setting and testing a bit in a minimal symbol that
283 marks it as 16-bit function. The MSB of the minimal symbol's
284 "info" field is used for this purpose.
286 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
287 i.e. refers to a 16-bit function, and sets a "special" bit in a
288 minimal symbol to mark it as a 16-bit function
290 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
293 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
295 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
297 MSYMBOL_INFO (msym
) = (char *)
298 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
299 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
304 msymbol_is_special (struct minimal_symbol
*msym
)
306 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
309 /* XFER a value from the big/little/left end of the register.
310 Depending on the size of the value it might occupy the entire
311 register or just part of it. Make an allowance for this, aligning
312 things accordingly. */
315 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
316 int reg_num
, int length
,
317 enum bfd_endian endian
, gdb_byte
*in
,
318 const gdb_byte
*out
, int buf_offset
)
322 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
323 /* Need to transfer the left or right part of the register, based on
324 the targets byte order. */
328 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
330 case BFD_ENDIAN_LITTLE
:
333 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
337 internal_error (__FILE__
, __LINE__
, _("bad switch"));
340 fprintf_unfiltered (gdb_stderr
,
341 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
342 reg_num
, reg_offset
, buf_offset
, length
);
343 if (mips_debug
&& out
!= NULL
)
346 fprintf_unfiltered (gdb_stdlog
, "out ");
347 for (i
= 0; i
< length
; i
++)
348 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
351 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
354 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
356 if (mips_debug
&& in
!= NULL
)
359 fprintf_unfiltered (gdb_stdlog
, "in ");
360 for (i
= 0; i
< length
; i
++)
361 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
364 fprintf_unfiltered (gdb_stdlog
, "\n");
367 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
368 compatiblity mode. A return value of 1 means that we have
369 physical 64-bit registers, but should treat them as 32-bit registers. */
372 mips2_fp_compat (struct frame_info
*frame
)
374 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
375 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
377 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
381 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
382 in all the places we deal with FP registers. PR gdb/413. */
383 /* Otherwise check the FR bit in the status register - it controls
384 the FP compatiblity mode. If it is clear we are in compatibility
386 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
393 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
395 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
397 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
399 static struct type
*mips_float_register_type (void);
400 static struct type
*mips_double_register_type (void);
402 /* The list of available "set mips " and "show mips " commands */
404 static struct cmd_list_element
*setmipscmdlist
= NULL
;
405 static struct cmd_list_element
*showmipscmdlist
= NULL
;
407 /* Integer registers 0 thru 31 are handled explicitly by
408 mips_register_name(). Processor specific registers 32 and above
409 are listed in the following tables. */
412 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
416 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
417 "sr", "lo", "hi", "bad", "cause", "pc",
418 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
419 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
420 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
421 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
422 "fsr", "fir", "" /*"fp" */ , "",
423 "", "", "", "", "", "", "", "",
424 "", "", "", "", "", "", "", "",
427 /* Names of IDT R3041 registers. */
429 static const char *mips_r3041_reg_names
[] = {
430 "sr", "lo", "hi", "bad", "cause", "pc",
431 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
432 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
433 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
434 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
435 "fsr", "fir", "", /*"fp" */ "",
436 "", "", "bus", "ccfg", "", "", "", "",
437 "", "", "port", "cmp", "", "", "epc", "prid",
440 /* Names of tx39 registers. */
442 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
443 "sr", "lo", "hi", "bad", "cause", "pc",
444 "", "", "", "", "", "", "", "",
445 "", "", "", "", "", "", "", "",
446 "", "", "", "", "", "", "", "",
447 "", "", "", "", "", "", "", "",
449 "", "", "", "", "", "", "", "",
450 "", "", "config", "cache", "debug", "depc", "epc", ""
453 /* Names of IRIX registers. */
454 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
455 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
456 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
457 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
458 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
459 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
463 /* Return the name of the register corresponding to REGNO. */
465 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
467 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
468 /* GPR names for all ABIs other than n32/n64. */
469 static char *mips_gpr_names
[] = {
470 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
471 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
472 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
473 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
476 /* GPR names for n32 and n64 ABIs. */
477 static char *mips_n32_n64_gpr_names
[] = {
478 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
479 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
480 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
481 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
484 enum mips_abi abi
= mips_abi (gdbarch
);
486 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
487 but then don't make the raw register names visible. */
488 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
489 if (regno
< gdbarch_num_regs (gdbarch
))
492 /* The MIPS integer registers are always mapped from 0 to 31. The
493 names of the registers (which reflects the conventions regarding
494 register use) vary depending on the ABI. */
495 if (0 <= rawnum
&& rawnum
< 32)
497 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
498 return mips_n32_n64_gpr_names
[rawnum
];
500 return mips_gpr_names
[rawnum
];
502 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
503 return tdesc_register_name (gdbarch
, rawnum
);
504 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
506 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
507 return tdep
->mips_processor_reg_names
[rawnum
- 32];
510 internal_error (__FILE__
, __LINE__
,
511 _("mips_register_name: bad register number %d"), rawnum
);
514 /* Return the groups that a MIPS register can be categorised into. */
517 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
518 struct reggroup
*reggroup
)
523 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
524 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
525 if (reggroup
== all_reggroup
)
527 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
528 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
529 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
530 (gdbarch), as not all architectures are multi-arch. */
531 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
532 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
533 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
535 if (reggroup
== float_reggroup
)
536 return float_p
&& pseudo
;
537 if (reggroup
== vector_reggroup
)
538 return vector_p
&& pseudo
;
539 if (reggroup
== general_reggroup
)
540 return (!vector_p
&& !float_p
) && pseudo
;
541 /* Save the pseudo registers. Need to make certain that any code
542 extracting register values from a saved register cache also uses
544 if (reggroup
== save_reggroup
)
545 return raw_p
&& pseudo
;
546 /* Restore the same pseudo register. */
547 if (reggroup
== restore_reggroup
)
548 return raw_p
&& pseudo
;
552 /* Return the groups that a MIPS register can be categorised into.
553 This version is only used if we have a target description which
554 describes real registers (and their groups). */
557 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
558 struct reggroup
*reggroup
)
560 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
561 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
564 /* Only save, restore, and display the pseudo registers. Need to
565 make certain that any code extracting register values from a
566 saved register cache also uses pseudo registers.
568 Note: saving and restoring the pseudo registers is slightly
569 strange; if we have 64 bits, we should save and restore all
570 64 bits. But this is hard and has little benefit. */
574 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
578 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
581 /* Map the symbol table registers which live in the range [1 *
582 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
583 registers. Take care of alignment and size problems. */
586 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
587 int cookednum
, gdb_byte
*buf
)
589 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
590 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
591 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
592 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
593 regcache_raw_read (regcache
, rawnum
, buf
);
594 else if (register_size (gdbarch
, rawnum
) >
595 register_size (gdbarch
, cookednum
))
597 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
598 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
599 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
601 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
604 internal_error (__FILE__
, __LINE__
, _("bad register size"));
608 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
609 struct regcache
*regcache
, int cookednum
,
612 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
613 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
614 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
615 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
616 regcache_raw_write (regcache
, rawnum
, buf
);
617 else if (register_size (gdbarch
, rawnum
) >
618 register_size (gdbarch
, cookednum
))
620 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
621 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
622 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
624 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
627 internal_error (__FILE__
, __LINE__
, _("bad register size"));
630 /* Table to translate MIPS16 register field to actual register number. */
631 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
633 /* Heuristic_proc_start may hunt through the text section for a long
634 time across a 2400 baud serial line. Allows the user to limit this
637 static unsigned int heuristic_fence_post
= 0;
639 /* Number of bytes of storage in the actual machine representation for
640 register N. NOTE: This defines the pseudo register type so need to
641 rebuild the architecture vector. */
643 static int mips64_transfers_32bit_regs_p
= 0;
646 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
647 struct cmd_list_element
*c
)
649 struct gdbarch_info info
;
650 gdbarch_info_init (&info
);
651 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
652 instead of relying on globals. Doing that would let generic code
653 handle the search for this specific architecture. */
654 if (!gdbarch_update_p (info
))
656 mips64_transfers_32bit_regs_p
= 0;
657 error (_("32-bit compatibility mode not supported"));
661 /* Convert to/from a register and the corresponding memory value. */
664 mips_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
666 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
667 && register_size (gdbarch
, regnum
) == 4
668 && (regnum
% gdbarch_num_regs (gdbarch
))
669 >= mips_regnum (gdbarch
)->fp0
670 && (regnum
% gdbarch_num_regs (gdbarch
))
671 < mips_regnum (gdbarch
)->fp0
+ 32
672 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
676 mips_register_to_value (struct frame_info
*frame
, int regnum
,
677 struct type
*type
, gdb_byte
*to
)
679 get_frame_register (frame
, regnum
+ 0, to
+ 4);
680 get_frame_register (frame
, regnum
+ 1, to
+ 0);
684 mips_value_to_register (struct frame_info
*frame
, int regnum
,
685 struct type
*type
, const gdb_byte
*from
)
687 put_frame_register (frame
, regnum
+ 0, from
+ 4);
688 put_frame_register (frame
, regnum
+ 1, from
+ 0);
691 /* Return the GDB type object for the "standard" data type of data in
695 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
697 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
698 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
699 && (regnum
% gdbarch_num_regs (gdbarch
))
700 < mips_regnum (gdbarch
)->fp0
+ 32)
702 /* The floating-point registers raw, or cooked, always match
703 mips_isa_regsize(), and also map 1:1, byte for byte. */
704 if (mips_isa_regsize (gdbarch
) == 4)
705 return builtin_type_ieee_single
;
707 return builtin_type_ieee_double
;
709 else if (regnum
< gdbarch_num_regs (gdbarch
))
711 /* The raw or ISA registers. These are all sized according to
713 if (mips_isa_regsize (gdbarch
) == 4)
714 return builtin_type_int32
;
716 return builtin_type_int64
;
720 /* The cooked or ABI registers. These are sized according to
721 the ABI (with a few complications). */
722 if (regnum
>= (gdbarch_num_regs (gdbarch
)
723 + mips_regnum (gdbarch
)->fp_control_status
)
724 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
725 /* The pseudo/cooked view of the embedded registers is always
726 32-bit. The raw view is handled below. */
727 return builtin_type_int32
;
728 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
729 /* The target, while possibly using a 64-bit register buffer,
730 is only transfering 32-bits of each integer register.
731 Reflect this in the cooked/pseudo (ABI) register value. */
732 return builtin_type_int32
;
733 else if (mips_abi_regsize (gdbarch
) == 4)
734 /* The ABI is restricted to 32-bit registers (the ISA could be
736 return builtin_type_int32
;
739 return builtin_type_int64
;
743 /* Return the GDB type for the pseudo register REGNUM, which is the
744 ABI-level view. This function is only called if there is a target
745 description which includes registers, so we know precisely the
746 types of hardware registers. */
749 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
751 const int num_regs
= gdbarch_num_regs (gdbarch
);
752 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
753 int rawnum
= regnum
% num_regs
;
754 struct type
*rawtype
;
756 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
758 /* Absent registers are still absent. */
759 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
760 if (TYPE_LENGTH (rawtype
) == 0)
763 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
764 /* Present the floating point registers however the hardware did;
765 do not try to convert between FPU layouts. */
768 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
770 /* The pseudo/cooked view of embedded registers is always
771 32-bit, even if the target transfers 64-bit values for them.
772 New targets relying on XML descriptions should only transfer
773 the necessary 32 bits, but older versions of GDB expected 64,
774 so allow the target to provide 64 bits without interfering
775 with the displayed type. */
776 return builtin_type_int32
;
779 /* Use pointer types for registers if we can. For n32 we can not,
780 since we do not have a 64-bit pointer type. */
781 if (mips_abi_regsize (gdbarch
) == TYPE_LENGTH (builtin_type_void_data_ptr
))
783 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
784 return builtin_type_void_data_ptr
;
785 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
786 return builtin_type_void_func_ptr
;
789 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
790 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
791 return builtin_type_int32
;
793 /* For all other registers, pass through the hardware type. */
797 /* Should the upper word of 64-bit addresses be zeroed? */
798 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
801 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
803 switch (mask_address_var
)
805 case AUTO_BOOLEAN_TRUE
:
807 case AUTO_BOOLEAN_FALSE
:
810 case AUTO_BOOLEAN_AUTO
:
811 return tdep
->default_mask_address_p
;
813 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
819 show_mask_address (struct ui_file
*file
, int from_tty
,
820 struct cmd_list_element
*c
, const char *value
)
822 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
824 deprecated_show_value_hack (file
, from_tty
, c
, value
);
825 switch (mask_address_var
)
827 case AUTO_BOOLEAN_TRUE
:
828 printf_filtered ("The 32 bit mips address mask is enabled\n");
830 case AUTO_BOOLEAN_FALSE
:
831 printf_filtered ("The 32 bit mips address mask is disabled\n");
833 case AUTO_BOOLEAN_AUTO
:
835 ("The 32 bit address mask is set automatically. Currently %s\n",
836 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
839 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
844 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
847 mips_pc_is_mips16 (CORE_ADDR memaddr
)
849 struct minimal_symbol
*sym
;
851 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
852 if (is_mips16_addr (memaddr
))
855 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
856 the high bit of the info field. Use this to decide if the function is
857 MIPS16 or normal MIPS. */
858 sym
= lookup_minimal_symbol_by_pc (memaddr
);
860 return msymbol_is_special (sym
);
865 /* MIPS believes that the PC has a sign extended value. Perhaps the
866 all registers should be sign extended for simplicity? */
869 mips_read_pc (struct regcache
*regcache
)
872 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
873 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
878 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
880 return frame_unwind_register_signed
881 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
885 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
887 return frame_unwind_register_signed
888 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
891 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
892 dummy frame. The frame ID's base needs to match the TOS value
893 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
896 static struct frame_id
897 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
899 return frame_id_build
900 (get_frame_register_signed (this_frame
,
901 gdbarch_num_regs (gdbarch
)
903 get_frame_pc (this_frame
));
907 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
909 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
910 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
913 /* Fetch and return instruction from the specified location. If the PC
914 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
917 mips_fetch_instruction (CORE_ADDR addr
)
919 gdb_byte buf
[MIPS_INSN32_SIZE
];
923 if (mips_pc_is_mips16 (addr
))
925 instlen
= MIPS_INSN16_SIZE
;
926 addr
= unmake_mips16_addr (addr
);
929 instlen
= MIPS_INSN32_SIZE
;
930 status
= target_read_memory (addr
, buf
, instlen
);
932 memory_error (status
, addr
);
933 return extract_unsigned_integer (buf
, instlen
);
936 /* These the fields of 32 bit mips instructions */
937 #define mips32_op(x) (x >> 26)
938 #define itype_op(x) (x >> 26)
939 #define itype_rs(x) ((x >> 21) & 0x1f)
940 #define itype_rt(x) ((x >> 16) & 0x1f)
941 #define itype_immediate(x) (x & 0xffff)
943 #define jtype_op(x) (x >> 26)
944 #define jtype_target(x) (x & 0x03ffffff)
946 #define rtype_op(x) (x >> 26)
947 #define rtype_rs(x) ((x >> 21) & 0x1f)
948 #define rtype_rt(x) ((x >> 16) & 0x1f)
949 #define rtype_rd(x) ((x >> 11) & 0x1f)
950 #define rtype_shamt(x) ((x >> 6) & 0x1f)
951 #define rtype_funct(x) (x & 0x3f)
954 mips32_relative_offset (ULONGEST inst
)
956 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
959 /* Determine where to set a single step breakpoint while considering
960 branch prediction. */
962 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
966 inst
= mips_fetch_instruction (pc
);
967 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
969 if (itype_op (inst
) >> 2 == 5)
970 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
972 op
= (itype_op (inst
) & 0x03);
987 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
988 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
990 int tf
= itype_rt (inst
) & 0x01;
991 int cnum
= itype_rt (inst
) >> 2;
993 get_frame_register_signed (frame
,
994 mips_regnum (get_frame_arch (frame
))->
996 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
998 if (((cond
>> cnum
) & 0x01) == tf
)
999 pc
+= mips32_relative_offset (inst
) + 4;
1004 pc
+= 4; /* Not a branch, next instruction is easy */
1007 { /* This gets way messy */
1009 /* Further subdivide into SPECIAL, REGIMM and other */
1010 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1012 case 0: /* SPECIAL */
1013 op
= rtype_funct (inst
);
1018 /* Set PC to that address */
1019 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1025 break; /* end SPECIAL */
1026 case 1: /* REGIMM */
1028 op
= itype_rt (inst
); /* branch condition */
1033 case 16: /* BLTZAL */
1034 case 18: /* BLTZALL */
1036 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1037 pc
+= mips32_relative_offset (inst
) + 4;
1039 pc
+= 8; /* after the delay slot */
1043 case 17: /* BGEZAL */
1044 case 19: /* BGEZALL */
1045 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1046 pc
+= mips32_relative_offset (inst
) + 4;
1048 pc
+= 8; /* after the delay slot */
1050 /* All of the other instructions in the REGIMM category */
1055 break; /* end REGIMM */
1060 reg
= jtype_target (inst
) << 2;
1061 /* Upper four bits get never changed... */
1062 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1065 /* FIXME case JALX : */
1068 reg
= jtype_target (inst
) << 2;
1069 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1070 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1072 break; /* The new PC will be alternate mode */
1073 case 4: /* BEQ, BEQL */
1075 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1076 get_frame_register_signed (frame
, itype_rt (inst
)))
1077 pc
+= mips32_relative_offset (inst
) + 4;
1081 case 5: /* BNE, BNEL */
1083 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1084 get_frame_register_signed (frame
, itype_rt (inst
)))
1085 pc
+= mips32_relative_offset (inst
) + 4;
1089 case 6: /* BLEZ, BLEZL */
1090 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1091 pc
+= mips32_relative_offset (inst
) + 4;
1097 greater_branch
: /* BGTZ, BGTZL */
1098 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1099 pc
+= mips32_relative_offset (inst
) + 4;
1106 } /* mips32_next_pc */
1108 /* Decoding the next place to set a breakpoint is irregular for the
1109 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1110 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1111 We dont want to set a single step instruction on the extend instruction
1115 /* Lots of mips16 instruction formats */
1116 /* Predicting jumps requires itype,ritype,i8type
1117 and their extensions extItype,extritype,extI8type
1119 enum mips16_inst_fmts
1121 itype
, /* 0 immediate 5,10 */
1122 ritype
, /* 1 5,3,8 */
1123 rrtype
, /* 2 5,3,3,5 */
1124 rritype
, /* 3 5,3,3,5 */
1125 rrrtype
, /* 4 5,3,3,3,2 */
1126 rriatype
, /* 5 5,3,3,1,4 */
1127 shifttype
, /* 6 5,3,3,3,2 */
1128 i8type
, /* 7 5,3,8 */
1129 i8movtype
, /* 8 5,3,3,5 */
1130 i8mov32rtype
, /* 9 5,3,5,3 */
1131 i64type
, /* 10 5,3,8 */
1132 ri64type
, /* 11 5,3,3,5 */
1133 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1134 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1135 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1136 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1137 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1138 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1139 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1140 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1141 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1142 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1144 /* I am heaping all the fields of the formats into one structure and
1145 then, only the fields which are involved in instruction extension */
1149 unsigned int regx
; /* Function in i8 type */
1154 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1155 for the bits which make up the immediate extension. */
1158 extended_offset (unsigned int extension
)
1161 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1163 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1165 value
|= extension
& 0x01f; /* extract 4:0 */
1169 /* Only call this function if you know that this is an extendable
1170 instruction. It won't malfunction, but why make excess remote memory
1171 references? If the immediate operands get sign extended or something,
1172 do it after the extension is performed. */
1173 /* FIXME: Every one of these cases needs to worry about sign extension
1174 when the offset is to be used in relative addressing. */
1177 fetch_mips_16 (CORE_ADDR pc
)
1180 pc
&= 0xfffffffe; /* clear the low order bit */
1181 target_read_memory (pc
, buf
, 2);
1182 return extract_unsigned_integer (buf
, 2);
1186 unpack_mips16 (CORE_ADDR pc
,
1187 unsigned int extension
,
1189 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1194 switch (insn_format
)
1201 value
= extended_offset (extension
);
1202 value
= value
<< 11; /* rom for the original value */
1203 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1207 value
= inst
& 0x7ff;
1208 /* FIXME : Consider sign extension */
1217 { /* A register identifier and an offset */
1218 /* Most of the fields are the same as I type but the
1219 immediate value is of a different length */
1223 value
= extended_offset (extension
);
1224 value
= value
<< 8; /* from the original instruction */
1225 value
|= inst
& 0xff; /* eleven bits from instruction */
1226 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1227 if (value
& 0x4000) /* test the sign bit , bit 26 */
1229 value
&= ~0x3fff; /* remove the sign bit */
1235 value
= inst
& 0xff; /* 8 bits */
1236 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1237 /* FIXME: Do sign extension , this format needs it */
1238 if (value
& 0x80) /* THIS CONFUSES ME */
1240 value
&= 0xef; /* remove the sign bit */
1250 unsigned long value
;
1251 unsigned int nexthalf
;
1252 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1253 value
= value
<< 16;
1254 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1262 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1264 upk
->offset
= offset
;
1271 add_offset_16 (CORE_ADDR pc
, int offset
)
1273 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1277 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1278 unsigned int extension
, unsigned int insn
)
1280 int op
= (insn
>> 11);
1283 case 2: /* Branch */
1286 struct upk_mips16 upk
;
1287 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1288 offset
= upk
.offset
;
1294 pc
+= (offset
<< 1) + 2;
1297 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1299 struct upk_mips16 upk
;
1300 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1301 pc
= add_offset_16 (pc
, upk
.offset
);
1302 if ((insn
>> 10) & 0x01) /* Exchange mode */
1303 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1310 struct upk_mips16 upk
;
1312 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1313 reg
= get_frame_register_signed (frame
, upk
.regx
);
1315 pc
+= (upk
.offset
<< 1) + 2;
1322 struct upk_mips16 upk
;
1324 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1325 reg
= get_frame_register_signed (frame
, upk
.regx
);
1327 pc
+= (upk
.offset
<< 1) + 2;
1332 case 12: /* I8 Formats btez btnez */
1334 struct upk_mips16 upk
;
1336 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1337 /* upk.regx contains the opcode */
1338 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1339 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1340 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1341 /* pc = add_offset_16(pc,upk.offset) ; */
1342 pc
+= (upk
.offset
<< 1) + 2;
1347 case 29: /* RR Formats JR, JALR, JALR-RA */
1349 struct upk_mips16 upk
;
1350 /* upk.fmt = rrtype; */
1355 upk
.regx
= (insn
>> 8) & 0x07;
1356 upk
.regy
= (insn
>> 5) & 0x07;
1364 break; /* Function return instruction */
1370 break; /* BOGUS Guess */
1372 pc
= get_frame_register_signed (frame
, reg
);
1379 /* This is an instruction extension. Fetch the real instruction
1380 (which follows the extension) and decode things based on
1384 pc
= extended_mips16_next_pc (frame
, pc
, insn
, fetch_mips_16 (pc
));
1397 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1399 unsigned int insn
= fetch_mips_16 (pc
);
1400 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1403 /* The mips_next_pc function supports single_step when the remote
1404 target monitor or stub is not developed enough to do a single_step.
1405 It works by decoding the current instruction and predicting where a
1406 branch will go. This isnt hard because all the data is available.
1407 The MIPS32 and MIPS16 variants are quite different. */
1409 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1411 if (is_mips16_addr (pc
))
1412 return mips16_next_pc (frame
, pc
);
1414 return mips32_next_pc (frame
, pc
);
1417 struct mips_frame_cache
1420 struct trad_frame_saved_reg
*saved_regs
;
1423 /* Set a register's saved stack address in temp_saved_regs. If an
1424 address has already been set for this register, do nothing; this
1425 way we will only recognize the first save of a given register in a
1428 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1429 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1430 Strictly speaking, only the second range is used as it is only second
1431 range (the ABI instead of ISA registers) that comes into play when finding
1432 saved registers in a frame. */
1435 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1436 int regnum
, CORE_ADDR offset
)
1438 if (this_cache
!= NULL
1439 && this_cache
->saved_regs
[regnum
].addr
== -1)
1441 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1443 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1449 /* Fetch the immediate value from a MIPS16 instruction.
1450 If the previous instruction was an EXTEND, use it to extend
1451 the upper bits of the immediate value. This is a helper function
1452 for mips16_scan_prologue. */
1455 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1456 unsigned short inst
, /* current instruction */
1457 int nbits
, /* number of bits in imm field */
1458 int scale
, /* scale factor to be applied to imm */
1459 int is_signed
) /* is the imm field signed? */
1463 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1465 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1466 if (offset
& 0x8000) /* check for negative extend */
1467 offset
= 0 - (0x10000 - (offset
& 0xffff));
1468 return offset
| (inst
& 0x1f);
1472 int max_imm
= 1 << nbits
;
1473 int mask
= max_imm
- 1;
1474 int sign_bit
= max_imm
>> 1;
1476 offset
= inst
& mask
;
1477 if (is_signed
&& (offset
& sign_bit
))
1478 offset
= 0 - (max_imm
- offset
);
1479 return offset
* scale
;
1484 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1485 the associated FRAME_CACHE if not null.
1486 Return the address of the first instruction past the prologue. */
1489 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1490 struct frame_info
*this_frame
,
1491 struct mips_frame_cache
*this_cache
)
1494 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1496 long frame_offset
= 0; /* Size of stack frame. */
1497 long frame_adjust
= 0; /* Offset of FP from SP. */
1498 int frame_reg
= MIPS_SP_REGNUM
;
1499 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1500 unsigned inst
= 0; /* current instruction */
1501 unsigned entry_inst
= 0; /* the entry instruction */
1502 unsigned save_inst
= 0; /* the save instruction */
1505 int extend_bytes
= 0;
1506 int prev_extend_bytes
;
1507 CORE_ADDR end_prologue_addr
= 0;
1508 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1510 /* Can be called when there's no process, and hence when there's no
1512 if (this_frame
!= NULL
)
1513 sp
= get_frame_register_signed (this_frame
,
1514 gdbarch_num_regs (gdbarch
)
1519 if (limit_pc
> start_pc
+ 200)
1520 limit_pc
= start_pc
+ 200;
1522 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1524 /* Save the previous instruction. If it's an EXTEND, we'll extract
1525 the immediate offset extension from it in mips16_get_imm. */
1528 /* Fetch and decode the instruction. */
1529 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1531 /* Normally we ignore extend instructions. However, if it is
1532 not followed by a valid prologue instruction, then this
1533 instruction is not part of the prologue either. We must
1534 remember in this case to adjust the end_prologue_addr back
1536 if ((inst
& 0xf800) == 0xf000) /* extend */
1538 extend_bytes
= MIPS_INSN16_SIZE
;
1542 prev_extend_bytes
= extend_bytes
;
1545 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1546 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1548 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1549 if (offset
< 0) /* negative stack adjustment? */
1550 frame_offset
-= offset
;
1552 /* Exit loop if a positive stack adjustment is found, which
1553 usually means that the stack cleanup code in the function
1554 epilogue is reached. */
1557 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1559 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1560 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1561 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1563 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1565 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1566 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1567 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1569 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1571 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1572 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1574 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1576 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1577 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1579 else if (inst
== 0x673d) /* move $s1, $sp */
1584 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1586 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1587 frame_addr
= sp
+ offset
;
1589 frame_adjust
= offset
;
1591 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1593 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1594 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1595 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1597 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1599 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1600 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1601 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1603 else if ((inst
& 0xf81f) == 0xe809
1604 && (inst
& 0x700) != 0x700) /* entry */
1605 entry_inst
= inst
; /* save for later processing */
1606 else if ((inst
& 0xff80) == 0x6480) /* save */
1608 save_inst
= inst
; /* save for later processing */
1609 if (prev_extend_bytes
) /* extend */
1610 save_inst
|= prev_inst
<< 16;
1612 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1613 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1614 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1616 /* This instruction is part of the prologue, but we don't
1617 need to do anything special to handle it. */
1621 /* This instruction is not an instruction typically found
1622 in a prologue, so we must have reached the end of the
1624 if (end_prologue_addr
== 0)
1625 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1629 /* The entry instruction is typically the first instruction in a function,
1630 and it stores registers at offsets relative to the value of the old SP
1631 (before the prologue). But the value of the sp parameter to this
1632 function is the new SP (after the prologue has been executed). So we
1633 can't calculate those offsets until we've seen the entire prologue,
1634 and can calculate what the old SP must have been. */
1635 if (entry_inst
!= 0)
1637 int areg_count
= (entry_inst
>> 8) & 7;
1638 int sreg_count
= (entry_inst
>> 6) & 3;
1640 /* The entry instruction always subtracts 32 from the SP. */
1643 /* Now we can calculate what the SP must have been at the
1644 start of the function prologue. */
1647 /* Check if a0-a3 were saved in the caller's argument save area. */
1648 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1650 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1651 offset
+= mips_abi_regsize (gdbarch
);
1654 /* Check if the ra register was pushed on the stack. */
1656 if (entry_inst
& 0x20)
1658 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1659 offset
-= mips_abi_regsize (gdbarch
);
1662 /* Check if the s0 and s1 registers were pushed on the stack. */
1663 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1665 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1666 offset
-= mips_abi_regsize (gdbarch
);
1670 /* The SAVE instruction is similar to ENTRY, except that defined by the
1671 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1672 size of the frame is specified as an immediate field of instruction
1673 and an extended variation exists which lets additional registers and
1674 frame space to be specified. The instruction always treats registers
1675 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1676 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1678 static int args_table
[16] = {
1679 0, 0, 0, 0, 1, 1, 1, 1,
1680 2, 2, 2, 0, 3, 3, 4, -1,
1682 static int astatic_table
[16] = {
1683 0, 1, 2, 3, 0, 1, 2, 3,
1684 0, 1, 2, 4, 0, 1, 0, -1,
1686 int aregs
= (save_inst
>> 16) & 0xf;
1687 int xsregs
= (save_inst
>> 24) & 0x7;
1688 int args
= args_table
[aregs
];
1689 int astatic
= astatic_table
[aregs
];
1694 warning (_("Invalid number of argument registers encoded in SAVE."));
1699 warning (_("Invalid number of static registers encoded in SAVE."));
1703 /* For standard SAVE the frame size of 0 means 128. */
1704 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1705 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1708 frame_offset
+= frame_size
;
1710 /* Now we can calculate what the SP must have been at the
1711 start of the function prologue. */
1714 /* Check if A0-A3 were saved in the caller's argument save area. */
1715 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1717 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1718 offset
+= mips_abi_regsize (gdbarch
);
1723 /* Check if the RA register was pushed on the stack. */
1724 if (save_inst
& 0x40)
1726 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1727 offset
-= mips_abi_regsize (gdbarch
);
1730 /* Check if the S8 register was pushed on the stack. */
1733 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1734 offset
-= mips_abi_regsize (gdbarch
);
1737 /* Check if S2-S7 were pushed on the stack. */
1738 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1740 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1741 offset
-= mips_abi_regsize (gdbarch
);
1744 /* Check if the S1 register was pushed on the stack. */
1745 if (save_inst
& 0x10)
1747 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1748 offset
-= mips_abi_regsize (gdbarch
);
1750 /* Check if the S0 register was pushed on the stack. */
1751 if (save_inst
& 0x20)
1753 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1754 offset
-= mips_abi_regsize (gdbarch
);
1757 /* Check if A0-A3 were pushed on the stack. */
1758 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1760 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1761 offset
-= mips_abi_regsize (gdbarch
);
1765 if (this_cache
!= NULL
)
1768 (get_frame_register_signed (this_frame
,
1769 gdbarch_num_regs (gdbarch
) + frame_reg
)
1770 + frame_offset
- frame_adjust
);
1771 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1772 be able to get rid of the assignment below, evetually. But it's
1773 still needed for now. */
1774 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1775 + mips_regnum (gdbarch
)->pc
]
1776 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1779 /* If we didn't reach the end of the prologue when scanning the function
1780 instructions, then set end_prologue_addr to the address of the
1781 instruction immediately after the last one we scanned. */
1782 if (end_prologue_addr
== 0)
1783 end_prologue_addr
= cur_pc
;
1785 return end_prologue_addr
;
1788 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1789 Procedures that use the 32-bit instruction set are handled by the
1790 mips_insn32 unwinder. */
1792 static struct mips_frame_cache
*
1793 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1795 struct mips_frame_cache
*cache
;
1797 if ((*this_cache
) != NULL
)
1798 return (*this_cache
);
1799 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1800 (*this_cache
) = cache
;
1801 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1803 /* Analyze the function prologue. */
1805 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1806 CORE_ADDR start_addr
;
1808 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1809 if (start_addr
== 0)
1810 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
1811 /* We can't analyze the prologue if we couldn't find the begining
1813 if (start_addr
== 0)
1816 mips16_scan_prologue (start_addr
, pc
, this_frame
, *this_cache
);
1819 /* gdbarch_sp_regnum contains the value and not the address. */
1820 trad_frame_set_value (cache
->saved_regs
,
1821 gdbarch_num_regs (get_frame_arch (this_frame
))
1825 return (*this_cache
);
1829 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1830 struct frame_id
*this_id
)
1832 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1834 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
1837 static struct value
*
1838 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
1839 void **this_cache
, int regnum
)
1841 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1843 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1847 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
1848 struct frame_info
*this_frame
, void **this_cache
)
1850 CORE_ADDR pc
= get_frame_pc (this_frame
);
1851 if (mips_pc_is_mips16 (pc
))
1856 static const struct frame_unwind mips_insn16_frame_unwind
=
1859 mips_insn16_frame_this_id
,
1860 mips_insn16_frame_prev_register
,
1862 mips_insn16_frame_sniffer
1866 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
1869 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1874 static const struct frame_base mips_insn16_frame_base
=
1876 &mips_insn16_frame_unwind
,
1877 mips_insn16_frame_base_address
,
1878 mips_insn16_frame_base_address
,
1879 mips_insn16_frame_base_address
1882 static const struct frame_base
*
1883 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
1885 CORE_ADDR pc
= get_frame_pc (this_frame
);
1886 if (mips_pc_is_mips16 (pc
))
1887 return &mips_insn16_frame_base
;
1892 /* Mark all the registers as unset in the saved_regs array
1893 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1896 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
1898 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1902 const int num_regs
= gdbarch_num_regs (gdbarch
);
1905 for (i
= 0; i
< num_regs
; i
++)
1907 this_cache
->saved_regs
[i
].addr
= -1;
1912 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1913 the associated FRAME_CACHE if not null.
1914 Return the address of the first instruction past the prologue. */
1917 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1918 struct frame_info
*this_frame
,
1919 struct mips_frame_cache
*this_cache
)
1922 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1925 int frame_reg
= MIPS_SP_REGNUM
;
1927 CORE_ADDR end_prologue_addr
= 0;
1928 int seen_sp_adjust
= 0;
1929 int load_immediate_bytes
= 0;
1930 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1931 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
1933 /* Can be called when there's no process, and hence when there's no
1935 if (this_frame
!= NULL
)
1936 sp
= get_frame_register_signed (this_frame
,
1937 gdbarch_num_regs (gdbarch
)
1942 if (limit_pc
> start_pc
+ 200)
1943 limit_pc
= start_pc
+ 200;
1948 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1950 unsigned long inst
, high_word
, low_word
;
1953 /* Fetch the instruction. */
1954 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1956 /* Save some code by pre-extracting some useful fields. */
1957 high_word
= (inst
>> 16) & 0xffff;
1958 low_word
= inst
& 0xffff;
1959 reg
= high_word
& 0x1f;
1961 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1962 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1963 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1965 if (low_word
& 0x8000) /* negative stack adjustment? */
1966 frame_offset
+= 0x10000 - low_word
;
1968 /* Exit loop if a positive stack adjustment is found, which
1969 usually means that the stack cleanup code in the function
1970 epilogue is reached. */
1974 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1975 && !regsize_is_64_bits
)
1977 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
1979 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1980 && regsize_is_64_bits
)
1982 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1983 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
1985 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1987 /* Old gcc frame, r30 is virtual frame pointer. */
1988 if ((long) low_word
!= frame_offset
)
1989 frame_addr
= sp
+ low_word
;
1990 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1992 unsigned alloca_adjust
;
1995 frame_addr
= get_frame_register_signed
1996 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
1998 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1999 if (alloca_adjust
> 0)
2001 /* FP > SP + frame_size. This may be because of
2002 an alloca or somethings similar. Fix sp to
2003 "pre-alloca" value, and try again. */
2004 sp
+= alloca_adjust
;
2005 /* Need to reset the status of all registers. Otherwise,
2006 we will hit a guard that prevents the new address
2007 for each register to be recomputed during the second
2009 reset_saved_regs (gdbarch
, this_cache
);
2014 /* move $30,$sp. With different versions of gas this will be either
2015 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2016 Accept any one of these. */
2017 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2019 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2020 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2022 unsigned alloca_adjust
;
2025 frame_addr
= get_frame_register_signed
2026 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2028 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2029 if (alloca_adjust
> 0)
2031 /* FP > SP + frame_size. This may be because of
2032 an alloca or somethings similar. Fix sp to
2033 "pre-alloca" value, and try again. */
2035 /* Need to reset the status of all registers. Otherwise,
2036 we will hit a guard that prevents the new address
2037 for each register to be recomputed during the second
2039 reset_saved_regs (gdbarch
, this_cache
);
2044 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2045 && !regsize_is_64_bits
)
2047 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2049 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2050 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2051 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2052 || high_word
== 0x3c1c /* lui $gp,n */
2053 || high_word
== 0x279c /* addiu $gp,$gp,n */
2054 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2055 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2058 /* These instructions are part of the prologue, but we don't
2059 need to do anything special to handle them. */
2061 /* The instructions below load $at or $t0 with an immediate
2062 value in preparation for a stack adjustment via
2063 subu $sp,$sp,[$at,$t0]. These instructions could also
2064 initialize a local variable, so we accept them only before
2065 a stack adjustment instruction was seen. */
2066 else if (!seen_sp_adjust
2067 && (high_word
== 0x3c01 /* lui $at,n */
2068 || high_word
== 0x3c08 /* lui $t0,n */
2069 || high_word
== 0x3421 /* ori $at,$at,n */
2070 || high_word
== 0x3508 /* ori $t0,$t0,n */
2071 || high_word
== 0x3401 /* ori $at,$zero,n */
2072 || high_word
== 0x3408 /* ori $t0,$zero,n */
2075 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2079 /* This instruction is not an instruction typically found
2080 in a prologue, so we must have reached the end of the
2082 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2083 loop now? Why would we need to continue scanning the function
2085 if (end_prologue_addr
== 0)
2086 end_prologue_addr
= cur_pc
;
2090 if (this_cache
!= NULL
)
2093 (get_frame_register_signed (this_frame
,
2094 gdbarch_num_regs (gdbarch
) + frame_reg
)
2096 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2097 this assignment below, eventually. But it's still needed
2099 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2100 + mips_regnum (gdbarch
)->pc
]
2101 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2105 /* If we didn't reach the end of the prologue when scanning the function
2106 instructions, then set end_prologue_addr to the address of the
2107 instruction immediately after the last one we scanned. */
2108 /* brobecker/2004-10-10: I don't think this would ever happen, but
2109 we may as well be careful and do our best if we have a null
2110 end_prologue_addr. */
2111 if (end_prologue_addr
== 0)
2112 end_prologue_addr
= cur_pc
;
2114 /* In a frameless function, we might have incorrectly
2115 skipped some load immediate instructions. Undo the skipping
2116 if the load immediate was not followed by a stack adjustment. */
2117 if (load_immediate_bytes
&& !seen_sp_adjust
)
2118 end_prologue_addr
-= load_immediate_bytes
;
2120 return end_prologue_addr
;
2123 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2124 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2125 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2128 static struct mips_frame_cache
*
2129 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2131 struct mips_frame_cache
*cache
;
2133 if ((*this_cache
) != NULL
)
2134 return (*this_cache
);
2136 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2137 (*this_cache
) = cache
;
2138 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2140 /* Analyze the function prologue. */
2142 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2143 CORE_ADDR start_addr
;
2145 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2146 if (start_addr
== 0)
2147 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
2148 /* We can't analyze the prologue if we couldn't find the begining
2150 if (start_addr
== 0)
2153 mips32_scan_prologue (start_addr
, pc
, this_frame
, *this_cache
);
2156 /* gdbarch_sp_regnum contains the value and not the address. */
2157 trad_frame_set_value (cache
->saved_regs
,
2158 gdbarch_num_regs (get_frame_arch (this_frame
))
2162 return (*this_cache
);
2166 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2167 struct frame_id
*this_id
)
2169 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2171 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2174 static struct value
*
2175 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2176 void **this_cache
, int regnum
)
2178 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2180 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2184 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2185 struct frame_info
*this_frame
, void **this_cache
)
2187 CORE_ADDR pc
= get_frame_pc (this_frame
);
2188 if (! mips_pc_is_mips16 (pc
))
2193 static const struct frame_unwind mips_insn32_frame_unwind
=
2196 mips_insn32_frame_this_id
,
2197 mips_insn32_frame_prev_register
,
2199 mips_insn32_frame_sniffer
2203 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2206 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2211 static const struct frame_base mips_insn32_frame_base
=
2213 &mips_insn32_frame_unwind
,
2214 mips_insn32_frame_base_address
,
2215 mips_insn32_frame_base_address
,
2216 mips_insn32_frame_base_address
2219 static const struct frame_base
*
2220 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2222 CORE_ADDR pc
= get_frame_pc (this_frame
);
2223 if (! mips_pc_is_mips16 (pc
))
2224 return &mips_insn32_frame_base
;
2229 static struct trad_frame_cache
*
2230 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2233 CORE_ADDR start_addr
;
2234 CORE_ADDR stack_addr
;
2235 struct trad_frame_cache
*this_trad_cache
;
2236 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2237 int num_regs
= gdbarch_num_regs (gdbarch
);
2239 if ((*this_cache
) != NULL
)
2240 return (*this_cache
);
2241 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2242 (*this_cache
) = this_trad_cache
;
2244 /* The return address is in the link register. */
2245 trad_frame_set_reg_realreg (this_trad_cache
,
2246 gdbarch_pc_regnum (gdbarch
),
2247 num_regs
+ MIPS_RA_REGNUM
);
2249 /* Frame ID, since it's a frameless / stackless function, no stack
2250 space is allocated and SP on entry is the current SP. */
2251 pc
= get_frame_pc (this_frame
);
2252 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2253 stack_addr
= get_frame_register_signed (this_frame
,
2254 num_regs
+ MIPS_SP_REGNUM
);
2255 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2257 /* Assume that the frame's base is the same as the
2259 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2261 return this_trad_cache
;
2265 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2266 struct frame_id
*this_id
)
2268 struct trad_frame_cache
*this_trad_cache
2269 = mips_stub_frame_cache (this_frame
, this_cache
);
2270 trad_frame_get_id (this_trad_cache
, this_id
);
2273 static struct value
*
2274 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2275 void **this_cache
, int regnum
)
2277 struct trad_frame_cache
*this_trad_cache
2278 = mips_stub_frame_cache (this_frame
, this_cache
);
2279 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2283 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2284 struct frame_info
*this_frame
, void **this_cache
)
2287 struct obj_section
*s
;
2288 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2290 /* Use the stub unwinder for unreadable code. */
2291 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2294 if (in_plt_section (pc
, NULL
))
2297 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2298 s
= find_pc_section (pc
);
2301 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2302 ".MIPS.stubs") == 0)
2308 static const struct frame_unwind mips_stub_frame_unwind
=
2311 mips_stub_frame_this_id
,
2312 mips_stub_frame_prev_register
,
2314 mips_stub_frame_sniffer
2318 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2321 struct trad_frame_cache
*this_trad_cache
2322 = mips_stub_frame_cache (this_frame
, this_cache
);
2323 return trad_frame_get_this_base (this_trad_cache
);
2326 static const struct frame_base mips_stub_frame_base
=
2328 &mips_stub_frame_unwind
,
2329 mips_stub_frame_base_address
,
2330 mips_stub_frame_base_address
,
2331 mips_stub_frame_base_address
2334 static const struct frame_base
*
2335 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2337 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2338 return &mips_stub_frame_base
;
2343 /* mips_addr_bits_remove - remove useless address bits */
2346 mips_addr_bits_remove (CORE_ADDR addr
)
2348 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2349 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2350 /* This hack is a work-around for existing boards using PMON, the
2351 simulator, and any other 64-bit targets that doesn't have true
2352 64-bit addressing. On these targets, the upper 32 bits of
2353 addresses are ignored by the hardware. Thus, the PC or SP are
2354 likely to have been sign extended to all 1s by instruction
2355 sequences that load 32-bit addresses. For example, a typical
2356 piece of code that loads an address is this:
2358 lui $r2, <upper 16 bits>
2359 ori $r2, <lower 16 bits>
2361 But the lui sign-extends the value such that the upper 32 bits
2362 may be all 1s. The workaround is simply to mask off these
2363 bits. In the future, gcc may be changed to support true 64-bit
2364 addressing, and this masking will have to be disabled. */
2365 return addr
&= 0xffffffffUL
;
2370 /* Instructions used during single-stepping of atomic sequences. */
2371 #define LL_OPCODE 0x30
2372 #define LLD_OPCODE 0x34
2373 #define SC_OPCODE 0x38
2374 #define SCD_OPCODE 0x3c
2376 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2377 instruction and ending with a SC/SCD instruction. If such a sequence
2378 is found, attempt to step through it. A breakpoint is placed at the end of
2382 deal_with_atomic_sequence (CORE_ADDR pc
)
2384 CORE_ADDR breaks
[2] = {-1, -1};
2386 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2390 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2391 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2396 insn
= mips_fetch_instruction (loc
);
2397 /* Assume all atomic sequences start with a ll/lld instruction. */
2398 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2401 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2403 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2406 loc
+= MIPS_INSN32_SIZE
;
2407 insn
= mips_fetch_instruction (loc
);
2409 /* Assume that there is at most one branch in the atomic
2410 sequence. If a branch is found, put a breakpoint in its
2411 destination address. */
2412 switch (itype_op (insn
))
2414 case 0: /* SPECIAL */
2415 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2416 return 0; /* fallback to the standard single-step code. */
2418 case 1: /* REGIMM */
2419 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2423 return 0; /* fallback to the standard single-step code. */
2430 case 22: /* BLEZL */
2431 case 23: /* BGTTL */
2437 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2442 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2443 if (last_breakpoint
>= 1)
2444 return 0; /* More than one branch found, fallback to the
2445 standard single-step code. */
2446 breaks
[1] = branch_bp
;
2450 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2454 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2455 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2458 loc
+= MIPS_INSN32_SIZE
;
2460 /* Insert a breakpoint right after the end of the atomic sequence. */
2463 /* Check for duplicated breakpoints. Check also for a breakpoint
2464 placed (branch instruction's destination) in the atomic sequence */
2465 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2466 last_breakpoint
= 0;
2468 /* Effectively inserts the breakpoints. */
2469 for (index
= 0; index
<= last_breakpoint
; index
++)
2470 insert_single_step_breakpoint (breaks
[index
]);
2475 /* mips_software_single_step() is called just before we want to resume
2476 the inferior, if we want to single-step it but there is no hardware
2477 or kernel single-step support (MIPS on GNU/Linux for example). We find
2478 the target of the coming instruction and breakpoint it. */
2481 mips_software_single_step (struct frame_info
*frame
)
2483 CORE_ADDR pc
, next_pc
;
2485 pc
= get_frame_pc (frame
);
2486 if (deal_with_atomic_sequence (pc
))
2489 next_pc
= mips_next_pc (frame
, pc
);
2491 insert_single_step_breakpoint (next_pc
);
2495 /* Test whether the PC points to the return instruction at the
2496 end of a function. */
2499 mips_about_to_return (CORE_ADDR pc
)
2501 if (mips_pc_is_mips16 (pc
))
2502 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2503 generates a "jr $ra"; other times it generates code to load
2504 the return address from the stack to an accessible register (such
2505 as $a3), then a "jr" using that register. This second case
2506 is almost impossible to distinguish from an indirect jump
2507 used for switch statements, so we don't even try. */
2508 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2510 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2514 /* This fencepost looks highly suspicious to me. Removing it also
2515 seems suspicious as it could affect remote debugging across serial
2519 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2526 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2528 fence
= start_pc
- heuristic_fence_post
;
2532 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2533 fence
= VM_MIN_ADDRESS
;
2535 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2537 /* search back for previous return */
2538 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2539 if (start_pc
< fence
)
2541 /* It's not clear to me why we reach this point when
2542 stop_soon, but with this test, at least we
2543 don't print out warnings for every child forked (eg, on
2544 decstation). 22apr93 rich@cygnus.com. */
2545 if (stop_soon
== NO_STOP_QUIETLY
)
2547 static int blurb_printed
= 0;
2549 warning (_("GDB can't find the start of the function at 0x%s."),
2554 /* This actually happens frequently in embedded
2555 development, when you first connect to a board
2556 and your stack pointer and pc are nowhere in
2557 particular. This message needs to give people
2558 in that situation enough information to
2559 determine that it's no big deal. */
2560 printf_filtered ("\n\
2561 GDB is unable to find the start of the function at 0x%s\n\
2562 and thus can't determine the size of that function's stack frame.\n\
2563 This means that GDB may be unable to access that stack frame, or\n\
2564 the frames below it.\n\
2565 This problem is most likely caused by an invalid program counter or\n\
2567 However, if you think GDB should simply search farther back\n\
2568 from 0x%s for code which looks like the beginning of a\n\
2569 function, you can increase the range of the search using the `set\n\
2570 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2577 else if (mips_pc_is_mips16 (start_pc
))
2579 unsigned short inst
;
2581 /* On MIPS16, any one of the following is likely to be the
2582 start of a function:
2588 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2589 inst
= mips_fetch_instruction (start_pc
);
2590 if ((inst
& 0xff80) == 0x6480) /* save */
2592 if (start_pc
- instlen
>= fence
)
2594 inst
= mips_fetch_instruction (start_pc
- instlen
);
2595 if ((inst
& 0xf800) == 0xf000) /* extend */
2596 start_pc
-= instlen
;
2600 else if (((inst
& 0xf81f) == 0xe809
2601 && (inst
& 0x700) != 0x700) /* entry */
2602 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2603 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2604 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2606 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2607 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2612 else if (mips_about_to_return (start_pc
))
2614 /* Skip return and its delay slot. */
2615 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2622 struct mips_objfile_private
2628 /* According to the current ABI, should the type be passed in a
2629 floating-point register (assuming that there is space)? When there
2630 is no FPU, FP are not even considered as possible candidates for
2631 FP registers and, consequently this returns false - forces FP
2632 arguments into integer registers. */
2635 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2636 struct type
*arg_type
)
2638 return ((typecode
== TYPE_CODE_FLT
2639 || (MIPS_EABI (gdbarch
)
2640 && (typecode
== TYPE_CODE_STRUCT
2641 || typecode
== TYPE_CODE_UNION
)
2642 && TYPE_NFIELDS (arg_type
) == 1
2643 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2645 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2648 /* On o32, argument passing in GPRs depends on the alignment of the type being
2649 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2652 mips_type_needs_double_align (struct type
*type
)
2654 enum type_code typecode
= TYPE_CODE (type
);
2656 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2658 else if (typecode
== TYPE_CODE_STRUCT
)
2660 if (TYPE_NFIELDS (type
) < 1)
2662 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2664 else if (typecode
== TYPE_CODE_UNION
)
2668 n
= TYPE_NFIELDS (type
);
2669 for (i
= 0; i
< n
; i
++)
2670 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2677 /* Adjust the address downward (direction of stack growth) so that it
2678 is correctly aligned for a new stack frame. */
2680 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2682 return align_down (addr
, 16);
2686 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2687 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2688 int nargs
, struct value
**args
, CORE_ADDR sp
,
2689 int struct_return
, CORE_ADDR struct_addr
)
2695 int stack_offset
= 0;
2696 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2697 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2698 int regsize
= mips_abi_regsize (gdbarch
);
2700 /* For shared libraries, "t9" needs to point at the function
2702 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2704 /* Set the return address register to point to the entry point of
2705 the program, where a breakpoint lies in wait. */
2706 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2708 /* First ensure that the stack and structure return address (if any)
2709 are properly aligned. The stack has to be at least 64-bit
2710 aligned even on 32-bit machines, because doubles must be 64-bit
2711 aligned. For n32 and n64, stack frames need to be 128-bit
2712 aligned, so we round to this widest known alignment. */
2714 sp
= align_down (sp
, 16);
2715 struct_addr
= align_down (struct_addr
, 16);
2717 /* Now make space on the stack for the args. We allocate more
2718 than necessary for EABI, because the first few arguments are
2719 passed in registers, but that's OK. */
2720 for (argnum
= 0; argnum
< nargs
; argnum
++)
2721 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2722 sp
-= align_up (len
, 16);
2725 fprintf_unfiltered (gdb_stdlog
,
2726 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2727 paddr_nz (sp
), (long) align_up (len
, 16));
2729 /* Initialize the integer and float register pointers. */
2730 argreg
= MIPS_A0_REGNUM
;
2731 float_argreg
= mips_fpa0_regnum (gdbarch
);
2733 /* The struct_return pointer occupies the first parameter-passing reg. */
2737 fprintf_unfiltered (gdb_stdlog
,
2738 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2739 argreg
, paddr_nz (struct_addr
));
2740 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2743 /* Now load as many as possible of the first arguments into
2744 registers, and push the rest onto the stack. Loop thru args
2745 from first to last. */
2746 for (argnum
= 0; argnum
< nargs
; argnum
++)
2748 const gdb_byte
*val
;
2749 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2750 struct value
*arg
= args
[argnum
];
2751 struct type
*arg_type
= check_typedef (value_type (arg
));
2752 int len
= TYPE_LENGTH (arg_type
);
2753 enum type_code typecode
= TYPE_CODE (arg_type
);
2756 fprintf_unfiltered (gdb_stdlog
,
2757 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2758 argnum
+ 1, len
, (int) typecode
);
2760 /* The EABI passes structures that do not fit in a register by
2763 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2765 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2766 typecode
= TYPE_CODE_PTR
;
2770 fprintf_unfiltered (gdb_stdlog
, " push");
2773 val
= value_contents (arg
);
2775 /* 32-bit ABIs always start floating point arguments in an
2776 even-numbered floating point register. Round the FP register
2777 up before the check to see if there are any FP registers
2778 left. Non MIPS_EABI targets also pass the FP in the integer
2779 registers so also round up normal registers. */
2780 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2782 if ((float_argreg
& 1))
2786 /* Floating point arguments passed in registers have to be
2787 treated specially. On 32-bit architectures, doubles
2788 are passed in register pairs; the even register gets
2789 the low word, and the odd register gets the high word.
2790 On non-EABI processors, the first two floating point arguments are
2791 also copied to general registers, because MIPS16 functions
2792 don't use float registers for arguments. This duplication of
2793 arguments in general registers can't hurt non-MIPS16 functions
2794 because those registers are normally skipped. */
2795 /* MIPS_EABI squeezes a struct that contains a single floating
2796 point value into an FP register instead of pushing it onto the
2798 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
2799 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
2801 /* EABI32 will pass doubles in consecutive registers, even on
2802 64-bit cores. At one time, we used to check the size of
2803 `float_argreg' to determine whether or not to pass doubles
2804 in consecutive registers, but this is not sufficient for
2805 making the ABI determination. */
2806 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2808 int low_offset
= gdbarch_byte_order (gdbarch
)
2809 == BFD_ENDIAN_BIG
? 4 : 0;
2810 unsigned long regval
;
2812 /* Write the low word of the double to the even register(s). */
2813 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2815 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2816 float_argreg
, phex (regval
, 4));
2817 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2819 /* Write the high word of the double to the odd register(s). */
2820 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2822 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2823 float_argreg
, phex (regval
, 4));
2824 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2828 /* This is a floating point value that fits entirely
2829 in a single register. */
2830 /* On 32 bit ABI's the float_argreg is further adjusted
2831 above to ensure that it is even register aligned. */
2832 LONGEST regval
= extract_unsigned_integer (val
, len
);
2834 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2835 float_argreg
, phex (regval
, len
));
2836 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2841 /* Copy the argument to general registers or the stack in
2842 register-sized pieces. Large arguments are split between
2843 registers and stack. */
2844 /* Note: structs whose size is not a multiple of regsize
2845 are treated specially: Irix cc passes
2846 them in registers where gcc sometimes puts them on the
2847 stack. For maximum compatibility, we will put them in
2849 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2851 /* Note: Floating-point values that didn't fit into an FP
2852 register are only written to memory. */
2855 /* Remember if the argument was written to the stack. */
2856 int stack_used_p
= 0;
2857 int partial_len
= (len
< regsize
? len
: regsize
);
2860 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2863 /* Write this portion of the argument to the stack. */
2864 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
2866 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2868 /* Should shorter than int integer values be
2869 promoted to int before being stored? */
2870 int longword_offset
= 0;
2873 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2876 && (typecode
== TYPE_CODE_INT
2877 || typecode
== TYPE_CODE_PTR
2878 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2879 longword_offset
= regsize
- len
;
2880 else if ((typecode
== TYPE_CODE_STRUCT
2881 || typecode
== TYPE_CODE_UNION
)
2882 && TYPE_LENGTH (arg_type
) < regsize
)
2883 longword_offset
= regsize
- len
;
2888 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2889 paddr_nz (stack_offset
));
2890 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2891 paddr_nz (longword_offset
));
2894 addr
= sp
+ stack_offset
+ longword_offset
;
2899 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2901 for (i
= 0; i
< partial_len
; i
++)
2903 fprintf_unfiltered (gdb_stdlog
, "%02x",
2907 write_memory (addr
, val
, partial_len
);
2910 /* Note!!! This is NOT an else clause. Odd sized
2911 structs may go thru BOTH paths. Floating point
2912 arguments will not. */
2913 /* Write this portion of the argument to a general
2914 purpose register. */
2915 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
2916 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2919 extract_unsigned_integer (val
, partial_len
);
2922 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2924 phex (regval
, regsize
));
2925 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2932 /* Compute the the offset into the stack at which we
2933 will copy the next parameter.
2935 In the new EABI (and the NABI32), the stack_offset
2936 only needs to be adjusted when it has been used. */
2939 stack_offset
+= align_up (partial_len
, regsize
);
2943 fprintf_unfiltered (gdb_stdlog
, "\n");
2946 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2948 /* Return adjusted stack pointer. */
2952 /* Determine the return value convention being used. */
2954 static enum return_value_convention
2955 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2956 struct type
*type
, struct regcache
*regcache
,
2957 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2959 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2960 int fp_return_type
= 0;
2961 int offset
, regnum
, xfer
;
2963 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2964 return RETURN_VALUE_STRUCT_CONVENTION
;
2966 /* Floating point type? */
2967 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2969 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2971 /* Structs with a single field of float type
2972 are returned in a floating point register. */
2973 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
2974 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2975 && TYPE_NFIELDS (type
) == 1)
2977 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
2979 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
2986 /* A floating-point value belongs in the least significant part
2989 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
2990 regnum
= mips_regnum (gdbarch
)->fp0
;
2994 /* An integer value goes in V0/V1. */
2996 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
2997 regnum
= MIPS_V0_REGNUM
;
3000 offset
< TYPE_LENGTH (type
);
3001 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3003 xfer
= mips_abi_regsize (gdbarch
);
3004 if (offset
+ xfer
> TYPE_LENGTH (type
))
3005 xfer
= TYPE_LENGTH (type
) - offset
;
3006 mips_xfer_register (gdbarch
, regcache
,
3007 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3008 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3012 return RETURN_VALUE_REGISTER_CONVENTION
;
3016 /* N32/N64 ABI stuff. */
3018 /* Search for a naturally aligned double at OFFSET inside a struct
3019 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3023 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3028 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3031 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3034 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3037 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3040 struct type
*field_type
;
3042 /* We're only looking at normal fields. */
3043 if (TYPE_FIELD_STATIC (arg_type
, i
)
3044 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3047 /* If we have gone past the offset, there is no double to pass. */
3048 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3052 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3054 /* If this field is entirely before the requested offset, go
3055 on to the next one. */
3056 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3059 /* If this is our special aligned double, we can stop. */
3060 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3061 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3064 /* This field starts at or before the requested offset, and
3065 overlaps it. If it is a structure, recurse inwards. */
3066 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3073 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3074 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3075 int nargs
, struct value
**args
, CORE_ADDR sp
,
3076 int struct_return
, CORE_ADDR struct_addr
)
3082 int stack_offset
= 0;
3083 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3084 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3086 /* For shared libraries, "t9" needs to point at the function
3088 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3090 /* Set the return address register to point to the entry point of
3091 the program, where a breakpoint lies in wait. */
3092 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3094 /* First ensure that the stack and structure return address (if any)
3095 are properly aligned. The stack has to be at least 64-bit
3096 aligned even on 32-bit machines, because doubles must be 64-bit
3097 aligned. For n32 and n64, stack frames need to be 128-bit
3098 aligned, so we round to this widest known alignment. */
3100 sp
= align_down (sp
, 16);
3101 struct_addr
= align_down (struct_addr
, 16);
3103 /* Now make space on the stack for the args. */
3104 for (argnum
= 0; argnum
< nargs
; argnum
++)
3105 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3106 sp
-= align_up (len
, 16);
3109 fprintf_unfiltered (gdb_stdlog
,
3110 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3111 paddr_nz (sp
), (long) align_up (len
, 16));
3113 /* Initialize the integer and float register pointers. */
3114 argreg
= MIPS_A0_REGNUM
;
3115 float_argreg
= mips_fpa0_regnum (gdbarch
);
3117 /* The struct_return pointer occupies the first parameter-passing reg. */
3121 fprintf_unfiltered (gdb_stdlog
,
3122 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3123 argreg
, paddr_nz (struct_addr
));
3124 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3127 /* Now load as many as possible of the first arguments into
3128 registers, and push the rest onto the stack. Loop thru args
3129 from first to last. */
3130 for (argnum
= 0; argnum
< nargs
; argnum
++)
3132 const gdb_byte
*val
;
3133 struct value
*arg
= args
[argnum
];
3134 struct type
*arg_type
= check_typedef (value_type (arg
));
3135 int len
= TYPE_LENGTH (arg_type
);
3136 enum type_code typecode
= TYPE_CODE (arg_type
);
3139 fprintf_unfiltered (gdb_stdlog
,
3140 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3141 argnum
+ 1, len
, (int) typecode
);
3143 val
= value_contents (arg
);
3145 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3146 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3148 /* This is a floating point value that fits entirely
3149 in a single register. */
3150 LONGEST regval
= extract_unsigned_integer (val
, len
);
3152 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3153 float_argreg
, phex (regval
, len
));
3154 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3157 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3158 argreg
, phex (regval
, len
));
3159 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3165 /* Copy the argument to general registers or the stack in
3166 register-sized pieces. Large arguments are split between
3167 registers and stack. */
3168 /* For N32/N64, structs, unions, or other composite types are
3169 treated as a sequence of doublewords, and are passed in integer
3170 or floating point registers as though they were simple scalar
3171 parameters to the extent that they fit, with any excess on the
3172 stack packed according to the normal memory layout of the
3174 The caller does not reserve space for the register arguments;
3175 the callee is responsible for reserving it if required. */
3176 /* Note: Floating-point values that didn't fit into an FP
3177 register are only written to memory. */
3180 /* Remember if the argument was written to the stack. */
3181 int stack_used_p
= 0;
3182 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3185 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3188 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3189 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3191 /* Write this portion of the argument to the stack. */
3192 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3194 /* Should shorter than int integer values be
3195 promoted to int before being stored? */
3196 int longword_offset
= 0;
3199 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3201 if ((typecode
== TYPE_CODE_INT
3202 || typecode
== TYPE_CODE_PTR
3203 || typecode
== TYPE_CODE_FLT
)
3205 longword_offset
= MIPS64_REGSIZE
- len
;
3210 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3211 paddr_nz (stack_offset
));
3212 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3213 paddr_nz (longword_offset
));
3216 addr
= sp
+ stack_offset
+ longword_offset
;
3221 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3223 for (i
= 0; i
< partial_len
; i
++)
3225 fprintf_unfiltered (gdb_stdlog
, "%02x",
3229 write_memory (addr
, val
, partial_len
);
3232 /* Note!!! This is NOT an else clause. Odd sized
3233 structs may go thru BOTH paths. */
3234 /* Write this portion of the argument to a general
3235 purpose register. */
3236 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3240 /* Sign extend pointers, 32-bit integers and signed
3241 16-bit and 8-bit integers; everything else is taken
3244 if ((partial_len
== 4
3245 && (typecode
== TYPE_CODE_PTR
3246 || typecode
== TYPE_CODE_INT
))
3248 && typecode
== TYPE_CODE_INT
3249 && !TYPE_UNSIGNED (arg_type
)))
3250 regval
= extract_signed_integer (val
, partial_len
);
3252 regval
= extract_unsigned_integer (val
, partial_len
);
3254 /* A non-floating-point argument being passed in a
3255 general register. If a struct or union, and if
3256 the remaining length is smaller than the register
3257 size, we have to adjust the register value on
3260 It does not seem to be necessary to do the
3261 same for integral types. */
3263 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3264 && partial_len
< MIPS64_REGSIZE
3265 && (typecode
== TYPE_CODE_STRUCT
3266 || typecode
== TYPE_CODE_UNION
))
3267 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3271 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3273 phex (regval
, MIPS64_REGSIZE
));
3274 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3276 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3277 TYPE_LENGTH (arg_type
) - len
))
3280 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3282 phex (regval
, MIPS64_REGSIZE
));
3283 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3294 /* Compute the the offset into the stack at which we
3295 will copy the next parameter.
3297 In N32 (N64?), the stack_offset only needs to be
3298 adjusted when it has been used. */
3301 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3305 fprintf_unfiltered (gdb_stdlog
, "\n");
3308 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3310 /* Return adjusted stack pointer. */
3314 static enum return_value_convention
3315 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3316 struct type
*type
, struct regcache
*regcache
,
3317 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3319 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3321 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3323 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3324 if needed), as appropriate for the type. Composite results (struct,
3325 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3328 * A struct with only one or two floating point fields is returned in $f0
3329 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3332 * Any other struct or union results of at most 128 bits are returned in
3333 $2 (first 64 bits) and $3 (remainder, if necessary).
3335 * Larger composite results are handled by converting the function to a
3336 procedure with an implicit first parameter, which is a pointer to an area
3337 reserved by the caller to receive the result. [The o32-bit ABI requires
3338 that all composite results be handled by conversion to implicit first
3339 parameters. The MIPS/SGI Fortran implementation has always made a
3340 specific exception to return COMPLEX results in the floating point
3343 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
3344 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3345 return RETURN_VALUE_STRUCT_CONVENTION
;
3346 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3347 && TYPE_LENGTH (type
) == 16
3348 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3350 /* A 128-bit floating-point value fills both $f0 and $f2. The
3351 two registers are used in the same as memory order, so the
3352 eight bytes with the lower memory address are in $f0. */
3354 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3355 mips_xfer_register (gdbarch
, regcache
,
3356 gdbarch_num_regs (gdbarch
)
3357 + mips_regnum (gdbarch
)->fp0
,
3358 8, gdbarch_byte_order (gdbarch
),
3359 readbuf
, writebuf
, 0);
3360 mips_xfer_register (gdbarch
, regcache
,
3361 gdbarch_num_regs (gdbarch
)
3362 + mips_regnum (gdbarch
)->fp0
+ 2,
3363 8, gdbarch_byte_order (gdbarch
),
3364 readbuf
? readbuf
+ 8 : readbuf
,
3365 writebuf
? writebuf
+ 8 : writebuf
, 0);
3366 return RETURN_VALUE_REGISTER_CONVENTION
;
3368 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3369 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3371 /* A single or double floating-point value that fits in FP0. */
3373 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3374 mips_xfer_register (gdbarch
, regcache
,
3375 gdbarch_num_regs (gdbarch
)
3376 + mips_regnum (gdbarch
)->fp0
,
3378 gdbarch_byte_order (gdbarch
),
3379 readbuf
, writebuf
, 0);
3380 return RETURN_VALUE_REGISTER_CONVENTION
;
3382 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3383 && TYPE_NFIELDS (type
) <= 2
3384 && TYPE_NFIELDS (type
) >= 1
3385 && ((TYPE_NFIELDS (type
) == 1
3386 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3388 || (TYPE_NFIELDS (type
) == 2
3389 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3391 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3393 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3395 /* A struct that contains one or two floats. Each value is part
3396 in the least significant part of their floating point
3400 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3401 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3403 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3406 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3408 mips_xfer_register (gdbarch
, regcache
,
3409 gdbarch_num_regs (gdbarch
) + regnum
,
3410 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3411 gdbarch_byte_order (gdbarch
),
3412 readbuf
, writebuf
, offset
);
3414 return RETURN_VALUE_REGISTER_CONVENTION
;
3416 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3417 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3419 /* A structure or union. Extract the left justified value,
3420 regardless of the byte order. I.e. DO NOT USE
3424 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3425 offset
< TYPE_LENGTH (type
);
3426 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3428 int xfer
= register_size (gdbarch
, regnum
);
3429 if (offset
+ xfer
> TYPE_LENGTH (type
))
3430 xfer
= TYPE_LENGTH (type
) - offset
;
3432 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3433 offset
, xfer
, regnum
);
3434 mips_xfer_register (gdbarch
, regcache
,
3435 gdbarch_num_regs (gdbarch
) + regnum
,
3436 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3439 return RETURN_VALUE_REGISTER_CONVENTION
;
3443 /* A scalar extract each part but least-significant-byte
3447 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3448 offset
< TYPE_LENGTH (type
);
3449 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3451 int xfer
= register_size (gdbarch
, regnum
);
3452 if (offset
+ xfer
> TYPE_LENGTH (type
))
3453 xfer
= TYPE_LENGTH (type
) - offset
;
3455 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3456 offset
, xfer
, regnum
);
3457 mips_xfer_register (gdbarch
, regcache
,
3458 gdbarch_num_regs (gdbarch
) + regnum
,
3459 xfer
, gdbarch_byte_order (gdbarch
),
3460 readbuf
, writebuf
, offset
);
3462 return RETURN_VALUE_REGISTER_CONVENTION
;
3466 /* O32 ABI stuff. */
3469 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3470 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3471 int nargs
, struct value
**args
, CORE_ADDR sp
,
3472 int struct_return
, CORE_ADDR struct_addr
)
3478 int stack_offset
= 0;
3479 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3480 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3482 /* For shared libraries, "t9" needs to point at the function
3484 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3486 /* Set the return address register to point to the entry point of
3487 the program, where a breakpoint lies in wait. */
3488 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3490 /* First ensure that the stack and structure return address (if any)
3491 are properly aligned. The stack has to be at least 64-bit
3492 aligned even on 32-bit machines, because doubles must be 64-bit
3493 aligned. For n32 and n64, stack frames need to be 128-bit
3494 aligned, so we round to this widest known alignment. */
3496 sp
= align_down (sp
, 16);
3497 struct_addr
= align_down (struct_addr
, 16);
3499 /* Now make space on the stack for the args. */
3500 for (argnum
= 0; argnum
< nargs
; argnum
++)
3502 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3503 int arglen
= TYPE_LENGTH (arg_type
);
3505 /* Align to double-word if necessary. */
3506 if (mips_type_needs_double_align (arg_type
))
3507 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3508 /* Allocate space on the stack. */
3509 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3511 sp
-= align_up (len
, 16);
3514 fprintf_unfiltered (gdb_stdlog
,
3515 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3516 paddr_nz (sp
), (long) align_up (len
, 16));
3518 /* Initialize the integer and float register pointers. */
3519 argreg
= MIPS_A0_REGNUM
;
3520 float_argreg
= mips_fpa0_regnum (gdbarch
);
3522 /* The struct_return pointer occupies the first parameter-passing reg. */
3526 fprintf_unfiltered (gdb_stdlog
,
3527 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3528 argreg
, paddr_nz (struct_addr
));
3529 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3530 stack_offset
+= MIPS32_REGSIZE
;
3533 /* Now load as many as possible of the first arguments into
3534 registers, and push the rest onto the stack. Loop thru args
3535 from first to last. */
3536 for (argnum
= 0; argnum
< nargs
; argnum
++)
3538 const gdb_byte
*val
;
3539 struct value
*arg
= args
[argnum
];
3540 struct type
*arg_type
= check_typedef (value_type (arg
));
3541 int len
= TYPE_LENGTH (arg_type
);
3542 enum type_code typecode
= TYPE_CODE (arg_type
);
3545 fprintf_unfiltered (gdb_stdlog
,
3546 "mips_o32_push_dummy_call: %d len=%d type=%d",
3547 argnum
+ 1, len
, (int) typecode
);
3549 val
= value_contents (arg
);
3551 /* 32-bit ABIs always start floating point arguments in an
3552 even-numbered floating point register. Round the FP register
3553 up before the check to see if there are any FP registers
3554 left. O32/O64 targets also pass the FP in the integer
3555 registers so also round up normal registers. */
3556 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3558 if ((float_argreg
& 1))
3562 /* Floating point arguments passed in registers have to be
3563 treated specially. On 32-bit architectures, doubles
3564 are passed in register pairs; the even register gets
3565 the low word, and the odd register gets the high word.
3566 On O32/O64, the first two floating point arguments are
3567 also copied to general registers, because MIPS16 functions
3568 don't use float registers for arguments. This duplication of
3569 arguments in general registers can't hurt non-MIPS16 functions
3570 because those registers are normally skipped. */
3572 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3573 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3575 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3577 int low_offset
= gdbarch_byte_order (gdbarch
)
3578 == BFD_ENDIAN_BIG
? 4 : 0;
3579 unsigned long regval
;
3581 /* Write the low word of the double to the even register(s). */
3582 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3584 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3585 float_argreg
, phex (regval
, 4));
3586 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3588 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3589 argreg
, phex (regval
, 4));
3590 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3592 /* Write the high word of the double to the odd register(s). */
3593 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3595 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3596 float_argreg
, phex (regval
, 4));
3597 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3600 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3601 argreg
, phex (regval
, 4));
3602 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3606 /* This is a floating point value that fits entirely
3607 in a single register. */
3608 /* On 32 bit ABI's the float_argreg is further adjusted
3609 above to ensure that it is even register aligned. */
3610 LONGEST regval
= extract_unsigned_integer (val
, len
);
3612 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3613 float_argreg
, phex (regval
, len
));
3614 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3615 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3616 registers for each argument. The below is (my
3617 guess) to ensure that the corresponding integer
3618 register has reserved the same space. */
3620 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3621 argreg
, phex (regval
, len
));
3622 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3625 /* Reserve space for the FP register. */
3626 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3630 /* Copy the argument to general registers or the stack in
3631 register-sized pieces. Large arguments are split between
3632 registers and stack. */
3633 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3634 are treated specially: Irix cc passes
3635 them in registers where gcc sometimes puts them on the
3636 stack. For maximum compatibility, we will put them in
3638 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3639 && len
% MIPS32_REGSIZE
!= 0);
3640 /* Structures should be aligned to eight bytes (even arg registers)
3641 on MIPS_ABI_O32, if their first member has double precision. */
3642 if (mips_type_needs_double_align (arg_type
))
3647 stack_offset
+= MIPS32_REGSIZE
;
3652 /* Remember if the argument was written to the stack. */
3653 int stack_used_p
= 0;
3654 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3657 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3660 /* Write this portion of the argument to the stack. */
3661 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3662 || odd_sized_struct
)
3664 /* Should shorter than int integer values be
3665 promoted to int before being stored? */
3666 int longword_offset
= 0;
3672 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3673 paddr_nz (stack_offset
));
3674 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3675 paddr_nz (longword_offset
));
3678 addr
= sp
+ stack_offset
+ longword_offset
;
3683 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3685 for (i
= 0; i
< partial_len
; i
++)
3687 fprintf_unfiltered (gdb_stdlog
, "%02x",
3691 write_memory (addr
, val
, partial_len
);
3694 /* Note!!! This is NOT an else clause. Odd sized
3695 structs may go thru BOTH paths. */
3696 /* Write this portion of the argument to a general
3697 purpose register. */
3698 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3700 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3701 /* Value may need to be sign extended, because
3702 mips_isa_regsize() != mips_abi_regsize(). */
3704 /* A non-floating-point argument being passed in a
3705 general register. If a struct or union, and if
3706 the remaining length is smaller than the register
3707 size, we have to adjust the register value on
3710 It does not seem to be necessary to do the
3711 same for integral types.
3713 Also don't do this adjustment on O64 binaries.
3715 cagney/2001-07-23: gdb/179: Also, GCC, when
3716 outputting LE O32 with sizeof (struct) <
3717 mips_abi_regsize(), generates a left shift
3718 as part of storing the argument in a register
3719 (the left shift isn't generated when
3720 sizeof (struct) >= mips_abi_regsize()). Since
3721 it is quite possible that this is GCC
3722 contradicting the LE/O32 ABI, GDB has not been
3723 adjusted to accommodate this. Either someone
3724 needs to demonstrate that the LE/O32 ABI
3725 specifies such a left shift OR this new ABI gets
3726 identified as such and GDB gets tweaked
3729 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3730 && partial_len
< MIPS32_REGSIZE
3731 && (typecode
== TYPE_CODE_STRUCT
3732 || typecode
== TYPE_CODE_UNION
))
3733 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3737 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3739 phex (regval
, MIPS32_REGSIZE
));
3740 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3743 /* Prevent subsequent floating point arguments from
3744 being passed in floating point registers. */
3745 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
3751 /* Compute the the offset into the stack at which we
3752 will copy the next parameter.
3754 In older ABIs, the caller reserved space for
3755 registers that contained arguments. This was loosely
3756 refered to as their "home". Consequently, space is
3757 always allocated. */
3759 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3763 fprintf_unfiltered (gdb_stdlog
, "\n");
3766 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3768 /* Return adjusted stack pointer. */
3772 static enum return_value_convention
3773 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3774 struct type
*type
, struct regcache
*regcache
,
3775 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3777 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3779 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3780 || TYPE_CODE (type
) == TYPE_CODE_UNION
3781 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3782 return RETURN_VALUE_STRUCT_CONVENTION
;
3783 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3784 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3786 /* A single-precision floating-point value. It fits in the
3787 least significant part of FP0. */
3789 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3790 mips_xfer_register (gdbarch
, regcache
,
3791 gdbarch_num_regs (gdbarch
)
3792 + mips_regnum (gdbarch
)->fp0
,
3794 gdbarch_byte_order (gdbarch
),
3795 readbuf
, writebuf
, 0);
3796 return RETURN_VALUE_REGISTER_CONVENTION
;
3798 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3799 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3801 /* A double-precision floating-point value. The most
3802 significant part goes in FP1, and the least significant in
3805 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3806 switch (gdbarch_byte_order (gdbarch
))
3808 case BFD_ENDIAN_LITTLE
:
3809 mips_xfer_register (gdbarch
, regcache
,
3810 gdbarch_num_regs (gdbarch
)
3811 + mips_regnum (gdbarch
)->fp0
+
3812 0, 4, gdbarch_byte_order (gdbarch
),
3813 readbuf
, writebuf
, 0);
3814 mips_xfer_register (gdbarch
, regcache
,
3815 gdbarch_num_regs (gdbarch
)
3816 + mips_regnum (gdbarch
)->fp0
+ 1,
3817 4, gdbarch_byte_order (gdbarch
),
3818 readbuf
, writebuf
, 4);
3820 case BFD_ENDIAN_BIG
:
3821 mips_xfer_register (gdbarch
, regcache
,
3822 gdbarch_num_regs (gdbarch
)
3823 + mips_regnum (gdbarch
)->fp0
+ 1,
3824 4, gdbarch_byte_order (gdbarch
),
3825 readbuf
, writebuf
, 0);
3826 mips_xfer_register (gdbarch
, regcache
,
3827 gdbarch_num_regs (gdbarch
)
3828 + mips_regnum (gdbarch
)->fp0
+ 0,
3829 4, gdbarch_byte_order (gdbarch
),
3830 readbuf
, writebuf
, 4);
3833 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3835 return RETURN_VALUE_REGISTER_CONVENTION
;
3838 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3839 && TYPE_NFIELDS (type
) <= 2
3840 && TYPE_NFIELDS (type
) >= 1
3841 && ((TYPE_NFIELDS (type
) == 1
3842 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3844 || (TYPE_NFIELDS (type
) == 2
3845 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3847 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3849 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3851 /* A struct that contains one or two floats. Each value is part
3852 in the least significant part of their floating point
3854 gdb_byte reg
[MAX_REGISTER_SIZE
];
3857 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3858 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3860 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3863 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3865 mips_xfer_register (gdbarch
, regcache
,
3866 gdbarch_num_regs (gdbarch
) + regnum
,
3867 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3868 gdbarch_byte_order (gdbarch
),
3869 readbuf
, writebuf
, offset
);
3871 return RETURN_VALUE_REGISTER_CONVENTION
;
3875 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3876 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3878 /* A structure or union. Extract the left justified value,
3879 regardless of the byte order. I.e. DO NOT USE
3883 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3884 offset
< TYPE_LENGTH (type
);
3885 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3887 int xfer
= register_size (gdbarch
, regnum
);
3888 if (offset
+ xfer
> TYPE_LENGTH (type
))
3889 xfer
= TYPE_LENGTH (type
) - offset
;
3891 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3892 offset
, xfer
, regnum
);
3893 mips_xfer_register (gdbarch
, regcache
,
3894 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3895 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3897 return RETURN_VALUE_REGISTER_CONVENTION
;
3902 /* A scalar extract each part but least-significant-byte
3903 justified. o32 thinks registers are 4 byte, regardless of
3907 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3908 offset
< TYPE_LENGTH (type
);
3909 offset
+= MIPS32_REGSIZE
, regnum
++)
3911 int xfer
= MIPS32_REGSIZE
;
3912 if (offset
+ xfer
> TYPE_LENGTH (type
))
3913 xfer
= TYPE_LENGTH (type
) - offset
;
3915 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3916 offset
, xfer
, regnum
);
3917 mips_xfer_register (gdbarch
, regcache
,
3918 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3919 gdbarch_byte_order (gdbarch
),
3920 readbuf
, writebuf
, offset
);
3922 return RETURN_VALUE_REGISTER_CONVENTION
;
3926 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3930 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3931 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3933 struct value
**args
, CORE_ADDR sp
,
3934 int struct_return
, CORE_ADDR struct_addr
)
3940 int stack_offset
= 0;
3941 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3942 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3944 /* For shared libraries, "t9" needs to point at the function
3946 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3948 /* Set the return address register to point to the entry point of
3949 the program, where a breakpoint lies in wait. */
3950 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3952 /* First ensure that the stack and structure return address (if any)
3953 are properly aligned. The stack has to be at least 64-bit
3954 aligned even on 32-bit machines, because doubles must be 64-bit
3955 aligned. For n32 and n64, stack frames need to be 128-bit
3956 aligned, so we round to this widest known alignment. */
3958 sp
= align_down (sp
, 16);
3959 struct_addr
= align_down (struct_addr
, 16);
3961 /* Now make space on the stack for the args. */
3962 for (argnum
= 0; argnum
< nargs
; argnum
++)
3964 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3965 int arglen
= TYPE_LENGTH (arg_type
);
3967 /* Allocate space on the stack. */
3968 len
+= align_up (arglen
, MIPS64_REGSIZE
);
3970 sp
-= align_up (len
, 16);
3973 fprintf_unfiltered (gdb_stdlog
,
3974 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3975 paddr_nz (sp
), (long) align_up (len
, 16));
3977 /* Initialize the integer and float register pointers. */
3978 argreg
= MIPS_A0_REGNUM
;
3979 float_argreg
= mips_fpa0_regnum (gdbarch
);
3981 /* The struct_return pointer occupies the first parameter-passing reg. */
3985 fprintf_unfiltered (gdb_stdlog
,
3986 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3987 argreg
, paddr_nz (struct_addr
));
3988 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3989 stack_offset
+= MIPS64_REGSIZE
;
3992 /* Now load as many as possible of the first arguments into
3993 registers, and push the rest onto the stack. Loop thru args
3994 from first to last. */
3995 for (argnum
= 0; argnum
< nargs
; argnum
++)
3997 const gdb_byte
*val
;
3998 struct value
*arg
= args
[argnum
];
3999 struct type
*arg_type
= check_typedef (value_type (arg
));
4000 int len
= TYPE_LENGTH (arg_type
);
4001 enum type_code typecode
= TYPE_CODE (arg_type
);
4004 fprintf_unfiltered (gdb_stdlog
,
4005 "mips_o64_push_dummy_call: %d len=%d type=%d",
4006 argnum
+ 1, len
, (int) typecode
);
4008 val
= value_contents (arg
);
4010 /* Floating point arguments passed in registers have to be
4011 treated specially. On 32-bit architectures, doubles
4012 are passed in register pairs; the even register gets
4013 the low word, and the odd register gets the high word.
4014 On O32/O64, the first two floating point arguments are
4015 also copied to general registers, because MIPS16 functions
4016 don't use float registers for arguments. This duplication of
4017 arguments in general registers can't hurt non-MIPS16 functions
4018 because those registers are normally skipped. */
4020 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4021 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4023 LONGEST regval
= extract_unsigned_integer (val
, len
);
4025 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4026 float_argreg
, phex (regval
, len
));
4027 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4029 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4030 argreg
, phex (regval
, len
));
4031 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4033 /* Reserve space for the FP register. */
4034 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4038 /* Copy the argument to general registers or the stack in
4039 register-sized pieces. Large arguments are split between
4040 registers and stack. */
4041 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4042 are treated specially: Irix cc passes them in registers
4043 where gcc sometimes puts them on the stack. For maximum
4044 compatibility, we will put them in both places. */
4045 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4046 && len
% MIPS64_REGSIZE
!= 0);
4049 /* Remember if the argument was written to the stack. */
4050 int stack_used_p
= 0;
4051 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4054 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4057 /* Write this portion of the argument to the stack. */
4058 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4059 || odd_sized_struct
)
4061 /* Should shorter than int integer values be
4062 promoted to int before being stored? */
4063 int longword_offset
= 0;
4066 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4068 if ((typecode
== TYPE_CODE_INT
4069 || typecode
== TYPE_CODE_PTR
4070 || typecode
== TYPE_CODE_FLT
)
4072 longword_offset
= MIPS64_REGSIZE
- len
;
4077 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4078 paddr_nz (stack_offset
));
4079 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4080 paddr_nz (longword_offset
));
4083 addr
= sp
+ stack_offset
+ longword_offset
;
4088 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4090 for (i
= 0; i
< partial_len
; i
++)
4092 fprintf_unfiltered (gdb_stdlog
, "%02x",
4096 write_memory (addr
, val
, partial_len
);
4099 /* Note!!! This is NOT an else clause. Odd sized
4100 structs may go thru BOTH paths. */
4101 /* Write this portion of the argument to a general
4102 purpose register. */
4103 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4105 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4106 /* Value may need to be sign extended, because
4107 mips_isa_regsize() != mips_abi_regsize(). */
4109 /* A non-floating-point argument being passed in a
4110 general register. If a struct or union, and if
4111 the remaining length is smaller than the register
4112 size, we have to adjust the register value on
4115 It does not seem to be necessary to do the
4116 same for integral types. */
4118 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4119 && partial_len
< MIPS64_REGSIZE
4120 && (typecode
== TYPE_CODE_STRUCT
4121 || typecode
== TYPE_CODE_UNION
))
4122 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4126 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4128 phex (regval
, MIPS64_REGSIZE
));
4129 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4132 /* Prevent subsequent floating point arguments from
4133 being passed in floating point registers. */
4134 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4140 /* Compute the the offset into the stack at which we
4141 will copy the next parameter.
4143 In older ABIs, the caller reserved space for
4144 registers that contained arguments. This was loosely
4145 refered to as their "home". Consequently, space is
4146 always allocated. */
4148 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4152 fprintf_unfiltered (gdb_stdlog
, "\n");
4155 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4157 /* Return adjusted stack pointer. */
4161 static enum return_value_convention
4162 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4163 struct type
*type
, struct regcache
*regcache
,
4164 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4166 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4168 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4169 || TYPE_CODE (type
) == TYPE_CODE_UNION
4170 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4171 return RETURN_VALUE_STRUCT_CONVENTION
;
4172 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4174 /* A floating-point value. It fits in the least significant
4177 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4178 mips_xfer_register (gdbarch
, regcache
,
4179 gdbarch_num_regs (gdbarch
)
4180 + mips_regnum (gdbarch
)->fp0
,
4182 gdbarch_byte_order (gdbarch
),
4183 readbuf
, writebuf
, 0);
4184 return RETURN_VALUE_REGISTER_CONVENTION
;
4188 /* A scalar extract each part but least-significant-byte
4192 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4193 offset
< TYPE_LENGTH (type
);
4194 offset
+= MIPS64_REGSIZE
, regnum
++)
4196 int xfer
= MIPS64_REGSIZE
;
4197 if (offset
+ xfer
> TYPE_LENGTH (type
))
4198 xfer
= TYPE_LENGTH (type
) - offset
;
4200 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4201 offset
, xfer
, regnum
);
4202 mips_xfer_register (gdbarch
, regcache
,
4203 gdbarch_num_regs (gdbarch
) + regnum
,
4204 xfer
, gdbarch_byte_order (gdbarch
),
4205 readbuf
, writebuf
, offset
);
4207 return RETURN_VALUE_REGISTER_CONVENTION
;
4211 /* Floating point register management.
4213 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4214 64bit operations, these early MIPS cpus treat fp register pairs
4215 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4216 registers and offer a compatibility mode that emulates the MIPS2 fp
4217 model. When operating in MIPS2 fp compat mode, later cpu's split
4218 double precision floats into two 32-bit chunks and store them in
4219 consecutive fp regs. To display 64-bit floats stored in this
4220 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4221 Throw in user-configurable endianness and you have a real mess.
4223 The way this works is:
4224 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4225 double-precision value will be split across two logical registers.
4226 The lower-numbered logical register will hold the low-order bits,
4227 regardless of the processor's endianness.
4228 - If we are on a 64-bit processor, and we are looking for a
4229 single-precision value, it will be in the low ordered bits
4230 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4231 save slot in memory.
4232 - If we are in 64-bit mode, everything is straightforward.
4234 Note that this code only deals with "live" registers at the top of the
4235 stack. We will attempt to deal with saved registers later, when
4236 the raw/cooked register interface is in place. (We need a general
4237 interface that can deal with dynamic saved register sizes -- fp
4238 regs could be 32 bits wide in one frame and 64 on the frame above
4241 static struct type
*
4242 mips_float_register_type (void)
4244 return builtin_type_ieee_single
;
4247 static struct type
*
4248 mips_double_register_type (void)
4250 return builtin_type_ieee_double
;
4253 /* Copy a 32-bit single-precision value from the current frame
4254 into rare_buffer. */
4257 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4258 gdb_byte
*rare_buffer
)
4260 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4261 int raw_size
= register_size (gdbarch
, regno
);
4262 gdb_byte
*raw_buffer
= alloca (raw_size
);
4264 if (!frame_register_read (frame
, regno
, raw_buffer
))
4265 error (_("can't read register %d (%s)"),
4266 regno
, gdbarch_register_name (gdbarch
, regno
));
4269 /* We have a 64-bit value for this register. Find the low-order
4273 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4278 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4282 memcpy (rare_buffer
, raw_buffer
, 4);
4286 /* Copy a 64-bit double-precision value from the current frame into
4287 rare_buffer. This may include getting half of it from the next
4291 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4292 gdb_byte
*rare_buffer
)
4294 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4295 int raw_size
= register_size (gdbarch
, regno
);
4297 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4299 /* We have a 64-bit value for this register, and we should use
4301 if (!frame_register_read (frame
, regno
, rare_buffer
))
4302 error (_("can't read register %d (%s)"),
4303 regno
, gdbarch_register_name (gdbarch
, regno
));
4307 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4309 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4310 internal_error (__FILE__
, __LINE__
,
4311 _("mips_read_fp_register_double: bad access to "
4312 "odd-numbered FP register"));
4314 /* mips_read_fp_register_single will find the correct 32 bits from
4316 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4318 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4319 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4323 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4324 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4330 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4332 { /* do values for FP (float) regs */
4333 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4334 gdb_byte
*raw_buffer
;
4335 double doub
, flt1
; /* doubles extracted from raw hex data */
4338 raw_buffer
= alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
));
4340 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4341 fprintf_filtered (file
, "%*s",
4342 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4345 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4347 /* 4-byte registers: Print hex and floating. Also print even
4348 numbered registers as doubles. */
4349 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4350 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4352 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4355 fprintf_filtered (file
, " flt: ");
4357 fprintf_filtered (file
, " <invalid float> ");
4359 fprintf_filtered (file
, "%-17.9g", flt1
);
4361 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4363 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4364 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4367 fprintf_filtered (file
, " dbl: ");
4369 fprintf_filtered (file
, "<invalid double>");
4371 fprintf_filtered (file
, "%-24.17g", doub
);
4376 /* Eight byte registers: print each one as hex, float and double. */
4377 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4378 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4380 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4381 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4384 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4387 fprintf_filtered (file
, " flt: ");
4389 fprintf_filtered (file
, "<invalid float>");
4391 fprintf_filtered (file
, "%-17.9g", flt1
);
4393 fprintf_filtered (file
, " dbl: ");
4395 fprintf_filtered (file
, "<invalid double>");
4397 fprintf_filtered (file
, "%-24.17g", doub
);
4402 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4405 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4406 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4409 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4411 mips_print_fp_register (file
, frame
, regnum
);
4415 /* Get the data in raw format. */
4416 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4418 fprintf_filtered (file
, "%s: [Invalid]",
4419 gdbarch_register_name (gdbarch
, regnum
));
4423 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4425 /* The problem with printing numeric register names (r26, etc.) is that
4426 the user can't use them on input. Probably the best solution is to
4427 fix it so that either the numeric or the funky (a2, etc.) names
4428 are accepted on input. */
4429 if (regnum
< MIPS_NUMREGS
)
4430 fprintf_filtered (file
, "(r%d): ", regnum
);
4432 fprintf_filtered (file
, ": ");
4434 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4436 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4440 print_scalar_formatted (raw_buffer
+ offset
,
4441 register_type (gdbarch
, regnum
), 'x', 0,
4445 /* Replacement for generic do_registers_info.
4446 Print regs in pretty columns. */
4449 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4452 fprintf_filtered (file
, " ");
4453 mips_print_fp_register (file
, frame
, regnum
);
4454 fprintf_filtered (file
, "\n");
4459 /* Print a row's worth of GP (int) registers, with name labels above */
4462 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4465 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4466 /* do values for GP (int) regs */
4467 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4468 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4472 /* For GP registers, we print a separate row of names above the vals */
4473 for (col
= 0, regnum
= start_regnum
;
4474 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4475 + gdbarch_num_pseudo_regs (gdbarch
);
4478 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4479 continue; /* unused register */
4480 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4482 break; /* end the row: reached FP register */
4483 /* Large registers are handled separately. */
4484 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4487 break; /* End the row before this register. */
4489 /* Print this register on a row by itself. */
4490 mips_print_register (file
, frame
, regnum
);
4491 fprintf_filtered (file
, "\n");
4495 fprintf_filtered (file
, " ");
4496 fprintf_filtered (file
,
4497 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4498 gdbarch_register_name (gdbarch
, regnum
));
4505 /* print the R0 to R31 names */
4506 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4507 fprintf_filtered (file
, "\n R%-4d",
4508 start_regnum
% gdbarch_num_regs (gdbarch
));
4510 fprintf_filtered (file
, "\n ");
4512 /* now print the values in hex, 4 or 8 to the row */
4513 for (col
= 0, regnum
= start_regnum
;
4514 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4515 + gdbarch_num_pseudo_regs (gdbarch
);
4518 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4519 continue; /* unused register */
4520 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4522 break; /* end row: reached FP register */
4523 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4524 break; /* End row: large register. */
4526 /* OK: get the data in raw format. */
4527 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4528 error (_("can't read register %d (%s)"),
4529 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4530 /* pad small registers */
4532 byte
< (mips_abi_regsize (gdbarch
)
4533 - register_size (gdbarch
, regnum
)); byte
++)
4534 printf_filtered (" ");
4535 /* Now print the register value in hex, endian order. */
4536 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4538 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4539 byte
< register_size (gdbarch
, regnum
); byte
++)
4540 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4542 for (byte
= register_size (gdbarch
, regnum
) - 1;
4544 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4545 fprintf_filtered (file
, " ");
4548 if (col
> 0) /* ie. if we actually printed anything... */
4549 fprintf_filtered (file
, "\n");
4554 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4557 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4558 struct frame_info
*frame
, int regnum
, int all
)
4560 if (regnum
!= -1) /* do one specified register */
4562 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4563 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4564 error (_("Not a valid register for the current processor type"));
4566 mips_print_register (file
, frame
, regnum
);
4567 fprintf_filtered (file
, "\n");
4570 /* do all (or most) registers */
4572 regnum
= gdbarch_num_regs (gdbarch
);
4573 while (regnum
< gdbarch_num_regs (gdbarch
)
4574 + gdbarch_num_pseudo_regs (gdbarch
))
4576 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4579 if (all
) /* true for "INFO ALL-REGISTERS" command */
4580 regnum
= print_fp_register_row (file
, frame
, regnum
);
4582 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4585 regnum
= print_gp_register_row (file
, frame
, regnum
);
4590 /* Is this a branch with a delay slot? */
4593 is_delayed (unsigned long insn
)
4596 for (i
= 0; i
< NUMOPCODES
; ++i
)
4597 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4598 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4600 return (i
< NUMOPCODES
4601 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4602 | INSN_COND_BRANCH_DELAY
4603 | INSN_COND_BRANCH_LIKELY
)));
4607 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4608 struct frame_info
*frame
)
4610 CORE_ADDR pc
= get_frame_pc (frame
);
4611 gdb_byte buf
[MIPS_INSN32_SIZE
];
4613 /* There is no branch delay slot on MIPS16. */
4614 if (mips_pc_is_mips16 (pc
))
4617 if (!breakpoint_here_p (pc
+ 4))
4620 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4621 /* If error reading memory, guess that it is not a delayed
4624 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4627 /* To skip prologues, I use this predicate. Returns either PC itself
4628 if the code at PC does not look like a function prologue; otherwise
4629 returns an address that (if we're lucky) follows the prologue. If
4630 LENIENT, then we must skip everything which is involved in setting
4631 up the frame (it's OK to skip more, just so long as we don't skip
4632 anything which might clobber the registers which are being saved.
4633 We must skip more in the case where part of the prologue is in the
4634 delay slot of a non-prologue instruction). */
4637 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4640 CORE_ADDR func_addr
;
4642 /* See if we can determine the end of the prologue via the symbol table.
4643 If so, then return either PC, or the PC after the prologue, whichever
4645 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4647 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4648 if (post_prologue_pc
!= 0)
4649 return max (pc
, post_prologue_pc
);
4652 /* Can't determine prologue from the symbol table, need to examine
4655 /* Find an upper limit on the function prologue using the debug
4656 information. If the debug information could not be used to provide
4657 that bound, then use an arbitrary large number as the upper bound. */
4658 limit_pc
= skip_prologue_using_sal (pc
);
4660 limit_pc
= pc
+ 100; /* Magic. */
4662 if (mips_pc_is_mips16 (pc
))
4663 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4665 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4668 /* Check whether the PC is in a function epilogue (32-bit version).
4669 This is a helper function for mips_in_function_epilogue_p. */
4671 mips32_in_function_epilogue_p (CORE_ADDR pc
)
4673 CORE_ADDR func_addr
= 0, func_end
= 0;
4675 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4677 /* The MIPS epilogue is max. 12 bytes long. */
4678 CORE_ADDR addr
= func_end
- 12;
4680 if (addr
< func_addr
+ 4)
4681 addr
= func_addr
+ 4;
4685 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4687 unsigned long high_word
;
4690 inst
= mips_fetch_instruction (pc
);
4691 high_word
= (inst
>> 16) & 0xffff;
4693 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4694 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4695 && inst
!= 0x03e00008 /* jr $ra */
4696 && inst
!= 0x00000000) /* nop */
4706 /* Check whether the PC is in a function epilogue (16-bit version).
4707 This is a helper function for mips_in_function_epilogue_p. */
4709 mips16_in_function_epilogue_p (CORE_ADDR pc
)
4711 CORE_ADDR func_addr
= 0, func_end
= 0;
4713 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4715 /* The MIPS epilogue is max. 12 bytes long. */
4716 CORE_ADDR addr
= func_end
- 12;
4718 if (addr
< func_addr
+ 4)
4719 addr
= func_addr
+ 4;
4723 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4725 unsigned short inst
;
4727 inst
= mips_fetch_instruction (pc
);
4729 if ((inst
& 0xf800) == 0xf000) /* extend */
4732 if (inst
!= 0x6300 /* addiu $sp,offset */
4733 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
4734 && inst
!= 0xe820 /* jr $ra */
4735 && inst
!= 0xe8a0 /* jrc $ra */
4736 && inst
!= 0x6500) /* nop */
4746 /* The epilogue is defined here as the area at the end of a function,
4747 after an instruction which destroys the function's stack frame. */
4749 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4751 if (mips_pc_is_mips16 (pc
))
4752 return mips16_in_function_epilogue_p (pc
);
4754 return mips32_in_function_epilogue_p (pc
);
4757 /* Root of all "set mips "/"show mips " commands. This will eventually be
4758 used for all MIPS-specific commands. */
4761 show_mips_command (char *args
, int from_tty
)
4763 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4767 set_mips_command (char *args
, int from_tty
)
4770 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4771 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4774 /* Commands to show/set the MIPS FPU type. */
4777 show_mipsfpu_command (char *args
, int from_tty
)
4781 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
4784 ("The MIPS floating-point coprocessor is unknown "
4785 "because the current architecture is not MIPS.\n");
4789 switch (MIPS_FPU_TYPE (current_gdbarch
))
4791 case MIPS_FPU_SINGLE
:
4792 fpu
= "single-precision";
4794 case MIPS_FPU_DOUBLE
:
4795 fpu
= "double-precision";
4798 fpu
= "absent (none)";
4801 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4803 if (mips_fpu_type_auto
)
4805 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4809 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4814 set_mipsfpu_command (char *args
, int from_tty
)
4817 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4818 show_mipsfpu_command (args
, from_tty
);
4822 set_mipsfpu_single_command (char *args
, int from_tty
)
4824 struct gdbarch_info info
;
4825 gdbarch_info_init (&info
);
4826 mips_fpu_type
= MIPS_FPU_SINGLE
;
4827 mips_fpu_type_auto
= 0;
4828 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4829 instead of relying on globals. Doing that would let generic code
4830 handle the search for this specific architecture. */
4831 if (!gdbarch_update_p (info
))
4832 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4836 set_mipsfpu_double_command (char *args
, int from_tty
)
4838 struct gdbarch_info info
;
4839 gdbarch_info_init (&info
);
4840 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4841 mips_fpu_type_auto
= 0;
4842 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4843 instead of relying on globals. Doing that would let generic code
4844 handle the search for this specific architecture. */
4845 if (!gdbarch_update_p (info
))
4846 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4850 set_mipsfpu_none_command (char *args
, int from_tty
)
4852 struct gdbarch_info info
;
4853 gdbarch_info_init (&info
);
4854 mips_fpu_type
= MIPS_FPU_NONE
;
4855 mips_fpu_type_auto
= 0;
4856 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4857 instead of relying on globals. Doing that would let generic code
4858 handle the search for this specific architecture. */
4859 if (!gdbarch_update_p (info
))
4860 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4864 set_mipsfpu_auto_command (char *args
, int from_tty
)
4866 mips_fpu_type_auto
= 1;
4869 /* Attempt to identify the particular processor model by reading the
4870 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4871 the relevant processor still exists (it dates back to '94) and
4872 secondly this is not the way to do this. The processor type should
4873 be set by forcing an architecture change. */
4876 deprecated_mips_set_processor_regs_hack (void)
4878 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4881 regcache_cooked_read_unsigned (get_current_regcache (),
4882 MIPS_PRID_REGNUM
, &prid
);
4883 if ((prid
& ~0xf) == 0x700)
4884 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4887 /* Just like reinit_frame_cache, but with the right arguments to be
4888 callable as an sfunc. */
4891 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4892 struct cmd_list_element
*c
)
4894 reinit_frame_cache ();
4898 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4900 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4902 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4903 disassembler needs to be able to locally determine the ISA, and
4904 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4906 if (mips_pc_is_mips16 (memaddr
))
4907 info
->mach
= bfd_mach_mips16
;
4909 /* Round down the instruction address to the appropriate boundary. */
4910 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4912 /* Set the disassembler options. */
4913 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4915 /* Set up the disassembler info, so that we get the right
4916 register names from libopcodes. */
4917 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4918 info
->disassembler_options
= "gpr-names=n32";
4920 info
->disassembler_options
= "gpr-names=64";
4921 info
->flavour
= bfd_target_elf_flavour
;
4924 /* This string is not recognized explicitly by the disassembler,
4925 but it tells the disassembler to not try to guess the ABI from
4926 the bfd elf headers, such that, if the user overrides the ABI
4927 of a program linked as NewABI, the disassembly will follow the
4928 register naming conventions specified by the user. */
4929 info
->disassembler_options
= "gpr-names=32";
4931 /* Call the appropriate disassembler based on the target endian-ness. */
4932 if (info
->endian
== BFD_ENDIAN_BIG
)
4933 return print_insn_big_mips (memaddr
, info
);
4935 return print_insn_little_mips (memaddr
, info
);
4938 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4939 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4940 It returns a pointer to a string of bytes that encode a breakpoint
4941 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4942 necessary) to point to the actual memory location where the breakpoint
4943 should be inserted. */
4945 static const gdb_byte
*
4946 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
4948 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4950 if (mips_pc_is_mips16 (*pcptr
))
4952 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4953 *pcptr
= unmake_mips16_addr (*pcptr
);
4954 *lenptr
= sizeof (mips16_big_breakpoint
);
4955 return mips16_big_breakpoint
;
4959 /* The IDT board uses an unusual breakpoint value, and
4960 sometimes gets confused when it sees the usual MIPS
4961 breakpoint instruction. */
4962 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4963 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4964 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4966 *lenptr
= sizeof (big_breakpoint
);
4968 if (strcmp (target_shortname
, "mips") == 0)
4969 return idt_big_breakpoint
;
4970 else if (strcmp (target_shortname
, "ddb") == 0
4971 || strcmp (target_shortname
, "pmon") == 0
4972 || strcmp (target_shortname
, "lsi") == 0)
4973 return pmon_big_breakpoint
;
4975 return big_breakpoint
;
4980 if (mips_pc_is_mips16 (*pcptr
))
4982 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4983 *pcptr
= unmake_mips16_addr (*pcptr
);
4984 *lenptr
= sizeof (mips16_little_breakpoint
);
4985 return mips16_little_breakpoint
;
4989 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4990 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4991 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4993 *lenptr
= sizeof (little_breakpoint
);
4995 if (strcmp (target_shortname
, "mips") == 0)
4996 return idt_little_breakpoint
;
4997 else if (strcmp (target_shortname
, "ddb") == 0
4998 || strcmp (target_shortname
, "pmon") == 0
4999 || strcmp (target_shortname
, "lsi") == 0)
5000 return pmon_little_breakpoint
;
5002 return little_breakpoint
;
5007 /* If PC is in a mips16 call or return stub, return the address of the target
5008 PC, which is either the callee or the caller. There are several
5009 cases which must be handled:
5011 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5012 target PC is in $31 ($ra).
5013 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5014 and the target PC is in $2.
5015 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5016 before the jal instruction, this is effectively a call stub
5017 and the the target PC is in $2. Otherwise this is effectively
5018 a return stub and the target PC is in $18.
5020 See the source code for the stubs in gcc/config/mips/mips16.S for
5024 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5027 CORE_ADDR start_addr
;
5029 /* Find the starting address and name of the function containing the PC. */
5030 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5033 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5034 target PC is in $31 ($ra). */
5035 if (strcmp (name
, "__mips16_ret_sf") == 0
5036 || strcmp (name
, "__mips16_ret_df") == 0)
5037 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5039 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5041 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5042 and the target PC is in $2. */
5043 if (name
[19] >= '0' && name
[19] <= '9')
5044 return get_frame_register_signed (frame
, 2);
5046 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5047 before the jal instruction, this is effectively a call stub
5048 and the the target PC is in $2. Otherwise this is effectively
5049 a return stub and the target PC is in $18. */
5050 else if (name
[19] == 's' || name
[19] == 'd')
5052 if (pc
== start_addr
)
5054 /* Check if the target of the stub is a compiler-generated
5055 stub. Such a stub for a function bar might have a name
5056 like __fn_stub_bar, and might look like this:
5061 la $1,bar (becomes a lui/addiu pair)
5063 So scan down to the lui/addi and extract the target
5064 address from those two instructions. */
5066 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5070 /* See if the name of the target function is __fn_stub_*. */
5071 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5074 if (strncmp (name
, "__fn_stub_", 10) != 0
5075 && strcmp (name
, "etext") != 0
5076 && strcmp (name
, "_etext") != 0)
5079 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5080 The limit on the search is arbitrarily set to 20
5081 instructions. FIXME. */
5082 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5084 inst
= mips_fetch_instruction (target_pc
);
5085 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5086 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5087 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5088 return pc
| (inst
& 0xffff); /* low word */
5091 /* Couldn't find the lui/addui pair, so return stub address. */
5095 /* This is the 'return' part of a call stub. The return
5096 address is in $r18. */
5097 return get_frame_register_signed (frame
, 18);
5100 return 0; /* not a stub */
5103 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5104 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5107 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5110 if (num
>= 0 && num
< 32)
5112 else if (num
>= 38 && num
< 70)
5113 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5115 regnum
= mips_regnum (gdbarch
)->hi
;
5117 regnum
= mips_regnum (gdbarch
)->lo
;
5119 /* This will hopefully (eventually) provoke a warning. Should
5120 we be calling complaint() here? */
5121 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5122 return gdbarch_num_regs (gdbarch
) + regnum
;
5126 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5127 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5130 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5133 if (num
>= 0 && num
< 32)
5135 else if (num
>= 32 && num
< 64)
5136 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5138 regnum
= mips_regnum (gdbarch
)->hi
;
5140 regnum
= mips_regnum (gdbarch
)->lo
;
5142 /* This will hopefully (eventually) provoke a warning. Should we
5143 be calling complaint() here? */
5144 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5145 return gdbarch_num_regs (gdbarch
) + regnum
;
5149 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5151 /* Only makes sense to supply raw registers. */
5152 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5153 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5154 decide if it is valid. Should instead define a standard sim/gdb
5155 register numbering scheme. */
5156 if (gdbarch_register_name (gdbarch
,
5157 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5158 && gdbarch_register_name (gdbarch
,
5159 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
5162 return LEGACY_SIM_REGNO_IGNORE
;
5166 /* Convert an integer into an address. Extracting the value signed
5167 guarantees a correctly sign extended address. */
5170 mips_integer_to_address (struct gdbarch
*gdbarch
,
5171 struct type
*type
, const gdb_byte
*buf
)
5173 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
5176 /* Dummy virtual frame pointer method. This is no more or less accurate
5177 than most other architectures; we just need to be explicit about it,
5178 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5179 an assertion failure. */
5182 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5183 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5185 *reg
= MIPS_SP_REGNUM
;
5190 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5192 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5193 const char *name
= bfd_get_section_name (abfd
, sect
);
5195 if (*abip
!= MIPS_ABI_UNKNOWN
)
5198 if (strncmp (name
, ".mdebug.", 8) != 0)
5201 if (strcmp (name
, ".mdebug.abi32") == 0)
5202 *abip
= MIPS_ABI_O32
;
5203 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5204 *abip
= MIPS_ABI_N32
;
5205 else if (strcmp (name
, ".mdebug.abi64") == 0)
5206 *abip
= MIPS_ABI_N64
;
5207 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5208 *abip
= MIPS_ABI_O64
;
5209 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5210 *abip
= MIPS_ABI_EABI32
;
5211 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5212 *abip
= MIPS_ABI_EABI64
;
5214 warning (_("unsupported ABI %s."), name
+ 8);
5218 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5220 int *lbp
= (int *) obj
;
5221 const char *name
= bfd_get_section_name (abfd
, sect
);
5223 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5225 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5227 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5228 warning (_("unrecognized .gcc_compiled_longXX"));
5231 static enum mips_abi
5232 global_mips_abi (void)
5236 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5237 if (mips_abi_strings
[i
] == mips_abi_string
)
5238 return (enum mips_abi
) i
;
5240 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5244 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5246 /* If the size matches the set of 32-bit or 64-bit integer registers,
5247 assume that's what we've got. */
5248 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5249 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5251 /* If the size matches the full set of registers GDB traditionally
5252 knows about, including floating point, for either 32-bit or
5253 64-bit, assume that's what we've got. */
5254 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5255 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5257 /* Otherwise we don't have a useful guess. */
5260 static struct value
*
5261 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5263 const int *reg_p
= baton
;
5264 return value_of_register (*reg_p
, frame
);
5267 static struct gdbarch
*
5268 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5270 struct gdbarch
*gdbarch
;
5271 struct gdbarch_tdep
*tdep
;
5273 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5275 enum mips_fpu_type fpu_type
;
5276 struct tdesc_arch_data
*tdesc_data
= NULL
;
5277 int elf_fpu_type
= 0;
5279 /* Check any target description for validity. */
5280 if (tdesc_has_registers (info
.target_desc
))
5282 static const char *const mips_gprs
[] = {
5283 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5284 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5285 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5286 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5288 static const char *const mips_fprs
[] = {
5289 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5290 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5291 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5292 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5295 const struct tdesc_feature
*feature
;
5298 feature
= tdesc_find_feature (info
.target_desc
,
5299 "org.gnu.gdb.mips.cpu");
5300 if (feature
== NULL
)
5303 tdesc_data
= tdesc_data_alloc ();
5306 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5307 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5311 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5312 MIPS_EMBED_LO_REGNUM
, "lo");
5313 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5314 MIPS_EMBED_HI_REGNUM
, "hi");
5315 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5316 MIPS_EMBED_PC_REGNUM
, "pc");
5320 tdesc_data_cleanup (tdesc_data
);
5324 feature
= tdesc_find_feature (info
.target_desc
,
5325 "org.gnu.gdb.mips.cp0");
5326 if (feature
== NULL
)
5328 tdesc_data_cleanup (tdesc_data
);
5333 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5334 MIPS_EMBED_BADVADDR_REGNUM
,
5336 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5337 MIPS_PS_REGNUM
, "status");
5338 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5339 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5343 tdesc_data_cleanup (tdesc_data
);
5347 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5348 backend is not prepared for that, though. */
5349 feature
= tdesc_find_feature (info
.target_desc
,
5350 "org.gnu.gdb.mips.fpu");
5351 if (feature
== NULL
)
5353 tdesc_data_cleanup (tdesc_data
);
5358 for (i
= 0; i
< 32; i
++)
5359 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5360 i
+ MIPS_EMBED_FP0_REGNUM
,
5363 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5364 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5365 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5366 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5370 tdesc_data_cleanup (tdesc_data
);
5374 /* It would be nice to detect an attempt to use a 64-bit ABI
5375 when only 32-bit registers are provided. */
5378 /* First of all, extract the elf_flags, if available. */
5379 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5380 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5381 else if (arches
!= NULL
)
5382 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5386 fprintf_unfiltered (gdb_stdlog
,
5387 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5389 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5390 switch ((elf_flags
& EF_MIPS_ABI
))
5392 case E_MIPS_ABI_O32
:
5393 found_abi
= MIPS_ABI_O32
;
5395 case E_MIPS_ABI_O64
:
5396 found_abi
= MIPS_ABI_O64
;
5398 case E_MIPS_ABI_EABI32
:
5399 found_abi
= MIPS_ABI_EABI32
;
5401 case E_MIPS_ABI_EABI64
:
5402 found_abi
= MIPS_ABI_EABI64
;
5405 if ((elf_flags
& EF_MIPS_ABI2
))
5406 found_abi
= MIPS_ABI_N32
;
5408 found_abi
= MIPS_ABI_UNKNOWN
;
5412 /* GCC creates a pseudo-section whose name describes the ABI. */
5413 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5414 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5416 /* If we have no useful BFD information, use the ABI from the last
5417 MIPS architecture (if there is one). */
5418 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5419 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5421 /* Try the architecture for any hint of the correct ABI. */
5422 if (found_abi
== MIPS_ABI_UNKNOWN
5423 && info
.bfd_arch_info
!= NULL
5424 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5426 switch (info
.bfd_arch_info
->mach
)
5428 case bfd_mach_mips3900
:
5429 found_abi
= MIPS_ABI_EABI32
;
5431 case bfd_mach_mips4100
:
5432 case bfd_mach_mips5000
:
5433 found_abi
= MIPS_ABI_EABI64
;
5435 case bfd_mach_mips8000
:
5436 case bfd_mach_mips10000
:
5437 /* On Irix, ELF64 executables use the N64 ABI. The
5438 pseudo-sections which describe the ABI aren't present
5439 on IRIX. (Even for executables created by gcc.) */
5440 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5441 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5442 found_abi
= MIPS_ABI_N64
;
5444 found_abi
= MIPS_ABI_N32
;
5449 /* Default 64-bit objects to N64 instead of O32. */
5450 if (found_abi
== MIPS_ABI_UNKNOWN
5451 && info
.abfd
!= NULL
5452 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5453 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5454 found_abi
= MIPS_ABI_N64
;
5457 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5460 /* What has the user specified from the command line? */
5461 wanted_abi
= global_mips_abi ();
5463 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5466 /* Now that we have found what the ABI for this binary would be,
5467 check whether the user is overriding it. */
5468 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5469 mips_abi
= wanted_abi
;
5470 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5471 mips_abi
= found_abi
;
5473 mips_abi
= MIPS_ABI_O32
;
5475 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5478 /* Also used when doing an architecture lookup. */
5480 fprintf_unfiltered (gdb_stdlog
,
5481 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5482 mips64_transfers_32bit_regs_p
);
5484 /* Determine the MIPS FPU type. */
5487 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5488 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5489 Tag_GNU_MIPS_ABI_FP
);
5490 #endif /* HAVE_ELF */
5492 if (!mips_fpu_type_auto
)
5493 fpu_type
= mips_fpu_type
;
5494 else if (elf_fpu_type
!= 0)
5496 switch (elf_fpu_type
)
5499 fpu_type
= MIPS_FPU_DOUBLE
;
5502 fpu_type
= MIPS_FPU_SINGLE
;
5506 /* Soft float or unknown. */
5507 fpu_type
= MIPS_FPU_NONE
;
5511 else if (info
.bfd_arch_info
!= NULL
5512 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5513 switch (info
.bfd_arch_info
->mach
)
5515 case bfd_mach_mips3900
:
5516 case bfd_mach_mips4100
:
5517 case bfd_mach_mips4111
:
5518 case bfd_mach_mips4120
:
5519 fpu_type
= MIPS_FPU_NONE
;
5521 case bfd_mach_mips4650
:
5522 fpu_type
= MIPS_FPU_SINGLE
;
5525 fpu_type
= MIPS_FPU_DOUBLE
;
5528 else if (arches
!= NULL
)
5529 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5531 fpu_type
= MIPS_FPU_DOUBLE
;
5533 fprintf_unfiltered (gdb_stdlog
,
5534 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5536 /* Check for blatant incompatibilities. */
5538 /* If we have only 32-bit registers, then we can't debug a 64-bit
5540 if (info
.target_desc
5541 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5542 && mips_abi
!= MIPS_ABI_EABI32
5543 && mips_abi
!= MIPS_ABI_O32
)
5545 if (tdesc_data
!= NULL
)
5546 tdesc_data_cleanup (tdesc_data
);
5550 /* try to find a pre-existing architecture */
5551 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5553 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5555 /* MIPS needs to be pedantic about which ABI the object is
5557 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5559 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5561 /* Need to be pedantic about which register virtual size is
5563 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5564 != mips64_transfers_32bit_regs_p
)
5566 /* Be pedantic about which FPU is selected. */
5567 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5570 if (tdesc_data
!= NULL
)
5571 tdesc_data_cleanup (tdesc_data
);
5572 return arches
->gdbarch
;
5575 /* Need a new architecture. Fill in a target specific vector. */
5576 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5577 gdbarch
= gdbarch_alloc (&info
, tdep
);
5578 tdep
->elf_flags
= elf_flags
;
5579 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5580 tdep
->found_abi
= found_abi
;
5581 tdep
->mips_abi
= mips_abi
;
5582 tdep
->mips_fpu_type
= fpu_type
;
5583 tdep
->register_size_valid_p
= 0;
5584 tdep
->register_size
= 0;
5586 if (info
.target_desc
)
5588 /* Some useful properties can be inferred from the target. */
5589 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5591 tdep
->register_size_valid_p
= 1;
5592 tdep
->register_size
= 4;
5594 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5596 tdep
->register_size_valid_p
= 1;
5597 tdep
->register_size
= 8;
5601 /* Initially set everything according to the default ABI/ISA. */
5602 set_gdbarch_short_bit (gdbarch
, 16);
5603 set_gdbarch_int_bit (gdbarch
, 32);
5604 set_gdbarch_float_bit (gdbarch
, 32);
5605 set_gdbarch_double_bit (gdbarch
, 64);
5606 set_gdbarch_long_double_bit (gdbarch
, 64);
5607 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5608 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5609 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5611 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5612 mips_elf_make_msymbol_special
);
5614 /* Fill in the OS dependant register numbers and names. */
5616 const char **reg_names
;
5617 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5618 struct mips_regnum
);
5619 if (tdesc_has_registers (info
.target_desc
))
5621 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5622 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5623 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5624 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5625 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5626 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5627 regnum
->fp_control_status
= 70;
5628 regnum
->fp_implementation_revision
= 71;
5629 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5632 else if (info
.osabi
== GDB_OSABI_IRIX
)
5637 regnum
->badvaddr
= 66;
5640 regnum
->fp_control_status
= 69;
5641 regnum
->fp_implementation_revision
= 70;
5643 reg_names
= mips_irix_reg_names
;
5647 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5648 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5649 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5650 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5651 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5652 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5653 regnum
->fp_control_status
= 70;
5654 regnum
->fp_implementation_revision
= 71;
5656 if (info
.bfd_arch_info
!= NULL
5657 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5658 reg_names
= mips_tx39_reg_names
;
5660 reg_names
= mips_generic_reg_names
;
5662 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5663 replaced by read_pc? */
5664 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5665 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5666 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5667 set_gdbarch_num_regs (gdbarch
, num_regs
);
5668 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5669 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5670 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
5671 tdep
->mips_processor_reg_names
= reg_names
;
5672 tdep
->regnum
= regnum
;
5678 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5679 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5680 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5681 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5682 tdep
->default_mask_address_p
= 0;
5683 set_gdbarch_long_bit (gdbarch
, 32);
5684 set_gdbarch_ptr_bit (gdbarch
, 32);
5685 set_gdbarch_long_long_bit (gdbarch
, 64);
5688 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5689 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5690 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5691 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5692 tdep
->default_mask_address_p
= 0;
5693 set_gdbarch_long_bit (gdbarch
, 32);
5694 set_gdbarch_ptr_bit (gdbarch
, 32);
5695 set_gdbarch_long_long_bit (gdbarch
, 64);
5697 case MIPS_ABI_EABI32
:
5698 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5699 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5700 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5701 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5702 tdep
->default_mask_address_p
= 0;
5703 set_gdbarch_long_bit (gdbarch
, 32);
5704 set_gdbarch_ptr_bit (gdbarch
, 32);
5705 set_gdbarch_long_long_bit (gdbarch
, 64);
5707 case MIPS_ABI_EABI64
:
5708 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5709 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5710 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5711 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5712 tdep
->default_mask_address_p
= 0;
5713 set_gdbarch_long_bit (gdbarch
, 64);
5714 set_gdbarch_ptr_bit (gdbarch
, 64);
5715 set_gdbarch_long_long_bit (gdbarch
, 64);
5718 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5719 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5720 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5721 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5722 tdep
->default_mask_address_p
= 0;
5723 set_gdbarch_long_bit (gdbarch
, 32);
5724 set_gdbarch_ptr_bit (gdbarch
, 32);
5725 set_gdbarch_long_long_bit (gdbarch
, 64);
5726 set_gdbarch_long_double_bit (gdbarch
, 128);
5727 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5730 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5731 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5732 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5733 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5734 tdep
->default_mask_address_p
= 0;
5735 set_gdbarch_long_bit (gdbarch
, 64);
5736 set_gdbarch_ptr_bit (gdbarch
, 64);
5737 set_gdbarch_long_long_bit (gdbarch
, 64);
5738 set_gdbarch_long_double_bit (gdbarch
, 128);
5739 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5742 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5745 /* GCC creates a pseudo-section whose name specifies the size of
5746 longs, since -mlong32 or -mlong64 may be used independent of
5747 other options. How those options affect pointer sizes is ABI and
5748 architecture dependent, so use them to override the default sizes
5749 set by the ABI. This table shows the relationship between ABI,
5750 -mlongXX, and size of pointers:
5752 ABI -mlongXX ptr bits
5753 --- -------- --------
5767 Note that for o32 and eabi32, pointers are always 32 bits
5768 regardless of any -mlongXX option. For all others, pointers and
5769 longs are the same, as set by -mlongXX or set by defaults.
5772 if (info
.abfd
!= NULL
)
5776 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5779 set_gdbarch_long_bit (gdbarch
, long_bit
);
5783 case MIPS_ABI_EABI32
:
5788 case MIPS_ABI_EABI64
:
5789 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5792 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5797 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5798 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5801 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5802 flag in object files because to do so would make it impossible to
5803 link with libraries compiled without "-gp32". This is
5804 unnecessarily restrictive.
5806 We could solve this problem by adding "-gp32" multilibs to gcc,
5807 but to set this flag before gcc is built with such multilibs will
5808 break too many systems.''
5810 But even more unhelpfully, the default linker output target for
5811 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5812 for 64-bit programs - you need to change the ABI to change this,
5813 and not all gcc targets support that currently. Therefore using
5814 this flag to detect 32-bit mode would do the wrong thing given
5815 the current gcc - it would make GDB treat these 64-bit programs
5816 as 32-bit programs by default. */
5818 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5819 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5821 /* Add/remove bits from an address. The MIPS needs be careful to
5822 ensure that all 32 bit addresses are sign extended to 64 bits. */
5823 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5825 /* Unwind the frame. */
5826 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5827 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5828 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
5830 /* Map debug register numbers onto internal register numbers. */
5831 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5832 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5833 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5834 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5835 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5836 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5838 /* MIPS version of CALL_DUMMY */
5840 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5841 replaced by a command, and all targets will default to on stack
5842 (regardless of the stack's execute status). */
5843 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5844 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5846 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5847 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5848 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5850 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5851 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5853 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5855 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
5857 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5858 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5859 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5861 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5863 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5865 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5867 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5868 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5869 need to all be folded into the target vector. Since they are
5870 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5871 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5873 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5875 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5877 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5879 /* Virtual tables. */
5880 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5882 mips_register_g_packet_guesses (gdbarch
);
5884 /* Hook in OS ABI-specific overrides, if they have been registered. */
5885 info
.tdep_info
= (void *) tdesc_data
;
5886 gdbarch_init_osabi (info
, gdbarch
);
5888 /* Unwind the frame. */
5889 dwarf2_append_unwinders (gdbarch
);
5890 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
5891 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
5892 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
5893 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
5894 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5895 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5896 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5900 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
5901 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
5903 /* Override the normal target description methods to handle our
5904 dual real and pseudo registers. */
5905 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5906 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
5908 num_regs
= gdbarch_num_regs (gdbarch
);
5909 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5910 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
5911 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5914 /* Add ABI-specific aliases for the registers. */
5915 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
5916 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
5917 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
5918 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
5920 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
5921 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
5922 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
5924 /* Add some other standard aliases. */
5925 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
5926 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
5927 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
5933 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5935 struct gdbarch_info info
;
5937 /* Force the architecture to update, and (if it's a MIPS architecture)
5938 mips_gdbarch_init will take care of the rest. */
5939 gdbarch_info_init (&info
);
5940 gdbarch_update_p (info
);
5943 /* Print out which MIPS ABI is in use. */
5946 show_mips_abi (struct ui_file
*file
,
5948 struct cmd_list_element
*ignored_cmd
,
5949 const char *ignored_value
)
5951 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5954 "The MIPS ABI is unknown because the current architecture "
5958 enum mips_abi global_abi
= global_mips_abi ();
5959 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5960 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5962 if (global_abi
== MIPS_ABI_UNKNOWN
)
5965 "The MIPS ABI is set automatically (currently \"%s\").\n",
5967 else if (global_abi
== actual_abi
)
5970 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5974 /* Probably shouldn't happen... */
5977 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5978 actual_abi_str
, mips_abi_strings
[global_abi
]);
5984 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
5986 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5990 int ef_mips_32bitmode
;
5991 /* Determine the ISA. */
5992 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6010 /* Determine the size of a pointer. */
6011 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6012 fprintf_unfiltered (file
,
6013 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6015 fprintf_unfiltered (file
,
6016 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6018 fprintf_unfiltered (file
,
6019 "mips_dump_tdep: ef_mips_arch = %d\n",
6021 fprintf_unfiltered (file
,
6022 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6023 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6024 fprintf_unfiltered (file
,
6025 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6026 mips_mask_address_p (tdep
),
6027 tdep
->default_mask_address_p
);
6029 fprintf_unfiltered (file
,
6030 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6031 MIPS_DEFAULT_FPU_TYPE
,
6032 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6033 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6034 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6036 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6037 MIPS_EABI (gdbarch
));
6038 fprintf_unfiltered (file
,
6039 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6040 MIPS_FPU_TYPE (gdbarch
),
6041 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6042 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6043 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6047 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6050 _initialize_mips_tdep (void)
6052 static struct cmd_list_element
*mipsfpulist
= NULL
;
6053 struct cmd_list_element
*c
;
6055 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6056 if (MIPS_ABI_LAST
+ 1
6057 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6058 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6060 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6062 mips_pdr_data
= register_objfile_data ();
6064 /* Create feature sets with the appropriate properties. The values
6065 are not important. */
6066 mips_tdesc_gp32
= allocate_target_description ();
6067 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6069 mips_tdesc_gp64
= allocate_target_description ();
6070 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6072 /* Add root prefix command for all "set mips"/"show mips" commands */
6073 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6074 _("Various MIPS specific commands."),
6075 &setmipscmdlist
, "set mips ", 0, &setlist
);
6077 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6078 _("Various MIPS specific commands."),
6079 &showmipscmdlist
, "show mips ", 0, &showlist
);
6081 /* Allow the user to override the ABI. */
6082 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6083 &mips_abi_string
, _("\
6084 Set the MIPS ABI used by this program."), _("\
6085 Show the MIPS ABI used by this program."), _("\
6086 This option can be set to one of:\n\
6087 auto - the default ABI associated with the current binary\n\
6096 &setmipscmdlist
, &showmipscmdlist
);
6098 /* Let the user turn off floating point and set the fence post for
6099 heuristic_proc_start. */
6101 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6102 _("Set use of MIPS floating-point coprocessor."),
6103 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6104 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6105 _("Select single-precision MIPS floating-point coprocessor."),
6107 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6108 _("Select double-precision MIPS floating-point coprocessor."),
6110 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6111 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6112 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6113 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6114 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6115 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6116 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6117 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6118 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6119 _("Select MIPS floating-point coprocessor automatically."),
6121 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6122 _("Show current use of MIPS floating-point coprocessor target."),
6125 /* We really would like to have both "0" and "unlimited" work, but
6126 command.c doesn't deal with that. So make it a var_zinteger
6127 because the user can always use "999999" or some such for unlimited. */
6128 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6129 &heuristic_fence_post
, _("\
6130 Set the distance searched for the start of a function."), _("\
6131 Show the distance searched for the start of a function."), _("\
6132 If you are debugging a stripped executable, GDB needs to search through the\n\
6133 program for the start of a function. This command sets the distance of the\n\
6134 search. The only need to set it is when debugging a stripped executable."),
6135 reinit_frame_cache_sfunc
,
6136 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
6137 &setlist
, &showlist
);
6139 /* Allow the user to control whether the upper bits of 64-bit
6140 addresses should be zeroed. */
6141 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6142 &mask_address_var
, _("\
6143 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6144 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6145 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6146 allow GDB to determine the correct value."),
6147 NULL
, show_mask_address
,
6148 &setmipscmdlist
, &showmipscmdlist
);
6150 /* Allow the user to control the size of 32 bit registers within the
6151 raw remote packet. */
6152 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6153 &mips64_transfers_32bit_regs_p
, _("\
6154 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6156 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6158 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6159 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6160 64 bits for others. Use \"off\" to disable compatibility mode"),
6161 set_mips64_transfers_32bit_regs
,
6162 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6163 &setlist
, &showlist
);
6165 /* Debug this files internals. */
6166 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6168 Set mips debugging."), _("\
6169 Show mips debugging."), _("\
6170 When non-zero, mips specific debugging is enabled."),
6172 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
6173 &setdebuglist
, &showdebuglist
);