1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
25 #include "gdb_string.h"
38 #include "opcode/mips.h"
40 struct frame_extra_info
42 mips_extra_func_info_t proc_desc
;
46 /* Some MIPS boards don't support floating point while others only
47 support single-precision floating-point operations. See also
48 FP_REGISTER_DOUBLE. */
52 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
53 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
54 MIPS_FPU_NONE
/* No floating point. */
57 #ifndef MIPS_DEFAULT_FPU_TYPE
58 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
60 static int mips_fpu_type_auto
= 1;
61 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
62 #define MIPS_FPU_TYPE mips_fpu_type
64 #ifndef MIPS_SAVED_REGSIZE
65 #define MIPS_SAVED_REGSIZE MIPS_REGSIZE
68 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
69 #ifndef FP_REGISTER_DOUBLE
70 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
74 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
77 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
80 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
82 static void mips_print_register
PARAMS ((int, int));
84 static mips_extra_func_info_t
85 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
87 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
89 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
91 void mips_set_processor_type_command
PARAMS ((char *, int));
93 int mips_set_processor_type
PARAMS ((char *));
95 static void mips_show_processor_type_command
PARAMS ((char *, int));
97 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
98 struct cmd_list_element
*));
100 static mips_extra_func_info_t
101 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
* next_frame
));
103 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
104 mips_extra_func_info_t proc_desc
));
106 /* This value is the model of MIPS in use. It is derived from the value
107 of the PrID register. */
109 char *mips_processor_type
;
111 char *tmp_mips_processor_type
;
113 /* A set of original names, to be used when restoring back to generic
114 registers from a specific set. */
116 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
117 char **mips_processor_reg_names
= mips_generic_reg_names
;
120 mips_register_name (i
)
123 return mips_processor_reg_names
[i
];
126 /* Names of IDT R3041 registers. */
128 char *mips_r3041_reg_names
[] = {
129 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
130 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
131 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
132 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
133 "sr", "lo", "hi", "bad", "cause","pc",
134 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
135 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
136 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
137 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
138 "fsr", "fir", "fp", "",
139 "", "", "bus", "ccfg", "", "", "", "",
140 "", "", "port", "cmp", "", "", "epc", "prid",
143 /* Names of IDT R3051 registers. */
145 char *mips_r3051_reg_names
[] = {
146 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
147 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
148 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
149 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
150 "sr", "lo", "hi", "bad", "cause","pc",
151 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
152 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
153 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
154 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
155 "fsr", "fir", "fp", "",
156 "inx", "rand", "elo", "", "ctxt", "", "", "",
157 "", "", "ehi", "", "", "", "epc", "prid",
160 /* Names of IDT R3081 registers. */
162 char *mips_r3081_reg_names
[] = {
163 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
164 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
165 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
166 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
167 "sr", "lo", "hi", "bad", "cause","pc",
168 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
169 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
170 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
171 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
172 "fsr", "fir", "fp", "",
173 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
174 "", "", "ehi", "", "", "", "epc", "prid",
177 /* Names of LSI 33k registers. */
179 char *mips_lsi33k_reg_names
[] = {
180 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
181 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
182 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
183 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
184 "epc", "hi", "lo", "sr", "cause","badvaddr",
185 "dcic", "bpc", "bda", "", "", "", "", "",
186 "", "", "", "", "", "", "", "",
187 "", "", "", "", "", "", "", "",
188 "", "", "", "", "", "", "", "",
190 "", "", "", "", "", "", "", "",
191 "", "", "", "", "", "", "", "",
197 } mips_processor_type_table
[] = {
198 { "generic", mips_generic_reg_names
},
199 { "r3041", mips_r3041_reg_names
},
200 { "r3051", mips_r3051_reg_names
},
201 { "r3071", mips_r3081_reg_names
},
202 { "r3081", mips_r3081_reg_names
},
203 { "lsi33k", mips_lsi33k_reg_names
},
211 /* Table to translate MIPS16 register field to actual register number. */
212 static int mips16_to_32_reg
[8] =
213 {16, 17, 2, 3, 4, 5, 6, 7};
215 /* Heuristic_proc_start may hunt through the text section for a long
216 time across a 2400 baud serial line. Allows the user to limit this
219 static unsigned int heuristic_fence_post
= 0;
221 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
222 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
223 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
224 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
225 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
226 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
227 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
228 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
229 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
230 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
231 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
232 #define _PROC_MAGIC_ 0x0F0F0F0F
233 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
234 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
236 struct linked_proc_info
238 struct mips_extra_func_info info
;
239 struct linked_proc_info
*next
;
241 *linked_proc_desc_table
= NULL
;
244 mips_print_extra_frame_info (fi
)
245 struct frame_info
*fi
;
249 && fi
->extra_info
->proc_desc
250 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
251 printf_filtered (" frame pointer is at %s+%d\n",
252 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
253 fi
->extra_info
->proc_desc
->pdr
.frameoffset
);
256 /* Convert between RAW and VIRTUAL registers. The RAW register size
257 defines the remote-gdb packet. */
259 static int mips64_transfers_32bit_regs_p
= 0;
262 mips_register_raw_size (reg_nr
)
265 if (mips64_transfers_32bit_regs_p
)
266 return REGISTER_VIRTUAL_SIZE (reg_nr
);
272 mips_register_convertible (reg_nr
)
275 if (mips64_transfers_32bit_regs_p
)
278 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
282 mips_register_convert_to_virtual (n
, virtual_type
, raw_buf
, virt_buf
)
284 struct type
*virtual_type
;
288 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
290 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
291 TYPE_LENGTH (virtual_type
));
295 TYPE_LENGTH (virtual_type
));
299 mips_register_convert_to_raw (virtual_type
, n
, virt_buf
, raw_buf
)
300 struct type
*virtual_type
;
305 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
306 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
307 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
309 TYPE_LENGTH (virtual_type
));
313 TYPE_LENGTH (virtual_type
));
316 /* Should the upper word of 64-bit addresses be zeroed? */
317 static int mask_address_p
= 1;
319 /* Should call_function allocate stack space for a struct return? */
321 mips_use_struct_convention (gcc_p
, type
)
326 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
328 return 1; /* Structures are returned by ref in extra arg0 */
331 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
334 pc_is_mips16 (bfd_vma memaddr
)
336 struct minimal_symbol
*sym
;
338 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
339 if (IS_MIPS16_ADDR (memaddr
))
342 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
343 the high bit of the info field. Use this to decide if the function is
344 MIPS16 or normal MIPS. */
345 sym
= lookup_minimal_symbol_by_pc (memaddr
);
347 return MSYMBOL_IS_SPECIAL (sym
);
353 /* This returns the PC of the first inst after the prologue. If we can't
354 find the prologue, then return 0. */
357 after_prologue (pc
, proc_desc
)
359 mips_extra_func_info_t proc_desc
;
361 struct symtab_and_line sal
;
362 CORE_ADDR func_addr
, func_end
;
365 proc_desc
= find_proc_desc (pc
, NULL
);
369 /* If function is frameless, then we need to do it the hard way. I
370 strongly suspect that frameless always means prologueless... */
371 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
372 && PROC_FRAME_OFFSET (proc_desc
) == 0)
376 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
377 return 0; /* Unknown */
379 sal
= find_pc_line (func_addr
, 0);
381 if (sal
.end
< func_end
)
384 /* The line after the prologue is after the end of the function. In this
385 case, tell the caller to find the prologue the hard way. */
390 /* Decode a MIPS32 instruction that saves a register in the stack, and
391 set the appropriate bit in the general register mask or float register mask
392 to indicate which register is saved. This is a helper function
393 for mips_find_saved_regs. */
396 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
398 unsigned long *gen_mask
;
399 unsigned long *float_mask
;
403 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
404 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
405 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
407 /* It might be possible to use the instruction to
408 find the offset, rather than the code below which
409 is based on things being in a certain order in the
410 frame, but figuring out what the instruction's offset
411 is relative to might be a little tricky. */
412 reg
= (inst
& 0x001f0000) >> 16;
413 *gen_mask
|= (1 << reg
);
415 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
416 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
417 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
420 reg
= ((inst
& 0x001f0000) >> 16);
421 *float_mask
|= (1 << reg
);
425 /* Decode a MIPS16 instruction that saves a register in the stack, and
426 set the appropriate bit in the general register or float register mask
427 to indicate which register is saved. This is a helper function
428 for mips_find_saved_regs. */
431 mips16_decode_reg_save (inst
, gen_mask
)
433 unsigned long *gen_mask
;
435 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
437 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
438 *gen_mask
|= (1 << reg
);
440 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
442 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
443 *gen_mask
|= (1 << reg
);
445 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
446 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
447 *gen_mask
|= (1 << RA_REGNUM
);
451 /* Fetch and return instruction from the specified location. If the PC
452 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
455 mips_fetch_instruction (addr
)
458 char buf
[MIPS_INSTLEN
];
462 if (pc_is_mips16 (addr
))
464 instlen
= MIPS16_INSTLEN
;
465 addr
= UNMAKE_MIPS16_ADDR (addr
);
468 instlen
= MIPS_INSTLEN
;
469 status
= read_memory_nobpt (addr
, buf
, instlen
);
471 memory_error (status
, addr
);
472 return extract_unsigned_integer (buf
, instlen
);
476 /* These the fields of 32 bit mips instructions */
477 #define mips32_op(x) (x >> 25)
478 #define itype_op(x) (x >> 25)
479 #define itype_rs(x) ((x >> 21)& 0x1f)
480 #define itype_rt(x) ((x >> 16) & 0x1f)
481 #define itype_immediate(x) ( x & 0xffff)
483 #define jtype_op(x) (x >> 25)
484 #define jtype_target(x) ( x & 0x03fffff)
486 #define rtype_op(x) (x >>25)
487 #define rtype_rs(x) ((x>>21) & 0x1f)
488 #define rtype_rt(x) ((x>>16) & 0x1f)
489 #define rtype_rd(x) ((x>>11) & 0x1f)
490 #define rtype_shamt(x) ((x>>6) & 0x1f)
491 #define rtype_funct(x) (x & 0x3f )
494 mips32_relative_offset (unsigned long inst
)
497 x
= itype_immediate (inst
);
498 if (x
& 0x8000) /* sign bit set */
500 x
|= 0xffff0000; /* sign extension */
506 /* Determine whate to set a single step breakpoint while considering
509 mips32_next_pc (CORE_ADDR pc
)
513 inst
= mips_fetch_instruction (pc
);
514 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
516 if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
518 op
= ((inst
>> 25) & 0x03);
522 goto equal_branch
; /* BEQL */
524 goto neq_branch
; /* BNEZ */
526 goto less_branch
; /* BLEZ */
528 goto greater_branch
; /* BGTZ */
534 pc
+= 4; /* Not a branch, next instruction is easy */
537 { /* This gets way messy */
539 /* Further subdivide into SPECIAL, REGIMM and other */
540 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
542 case 0: /* SPECIAL */
543 op
= rtype_funct (inst
);
548 pc
= read_register (rtype_rs (inst
)); /* Set PC to that address */
554 break; /* end special */
557 op
= jtype_op (inst
); /* branch condition */
558 switch (jtype_op (inst
))
562 case 16: /* BLTZALL */
563 case 18: /* BLTZALL */
565 if (read_register (itype_rs (inst
)) < 0)
566 pc
+= mips32_relative_offset (inst
) + 4;
568 pc
+= 8; /* after the delay slot */
572 case 17: /* BGEZAL */
573 case 19: /* BGEZALL */
574 greater_equal_branch
:
575 if (read_register (itype_rs (inst
)) >= 0)
576 pc
+= mips32_relative_offset (inst
) + 4;
578 pc
+= 8; /* after the delay slot */
580 /* All of the other intructions in the REGIMM catagory */
585 break; /* end REGIMM */
590 reg
= jtype_target (inst
) << 2;
591 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
592 /* Whats this mysterious 0xf000000 adjustment ??? */
595 /* FIXME case JALX : */
598 reg
= jtype_target (inst
) << 2;
599 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
600 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
602 break; /* The new PC will be alternate mode */
603 case 4: /* BEQ , BEQL */
605 if (read_register (itype_rs (inst
)) ==
606 read_register (itype_rt (inst
)))
607 pc
+= mips32_relative_offset (inst
) + 4;
611 case 5: /* BNE , BNEL */
613 if (read_register (itype_rs (inst
)) !=
614 read_register (itype_rs (inst
)))
615 pc
+= mips32_relative_offset (inst
) + 4;
619 case 6: /* BLEZ , BLEZL */
621 if (read_register (itype_rs (inst
) <= 0))
622 pc
+= mips32_relative_offset (inst
) + 4;
627 greater_branch
: /* BGTZ BGTZL */
628 if (read_register (itype_rs (inst
) > 0))
629 pc
+= mips32_relative_offset (inst
) + 4;
638 } /* mips32_next_pc */
640 /* Decoding the next place to set a breakpoint is irregular for the
641 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
642 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
643 We dont want to set a single step instruction on the extend instruction
647 /* Lots of mips16 instruction formats */
648 /* Predicting jumps requires itype,ritype,i8type
649 and their extensions extItype,extritype,extI8type
651 enum mips16_inst_fmts
653 itype
, /* 0 immediate 5,10 */
654 ritype
, /* 1 5,3,8 */
655 rrtype
, /* 2 5,3,3,5 */
656 rritype
, /* 3 5,3,3,5 */
657 rrrtype
, /* 4 5,3,3,3,2 */
658 rriatype
, /* 5 5,3,3,1,4 */
659 shifttype
, /* 6 5,3,3,3,2 */
660 i8type
, /* 7 5,3,8 */
661 i8movtype
, /* 8 5,3,3,5 */
662 i8mov32rtype
, /* 9 5,3,5,3 */
663 i64type
, /* 10 5,3,8 */
664 ri64type
, /* 11 5,3,3,5 */
665 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
666 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
667 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
668 extRRItype
, /* 15 5,5,5,5,3,3,5 */
669 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
670 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
671 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
672 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
673 extRi64type
, /* 20 5,6,5,5,3,3,5 */
674 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
676 /* I am heaping all the fields of the formats into one structure and then,
677 only the fields which are involved in instruction extension */
681 enum mips16_inst_fmts fmt
;
682 unsigned long offset
;
683 unsigned int regx
; /* Function in i8 type */
690 print_unpack (char *comment
,
691 struct upk_mips16
*u
)
693 printf ("%s %04x ,f(%d) off(%08x) (x(%x) y(%x)\n",
694 comment
, u
->inst
, u
->fmt
, u
->offset
, u
->regx
, u
->regy
);
697 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
698 format for the bits which make up the immediatate extension.
701 extended_offset (unsigned long extension
)
704 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
706 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
708 value
|= extension
& 0x01f; /* extract 4:0 */
712 /* Only call this function if you know that this is an extendable
713 instruction, It wont malfunction, but why make excess remote memory references?
714 If the immediate operands get sign extended or somthing, do it after
715 the extension is performed.
717 /* FIXME: Every one of these cases needs to worry about sign extension
718 when the offset is to be used in relative addressing */
721 static unsigned short
722 fetch_mips_16 (CORE_ADDR pc
)
725 pc
&= 0xfffffffe; /* clear the low order bit */
726 target_read_memory (pc
, buf
, 2);
727 return extract_unsigned_integer (buf
, 2);
731 unpack_mips16 (CORE_ADDR pc
,
732 struct upk_mips16
*upk
)
735 unsigned long extension
;
737 extpc
= (pc
- 4) & ~0x01; /* Extensions are 32 bit instructions */
738 /* Decrement to previous address and loose the 16bit mode flag */
739 /* return if the instruction was extendable, but not actually extended */
740 extended
= ((mips32_op (extension
) == 30) ? 1 : 0);
743 extension
= mips_fetch_instruction (extpc
);
752 value
= extended_offset (extension
);
753 value
= value
<< 11; /* rom for the original value */
754 value
|= upk
->inst
& 0x7ff; /* eleven bits from instruction */
758 value
= upk
->inst
& 0x7ff;
759 /* FIXME : Consider sign extension */
766 { /* A register identifier and an offset */
767 /* Most of the fields are the same as I type but the
768 immediate value is of a different length */
772 value
= extended_offset (extension
);
773 value
= value
<< 8; /* from the original instruction */
774 value
|= upk
->inst
& 0xff; /* eleven bits from instruction */
775 upk
->regx
= (extension
>> 8) & 0x07; /* or i8 funct */
776 if (value
& 0x4000) /* test the sign bit , bit 26 */
778 value
&= ~0x3fff; /* remove the sign bit */
784 value
= upk
->inst
& 0xff; /* 8 bits */
785 upk
->regx
= (upk
->inst
>> 8) & 0x07; /* or i8 funct */
786 /* FIXME: Do sign extension , this format needs it */
787 if (value
& 0x80) /* THIS CONFUSES ME */
789 value
&= 0xef; /* remove the sign bit */
800 unsigned short nexthalf
;
801 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f);
803 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
809 printf_filtered ("Decoding unimplemented instruction format type\n");
812 /* print_unpack("UPK",upk) ; */
816 #define mips16_op(x) (x >> 11)
818 /* This is a map of the opcodes which ae known to perform branches */
819 static unsigned char map16
[32] =
820 {0, 0, 1, 1, 1, 1, 0, 0,
821 0, 0, 0, 0, 1, 0, 0, 0,
822 0, 0, 0, 0, 0, 0, 0, 0,
823 0, 0, 0, 0, 0, 1, 1, 0
827 add_offset_16 (CORE_ADDR pc
, int offset
)
829 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
835 static struct upk_mips16 upk
;
838 mips16_next_pc (CORE_ADDR pc
)
842 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
843 inst
= fetch_mips_16 (pc
);
845 op
= mips16_op (upk
.inst
);
853 unpack_mips16 (pc
, &upk
);
862 pc
+= (offset
<< 1) + 2;
865 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
867 unpack_mips16 (pc
, &upk
);
868 pc
= add_offset_16 (pc
, upk
.offset
);
869 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
870 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
876 unpack_mips16 (pc
, &upk
);
877 reg
= read_register (upk
.regx
);
879 pc
+= (upk
.offset
<< 1) + 2;
885 unpack_mips16 (pc
, &upk
);
886 reg
= read_register (upk
.regx
);
888 pc
+= (upk
.offset
<< 1) + 2;
892 case 12: /* I8 Formats btez btnez */
894 unpack_mips16 (pc
, &upk
);
895 /* upk.regx contains the opcode */
896 reg
= read_register (24); /* Test register is 24 */
897 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
898 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
899 /* pc = add_offset_16(pc,upk.offset) ; */
900 pc
+= (upk
.offset
<< 1) + 2;
904 case 29: /* RR Formats JR, JALR, JALR-RA */
906 op
= upk
.inst
& 0x1f;
909 upk
.regx
= (upk
.inst
>> 8) & 0x07;
910 upk
.regy
= (upk
.inst
>> 5) & 0x07;
918 break; /* Function return instruction */
924 break; /* BOGUS Guess */
926 pc
= read_register (reg
);
931 case 30: /* This is an extend instruction */
932 pc
+= 4; /* Dont be setting breakpints on the second half */
935 printf ("Filtered - next PC probably incorrrect due to jump inst\n");
941 pc
+= 2; /* just a good old instruction */
942 /* See if we CAN actually break on the next instruction */
943 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
945 } /* mips16_next_pc */
947 /* The mips_next_pc function supports single_tep when the remote target monitor or
948 stub is not developed enough to so a single_step.
949 It works by decoding the current instruction and predicting where a branch
950 will go. This isnt hard because all the data is available.
951 The MIPS32 and MIPS16 variants are quite different
954 mips_next_pc (CORE_ADDR pc
)
957 /* inst = mips_fetch_instruction(pc) ; */
958 /* if (pc_is_mips16) <----- This is failing */
960 return mips16_next_pc (pc
);
962 return mips32_next_pc (pc
);
965 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
969 mips_find_saved_regs (fci
)
970 struct frame_info
*fci
;
973 CORE_ADDR reg_position
;
974 /* r0 bit means kernel trap */
976 /* What registers have been saved? Bitmasks. */
977 unsigned long gen_mask
, float_mask
;
978 mips_extra_func_info_t proc_desc
;
981 frame_saved_regs_zalloc (fci
);
983 /* If it is the frame for sigtramp, the saved registers are located
984 in a sigcontext structure somewhere on the stack.
985 If the stack layout for sigtramp changes we might have to change these
986 constants and the companion fixup_sigtramp in mdebugread.c */
987 #ifndef SIGFRAME_BASE
988 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
989 above the sigtramp frame. */
990 #define SIGFRAME_BASE MIPS_REGSIZE
991 /* FIXME! Are these correct?? */
992 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
993 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
994 #define SIGFRAME_FPREGSAVE_OFF \
995 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
997 #ifndef SIGFRAME_REG_SIZE
998 /* FIXME! Is this correct?? */
999 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1001 if (fci
->signal_handler_caller
)
1003 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1005 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1006 + ireg
* SIGFRAME_REG_SIZE
;
1007 fci
->saved_regs
[ireg
] = reg_position
;
1009 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1011 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1012 + ireg
* SIGFRAME_REG_SIZE
;
1013 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1015 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1019 proc_desc
= fci
->extra_info
->proc_desc
;
1020 if (proc_desc
== NULL
)
1021 /* I'm not sure how/whether this can happen. Normally when we can't
1022 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1023 and set the saved_regs right away. */
1026 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1027 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1028 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1030 if ( /* In any frame other than the innermost or a frame interrupted by
1031 a signal, we assume that all registers have been saved.
1032 This assumes that all register saves in a function happen before
1033 the first function call. */
1034 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1036 /* In a dummy frame we know exactly where things are saved. */
1037 && !PROC_DESC_IS_DUMMY (proc_desc
)
1039 /* Don't bother unless we are inside a function prologue. Outside the
1040 prologue, we know where everything is. */
1042 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1044 /* Not sure exactly what kernel_trap means, but if it means
1045 the kernel saves the registers without a prologue doing it,
1046 we better not examine the prologue to see whether registers
1047 have been saved yet. */
1050 /* We need to figure out whether the registers that the proc_desc
1051 claims are saved have been saved yet. */
1055 /* Bitmasks; set if we have found a save for the register. */
1056 unsigned long gen_save_found
= 0;
1057 unsigned long float_save_found
= 0;
1060 /* If the address is odd, assume this is MIPS16 code. */
1061 addr
= PROC_LOW_ADDR (proc_desc
);
1062 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1064 /* Scan through this function's instructions preceding the current
1065 PC, and look for those that save registers. */
1066 while (addr
< fci
->pc
)
1068 inst
= mips_fetch_instruction (addr
);
1069 if (pc_is_mips16 (addr
))
1070 mips16_decode_reg_save (inst
, &gen_save_found
);
1072 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1075 gen_mask
= gen_save_found
;
1076 float_mask
= float_save_found
;
1079 /* Fill in the offsets for the registers which gen_mask says
1081 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1082 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1083 if (gen_mask
& 0x80000000)
1085 fci
->saved_regs
[ireg
] = reg_position
;
1086 reg_position
-= MIPS_SAVED_REGSIZE
;
1089 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1090 of that normally used by gcc. Therefore, we have to fetch the first
1091 instruction of the function, and if it's an entry instruction that
1092 saves $s0 or $s1, correct their saved addresses. */
1093 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1095 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1096 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1099 int sreg_count
= (inst
>> 6) & 3;
1101 /* Check if the ra register was pushed on the stack. */
1102 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1104 reg_position
-= MIPS_SAVED_REGSIZE
;
1106 /* Check if the s0 and s1 registers were pushed on the stack. */
1107 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1109 fci
->saved_regs
[reg
] = reg_position
;
1110 reg_position
-= MIPS_SAVED_REGSIZE
;
1115 /* Fill in the offsets for the registers which float_mask says
1117 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1119 /* The freg_offset points to where the first *double* register
1120 is saved. So skip to the high-order word. */
1121 if (!GDB_TARGET_IS_MIPS64
)
1122 reg_position
+= MIPS_SAVED_REGSIZE
;
1124 /* Fill in the offsets for the float registers which float_mask says
1126 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1127 if (float_mask
& 0x80000000)
1129 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1130 reg_position
-= MIPS_SAVED_REGSIZE
;
1133 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1137 read_next_frame_reg (fi
, regno
)
1138 struct frame_info
*fi
;
1141 for (; fi
; fi
= fi
->next
)
1143 /* We have to get the saved sp from the sigcontext
1144 if it is a signal handler frame. */
1145 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1149 if (fi
->saved_regs
== NULL
)
1150 mips_find_saved_regs (fi
);
1151 if (fi
->saved_regs
[regno
])
1152 return read_memory_integer (fi
->saved_regs
[regno
], MIPS_SAVED_REGSIZE
);
1155 return read_register (regno
);
1158 /* mips_addr_bits_remove - remove useless address bits */
1161 mips_addr_bits_remove (addr
)
1164 #if GDB_TARGET_IS_MIPS64
1165 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1167 /* This hack is a work-around for existing boards using PMON,
1168 the simulator, and any other 64-bit targets that doesn't have
1169 true 64-bit addressing. On these targets, the upper 32 bits
1170 of addresses are ignored by the hardware. Thus, the PC or SP
1171 are likely to have been sign extended to all 1s by instruction
1172 sequences that load 32-bit addresses. For example, a typical
1173 piece of code that loads an address is this:
1174 lui $r2, <upper 16 bits>
1175 ori $r2, <lower 16 bits>
1176 But the lui sign-extends the value such that the upper 32 bits
1177 may be all 1s. The workaround is simply to mask off these bits.
1178 In the future, gcc may be changed to support true 64-bit
1179 addressing, and this masking will have to be disabled. */
1180 addr
&= (CORE_ADDR
) 0xffffffff;
1183 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1184 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1185 So we still have to mask off useless bits from addresses. */
1186 addr
&= (CORE_ADDR
) 0xffffffff;
1193 mips_init_frame_pc_first (fromleaf
, prev
)
1195 struct frame_info
*prev
;
1199 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1200 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1201 tmp
= mips_skip_stub (pc
);
1202 prev
->pc
= tmp
? tmp
: pc
;
1207 mips_frame_saved_pc (frame
)
1208 struct frame_info
*frame
;
1211 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1212 /* We have to get the saved pc from the sigcontext
1213 if it is a signal handler frame. */
1214 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1215 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1217 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1218 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1220 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1222 return ADDR_BITS_REMOVE (saved_pc
);
1225 static struct mips_extra_func_info temp_proc_desc
;
1226 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1228 /* Set a register's saved stack address in temp_saved_regs. If an address
1229 has already been set for this register, do nothing; this way we will
1230 only recognize the first save of a given register in a function prologue.
1231 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1234 set_reg_offset (regno
, offset
)
1238 if (temp_saved_regs
[regno
] == 0)
1239 temp_saved_regs
[regno
] = offset
;
1243 /* Test whether the PC points to the return instruction at the
1244 end of a function. */
1247 mips_about_to_return (pc
)
1250 if (pc_is_mips16 (pc
))
1251 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1252 generates a "jr $ra"; other times it generates code to load
1253 the return address from the stack to an accessible register (such
1254 as $a3), then a "jr" using that register. This second case
1255 is almost impossible to distinguish from an indirect jump
1256 used for switch statements, so we don't even try. */
1257 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1259 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1263 /* This fencepost looks highly suspicious to me. Removing it also
1264 seems suspicious as it could affect remote debugging across serial
1268 heuristic_proc_start (pc
)
1276 pc
= ADDR_BITS_REMOVE (pc
);
1278 fence
= start_pc
- heuristic_fence_post
;
1282 if (heuristic_fence_post
== UINT_MAX
1283 || fence
< VM_MIN_ADDRESS
)
1284 fence
= VM_MIN_ADDRESS
;
1286 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1288 /* search back for previous return */
1289 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1290 if (start_pc
< fence
)
1292 /* It's not clear to me why we reach this point when
1293 stop_soon_quietly, but with this test, at least we
1294 don't print out warnings for every child forked (eg, on
1295 decstation). 22apr93 rich@cygnus.com. */
1296 if (!stop_soon_quietly
)
1298 static int blurb_printed
= 0;
1300 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1305 /* This actually happens frequently in embedded
1306 development, when you first connect to a board
1307 and your stack pointer and pc are nowhere in
1308 particular. This message needs to give people
1309 in that situation enough information to
1310 determine that it's no big deal. */
1311 printf_filtered ("\n\
1312 GDB is unable to find the start of the function at 0x%s\n\
1313 and thus can't determine the size of that function's stack frame.\n\
1314 This means that GDB may be unable to access that stack frame, or\n\
1315 the frames below it.\n\
1316 This problem is most likely caused by an invalid program counter or\n\
1318 However, if you think GDB should simply search farther back\n\
1319 from 0x%s for code which looks like the beginning of a\n\
1320 function, you can increase the range of the search using the `set\n\
1321 heuristic-fence-post' command.\n",
1322 paddr_nz (pc
), paddr_nz (pc
));
1329 else if (pc_is_mips16 (start_pc
))
1331 unsigned short inst
;
1333 /* On MIPS16, any one of the following is likely to be the
1334 start of a function:
1338 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1339 inst
= mips_fetch_instruction (start_pc
);
1340 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1341 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1342 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1343 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1345 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1346 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1351 else if (mips_about_to_return (start_pc
))
1353 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1358 /* skip nops (usually 1) 0 - is this */
1359 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1360 start_pc
+= MIPS_INSTLEN
;
1365 /* Fetch the immediate value from a MIPS16 instruction.
1366 If the previous instruction was an EXTEND, use it to extend
1367 the upper bits of the immediate value. This is a helper function
1368 for mips16_heuristic_proc_desc. */
1371 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1372 unsigned short prev_inst
; /* previous instruction */
1373 unsigned short inst
; /* current instruction */
1374 int nbits
; /* number of bits in imm field */
1375 int scale
; /* scale factor to be applied to imm */
1376 int is_signed
; /* is the imm field signed? */
1380 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1382 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1383 if (offset
& 0x8000) /* check for negative extend */
1384 offset
= 0 - (0x10000 - (offset
& 0xffff));
1385 return offset
| (inst
& 0x1f);
1389 int max_imm
= 1 << nbits
;
1390 int mask
= max_imm
- 1;
1391 int sign_bit
= max_imm
>> 1;
1393 offset
= inst
& mask
;
1394 if (is_signed
&& (offset
& sign_bit
))
1395 offset
= 0 - (max_imm
- offset
);
1396 return offset
* scale
;
1401 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1402 stream from start_pc to limit_pc. */
1405 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1406 CORE_ADDR start_pc
, limit_pc
;
1407 struct frame_info
*next_frame
;
1411 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1412 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1413 unsigned inst
= 0; /* current instruction */
1414 unsigned entry_inst
= 0; /* the entry instruction */
1417 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1418 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1420 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1422 /* Save the previous instruction. If it's an EXTEND, we'll extract
1423 the immediate offset extension from it in mips16_get_imm. */
1426 /* Fetch and decode the instruction. */
1427 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1428 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1429 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1431 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1432 if (offset
< 0) /* negative stack adjustment? */
1433 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1435 /* Exit loop if a positive stack adjustment is found, which
1436 usually means that the stack cleanup code in the function
1437 epilogue is reached. */
1440 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1442 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1443 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1444 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1445 set_reg_offset (reg
, sp
+ offset
);
1447 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1449 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1450 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1451 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1452 set_reg_offset (reg
, sp
+ offset
);
1454 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1456 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1457 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1458 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1460 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1462 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1463 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1464 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1466 else if (inst
== 0x673d) /* move $s1, $sp */
1469 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1471 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1473 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1474 frame_addr
= sp
+ offset
;
1475 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1476 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1478 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1480 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1481 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1482 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1483 set_reg_offset (reg
, frame_addr
+ offset
);
1485 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1487 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1488 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1489 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1490 set_reg_offset (reg
, frame_addr
+ offset
);
1492 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1493 entry_inst
= inst
; /* save for later processing */
1494 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1495 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1498 /* The entry instruction is typically the first instruction in a function,
1499 and it stores registers at offsets relative to the value of the old SP
1500 (before the prologue). But the value of the sp parameter to this
1501 function is the new SP (after the prologue has been executed). So we
1502 can't calculate those offsets until we've seen the entire prologue,
1503 and can calculate what the old SP must have been. */
1504 if (entry_inst
!= 0)
1506 int areg_count
= (entry_inst
>> 8) & 7;
1507 int sreg_count
= (entry_inst
>> 6) & 3;
1509 /* The entry instruction always subtracts 32 from the SP. */
1510 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1512 /* Now we can calculate what the SP must have been at the
1513 start of the function prologue. */
1514 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1516 /* Check if a0-a3 were saved in the caller's argument save area. */
1517 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1519 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1520 set_reg_offset (reg
, sp
+ offset
);
1521 offset
+= MIPS_SAVED_REGSIZE
;
1524 /* Check if the ra register was pushed on the stack. */
1526 if (entry_inst
& 0x20)
1528 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1529 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1530 offset
-= MIPS_SAVED_REGSIZE
;
1533 /* Check if the s0 and s1 registers were pushed on the stack. */
1534 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1536 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1537 set_reg_offset (reg
, sp
+ offset
);
1538 offset
-= MIPS_SAVED_REGSIZE
;
1544 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1545 CORE_ADDR start_pc
, limit_pc
;
1546 struct frame_info
*next_frame
;
1550 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1552 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1553 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1554 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1555 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1557 unsigned long inst
, high_word
, low_word
;
1560 /* Fetch the instruction. */
1561 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1563 /* Save some code by pre-extracting some useful fields. */
1564 high_word
= (inst
>> 16) & 0xffff;
1565 low_word
= inst
& 0xffff;
1566 reg
= high_word
& 0x1f;
1568 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1569 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1570 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1572 if (low_word
& 0x8000) /* negative stack adjustment? */
1573 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1575 /* Exit loop if a positive stack adjustment is found, which
1576 usually means that the stack cleanup code in the function
1577 epilogue is reached. */
1580 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1582 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1583 set_reg_offset (reg
, sp
+ low_word
);
1585 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1587 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1588 but the register size used is only 32 bits. Make the address
1589 for the saved register point to the lower 32 bits. */
1590 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1591 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1593 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1595 /* Old gcc frame, r30 is virtual frame pointer. */
1596 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1597 frame_addr
= sp
+ low_word
;
1598 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1600 unsigned alloca_adjust
;
1601 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1602 frame_addr
= read_next_frame_reg (next_frame
, 30);
1603 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1604 if (alloca_adjust
> 0)
1606 /* FP > SP + frame_size. This may be because
1607 * of an alloca or somethings similar.
1608 * Fix sp to "pre-alloca" value, and try again.
1610 sp
+= alloca_adjust
;
1615 /* move $30,$sp. With different versions of gas this will be either
1616 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1617 Accept any one of these. */
1618 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1620 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1621 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1623 unsigned alloca_adjust
;
1624 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1625 frame_addr
= read_next_frame_reg (next_frame
, 30);
1626 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1627 if (alloca_adjust
> 0)
1629 /* FP > SP + frame_size. This may be because
1630 * of an alloca or somethings similar.
1631 * Fix sp to "pre-alloca" value, and try again.
1633 sp
+= alloca_adjust
;
1638 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1640 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1641 set_reg_offset (reg
, frame_addr
+ low_word
);
1646 static mips_extra_func_info_t
1647 heuristic_proc_desc (start_pc
, limit_pc
, next_frame
)
1648 CORE_ADDR start_pc
, limit_pc
;
1649 struct frame_info
*next_frame
;
1651 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1655 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1656 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1657 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1658 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1659 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1661 if (start_pc
+ 200 < limit_pc
)
1662 limit_pc
= start_pc
+ 200;
1663 if (pc_is_mips16 (start_pc
))
1664 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1666 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1667 return &temp_proc_desc
;
1670 static mips_extra_func_info_t
1671 non_heuristic_proc_desc (pc
, addrptr
)
1675 CORE_ADDR startaddr
;
1676 mips_extra_func_info_t proc_desc
;
1677 struct block
*b
= block_for_pc (pc
);
1680 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1682 *addrptr
= startaddr
;
1683 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1687 if (startaddr
> BLOCK_START (b
))
1688 /* This is the "pathological" case referred to in a comment in
1689 print_frame_info. It might be better to move this check into
1693 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1696 /* If we never found a PDR for this function in symbol reading, then
1697 examine prologues to find the information. */
1700 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1701 if (PROC_FRAME_REG (proc_desc
) == -1)
1711 static mips_extra_func_info_t
1712 find_proc_desc (pc
, next_frame
)
1714 struct frame_info
*next_frame
;
1716 mips_extra_func_info_t proc_desc
;
1717 CORE_ADDR startaddr
;
1719 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1723 /* IF this is the topmost frame AND
1724 * (this proc does not have debugging information OR
1725 * the PC is in the procedure prologue)
1726 * THEN create a "heuristic" proc_desc (by analyzing
1727 * the actual code) to replace the "official" proc_desc.
1729 if (next_frame
== NULL
)
1731 struct symtab_and_line val
;
1732 struct symbol
*proc_symbol
=
1733 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1737 val
= find_pc_line (BLOCK_START
1738 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1740 val
.pc
= val
.end
? val
.end
: pc
;
1742 if (!proc_symbol
|| pc
< val
.pc
)
1744 mips_extra_func_info_t found_heuristic
=
1745 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1747 if (found_heuristic
)
1748 proc_desc
= found_heuristic
;
1754 /* Is linked_proc_desc_table really necessary? It only seems to be used
1755 by procedure call dummys. However, the procedures being called ought
1756 to have their own proc_descs, and even if they don't,
1757 heuristic_proc_desc knows how to create them! */
1759 register struct linked_proc_info
*link
;
1761 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1762 if (PROC_LOW_ADDR (&link
->info
) <= pc
1763 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1767 startaddr
= heuristic_proc_start (pc
);
1770 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1776 get_frame_pointer (frame
, proc_desc
)
1777 struct frame_info
*frame
;
1778 mips_extra_func_info_t proc_desc
;
1780 return ADDR_BITS_REMOVE (
1781 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1782 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1785 mips_extra_func_info_t cached_proc_desc
;
1788 mips_frame_chain (frame
)
1789 struct frame_info
*frame
;
1791 mips_extra_func_info_t proc_desc
;
1793 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
1795 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1798 /* Check if the PC is inside a call stub. If it is, fetch the
1799 PC of the caller of that stub. */
1800 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1803 /* Look up the procedure descriptor for this PC. */
1804 proc_desc
= find_proc_desc (saved_pc
, frame
);
1808 cached_proc_desc
= proc_desc
;
1810 /* If no frame pointer and frame size is zero, we must be at end
1811 of stack (or otherwise hosed). If we don't check frame size,
1812 we loop forever if we see a zero size frame. */
1813 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1814 && PROC_FRAME_OFFSET (proc_desc
) == 0
1815 /* The previous frame from a sigtramp frame might be frameless
1816 and have frame size zero. */
1817 && !frame
->signal_handler_caller
)
1820 return get_frame_pointer (frame
, proc_desc
);
1824 mips_init_extra_frame_info (fromleaf
, fci
)
1826 struct frame_info
*fci
;
1830 /* Use proc_desc calculated in frame_chain */
1831 mips_extra_func_info_t proc_desc
=
1832 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
1834 fci
->extra_info
= (struct frame_extra_info
*)
1835 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1837 fci
->saved_regs
= NULL
;
1838 fci
->extra_info
->proc_desc
=
1839 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1842 /* Fixup frame-pointer - only needed for top frame */
1843 /* This may not be quite right, if proc has a real frame register.
1844 Get the value of the frame relative sp, procedure might have been
1845 interrupted by a signal at it's very start. */
1846 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1847 && !PROC_DESC_IS_DUMMY (proc_desc
))
1848 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1850 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1852 if (proc_desc
== &temp_proc_desc
)
1856 /* Do not set the saved registers for a sigtramp frame,
1857 mips_find_saved_registers will do that for us.
1858 We can't use fci->signal_handler_caller, it is not yet set. */
1859 find_pc_partial_function (fci
->pc
, &name
,
1860 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
1861 if (!IN_SIGTRAMP (fci
->pc
, name
))
1863 frame_saved_regs_zalloc (fci
);
1864 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
1865 fci
->saved_regs
[PC_REGNUM
]
1866 = fci
->saved_regs
[RA_REGNUM
];
1870 /* hack: if argument regs are saved, guess these contain args */
1871 /* assume we can't tell how many args for now */
1872 fci
->extra_info
->num_args
= -1;
1873 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1875 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
1877 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
1884 /* MIPS stack frames are almost impenetrable. When execution stops,
1885 we basically have to look at symbol information for the function
1886 that we stopped in, which tells us *which* register (if any) is
1887 the base of the frame pointer, and what offset from that register
1888 the frame itself is at.
1890 This presents a problem when trying to examine a stack in memory
1891 (that isn't executing at the moment), using the "frame" command. We
1892 don't have a PC, nor do we have any registers except SP.
1894 This routine takes two arguments, SP and PC, and tries to make the
1895 cached frames look as if these two arguments defined a frame on the
1896 cache. This allows the rest of info frame to extract the important
1897 arguments without difficulty. */
1900 setup_arbitrary_frame (argc
, argv
)
1905 error ("MIPS frame specifications require two arguments: sp and pc");
1907 return create_new_frame (argv
[0], argv
[1]);
1911 * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack?
1913 * For n32 ABI, eight.
1914 * For all others, he same as the size of a general register.
1916 #if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
1917 #define MIPS_NABI32 1
1918 #define STACK_ARGSIZE 8
1920 #define MIPS_NABI32 0
1921 #define STACK_ARGSIZE MIPS_SAVED_REGSIZE
1925 mips_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
1930 CORE_ADDR struct_addr
;
1936 int stack_offset
= 0;
1938 /* Macros to round N up or down to the next A boundary; A must be
1940 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1941 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1943 /* First ensure that the stack and structure return address (if any)
1944 are properly aligned. The stack has to be at least 64-bit aligned
1945 even on 32-bit machines, because doubles must be 64-bit aligned.
1946 On at least one MIPS variant, stack frames need to be 128-bit
1947 aligned, so we round to this widest known alignment. */
1948 sp
= ROUND_DOWN (sp
, 16);
1949 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_SAVED_REGSIZE
);
1951 /* Now make space on the stack for the args. We allocate more
1952 than necessary for EABI, because the first few arguments are
1953 passed in registers, but that's OK. */
1954 for (argnum
= 0; argnum
< nargs
; argnum
++)
1955 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_SAVED_REGSIZE
);
1956 sp
-= ROUND_UP (len
, 16);
1958 /* Initialize the integer and float register pointers. */
1960 float_argreg
= FPA0_REGNUM
;
1962 /* the struct_return pointer occupies the first parameter-passing reg */
1964 write_register (argreg
++, struct_addr
);
1966 /* Now load as many as possible of the first arguments into
1967 registers, and push the rest onto the stack. Loop thru args
1968 from first to last. */
1969 for (argnum
= 0; argnum
< nargs
; argnum
++)
1972 char valbuf
[MAX_REGISTER_RAW_SIZE
];
1973 value_ptr arg
= args
[argnum
];
1974 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1975 int len
= TYPE_LENGTH (arg_type
);
1976 enum type_code typecode
= TYPE_CODE (arg_type
);
1978 /* The EABI passes structures that do not fit in a register by
1979 reference. In all other cases, pass the structure by value. */
1980 if (MIPS_EABI
&& len
> MIPS_SAVED_REGSIZE
&&
1981 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1983 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
1984 typecode
= TYPE_CODE_PTR
;
1985 len
= MIPS_SAVED_REGSIZE
;
1989 val
= (char *) VALUE_CONTENTS (arg
);
1991 /* 32-bit ABIs always start floating point arguments in an
1992 even-numbered floating point register. */
1993 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
1994 && (float_argreg
& 1))
1997 /* Floating point arguments passed in registers have to be
1998 treated specially. On 32-bit architectures, doubles
1999 are passed in register pairs; the even register gets
2000 the low word, and the odd register gets the high word.
2001 On non-EABI processors, the first two floating point arguments are
2002 also copied to general registers, because MIPS16 functions
2003 don't use float registers for arguments. This duplication of
2004 arguments in general registers can't hurt non-MIPS16 functions
2005 because those registers are normally skipped. */
2006 if (typecode
== TYPE_CODE_FLT
2007 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
2008 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2010 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2012 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2013 unsigned long regval
;
2015 /* Write the low word of the double to the even register(s). */
2016 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2017 write_register (float_argreg
++, regval
);
2019 write_register (argreg
+ 1, regval
);
2021 /* Write the high word of the double to the odd register(s). */
2022 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2023 write_register (float_argreg
++, regval
);
2026 write_register (argreg
, regval
);
2033 /* This is a floating point value that fits entirely
2034 in a single register. */
2035 CORE_ADDR regval
= extract_address (val
, len
);
2036 write_register (float_argreg
++, regval
);
2039 write_register (argreg
, regval
);
2040 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2046 /* Copy the argument to general registers or the stack in
2047 register-sized pieces. Large arguments are split between
2048 registers and stack. */
2049 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2050 are treated specially: Irix cc passes them in registers
2051 where gcc sometimes puts them on the stack. For maximum
2052 compatibility, we will put them in both places. */
2054 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2055 (len
% MIPS_SAVED_REGSIZE
!= 0));
2058 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2060 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
2062 /* Write this portion of the argument to the stack. */
2063 /* Should shorter than int integer values be
2064 promoted to int before being stored? */
2066 int longword_offset
= 0;
2067 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2069 if (STACK_ARGSIZE
== 8 &&
2070 (typecode
== TYPE_CODE_INT
||
2071 typecode
== TYPE_CODE_PTR
||
2072 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2073 longword_offset
= STACK_ARGSIZE
- len
;
2074 else if ((typecode
== TYPE_CODE_STRUCT
||
2075 typecode
== TYPE_CODE_UNION
) &&
2076 TYPE_LENGTH (arg_type
) < STACK_ARGSIZE
)
2077 longword_offset
= STACK_ARGSIZE
- len
;
2080 write_memory (sp
+ stack_offset
+ longword_offset
,
2084 /* Note!!! This is NOT an else clause.
2085 Odd sized structs may go thru BOTH paths. */
2086 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
2088 CORE_ADDR regval
= extract_address (val
, partial_len
);
2090 /* A non-floating-point argument being passed in a
2091 general register. If a struct or union, and if
2092 the remaining length is smaller than the register
2093 size, we have to adjust the register value on
2096 It does not seem to be necessary to do the
2097 same for integral types.
2099 Also don't do this adjustment on EABI and O64
2103 && MIPS_SAVED_REGSIZE
< 8
2104 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2105 && partial_len
< MIPS_SAVED_REGSIZE
2106 && (typecode
== TYPE_CODE_STRUCT
||
2107 typecode
== TYPE_CODE_UNION
))
2108 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2111 write_register (argreg
, regval
);
2114 /* If this is the old ABI, prevent subsequent floating
2115 point arguments from being passed in floating point
2118 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2124 /* The offset onto the stack at which we will start
2125 copying parameters (after the registers are used up)
2126 begins at (4 * MIPS_REGSIZE) in the old ABI. This
2127 leaves room for the "home" area for register parameters.
2129 In the new EABI (and the NABI32), the 8 register parameters
2130 do not have "home" stack space reserved for them, so the
2131 stack offset does not get incremented until after
2132 we have used up the 8 parameter registers. */
2134 if (!(MIPS_EABI
|| MIPS_NABI32
) ||
2136 stack_offset
+= ROUND_UP (partial_len
, STACK_ARGSIZE
);
2141 /* Return adjusted stack pointer. */
2146 mips_push_return_address (pc
, sp
)
2150 /* Set the return address register to point to the entry
2151 point of the program, where a breakpoint lies in wait. */
2152 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2157 mips_push_register (CORE_ADDR
* sp
, int regno
)
2159 char buffer
[MAX_REGISTER_RAW_SIZE
];
2162 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2164 regsize
= MIPS_SAVED_REGSIZE
;
2165 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2166 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2171 regsize
= REGISTER_RAW_SIZE (regno
);
2175 read_register_gen (regno
, buffer
);
2176 write_memory (*sp
, buffer
+ offset
, regsize
);
2179 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2180 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2183 mips_push_dummy_frame ()
2186 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2187 xmalloc (sizeof (struct linked_proc_info
));
2188 mips_extra_func_info_t proc_desc
= &link
->info
;
2189 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2190 CORE_ADDR old_sp
= sp
;
2191 link
->next
= linked_proc_desc_table
;
2192 linked_proc_desc_table
= link
;
2194 /* FIXME! are these correct ? */
2195 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2196 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2197 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2198 #define FLOAT_SINGLE_REG_SAVE_MASK \
2199 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2201 * The registers we must save are all those not preserved across
2202 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2203 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2204 * and FP Control/Status registers.
2207 * Dummy frame layout:
2210 * Saved MMHI, MMLO, FPC_CSR
2215 * Saved D18 (i.e. F19, F18)
2217 * Saved D0 (i.e. F1, F0)
2218 * Argument build area and stack arguments written via mips_push_arguments
2222 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2223 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2224 PROC_FRAME_OFFSET (proc_desc
) = 0;
2225 PROC_FRAME_ADJUST (proc_desc
) = 0;
2226 mips_push_register (&sp
, PC_REGNUM
);
2227 mips_push_register (&sp
, HI_REGNUM
);
2228 mips_push_register (&sp
, LO_REGNUM
);
2229 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2231 /* Save general CPU registers */
2232 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2233 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2234 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2235 for (ireg
= 32; --ireg
>= 0;)
2236 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2237 mips_push_register (&sp
, ireg
);
2239 /* Save floating point registers starting with high order word */
2240 PROC_FREG_MASK (proc_desc
) =
2241 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2242 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2243 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2245 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2246 for (ireg
= 32; --ireg
>= 0;)
2247 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2248 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2250 /* Update the frame pointer for the call dummy and the stack pointer.
2251 Set the procedure's starting and ending addresses to point to the
2252 call dummy address at the entry point. */
2253 write_register (PUSH_FP_REGNUM
, old_sp
);
2254 write_register (SP_REGNUM
, sp
);
2255 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2256 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2257 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2258 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2264 register int regnum
;
2265 struct frame_info
*frame
= get_current_frame ();
2266 CORE_ADDR new_sp
= FRAME_FP (frame
);
2268 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2270 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2271 if (frame
->saved_regs
== NULL
)
2272 mips_find_saved_regs (frame
);
2273 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2275 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2276 && frame
->saved_regs
[regnum
])
2277 write_register (regnum
,
2278 read_memory_integer (frame
->saved_regs
[regnum
],
2279 MIPS_SAVED_REGSIZE
));
2281 write_register (SP_REGNUM
, new_sp
);
2282 flush_cached_frames ();
2284 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2286 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2288 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2290 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2292 if (&pi_ptr
->info
== proc_desc
)
2297 error ("Can't locate dummy extra frame info\n");
2299 if (prev_ptr
!= NULL
)
2300 prev_ptr
->next
= pi_ptr
->next
;
2302 linked_proc_desc_table
= pi_ptr
->next
;
2306 write_register (HI_REGNUM
,
2307 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2308 MIPS_SAVED_REGSIZE
));
2309 write_register (LO_REGNUM
,
2310 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2311 MIPS_SAVED_REGSIZE
));
2312 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2313 write_register (FCRCS_REGNUM
,
2314 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2315 MIPS_SAVED_REGSIZE
));
2320 mips_print_register (regnum
, all
)
2323 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2325 /* Get the data in raw format. */
2326 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2328 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2332 /* If an even floating point register, also print as double. */
2333 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2334 && !((regnum
- FP0_REGNUM
) & 1))
2335 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2337 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2339 read_relative_register_raw_bytes (regnum
, dbuffer
);
2340 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2341 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2343 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2344 val_print (builtin_type_double
, dbuffer
, 0, 0,
2345 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2346 printf_filtered ("); ");
2348 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2350 /* The problem with printing numeric register names (r26, etc.) is that
2351 the user can't use them on input. Probably the best solution is to
2352 fix it so that either the numeric or the funky (a2, etc.) names
2353 are accepted on input. */
2354 if (regnum
< MIPS_NUMREGS
)
2355 printf_filtered ("(r%d): ", regnum
);
2357 printf_filtered (": ");
2359 /* If virtual format is floating, print it that way. */
2360 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2361 if (FP_REGISTER_DOUBLE
)
2362 { /* show 8-byte floats as float AND double: */
2363 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2365 printf_filtered (" (float) ");
2366 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2367 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2368 printf_filtered (", (double) ");
2369 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2370 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2373 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2374 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2375 /* Else print as integer in hex. */
2377 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
2378 'x', 0, gdb_stdout
);
2381 /* Replacement for generic do_registers_info.
2382 Print regs in pretty columns. */
2385 do_fp_register_row (regnum
)
2387 { /* do values for FP (float) regs */
2388 char *raw_buffer
[2];
2390 /* use HI and LO to control the order of combining two flt regs */
2391 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2392 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2393 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2394 int inv1
, inv2
, inv3
;
2396 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2397 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2398 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2400 /* Get the data in raw format. */
2401 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2402 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2403 if (REGISTER_RAW_SIZE (regnum
) == 4)
2405 /* 4-byte registers: we can fit two registers per row. */
2406 /* Also print every pair of 4-byte regs as an 8-byte double. */
2407 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2408 error ("can't read register %d (%s)",
2409 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2411 /* copy the two floats into one double, and unpack both */
2412 memcpy (dbl_buffer
, raw_buffer
, sizeof (dbl_buffer
));
2413 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2414 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2415 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2417 printf_filtered (inv1
? " %-5s: <invalid float>" :
2418 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2419 printf_filtered (inv2
? " %-5s: <invalid float>" :
2420 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2421 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2422 " dbl: %-24.17g\n", doub
);
2423 /* may want to do hex display here (future enhancement) */
2427 { /* eight byte registers: print each one as float AND as double. */
2428 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2430 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof (dbl_buffer
));
2431 flt1
= unpack_double (builtin_type_float
,
2432 &raw_buffer
[HI
][offset
], &inv1
);
2433 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2435 printf_filtered (inv1
? " %-5s: <invalid float>" :
2436 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2437 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2438 " dbl: %-24.17g\n", doub
);
2439 /* may want to do hex display here (future enhancement) */
2445 /* Print a row's worth of GP (int) registers, with name labels above */
2448 do_gp_register_row (regnum
)
2451 /* do values for GP (int) regs */
2452 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2453 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2455 int start_regnum
= regnum
;
2456 int numregs
= NUM_REGS
;
2459 /* For GP registers, we print a separate row of names above the vals */
2460 printf_filtered (" ");
2461 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2463 if (*REGISTER_NAME (regnum
) == '\0')
2464 continue; /* unused register */
2465 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2466 break; /* end the row: reached FP register */
2467 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2468 REGISTER_NAME (regnum
));
2471 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2472 start_regnum
); /* print the R0 to R31 names */
2474 regnum
= start_regnum
; /* go back to start of row */
2475 /* now print the values in hex, 4 or 8 to the row */
2476 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2478 if (*REGISTER_NAME (regnum
) == '\0')
2479 continue; /* unused register */
2480 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2481 break; /* end row: reached FP register */
2482 /* OK: get the data in raw format. */
2483 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2484 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2485 /* pad small registers */
2486 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
2487 printf_filtered (" ");
2488 /* Now print the register value in hex, endian order. */
2489 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2490 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2491 byte
< REGISTER_RAW_SIZE (regnum
);
2493 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2495 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
2498 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2499 printf_filtered (" ");
2502 if (col
> 0) /* ie. if we actually printed anything... */
2503 printf_filtered ("\n");
2508 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2511 mips_do_registers_info (regnum
, fpregs
)
2515 if (regnum
!= -1) /* do one specified register */
2517 if (*(REGISTER_NAME (regnum
)) == '\0')
2518 error ("Not a valid register for the current processor type");
2520 mips_print_register (regnum
, 0);
2521 printf_filtered ("\n");
2524 /* do all (or most) registers */
2527 while (regnum
< NUM_REGS
)
2529 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2530 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2531 regnum
= do_fp_register_row (regnum
); /* FP regs */
2533 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2535 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2540 /* Return number of args passed to a frame. described by FIP.
2541 Can return -1, meaning no way to tell. */
2544 mips_frame_num_args (frame
)
2545 struct frame_info
*frame
;
2547 #if 0 /* FIXME Use or lose this! */
2548 struct chain_info_t
*p
;
2550 p
= mips_find_cached_frame (FRAME_FP (frame
));
2552 return p
->the_info
.numargs
;
2557 /* Is this a branch with a delay slot? */
2559 static int is_delayed
PARAMS ((unsigned long));
2566 for (i
= 0; i
< NUMOPCODES
; ++i
)
2567 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2568 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2570 return (i
< NUMOPCODES
2571 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2572 | INSN_COND_BRANCH_DELAY
2573 | INSN_COND_BRANCH_LIKELY
)));
2577 mips_step_skips_delay (pc
)
2580 char buf
[MIPS_INSTLEN
];
2582 /* There is no branch delay slot on MIPS16. */
2583 if (pc_is_mips16 (pc
))
2586 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2587 /* If error reading memory, guess that it is not a delayed branch. */
2589 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2593 /* Skip the PC past function prologue instructions (32-bit version).
2594 This is a helper function for mips_skip_prologue. */
2597 mips32_skip_prologue (pc
, lenient
)
2598 CORE_ADDR pc
; /* starting PC to search from */
2603 int seen_sp_adjust
= 0;
2604 int load_immediate_bytes
= 0;
2606 /* Skip the typical prologue instructions. These are the stack adjustment
2607 instruction and the instructions that save registers on the stack
2608 or in the gcc frame. */
2609 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2611 unsigned long high_word
;
2613 inst
= mips_fetch_instruction (pc
);
2614 high_word
= (inst
>> 16) & 0xffff;
2617 if (lenient
&& is_delayed (inst
))
2621 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2622 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2624 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2625 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2627 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2628 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2629 && (inst
& 0x001F0000)) /* reg != $zero */
2632 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2634 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2636 continue; /* reg != $zero */
2638 /* move $s8,$sp. With different versions of gas this will be either
2639 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2640 Accept any one of these. */
2641 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2644 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2646 else if (high_word
== 0x3c1c) /* lui $gp,n */
2648 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2650 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2651 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2653 /* The following instructions load $at or $t0 with an immediate
2654 value in preparation for a stack adjustment via
2655 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2656 a local variable, so we accept them only before a stack adjustment
2657 instruction was seen. */
2658 else if (!seen_sp_adjust
)
2660 if (high_word
== 0x3c01 || /* lui $at,n */
2661 high_word
== 0x3c08) /* lui $t0,n */
2663 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2666 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2667 high_word
== 0x3508 || /* ori $t0,$t0,n */
2668 high_word
== 0x3401 || /* ori $at,$zero,n */
2669 high_word
== 0x3408) /* ori $t0,$zero,n */
2671 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2681 /* In a frameless function, we might have incorrectly
2682 skipped some load immediate instructions. Undo the skipping
2683 if the load immediate was not followed by a stack adjustment. */
2684 if (load_immediate_bytes
&& !seen_sp_adjust
)
2685 pc
-= load_immediate_bytes
;
2689 /* Skip the PC past function prologue instructions (16-bit version).
2690 This is a helper function for mips_skip_prologue. */
2693 mips16_skip_prologue (pc
, lenient
)
2694 CORE_ADDR pc
; /* starting PC to search from */
2698 int extend_bytes
= 0;
2699 int prev_extend_bytes
;
2701 /* Table of instructions likely to be found in a function prologue. */
2704 unsigned short inst
;
2705 unsigned short mask
;
2712 , /* addiu $sp,offset */
2716 , /* daddiu $sp,offset */
2720 , /* sw reg,n($sp) */
2724 , /* sd reg,n($sp) */
2728 , /* sw $ra,n($sp) */
2732 , /* sd $ra,n($sp) */
2740 , /* sw $a0-$a3,n($s1) */
2744 , /* move reg,$a0-$a3 */
2748 , /* entry pseudo-op */
2752 , /* addiu $s1,$sp,n */
2755 } /* end of table marker */
2758 /* Skip the typical prologue instructions. These are the stack adjustment
2759 instruction and the instructions that save registers on the stack
2760 or in the gcc frame. */
2761 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2763 unsigned short inst
;
2766 inst
= mips_fetch_instruction (pc
);
2768 /* Normally we ignore an extend instruction. However, if it is
2769 not followed by a valid prologue instruction, we must adjust
2770 the pc back over the extend so that it won't be considered
2771 part of the prologue. */
2772 if ((inst
& 0xf800) == 0xf000) /* extend */
2774 extend_bytes
= MIPS16_INSTLEN
;
2777 prev_extend_bytes
= extend_bytes
;
2780 /* Check for other valid prologue instructions besides extend. */
2781 for (i
= 0; table
[i
].mask
!= 0; i
++)
2782 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2784 if (table
[i
].mask
!= 0) /* it was in table? */
2785 continue; /* ignore it */
2789 /* Return the current pc, adjusted backwards by 2 if
2790 the previous instruction was an extend. */
2791 return pc
- prev_extend_bytes
;
2797 /* To skip prologues, I use this predicate. Returns either PC itself
2798 if the code at PC does not look like a function prologue; otherwise
2799 returns an address that (if we're lucky) follows the prologue. If
2800 LENIENT, then we must skip everything which is involved in setting
2801 up the frame (it's OK to skip more, just so long as we don't skip
2802 anything which might clobber the registers which are being saved.
2803 We must skip more in the case where part of the prologue is in the
2804 delay slot of a non-prologue instruction). */
2807 mips_skip_prologue (pc
, lenient
)
2811 /* See if we can determine the end of the prologue via the symbol table.
2812 If so, then return either PC, or the PC after the prologue, whichever
2815 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2817 if (post_prologue_pc
!= 0)
2818 return max (pc
, post_prologue_pc
);
2820 /* Can't determine prologue from the symbol table, need to examine
2823 if (pc_is_mips16 (pc
))
2824 return mips16_skip_prologue (pc
, lenient
);
2826 return mips32_skip_prologue (pc
, lenient
);
2830 /* The lenient prologue stuff should be superseded by the code in
2831 init_extra_frame_info which looks to see whether the stores mentioned
2832 in the proc_desc have actually taken place. */
2834 /* Is address PC in the prologue (loosely defined) for function at
2838 mips_in_lenient_prologue (startaddr
, pc
)
2839 CORE_ADDR startaddr
;
2842 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2843 return pc
>= startaddr
&& pc
< end_prologue
;
2847 /* Determine how a return value is stored within the MIPS register
2848 file, given the return type `valtype'. */
2850 struct return_value_word
2858 static void return_value_location
PARAMS ((struct type
*, struct return_value_word
*, struct return_value_word
*));
2861 return_value_location (valtype
, hi
, lo
)
2862 struct type
*valtype
;
2863 struct return_value_word
*hi
;
2864 struct return_value_word
*lo
;
2866 int len
= TYPE_LENGTH (valtype
);
2868 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2869 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2870 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2872 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2874 /* We need to break a 64bit float in two 32 bit halves and
2875 spread them across a floating-point register pair. */
2876 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2877 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
2878 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2879 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
2881 hi
->reg_offset
= lo
->reg_offset
;
2882 lo
->reg
= FP0_REGNUM
+ 0;
2883 hi
->reg
= FP0_REGNUM
+ 1;
2889 /* The floating point value fits in a single floating-point
2891 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2892 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
2895 lo
->reg
= FP0_REGNUM
;
2906 /* Locate a result possibly spread across two registers. */
2908 lo
->reg
= regnum
+ 0;
2909 hi
->reg
= regnum
+ 1;
2910 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2911 && len
< MIPS_SAVED_REGSIZE
)
2913 /* "un-left-justify" the value in the low register */
2914 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
2919 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2920 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
2921 && len
< MIPS_SAVED_REGSIZE
* 2
2922 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2923 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2925 /* "un-left-justify" the value spread across two registers. */
2926 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
2927 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
2929 hi
->len
= len
- lo
->len
;
2933 /* Only perform a partial copy of the second register. */
2936 if (len
> MIPS_SAVED_REGSIZE
)
2938 lo
->len
= MIPS_SAVED_REGSIZE
;
2939 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
2947 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2948 && REGISTER_RAW_SIZE (regnum
) == 8
2949 && MIPS_SAVED_REGSIZE
== 4)
2951 /* Account for the fact that only the least-signficant part
2952 of the register is being used */
2953 lo
->reg_offset
+= 4;
2954 hi
->reg_offset
+= 4;
2957 hi
->buf_offset
= lo
->len
;
2961 /* Given a return value in `regbuf' with a type `valtype', extract and
2962 copy its value into `valbuf'. */
2965 mips_extract_return_value (valtype
, regbuf
, valbuf
)
2966 struct type
*valtype
;
2967 char regbuf
[REGISTER_BYTES
];
2970 struct return_value_word lo
;
2971 struct return_value_word hi
;
2972 return_value_location (valtype
, &lo
, &hi
);
2974 memcpy (valbuf
+ lo
.buf_offset
,
2975 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
2979 memcpy (valbuf
+ hi
.buf_offset
,
2980 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
2986 int len
= TYPE_LENGTH (valtype
);
2989 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2990 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
2991 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
2992 && len
<= MIPS_FPU_SINGLE_REGSIZE
)))
2993 regnum
= FP0_REGNUM
;
2995 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2996 { /* "un-left-justify" the value from the register */
2997 if (len
< REGISTER_RAW_SIZE (regnum
))
2998 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2999 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3000 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3001 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3002 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3003 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3005 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
3006 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
3010 /* Given a return value in `valbuf' with a type `valtype', write it's
3011 value into the appropriate register. */
3014 mips_store_return_value (valtype
, valbuf
)
3015 struct type
*valtype
;
3018 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3019 struct return_value_word lo
;
3020 struct return_value_word hi
;
3021 return_value_location (valtype
, &lo
, &hi
);
3023 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3024 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3025 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3027 REGISTER_RAW_SIZE (lo
.reg
));
3031 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3032 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3033 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3035 REGISTER_RAW_SIZE (hi
.reg
));
3041 int len
= TYPE_LENGTH (valtype
);
3042 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3045 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3046 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3047 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3048 && len
<= MIPS_REGSIZE
)))
3049 regnum
= FP0_REGNUM
;
3051 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3052 { /* "left-justify" the value in the register */
3053 if (len
< REGISTER_RAW_SIZE (regnum
))
3054 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3055 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3056 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3057 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3058 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3059 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3061 memcpy (raw_buffer
+ offset
, valbuf
, len
);
3062 REGISTER_CONVERT_FROM_TYPE (regnum
, valtype
, raw_buffer
);
3063 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
,
3064 len
> REGISTER_RAW_SIZE (regnum
) ?
3065 len
: REGISTER_RAW_SIZE (regnum
));
3069 /* Exported procedure: Is PC in the signal trampoline code */
3072 in_sigtramp (pc
, ignore
)
3074 char *ignore
; /* function name */
3076 if (sigtramp_address
== 0)
3078 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3081 /* Commands to show/set the MIPS FPU type. */
3083 static void show_mipsfpu_command
PARAMS ((char *, int));
3085 show_mipsfpu_command (args
, from_tty
)
3091 switch (MIPS_FPU_TYPE
)
3093 case MIPS_FPU_SINGLE
:
3094 fpu
= "single-precision";
3096 case MIPS_FPU_DOUBLE
:
3097 fpu
= "double-precision";
3100 fpu
= "absent (none)";
3103 if (mips_fpu_type_auto
)
3104 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3107 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3112 static void set_mipsfpu_command
PARAMS ((char *, int));
3114 set_mipsfpu_command (args
, from_tty
)
3118 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3119 show_mipsfpu_command (args
, from_tty
);
3122 static void set_mipsfpu_single_command
PARAMS ((char *, int));
3124 set_mipsfpu_single_command (args
, from_tty
)
3128 mips_fpu_type
= MIPS_FPU_SINGLE
;
3129 mips_fpu_type_auto
= 0;
3132 static void set_mipsfpu_double_command
PARAMS ((char *, int));
3134 set_mipsfpu_double_command (args
, from_tty
)
3138 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3139 mips_fpu_type_auto
= 0;
3142 static void set_mipsfpu_none_command
PARAMS ((char *, int));
3144 set_mipsfpu_none_command (args
, from_tty
)
3148 mips_fpu_type
= MIPS_FPU_NONE
;
3149 mips_fpu_type_auto
= 0;
3152 static void set_mipsfpu_auto_command
PARAMS ((char *, int));
3154 set_mipsfpu_auto_command (args
, from_tty
)
3158 mips_fpu_type_auto
= 1;
3161 /* Command to set the processor type. */
3164 mips_set_processor_type_command (args
, from_tty
)
3170 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3172 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3173 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3174 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3176 /* Restore the value. */
3177 tmp_mips_processor_type
= strsave (mips_processor_type
);
3182 if (!mips_set_processor_type (tmp_mips_processor_type
))
3184 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3185 /* Restore its value. */
3186 tmp_mips_processor_type
= strsave (mips_processor_type
);
3191 mips_show_processor_type_command (args
, from_tty
)
3197 /* Modify the actual processor type. */
3200 mips_set_processor_type (str
)
3208 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3210 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3212 mips_processor_type
= str
;
3213 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3215 /* FIXME tweak fpu flag too */
3222 /* Attempt to identify the particular processor model by reading the
3226 mips_read_processor_type ()
3230 prid
= read_register (PRID_REGNUM
);
3232 if ((prid
& ~0xf) == 0x700)
3233 return savestring ("r3041", strlen ("r3041"));
3238 /* Just like reinit_frame_cache, but with the right arguments to be
3239 callable as an sfunc. */
3242 reinit_frame_cache_sfunc (args
, from_tty
, c
)
3245 struct cmd_list_element
*c
;
3247 reinit_frame_cache ();
3251 gdb_print_insn_mips (memaddr
, info
)
3253 disassemble_info
*info
;
3255 mips_extra_func_info_t proc_desc
;
3257 /* Search for the function containing this address. Set the low bit
3258 of the address when searching, in case we were given an even address
3259 that is the start of a 16-bit function. If we didn't do this,
3260 the search would fail because the symbol table says the function
3261 starts at an odd address, i.e. 1 byte past the given address. */
3262 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3263 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3265 /* Make an attempt to determine if this is a 16-bit function. If
3266 the procedure descriptor exists and the address therein is odd,
3267 it's definitely a 16-bit function. Otherwise, we have to just
3268 guess that if the address passed in is odd, it's 16-bits. */
3270 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
3272 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
3274 /* Round down the instruction address to the appropriate boundary. */
3275 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
3277 /* Call the appropriate disassembler based on the target endian-ness. */
3278 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3279 return print_insn_big_mips (memaddr
, info
);
3281 return print_insn_little_mips (memaddr
, info
);
3284 /* Old-style breakpoint macros.
3285 The IDT board uses an unusual breakpoint value, and sometimes gets
3286 confused when it sees the usual MIPS breakpoint instruction. */
3288 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3289 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3290 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3291 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3292 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3293 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3294 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3295 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3297 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3298 counter value to determine whether a 16- or 32-bit breakpoint should be
3299 used. It returns a pointer to a string of bytes that encode a breakpoint
3300 instruction, stores the length of the string to *lenptr, and adjusts pc
3301 (if necessary) to point to the actual memory location where the
3302 breakpoint should be inserted. */
3305 mips_breakpoint_from_pc (pcptr
, lenptr
)
3309 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3311 if (pc_is_mips16 (*pcptr
))
3313 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3314 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3315 *lenptr
= sizeof (mips16_big_breakpoint
);
3316 return mips16_big_breakpoint
;
3320 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3321 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3322 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3324 *lenptr
= sizeof (big_breakpoint
);
3326 if (strcmp (target_shortname
, "mips") == 0)
3327 return idt_big_breakpoint
;
3328 else if (strcmp (target_shortname
, "ddb") == 0
3329 || strcmp (target_shortname
, "pmon") == 0
3330 || strcmp (target_shortname
, "lsi") == 0)
3331 return pmon_big_breakpoint
;
3333 return big_breakpoint
;
3338 if (pc_is_mips16 (*pcptr
))
3340 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3341 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3342 *lenptr
= sizeof (mips16_little_breakpoint
);
3343 return mips16_little_breakpoint
;
3347 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3348 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3349 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3351 *lenptr
= sizeof (little_breakpoint
);
3353 if (strcmp (target_shortname
, "mips") == 0)
3354 return idt_little_breakpoint
;
3355 else if (strcmp (target_shortname
, "ddb") == 0
3356 || strcmp (target_shortname
, "pmon") == 0
3357 || strcmp (target_shortname
, "lsi") == 0)
3358 return pmon_little_breakpoint
;
3360 return little_breakpoint
;
3365 /* If PC is in a mips16 call or return stub, return the address of the target
3366 PC, which is either the callee or the caller. There are several
3367 cases which must be handled:
3369 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3370 target PC is in $31 ($ra).
3371 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3372 and the target PC is in $2.
3373 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3374 before the jal instruction, this is effectively a call stub
3375 and the the target PC is in $2. Otherwise this is effectively
3376 a return stub and the target PC is in $18.
3378 See the source code for the stubs in gcc/config/mips/mips16.S for
3381 This function implements the SKIP_TRAMPOLINE_CODE macro.
3389 CORE_ADDR start_addr
;
3391 /* Find the starting address and name of the function containing the PC. */
3392 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3395 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3396 target PC is in $31 ($ra). */
3397 if (strcmp (name
, "__mips16_ret_sf") == 0
3398 || strcmp (name
, "__mips16_ret_df") == 0)
3399 return read_register (RA_REGNUM
);
3401 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3403 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3404 and the target PC is in $2. */
3405 if (name
[19] >= '0' && name
[19] <= '9')
3406 return read_register (2);
3408 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3409 before the jal instruction, this is effectively a call stub
3410 and the the target PC is in $2. Otherwise this is effectively
3411 a return stub and the target PC is in $18. */
3412 else if (name
[19] == 's' || name
[19] == 'd')
3414 if (pc
== start_addr
)
3416 /* Check if the target of the stub is a compiler-generated
3417 stub. Such a stub for a function bar might have a name
3418 like __fn_stub_bar, and might look like this:
3423 la $1,bar (becomes a lui/addiu pair)
3425 So scan down to the lui/addi and extract the target
3426 address from those two instructions. */
3428 CORE_ADDR target_pc
= read_register (2);
3432 /* See if the name of the target function is __fn_stub_*. */
3433 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3435 if (strncmp (name
, "__fn_stub_", 10) != 0
3436 && strcmp (name
, "etext") != 0
3437 && strcmp (name
, "_etext") != 0)
3440 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3441 The limit on the search is arbitrarily set to 20
3442 instructions. FIXME. */
3443 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3445 inst
= mips_fetch_instruction (target_pc
);
3446 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3447 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3448 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3449 return pc
| (inst
& 0xffff); /* low word */
3452 /* Couldn't find the lui/addui pair, so return stub address. */
3456 /* This is the 'return' part of a call stub. The return
3457 address is in $r18. */
3458 return read_register (18);
3461 return 0; /* not a stub */
3465 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3466 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3469 mips_in_call_stub (pc
, name
)
3473 CORE_ADDR start_addr
;
3475 /* Find the starting address of the function containing the PC. If the
3476 caller didn't give us a name, look it up at the same time. */
3477 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3480 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3482 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3483 if (name
[19] >= '0' && name
[19] <= '9')
3485 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3486 before the jal instruction, this is effectively a call stub. */
3487 else if (name
[19] == 's' || name
[19] == 'd')
3488 return pc
== start_addr
;
3491 return 0; /* not a stub */
3495 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3496 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3499 mips_in_return_stub (pc
, name
)
3503 CORE_ADDR start_addr
;
3505 /* Find the starting address of the function containing the PC. */
3506 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3509 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3510 if (strcmp (name
, "__mips16_ret_sf") == 0
3511 || strcmp (name
, "__mips16_ret_df") == 0)
3514 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3515 i.e. after the jal instruction, this is effectively a return stub. */
3516 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3517 && (name
[19] == 's' || name
[19] == 'd')
3518 && pc
!= start_addr
)
3521 return 0; /* not a stub */
3525 /* Return non-zero if the PC is in a library helper function that should
3526 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3529 mips_ignore_helper (pc
)
3534 /* Find the starting address and name of the function containing the PC. */
3535 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3538 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3539 that we want to ignore. */
3540 return (strcmp (name
, "__mips16_ret_sf") == 0
3541 || strcmp (name
, "__mips16_ret_df") == 0);
3545 /* Return a location where we can set a breakpoint that will be hit
3546 when an inferior function call returns. This is normally the
3547 program's entry point. Executables that don't have an entry
3548 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3549 whose address is the location where the breakpoint should be placed. */
3552 mips_call_dummy_address ()
3554 struct minimal_symbol
*sym
;
3556 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3558 return SYMBOL_VALUE_ADDRESS (sym
);
3560 return entry_point_address ();
3565 _initialize_mips_tdep ()
3567 static struct cmd_list_element
*mipsfpulist
= NULL
;
3568 struct cmd_list_element
*c
;
3570 if (!tm_print_insn
) /* Someone may have already set it */
3571 tm_print_insn
= gdb_print_insn_mips
;
3573 /* Let the user turn off floating point and set the fence post for
3574 heuristic_proc_start. */
3576 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
3577 "Set use of MIPS floating-point coprocessor.",
3578 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
3579 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
3580 "Select single-precision MIPS floating-point coprocessor.",
3582 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
3583 "Select double-precision MIPS floating-point coprocessor .",
3585 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
3586 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
3587 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
3588 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
3589 "Select no MIPS floating-point coprocessor.",
3591 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
3592 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
3593 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
3594 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
3595 "Select MIPS floating-point coprocessor automatically.",
3597 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
3598 "Show current use of MIPS floating-point coprocessor target.",
3601 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
3602 (char *) &tmp_mips_processor_type
,
3603 "Set the type of MIPS processor in use.\n\
3604 Set this to be able to access processor-type-specific registers.\n\
3607 c
->function
.cfunc
= mips_set_processor_type_command
;
3608 c
= add_show_from_set (c
, &showlist
);
3609 c
->function
.cfunc
= mips_show_processor_type_command
;
3611 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
3612 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
3614 /* We really would like to have both "0" and "unlimited" work, but
3615 command.c doesn't deal with that. So make it a var_zinteger
3616 because the user can always use "999999" or some such for unlimited. */
3617 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
3618 (char *) &heuristic_fence_post
,
3620 Set the distance searched for the start of a function.\n\
3621 If you are debugging a stripped executable, GDB needs to search through the\n\
3622 program for the start of a function. This command sets the distance of the\n\
3623 search. The only need to set it is when debugging a stripped executable.",
3625 /* We need to throw away the frame cache when we set this, since it
3626 might change our ability to get backtraces. */
3627 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
3628 add_show_from_set (c
, &showlist
);
3630 /* Allow the user to control whether the upper bits of 64-bit
3631 addresses should be zeroed. */
3633 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *) &mask_address_p
,
3634 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
3635 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
3636 Without an argument, zeroing of upper address bits is enabled.", &setlist
),
3639 /* Allow the user to control the size of 32 bit registers within the
3640 raw remote packet. */
3641 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
3644 (char *)&mips64_transfers_32bit_regs_p
, "\
3645 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
3646 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
3647 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
3648 64 bits for others. Use \"off\" to disable compatibility mode",