1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 /* Some MIPS boards don't support floating point while others only
146 support single-precision floating-point operations. */
150 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
151 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
152 MIPS_FPU_NONE
/* No floating point. */
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto
= 1;
159 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
161 static int mips_debug
= 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc
*mips_tdesc_gp32
;
169 struct target_desc
*mips_tdesc_gp64
;
171 /* MIPS specific per-architecture information */
174 /* from the elf header */
178 enum mips_abi mips_abi
;
179 enum mips_abi found_abi
;
180 enum mips_fpu_type mips_fpu_type
;
181 int mips_last_arg_regnum
;
182 int mips_last_fp_arg_regnum
;
183 int default_mask_address_p
;
184 /* Is the target using 64-bit raw integer registers but only
185 storing a left-aligned 32-bit value in each? */
186 int mips64_transfers_32bit_regs_p
;
187 /* Indexes for various registers. IRIX and embedded have
188 different values. This contains the "public" fields. Don't
189 add any that do not need to be public. */
190 const struct mips_regnum
*regnum
;
191 /* Register names table for the current register set. */
192 const char **mips_processor_reg_names
;
194 /* The size of register data available from the target, if known.
195 This doesn't quite obsolete the manual
196 mips64_transfers_32bit_regs_p, since that is documented to force
197 left alignment even for big endian (very strange). */
198 int register_size_valid_p
;
203 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
209 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
210 They are implemented as a pair of 64bit doubles where the high
211 part holds the result of the operation rounded to double, and
212 the low double holds the difference between the exact result and
213 the rounded result. So "high" + "low" contains the result with
214 added precision. Unfortunately, the floatformat structure used
215 by GDB is not powerful enough to describe this format. As a temporary
216 measure, we define a 128bit floatformat that only uses the high part.
217 We lose a bit of precision but that's probably the best we can do
218 for now with the current infrastructure. */
220 static const struct floatformat floatformat_n32n64_long_double_big
=
222 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
223 floatformat_intbit_no
,
224 "floatformat_n32n64_long_double_big",
225 n32n64_floatformat_always_valid
228 static const struct floatformat
*floatformats_n32n64_long
[BFD_ENDIAN_UNKNOWN
] =
230 &floatformat_n32n64_long_double_big
,
231 &floatformat_n32n64_long_double_big
234 const struct mips_regnum
*
235 mips_regnum (struct gdbarch
*gdbarch
)
237 return gdbarch_tdep (gdbarch
)->regnum
;
241 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
243 return mips_regnum (gdbarch
)->fp0
+ 12;
246 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
247 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
249 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
251 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
253 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
255 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
256 functions to test, set, or clear bit 0 of addresses. */
259 is_mips16_addr (CORE_ADDR addr
)
265 unmake_mips16_addr (CORE_ADDR addr
)
267 return ((addr
) & ~(CORE_ADDR
) 1);
270 /* Return the MIPS ABI associated with GDBARCH. */
272 mips_abi (struct gdbarch
*gdbarch
)
274 return gdbarch_tdep (gdbarch
)->mips_abi
;
278 mips_isa_regsize (struct gdbarch
*gdbarch
)
280 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
282 /* If we know how big the registers are, use that size. */
283 if (tdep
->register_size_valid_p
)
284 return tdep
->register_size
;
286 /* Fall back to the previous behavior. */
287 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
288 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
291 /* Return the currently configured (or set) saved register size. */
294 mips_abi_regsize (struct gdbarch
*gdbarch
)
296 switch (mips_abi (gdbarch
))
298 case MIPS_ABI_EABI32
:
304 case MIPS_ABI_EABI64
:
306 case MIPS_ABI_UNKNOWN
:
309 internal_error (__FILE__
, __LINE__
, _("bad switch"));
313 /* Functions for setting and testing a bit in a minimal symbol that
314 marks it as 16-bit function. The MSB of the minimal symbol's
315 "info" field is used for this purpose.
317 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
318 i.e. refers to a 16-bit function, and sets a "special" bit in a
319 minimal symbol to mark it as a 16-bit function
321 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
324 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
326 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
328 MSYMBOL_INFO (msym
) = (char *)
329 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
330 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
335 msymbol_is_special (struct minimal_symbol
*msym
)
337 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
340 /* XFER a value from the big/little/left end of the register.
341 Depending on the size of the value it might occupy the entire
342 register or just part of it. Make an allowance for this, aligning
343 things accordingly. */
346 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
347 int reg_num
, int length
,
348 enum bfd_endian endian
, gdb_byte
*in
,
349 const gdb_byte
*out
, int buf_offset
)
353 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
354 /* Need to transfer the left or right part of the register, based on
355 the targets byte order. */
359 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
361 case BFD_ENDIAN_LITTLE
:
364 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
368 internal_error (__FILE__
, __LINE__
, _("bad switch"));
371 fprintf_unfiltered (gdb_stderr
,
372 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
373 reg_num
, reg_offset
, buf_offset
, length
);
374 if (mips_debug
&& out
!= NULL
)
377 fprintf_unfiltered (gdb_stdlog
, "out ");
378 for (i
= 0; i
< length
; i
++)
379 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
382 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
385 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
387 if (mips_debug
&& in
!= NULL
)
390 fprintf_unfiltered (gdb_stdlog
, "in ");
391 for (i
= 0; i
< length
; i
++)
392 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
395 fprintf_unfiltered (gdb_stdlog
, "\n");
398 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
399 compatiblity mode. A return value of 1 means that we have
400 physical 64-bit registers, but should treat them as 32-bit registers. */
403 mips2_fp_compat (struct frame_info
*frame
)
405 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
406 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
408 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
412 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
413 in all the places we deal with FP registers. PR gdb/413. */
414 /* Otherwise check the FR bit in the status register - it controls
415 the FP compatiblity mode. If it is clear we are in compatibility
417 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
424 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
426 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
428 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
430 static struct type
*mips_float_register_type (void);
431 static struct type
*mips_double_register_type (void);
433 /* The list of available "set mips " and "show mips " commands */
435 static struct cmd_list_element
*setmipscmdlist
= NULL
;
436 static struct cmd_list_element
*showmipscmdlist
= NULL
;
438 /* Integer registers 0 thru 31 are handled explicitly by
439 mips_register_name(). Processor specific registers 32 and above
440 are listed in the following tables. */
443 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
447 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
448 "sr", "lo", "hi", "bad", "cause", "pc",
449 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
450 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
451 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
452 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
453 "fsr", "fir", "" /*"fp" */ , "",
454 "", "", "", "", "", "", "", "",
455 "", "", "", "", "", "", "", "",
458 /* Names of IDT R3041 registers. */
460 static const char *mips_r3041_reg_names
[] = {
461 "sr", "lo", "hi", "bad", "cause", "pc",
462 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
463 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
464 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
465 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
466 "fsr", "fir", "", /*"fp" */ "",
467 "", "", "bus", "ccfg", "", "", "", "",
468 "", "", "port", "cmp", "", "", "epc", "prid",
471 /* Names of tx39 registers. */
473 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
474 "sr", "lo", "hi", "bad", "cause", "pc",
475 "", "", "", "", "", "", "", "",
476 "", "", "", "", "", "", "", "",
477 "", "", "", "", "", "", "", "",
478 "", "", "", "", "", "", "", "",
480 "", "", "", "", "", "", "", "",
481 "", "", "config", "cache", "debug", "depc", "epc", ""
484 /* Names of IRIX registers. */
485 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
486 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
487 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
488 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
489 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
490 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
494 /* Return the name of the register corresponding to REGNO. */
496 mips_register_name (int regno
)
498 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
499 /* GPR names for all ABIs other than n32/n64. */
500 static char *mips_gpr_names
[] = {
501 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
502 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
503 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
504 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
507 /* GPR names for n32 and n64 ABIs. */
508 static char *mips_n32_n64_gpr_names
[] = {
509 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
510 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
511 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
512 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
515 enum mips_abi abi
= mips_abi (current_gdbarch
);
517 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
518 but then don't make the raw register names visible. */
519 int rawnum
= regno
% gdbarch_num_regs (current_gdbarch
);
520 if (regno
< gdbarch_num_regs (current_gdbarch
))
523 /* The MIPS integer registers are always mapped from 0 to 31. The
524 names of the registers (which reflects the conventions regarding
525 register use) vary depending on the ABI. */
526 if (0 <= rawnum
&& rawnum
< 32)
528 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
529 return mips_n32_n64_gpr_names
[rawnum
];
531 return mips_gpr_names
[rawnum
];
533 else if (tdesc_has_registers (gdbarch_target_desc (current_gdbarch
)))
534 return tdesc_register_name (rawnum
);
535 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (current_gdbarch
))
537 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
538 return tdep
->mips_processor_reg_names
[rawnum
- 32];
541 internal_error (__FILE__
, __LINE__
,
542 _("mips_register_name: bad register number %d"), rawnum
);
545 /* Return the groups that a MIPS register can be categorised into. */
548 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
549 struct reggroup
*reggroup
)
554 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
555 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
556 if (reggroup
== all_reggroup
)
558 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
559 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
560 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
561 (gdbarch), as not all architectures are multi-arch. */
562 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
563 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
564 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
566 if (reggroup
== float_reggroup
)
567 return float_p
&& pseudo
;
568 if (reggroup
== vector_reggroup
)
569 return vector_p
&& pseudo
;
570 if (reggroup
== general_reggroup
)
571 return (!vector_p
&& !float_p
) && pseudo
;
572 /* Save the pseudo registers. Need to make certain that any code
573 extracting register values from a saved register cache also uses
575 if (reggroup
== save_reggroup
)
576 return raw_p
&& pseudo
;
577 /* Restore the same pseudo register. */
578 if (reggroup
== restore_reggroup
)
579 return raw_p
&& pseudo
;
583 /* Return the groups that a MIPS register can be categorised into.
584 This version is only used if we have a target description which
585 describes real registers (and their groups). */
588 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
589 struct reggroup
*reggroup
)
591 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
592 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
595 /* Only save, restore, and display the pseudo registers. Need to
596 make certain that any code extracting register values from a
597 saved register cache also uses pseudo registers.
599 Note: saving and restoring the pseudo registers is slightly
600 strange; if we have 64 bits, we should save and restore all
601 64 bits. But this is hard and has little benefit. */
605 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
609 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
612 /* Map the symbol table registers which live in the range [1 *
613 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
614 registers. Take care of alignment and size problems. */
617 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
618 int cookednum
, gdb_byte
*buf
)
620 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
621 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
622 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
623 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
624 regcache_raw_read (regcache
, rawnum
, buf
);
625 else if (register_size (gdbarch
, rawnum
) >
626 register_size (gdbarch
, cookednum
))
628 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
629 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
630 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
632 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
635 internal_error (__FILE__
, __LINE__
, _("bad register size"));
639 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
640 struct regcache
*regcache
, int cookednum
,
643 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
644 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
645 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
646 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
647 regcache_raw_write (regcache
, rawnum
, buf
);
648 else if (register_size (gdbarch
, rawnum
) >
649 register_size (gdbarch
, cookednum
))
651 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
652 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
653 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
655 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
658 internal_error (__FILE__
, __LINE__
, _("bad register size"));
661 /* Table to translate MIPS16 register field to actual register number. */
662 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
664 /* Heuristic_proc_start may hunt through the text section for a long
665 time across a 2400 baud serial line. Allows the user to limit this
668 static unsigned int heuristic_fence_post
= 0;
670 /* Number of bytes of storage in the actual machine representation for
671 register N. NOTE: This defines the pseudo register type so need to
672 rebuild the architecture vector. */
674 static int mips64_transfers_32bit_regs_p
= 0;
677 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
678 struct cmd_list_element
*c
)
680 struct gdbarch_info info
;
681 gdbarch_info_init (&info
);
682 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
683 instead of relying on globals. Doing that would let generic code
684 handle the search for this specific architecture. */
685 if (!gdbarch_update_p (info
))
687 mips64_transfers_32bit_regs_p
= 0;
688 error (_("32-bit compatibility mode not supported"));
692 /* Convert to/from a register and the corresponding memory value. */
695 mips_convert_register_p (int regnum
, struct type
*type
)
697 return (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
698 && register_size (current_gdbarch
, regnum
) == 4
699 && (regnum
% gdbarch_num_regs (current_gdbarch
))
700 >= mips_regnum (current_gdbarch
)->fp0
701 && (regnum
% gdbarch_num_regs (current_gdbarch
))
702 < mips_regnum (current_gdbarch
)->fp0
+ 32
703 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
707 mips_register_to_value (struct frame_info
*frame
, int regnum
,
708 struct type
*type
, gdb_byte
*to
)
710 get_frame_register (frame
, regnum
+ 0, to
+ 4);
711 get_frame_register (frame
, regnum
+ 1, to
+ 0);
715 mips_value_to_register (struct frame_info
*frame
, int regnum
,
716 struct type
*type
, const gdb_byte
*from
)
718 put_frame_register (frame
, regnum
+ 0, from
+ 4);
719 put_frame_register (frame
, regnum
+ 1, from
+ 0);
722 /* Return the GDB type object for the "standard" data type of data in
726 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
728 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
729 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
730 && (regnum
% gdbarch_num_regs (gdbarch
))
731 < mips_regnum (gdbarch
)->fp0
+ 32)
733 /* The floating-point registers raw, or cooked, always match
734 mips_isa_regsize(), and also map 1:1, byte for byte. */
735 if (mips_isa_regsize (gdbarch
) == 4)
736 return builtin_type_ieee_single
;
738 return builtin_type_ieee_double
;
740 else if (regnum
< gdbarch_num_regs (gdbarch
))
742 /* The raw or ISA registers. These are all sized according to
744 if (mips_isa_regsize (gdbarch
) == 4)
745 return builtin_type_int32
;
747 return builtin_type_int64
;
751 /* The cooked or ABI registers. These are sized according to
752 the ABI (with a few complications). */
753 if (regnum
>= (gdbarch_num_regs (gdbarch
)
754 + mips_regnum (gdbarch
)->fp_control_status
)
755 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
756 /* The pseudo/cooked view of the embedded registers is always
757 32-bit. The raw view is handled below. */
758 return builtin_type_int32
;
759 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
760 /* The target, while possibly using a 64-bit register buffer,
761 is only transfering 32-bits of each integer register.
762 Reflect this in the cooked/pseudo (ABI) register value. */
763 return builtin_type_int32
;
764 else if (mips_abi_regsize (gdbarch
) == 4)
765 /* The ABI is restricted to 32-bit registers (the ISA could be
767 return builtin_type_int32
;
770 return builtin_type_int64
;
774 /* Return the GDB type for the pseudo register REGNUM, which is the
775 ABI-level view. This function is only called if there is a target
776 description which includes registers, so we know precisely the
777 types of hardware registers. */
780 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
782 const int num_regs
= gdbarch_num_regs (gdbarch
);
783 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
784 int rawnum
= regnum
% num_regs
;
785 struct type
*rawtype
;
787 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
789 /* Absent registers are still absent. */
790 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
791 if (TYPE_LENGTH (rawtype
) == 0)
794 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
795 /* Present the floating point registers however the hardware did;
796 do not try to convert between FPU layouts. */
799 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
801 /* The pseudo/cooked view of embedded registers is always
802 32-bit, even if the target transfers 64-bit values for them.
803 New targets relying on XML descriptions should only transfer
804 the necessary 32 bits, but older versions of GDB expected 64,
805 so allow the target to provide 64 bits without interfering
806 with the displayed type. */
807 return builtin_type_int32
;
810 /* Use pointer types for registers if we can. For n32 we can not,
811 since we do not have a 64-bit pointer type. */
812 if (mips_abi_regsize (gdbarch
) == TYPE_LENGTH (builtin_type_void_data_ptr
))
814 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
815 return builtin_type_void_data_ptr
;
816 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
817 return builtin_type_void_func_ptr
;
820 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
821 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
822 return builtin_type_int32
;
824 /* For all other registers, pass through the hardware type. */
828 /* Should the upper word of 64-bit addresses be zeroed? */
829 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
832 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
834 switch (mask_address_var
)
836 case AUTO_BOOLEAN_TRUE
:
838 case AUTO_BOOLEAN_FALSE
:
841 case AUTO_BOOLEAN_AUTO
:
842 return tdep
->default_mask_address_p
;
844 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
850 show_mask_address (struct ui_file
*file
, int from_tty
,
851 struct cmd_list_element
*c
, const char *value
)
853 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
855 deprecated_show_value_hack (file
, from_tty
, c
, value
);
856 switch (mask_address_var
)
858 case AUTO_BOOLEAN_TRUE
:
859 printf_filtered ("The 32 bit mips address mask is enabled\n");
861 case AUTO_BOOLEAN_FALSE
:
862 printf_filtered ("The 32 bit mips address mask is disabled\n");
864 case AUTO_BOOLEAN_AUTO
:
866 ("The 32 bit address mask is set automatically. Currently %s\n",
867 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
870 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
875 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
878 mips_pc_is_mips16 (CORE_ADDR memaddr
)
880 struct minimal_symbol
*sym
;
882 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
883 if (is_mips16_addr (memaddr
))
886 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
887 the high bit of the info field. Use this to decide if the function is
888 MIPS16 or normal MIPS. */
889 sym
= lookup_minimal_symbol_by_pc (memaddr
);
891 return msymbol_is_special (sym
);
896 /* MIPS believes that the PC has a sign extended value. Perhaps the
897 all registers should be sign extended for simplicity? */
900 mips_read_pc (struct regcache
*regcache
)
903 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
904 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
909 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
911 return frame_unwind_register_signed
912 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
916 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
918 return frame_unwind_register_signed
919 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
922 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
923 dummy frame. The frame ID's base needs to match the TOS value
924 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
927 static struct frame_id
928 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
930 return frame_id_build
931 (frame_unwind_register_signed (next_frame
,
932 gdbarch_num_regs (gdbarch
)
934 frame_pc_unwind (next_frame
));
938 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
940 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
941 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
944 /* Fetch and return instruction from the specified location. If the PC
945 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
948 mips_fetch_instruction (CORE_ADDR addr
)
950 gdb_byte buf
[MIPS_INSN32_SIZE
];
954 if (mips_pc_is_mips16 (addr
))
956 instlen
= MIPS_INSN16_SIZE
;
957 addr
= unmake_mips16_addr (addr
);
960 instlen
= MIPS_INSN32_SIZE
;
961 status
= read_memory_nobpt (addr
, buf
, instlen
);
963 memory_error (status
, addr
);
964 return extract_unsigned_integer (buf
, instlen
);
967 /* These the fields of 32 bit mips instructions */
968 #define mips32_op(x) (x >> 26)
969 #define itype_op(x) (x >> 26)
970 #define itype_rs(x) ((x >> 21) & 0x1f)
971 #define itype_rt(x) ((x >> 16) & 0x1f)
972 #define itype_immediate(x) (x & 0xffff)
974 #define jtype_op(x) (x >> 26)
975 #define jtype_target(x) (x & 0x03ffffff)
977 #define rtype_op(x) (x >> 26)
978 #define rtype_rs(x) ((x >> 21) & 0x1f)
979 #define rtype_rt(x) ((x >> 16) & 0x1f)
980 #define rtype_rd(x) ((x >> 11) & 0x1f)
981 #define rtype_shamt(x) ((x >> 6) & 0x1f)
982 #define rtype_funct(x) (x & 0x3f)
985 mips32_relative_offset (ULONGEST inst
)
987 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
990 /* Determine where to set a single step breakpoint while considering
991 branch prediction. */
993 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
997 inst
= mips_fetch_instruction (pc
);
998 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1000 if (itype_op (inst
) >> 2 == 5)
1001 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1003 op
= (itype_op (inst
) & 0x03);
1013 goto greater_branch
;
1018 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1019 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1021 int tf
= itype_rt (inst
) & 0x01;
1022 int cnum
= itype_rt (inst
) >> 2;
1024 get_frame_register_signed (frame
,
1025 mips_regnum (get_frame_arch (frame
))->
1027 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1029 if (((cond
>> cnum
) & 0x01) == tf
)
1030 pc
+= mips32_relative_offset (inst
) + 4;
1035 pc
+= 4; /* Not a branch, next instruction is easy */
1038 { /* This gets way messy */
1040 /* Further subdivide into SPECIAL, REGIMM and other */
1041 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1043 case 0: /* SPECIAL */
1044 op
= rtype_funct (inst
);
1049 /* Set PC to that address */
1050 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1056 break; /* end SPECIAL */
1057 case 1: /* REGIMM */
1059 op
= itype_rt (inst
); /* branch condition */
1064 case 16: /* BLTZAL */
1065 case 18: /* BLTZALL */
1067 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1068 pc
+= mips32_relative_offset (inst
) + 4;
1070 pc
+= 8; /* after the delay slot */
1074 case 17: /* BGEZAL */
1075 case 19: /* BGEZALL */
1076 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1077 pc
+= mips32_relative_offset (inst
) + 4;
1079 pc
+= 8; /* after the delay slot */
1081 /* All of the other instructions in the REGIMM category */
1086 break; /* end REGIMM */
1091 reg
= jtype_target (inst
) << 2;
1092 /* Upper four bits get never changed... */
1093 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1096 /* FIXME case JALX : */
1099 reg
= jtype_target (inst
) << 2;
1100 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1101 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1103 break; /* The new PC will be alternate mode */
1104 case 4: /* BEQ, BEQL */
1106 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1107 get_frame_register_signed (frame
, itype_rt (inst
)))
1108 pc
+= mips32_relative_offset (inst
) + 4;
1112 case 5: /* BNE, BNEL */
1114 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1115 get_frame_register_signed (frame
, itype_rt (inst
)))
1116 pc
+= mips32_relative_offset (inst
) + 4;
1120 case 6: /* BLEZ, BLEZL */
1121 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1122 pc
+= mips32_relative_offset (inst
) + 4;
1128 greater_branch
: /* BGTZ, BGTZL */
1129 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1130 pc
+= mips32_relative_offset (inst
) + 4;
1137 } /* mips32_next_pc */
1139 /* Decoding the next place to set a breakpoint is irregular for the
1140 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1141 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1142 We dont want to set a single step instruction on the extend instruction
1146 /* Lots of mips16 instruction formats */
1147 /* Predicting jumps requires itype,ritype,i8type
1148 and their extensions extItype,extritype,extI8type
1150 enum mips16_inst_fmts
1152 itype
, /* 0 immediate 5,10 */
1153 ritype
, /* 1 5,3,8 */
1154 rrtype
, /* 2 5,3,3,5 */
1155 rritype
, /* 3 5,3,3,5 */
1156 rrrtype
, /* 4 5,3,3,3,2 */
1157 rriatype
, /* 5 5,3,3,1,4 */
1158 shifttype
, /* 6 5,3,3,3,2 */
1159 i8type
, /* 7 5,3,8 */
1160 i8movtype
, /* 8 5,3,3,5 */
1161 i8mov32rtype
, /* 9 5,3,5,3 */
1162 i64type
, /* 10 5,3,8 */
1163 ri64type
, /* 11 5,3,3,5 */
1164 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1165 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1166 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1167 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1168 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1169 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1170 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1171 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1172 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1173 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1175 /* I am heaping all the fields of the formats into one structure and
1176 then, only the fields which are involved in instruction extension */
1180 unsigned int regx
; /* Function in i8 type */
1185 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1186 for the bits which make up the immediatate extension. */
1189 extended_offset (unsigned int extension
)
1192 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1194 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1196 value
|= extension
& 0x01f; /* extract 4:0 */
1200 /* Only call this function if you know that this is an extendable
1201 instruction. It won't malfunction, but why make excess remote memory
1202 references? If the immediate operands get sign extended or something,
1203 do it after the extension is performed. */
1204 /* FIXME: Every one of these cases needs to worry about sign extension
1205 when the offset is to be used in relative addressing. */
1208 fetch_mips_16 (CORE_ADDR pc
)
1211 pc
&= 0xfffffffe; /* clear the low order bit */
1212 target_read_memory (pc
, buf
, 2);
1213 return extract_unsigned_integer (buf
, 2);
1217 unpack_mips16 (CORE_ADDR pc
,
1218 unsigned int extension
,
1220 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1225 switch (insn_format
)
1232 value
= extended_offset (extension
);
1233 value
= value
<< 11; /* rom for the original value */
1234 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1238 value
= inst
& 0x7ff;
1239 /* FIXME : Consider sign extension */
1248 { /* A register identifier and an offset */
1249 /* Most of the fields are the same as I type but the
1250 immediate value is of a different length */
1254 value
= extended_offset (extension
);
1255 value
= value
<< 8; /* from the original instruction */
1256 value
|= inst
& 0xff; /* eleven bits from instruction */
1257 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1258 if (value
& 0x4000) /* test the sign bit , bit 26 */
1260 value
&= ~0x3fff; /* remove the sign bit */
1266 value
= inst
& 0xff; /* 8 bits */
1267 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1268 /* FIXME: Do sign extension , this format needs it */
1269 if (value
& 0x80) /* THIS CONFUSES ME */
1271 value
&= 0xef; /* remove the sign bit */
1281 unsigned long value
;
1282 unsigned int nexthalf
;
1283 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1284 value
= value
<< 16;
1285 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1293 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1295 upk
->offset
= offset
;
1302 add_offset_16 (CORE_ADDR pc
, int offset
)
1304 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1308 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1309 unsigned int extension
, unsigned int insn
)
1311 int op
= (insn
>> 11);
1314 case 2: /* Branch */
1317 struct upk_mips16 upk
;
1318 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1319 offset
= upk
.offset
;
1325 pc
+= (offset
<< 1) + 2;
1328 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1330 struct upk_mips16 upk
;
1331 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1332 pc
= add_offset_16 (pc
, upk
.offset
);
1333 if ((insn
>> 10) & 0x01) /* Exchange mode */
1334 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1341 struct upk_mips16 upk
;
1343 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1344 reg
= get_frame_register_signed (frame
, upk
.regx
);
1346 pc
+= (upk
.offset
<< 1) + 2;
1353 struct upk_mips16 upk
;
1355 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1356 reg
= get_frame_register_signed (frame
, upk
.regx
);
1358 pc
+= (upk
.offset
<< 1) + 2;
1363 case 12: /* I8 Formats btez btnez */
1365 struct upk_mips16 upk
;
1367 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1368 /* upk.regx contains the opcode */
1369 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1370 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1371 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1372 /* pc = add_offset_16(pc,upk.offset) ; */
1373 pc
+= (upk
.offset
<< 1) + 2;
1378 case 29: /* RR Formats JR, JALR, JALR-RA */
1380 struct upk_mips16 upk
;
1381 /* upk.fmt = rrtype; */
1386 upk
.regx
= (insn
>> 8) & 0x07;
1387 upk
.regy
= (insn
>> 5) & 0x07;
1395 break; /* Function return instruction */
1401 break; /* BOGUS Guess */
1403 pc
= get_frame_register_signed (frame
, reg
);
1410 /* This is an instruction extension. Fetch the real instruction
1411 (which follows the extension) and decode things based on
1415 pc
= extended_mips16_next_pc (frame
, pc
, insn
, fetch_mips_16 (pc
));
1428 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1430 unsigned int insn
= fetch_mips_16 (pc
);
1431 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1434 /* The mips_next_pc function supports single_step when the remote
1435 target monitor or stub is not developed enough to do a single_step.
1436 It works by decoding the current instruction and predicting where a
1437 branch will go. This isnt hard because all the data is available.
1438 The MIPS32 and MIPS16 variants are quite different. */
1440 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1442 if (is_mips16_addr (pc
))
1443 return mips16_next_pc (frame
, pc
);
1445 return mips32_next_pc (frame
, pc
);
1448 struct mips_frame_cache
1451 struct trad_frame_saved_reg
*saved_regs
;
1454 /* Set a register's saved stack address in temp_saved_regs. If an
1455 address has already been set for this register, do nothing; this
1456 way we will only recognize the first save of a given register in a
1459 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1460 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1461 Strictly speaking, only the second range is used as it is only second
1462 range (the ABI instead of ISA registers) that comes into play when finding
1463 saved registers in a frame. */
1466 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1469 if (this_cache
!= NULL
1470 && this_cache
->saved_regs
[regnum
].addr
== -1)
1472 this_cache
->saved_regs
[regnum
1473 + 0 * gdbarch_num_regs (current_gdbarch
)].addr
1475 this_cache
->saved_regs
[regnum
1476 + 1 * gdbarch_num_regs (current_gdbarch
)].addr
1482 /* Fetch the immediate value from a MIPS16 instruction.
1483 If the previous instruction was an EXTEND, use it to extend
1484 the upper bits of the immediate value. This is a helper function
1485 for mips16_scan_prologue. */
1488 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1489 unsigned short inst
, /* current instruction */
1490 int nbits
, /* number of bits in imm field */
1491 int scale
, /* scale factor to be applied to imm */
1492 int is_signed
) /* is the imm field signed? */
1496 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1498 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1499 if (offset
& 0x8000) /* check for negative extend */
1500 offset
= 0 - (0x10000 - (offset
& 0xffff));
1501 return offset
| (inst
& 0x1f);
1505 int max_imm
= 1 << nbits
;
1506 int mask
= max_imm
- 1;
1507 int sign_bit
= max_imm
>> 1;
1509 offset
= inst
& mask
;
1510 if (is_signed
&& (offset
& sign_bit
))
1511 offset
= 0 - (max_imm
- offset
);
1512 return offset
* scale
;
1517 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1518 the associated FRAME_CACHE if not null.
1519 Return the address of the first instruction past the prologue. */
1522 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1523 struct frame_info
*next_frame
,
1524 struct mips_frame_cache
*this_cache
)
1527 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1529 long frame_offset
= 0; /* Size of stack frame. */
1530 long frame_adjust
= 0; /* Offset of FP from SP. */
1531 int frame_reg
= MIPS_SP_REGNUM
;
1532 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1533 unsigned inst
= 0; /* current instruction */
1534 unsigned entry_inst
= 0; /* the entry instruction */
1537 int extend_bytes
= 0;
1538 int prev_extend_bytes
;
1539 CORE_ADDR end_prologue_addr
= 0;
1540 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1542 /* Can be called when there's no process, and hence when there's no
1544 if (next_frame
!= NULL
)
1545 sp
= frame_unwind_register_signed (next_frame
,
1546 gdbarch_num_regs (gdbarch
)
1551 if (limit_pc
> start_pc
+ 200)
1552 limit_pc
= start_pc
+ 200;
1554 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1556 /* Save the previous instruction. If it's an EXTEND, we'll extract
1557 the immediate offset extension from it in mips16_get_imm. */
1560 /* Fetch and decode the instruction. */
1561 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1563 /* Normally we ignore extend instructions. However, if it is
1564 not followed by a valid prologue instruction, then this
1565 instruction is not part of the prologue either. We must
1566 remember in this case to adjust the end_prologue_addr back
1568 if ((inst
& 0xf800) == 0xf000) /* extend */
1570 extend_bytes
= MIPS_INSN16_SIZE
;
1574 prev_extend_bytes
= extend_bytes
;
1577 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1578 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1580 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1581 if (offset
< 0) /* negative stack adjustment? */
1582 frame_offset
-= offset
;
1584 /* Exit loop if a positive stack adjustment is found, which
1585 usually means that the stack cleanup code in the function
1586 epilogue is reached. */
1589 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1591 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1592 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1593 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1595 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1597 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1598 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1599 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1601 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1603 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1604 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1606 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1608 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1609 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1611 else if (inst
== 0x673d) /* move $s1, $sp */
1616 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1618 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1619 frame_addr
= sp
+ offset
;
1621 frame_adjust
= offset
;
1623 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1625 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1626 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1627 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1629 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1631 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1632 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1633 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1635 else if ((inst
& 0xf81f) == 0xe809
1636 && (inst
& 0x700) != 0x700) /* entry */
1637 entry_inst
= inst
; /* save for later processing */
1638 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1639 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1640 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1642 /* This instruction is part of the prologue, but we don't
1643 need to do anything special to handle it. */
1647 /* This instruction is not an instruction typically found
1648 in a prologue, so we must have reached the end of the
1650 if (end_prologue_addr
== 0)
1651 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1655 /* The entry instruction is typically the first instruction in a function,
1656 and it stores registers at offsets relative to the value of the old SP
1657 (before the prologue). But the value of the sp parameter to this
1658 function is the new SP (after the prologue has been executed). So we
1659 can't calculate those offsets until we've seen the entire prologue,
1660 and can calculate what the old SP must have been. */
1661 if (entry_inst
!= 0)
1663 int areg_count
= (entry_inst
>> 8) & 7;
1664 int sreg_count
= (entry_inst
>> 6) & 3;
1666 /* The entry instruction always subtracts 32 from the SP. */
1669 /* Now we can calculate what the SP must have been at the
1670 start of the function prologue. */
1673 /* Check if a0-a3 were saved in the caller's argument save area. */
1674 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1676 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1677 offset
+= mips_abi_regsize (gdbarch
);
1680 /* Check if the ra register was pushed on the stack. */
1682 if (entry_inst
& 0x20)
1684 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1685 offset
-= mips_abi_regsize (gdbarch
);
1688 /* Check if the s0 and s1 registers were pushed on the stack. */
1689 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1691 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1692 offset
-= mips_abi_regsize (gdbarch
);
1696 if (this_cache
!= NULL
)
1699 (frame_unwind_register_signed (next_frame
,
1700 gdbarch_num_regs (gdbarch
) + frame_reg
)
1701 + frame_offset
- frame_adjust
);
1702 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1703 be able to get rid of the assignment below, evetually. But it's
1704 still needed for now. */
1705 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1706 + mips_regnum (gdbarch
)->pc
]
1707 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1710 /* If we didn't reach the end of the prologue when scanning the function
1711 instructions, then set end_prologue_addr to the address of the
1712 instruction immediately after the last one we scanned. */
1713 if (end_prologue_addr
== 0)
1714 end_prologue_addr
= cur_pc
;
1716 return end_prologue_addr
;
1719 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1720 Procedures that use the 32-bit instruction set are handled by the
1721 mips_insn32 unwinder. */
1723 static struct mips_frame_cache
*
1724 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1726 struct mips_frame_cache
*cache
;
1728 if ((*this_cache
) != NULL
)
1729 return (*this_cache
);
1730 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1731 (*this_cache
) = cache
;
1732 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1734 /* Analyze the function prologue. */
1736 const CORE_ADDR pc
=
1737 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1738 CORE_ADDR start_addr
;
1740 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1741 if (start_addr
== 0)
1742 start_addr
= heuristic_proc_start (pc
);
1743 /* We can't analyze the prologue if we couldn't find the begining
1745 if (start_addr
== 0)
1748 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1751 /* gdbarch_sp_regnum contains the value and not the address. */
1752 trad_frame_set_value (cache
->saved_regs
,
1753 gdbarch_num_regs (get_frame_arch (next_frame
))
1757 return (*this_cache
);
1761 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1762 struct frame_id
*this_id
)
1764 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1766 (*this_id
) = frame_id_build (info
->base
,
1767 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1771 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1773 int regnum
, int *optimizedp
,
1774 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1775 int *realnump
, gdb_byte
*valuep
)
1777 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1779 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1780 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1783 static const struct frame_unwind mips_insn16_frame_unwind
=
1786 mips_insn16_frame_this_id
,
1787 mips_insn16_frame_prev_register
1790 static const struct frame_unwind
*
1791 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1793 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1794 if (mips_pc_is_mips16 (pc
))
1795 return &mips_insn16_frame_unwind
;
1800 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1803 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1808 static const struct frame_base mips_insn16_frame_base
=
1810 &mips_insn16_frame_unwind
,
1811 mips_insn16_frame_base_address
,
1812 mips_insn16_frame_base_address
,
1813 mips_insn16_frame_base_address
1816 static const struct frame_base
*
1817 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1819 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1820 return &mips_insn16_frame_base
;
1825 /* Mark all the registers as unset in the saved_regs array
1826 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1829 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1831 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1835 const int num_regs
= gdbarch_num_regs (current_gdbarch
);
1838 for (i
= 0; i
< num_regs
; i
++)
1840 this_cache
->saved_regs
[i
].addr
= -1;
1845 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1846 the associated FRAME_CACHE if not null.
1847 Return the address of the first instruction past the prologue. */
1850 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1851 struct frame_info
*next_frame
,
1852 struct mips_frame_cache
*this_cache
)
1855 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1858 int frame_reg
= MIPS_SP_REGNUM
;
1860 CORE_ADDR end_prologue_addr
= 0;
1861 int seen_sp_adjust
= 0;
1862 int load_immediate_bytes
= 0;
1863 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1865 /* Can be called when there's no process, and hence when there's no
1867 if (next_frame
!= NULL
)
1868 sp
= frame_unwind_register_signed (next_frame
,
1869 gdbarch_num_regs (gdbarch
)
1874 if (limit_pc
> start_pc
+ 200)
1875 limit_pc
= start_pc
+ 200;
1880 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1882 unsigned long inst
, high_word
, low_word
;
1885 /* Fetch the instruction. */
1886 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1888 /* Save some code by pre-extracting some useful fields. */
1889 high_word
= (inst
>> 16) & 0xffff;
1890 low_word
= inst
& 0xffff;
1891 reg
= high_word
& 0x1f;
1893 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1894 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1895 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1897 if (low_word
& 0x8000) /* negative stack adjustment? */
1898 frame_offset
+= 0x10000 - low_word
;
1900 /* Exit loop if a positive stack adjustment is found, which
1901 usually means that the stack cleanup code in the function
1902 epilogue is reached. */
1906 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1908 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1910 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1912 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1913 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1915 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1917 /* Old gcc frame, r30 is virtual frame pointer. */
1918 if ((long) low_word
!= frame_offset
)
1919 frame_addr
= sp
+ low_word
;
1920 else if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1922 unsigned alloca_adjust
;
1925 frame_addr
= frame_unwind_register_signed
1926 (next_frame
, gdbarch_num_regs (gdbarch
) + 30);
1928 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1929 if (alloca_adjust
> 0)
1931 /* FP > SP + frame_size. This may be because of
1932 an alloca or somethings similar. Fix sp to
1933 "pre-alloca" value, and try again. */
1934 sp
+= alloca_adjust
;
1935 /* Need to reset the status of all registers. Otherwise,
1936 we will hit a guard that prevents the new address
1937 for each register to be recomputed during the second
1939 reset_saved_regs (this_cache
);
1944 /* move $30,$sp. With different versions of gas this will be either
1945 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1946 Accept any one of these. */
1947 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1949 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1950 if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1952 unsigned alloca_adjust
;
1955 frame_addr
= frame_unwind_register_signed
1956 (next_frame
, gdbarch_num_regs (gdbarch
) + 30);
1958 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1959 if (alloca_adjust
> 0)
1961 /* FP > SP + frame_size. This may be because of
1962 an alloca or somethings similar. Fix sp to
1963 "pre-alloca" value, and try again. */
1965 /* Need to reset the status of all registers. Otherwise,
1966 we will hit a guard that prevents the new address
1967 for each register to be recomputed during the second
1969 reset_saved_regs (this_cache
);
1974 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1976 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
1978 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1979 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1980 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1981 || high_word
== 0x3c1c /* lui $gp,n */
1982 || high_word
== 0x279c /* addiu $gp,$gp,n */
1983 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1984 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
1987 /* These instructions are part of the prologue, but we don't
1988 need to do anything special to handle them. */
1990 /* The instructions below load $at or $t0 with an immediate
1991 value in preparation for a stack adjustment via
1992 subu $sp,$sp,[$at,$t0]. These instructions could also
1993 initialize a local variable, so we accept them only before
1994 a stack adjustment instruction was seen. */
1995 else if (!seen_sp_adjust
1996 && (high_word
== 0x3c01 /* lui $at,n */
1997 || high_word
== 0x3c08 /* lui $t0,n */
1998 || high_word
== 0x3421 /* ori $at,$at,n */
1999 || high_word
== 0x3508 /* ori $t0,$t0,n */
2000 || high_word
== 0x3401 /* ori $at,$zero,n */
2001 || high_word
== 0x3408 /* ori $t0,$zero,n */
2004 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2008 /* This instruction is not an instruction typically found
2009 in a prologue, so we must have reached the end of the
2011 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2012 loop now? Why would we need to continue scanning the function
2014 if (end_prologue_addr
== 0)
2015 end_prologue_addr
= cur_pc
;
2019 if (this_cache
!= NULL
)
2022 (frame_unwind_register_signed (next_frame
,
2023 gdbarch_num_regs (gdbarch
) + frame_reg
)
2025 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2026 this assignment below, eventually. But it's still needed
2028 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2029 + mips_regnum (gdbarch
)->pc
]
2030 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2034 /* If we didn't reach the end of the prologue when scanning the function
2035 instructions, then set end_prologue_addr to the address of the
2036 instruction immediately after the last one we scanned. */
2037 /* brobecker/2004-10-10: I don't think this would ever happen, but
2038 we may as well be careful and do our best if we have a null
2039 end_prologue_addr. */
2040 if (end_prologue_addr
== 0)
2041 end_prologue_addr
= cur_pc
;
2043 /* In a frameless function, we might have incorrectly
2044 skipped some load immediate instructions. Undo the skipping
2045 if the load immediate was not followed by a stack adjustment. */
2046 if (load_immediate_bytes
&& !seen_sp_adjust
)
2047 end_prologue_addr
-= load_immediate_bytes
;
2049 return end_prologue_addr
;
2052 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2053 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2054 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2057 static struct mips_frame_cache
*
2058 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2060 struct mips_frame_cache
*cache
;
2062 if ((*this_cache
) != NULL
)
2063 return (*this_cache
);
2065 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2066 (*this_cache
) = cache
;
2067 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2069 /* Analyze the function prologue. */
2071 const CORE_ADDR pc
=
2072 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2073 CORE_ADDR start_addr
;
2075 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2076 if (start_addr
== 0)
2077 start_addr
= heuristic_proc_start (pc
);
2078 /* We can't analyze the prologue if we couldn't find the begining
2080 if (start_addr
== 0)
2083 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
2086 /* gdbarch_sp_regnum contains the value and not the address. */
2087 trad_frame_set_value (cache
->saved_regs
,
2088 gdbarch_num_regs (get_frame_arch (next_frame
))
2092 return (*this_cache
);
2096 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2097 struct frame_id
*this_id
)
2099 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2101 (*this_id
) = frame_id_build (info
->base
,
2102 frame_func_unwind (next_frame
, NORMAL_FRAME
));
2106 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2108 int regnum
, int *optimizedp
,
2109 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2110 int *realnump
, gdb_byte
*valuep
)
2112 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2114 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2115 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2118 static const struct frame_unwind mips_insn32_frame_unwind
=
2121 mips_insn32_frame_this_id
,
2122 mips_insn32_frame_prev_register
2125 static const struct frame_unwind
*
2126 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2128 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2129 if (! mips_pc_is_mips16 (pc
))
2130 return &mips_insn32_frame_unwind
;
2135 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2138 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2143 static const struct frame_base mips_insn32_frame_base
=
2145 &mips_insn32_frame_unwind
,
2146 mips_insn32_frame_base_address
,
2147 mips_insn32_frame_base_address
,
2148 mips_insn32_frame_base_address
2151 static const struct frame_base
*
2152 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2154 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2155 return &mips_insn32_frame_base
;
2160 static struct trad_frame_cache
*
2161 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2164 CORE_ADDR start_addr
;
2165 CORE_ADDR stack_addr
;
2166 struct trad_frame_cache
*this_trad_cache
;
2167 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2169 if ((*this_cache
) != NULL
)
2170 return (*this_cache
);
2171 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2172 (*this_cache
) = this_trad_cache
;
2174 /* The return address is in the link register. */
2175 trad_frame_set_reg_realreg (this_trad_cache
,
2176 gdbarch_pc_regnum (gdbarch
),
2177 (gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
));
2179 /* Frame ID, since it's a frameless / stackless function, no stack
2180 space is allocated and SP on entry is the current SP. */
2181 pc
= frame_pc_unwind (next_frame
);
2182 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2183 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2184 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2186 /* Assume that the frame's base is the same as the
2188 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2190 return this_trad_cache
;
2194 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2195 struct frame_id
*this_id
)
2197 struct trad_frame_cache
*this_trad_cache
2198 = mips_stub_frame_cache (next_frame
, this_cache
);
2199 trad_frame_get_id (this_trad_cache
, this_id
);
2203 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2205 int regnum
, int *optimizedp
,
2206 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2207 int *realnump
, gdb_byte
*valuep
)
2209 struct trad_frame_cache
*this_trad_cache
2210 = mips_stub_frame_cache (next_frame
, this_cache
);
2211 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2212 lvalp
, addrp
, realnump
, valuep
);
2215 static const struct frame_unwind mips_stub_frame_unwind
=
2218 mips_stub_frame_this_id
,
2219 mips_stub_frame_prev_register
2222 static const struct frame_unwind
*
2223 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2226 struct obj_section
*s
;
2227 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2229 /* Use the stub unwinder for unreadable code. */
2230 if (target_read_memory (frame_pc_unwind (next_frame
), dummy
, 4) != 0)
2231 return &mips_stub_frame_unwind
;
2233 if (in_plt_section (pc
, NULL
))
2234 return &mips_stub_frame_unwind
;
2236 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2237 s
= find_pc_section (pc
);
2240 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2241 ".MIPS.stubs") == 0)
2242 return &mips_stub_frame_unwind
;
2248 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2251 struct trad_frame_cache
*this_trad_cache
2252 = mips_stub_frame_cache (next_frame
, this_cache
);
2253 return trad_frame_get_this_base (this_trad_cache
);
2256 static const struct frame_base mips_stub_frame_base
=
2258 &mips_stub_frame_unwind
,
2259 mips_stub_frame_base_address
,
2260 mips_stub_frame_base_address
,
2261 mips_stub_frame_base_address
2264 static const struct frame_base
*
2265 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2267 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2268 return &mips_stub_frame_base
;
2273 /* mips_addr_bits_remove - remove useless address bits */
2276 mips_addr_bits_remove (CORE_ADDR addr
)
2278 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2279 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2280 /* This hack is a work-around for existing boards using PMON, the
2281 simulator, and any other 64-bit targets that doesn't have true
2282 64-bit addressing. On these targets, the upper 32 bits of
2283 addresses are ignored by the hardware. Thus, the PC or SP are
2284 likely to have been sign extended to all 1s by instruction
2285 sequences that load 32-bit addresses. For example, a typical
2286 piece of code that loads an address is this:
2288 lui $r2, <upper 16 bits>
2289 ori $r2, <lower 16 bits>
2291 But the lui sign-extends the value such that the upper 32 bits
2292 may be all 1s. The workaround is simply to mask off these
2293 bits. In the future, gcc may be changed to support true 64-bit
2294 addressing, and this masking will have to be disabled. */
2295 return addr
&= 0xffffffffUL
;
2300 /* mips_software_single_step() is called just before we want to resume
2301 the inferior, if we want to single-step it but there is no hardware
2302 or kernel single-step support (MIPS on GNU/Linux for example). We find
2303 the target of the coming instruction and breakpoint it. */
2306 mips_software_single_step (struct frame_info
*frame
)
2308 CORE_ADDR pc
, next_pc
;
2310 pc
= get_frame_pc (frame
);
2311 next_pc
= mips_next_pc (frame
, pc
);
2313 insert_single_step_breakpoint (next_pc
);
2317 /* Test whether the PC points to the return instruction at the
2318 end of a function. */
2321 mips_about_to_return (CORE_ADDR pc
)
2323 if (mips_pc_is_mips16 (pc
))
2324 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2325 generates a "jr $ra"; other times it generates code to load
2326 the return address from the stack to an accessible register (such
2327 as $a3), then a "jr" using that register. This second case
2328 is almost impossible to distinguish from an indirect jump
2329 used for switch statements, so we don't even try. */
2330 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2332 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2336 /* This fencepost looks highly suspicious to me. Removing it also
2337 seems suspicious as it could affect remote debugging across serial
2341 heuristic_proc_start (CORE_ADDR pc
)
2348 pc
= gdbarch_addr_bits_remove (current_gdbarch
, pc
);
2350 fence
= start_pc
- heuristic_fence_post
;
2354 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2355 fence
= VM_MIN_ADDRESS
;
2357 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2359 /* search back for previous return */
2360 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2361 if (start_pc
< fence
)
2363 /* It's not clear to me why we reach this point when
2364 stop_soon, but with this test, at least we
2365 don't print out warnings for every child forked (eg, on
2366 decstation). 22apr93 rich@cygnus.com. */
2367 if (stop_soon
== NO_STOP_QUIETLY
)
2369 static int blurb_printed
= 0;
2371 warning (_("GDB can't find the start of the function at 0x%s."),
2376 /* This actually happens frequently in embedded
2377 development, when you first connect to a board
2378 and your stack pointer and pc are nowhere in
2379 particular. This message needs to give people
2380 in that situation enough information to
2381 determine that it's no big deal. */
2382 printf_filtered ("\n\
2383 GDB is unable to find the start of the function at 0x%s\n\
2384 and thus can't determine the size of that function's stack frame.\n\
2385 This means that GDB may be unable to access that stack frame, or\n\
2386 the frames below it.\n\
2387 This problem is most likely caused by an invalid program counter or\n\
2389 However, if you think GDB should simply search farther back\n\
2390 from 0x%s for code which looks like the beginning of a\n\
2391 function, you can increase the range of the search using the `set\n\
2392 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2399 else if (mips_pc_is_mips16 (start_pc
))
2401 unsigned short inst
;
2403 /* On MIPS16, any one of the following is likely to be the
2404 start of a function:
2410 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2411 inst
= mips_fetch_instruction (start_pc
);
2412 if ((inst
& 0xff80) == 0x6480) /* save */
2414 if (start_pc
- instlen
>= fence
)
2416 inst
= mips_fetch_instruction (start_pc
- instlen
);
2417 if ((inst
& 0xf800) == 0xf000) /* extend */
2418 start_pc
-= instlen
;
2422 else if (((inst
& 0xf81f) == 0xe809
2423 && (inst
& 0x700) != 0x700) /* entry */
2424 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2425 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2426 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2428 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2429 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2434 else if (mips_about_to_return (start_pc
))
2436 /* Skip return and its delay slot. */
2437 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2444 struct mips_objfile_private
2450 /* According to the current ABI, should the type be passed in a
2451 floating-point register (assuming that there is space)? When there
2452 is no FPU, FP are not even considered as possible candidates for
2453 FP registers and, consequently this returns false - forces FP
2454 arguments into integer registers. */
2457 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2459 return ((typecode
== TYPE_CODE_FLT
2461 && (typecode
== TYPE_CODE_STRUCT
2462 || typecode
== TYPE_CODE_UNION
)
2463 && TYPE_NFIELDS (arg_type
) == 1
2464 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2466 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2469 /* On o32, argument passing in GPRs depends on the alignment of the type being
2470 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2473 mips_type_needs_double_align (struct type
*type
)
2475 enum type_code typecode
= TYPE_CODE (type
);
2477 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2479 else if (typecode
== TYPE_CODE_STRUCT
)
2481 if (TYPE_NFIELDS (type
) < 1)
2483 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2485 else if (typecode
== TYPE_CODE_UNION
)
2489 n
= TYPE_NFIELDS (type
);
2490 for (i
= 0; i
< n
; i
++)
2491 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2498 /* Adjust the address downward (direction of stack growth) so that it
2499 is correctly aligned for a new stack frame. */
2501 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2503 return align_down (addr
, 16);
2507 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2508 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2509 int nargs
, struct value
**args
, CORE_ADDR sp
,
2510 int struct_return
, CORE_ADDR struct_addr
)
2516 int stack_offset
= 0;
2517 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2518 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2519 int regsize
= mips_abi_regsize (gdbarch
);
2521 /* For shared libraries, "t9" needs to point at the function
2523 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2525 /* Set the return address register to point to the entry point of
2526 the program, where a breakpoint lies in wait. */
2527 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2529 /* First ensure that the stack and structure return address (if any)
2530 are properly aligned. The stack has to be at least 64-bit
2531 aligned even on 32-bit machines, because doubles must be 64-bit
2532 aligned. For n32 and n64, stack frames need to be 128-bit
2533 aligned, so we round to this widest known alignment. */
2535 sp
= align_down (sp
, 16);
2536 struct_addr
= align_down (struct_addr
, 16);
2538 /* Now make space on the stack for the args. We allocate more
2539 than necessary for EABI, because the first few arguments are
2540 passed in registers, but that's OK. */
2541 for (argnum
= 0; argnum
< nargs
; argnum
++)
2542 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2543 sp
-= align_up (len
, 16);
2546 fprintf_unfiltered (gdb_stdlog
,
2547 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2548 paddr_nz (sp
), (long) align_up (len
, 16));
2550 /* Initialize the integer and float register pointers. */
2551 argreg
= MIPS_A0_REGNUM
;
2552 float_argreg
= mips_fpa0_regnum (gdbarch
);
2554 /* The struct_return pointer occupies the first parameter-passing reg. */
2558 fprintf_unfiltered (gdb_stdlog
,
2559 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2560 argreg
, paddr_nz (struct_addr
));
2561 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2564 /* Now load as many as possible of the first arguments into
2565 registers, and push the rest onto the stack. Loop thru args
2566 from first to last. */
2567 for (argnum
= 0; argnum
< nargs
; argnum
++)
2569 const gdb_byte
*val
;
2570 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2571 struct value
*arg
= args
[argnum
];
2572 struct type
*arg_type
= check_typedef (value_type (arg
));
2573 int len
= TYPE_LENGTH (arg_type
);
2574 enum type_code typecode
= TYPE_CODE (arg_type
);
2577 fprintf_unfiltered (gdb_stdlog
,
2578 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2579 argnum
+ 1, len
, (int) typecode
);
2581 /* The EABI passes structures that do not fit in a register by
2584 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2586 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2587 typecode
= TYPE_CODE_PTR
;
2591 fprintf_unfiltered (gdb_stdlog
, " push");
2594 val
= value_contents (arg
);
2596 /* 32-bit ABIs always start floating point arguments in an
2597 even-numbered floating point register. Round the FP register
2598 up before the check to see if there are any FP registers
2599 left. Non MIPS_EABI targets also pass the FP in the integer
2600 registers so also round up normal registers. */
2601 if (regsize
< 8 && fp_register_arg_p (typecode
, arg_type
))
2603 if ((float_argreg
& 1))
2607 /* Floating point arguments passed in registers have to be
2608 treated specially. On 32-bit architectures, doubles
2609 are passed in register pairs; the even register gets
2610 the low word, and the odd register gets the high word.
2611 On non-EABI processors, the first two floating point arguments are
2612 also copied to general registers, because MIPS16 functions
2613 don't use float registers for arguments. This duplication of
2614 arguments in general registers can't hurt non-MIPS16 functions
2615 because those registers are normally skipped. */
2616 /* MIPS_EABI squeezes a struct that contains a single floating
2617 point value into an FP register instead of pushing it onto the
2619 if (fp_register_arg_p (typecode
, arg_type
)
2620 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2622 /* EABI32 will pass doubles in consecutive registers, even on
2623 64-bit cores. At one time, we used to check the size of
2624 `float_argreg' to determine whether or not to pass doubles
2625 in consecutive registers, but this is not sufficient for
2626 making the ABI determination. */
2627 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2629 int low_offset
= gdbarch_byte_order (gdbarch
)
2630 == BFD_ENDIAN_BIG
? 4 : 0;
2631 unsigned long regval
;
2633 /* Write the low word of the double to the even register(s). */
2634 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2636 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2637 float_argreg
, phex (regval
, 4));
2638 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2640 /* Write the high word of the double to the odd register(s). */
2641 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2643 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2644 float_argreg
, phex (regval
, 4));
2645 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2649 /* This is a floating point value that fits entirely
2650 in a single register. */
2651 /* On 32 bit ABI's the float_argreg is further adjusted
2652 above to ensure that it is even register aligned. */
2653 LONGEST regval
= extract_unsigned_integer (val
, len
);
2655 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2656 float_argreg
, phex (regval
, len
));
2657 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2662 /* Copy the argument to general registers or the stack in
2663 register-sized pieces. Large arguments are split between
2664 registers and stack. */
2665 /* Note: structs whose size is not a multiple of regsize
2666 are treated specially: Irix cc passes
2667 them in registers where gcc sometimes puts them on the
2668 stack. For maximum compatibility, we will put them in
2670 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2672 /* Note: Floating-point values that didn't fit into an FP
2673 register are only written to memory. */
2676 /* Remember if the argument was written to the stack. */
2677 int stack_used_p
= 0;
2678 int partial_len
= (len
< regsize
? len
: regsize
);
2681 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2684 /* Write this portion of the argument to the stack. */
2685 if (argreg
> MIPS_LAST_ARG_REGNUM
2687 || fp_register_arg_p (typecode
, arg_type
))
2689 /* Should shorter than int integer values be
2690 promoted to int before being stored? */
2691 int longword_offset
= 0;
2694 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2697 && (typecode
== TYPE_CODE_INT
2698 || typecode
== TYPE_CODE_PTR
2699 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2700 longword_offset
= regsize
- len
;
2701 else if ((typecode
== TYPE_CODE_STRUCT
2702 || typecode
== TYPE_CODE_UNION
)
2703 && TYPE_LENGTH (arg_type
) < regsize
)
2704 longword_offset
= regsize
- len
;
2709 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2710 paddr_nz (stack_offset
));
2711 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2712 paddr_nz (longword_offset
));
2715 addr
= sp
+ stack_offset
+ longword_offset
;
2720 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2722 for (i
= 0; i
< partial_len
; i
++)
2724 fprintf_unfiltered (gdb_stdlog
, "%02x",
2728 write_memory (addr
, val
, partial_len
);
2731 /* Note!!! This is NOT an else clause. Odd sized
2732 structs may go thru BOTH paths. Floating point
2733 arguments will not. */
2734 /* Write this portion of the argument to a general
2735 purpose register. */
2736 if (argreg
<= MIPS_LAST_ARG_REGNUM
2737 && !fp_register_arg_p (typecode
, arg_type
))
2740 extract_unsigned_integer (val
, partial_len
);
2743 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2745 phex (regval
, regsize
));
2746 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2753 /* Compute the the offset into the stack at which we
2754 will copy the next parameter.
2756 In the new EABI (and the NABI32), the stack_offset
2757 only needs to be adjusted when it has been used. */
2760 stack_offset
+= align_up (partial_len
, regsize
);
2764 fprintf_unfiltered (gdb_stdlog
, "\n");
2767 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2769 /* Return adjusted stack pointer. */
2773 /* Determine the return value convention being used. */
2775 static enum return_value_convention
2776 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2777 struct type
*type
, struct regcache
*regcache
,
2778 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2780 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2781 return RETURN_VALUE_STRUCT_CONVENTION
;
2783 memset (readbuf
, 0, TYPE_LENGTH (type
));
2784 return RETURN_VALUE_REGISTER_CONVENTION
;
2788 /* N32/N64 ABI stuff. */
2790 /* Search for a naturally aligned double at OFFSET inside a struct
2791 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
2795 mips_n32n64_fp_arg_chunk_p (struct type
*arg_type
, int offset
)
2799 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
2802 if (MIPS_FPU_TYPE
!= MIPS_FPU_DOUBLE
)
2805 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
2808 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
2811 struct type
*field_type
;
2813 /* We're only looking at normal fields. */
2814 if (TYPE_FIELD_STATIC (arg_type
, i
)
2815 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
2818 /* If we have gone past the offset, there is no double to pass. */
2819 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
2823 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
2825 /* If this field is entirely before the requested offset, go
2826 on to the next one. */
2827 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
2830 /* If this is our special aligned double, we can stop. */
2831 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
2832 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
2835 /* This field starts at or before the requested offset, and
2836 overlaps it. If it is a structure, recurse inwards. */
2837 return mips_n32n64_fp_arg_chunk_p (field_type
, offset
- pos
);
2844 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2845 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2846 int nargs
, struct value
**args
, CORE_ADDR sp
,
2847 int struct_return
, CORE_ADDR struct_addr
)
2853 int stack_offset
= 0;
2854 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2855 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2857 /* For shared libraries, "t9" needs to point at the function
2859 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2861 /* Set the return address register to point to the entry point of
2862 the program, where a breakpoint lies in wait. */
2863 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2865 /* First ensure that the stack and structure return address (if any)
2866 are properly aligned. The stack has to be at least 64-bit
2867 aligned even on 32-bit machines, because doubles must be 64-bit
2868 aligned. For n32 and n64, stack frames need to be 128-bit
2869 aligned, so we round to this widest known alignment. */
2871 sp
= align_down (sp
, 16);
2872 struct_addr
= align_down (struct_addr
, 16);
2874 /* Now make space on the stack for the args. */
2875 for (argnum
= 0; argnum
< nargs
; argnum
++)
2876 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
2877 sp
-= align_up (len
, 16);
2880 fprintf_unfiltered (gdb_stdlog
,
2881 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2882 paddr_nz (sp
), (long) align_up (len
, 16));
2884 /* Initialize the integer and float register pointers. */
2885 argreg
= MIPS_A0_REGNUM
;
2886 float_argreg
= mips_fpa0_regnum (gdbarch
);
2888 /* The struct_return pointer occupies the first parameter-passing reg. */
2892 fprintf_unfiltered (gdb_stdlog
,
2893 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2894 argreg
, paddr_nz (struct_addr
));
2895 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2898 /* Now load as many as possible of the first arguments into
2899 registers, and push the rest onto the stack. Loop thru args
2900 from first to last. */
2901 for (argnum
= 0; argnum
< nargs
; argnum
++)
2903 const gdb_byte
*val
;
2904 struct value
*arg
= args
[argnum
];
2905 struct type
*arg_type
= check_typedef (value_type (arg
));
2906 int len
= TYPE_LENGTH (arg_type
);
2907 enum type_code typecode
= TYPE_CODE (arg_type
);
2910 fprintf_unfiltered (gdb_stdlog
,
2911 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2912 argnum
+ 1, len
, (int) typecode
);
2914 val
= value_contents (arg
);
2916 if (fp_register_arg_p (typecode
, arg_type
)
2917 && argreg
<= MIPS_LAST_ARG_REGNUM
)
2919 /* This is a floating point value that fits entirely
2920 in a single register. */
2921 LONGEST regval
= extract_unsigned_integer (val
, len
);
2923 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2924 float_argreg
, phex (regval
, len
));
2925 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
2928 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2929 argreg
, phex (regval
, len
));
2930 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2936 /* Copy the argument to general registers or the stack in
2937 register-sized pieces. Large arguments are split between
2938 registers and stack. */
2939 /* For N32/N64, structs, unions, or other composite types are
2940 treated as a sequence of doublewords, and are passed in integer
2941 or floating point registers as though they were simple scalar
2942 parameters to the extent that they fit, with any excess on the
2943 stack packed according to the normal memory layout of the
2945 The caller does not reserve space for the register arguments;
2946 the callee is responsible for reserving it if required. */
2947 /* Note: Floating-point values that didn't fit into an FP
2948 register are only written to memory. */
2951 /* Remember if the argument was written to the stack. */
2952 int stack_used_p
= 0;
2953 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
2956 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2959 if (fp_register_arg_p (typecode
, arg_type
))
2960 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM
);
2962 /* Write this portion of the argument to the stack. */
2963 if (argreg
> MIPS_LAST_ARG_REGNUM
)
2965 /* Should shorter than int integer values be
2966 promoted to int before being stored? */
2967 int longword_offset
= 0;
2970 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2972 if ((typecode
== TYPE_CODE_INT
2973 || typecode
== TYPE_CODE_PTR
2974 || typecode
== TYPE_CODE_FLT
)
2976 longword_offset
= MIPS64_REGSIZE
- len
;
2981 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2982 paddr_nz (stack_offset
));
2983 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2984 paddr_nz (longword_offset
));
2987 addr
= sp
+ stack_offset
+ longword_offset
;
2992 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2994 for (i
= 0; i
< partial_len
; i
++)
2996 fprintf_unfiltered (gdb_stdlog
, "%02x",
3000 write_memory (addr
, val
, partial_len
);
3003 /* Note!!! This is NOT an else clause. Odd sized
3004 structs may go thru BOTH paths. */
3005 /* Write this portion of the argument to a general
3006 purpose register. */
3007 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3010 extract_unsigned_integer (val
, partial_len
);
3012 /* A non-floating-point argument being passed in a
3013 general register. If a struct or union, and if
3014 the remaining length is smaller than the register
3015 size, we have to adjust the register value on
3018 It does not seem to be necessary to do the
3019 same for integral types. */
3021 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3022 && partial_len
< MIPS64_REGSIZE
3023 && (typecode
== TYPE_CODE_STRUCT
3024 || typecode
== TYPE_CODE_UNION
))
3025 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3029 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3031 phex (regval
, MIPS64_REGSIZE
));
3032 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3034 if (mips_n32n64_fp_arg_chunk_p (arg_type
,
3035 TYPE_LENGTH (arg_type
) - len
))
3038 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3040 phex (regval
, MIPS64_REGSIZE
));
3041 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3052 /* Compute the the offset into the stack at which we
3053 will copy the next parameter.
3055 In N32 (N64?), the stack_offset only needs to be
3056 adjusted when it has been used. */
3059 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3063 fprintf_unfiltered (gdb_stdlog
, "\n");
3066 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3068 /* Return adjusted stack pointer. */
3072 static enum return_value_convention
3073 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3074 struct type
*type
, struct regcache
*regcache
,
3075 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3077 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3079 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3081 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3082 if needed), as appropriate for the type. Composite results (struct,
3083 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3086 * A struct with only one or two floating point fields is returned in $f0
3087 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3090 * Any other struct or union results of at most 128 bits are returned in
3091 $2 (first 64 bits) and $3 (remainder, if necessary).
3093 * Larger composite results are handled by converting the function to a
3094 procedure with an implicit first parameter, which is a pointer to an area
3095 reserved by the caller to receive the result. [The o32-bit ABI requires
3096 that all composite results be handled by conversion to implicit first
3097 parameters. The MIPS/SGI Fortran implementation has always made a
3098 specific exception to return COMPLEX results in the floating point
3101 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
3102 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3103 return RETURN_VALUE_STRUCT_CONVENTION
;
3104 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3105 && TYPE_LENGTH (type
) == 16
3106 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3108 /* A 128-bit floating-point value fills both $f0 and $f2. The
3109 two registers are used in the same as memory order, so the
3110 eight bytes with the lower memory address are in $f0. */
3112 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3113 mips_xfer_register (gdbarch
, regcache
,
3114 gdbarch_num_regs (gdbarch
)
3115 + mips_regnum (gdbarch
)->fp0
,
3116 8, gdbarch_byte_order (gdbarch
),
3117 readbuf
, writebuf
, 0);
3118 mips_xfer_register (gdbarch
, regcache
,
3119 gdbarch_num_regs (gdbarch
)
3120 + mips_regnum (gdbarch
)->fp0
+ 2,
3121 8, gdbarch_byte_order (gdbarch
),
3122 readbuf
? readbuf
+ 8 : readbuf
,
3123 writebuf
? writebuf
+ 8 : writebuf
, 0);
3124 return RETURN_VALUE_REGISTER_CONVENTION
;
3126 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3127 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3129 /* A single or double floating-point value that fits in FP0. */
3131 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3132 mips_xfer_register (gdbarch
, regcache
,
3133 gdbarch_num_regs (gdbarch
)
3134 + mips_regnum (gdbarch
)->fp0
,
3136 gdbarch_byte_order (gdbarch
),
3137 readbuf
, writebuf
, 0);
3138 return RETURN_VALUE_REGISTER_CONVENTION
;
3140 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3141 && TYPE_NFIELDS (type
) <= 2
3142 && TYPE_NFIELDS (type
) >= 1
3143 && ((TYPE_NFIELDS (type
) == 1
3144 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3146 || (TYPE_NFIELDS (type
) == 2
3147 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3149 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3151 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3153 /* A struct that contains one or two floats. Each value is part
3154 in the least significant part of their floating point
3158 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3159 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3161 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3164 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3166 mips_xfer_register (gdbarch
, regcache
,
3167 gdbarch_num_regs (gdbarch
) + regnum
,
3168 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3169 gdbarch_byte_order (gdbarch
),
3170 readbuf
, writebuf
, offset
);
3172 return RETURN_VALUE_REGISTER_CONVENTION
;
3174 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3175 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3177 /* A structure or union. Extract the left justified value,
3178 regardless of the byte order. I.e. DO NOT USE
3182 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3183 offset
< TYPE_LENGTH (type
);
3184 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3186 int xfer
= register_size (gdbarch
, regnum
);
3187 if (offset
+ xfer
> TYPE_LENGTH (type
))
3188 xfer
= TYPE_LENGTH (type
) - offset
;
3190 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3191 offset
, xfer
, regnum
);
3192 mips_xfer_register (gdbarch
, regcache
,
3193 gdbarch_num_regs (gdbarch
) + regnum
,
3194 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3197 return RETURN_VALUE_REGISTER_CONVENTION
;
3201 /* A scalar extract each part but least-significant-byte
3205 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3206 offset
< TYPE_LENGTH (type
);
3207 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3209 int xfer
= register_size (gdbarch
, regnum
);
3210 if (offset
+ xfer
> TYPE_LENGTH (type
))
3211 xfer
= TYPE_LENGTH (type
) - offset
;
3213 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3214 offset
, xfer
, regnum
);
3215 mips_xfer_register (gdbarch
, regcache
,
3216 gdbarch_num_regs (gdbarch
) + regnum
,
3217 xfer
, gdbarch_byte_order (gdbarch
),
3218 readbuf
, writebuf
, offset
);
3220 return RETURN_VALUE_REGISTER_CONVENTION
;
3224 /* O32 ABI stuff. */
3227 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3228 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3229 int nargs
, struct value
**args
, CORE_ADDR sp
,
3230 int struct_return
, CORE_ADDR struct_addr
)
3236 int stack_offset
= 0;
3237 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3238 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3240 /* For shared libraries, "t9" needs to point at the function
3242 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3244 /* Set the return address register to point to the entry point of
3245 the program, where a breakpoint lies in wait. */
3246 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3248 /* First ensure that the stack and structure return address (if any)
3249 are properly aligned. The stack has to be at least 64-bit
3250 aligned even on 32-bit machines, because doubles must be 64-bit
3251 aligned. For n32 and n64, stack frames need to be 128-bit
3252 aligned, so we round to this widest known alignment. */
3254 sp
= align_down (sp
, 16);
3255 struct_addr
= align_down (struct_addr
, 16);
3257 /* Now make space on the stack for the args. */
3258 for (argnum
= 0; argnum
< nargs
; argnum
++)
3260 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3261 int arglen
= TYPE_LENGTH (arg_type
);
3263 /* Align to double-word if necessary. */
3264 if (mips_type_needs_double_align (arg_type
))
3265 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3266 /* Allocate space on the stack. */
3267 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3269 sp
-= align_up (len
, 16);
3272 fprintf_unfiltered (gdb_stdlog
,
3273 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3274 paddr_nz (sp
), (long) align_up (len
, 16));
3276 /* Initialize the integer and float register pointers. */
3277 argreg
= MIPS_A0_REGNUM
;
3278 float_argreg
= mips_fpa0_regnum (gdbarch
);
3280 /* The struct_return pointer occupies the first parameter-passing reg. */
3284 fprintf_unfiltered (gdb_stdlog
,
3285 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3286 argreg
, paddr_nz (struct_addr
));
3287 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3288 stack_offset
+= MIPS32_REGSIZE
;
3291 /* Now load as many as possible of the first arguments into
3292 registers, and push the rest onto the stack. Loop thru args
3293 from first to last. */
3294 for (argnum
= 0; argnum
< nargs
; argnum
++)
3296 const gdb_byte
*val
;
3297 struct value
*arg
= args
[argnum
];
3298 struct type
*arg_type
= check_typedef (value_type (arg
));
3299 int len
= TYPE_LENGTH (arg_type
);
3300 enum type_code typecode
= TYPE_CODE (arg_type
);
3303 fprintf_unfiltered (gdb_stdlog
,
3304 "mips_o32_push_dummy_call: %d len=%d type=%d",
3305 argnum
+ 1, len
, (int) typecode
);
3307 val
= value_contents (arg
);
3309 /* 32-bit ABIs always start floating point arguments in an
3310 even-numbered floating point register. Round the FP register
3311 up before the check to see if there are any FP registers
3312 left. O32/O64 targets also pass the FP in the integer
3313 registers so also round up normal registers. */
3314 if (fp_register_arg_p (typecode
, arg_type
))
3316 if ((float_argreg
& 1))
3320 /* Floating point arguments passed in registers have to be
3321 treated specially. On 32-bit architectures, doubles
3322 are passed in register pairs; the even register gets
3323 the low word, and the odd register gets the high word.
3324 On O32/O64, the first two floating point arguments are
3325 also copied to general registers, because MIPS16 functions
3326 don't use float registers for arguments. This duplication of
3327 arguments in general registers can't hurt non-MIPS16 functions
3328 because those registers are normally skipped. */
3330 if (fp_register_arg_p (typecode
, arg_type
)
3331 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3333 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3335 int low_offset
= gdbarch_byte_order (gdbarch
)
3336 == BFD_ENDIAN_BIG
? 4 : 0;
3337 unsigned long regval
;
3339 /* Write the low word of the double to the even register(s). */
3340 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3342 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3343 float_argreg
, phex (regval
, 4));
3344 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3346 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3347 argreg
, phex (regval
, 4));
3348 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3350 /* Write the high word of the double to the odd register(s). */
3351 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3353 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3354 float_argreg
, phex (regval
, 4));
3355 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3358 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3359 argreg
, phex (regval
, 4));
3360 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3364 /* This is a floating point value that fits entirely
3365 in a single register. */
3366 /* On 32 bit ABI's the float_argreg is further adjusted
3367 above to ensure that it is even register aligned. */
3368 LONGEST regval
= extract_unsigned_integer (val
, len
);
3370 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3371 float_argreg
, phex (regval
, len
));
3372 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3373 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3374 registers for each argument. The below is (my
3375 guess) to ensure that the corresponding integer
3376 register has reserved the same space. */
3378 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3379 argreg
, phex (regval
, len
));
3380 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3383 /* Reserve space for the FP register. */
3384 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3388 /* Copy the argument to general registers or the stack in
3389 register-sized pieces. Large arguments are split between
3390 registers and stack. */
3391 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3392 are treated specially: Irix cc passes
3393 them in registers where gcc sometimes puts them on the
3394 stack. For maximum compatibility, we will put them in
3396 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3397 && len
% MIPS32_REGSIZE
!= 0);
3398 /* Structures should be aligned to eight bytes (even arg registers)
3399 on MIPS_ABI_O32, if their first member has double precision. */
3400 if (mips_type_needs_double_align (arg_type
))
3405 stack_offset
+= MIPS32_REGSIZE
;
3410 /* Remember if the argument was written to the stack. */
3411 int stack_used_p
= 0;
3412 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3415 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3418 /* Write this portion of the argument to the stack. */
3419 if (argreg
> MIPS_LAST_ARG_REGNUM
3420 || odd_sized_struct
)
3422 /* Should shorter than int integer values be
3423 promoted to int before being stored? */
3424 int longword_offset
= 0;
3430 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3431 paddr_nz (stack_offset
));
3432 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3433 paddr_nz (longword_offset
));
3436 addr
= sp
+ stack_offset
+ longword_offset
;
3441 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3443 for (i
= 0; i
< partial_len
; i
++)
3445 fprintf_unfiltered (gdb_stdlog
, "%02x",
3449 write_memory (addr
, val
, partial_len
);
3452 /* Note!!! This is NOT an else clause. Odd sized
3453 structs may go thru BOTH paths. */
3454 /* Write this portion of the argument to a general
3455 purpose register. */
3456 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3458 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3459 /* Value may need to be sign extended, because
3460 mips_isa_regsize() != mips_abi_regsize(). */
3462 /* A non-floating-point argument being passed in a
3463 general register. If a struct or union, and if
3464 the remaining length is smaller than the register
3465 size, we have to adjust the register value on
3468 It does not seem to be necessary to do the
3469 same for integral types.
3471 Also don't do this adjustment on O64 binaries.
3473 cagney/2001-07-23: gdb/179: Also, GCC, when
3474 outputting LE O32 with sizeof (struct) <
3475 mips_abi_regsize(), generates a left shift
3476 as part of storing the argument in a register
3477 (the left shift isn't generated when
3478 sizeof (struct) >= mips_abi_regsize()). Since
3479 it is quite possible that this is GCC
3480 contradicting the LE/O32 ABI, GDB has not been
3481 adjusted to accommodate this. Either someone
3482 needs to demonstrate that the LE/O32 ABI
3483 specifies such a left shift OR this new ABI gets
3484 identified as such and GDB gets tweaked
3487 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3488 && partial_len
< MIPS32_REGSIZE
3489 && (typecode
== TYPE_CODE_STRUCT
3490 || typecode
== TYPE_CODE_UNION
))
3491 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3495 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3497 phex (regval
, MIPS32_REGSIZE
));
3498 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3501 /* Prevent subsequent floating point arguments from
3502 being passed in floating point registers. */
3503 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3509 /* Compute the the offset into the stack at which we
3510 will copy the next parameter.
3512 In older ABIs, the caller reserved space for
3513 registers that contained arguments. This was loosely
3514 refered to as their "home". Consequently, space is
3515 always allocated. */
3517 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3521 fprintf_unfiltered (gdb_stdlog
, "\n");
3524 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3526 /* Return adjusted stack pointer. */
3530 static enum return_value_convention
3531 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3532 struct regcache
*regcache
,
3533 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3535 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3537 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3538 || TYPE_CODE (type
) == TYPE_CODE_UNION
3539 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3540 return RETURN_VALUE_STRUCT_CONVENTION
;
3541 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3542 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3544 /* A single-precision floating-point value. It fits in the
3545 least significant part of FP0. */
3547 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3548 mips_xfer_register (gdbarch
, regcache
,
3549 gdbarch_num_regs (gdbarch
)
3550 + mips_regnum (gdbarch
)->fp0
,
3552 gdbarch_byte_order (gdbarch
),
3553 readbuf
, writebuf
, 0);
3554 return RETURN_VALUE_REGISTER_CONVENTION
;
3556 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3557 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3559 /* A double-precision floating-point value. The most
3560 significant part goes in FP1, and the least significant in
3563 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3564 switch (gdbarch_byte_order (gdbarch
))
3566 case BFD_ENDIAN_LITTLE
:
3567 mips_xfer_register (gdbarch
, regcache
,
3568 gdbarch_num_regs (gdbarch
)
3569 + mips_regnum (gdbarch
)->fp0
+
3570 0, 4, gdbarch_byte_order (gdbarch
),
3571 readbuf
, writebuf
, 0);
3572 mips_xfer_register (gdbarch
, regcache
,
3573 gdbarch_num_regs (gdbarch
)
3574 + mips_regnum (gdbarch
)->fp0
+ 1,
3575 4, gdbarch_byte_order (gdbarch
),
3576 readbuf
, writebuf
, 4);
3578 case BFD_ENDIAN_BIG
:
3579 mips_xfer_register (gdbarch
, regcache
,
3580 gdbarch_num_regs (gdbarch
)
3581 + mips_regnum (gdbarch
)->fp0
+ 1,
3582 4, gdbarch_byte_order (gdbarch
),
3583 readbuf
, writebuf
, 0);
3584 mips_xfer_register (gdbarch
, regcache
,
3585 gdbarch_num_regs (gdbarch
)
3586 + mips_regnum (gdbarch
)->fp0
+ 0,
3587 4, gdbarch_byte_order (gdbarch
),
3588 readbuf
, writebuf
, 4);
3591 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3593 return RETURN_VALUE_REGISTER_CONVENTION
;
3596 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3597 && TYPE_NFIELDS (type
) <= 2
3598 && TYPE_NFIELDS (type
) >= 1
3599 && ((TYPE_NFIELDS (type
) == 1
3600 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3602 || (TYPE_NFIELDS (type
) == 2
3603 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3605 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3607 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3609 /* A struct that contains one or two floats. Each value is part
3610 in the least significant part of their floating point
3612 gdb_byte reg
[MAX_REGISTER_SIZE
];
3615 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3616 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3618 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3621 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3623 mips_xfer_register (gdbarch
, regcache
,
3624 gdbarch_num_regs (gdbarch
) + regnum
,
3625 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3626 gdbarch_byte_order (gdbarch
),
3627 readbuf
, writebuf
, offset
);
3629 return RETURN_VALUE_REGISTER_CONVENTION
;
3633 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3634 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3636 /* A structure or union. Extract the left justified value,
3637 regardless of the byte order. I.e. DO NOT USE
3641 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3642 offset
< TYPE_LENGTH (type
);
3643 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3645 int xfer
= register_size (gdbarch
, regnum
);
3646 if (offset
+ xfer
> TYPE_LENGTH (type
))
3647 xfer
= TYPE_LENGTH (type
) - offset
;
3649 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3650 offset
, xfer
, regnum
);
3651 mips_xfer_register (gdbarch
, regcache
,
3652 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3653 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3655 return RETURN_VALUE_REGISTER_CONVENTION
;
3660 /* A scalar extract each part but least-significant-byte
3661 justified. o32 thinks registers are 4 byte, regardless of
3665 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3666 offset
< TYPE_LENGTH (type
);
3667 offset
+= MIPS32_REGSIZE
, regnum
++)
3669 int xfer
= MIPS32_REGSIZE
;
3670 if (offset
+ xfer
> TYPE_LENGTH (type
))
3671 xfer
= TYPE_LENGTH (type
) - offset
;
3673 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3674 offset
, xfer
, regnum
);
3675 mips_xfer_register (gdbarch
, regcache
,
3676 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3677 gdbarch_byte_order (gdbarch
),
3678 readbuf
, writebuf
, offset
);
3680 return RETURN_VALUE_REGISTER_CONVENTION
;
3684 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3688 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3689 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3691 struct value
**args
, CORE_ADDR sp
,
3692 int struct_return
, CORE_ADDR struct_addr
)
3698 int stack_offset
= 0;
3699 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3700 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3702 /* For shared libraries, "t9" needs to point at the function
3704 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3706 /* Set the return address register to point to the entry point of
3707 the program, where a breakpoint lies in wait. */
3708 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3710 /* First ensure that the stack and structure return address (if any)
3711 are properly aligned. The stack has to be at least 64-bit
3712 aligned even on 32-bit machines, because doubles must be 64-bit
3713 aligned. For n32 and n64, stack frames need to be 128-bit
3714 aligned, so we round to this widest known alignment. */
3716 sp
= align_down (sp
, 16);
3717 struct_addr
= align_down (struct_addr
, 16);
3719 /* Now make space on the stack for the args. */
3720 for (argnum
= 0; argnum
< nargs
; argnum
++)
3722 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3723 int arglen
= TYPE_LENGTH (arg_type
);
3725 /* Allocate space on the stack. */
3726 len
+= align_up (arglen
, MIPS64_REGSIZE
);
3728 sp
-= align_up (len
, 16);
3731 fprintf_unfiltered (gdb_stdlog
,
3732 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3733 paddr_nz (sp
), (long) align_up (len
, 16));
3735 /* Initialize the integer and float register pointers. */
3736 argreg
= MIPS_A0_REGNUM
;
3737 float_argreg
= mips_fpa0_regnum (gdbarch
);
3739 /* The struct_return pointer occupies the first parameter-passing reg. */
3743 fprintf_unfiltered (gdb_stdlog
,
3744 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3745 argreg
, paddr_nz (struct_addr
));
3746 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3747 stack_offset
+= MIPS64_REGSIZE
;
3750 /* Now load as many as possible of the first arguments into
3751 registers, and push the rest onto the stack. Loop thru args
3752 from first to last. */
3753 for (argnum
= 0; argnum
< nargs
; argnum
++)
3755 const gdb_byte
*val
;
3756 struct value
*arg
= args
[argnum
];
3757 struct type
*arg_type
= check_typedef (value_type (arg
));
3758 int len
= TYPE_LENGTH (arg_type
);
3759 enum type_code typecode
= TYPE_CODE (arg_type
);
3762 fprintf_unfiltered (gdb_stdlog
,
3763 "mips_o64_push_dummy_call: %d len=%d type=%d",
3764 argnum
+ 1, len
, (int) typecode
);
3766 val
= value_contents (arg
);
3768 /* Floating point arguments passed in registers have to be
3769 treated specially. On 32-bit architectures, doubles
3770 are passed in register pairs; the even register gets
3771 the low word, and the odd register gets the high word.
3772 On O32/O64, the first two floating point arguments are
3773 also copied to general registers, because MIPS16 functions
3774 don't use float registers for arguments. This duplication of
3775 arguments in general registers can't hurt non-MIPS16 functions
3776 because those registers are normally skipped. */
3778 if (fp_register_arg_p (typecode
, arg_type
)
3779 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3781 LONGEST regval
= extract_unsigned_integer (val
, len
);
3783 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3784 float_argreg
, phex (regval
, len
));
3785 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3787 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3788 argreg
, phex (regval
, len
));
3789 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3791 /* Reserve space for the FP register. */
3792 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
3796 /* Copy the argument to general registers or the stack in
3797 register-sized pieces. Large arguments are split between
3798 registers and stack. */
3799 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
3800 are treated specially: Irix cc passes them in registers
3801 where gcc sometimes puts them on the stack. For maximum
3802 compatibility, we will put them in both places. */
3803 int odd_sized_struct
= (len
> MIPS64_REGSIZE
3804 && len
% MIPS64_REGSIZE
!= 0);
3807 /* Remember if the argument was written to the stack. */
3808 int stack_used_p
= 0;
3809 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3812 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3815 /* Write this portion of the argument to the stack. */
3816 if (argreg
> MIPS_LAST_ARG_REGNUM
3817 || odd_sized_struct
)
3819 /* Should shorter than int integer values be
3820 promoted to int before being stored? */
3821 int longword_offset
= 0;
3824 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3826 if ((typecode
== TYPE_CODE_INT
3827 || typecode
== TYPE_CODE_PTR
3828 || typecode
== TYPE_CODE_FLT
)
3830 longword_offset
= MIPS64_REGSIZE
- len
;
3835 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3836 paddr_nz (stack_offset
));
3837 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3838 paddr_nz (longword_offset
));
3841 addr
= sp
+ stack_offset
+ longword_offset
;
3846 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3848 for (i
= 0; i
< partial_len
; i
++)
3850 fprintf_unfiltered (gdb_stdlog
, "%02x",
3854 write_memory (addr
, val
, partial_len
);
3857 /* Note!!! This is NOT an else clause. Odd sized
3858 structs may go thru BOTH paths. */
3859 /* Write this portion of the argument to a general
3860 purpose register. */
3861 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3863 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3864 /* Value may need to be sign extended, because
3865 mips_isa_regsize() != mips_abi_regsize(). */
3867 /* A non-floating-point argument being passed in a
3868 general register. If a struct or union, and if
3869 the remaining length is smaller than the register
3870 size, we have to adjust the register value on
3873 It does not seem to be necessary to do the
3874 same for integral types. */
3876 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3877 && partial_len
< MIPS64_REGSIZE
3878 && (typecode
== TYPE_CODE_STRUCT
3879 || typecode
== TYPE_CODE_UNION
))
3880 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3884 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3886 phex (regval
, MIPS64_REGSIZE
));
3887 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3890 /* Prevent subsequent floating point arguments from
3891 being passed in floating point registers. */
3892 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3898 /* Compute the the offset into the stack at which we
3899 will copy the next parameter.
3901 In older ABIs, the caller reserved space for
3902 registers that contained arguments. This was loosely
3903 refered to as their "home". Consequently, space is
3904 always allocated. */
3906 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3910 fprintf_unfiltered (gdb_stdlog
, "\n");
3913 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3915 /* Return adjusted stack pointer. */
3919 static enum return_value_convention
3920 mips_o64_return_value (struct gdbarch
*gdbarch
,
3921 struct type
*type
, struct regcache
*regcache
,
3922 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3924 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3926 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3927 || TYPE_CODE (type
) == TYPE_CODE_UNION
3928 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3929 return RETURN_VALUE_STRUCT_CONVENTION
;
3930 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
3932 /* A floating-point value. It fits in the least significant
3935 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3936 mips_xfer_register (gdbarch
, regcache
,
3937 gdbarch_num_regs (gdbarch
)
3938 + mips_regnum (gdbarch
)->fp0
,
3940 gdbarch_byte_order (gdbarch
),
3941 readbuf
, writebuf
, 0);
3942 return RETURN_VALUE_REGISTER_CONVENTION
;
3946 /* A scalar extract each part but least-significant-byte
3950 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3951 offset
< TYPE_LENGTH (type
);
3952 offset
+= MIPS64_REGSIZE
, regnum
++)
3954 int xfer
= MIPS64_REGSIZE
;
3955 if (offset
+ xfer
> TYPE_LENGTH (type
))
3956 xfer
= TYPE_LENGTH (type
) - offset
;
3958 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3959 offset
, xfer
, regnum
);
3960 mips_xfer_register (gdbarch
, regcache
,
3961 gdbarch_num_regs (gdbarch
) + regnum
,
3962 xfer
, gdbarch_byte_order (gdbarch
),
3963 readbuf
, writebuf
, offset
);
3965 return RETURN_VALUE_REGISTER_CONVENTION
;
3969 /* Floating point register management.
3971 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3972 64bit operations, these early MIPS cpus treat fp register pairs
3973 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3974 registers and offer a compatibility mode that emulates the MIPS2 fp
3975 model. When operating in MIPS2 fp compat mode, later cpu's split
3976 double precision floats into two 32-bit chunks and store them in
3977 consecutive fp regs. To display 64-bit floats stored in this
3978 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3979 Throw in user-configurable endianness and you have a real mess.
3981 The way this works is:
3982 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3983 double-precision value will be split across two logical registers.
3984 The lower-numbered logical register will hold the low-order bits,
3985 regardless of the processor's endianness.
3986 - If we are on a 64-bit processor, and we are looking for a
3987 single-precision value, it will be in the low ordered bits
3988 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3989 save slot in memory.
3990 - If we are in 64-bit mode, everything is straightforward.
3992 Note that this code only deals with "live" registers at the top of the
3993 stack. We will attempt to deal with saved registers later, when
3994 the raw/cooked register interface is in place. (We need a general
3995 interface that can deal with dynamic saved register sizes -- fp
3996 regs could be 32 bits wide in one frame and 64 on the frame above
3999 static struct type
*
4000 mips_float_register_type (void)
4002 return builtin_type_ieee_single
;
4005 static struct type
*
4006 mips_double_register_type (void)
4008 return builtin_type_ieee_double
;
4011 /* Copy a 32-bit single-precision value from the current frame
4012 into rare_buffer. */
4015 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4016 gdb_byte
*rare_buffer
)
4018 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4019 int raw_size
= register_size (gdbarch
, regno
);
4020 gdb_byte
*raw_buffer
= alloca (raw_size
);
4022 if (!frame_register_read (frame
, regno
, raw_buffer
))
4023 error (_("can't read register %d (%s)"),
4024 regno
, gdbarch_register_name (gdbarch
, regno
));
4027 /* We have a 64-bit value for this register. Find the low-order
4031 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4036 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4040 memcpy (rare_buffer
, raw_buffer
, 4);
4044 /* Copy a 64-bit double-precision value from the current frame into
4045 rare_buffer. This may include getting half of it from the next
4049 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4050 gdb_byte
*rare_buffer
)
4052 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4053 int raw_size
= register_size (gdbarch
, regno
);
4055 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4057 /* We have a 64-bit value for this register, and we should use
4059 if (!frame_register_read (frame
, regno
, rare_buffer
))
4060 error (_("can't read register %d (%s)"),
4061 regno
, gdbarch_register_name (gdbarch
, regno
));
4065 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4067 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4068 internal_error (__FILE__
, __LINE__
,
4069 _("mips_read_fp_register_double: bad access to "
4070 "odd-numbered FP register"));
4072 /* mips_read_fp_register_single will find the correct 32 bits from
4074 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4076 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4077 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4081 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4082 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4088 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4090 { /* do values for FP (float) regs */
4091 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4092 gdb_byte
*raw_buffer
;
4093 double doub
, flt1
; /* doubles extracted from raw hex data */
4096 raw_buffer
= alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
));
4098 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4099 fprintf_filtered (file
, "%*s",
4100 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4103 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4105 /* 4-byte registers: Print hex and floating. Also print even
4106 numbered registers as doubles. */
4107 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4108 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4110 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4113 fprintf_filtered (file
, " flt: ");
4115 fprintf_filtered (file
, " <invalid float> ");
4117 fprintf_filtered (file
, "%-17.9g", flt1
);
4119 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4121 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4122 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4125 fprintf_filtered (file
, " dbl: ");
4127 fprintf_filtered (file
, "<invalid double>");
4129 fprintf_filtered (file
, "%-24.17g", doub
);
4134 /* Eight byte registers: print each one as hex, float and double. */
4135 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4136 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4138 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4139 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4142 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4145 fprintf_filtered (file
, " flt: ");
4147 fprintf_filtered (file
, "<invalid float>");
4149 fprintf_filtered (file
, "%-17.9g", flt1
);
4151 fprintf_filtered (file
, " dbl: ");
4153 fprintf_filtered (file
, "<invalid double>");
4155 fprintf_filtered (file
, "%-24.17g", doub
);
4160 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4163 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4164 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4167 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4169 mips_print_fp_register (file
, frame
, regnum
);
4173 /* Get the data in raw format. */
4174 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4176 fprintf_filtered (file
, "%s: [Invalid]",
4177 gdbarch_register_name (gdbarch
, regnum
));
4181 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4183 /* The problem with printing numeric register names (r26, etc.) is that
4184 the user can't use them on input. Probably the best solution is to
4185 fix it so that either the numeric or the funky (a2, etc.) names
4186 are accepted on input. */
4187 if (regnum
< MIPS_NUMREGS
)
4188 fprintf_filtered (file
, "(r%d): ", regnum
);
4190 fprintf_filtered (file
, ": ");
4192 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4194 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4198 print_scalar_formatted (raw_buffer
+ offset
,
4199 register_type (gdbarch
, regnum
), 'x', 0,
4203 /* Replacement for generic do_registers_info.
4204 Print regs in pretty columns. */
4207 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4210 fprintf_filtered (file
, " ");
4211 mips_print_fp_register (file
, frame
, regnum
);
4212 fprintf_filtered (file
, "\n");
4217 /* Print a row's worth of GP (int) registers, with name labels above */
4220 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4223 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4224 /* do values for GP (int) regs */
4225 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4226 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4230 /* For GP registers, we print a separate row of names above the vals */
4231 for (col
= 0, regnum
= start_regnum
;
4232 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4233 + gdbarch_num_pseudo_regs (gdbarch
);
4236 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4237 continue; /* unused register */
4238 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4240 break; /* end the row: reached FP register */
4241 /* Large registers are handled separately. */
4242 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4245 break; /* End the row before this register. */
4247 /* Print this register on a row by itself. */
4248 mips_print_register (file
, frame
, regnum
);
4249 fprintf_filtered (file
, "\n");
4253 fprintf_filtered (file
, " ");
4254 fprintf_filtered (file
,
4255 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4256 gdbarch_register_name (gdbarch
, regnum
));
4263 /* print the R0 to R31 names */
4264 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4265 fprintf_filtered (file
, "\n R%-4d",
4266 start_regnum
% gdbarch_num_regs (gdbarch
));
4268 fprintf_filtered (file
, "\n ");
4270 /* now print the values in hex, 4 or 8 to the row */
4271 for (col
= 0, regnum
= start_regnum
;
4272 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4273 + gdbarch_num_pseudo_regs (gdbarch
);
4276 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4277 continue; /* unused register */
4278 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4280 break; /* end row: reached FP register */
4281 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4282 break; /* End row: large register. */
4284 /* OK: get the data in raw format. */
4285 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4286 error (_("can't read register %d (%s)"),
4287 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4288 /* pad small registers */
4290 byte
< (mips_abi_regsize (gdbarch
)
4291 - register_size (gdbarch
, regnum
)); byte
++)
4292 printf_filtered (" ");
4293 /* Now print the register value in hex, endian order. */
4294 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4296 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4297 byte
< register_size (gdbarch
, regnum
); byte
++)
4298 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4300 for (byte
= register_size (gdbarch
, regnum
) - 1;
4302 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4303 fprintf_filtered (file
, " ");
4306 if (col
> 0) /* ie. if we actually printed anything... */
4307 fprintf_filtered (file
, "\n");
4312 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4315 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4316 struct frame_info
*frame
, int regnum
, int all
)
4318 if (regnum
!= -1) /* do one specified register */
4320 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4321 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4322 error (_("Not a valid register for the current processor type"));
4324 mips_print_register (file
, frame
, regnum
);
4325 fprintf_filtered (file
, "\n");
4328 /* do all (or most) registers */
4330 regnum
= gdbarch_num_regs (gdbarch
);
4331 while (regnum
< gdbarch_num_regs (gdbarch
)
4332 + gdbarch_num_pseudo_regs (gdbarch
))
4334 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4337 if (all
) /* true for "INFO ALL-REGISTERS" command */
4338 regnum
= print_fp_register_row (file
, frame
, regnum
);
4340 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4343 regnum
= print_gp_register_row (file
, frame
, regnum
);
4348 /* Is this a branch with a delay slot? */
4351 is_delayed (unsigned long insn
)
4354 for (i
= 0; i
< NUMOPCODES
; ++i
)
4355 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4356 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4358 return (i
< NUMOPCODES
4359 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4360 | INSN_COND_BRANCH_DELAY
4361 | INSN_COND_BRANCH_LIKELY
)));
4365 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4366 struct frame_info
*frame
)
4368 CORE_ADDR pc
= get_frame_pc (frame
);
4369 gdb_byte buf
[MIPS_INSN32_SIZE
];
4371 /* There is no branch delay slot on MIPS16. */
4372 if (mips_pc_is_mips16 (pc
))
4375 if (!breakpoint_here_p (pc
+ 4))
4378 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4379 /* If error reading memory, guess that it is not a delayed
4382 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4385 /* To skip prologues, I use this predicate. Returns either PC itself
4386 if the code at PC does not look like a function prologue; otherwise
4387 returns an address that (if we're lucky) follows the prologue. If
4388 LENIENT, then we must skip everything which is involved in setting
4389 up the frame (it's OK to skip more, just so long as we don't skip
4390 anything which might clobber the registers which are being saved.
4391 We must skip more in the case where part of the prologue is in the
4392 delay slot of a non-prologue instruction). */
4395 mips_skip_prologue (CORE_ADDR pc
)
4398 CORE_ADDR func_addr
;
4400 /* See if we can determine the end of the prologue via the symbol table.
4401 If so, then return either PC, or the PC after the prologue, whichever
4403 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4405 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4406 if (post_prologue_pc
!= 0)
4407 return max (pc
, post_prologue_pc
);
4410 /* Can't determine prologue from the symbol table, need to examine
4413 /* Find an upper limit on the function prologue using the debug
4414 information. If the debug information could not be used to provide
4415 that bound, then use an arbitrary large number as the upper bound. */
4416 limit_pc
= skip_prologue_using_sal (pc
);
4418 limit_pc
= pc
+ 100; /* Magic. */
4420 if (mips_pc_is_mips16 (pc
))
4421 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4423 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4426 /* Check whether the PC is in a function epilogue (32-bit version).
4427 This is a helper function for mips_in_function_epilogue_p. */
4429 mips32_in_function_epilogue_p (CORE_ADDR pc
)
4431 CORE_ADDR func_addr
= 0, func_end
= 0;
4433 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4435 /* The MIPS epilogue is max. 12 bytes long. */
4436 CORE_ADDR addr
= func_end
- 12;
4438 if (addr
< func_addr
+ 4)
4439 addr
= func_addr
+ 4;
4443 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4445 unsigned long high_word
;
4448 inst
= mips_fetch_instruction (pc
);
4449 high_word
= (inst
>> 16) & 0xffff;
4451 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4452 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4453 && inst
!= 0x03e00008 /* jr $ra */
4454 && inst
!= 0x00000000) /* nop */
4464 /* Check whether the PC is in a function epilogue (16-bit version).
4465 This is a helper function for mips_in_function_epilogue_p. */
4467 mips16_in_function_epilogue_p (CORE_ADDR pc
)
4469 CORE_ADDR func_addr
= 0, func_end
= 0;
4471 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4473 /* The MIPS epilogue is max. 12 bytes long. */
4474 CORE_ADDR addr
= func_end
- 12;
4476 if (addr
< func_addr
+ 4)
4477 addr
= func_addr
+ 4;
4481 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4483 unsigned short inst
;
4485 inst
= mips_fetch_instruction (pc
);
4487 if ((inst
& 0xf800) == 0xf000) /* extend */
4490 if (inst
!= 0x6300 /* addiu $sp,offset */
4491 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
4492 && inst
!= 0xe820 /* jr $ra */
4493 && inst
!= 0xe8a0 /* jrc $ra */
4494 && inst
!= 0x6500) /* nop */
4504 /* The epilogue is defined here as the area at the end of a function,
4505 after an instruction which destroys the function's stack frame. */
4507 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4509 if (mips_pc_is_mips16 (pc
))
4510 return mips16_in_function_epilogue_p (pc
);
4512 return mips32_in_function_epilogue_p (pc
);
4515 /* Root of all "set mips "/"show mips " commands. This will eventually be
4516 used for all MIPS-specific commands. */
4519 show_mips_command (char *args
, int from_tty
)
4521 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4525 set_mips_command (char *args
, int from_tty
)
4528 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4529 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4532 /* Commands to show/set the MIPS FPU type. */
4535 show_mipsfpu_command (char *args
, int from_tty
)
4538 switch (MIPS_FPU_TYPE
)
4540 case MIPS_FPU_SINGLE
:
4541 fpu
= "single-precision";
4543 case MIPS_FPU_DOUBLE
:
4544 fpu
= "double-precision";
4547 fpu
= "absent (none)";
4550 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4552 if (mips_fpu_type_auto
)
4554 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4558 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4563 set_mipsfpu_command (char *args
, int from_tty
)
4566 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4567 show_mipsfpu_command (args
, from_tty
);
4571 set_mipsfpu_single_command (char *args
, int from_tty
)
4573 struct gdbarch_info info
;
4574 gdbarch_info_init (&info
);
4575 mips_fpu_type
= MIPS_FPU_SINGLE
;
4576 mips_fpu_type_auto
= 0;
4577 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4578 instead of relying on globals. Doing that would let generic code
4579 handle the search for this specific architecture. */
4580 if (!gdbarch_update_p (info
))
4581 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4585 set_mipsfpu_double_command (char *args
, int from_tty
)
4587 struct gdbarch_info info
;
4588 gdbarch_info_init (&info
);
4589 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4590 mips_fpu_type_auto
= 0;
4591 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4592 instead of relying on globals. Doing that would let generic code
4593 handle the search for this specific architecture. */
4594 if (!gdbarch_update_p (info
))
4595 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4599 set_mipsfpu_none_command (char *args
, int from_tty
)
4601 struct gdbarch_info info
;
4602 gdbarch_info_init (&info
);
4603 mips_fpu_type
= MIPS_FPU_NONE
;
4604 mips_fpu_type_auto
= 0;
4605 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4606 instead of relying on globals. Doing that would let generic code
4607 handle the search for this specific architecture. */
4608 if (!gdbarch_update_p (info
))
4609 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4613 set_mipsfpu_auto_command (char *args
, int from_tty
)
4615 mips_fpu_type_auto
= 1;
4618 /* Attempt to identify the particular processor model by reading the
4619 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4620 the relevant processor still exists (it dates back to '94) and
4621 secondly this is not the way to do this. The processor type should
4622 be set by forcing an architecture change. */
4625 deprecated_mips_set_processor_regs_hack (void)
4627 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4630 regcache_cooked_read_unsigned (get_current_regcache (),
4631 MIPS_PRID_REGNUM
, &prid
);
4632 if ((prid
& ~0xf) == 0x700)
4633 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4636 /* Just like reinit_frame_cache, but with the right arguments to be
4637 callable as an sfunc. */
4640 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4641 struct cmd_list_element
*c
)
4643 reinit_frame_cache ();
4647 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4649 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4651 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4652 disassembler needs to be able to locally determine the ISA, and
4653 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4655 if (mips_pc_is_mips16 (memaddr
))
4656 info
->mach
= bfd_mach_mips16
;
4658 /* Round down the instruction address to the appropriate boundary. */
4659 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4661 /* Set the disassembler options. */
4662 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4664 /* Set up the disassembler info, so that we get the right
4665 register names from libopcodes. */
4666 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4667 info
->disassembler_options
= "gpr-names=n32";
4669 info
->disassembler_options
= "gpr-names=64";
4670 info
->flavour
= bfd_target_elf_flavour
;
4673 /* This string is not recognized explicitly by the disassembler,
4674 but it tells the disassembler to not try to guess the ABI from
4675 the bfd elf headers, such that, if the user overrides the ABI
4676 of a program linked as NewABI, the disassembly will follow the
4677 register naming conventions specified by the user. */
4678 info
->disassembler_options
= "gpr-names=32";
4680 /* Call the appropriate disassembler based on the target endian-ness. */
4681 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4682 return print_insn_big_mips (memaddr
, info
);
4684 return print_insn_little_mips (memaddr
, info
);
4687 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4688 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4689 It returns a pointer to a string of bytes that encode a breakpoint
4690 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4691 necessary) to point to the actual memory location where the breakpoint
4692 should be inserted. */
4694 static const gdb_byte
*
4695 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4697 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4699 if (mips_pc_is_mips16 (*pcptr
))
4701 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4702 *pcptr
= unmake_mips16_addr (*pcptr
);
4703 *lenptr
= sizeof (mips16_big_breakpoint
);
4704 return mips16_big_breakpoint
;
4708 /* The IDT board uses an unusual breakpoint value, and
4709 sometimes gets confused when it sees the usual MIPS
4710 breakpoint instruction. */
4711 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4712 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4713 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4715 *lenptr
= sizeof (big_breakpoint
);
4717 if (strcmp (target_shortname
, "mips") == 0)
4718 return idt_big_breakpoint
;
4719 else if (strcmp (target_shortname
, "ddb") == 0
4720 || strcmp (target_shortname
, "pmon") == 0
4721 || strcmp (target_shortname
, "lsi") == 0)
4722 return pmon_big_breakpoint
;
4724 return big_breakpoint
;
4729 if (mips_pc_is_mips16 (*pcptr
))
4731 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4732 *pcptr
= unmake_mips16_addr (*pcptr
);
4733 *lenptr
= sizeof (mips16_little_breakpoint
);
4734 return mips16_little_breakpoint
;
4738 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4739 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4740 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4742 *lenptr
= sizeof (little_breakpoint
);
4744 if (strcmp (target_shortname
, "mips") == 0)
4745 return idt_little_breakpoint
;
4746 else if (strcmp (target_shortname
, "ddb") == 0
4747 || strcmp (target_shortname
, "pmon") == 0
4748 || strcmp (target_shortname
, "lsi") == 0)
4749 return pmon_little_breakpoint
;
4751 return little_breakpoint
;
4756 /* If PC is in a mips16 call or return stub, return the address of the target
4757 PC, which is either the callee or the caller. There are several
4758 cases which must be handled:
4760 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4761 target PC is in $31 ($ra).
4762 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4763 and the target PC is in $2.
4764 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4765 before the jal instruction, this is effectively a call stub
4766 and the the target PC is in $2. Otherwise this is effectively
4767 a return stub and the target PC is in $18.
4769 See the source code for the stubs in gcc/config/mips/mips16.S for
4773 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
4776 CORE_ADDR start_addr
;
4778 /* Find the starting address and name of the function containing the PC. */
4779 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4782 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4783 target PC is in $31 ($ra). */
4784 if (strcmp (name
, "__mips16_ret_sf") == 0
4785 || strcmp (name
, "__mips16_ret_df") == 0)
4786 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
4788 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4790 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4791 and the target PC is in $2. */
4792 if (name
[19] >= '0' && name
[19] <= '9')
4793 return get_frame_register_signed (frame
, 2);
4795 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4796 before the jal instruction, this is effectively a call stub
4797 and the the target PC is in $2. Otherwise this is effectively
4798 a return stub and the target PC is in $18. */
4799 else if (name
[19] == 's' || name
[19] == 'd')
4801 if (pc
== start_addr
)
4803 /* Check if the target of the stub is a compiler-generated
4804 stub. Such a stub for a function bar might have a name
4805 like __fn_stub_bar, and might look like this:
4810 la $1,bar (becomes a lui/addiu pair)
4812 So scan down to the lui/addi and extract the target
4813 address from those two instructions. */
4815 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
4819 /* See if the name of the target function is __fn_stub_*. */
4820 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4823 if (strncmp (name
, "__fn_stub_", 10) != 0
4824 && strcmp (name
, "etext") != 0
4825 && strcmp (name
, "_etext") != 0)
4828 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4829 The limit on the search is arbitrarily set to 20
4830 instructions. FIXME. */
4831 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
4833 inst
= mips_fetch_instruction (target_pc
);
4834 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4835 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4836 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4837 return pc
| (inst
& 0xffff); /* low word */
4840 /* Couldn't find the lui/addui pair, so return stub address. */
4844 /* This is the 'return' part of a call stub. The return
4845 address is in $r18. */
4846 return get_frame_register_signed (frame
, 18);
4849 return 0; /* not a stub */
4852 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4853 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4856 mips_stab_reg_to_regnum (int num
)
4859 if (num
>= 0 && num
< 32)
4861 else if (num
>= 38 && num
< 70)
4862 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4864 regnum
= mips_regnum (current_gdbarch
)->hi
;
4866 regnum
= mips_regnum (current_gdbarch
)->lo
;
4868 /* This will hopefully (eventually) provoke a warning. Should
4869 we be calling complaint() here? */
4870 return gdbarch_num_regs (current_gdbarch
)
4871 + gdbarch_num_pseudo_regs (current_gdbarch
);
4872 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4876 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4877 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4880 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4883 if (num
>= 0 && num
< 32)
4885 else if (num
>= 32 && num
< 64)
4886 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4888 regnum
= mips_regnum (current_gdbarch
)->hi
;
4890 regnum
= mips_regnum (current_gdbarch
)->lo
;
4892 /* This will hopefully (eventually) provoke a warning. Should we
4893 be calling complaint() here? */
4894 return gdbarch_num_regs (current_gdbarch
)
4895 + gdbarch_num_pseudo_regs (current_gdbarch
);
4896 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4900 mips_register_sim_regno (int regnum
)
4902 /* Only makes sense to supply raw registers. */
4903 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
));
4904 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4905 decide if it is valid. Should instead define a standard sim/gdb
4906 register numbering scheme. */
4907 if (gdbarch_register_name (current_gdbarch
,
4909 (current_gdbarch
) + regnum
) != NULL
4910 && gdbarch_register_name (current_gdbarch
,
4912 (current_gdbarch
) + regnum
)[0] != '\0')
4915 return LEGACY_SIM_REGNO_IGNORE
;
4919 /* Convert an integer into an address. Extracting the value signed
4920 guarantees a correctly sign extended address. */
4923 mips_integer_to_address (struct gdbarch
*gdbarch
,
4924 struct type
*type
, const gdb_byte
*buf
)
4926 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
4929 /* Dummy virtual frame pointer method. This is no more or less accurate
4930 than most other architectures; we just need to be explicit about it,
4931 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
4932 an assertion failure. */
4935 mips_virtual_frame_pointer (CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
4937 *reg
= MIPS_SP_REGNUM
;
4942 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4944 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4945 const char *name
= bfd_get_section_name (abfd
, sect
);
4947 if (*abip
!= MIPS_ABI_UNKNOWN
)
4950 if (strncmp (name
, ".mdebug.", 8) != 0)
4953 if (strcmp (name
, ".mdebug.abi32") == 0)
4954 *abip
= MIPS_ABI_O32
;
4955 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4956 *abip
= MIPS_ABI_N32
;
4957 else if (strcmp (name
, ".mdebug.abi64") == 0)
4958 *abip
= MIPS_ABI_N64
;
4959 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4960 *abip
= MIPS_ABI_O64
;
4961 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4962 *abip
= MIPS_ABI_EABI32
;
4963 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4964 *abip
= MIPS_ABI_EABI64
;
4966 warning (_("unsupported ABI %s."), name
+ 8);
4970 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
4972 int *lbp
= (int *) obj
;
4973 const char *name
= bfd_get_section_name (abfd
, sect
);
4975 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
4977 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
4979 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
4980 warning (_("unrecognized .gcc_compiled_longXX"));
4983 static enum mips_abi
4984 global_mips_abi (void)
4988 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4989 if (mips_abi_strings
[i
] == mips_abi_string
)
4990 return (enum mips_abi
) i
;
4992 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
4996 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
4998 /* If the size matches the set of 32-bit or 64-bit integer registers,
4999 assume that's what we've got. */
5000 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5001 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5003 /* If the size matches the full set of registers GDB traditionally
5004 knows about, including floating point, for either 32-bit or
5005 64-bit, assume that's what we've got. */
5006 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5007 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5009 /* Otherwise we don't have a useful guess. */
5012 static struct value
*
5013 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5015 const int *reg_p
= baton
;
5016 return value_of_register (*reg_p
, frame
);
5019 static struct gdbarch
*
5020 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5022 struct gdbarch
*gdbarch
;
5023 struct gdbarch_tdep
*tdep
;
5025 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5027 enum mips_fpu_type fpu_type
;
5028 struct tdesc_arch_data
*tdesc_data
= NULL
;
5029 int elf_fpu_type
= 0;
5031 /* Check any target description for validity. */
5032 if (tdesc_has_registers (info
.target_desc
))
5034 static const char *const mips_gprs
[] = {
5035 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5036 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5037 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5038 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5040 static const char *const mips_fprs
[] = {
5041 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5042 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5043 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5044 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5047 const struct tdesc_feature
*feature
;
5050 feature
= tdesc_find_feature (info
.target_desc
,
5051 "org.gnu.gdb.mips.cpu");
5052 if (feature
== NULL
)
5055 tdesc_data
= tdesc_data_alloc ();
5058 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5059 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5063 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5064 MIPS_EMBED_LO_REGNUM
, "lo");
5065 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5066 MIPS_EMBED_HI_REGNUM
, "hi");
5067 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5068 MIPS_EMBED_PC_REGNUM
, "pc");
5072 tdesc_data_cleanup (tdesc_data
);
5076 feature
= tdesc_find_feature (info
.target_desc
,
5077 "org.gnu.gdb.mips.cp0");
5078 if (feature
== NULL
)
5080 tdesc_data_cleanup (tdesc_data
);
5085 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5086 MIPS_EMBED_BADVADDR_REGNUM
,
5088 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5089 MIPS_PS_REGNUM
, "status");
5090 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5091 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5095 tdesc_data_cleanup (tdesc_data
);
5099 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5100 backend is not prepared for that, though. */
5101 feature
= tdesc_find_feature (info
.target_desc
,
5102 "org.gnu.gdb.mips.fpu");
5103 if (feature
== NULL
)
5105 tdesc_data_cleanup (tdesc_data
);
5110 for (i
= 0; i
< 32; i
++)
5111 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5112 i
+ MIPS_EMBED_FP0_REGNUM
,
5115 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5116 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5117 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5118 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5122 tdesc_data_cleanup (tdesc_data
);
5126 /* It would be nice to detect an attempt to use a 64-bit ABI
5127 when only 32-bit registers are provided. */
5130 /* First of all, extract the elf_flags, if available. */
5131 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5132 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5133 else if (arches
!= NULL
)
5134 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5138 fprintf_unfiltered (gdb_stdlog
,
5139 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5141 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5142 switch ((elf_flags
& EF_MIPS_ABI
))
5144 case E_MIPS_ABI_O32
:
5145 found_abi
= MIPS_ABI_O32
;
5147 case E_MIPS_ABI_O64
:
5148 found_abi
= MIPS_ABI_O64
;
5150 case E_MIPS_ABI_EABI32
:
5151 found_abi
= MIPS_ABI_EABI32
;
5153 case E_MIPS_ABI_EABI64
:
5154 found_abi
= MIPS_ABI_EABI64
;
5157 if ((elf_flags
& EF_MIPS_ABI2
))
5158 found_abi
= MIPS_ABI_N32
;
5160 found_abi
= MIPS_ABI_UNKNOWN
;
5164 /* GCC creates a pseudo-section whose name describes the ABI. */
5165 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5166 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5168 /* If we have no useful BFD information, use the ABI from the last
5169 MIPS architecture (if there is one). */
5170 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5171 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5173 /* Try the architecture for any hint of the correct ABI. */
5174 if (found_abi
== MIPS_ABI_UNKNOWN
5175 && info
.bfd_arch_info
!= NULL
5176 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5178 switch (info
.bfd_arch_info
->mach
)
5180 case bfd_mach_mips3900
:
5181 found_abi
= MIPS_ABI_EABI32
;
5183 case bfd_mach_mips4100
:
5184 case bfd_mach_mips5000
:
5185 found_abi
= MIPS_ABI_EABI64
;
5187 case bfd_mach_mips8000
:
5188 case bfd_mach_mips10000
:
5189 /* On Irix, ELF64 executables use the N64 ABI. The
5190 pseudo-sections which describe the ABI aren't present
5191 on IRIX. (Even for executables created by gcc.) */
5192 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5193 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5194 found_abi
= MIPS_ABI_N64
;
5196 found_abi
= MIPS_ABI_N32
;
5201 /* Default 64-bit objects to N64 instead of O32. */
5202 if (found_abi
== MIPS_ABI_UNKNOWN
5203 && info
.abfd
!= NULL
5204 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5205 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5206 found_abi
= MIPS_ABI_N64
;
5209 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5212 /* What has the user specified from the command line? */
5213 wanted_abi
= global_mips_abi ();
5215 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5218 /* Now that we have found what the ABI for this binary would be,
5219 check whether the user is overriding it. */
5220 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5221 mips_abi
= wanted_abi
;
5222 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5223 mips_abi
= found_abi
;
5225 mips_abi
= MIPS_ABI_O32
;
5227 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5230 /* Also used when doing an architecture lookup. */
5232 fprintf_unfiltered (gdb_stdlog
,
5233 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5234 mips64_transfers_32bit_regs_p
);
5236 /* Determine the MIPS FPU type. */
5239 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5240 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5241 Tag_GNU_MIPS_ABI_FP
);
5242 #endif /* HAVE_ELF */
5244 if (!mips_fpu_type_auto
)
5245 fpu_type
= mips_fpu_type
;
5246 else if (elf_fpu_type
!= 0)
5248 switch (elf_fpu_type
)
5251 fpu_type
= MIPS_FPU_DOUBLE
;
5254 fpu_type
= MIPS_FPU_SINGLE
;
5258 /* Soft float or unknown. */
5259 fpu_type
= MIPS_FPU_NONE
;
5263 else if (info
.bfd_arch_info
!= NULL
5264 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5265 switch (info
.bfd_arch_info
->mach
)
5267 case bfd_mach_mips3900
:
5268 case bfd_mach_mips4100
:
5269 case bfd_mach_mips4111
:
5270 case bfd_mach_mips4120
:
5271 fpu_type
= MIPS_FPU_NONE
;
5273 case bfd_mach_mips4650
:
5274 fpu_type
= MIPS_FPU_SINGLE
;
5277 fpu_type
= MIPS_FPU_DOUBLE
;
5280 else if (arches
!= NULL
)
5281 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5283 fpu_type
= MIPS_FPU_DOUBLE
;
5285 fprintf_unfiltered (gdb_stdlog
,
5286 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5288 /* Check for blatant incompatibilities. */
5290 /* If we have only 32-bit registers, then we can't debug a 64-bit
5292 if (info
.target_desc
5293 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5294 && mips_abi
!= MIPS_ABI_EABI32
5295 && mips_abi
!= MIPS_ABI_O32
)
5297 if (tdesc_data
!= NULL
)
5298 tdesc_data_cleanup (tdesc_data
);
5302 /* try to find a pre-existing architecture */
5303 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5305 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5307 /* MIPS needs to be pedantic about which ABI the object is
5309 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5311 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5313 /* Need to be pedantic about which register virtual size is
5315 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5316 != mips64_transfers_32bit_regs_p
)
5318 /* Be pedantic about which FPU is selected. */
5319 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5322 if (tdesc_data
!= NULL
)
5323 tdesc_data_cleanup (tdesc_data
);
5324 return arches
->gdbarch
;
5327 /* Need a new architecture. Fill in a target specific vector. */
5328 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5329 gdbarch
= gdbarch_alloc (&info
, tdep
);
5330 tdep
->elf_flags
= elf_flags
;
5331 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5332 tdep
->found_abi
= found_abi
;
5333 tdep
->mips_abi
= mips_abi
;
5334 tdep
->mips_fpu_type
= fpu_type
;
5335 tdep
->register_size_valid_p
= 0;
5336 tdep
->register_size
= 0;
5338 if (info
.target_desc
)
5340 /* Some useful properties can be inferred from the target. */
5341 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5343 tdep
->register_size_valid_p
= 1;
5344 tdep
->register_size
= 4;
5346 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5348 tdep
->register_size_valid_p
= 1;
5349 tdep
->register_size
= 8;
5353 /* Initially set everything according to the default ABI/ISA. */
5354 set_gdbarch_short_bit (gdbarch
, 16);
5355 set_gdbarch_int_bit (gdbarch
, 32);
5356 set_gdbarch_float_bit (gdbarch
, 32);
5357 set_gdbarch_double_bit (gdbarch
, 64);
5358 set_gdbarch_long_double_bit (gdbarch
, 64);
5359 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5360 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5361 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5363 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5364 mips_elf_make_msymbol_special
);
5366 /* Fill in the OS dependant register numbers and names. */
5368 const char **reg_names
;
5369 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5370 struct mips_regnum
);
5371 if (tdesc_has_registers (info
.target_desc
))
5373 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5374 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5375 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5376 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5377 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5378 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5379 regnum
->fp_control_status
= 70;
5380 regnum
->fp_implementation_revision
= 71;
5381 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5384 else if (info
.osabi
== GDB_OSABI_IRIX
)
5389 regnum
->badvaddr
= 66;
5392 regnum
->fp_control_status
= 69;
5393 regnum
->fp_implementation_revision
= 70;
5395 reg_names
= mips_irix_reg_names
;
5399 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5400 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5401 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5402 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5403 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5404 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5405 regnum
->fp_control_status
= 70;
5406 regnum
->fp_implementation_revision
= 71;
5408 if (info
.bfd_arch_info
!= NULL
5409 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5410 reg_names
= mips_tx39_reg_names
;
5412 reg_names
= mips_generic_reg_names
;
5414 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5415 replaced by read_pc? */
5416 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5417 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5418 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5419 set_gdbarch_num_regs (gdbarch
, num_regs
);
5420 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5421 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5422 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
5423 tdep
->mips_processor_reg_names
= reg_names
;
5424 tdep
->regnum
= regnum
;
5430 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5431 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5432 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5433 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5434 tdep
->default_mask_address_p
= 0;
5435 set_gdbarch_long_bit (gdbarch
, 32);
5436 set_gdbarch_ptr_bit (gdbarch
, 32);
5437 set_gdbarch_long_long_bit (gdbarch
, 64);
5440 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5441 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5442 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5443 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5444 tdep
->default_mask_address_p
= 0;
5445 set_gdbarch_long_bit (gdbarch
, 32);
5446 set_gdbarch_ptr_bit (gdbarch
, 32);
5447 set_gdbarch_long_long_bit (gdbarch
, 64);
5449 case MIPS_ABI_EABI32
:
5450 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5451 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5452 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5453 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5454 tdep
->default_mask_address_p
= 0;
5455 set_gdbarch_long_bit (gdbarch
, 32);
5456 set_gdbarch_ptr_bit (gdbarch
, 32);
5457 set_gdbarch_long_long_bit (gdbarch
, 64);
5459 case MIPS_ABI_EABI64
:
5460 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5461 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5462 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5463 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5464 tdep
->default_mask_address_p
= 0;
5465 set_gdbarch_long_bit (gdbarch
, 64);
5466 set_gdbarch_ptr_bit (gdbarch
, 64);
5467 set_gdbarch_long_long_bit (gdbarch
, 64);
5470 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5471 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5472 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5473 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5474 tdep
->default_mask_address_p
= 0;
5475 set_gdbarch_long_bit (gdbarch
, 32);
5476 set_gdbarch_ptr_bit (gdbarch
, 32);
5477 set_gdbarch_long_long_bit (gdbarch
, 64);
5478 set_gdbarch_long_double_bit (gdbarch
, 128);
5479 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5482 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5483 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5484 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5485 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5486 tdep
->default_mask_address_p
= 0;
5487 set_gdbarch_long_bit (gdbarch
, 64);
5488 set_gdbarch_ptr_bit (gdbarch
, 64);
5489 set_gdbarch_long_long_bit (gdbarch
, 64);
5490 set_gdbarch_long_double_bit (gdbarch
, 128);
5491 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5494 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5497 /* GCC creates a pseudo-section whose name specifies the size of
5498 longs, since -mlong32 or -mlong64 may be used independent of
5499 other options. How those options affect pointer sizes is ABI and
5500 architecture dependent, so use them to override the default sizes
5501 set by the ABI. This table shows the relationship between ABI,
5502 -mlongXX, and size of pointers:
5504 ABI -mlongXX ptr bits
5505 --- -------- --------
5519 Note that for o32 and eabi32, pointers are always 32 bits
5520 regardless of any -mlongXX option. For all others, pointers and
5521 longs are the same, as set by -mlongXX or set by defaults.
5524 if (info
.abfd
!= NULL
)
5528 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5531 set_gdbarch_long_bit (gdbarch
, long_bit
);
5535 case MIPS_ABI_EABI32
:
5540 case MIPS_ABI_EABI64
:
5541 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5544 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5549 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5550 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5553 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5554 flag in object files because to do so would make it impossible to
5555 link with libraries compiled without "-gp32". This is
5556 unnecessarily restrictive.
5558 We could solve this problem by adding "-gp32" multilibs to gcc,
5559 but to set this flag before gcc is built with such multilibs will
5560 break too many systems.''
5562 But even more unhelpfully, the default linker output target for
5563 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5564 for 64-bit programs - you need to change the ABI to change this,
5565 and not all gcc targets support that currently. Therefore using
5566 this flag to detect 32-bit mode would do the wrong thing given
5567 the current gcc - it would make GDB treat these 64-bit programs
5568 as 32-bit programs by default. */
5570 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5571 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5573 /* Add/remove bits from an address. The MIPS needs be careful to
5574 ensure that all 32 bit addresses are sign extended to 64 bits. */
5575 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5577 /* Unwind the frame. */
5578 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5579 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5580 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5582 /* Map debug register numbers onto internal register numbers. */
5583 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5584 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5585 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5586 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5587 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5588 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5589 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5590 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5592 /* MIPS version of CALL_DUMMY */
5594 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5595 replaced by a command, and all targets will default to on stack
5596 (regardless of the stack's execute status). */
5597 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5598 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5600 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5601 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5602 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5604 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5605 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5607 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5609 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
5611 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5612 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5613 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5615 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5617 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5619 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5621 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5622 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5623 need to all be folded into the target vector. Since they are
5624 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5625 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5627 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5629 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5631 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5633 /* Virtual tables. */
5634 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5636 mips_register_g_packet_guesses (gdbarch
);
5638 /* Hook in OS ABI-specific overrides, if they have been registered. */
5639 info
.tdep_info
= (void *) tdesc_data
;
5640 gdbarch_init_osabi (info
, gdbarch
);
5642 /* Unwind the frame. */
5643 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
5644 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5645 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5646 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5647 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
5648 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5649 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5650 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5654 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
5655 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
5657 /* Override the normal target description methods to handle our
5658 dual real and pseudo registers. */
5659 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5660 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
5662 num_regs
= gdbarch_num_regs (gdbarch
);
5663 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5664 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
5665 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5668 /* Add ABI-specific aliases for the registers. */
5669 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
5670 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
5671 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
5672 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
5674 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
5675 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
5676 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
5678 /* Add some other standard aliases. */
5679 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
5680 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
5681 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
5687 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5689 struct gdbarch_info info
;
5691 /* Force the architecture to update, and (if it's a MIPS architecture)
5692 mips_gdbarch_init will take care of the rest. */
5693 gdbarch_info_init (&info
);
5694 gdbarch_update_p (info
);
5697 /* Print out which MIPS ABI is in use. */
5700 show_mips_abi (struct ui_file
*file
,
5702 struct cmd_list_element
*ignored_cmd
,
5703 const char *ignored_value
)
5705 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5708 "The MIPS ABI is unknown because the current architecture "
5712 enum mips_abi global_abi
= global_mips_abi ();
5713 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5714 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5716 if (global_abi
== MIPS_ABI_UNKNOWN
)
5719 "The MIPS ABI is set automatically (currently \"%s\").\n",
5721 else if (global_abi
== actual_abi
)
5724 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5728 /* Probably shouldn't happen... */
5731 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5732 actual_abi_str
, mips_abi_strings
[global_abi
]);
5738 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
5740 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5744 int ef_mips_32bitmode
;
5745 /* Determine the ISA. */
5746 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5764 /* Determine the size of a pointer. */
5765 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5766 fprintf_unfiltered (file
,
5767 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5769 fprintf_unfiltered (file
,
5770 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5772 fprintf_unfiltered (file
,
5773 "mips_dump_tdep: ef_mips_arch = %d\n",
5775 fprintf_unfiltered (file
,
5776 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5777 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5778 fprintf_unfiltered (file
,
5779 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5780 mips_mask_address_p (tdep
),
5781 tdep
->default_mask_address_p
);
5783 fprintf_unfiltered (file
,
5784 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5785 MIPS_DEFAULT_FPU_TYPE
,
5786 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5787 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5788 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5790 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5791 fprintf_unfiltered (file
,
5792 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5794 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5795 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5796 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5800 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5803 _initialize_mips_tdep (void)
5805 static struct cmd_list_element
*mipsfpulist
= NULL
;
5806 struct cmd_list_element
*c
;
5808 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5809 if (MIPS_ABI_LAST
+ 1
5810 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5811 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
5813 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5815 mips_pdr_data
= register_objfile_data ();
5817 /* Create feature sets with the appropriate properties. The values
5818 are not important. */
5819 mips_tdesc_gp32
= allocate_target_description ();
5820 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
5822 mips_tdesc_gp64
= allocate_target_description ();
5823 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
5825 /* Add root prefix command for all "set mips"/"show mips" commands */
5826 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5827 _("Various MIPS specific commands."),
5828 &setmipscmdlist
, "set mips ", 0, &setlist
);
5830 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5831 _("Various MIPS specific commands."),
5832 &showmipscmdlist
, "show mips ", 0, &showlist
);
5834 /* Allow the user to override the ABI. */
5835 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
5836 &mips_abi_string
, _("\
5837 Set the MIPS ABI used by this program."), _("\
5838 Show the MIPS ABI used by this program."), _("\
5839 This option can be set to one of:\n\
5840 auto - the default ABI associated with the current binary\n\
5849 &setmipscmdlist
, &showmipscmdlist
);
5851 /* Let the user turn off floating point and set the fence post for
5852 heuristic_proc_start. */
5854 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5855 _("Set use of MIPS floating-point coprocessor."),
5856 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5857 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5858 _("Select single-precision MIPS floating-point coprocessor."),
5860 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5861 _("Select double-precision MIPS floating-point coprocessor."),
5863 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5864 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5865 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5866 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5867 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
5868 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5869 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5870 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5871 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5872 _("Select MIPS floating-point coprocessor automatically."),
5874 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5875 _("Show current use of MIPS floating-point coprocessor target."),
5878 /* We really would like to have both "0" and "unlimited" work, but
5879 command.c doesn't deal with that. So make it a var_zinteger
5880 because the user can always use "999999" or some such for unlimited. */
5881 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5882 &heuristic_fence_post
, _("\
5883 Set the distance searched for the start of a function."), _("\
5884 Show the distance searched for the start of a function."), _("\
5885 If you are debugging a stripped executable, GDB needs to search through the\n\
5886 program for the start of a function. This command sets the distance of the\n\
5887 search. The only need to set it is when debugging a stripped executable."),
5888 reinit_frame_cache_sfunc
,
5889 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5890 &setlist
, &showlist
);
5892 /* Allow the user to control whether the upper bits of 64-bit
5893 addresses should be zeroed. */
5894 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
5895 &mask_address_var
, _("\
5896 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5897 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5898 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5899 allow GDB to determine the correct value."),
5900 NULL
, show_mask_address
,
5901 &setmipscmdlist
, &showmipscmdlist
);
5903 /* Allow the user to control the size of 32 bit registers within the
5904 raw remote packet. */
5905 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
5906 &mips64_transfers_32bit_regs_p
, _("\
5907 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5909 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5911 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5912 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5913 64 bits for others. Use \"off\" to disable compatibility mode"),
5914 set_mips64_transfers_32bit_regs
,
5915 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
5916 &setlist
, &showlist
);
5918 /* Debug this files internals. */
5919 add_setshow_zinteger_cmd ("mips", class_maintenance
,
5921 Set mips debugging."), _("\
5922 Show mips debugging."), _("\
5923 When non-zero, mips specific debugging is enabled."),
5925 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
5926 &setdebuglist
, &showdebuglist
);