1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_string.h"
25 #include "gdb_assert.h"
37 #include "arch-utils.h"
40 #include "mips-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/mips.h"
47 #include "sim-regno.h"
49 #include "frame-unwind.h"
50 #include "frame-base.h"
51 #include "trad-frame.h"
53 #include "floatformat.h"
55 #include "target-descriptions.h"
56 #include "dwarf2-frame.h"
57 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *const mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 const struct register_alias mips_numeric_register_aliases
[] = {
146 #define R(n) { #n, n }
147 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
148 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
149 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
150 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
154 #ifndef MIPS_DEFAULT_FPU_TYPE
155 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
157 static int mips_fpu_type_auto
= 1;
158 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
160 static int mips_debug
= 0;
162 /* Properties (for struct target_desc) describing the g/G packet
164 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
165 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
167 struct target_desc
*mips_tdesc_gp32
;
168 struct target_desc
*mips_tdesc_gp64
;
170 const struct mips_regnum
*
171 mips_regnum (struct gdbarch
*gdbarch
)
173 return gdbarch_tdep (gdbarch
)->regnum
;
177 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
179 return mips_regnum (gdbarch
)->fp0
+ 12;
182 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
184 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
186 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
187 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
189 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
190 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
192 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
194 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
195 functions to test, set, or clear bit 0 of addresses. */
198 is_mips16_addr (CORE_ADDR addr
)
204 unmake_mips16_addr (CORE_ADDR addr
)
206 return ((addr
) & ~(CORE_ADDR
) 1);
210 make_mips16_addr (CORE_ADDR addr
)
212 return ((addr
) | (CORE_ADDR
) 1);
215 /* Return the MIPS ABI associated with GDBARCH. */
217 mips_abi (struct gdbarch
*gdbarch
)
219 return gdbarch_tdep (gdbarch
)->mips_abi
;
223 mips_isa_regsize (struct gdbarch
*gdbarch
)
225 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
227 /* If we know how big the registers are, use that size. */
228 if (tdep
->register_size_valid_p
)
229 return tdep
->register_size
;
231 /* Fall back to the previous behavior. */
232 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
233 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
236 /* Return the currently configured (or set) saved register size. */
239 mips_abi_regsize (struct gdbarch
*gdbarch
)
241 switch (mips_abi (gdbarch
))
243 case MIPS_ABI_EABI32
:
249 case MIPS_ABI_EABI64
:
251 case MIPS_ABI_UNKNOWN
:
254 internal_error (__FILE__
, __LINE__
, _("bad switch"));
258 /* Functions for setting and testing a bit in a minimal symbol that
259 marks it as 16-bit function. The MSB of the minimal symbol's
260 "info" field is used for this purpose.
262 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
263 i.e. refers to a 16-bit function, and sets a "special" bit in a
264 minimal symbol to mark it as a 16-bit function
266 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
269 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
271 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
273 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
278 msymbol_is_special (struct minimal_symbol
*msym
)
280 return MSYMBOL_TARGET_FLAG_1 (msym
);
283 /* XFER a value from the big/little/left end of the register.
284 Depending on the size of the value it might occupy the entire
285 register or just part of it. Make an allowance for this, aligning
286 things accordingly. */
289 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
290 int reg_num
, int length
,
291 enum bfd_endian endian
, gdb_byte
*in
,
292 const gdb_byte
*out
, int buf_offset
)
296 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
297 /* Need to transfer the left or right part of the register, based on
298 the targets byte order. */
302 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
304 case BFD_ENDIAN_LITTLE
:
307 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
311 internal_error (__FILE__
, __LINE__
, _("bad switch"));
314 fprintf_unfiltered (gdb_stderr
,
315 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
316 reg_num
, reg_offset
, buf_offset
, length
);
317 if (mips_debug
&& out
!= NULL
)
320 fprintf_unfiltered (gdb_stdlog
, "out ");
321 for (i
= 0; i
< length
; i
++)
322 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
325 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
328 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
330 if (mips_debug
&& in
!= NULL
)
333 fprintf_unfiltered (gdb_stdlog
, "in ");
334 for (i
= 0; i
< length
; i
++)
335 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
338 fprintf_unfiltered (gdb_stdlog
, "\n");
341 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
342 compatiblity mode. A return value of 1 means that we have
343 physical 64-bit registers, but should treat them as 32-bit registers. */
346 mips2_fp_compat (struct frame_info
*frame
)
348 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
349 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
351 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
355 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
356 in all the places we deal with FP registers. PR gdb/413. */
357 /* Otherwise check the FR bit in the status register - it controls
358 the FP compatiblity mode. If it is clear we are in compatibility
360 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
367 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
369 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
371 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
373 /* The list of available "set mips " and "show mips " commands. */
375 static struct cmd_list_element
*setmipscmdlist
= NULL
;
376 static struct cmd_list_element
*showmipscmdlist
= NULL
;
378 /* Integer registers 0 thru 31 are handled explicitly by
379 mips_register_name(). Processor specific registers 32 and above
380 are listed in the following tables. */
383 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
387 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
388 "sr", "lo", "hi", "bad", "cause", "pc",
389 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
390 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
391 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
392 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
396 /* Names of IDT R3041 registers. */
398 static const char *mips_r3041_reg_names
[] = {
399 "sr", "lo", "hi", "bad", "cause", "pc",
400 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
401 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
402 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
403 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
404 "fsr", "fir", "", /*"fp" */ "",
405 "", "", "bus", "ccfg", "", "", "", "",
406 "", "", "port", "cmp", "", "", "epc", "prid",
409 /* Names of tx39 registers. */
411 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
412 "sr", "lo", "hi", "bad", "cause", "pc",
413 "", "", "", "", "", "", "", "",
414 "", "", "", "", "", "", "", "",
415 "", "", "", "", "", "", "", "",
416 "", "", "", "", "", "", "", "",
418 "", "", "", "", "", "", "", "",
419 "", "", "config", "cache", "debug", "depc", "epc",
422 /* Names of IRIX registers. */
423 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
424 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
425 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
426 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
427 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
428 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
431 /* Names of registers with Linux kernels. */
432 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
433 "sr", "lo", "hi", "bad", "cause", "pc",
434 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
435 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
436 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
437 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
442 /* Return the name of the register corresponding to REGNO. */
444 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
446 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
447 /* GPR names for all ABIs other than n32/n64. */
448 static char *mips_gpr_names
[] = {
449 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
450 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
451 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
452 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
455 /* GPR names for n32 and n64 ABIs. */
456 static char *mips_n32_n64_gpr_names
[] = {
457 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
458 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
459 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
460 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
463 enum mips_abi abi
= mips_abi (gdbarch
);
465 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
466 but then don't make the raw register names visible. This (upper)
467 range of user visible register numbers are the pseudo-registers.
469 This approach was adopted accommodate the following scenario:
470 It is possible to debug a 64-bit device using a 32-bit
471 programming model. In such instances, the raw registers are
472 configured to be 64-bits wide, while the pseudo registers are
473 configured to be 32-bits wide. The registers that the user
474 sees - the pseudo registers - match the users expectations
475 given the programming model being used. */
476 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
477 if (regno
< gdbarch_num_regs (gdbarch
))
480 /* The MIPS integer registers are always mapped from 0 to 31. The
481 names of the registers (which reflects the conventions regarding
482 register use) vary depending on the ABI. */
483 if (0 <= rawnum
&& rawnum
< 32)
485 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
486 return mips_n32_n64_gpr_names
[rawnum
];
488 return mips_gpr_names
[rawnum
];
490 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
491 return tdesc_register_name (gdbarch
, rawnum
);
492 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
494 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
495 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
496 return tdep
->mips_processor_reg_names
[rawnum
- 32];
500 internal_error (__FILE__
, __LINE__
,
501 _("mips_register_name: bad register number %d"), rawnum
);
504 /* Return the groups that a MIPS register can be categorised into. */
507 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
508 struct reggroup
*reggroup
)
513 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
514 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
515 if (reggroup
== all_reggroup
)
517 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
518 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
519 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
520 (gdbarch), as not all architectures are multi-arch. */
521 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
522 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
523 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
525 if (reggroup
== float_reggroup
)
526 return float_p
&& pseudo
;
527 if (reggroup
== vector_reggroup
)
528 return vector_p
&& pseudo
;
529 if (reggroup
== general_reggroup
)
530 return (!vector_p
&& !float_p
) && pseudo
;
531 /* Save the pseudo registers. Need to make certain that any code
532 extracting register values from a saved register cache also uses
534 if (reggroup
== save_reggroup
)
535 return raw_p
&& pseudo
;
536 /* Restore the same pseudo register. */
537 if (reggroup
== restore_reggroup
)
538 return raw_p
&& pseudo
;
542 /* Return the groups that a MIPS register can be categorised into.
543 This version is only used if we have a target description which
544 describes real registers (and their groups). */
547 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
548 struct reggroup
*reggroup
)
550 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
551 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
554 /* Only save, restore, and display the pseudo registers. Need to
555 make certain that any code extracting register values from a
556 saved register cache also uses pseudo registers.
558 Note: saving and restoring the pseudo registers is slightly
559 strange; if we have 64 bits, we should save and restore all
560 64 bits. But this is hard and has little benefit. */
564 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
568 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
571 /* Map the symbol table registers which live in the range [1 *
572 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
573 registers. Take care of alignment and size problems. */
575 static enum register_status
576 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
577 int cookednum
, gdb_byte
*buf
)
579 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
580 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
581 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
582 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
583 return regcache_raw_read (regcache
, rawnum
, buf
);
584 else if (register_size (gdbarch
, rawnum
) >
585 register_size (gdbarch
, cookednum
))
587 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
588 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
591 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
593 enum register_status status
;
595 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
596 if (status
== REG_VALID
)
597 store_signed_integer (buf
, 4, byte_order
, regval
);
602 internal_error (__FILE__
, __LINE__
, _("bad register size"));
606 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
607 struct regcache
*regcache
, int cookednum
,
610 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
611 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
612 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
613 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
614 regcache_raw_write (regcache
, rawnum
, buf
);
615 else if (register_size (gdbarch
, rawnum
) >
616 register_size (gdbarch
, cookednum
))
618 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
619 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
622 /* Sign extend the shortened version of the register prior
623 to placing it in the raw register. This is required for
624 some mips64 parts in order to avoid unpredictable behavior. */
625 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
626 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
627 regcache_raw_write_signed (regcache
, rawnum
, regval
);
631 internal_error (__FILE__
, __LINE__
, _("bad register size"));
635 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
636 struct agent_expr
*ax
, int reg
)
638 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
639 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
640 && reg
< 2 * gdbarch_num_regs (gdbarch
));
642 ax_reg_mask (ax
, rawnum
);
648 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
649 struct agent_expr
*ax
, int reg
)
651 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
652 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
653 && reg
< 2 * gdbarch_num_regs (gdbarch
));
654 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
658 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
660 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
661 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
664 ax_simple (ax
, aop_lsh
);
667 ax_simple (ax
, aop_rsh_signed
);
671 internal_error (__FILE__
, __LINE__
, _("bad register size"));
676 /* Table to translate MIPS16 register field to actual register number. */
677 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
679 /* Heuristic_proc_start may hunt through the text section for a long
680 time across a 2400 baud serial line. Allows the user to limit this
683 static unsigned int heuristic_fence_post
= 0;
685 /* Number of bytes of storage in the actual machine representation for
686 register N. NOTE: This defines the pseudo register type so need to
687 rebuild the architecture vector. */
689 static int mips64_transfers_32bit_regs_p
= 0;
692 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
693 struct cmd_list_element
*c
)
695 struct gdbarch_info info
;
696 gdbarch_info_init (&info
);
697 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
698 instead of relying on globals. Doing that would let generic code
699 handle the search for this specific architecture. */
700 if (!gdbarch_update_p (info
))
702 mips64_transfers_32bit_regs_p
= 0;
703 error (_("32-bit compatibility mode not supported"));
707 /* Convert to/from a register and the corresponding memory value. */
709 /* This predicate tests for the case of an 8 byte floating point
710 value that is being transferred to or from a pair of floating point
711 registers each of which are (or are considered to be) only 4 bytes
714 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
717 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
718 && register_size (gdbarch
, regnum
) == 4
719 && (regnum
% gdbarch_num_regs (gdbarch
))
720 >= mips_regnum (gdbarch
)->fp0
721 && (regnum
% gdbarch_num_regs (gdbarch
))
722 < mips_regnum (gdbarch
)->fp0
+ 32
723 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
726 /* This predicate tests for the case of a value of less than 8
727 bytes in width that is being transfered to or from an 8 byte
728 general purpose register. */
730 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
733 int num_regs
= gdbarch_num_regs (gdbarch
);
735 return (register_size (gdbarch
, regnum
) == 8
736 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
737 && TYPE_LENGTH (type
) < 8);
741 mips_convert_register_p (struct gdbarch
*gdbarch
,
742 int regnum
, struct type
*type
)
744 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
745 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
749 mips_register_to_value (struct frame_info
*frame
, int regnum
,
750 struct type
*type
, gdb_byte
*to
,
751 int *optimizedp
, int *unavailablep
)
753 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
755 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
757 get_frame_register (frame
, regnum
+ 0, to
+ 4);
758 get_frame_register (frame
, regnum
+ 1, to
+ 0);
760 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
761 optimizedp
, unavailablep
))
764 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
765 optimizedp
, unavailablep
))
767 *optimizedp
= *unavailablep
= 0;
770 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
772 int len
= TYPE_LENGTH (type
);
775 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
776 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
777 optimizedp
, unavailablep
))
780 *optimizedp
= *unavailablep
= 0;
785 internal_error (__FILE__
, __LINE__
,
786 _("mips_register_to_value: unrecognized case"));
791 mips_value_to_register (struct frame_info
*frame
, int regnum
,
792 struct type
*type
, const gdb_byte
*from
)
794 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
796 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
798 put_frame_register (frame
, regnum
+ 0, from
+ 4);
799 put_frame_register (frame
, regnum
+ 1, from
+ 0);
801 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
804 int len
= TYPE_LENGTH (type
);
806 /* Sign extend values, irrespective of type, that are stored to
807 a 64-bit general purpose register. (32-bit unsigned values
808 are stored as signed quantities within a 64-bit register.
809 When performing an operation, in compiled code, that combines
810 a 32-bit unsigned value with a signed 64-bit value, a type
811 conversion is first performed that zeroes out the high 32 bits.) */
812 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
815 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
817 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
818 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
819 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
823 if (from
[len
-1] & 0x80)
824 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
826 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
827 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
828 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
833 internal_error (__FILE__
, __LINE__
,
834 _("mips_value_to_register: unrecognized case"));
838 /* Return the GDB type object for the "standard" data type of data in
842 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
844 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
845 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
846 && (regnum
% gdbarch_num_regs (gdbarch
))
847 < mips_regnum (gdbarch
)->fp0
+ 32)
849 /* The floating-point registers raw, or cooked, always match
850 mips_isa_regsize(), and also map 1:1, byte for byte. */
851 if (mips_isa_regsize (gdbarch
) == 4)
852 return builtin_type (gdbarch
)->builtin_float
;
854 return builtin_type (gdbarch
)->builtin_double
;
856 else if (regnum
< gdbarch_num_regs (gdbarch
))
858 /* The raw or ISA registers. These are all sized according to
860 if (mips_isa_regsize (gdbarch
) == 4)
861 return builtin_type (gdbarch
)->builtin_int32
;
863 return builtin_type (gdbarch
)->builtin_int64
;
867 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
869 /* The cooked or ABI registers. These are sized according to
870 the ABI (with a few complications). */
871 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
872 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
873 return builtin_type (gdbarch
)->builtin_int32
;
874 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
875 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
876 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
877 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
878 /* The pseudo/cooked view of the embedded registers is always
879 32-bit. The raw view is handled below. */
880 return builtin_type (gdbarch
)->builtin_int32
;
881 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
882 /* The target, while possibly using a 64-bit register buffer,
883 is only transfering 32-bits of each integer register.
884 Reflect this in the cooked/pseudo (ABI) register value. */
885 return builtin_type (gdbarch
)->builtin_int32
;
886 else if (mips_abi_regsize (gdbarch
) == 4)
887 /* The ABI is restricted to 32-bit registers (the ISA could be
889 return builtin_type (gdbarch
)->builtin_int32
;
892 return builtin_type (gdbarch
)->builtin_int64
;
896 /* Return the GDB type for the pseudo register REGNUM, which is the
897 ABI-level view. This function is only called if there is a target
898 description which includes registers, so we know precisely the
899 types of hardware registers. */
902 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
904 const int num_regs
= gdbarch_num_regs (gdbarch
);
905 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
906 int rawnum
= regnum
% num_regs
;
907 struct type
*rawtype
;
909 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
911 /* Absent registers are still absent. */
912 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
913 if (TYPE_LENGTH (rawtype
) == 0)
916 if (rawnum
>= mips_regnum (gdbarch
)->fp0
917 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32)
918 /* Present the floating point registers however the hardware did;
919 do not try to convert between FPU layouts. */
922 /* Use pointer types for registers if we can. For n32 we can not,
923 since we do not have a 64-bit pointer type. */
924 if (mips_abi_regsize (gdbarch
)
925 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
927 if (rawnum
== MIPS_SP_REGNUM
928 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
929 return builtin_type (gdbarch
)->builtin_data_ptr
;
930 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
931 return builtin_type (gdbarch
)->builtin_func_ptr
;
934 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
935 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
936 || rawnum
== mips_regnum (gdbarch
)->lo
937 || rawnum
== mips_regnum (gdbarch
)->hi
938 || rawnum
== mips_regnum (gdbarch
)->badvaddr
939 || rawnum
== mips_regnum (gdbarch
)->cause
940 || rawnum
== mips_regnum (gdbarch
)->pc
941 || (mips_regnum (gdbarch
)->dspacc
!= -1
942 && rawnum
>= mips_regnum (gdbarch
)->dspacc
943 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
944 return builtin_type (gdbarch
)->builtin_int32
;
946 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
947 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
948 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
949 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
951 /* The pseudo/cooked view of embedded registers is always
952 32-bit, even if the target transfers 64-bit values for them.
953 New targets relying on XML descriptions should only transfer
954 the necessary 32 bits, but older versions of GDB expected 64,
955 so allow the target to provide 64 bits without interfering
956 with the displayed type. */
957 return builtin_type (gdbarch
)->builtin_int32
;
960 /* For all other registers, pass through the hardware type. */
964 /* Should the upper word of 64-bit addresses be zeroed? */
965 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
968 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
970 switch (mask_address_var
)
972 case AUTO_BOOLEAN_TRUE
:
974 case AUTO_BOOLEAN_FALSE
:
977 case AUTO_BOOLEAN_AUTO
:
978 return tdep
->default_mask_address_p
;
980 internal_error (__FILE__
, __LINE__
,
981 _("mips_mask_address_p: bad switch"));
987 show_mask_address (struct ui_file
*file
, int from_tty
,
988 struct cmd_list_element
*c
, const char *value
)
990 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
992 deprecated_show_value_hack (file
, from_tty
, c
, value
);
993 switch (mask_address_var
)
995 case AUTO_BOOLEAN_TRUE
:
996 printf_filtered ("The 32 bit mips address mask is enabled\n");
998 case AUTO_BOOLEAN_FALSE
:
999 printf_filtered ("The 32 bit mips address mask is disabled\n");
1001 case AUTO_BOOLEAN_AUTO
:
1003 ("The 32 bit address mask is set automatically. Currently %s\n",
1004 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1007 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1012 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1015 mips_pc_is_mips16 (CORE_ADDR memaddr
)
1017 struct minimal_symbol
*sym
;
1019 /* A flag indicating that this is a MIPS16 function is stored by
1020 elfread.c in the high bit of the info field. Use this to decide
1021 if the function is MIPS16 or normal MIPS. Otherwise if bit 0 of
1022 the address is set, assume this is a MIPS16 address. */
1023 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1025 return msymbol_is_special (sym
);
1027 return is_mips16_addr (memaddr
);
1030 /* MIPS believes that the PC has a sign extended value. Perhaps the
1031 all registers should be sign extended for simplicity? */
1034 mips_read_pc (struct regcache
*regcache
)
1037 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1038 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1039 if (is_mips16_addr (pc
))
1040 pc
= unmake_mips16_addr (pc
);
1045 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1049 pc
= frame_unwind_register_signed
1050 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
1051 if (is_mips16_addr (pc
))
1052 pc
= unmake_mips16_addr (pc
);
1057 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1059 return frame_unwind_register_signed
1060 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1063 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1064 dummy frame. The frame ID's base needs to match the TOS value
1065 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1068 static struct frame_id
1069 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1071 return frame_id_build
1072 (get_frame_register_signed (this_frame
,
1073 gdbarch_num_regs (gdbarch
)
1075 get_frame_pc (this_frame
));
1079 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1081 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1082 if (mips_pc_is_mips16 (pc
))
1083 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
1085 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1088 /* Fetch and return instruction from the specified location. If the PC
1089 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1092 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1094 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1095 gdb_byte buf
[MIPS_INSN32_SIZE
];
1099 if (mips_pc_is_mips16 (addr
))
1101 instlen
= MIPS_INSN16_SIZE
;
1102 addr
= unmake_mips16_addr (addr
);
1105 instlen
= MIPS_INSN32_SIZE
;
1106 status
= target_read_memory (addr
, buf
, instlen
);
1108 memory_error (status
, addr
);
1109 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1112 /* These are the fields of 32 bit mips instructions. */
1113 #define mips32_op(x) (x >> 26)
1114 #define itype_op(x) (x >> 26)
1115 #define itype_rs(x) ((x >> 21) & 0x1f)
1116 #define itype_rt(x) ((x >> 16) & 0x1f)
1117 #define itype_immediate(x) (x & 0xffff)
1119 #define jtype_op(x) (x >> 26)
1120 #define jtype_target(x) (x & 0x03ffffff)
1122 #define rtype_op(x) (x >> 26)
1123 #define rtype_rs(x) ((x >> 21) & 0x1f)
1124 #define rtype_rt(x) ((x >> 16) & 0x1f)
1125 #define rtype_rd(x) ((x >> 11) & 0x1f)
1126 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1127 #define rtype_funct(x) (x & 0x3f)
1130 mips32_relative_offset (ULONGEST inst
)
1132 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1135 /* Determine the address of the next instruction executed after the INST
1136 floating condition branch instruction at PC. COUNT specifies the
1137 number of the floating condition bits tested by the branch. */
1140 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1141 ULONGEST inst
, CORE_ADDR pc
, int count
)
1143 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1144 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1145 int tf
= itype_rt (inst
) & 1;
1146 int mask
= (1 << count
) - 1;
1151 /* No way to handle; it'll most likely trap anyway. */
1154 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1155 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1157 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1158 pc
+= mips32_relative_offset (inst
);
1165 /* Determine where to set a single step breakpoint while considering
1166 branch prediction. */
1168 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1170 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1173 inst
= mips_fetch_instruction (gdbarch
, pc
);
1174 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1177 if (itype_op (inst
) >> 2 == 5)
1178 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1180 op
= (itype_op (inst
) & 0x03);
1190 goto greater_branch
;
1195 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1196 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1197 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1198 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 9
1199 && (itype_rt (inst
) & 2) == 0)
1200 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1201 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1202 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 10
1203 && (itype_rt (inst
) & 2) == 0)
1204 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1205 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1206 else if (itype_op (inst
) == 29)
1208 /* The new PC will be alternate mode. */
1212 reg
= jtype_target (inst
) << 2;
1213 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1214 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1217 pc
+= 4; /* Not a branch, next instruction is easy. */
1220 { /* This gets way messy. */
1222 /* Further subdivide into SPECIAL, REGIMM and other. */
1223 switch (op
= itype_op (inst
) & 0x07) /* Extract bits 28,27,26. */
1225 case 0: /* SPECIAL */
1226 op
= rtype_funct (inst
);
1231 /* Set PC to that address. */
1232 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1234 case 12: /* SYSCALL */
1236 struct gdbarch_tdep
*tdep
;
1238 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1239 if (tdep
->syscall_next_pc
!= NULL
)
1240 pc
= tdep
->syscall_next_pc (frame
);
1249 break; /* end SPECIAL */
1250 case 1: /* REGIMM */
1252 op
= itype_rt (inst
); /* branch condition */
1257 case 16: /* BLTZAL */
1258 case 18: /* BLTZALL */
1260 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1261 pc
+= mips32_relative_offset (inst
) + 4;
1263 pc
+= 8; /* after the delay slot */
1267 case 17: /* BGEZAL */
1268 case 19: /* BGEZALL */
1269 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1270 pc
+= mips32_relative_offset (inst
) + 4;
1272 pc
+= 8; /* after the delay slot */
1274 case 0x1c: /* BPOSGE32 */
1275 case 0x1e: /* BPOSGE64 */
1277 if (itype_rs (inst
) == 0)
1279 unsigned int pos
= (op
& 2) ? 64 : 32;
1280 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1283 /* No way to handle; it'll most likely trap anyway. */
1286 if ((get_frame_register_unsigned (frame
,
1287 dspctl
) & 0x7f) >= pos
)
1288 pc
+= mips32_relative_offset (inst
);
1293 /* All of the other instructions in the REGIMM category */
1298 break; /* end REGIMM */
1303 reg
= jtype_target (inst
) << 2;
1304 /* Upper four bits get never changed... */
1305 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1308 case 4: /* BEQ, BEQL */
1310 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1311 get_frame_register_signed (frame
, itype_rt (inst
)))
1312 pc
+= mips32_relative_offset (inst
) + 4;
1316 case 5: /* BNE, BNEL */
1318 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1319 get_frame_register_signed (frame
, itype_rt (inst
)))
1320 pc
+= mips32_relative_offset (inst
) + 4;
1324 case 6: /* BLEZ, BLEZL */
1325 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1326 pc
+= mips32_relative_offset (inst
) + 4;
1332 greater_branch
: /* BGTZ, BGTZL */
1333 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1334 pc
+= mips32_relative_offset (inst
) + 4;
1341 } /* mips32_next_pc */
1343 /* Decoding the next place to set a breakpoint is irregular for the
1344 mips 16 variant, but fortunately, there fewer instructions. We have
1345 to cope ith extensions for 16 bit instructions and a pair of actual
1346 32 bit instructions. We dont want to set a single step instruction
1347 on the extend instruction either. */
1349 /* Lots of mips16 instruction formats */
1350 /* Predicting jumps requires itype,ritype,i8type
1351 and their extensions extItype,extritype,extI8type. */
1352 enum mips16_inst_fmts
1354 itype
, /* 0 immediate 5,10 */
1355 ritype
, /* 1 5,3,8 */
1356 rrtype
, /* 2 5,3,3,5 */
1357 rritype
, /* 3 5,3,3,5 */
1358 rrrtype
, /* 4 5,3,3,3,2 */
1359 rriatype
, /* 5 5,3,3,1,4 */
1360 shifttype
, /* 6 5,3,3,3,2 */
1361 i8type
, /* 7 5,3,8 */
1362 i8movtype
, /* 8 5,3,3,5 */
1363 i8mov32rtype
, /* 9 5,3,5,3 */
1364 i64type
, /* 10 5,3,8 */
1365 ri64type
, /* 11 5,3,3,5 */
1366 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1367 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1368 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1369 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1370 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1371 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1372 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1373 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1374 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1375 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1377 /* I am heaping all the fields of the formats into one structure and
1378 then, only the fields which are involved in instruction extension. */
1382 unsigned int regx
; /* Function in i8 type. */
1387 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1388 for the bits which make up the immediate extension. */
1391 extended_offset (unsigned int extension
)
1395 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
1397 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
1399 value
|= extension
& 0x1f; /* Extract 4:0. */
1404 /* Only call this function if you know that this is an extendable
1405 instruction. It won't malfunction, but why make excess remote memory
1406 references? If the immediate operands get sign extended or something,
1407 do it after the extension is performed. */
1408 /* FIXME: Every one of these cases needs to worry about sign extension
1409 when the offset is to be used in relative addressing. */
1412 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1414 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1416 pc
&= 0xfffffffe; /* Clear the low order bit. */
1417 target_read_memory (pc
, buf
, 2);
1418 return extract_unsigned_integer (buf
, 2, byte_order
);
1422 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1423 unsigned int extension
,
1425 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1430 switch (insn_format
)
1437 value
= extended_offset ((extension
<< 16) | inst
);
1438 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1442 value
= inst
& 0x7ff;
1443 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
1452 { /* A register identifier and an offset. */
1453 /* Most of the fields are the same as I type but the
1454 immediate value is of a different length. */
1458 value
= extended_offset ((extension
<< 16) | inst
);
1459 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1463 value
= inst
& 0xff; /* 8 bits */
1464 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
1467 regx
= (inst
>> 8) & 0x07; /* i8 funct */
1473 unsigned long value
;
1474 unsigned int nexthalf
;
1475 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1476 value
= value
<< 16;
1477 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit
1486 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1488 upk
->offset
= offset
;
1495 add_offset_16 (CORE_ADDR pc
, int offset
)
1497 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1501 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1502 unsigned int extension
, unsigned int insn
)
1504 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1505 int op
= (insn
>> 11);
1508 case 2: /* Branch */
1511 struct upk_mips16 upk
;
1512 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1513 pc
+= (upk
.offset
<< 1) + 2;
1516 case 3: /* JAL , JALX - Watch out, these are 32 bit
1519 struct upk_mips16 upk
;
1520 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1521 pc
= add_offset_16 (pc
, upk
.offset
);
1522 if ((insn
>> 10) & 0x01) /* Exchange mode */
1523 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
1530 struct upk_mips16 upk
;
1532 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1533 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1535 pc
+= (upk
.offset
<< 1) + 2;
1542 struct upk_mips16 upk
;
1544 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1545 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1547 pc
+= (upk
.offset
<< 1) + 2;
1552 case 12: /* I8 Formats btez btnez */
1554 struct upk_mips16 upk
;
1556 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1557 /* upk.regx contains the opcode */
1558 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1559 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1560 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1561 /* pc = add_offset_16(pc,upk.offset) ; */
1562 pc
+= (upk
.offset
<< 1) + 2;
1567 case 29: /* RR Formats JR, JALR, JALR-RA */
1569 struct upk_mips16 upk
;
1570 /* upk.fmt = rrtype; */
1575 upk
.regx
= (insn
>> 8) & 0x07;
1576 upk
.regy
= (insn
>> 5) & 0x07;
1577 if ((upk
.regy
& 1) == 0)
1578 reg
= mips16_to_32_reg
[upk
.regx
];
1580 reg
= 31; /* Function return instruction. */
1581 pc
= get_frame_register_signed (frame
, reg
);
1588 /* This is an instruction extension. Fetch the real instruction
1589 (which follows the extension) and decode things based on
1593 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1594 fetch_mips_16 (gdbarch
, pc
));
1607 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1609 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1610 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1611 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1614 /* The mips_next_pc function supports single_step when the remote
1615 target monitor or stub is not developed enough to do a single_step.
1616 It works by decoding the current instruction and predicting where a
1617 branch will go. This isnt hard because all the data is available.
1618 The MIPS32 and MIPS16 variants are quite different. */
1620 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1622 if (mips_pc_is_mips16 (pc
))
1623 return mips16_next_pc (frame
, pc
);
1625 return mips32_next_pc (frame
, pc
);
1628 struct mips_frame_cache
1631 struct trad_frame_saved_reg
*saved_regs
;
1634 /* Set a register's saved stack address in temp_saved_regs. If an
1635 address has already been set for this register, do nothing; this
1636 way we will only recognize the first save of a given register in a
1639 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1640 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1641 Strictly speaking, only the second range is used as it is only second
1642 range (the ABI instead of ISA registers) that comes into play when finding
1643 saved registers in a frame. */
1646 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1647 int regnum
, CORE_ADDR offset
)
1649 if (this_cache
!= NULL
1650 && this_cache
->saved_regs
[regnum
].addr
== -1)
1652 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1654 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1660 /* Fetch the immediate value from a MIPS16 instruction.
1661 If the previous instruction was an EXTEND, use it to extend
1662 the upper bits of the immediate value. This is a helper function
1663 for mips16_scan_prologue. */
1666 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1667 unsigned short inst
, /* current instruction */
1668 int nbits
, /* number of bits in imm field */
1669 int scale
, /* scale factor to be applied to imm */
1670 int is_signed
) /* is the imm field signed? */
1674 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1676 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1677 if (offset
& 0x8000) /* check for negative extend */
1678 offset
= 0 - (0x10000 - (offset
& 0xffff));
1679 return offset
| (inst
& 0x1f);
1683 int max_imm
= 1 << nbits
;
1684 int mask
= max_imm
- 1;
1685 int sign_bit
= max_imm
>> 1;
1687 offset
= inst
& mask
;
1688 if (is_signed
&& (offset
& sign_bit
))
1689 offset
= 0 - (max_imm
- offset
);
1690 return offset
* scale
;
1695 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1696 the associated FRAME_CACHE if not null.
1697 Return the address of the first instruction past the prologue. */
1700 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1701 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1702 struct frame_info
*this_frame
,
1703 struct mips_frame_cache
*this_cache
)
1706 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
1708 long frame_offset
= 0; /* Size of stack frame. */
1709 long frame_adjust
= 0; /* Offset of FP from SP. */
1710 int frame_reg
= MIPS_SP_REGNUM
;
1711 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
1712 unsigned inst
= 0; /* current instruction */
1713 unsigned entry_inst
= 0; /* the entry instruction */
1714 unsigned save_inst
= 0; /* the save instruction */
1717 int extend_bytes
= 0;
1718 int prev_extend_bytes
;
1719 CORE_ADDR end_prologue_addr
= 0;
1721 /* Can be called when there's no process, and hence when there's no
1723 if (this_frame
!= NULL
)
1724 sp
= get_frame_register_signed (this_frame
,
1725 gdbarch_num_regs (gdbarch
)
1730 if (limit_pc
> start_pc
+ 200)
1731 limit_pc
= start_pc
+ 200;
1733 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1735 /* Save the previous instruction. If it's an EXTEND, we'll extract
1736 the immediate offset extension from it in mips16_get_imm. */
1739 /* Fetch and decode the instruction. */
1740 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1742 /* Normally we ignore extend instructions. However, if it is
1743 not followed by a valid prologue instruction, then this
1744 instruction is not part of the prologue either. We must
1745 remember in this case to adjust the end_prologue_addr back
1747 if ((inst
& 0xf800) == 0xf000) /* extend */
1749 extend_bytes
= MIPS_INSN16_SIZE
;
1753 prev_extend_bytes
= extend_bytes
;
1756 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1757 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1759 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1760 if (offset
< 0) /* Negative stack adjustment? */
1761 frame_offset
-= offset
;
1763 /* Exit loop if a positive stack adjustment is found, which
1764 usually means that the stack cleanup code in the function
1765 epilogue is reached. */
1768 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1770 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1771 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1772 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1774 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1776 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1777 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1778 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1780 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1782 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1783 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1785 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1787 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1788 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1790 else if (inst
== 0x673d) /* move $s1, $sp */
1795 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1797 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1798 frame_addr
= sp
+ offset
;
1800 frame_adjust
= offset
;
1802 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1804 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1805 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1806 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1808 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1810 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1811 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1812 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1814 else if ((inst
& 0xf81f) == 0xe809
1815 && (inst
& 0x700) != 0x700) /* entry */
1816 entry_inst
= inst
; /* Save for later processing. */
1817 else if ((inst
& 0xff80) == 0x6480) /* save */
1819 save_inst
= inst
; /* Save for later processing. */
1820 if (prev_extend_bytes
) /* extend */
1821 save_inst
|= prev_inst
<< 16;
1823 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1824 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1825 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1827 /* This instruction is part of the prologue, but we don't
1828 need to do anything special to handle it. */
1832 /* This instruction is not an instruction typically found
1833 in a prologue, so we must have reached the end of the
1835 if (end_prologue_addr
== 0)
1836 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1840 /* The entry instruction is typically the first instruction in a function,
1841 and it stores registers at offsets relative to the value of the old SP
1842 (before the prologue). But the value of the sp parameter to this
1843 function is the new SP (after the prologue has been executed). So we
1844 can't calculate those offsets until we've seen the entire prologue,
1845 and can calculate what the old SP must have been. */
1846 if (entry_inst
!= 0)
1848 int areg_count
= (entry_inst
>> 8) & 7;
1849 int sreg_count
= (entry_inst
>> 6) & 3;
1851 /* The entry instruction always subtracts 32 from the SP. */
1854 /* Now we can calculate what the SP must have been at the
1855 start of the function prologue. */
1858 /* Check if a0-a3 were saved in the caller's argument save area. */
1859 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1861 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1862 offset
+= mips_abi_regsize (gdbarch
);
1865 /* Check if the ra register was pushed on the stack. */
1867 if (entry_inst
& 0x20)
1869 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1870 offset
-= mips_abi_regsize (gdbarch
);
1873 /* Check if the s0 and s1 registers were pushed on the stack. */
1874 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1876 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1877 offset
-= mips_abi_regsize (gdbarch
);
1881 /* The SAVE instruction is similar to ENTRY, except that defined by the
1882 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1883 size of the frame is specified as an immediate field of instruction
1884 and an extended variation exists which lets additional registers and
1885 frame space to be specified. The instruction always treats registers
1886 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1887 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1889 static int args_table
[16] = {
1890 0, 0, 0, 0, 1, 1, 1, 1,
1891 2, 2, 2, 0, 3, 3, 4, -1,
1893 static int astatic_table
[16] = {
1894 0, 1, 2, 3, 0, 1, 2, 3,
1895 0, 1, 2, 4, 0, 1, 0, -1,
1897 int aregs
= (save_inst
>> 16) & 0xf;
1898 int xsregs
= (save_inst
>> 24) & 0x7;
1899 int args
= args_table
[aregs
];
1900 int astatic
= astatic_table
[aregs
];
1905 warning (_("Invalid number of argument registers encoded in SAVE."));
1910 warning (_("Invalid number of static registers encoded in SAVE."));
1914 /* For standard SAVE the frame size of 0 means 128. */
1915 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1916 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1919 frame_offset
+= frame_size
;
1921 /* Now we can calculate what the SP must have been at the
1922 start of the function prologue. */
1925 /* Check if A0-A3 were saved in the caller's argument save area. */
1926 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1928 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1929 offset
+= mips_abi_regsize (gdbarch
);
1934 /* Check if the RA register was pushed on the stack. */
1935 if (save_inst
& 0x40)
1937 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1938 offset
-= mips_abi_regsize (gdbarch
);
1941 /* Check if the S8 register was pushed on the stack. */
1944 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1945 offset
-= mips_abi_regsize (gdbarch
);
1948 /* Check if S2-S7 were pushed on the stack. */
1949 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1951 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1952 offset
-= mips_abi_regsize (gdbarch
);
1955 /* Check if the S1 register was pushed on the stack. */
1956 if (save_inst
& 0x10)
1958 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1959 offset
-= mips_abi_regsize (gdbarch
);
1961 /* Check if the S0 register was pushed on the stack. */
1962 if (save_inst
& 0x20)
1964 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1965 offset
-= mips_abi_regsize (gdbarch
);
1968 /* Check if A0-A3 were pushed on the stack. */
1969 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1971 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1972 offset
-= mips_abi_regsize (gdbarch
);
1976 if (this_cache
!= NULL
)
1979 (get_frame_register_signed (this_frame
,
1980 gdbarch_num_regs (gdbarch
) + frame_reg
)
1981 + frame_offset
- frame_adjust
);
1982 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1983 be able to get rid of the assignment below, evetually. But it's
1984 still needed for now. */
1985 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1986 + mips_regnum (gdbarch
)->pc
]
1987 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1990 /* If we didn't reach the end of the prologue when scanning the function
1991 instructions, then set end_prologue_addr to the address of the
1992 instruction immediately after the last one we scanned. */
1993 if (end_prologue_addr
== 0)
1994 end_prologue_addr
= cur_pc
;
1996 return end_prologue_addr
;
1999 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2000 Procedures that use the 32-bit instruction set are handled by the
2001 mips_insn32 unwinder. */
2003 static struct mips_frame_cache
*
2004 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2006 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2007 struct mips_frame_cache
*cache
;
2009 if ((*this_cache
) != NULL
)
2010 return (*this_cache
);
2011 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2012 (*this_cache
) = cache
;
2013 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2015 /* Analyze the function prologue. */
2017 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2018 CORE_ADDR start_addr
;
2020 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2021 if (start_addr
== 0)
2022 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2023 /* We can't analyze the prologue if we couldn't find the begining
2025 if (start_addr
== 0)
2028 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2031 /* gdbarch_sp_regnum contains the value and not the address. */
2032 trad_frame_set_value (cache
->saved_regs
,
2033 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2036 return (*this_cache
);
2040 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2041 struct frame_id
*this_id
)
2043 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2045 /* This marks the outermost frame. */
2046 if (info
->base
== 0)
2048 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2051 static struct value
*
2052 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2053 void **this_cache
, int regnum
)
2055 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2057 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2061 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2062 struct frame_info
*this_frame
, void **this_cache
)
2064 CORE_ADDR pc
= get_frame_pc (this_frame
);
2065 if (mips_pc_is_mips16 (pc
))
2070 static const struct frame_unwind mips_insn16_frame_unwind
=
2073 default_frame_unwind_stop_reason
,
2074 mips_insn16_frame_this_id
,
2075 mips_insn16_frame_prev_register
,
2077 mips_insn16_frame_sniffer
2081 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2084 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2089 static const struct frame_base mips_insn16_frame_base
=
2091 &mips_insn16_frame_unwind
,
2092 mips_insn16_frame_base_address
,
2093 mips_insn16_frame_base_address
,
2094 mips_insn16_frame_base_address
2097 static const struct frame_base
*
2098 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2100 CORE_ADDR pc
= get_frame_pc (this_frame
);
2101 if (mips_pc_is_mips16 (pc
))
2102 return &mips_insn16_frame_base
;
2107 /* Mark all the registers as unset in the saved_regs array
2108 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2111 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
2113 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2117 const int num_regs
= gdbarch_num_regs (gdbarch
);
2120 for (i
= 0; i
< num_regs
; i
++)
2122 this_cache
->saved_regs
[i
].addr
= -1;
2127 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2128 the associated FRAME_CACHE if not null.
2129 Return the address of the first instruction past the prologue. */
2132 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2133 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2134 struct frame_info
*this_frame
,
2135 struct mips_frame_cache
*this_cache
)
2138 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
2142 int frame_reg
= MIPS_SP_REGNUM
;
2144 CORE_ADDR end_prologue_addr
= 0;
2145 int seen_sp_adjust
= 0;
2146 int load_immediate_bytes
= 0;
2147 int in_delay_slot
= 0;
2148 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2150 /* Can be called when there's no process, and hence when there's no
2152 if (this_frame
!= NULL
)
2153 sp
= get_frame_register_signed (this_frame
,
2154 gdbarch_num_regs (gdbarch
)
2159 if (limit_pc
> start_pc
+ 200)
2160 limit_pc
= start_pc
+ 200;
2165 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2167 unsigned long inst
, high_word
, low_word
;
2170 /* Fetch the instruction. */
2171 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2173 /* Save some code by pre-extracting some useful fields. */
2174 high_word
= (inst
>> 16) & 0xffff;
2175 low_word
= inst
& 0xffff;
2176 reg
= high_word
& 0x1f;
2178 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2179 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2180 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2182 if (low_word
& 0x8000) /* Negative stack adjustment? */
2183 frame_offset
+= 0x10000 - low_word
;
2185 /* Exit loop if a positive stack adjustment is found, which
2186 usually means that the stack cleanup code in the function
2187 epilogue is reached. */
2191 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2192 && !regsize_is_64_bits
)
2194 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2196 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2197 && regsize_is_64_bits
)
2199 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2200 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2202 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2204 /* Old gcc frame, r30 is virtual frame pointer. */
2205 if ((long) low_word
!= frame_offset
)
2206 frame_addr
= sp
+ low_word
;
2207 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2209 unsigned alloca_adjust
;
2212 frame_addr
= get_frame_register_signed
2213 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2215 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2216 if (alloca_adjust
> 0)
2218 /* FP > SP + frame_size. This may be because of
2219 an alloca or somethings similar. Fix sp to
2220 "pre-alloca" value, and try again. */
2221 sp
+= alloca_adjust
;
2222 /* Need to reset the status of all registers. Otherwise,
2223 we will hit a guard that prevents the new address
2224 for each register to be recomputed during the second
2226 reset_saved_regs (gdbarch
, this_cache
);
2231 /* move $30,$sp. With different versions of gas this will be either
2232 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2233 Accept any one of these. */
2234 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2236 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2237 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2239 unsigned alloca_adjust
;
2242 frame_addr
= get_frame_register_signed
2243 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2245 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2246 if (alloca_adjust
> 0)
2248 /* FP > SP + frame_size. This may be because of
2249 an alloca or somethings similar. Fix sp to
2250 "pre-alloca" value, and try again. */
2252 /* Need to reset the status of all registers. Otherwise,
2253 we will hit a guard that prevents the new address
2254 for each register to be recomputed during the second
2256 reset_saved_regs (gdbarch
, this_cache
);
2261 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2262 && !regsize_is_64_bits
)
2264 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2266 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2267 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2268 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2269 || high_word
== 0x3c1c /* lui $gp,n */
2270 || high_word
== 0x279c /* addiu $gp,$gp,n */
2271 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2272 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2275 /* These instructions are part of the prologue, but we don't
2276 need to do anything special to handle them. */
2278 /* The instructions below load $at or $t0 with an immediate
2279 value in preparation for a stack adjustment via
2280 subu $sp,$sp,[$at,$t0]. These instructions could also
2281 initialize a local variable, so we accept them only before
2282 a stack adjustment instruction was seen. */
2283 else if (!seen_sp_adjust
2284 && (high_word
== 0x3c01 /* lui $at,n */
2285 || high_word
== 0x3c08 /* lui $t0,n */
2286 || high_word
== 0x3421 /* ori $at,$at,n */
2287 || high_word
== 0x3508 /* ori $t0,$t0,n */
2288 || high_word
== 0x3401 /* ori $at,$zero,n */
2289 || high_word
== 0x3408 /* ori $t0,$zero,n */
2292 if (end_prologue_addr
== 0)
2293 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2297 /* This instruction is not an instruction typically found
2298 in a prologue, so we must have reached the end of the
2300 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2301 loop now? Why would we need to continue scanning the function
2303 if (end_prologue_addr
== 0)
2304 end_prologue_addr
= cur_pc
;
2306 /* Check for branches and jumps. For now, only jump to
2307 register are caught (i.e. returns). */
2308 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2312 /* If the previous instruction was a jump, we must have reached
2313 the end of the prologue by now. Stop scanning so that we do
2314 not go past the function return. */
2319 if (this_cache
!= NULL
)
2322 (get_frame_register_signed (this_frame
,
2323 gdbarch_num_regs (gdbarch
) + frame_reg
)
2325 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2326 this assignment below, eventually. But it's still needed
2328 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2329 + mips_regnum (gdbarch
)->pc
]
2330 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2334 /* If we didn't reach the end of the prologue when scanning the function
2335 instructions, then set end_prologue_addr to the address of the
2336 instruction immediately after the last one we scanned. */
2337 /* brobecker/2004-10-10: I don't think this would ever happen, but
2338 we may as well be careful and do our best if we have a null
2339 end_prologue_addr. */
2340 if (end_prologue_addr
== 0)
2341 end_prologue_addr
= cur_pc
;
2343 /* In a frameless function, we might have incorrectly
2344 skipped some load immediate instructions. Undo the skipping
2345 if the load immediate was not followed by a stack adjustment. */
2346 if (load_immediate_bytes
&& !seen_sp_adjust
)
2347 end_prologue_addr
-= load_immediate_bytes
;
2349 return end_prologue_addr
;
2352 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2353 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2354 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2357 static struct mips_frame_cache
*
2358 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2360 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2361 struct mips_frame_cache
*cache
;
2363 if ((*this_cache
) != NULL
)
2364 return (*this_cache
);
2366 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2367 (*this_cache
) = cache
;
2368 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2370 /* Analyze the function prologue. */
2372 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2373 CORE_ADDR start_addr
;
2375 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2376 if (start_addr
== 0)
2377 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2378 /* We can't analyze the prologue if we couldn't find the begining
2380 if (start_addr
== 0)
2383 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2386 /* gdbarch_sp_regnum contains the value and not the address. */
2387 trad_frame_set_value (cache
->saved_regs
,
2388 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2391 return (*this_cache
);
2395 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2396 struct frame_id
*this_id
)
2398 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2400 /* This marks the outermost frame. */
2401 if (info
->base
== 0)
2403 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2406 static struct value
*
2407 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2408 void **this_cache
, int regnum
)
2410 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2412 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2416 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2417 struct frame_info
*this_frame
, void **this_cache
)
2419 CORE_ADDR pc
= get_frame_pc (this_frame
);
2420 if (! mips_pc_is_mips16 (pc
))
2425 static const struct frame_unwind mips_insn32_frame_unwind
=
2428 default_frame_unwind_stop_reason
,
2429 mips_insn32_frame_this_id
,
2430 mips_insn32_frame_prev_register
,
2432 mips_insn32_frame_sniffer
2436 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2439 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2444 static const struct frame_base mips_insn32_frame_base
=
2446 &mips_insn32_frame_unwind
,
2447 mips_insn32_frame_base_address
,
2448 mips_insn32_frame_base_address
,
2449 mips_insn32_frame_base_address
2452 static const struct frame_base
*
2453 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2455 CORE_ADDR pc
= get_frame_pc (this_frame
);
2456 if (! mips_pc_is_mips16 (pc
))
2457 return &mips_insn32_frame_base
;
2462 static struct trad_frame_cache
*
2463 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2466 CORE_ADDR start_addr
;
2467 CORE_ADDR stack_addr
;
2468 struct trad_frame_cache
*this_trad_cache
;
2469 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2470 int num_regs
= gdbarch_num_regs (gdbarch
);
2472 if ((*this_cache
) != NULL
)
2473 return (*this_cache
);
2474 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2475 (*this_cache
) = this_trad_cache
;
2477 /* The return address is in the link register. */
2478 trad_frame_set_reg_realreg (this_trad_cache
,
2479 gdbarch_pc_regnum (gdbarch
),
2480 num_regs
+ MIPS_RA_REGNUM
);
2482 /* Frame ID, since it's a frameless / stackless function, no stack
2483 space is allocated and SP on entry is the current SP. */
2484 pc
= get_frame_pc (this_frame
);
2485 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2486 stack_addr
= get_frame_register_signed (this_frame
,
2487 num_regs
+ MIPS_SP_REGNUM
);
2488 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2490 /* Assume that the frame's base is the same as the
2492 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2494 return this_trad_cache
;
2498 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2499 struct frame_id
*this_id
)
2501 struct trad_frame_cache
*this_trad_cache
2502 = mips_stub_frame_cache (this_frame
, this_cache
);
2503 trad_frame_get_id (this_trad_cache
, this_id
);
2506 static struct value
*
2507 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2508 void **this_cache
, int regnum
)
2510 struct trad_frame_cache
*this_trad_cache
2511 = mips_stub_frame_cache (this_frame
, this_cache
);
2512 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2516 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2517 struct frame_info
*this_frame
, void **this_cache
)
2520 struct obj_section
*s
;
2521 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2522 struct minimal_symbol
*msym
;
2524 /* Use the stub unwinder for unreadable code. */
2525 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2528 if (in_plt_section (pc
, NULL
))
2531 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2532 s
= find_pc_section (pc
);
2535 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2536 ".MIPS.stubs") == 0)
2539 /* Calling a PIC function from a non-PIC function passes through a
2540 stub. The stub for foo is named ".pic.foo". */
2541 msym
= lookup_minimal_symbol_by_pc (pc
);
2543 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2544 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2550 static const struct frame_unwind mips_stub_frame_unwind
=
2553 default_frame_unwind_stop_reason
,
2554 mips_stub_frame_this_id
,
2555 mips_stub_frame_prev_register
,
2557 mips_stub_frame_sniffer
2561 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2564 struct trad_frame_cache
*this_trad_cache
2565 = mips_stub_frame_cache (this_frame
, this_cache
);
2566 return trad_frame_get_this_base (this_trad_cache
);
2569 static const struct frame_base mips_stub_frame_base
=
2571 &mips_stub_frame_unwind
,
2572 mips_stub_frame_base_address
,
2573 mips_stub_frame_base_address
,
2574 mips_stub_frame_base_address
2577 static const struct frame_base
*
2578 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2580 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2581 return &mips_stub_frame_base
;
2586 /* mips_addr_bits_remove - remove useless address bits */
2589 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2591 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2593 if (is_mips16_addr (addr
))
2594 addr
= unmake_mips16_addr (addr
);
2596 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2597 /* This hack is a work-around for existing boards using PMON, the
2598 simulator, and any other 64-bit targets that doesn't have true
2599 64-bit addressing. On these targets, the upper 32 bits of
2600 addresses are ignored by the hardware. Thus, the PC or SP are
2601 likely to have been sign extended to all 1s by instruction
2602 sequences that load 32-bit addresses. For example, a typical
2603 piece of code that loads an address is this:
2605 lui $r2, <upper 16 bits>
2606 ori $r2, <lower 16 bits>
2608 But the lui sign-extends the value such that the upper 32 bits
2609 may be all 1s. The workaround is simply to mask off these
2610 bits. In the future, gcc may be changed to support true 64-bit
2611 addressing, and this masking will have to be disabled. */
2612 return addr
&= 0xffffffffUL
;
2617 /* Instructions used during single-stepping of atomic sequences. */
2618 #define LL_OPCODE 0x30
2619 #define LLD_OPCODE 0x34
2620 #define SC_OPCODE 0x38
2621 #define SCD_OPCODE 0x3c
2623 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2624 instruction and ending with a SC/SCD instruction. If such a sequence
2625 is found, attempt to step through it. A breakpoint is placed at the end of
2629 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2630 struct address_space
*aspace
, CORE_ADDR pc
)
2632 CORE_ADDR breaks
[2] = {-1, -1};
2634 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2638 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2639 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2644 insn
= mips_fetch_instruction (gdbarch
, loc
);
2645 /* Assume all atomic sequences start with a ll/lld instruction. */
2646 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2649 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2651 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2654 loc
+= MIPS_INSN32_SIZE
;
2655 insn
= mips_fetch_instruction (gdbarch
, loc
);
2657 /* Assume that there is at most one branch in the atomic
2658 sequence. If a branch is found, put a breakpoint in its
2659 destination address. */
2660 switch (itype_op (insn
))
2662 case 0: /* SPECIAL */
2663 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2664 return 0; /* fallback to the standard single-step code. */
2666 case 1: /* REGIMM */
2667 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
2668 || ((itype_rt (insn
) & 0x1e) == 0
2669 && itype_rs (insn
) == 0)); /* BPOSGE* */
2673 return 0; /* fallback to the standard single-step code. */
2680 case 22: /* BLEZL */
2681 case 23: /* BGTTL */
2685 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
2686 && (itype_rt (insn
) & 0x2) == 0);
2687 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
2692 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2697 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2698 if (last_breakpoint
>= 1)
2699 return 0; /* More than one branch found, fallback to the
2700 standard single-step code. */
2701 breaks
[1] = branch_bp
;
2705 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2709 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2710 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2713 loc
+= MIPS_INSN32_SIZE
;
2715 /* Insert a breakpoint right after the end of the atomic sequence. */
2718 /* Check for duplicated breakpoints. Check also for a breakpoint
2719 placed (branch instruction's destination) in the atomic sequence. */
2720 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2721 last_breakpoint
= 0;
2723 /* Effectively inserts the breakpoints. */
2724 for (index
= 0; index
<= last_breakpoint
; index
++)
2725 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2730 /* mips_software_single_step() is called just before we want to resume
2731 the inferior, if we want to single-step it but there is no hardware
2732 or kernel single-step support (MIPS on GNU/Linux for example). We find
2733 the target of the coming instruction and breakpoint it. */
2736 mips_software_single_step (struct frame_info
*frame
)
2738 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2739 struct address_space
*aspace
= get_frame_address_space (frame
);
2740 CORE_ADDR pc
, next_pc
;
2742 pc
= get_frame_pc (frame
);
2743 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2746 next_pc
= mips_next_pc (frame
, pc
);
2748 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2752 /* Test whether the PC points to the return instruction at the
2753 end of a function. */
2756 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2758 if (mips_pc_is_mips16 (pc
))
2759 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2760 generates a "jr $ra"; other times it generates code to load
2761 the return address from the stack to an accessible register (such
2762 as $a3), then a "jr" using that register. This second case
2763 is almost impossible to distinguish from an indirect jump
2764 used for switch statements, so we don't even try. */
2765 return mips_fetch_instruction (gdbarch
, pc
) == 0xe820; /* jr $ra */
2767 return mips_fetch_instruction (gdbarch
, pc
) == 0x3e00008; /* jr $ra */
2771 /* This fencepost looks highly suspicious to me. Removing it also
2772 seems suspicious as it could affect remote debugging across serial
2776 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2782 struct inferior
*inf
;
2784 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2786 fence
= start_pc
- heuristic_fence_post
;
2790 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2791 fence
= VM_MIN_ADDRESS
;
2793 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2795 inf
= current_inferior ();
2797 /* Search back for previous return. */
2798 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2799 if (start_pc
< fence
)
2801 /* It's not clear to me why we reach this point when
2802 stop_soon, but with this test, at least we
2803 don't print out warnings for every child forked (eg, on
2804 decstation). 22apr93 rich@cygnus.com. */
2805 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2807 static int blurb_printed
= 0;
2809 warning (_("GDB can't find the start of the function at %s."),
2810 paddress (gdbarch
, pc
));
2814 /* This actually happens frequently in embedded
2815 development, when you first connect to a board
2816 and your stack pointer and pc are nowhere in
2817 particular. This message needs to give people
2818 in that situation enough information to
2819 determine that it's no big deal. */
2820 printf_filtered ("\n\
2821 GDB is unable to find the start of the function at %s\n\
2822 and thus can't determine the size of that function's stack frame.\n\
2823 This means that GDB may be unable to access that stack frame, or\n\
2824 the frames below it.\n\
2825 This problem is most likely caused by an invalid program counter or\n\
2827 However, if you think GDB should simply search farther back\n\
2828 from %s for code which looks like the beginning of a\n\
2829 function, you can increase the range of the search using the `set\n\
2830 heuristic-fence-post' command.\n",
2831 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2838 else if (mips_pc_is_mips16 (start_pc
))
2840 unsigned short inst
;
2842 /* On MIPS16, any one of the following is likely to be the
2843 start of a function:
2849 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
2850 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2851 if ((inst
& 0xff80) == 0x6480) /* save */
2853 if (start_pc
- instlen
>= fence
)
2855 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2856 if ((inst
& 0xf800) == 0xf000) /* extend */
2857 start_pc
-= instlen
;
2861 else if (((inst
& 0xf81f) == 0xe809
2862 && (inst
& 0x700) != 0x700) /* entry */
2863 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2864 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2865 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2867 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2868 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2873 else if (mips_about_to_return (gdbarch
, start_pc
))
2875 /* Skip return and its delay slot. */
2876 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2883 struct mips_objfile_private
2889 /* According to the current ABI, should the type be passed in a
2890 floating-point register (assuming that there is space)? When there
2891 is no FPU, FP are not even considered as possible candidates for
2892 FP registers and, consequently this returns false - forces FP
2893 arguments into integer registers. */
2896 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2897 struct type
*arg_type
)
2899 return ((typecode
== TYPE_CODE_FLT
2900 || (MIPS_EABI (gdbarch
)
2901 && (typecode
== TYPE_CODE_STRUCT
2902 || typecode
== TYPE_CODE_UNION
)
2903 && TYPE_NFIELDS (arg_type
) == 1
2904 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2906 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2909 /* On o32, argument passing in GPRs depends on the alignment of the type being
2910 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2913 mips_type_needs_double_align (struct type
*type
)
2915 enum type_code typecode
= TYPE_CODE (type
);
2917 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2919 else if (typecode
== TYPE_CODE_STRUCT
)
2921 if (TYPE_NFIELDS (type
) < 1)
2923 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2925 else if (typecode
== TYPE_CODE_UNION
)
2929 n
= TYPE_NFIELDS (type
);
2930 for (i
= 0; i
< n
; i
++)
2931 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2938 /* Adjust the address downward (direction of stack growth) so that it
2939 is correctly aligned for a new stack frame. */
2941 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2943 return align_down (addr
, 16);
2947 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2948 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2949 int nargs
, struct value
**args
, CORE_ADDR sp
,
2950 int struct_return
, CORE_ADDR struct_addr
)
2956 int stack_offset
= 0;
2957 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2958 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2959 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2960 int regsize
= mips_abi_regsize (gdbarch
);
2962 /* For shared libraries, "t9" needs to point at the function
2964 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2966 /* Set the return address register to point to the entry point of
2967 the program, where a breakpoint lies in wait. */
2968 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2970 /* First ensure that the stack and structure return address (if any)
2971 are properly aligned. The stack has to be at least 64-bit
2972 aligned even on 32-bit machines, because doubles must be 64-bit
2973 aligned. For n32 and n64, stack frames need to be 128-bit
2974 aligned, so we round to this widest known alignment. */
2976 sp
= align_down (sp
, 16);
2977 struct_addr
= align_down (struct_addr
, 16);
2979 /* Now make space on the stack for the args. We allocate more
2980 than necessary for EABI, because the first few arguments are
2981 passed in registers, but that's OK. */
2982 for (argnum
= 0; argnum
< nargs
; argnum
++)
2983 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2984 sp
-= align_up (len
, 16);
2987 fprintf_unfiltered (gdb_stdlog
,
2988 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2989 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2991 /* Initialize the integer and float register pointers. */
2992 argreg
= MIPS_A0_REGNUM
;
2993 float_argreg
= mips_fpa0_regnum (gdbarch
);
2995 /* The struct_return pointer occupies the first parameter-passing reg. */
2999 fprintf_unfiltered (gdb_stdlog
,
3000 "mips_eabi_push_dummy_call: "
3001 "struct_return reg=%d %s\n",
3002 argreg
, paddress (gdbarch
, struct_addr
));
3003 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3006 /* Now load as many as possible of the first arguments into
3007 registers, and push the rest onto the stack. Loop thru args
3008 from first to last. */
3009 for (argnum
= 0; argnum
< nargs
; argnum
++)
3011 const gdb_byte
*val
;
3012 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
3013 struct value
*arg
= args
[argnum
];
3014 struct type
*arg_type
= check_typedef (value_type (arg
));
3015 int len
= TYPE_LENGTH (arg_type
);
3016 enum type_code typecode
= TYPE_CODE (arg_type
);
3019 fprintf_unfiltered (gdb_stdlog
,
3020 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3021 argnum
+ 1, len
, (int) typecode
);
3023 /* Function pointer arguments to mips16 code need to be made into
3025 if (typecode
== TYPE_CODE_PTR
3026 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
3028 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
3030 if (mips_pc_is_mips16 (addr
))
3032 store_signed_integer (valbuf
, len
, byte_order
,
3033 make_mips16_addr (addr
));
3037 val
= value_contents (arg
);
3039 /* The EABI passes structures that do not fit in a register by
3041 else if (len
> regsize
3042 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3044 store_unsigned_integer (valbuf
, regsize
, byte_order
,
3045 value_address (arg
));
3046 typecode
= TYPE_CODE_PTR
;
3050 fprintf_unfiltered (gdb_stdlog
, " push");
3053 val
= value_contents (arg
);
3055 /* 32-bit ABIs always start floating point arguments in an
3056 even-numbered floating point register. Round the FP register
3057 up before the check to see if there are any FP registers
3058 left. Non MIPS_EABI targets also pass the FP in the integer
3059 registers so also round up normal registers. */
3060 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3062 if ((float_argreg
& 1))
3066 /* Floating point arguments passed in registers have to be
3067 treated specially. On 32-bit architectures, doubles
3068 are passed in register pairs; the even register gets
3069 the low word, and the odd register gets the high word.
3070 On non-EABI processors, the first two floating point arguments are
3071 also copied to general registers, because MIPS16 functions
3072 don't use float registers for arguments. This duplication of
3073 arguments in general registers can't hurt non-MIPS16 functions
3074 because those registers are normally skipped. */
3075 /* MIPS_EABI squeezes a struct that contains a single floating
3076 point value into an FP register instead of pushing it onto the
3078 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3079 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3081 /* EABI32 will pass doubles in consecutive registers, even on
3082 64-bit cores. At one time, we used to check the size of
3083 `float_argreg' to determine whether or not to pass doubles
3084 in consecutive registers, but this is not sufficient for
3085 making the ABI determination. */
3086 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
3088 int low_offset
= gdbarch_byte_order (gdbarch
)
3089 == BFD_ENDIAN_BIG
? 4 : 0;
3092 /* Write the low word of the double to the even register(s). */
3093 regval
= extract_signed_integer (val
+ low_offset
,
3096 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3097 float_argreg
, phex (regval
, 4));
3098 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3100 /* Write the high word of the double to the odd register(s). */
3101 regval
= extract_signed_integer (val
+ 4 - low_offset
,
3104 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3105 float_argreg
, phex (regval
, 4));
3106 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3110 /* This is a floating point value that fits entirely
3111 in a single register. */
3112 /* On 32 bit ABI's the float_argreg is further adjusted
3113 above to ensure that it is even register aligned. */
3114 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
3116 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3117 float_argreg
, phex (regval
, len
));
3118 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3123 /* Copy the argument to general registers or the stack in
3124 register-sized pieces. Large arguments are split between
3125 registers and stack. */
3126 /* Note: structs whose size is not a multiple of regsize
3127 are treated specially: Irix cc passes
3128 them in registers where gcc sometimes puts them on the
3129 stack. For maximum compatibility, we will put them in
3131 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3133 /* Note: Floating-point values that didn't fit into an FP
3134 register are only written to memory. */
3137 /* Remember if the argument was written to the stack. */
3138 int stack_used_p
= 0;
3139 int partial_len
= (len
< regsize
? len
: regsize
);
3142 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3145 /* Write this portion of the argument to the stack. */
3146 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3148 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3150 /* Should shorter than int integer values be
3151 promoted to int before being stored? */
3152 int longword_offset
= 0;
3155 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3158 && (typecode
== TYPE_CODE_INT
3159 || typecode
== TYPE_CODE_PTR
3160 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3161 longword_offset
= regsize
- len
;
3162 else if ((typecode
== TYPE_CODE_STRUCT
3163 || typecode
== TYPE_CODE_UNION
)
3164 && TYPE_LENGTH (arg_type
) < regsize
)
3165 longword_offset
= regsize
- len
;
3170 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3171 paddress (gdbarch
, stack_offset
));
3172 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3173 paddress (gdbarch
, longword_offset
));
3176 addr
= sp
+ stack_offset
+ longword_offset
;
3181 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3182 paddress (gdbarch
, addr
));
3183 for (i
= 0; i
< partial_len
; i
++)
3185 fprintf_unfiltered (gdb_stdlog
, "%02x",
3189 write_memory (addr
, val
, partial_len
);
3192 /* Note!!! This is NOT an else clause. Odd sized
3193 structs may go thru BOTH paths. Floating point
3194 arguments will not. */
3195 /* Write this portion of the argument to a general
3196 purpose register. */
3197 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3198 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3201 extract_signed_integer (val
, partial_len
, byte_order
);
3204 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3206 phex (regval
, regsize
));
3207 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3214 /* Compute the offset into the stack at which we will
3215 copy the next parameter.
3217 In the new EABI (and the NABI32), the stack_offset
3218 only needs to be adjusted when it has been used. */
3221 stack_offset
+= align_up (partial_len
, regsize
);
3225 fprintf_unfiltered (gdb_stdlog
, "\n");
3228 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3230 /* Return adjusted stack pointer. */
3234 /* Determine the return value convention being used. */
3236 static enum return_value_convention
3237 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3238 struct type
*type
, struct regcache
*regcache
,
3239 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3241 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3242 int fp_return_type
= 0;
3243 int offset
, regnum
, xfer
;
3245 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3246 return RETURN_VALUE_STRUCT_CONVENTION
;
3248 /* Floating point type? */
3249 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3251 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3253 /* Structs with a single field of float type
3254 are returned in a floating point register. */
3255 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3256 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3257 && TYPE_NFIELDS (type
) == 1)
3259 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3261 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3268 /* A floating-point value belongs in the least significant part
3271 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3272 regnum
= mips_regnum (gdbarch
)->fp0
;
3276 /* An integer value goes in V0/V1. */
3278 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3279 regnum
= MIPS_V0_REGNUM
;
3282 offset
< TYPE_LENGTH (type
);
3283 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3285 xfer
= mips_abi_regsize (gdbarch
);
3286 if (offset
+ xfer
> TYPE_LENGTH (type
))
3287 xfer
= TYPE_LENGTH (type
) - offset
;
3288 mips_xfer_register (gdbarch
, regcache
,
3289 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3290 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3294 return RETURN_VALUE_REGISTER_CONVENTION
;
3298 /* N32/N64 ABI stuff. */
3300 /* Search for a naturally aligned double at OFFSET inside a struct
3301 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3305 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3310 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3313 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3316 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3319 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3322 struct type
*field_type
;
3324 /* We're only looking at normal fields. */
3325 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3326 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3329 /* If we have gone past the offset, there is no double to pass. */
3330 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3334 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3336 /* If this field is entirely before the requested offset, go
3337 on to the next one. */
3338 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3341 /* If this is our special aligned double, we can stop. */
3342 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3343 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3346 /* This field starts at or before the requested offset, and
3347 overlaps it. If it is a structure, recurse inwards. */
3348 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3355 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3356 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3357 int nargs
, struct value
**args
, CORE_ADDR sp
,
3358 int struct_return
, CORE_ADDR struct_addr
)
3364 int stack_offset
= 0;
3365 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3366 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3367 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3369 /* For shared libraries, "t9" needs to point at the function
3371 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3373 /* Set the return address register to point to the entry point of
3374 the program, where a breakpoint lies in wait. */
3375 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3377 /* First ensure that the stack and structure return address (if any)
3378 are properly aligned. The stack has to be at least 64-bit
3379 aligned even on 32-bit machines, because doubles must be 64-bit
3380 aligned. For n32 and n64, stack frames need to be 128-bit
3381 aligned, so we round to this widest known alignment. */
3383 sp
= align_down (sp
, 16);
3384 struct_addr
= align_down (struct_addr
, 16);
3386 /* Now make space on the stack for the args. */
3387 for (argnum
= 0; argnum
< nargs
; argnum
++)
3388 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3389 sp
-= align_up (len
, 16);
3392 fprintf_unfiltered (gdb_stdlog
,
3393 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3394 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3396 /* Initialize the integer and float register pointers. */
3397 argreg
= MIPS_A0_REGNUM
;
3398 float_argreg
= mips_fpa0_regnum (gdbarch
);
3400 /* The struct_return pointer occupies the first parameter-passing reg. */
3404 fprintf_unfiltered (gdb_stdlog
,
3405 "mips_n32n64_push_dummy_call: "
3406 "struct_return reg=%d %s\n",
3407 argreg
, paddress (gdbarch
, struct_addr
));
3408 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3411 /* Now load as many as possible of the first arguments into
3412 registers, and push the rest onto the stack. Loop thru args
3413 from first to last. */
3414 for (argnum
= 0; argnum
< nargs
; argnum
++)
3416 const gdb_byte
*val
;
3417 struct value
*arg
= args
[argnum
];
3418 struct type
*arg_type
= check_typedef (value_type (arg
));
3419 int len
= TYPE_LENGTH (arg_type
);
3420 enum type_code typecode
= TYPE_CODE (arg_type
);
3423 fprintf_unfiltered (gdb_stdlog
,
3424 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3425 argnum
+ 1, len
, (int) typecode
);
3427 val
= value_contents (arg
);
3429 /* A 128-bit long double value requires an even-odd pair of
3430 floating-point registers. */
3432 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3433 && (float_argreg
& 1))
3439 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3440 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3442 /* This is a floating point value that fits entirely
3443 in a single register or a pair of registers. */
3444 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3445 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3447 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3448 float_argreg
, phex (regval
, reglen
));
3449 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3452 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3453 argreg
, phex (regval
, reglen
));
3454 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3459 regval
= extract_unsigned_integer (val
+ reglen
,
3460 reglen
, byte_order
);
3462 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3463 float_argreg
, phex (regval
, reglen
));
3464 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3467 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3468 argreg
, phex (regval
, reglen
));
3469 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3476 /* Copy the argument to general registers or the stack in
3477 register-sized pieces. Large arguments are split between
3478 registers and stack. */
3479 /* For N32/N64, structs, unions, or other composite types are
3480 treated as a sequence of doublewords, and are passed in integer
3481 or floating point registers as though they were simple scalar
3482 parameters to the extent that they fit, with any excess on the
3483 stack packed according to the normal memory layout of the
3485 The caller does not reserve space for the register arguments;
3486 the callee is responsible for reserving it if required. */
3487 /* Note: Floating-point values that didn't fit into an FP
3488 register are only written to memory. */
3491 /* Remember if the argument was written to the stack. */
3492 int stack_used_p
= 0;
3493 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3496 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3499 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3500 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3502 /* Write this portion of the argument to the stack. */
3503 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3505 /* Should shorter than int integer values be
3506 promoted to int before being stored? */
3507 int longword_offset
= 0;
3510 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3512 if ((typecode
== TYPE_CODE_INT
3513 || typecode
== TYPE_CODE_PTR
)
3515 longword_offset
= MIPS64_REGSIZE
- len
;
3520 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3521 paddress (gdbarch
, stack_offset
));
3522 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3523 paddress (gdbarch
, longword_offset
));
3526 addr
= sp
+ stack_offset
+ longword_offset
;
3531 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3532 paddress (gdbarch
, addr
));
3533 for (i
= 0; i
< partial_len
; i
++)
3535 fprintf_unfiltered (gdb_stdlog
, "%02x",
3539 write_memory (addr
, val
, partial_len
);
3542 /* Note!!! This is NOT an else clause. Odd sized
3543 structs may go thru BOTH paths. */
3544 /* Write this portion of the argument to a general
3545 purpose register. */
3546 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3550 /* Sign extend pointers, 32-bit integers and signed
3551 16-bit and 8-bit integers; everything else is taken
3554 if ((partial_len
== 4
3555 && (typecode
== TYPE_CODE_PTR
3556 || typecode
== TYPE_CODE_INT
))
3558 && typecode
== TYPE_CODE_INT
3559 && !TYPE_UNSIGNED (arg_type
)))
3560 regval
= extract_signed_integer (val
, partial_len
,
3563 regval
= extract_unsigned_integer (val
, partial_len
,
3566 /* A non-floating-point argument being passed in a
3567 general register. If a struct or union, and if
3568 the remaining length is smaller than the register
3569 size, we have to adjust the register value on
3572 It does not seem to be necessary to do the
3573 same for integral types. */
3575 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3576 && partial_len
< MIPS64_REGSIZE
3577 && (typecode
== TYPE_CODE_STRUCT
3578 || typecode
== TYPE_CODE_UNION
))
3579 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3583 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3585 phex (regval
, MIPS64_REGSIZE
));
3586 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3588 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3589 TYPE_LENGTH (arg_type
) - len
))
3592 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3594 phex (regval
, MIPS64_REGSIZE
));
3595 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3606 /* Compute the offset into the stack at which we will
3607 copy the next parameter.
3609 In N32 (N64?), the stack_offset only needs to be
3610 adjusted when it has been used. */
3613 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3617 fprintf_unfiltered (gdb_stdlog
, "\n");
3620 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3622 /* Return adjusted stack pointer. */
3626 static enum return_value_convention
3627 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3628 struct type
*type
, struct regcache
*regcache
,
3629 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3631 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3633 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3635 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3636 if needed), as appropriate for the type. Composite results (struct,
3637 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3640 * A struct with only one or two floating point fields is returned in $f0
3641 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3644 * Any other composite results of at most 128 bits are returned in
3645 $2 (first 64 bits) and $3 (remainder, if necessary).
3647 * Larger composite results are handled by converting the function to a
3648 procedure with an implicit first parameter, which is a pointer to an area
3649 reserved by the caller to receive the result. [The o32-bit ABI requires
3650 that all composite results be handled by conversion to implicit first
3651 parameters. The MIPS/SGI Fortran implementation has always made a
3652 specific exception to return COMPLEX results in the floating point
3655 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3656 return RETURN_VALUE_STRUCT_CONVENTION
;
3657 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3658 && TYPE_LENGTH (type
) == 16
3659 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3661 /* A 128-bit floating-point value fills both $f0 and $f2. The
3662 two registers are used in the same as memory order, so the
3663 eight bytes with the lower memory address are in $f0. */
3665 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3666 mips_xfer_register (gdbarch
, regcache
,
3667 gdbarch_num_regs (gdbarch
)
3668 + mips_regnum (gdbarch
)->fp0
,
3669 8, gdbarch_byte_order (gdbarch
),
3670 readbuf
, writebuf
, 0);
3671 mips_xfer_register (gdbarch
, regcache
,
3672 gdbarch_num_regs (gdbarch
)
3673 + mips_regnum (gdbarch
)->fp0
+ 2,
3674 8, gdbarch_byte_order (gdbarch
),
3675 readbuf
? readbuf
+ 8 : readbuf
,
3676 writebuf
? writebuf
+ 8 : writebuf
, 0);
3677 return RETURN_VALUE_REGISTER_CONVENTION
;
3679 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3680 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3682 /* A single or double floating-point value that fits in FP0. */
3684 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3685 mips_xfer_register (gdbarch
, regcache
,
3686 gdbarch_num_regs (gdbarch
)
3687 + mips_regnum (gdbarch
)->fp0
,
3689 gdbarch_byte_order (gdbarch
),
3690 readbuf
, writebuf
, 0);
3691 return RETURN_VALUE_REGISTER_CONVENTION
;
3693 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3694 && TYPE_NFIELDS (type
) <= 2
3695 && TYPE_NFIELDS (type
) >= 1
3696 && ((TYPE_NFIELDS (type
) == 1
3697 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3699 || (TYPE_NFIELDS (type
) == 2
3700 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3702 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3703 == TYPE_CODE_FLT
))))
3705 /* A struct that contains one or two floats. Each value is part
3706 in the least significant part of their floating point
3707 register (or GPR, for soft float). */
3710 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3711 ? mips_regnum (gdbarch
)->fp0
3713 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3715 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3718 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3720 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3722 /* A 16-byte long double field goes in two consecutive
3724 mips_xfer_register (gdbarch
, regcache
,
3725 gdbarch_num_regs (gdbarch
) + regnum
,
3727 gdbarch_byte_order (gdbarch
),
3728 readbuf
, writebuf
, offset
);
3729 mips_xfer_register (gdbarch
, regcache
,
3730 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3732 gdbarch_byte_order (gdbarch
),
3733 readbuf
, writebuf
, offset
+ 8);
3736 mips_xfer_register (gdbarch
, regcache
,
3737 gdbarch_num_regs (gdbarch
) + regnum
,
3738 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3739 gdbarch_byte_order (gdbarch
),
3740 readbuf
, writebuf
, offset
);
3742 return RETURN_VALUE_REGISTER_CONVENTION
;
3744 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3745 || TYPE_CODE (type
) == TYPE_CODE_UNION
3746 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3748 /* A composite type. Extract the left justified value,
3749 regardless of the byte order. I.e. DO NOT USE
3753 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3754 offset
< TYPE_LENGTH (type
);
3755 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3757 int xfer
= register_size (gdbarch
, regnum
);
3758 if (offset
+ xfer
> TYPE_LENGTH (type
))
3759 xfer
= TYPE_LENGTH (type
) - offset
;
3761 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3762 offset
, xfer
, regnum
);
3763 mips_xfer_register (gdbarch
, regcache
,
3764 gdbarch_num_regs (gdbarch
) + regnum
,
3765 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3768 return RETURN_VALUE_REGISTER_CONVENTION
;
3772 /* A scalar extract each part but least-significant-byte
3776 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3777 offset
< TYPE_LENGTH (type
);
3778 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3780 int xfer
= register_size (gdbarch
, regnum
);
3781 if (offset
+ xfer
> TYPE_LENGTH (type
))
3782 xfer
= TYPE_LENGTH (type
) - offset
;
3784 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3785 offset
, xfer
, regnum
);
3786 mips_xfer_register (gdbarch
, regcache
,
3787 gdbarch_num_regs (gdbarch
) + regnum
,
3788 xfer
, gdbarch_byte_order (gdbarch
),
3789 readbuf
, writebuf
, offset
);
3791 return RETURN_VALUE_REGISTER_CONVENTION
;
3795 /* O32 ABI stuff. */
3798 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3799 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3800 int nargs
, struct value
**args
, CORE_ADDR sp
,
3801 int struct_return
, CORE_ADDR struct_addr
)
3807 int stack_offset
= 0;
3808 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3809 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3810 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3812 /* For shared libraries, "t9" needs to point at the function
3814 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3816 /* Set the return address register to point to the entry point of
3817 the program, where a breakpoint lies in wait. */
3818 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3820 /* First ensure that the stack and structure return address (if any)
3821 are properly aligned. The stack has to be at least 64-bit
3822 aligned even on 32-bit machines, because doubles must be 64-bit
3823 aligned. For n32 and n64, stack frames need to be 128-bit
3824 aligned, so we round to this widest known alignment. */
3826 sp
= align_down (sp
, 16);
3827 struct_addr
= align_down (struct_addr
, 16);
3829 /* Now make space on the stack for the args. */
3830 for (argnum
= 0; argnum
< nargs
; argnum
++)
3832 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3833 int arglen
= TYPE_LENGTH (arg_type
);
3835 /* Align to double-word if necessary. */
3836 if (mips_type_needs_double_align (arg_type
))
3837 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3838 /* Allocate space on the stack. */
3839 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3841 sp
-= align_up (len
, 16);
3844 fprintf_unfiltered (gdb_stdlog
,
3845 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3846 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3848 /* Initialize the integer and float register pointers. */
3849 argreg
= MIPS_A0_REGNUM
;
3850 float_argreg
= mips_fpa0_regnum (gdbarch
);
3852 /* The struct_return pointer occupies the first parameter-passing reg. */
3856 fprintf_unfiltered (gdb_stdlog
,
3857 "mips_o32_push_dummy_call: "
3858 "struct_return reg=%d %s\n",
3859 argreg
, paddress (gdbarch
, struct_addr
));
3860 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3861 stack_offset
+= MIPS32_REGSIZE
;
3864 /* Now load as many as possible of the first arguments into
3865 registers, and push the rest onto the stack. Loop thru args
3866 from first to last. */
3867 for (argnum
= 0; argnum
< nargs
; argnum
++)
3869 const gdb_byte
*val
;
3870 struct value
*arg
= args
[argnum
];
3871 struct type
*arg_type
= check_typedef (value_type (arg
));
3872 int len
= TYPE_LENGTH (arg_type
);
3873 enum type_code typecode
= TYPE_CODE (arg_type
);
3876 fprintf_unfiltered (gdb_stdlog
,
3877 "mips_o32_push_dummy_call: %d len=%d type=%d",
3878 argnum
+ 1, len
, (int) typecode
);
3880 val
= value_contents (arg
);
3882 /* 32-bit ABIs always start floating point arguments in an
3883 even-numbered floating point register. Round the FP register
3884 up before the check to see if there are any FP registers
3885 left. O32/O64 targets also pass the FP in the integer
3886 registers so also round up normal registers. */
3887 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3889 if ((float_argreg
& 1))
3893 /* Floating point arguments passed in registers have to be
3894 treated specially. On 32-bit architectures, doubles
3895 are passed in register pairs; the even register gets
3896 the low word, and the odd register gets the high word.
3897 On O32/O64, the first two floating point arguments are
3898 also copied to general registers, because MIPS16 functions
3899 don't use float registers for arguments. This duplication of
3900 arguments in general registers can't hurt non-MIPS16 functions
3901 because those registers are normally skipped. */
3903 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3904 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3906 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3908 int low_offset
= gdbarch_byte_order (gdbarch
)
3909 == BFD_ENDIAN_BIG
? 4 : 0;
3910 unsigned long regval
;
3912 /* Write the low word of the double to the even register(s). */
3913 regval
= extract_unsigned_integer (val
+ low_offset
,
3916 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3917 float_argreg
, phex (regval
, 4));
3918 regcache_cooked_write_unsigned (regcache
,
3919 float_argreg
++, regval
);
3921 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3922 argreg
, phex (regval
, 4));
3923 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3925 /* Write the high word of the double to the odd register(s). */
3926 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3929 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3930 float_argreg
, phex (regval
, 4));
3931 regcache_cooked_write_unsigned (regcache
,
3932 float_argreg
++, regval
);
3935 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3936 argreg
, phex (regval
, 4));
3937 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3941 /* This is a floating point value that fits entirely
3942 in a single register. */
3943 /* On 32 bit ABI's the float_argreg is further adjusted
3944 above to ensure that it is even register aligned. */
3945 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
3947 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3948 float_argreg
, phex (regval
, len
));
3949 regcache_cooked_write_unsigned (regcache
,
3950 float_argreg
++, regval
);
3951 /* Although two FP registers are reserved for each
3952 argument, only one corresponding integer register is
3955 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3956 argreg
, phex (regval
, len
));
3957 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3959 /* Reserve space for the FP register. */
3960 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3964 /* Copy the argument to general registers or the stack in
3965 register-sized pieces. Large arguments are split between
3966 registers and stack. */
3967 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3968 are treated specially: Irix cc passes
3969 them in registers where gcc sometimes puts them on the
3970 stack. For maximum compatibility, we will put them in
3972 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3973 && len
% MIPS32_REGSIZE
!= 0);
3974 /* Structures should be aligned to eight bytes (even arg registers)
3975 on MIPS_ABI_O32, if their first member has double precision. */
3976 if (mips_type_needs_double_align (arg_type
))
3981 stack_offset
+= MIPS32_REGSIZE
;
3986 /* Remember if the argument was written to the stack. */
3987 int stack_used_p
= 0;
3988 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3991 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3994 /* Write this portion of the argument to the stack. */
3995 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3996 || odd_sized_struct
)
3998 /* Should shorter than int integer values be
3999 promoted to int before being stored? */
4000 int longword_offset
= 0;
4006 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4007 paddress (gdbarch
, stack_offset
));
4008 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4009 paddress (gdbarch
, longword_offset
));
4012 addr
= sp
+ stack_offset
+ longword_offset
;
4017 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4018 paddress (gdbarch
, addr
));
4019 for (i
= 0; i
< partial_len
; i
++)
4021 fprintf_unfiltered (gdb_stdlog
, "%02x",
4025 write_memory (addr
, val
, partial_len
);
4028 /* Note!!! This is NOT an else clause. Odd sized
4029 structs may go thru BOTH paths. */
4030 /* Write this portion of the argument to a general
4031 purpose register. */
4032 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4034 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4036 /* Value may need to be sign extended, because
4037 mips_isa_regsize() != mips_abi_regsize(). */
4039 /* A non-floating-point argument being passed in a
4040 general register. If a struct or union, and if
4041 the remaining length is smaller than the register
4042 size, we have to adjust the register value on
4045 It does not seem to be necessary to do the
4046 same for integral types.
4048 Also don't do this adjustment on O64 binaries.
4050 cagney/2001-07-23: gdb/179: Also, GCC, when
4051 outputting LE O32 with sizeof (struct) <
4052 mips_abi_regsize(), generates a left shift
4053 as part of storing the argument in a register
4054 (the left shift isn't generated when
4055 sizeof (struct) >= mips_abi_regsize()). Since
4056 it is quite possible that this is GCC
4057 contradicting the LE/O32 ABI, GDB has not been
4058 adjusted to accommodate this. Either someone
4059 needs to demonstrate that the LE/O32 ABI
4060 specifies such a left shift OR this new ABI gets
4061 identified as such and GDB gets tweaked
4064 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4065 && partial_len
< MIPS32_REGSIZE
4066 && (typecode
== TYPE_CODE_STRUCT
4067 || typecode
== TYPE_CODE_UNION
))
4068 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
4072 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4074 phex (regval
, MIPS32_REGSIZE
));
4075 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4078 /* Prevent subsequent floating point arguments from
4079 being passed in floating point registers. */
4080 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4086 /* Compute the offset into the stack at which we will
4087 copy the next parameter.
4089 In older ABIs, the caller reserved space for
4090 registers that contained arguments. This was loosely
4091 refered to as their "home". Consequently, space is
4092 always allocated. */
4094 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
4098 fprintf_unfiltered (gdb_stdlog
, "\n");
4101 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4103 /* Return adjusted stack pointer. */
4107 static enum return_value_convention
4108 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4109 struct type
*type
, struct regcache
*regcache
,
4110 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4112 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4114 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4115 || TYPE_CODE (type
) == TYPE_CODE_UNION
4116 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4117 return RETURN_VALUE_STRUCT_CONVENTION
;
4118 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4119 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4121 /* A single-precision floating-point value. It fits in the
4122 least significant part of FP0. */
4124 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4125 mips_xfer_register (gdbarch
, regcache
,
4126 gdbarch_num_regs (gdbarch
)
4127 + mips_regnum (gdbarch
)->fp0
,
4129 gdbarch_byte_order (gdbarch
),
4130 readbuf
, writebuf
, 0);
4131 return RETURN_VALUE_REGISTER_CONVENTION
;
4133 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4134 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4136 /* A double-precision floating-point value. The most
4137 significant part goes in FP1, and the least significant in
4140 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4141 switch (gdbarch_byte_order (gdbarch
))
4143 case BFD_ENDIAN_LITTLE
:
4144 mips_xfer_register (gdbarch
, regcache
,
4145 gdbarch_num_regs (gdbarch
)
4146 + mips_regnum (gdbarch
)->fp0
+
4147 0, 4, gdbarch_byte_order (gdbarch
),
4148 readbuf
, writebuf
, 0);
4149 mips_xfer_register (gdbarch
, regcache
,
4150 gdbarch_num_regs (gdbarch
)
4151 + mips_regnum (gdbarch
)->fp0
+ 1,
4152 4, gdbarch_byte_order (gdbarch
),
4153 readbuf
, writebuf
, 4);
4155 case BFD_ENDIAN_BIG
:
4156 mips_xfer_register (gdbarch
, regcache
,
4157 gdbarch_num_regs (gdbarch
)
4158 + mips_regnum (gdbarch
)->fp0
+ 1,
4159 4, gdbarch_byte_order (gdbarch
),
4160 readbuf
, writebuf
, 0);
4161 mips_xfer_register (gdbarch
, regcache
,
4162 gdbarch_num_regs (gdbarch
)
4163 + mips_regnum (gdbarch
)->fp0
+ 0,
4164 4, gdbarch_byte_order (gdbarch
),
4165 readbuf
, writebuf
, 4);
4168 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4170 return RETURN_VALUE_REGISTER_CONVENTION
;
4173 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4174 && TYPE_NFIELDS (type
) <= 2
4175 && TYPE_NFIELDS (type
) >= 1
4176 && ((TYPE_NFIELDS (type
) == 1
4177 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4179 || (TYPE_NFIELDS (type
) == 2
4180 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4182 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4184 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4186 /* A struct that contains one or two floats. Each value is part
4187 in the least significant part of their floating point
4189 gdb_byte reg
[MAX_REGISTER_SIZE
];
4192 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4193 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4195 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4198 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4200 mips_xfer_register (gdbarch
, regcache
,
4201 gdbarch_num_regs (gdbarch
) + regnum
,
4202 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4203 gdbarch_byte_order (gdbarch
),
4204 readbuf
, writebuf
, offset
);
4206 return RETURN_VALUE_REGISTER_CONVENTION
;
4210 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4211 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4213 /* A structure or union. Extract the left justified value,
4214 regardless of the byte order. I.e. DO NOT USE
4218 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4219 offset
< TYPE_LENGTH (type
);
4220 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4222 int xfer
= register_size (gdbarch
, regnum
);
4223 if (offset
+ xfer
> TYPE_LENGTH (type
))
4224 xfer
= TYPE_LENGTH (type
) - offset
;
4226 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4227 offset
, xfer
, regnum
);
4228 mips_xfer_register (gdbarch
, regcache
,
4229 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4230 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4232 return RETURN_VALUE_REGISTER_CONVENTION
;
4237 /* A scalar extract each part but least-significant-byte
4238 justified. o32 thinks registers are 4 byte, regardless of
4242 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4243 offset
< TYPE_LENGTH (type
);
4244 offset
+= MIPS32_REGSIZE
, regnum
++)
4246 int xfer
= MIPS32_REGSIZE
;
4247 if (offset
+ xfer
> TYPE_LENGTH (type
))
4248 xfer
= TYPE_LENGTH (type
) - offset
;
4250 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4251 offset
, xfer
, regnum
);
4252 mips_xfer_register (gdbarch
, regcache
,
4253 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4254 gdbarch_byte_order (gdbarch
),
4255 readbuf
, writebuf
, offset
);
4257 return RETURN_VALUE_REGISTER_CONVENTION
;
4261 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4265 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4266 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4268 struct value
**args
, CORE_ADDR sp
,
4269 int struct_return
, CORE_ADDR struct_addr
)
4275 int stack_offset
= 0;
4276 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4277 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4278 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4280 /* For shared libraries, "t9" needs to point at the function
4282 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4284 /* Set the return address register to point to the entry point of
4285 the program, where a breakpoint lies in wait. */
4286 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4288 /* First ensure that the stack and structure return address (if any)
4289 are properly aligned. The stack has to be at least 64-bit
4290 aligned even on 32-bit machines, because doubles must be 64-bit
4291 aligned. For n32 and n64, stack frames need to be 128-bit
4292 aligned, so we round to this widest known alignment. */
4294 sp
= align_down (sp
, 16);
4295 struct_addr
= align_down (struct_addr
, 16);
4297 /* Now make space on the stack for the args. */
4298 for (argnum
= 0; argnum
< nargs
; argnum
++)
4300 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4301 int arglen
= TYPE_LENGTH (arg_type
);
4303 /* Allocate space on the stack. */
4304 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4306 sp
-= align_up (len
, 16);
4309 fprintf_unfiltered (gdb_stdlog
,
4310 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4311 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4313 /* Initialize the integer and float register pointers. */
4314 argreg
= MIPS_A0_REGNUM
;
4315 float_argreg
= mips_fpa0_regnum (gdbarch
);
4317 /* The struct_return pointer occupies the first parameter-passing reg. */
4321 fprintf_unfiltered (gdb_stdlog
,
4322 "mips_o64_push_dummy_call: "
4323 "struct_return reg=%d %s\n",
4324 argreg
, paddress (gdbarch
, struct_addr
));
4325 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4326 stack_offset
+= MIPS64_REGSIZE
;
4329 /* Now load as many as possible of the first arguments into
4330 registers, and push the rest onto the stack. Loop thru args
4331 from first to last. */
4332 for (argnum
= 0; argnum
< nargs
; argnum
++)
4334 const gdb_byte
*val
;
4335 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4336 struct value
*arg
= args
[argnum
];
4337 struct type
*arg_type
= check_typedef (value_type (arg
));
4338 int len
= TYPE_LENGTH (arg_type
);
4339 enum type_code typecode
= TYPE_CODE (arg_type
);
4342 fprintf_unfiltered (gdb_stdlog
,
4343 "mips_o64_push_dummy_call: %d len=%d type=%d",
4344 argnum
+ 1, len
, (int) typecode
);
4346 val
= value_contents (arg
);
4348 /* Function pointer arguments to mips16 code need to be made into
4350 if (typecode
== TYPE_CODE_PTR
4351 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4353 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4355 if (mips_pc_is_mips16 (addr
))
4357 store_signed_integer (valbuf
, len
, byte_order
,
4358 make_mips16_addr (addr
));
4363 /* Floating point arguments passed in registers have to be
4364 treated specially. On 32-bit architectures, doubles
4365 are passed in register pairs; the even register gets
4366 the low word, and the odd register gets the high word.
4367 On O32/O64, the first two floating point arguments are
4368 also copied to general registers, because MIPS16 functions
4369 don't use float registers for arguments. This duplication of
4370 arguments in general registers can't hurt non-MIPS16 functions
4371 because those registers are normally skipped. */
4373 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4374 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4376 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4378 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4379 float_argreg
, phex (regval
, len
));
4380 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4382 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4383 argreg
, phex (regval
, len
));
4384 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4386 /* Reserve space for the FP register. */
4387 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4391 /* Copy the argument to general registers or the stack in
4392 register-sized pieces. Large arguments are split between
4393 registers and stack. */
4394 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4395 are treated specially: Irix cc passes them in registers
4396 where gcc sometimes puts them on the stack. For maximum
4397 compatibility, we will put them in both places. */
4398 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4399 && len
% MIPS64_REGSIZE
!= 0);
4402 /* Remember if the argument was written to the stack. */
4403 int stack_used_p
= 0;
4404 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4407 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4410 /* Write this portion of the argument to the stack. */
4411 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4412 || odd_sized_struct
)
4414 /* Should shorter than int integer values be
4415 promoted to int before being stored? */
4416 int longword_offset
= 0;
4419 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4421 if ((typecode
== TYPE_CODE_INT
4422 || typecode
== TYPE_CODE_PTR
4423 || typecode
== TYPE_CODE_FLT
)
4425 longword_offset
= MIPS64_REGSIZE
- len
;
4430 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4431 paddress (gdbarch
, stack_offset
));
4432 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4433 paddress (gdbarch
, longword_offset
));
4436 addr
= sp
+ stack_offset
+ longword_offset
;
4441 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4442 paddress (gdbarch
, addr
));
4443 for (i
= 0; i
< partial_len
; i
++)
4445 fprintf_unfiltered (gdb_stdlog
, "%02x",
4449 write_memory (addr
, val
, partial_len
);
4452 /* Note!!! This is NOT an else clause. Odd sized
4453 structs may go thru BOTH paths. */
4454 /* Write this portion of the argument to a general
4455 purpose register. */
4456 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4458 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4460 /* Value may need to be sign extended, because
4461 mips_isa_regsize() != mips_abi_regsize(). */
4463 /* A non-floating-point argument being passed in a
4464 general register. If a struct or union, and if
4465 the remaining length is smaller than the register
4466 size, we have to adjust the register value on
4469 It does not seem to be necessary to do the
4470 same for integral types. */
4472 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4473 && partial_len
< MIPS64_REGSIZE
4474 && (typecode
== TYPE_CODE_STRUCT
4475 || typecode
== TYPE_CODE_UNION
))
4476 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4480 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4482 phex (regval
, MIPS64_REGSIZE
));
4483 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4486 /* Prevent subsequent floating point arguments from
4487 being passed in floating point registers. */
4488 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4494 /* Compute the offset into the stack at which we will
4495 copy the next parameter.
4497 In older ABIs, the caller reserved space for
4498 registers that contained arguments. This was loosely
4499 refered to as their "home". Consequently, space is
4500 always allocated. */
4502 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4506 fprintf_unfiltered (gdb_stdlog
, "\n");
4509 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4511 /* Return adjusted stack pointer. */
4515 static enum return_value_convention
4516 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4517 struct type
*type
, struct regcache
*regcache
,
4518 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4520 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4522 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4523 || TYPE_CODE (type
) == TYPE_CODE_UNION
4524 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4525 return RETURN_VALUE_STRUCT_CONVENTION
;
4526 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4528 /* A floating-point value. It fits in the least significant
4531 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4532 mips_xfer_register (gdbarch
, regcache
,
4533 gdbarch_num_regs (gdbarch
)
4534 + mips_regnum (gdbarch
)->fp0
,
4536 gdbarch_byte_order (gdbarch
),
4537 readbuf
, writebuf
, 0);
4538 return RETURN_VALUE_REGISTER_CONVENTION
;
4542 /* A scalar extract each part but least-significant-byte
4546 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4547 offset
< TYPE_LENGTH (type
);
4548 offset
+= MIPS64_REGSIZE
, regnum
++)
4550 int xfer
= MIPS64_REGSIZE
;
4551 if (offset
+ xfer
> TYPE_LENGTH (type
))
4552 xfer
= TYPE_LENGTH (type
) - offset
;
4554 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4555 offset
, xfer
, regnum
);
4556 mips_xfer_register (gdbarch
, regcache
,
4557 gdbarch_num_regs (gdbarch
) + regnum
,
4558 xfer
, gdbarch_byte_order (gdbarch
),
4559 readbuf
, writebuf
, offset
);
4561 return RETURN_VALUE_REGISTER_CONVENTION
;
4565 /* Floating point register management.
4567 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4568 64bit operations, these early MIPS cpus treat fp register pairs
4569 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4570 registers and offer a compatibility mode that emulates the MIPS2 fp
4571 model. When operating in MIPS2 fp compat mode, later cpu's split
4572 double precision floats into two 32-bit chunks and store them in
4573 consecutive fp regs. To display 64-bit floats stored in this
4574 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4575 Throw in user-configurable endianness and you have a real mess.
4577 The way this works is:
4578 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4579 double-precision value will be split across two logical registers.
4580 The lower-numbered logical register will hold the low-order bits,
4581 regardless of the processor's endianness.
4582 - If we are on a 64-bit processor, and we are looking for a
4583 single-precision value, it will be in the low ordered bits
4584 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4585 save slot in memory.
4586 - If we are in 64-bit mode, everything is straightforward.
4588 Note that this code only deals with "live" registers at the top of the
4589 stack. We will attempt to deal with saved registers later, when
4590 the raw/cooked register interface is in place. (We need a general
4591 interface that can deal with dynamic saved register sizes -- fp
4592 regs could be 32 bits wide in one frame and 64 on the frame above
4595 /* Copy a 32-bit single-precision value from the current frame
4596 into rare_buffer. */
4599 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4600 gdb_byte
*rare_buffer
)
4602 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4603 int raw_size
= register_size (gdbarch
, regno
);
4604 gdb_byte
*raw_buffer
= alloca (raw_size
);
4606 if (!frame_register_read (frame
, regno
, raw_buffer
))
4607 error (_("can't read register %d (%s)"),
4608 regno
, gdbarch_register_name (gdbarch
, regno
));
4611 /* We have a 64-bit value for this register. Find the low-order
4615 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4620 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4624 memcpy (rare_buffer
, raw_buffer
, 4);
4628 /* Copy a 64-bit double-precision value from the current frame into
4629 rare_buffer. This may include getting half of it from the next
4633 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4634 gdb_byte
*rare_buffer
)
4636 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4637 int raw_size
= register_size (gdbarch
, regno
);
4639 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4641 /* We have a 64-bit value for this register, and we should use
4643 if (!frame_register_read (frame
, regno
, rare_buffer
))
4644 error (_("can't read register %d (%s)"),
4645 regno
, gdbarch_register_name (gdbarch
, regno
));
4649 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4651 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4652 internal_error (__FILE__
, __LINE__
,
4653 _("mips_read_fp_register_double: bad access to "
4654 "odd-numbered FP register"));
4656 /* mips_read_fp_register_single will find the correct 32 bits from
4658 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4660 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4661 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4665 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4666 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4672 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4674 { /* Do values for FP (float) regs. */
4675 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4676 gdb_byte
*raw_buffer
;
4677 double doub
, flt1
; /* Doubles extracted from raw hex data. */
4680 raw_buffer
= alloca (2 * register_size (gdbarch
,
4681 mips_regnum (gdbarch
)->fp0
));
4683 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4684 fprintf_filtered (file
, "%*s",
4685 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4688 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4690 struct value_print_options opts
;
4692 /* 4-byte registers: Print hex and floating. Also print even
4693 numbered registers as doubles. */
4694 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4695 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4698 get_formatted_print_options (&opts
, 'x');
4699 print_scalar_formatted (raw_buffer
,
4700 builtin_type (gdbarch
)->builtin_uint32
,
4703 fprintf_filtered (file
, " flt: ");
4705 fprintf_filtered (file
, " <invalid float> ");
4707 fprintf_filtered (file
, "%-17.9g", flt1
);
4709 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4711 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4712 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4715 fprintf_filtered (file
, " dbl: ");
4717 fprintf_filtered (file
, "<invalid double>");
4719 fprintf_filtered (file
, "%-24.17g", doub
);
4724 struct value_print_options opts
;
4726 /* Eight byte registers: print each one as hex, float and double. */
4727 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4728 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4731 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4732 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4735 get_formatted_print_options (&opts
, 'x');
4736 print_scalar_formatted (raw_buffer
,
4737 builtin_type (gdbarch
)->builtin_uint64
,
4740 fprintf_filtered (file
, " flt: ");
4742 fprintf_filtered (file
, "<invalid float>");
4744 fprintf_filtered (file
, "%-17.9g", flt1
);
4746 fprintf_filtered (file
, " dbl: ");
4748 fprintf_filtered (file
, "<invalid double>");
4750 fprintf_filtered (file
, "%-24.17g", doub
);
4755 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4758 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4760 struct value_print_options opts
;
4763 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4765 mips_print_fp_register (file
, frame
, regnum
);
4769 val
= get_frame_register_value (frame
, regnum
);
4770 if (value_optimized_out (val
))
4772 fprintf_filtered (file
, "%s: [Invalid]",
4773 gdbarch_register_name (gdbarch
, regnum
));
4777 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4779 /* The problem with printing numeric register names (r26, etc.) is that
4780 the user can't use them on input. Probably the best solution is to
4781 fix it so that either the numeric or the funky (a2, etc.) names
4782 are accepted on input. */
4783 if (regnum
< MIPS_NUMREGS
)
4784 fprintf_filtered (file
, "(r%d): ", regnum
);
4786 fprintf_filtered (file
, ": ");
4788 get_formatted_print_options (&opts
, 'x');
4789 val_print_scalar_formatted (value_type (val
),
4790 value_contents_for_printing (val
),
4791 value_embedded_offset (val
),
4796 /* Replacement for generic do_registers_info.
4797 Print regs in pretty columns. */
4800 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4803 fprintf_filtered (file
, " ");
4804 mips_print_fp_register (file
, frame
, regnum
);
4805 fprintf_filtered (file
, "\n");
4810 /* Print a row's worth of GP (int) registers, with name labels above. */
4813 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4816 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4817 /* Do values for GP (int) regs. */
4818 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4819 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
4824 /* For GP registers, we print a separate row of names above the vals. */
4825 for (col
= 0, regnum
= start_regnum
;
4826 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4827 + gdbarch_num_pseudo_regs (gdbarch
);
4830 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4831 continue; /* unused register */
4832 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4834 break; /* End the row: reached FP register. */
4835 /* Large registers are handled separately. */
4836 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4839 break; /* End the row before this register. */
4841 /* Print this register on a row by itself. */
4842 mips_print_register (file
, frame
, regnum
);
4843 fprintf_filtered (file
, "\n");
4847 fprintf_filtered (file
, " ");
4848 fprintf_filtered (file
,
4849 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4850 gdbarch_register_name (gdbarch
, regnum
));
4857 /* Print the R0 to R31 names. */
4858 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4859 fprintf_filtered (file
, "\n R%-4d",
4860 start_regnum
% gdbarch_num_regs (gdbarch
));
4862 fprintf_filtered (file
, "\n ");
4864 /* Now print the values in hex, 4 or 8 to the row. */
4865 for (col
= 0, regnum
= start_regnum
;
4866 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4867 + gdbarch_num_pseudo_regs (gdbarch
);
4870 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4871 continue; /* unused register */
4872 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4874 break; /* End row: reached FP register. */
4875 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4876 break; /* End row: large register. */
4878 /* OK: get the data in raw format. */
4879 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4880 error (_("can't read register %d (%s)"),
4881 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4882 /* pad small registers */
4884 byte
< (mips_abi_regsize (gdbarch
)
4885 - register_size (gdbarch
, regnum
)); byte
++)
4886 printf_filtered (" ");
4887 /* Now print the register value in hex, endian order. */
4888 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4890 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4891 byte
< register_size (gdbarch
, regnum
); byte
++)
4892 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4894 for (byte
= register_size (gdbarch
, regnum
) - 1;
4896 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4897 fprintf_filtered (file
, " ");
4900 if (col
> 0) /* ie. if we actually printed anything... */
4901 fprintf_filtered (file
, "\n");
4906 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
4909 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4910 struct frame_info
*frame
, int regnum
, int all
)
4912 if (regnum
!= -1) /* Do one specified register. */
4914 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4915 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4916 error (_("Not a valid register for the current processor type"));
4918 mips_print_register (file
, frame
, regnum
);
4919 fprintf_filtered (file
, "\n");
4922 /* Do all (or most) registers. */
4924 regnum
= gdbarch_num_regs (gdbarch
);
4925 while (regnum
< gdbarch_num_regs (gdbarch
)
4926 + gdbarch_num_pseudo_regs (gdbarch
))
4928 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4931 if (all
) /* True for "INFO ALL-REGISTERS" command. */
4932 regnum
= print_fp_register_row (file
, frame
, regnum
);
4934 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
4937 regnum
= print_gp_register_row (file
, frame
, regnum
);
4942 /* Is this a branch with a delay slot? */
4945 is_delayed (unsigned long insn
)
4948 for (i
= 0; i
< NUMOPCODES
; ++i
)
4949 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4950 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4952 return (i
< NUMOPCODES
4953 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4954 | INSN_COND_BRANCH_DELAY
4955 | INSN_COND_BRANCH_LIKELY
)));
4959 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4960 struct frame_info
*frame
)
4962 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4963 CORE_ADDR pc
= get_frame_pc (frame
);
4964 gdb_byte buf
[MIPS_INSN32_SIZE
];
4966 /* There is no branch delay slot on MIPS16. */
4967 if (mips_pc_is_mips16 (pc
))
4970 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
4973 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4974 /* If error reading memory, guess that it is not a delayed
4977 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
4980 /* To skip prologues, I use this predicate. Returns either PC itself
4981 if the code at PC does not look like a function prologue; otherwise
4982 returns an address that (if we're lucky) follows the prologue. If
4983 LENIENT, then we must skip everything which is involved in setting
4984 up the frame (it's OK to skip more, just so long as we don't skip
4985 anything which might clobber the registers which are being saved.
4986 We must skip more in the case where part of the prologue is in the
4987 delay slot of a non-prologue instruction). */
4990 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4993 CORE_ADDR func_addr
;
4995 /* See if we can determine the end of the prologue via the symbol table.
4996 If so, then return either PC, or the PC after the prologue, whichever
4998 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
5000 CORE_ADDR post_prologue_pc
5001 = skip_prologue_using_sal (gdbarch
, func_addr
);
5002 if (post_prologue_pc
!= 0)
5003 return max (pc
, post_prologue_pc
);
5006 /* Can't determine prologue from the symbol table, need to examine
5009 /* Find an upper limit on the function prologue using the debug
5010 information. If the debug information could not be used to provide
5011 that bound, then use an arbitrary large number as the upper bound. */
5012 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
5014 limit_pc
= pc
+ 100; /* Magic. */
5016 if (mips_pc_is_mips16 (pc
))
5017 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
5019 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
5022 /* Check whether the PC is in a function epilogue (32-bit version).
5023 This is a helper function for mips_in_function_epilogue_p. */
5025 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5027 CORE_ADDR func_addr
= 0, func_end
= 0;
5029 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5031 /* The MIPS epilogue is max. 12 bytes long. */
5032 CORE_ADDR addr
= func_end
- 12;
5034 if (addr
< func_addr
+ 4)
5035 addr
= func_addr
+ 4;
5039 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
5041 unsigned long high_word
;
5044 inst
= mips_fetch_instruction (gdbarch
, pc
);
5045 high_word
= (inst
>> 16) & 0xffff;
5047 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
5048 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
5049 && inst
!= 0x03e00008 /* jr $ra */
5050 && inst
!= 0x00000000) /* nop */
5060 /* Check whether the PC is in a function epilogue (16-bit version).
5061 This is a helper function for mips_in_function_epilogue_p. */
5063 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5065 CORE_ADDR func_addr
= 0, func_end
= 0;
5067 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5069 /* The MIPS epilogue is max. 12 bytes long. */
5070 CORE_ADDR addr
= func_end
- 12;
5072 if (addr
< func_addr
+ 4)
5073 addr
= func_addr
+ 4;
5077 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
5079 unsigned short inst
;
5081 inst
= mips_fetch_instruction (gdbarch
, pc
);
5083 if ((inst
& 0xf800) == 0xf000) /* extend */
5086 if (inst
!= 0x6300 /* addiu $sp,offset */
5087 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
5088 && inst
!= 0xe820 /* jr $ra */
5089 && inst
!= 0xe8a0 /* jrc $ra */
5090 && inst
!= 0x6500) /* nop */
5100 /* The epilogue is defined here as the area at the end of a function,
5101 after an instruction which destroys the function's stack frame. */
5103 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5105 if (mips_pc_is_mips16 (pc
))
5106 return mips16_in_function_epilogue_p (gdbarch
, pc
);
5108 return mips32_in_function_epilogue_p (gdbarch
, pc
);
5111 /* Root of all "set mips "/"show mips " commands. This will eventually be
5112 used for all MIPS-specific commands. */
5115 show_mips_command (char *args
, int from_tty
)
5117 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5121 set_mips_command (char *args
, int from_tty
)
5124 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5125 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5128 /* Commands to show/set the MIPS FPU type. */
5131 show_mipsfpu_command (char *args
, int from_tty
)
5135 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5138 ("The MIPS floating-point coprocessor is unknown "
5139 "because the current architecture is not MIPS.\n");
5143 switch (MIPS_FPU_TYPE (target_gdbarch
))
5145 case MIPS_FPU_SINGLE
:
5146 fpu
= "single-precision";
5148 case MIPS_FPU_DOUBLE
:
5149 fpu
= "double-precision";
5152 fpu
= "absent (none)";
5155 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5157 if (mips_fpu_type_auto
)
5158 printf_unfiltered ("The MIPS floating-point coprocessor "
5159 "is set automatically (currently %s)\n",
5163 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5168 set_mipsfpu_command (char *args
, int from_tty
)
5170 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
5171 "\"single\",\"none\" or \"auto\".\n");
5172 show_mipsfpu_command (args
, from_tty
);
5176 set_mipsfpu_single_command (char *args
, int from_tty
)
5178 struct gdbarch_info info
;
5179 gdbarch_info_init (&info
);
5180 mips_fpu_type
= MIPS_FPU_SINGLE
;
5181 mips_fpu_type_auto
= 0;
5182 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5183 instead of relying on globals. Doing that would let generic code
5184 handle the search for this specific architecture. */
5185 if (!gdbarch_update_p (info
))
5186 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5190 set_mipsfpu_double_command (char *args
, int from_tty
)
5192 struct gdbarch_info info
;
5193 gdbarch_info_init (&info
);
5194 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5195 mips_fpu_type_auto
= 0;
5196 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5197 instead of relying on globals. Doing that would let generic code
5198 handle the search for this specific architecture. */
5199 if (!gdbarch_update_p (info
))
5200 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5204 set_mipsfpu_none_command (char *args
, int from_tty
)
5206 struct gdbarch_info info
;
5207 gdbarch_info_init (&info
);
5208 mips_fpu_type
= MIPS_FPU_NONE
;
5209 mips_fpu_type_auto
= 0;
5210 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5211 instead of relying on globals. Doing that would let generic code
5212 handle the search for this specific architecture. */
5213 if (!gdbarch_update_p (info
))
5214 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5218 set_mipsfpu_auto_command (char *args
, int from_tty
)
5220 mips_fpu_type_auto
= 1;
5223 /* Attempt to identify the particular processor model by reading the
5224 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5225 the relevant processor still exists (it dates back to '94) and
5226 secondly this is not the way to do this. The processor type should
5227 be set by forcing an architecture change. */
5230 deprecated_mips_set_processor_regs_hack (void)
5232 struct regcache
*regcache
= get_current_regcache ();
5233 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5234 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5237 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5238 if ((prid
& ~0xf) == 0x700)
5239 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5242 /* Just like reinit_frame_cache, but with the right arguments to be
5243 callable as an sfunc. */
5246 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5247 struct cmd_list_element
*c
)
5249 reinit_frame_cache ();
5253 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5255 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5256 disassembler needs to be able to locally determine the ISA, and
5257 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5259 if (mips_pc_is_mips16 (memaddr
))
5260 info
->mach
= bfd_mach_mips16
;
5262 /* Round down the instruction address to the appropriate boundary. */
5263 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5265 /* Set the disassembler options. */
5266 if (!info
->disassembler_options
)
5267 /* This string is not recognized explicitly by the disassembler,
5268 but it tells the disassembler to not try to guess the ABI from
5269 the bfd elf headers, such that, if the user overrides the ABI
5270 of a program linked as NewABI, the disassembly will follow the
5271 register naming conventions specified by the user. */
5272 info
->disassembler_options
= "gpr-names=32";
5274 /* Call the appropriate disassembler based on the target endian-ness. */
5275 if (info
->endian
== BFD_ENDIAN_BIG
)
5276 return print_insn_big_mips (memaddr
, info
);
5278 return print_insn_little_mips (memaddr
, info
);
5282 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5284 /* Set up the disassembler info, so that we get the right
5285 register names from libopcodes. */
5286 info
->disassembler_options
= "gpr-names=n32";
5287 info
->flavour
= bfd_target_elf_flavour
;
5289 return gdb_print_insn_mips (memaddr
, info
);
5293 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5295 /* Set up the disassembler info, so that we get the right
5296 register names from libopcodes. */
5297 info
->disassembler_options
= "gpr-names=64";
5298 info
->flavour
= bfd_target_elf_flavour
;
5300 return gdb_print_insn_mips (memaddr
, info
);
5303 /* This function implements gdbarch_breakpoint_from_pc. It uses the
5304 program counter value to determine whether a 16- or 32-bit breakpoint
5305 should be used. It returns a pointer to a string of bytes that encode a
5306 breakpoint instruction, stores the length of the string to *lenptr, and
5307 adjusts pc (if necessary) to point to the actual memory location where
5308 the breakpoint should be inserted. */
5310 static const gdb_byte
*
5311 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
5312 CORE_ADDR
*pcptr
, int *lenptr
)
5314 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5316 if (mips_pc_is_mips16 (*pcptr
))
5318 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5319 *pcptr
= unmake_mips16_addr (*pcptr
);
5320 *lenptr
= sizeof (mips16_big_breakpoint
);
5321 return mips16_big_breakpoint
;
5325 /* The IDT board uses an unusual breakpoint value, and
5326 sometimes gets confused when it sees the usual MIPS
5327 breakpoint instruction. */
5328 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5329 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5330 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5331 /* Likewise, IRIX appears to expect a different breakpoint,
5332 although this is not apparent until you try to use pthreads. */
5333 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5335 *lenptr
= sizeof (big_breakpoint
);
5337 if (strcmp (target_shortname
, "mips") == 0)
5338 return idt_big_breakpoint
;
5339 else if (strcmp (target_shortname
, "ddb") == 0
5340 || strcmp (target_shortname
, "pmon") == 0
5341 || strcmp (target_shortname
, "lsi") == 0)
5342 return pmon_big_breakpoint
;
5343 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5344 return irix_big_breakpoint
;
5346 return big_breakpoint
;
5351 if (mips_pc_is_mips16 (*pcptr
))
5353 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5354 *pcptr
= unmake_mips16_addr (*pcptr
);
5355 *lenptr
= sizeof (mips16_little_breakpoint
);
5356 return mips16_little_breakpoint
;
5360 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5361 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5362 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5364 *lenptr
= sizeof (little_breakpoint
);
5366 if (strcmp (target_shortname
, "mips") == 0)
5367 return idt_little_breakpoint
;
5368 else if (strcmp (target_shortname
, "ddb") == 0
5369 || strcmp (target_shortname
, "pmon") == 0
5370 || strcmp (target_shortname
, "lsi") == 0)
5371 return pmon_little_breakpoint
;
5373 return little_breakpoint
;
5378 /* Return non-zero if the ADDR instruction has a branch delay slot
5379 (i.e. it is a jump or branch instruction). This function is based
5380 on mips32_next_pc. */
5383 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
5385 gdb_byte buf
[MIPS_INSN32_SIZE
];
5392 status
= target_read_memory (addr
, buf
, MIPS_INSN32_SIZE
);
5396 inst
= mips_fetch_instruction (gdbarch
, addr
);
5397 op
= itype_op (inst
);
5398 if ((inst
& 0xe0000000) != 0)
5400 rs
= itype_rs (inst
);
5401 rt
= itype_rt (inst
);
5402 return (op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
5403 || op
== 29 /* JALX: bits 011101 */
5406 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
5407 || (rs
== 9 && (rt
& 0x2) == 0)
5408 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
5409 || (rs
== 10 && (rt
& 0x2) == 0))));
5410 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
5413 switch (op
& 0x07) /* extract bits 28,27,26 */
5415 case 0: /* SPECIAL */
5416 op
= rtype_funct (inst
);
5417 return (op
== 8 /* JR */
5418 || op
== 9); /* JALR */
5419 break; /* end SPECIAL */
5420 case 1: /* REGIMM */
5421 rs
= itype_rs (inst
);
5422 rt
= itype_rt (inst
); /* branch condition */
5423 return ((rt
& 0xc) == 0
5424 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
5425 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
5426 || ((rt
& 0x1e) == 0x1c && rs
== 0));
5427 /* BPOSGE32, BPOSGE64: bits 1110x */
5428 break; /* end REGIMM */
5429 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
5435 /* Return non-zero if the ADDR instruction, which must be a 32-bit
5436 instruction if MUSTBE32 is set or can be any instruction otherwise,
5437 has a branch delay slot (i.e. it is a non-compact jump instruction). */
5440 mips16_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
5443 gdb_byte buf
[MIPS_INSN16_SIZE
];
5444 unsigned short inst
;
5447 status
= target_read_memory (addr
, buf
, MIPS_INSN16_SIZE
);
5451 inst
= mips_fetch_instruction (gdbarch
, addr
);
5453 return (inst
& 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
5454 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
5457 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
5458 This assumes KSSEG exists. */
5461 mips_segment_boundary (CORE_ADDR bpaddr
)
5463 CORE_ADDR mask
= CORE_ADDR_MAX
;
5466 if (sizeof (CORE_ADDR
) == 8)
5467 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
5468 a compiler warning produced where CORE_ADDR is a 32-bit type even
5469 though in that case this is dead code). */
5470 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
5473 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
5474 segsize
= 29; /* 32-bit compatibility segment */
5476 segsize
= 62; /* xkseg */
5478 case 2: /* xkphys */
5481 default: /* xksseg (1), xkuseg/kuseg (0) */
5485 else if (bpaddr
& 0x80000000) /* kernel segment */
5488 segsize
= 31; /* user segment */
5490 return bpaddr
& mask
;
5493 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
5494 it backwards if necessary. Return the address of the new location. */
5497 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5499 CORE_ADDR prev_addr
, next_addr
;
5501 CORE_ADDR func_addr
;
5503 /* If a breakpoint is set on the instruction in a branch delay slot,
5504 GDB gets confused. When the breakpoint is hit, the PC isn't on
5505 the instruction in the branch delay slot, the PC will point to
5506 the branch instruction. Since the PC doesn't match any known
5507 breakpoints, GDB reports a trap exception.
5509 There are two possible fixes for this problem.
5511 1) When the breakpoint gets hit, see if the BD bit is set in the
5512 Cause register (which indicates the last exception occurred in a
5513 branch delay slot). If the BD bit is set, fix the PC to point to
5514 the instruction in the branch delay slot.
5516 2) When the user sets the breakpoint, don't allow him to set the
5517 breakpoint on the instruction in the branch delay slot. Instead
5518 move the breakpoint to the branch instruction (which will have
5521 The problem with the first solution is that if the user then
5522 single-steps the processor, the branch instruction will get
5523 skipped (since GDB thinks the PC is on the instruction in the
5526 So, we'll use the second solution. To do this we need to know if
5527 the instruction we're trying to set the breakpoint on is in the
5528 branch delay slot. */
5530 boundary
= mips_segment_boundary (bpaddr
);
5532 /* Make sure we don't scan back before the beginning of the current
5533 function, since we may fetch constant data or insns that look like
5534 a jump. Of course we might do that anyway if the compiler has
5535 moved constants inline. :-( */
5536 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
5537 && func_addr
> boundary
&& func_addr
<= bpaddr
)
5538 boundary
= func_addr
;
5540 if (!mips_pc_is_mips16 (bpaddr
))
5542 if (bpaddr
== boundary
)
5545 /* If the previous instruction has a branch delay slot, we have
5546 to move the breakpoint to the branch instruction. */
5547 prev_addr
= bpaddr
- 4;
5548 if (mips32_instruction_has_delay_slot (gdbarch
, prev_addr
))
5553 struct minimal_symbol
*sym
;
5554 CORE_ADDR addr
, jmpaddr
;
5557 boundary
= unmake_mips16_addr (boundary
);
5559 /* The only MIPS16 instructions with delay slots are JAL, JALX,
5560 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
5561 so try for that first, then try the 2 byte JALR/JR.
5562 FIXME: We have to assume that bpaddr is not the second half
5563 of an extended instruction. */
5567 for (i
= 1; i
< 4; i
++)
5569 if (unmake_mips16_addr (addr
) == boundary
)
5572 if (i
== 1 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 0))
5573 /* Looks like a JR/JALR at [target-1], but it could be
5574 the second word of a previous JAL/JALX, so record it
5575 and check back one more. */
5578 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 1))
5581 /* Looks like a JAL/JALX at [target-2], but it could also
5582 be the second word of a previous JAL/JALX, record it,
5583 and check back one more. */
5586 /* Looks like a JAL/JALX at [target-3], so any previously
5587 recorded JAL/JALX or JR/JALR must be wrong, because:
5590 -2: JAL-ext (can't be JAL/JALX)
5591 -1: bdslot (can't be JR/JALR)
5594 Of course it could be another JAL-ext which looks
5595 like a JAL, but in that case we'd have broken out
5596 of this loop at [target-2]:
5600 -2: bdslot (can't be jmp)
5607 /* Not a jump instruction: if we're at [target-1] this
5608 could be the second word of a JAL/JALX, so continue;
5609 otherwise we're done. */
5622 /* If PC is in a mips16 call or return stub, return the address of the target
5623 PC, which is either the callee or the caller. There are several
5624 cases which must be handled:
5626 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5627 target PC is in $31 ($ra).
5628 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5629 and the target PC is in $2.
5630 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5631 before the jal instruction, this is effectively a call stub
5632 and the target PC is in $2. Otherwise this is effectively
5633 a return stub and the target PC is in $18.
5635 See the source code for the stubs in gcc/config/mips/mips16.S for
5639 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5641 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5643 CORE_ADDR start_addr
;
5645 /* Find the starting address and name of the function containing the PC. */
5646 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5649 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5650 target PC is in $31 ($ra). */
5651 if (strcmp (name
, "__mips16_ret_sf") == 0
5652 || strcmp (name
, "__mips16_ret_df") == 0)
5653 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5655 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5657 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5658 and the target PC is in $2. */
5659 if (name
[19] >= '0' && name
[19] <= '9')
5660 return get_frame_register_signed (frame
, 2);
5662 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5663 before the jal instruction, this is effectively a call stub
5664 and the target PC is in $2. Otherwise this is effectively
5665 a return stub and the target PC is in $18. */
5666 else if (name
[19] == 's' || name
[19] == 'd')
5668 if (pc
== start_addr
)
5670 /* Check if the target of the stub is a compiler-generated
5671 stub. Such a stub for a function bar might have a name
5672 like __fn_stub_bar, and might look like this:
5677 la $1,bar (becomes a lui/addiu pair)
5679 So scan down to the lui/addi and extract the target
5680 address from those two instructions. */
5682 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5685 /* See if the name of the target function is __fn_stub_*. */
5686 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5689 if (strncmp (name
, "__fn_stub_", 10) != 0
5690 && strcmp (name
, "etext") != 0
5691 && strcmp (name
, "_etext") != 0)
5694 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5695 The limit on the search is arbitrarily set to 20
5696 instructions. FIXME. */
5697 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5699 ULONGEST inst
= mips_fetch_instruction (gdbarch
, target_pc
);
5700 CORE_ADDR addr
= inst
;
5702 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5703 pc
= (((addr
& 0xffff) ^ 0x8000) - 0x8000) << 16;
5705 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5706 return pc
+ ((addr
& 0xffff) ^ 0x8000) - 0x8000;
5710 /* Couldn't find the lui/addui pair, so return stub address. */
5714 /* This is the 'return' part of a call stub. The return
5715 address is in $r18. */
5716 return get_frame_register_signed (frame
, 18);
5719 return 0; /* not a stub */
5722 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5723 PC of the stub target. The stub just loads $t9 and jumps to it,
5724 so that $t9 has the correct value at function entry. */
5727 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5729 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5730 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5731 struct minimal_symbol
*msym
;
5733 gdb_byte stub_code
[16];
5734 int32_t stub_words
[4];
5736 /* The stub for foo is named ".pic.foo", and is either two
5737 instructions inserted before foo or a three instruction sequence
5738 which jumps to foo. */
5739 msym
= lookup_minimal_symbol_by_pc (pc
);
5741 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5742 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5743 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5746 /* A two-instruction header. */
5747 if (MSYMBOL_SIZE (msym
) == 8)
5750 /* A three-instruction (plus delay slot) trampoline. */
5751 if (MSYMBOL_SIZE (msym
) == 16)
5753 if (target_read_memory (pc
, stub_code
, 16) != 0)
5755 for (i
= 0; i
< 4; i
++)
5756 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
5759 /* A stub contains these instructions:
5762 addiu t9, t9, %lo(target)
5765 This works even for N64, since stubs are only generated with
5767 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5768 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5769 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5770 && stub_words
[3] == 0x00000000)
5771 return ((((stub_words
[0] & 0x0000ffff) << 16)
5772 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
5775 /* Not a recognized stub. */
5780 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5782 CORE_ADDR target_pc
;
5784 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5788 target_pc
= find_solib_trampoline_target (frame
, pc
);
5792 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5799 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5800 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5803 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5806 if (num
>= 0 && num
< 32)
5808 else if (num
>= 38 && num
< 70)
5809 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5811 regnum
= mips_regnum (gdbarch
)->hi
;
5813 regnum
= mips_regnum (gdbarch
)->lo
;
5814 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
5815 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
5817 /* This will hopefully (eventually) provoke a warning. Should
5818 we be calling complaint() here? */
5819 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5820 return gdbarch_num_regs (gdbarch
) + regnum
;
5824 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5825 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5828 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5831 if (num
>= 0 && num
< 32)
5833 else if (num
>= 32 && num
< 64)
5834 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5836 regnum
= mips_regnum (gdbarch
)->hi
;
5838 regnum
= mips_regnum (gdbarch
)->lo
;
5839 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
5840 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
5842 /* This will hopefully (eventually) provoke a warning. Should we
5843 be calling complaint() here? */
5844 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5845 return gdbarch_num_regs (gdbarch
) + regnum
;
5849 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5851 /* Only makes sense to supply raw registers. */
5852 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5853 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5854 decide if it is valid. Should instead define a standard sim/gdb
5855 register numbering scheme. */
5856 if (gdbarch_register_name (gdbarch
,
5857 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5858 && gdbarch_register_name (gdbarch
,
5859 gdbarch_num_regs (gdbarch
)
5860 + regnum
)[0] != '\0')
5863 return LEGACY_SIM_REGNO_IGNORE
;
5867 /* Convert an integer into an address. Extracting the value signed
5868 guarantees a correctly sign extended address. */
5871 mips_integer_to_address (struct gdbarch
*gdbarch
,
5872 struct type
*type
, const gdb_byte
*buf
)
5874 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5875 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
5878 /* Dummy virtual frame pointer method. This is no more or less accurate
5879 than most other architectures; we just need to be explicit about it,
5880 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5881 an assertion failure. */
5884 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5885 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5887 *reg
= MIPS_SP_REGNUM
;
5892 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5894 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5895 const char *name
= bfd_get_section_name (abfd
, sect
);
5897 if (*abip
!= MIPS_ABI_UNKNOWN
)
5900 if (strncmp (name
, ".mdebug.", 8) != 0)
5903 if (strcmp (name
, ".mdebug.abi32") == 0)
5904 *abip
= MIPS_ABI_O32
;
5905 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5906 *abip
= MIPS_ABI_N32
;
5907 else if (strcmp (name
, ".mdebug.abi64") == 0)
5908 *abip
= MIPS_ABI_N64
;
5909 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5910 *abip
= MIPS_ABI_O64
;
5911 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5912 *abip
= MIPS_ABI_EABI32
;
5913 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5914 *abip
= MIPS_ABI_EABI64
;
5916 warning (_("unsupported ABI %s."), name
+ 8);
5920 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5922 int *lbp
= (int *) obj
;
5923 const char *name
= bfd_get_section_name (abfd
, sect
);
5925 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5927 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5929 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5930 warning (_("unrecognized .gcc_compiled_longXX"));
5933 static enum mips_abi
5934 global_mips_abi (void)
5938 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5939 if (mips_abi_strings
[i
] == mips_abi_string
)
5940 return (enum mips_abi
) i
;
5942 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5946 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5948 /* If the size matches the set of 32-bit or 64-bit integer registers,
5949 assume that's what we've got. */
5950 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5951 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5953 /* If the size matches the full set of registers GDB traditionally
5954 knows about, including floating point, for either 32-bit or
5955 64-bit, assume that's what we've got. */
5956 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5957 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5959 /* Otherwise we don't have a useful guess. */
5962 static struct value
*
5963 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5965 const int *reg_p
= baton
;
5966 return value_of_register (*reg_p
, frame
);
5969 static struct gdbarch
*
5970 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5972 struct gdbarch
*gdbarch
;
5973 struct gdbarch_tdep
*tdep
;
5975 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5977 enum mips_fpu_type fpu_type
;
5978 struct tdesc_arch_data
*tdesc_data
= NULL
;
5979 int elf_fpu_type
= 0;
5980 const char **reg_names
;
5981 struct mips_regnum mips_regnum
, *regnum
;
5985 /* Fill in the OS dependent register numbers and names. */
5986 if (info
.osabi
== GDB_OSABI_IRIX
)
5988 mips_regnum
.fp0
= 32;
5989 mips_regnum
.pc
= 64;
5990 mips_regnum
.cause
= 65;
5991 mips_regnum
.badvaddr
= 66;
5992 mips_regnum
.hi
= 67;
5993 mips_regnum
.lo
= 68;
5994 mips_regnum
.fp_control_status
= 69;
5995 mips_regnum
.fp_implementation_revision
= 70;
5996 mips_regnum
.dspacc
= dspacc
= -1;
5997 mips_regnum
.dspctl
= dspctl
= -1;
5999 reg_names
= mips_irix_reg_names
;
6001 else if (info
.osabi
== GDB_OSABI_LINUX
)
6003 mips_regnum
.fp0
= 38;
6004 mips_regnum
.pc
= 37;
6005 mips_regnum
.cause
= 36;
6006 mips_regnum
.badvaddr
= 35;
6007 mips_regnum
.hi
= 34;
6008 mips_regnum
.lo
= 33;
6009 mips_regnum
.fp_control_status
= 70;
6010 mips_regnum
.fp_implementation_revision
= 71;
6011 mips_regnum
.dspacc
= -1;
6012 mips_regnum
.dspctl
= -1;
6016 reg_names
= mips_linux_reg_names
;
6020 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
6021 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
6022 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6023 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
6024 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
6025 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
6026 mips_regnum
.fp_control_status
= 70;
6027 mips_regnum
.fp_implementation_revision
= 71;
6028 mips_regnum
.dspacc
= dspacc
= -1;
6029 mips_regnum
.dspctl
= dspctl
= -1;
6030 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
6031 if (info
.bfd_arch_info
!= NULL
6032 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6033 reg_names
= mips_tx39_reg_names
;
6035 reg_names
= mips_generic_reg_names
;
6038 /* Check any target description for validity. */
6039 if (tdesc_has_registers (info
.target_desc
))
6041 static const char *const mips_gprs
[] = {
6042 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6043 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6044 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6045 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6047 static const char *const mips_fprs
[] = {
6048 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6049 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6050 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6051 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
6054 const struct tdesc_feature
*feature
;
6057 feature
= tdesc_find_feature (info
.target_desc
,
6058 "org.gnu.gdb.mips.cpu");
6059 if (feature
== NULL
)
6062 tdesc_data
= tdesc_data_alloc ();
6065 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
6066 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6070 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6071 mips_regnum
.lo
, "lo");
6072 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6073 mips_regnum
.hi
, "hi");
6074 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6075 mips_regnum
.pc
, "pc");
6079 tdesc_data_cleanup (tdesc_data
);
6083 feature
= tdesc_find_feature (info
.target_desc
,
6084 "org.gnu.gdb.mips.cp0");
6085 if (feature
== NULL
)
6087 tdesc_data_cleanup (tdesc_data
);
6092 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6093 mips_regnum
.badvaddr
, "badvaddr");
6094 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6095 MIPS_PS_REGNUM
, "status");
6096 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6097 mips_regnum
.cause
, "cause");
6101 tdesc_data_cleanup (tdesc_data
);
6105 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
6106 backend is not prepared for that, though. */
6107 feature
= tdesc_find_feature (info
.target_desc
,
6108 "org.gnu.gdb.mips.fpu");
6109 if (feature
== NULL
)
6111 tdesc_data_cleanup (tdesc_data
);
6116 for (i
= 0; i
< 32; i
++)
6117 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6118 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
6120 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6121 mips_regnum
.fp_control_status
,
6124 &= tdesc_numbered_register (feature
, tdesc_data
,
6125 mips_regnum
.fp_implementation_revision
,
6130 tdesc_data_cleanup (tdesc_data
);
6136 feature
= tdesc_find_feature (info
.target_desc
,
6137 "org.gnu.gdb.mips.dsp");
6138 /* The DSP registers are optional; it's OK if they are absent. */
6139 if (feature
!= NULL
)
6143 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6144 dspacc
+ i
++, "hi1");
6145 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6146 dspacc
+ i
++, "lo1");
6147 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6148 dspacc
+ i
++, "hi2");
6149 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6150 dspacc
+ i
++, "lo2");
6151 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6152 dspacc
+ i
++, "hi3");
6153 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6154 dspacc
+ i
++, "lo3");
6156 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6161 tdesc_data_cleanup (tdesc_data
);
6165 mips_regnum
.dspacc
= dspacc
;
6166 mips_regnum
.dspctl
= dspctl
;
6170 /* It would be nice to detect an attempt to use a 64-bit ABI
6171 when only 32-bit registers are provided. */
6175 /* First of all, extract the elf_flags, if available. */
6176 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6177 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6178 else if (arches
!= NULL
)
6179 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
6183 fprintf_unfiltered (gdb_stdlog
,
6184 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
6186 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
6187 switch ((elf_flags
& EF_MIPS_ABI
))
6189 case E_MIPS_ABI_O32
:
6190 found_abi
= MIPS_ABI_O32
;
6192 case E_MIPS_ABI_O64
:
6193 found_abi
= MIPS_ABI_O64
;
6195 case E_MIPS_ABI_EABI32
:
6196 found_abi
= MIPS_ABI_EABI32
;
6198 case E_MIPS_ABI_EABI64
:
6199 found_abi
= MIPS_ABI_EABI64
;
6202 if ((elf_flags
& EF_MIPS_ABI2
))
6203 found_abi
= MIPS_ABI_N32
;
6205 found_abi
= MIPS_ABI_UNKNOWN
;
6209 /* GCC creates a pseudo-section whose name describes the ABI. */
6210 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
6211 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6213 /* If we have no useful BFD information, use the ABI from the last
6214 MIPS architecture (if there is one). */
6215 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6216 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6218 /* Try the architecture for any hint of the correct ABI. */
6219 if (found_abi
== MIPS_ABI_UNKNOWN
6220 && info
.bfd_arch_info
!= NULL
6221 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6223 switch (info
.bfd_arch_info
->mach
)
6225 case bfd_mach_mips3900
:
6226 found_abi
= MIPS_ABI_EABI32
;
6228 case bfd_mach_mips4100
:
6229 case bfd_mach_mips5000
:
6230 found_abi
= MIPS_ABI_EABI64
;
6232 case bfd_mach_mips8000
:
6233 case bfd_mach_mips10000
:
6234 /* On Irix, ELF64 executables use the N64 ABI. The
6235 pseudo-sections which describe the ABI aren't present
6236 on IRIX. (Even for executables created by gcc.) */
6237 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6238 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6239 found_abi
= MIPS_ABI_N64
;
6241 found_abi
= MIPS_ABI_N32
;
6246 /* Default 64-bit objects to N64 instead of O32. */
6247 if (found_abi
== MIPS_ABI_UNKNOWN
6248 && info
.abfd
!= NULL
6249 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6250 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6251 found_abi
= MIPS_ABI_N64
;
6254 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6257 /* What has the user specified from the command line? */
6258 wanted_abi
= global_mips_abi ();
6260 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6263 /* Now that we have found what the ABI for this binary would be,
6264 check whether the user is overriding it. */
6265 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6266 mips_abi
= wanted_abi
;
6267 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6268 mips_abi
= found_abi
;
6270 mips_abi
= MIPS_ABI_O32
;
6272 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6275 /* Also used when doing an architecture lookup. */
6277 fprintf_unfiltered (gdb_stdlog
,
6278 "mips_gdbarch_init: "
6279 "mips64_transfers_32bit_regs_p = %d\n",
6280 mips64_transfers_32bit_regs_p
);
6282 /* Determine the MIPS FPU type. */
6285 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6286 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6287 Tag_GNU_MIPS_ABI_FP
);
6288 #endif /* HAVE_ELF */
6290 if (!mips_fpu_type_auto
)
6291 fpu_type
= mips_fpu_type
;
6292 else if (elf_fpu_type
!= 0)
6294 switch (elf_fpu_type
)
6297 fpu_type
= MIPS_FPU_DOUBLE
;
6300 fpu_type
= MIPS_FPU_SINGLE
;
6304 /* Soft float or unknown. */
6305 fpu_type
= MIPS_FPU_NONE
;
6309 else if (info
.bfd_arch_info
!= NULL
6310 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6311 switch (info
.bfd_arch_info
->mach
)
6313 case bfd_mach_mips3900
:
6314 case bfd_mach_mips4100
:
6315 case bfd_mach_mips4111
:
6316 case bfd_mach_mips4120
:
6317 fpu_type
= MIPS_FPU_NONE
;
6319 case bfd_mach_mips4650
:
6320 fpu_type
= MIPS_FPU_SINGLE
;
6323 fpu_type
= MIPS_FPU_DOUBLE
;
6326 else if (arches
!= NULL
)
6327 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6329 fpu_type
= MIPS_FPU_DOUBLE
;
6331 fprintf_unfiltered (gdb_stdlog
,
6332 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6334 /* Check for blatant incompatibilities. */
6336 /* If we have only 32-bit registers, then we can't debug a 64-bit
6338 if (info
.target_desc
6339 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
6340 && mips_abi
!= MIPS_ABI_EABI32
6341 && mips_abi
!= MIPS_ABI_O32
)
6343 if (tdesc_data
!= NULL
)
6344 tdesc_data_cleanup (tdesc_data
);
6348 /* Try to find a pre-existing architecture. */
6349 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6351 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6353 /* MIPS needs to be pedantic about which ABI the object is
6355 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6357 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6359 /* Need to be pedantic about which register virtual size is
6361 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6362 != mips64_transfers_32bit_regs_p
)
6364 /* Be pedantic about which FPU is selected. */
6365 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6368 if (tdesc_data
!= NULL
)
6369 tdesc_data_cleanup (tdesc_data
);
6370 return arches
->gdbarch
;
6373 /* Need a new architecture. Fill in a target specific vector. */
6374 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6375 gdbarch
= gdbarch_alloc (&info
, tdep
);
6376 tdep
->elf_flags
= elf_flags
;
6377 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6378 tdep
->found_abi
= found_abi
;
6379 tdep
->mips_abi
= mips_abi
;
6380 tdep
->mips_fpu_type
= fpu_type
;
6381 tdep
->register_size_valid_p
= 0;
6382 tdep
->register_size
= 0;
6383 tdep
->gregset
= NULL
;
6384 tdep
->gregset64
= NULL
;
6385 tdep
->fpregset
= NULL
;
6386 tdep
->fpregset64
= NULL
;
6388 if (info
.target_desc
)
6390 /* Some useful properties can be inferred from the target. */
6391 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
6393 tdep
->register_size_valid_p
= 1;
6394 tdep
->register_size
= 4;
6396 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
6398 tdep
->register_size_valid_p
= 1;
6399 tdep
->register_size
= 8;
6403 /* Initially set everything according to the default ABI/ISA. */
6404 set_gdbarch_short_bit (gdbarch
, 16);
6405 set_gdbarch_int_bit (gdbarch
, 32);
6406 set_gdbarch_float_bit (gdbarch
, 32);
6407 set_gdbarch_double_bit (gdbarch
, 64);
6408 set_gdbarch_long_double_bit (gdbarch
, 64);
6409 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6410 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6411 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6413 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6414 mips_ax_pseudo_register_collect
);
6415 set_gdbarch_ax_pseudo_register_push_stack
6416 (gdbarch
, mips_ax_pseudo_register_push_stack
);
6418 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6419 mips_elf_make_msymbol_special
);
6421 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
6422 *regnum
= mips_regnum
;
6423 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6424 set_gdbarch_num_regs (gdbarch
, num_regs
);
6425 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6426 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6427 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
6428 tdep
->mips_processor_reg_names
= reg_names
;
6429 tdep
->regnum
= regnum
;
6434 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6435 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6436 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6437 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6438 tdep
->default_mask_address_p
= 0;
6439 set_gdbarch_long_bit (gdbarch
, 32);
6440 set_gdbarch_ptr_bit (gdbarch
, 32);
6441 set_gdbarch_long_long_bit (gdbarch
, 64);
6444 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6445 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6446 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6447 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6448 tdep
->default_mask_address_p
= 0;
6449 set_gdbarch_long_bit (gdbarch
, 32);
6450 set_gdbarch_ptr_bit (gdbarch
, 32);
6451 set_gdbarch_long_long_bit (gdbarch
, 64);
6453 case MIPS_ABI_EABI32
:
6454 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6455 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6456 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6457 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6458 tdep
->default_mask_address_p
= 0;
6459 set_gdbarch_long_bit (gdbarch
, 32);
6460 set_gdbarch_ptr_bit (gdbarch
, 32);
6461 set_gdbarch_long_long_bit (gdbarch
, 64);
6463 case MIPS_ABI_EABI64
:
6464 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6465 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6466 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6467 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6468 tdep
->default_mask_address_p
= 0;
6469 set_gdbarch_long_bit (gdbarch
, 64);
6470 set_gdbarch_ptr_bit (gdbarch
, 64);
6471 set_gdbarch_long_long_bit (gdbarch
, 64);
6474 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6475 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6476 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6477 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6478 tdep
->default_mask_address_p
= 0;
6479 set_gdbarch_long_bit (gdbarch
, 32);
6480 set_gdbarch_ptr_bit (gdbarch
, 32);
6481 set_gdbarch_long_long_bit (gdbarch
, 64);
6482 set_gdbarch_long_double_bit (gdbarch
, 128);
6483 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6486 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6487 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6488 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6489 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6490 tdep
->default_mask_address_p
= 0;
6491 set_gdbarch_long_bit (gdbarch
, 64);
6492 set_gdbarch_ptr_bit (gdbarch
, 64);
6493 set_gdbarch_long_long_bit (gdbarch
, 64);
6494 set_gdbarch_long_double_bit (gdbarch
, 128);
6495 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6498 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6501 /* GCC creates a pseudo-section whose name specifies the size of
6502 longs, since -mlong32 or -mlong64 may be used independent of
6503 other options. How those options affect pointer sizes is ABI and
6504 architecture dependent, so use them to override the default sizes
6505 set by the ABI. This table shows the relationship between ABI,
6506 -mlongXX, and size of pointers:
6508 ABI -mlongXX ptr bits
6509 --- -------- --------
6523 Note that for o32 and eabi32, pointers are always 32 bits
6524 regardless of any -mlongXX option. For all others, pointers and
6525 longs are the same, as set by -mlongXX or set by defaults. */
6527 if (info
.abfd
!= NULL
)
6531 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6534 set_gdbarch_long_bit (gdbarch
, long_bit
);
6538 case MIPS_ABI_EABI32
:
6543 case MIPS_ABI_EABI64
:
6544 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6547 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6552 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6553 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6556 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6557 flag in object files because to do so would make it impossible to
6558 link with libraries compiled without "-gp32". This is
6559 unnecessarily restrictive.
6561 We could solve this problem by adding "-gp32" multilibs to gcc,
6562 but to set this flag before gcc is built with such multilibs will
6563 break too many systems.''
6565 But even more unhelpfully, the default linker output target for
6566 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6567 for 64-bit programs - you need to change the ABI to change this,
6568 and not all gcc targets support that currently. Therefore using
6569 this flag to detect 32-bit mode would do the wrong thing given
6570 the current gcc - it would make GDB treat these 64-bit programs
6571 as 32-bit programs by default. */
6573 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6574 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6576 /* Add/remove bits from an address. The MIPS needs be careful to
6577 ensure that all 32 bit addresses are sign extended to 64 bits. */
6578 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6580 /* Unwind the frame. */
6581 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6582 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
6583 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
6585 /* Map debug register numbers onto internal register numbers. */
6586 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6587 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6588 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6589 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6590 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6591 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6593 /* MIPS version of CALL_DUMMY. */
6595 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6596 replaced by a command, and all targets will default to on stack
6597 (regardless of the stack's execute status). */
6598 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6599 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6601 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6602 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6603 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6605 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6606 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6607 set_gdbarch_adjust_breakpoint_address (gdbarch
,
6608 mips_adjust_breakpoint_address
);
6610 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6612 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6614 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6615 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6616 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6618 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6620 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6622 if (mips_abi
== MIPS_ABI_N32
)
6623 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6624 else if (mips_abi
== MIPS_ABI_N64
)
6625 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6627 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6629 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6630 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6631 need to all be folded into the target vector. Since they are
6632 being used as guards for target_stopped_by_watchpoint, why not have
6633 target_stopped_by_watchpoint return the type of watchpoint that the code
6635 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6637 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6639 set_gdbarch_single_step_through_delay (gdbarch
,
6640 mips_single_step_through_delay
);
6642 /* Virtual tables. */
6643 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6645 mips_register_g_packet_guesses (gdbarch
);
6647 /* Hook in OS ABI-specific overrides, if they have been registered. */
6648 info
.tdep_info
= (void *) tdesc_data
;
6649 gdbarch_init_osabi (info
, gdbarch
);
6651 /* The hook may have adjusted num_regs, fetch the final value and
6652 set pc_regnum and sp_regnum now that it has been fixed. */
6653 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
6654 replaced by gdbarch_read_pc? */
6655 num_regs
= gdbarch_num_regs (gdbarch
);
6656 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6657 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6659 /* Unwind the frame. */
6660 dwarf2_append_unwinders (gdbarch
);
6661 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6662 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6663 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6664 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6665 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6666 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6667 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6671 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6672 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6674 /* Override the normal target description methods to handle our
6675 dual real and pseudo registers. */
6676 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6677 set_gdbarch_register_reggroup_p (gdbarch
,
6678 mips_tdesc_register_reggroup_p
);
6680 num_regs
= gdbarch_num_regs (gdbarch
);
6681 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6682 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6683 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6686 /* Add ABI-specific aliases for the registers. */
6687 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6688 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6689 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6690 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6692 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6693 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6694 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6696 /* Add some other standard aliases. */
6697 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6698 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6699 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6701 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6702 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6703 value_of_mips_user_reg
,
6704 &mips_numeric_register_aliases
[i
].regnum
);
6710 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6712 struct gdbarch_info info
;
6714 /* Force the architecture to update, and (if it's a MIPS architecture)
6715 mips_gdbarch_init will take care of the rest. */
6716 gdbarch_info_init (&info
);
6717 gdbarch_update_p (info
);
6720 /* Print out which MIPS ABI is in use. */
6723 show_mips_abi (struct ui_file
*file
,
6725 struct cmd_list_element
*ignored_cmd
,
6726 const char *ignored_value
)
6728 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6731 "The MIPS ABI is unknown because the current architecture "
6735 enum mips_abi global_abi
= global_mips_abi ();
6736 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6737 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6739 if (global_abi
== MIPS_ABI_UNKNOWN
)
6742 "The MIPS ABI is set automatically (currently \"%s\").\n",
6744 else if (global_abi
== actual_abi
)
6747 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6751 /* Probably shouldn't happen... */
6752 fprintf_filtered (file
,
6753 "The (auto detected) MIPS ABI \"%s\" is in use "
6754 "even though the user setting was \"%s\".\n",
6755 actual_abi_str
, mips_abi_strings
[global_abi
]);
6761 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6763 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6767 int ef_mips_32bitmode
;
6768 /* Determine the ISA. */
6769 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6787 /* Determine the size of a pointer. */
6788 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6789 fprintf_unfiltered (file
,
6790 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6792 fprintf_unfiltered (file
,
6793 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6795 fprintf_unfiltered (file
,
6796 "mips_dump_tdep: ef_mips_arch = %d\n",
6798 fprintf_unfiltered (file
,
6799 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6800 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6801 fprintf_unfiltered (file
,
6803 "mips_mask_address_p() %d (default %d)\n",
6804 mips_mask_address_p (tdep
),
6805 tdep
->default_mask_address_p
);
6807 fprintf_unfiltered (file
,
6808 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6809 MIPS_DEFAULT_FPU_TYPE
,
6810 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6811 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6812 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6814 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6815 MIPS_EABI (gdbarch
));
6816 fprintf_unfiltered (file
,
6817 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6818 MIPS_FPU_TYPE (gdbarch
),
6819 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6820 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6821 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6825 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6828 _initialize_mips_tdep (void)
6830 static struct cmd_list_element
*mipsfpulist
= NULL
;
6831 struct cmd_list_element
*c
;
6833 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6834 if (MIPS_ABI_LAST
+ 1
6835 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6836 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6838 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6840 mips_pdr_data
= register_objfile_data ();
6842 /* Create feature sets with the appropriate properties. The values
6843 are not important. */
6844 mips_tdesc_gp32
= allocate_target_description ();
6845 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6847 mips_tdesc_gp64
= allocate_target_description ();
6848 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6850 /* Add root prefix command for all "set mips"/"show mips" commands. */
6851 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6852 _("Various MIPS specific commands."),
6853 &setmipscmdlist
, "set mips ", 0, &setlist
);
6855 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6856 _("Various MIPS specific commands."),
6857 &showmipscmdlist
, "show mips ", 0, &showlist
);
6859 /* Allow the user to override the ABI. */
6860 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6861 &mips_abi_string
, _("\
6862 Set the MIPS ABI used by this program."), _("\
6863 Show the MIPS ABI used by this program."), _("\
6864 This option can be set to one of:\n\
6865 auto - the default ABI associated with the current binary\n\
6874 &setmipscmdlist
, &showmipscmdlist
);
6876 /* Let the user turn off floating point and set the fence post for
6877 heuristic_proc_start. */
6879 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6880 _("Set use of MIPS floating-point coprocessor."),
6881 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6882 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6883 _("Select single-precision MIPS floating-point coprocessor."),
6885 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6886 _("Select double-precision MIPS floating-point coprocessor."),
6888 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6889 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6890 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6891 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6892 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6893 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6894 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6895 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6896 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6897 _("Select MIPS floating-point coprocessor automatically."),
6899 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6900 _("Show current use of MIPS floating-point coprocessor target."),
6903 /* We really would like to have both "0" and "unlimited" work, but
6904 command.c doesn't deal with that. So make it a var_zinteger
6905 because the user can always use "999999" or some such for unlimited. */
6906 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6907 &heuristic_fence_post
, _("\
6908 Set the distance searched for the start of a function."), _("\
6909 Show the distance searched for the start of a function."), _("\
6910 If you are debugging a stripped executable, GDB needs to search through the\n\
6911 program for the start of a function. This command sets the distance of the\n\
6912 search. The only need to set it is when debugging a stripped executable."),
6913 reinit_frame_cache_sfunc
,
6914 NULL
, /* FIXME: i18n: The distance searched for
6915 the start of a function is %s. */
6916 &setlist
, &showlist
);
6918 /* Allow the user to control whether the upper bits of 64-bit
6919 addresses should be zeroed. */
6920 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6921 &mask_address_var
, _("\
6922 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6923 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6924 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
6925 allow GDB to determine the correct value."),
6926 NULL
, show_mask_address
,
6927 &setmipscmdlist
, &showmipscmdlist
);
6929 /* Allow the user to control the size of 32 bit registers within the
6930 raw remote packet. */
6931 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6932 &mips64_transfers_32bit_regs_p
, _("\
6933 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6935 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6937 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6938 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6939 64 bits for others. Use \"off\" to disable compatibility mode"),
6940 set_mips64_transfers_32bit_regs
,
6941 NULL
, /* FIXME: i18n: Compatibility with 64-bit
6942 MIPS target that transfers 32-bit
6943 quantities is %s. */
6944 &setlist
, &showlist
);
6946 /* Debug this files internals. */
6947 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6949 Set mips debugging."), _("\
6950 Show mips debugging."), _("\
6951 When non-zero, mips specific debugging is enabled."),
6953 NULL
, /* FIXME: i18n: Mips debugging is
6955 &setdebuglist
, &showdebuglist
);