1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
63 static const struct objfile_data
*mips_pdr_data
;
65 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
67 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
68 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
69 #define ST0_FR (1 << 26)
71 /* The sizes of floating point registers. */
75 MIPS_FPU_SINGLE_REGSIZE
= 4,
76 MIPS_FPU_DOUBLE_REGSIZE
= 8
85 static const char *mips_abi_string
;
87 static const char *mips_abi_strings
[] = {
98 /* The standard register names, and all the valid aliases for them. */
105 /* Aliases for o32 and most other ABIs. */
106 const struct register_alias mips_o32_aliases
[] = {
113 /* Aliases for n32 and n64. */
114 const struct register_alias mips_n32_n64_aliases
[] = {
121 /* Aliases for ABI-independent registers. */
122 const struct register_alias mips_register_aliases
[] = {
123 /* The architecture manuals specify these ABI-independent names for
125 #define R(n) { "r" #n, n }
126 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
127 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
128 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
129 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
132 /* k0 and k1 are sometimes called these instead (for "kernel
137 /* This is the traditional GDB name for the CP0 status register. */
138 { "sr", MIPS_PS_REGNUM
},
140 /* This is the traditional GDB name for the CP0 BadVAddr register. */
141 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
143 /* This is the traditional GDB name for the FCSR. */
144 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
147 const struct register_alias mips_numeric_register_aliases
[] = {
148 #define R(n) { #n, n }
149 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
150 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
151 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
152 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
156 #ifndef MIPS_DEFAULT_FPU_TYPE
157 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
159 static int mips_fpu_type_auto
= 1;
160 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
162 static int mips_debug
= 0;
164 /* Properties (for struct target_desc) describing the g/G packet
166 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
167 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
169 struct target_desc
*mips_tdesc_gp32
;
170 struct target_desc
*mips_tdesc_gp64
;
172 const struct mips_regnum
*
173 mips_regnum (struct gdbarch
*gdbarch
)
175 return gdbarch_tdep (gdbarch
)->regnum
;
179 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
181 return mips_regnum (gdbarch
)->fp0
+ 12;
184 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
186 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
188 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
189 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
191 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
192 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
194 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
196 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
197 functions to test, set, or clear bit 0 of addresses. */
200 is_mips16_addr (CORE_ADDR addr
)
206 unmake_mips16_addr (CORE_ADDR addr
)
208 return ((addr
) & ~(CORE_ADDR
) 1);
212 make_mips16_addr (CORE_ADDR addr
)
214 return ((addr
) | (CORE_ADDR
) 1);
217 /* Return the MIPS ABI associated with GDBARCH. */
219 mips_abi (struct gdbarch
*gdbarch
)
221 return gdbarch_tdep (gdbarch
)->mips_abi
;
225 mips_isa_regsize (struct gdbarch
*gdbarch
)
227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
229 /* If we know how big the registers are, use that size. */
230 if (tdep
->register_size_valid_p
)
231 return tdep
->register_size
;
233 /* Fall back to the previous behavior. */
234 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
235 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
238 /* Return the currently configured (or set) saved register size. */
241 mips_abi_regsize (struct gdbarch
*gdbarch
)
243 switch (mips_abi (gdbarch
))
245 case MIPS_ABI_EABI32
:
251 case MIPS_ABI_EABI64
:
253 case MIPS_ABI_UNKNOWN
:
256 internal_error (__FILE__
, __LINE__
, _("bad switch"));
260 /* Functions for setting and testing a bit in a minimal symbol that
261 marks it as 16-bit function. The MSB of the minimal symbol's
262 "info" field is used for this purpose.
264 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
265 i.e. refers to a 16-bit function, and sets a "special" bit in a
266 minimal symbol to mark it as a 16-bit function
268 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
271 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
273 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
275 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
280 msymbol_is_special (struct minimal_symbol
*msym
)
282 return MSYMBOL_TARGET_FLAG_1 (msym
);
285 /* XFER a value from the big/little/left end of the register.
286 Depending on the size of the value it might occupy the entire
287 register or just part of it. Make an allowance for this, aligning
288 things accordingly. */
291 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
292 int reg_num
, int length
,
293 enum bfd_endian endian
, gdb_byte
*in
,
294 const gdb_byte
*out
, int buf_offset
)
298 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
299 /* Need to transfer the left or right part of the register, based on
300 the targets byte order. */
304 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
306 case BFD_ENDIAN_LITTLE
:
309 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
313 internal_error (__FILE__
, __LINE__
, _("bad switch"));
316 fprintf_unfiltered (gdb_stderr
,
317 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
318 reg_num
, reg_offset
, buf_offset
, length
);
319 if (mips_debug
&& out
!= NULL
)
322 fprintf_unfiltered (gdb_stdlog
, "out ");
323 for (i
= 0; i
< length
; i
++)
324 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
327 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
330 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
332 if (mips_debug
&& in
!= NULL
)
335 fprintf_unfiltered (gdb_stdlog
, "in ");
336 for (i
= 0; i
< length
; i
++)
337 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
340 fprintf_unfiltered (gdb_stdlog
, "\n");
343 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
344 compatiblity mode. A return value of 1 means that we have
345 physical 64-bit registers, but should treat them as 32-bit registers. */
348 mips2_fp_compat (struct frame_info
*frame
)
350 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
351 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
353 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
357 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
358 in all the places we deal with FP registers. PR gdb/413. */
359 /* Otherwise check the FR bit in the status register - it controls
360 the FP compatiblity mode. If it is clear we are in compatibility
362 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
369 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
371 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
373 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
375 /* The list of available "set mips " and "show mips " commands. */
377 static struct cmd_list_element
*setmipscmdlist
= NULL
;
378 static struct cmd_list_element
*showmipscmdlist
= NULL
;
380 /* Integer registers 0 thru 31 are handled explicitly by
381 mips_register_name(). Processor specific registers 32 and above
382 are listed in the following tables. */
385 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
389 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
390 "sr", "lo", "hi", "bad", "cause", "pc",
391 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
392 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
393 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
394 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
395 "fsr", "fir", "" /*"fp" */ , "",
396 "", "", "", "", "", "", "", "",
397 "", "", "", "", "", "", "", "",
400 /* Names of IDT R3041 registers. */
402 static const char *mips_r3041_reg_names
[] = {
403 "sr", "lo", "hi", "bad", "cause", "pc",
404 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
405 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
406 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
407 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
408 "fsr", "fir", "", /*"fp" */ "",
409 "", "", "bus", "ccfg", "", "", "", "",
410 "", "", "port", "cmp", "", "", "epc", "prid",
413 /* Names of tx39 registers. */
415 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
416 "sr", "lo", "hi", "bad", "cause", "pc",
417 "", "", "", "", "", "", "", "",
418 "", "", "", "", "", "", "", "",
419 "", "", "", "", "", "", "", "",
420 "", "", "", "", "", "", "", "",
422 "", "", "", "", "", "", "", "",
423 "", "", "config", "cache", "debug", "depc", "epc", ""
426 /* Names of IRIX registers. */
427 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
428 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
429 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
430 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
431 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
432 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
436 /* Return the name of the register corresponding to REGNO. */
438 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
440 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
441 /* GPR names for all ABIs other than n32/n64. */
442 static char *mips_gpr_names
[] = {
443 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
444 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
445 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
446 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
449 /* GPR names for n32 and n64 ABIs. */
450 static char *mips_n32_n64_gpr_names
[] = {
451 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
452 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
453 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
454 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
457 enum mips_abi abi
= mips_abi (gdbarch
);
459 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
460 but then don't make the raw register names visible. This (upper)
461 range of user visible register numbers are the pseudo-registers.
463 This approach was adopted accommodate the following scenario:
464 It is possible to debug a 64-bit device using a 32-bit
465 programming model. In such instances, the raw registers are
466 configured to be 64-bits wide, while the pseudo registers are
467 configured to be 32-bits wide. The registers that the user
468 sees - the pseudo registers - match the users expectations
469 given the programming model being used. */
470 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
471 if (regno
< gdbarch_num_regs (gdbarch
))
474 /* The MIPS integer registers are always mapped from 0 to 31. The
475 names of the registers (which reflects the conventions regarding
476 register use) vary depending on the ABI. */
477 if (0 <= rawnum
&& rawnum
< 32)
479 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
480 return mips_n32_n64_gpr_names
[rawnum
];
482 return mips_gpr_names
[rawnum
];
484 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
485 return tdesc_register_name (gdbarch
, rawnum
);
486 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
488 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
489 return tdep
->mips_processor_reg_names
[rawnum
- 32];
492 internal_error (__FILE__
, __LINE__
,
493 _("mips_register_name: bad register number %d"), rawnum
);
496 /* Return the groups that a MIPS register can be categorised into. */
499 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
500 struct reggroup
*reggroup
)
505 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
506 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
507 if (reggroup
== all_reggroup
)
509 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
510 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
511 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
512 (gdbarch), as not all architectures are multi-arch. */
513 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
514 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
515 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
517 if (reggroup
== float_reggroup
)
518 return float_p
&& pseudo
;
519 if (reggroup
== vector_reggroup
)
520 return vector_p
&& pseudo
;
521 if (reggroup
== general_reggroup
)
522 return (!vector_p
&& !float_p
) && pseudo
;
523 /* Save the pseudo registers. Need to make certain that any code
524 extracting register values from a saved register cache also uses
526 if (reggroup
== save_reggroup
)
527 return raw_p
&& pseudo
;
528 /* Restore the same pseudo register. */
529 if (reggroup
== restore_reggroup
)
530 return raw_p
&& pseudo
;
534 /* Return the groups that a MIPS register can be categorised into.
535 This version is only used if we have a target description which
536 describes real registers (and their groups). */
539 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
540 struct reggroup
*reggroup
)
542 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
543 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
546 /* Only save, restore, and display the pseudo registers. Need to
547 make certain that any code extracting register values from a
548 saved register cache also uses pseudo registers.
550 Note: saving and restoring the pseudo registers is slightly
551 strange; if we have 64 bits, we should save and restore all
552 64 bits. But this is hard and has little benefit. */
556 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
560 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
563 /* Map the symbol table registers which live in the range [1 *
564 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
565 registers. Take care of alignment and size problems. */
567 static enum register_status
568 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
569 int cookednum
, gdb_byte
*buf
)
571 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
572 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
573 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
574 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
575 return regcache_raw_read (regcache
, rawnum
, buf
);
576 else if (register_size (gdbarch
, rawnum
) >
577 register_size (gdbarch
, cookednum
))
579 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
580 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
583 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
585 enum register_status status
;
587 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
588 if (status
== REG_VALID
)
589 store_signed_integer (buf
, 4, byte_order
, regval
);
594 internal_error (__FILE__
, __LINE__
, _("bad register size"));
598 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
599 struct regcache
*regcache
, int cookednum
,
602 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
603 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
604 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
605 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
606 regcache_raw_write (regcache
, rawnum
, buf
);
607 else if (register_size (gdbarch
, rawnum
) >
608 register_size (gdbarch
, cookednum
))
610 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
611 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
614 /* Sign extend the shortened version of the register prior
615 to placing it in the raw register. This is required for
616 some mips64 parts in order to avoid unpredictable behavior. */
617 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
618 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
619 regcache_raw_write_signed (regcache
, rawnum
, regval
);
623 internal_error (__FILE__
, __LINE__
, _("bad register size"));
627 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
628 struct agent_expr
*ax
, int reg
)
630 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
631 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
632 && reg
< 2 * gdbarch_num_regs (gdbarch
));
634 ax_reg_mask (ax
, rawnum
);
640 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
641 struct agent_expr
*ax
, int reg
)
643 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
644 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
645 && reg
< 2 * gdbarch_num_regs (gdbarch
));
646 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
650 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
652 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
653 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
656 ax_simple (ax
, aop_lsh
);
659 ax_simple (ax
, aop_rsh_signed
);
663 internal_error (__FILE__
, __LINE__
, _("bad register size"));
668 /* Table to translate MIPS16 register field to actual register number. */
669 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
671 /* Heuristic_proc_start may hunt through the text section for a long
672 time across a 2400 baud serial line. Allows the user to limit this
675 static unsigned int heuristic_fence_post
= 0;
677 /* Number of bytes of storage in the actual machine representation for
678 register N. NOTE: This defines the pseudo register type so need to
679 rebuild the architecture vector. */
681 static int mips64_transfers_32bit_regs_p
= 0;
684 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
685 struct cmd_list_element
*c
)
687 struct gdbarch_info info
;
688 gdbarch_info_init (&info
);
689 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
690 instead of relying on globals. Doing that would let generic code
691 handle the search for this specific architecture. */
692 if (!gdbarch_update_p (info
))
694 mips64_transfers_32bit_regs_p
= 0;
695 error (_("32-bit compatibility mode not supported"));
699 /* Convert to/from a register and the corresponding memory value. */
701 /* This predicate tests for the case of an 8 byte floating point
702 value that is being transferred to or from a pair of floating point
703 registers each of which are (or are considered to be) only 4 bytes
706 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
709 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
710 && register_size (gdbarch
, regnum
) == 4
711 && (regnum
% gdbarch_num_regs (gdbarch
))
712 >= mips_regnum (gdbarch
)->fp0
713 && (regnum
% gdbarch_num_regs (gdbarch
))
714 < mips_regnum (gdbarch
)->fp0
+ 32
715 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
718 /* This predicate tests for the case of a value of less than 8
719 bytes in width that is being transfered to or from an 8 byte
720 general purpose register. */
722 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
725 int num_regs
= gdbarch_num_regs (gdbarch
);
727 return (register_size (gdbarch
, regnum
) == 8
728 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
729 && TYPE_LENGTH (type
) < 8);
733 mips_convert_register_p (struct gdbarch
*gdbarch
,
734 int regnum
, struct type
*type
)
736 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
737 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
741 mips_register_to_value (struct frame_info
*frame
, int regnum
,
742 struct type
*type
, gdb_byte
*to
,
743 int *optimizedp
, int *unavailablep
)
745 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
747 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
749 get_frame_register (frame
, regnum
+ 0, to
+ 4);
750 get_frame_register (frame
, regnum
+ 1, to
+ 0);
752 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
753 optimizedp
, unavailablep
))
756 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
757 optimizedp
, unavailablep
))
759 *optimizedp
= *unavailablep
= 0;
762 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
764 int len
= TYPE_LENGTH (type
);
767 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
768 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
769 optimizedp
, unavailablep
))
772 *optimizedp
= *unavailablep
= 0;
777 internal_error (__FILE__
, __LINE__
,
778 _("mips_register_to_value: unrecognized case"));
783 mips_value_to_register (struct frame_info
*frame
, int regnum
,
784 struct type
*type
, const gdb_byte
*from
)
786 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
788 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
790 put_frame_register (frame
, regnum
+ 0, from
+ 4);
791 put_frame_register (frame
, regnum
+ 1, from
+ 0);
793 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
796 int len
= TYPE_LENGTH (type
);
798 /* Sign extend values, irrespective of type, that are stored to
799 a 64-bit general purpose register. (32-bit unsigned values
800 are stored as signed quantities within a 64-bit register.
801 When performing an operation, in compiled code, that combines
802 a 32-bit unsigned value with a signed 64-bit value, a type
803 conversion is first performed that zeroes out the high 32 bits.) */
804 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
807 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
809 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
810 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
811 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
815 if (from
[len
-1] & 0x80)
816 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
818 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
819 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
820 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
825 internal_error (__FILE__
, __LINE__
,
826 _("mips_value_to_register: unrecognized case"));
830 /* Return the GDB type object for the "standard" data type of data in
834 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
836 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
837 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
838 && (regnum
% gdbarch_num_regs (gdbarch
))
839 < mips_regnum (gdbarch
)->fp0
+ 32)
841 /* The floating-point registers raw, or cooked, always match
842 mips_isa_regsize(), and also map 1:1, byte for byte. */
843 if (mips_isa_regsize (gdbarch
) == 4)
844 return builtin_type (gdbarch
)->builtin_float
;
846 return builtin_type (gdbarch
)->builtin_double
;
848 else if (regnum
< gdbarch_num_regs (gdbarch
))
850 /* The raw or ISA registers. These are all sized according to
852 if (mips_isa_regsize (gdbarch
) == 4)
853 return builtin_type (gdbarch
)->builtin_int32
;
855 return builtin_type (gdbarch
)->builtin_int64
;
859 /* The cooked or ABI registers. These are sized according to
860 the ABI (with a few complications). */
861 if (regnum
>= (gdbarch_num_regs (gdbarch
)
862 + mips_regnum (gdbarch
)->fp_control_status
)
863 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
864 /* The pseudo/cooked view of the embedded registers is always
865 32-bit. The raw view is handled below. */
866 return builtin_type (gdbarch
)->builtin_int32
;
867 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
868 /* The target, while possibly using a 64-bit register buffer,
869 is only transfering 32-bits of each integer register.
870 Reflect this in the cooked/pseudo (ABI) register value. */
871 return builtin_type (gdbarch
)->builtin_int32
;
872 else if (mips_abi_regsize (gdbarch
) == 4)
873 /* The ABI is restricted to 32-bit registers (the ISA could be
875 return builtin_type (gdbarch
)->builtin_int32
;
878 return builtin_type (gdbarch
)->builtin_int64
;
882 /* Return the GDB type for the pseudo register REGNUM, which is the
883 ABI-level view. This function is only called if there is a target
884 description which includes registers, so we know precisely the
885 types of hardware registers. */
888 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
890 const int num_regs
= gdbarch_num_regs (gdbarch
);
891 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
892 int rawnum
= regnum
% num_regs
;
893 struct type
*rawtype
;
895 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
897 /* Absent registers are still absent. */
898 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
899 if (TYPE_LENGTH (rawtype
) == 0)
902 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
903 /* Present the floating point registers however the hardware did;
904 do not try to convert between FPU layouts. */
907 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
909 /* The pseudo/cooked view of embedded registers is always
910 32-bit, even if the target transfers 64-bit values for them.
911 New targets relying on XML descriptions should only transfer
912 the necessary 32 bits, but older versions of GDB expected 64,
913 so allow the target to provide 64 bits without interfering
914 with the displayed type. */
915 return builtin_type (gdbarch
)->builtin_int32
;
918 /* Use pointer types for registers if we can. For n32 we can not,
919 since we do not have a 64-bit pointer type. */
920 if (mips_abi_regsize (gdbarch
)
921 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
923 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
924 return builtin_type (gdbarch
)->builtin_data_ptr
;
925 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
926 return builtin_type (gdbarch
)->builtin_func_ptr
;
929 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
930 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
931 return builtin_type (gdbarch
)->builtin_int32
;
933 /* For all other registers, pass through the hardware type. */
937 /* Should the upper word of 64-bit addresses be zeroed? */
938 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
941 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
943 switch (mask_address_var
)
945 case AUTO_BOOLEAN_TRUE
:
947 case AUTO_BOOLEAN_FALSE
:
950 case AUTO_BOOLEAN_AUTO
:
951 return tdep
->default_mask_address_p
;
953 internal_error (__FILE__
, __LINE__
,
954 _("mips_mask_address_p: bad switch"));
960 show_mask_address (struct ui_file
*file
, int from_tty
,
961 struct cmd_list_element
*c
, const char *value
)
963 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
965 deprecated_show_value_hack (file
, from_tty
, c
, value
);
966 switch (mask_address_var
)
968 case AUTO_BOOLEAN_TRUE
:
969 printf_filtered ("The 32 bit mips address mask is enabled\n");
971 case AUTO_BOOLEAN_FALSE
:
972 printf_filtered ("The 32 bit mips address mask is disabled\n");
974 case AUTO_BOOLEAN_AUTO
:
976 ("The 32 bit address mask is set automatically. Currently %s\n",
977 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
980 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
985 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
988 mips_pc_is_mips16 (CORE_ADDR memaddr
)
990 struct minimal_symbol
*sym
;
992 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
993 if (is_mips16_addr (memaddr
))
996 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
997 the high bit of the info field. Use this to decide if the function is
998 MIPS16 or normal MIPS. */
999 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1001 return msymbol_is_special (sym
);
1006 /* MIPS believes that the PC has a sign extended value. Perhaps the
1007 all registers should be sign extended for simplicity? */
1010 mips_read_pc (struct regcache
*regcache
)
1013 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1014 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1015 if (is_mips16_addr (pc
))
1016 pc
= unmake_mips16_addr (pc
);
1021 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1025 pc
= frame_unwind_register_signed
1026 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
1027 if (is_mips16_addr (pc
))
1028 pc
= unmake_mips16_addr (pc
);
1033 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1035 return frame_unwind_register_signed
1036 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1039 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1040 dummy frame. The frame ID's base needs to match the TOS value
1041 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1044 static struct frame_id
1045 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1047 return frame_id_build
1048 (get_frame_register_signed (this_frame
,
1049 gdbarch_num_regs (gdbarch
)
1051 get_frame_pc (this_frame
));
1055 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1057 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1058 if (mips_pc_is_mips16 (pc
))
1059 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
1061 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1064 /* Fetch and return instruction from the specified location. If the PC
1065 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1068 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1070 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1071 gdb_byte buf
[MIPS_INSN32_SIZE
];
1075 if (mips_pc_is_mips16 (addr
))
1077 instlen
= MIPS_INSN16_SIZE
;
1078 addr
= unmake_mips16_addr (addr
);
1081 instlen
= MIPS_INSN32_SIZE
;
1082 status
= target_read_memory (addr
, buf
, instlen
);
1084 memory_error (status
, addr
);
1085 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1088 /* These are the fields of 32 bit mips instructions. */
1089 #define mips32_op(x) (x >> 26)
1090 #define itype_op(x) (x >> 26)
1091 #define itype_rs(x) ((x >> 21) & 0x1f)
1092 #define itype_rt(x) ((x >> 16) & 0x1f)
1093 #define itype_immediate(x) (x & 0xffff)
1095 #define jtype_op(x) (x >> 26)
1096 #define jtype_target(x) (x & 0x03ffffff)
1098 #define rtype_op(x) (x >> 26)
1099 #define rtype_rs(x) ((x >> 21) & 0x1f)
1100 #define rtype_rt(x) ((x >> 16) & 0x1f)
1101 #define rtype_rd(x) ((x >> 11) & 0x1f)
1102 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1103 #define rtype_funct(x) (x & 0x3f)
1106 mips32_relative_offset (ULONGEST inst
)
1108 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1111 /* Determine where to set a single step breakpoint while considering
1112 branch prediction. */
1114 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1116 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1119 inst
= mips_fetch_instruction (gdbarch
, pc
);
1120 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1123 if (itype_op (inst
) >> 2 == 5)
1124 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1126 op
= (itype_op (inst
) & 0x03);
1136 goto greater_branch
;
1141 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1142 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1144 int tf
= itype_rt (inst
) & 0x01;
1145 int cnum
= itype_rt (inst
) >> 2;
1147 get_frame_register_signed (frame
,
1148 mips_regnum (get_frame_arch (frame
))->
1150 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1152 if (((cond
>> cnum
) & 0x01) == tf
)
1153 pc
+= mips32_relative_offset (inst
) + 4;
1158 pc
+= 4; /* Not a branch, next instruction is easy. */
1161 { /* This gets way messy. */
1163 /* Further subdivide into SPECIAL, REGIMM and other. */
1164 switch (op
= itype_op (inst
) & 0x07) /* Extract bits 28,27,26. */
1166 case 0: /* SPECIAL */
1167 op
= rtype_funct (inst
);
1172 /* Set PC to that address. */
1173 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1175 case 12: /* SYSCALL */
1177 struct gdbarch_tdep
*tdep
;
1179 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1180 if (tdep
->syscall_next_pc
!= NULL
)
1181 pc
= tdep
->syscall_next_pc (frame
);
1190 break; /* end SPECIAL */
1191 case 1: /* REGIMM */
1193 op
= itype_rt (inst
); /* branch condition */
1198 case 16: /* BLTZAL */
1199 case 18: /* BLTZALL */
1201 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1202 pc
+= mips32_relative_offset (inst
) + 4;
1204 pc
+= 8; /* after the delay slot */
1208 case 17: /* BGEZAL */
1209 case 19: /* BGEZALL */
1210 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1211 pc
+= mips32_relative_offset (inst
) + 4;
1213 pc
+= 8; /* after the delay slot */
1215 /* All of the other instructions in the REGIMM category */
1220 break; /* end REGIMM */
1225 reg
= jtype_target (inst
) << 2;
1226 /* Upper four bits get never changed... */
1227 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1230 /* FIXME case JALX : */
1233 reg
= jtype_target (inst
) << 2;
1234 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1235 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1237 break; /* The new PC will be alternate mode */
1238 case 4: /* BEQ, BEQL */
1240 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1241 get_frame_register_signed (frame
, itype_rt (inst
)))
1242 pc
+= mips32_relative_offset (inst
) + 4;
1246 case 5: /* BNE, BNEL */
1248 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1249 get_frame_register_signed (frame
, itype_rt (inst
)))
1250 pc
+= mips32_relative_offset (inst
) + 4;
1254 case 6: /* BLEZ, BLEZL */
1255 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1256 pc
+= mips32_relative_offset (inst
) + 4;
1262 greater_branch
: /* BGTZ, BGTZL */
1263 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1264 pc
+= mips32_relative_offset (inst
) + 4;
1271 } /* mips32_next_pc */
1273 /* Decoding the next place to set a breakpoint is irregular for the
1274 mips 16 variant, but fortunately, there fewer instructions. We have
1275 to cope ith extensions for 16 bit instructions and a pair of actual
1276 32 bit instructions. We dont want to set a single step instruction
1277 on the extend instruction either. */
1279 /* Lots of mips16 instruction formats */
1280 /* Predicting jumps requires itype,ritype,i8type
1281 and their extensions extItype,extritype,extI8type. */
1282 enum mips16_inst_fmts
1284 itype
, /* 0 immediate 5,10 */
1285 ritype
, /* 1 5,3,8 */
1286 rrtype
, /* 2 5,3,3,5 */
1287 rritype
, /* 3 5,3,3,5 */
1288 rrrtype
, /* 4 5,3,3,3,2 */
1289 rriatype
, /* 5 5,3,3,1,4 */
1290 shifttype
, /* 6 5,3,3,3,2 */
1291 i8type
, /* 7 5,3,8 */
1292 i8movtype
, /* 8 5,3,3,5 */
1293 i8mov32rtype
, /* 9 5,3,5,3 */
1294 i64type
, /* 10 5,3,8 */
1295 ri64type
, /* 11 5,3,3,5 */
1296 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1297 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1298 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1299 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1300 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1301 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1302 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1303 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1304 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1305 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1307 /* I am heaping all the fields of the formats into one structure and
1308 then, only the fields which are involved in instruction extension. */
1312 unsigned int regx
; /* Function in i8 type. */
1317 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1318 for the bits which make up the immediate extension. */
1321 extended_offset (unsigned int extension
)
1325 value
= (extension
>> 21) & 0x3f; /* Extract 15:11. */
1327 value
|= (extension
>> 16) & 0x1f; /* Extract 10:5. */
1329 value
|= extension
& 0x1f; /* Extract 4:0. */
1334 /* Only call this function if you know that this is an extendable
1335 instruction. It won't malfunction, but why make excess remote memory
1336 references? If the immediate operands get sign extended or something,
1337 do it after the extension is performed. */
1338 /* FIXME: Every one of these cases needs to worry about sign extension
1339 when the offset is to be used in relative addressing. */
1342 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1344 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1346 pc
&= 0xfffffffe; /* Clear the low order bit. */
1347 target_read_memory (pc
, buf
, 2);
1348 return extract_unsigned_integer (buf
, 2, byte_order
);
1352 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1353 unsigned int extension
,
1355 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1360 switch (insn_format
)
1367 value
= extended_offset (extension
);
1368 value
= value
<< 11; /* rom for the original value */
1369 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1373 value
= inst
& 0x7ff;
1374 /* FIXME : Consider sign extension. */
1383 { /* A register identifier and an offset. */
1384 /* Most of the fields are the same as I type but the
1385 immediate value is of a different length. */
1389 value
= extended_offset (extension
);
1390 value
= value
<< 8; /* from the original instruction */
1391 value
|= inst
& 0xff; /* eleven bits from instruction */
1392 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1393 if (value
& 0x4000) /* Test the sign bit, bit 26. */
1395 value
&= ~0x3fff; /* Remove the sign bit. */
1401 value
= inst
& 0xff; /* 8 bits */
1402 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1403 /* FIXME: Do sign extension, this format needs it. */
1404 if (value
& 0x80) /* THIS CONFUSES ME. */
1406 value
&= 0xef; /* Remove the sign bit. */
1416 unsigned long value
;
1417 unsigned int nexthalf
;
1418 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1419 value
= value
<< 16;
1420 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit
1429 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1431 upk
->offset
= offset
;
1438 add_offset_16 (CORE_ADDR pc
, int offset
)
1440 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1444 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1445 unsigned int extension
, unsigned int insn
)
1447 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1448 int op
= (insn
>> 11);
1451 case 2: /* Branch */
1454 struct upk_mips16 upk
;
1455 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1456 offset
= upk
.offset
;
1462 pc
+= (offset
<< 1) + 2;
1465 case 3: /* JAL , JALX - Watch out, these are 32 bit
1468 struct upk_mips16 upk
;
1469 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1470 pc
= add_offset_16 (pc
, upk
.offset
);
1471 if ((insn
>> 10) & 0x01) /* Exchange mode */
1472 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
1479 struct upk_mips16 upk
;
1481 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1482 reg
= get_frame_register_signed (frame
, upk
.regx
);
1484 pc
+= (upk
.offset
<< 1) + 2;
1491 struct upk_mips16 upk
;
1493 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1494 reg
= get_frame_register_signed (frame
, upk
.regx
);
1496 pc
+= (upk
.offset
<< 1) + 2;
1501 case 12: /* I8 Formats btez btnez */
1503 struct upk_mips16 upk
;
1505 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1506 /* upk.regx contains the opcode */
1507 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1508 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1509 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1510 /* pc = add_offset_16(pc,upk.offset) ; */
1511 pc
+= (upk
.offset
<< 1) + 2;
1516 case 29: /* RR Formats JR, JALR, JALR-RA */
1518 struct upk_mips16 upk
;
1519 /* upk.fmt = rrtype; */
1524 upk
.regx
= (insn
>> 8) & 0x07;
1525 upk
.regy
= (insn
>> 5) & 0x07;
1533 break; /* Function return instruction. */
1539 break; /* BOGUS Guess */
1541 pc
= get_frame_register_signed (frame
, reg
);
1548 /* This is an instruction extension. Fetch the real instruction
1549 (which follows the extension) and decode things based on
1553 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1554 fetch_mips_16 (gdbarch
, pc
));
1567 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1569 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1570 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1571 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1574 /* The mips_next_pc function supports single_step when the remote
1575 target monitor or stub is not developed enough to do a single_step.
1576 It works by decoding the current instruction and predicting where a
1577 branch will go. This isnt hard because all the data is available.
1578 The MIPS32 and MIPS16 variants are quite different. */
1580 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1582 if (is_mips16_addr (pc
))
1583 return mips16_next_pc (frame
, pc
);
1585 return mips32_next_pc (frame
, pc
);
1588 struct mips_frame_cache
1591 struct trad_frame_saved_reg
*saved_regs
;
1594 /* Set a register's saved stack address in temp_saved_regs. If an
1595 address has already been set for this register, do nothing; this
1596 way we will only recognize the first save of a given register in a
1599 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1600 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1601 Strictly speaking, only the second range is used as it is only second
1602 range (the ABI instead of ISA registers) that comes into play when finding
1603 saved registers in a frame. */
1606 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1607 int regnum
, CORE_ADDR offset
)
1609 if (this_cache
!= NULL
1610 && this_cache
->saved_regs
[regnum
].addr
== -1)
1612 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1614 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1620 /* Fetch the immediate value from a MIPS16 instruction.
1621 If the previous instruction was an EXTEND, use it to extend
1622 the upper bits of the immediate value. This is a helper function
1623 for mips16_scan_prologue. */
1626 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1627 unsigned short inst
, /* current instruction */
1628 int nbits
, /* number of bits in imm field */
1629 int scale
, /* scale factor to be applied to imm */
1630 int is_signed
) /* is the imm field signed? */
1634 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1636 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1637 if (offset
& 0x8000) /* check for negative extend */
1638 offset
= 0 - (0x10000 - (offset
& 0xffff));
1639 return offset
| (inst
& 0x1f);
1643 int max_imm
= 1 << nbits
;
1644 int mask
= max_imm
- 1;
1645 int sign_bit
= max_imm
>> 1;
1647 offset
= inst
& mask
;
1648 if (is_signed
&& (offset
& sign_bit
))
1649 offset
= 0 - (max_imm
- offset
);
1650 return offset
* scale
;
1655 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1656 the associated FRAME_CACHE if not null.
1657 Return the address of the first instruction past the prologue. */
1660 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1661 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1662 struct frame_info
*this_frame
,
1663 struct mips_frame_cache
*this_cache
)
1666 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
1668 long frame_offset
= 0; /* Size of stack frame. */
1669 long frame_adjust
= 0; /* Offset of FP from SP. */
1670 int frame_reg
= MIPS_SP_REGNUM
;
1671 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
1672 unsigned inst
= 0; /* current instruction */
1673 unsigned entry_inst
= 0; /* the entry instruction */
1674 unsigned save_inst
= 0; /* the save instruction */
1677 int extend_bytes
= 0;
1678 int prev_extend_bytes
;
1679 CORE_ADDR end_prologue_addr
= 0;
1681 /* Can be called when there's no process, and hence when there's no
1683 if (this_frame
!= NULL
)
1684 sp
= get_frame_register_signed (this_frame
,
1685 gdbarch_num_regs (gdbarch
)
1690 if (limit_pc
> start_pc
+ 200)
1691 limit_pc
= start_pc
+ 200;
1693 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1695 /* Save the previous instruction. If it's an EXTEND, we'll extract
1696 the immediate offset extension from it in mips16_get_imm. */
1699 /* Fetch and decode the instruction. */
1700 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1702 /* Normally we ignore extend instructions. However, if it is
1703 not followed by a valid prologue instruction, then this
1704 instruction is not part of the prologue either. We must
1705 remember in this case to adjust the end_prologue_addr back
1707 if ((inst
& 0xf800) == 0xf000) /* extend */
1709 extend_bytes
= MIPS_INSN16_SIZE
;
1713 prev_extend_bytes
= extend_bytes
;
1716 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1717 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1719 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1720 if (offset
< 0) /* Negative stack adjustment? */
1721 frame_offset
-= offset
;
1723 /* Exit loop if a positive stack adjustment is found, which
1724 usually means that the stack cleanup code in the function
1725 epilogue is reached. */
1728 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1730 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1731 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1732 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1734 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1736 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1737 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1738 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1740 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1742 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1743 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1745 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1747 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1748 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1750 else if (inst
== 0x673d) /* move $s1, $sp */
1755 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1757 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1758 frame_addr
= sp
+ offset
;
1760 frame_adjust
= offset
;
1762 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1764 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1765 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1766 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1768 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1770 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1771 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1772 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1774 else if ((inst
& 0xf81f) == 0xe809
1775 && (inst
& 0x700) != 0x700) /* entry */
1776 entry_inst
= inst
; /* Save for later processing. */
1777 else if ((inst
& 0xff80) == 0x6480) /* save */
1779 save_inst
= inst
; /* Save for later processing. */
1780 if (prev_extend_bytes
) /* extend */
1781 save_inst
|= prev_inst
<< 16;
1783 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1784 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1785 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1787 /* This instruction is part of the prologue, but we don't
1788 need to do anything special to handle it. */
1792 /* This instruction is not an instruction typically found
1793 in a prologue, so we must have reached the end of the
1795 if (end_prologue_addr
== 0)
1796 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1800 /* The entry instruction is typically the first instruction in a function,
1801 and it stores registers at offsets relative to the value of the old SP
1802 (before the prologue). But the value of the sp parameter to this
1803 function is the new SP (after the prologue has been executed). So we
1804 can't calculate those offsets until we've seen the entire prologue,
1805 and can calculate what the old SP must have been. */
1806 if (entry_inst
!= 0)
1808 int areg_count
= (entry_inst
>> 8) & 7;
1809 int sreg_count
= (entry_inst
>> 6) & 3;
1811 /* The entry instruction always subtracts 32 from the SP. */
1814 /* Now we can calculate what the SP must have been at the
1815 start of the function prologue. */
1818 /* Check if a0-a3 were saved in the caller's argument save area. */
1819 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1821 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1822 offset
+= mips_abi_regsize (gdbarch
);
1825 /* Check if the ra register was pushed on the stack. */
1827 if (entry_inst
& 0x20)
1829 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1830 offset
-= mips_abi_regsize (gdbarch
);
1833 /* Check if the s0 and s1 registers were pushed on the stack. */
1834 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1836 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1837 offset
-= mips_abi_regsize (gdbarch
);
1841 /* The SAVE instruction is similar to ENTRY, except that defined by the
1842 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1843 size of the frame is specified as an immediate field of instruction
1844 and an extended variation exists which lets additional registers and
1845 frame space to be specified. The instruction always treats registers
1846 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1847 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1849 static int args_table
[16] = {
1850 0, 0, 0, 0, 1, 1, 1, 1,
1851 2, 2, 2, 0, 3, 3, 4, -1,
1853 static int astatic_table
[16] = {
1854 0, 1, 2, 3, 0, 1, 2, 3,
1855 0, 1, 2, 4, 0, 1, 0, -1,
1857 int aregs
= (save_inst
>> 16) & 0xf;
1858 int xsregs
= (save_inst
>> 24) & 0x7;
1859 int args
= args_table
[aregs
];
1860 int astatic
= astatic_table
[aregs
];
1865 warning (_("Invalid number of argument registers encoded in SAVE."));
1870 warning (_("Invalid number of static registers encoded in SAVE."));
1874 /* For standard SAVE the frame size of 0 means 128. */
1875 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1876 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1879 frame_offset
+= frame_size
;
1881 /* Now we can calculate what the SP must have been at the
1882 start of the function prologue. */
1885 /* Check if A0-A3 were saved in the caller's argument save area. */
1886 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1888 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1889 offset
+= mips_abi_regsize (gdbarch
);
1894 /* Check if the RA register was pushed on the stack. */
1895 if (save_inst
& 0x40)
1897 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1898 offset
-= mips_abi_regsize (gdbarch
);
1901 /* Check if the S8 register was pushed on the stack. */
1904 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1905 offset
-= mips_abi_regsize (gdbarch
);
1908 /* Check if S2-S7 were pushed on the stack. */
1909 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1911 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1912 offset
-= mips_abi_regsize (gdbarch
);
1915 /* Check if the S1 register was pushed on the stack. */
1916 if (save_inst
& 0x10)
1918 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1919 offset
-= mips_abi_regsize (gdbarch
);
1921 /* Check if the S0 register was pushed on the stack. */
1922 if (save_inst
& 0x20)
1924 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1925 offset
-= mips_abi_regsize (gdbarch
);
1928 /* Check if A0-A3 were pushed on the stack. */
1929 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1931 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1932 offset
-= mips_abi_regsize (gdbarch
);
1936 if (this_cache
!= NULL
)
1939 (get_frame_register_signed (this_frame
,
1940 gdbarch_num_regs (gdbarch
) + frame_reg
)
1941 + frame_offset
- frame_adjust
);
1942 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1943 be able to get rid of the assignment below, evetually. But it's
1944 still needed for now. */
1945 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1946 + mips_regnum (gdbarch
)->pc
]
1947 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1950 /* If we didn't reach the end of the prologue when scanning the function
1951 instructions, then set end_prologue_addr to the address of the
1952 instruction immediately after the last one we scanned. */
1953 if (end_prologue_addr
== 0)
1954 end_prologue_addr
= cur_pc
;
1956 return end_prologue_addr
;
1959 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1960 Procedures that use the 32-bit instruction set are handled by the
1961 mips_insn32 unwinder. */
1963 static struct mips_frame_cache
*
1964 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1966 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1967 struct mips_frame_cache
*cache
;
1969 if ((*this_cache
) != NULL
)
1970 return (*this_cache
);
1971 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1972 (*this_cache
) = cache
;
1973 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1975 /* Analyze the function prologue. */
1977 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1978 CORE_ADDR start_addr
;
1980 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1981 if (start_addr
== 0)
1982 start_addr
= heuristic_proc_start (gdbarch
, pc
);
1983 /* We can't analyze the prologue if we couldn't find the begining
1985 if (start_addr
== 0)
1988 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
1991 /* gdbarch_sp_regnum contains the value and not the address. */
1992 trad_frame_set_value (cache
->saved_regs
,
1993 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
1996 return (*this_cache
);
2000 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2001 struct frame_id
*this_id
)
2003 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2005 /* This marks the outermost frame. */
2006 if (info
->base
== 0)
2008 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2011 static struct value
*
2012 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2013 void **this_cache
, int regnum
)
2015 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2017 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2021 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2022 struct frame_info
*this_frame
, void **this_cache
)
2024 CORE_ADDR pc
= get_frame_pc (this_frame
);
2025 if (mips_pc_is_mips16 (pc
))
2030 static const struct frame_unwind mips_insn16_frame_unwind
=
2033 default_frame_unwind_stop_reason
,
2034 mips_insn16_frame_this_id
,
2035 mips_insn16_frame_prev_register
,
2037 mips_insn16_frame_sniffer
2041 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2044 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2049 static const struct frame_base mips_insn16_frame_base
=
2051 &mips_insn16_frame_unwind
,
2052 mips_insn16_frame_base_address
,
2053 mips_insn16_frame_base_address
,
2054 mips_insn16_frame_base_address
2057 static const struct frame_base
*
2058 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2060 CORE_ADDR pc
= get_frame_pc (this_frame
);
2061 if (mips_pc_is_mips16 (pc
))
2062 return &mips_insn16_frame_base
;
2067 /* Mark all the registers as unset in the saved_regs array
2068 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2071 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
2073 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2077 const int num_regs
= gdbarch_num_regs (gdbarch
);
2080 for (i
= 0; i
< num_regs
; i
++)
2082 this_cache
->saved_regs
[i
].addr
= -1;
2087 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2088 the associated FRAME_CACHE if not null.
2089 Return the address of the first instruction past the prologue. */
2092 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2093 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2094 struct frame_info
*this_frame
,
2095 struct mips_frame_cache
*this_cache
)
2098 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
2102 int frame_reg
= MIPS_SP_REGNUM
;
2104 CORE_ADDR end_prologue_addr
= 0;
2105 int seen_sp_adjust
= 0;
2106 int load_immediate_bytes
= 0;
2107 int in_delay_slot
= 0;
2108 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2110 /* Can be called when there's no process, and hence when there's no
2112 if (this_frame
!= NULL
)
2113 sp
= get_frame_register_signed (this_frame
,
2114 gdbarch_num_regs (gdbarch
)
2119 if (limit_pc
> start_pc
+ 200)
2120 limit_pc
= start_pc
+ 200;
2125 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2127 unsigned long inst
, high_word
, low_word
;
2130 /* Fetch the instruction. */
2131 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2133 /* Save some code by pre-extracting some useful fields. */
2134 high_word
= (inst
>> 16) & 0xffff;
2135 low_word
= inst
& 0xffff;
2136 reg
= high_word
& 0x1f;
2138 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2139 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2140 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2142 if (low_word
& 0x8000) /* Negative stack adjustment? */
2143 frame_offset
+= 0x10000 - low_word
;
2145 /* Exit loop if a positive stack adjustment is found, which
2146 usually means that the stack cleanup code in the function
2147 epilogue is reached. */
2151 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2152 && !regsize_is_64_bits
)
2154 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2156 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2157 && regsize_is_64_bits
)
2159 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2160 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2162 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2164 /* Old gcc frame, r30 is virtual frame pointer. */
2165 if ((long) low_word
!= frame_offset
)
2166 frame_addr
= sp
+ low_word
;
2167 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2169 unsigned alloca_adjust
;
2172 frame_addr
= get_frame_register_signed
2173 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2175 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2176 if (alloca_adjust
> 0)
2178 /* FP > SP + frame_size. This may be because of
2179 an alloca or somethings similar. Fix sp to
2180 "pre-alloca" value, and try again. */
2181 sp
+= alloca_adjust
;
2182 /* Need to reset the status of all registers. Otherwise,
2183 we will hit a guard that prevents the new address
2184 for each register to be recomputed during the second
2186 reset_saved_regs (gdbarch
, this_cache
);
2191 /* move $30,$sp. With different versions of gas this will be either
2192 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2193 Accept any one of these. */
2194 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2196 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2197 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2199 unsigned alloca_adjust
;
2202 frame_addr
= get_frame_register_signed
2203 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2205 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2206 if (alloca_adjust
> 0)
2208 /* FP > SP + frame_size. This may be because of
2209 an alloca or somethings similar. Fix sp to
2210 "pre-alloca" value, and try again. */
2212 /* Need to reset the status of all registers. Otherwise,
2213 we will hit a guard that prevents the new address
2214 for each register to be recomputed during the second
2216 reset_saved_regs (gdbarch
, this_cache
);
2221 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2222 && !regsize_is_64_bits
)
2224 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2226 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2227 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2228 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2229 || high_word
== 0x3c1c /* lui $gp,n */
2230 || high_word
== 0x279c /* addiu $gp,$gp,n */
2231 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2232 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2235 /* These instructions are part of the prologue, but we don't
2236 need to do anything special to handle them. */
2238 /* The instructions below load $at or $t0 with an immediate
2239 value in preparation for a stack adjustment via
2240 subu $sp,$sp,[$at,$t0]. These instructions could also
2241 initialize a local variable, so we accept them only before
2242 a stack adjustment instruction was seen. */
2243 else if (!seen_sp_adjust
2244 && (high_word
== 0x3c01 /* lui $at,n */
2245 || high_word
== 0x3c08 /* lui $t0,n */
2246 || high_word
== 0x3421 /* ori $at,$at,n */
2247 || high_word
== 0x3508 /* ori $t0,$t0,n */
2248 || high_word
== 0x3401 /* ori $at,$zero,n */
2249 || high_word
== 0x3408 /* ori $t0,$zero,n */
2252 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2256 /* This instruction is not an instruction typically found
2257 in a prologue, so we must have reached the end of the
2259 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2260 loop now? Why would we need to continue scanning the function
2262 if (end_prologue_addr
== 0)
2263 end_prologue_addr
= cur_pc
;
2265 /* Check for branches and jumps. For now, only jump to
2266 register are caught (i.e. returns). */
2267 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2271 /* If the previous instruction was a jump, we must have reached
2272 the end of the prologue by now. Stop scanning so that we do
2273 not go past the function return. */
2278 if (this_cache
!= NULL
)
2281 (get_frame_register_signed (this_frame
,
2282 gdbarch_num_regs (gdbarch
) + frame_reg
)
2284 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2285 this assignment below, eventually. But it's still needed
2287 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2288 + mips_regnum (gdbarch
)->pc
]
2289 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2293 /* If we didn't reach the end of the prologue when scanning the function
2294 instructions, then set end_prologue_addr to the address of the
2295 instruction immediately after the last one we scanned. */
2296 /* brobecker/2004-10-10: I don't think this would ever happen, but
2297 we may as well be careful and do our best if we have a null
2298 end_prologue_addr. */
2299 if (end_prologue_addr
== 0)
2300 end_prologue_addr
= cur_pc
;
2302 /* In a frameless function, we might have incorrectly
2303 skipped some load immediate instructions. Undo the skipping
2304 if the load immediate was not followed by a stack adjustment. */
2305 if (load_immediate_bytes
&& !seen_sp_adjust
)
2306 end_prologue_addr
-= load_immediate_bytes
;
2308 return end_prologue_addr
;
2311 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2312 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2313 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2316 static struct mips_frame_cache
*
2317 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2319 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2320 struct mips_frame_cache
*cache
;
2322 if ((*this_cache
) != NULL
)
2323 return (*this_cache
);
2325 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2326 (*this_cache
) = cache
;
2327 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2329 /* Analyze the function prologue. */
2331 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2332 CORE_ADDR start_addr
;
2334 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2335 if (start_addr
== 0)
2336 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2337 /* We can't analyze the prologue if we couldn't find the begining
2339 if (start_addr
== 0)
2342 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2345 /* gdbarch_sp_regnum contains the value and not the address. */
2346 trad_frame_set_value (cache
->saved_regs
,
2347 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2350 return (*this_cache
);
2354 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2355 struct frame_id
*this_id
)
2357 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2359 /* This marks the outermost frame. */
2360 if (info
->base
== 0)
2362 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2365 static struct value
*
2366 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2367 void **this_cache
, int regnum
)
2369 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2371 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2375 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2376 struct frame_info
*this_frame
, void **this_cache
)
2378 CORE_ADDR pc
= get_frame_pc (this_frame
);
2379 if (! mips_pc_is_mips16 (pc
))
2384 static const struct frame_unwind mips_insn32_frame_unwind
=
2387 default_frame_unwind_stop_reason
,
2388 mips_insn32_frame_this_id
,
2389 mips_insn32_frame_prev_register
,
2391 mips_insn32_frame_sniffer
2395 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2398 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2403 static const struct frame_base mips_insn32_frame_base
=
2405 &mips_insn32_frame_unwind
,
2406 mips_insn32_frame_base_address
,
2407 mips_insn32_frame_base_address
,
2408 mips_insn32_frame_base_address
2411 static const struct frame_base
*
2412 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2414 CORE_ADDR pc
= get_frame_pc (this_frame
);
2415 if (! mips_pc_is_mips16 (pc
))
2416 return &mips_insn32_frame_base
;
2421 static struct trad_frame_cache
*
2422 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2425 CORE_ADDR start_addr
;
2426 CORE_ADDR stack_addr
;
2427 struct trad_frame_cache
*this_trad_cache
;
2428 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2429 int num_regs
= gdbarch_num_regs (gdbarch
);
2431 if ((*this_cache
) != NULL
)
2432 return (*this_cache
);
2433 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2434 (*this_cache
) = this_trad_cache
;
2436 /* The return address is in the link register. */
2437 trad_frame_set_reg_realreg (this_trad_cache
,
2438 gdbarch_pc_regnum (gdbarch
),
2439 num_regs
+ MIPS_RA_REGNUM
);
2441 /* Frame ID, since it's a frameless / stackless function, no stack
2442 space is allocated and SP on entry is the current SP. */
2443 pc
= get_frame_pc (this_frame
);
2444 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2445 stack_addr
= get_frame_register_signed (this_frame
,
2446 num_regs
+ MIPS_SP_REGNUM
);
2447 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2449 /* Assume that the frame's base is the same as the
2451 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2453 return this_trad_cache
;
2457 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2458 struct frame_id
*this_id
)
2460 struct trad_frame_cache
*this_trad_cache
2461 = mips_stub_frame_cache (this_frame
, this_cache
);
2462 trad_frame_get_id (this_trad_cache
, this_id
);
2465 static struct value
*
2466 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2467 void **this_cache
, int regnum
)
2469 struct trad_frame_cache
*this_trad_cache
2470 = mips_stub_frame_cache (this_frame
, this_cache
);
2471 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2475 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2476 struct frame_info
*this_frame
, void **this_cache
)
2479 struct obj_section
*s
;
2480 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2481 struct minimal_symbol
*msym
;
2483 /* Use the stub unwinder for unreadable code. */
2484 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2487 if (in_plt_section (pc
, NULL
))
2490 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2491 s
= find_pc_section (pc
);
2494 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2495 ".MIPS.stubs") == 0)
2498 /* Calling a PIC function from a non-PIC function passes through a
2499 stub. The stub for foo is named ".pic.foo". */
2500 msym
= lookup_minimal_symbol_by_pc (pc
);
2502 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2503 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2509 static const struct frame_unwind mips_stub_frame_unwind
=
2512 default_frame_unwind_stop_reason
,
2513 mips_stub_frame_this_id
,
2514 mips_stub_frame_prev_register
,
2516 mips_stub_frame_sniffer
2520 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2523 struct trad_frame_cache
*this_trad_cache
2524 = mips_stub_frame_cache (this_frame
, this_cache
);
2525 return trad_frame_get_this_base (this_trad_cache
);
2528 static const struct frame_base mips_stub_frame_base
=
2530 &mips_stub_frame_unwind
,
2531 mips_stub_frame_base_address
,
2532 mips_stub_frame_base_address
,
2533 mips_stub_frame_base_address
2536 static const struct frame_base
*
2537 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2539 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2540 return &mips_stub_frame_base
;
2545 /* mips_addr_bits_remove - remove useless address bits */
2548 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2550 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2552 if (is_mips16_addr (addr
))
2553 addr
= unmake_mips16_addr (addr
);
2555 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2556 /* This hack is a work-around for existing boards using PMON, the
2557 simulator, and any other 64-bit targets that doesn't have true
2558 64-bit addressing. On these targets, the upper 32 bits of
2559 addresses are ignored by the hardware. Thus, the PC or SP are
2560 likely to have been sign extended to all 1s by instruction
2561 sequences that load 32-bit addresses. For example, a typical
2562 piece of code that loads an address is this:
2564 lui $r2, <upper 16 bits>
2565 ori $r2, <lower 16 bits>
2567 But the lui sign-extends the value such that the upper 32 bits
2568 may be all 1s. The workaround is simply to mask off these
2569 bits. In the future, gcc may be changed to support true 64-bit
2570 addressing, and this masking will have to be disabled. */
2571 return addr
&= 0xffffffffUL
;
2576 /* Instructions used during single-stepping of atomic sequences. */
2577 #define LL_OPCODE 0x30
2578 #define LLD_OPCODE 0x34
2579 #define SC_OPCODE 0x38
2580 #define SCD_OPCODE 0x3c
2582 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2583 instruction and ending with a SC/SCD instruction. If such a sequence
2584 is found, attempt to step through it. A breakpoint is placed at the end of
2588 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2589 struct address_space
*aspace
, CORE_ADDR pc
)
2591 CORE_ADDR breaks
[2] = {-1, -1};
2593 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2597 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2598 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2603 insn
= mips_fetch_instruction (gdbarch
, loc
);
2604 /* Assume all atomic sequences start with a ll/lld instruction. */
2605 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2608 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2610 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2613 loc
+= MIPS_INSN32_SIZE
;
2614 insn
= mips_fetch_instruction (gdbarch
, loc
);
2616 /* Assume that there is at most one branch in the atomic
2617 sequence. If a branch is found, put a breakpoint in its
2618 destination address. */
2619 switch (itype_op (insn
))
2621 case 0: /* SPECIAL */
2622 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2623 return 0; /* fallback to the standard single-step code. */
2625 case 1: /* REGIMM */
2626 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2630 return 0; /* fallback to the standard single-step code. */
2637 case 22: /* BLEZL */
2638 case 23: /* BGTTL */
2644 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2649 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2650 if (last_breakpoint
>= 1)
2651 return 0; /* More than one branch found, fallback to the
2652 standard single-step code. */
2653 breaks
[1] = branch_bp
;
2657 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2661 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2662 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2665 loc
+= MIPS_INSN32_SIZE
;
2667 /* Insert a breakpoint right after the end of the atomic sequence. */
2670 /* Check for duplicated breakpoints. Check also for a breakpoint
2671 placed (branch instruction's destination) in the atomic sequence. */
2672 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2673 last_breakpoint
= 0;
2675 /* Effectively inserts the breakpoints. */
2676 for (index
= 0; index
<= last_breakpoint
; index
++)
2677 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2682 /* mips_software_single_step() is called just before we want to resume
2683 the inferior, if we want to single-step it but there is no hardware
2684 or kernel single-step support (MIPS on GNU/Linux for example). We find
2685 the target of the coming instruction and breakpoint it. */
2688 mips_software_single_step (struct frame_info
*frame
)
2690 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2691 struct address_space
*aspace
= get_frame_address_space (frame
);
2692 CORE_ADDR pc
, next_pc
;
2694 pc
= get_frame_pc (frame
);
2695 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2698 next_pc
= mips_next_pc (frame
, pc
);
2700 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2704 /* Test whether the PC points to the return instruction at the
2705 end of a function. */
2708 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2710 if (mips_pc_is_mips16 (pc
))
2711 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2712 generates a "jr $ra"; other times it generates code to load
2713 the return address from the stack to an accessible register (such
2714 as $a3), then a "jr" using that register. This second case
2715 is almost impossible to distinguish from an indirect jump
2716 used for switch statements, so we don't even try. */
2717 return mips_fetch_instruction (gdbarch
, pc
) == 0xe820; /* jr $ra */
2719 return mips_fetch_instruction (gdbarch
, pc
) == 0x3e00008; /* jr $ra */
2723 /* This fencepost looks highly suspicious to me. Removing it also
2724 seems suspicious as it could affect remote debugging across serial
2728 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2734 struct inferior
*inf
;
2736 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2738 fence
= start_pc
- heuristic_fence_post
;
2742 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2743 fence
= VM_MIN_ADDRESS
;
2745 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2747 inf
= current_inferior ();
2749 /* Search back for previous return. */
2750 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2751 if (start_pc
< fence
)
2753 /* It's not clear to me why we reach this point when
2754 stop_soon, but with this test, at least we
2755 don't print out warnings for every child forked (eg, on
2756 decstation). 22apr93 rich@cygnus.com. */
2757 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2759 static int blurb_printed
= 0;
2761 warning (_("GDB can't find the start of the function at %s."),
2762 paddress (gdbarch
, pc
));
2766 /* This actually happens frequently in embedded
2767 development, when you first connect to a board
2768 and your stack pointer and pc are nowhere in
2769 particular. This message needs to give people
2770 in that situation enough information to
2771 determine that it's no big deal. */
2772 printf_filtered ("\n\
2773 GDB is unable to find the start of the function at %s\n\
2774 and thus can't determine the size of that function's stack frame.\n\
2775 This means that GDB may be unable to access that stack frame, or\n\
2776 the frames below it.\n\
2777 This problem is most likely caused by an invalid program counter or\n\
2779 However, if you think GDB should simply search farther back\n\
2780 from %s for code which looks like the beginning of a\n\
2781 function, you can increase the range of the search using the `set\n\
2782 heuristic-fence-post' command.\n",
2783 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2790 else if (mips_pc_is_mips16 (start_pc
))
2792 unsigned short inst
;
2794 /* On MIPS16, any one of the following is likely to be the
2795 start of a function:
2801 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
2802 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2803 if ((inst
& 0xff80) == 0x6480) /* save */
2805 if (start_pc
- instlen
>= fence
)
2807 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2808 if ((inst
& 0xf800) == 0xf000) /* extend */
2809 start_pc
-= instlen
;
2813 else if (((inst
& 0xf81f) == 0xe809
2814 && (inst
& 0x700) != 0x700) /* entry */
2815 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2816 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2817 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2819 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2820 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2825 else if (mips_about_to_return (gdbarch
, start_pc
))
2827 /* Skip return and its delay slot. */
2828 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2835 struct mips_objfile_private
2841 /* According to the current ABI, should the type be passed in a
2842 floating-point register (assuming that there is space)? When there
2843 is no FPU, FP are not even considered as possible candidates for
2844 FP registers and, consequently this returns false - forces FP
2845 arguments into integer registers. */
2848 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2849 struct type
*arg_type
)
2851 return ((typecode
== TYPE_CODE_FLT
2852 || (MIPS_EABI (gdbarch
)
2853 && (typecode
== TYPE_CODE_STRUCT
2854 || typecode
== TYPE_CODE_UNION
)
2855 && TYPE_NFIELDS (arg_type
) == 1
2856 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2858 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2861 /* On o32, argument passing in GPRs depends on the alignment of the type being
2862 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2865 mips_type_needs_double_align (struct type
*type
)
2867 enum type_code typecode
= TYPE_CODE (type
);
2869 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2871 else if (typecode
== TYPE_CODE_STRUCT
)
2873 if (TYPE_NFIELDS (type
) < 1)
2875 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2877 else if (typecode
== TYPE_CODE_UNION
)
2881 n
= TYPE_NFIELDS (type
);
2882 for (i
= 0; i
< n
; i
++)
2883 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2890 /* Adjust the address downward (direction of stack growth) so that it
2891 is correctly aligned for a new stack frame. */
2893 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2895 return align_down (addr
, 16);
2899 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2900 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2901 int nargs
, struct value
**args
, CORE_ADDR sp
,
2902 int struct_return
, CORE_ADDR struct_addr
)
2908 int stack_offset
= 0;
2909 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2910 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2911 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2912 int regsize
= mips_abi_regsize (gdbarch
);
2914 /* For shared libraries, "t9" needs to point at the function
2916 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2918 /* Set the return address register to point to the entry point of
2919 the program, where a breakpoint lies in wait. */
2920 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2922 /* First ensure that the stack and structure return address (if any)
2923 are properly aligned. The stack has to be at least 64-bit
2924 aligned even on 32-bit machines, because doubles must be 64-bit
2925 aligned. For n32 and n64, stack frames need to be 128-bit
2926 aligned, so we round to this widest known alignment. */
2928 sp
= align_down (sp
, 16);
2929 struct_addr
= align_down (struct_addr
, 16);
2931 /* Now make space on the stack for the args. We allocate more
2932 than necessary for EABI, because the first few arguments are
2933 passed in registers, but that's OK. */
2934 for (argnum
= 0; argnum
< nargs
; argnum
++)
2935 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2936 sp
-= align_up (len
, 16);
2939 fprintf_unfiltered (gdb_stdlog
,
2940 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2941 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2943 /* Initialize the integer and float register pointers. */
2944 argreg
= MIPS_A0_REGNUM
;
2945 float_argreg
= mips_fpa0_regnum (gdbarch
);
2947 /* The struct_return pointer occupies the first parameter-passing reg. */
2951 fprintf_unfiltered (gdb_stdlog
,
2952 "mips_eabi_push_dummy_call: "
2953 "struct_return reg=%d %s\n",
2954 argreg
, paddress (gdbarch
, struct_addr
));
2955 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2958 /* Now load as many as possible of the first arguments into
2959 registers, and push the rest onto the stack. Loop thru args
2960 from first to last. */
2961 for (argnum
= 0; argnum
< nargs
; argnum
++)
2963 const gdb_byte
*val
;
2964 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2965 struct value
*arg
= args
[argnum
];
2966 struct type
*arg_type
= check_typedef (value_type (arg
));
2967 int len
= TYPE_LENGTH (arg_type
);
2968 enum type_code typecode
= TYPE_CODE (arg_type
);
2971 fprintf_unfiltered (gdb_stdlog
,
2972 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2973 argnum
+ 1, len
, (int) typecode
);
2975 /* Function pointer arguments to mips16 code need to be made into
2977 if (typecode
== TYPE_CODE_PTR
2978 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
2980 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
2982 if (mips_pc_is_mips16 (addr
))
2984 store_signed_integer (valbuf
, len
, byte_order
,
2985 make_mips16_addr (addr
));
2989 val
= value_contents (arg
);
2991 /* The EABI passes structures that do not fit in a register by
2993 else if (len
> regsize
2994 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2996 store_unsigned_integer (valbuf
, regsize
, byte_order
,
2997 value_address (arg
));
2998 typecode
= TYPE_CODE_PTR
;
3002 fprintf_unfiltered (gdb_stdlog
, " push");
3005 val
= value_contents (arg
);
3007 /* 32-bit ABIs always start floating point arguments in an
3008 even-numbered floating point register. Round the FP register
3009 up before the check to see if there are any FP registers
3010 left. Non MIPS_EABI targets also pass the FP in the integer
3011 registers so also round up normal registers. */
3012 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3014 if ((float_argreg
& 1))
3018 /* Floating point arguments passed in registers have to be
3019 treated specially. On 32-bit architectures, doubles
3020 are passed in register pairs; the even register gets
3021 the low word, and the odd register gets the high word.
3022 On non-EABI processors, the first two floating point arguments are
3023 also copied to general registers, because MIPS16 functions
3024 don't use float registers for arguments. This duplication of
3025 arguments in general registers can't hurt non-MIPS16 functions
3026 because those registers are normally skipped. */
3027 /* MIPS_EABI squeezes a struct that contains a single floating
3028 point value into an FP register instead of pushing it onto the
3030 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3031 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3033 /* EABI32 will pass doubles in consecutive registers, even on
3034 64-bit cores. At one time, we used to check the size of
3035 `float_argreg' to determine whether or not to pass doubles
3036 in consecutive registers, but this is not sufficient for
3037 making the ABI determination. */
3038 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
3040 int low_offset
= gdbarch_byte_order (gdbarch
)
3041 == BFD_ENDIAN_BIG
? 4 : 0;
3044 /* Write the low word of the double to the even register(s). */
3045 regval
= extract_signed_integer (val
+ low_offset
,
3048 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3049 float_argreg
, phex (regval
, 4));
3050 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3052 /* Write the high word of the double to the odd register(s). */
3053 regval
= extract_signed_integer (val
+ 4 - low_offset
,
3056 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3057 float_argreg
, phex (regval
, 4));
3058 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3062 /* This is a floating point value that fits entirely
3063 in a single register. */
3064 /* On 32 bit ABI's the float_argreg is further adjusted
3065 above to ensure that it is even register aligned. */
3066 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
3068 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3069 float_argreg
, phex (regval
, len
));
3070 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3075 /* Copy the argument to general registers or the stack in
3076 register-sized pieces. Large arguments are split between
3077 registers and stack. */
3078 /* Note: structs whose size is not a multiple of regsize
3079 are treated specially: Irix cc passes
3080 them in registers where gcc sometimes puts them on the
3081 stack. For maximum compatibility, we will put them in
3083 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3085 /* Note: Floating-point values that didn't fit into an FP
3086 register are only written to memory. */
3089 /* Remember if the argument was written to the stack. */
3090 int stack_used_p
= 0;
3091 int partial_len
= (len
< regsize
? len
: regsize
);
3094 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3097 /* Write this portion of the argument to the stack. */
3098 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3100 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3102 /* Should shorter than int integer values be
3103 promoted to int before being stored? */
3104 int longword_offset
= 0;
3107 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3110 && (typecode
== TYPE_CODE_INT
3111 || typecode
== TYPE_CODE_PTR
3112 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3113 longword_offset
= regsize
- len
;
3114 else if ((typecode
== TYPE_CODE_STRUCT
3115 || typecode
== TYPE_CODE_UNION
)
3116 && TYPE_LENGTH (arg_type
) < regsize
)
3117 longword_offset
= regsize
- len
;
3122 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3123 paddress (gdbarch
, stack_offset
));
3124 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3125 paddress (gdbarch
, longword_offset
));
3128 addr
= sp
+ stack_offset
+ longword_offset
;
3133 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3134 paddress (gdbarch
, addr
));
3135 for (i
= 0; i
< partial_len
; i
++)
3137 fprintf_unfiltered (gdb_stdlog
, "%02x",
3141 write_memory (addr
, val
, partial_len
);
3144 /* Note!!! This is NOT an else clause. Odd sized
3145 structs may go thru BOTH paths. Floating point
3146 arguments will not. */
3147 /* Write this portion of the argument to a general
3148 purpose register. */
3149 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3150 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3153 extract_signed_integer (val
, partial_len
, byte_order
);
3156 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3158 phex (regval
, regsize
));
3159 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3166 /* Compute the offset into the stack at which we will
3167 copy the next parameter.
3169 In the new EABI (and the NABI32), the stack_offset
3170 only needs to be adjusted when it has been used. */
3173 stack_offset
+= align_up (partial_len
, regsize
);
3177 fprintf_unfiltered (gdb_stdlog
, "\n");
3180 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3182 /* Return adjusted stack pointer. */
3186 /* Determine the return value convention being used. */
3188 static enum return_value_convention
3189 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3190 struct type
*type
, struct regcache
*regcache
,
3191 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3193 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3194 int fp_return_type
= 0;
3195 int offset
, regnum
, xfer
;
3197 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3198 return RETURN_VALUE_STRUCT_CONVENTION
;
3200 /* Floating point type? */
3201 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3203 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3205 /* Structs with a single field of float type
3206 are returned in a floating point register. */
3207 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3208 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3209 && TYPE_NFIELDS (type
) == 1)
3211 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3213 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3220 /* A floating-point value belongs in the least significant part
3223 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3224 regnum
= mips_regnum (gdbarch
)->fp0
;
3228 /* An integer value goes in V0/V1. */
3230 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3231 regnum
= MIPS_V0_REGNUM
;
3234 offset
< TYPE_LENGTH (type
);
3235 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3237 xfer
= mips_abi_regsize (gdbarch
);
3238 if (offset
+ xfer
> TYPE_LENGTH (type
))
3239 xfer
= TYPE_LENGTH (type
) - offset
;
3240 mips_xfer_register (gdbarch
, regcache
,
3241 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3242 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3246 return RETURN_VALUE_REGISTER_CONVENTION
;
3250 /* N32/N64 ABI stuff. */
3252 /* Search for a naturally aligned double at OFFSET inside a struct
3253 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3257 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3262 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3265 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3268 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3271 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3274 struct type
*field_type
;
3276 /* We're only looking at normal fields. */
3277 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3278 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3281 /* If we have gone past the offset, there is no double to pass. */
3282 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3286 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3288 /* If this field is entirely before the requested offset, go
3289 on to the next one. */
3290 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3293 /* If this is our special aligned double, we can stop. */
3294 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3295 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3298 /* This field starts at or before the requested offset, and
3299 overlaps it. If it is a structure, recurse inwards. */
3300 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3307 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3308 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3309 int nargs
, struct value
**args
, CORE_ADDR sp
,
3310 int struct_return
, CORE_ADDR struct_addr
)
3316 int stack_offset
= 0;
3317 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3318 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3319 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3321 /* For shared libraries, "t9" needs to point at the function
3323 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3325 /* Set the return address register to point to the entry point of
3326 the program, where a breakpoint lies in wait. */
3327 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3329 /* First ensure that the stack and structure return address (if any)
3330 are properly aligned. The stack has to be at least 64-bit
3331 aligned even on 32-bit machines, because doubles must be 64-bit
3332 aligned. For n32 and n64, stack frames need to be 128-bit
3333 aligned, so we round to this widest known alignment. */
3335 sp
= align_down (sp
, 16);
3336 struct_addr
= align_down (struct_addr
, 16);
3338 /* Now make space on the stack for the args. */
3339 for (argnum
= 0; argnum
< nargs
; argnum
++)
3340 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3341 sp
-= align_up (len
, 16);
3344 fprintf_unfiltered (gdb_stdlog
,
3345 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3346 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3348 /* Initialize the integer and float register pointers. */
3349 argreg
= MIPS_A0_REGNUM
;
3350 float_argreg
= mips_fpa0_regnum (gdbarch
);
3352 /* The struct_return pointer occupies the first parameter-passing reg. */
3356 fprintf_unfiltered (gdb_stdlog
,
3357 "mips_n32n64_push_dummy_call: "
3358 "struct_return reg=%d %s\n",
3359 argreg
, paddress (gdbarch
, struct_addr
));
3360 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3363 /* Now load as many as possible of the first arguments into
3364 registers, and push the rest onto the stack. Loop thru args
3365 from first to last. */
3366 for (argnum
= 0; argnum
< nargs
; argnum
++)
3368 const gdb_byte
*val
;
3369 struct value
*arg
= args
[argnum
];
3370 struct type
*arg_type
= check_typedef (value_type (arg
));
3371 int len
= TYPE_LENGTH (arg_type
);
3372 enum type_code typecode
= TYPE_CODE (arg_type
);
3375 fprintf_unfiltered (gdb_stdlog
,
3376 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3377 argnum
+ 1, len
, (int) typecode
);
3379 val
= value_contents (arg
);
3381 /* A 128-bit long double value requires an even-odd pair of
3382 floating-point registers. */
3384 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3385 && (float_argreg
& 1))
3391 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3392 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3394 /* This is a floating point value that fits entirely
3395 in a single register or a pair of registers. */
3396 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3397 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3399 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3400 float_argreg
, phex (regval
, reglen
));
3401 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3404 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3405 argreg
, phex (regval
, reglen
));
3406 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3411 regval
= extract_unsigned_integer (val
+ reglen
,
3412 reglen
, byte_order
);
3414 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3415 float_argreg
, phex (regval
, reglen
));
3416 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3419 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3420 argreg
, phex (regval
, reglen
));
3421 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3428 /* Copy the argument to general registers or the stack in
3429 register-sized pieces. Large arguments are split between
3430 registers and stack. */
3431 /* For N32/N64, structs, unions, or other composite types are
3432 treated as a sequence of doublewords, and are passed in integer
3433 or floating point registers as though they were simple scalar
3434 parameters to the extent that they fit, with any excess on the
3435 stack packed according to the normal memory layout of the
3437 The caller does not reserve space for the register arguments;
3438 the callee is responsible for reserving it if required. */
3439 /* Note: Floating-point values that didn't fit into an FP
3440 register are only written to memory. */
3443 /* Remember if the argument was written to the stack. */
3444 int stack_used_p
= 0;
3445 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3448 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3451 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3452 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3454 /* Write this portion of the argument to the stack. */
3455 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3457 /* Should shorter than int integer values be
3458 promoted to int before being stored? */
3459 int longword_offset
= 0;
3462 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3464 if ((typecode
== TYPE_CODE_INT
3465 || typecode
== TYPE_CODE_PTR
)
3467 longword_offset
= MIPS64_REGSIZE
- len
;
3472 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3473 paddress (gdbarch
, stack_offset
));
3474 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3475 paddress (gdbarch
, longword_offset
));
3478 addr
= sp
+ stack_offset
+ longword_offset
;
3483 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3484 paddress (gdbarch
, addr
));
3485 for (i
= 0; i
< partial_len
; i
++)
3487 fprintf_unfiltered (gdb_stdlog
, "%02x",
3491 write_memory (addr
, val
, partial_len
);
3494 /* Note!!! This is NOT an else clause. Odd sized
3495 structs may go thru BOTH paths. */
3496 /* Write this portion of the argument to a general
3497 purpose register. */
3498 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3502 /* Sign extend pointers, 32-bit integers and signed
3503 16-bit and 8-bit integers; everything else is taken
3506 if ((partial_len
== 4
3507 && (typecode
== TYPE_CODE_PTR
3508 || typecode
== TYPE_CODE_INT
))
3510 && typecode
== TYPE_CODE_INT
3511 && !TYPE_UNSIGNED (arg_type
)))
3512 regval
= extract_signed_integer (val
, partial_len
,
3515 regval
= extract_unsigned_integer (val
, partial_len
,
3518 /* A non-floating-point argument being passed in a
3519 general register. If a struct or union, and if
3520 the remaining length is smaller than the register
3521 size, we have to adjust the register value on
3524 It does not seem to be necessary to do the
3525 same for integral types. */
3527 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3528 && partial_len
< MIPS64_REGSIZE
3529 && (typecode
== TYPE_CODE_STRUCT
3530 || typecode
== TYPE_CODE_UNION
))
3531 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3535 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3537 phex (regval
, MIPS64_REGSIZE
));
3538 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3540 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3541 TYPE_LENGTH (arg_type
) - len
))
3544 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3546 phex (regval
, MIPS64_REGSIZE
));
3547 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3558 /* Compute the offset into the stack at which we will
3559 copy the next parameter.
3561 In N32 (N64?), the stack_offset only needs to be
3562 adjusted when it has been used. */
3565 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3569 fprintf_unfiltered (gdb_stdlog
, "\n");
3572 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3574 /* Return adjusted stack pointer. */
3578 static enum return_value_convention
3579 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3580 struct type
*type
, struct regcache
*regcache
,
3581 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3583 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3585 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3587 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3588 if needed), as appropriate for the type. Composite results (struct,
3589 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3592 * A struct with only one or two floating point fields is returned in $f0
3593 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3596 * Any other composite results of at most 128 bits are returned in
3597 $2 (first 64 bits) and $3 (remainder, if necessary).
3599 * Larger composite results are handled by converting the function to a
3600 procedure with an implicit first parameter, which is a pointer to an area
3601 reserved by the caller to receive the result. [The o32-bit ABI requires
3602 that all composite results be handled by conversion to implicit first
3603 parameters. The MIPS/SGI Fortran implementation has always made a
3604 specific exception to return COMPLEX results in the floating point
3607 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3608 return RETURN_VALUE_STRUCT_CONVENTION
;
3609 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3610 && TYPE_LENGTH (type
) == 16
3611 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3613 /* A 128-bit floating-point value fills both $f0 and $f2. The
3614 two registers are used in the same as memory order, so the
3615 eight bytes with the lower memory address are in $f0. */
3617 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3618 mips_xfer_register (gdbarch
, regcache
,
3619 gdbarch_num_regs (gdbarch
)
3620 + mips_regnum (gdbarch
)->fp0
,
3621 8, gdbarch_byte_order (gdbarch
),
3622 readbuf
, writebuf
, 0);
3623 mips_xfer_register (gdbarch
, regcache
,
3624 gdbarch_num_regs (gdbarch
)
3625 + mips_regnum (gdbarch
)->fp0
+ 2,
3626 8, gdbarch_byte_order (gdbarch
),
3627 readbuf
? readbuf
+ 8 : readbuf
,
3628 writebuf
? writebuf
+ 8 : writebuf
, 0);
3629 return RETURN_VALUE_REGISTER_CONVENTION
;
3631 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3632 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3634 /* A single or double floating-point value that fits in FP0. */
3636 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3637 mips_xfer_register (gdbarch
, regcache
,
3638 gdbarch_num_regs (gdbarch
)
3639 + mips_regnum (gdbarch
)->fp0
,
3641 gdbarch_byte_order (gdbarch
),
3642 readbuf
, writebuf
, 0);
3643 return RETURN_VALUE_REGISTER_CONVENTION
;
3645 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3646 && TYPE_NFIELDS (type
) <= 2
3647 && TYPE_NFIELDS (type
) >= 1
3648 && ((TYPE_NFIELDS (type
) == 1
3649 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3651 || (TYPE_NFIELDS (type
) == 2
3652 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3654 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3655 == TYPE_CODE_FLT
))))
3657 /* A struct that contains one or two floats. Each value is part
3658 in the least significant part of their floating point
3659 register (or GPR, for soft float). */
3662 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3663 ? mips_regnum (gdbarch
)->fp0
3665 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3667 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3670 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3672 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3674 /* A 16-byte long double field goes in two consecutive
3676 mips_xfer_register (gdbarch
, regcache
,
3677 gdbarch_num_regs (gdbarch
) + regnum
,
3679 gdbarch_byte_order (gdbarch
),
3680 readbuf
, writebuf
, offset
);
3681 mips_xfer_register (gdbarch
, regcache
,
3682 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3684 gdbarch_byte_order (gdbarch
),
3685 readbuf
, writebuf
, offset
+ 8);
3688 mips_xfer_register (gdbarch
, regcache
,
3689 gdbarch_num_regs (gdbarch
) + regnum
,
3690 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3691 gdbarch_byte_order (gdbarch
),
3692 readbuf
, writebuf
, offset
);
3694 return RETURN_VALUE_REGISTER_CONVENTION
;
3696 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3697 || TYPE_CODE (type
) == TYPE_CODE_UNION
3698 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3700 /* A composite type. Extract the left justified value,
3701 regardless of the byte order. I.e. DO NOT USE
3705 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3706 offset
< TYPE_LENGTH (type
);
3707 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3709 int xfer
= register_size (gdbarch
, regnum
);
3710 if (offset
+ xfer
> TYPE_LENGTH (type
))
3711 xfer
= TYPE_LENGTH (type
) - offset
;
3713 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3714 offset
, xfer
, regnum
);
3715 mips_xfer_register (gdbarch
, regcache
,
3716 gdbarch_num_regs (gdbarch
) + regnum
,
3717 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3720 return RETURN_VALUE_REGISTER_CONVENTION
;
3724 /* A scalar extract each part but least-significant-byte
3728 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3729 offset
< TYPE_LENGTH (type
);
3730 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3732 int xfer
= register_size (gdbarch
, regnum
);
3733 if (offset
+ xfer
> TYPE_LENGTH (type
))
3734 xfer
= TYPE_LENGTH (type
) - offset
;
3736 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3737 offset
, xfer
, regnum
);
3738 mips_xfer_register (gdbarch
, regcache
,
3739 gdbarch_num_regs (gdbarch
) + regnum
,
3740 xfer
, gdbarch_byte_order (gdbarch
),
3741 readbuf
, writebuf
, offset
);
3743 return RETURN_VALUE_REGISTER_CONVENTION
;
3747 /* O32 ABI stuff. */
3750 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3751 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3752 int nargs
, struct value
**args
, CORE_ADDR sp
,
3753 int struct_return
, CORE_ADDR struct_addr
)
3759 int stack_offset
= 0;
3760 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3761 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3762 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3764 /* For shared libraries, "t9" needs to point at the function
3766 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3768 /* Set the return address register to point to the entry point of
3769 the program, where a breakpoint lies in wait. */
3770 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3772 /* First ensure that the stack and structure return address (if any)
3773 are properly aligned. The stack has to be at least 64-bit
3774 aligned even on 32-bit machines, because doubles must be 64-bit
3775 aligned. For n32 and n64, stack frames need to be 128-bit
3776 aligned, so we round to this widest known alignment. */
3778 sp
= align_down (sp
, 16);
3779 struct_addr
= align_down (struct_addr
, 16);
3781 /* Now make space on the stack for the args. */
3782 for (argnum
= 0; argnum
< nargs
; argnum
++)
3784 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3785 int arglen
= TYPE_LENGTH (arg_type
);
3787 /* Align to double-word if necessary. */
3788 if (mips_type_needs_double_align (arg_type
))
3789 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3790 /* Allocate space on the stack. */
3791 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3793 sp
-= align_up (len
, 16);
3796 fprintf_unfiltered (gdb_stdlog
,
3797 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3798 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3800 /* Initialize the integer and float register pointers. */
3801 argreg
= MIPS_A0_REGNUM
;
3802 float_argreg
= mips_fpa0_regnum (gdbarch
);
3804 /* The struct_return pointer occupies the first parameter-passing reg. */
3808 fprintf_unfiltered (gdb_stdlog
,
3809 "mips_o32_push_dummy_call: "
3810 "struct_return reg=%d %s\n",
3811 argreg
, paddress (gdbarch
, struct_addr
));
3812 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3813 stack_offset
+= MIPS32_REGSIZE
;
3816 /* Now load as many as possible of the first arguments into
3817 registers, and push the rest onto the stack. Loop thru args
3818 from first to last. */
3819 for (argnum
= 0; argnum
< nargs
; argnum
++)
3821 const gdb_byte
*val
;
3822 struct value
*arg
= args
[argnum
];
3823 struct type
*arg_type
= check_typedef (value_type (arg
));
3824 int len
= TYPE_LENGTH (arg_type
);
3825 enum type_code typecode
= TYPE_CODE (arg_type
);
3828 fprintf_unfiltered (gdb_stdlog
,
3829 "mips_o32_push_dummy_call: %d len=%d type=%d",
3830 argnum
+ 1, len
, (int) typecode
);
3832 val
= value_contents (arg
);
3834 /* 32-bit ABIs always start floating point arguments in an
3835 even-numbered floating point register. Round the FP register
3836 up before the check to see if there are any FP registers
3837 left. O32/O64 targets also pass the FP in the integer
3838 registers so also round up normal registers. */
3839 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3841 if ((float_argreg
& 1))
3845 /* Floating point arguments passed in registers have to be
3846 treated specially. On 32-bit architectures, doubles
3847 are passed in register pairs; the even register gets
3848 the low word, and the odd register gets the high word.
3849 On O32/O64, the first two floating point arguments are
3850 also copied to general registers, because MIPS16 functions
3851 don't use float registers for arguments. This duplication of
3852 arguments in general registers can't hurt non-MIPS16 functions
3853 because those registers are normally skipped. */
3855 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3856 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3858 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3860 int low_offset
= gdbarch_byte_order (gdbarch
)
3861 == BFD_ENDIAN_BIG
? 4 : 0;
3862 unsigned long regval
;
3864 /* Write the low word of the double to the even register(s). */
3865 regval
= extract_unsigned_integer (val
+ low_offset
,
3868 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3869 float_argreg
, phex (regval
, 4));
3870 regcache_cooked_write_unsigned (regcache
,
3871 float_argreg
++, regval
);
3873 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3874 argreg
, phex (regval
, 4));
3875 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3877 /* Write the high word of the double to the odd register(s). */
3878 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3881 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3882 float_argreg
, phex (regval
, 4));
3883 regcache_cooked_write_unsigned (regcache
,
3884 float_argreg
++, regval
);
3887 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3888 argreg
, phex (regval
, 4));
3889 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3893 /* This is a floating point value that fits entirely
3894 in a single register. */
3895 /* On 32 bit ABI's the float_argreg is further adjusted
3896 above to ensure that it is even register aligned. */
3897 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
3899 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3900 float_argreg
, phex (regval
, len
));
3901 regcache_cooked_write_unsigned (regcache
,
3902 float_argreg
++, regval
);
3903 /* Although two FP registers are reserved for each
3904 argument, only one corresponding integer register is
3907 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3908 argreg
, phex (regval
, len
));
3909 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3911 /* Reserve space for the FP register. */
3912 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3916 /* Copy the argument to general registers or the stack in
3917 register-sized pieces. Large arguments are split between
3918 registers and stack. */
3919 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3920 are treated specially: Irix cc passes
3921 them in registers where gcc sometimes puts them on the
3922 stack. For maximum compatibility, we will put them in
3924 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3925 && len
% MIPS32_REGSIZE
!= 0);
3926 /* Structures should be aligned to eight bytes (even arg registers)
3927 on MIPS_ABI_O32, if their first member has double precision. */
3928 if (mips_type_needs_double_align (arg_type
))
3933 stack_offset
+= MIPS32_REGSIZE
;
3938 /* Remember if the argument was written to the stack. */
3939 int stack_used_p
= 0;
3940 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3943 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3946 /* Write this portion of the argument to the stack. */
3947 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3948 || odd_sized_struct
)
3950 /* Should shorter than int integer values be
3951 promoted to int before being stored? */
3952 int longword_offset
= 0;
3958 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3959 paddress (gdbarch
, stack_offset
));
3960 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3961 paddress (gdbarch
, longword_offset
));
3964 addr
= sp
+ stack_offset
+ longword_offset
;
3969 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3970 paddress (gdbarch
, addr
));
3971 for (i
= 0; i
< partial_len
; i
++)
3973 fprintf_unfiltered (gdb_stdlog
, "%02x",
3977 write_memory (addr
, val
, partial_len
);
3980 /* Note!!! This is NOT an else clause. Odd sized
3981 structs may go thru BOTH paths. */
3982 /* Write this portion of the argument to a general
3983 purpose register. */
3984 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3986 LONGEST regval
= extract_signed_integer (val
, partial_len
,
3988 /* Value may need to be sign extended, because
3989 mips_isa_regsize() != mips_abi_regsize(). */
3991 /* A non-floating-point argument being passed in a
3992 general register. If a struct or union, and if
3993 the remaining length is smaller than the register
3994 size, we have to adjust the register value on
3997 It does not seem to be necessary to do the
3998 same for integral types.
4000 Also don't do this adjustment on O64 binaries.
4002 cagney/2001-07-23: gdb/179: Also, GCC, when
4003 outputting LE O32 with sizeof (struct) <
4004 mips_abi_regsize(), generates a left shift
4005 as part of storing the argument in a register
4006 (the left shift isn't generated when
4007 sizeof (struct) >= mips_abi_regsize()). Since
4008 it is quite possible that this is GCC
4009 contradicting the LE/O32 ABI, GDB has not been
4010 adjusted to accommodate this. Either someone
4011 needs to demonstrate that the LE/O32 ABI
4012 specifies such a left shift OR this new ABI gets
4013 identified as such and GDB gets tweaked
4016 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4017 && partial_len
< MIPS32_REGSIZE
4018 && (typecode
== TYPE_CODE_STRUCT
4019 || typecode
== TYPE_CODE_UNION
))
4020 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
4024 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4026 phex (regval
, MIPS32_REGSIZE
));
4027 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4030 /* Prevent subsequent floating point arguments from
4031 being passed in floating point registers. */
4032 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4038 /* Compute the offset into the stack at which we will
4039 copy the next parameter.
4041 In older ABIs, the caller reserved space for
4042 registers that contained arguments. This was loosely
4043 refered to as their "home". Consequently, space is
4044 always allocated. */
4046 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
4050 fprintf_unfiltered (gdb_stdlog
, "\n");
4053 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4055 /* Return adjusted stack pointer. */
4059 static enum return_value_convention
4060 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4061 struct type
*type
, struct regcache
*regcache
,
4062 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4064 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4066 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4067 || TYPE_CODE (type
) == TYPE_CODE_UNION
4068 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4069 return RETURN_VALUE_STRUCT_CONVENTION
;
4070 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4071 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4073 /* A single-precision floating-point value. It fits in the
4074 least significant part of FP0. */
4076 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4077 mips_xfer_register (gdbarch
, regcache
,
4078 gdbarch_num_regs (gdbarch
)
4079 + mips_regnum (gdbarch
)->fp0
,
4081 gdbarch_byte_order (gdbarch
),
4082 readbuf
, writebuf
, 0);
4083 return RETURN_VALUE_REGISTER_CONVENTION
;
4085 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4086 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4088 /* A double-precision floating-point value. The most
4089 significant part goes in FP1, and the least significant in
4092 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4093 switch (gdbarch_byte_order (gdbarch
))
4095 case BFD_ENDIAN_LITTLE
:
4096 mips_xfer_register (gdbarch
, regcache
,
4097 gdbarch_num_regs (gdbarch
)
4098 + mips_regnum (gdbarch
)->fp0
+
4099 0, 4, gdbarch_byte_order (gdbarch
),
4100 readbuf
, writebuf
, 0);
4101 mips_xfer_register (gdbarch
, regcache
,
4102 gdbarch_num_regs (gdbarch
)
4103 + mips_regnum (gdbarch
)->fp0
+ 1,
4104 4, gdbarch_byte_order (gdbarch
),
4105 readbuf
, writebuf
, 4);
4107 case BFD_ENDIAN_BIG
:
4108 mips_xfer_register (gdbarch
, regcache
,
4109 gdbarch_num_regs (gdbarch
)
4110 + mips_regnum (gdbarch
)->fp0
+ 1,
4111 4, gdbarch_byte_order (gdbarch
),
4112 readbuf
, writebuf
, 0);
4113 mips_xfer_register (gdbarch
, regcache
,
4114 gdbarch_num_regs (gdbarch
)
4115 + mips_regnum (gdbarch
)->fp0
+ 0,
4116 4, gdbarch_byte_order (gdbarch
),
4117 readbuf
, writebuf
, 4);
4120 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4122 return RETURN_VALUE_REGISTER_CONVENTION
;
4125 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4126 && TYPE_NFIELDS (type
) <= 2
4127 && TYPE_NFIELDS (type
) >= 1
4128 && ((TYPE_NFIELDS (type
) == 1
4129 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4131 || (TYPE_NFIELDS (type
) == 2
4132 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4134 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4136 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4138 /* A struct that contains one or two floats. Each value is part
4139 in the least significant part of their floating point
4141 gdb_byte reg
[MAX_REGISTER_SIZE
];
4144 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4145 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4147 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4150 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4152 mips_xfer_register (gdbarch
, regcache
,
4153 gdbarch_num_regs (gdbarch
) + regnum
,
4154 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4155 gdbarch_byte_order (gdbarch
),
4156 readbuf
, writebuf
, offset
);
4158 return RETURN_VALUE_REGISTER_CONVENTION
;
4162 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4163 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4165 /* A structure or union. Extract the left justified value,
4166 regardless of the byte order. I.e. DO NOT USE
4170 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4171 offset
< TYPE_LENGTH (type
);
4172 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4174 int xfer
= register_size (gdbarch
, regnum
);
4175 if (offset
+ xfer
> TYPE_LENGTH (type
))
4176 xfer
= TYPE_LENGTH (type
) - offset
;
4178 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4179 offset
, xfer
, regnum
);
4180 mips_xfer_register (gdbarch
, regcache
,
4181 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4182 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4184 return RETURN_VALUE_REGISTER_CONVENTION
;
4189 /* A scalar extract each part but least-significant-byte
4190 justified. o32 thinks registers are 4 byte, regardless of
4194 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4195 offset
< TYPE_LENGTH (type
);
4196 offset
+= MIPS32_REGSIZE
, regnum
++)
4198 int xfer
= MIPS32_REGSIZE
;
4199 if (offset
+ xfer
> TYPE_LENGTH (type
))
4200 xfer
= TYPE_LENGTH (type
) - offset
;
4202 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4203 offset
, xfer
, regnum
);
4204 mips_xfer_register (gdbarch
, regcache
,
4205 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4206 gdbarch_byte_order (gdbarch
),
4207 readbuf
, writebuf
, offset
);
4209 return RETURN_VALUE_REGISTER_CONVENTION
;
4213 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4217 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4218 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4220 struct value
**args
, CORE_ADDR sp
,
4221 int struct_return
, CORE_ADDR struct_addr
)
4227 int stack_offset
= 0;
4228 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4229 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4230 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4232 /* For shared libraries, "t9" needs to point at the function
4234 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4236 /* Set the return address register to point to the entry point of
4237 the program, where a breakpoint lies in wait. */
4238 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4240 /* First ensure that the stack and structure return address (if any)
4241 are properly aligned. The stack has to be at least 64-bit
4242 aligned even on 32-bit machines, because doubles must be 64-bit
4243 aligned. For n32 and n64, stack frames need to be 128-bit
4244 aligned, so we round to this widest known alignment. */
4246 sp
= align_down (sp
, 16);
4247 struct_addr
= align_down (struct_addr
, 16);
4249 /* Now make space on the stack for the args. */
4250 for (argnum
= 0; argnum
< nargs
; argnum
++)
4252 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4253 int arglen
= TYPE_LENGTH (arg_type
);
4255 /* Allocate space on the stack. */
4256 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4258 sp
-= align_up (len
, 16);
4261 fprintf_unfiltered (gdb_stdlog
,
4262 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4263 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4265 /* Initialize the integer and float register pointers. */
4266 argreg
= MIPS_A0_REGNUM
;
4267 float_argreg
= mips_fpa0_regnum (gdbarch
);
4269 /* The struct_return pointer occupies the first parameter-passing reg. */
4273 fprintf_unfiltered (gdb_stdlog
,
4274 "mips_o64_push_dummy_call: "
4275 "struct_return reg=%d %s\n",
4276 argreg
, paddress (gdbarch
, struct_addr
));
4277 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4278 stack_offset
+= MIPS64_REGSIZE
;
4281 /* Now load as many as possible of the first arguments into
4282 registers, and push the rest onto the stack. Loop thru args
4283 from first to last. */
4284 for (argnum
= 0; argnum
< nargs
; argnum
++)
4286 const gdb_byte
*val
;
4287 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4288 struct value
*arg
= args
[argnum
];
4289 struct type
*arg_type
= check_typedef (value_type (arg
));
4290 int len
= TYPE_LENGTH (arg_type
);
4291 enum type_code typecode
= TYPE_CODE (arg_type
);
4294 fprintf_unfiltered (gdb_stdlog
,
4295 "mips_o64_push_dummy_call: %d len=%d type=%d",
4296 argnum
+ 1, len
, (int) typecode
);
4298 val
= value_contents (arg
);
4300 /* Function pointer arguments to mips16 code need to be made into
4302 if (typecode
== TYPE_CODE_PTR
4303 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4305 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4307 if (mips_pc_is_mips16 (addr
))
4309 store_signed_integer (valbuf
, len
, byte_order
,
4310 make_mips16_addr (addr
));
4315 /* Floating point arguments passed in registers have to be
4316 treated specially. On 32-bit architectures, doubles
4317 are passed in register pairs; the even register gets
4318 the low word, and the odd register gets the high word.
4319 On O32/O64, the first two floating point arguments are
4320 also copied to general registers, because MIPS16 functions
4321 don't use float registers for arguments. This duplication of
4322 arguments in general registers can't hurt non-MIPS16 functions
4323 because those registers are normally skipped. */
4325 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4326 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4328 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4330 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4331 float_argreg
, phex (regval
, len
));
4332 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4334 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4335 argreg
, phex (regval
, len
));
4336 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4338 /* Reserve space for the FP register. */
4339 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4343 /* Copy the argument to general registers or the stack in
4344 register-sized pieces. Large arguments are split between
4345 registers and stack. */
4346 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4347 are treated specially: Irix cc passes them in registers
4348 where gcc sometimes puts them on the stack. For maximum
4349 compatibility, we will put them in both places. */
4350 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4351 && len
% MIPS64_REGSIZE
!= 0);
4354 /* Remember if the argument was written to the stack. */
4355 int stack_used_p
= 0;
4356 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4359 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4362 /* Write this portion of the argument to the stack. */
4363 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4364 || odd_sized_struct
)
4366 /* Should shorter than int integer values be
4367 promoted to int before being stored? */
4368 int longword_offset
= 0;
4371 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4373 if ((typecode
== TYPE_CODE_INT
4374 || typecode
== TYPE_CODE_PTR
4375 || typecode
== TYPE_CODE_FLT
)
4377 longword_offset
= MIPS64_REGSIZE
- len
;
4382 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4383 paddress (gdbarch
, stack_offset
));
4384 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4385 paddress (gdbarch
, longword_offset
));
4388 addr
= sp
+ stack_offset
+ longword_offset
;
4393 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4394 paddress (gdbarch
, addr
));
4395 for (i
= 0; i
< partial_len
; i
++)
4397 fprintf_unfiltered (gdb_stdlog
, "%02x",
4401 write_memory (addr
, val
, partial_len
);
4404 /* Note!!! This is NOT an else clause. Odd sized
4405 structs may go thru BOTH paths. */
4406 /* Write this portion of the argument to a general
4407 purpose register. */
4408 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4410 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4412 /* Value may need to be sign extended, because
4413 mips_isa_regsize() != mips_abi_regsize(). */
4415 /* A non-floating-point argument being passed in a
4416 general register. If a struct or union, and if
4417 the remaining length is smaller than the register
4418 size, we have to adjust the register value on
4421 It does not seem to be necessary to do the
4422 same for integral types. */
4424 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4425 && partial_len
< MIPS64_REGSIZE
4426 && (typecode
== TYPE_CODE_STRUCT
4427 || typecode
== TYPE_CODE_UNION
))
4428 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4432 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4434 phex (regval
, MIPS64_REGSIZE
));
4435 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4438 /* Prevent subsequent floating point arguments from
4439 being passed in floating point registers. */
4440 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4446 /* Compute the offset into the stack at which we will
4447 copy the next parameter.
4449 In older ABIs, the caller reserved space for
4450 registers that contained arguments. This was loosely
4451 refered to as their "home". Consequently, space is
4452 always allocated. */
4454 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4458 fprintf_unfiltered (gdb_stdlog
, "\n");
4461 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4463 /* Return adjusted stack pointer. */
4467 static enum return_value_convention
4468 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4469 struct type
*type
, struct regcache
*regcache
,
4470 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4472 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4474 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4475 || TYPE_CODE (type
) == TYPE_CODE_UNION
4476 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4477 return RETURN_VALUE_STRUCT_CONVENTION
;
4478 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4480 /* A floating-point value. It fits in the least significant
4483 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4484 mips_xfer_register (gdbarch
, regcache
,
4485 gdbarch_num_regs (gdbarch
)
4486 + mips_regnum (gdbarch
)->fp0
,
4488 gdbarch_byte_order (gdbarch
),
4489 readbuf
, writebuf
, 0);
4490 return RETURN_VALUE_REGISTER_CONVENTION
;
4494 /* A scalar extract each part but least-significant-byte
4498 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4499 offset
< TYPE_LENGTH (type
);
4500 offset
+= MIPS64_REGSIZE
, regnum
++)
4502 int xfer
= MIPS64_REGSIZE
;
4503 if (offset
+ xfer
> TYPE_LENGTH (type
))
4504 xfer
= TYPE_LENGTH (type
) - offset
;
4506 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4507 offset
, xfer
, regnum
);
4508 mips_xfer_register (gdbarch
, regcache
,
4509 gdbarch_num_regs (gdbarch
) + regnum
,
4510 xfer
, gdbarch_byte_order (gdbarch
),
4511 readbuf
, writebuf
, offset
);
4513 return RETURN_VALUE_REGISTER_CONVENTION
;
4517 /* Floating point register management.
4519 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4520 64bit operations, these early MIPS cpus treat fp register pairs
4521 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4522 registers and offer a compatibility mode that emulates the MIPS2 fp
4523 model. When operating in MIPS2 fp compat mode, later cpu's split
4524 double precision floats into two 32-bit chunks and store them in
4525 consecutive fp regs. To display 64-bit floats stored in this
4526 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4527 Throw in user-configurable endianness and you have a real mess.
4529 The way this works is:
4530 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4531 double-precision value will be split across two logical registers.
4532 The lower-numbered logical register will hold the low-order bits,
4533 regardless of the processor's endianness.
4534 - If we are on a 64-bit processor, and we are looking for a
4535 single-precision value, it will be in the low ordered bits
4536 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4537 save slot in memory.
4538 - If we are in 64-bit mode, everything is straightforward.
4540 Note that this code only deals with "live" registers at the top of the
4541 stack. We will attempt to deal with saved registers later, when
4542 the raw/cooked register interface is in place. (We need a general
4543 interface that can deal with dynamic saved register sizes -- fp
4544 regs could be 32 bits wide in one frame and 64 on the frame above
4547 /* Copy a 32-bit single-precision value from the current frame
4548 into rare_buffer. */
4551 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4552 gdb_byte
*rare_buffer
)
4554 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4555 int raw_size
= register_size (gdbarch
, regno
);
4556 gdb_byte
*raw_buffer
= alloca (raw_size
);
4558 if (!frame_register_read (frame
, regno
, raw_buffer
))
4559 error (_("can't read register %d (%s)"),
4560 regno
, gdbarch_register_name (gdbarch
, regno
));
4563 /* We have a 64-bit value for this register. Find the low-order
4567 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4572 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4576 memcpy (rare_buffer
, raw_buffer
, 4);
4580 /* Copy a 64-bit double-precision value from the current frame into
4581 rare_buffer. This may include getting half of it from the next
4585 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4586 gdb_byte
*rare_buffer
)
4588 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4589 int raw_size
= register_size (gdbarch
, regno
);
4591 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4593 /* We have a 64-bit value for this register, and we should use
4595 if (!frame_register_read (frame
, regno
, rare_buffer
))
4596 error (_("can't read register %d (%s)"),
4597 regno
, gdbarch_register_name (gdbarch
, regno
));
4601 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4603 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4604 internal_error (__FILE__
, __LINE__
,
4605 _("mips_read_fp_register_double: bad access to "
4606 "odd-numbered FP register"));
4608 /* mips_read_fp_register_single will find the correct 32 bits from
4610 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4612 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4613 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4617 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4618 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4624 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4626 { /* Do values for FP (float) regs. */
4627 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4628 gdb_byte
*raw_buffer
;
4629 double doub
, flt1
; /* Doubles extracted from raw hex data. */
4632 raw_buffer
= alloca (2 * register_size (gdbarch
,
4633 mips_regnum (gdbarch
)->fp0
));
4635 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4636 fprintf_filtered (file
, "%*s",
4637 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4640 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4642 struct value_print_options opts
;
4644 /* 4-byte registers: Print hex and floating. Also print even
4645 numbered registers as doubles. */
4646 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4647 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4650 get_formatted_print_options (&opts
, 'x');
4651 print_scalar_formatted (raw_buffer
,
4652 builtin_type (gdbarch
)->builtin_uint32
,
4655 fprintf_filtered (file
, " flt: ");
4657 fprintf_filtered (file
, " <invalid float> ");
4659 fprintf_filtered (file
, "%-17.9g", flt1
);
4661 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4663 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4664 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4667 fprintf_filtered (file
, " dbl: ");
4669 fprintf_filtered (file
, "<invalid double>");
4671 fprintf_filtered (file
, "%-24.17g", doub
);
4676 struct value_print_options opts
;
4678 /* Eight byte registers: print each one as hex, float and double. */
4679 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4680 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4683 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4684 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4687 get_formatted_print_options (&opts
, 'x');
4688 print_scalar_formatted (raw_buffer
,
4689 builtin_type (gdbarch
)->builtin_uint64
,
4692 fprintf_filtered (file
, " flt: ");
4694 fprintf_filtered (file
, "<invalid float>");
4696 fprintf_filtered (file
, "%-17.9g", flt1
);
4698 fprintf_filtered (file
, " dbl: ");
4700 fprintf_filtered (file
, "<invalid double>");
4702 fprintf_filtered (file
, "%-24.17g", doub
);
4707 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4710 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4712 struct value_print_options opts
;
4715 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4717 mips_print_fp_register (file
, frame
, regnum
);
4721 val
= get_frame_register_value (frame
, regnum
);
4722 if (value_optimized_out (val
))
4724 fprintf_filtered (file
, "%s: [Invalid]",
4725 gdbarch_register_name (gdbarch
, regnum
));
4729 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4731 /* The problem with printing numeric register names (r26, etc.) is that
4732 the user can't use them on input. Probably the best solution is to
4733 fix it so that either the numeric or the funky (a2, etc.) names
4734 are accepted on input. */
4735 if (regnum
< MIPS_NUMREGS
)
4736 fprintf_filtered (file
, "(r%d): ", regnum
);
4738 fprintf_filtered (file
, ": ");
4740 get_formatted_print_options (&opts
, 'x');
4741 val_print_scalar_formatted (value_type (val
),
4742 value_contents_for_printing (val
),
4743 value_embedded_offset (val
),
4748 /* Replacement for generic do_registers_info.
4749 Print regs in pretty columns. */
4752 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4755 fprintf_filtered (file
, " ");
4756 mips_print_fp_register (file
, frame
, regnum
);
4757 fprintf_filtered (file
, "\n");
4762 /* Print a row's worth of GP (int) registers, with name labels above. */
4765 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4768 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4769 /* Do values for GP (int) regs. */
4770 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4771 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
4776 /* For GP registers, we print a separate row of names above the vals. */
4777 for (col
= 0, regnum
= start_regnum
;
4778 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4779 + gdbarch_num_pseudo_regs (gdbarch
);
4782 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4783 continue; /* unused register */
4784 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4786 break; /* End the row: reached FP register. */
4787 /* Large registers are handled separately. */
4788 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4791 break; /* End the row before this register. */
4793 /* Print this register on a row by itself. */
4794 mips_print_register (file
, frame
, regnum
);
4795 fprintf_filtered (file
, "\n");
4799 fprintf_filtered (file
, " ");
4800 fprintf_filtered (file
,
4801 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4802 gdbarch_register_name (gdbarch
, regnum
));
4809 /* Print the R0 to R31 names. */
4810 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4811 fprintf_filtered (file
, "\n R%-4d",
4812 start_regnum
% gdbarch_num_regs (gdbarch
));
4814 fprintf_filtered (file
, "\n ");
4816 /* Now print the values in hex, 4 or 8 to the row. */
4817 for (col
= 0, regnum
= start_regnum
;
4818 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4819 + gdbarch_num_pseudo_regs (gdbarch
);
4822 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4823 continue; /* unused register */
4824 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4826 break; /* End row: reached FP register. */
4827 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4828 break; /* End row: large register. */
4830 /* OK: get the data in raw format. */
4831 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4832 error (_("can't read register %d (%s)"),
4833 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4834 /* pad small registers */
4836 byte
< (mips_abi_regsize (gdbarch
)
4837 - register_size (gdbarch
, regnum
)); byte
++)
4838 printf_filtered (" ");
4839 /* Now print the register value in hex, endian order. */
4840 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4842 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4843 byte
< register_size (gdbarch
, regnum
); byte
++)
4844 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4846 for (byte
= register_size (gdbarch
, regnum
) - 1;
4848 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4849 fprintf_filtered (file
, " ");
4852 if (col
> 0) /* ie. if we actually printed anything... */
4853 fprintf_filtered (file
, "\n");
4858 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
4861 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4862 struct frame_info
*frame
, int regnum
, int all
)
4864 if (regnum
!= -1) /* Do one specified register. */
4866 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4867 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4868 error (_("Not a valid register for the current processor type"));
4870 mips_print_register (file
, frame
, regnum
);
4871 fprintf_filtered (file
, "\n");
4874 /* Do all (or most) registers. */
4876 regnum
= gdbarch_num_regs (gdbarch
);
4877 while (regnum
< gdbarch_num_regs (gdbarch
)
4878 + gdbarch_num_pseudo_regs (gdbarch
))
4880 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4883 if (all
) /* True for "INFO ALL-REGISTERS" command. */
4884 regnum
= print_fp_register_row (file
, frame
, regnum
);
4886 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
4889 regnum
= print_gp_register_row (file
, frame
, regnum
);
4894 /* Is this a branch with a delay slot? */
4897 is_delayed (unsigned long insn
)
4900 for (i
= 0; i
< NUMOPCODES
; ++i
)
4901 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4902 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4904 return (i
< NUMOPCODES
4905 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4906 | INSN_COND_BRANCH_DELAY
4907 | INSN_COND_BRANCH_LIKELY
)));
4911 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4912 struct frame_info
*frame
)
4914 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4915 CORE_ADDR pc
= get_frame_pc (frame
);
4916 gdb_byte buf
[MIPS_INSN32_SIZE
];
4918 /* There is no branch delay slot on MIPS16. */
4919 if (mips_pc_is_mips16 (pc
))
4922 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
4925 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4926 /* If error reading memory, guess that it is not a delayed
4929 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
4932 /* To skip prologues, I use this predicate. Returns either PC itself
4933 if the code at PC does not look like a function prologue; otherwise
4934 returns an address that (if we're lucky) follows the prologue. If
4935 LENIENT, then we must skip everything which is involved in setting
4936 up the frame (it's OK to skip more, just so long as we don't skip
4937 anything which might clobber the registers which are being saved.
4938 We must skip more in the case where part of the prologue is in the
4939 delay slot of a non-prologue instruction). */
4942 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4945 CORE_ADDR func_addr
;
4947 /* See if we can determine the end of the prologue via the symbol table.
4948 If so, then return either PC, or the PC after the prologue, whichever
4950 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4952 CORE_ADDR post_prologue_pc
4953 = skip_prologue_using_sal (gdbarch
, func_addr
);
4954 if (post_prologue_pc
!= 0)
4955 return max (pc
, post_prologue_pc
);
4958 /* Can't determine prologue from the symbol table, need to examine
4961 /* Find an upper limit on the function prologue using the debug
4962 information. If the debug information could not be used to provide
4963 that bound, then use an arbitrary large number as the upper bound. */
4964 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
4966 limit_pc
= pc
+ 100; /* Magic. */
4968 if (mips_pc_is_mips16 (pc
))
4969 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4971 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4974 /* Check whether the PC is in a function epilogue (32-bit version).
4975 This is a helper function for mips_in_function_epilogue_p. */
4977 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4979 CORE_ADDR func_addr
= 0, func_end
= 0;
4981 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4983 /* The MIPS epilogue is max. 12 bytes long. */
4984 CORE_ADDR addr
= func_end
- 12;
4986 if (addr
< func_addr
+ 4)
4987 addr
= func_addr
+ 4;
4991 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4993 unsigned long high_word
;
4996 inst
= mips_fetch_instruction (gdbarch
, pc
);
4997 high_word
= (inst
>> 16) & 0xffff;
4999 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
5000 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
5001 && inst
!= 0x03e00008 /* jr $ra */
5002 && inst
!= 0x00000000) /* nop */
5012 /* Check whether the PC is in a function epilogue (16-bit version).
5013 This is a helper function for mips_in_function_epilogue_p. */
5015 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5017 CORE_ADDR func_addr
= 0, func_end
= 0;
5019 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5021 /* The MIPS epilogue is max. 12 bytes long. */
5022 CORE_ADDR addr
= func_end
- 12;
5024 if (addr
< func_addr
+ 4)
5025 addr
= func_addr
+ 4;
5029 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
5031 unsigned short inst
;
5033 inst
= mips_fetch_instruction (gdbarch
, pc
);
5035 if ((inst
& 0xf800) == 0xf000) /* extend */
5038 if (inst
!= 0x6300 /* addiu $sp,offset */
5039 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
5040 && inst
!= 0xe820 /* jr $ra */
5041 && inst
!= 0xe8a0 /* jrc $ra */
5042 && inst
!= 0x6500) /* nop */
5052 /* The epilogue is defined here as the area at the end of a function,
5053 after an instruction which destroys the function's stack frame. */
5055 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5057 if (mips_pc_is_mips16 (pc
))
5058 return mips16_in_function_epilogue_p (gdbarch
, pc
);
5060 return mips32_in_function_epilogue_p (gdbarch
, pc
);
5063 /* Root of all "set mips "/"show mips " commands. This will eventually be
5064 used for all MIPS-specific commands. */
5067 show_mips_command (char *args
, int from_tty
)
5069 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5073 set_mips_command (char *args
, int from_tty
)
5076 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5077 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5080 /* Commands to show/set the MIPS FPU type. */
5083 show_mipsfpu_command (char *args
, int from_tty
)
5087 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5090 ("The MIPS floating-point coprocessor is unknown "
5091 "because the current architecture is not MIPS.\n");
5095 switch (MIPS_FPU_TYPE (target_gdbarch
))
5097 case MIPS_FPU_SINGLE
:
5098 fpu
= "single-precision";
5100 case MIPS_FPU_DOUBLE
:
5101 fpu
= "double-precision";
5104 fpu
= "absent (none)";
5107 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5109 if (mips_fpu_type_auto
)
5110 printf_unfiltered ("The MIPS floating-point coprocessor "
5111 "is set automatically (currently %s)\n",
5115 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5120 set_mipsfpu_command (char *args
, int from_tty
)
5122 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
5123 "\"single\",\"none\" or \"auto\".\n");
5124 show_mipsfpu_command (args
, from_tty
);
5128 set_mipsfpu_single_command (char *args
, int from_tty
)
5130 struct gdbarch_info info
;
5131 gdbarch_info_init (&info
);
5132 mips_fpu_type
= MIPS_FPU_SINGLE
;
5133 mips_fpu_type_auto
= 0;
5134 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5135 instead of relying on globals. Doing that would let generic code
5136 handle the search for this specific architecture. */
5137 if (!gdbarch_update_p (info
))
5138 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5142 set_mipsfpu_double_command (char *args
, int from_tty
)
5144 struct gdbarch_info info
;
5145 gdbarch_info_init (&info
);
5146 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5147 mips_fpu_type_auto
= 0;
5148 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5149 instead of relying on globals. Doing that would let generic code
5150 handle the search for this specific architecture. */
5151 if (!gdbarch_update_p (info
))
5152 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5156 set_mipsfpu_none_command (char *args
, int from_tty
)
5158 struct gdbarch_info info
;
5159 gdbarch_info_init (&info
);
5160 mips_fpu_type
= MIPS_FPU_NONE
;
5161 mips_fpu_type_auto
= 0;
5162 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5163 instead of relying on globals. Doing that would let generic code
5164 handle the search for this specific architecture. */
5165 if (!gdbarch_update_p (info
))
5166 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5170 set_mipsfpu_auto_command (char *args
, int from_tty
)
5172 mips_fpu_type_auto
= 1;
5175 /* Attempt to identify the particular processor model by reading the
5176 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5177 the relevant processor still exists (it dates back to '94) and
5178 secondly this is not the way to do this. The processor type should
5179 be set by forcing an architecture change. */
5182 deprecated_mips_set_processor_regs_hack (void)
5184 struct regcache
*regcache
= get_current_regcache ();
5185 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5186 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5189 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5190 if ((prid
& ~0xf) == 0x700)
5191 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5194 /* Just like reinit_frame_cache, but with the right arguments to be
5195 callable as an sfunc. */
5198 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5199 struct cmd_list_element
*c
)
5201 reinit_frame_cache ();
5205 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5207 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5208 disassembler needs to be able to locally determine the ISA, and
5209 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5211 if (mips_pc_is_mips16 (memaddr
))
5212 info
->mach
= bfd_mach_mips16
;
5214 /* Round down the instruction address to the appropriate boundary. */
5215 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5217 /* Set the disassembler options. */
5218 if (!info
->disassembler_options
)
5219 /* This string is not recognized explicitly by the disassembler,
5220 but it tells the disassembler to not try to guess the ABI from
5221 the bfd elf headers, such that, if the user overrides the ABI
5222 of a program linked as NewABI, the disassembly will follow the
5223 register naming conventions specified by the user. */
5224 info
->disassembler_options
= "gpr-names=32";
5226 /* Call the appropriate disassembler based on the target endian-ness. */
5227 if (info
->endian
== BFD_ENDIAN_BIG
)
5228 return print_insn_big_mips (memaddr
, info
);
5230 return print_insn_little_mips (memaddr
, info
);
5234 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5236 /* Set up the disassembler info, so that we get the right
5237 register names from libopcodes. */
5238 info
->disassembler_options
= "gpr-names=n32";
5239 info
->flavour
= bfd_target_elf_flavour
;
5241 return gdb_print_insn_mips (memaddr
, info
);
5245 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5247 /* Set up the disassembler info, so that we get the right
5248 register names from libopcodes. */
5249 info
->disassembler_options
= "gpr-names=64";
5250 info
->flavour
= bfd_target_elf_flavour
;
5252 return gdb_print_insn_mips (memaddr
, info
);
5255 /* This function implements gdbarch_breakpoint_from_pc. It uses the
5256 program counter value to determine whether a 16- or 32-bit breakpoint
5257 should be used. It returns a pointer to a string of bytes that encode a
5258 breakpoint instruction, stores the length of the string to *lenptr, and
5259 adjusts pc (if necessary) to point to the actual memory location where
5260 the breakpoint should be inserted. */
5262 static const gdb_byte
*
5263 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
5264 CORE_ADDR
*pcptr
, int *lenptr
)
5266 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5268 if (mips_pc_is_mips16 (*pcptr
))
5270 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5271 *pcptr
= unmake_mips16_addr (*pcptr
);
5272 *lenptr
= sizeof (mips16_big_breakpoint
);
5273 return mips16_big_breakpoint
;
5277 /* The IDT board uses an unusual breakpoint value, and
5278 sometimes gets confused when it sees the usual MIPS
5279 breakpoint instruction. */
5280 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5281 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5282 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5283 /* Likewise, IRIX appears to expect a different breakpoint,
5284 although this is not apparent until you try to use pthreads. */
5285 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5287 *lenptr
= sizeof (big_breakpoint
);
5289 if (strcmp (target_shortname
, "mips") == 0)
5290 return idt_big_breakpoint
;
5291 else if (strcmp (target_shortname
, "ddb") == 0
5292 || strcmp (target_shortname
, "pmon") == 0
5293 || strcmp (target_shortname
, "lsi") == 0)
5294 return pmon_big_breakpoint
;
5295 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5296 return irix_big_breakpoint
;
5298 return big_breakpoint
;
5303 if (mips_pc_is_mips16 (*pcptr
))
5305 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5306 *pcptr
= unmake_mips16_addr (*pcptr
);
5307 *lenptr
= sizeof (mips16_little_breakpoint
);
5308 return mips16_little_breakpoint
;
5312 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5313 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5314 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5316 *lenptr
= sizeof (little_breakpoint
);
5318 if (strcmp (target_shortname
, "mips") == 0)
5319 return idt_little_breakpoint
;
5320 else if (strcmp (target_shortname
, "ddb") == 0
5321 || strcmp (target_shortname
, "pmon") == 0
5322 || strcmp (target_shortname
, "lsi") == 0)
5323 return pmon_little_breakpoint
;
5325 return little_breakpoint
;
5330 /* If PC is in a mips16 call or return stub, return the address of the target
5331 PC, which is either the callee or the caller. There are several
5332 cases which must be handled:
5334 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5335 target PC is in $31 ($ra).
5336 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5337 and the target PC is in $2.
5338 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5339 before the jal instruction, this is effectively a call stub
5340 and the target PC is in $2. Otherwise this is effectively
5341 a return stub and the target PC is in $18.
5343 See the source code for the stubs in gcc/config/mips/mips16.S for
5347 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5349 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5351 CORE_ADDR start_addr
;
5353 /* Find the starting address and name of the function containing the PC. */
5354 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5357 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5358 target PC is in $31 ($ra). */
5359 if (strcmp (name
, "__mips16_ret_sf") == 0
5360 || strcmp (name
, "__mips16_ret_df") == 0)
5361 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5363 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5365 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5366 and the target PC is in $2. */
5367 if (name
[19] >= '0' && name
[19] <= '9')
5368 return get_frame_register_signed (frame
, 2);
5370 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5371 before the jal instruction, this is effectively a call stub
5372 and the target PC is in $2. Otherwise this is effectively
5373 a return stub and the target PC is in $18. */
5374 else if (name
[19] == 's' || name
[19] == 'd')
5376 if (pc
== start_addr
)
5378 /* Check if the target of the stub is a compiler-generated
5379 stub. Such a stub for a function bar might have a name
5380 like __fn_stub_bar, and might look like this:
5385 la $1,bar (becomes a lui/addiu pair)
5387 So scan down to the lui/addi and extract the target
5388 address from those two instructions. */
5390 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5394 /* See if the name of the target function is __fn_stub_*. */
5395 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5398 if (strncmp (name
, "__fn_stub_", 10) != 0
5399 && strcmp (name
, "etext") != 0
5400 && strcmp (name
, "_etext") != 0)
5403 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5404 The limit on the search is arbitrarily set to 20
5405 instructions. FIXME. */
5406 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5408 inst
= mips_fetch_instruction (gdbarch
, target_pc
);
5409 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5410 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5411 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5412 return pc
| (inst
& 0xffff); /* low word */
5415 /* Couldn't find the lui/addui pair, so return stub address. */
5419 /* This is the 'return' part of a call stub. The return
5420 address is in $r18. */
5421 return get_frame_register_signed (frame
, 18);
5424 return 0; /* not a stub */
5427 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5428 PC of the stub target. The stub just loads $t9 and jumps to it,
5429 so that $t9 has the correct value at function entry. */
5432 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5434 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5435 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5436 struct minimal_symbol
*msym
;
5438 gdb_byte stub_code
[16];
5439 int32_t stub_words
[4];
5441 /* The stub for foo is named ".pic.foo", and is either two
5442 instructions inserted before foo or a three instruction sequence
5443 which jumps to foo. */
5444 msym
= lookup_minimal_symbol_by_pc (pc
);
5446 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5447 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5448 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5451 /* A two-instruction header. */
5452 if (MSYMBOL_SIZE (msym
) == 8)
5455 /* A three-instruction (plus delay slot) trampoline. */
5456 if (MSYMBOL_SIZE (msym
) == 16)
5458 if (target_read_memory (pc
, stub_code
, 16) != 0)
5460 for (i
= 0; i
< 4; i
++)
5461 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
5464 /* A stub contains these instructions:
5467 addiu t9, t9, %lo(target)
5470 This works even for N64, since stubs are only generated with
5472 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5473 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5474 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5475 && stub_words
[3] == 0x00000000)
5476 return (((stub_words
[0] & 0x0000ffff) << 16)
5477 + (stub_words
[2] & 0x0000ffff));
5480 /* Not a recognized stub. */
5485 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5487 CORE_ADDR target_pc
;
5489 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5493 target_pc
= find_solib_trampoline_target (frame
, pc
);
5497 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5504 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5505 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5508 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5511 if (num
>= 0 && num
< 32)
5513 else if (num
>= 38 && num
< 70)
5514 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5516 regnum
= mips_regnum (gdbarch
)->hi
;
5518 regnum
= mips_regnum (gdbarch
)->lo
;
5520 /* This will hopefully (eventually) provoke a warning. Should
5521 we be calling complaint() here? */
5522 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5523 return gdbarch_num_regs (gdbarch
) + regnum
;
5527 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5528 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5531 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5534 if (num
>= 0 && num
< 32)
5536 else if (num
>= 32 && num
< 64)
5537 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5539 regnum
= mips_regnum (gdbarch
)->hi
;
5541 regnum
= mips_regnum (gdbarch
)->lo
;
5543 /* This will hopefully (eventually) provoke a warning. Should we
5544 be calling complaint() here? */
5545 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5546 return gdbarch_num_regs (gdbarch
) + regnum
;
5550 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5552 /* Only makes sense to supply raw registers. */
5553 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5554 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5555 decide if it is valid. Should instead define a standard sim/gdb
5556 register numbering scheme. */
5557 if (gdbarch_register_name (gdbarch
,
5558 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5559 && gdbarch_register_name (gdbarch
,
5560 gdbarch_num_regs (gdbarch
)
5561 + regnum
)[0] != '\0')
5564 return LEGACY_SIM_REGNO_IGNORE
;
5568 /* Convert an integer into an address. Extracting the value signed
5569 guarantees a correctly sign extended address. */
5572 mips_integer_to_address (struct gdbarch
*gdbarch
,
5573 struct type
*type
, const gdb_byte
*buf
)
5575 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5576 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
5579 /* Dummy virtual frame pointer method. This is no more or less accurate
5580 than most other architectures; we just need to be explicit about it,
5581 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5582 an assertion failure. */
5585 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5586 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5588 *reg
= MIPS_SP_REGNUM
;
5593 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5595 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5596 const char *name
= bfd_get_section_name (abfd
, sect
);
5598 if (*abip
!= MIPS_ABI_UNKNOWN
)
5601 if (strncmp (name
, ".mdebug.", 8) != 0)
5604 if (strcmp (name
, ".mdebug.abi32") == 0)
5605 *abip
= MIPS_ABI_O32
;
5606 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5607 *abip
= MIPS_ABI_N32
;
5608 else if (strcmp (name
, ".mdebug.abi64") == 0)
5609 *abip
= MIPS_ABI_N64
;
5610 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5611 *abip
= MIPS_ABI_O64
;
5612 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5613 *abip
= MIPS_ABI_EABI32
;
5614 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5615 *abip
= MIPS_ABI_EABI64
;
5617 warning (_("unsupported ABI %s."), name
+ 8);
5621 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5623 int *lbp
= (int *) obj
;
5624 const char *name
= bfd_get_section_name (abfd
, sect
);
5626 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5628 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5630 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5631 warning (_("unrecognized .gcc_compiled_longXX"));
5634 static enum mips_abi
5635 global_mips_abi (void)
5639 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5640 if (mips_abi_strings
[i
] == mips_abi_string
)
5641 return (enum mips_abi
) i
;
5643 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5647 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5649 /* If the size matches the set of 32-bit or 64-bit integer registers,
5650 assume that's what we've got. */
5651 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5652 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5654 /* If the size matches the full set of registers GDB traditionally
5655 knows about, including floating point, for either 32-bit or
5656 64-bit, assume that's what we've got. */
5657 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5658 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5660 /* Otherwise we don't have a useful guess. */
5663 static struct value
*
5664 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5666 const int *reg_p
= baton
;
5667 return value_of_register (*reg_p
, frame
);
5670 static struct gdbarch
*
5671 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5673 struct gdbarch
*gdbarch
;
5674 struct gdbarch_tdep
*tdep
;
5676 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5678 enum mips_fpu_type fpu_type
;
5679 struct tdesc_arch_data
*tdesc_data
= NULL
;
5680 int elf_fpu_type
= 0;
5682 /* Check any target description for validity. */
5683 if (tdesc_has_registers (info
.target_desc
))
5685 static const char *const mips_gprs
[] = {
5686 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5687 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5688 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5689 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5691 static const char *const mips_fprs
[] = {
5692 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5693 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5694 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5695 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5698 const struct tdesc_feature
*feature
;
5701 feature
= tdesc_find_feature (info
.target_desc
,
5702 "org.gnu.gdb.mips.cpu");
5703 if (feature
== NULL
)
5706 tdesc_data
= tdesc_data_alloc ();
5709 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5710 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5714 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5715 MIPS_EMBED_LO_REGNUM
, "lo");
5716 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5717 MIPS_EMBED_HI_REGNUM
, "hi");
5718 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5719 MIPS_EMBED_PC_REGNUM
, "pc");
5723 tdesc_data_cleanup (tdesc_data
);
5727 feature
= tdesc_find_feature (info
.target_desc
,
5728 "org.gnu.gdb.mips.cp0");
5729 if (feature
== NULL
)
5731 tdesc_data_cleanup (tdesc_data
);
5736 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5737 MIPS_EMBED_BADVADDR_REGNUM
,
5739 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5740 MIPS_PS_REGNUM
, "status");
5741 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5742 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5746 tdesc_data_cleanup (tdesc_data
);
5750 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5751 backend is not prepared for that, though. */
5752 feature
= tdesc_find_feature (info
.target_desc
,
5753 "org.gnu.gdb.mips.fpu");
5754 if (feature
== NULL
)
5756 tdesc_data_cleanup (tdesc_data
);
5761 for (i
= 0; i
< 32; i
++)
5762 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5763 i
+ MIPS_EMBED_FP0_REGNUM
,
5766 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5767 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5768 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5769 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5773 tdesc_data_cleanup (tdesc_data
);
5777 /* It would be nice to detect an attempt to use a 64-bit ABI
5778 when only 32-bit registers are provided. */
5781 /* First of all, extract the elf_flags, if available. */
5782 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5783 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5784 else if (arches
!= NULL
)
5785 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5789 fprintf_unfiltered (gdb_stdlog
,
5790 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5792 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5793 switch ((elf_flags
& EF_MIPS_ABI
))
5795 case E_MIPS_ABI_O32
:
5796 found_abi
= MIPS_ABI_O32
;
5798 case E_MIPS_ABI_O64
:
5799 found_abi
= MIPS_ABI_O64
;
5801 case E_MIPS_ABI_EABI32
:
5802 found_abi
= MIPS_ABI_EABI32
;
5804 case E_MIPS_ABI_EABI64
:
5805 found_abi
= MIPS_ABI_EABI64
;
5808 if ((elf_flags
& EF_MIPS_ABI2
))
5809 found_abi
= MIPS_ABI_N32
;
5811 found_abi
= MIPS_ABI_UNKNOWN
;
5815 /* GCC creates a pseudo-section whose name describes the ABI. */
5816 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5817 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5819 /* If we have no useful BFD information, use the ABI from the last
5820 MIPS architecture (if there is one). */
5821 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5822 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5824 /* Try the architecture for any hint of the correct ABI. */
5825 if (found_abi
== MIPS_ABI_UNKNOWN
5826 && info
.bfd_arch_info
!= NULL
5827 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5829 switch (info
.bfd_arch_info
->mach
)
5831 case bfd_mach_mips3900
:
5832 found_abi
= MIPS_ABI_EABI32
;
5834 case bfd_mach_mips4100
:
5835 case bfd_mach_mips5000
:
5836 found_abi
= MIPS_ABI_EABI64
;
5838 case bfd_mach_mips8000
:
5839 case bfd_mach_mips10000
:
5840 /* On Irix, ELF64 executables use the N64 ABI. The
5841 pseudo-sections which describe the ABI aren't present
5842 on IRIX. (Even for executables created by gcc.) */
5843 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5844 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5845 found_abi
= MIPS_ABI_N64
;
5847 found_abi
= MIPS_ABI_N32
;
5852 /* Default 64-bit objects to N64 instead of O32. */
5853 if (found_abi
== MIPS_ABI_UNKNOWN
5854 && info
.abfd
!= NULL
5855 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5856 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5857 found_abi
= MIPS_ABI_N64
;
5860 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5863 /* What has the user specified from the command line? */
5864 wanted_abi
= global_mips_abi ();
5866 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5869 /* Now that we have found what the ABI for this binary would be,
5870 check whether the user is overriding it. */
5871 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5872 mips_abi
= wanted_abi
;
5873 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5874 mips_abi
= found_abi
;
5876 mips_abi
= MIPS_ABI_O32
;
5878 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5881 /* Also used when doing an architecture lookup. */
5883 fprintf_unfiltered (gdb_stdlog
,
5884 "mips_gdbarch_init: "
5885 "mips64_transfers_32bit_regs_p = %d\n",
5886 mips64_transfers_32bit_regs_p
);
5888 /* Determine the MIPS FPU type. */
5891 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5892 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5893 Tag_GNU_MIPS_ABI_FP
);
5894 #endif /* HAVE_ELF */
5896 if (!mips_fpu_type_auto
)
5897 fpu_type
= mips_fpu_type
;
5898 else if (elf_fpu_type
!= 0)
5900 switch (elf_fpu_type
)
5903 fpu_type
= MIPS_FPU_DOUBLE
;
5906 fpu_type
= MIPS_FPU_SINGLE
;
5910 /* Soft float or unknown. */
5911 fpu_type
= MIPS_FPU_NONE
;
5915 else if (info
.bfd_arch_info
!= NULL
5916 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5917 switch (info
.bfd_arch_info
->mach
)
5919 case bfd_mach_mips3900
:
5920 case bfd_mach_mips4100
:
5921 case bfd_mach_mips4111
:
5922 case bfd_mach_mips4120
:
5923 fpu_type
= MIPS_FPU_NONE
;
5925 case bfd_mach_mips4650
:
5926 fpu_type
= MIPS_FPU_SINGLE
;
5929 fpu_type
= MIPS_FPU_DOUBLE
;
5932 else if (arches
!= NULL
)
5933 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5935 fpu_type
= MIPS_FPU_DOUBLE
;
5937 fprintf_unfiltered (gdb_stdlog
,
5938 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5940 /* Check for blatant incompatibilities. */
5942 /* If we have only 32-bit registers, then we can't debug a 64-bit
5944 if (info
.target_desc
5945 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5946 && mips_abi
!= MIPS_ABI_EABI32
5947 && mips_abi
!= MIPS_ABI_O32
)
5949 if (tdesc_data
!= NULL
)
5950 tdesc_data_cleanup (tdesc_data
);
5954 /* Try to find a pre-existing architecture. */
5955 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5957 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5959 /* MIPS needs to be pedantic about which ABI the object is
5961 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5963 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5965 /* Need to be pedantic about which register virtual size is
5967 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5968 != mips64_transfers_32bit_regs_p
)
5970 /* Be pedantic about which FPU is selected. */
5971 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5974 if (tdesc_data
!= NULL
)
5975 tdesc_data_cleanup (tdesc_data
);
5976 return arches
->gdbarch
;
5979 /* Need a new architecture. Fill in a target specific vector. */
5980 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5981 gdbarch
= gdbarch_alloc (&info
, tdep
);
5982 tdep
->elf_flags
= elf_flags
;
5983 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5984 tdep
->found_abi
= found_abi
;
5985 tdep
->mips_abi
= mips_abi
;
5986 tdep
->mips_fpu_type
= fpu_type
;
5987 tdep
->register_size_valid_p
= 0;
5988 tdep
->register_size
= 0;
5989 tdep
->gregset
= NULL
;
5990 tdep
->gregset64
= NULL
;
5991 tdep
->fpregset
= NULL
;
5992 tdep
->fpregset64
= NULL
;
5994 if (info
.target_desc
)
5996 /* Some useful properties can be inferred from the target. */
5997 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5999 tdep
->register_size_valid_p
= 1;
6000 tdep
->register_size
= 4;
6002 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
6004 tdep
->register_size_valid_p
= 1;
6005 tdep
->register_size
= 8;
6009 /* Initially set everything according to the default ABI/ISA. */
6010 set_gdbarch_short_bit (gdbarch
, 16);
6011 set_gdbarch_int_bit (gdbarch
, 32);
6012 set_gdbarch_float_bit (gdbarch
, 32);
6013 set_gdbarch_double_bit (gdbarch
, 64);
6014 set_gdbarch_long_double_bit (gdbarch
, 64);
6015 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6016 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6017 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6019 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6020 mips_ax_pseudo_register_collect
);
6021 set_gdbarch_ax_pseudo_register_push_stack
6022 (gdbarch
, mips_ax_pseudo_register_push_stack
);
6024 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6025 mips_elf_make_msymbol_special
);
6027 /* Fill in the OS dependant register numbers and names. */
6029 const char **reg_names
;
6030 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
6031 struct mips_regnum
);
6032 if (tdesc_has_registers (info
.target_desc
))
6034 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6035 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6036 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6037 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6038 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6039 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6040 regnum
->fp_control_status
= 70;
6041 regnum
->fp_implementation_revision
= 71;
6042 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
6045 else if (info
.osabi
== GDB_OSABI_IRIX
)
6050 regnum
->badvaddr
= 66;
6053 regnum
->fp_control_status
= 69;
6054 regnum
->fp_implementation_revision
= 70;
6056 reg_names
= mips_irix_reg_names
;
6060 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6061 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6062 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6063 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6064 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6065 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6066 regnum
->fp_control_status
= 70;
6067 regnum
->fp_implementation_revision
= 71;
6069 if (info
.bfd_arch_info
!= NULL
6070 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6071 reg_names
= mips_tx39_reg_names
;
6073 reg_names
= mips_generic_reg_names
;
6075 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
6076 replaced by gdbarch_read_pc? */
6077 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6078 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6079 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6080 set_gdbarch_num_regs (gdbarch
, num_regs
);
6081 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6082 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6083 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
6084 tdep
->mips_processor_reg_names
= reg_names
;
6085 tdep
->regnum
= regnum
;
6091 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6092 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6093 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6094 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6095 tdep
->default_mask_address_p
= 0;
6096 set_gdbarch_long_bit (gdbarch
, 32);
6097 set_gdbarch_ptr_bit (gdbarch
, 32);
6098 set_gdbarch_long_long_bit (gdbarch
, 64);
6101 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6102 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6103 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6104 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6105 tdep
->default_mask_address_p
= 0;
6106 set_gdbarch_long_bit (gdbarch
, 32);
6107 set_gdbarch_ptr_bit (gdbarch
, 32);
6108 set_gdbarch_long_long_bit (gdbarch
, 64);
6110 case MIPS_ABI_EABI32
:
6111 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6112 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6113 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6114 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6115 tdep
->default_mask_address_p
= 0;
6116 set_gdbarch_long_bit (gdbarch
, 32);
6117 set_gdbarch_ptr_bit (gdbarch
, 32);
6118 set_gdbarch_long_long_bit (gdbarch
, 64);
6120 case MIPS_ABI_EABI64
:
6121 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6122 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6123 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6124 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6125 tdep
->default_mask_address_p
= 0;
6126 set_gdbarch_long_bit (gdbarch
, 64);
6127 set_gdbarch_ptr_bit (gdbarch
, 64);
6128 set_gdbarch_long_long_bit (gdbarch
, 64);
6131 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6132 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6133 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6134 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6135 tdep
->default_mask_address_p
= 0;
6136 set_gdbarch_long_bit (gdbarch
, 32);
6137 set_gdbarch_ptr_bit (gdbarch
, 32);
6138 set_gdbarch_long_long_bit (gdbarch
, 64);
6139 set_gdbarch_long_double_bit (gdbarch
, 128);
6140 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6143 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6144 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6145 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6146 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6147 tdep
->default_mask_address_p
= 0;
6148 set_gdbarch_long_bit (gdbarch
, 64);
6149 set_gdbarch_ptr_bit (gdbarch
, 64);
6150 set_gdbarch_long_long_bit (gdbarch
, 64);
6151 set_gdbarch_long_double_bit (gdbarch
, 128);
6152 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6155 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6158 /* GCC creates a pseudo-section whose name specifies the size of
6159 longs, since -mlong32 or -mlong64 may be used independent of
6160 other options. How those options affect pointer sizes is ABI and
6161 architecture dependent, so use them to override the default sizes
6162 set by the ABI. This table shows the relationship between ABI,
6163 -mlongXX, and size of pointers:
6165 ABI -mlongXX ptr bits
6166 --- -------- --------
6180 Note that for o32 and eabi32, pointers are always 32 bits
6181 regardless of any -mlongXX option. For all others, pointers and
6182 longs are the same, as set by -mlongXX or set by defaults. */
6184 if (info
.abfd
!= NULL
)
6188 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6191 set_gdbarch_long_bit (gdbarch
, long_bit
);
6195 case MIPS_ABI_EABI32
:
6200 case MIPS_ABI_EABI64
:
6201 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6204 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6209 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6210 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6213 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6214 flag in object files because to do so would make it impossible to
6215 link with libraries compiled without "-gp32". This is
6216 unnecessarily restrictive.
6218 We could solve this problem by adding "-gp32" multilibs to gcc,
6219 but to set this flag before gcc is built with such multilibs will
6220 break too many systems.''
6222 But even more unhelpfully, the default linker output target for
6223 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6224 for 64-bit programs - you need to change the ABI to change this,
6225 and not all gcc targets support that currently. Therefore using
6226 this flag to detect 32-bit mode would do the wrong thing given
6227 the current gcc - it would make GDB treat these 64-bit programs
6228 as 32-bit programs by default. */
6230 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6231 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6233 /* Add/remove bits from an address. The MIPS needs be careful to
6234 ensure that all 32 bit addresses are sign extended to 64 bits. */
6235 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6237 /* Unwind the frame. */
6238 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6239 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
6240 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
6242 /* Map debug register numbers onto internal register numbers. */
6243 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6244 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6245 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6246 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6247 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6248 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6250 /* MIPS version of CALL_DUMMY. */
6252 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6253 replaced by a command, and all targets will default to on stack
6254 (regardless of the stack's execute status). */
6255 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6256 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6258 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6259 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6260 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6262 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6263 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6265 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6267 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6269 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6270 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6271 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6273 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6275 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6277 if (mips_abi
== MIPS_ABI_N32
)
6278 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6279 else if (mips_abi
== MIPS_ABI_N64
)
6280 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6282 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6284 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6285 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6286 need to all be folded into the target vector. Since they are
6287 being used as guards for target_stopped_by_watchpoint, why not have
6288 target_stopped_by_watchpoint return the type of watchpoint that the code
6290 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6292 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6294 set_gdbarch_single_step_through_delay (gdbarch
,
6295 mips_single_step_through_delay
);
6297 /* Virtual tables. */
6298 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6300 mips_register_g_packet_guesses (gdbarch
);
6302 /* Hook in OS ABI-specific overrides, if they have been registered. */
6303 info
.tdep_info
= (void *) tdesc_data
;
6304 gdbarch_init_osabi (info
, gdbarch
);
6306 /* Unwind the frame. */
6307 dwarf2_append_unwinders (gdbarch
);
6308 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6309 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6310 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6311 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6312 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6313 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6314 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6318 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6319 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6321 /* Override the normal target description methods to handle our
6322 dual real and pseudo registers. */
6323 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6324 set_gdbarch_register_reggroup_p (gdbarch
,
6325 mips_tdesc_register_reggroup_p
);
6327 num_regs
= gdbarch_num_regs (gdbarch
);
6328 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6329 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6330 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6333 /* Add ABI-specific aliases for the registers. */
6334 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6335 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6336 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6337 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6339 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6340 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6341 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6343 /* Add some other standard aliases. */
6344 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6345 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6346 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6348 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6349 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6350 value_of_mips_user_reg
,
6351 &mips_numeric_register_aliases
[i
].regnum
);
6357 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6359 struct gdbarch_info info
;
6361 /* Force the architecture to update, and (if it's a MIPS architecture)
6362 mips_gdbarch_init will take care of the rest. */
6363 gdbarch_info_init (&info
);
6364 gdbarch_update_p (info
);
6367 /* Print out which MIPS ABI is in use. */
6370 show_mips_abi (struct ui_file
*file
,
6372 struct cmd_list_element
*ignored_cmd
,
6373 const char *ignored_value
)
6375 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6378 "The MIPS ABI is unknown because the current architecture "
6382 enum mips_abi global_abi
= global_mips_abi ();
6383 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6384 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6386 if (global_abi
== MIPS_ABI_UNKNOWN
)
6389 "The MIPS ABI is set automatically (currently \"%s\").\n",
6391 else if (global_abi
== actual_abi
)
6394 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6398 /* Probably shouldn't happen... */
6399 fprintf_filtered (file
,
6400 "The (auto detected) MIPS ABI \"%s\" is in use "
6401 "even though the user setting was \"%s\".\n",
6402 actual_abi_str
, mips_abi_strings
[global_abi
]);
6408 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6410 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6414 int ef_mips_32bitmode
;
6415 /* Determine the ISA. */
6416 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6434 /* Determine the size of a pointer. */
6435 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6436 fprintf_unfiltered (file
,
6437 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6439 fprintf_unfiltered (file
,
6440 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6442 fprintf_unfiltered (file
,
6443 "mips_dump_tdep: ef_mips_arch = %d\n",
6445 fprintf_unfiltered (file
,
6446 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6447 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6448 fprintf_unfiltered (file
,
6450 "mips_mask_address_p() %d (default %d)\n",
6451 mips_mask_address_p (tdep
),
6452 tdep
->default_mask_address_p
);
6454 fprintf_unfiltered (file
,
6455 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6456 MIPS_DEFAULT_FPU_TYPE
,
6457 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6458 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6459 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6461 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6462 MIPS_EABI (gdbarch
));
6463 fprintf_unfiltered (file
,
6464 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6465 MIPS_FPU_TYPE (gdbarch
),
6466 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6467 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6468 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6472 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6475 _initialize_mips_tdep (void)
6477 static struct cmd_list_element
*mipsfpulist
= NULL
;
6478 struct cmd_list_element
*c
;
6480 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6481 if (MIPS_ABI_LAST
+ 1
6482 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6483 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6485 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6487 mips_pdr_data
= register_objfile_data ();
6489 /* Create feature sets with the appropriate properties. The values
6490 are not important. */
6491 mips_tdesc_gp32
= allocate_target_description ();
6492 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6494 mips_tdesc_gp64
= allocate_target_description ();
6495 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6497 /* Add root prefix command for all "set mips"/"show mips" commands. */
6498 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6499 _("Various MIPS specific commands."),
6500 &setmipscmdlist
, "set mips ", 0, &setlist
);
6502 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6503 _("Various MIPS specific commands."),
6504 &showmipscmdlist
, "show mips ", 0, &showlist
);
6506 /* Allow the user to override the ABI. */
6507 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6508 &mips_abi_string
, _("\
6509 Set the MIPS ABI used by this program."), _("\
6510 Show the MIPS ABI used by this program."), _("\
6511 This option can be set to one of:\n\
6512 auto - the default ABI associated with the current binary\n\
6521 &setmipscmdlist
, &showmipscmdlist
);
6523 /* Let the user turn off floating point and set the fence post for
6524 heuristic_proc_start. */
6526 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6527 _("Set use of MIPS floating-point coprocessor."),
6528 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6529 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6530 _("Select single-precision MIPS floating-point coprocessor."),
6532 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6533 _("Select double-precision MIPS floating-point coprocessor."),
6535 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6536 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6537 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6538 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6539 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6540 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6541 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6542 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6543 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6544 _("Select MIPS floating-point coprocessor automatically."),
6546 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6547 _("Show current use of MIPS floating-point coprocessor target."),
6550 /* We really would like to have both "0" and "unlimited" work, but
6551 command.c doesn't deal with that. So make it a var_zinteger
6552 because the user can always use "999999" or some such for unlimited. */
6553 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6554 &heuristic_fence_post
, _("\
6555 Set the distance searched for the start of a function."), _("\
6556 Show the distance searched for the start of a function."), _("\
6557 If you are debugging a stripped executable, GDB needs to search through the\n\
6558 program for the start of a function. This command sets the distance of the\n\
6559 search. The only need to set it is when debugging a stripped executable."),
6560 reinit_frame_cache_sfunc
,
6561 NULL
, /* FIXME: i18n: The distance searched for
6562 the start of a function is %s. */
6563 &setlist
, &showlist
);
6565 /* Allow the user to control whether the upper bits of 64-bit
6566 addresses should be zeroed. */
6567 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6568 &mask_address_var
, _("\
6569 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6570 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6571 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
6572 allow GDB to determine the correct value."),
6573 NULL
, show_mask_address
,
6574 &setmipscmdlist
, &showmipscmdlist
);
6576 /* Allow the user to control the size of 32 bit registers within the
6577 raw remote packet. */
6578 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6579 &mips64_transfers_32bit_regs_p
, _("\
6580 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6582 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6584 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6585 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6586 64 bits for others. Use \"off\" to disable compatibility mode"),
6587 set_mips64_transfers_32bit_regs
,
6588 NULL
, /* FIXME: i18n: Compatibility with 64-bit
6589 MIPS target that transfers 32-bit
6590 quantities is %s. */
6591 &setlist
, &showlist
);
6593 /* Debug this files internals. */
6594 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6596 Set mips debugging."), _("\
6597 Show mips debugging."), _("\
6598 When non-zero, mips specific debugging is enabled."),
6600 NULL
, /* FIXME: i18n: Mips debugging is
6602 &setdebuglist
, &showdebuglist
);