1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
28 #include "gdb_assert.h"
40 #include "arch-utils.h"
43 #include "mips-tdep.h"
45 #include "reggroups.h"
46 #include "opcode/mips.h"
50 #include "sim-regno.h"
53 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
54 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
56 /* A useful bit in the CP0 status register (PS_REGNUM). */
57 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
58 #define ST0_FR (1 << 26)
60 /* The sizes of floating point registers. */
64 MIPS_FPU_SINGLE_REGSIZE
= 4,
65 MIPS_FPU_DOUBLE_REGSIZE
= 8
69 static const char *mips_abi_string
;
71 static const char *mips_abi_strings
[] = {
82 struct frame_extra_info
84 mips_extra_func_info_t proc_desc
;
88 /* Various MIPS ISA options (related to stack analysis) can be
89 overridden dynamically. Establish an enum/array for managing
92 static const char size_auto
[] = "auto";
93 static const char size_32
[] = "32";
94 static const char size_64
[] = "64";
96 static const char *size_enums
[] = {
103 /* Some MIPS boards don't support floating point while others only
104 support single-precision floating-point operations. See also
105 FP_REGISTER_DOUBLE. */
109 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
110 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
111 MIPS_FPU_NONE
/* No floating point. */
114 #ifndef MIPS_DEFAULT_FPU_TYPE
115 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
117 static int mips_fpu_type_auto
= 1;
118 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
120 static int mips_debug
= 0;
122 /* MIPS specific per-architecture information */
125 /* from the elf header */
129 enum mips_abi mips_abi
;
130 enum mips_abi found_abi
;
131 enum mips_fpu_type mips_fpu_type
;
132 int mips_last_arg_regnum
;
133 int mips_last_fp_arg_regnum
;
134 int mips_default_saved_regsize
;
135 int mips_fp_register_double
;
136 int mips_default_stack_argsize
;
137 int default_mask_address_p
;
138 /* Is the target using 64-bit raw integer registers but only
139 storing a left-aligned 32-bit value in each? */
140 int mips64_transfers_32bit_regs_p
;
141 /* Indexes for various registers. IRIX and embedded have
142 different values. This contains the "public" fields. Don't
143 add any that do not need to be public. */
144 const struct mips_regnum
*regnum
;
145 /* Register names table for the current register set. */
146 const char **mips_processor_reg_names
;
149 const struct mips_regnum
*
150 mips_regnum (struct gdbarch
*gdbarch
)
152 return gdbarch_tdep (gdbarch
)->regnum
;
156 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
158 return mips_regnum (gdbarch
)->fp0
+ 12;
161 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
162 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
164 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
166 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
168 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
170 /* Return the currently configured (or set) saved register size. */
172 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
174 static const char *mips_saved_regsize_string
= size_auto
;
176 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
178 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
179 functions to test, set, or clear bit 0 of addresses. */
182 is_mips16_addr (CORE_ADDR addr
)
188 make_mips16_addr (CORE_ADDR addr
)
194 unmake_mips16_addr (CORE_ADDR addr
)
196 return ((addr
) & ~1);
199 /* Return the contents of register REGNUM as a signed integer. */
202 read_signed_register (int regnum
)
204 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
205 deprecated_read_register_gen (regnum
, buf
);
206 return (extract_signed_integer (buf
, register_size (current_gdbarch
, regnum
)));
210 read_signed_register_pid (int regnum
, ptid_t ptid
)
215 if (ptid_equal (ptid
, inferior_ptid
))
216 return read_signed_register (regnum
);
218 save_ptid
= inferior_ptid
;
220 inferior_ptid
= ptid
;
222 retval
= read_signed_register (regnum
);
224 inferior_ptid
= save_ptid
;
229 /* Return the MIPS ABI associated with GDBARCH. */
231 mips_abi (struct gdbarch
*gdbarch
)
233 return gdbarch_tdep (gdbarch
)->mips_abi
;
237 mips_regsize (struct gdbarch
*gdbarch
)
239 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
240 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
244 mips_saved_regsize (void)
246 if (mips_saved_regsize_string
== size_auto
)
247 return MIPS_DEFAULT_SAVED_REGSIZE
;
248 else if (mips_saved_regsize_string
== size_64
)
250 else /* if (mips_saved_regsize_string == size_32) */
254 /* Functions for setting and testing a bit in a minimal symbol that
255 marks it as 16-bit function. The MSB of the minimal symbol's
256 "info" field is used for this purpose.
258 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
259 i.e. refers to a 16-bit function, and sets a "special" bit in a
260 minimal symbol to mark it as a 16-bit function
262 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
265 mips_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
267 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
269 MSYMBOL_INFO (msym
) = (char *)
270 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
271 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
276 msymbol_is_special (struct minimal_symbol
*msym
)
278 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
281 /* XFER a value from the big/little/left end of the register.
282 Depending on the size of the value it might occupy the entire
283 register or just part of it. Make an allowance for this, aligning
284 things accordingly. */
287 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
288 enum bfd_endian endian
, bfd_byte
*in
, const bfd_byte
*out
,
291 bfd_byte reg
[MAX_REGISTER_SIZE
];
293 gdb_assert (reg_num
>= NUM_REGS
);
294 /* Need to transfer the left or right part of the register, based on
295 the targets byte order. */
299 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
301 case BFD_ENDIAN_LITTLE
:
304 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
308 internal_error (__FILE__
, __LINE__
, "bad switch");
311 fprintf_unfiltered (gdb_stderr
,
312 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
313 reg_num
, reg_offset
, buf_offset
, length
);
314 if (mips_debug
&& out
!= NULL
)
317 fprintf_unfiltered (gdb_stdlog
, "out ");
318 for (i
= 0; i
< length
; i
++)
319 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
322 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
, in
+ buf_offset
);
324 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
, out
+ buf_offset
);
325 if (mips_debug
&& in
!= NULL
)
328 fprintf_unfiltered (gdb_stdlog
, "in ");
329 for (i
= 0; i
< length
; i
++)
330 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
333 fprintf_unfiltered (gdb_stdlog
, "\n");
336 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
337 compatiblity mode. A return value of 1 means that we have
338 physical 64-bit registers, but should treat them as 32-bit registers. */
341 mips2_fp_compat (void)
343 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
345 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 4)
349 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
350 in all the places we deal with FP registers. PR gdb/413. */
351 /* Otherwise check the FR bit in the status register - it controls
352 the FP compatiblity mode. If it is clear we are in compatibility
354 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
361 /* Indicate that the ABI makes use of double-precision registers
362 provided by the FPU (rather than combining pairs of registers to
363 form double-precision values). See also MIPS_FPU_TYPE. */
364 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
366 /* The amount of space reserved on the stack for registers. This is
367 different to MIPS_SAVED_REGSIZE as it determines the alignment of
368 data allocated after the registers have run out. */
370 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
372 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
374 static const char *mips_stack_argsize_string
= size_auto
;
377 mips_stack_argsize (void)
379 if (mips_stack_argsize_string
== size_auto
)
380 return MIPS_DEFAULT_STACK_ARGSIZE
;
381 else if (mips_stack_argsize_string
== size_64
)
383 else /* if (mips_stack_argsize_string == size_32) */
387 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
389 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
391 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
392 struct frame_info
*, int);
394 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
396 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
398 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
400 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
401 struct frame_info
*next_frame
,
404 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
405 mips_extra_func_info_t proc_desc
);
407 static struct type
*mips_float_register_type (void);
408 static struct type
*mips_double_register_type (void);
410 /* The list of available "set mips " and "show mips " commands */
412 static struct cmd_list_element
*setmipscmdlist
= NULL
;
413 static struct cmd_list_element
*showmipscmdlist
= NULL
;
415 /* Integer registers 0 thru 31 are handled explicitly by
416 mips_register_name(). Processor specific registers 32 and above
417 are listed in the followign tables. */
419 enum { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
423 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
424 "sr", "lo", "hi", "bad", "cause","pc",
425 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
426 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
427 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
428 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
429 "fsr", "fir", ""/*"fp"*/, "",
430 "", "", "", "", "", "", "", "",
431 "", "", "", "", "", "", "", "",
434 /* Names of IDT R3041 registers. */
436 static const char *mips_r3041_reg_names
[] = {
437 "sr", "lo", "hi", "bad", "cause","pc",
438 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
439 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
440 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
441 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
442 "fsr", "fir", "",/*"fp"*/ "",
443 "", "", "bus", "ccfg", "", "", "", "",
444 "", "", "port", "cmp", "", "", "epc", "prid",
447 /* Names of tx39 registers. */
449 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
450 "sr", "lo", "hi", "bad", "cause","pc",
451 "", "", "", "", "", "", "", "",
452 "", "", "", "", "", "", "", "",
453 "", "", "", "", "", "", "", "",
454 "", "", "", "", "", "", "", "",
456 "", "", "", "", "", "", "", "",
457 "", "", "config", "cache", "debug", "depc", "epc", ""
460 /* Names of IRIX registers. */
461 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
462 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
463 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
464 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
465 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
466 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
470 /* Return the name of the register corresponding to REGNO. */
472 mips_register_name (int regno
)
474 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
475 /* GPR names for all ABIs other than n32/n64. */
476 static char *mips_gpr_names
[] = {
477 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
478 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
479 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
480 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
483 /* GPR names for n32 and n64 ABIs. */
484 static char *mips_n32_n64_gpr_names
[] = {
485 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
486 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
487 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
488 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
491 enum mips_abi abi
= mips_abi (current_gdbarch
);
493 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
494 don't make the raw register names visible. */
495 int rawnum
= regno
% NUM_REGS
;
496 if (regno
< NUM_REGS
)
499 /* The MIPS integer registers are always mapped from 0 to 31. The
500 names of the registers (which reflects the conventions regarding
501 register use) vary depending on the ABI. */
502 if (0 <= rawnum
&& rawnum
< 32)
504 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
505 return mips_n32_n64_gpr_names
[rawnum
];
507 return mips_gpr_names
[rawnum
];
509 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
511 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
512 return tdep
->mips_processor_reg_names
[rawnum
- 32];
515 internal_error (__FILE__
, __LINE__
,
516 "mips_register_name: bad register number %d", rawnum
);
519 /* Return the groups that a MIPS register can be categorised into. */
522 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
523 struct reggroup
*reggroup
)
528 int rawnum
= regnum
% NUM_REGS
;
529 int pseudo
= regnum
/ NUM_REGS
;
530 if (reggroup
== all_reggroup
)
532 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
533 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
534 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
535 (gdbarch), as not all architectures are multi-arch. */
536 raw_p
= rawnum
< NUM_REGS
;
537 if (REGISTER_NAME (regnum
) == NULL
538 || REGISTER_NAME (regnum
)[0] == '\0')
540 if (reggroup
== float_reggroup
)
541 return float_p
&& pseudo
;
542 if (reggroup
== vector_reggroup
)
543 return vector_p
&& pseudo
;
544 if (reggroup
== general_reggroup
)
545 return (!vector_p
&& !float_p
) && pseudo
;
546 /* Save the pseudo registers. Need to make certain that any code
547 extracting register values from a saved register cache also uses
549 if (reggroup
== save_reggroup
)
550 return raw_p
&& pseudo
;
551 /* Restore the same pseudo register. */
552 if (reggroup
== restore_reggroup
)
553 return raw_p
&& pseudo
;
557 /* Map the symbol table registers which live in the range [1 *
558 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
559 registers. Take care of alignment and size problems. */
562 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
563 int cookednum
, void *buf
)
565 int rawnum
= cookednum
% NUM_REGS
;
566 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
567 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
568 return regcache_raw_read (regcache
, rawnum
, buf
);
569 else if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, cookednum
))
571 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
572 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
573 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
575 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
578 internal_error (__FILE__
, __LINE__
, "bad register size");
582 mips_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
583 int cookednum
, const void *buf
)
585 int rawnum
= cookednum
% NUM_REGS
;
586 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
587 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
588 return regcache_raw_write (regcache
, rawnum
, buf
);
589 else if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, cookednum
))
591 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
592 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
593 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
595 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
598 internal_error (__FILE__
, __LINE__
, "bad register size");
601 /* Table to translate MIPS16 register field to actual register number. */
602 static int mips16_to_32_reg
[8] =
603 {16, 17, 2, 3, 4, 5, 6, 7};
605 /* Heuristic_proc_start may hunt through the text section for a long
606 time across a 2400 baud serial line. Allows the user to limit this
609 static unsigned int heuristic_fence_post
= 0;
611 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
612 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
613 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
614 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
615 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
616 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
617 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
618 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
619 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
620 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
621 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
622 this will corrupt pdr.iline. Fortunately we don't use it. */
623 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
624 #define _PROC_MAGIC_ 0x0F0F0F0F
625 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
626 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
628 struct linked_proc_info
630 struct mips_extra_func_info info
;
631 struct linked_proc_info
*next
;
633 *linked_proc_desc_table
= NULL
;
635 /* Number of bytes of storage in the actual machine representation for
636 register N. NOTE: This defines the pseudo register type so need to
637 rebuild the architecture vector. */
639 static int mips64_transfers_32bit_regs_p
= 0;
642 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
643 struct cmd_list_element
*c
)
645 struct gdbarch_info info
;
646 gdbarch_info_init (&info
);
647 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
648 instead of relying on globals. Doing that would let generic code
649 handle the search for this specific architecture. */
650 if (!gdbarch_update_p (info
))
652 mips64_transfers_32bit_regs_p
= 0;
653 error ("32-bit compatibility mode not supported");
657 /* Convert to/from a register and the corresponding memory value. */
660 mips_convert_register_p (int regnum
, struct type
*type
)
662 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
663 && register_size (current_gdbarch
, regnum
) == 4
664 && (regnum
) >= mips_regnum (current_gdbarch
)->fp0
&& (regnum
) < mips_regnum (current_gdbarch
)->fp0
+ 32
665 && TYPE_CODE(type
) == TYPE_CODE_FLT
666 && TYPE_LENGTH(type
) == 8);
670 mips_register_to_value (struct frame_info
*frame
, int regnum
,
671 struct type
*type
, void *to
)
673 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
674 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
678 mips_value_to_register (struct frame_info
*frame
, int regnum
,
679 struct type
*type
, const void *from
)
681 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
682 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
685 /* Return the GDB type object for the "standard" data type of data in
689 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
691 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
692 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
693 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
695 /* The floating-point registers raw, or cooked, always match
696 mips_regsize(), and also map 1:1, byte for byte. */
697 switch (gdbarch_byte_order (gdbarch
))
700 if (mips_regsize (gdbarch
) == 4)
701 return builtin_type_ieee_single_big
;
703 return builtin_type_ieee_double_big
;
704 case BFD_ENDIAN_LITTLE
:
705 if (mips_regsize (gdbarch
) == 4)
706 return builtin_type_ieee_single_little
;
708 return builtin_type_ieee_double_little
;
709 case BFD_ENDIAN_UNKNOWN
:
711 internal_error (__FILE__
, __LINE__
, "bad switch");
714 else if (regnum
>= (NUM_REGS
+ mips_regnum (current_gdbarch
)->fp_control_status
)
715 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
716 /* The pseudo/cooked view of the embedded registers is always
717 32-bit. The raw view is handled below. */
718 return builtin_type_int32
;
719 else if (regnum
>= NUM_REGS
&& mips_regsize (gdbarch
)
720 && gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
721 /* The target, while using a 64-bit register buffer, is only
722 transfering 32-bits of each integer register. Reflect this in
723 the cooked/pseudo register value. */
724 return builtin_type_int32
;
725 else if (mips_regsize (gdbarch
) == 8)
727 return builtin_type_int64
;
730 return builtin_type_int32
;
733 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
738 return read_signed_register (SP_REGNUM
);
741 /* Should the upper word of 64-bit addresses be zeroed? */
742 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
745 mips_mask_address_p (void)
747 switch (mask_address_var
)
749 case AUTO_BOOLEAN_TRUE
:
751 case AUTO_BOOLEAN_FALSE
:
754 case AUTO_BOOLEAN_AUTO
:
755 return MIPS_DEFAULT_MASK_ADDRESS_P
;
757 internal_error (__FILE__
, __LINE__
,
758 "mips_mask_address_p: bad switch");
764 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
766 switch (mask_address_var
)
768 case AUTO_BOOLEAN_TRUE
:
769 printf_filtered ("The 32 bit mips address mask is enabled\n");
771 case AUTO_BOOLEAN_FALSE
:
772 printf_filtered ("The 32 bit mips address mask is disabled\n");
774 case AUTO_BOOLEAN_AUTO
:
775 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
776 mips_mask_address_p () ? "enabled" : "disabled");
779 internal_error (__FILE__
, __LINE__
,
780 "show_mask_address: bad switch");
785 /* Should call_function allocate stack space for a struct return? */
788 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
790 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
793 /* Should call_function pass struct by reference?
794 For each architecture, structs are passed either by
795 value or by reference, depending on their size. */
798 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
800 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
801 int len
= TYPE_LENGTH (check_typedef (type
));
803 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
804 return (len
> MIPS_SAVED_REGSIZE
);
810 mips_n32n64_reg_struct_has_addr (int gcc_p
, struct type
*type
)
812 return 0; /* Assumption: N32/N64 never passes struct by ref. */
816 mips_o32_reg_struct_has_addr (int gcc_p
, struct type
*type
)
818 return 0; /* Assumption: O32/O64 never passes struct by ref. */
821 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
824 pc_is_mips16 (bfd_vma memaddr
)
826 struct minimal_symbol
*sym
;
828 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
829 if (is_mips16_addr (memaddr
))
832 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
833 the high bit of the info field. Use this to decide if the function is
834 MIPS16 or normal MIPS. */
835 sym
= lookup_minimal_symbol_by_pc (memaddr
);
837 return msymbol_is_special (sym
);
842 /* MIPS believes that the PC has a sign extended value. Perhaphs the
843 all registers should be sign extended for simplicity? */
846 mips_read_pc (ptid_t ptid
)
848 return read_signed_register_pid (PC_REGNUM
, ptid
);
851 /* This returns the PC of the first inst after the prologue. If we can't
852 find the prologue, then return 0. */
855 after_prologue (CORE_ADDR pc
,
856 mips_extra_func_info_t proc_desc
)
858 struct symtab_and_line sal
;
859 CORE_ADDR func_addr
, func_end
;
861 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
862 to read the stack pointer from the current machine state, because
863 the current machine state has nothing to do with the information
864 we need from the proc_desc; and the process may or may not exist
867 proc_desc
= find_proc_desc (pc
, NULL
, 0);
871 /* If function is frameless, then we need to do it the hard way. I
872 strongly suspect that frameless always means prologueless... */
873 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
874 && PROC_FRAME_OFFSET (proc_desc
) == 0)
878 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
879 return 0; /* Unknown */
881 sal
= find_pc_line (func_addr
, 0);
883 if (sal
.end
< func_end
)
886 /* The line after the prologue is after the end of the function. In this
887 case, tell the caller to find the prologue the hard way. */
892 /* Decode a MIPS32 instruction that saves a register in the stack, and
893 set the appropriate bit in the general register mask or float register mask
894 to indicate which register is saved. This is a helper function
895 for mips_find_saved_regs. */
898 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
899 unsigned long *float_mask
)
903 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
904 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
905 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
907 /* It might be possible to use the instruction to
908 find the offset, rather than the code below which
909 is based on things being in a certain order in the
910 frame, but figuring out what the instruction's offset
911 is relative to might be a little tricky. */
912 reg
= (inst
& 0x001f0000) >> 16;
913 *gen_mask
|= (1 << reg
);
915 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
916 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
917 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
920 reg
= ((inst
& 0x001f0000) >> 16);
921 *float_mask
|= (1 << reg
);
925 /* Decode a MIPS16 instruction that saves a register in the stack, and
926 set the appropriate bit in the general register or float register mask
927 to indicate which register is saved. This is a helper function
928 for mips_find_saved_regs. */
931 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
933 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
935 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
936 *gen_mask
|= (1 << reg
);
938 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
940 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
941 *gen_mask
|= (1 << reg
);
943 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
944 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
945 *gen_mask
|= (1 << RA_REGNUM
);
949 /* Fetch and return instruction from the specified location. If the PC
950 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
953 mips_fetch_instruction (CORE_ADDR addr
)
955 char buf
[MIPS_INSTLEN
];
959 if (pc_is_mips16 (addr
))
961 instlen
= MIPS16_INSTLEN
;
962 addr
= unmake_mips16_addr (addr
);
965 instlen
= MIPS_INSTLEN
;
966 status
= read_memory_nobpt (addr
, buf
, instlen
);
968 memory_error (status
, addr
);
969 return extract_unsigned_integer (buf
, instlen
);
973 /* These the fields of 32 bit mips instructions */
974 #define mips32_op(x) (x >> 26)
975 #define itype_op(x) (x >> 26)
976 #define itype_rs(x) ((x >> 21) & 0x1f)
977 #define itype_rt(x) ((x >> 16) & 0x1f)
978 #define itype_immediate(x) (x & 0xffff)
980 #define jtype_op(x) (x >> 26)
981 #define jtype_target(x) (x & 0x03ffffff)
983 #define rtype_op(x) (x >> 26)
984 #define rtype_rs(x) ((x >> 21) & 0x1f)
985 #define rtype_rt(x) ((x >> 16) & 0x1f)
986 #define rtype_rd(x) ((x >> 11) & 0x1f)
987 #define rtype_shamt(x) ((x >> 6) & 0x1f)
988 #define rtype_funct(x) (x & 0x3f)
991 mips32_relative_offset (unsigned long inst
)
994 x
= itype_immediate (inst
);
995 if (x
& 0x8000) /* sign bit set */
997 x
|= 0xffff0000; /* sign extension */
1003 /* Determine whate to set a single step breakpoint while considering
1004 branch prediction */
1006 mips32_next_pc (CORE_ADDR pc
)
1010 inst
= mips_fetch_instruction (pc
);
1011 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1013 if (itype_op (inst
) >> 2 == 5)
1014 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1016 op
= (itype_op (inst
) & 0x03);
1026 goto greater_branch
;
1031 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1032 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1034 int tf
= itype_rt (inst
) & 0x01;
1035 int cnum
= itype_rt (inst
) >> 2;
1036 int fcrcs
= read_signed_register (mips_regnum (current_gdbarch
)->fp_control_status
);
1037 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1039 if (((cond
>> cnum
) & 0x01) == tf
)
1040 pc
+= mips32_relative_offset (inst
) + 4;
1045 pc
+= 4; /* Not a branch, next instruction is easy */
1048 { /* This gets way messy */
1050 /* Further subdivide into SPECIAL, REGIMM and other */
1051 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1053 case 0: /* SPECIAL */
1054 op
= rtype_funct (inst
);
1059 /* Set PC to that address */
1060 pc
= read_signed_register (rtype_rs (inst
));
1066 break; /* end SPECIAL */
1067 case 1: /* REGIMM */
1069 op
= itype_rt (inst
); /* branch condition */
1074 case 16: /* BLTZAL */
1075 case 18: /* BLTZALL */
1077 if (read_signed_register (itype_rs (inst
)) < 0)
1078 pc
+= mips32_relative_offset (inst
) + 4;
1080 pc
+= 8; /* after the delay slot */
1084 case 17: /* BGEZAL */
1085 case 19: /* BGEZALL */
1086 greater_equal_branch
:
1087 if (read_signed_register (itype_rs (inst
)) >= 0)
1088 pc
+= mips32_relative_offset (inst
) + 4;
1090 pc
+= 8; /* after the delay slot */
1092 /* All of the other instructions in the REGIMM category */
1097 break; /* end REGIMM */
1102 reg
= jtype_target (inst
) << 2;
1103 /* Upper four bits get never changed... */
1104 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1107 /* FIXME case JALX : */
1110 reg
= jtype_target (inst
) << 2;
1111 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1112 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1114 break; /* The new PC will be alternate mode */
1115 case 4: /* BEQ, BEQL */
1117 if (read_signed_register (itype_rs (inst
)) ==
1118 read_signed_register (itype_rt (inst
)))
1119 pc
+= mips32_relative_offset (inst
) + 4;
1123 case 5: /* BNE, BNEL */
1125 if (read_signed_register (itype_rs (inst
)) !=
1126 read_signed_register (itype_rt (inst
)))
1127 pc
+= mips32_relative_offset (inst
) + 4;
1131 case 6: /* BLEZ, BLEZL */
1133 if (read_signed_register (itype_rs (inst
) <= 0))
1134 pc
+= mips32_relative_offset (inst
) + 4;
1140 greater_branch
: /* BGTZ, BGTZL */
1141 if (read_signed_register (itype_rs (inst
) > 0))
1142 pc
+= mips32_relative_offset (inst
) + 4;
1149 } /* mips32_next_pc */
1151 /* Decoding the next place to set a breakpoint is irregular for the
1152 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1153 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1154 We dont want to set a single step instruction on the extend instruction
1158 /* Lots of mips16 instruction formats */
1159 /* Predicting jumps requires itype,ritype,i8type
1160 and their extensions extItype,extritype,extI8type
1162 enum mips16_inst_fmts
1164 itype
, /* 0 immediate 5,10 */
1165 ritype
, /* 1 5,3,8 */
1166 rrtype
, /* 2 5,3,3,5 */
1167 rritype
, /* 3 5,3,3,5 */
1168 rrrtype
, /* 4 5,3,3,3,2 */
1169 rriatype
, /* 5 5,3,3,1,4 */
1170 shifttype
, /* 6 5,3,3,3,2 */
1171 i8type
, /* 7 5,3,8 */
1172 i8movtype
, /* 8 5,3,3,5 */
1173 i8mov32rtype
, /* 9 5,3,5,3 */
1174 i64type
, /* 10 5,3,8 */
1175 ri64type
, /* 11 5,3,3,5 */
1176 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1177 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1178 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1179 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1180 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1181 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1182 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1183 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1184 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1185 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1187 /* I am heaping all the fields of the formats into one structure and
1188 then, only the fields which are involved in instruction extension */
1192 unsigned int regx
; /* Function in i8 type */
1197 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1198 for the bits which make up the immediatate extension. */
1201 extended_offset (unsigned int extension
)
1204 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1206 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1208 value
|= extension
& 0x01f; /* extract 4:0 */
1212 /* Only call this function if you know that this is an extendable
1213 instruction, It wont malfunction, but why make excess remote memory references?
1214 If the immediate operands get sign extended or somthing, do it after
1215 the extension is performed.
1217 /* FIXME: Every one of these cases needs to worry about sign extension
1218 when the offset is to be used in relative addressing */
1222 fetch_mips_16 (CORE_ADDR pc
)
1225 pc
&= 0xfffffffe; /* clear the low order bit */
1226 target_read_memory (pc
, buf
, 2);
1227 return extract_unsigned_integer (buf
, 2);
1231 unpack_mips16 (CORE_ADDR pc
,
1232 unsigned int extension
,
1234 enum mips16_inst_fmts insn_format
,
1235 struct upk_mips16
*upk
)
1240 switch (insn_format
)
1247 value
= extended_offset (extension
);
1248 value
= value
<< 11; /* rom for the original value */
1249 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1253 value
= inst
& 0x7ff;
1254 /* FIXME : Consider sign extension */
1263 { /* A register identifier and an offset */
1264 /* Most of the fields are the same as I type but the
1265 immediate value is of a different length */
1269 value
= extended_offset (extension
);
1270 value
= value
<< 8; /* from the original instruction */
1271 value
|= inst
& 0xff; /* eleven bits from instruction */
1272 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1273 if (value
& 0x4000) /* test the sign bit , bit 26 */
1275 value
&= ~0x3fff; /* remove the sign bit */
1281 value
= inst
& 0xff; /* 8 bits */
1282 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1283 /* FIXME: Do sign extension , this format needs it */
1284 if (value
& 0x80) /* THIS CONFUSES ME */
1286 value
&= 0xef; /* remove the sign bit */
1296 unsigned long value
;
1297 unsigned int nexthalf
;
1298 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1299 value
= value
<< 16;
1300 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1308 internal_error (__FILE__
, __LINE__
,
1311 upk
->offset
= offset
;
1318 add_offset_16 (CORE_ADDR pc
, int offset
)
1320 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1324 extended_mips16_next_pc (CORE_ADDR pc
,
1325 unsigned int extension
,
1328 int op
= (insn
>> 11);
1331 case 2: /* Branch */
1334 struct upk_mips16 upk
;
1335 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1336 offset
= upk
.offset
;
1342 pc
+= (offset
<< 1) + 2;
1345 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1347 struct upk_mips16 upk
;
1348 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1349 pc
= add_offset_16 (pc
, upk
.offset
);
1350 if ((insn
>> 10) & 0x01) /* Exchange mode */
1351 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1358 struct upk_mips16 upk
;
1360 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1361 reg
= read_signed_register (upk
.regx
);
1363 pc
+= (upk
.offset
<< 1) + 2;
1370 struct upk_mips16 upk
;
1372 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1373 reg
= read_signed_register (upk
.regx
);
1375 pc
+= (upk
.offset
<< 1) + 2;
1380 case 12: /* I8 Formats btez btnez */
1382 struct upk_mips16 upk
;
1384 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1385 /* upk.regx contains the opcode */
1386 reg
= read_signed_register (24); /* Test register is 24 */
1387 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1388 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1389 /* pc = add_offset_16(pc,upk.offset) ; */
1390 pc
+= (upk
.offset
<< 1) + 2;
1395 case 29: /* RR Formats JR, JALR, JALR-RA */
1397 struct upk_mips16 upk
;
1398 /* upk.fmt = rrtype; */
1403 upk
.regx
= (insn
>> 8) & 0x07;
1404 upk
.regy
= (insn
>> 5) & 0x07;
1412 break; /* Function return instruction */
1418 break; /* BOGUS Guess */
1420 pc
= read_signed_register (reg
);
1427 /* This is an instruction extension. Fetch the real instruction
1428 (which follows the extension) and decode things based on
1432 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1445 mips16_next_pc (CORE_ADDR pc
)
1447 unsigned int insn
= fetch_mips_16 (pc
);
1448 return extended_mips16_next_pc (pc
, 0, insn
);
1451 /* The mips_next_pc function supports single_step when the remote
1452 target monitor or stub is not developed enough to do a single_step.
1453 It works by decoding the current instruction and predicting where a
1454 branch will go. This isnt hard because all the data is available.
1455 The MIPS32 and MIPS16 variants are quite different */
1457 mips_next_pc (CORE_ADDR pc
)
1460 return mips16_next_pc (pc
);
1462 return mips32_next_pc (pc
);
1465 /* Set up the 'saved_regs' array. This is a data structure containing
1466 the addresses on the stack where each register has been saved, for
1467 each stack frame. Registers that have not been saved will have
1468 zero here. The stack pointer register is special: rather than the
1469 address where the stack register has been saved,
1470 saved_regs[SP_REGNUM] will have the actual value of the previous
1471 frame's stack register. */
1474 mips_find_saved_regs (struct frame_info
*fci
)
1477 /* r0 bit means kernel trap */
1479 /* What registers have been saved? Bitmasks. */
1480 unsigned long gen_mask
, float_mask
;
1481 mips_extra_func_info_t proc_desc
;
1483 CORE_ADDR
*saved_regs
;
1485 if (deprecated_get_frame_saved_regs (fci
) != NULL
)
1487 saved_regs
= frame_saved_regs_zalloc (fci
);
1489 /* If it is the frame for sigtramp, the saved registers are located
1490 in a sigcontext structure somewhere on the stack. If the stack
1491 layout for sigtramp changes we might have to change these
1492 constants and the companion fixup_sigtramp in mdebugread.c */
1493 #ifndef SIGFRAME_BASE
1494 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1495 above the sigtramp frame. */
1496 #define SIGFRAME_BASE mips_regsize (current_gdbarch)
1497 /* FIXME! Are these correct?? */
1498 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch))
1499 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch))
1500 #define SIGFRAME_FPREGSAVE_OFF \
1501 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch))
1503 if ((get_frame_type (fci
) == SIGTRAMP_FRAME
))
1505 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1507 CORE_ADDR reg_position
= (get_frame_base (fci
) + SIGFRAME_REGSAVE_OFF
1508 + ireg
* mips_regsize (current_gdbarch
));
1509 set_reg_offset (saved_regs
, ireg
, reg_position
);
1511 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1513 CORE_ADDR reg_position
= (get_frame_base (fci
)
1514 + SIGFRAME_FPREGSAVE_OFF
1515 + ireg
* mips_regsize (current_gdbarch
));
1516 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
, reg_position
);
1519 set_reg_offset (saved_regs
, PC_REGNUM
, get_frame_base (fci
) + SIGFRAME_PC_OFF
);
1520 /* SP_REGNUM, contains the value and not the address. */
1521 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1525 proc_desc
= get_frame_extra_info (fci
)->proc_desc
;
1526 if (proc_desc
== NULL
)
1527 /* I'm not sure how/whether this can happen. Normally when we
1528 can't find a proc_desc, we "synthesize" one using
1529 heuristic_proc_desc and set the saved_regs right away. */
1532 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1533 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1534 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1536 if (/* In any frame other than the innermost or a frame interrupted
1537 by a signal, we assume that all registers have been saved.
1538 This assumes that all register saves in a function happen
1539 before the first function call. */
1540 (get_next_frame (fci
) == NULL
1541 || (get_frame_type (get_next_frame (fci
)) == SIGTRAMP_FRAME
))
1543 /* In a dummy frame we know exactly where things are saved. */
1544 && !PROC_DESC_IS_DUMMY (proc_desc
)
1546 /* Don't bother unless we are inside a function prologue.
1547 Outside the prologue, we know where everything is. */
1549 && in_prologue (get_frame_pc (fci
), PROC_LOW_ADDR (proc_desc
))
1551 /* Not sure exactly what kernel_trap means, but if it means the
1552 kernel saves the registers without a prologue doing it, we
1553 better not examine the prologue to see whether registers
1554 have been saved yet. */
1557 /* We need to figure out whether the registers that the
1558 proc_desc claims are saved have been saved yet. */
1562 /* Bitmasks; set if we have found a save for the register. */
1563 unsigned long gen_save_found
= 0;
1564 unsigned long float_save_found
= 0;
1567 /* If the address is odd, assume this is MIPS16 code. */
1568 addr
= PROC_LOW_ADDR (proc_desc
);
1569 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1571 /* Scan through this function's instructions preceding the
1572 current PC, and look for those that save registers. */
1573 while (addr
< get_frame_pc (fci
))
1575 inst
= mips_fetch_instruction (addr
);
1576 if (pc_is_mips16 (addr
))
1577 mips16_decode_reg_save (inst
, &gen_save_found
);
1579 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1582 gen_mask
= gen_save_found
;
1583 float_mask
= float_save_found
;
1586 /* Fill in the offsets for the registers which gen_mask says were
1589 CORE_ADDR reg_position
= (get_frame_base (fci
)
1590 + PROC_REG_OFFSET (proc_desc
));
1591 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1592 if (gen_mask
& 0x80000000)
1594 set_reg_offset (saved_regs
, ireg
, reg_position
);
1595 reg_position
-= MIPS_SAVED_REGSIZE
;
1599 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1600 order of that normally used by gcc. Therefore, we have to fetch
1601 the first instruction of the function, and if it's an entry
1602 instruction that saves $s0 or $s1, correct their saved addresses. */
1603 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1605 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1606 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1610 int sreg_count
= (inst
>> 6) & 3;
1612 /* Check if the ra register was pushed on the stack. */
1613 CORE_ADDR reg_position
= (get_frame_base (fci
)
1614 + PROC_REG_OFFSET (proc_desc
));
1616 reg_position
-= MIPS_SAVED_REGSIZE
;
1618 /* Check if the s0 and s1 registers were pushed on the
1620 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1622 set_reg_offset (saved_regs
, reg
, reg_position
);
1623 reg_position
-= MIPS_SAVED_REGSIZE
;
1628 /* Fill in the offsets for the registers which float_mask says were
1631 CORE_ADDR reg_position
= (get_frame_base (fci
)
1632 + PROC_FREG_OFFSET (proc_desc
));
1634 /* Fill in the offsets for the float registers which float_mask
1636 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1637 if (float_mask
& 0x80000000)
1639 if (MIPS_SAVED_REGSIZE
== 4 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1641 /* On a big endian 32 bit ABI, floating point registers
1642 are paired to form doubles such that the most
1643 significant part is in $f[N+1] and the least
1644 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1645 registers are also spilled as a pair and stored as a
1648 When little-endian the least significant part is
1649 stored first leading to the memory order $f[N] and
1652 Unfortunately, when big-endian the most significant
1653 part of the double is stored first, and the least
1654 significant is stored second. This leads to the
1655 registers being ordered in memory as firt $f[N+1] and
1658 For the big-endian case make certain that the
1659 addresses point at the correct (swapped) locations
1660 $f[N] and $f[N+1] pair (keep in mind that
1661 reg_position is decremented each time through the
1664 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1665 reg_position
- MIPS_SAVED_REGSIZE
);
1667 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1668 reg_position
+ MIPS_SAVED_REGSIZE
);
1671 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
, reg_position
);
1672 reg_position
-= MIPS_SAVED_REGSIZE
;
1675 set_reg_offset (saved_regs
, PC_REGNUM
, saved_regs
[RA_REGNUM
]);
1678 /* SP_REGNUM, contains the value and not the address. */
1679 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1683 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1685 /* Always a pseudo. */
1686 gdb_assert (regno
>= NUM_REGS
);
1690 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1693 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1694 /* The SP_REGNUM is special, its value is stored in saved_regs.
1695 In fact, it is so special that it can even only be fetched
1696 using a raw register number! Once this code as been converted
1697 to frame-unwind the problem goes away. */
1698 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1700 return frame_unwind_register_signed (fi
, regno
);
1704 /* mips_addr_bits_remove - remove useless address bits */
1707 mips_addr_bits_remove (CORE_ADDR addr
)
1709 if (mips_mask_address_p ()
1710 && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
1711 /* This hack is a work-around for existing boards using PMON, the
1712 simulator, and any other 64-bit targets that doesn't have true
1713 64-bit addressing. On these targets, the upper 32 bits of
1714 addresses are ignored by the hardware. Thus, the PC or SP are
1715 likely to have been sign extended to all 1s by instruction
1716 sequences that load 32-bit addresses. For example, a typical
1717 piece of code that loads an address is this:
1719 lui $r2, <upper 16 bits>
1720 ori $r2, <lower 16 bits>
1722 But the lui sign-extends the value such that the upper 32 bits
1723 may be all 1s. The workaround is simply to mask off these
1724 bits. In the future, gcc may be changed to support true 64-bit
1725 addressing, and this masking will have to be disabled. */
1726 return addr
&= 0xffffffffUL
;
1731 /* mips_software_single_step() is called just before we want to resume
1732 the inferior, if we want to single-step it but there is no hardware
1733 or kernel single-step support (MIPS on GNU/Linux for example). We find
1734 the target of the coming instruction and breakpoint it.
1736 single_step is also called just after the inferior stops. If we had
1737 set up a simulated single-step, we undo our damage. */
1740 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1742 static CORE_ADDR next_pc
;
1743 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1744 static binsn_quantum break_mem
;
1747 if (insert_breakpoints_p
)
1749 pc
= read_register (PC_REGNUM
);
1750 next_pc
= mips_next_pc (pc
);
1752 target_insert_breakpoint (next_pc
, break_mem
);
1755 target_remove_breakpoint (next_pc
, break_mem
);
1759 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1764 ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev
))
1765 : get_next_frame (prev
)
1766 ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev
))
1768 tmp
= SKIP_TRAMPOLINE_CODE (pc
);
1769 return tmp
? tmp
: pc
;
1774 mips_frame_saved_pc (struct frame_info
*frame
)
1778 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
1781 /* Always unwind the cooked PC register value. */
1782 frame_unwind_signed_register (frame
, NUM_REGS
+ PC_REGNUM
, &tmp
);
1787 mips_extra_func_info_t proc_desc
1788 = get_frame_extra_info (frame
)->proc_desc
;
1789 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1790 saved_pc
= read_memory_integer (get_frame_base (frame
) - MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1793 /* We have to get the saved pc from the sigcontext if it is
1794 a signal handler frame. */
1795 int pcreg
= (get_frame_type (frame
) == SIGTRAMP_FRAME
? PC_REGNUM
1796 : proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1797 saved_pc
= read_next_frame_reg (frame
, NUM_REGS
+ pcreg
);
1800 return ADDR_BITS_REMOVE (saved_pc
);
1803 static struct mips_extra_func_info temp_proc_desc
;
1805 /* This hack will go away once the get_prev_frame() code has been
1806 modified to set the frame's type first. That is BEFORE init extra
1807 frame info et.al. is called. This is because it will become
1808 possible to skip the init extra info call for sigtramp and dummy
1810 static CORE_ADDR
*temp_saved_regs
;
1812 /* Set a register's saved stack address in temp_saved_regs. If an
1813 address has already been set for this register, do nothing; this
1814 way we will only recognize the first save of a given register in a
1817 For simplicity, save the address in both [0 .. NUM_REGS) and
1818 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1819 is used as it is only second range (the ABI instead of ISA
1820 registers) that comes into play when finding saved registers in a
1824 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
1826 if (saved_regs
[regno
] == 0)
1828 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
1829 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
1834 /* Test whether the PC points to the return instruction at the
1835 end of a function. */
1838 mips_about_to_return (CORE_ADDR pc
)
1840 if (pc_is_mips16 (pc
))
1841 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1842 generates a "jr $ra"; other times it generates code to load
1843 the return address from the stack to an accessible register (such
1844 as $a3), then a "jr" using that register. This second case
1845 is almost impossible to distinguish from an indirect jump
1846 used for switch statements, so we don't even try. */
1847 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1849 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1853 /* This fencepost looks highly suspicious to me. Removing it also
1854 seems suspicious as it could affect remote debugging across serial
1858 heuristic_proc_start (CORE_ADDR pc
)
1865 pc
= ADDR_BITS_REMOVE (pc
);
1867 fence
= start_pc
- heuristic_fence_post
;
1871 if (heuristic_fence_post
== UINT_MAX
1872 || fence
< VM_MIN_ADDRESS
)
1873 fence
= VM_MIN_ADDRESS
;
1875 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1877 /* search back for previous return */
1878 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1879 if (start_pc
< fence
)
1881 /* It's not clear to me why we reach this point when
1882 stop_soon, but with this test, at least we
1883 don't print out warnings for every child forked (eg, on
1884 decstation). 22apr93 rich@cygnus.com. */
1885 if (stop_soon
== NO_STOP_QUIETLY
)
1887 static int blurb_printed
= 0;
1889 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1894 /* This actually happens frequently in embedded
1895 development, when you first connect to a board
1896 and your stack pointer and pc are nowhere in
1897 particular. This message needs to give people
1898 in that situation enough information to
1899 determine that it's no big deal. */
1900 printf_filtered ("\n\
1901 GDB is unable to find the start of the function at 0x%s\n\
1902 and thus can't determine the size of that function's stack frame.\n\
1903 This means that GDB may be unable to access that stack frame, or\n\
1904 the frames below it.\n\
1905 This problem is most likely caused by an invalid program counter or\n\
1907 However, if you think GDB should simply search farther back\n\
1908 from 0x%s for code which looks like the beginning of a\n\
1909 function, you can increase the range of the search using the `set\n\
1910 heuristic-fence-post' command.\n",
1911 paddr_nz (pc
), paddr_nz (pc
));
1918 else if (pc_is_mips16 (start_pc
))
1920 unsigned short inst
;
1922 /* On MIPS16, any one of the following is likely to be the
1923 start of a function:
1927 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1928 inst
= mips_fetch_instruction (start_pc
);
1929 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1930 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1931 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1932 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1934 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1935 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1940 else if (mips_about_to_return (start_pc
))
1942 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1949 /* Fetch the immediate value from a MIPS16 instruction.
1950 If the previous instruction was an EXTEND, use it to extend
1951 the upper bits of the immediate value. This is a helper function
1952 for mips16_heuristic_proc_desc. */
1955 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1956 unsigned short inst
, /* current instruction */
1957 int nbits
, /* number of bits in imm field */
1958 int scale
, /* scale factor to be applied to imm */
1959 int is_signed
) /* is the imm field signed? */
1963 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1965 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1966 if (offset
& 0x8000) /* check for negative extend */
1967 offset
= 0 - (0x10000 - (offset
& 0xffff));
1968 return offset
| (inst
& 0x1f);
1972 int max_imm
= 1 << nbits
;
1973 int mask
= max_imm
- 1;
1974 int sign_bit
= max_imm
>> 1;
1976 offset
= inst
& mask
;
1977 if (is_signed
&& (offset
& sign_bit
))
1978 offset
= 0 - (max_imm
- offset
);
1979 return offset
* scale
;
1984 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1985 stream from start_pc to limit_pc. */
1988 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1989 struct frame_info
*next_frame
, CORE_ADDR sp
)
1992 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1993 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1994 unsigned inst
= 0; /* current instruction */
1995 unsigned entry_inst
= 0; /* the entry instruction */
1998 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1999 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2001 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2003 /* Save the previous instruction. If it's an EXTEND, we'll extract
2004 the immediate offset extension from it in mips16_get_imm. */
2007 /* Fetch and decode the instruction. */
2008 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2009 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2010 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2012 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2013 if (offset
< 0) /* negative stack adjustment? */
2014 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2016 /* Exit loop if a positive stack adjustment is found, which
2017 usually means that the stack cleanup code in the function
2018 epilogue is reached. */
2021 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2023 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2024 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2025 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2026 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2028 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2030 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2031 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2032 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2033 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2035 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2037 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2038 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2039 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2041 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2043 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2044 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2045 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2047 else if (inst
== 0x673d) /* move $s1, $sp */
2050 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2052 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2054 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2055 frame_addr
= sp
+ offset
;
2056 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2057 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2059 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2061 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2062 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2063 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2064 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2066 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2068 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2069 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2070 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2071 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2073 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2074 entry_inst
= inst
; /* save for later processing */
2075 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2076 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2079 /* The entry instruction is typically the first instruction in a function,
2080 and it stores registers at offsets relative to the value of the old SP
2081 (before the prologue). But the value of the sp parameter to this
2082 function is the new SP (after the prologue has been executed). So we
2083 can't calculate those offsets until we've seen the entire prologue,
2084 and can calculate what the old SP must have been. */
2085 if (entry_inst
!= 0)
2087 int areg_count
= (entry_inst
>> 8) & 7;
2088 int sreg_count
= (entry_inst
>> 6) & 3;
2090 /* The entry instruction always subtracts 32 from the SP. */
2091 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2093 /* Now we can calculate what the SP must have been at the
2094 start of the function prologue. */
2095 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2097 /* Check if a0-a3 were saved in the caller's argument save area. */
2098 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2100 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2101 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2102 offset
+= MIPS_SAVED_REGSIZE
;
2105 /* Check if the ra register was pushed on the stack. */
2107 if (entry_inst
& 0x20)
2109 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2110 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2111 offset
-= MIPS_SAVED_REGSIZE
;
2114 /* Check if the s0 and s1 registers were pushed on the stack. */
2115 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2117 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2118 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2119 offset
-= MIPS_SAVED_REGSIZE
;
2125 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2126 struct frame_info
*next_frame
, CORE_ADDR sp
)
2129 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2131 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2132 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2133 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2134 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2135 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2137 unsigned long inst
, high_word
, low_word
;
2140 /* Fetch the instruction. */
2141 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2143 /* Save some code by pre-extracting some useful fields. */
2144 high_word
= (inst
>> 16) & 0xffff;
2145 low_word
= inst
& 0xffff;
2146 reg
= high_word
& 0x1f;
2148 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2149 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2150 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2152 if (low_word
& 0x8000) /* negative stack adjustment? */
2153 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2155 /* Exit loop if a positive stack adjustment is found, which
2156 usually means that the stack cleanup code in the function
2157 epilogue is reached. */
2160 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2162 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2163 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2165 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2167 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2168 but the register size used is only 32 bits. Make the address
2169 for the saved register point to the lower 32 bits. */
2170 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2171 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
+ 8 - mips_regsize (current_gdbarch
));
2173 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2175 /* Old gcc frame, r30 is virtual frame pointer. */
2176 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2177 frame_addr
= sp
+ low_word
;
2178 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2180 unsigned alloca_adjust
;
2181 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2182 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2183 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2184 if (alloca_adjust
> 0)
2186 /* FP > SP + frame_size. This may be because
2187 * of an alloca or somethings similar.
2188 * Fix sp to "pre-alloca" value, and try again.
2190 sp
+= alloca_adjust
;
2195 /* move $30,$sp. With different versions of gas this will be either
2196 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2197 Accept any one of these. */
2198 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2200 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2201 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2203 unsigned alloca_adjust
;
2204 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2205 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2206 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2207 if (alloca_adjust
> 0)
2209 /* FP > SP + frame_size. This may be because
2210 * of an alloca or somethings similar.
2211 * Fix sp to "pre-alloca" value, and try again.
2213 sp
+= alloca_adjust
;
2218 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2220 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2221 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2226 static mips_extra_func_info_t
2227 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2228 struct frame_info
*next_frame
, int cur_frame
)
2233 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2239 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2240 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2241 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2242 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2243 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2244 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2246 if (start_pc
+ 200 < limit_pc
)
2247 limit_pc
= start_pc
+ 200;
2248 if (pc_is_mips16 (start_pc
))
2249 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2251 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2252 return &temp_proc_desc
;
2255 struct mips_objfile_private
2261 /* Global used to communicate between non_heuristic_proc_desc and
2262 compare_pdr_entries within qsort (). */
2263 static bfd
*the_bfd
;
2266 compare_pdr_entries (const void *a
, const void *b
)
2268 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2269 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2273 else if (lhs
== rhs
)
2279 static mips_extra_func_info_t
2280 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2282 CORE_ADDR startaddr
;
2283 mips_extra_func_info_t proc_desc
;
2284 struct block
*b
= block_for_pc (pc
);
2286 struct obj_section
*sec
;
2287 struct mips_objfile_private
*priv
;
2289 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2292 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2294 *addrptr
= startaddr
;
2298 sec
= find_pc_section (pc
);
2301 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2303 /* Search the ".pdr" section generated by GAS. This includes most of
2304 the information normally found in ECOFF PDRs. */
2306 the_bfd
= sec
->objfile
->obfd
;
2308 && (the_bfd
->format
== bfd_object
2309 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2310 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2312 /* Right now GAS only outputs the address as a four-byte sequence.
2313 This means that we should not bother with this method on 64-bit
2314 targets (until that is fixed). */
2316 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2317 sizeof (struct mips_objfile_private
));
2319 sec
->objfile
->obj_private
= priv
;
2321 else if (priv
== NULL
)
2325 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2326 sizeof (struct mips_objfile_private
));
2328 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2331 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2332 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2334 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2335 priv
->contents
, 0, priv
->size
);
2337 /* In general, the .pdr section is sorted. However, in the
2338 presence of multiple code sections (and other corner cases)
2339 it can become unsorted. Sort it so that we can use a faster
2341 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
2346 sec
->objfile
->obj_private
= priv
;
2350 if (priv
->size
!= 0)
2356 high
= priv
->size
/ 32;
2362 mid
= (low
+ high
) / 2;
2364 ptr
= priv
->contents
+ mid
* 32;
2365 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2366 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2367 SECT_OFF_TEXT (sec
->objfile
));
2368 if (pdr_pc
== startaddr
)
2370 if (pdr_pc
> startaddr
)
2375 while (low
!= high
);
2379 struct symbol
*sym
= find_pc_function (pc
);
2381 /* Fill in what we need of the proc_desc. */
2382 proc_desc
= (mips_extra_func_info_t
)
2383 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2384 sizeof (struct mips_extra_func_info
));
2385 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2387 /* Only used for dummy frames. */
2388 PROC_HIGH_ADDR (proc_desc
) = 0;
2390 PROC_FRAME_OFFSET (proc_desc
)
2391 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2392 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2394 PROC_FRAME_ADJUST (proc_desc
) = 0;
2395 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2397 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2399 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2401 PROC_FREG_OFFSET (proc_desc
)
2402 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2403 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2405 proc_desc
->pdr
.isym
= (long) sym
;
2415 if (startaddr
> BLOCK_START (b
))
2417 /* This is the "pathological" case referred to in a comment in
2418 print_frame_info. It might be better to move this check into
2423 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2425 /* If we never found a PDR for this function in symbol reading, then
2426 examine prologues to find the information. */
2429 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2430 if (PROC_FRAME_REG (proc_desc
) == -1)
2440 static mips_extra_func_info_t
2441 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2443 mips_extra_func_info_t proc_desc
;
2444 CORE_ADDR startaddr
= 0;
2446 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2450 /* IF this is the topmost frame AND
2451 * (this proc does not have debugging information OR
2452 * the PC is in the procedure prologue)
2453 * THEN create a "heuristic" proc_desc (by analyzing
2454 * the actual code) to replace the "official" proc_desc.
2456 if (next_frame
== NULL
)
2458 struct symtab_and_line val
;
2459 struct symbol
*proc_symbol
=
2460 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2464 val
= find_pc_line (BLOCK_START
2465 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2467 val
.pc
= val
.end
? val
.end
: pc
;
2469 if (!proc_symbol
|| pc
< val
.pc
)
2471 mips_extra_func_info_t found_heuristic
=
2472 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2473 pc
, next_frame
, cur_frame
);
2474 if (found_heuristic
)
2475 proc_desc
= found_heuristic
;
2481 /* Is linked_proc_desc_table really necessary? It only seems to be used
2482 by procedure call dummys. However, the procedures being called ought
2483 to have their own proc_descs, and even if they don't,
2484 heuristic_proc_desc knows how to create them! */
2486 struct linked_proc_info
*link
;
2488 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2489 if (PROC_LOW_ADDR (&link
->info
) <= pc
2490 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2494 startaddr
= heuristic_proc_start (pc
);
2497 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2503 get_frame_pointer (struct frame_info
*frame
,
2504 mips_extra_func_info_t proc_desc
)
2506 return (read_next_frame_reg (frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2507 + PROC_FRAME_OFFSET (proc_desc
)
2508 - PROC_FRAME_ADJUST (proc_desc
));
2511 static mips_extra_func_info_t cached_proc_desc
;
2514 mips_frame_chain (struct frame_info
*frame
)
2516 mips_extra_func_info_t proc_desc
;
2518 CORE_ADDR saved_pc
= DEPRECATED_FRAME_SAVED_PC (frame
);
2520 /* Check if the PC is inside a call stub. If it is, fetch the
2521 PC of the caller of that stub. */
2522 if ((tmp
= SKIP_TRAMPOLINE_CODE (saved_pc
)) != 0)
2525 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc
, 0, 0))
2527 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2528 is well, frame->frame the bottom of the current frame will
2529 contain that value. */
2530 return get_frame_base (frame
);
2533 /* Look up the procedure descriptor for this PC. */
2534 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2538 cached_proc_desc
= proc_desc
;
2540 /* If no frame pointer and frame size is zero, we must be at end
2541 of stack (or otherwise hosed). If we don't check frame size,
2542 we loop forever if we see a zero size frame. */
2543 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2544 && PROC_FRAME_OFFSET (proc_desc
) == 0
2545 /* The previous frame from a sigtramp frame might be frameless
2546 and have frame size zero. */
2547 && !(get_frame_type (frame
) == SIGTRAMP_FRAME
)
2548 /* For a generic dummy frame, let get_frame_pointer() unwind a
2549 register value saved as part of the dummy frame call. */
2550 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0)))
2553 return get_frame_pointer (frame
, proc_desc
);
2557 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2560 mips_extra_func_info_t proc_desc
;
2562 if (get_frame_type (fci
) == DUMMY_FRAME
)
2565 /* Use proc_desc calculated in frame_chain. When there is no
2566 next frame, i.e, get_next_frame (fci) == NULL, we call
2567 find_proc_desc () to calculate it, passing an explicit
2568 NULL as the frame parameter. */
2570 get_next_frame (fci
)
2572 : find_proc_desc (get_frame_pc (fci
),
2573 NULL
/* i.e, get_next_frame (fci) */,
2576 frame_extra_info_zalloc (fci
, sizeof (struct frame_extra_info
));
2578 get_frame_extra_info (fci
)->proc_desc
=
2579 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2582 /* Fixup frame-pointer - only needed for top frame */
2583 /* This may not be quite right, if proc has a real frame register.
2584 Get the value of the frame relative sp, procedure might have been
2585 interrupted by a signal at it's very start. */
2586 if (get_frame_pc (fci
) == PROC_LOW_ADDR (proc_desc
)
2587 && !PROC_DESC_IS_DUMMY (proc_desc
))
2588 deprecated_update_frame_base_hack (fci
, read_next_frame_reg (get_next_frame (fci
), NUM_REGS
+ SP_REGNUM
));
2589 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci
), 0, 0))
2590 /* Do not ``fix'' fci->frame. It will have the value of the
2591 generic dummy frame's top-of-stack (since the draft
2592 fci->frame is obtained by returning the unwound stack
2593 pointer) and that is what we want. That way the fci->frame
2594 value will match the top-of-stack value that was saved as
2595 part of the dummy frames data. */
2598 deprecated_update_frame_base_hack (fci
, get_frame_pointer (get_next_frame (fci
), proc_desc
));
2600 if (proc_desc
== &temp_proc_desc
)
2604 /* Do not set the saved registers for a sigtramp frame,
2605 mips_find_saved_registers will do that for us. We can't
2606 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2608 /* FIXME: cagney/2002-11-18: This problem will go away once
2609 frame.c:get_prev_frame() is modified to set the frame's
2610 type before calling functions like this. */
2611 find_pc_partial_function (get_frame_pc (fci
), &name
,
2612 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2613 if (!PC_IN_SIGTRAMP (get_frame_pc (fci
), name
))
2615 frame_saved_regs_zalloc (fci
);
2616 /* Set value of previous frame's stack pointer.
2617 Remember that saved_regs[SP_REGNUM] is special in
2618 that it contains the value of the stack pointer
2619 register. The other saved_regs values are addresses
2620 (in the inferior) at which a given register's value
2622 set_reg_offset (temp_saved_regs
, SP_REGNUM
,
2623 get_frame_base (fci
));
2624 set_reg_offset (temp_saved_regs
, PC_REGNUM
,
2625 temp_saved_regs
[RA_REGNUM
]);
2626 memcpy (deprecated_get_frame_saved_regs (fci
), temp_saved_regs
,
2627 SIZEOF_FRAME_SAVED_REGS
);
2631 /* hack: if argument regs are saved, guess these contain args */
2632 /* assume we can't tell how many args for now */
2633 get_frame_extra_info (fci
)->num_args
= -1;
2634 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2636 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2638 get_frame_extra_info (fci
)->num_args
= regnum
- A0_REGNUM
+ 1;
2645 /* MIPS stack frames are almost impenetrable. When execution stops,
2646 we basically have to look at symbol information for the function
2647 that we stopped in, which tells us *which* register (if any) is
2648 the base of the frame pointer, and what offset from that register
2649 the frame itself is at.
2651 This presents a problem when trying to examine a stack in memory
2652 (that isn't executing at the moment), using the "frame" command. We
2653 don't have a PC, nor do we have any registers except SP.
2655 This routine takes two arguments, SP and PC, and tries to make the
2656 cached frames look as if these two arguments defined a frame on the
2657 cache. This allows the rest of info frame to extract the important
2658 arguments without difficulty. */
2661 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2664 error ("MIPS frame specifications require two arguments: sp and pc");
2666 return create_new_frame (argv
[0], argv
[1]);
2669 /* According to the current ABI, should the type be passed in a
2670 floating-point register (assuming that there is space)? When there
2671 is no FPU, FP are not even considered as possibile candidates for
2672 FP registers and, consequently this returns false - forces FP
2673 arguments into integer registers. */
2676 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2678 return ((typecode
== TYPE_CODE_FLT
2680 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2681 && TYPE_NFIELDS (arg_type
) == 1
2682 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2683 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2686 /* On o32, argument passing in GPRs depends on the alignment of the type being
2687 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2690 mips_type_needs_double_align (struct type
*type
)
2692 enum type_code typecode
= TYPE_CODE (type
);
2694 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2696 else if (typecode
== TYPE_CODE_STRUCT
)
2698 if (TYPE_NFIELDS (type
) < 1)
2700 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2702 else if (typecode
== TYPE_CODE_UNION
)
2706 n
= TYPE_NFIELDS (type
);
2707 for (i
= 0; i
< n
; i
++)
2708 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2715 /* Adjust the address downward (direction of stack growth) so that it
2716 is correctly aligned for a new stack frame. */
2718 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2720 return align_down (addr
, 16);
2724 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2725 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2726 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2727 CORE_ADDR struct_addr
)
2733 int stack_offset
= 0;
2735 /* For shared libraries, "t9" needs to point at the function
2737 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2739 /* Set the return address register to point to the entry point of
2740 the program, where a breakpoint lies in wait. */
2741 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2743 /* First ensure that the stack and structure return address (if any)
2744 are properly aligned. The stack has to be at least 64-bit
2745 aligned even on 32-bit machines, because doubles must be 64-bit
2746 aligned. For n32 and n64, stack frames need to be 128-bit
2747 aligned, so we round to this widest known alignment. */
2749 sp
= align_down (sp
, 16);
2750 struct_addr
= align_down (struct_addr
, 16);
2752 /* Now make space on the stack for the args. We allocate more
2753 than necessary for EABI, because the first few arguments are
2754 passed in registers, but that's OK. */
2755 for (argnum
= 0; argnum
< nargs
; argnum
++)
2756 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2757 MIPS_STACK_ARGSIZE
);
2758 sp
-= align_up (len
, 16);
2761 fprintf_unfiltered (gdb_stdlog
,
2762 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2763 paddr_nz (sp
), (long) align_up (len
, 16));
2765 /* Initialize the integer and float register pointers. */
2767 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2769 /* The struct_return pointer occupies the first parameter-passing reg. */
2773 fprintf_unfiltered (gdb_stdlog
,
2774 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2775 argreg
, paddr_nz (struct_addr
));
2776 write_register (argreg
++, struct_addr
);
2779 /* Now load as many as possible of the first arguments into
2780 registers, and push the rest onto the stack. Loop thru args
2781 from first to last. */
2782 for (argnum
= 0; argnum
< nargs
; argnum
++)
2785 char valbuf
[MAX_REGISTER_SIZE
];
2786 struct value
*arg
= args
[argnum
];
2787 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2788 int len
= TYPE_LENGTH (arg_type
);
2789 enum type_code typecode
= TYPE_CODE (arg_type
);
2792 fprintf_unfiltered (gdb_stdlog
,
2793 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2794 argnum
+ 1, len
, (int) typecode
);
2796 /* The EABI passes structures that do not fit in a register by
2798 if (len
> MIPS_SAVED_REGSIZE
2799 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2801 store_unsigned_integer (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2802 typecode
= TYPE_CODE_PTR
;
2803 len
= MIPS_SAVED_REGSIZE
;
2806 fprintf_unfiltered (gdb_stdlog
, " push");
2809 val
= (char *) VALUE_CONTENTS (arg
);
2811 /* 32-bit ABIs always start floating point arguments in an
2812 even-numbered floating point register. Round the FP register
2813 up before the check to see if there are any FP registers
2814 left. Non MIPS_EABI targets also pass the FP in the integer
2815 registers so also round up normal registers. */
2816 if (!FP_REGISTER_DOUBLE
2817 && fp_register_arg_p (typecode
, arg_type
))
2819 if ((float_argreg
& 1))
2823 /* Floating point arguments passed in registers have to be
2824 treated specially. On 32-bit architectures, doubles
2825 are passed in register pairs; the even register gets
2826 the low word, and the odd register gets the high word.
2827 On non-EABI processors, the first two floating point arguments are
2828 also copied to general registers, because MIPS16 functions
2829 don't use float registers for arguments. This duplication of
2830 arguments in general registers can't hurt non-MIPS16 functions
2831 because those registers are normally skipped. */
2832 /* MIPS_EABI squeezes a struct that contains a single floating
2833 point value into an FP register instead of pushing it onto the
2835 if (fp_register_arg_p (typecode
, arg_type
)
2836 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2838 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2840 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2841 unsigned long regval
;
2843 /* Write the low word of the double to the even register(s). */
2844 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2846 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2847 float_argreg
, phex (regval
, 4));
2848 write_register (float_argreg
++, regval
);
2850 /* Write the high word of the double to the odd register(s). */
2851 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2853 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2854 float_argreg
, phex (regval
, 4));
2855 write_register (float_argreg
++, regval
);
2859 /* This is a floating point value that fits entirely
2860 in a single register. */
2861 /* On 32 bit ABI's the float_argreg is further adjusted
2862 above to ensure that it is even register aligned. */
2863 LONGEST regval
= extract_unsigned_integer (val
, len
);
2865 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2866 float_argreg
, phex (regval
, len
));
2867 write_register (float_argreg
++, regval
);
2872 /* Copy the argument to general registers or the stack in
2873 register-sized pieces. Large arguments are split between
2874 registers and stack. */
2875 /* Note: structs whose size is not a multiple of
2876 mips_regsize() are treated specially: Irix cc passes them
2877 in registers where gcc sometimes puts them on the stack.
2878 For maximum compatibility, we will put them in both
2880 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2881 (len
% MIPS_SAVED_REGSIZE
!= 0));
2883 /* Note: Floating-point values that didn't fit into an FP
2884 register are only written to memory. */
2887 /* Remember if the argument was written to the stack. */
2888 int stack_used_p
= 0;
2890 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2893 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2896 /* Write this portion of the argument to the stack. */
2897 if (argreg
> MIPS_LAST_ARG_REGNUM
2899 || fp_register_arg_p (typecode
, arg_type
))
2901 /* Should shorter than int integer values be
2902 promoted to int before being stored? */
2903 int longword_offset
= 0;
2906 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2908 if (MIPS_STACK_ARGSIZE
== 8 &&
2909 (typecode
== TYPE_CODE_INT
||
2910 typecode
== TYPE_CODE_PTR
||
2911 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2912 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2913 else if ((typecode
== TYPE_CODE_STRUCT
||
2914 typecode
== TYPE_CODE_UNION
) &&
2915 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2916 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2921 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2922 paddr_nz (stack_offset
));
2923 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2924 paddr_nz (longword_offset
));
2927 addr
= sp
+ stack_offset
+ longword_offset
;
2932 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2934 for (i
= 0; i
< partial_len
; i
++)
2936 fprintf_unfiltered (gdb_stdlog
, "%02x",
2940 write_memory (addr
, val
, partial_len
);
2943 /* Note!!! This is NOT an else clause. Odd sized
2944 structs may go thru BOTH paths. Floating point
2945 arguments will not. */
2946 /* Write this portion of the argument to a general
2947 purpose register. */
2948 if (argreg
<= MIPS_LAST_ARG_REGNUM
2949 && !fp_register_arg_p (typecode
, arg_type
))
2951 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2954 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2956 phex (regval
, MIPS_SAVED_REGSIZE
));
2957 write_register (argreg
, regval
);
2964 /* Compute the the offset into the stack at which we
2965 will copy the next parameter.
2967 In the new EABI (and the NABI32), the stack_offset
2968 only needs to be adjusted when it has been used. */
2971 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
2975 fprintf_unfiltered (gdb_stdlog
, "\n");
2978 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
2980 /* Return adjusted stack pointer. */
2984 /* N32/N64 version of push_dummy_call. */
2987 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2988 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2989 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2990 CORE_ADDR struct_addr
)
2996 int stack_offset
= 0;
2998 /* For shared libraries, "t9" needs to point at the function
3000 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3002 /* Set the return address register to point to the entry point of
3003 the program, where a breakpoint lies in wait. */
3004 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3006 /* First ensure that the stack and structure return address (if any)
3007 are properly aligned. The stack has to be at least 64-bit
3008 aligned even on 32-bit machines, because doubles must be 64-bit
3009 aligned. For n32 and n64, stack frames need to be 128-bit
3010 aligned, so we round to this widest known alignment. */
3012 sp
= align_down (sp
, 16);
3013 struct_addr
= align_down (struct_addr
, 16);
3015 /* Now make space on the stack for the args. */
3016 for (argnum
= 0; argnum
< nargs
; argnum
++)
3017 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3018 MIPS_STACK_ARGSIZE
);
3019 sp
-= align_up (len
, 16);
3022 fprintf_unfiltered (gdb_stdlog
,
3023 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3024 paddr_nz (sp
), (long) align_up (len
, 16));
3026 /* Initialize the integer and float register pointers. */
3028 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3030 /* The struct_return pointer occupies the first parameter-passing reg. */
3034 fprintf_unfiltered (gdb_stdlog
,
3035 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3036 argreg
, paddr_nz (struct_addr
));
3037 write_register (argreg
++, struct_addr
);
3040 /* Now load as many as possible of the first arguments into
3041 registers, and push the rest onto the stack. Loop thru args
3042 from first to last. */
3043 for (argnum
= 0; argnum
< nargs
; argnum
++)
3046 char valbuf
[MAX_REGISTER_SIZE
];
3047 struct value
*arg
= args
[argnum
];
3048 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3049 int len
= TYPE_LENGTH (arg_type
);
3050 enum type_code typecode
= TYPE_CODE (arg_type
);
3053 fprintf_unfiltered (gdb_stdlog
,
3054 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3055 argnum
+ 1, len
, (int) typecode
);
3057 val
= (char *) VALUE_CONTENTS (arg
);
3059 if (fp_register_arg_p (typecode
, arg_type
)
3060 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3062 /* This is a floating point value that fits entirely
3063 in a single register. */
3064 /* On 32 bit ABI's the float_argreg is further adjusted
3065 above to ensure that it is even register aligned. */
3066 LONGEST regval
= extract_unsigned_integer (val
, len
);
3068 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3069 float_argreg
, phex (regval
, len
));
3070 write_register (float_argreg
++, regval
);
3073 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3074 argreg
, phex (regval
, len
));
3075 write_register (argreg
, regval
);
3080 /* Copy the argument to general registers or the stack in
3081 register-sized pieces. Large arguments are split between
3082 registers and stack. */
3083 /* Note: structs whose size is not a multiple of
3084 mips_regsize() are treated specially: Irix cc passes them
3085 in registers where gcc sometimes puts them on the stack.
3086 For maximum compatibility, we will put them in both
3088 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3089 (len
% MIPS_SAVED_REGSIZE
!= 0));
3090 /* Note: Floating-point values that didn't fit into an FP
3091 register are only written to memory. */
3094 /* Rememer if the argument was written to the stack. */
3095 int stack_used_p
= 0;
3096 int partial_len
= len
< MIPS_SAVED_REGSIZE
?
3097 len
: MIPS_SAVED_REGSIZE
;
3100 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3103 /* Write this portion of the argument to the stack. */
3104 if (argreg
> MIPS_LAST_ARG_REGNUM
3106 || fp_register_arg_p (typecode
, arg_type
))
3108 /* Should shorter than int integer values be
3109 promoted to int before being stored? */
3110 int longword_offset
= 0;
3113 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3115 if (MIPS_STACK_ARGSIZE
== 8 &&
3116 (typecode
== TYPE_CODE_INT
||
3117 typecode
== TYPE_CODE_PTR
||
3118 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3119 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3124 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3125 paddr_nz (stack_offset
));
3126 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3127 paddr_nz (longword_offset
));
3130 addr
= sp
+ stack_offset
+ longword_offset
;
3135 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3137 for (i
= 0; i
< partial_len
; i
++)
3139 fprintf_unfiltered (gdb_stdlog
, "%02x",
3143 write_memory (addr
, val
, partial_len
);
3146 /* Note!!! This is NOT an else clause. Odd sized
3147 structs may go thru BOTH paths. Floating point
3148 arguments will not. */
3149 /* Write this portion of the argument to a general
3150 purpose register. */
3151 if (argreg
<= MIPS_LAST_ARG_REGNUM
3152 && !fp_register_arg_p (typecode
, arg_type
))
3154 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
3156 /* A non-floating-point argument being passed in a
3157 general register. If a struct or union, and if
3158 the remaining length is smaller than the register
3159 size, we have to adjust the register value on
3162 It does not seem to be necessary to do the
3163 same for integral types.
3165 cagney/2001-07-23: gdb/179: Also, GCC, when
3166 outputting LE O32 with sizeof (struct) <
3167 MIPS_SAVED_REGSIZE, generates a left shift as
3168 part of storing the argument in a register a
3169 register (the left shift isn't generated when
3170 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3171 is quite possible that this is GCC contradicting
3172 the LE/O32 ABI, GDB has not been adjusted to
3173 accommodate this. Either someone needs to
3174 demonstrate that the LE/O32 ABI specifies such a
3175 left shift OR this new ABI gets identified as
3176 such and GDB gets tweaked accordingly. */
3178 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3179 && partial_len
< MIPS_SAVED_REGSIZE
3180 && (typecode
== TYPE_CODE_STRUCT
||
3181 typecode
== TYPE_CODE_UNION
))
3182 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3186 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3188 phex (regval
, MIPS_SAVED_REGSIZE
));
3189 write_register (argreg
, regval
);
3196 /* Compute the the offset into the stack at which we
3197 will copy the next parameter.
3199 In N32 (N64?), the stack_offset only needs to be
3200 adjusted when it has been used. */
3203 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3207 fprintf_unfiltered (gdb_stdlog
, "\n");
3210 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3212 /* Return adjusted stack pointer. */
3216 /* O32 version of push_dummy_call. */
3219 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3220 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3221 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3222 CORE_ADDR struct_addr
)
3228 int stack_offset
= 0;
3230 /* For shared libraries, "t9" needs to point at the function
3232 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3234 /* Set the return address register to point to the entry point of
3235 the program, where a breakpoint lies in wait. */
3236 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3238 /* First ensure that the stack and structure return address (if any)
3239 are properly aligned. The stack has to be at least 64-bit
3240 aligned even on 32-bit machines, because doubles must be 64-bit
3241 aligned. For n32 and n64, stack frames need to be 128-bit
3242 aligned, so we round to this widest known alignment. */
3244 sp
= align_down (sp
, 16);
3245 struct_addr
= align_down (struct_addr
, 16);
3247 /* Now make space on the stack for the args. */
3248 for (argnum
= 0; argnum
< nargs
; argnum
++)
3249 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3250 MIPS_STACK_ARGSIZE
);
3251 sp
-= align_up (len
, 16);
3254 fprintf_unfiltered (gdb_stdlog
,
3255 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3256 paddr_nz (sp
), (long) align_up (len
, 16));
3258 /* Initialize the integer and float register pointers. */
3260 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3262 /* The struct_return pointer occupies the first parameter-passing reg. */
3266 fprintf_unfiltered (gdb_stdlog
,
3267 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3268 argreg
, paddr_nz (struct_addr
));
3269 write_register (argreg
++, struct_addr
);
3270 stack_offset
+= MIPS_STACK_ARGSIZE
;
3273 /* Now load as many as possible of the first arguments into
3274 registers, and push the rest onto the stack. Loop thru args
3275 from first to last. */
3276 for (argnum
= 0; argnum
< nargs
; argnum
++)
3279 char valbuf
[MAX_REGISTER_SIZE
];
3280 struct value
*arg
= args
[argnum
];
3281 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3282 int len
= TYPE_LENGTH (arg_type
);
3283 enum type_code typecode
= TYPE_CODE (arg_type
);
3286 fprintf_unfiltered (gdb_stdlog
,
3287 "mips_o32_push_dummy_call: %d len=%d type=%d",
3288 argnum
+ 1, len
, (int) typecode
);
3290 val
= (char *) VALUE_CONTENTS (arg
);
3292 /* 32-bit ABIs always start floating point arguments in an
3293 even-numbered floating point register. Round the FP register
3294 up before the check to see if there are any FP registers
3295 left. O32/O64 targets also pass the FP in the integer
3296 registers so also round up normal registers. */
3297 if (!FP_REGISTER_DOUBLE
3298 && fp_register_arg_p (typecode
, arg_type
))
3300 if ((float_argreg
& 1))
3304 /* Floating point arguments passed in registers have to be
3305 treated specially. On 32-bit architectures, doubles
3306 are passed in register pairs; the even register gets
3307 the low word, and the odd register gets the high word.
3308 On O32/O64, the first two floating point arguments are
3309 also copied to general registers, because MIPS16 functions
3310 don't use float registers for arguments. This duplication of
3311 arguments in general registers can't hurt non-MIPS16 functions
3312 because those registers are normally skipped. */
3314 if (fp_register_arg_p (typecode
, arg_type
)
3315 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3317 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3319 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3320 unsigned long regval
;
3322 /* Write the low word of the double to the even register(s). */
3323 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3325 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3326 float_argreg
, phex (regval
, 4));
3327 write_register (float_argreg
++, regval
);
3329 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3330 argreg
, phex (regval
, 4));
3331 write_register (argreg
++, regval
);
3333 /* Write the high word of the double to the odd register(s). */
3334 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3336 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3337 float_argreg
, phex (regval
, 4));
3338 write_register (float_argreg
++, regval
);
3341 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3342 argreg
, phex (regval
, 4));
3343 write_register (argreg
++, regval
);
3347 /* This is a floating point value that fits entirely
3348 in a single register. */
3349 /* On 32 bit ABI's the float_argreg is further adjusted
3350 above to ensure that it is even register aligned. */
3351 LONGEST regval
= extract_unsigned_integer (val
, len
);
3353 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3354 float_argreg
, phex (regval
, len
));
3355 write_register (float_argreg
++, regval
);
3356 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3357 registers for each argument. The below is (my
3358 guess) to ensure that the corresponding integer
3359 register has reserved the same space. */
3361 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3362 argreg
, phex (regval
, len
));
3363 write_register (argreg
, regval
);
3364 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3366 /* Reserve space for the FP register. */
3367 stack_offset
+= align_up (len
, MIPS_STACK_ARGSIZE
);
3371 /* Copy the argument to general registers or the stack in
3372 register-sized pieces. Large arguments are split between
3373 registers and stack. */
3374 /* Note: structs whose size is not a multiple of
3375 mips_regsize() are treated specially: Irix cc passes them
3376 in registers where gcc sometimes puts them on the stack.
3377 For maximum compatibility, we will put them in both
3379 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3380 (len
% MIPS_SAVED_REGSIZE
!= 0));
3381 /* Structures should be aligned to eight bytes (even arg registers)
3382 on MIPS_ABI_O32, if their first member has double precision. */
3383 if (MIPS_SAVED_REGSIZE
< 8
3384 && mips_type_needs_double_align (arg_type
))
3389 /* Note: Floating-point values that didn't fit into an FP
3390 register are only written to memory. */
3393 /* Remember if the argument was written to the stack. */
3394 int stack_used_p
= 0;
3396 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3399 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3402 /* Write this portion of the argument to the stack. */
3403 if (argreg
> MIPS_LAST_ARG_REGNUM
3405 || fp_register_arg_p (typecode
, arg_type
))
3407 /* Should shorter than int integer values be
3408 promoted to int before being stored? */
3409 int longword_offset
= 0;
3412 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3414 if (MIPS_STACK_ARGSIZE
== 8 &&
3415 (typecode
== TYPE_CODE_INT
||
3416 typecode
== TYPE_CODE_PTR
||
3417 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3418 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3423 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3424 paddr_nz (stack_offset
));
3425 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3426 paddr_nz (longword_offset
));
3429 addr
= sp
+ stack_offset
+ longword_offset
;
3434 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3436 for (i
= 0; i
< partial_len
; i
++)
3438 fprintf_unfiltered (gdb_stdlog
, "%02x",
3442 write_memory (addr
, val
, partial_len
);
3445 /* Note!!! This is NOT an else clause. Odd sized
3446 structs may go thru BOTH paths. Floating point
3447 arguments will not. */
3448 /* Write this portion of the argument to a general
3449 purpose register. */
3450 if (argreg
<= MIPS_LAST_ARG_REGNUM
3451 && !fp_register_arg_p (typecode
, arg_type
))
3453 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3454 /* Value may need to be sign extended, because
3455 mips_regsize() != MIPS_SAVED_REGSIZE. */
3457 /* A non-floating-point argument being passed in a
3458 general register. If a struct or union, and if
3459 the remaining length is smaller than the register
3460 size, we have to adjust the register value on
3463 It does not seem to be necessary to do the
3464 same for integral types.
3466 Also don't do this adjustment on O64 binaries.
3468 cagney/2001-07-23: gdb/179: Also, GCC, when
3469 outputting LE O32 with sizeof (struct) <
3470 MIPS_SAVED_REGSIZE, generates a left shift as
3471 part of storing the argument in a register a
3472 register (the left shift isn't generated when
3473 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3474 is quite possible that this is GCC contradicting
3475 the LE/O32 ABI, GDB has not been adjusted to
3476 accommodate this. Either someone needs to
3477 demonstrate that the LE/O32 ABI specifies such a
3478 left shift OR this new ABI gets identified as
3479 such and GDB gets tweaked accordingly. */
3481 if (MIPS_SAVED_REGSIZE
< 8
3482 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3483 && partial_len
< MIPS_SAVED_REGSIZE
3484 && (typecode
== TYPE_CODE_STRUCT
||
3485 typecode
== TYPE_CODE_UNION
))
3486 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3490 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3492 phex (regval
, MIPS_SAVED_REGSIZE
));
3493 write_register (argreg
, regval
);
3496 /* Prevent subsequent floating point arguments from
3497 being passed in floating point registers. */
3498 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3504 /* Compute the the offset into the stack at which we
3505 will copy the next parameter.
3507 In older ABIs, the caller reserved space for
3508 registers that contained arguments. This was loosely
3509 refered to as their "home". Consequently, space is
3510 always allocated. */
3512 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3516 fprintf_unfiltered (gdb_stdlog
, "\n");
3519 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3521 /* Return adjusted stack pointer. */
3525 /* O64 version of push_dummy_call. */
3528 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3529 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3530 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3531 CORE_ADDR struct_addr
)
3537 int stack_offset
= 0;
3539 /* For shared libraries, "t9" needs to point at the function
3541 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3543 /* Set the return address register to point to the entry point of
3544 the program, where a breakpoint lies in wait. */
3545 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3547 /* First ensure that the stack and structure return address (if any)
3548 are properly aligned. The stack has to be at least 64-bit
3549 aligned even on 32-bit machines, because doubles must be 64-bit
3550 aligned. For n32 and n64, stack frames need to be 128-bit
3551 aligned, so we round to this widest known alignment. */
3553 sp
= align_down (sp
, 16);
3554 struct_addr
= align_down (struct_addr
, 16);
3556 /* Now make space on the stack for the args. */
3557 for (argnum
= 0; argnum
< nargs
; argnum
++)
3558 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3559 MIPS_STACK_ARGSIZE
);
3560 sp
-= align_up (len
, 16);
3563 fprintf_unfiltered (gdb_stdlog
,
3564 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3565 paddr_nz (sp
), (long) align_up (len
, 16));
3567 /* Initialize the integer and float register pointers. */
3569 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3571 /* The struct_return pointer occupies the first parameter-passing reg. */
3575 fprintf_unfiltered (gdb_stdlog
,
3576 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3577 argreg
, paddr_nz (struct_addr
));
3578 write_register (argreg
++, struct_addr
);
3579 stack_offset
+= MIPS_STACK_ARGSIZE
;
3582 /* Now load as many as possible of the first arguments into
3583 registers, and push the rest onto the stack. Loop thru args
3584 from first to last. */
3585 for (argnum
= 0; argnum
< nargs
; argnum
++)
3588 char valbuf
[MAX_REGISTER_SIZE
];
3589 struct value
*arg
= args
[argnum
];
3590 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3591 int len
= TYPE_LENGTH (arg_type
);
3592 enum type_code typecode
= TYPE_CODE (arg_type
);
3595 fprintf_unfiltered (gdb_stdlog
,
3596 "mips_o64_push_dummy_call: %d len=%d type=%d",
3597 argnum
+ 1, len
, (int) typecode
);
3599 val
= (char *) VALUE_CONTENTS (arg
);
3601 /* 32-bit ABIs always start floating point arguments in an
3602 even-numbered floating point register. Round the FP register
3603 up before the check to see if there are any FP registers
3604 left. O32/O64 targets also pass the FP in the integer
3605 registers so also round up normal registers. */
3606 if (!FP_REGISTER_DOUBLE
3607 && fp_register_arg_p (typecode
, arg_type
))
3609 if ((float_argreg
& 1))
3613 /* Floating point arguments passed in registers have to be
3614 treated specially. On 32-bit architectures, doubles
3615 are passed in register pairs; the even register gets
3616 the low word, and the odd register gets the high word.
3617 On O32/O64, the first two floating point arguments are
3618 also copied to general registers, because MIPS16 functions
3619 don't use float registers for arguments. This duplication of
3620 arguments in general registers can't hurt non-MIPS16 functions
3621 because those registers are normally skipped. */
3623 if (fp_register_arg_p (typecode
, arg_type
)
3624 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3626 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3628 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3629 unsigned long regval
;
3631 /* Write the low word of the double to the even register(s). */
3632 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3634 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3635 float_argreg
, phex (regval
, 4));
3636 write_register (float_argreg
++, regval
);
3638 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3639 argreg
, phex (regval
, 4));
3640 write_register (argreg
++, regval
);
3642 /* Write the high word of the double to the odd register(s). */
3643 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3645 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3646 float_argreg
, phex (regval
, 4));
3647 write_register (float_argreg
++, regval
);
3650 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3651 argreg
, phex (regval
, 4));
3652 write_register (argreg
++, regval
);
3656 /* This is a floating point value that fits entirely
3657 in a single register. */
3658 /* On 32 bit ABI's the float_argreg is further adjusted
3659 above to ensure that it is even register aligned. */
3660 LONGEST regval
= extract_unsigned_integer (val
, len
);
3662 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3663 float_argreg
, phex (regval
, len
));
3664 write_register (float_argreg
++, regval
);
3665 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3666 registers for each argument. The below is (my
3667 guess) to ensure that the corresponding integer
3668 register has reserved the same space. */
3670 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3671 argreg
, phex (regval
, len
));
3672 write_register (argreg
, regval
);
3673 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3675 /* Reserve space for the FP register. */
3676 stack_offset
+= align_up (len
, MIPS_STACK_ARGSIZE
);
3680 /* Copy the argument to general registers or the stack in
3681 register-sized pieces. Large arguments are split between
3682 registers and stack. */
3683 /* Note: structs whose size is not a multiple of
3684 mips_regsize() are treated specially: Irix cc passes them
3685 in registers where gcc sometimes puts them on the stack.
3686 For maximum compatibility, we will put them in both
3688 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3689 (len
% MIPS_SAVED_REGSIZE
!= 0));
3690 /* Structures should be aligned to eight bytes (even arg registers)
3691 on MIPS_ABI_O32, if their first member has double precision. */
3692 if (MIPS_SAVED_REGSIZE
< 8
3693 && mips_type_needs_double_align (arg_type
))
3698 /* Note: Floating-point values that didn't fit into an FP
3699 register are only written to memory. */
3702 /* Remember if the argument was written to the stack. */
3703 int stack_used_p
= 0;
3705 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3708 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3711 /* Write this portion of the argument to the stack. */
3712 if (argreg
> MIPS_LAST_ARG_REGNUM
3714 || fp_register_arg_p (typecode
, arg_type
))
3716 /* Should shorter than int integer values be
3717 promoted to int before being stored? */
3718 int longword_offset
= 0;
3721 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3723 if (MIPS_STACK_ARGSIZE
== 8 &&
3724 (typecode
== TYPE_CODE_INT
||
3725 typecode
== TYPE_CODE_PTR
||
3726 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3727 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3732 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3733 paddr_nz (stack_offset
));
3734 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3735 paddr_nz (longword_offset
));
3738 addr
= sp
+ stack_offset
+ longword_offset
;
3743 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3745 for (i
= 0; i
< partial_len
; i
++)
3747 fprintf_unfiltered (gdb_stdlog
, "%02x",
3751 write_memory (addr
, val
, partial_len
);
3754 /* Note!!! This is NOT an else clause. Odd sized
3755 structs may go thru BOTH paths. Floating point
3756 arguments will not. */
3757 /* Write this portion of the argument to a general
3758 purpose register. */
3759 if (argreg
<= MIPS_LAST_ARG_REGNUM
3760 && !fp_register_arg_p (typecode
, arg_type
))
3762 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3763 /* Value may need to be sign extended, because
3764 mips_regsize() != MIPS_SAVED_REGSIZE. */
3766 /* A non-floating-point argument being passed in a
3767 general register. If a struct or union, and if
3768 the remaining length is smaller than the register
3769 size, we have to adjust the register value on
3772 It does not seem to be necessary to do the
3773 same for integral types.
3775 Also don't do this adjustment on O64 binaries.
3777 cagney/2001-07-23: gdb/179: Also, GCC, when
3778 outputting LE O32 with sizeof (struct) <
3779 MIPS_SAVED_REGSIZE, generates a left shift as
3780 part of storing the argument in a register a
3781 register (the left shift isn't generated when
3782 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3783 is quite possible that this is GCC contradicting
3784 the LE/O32 ABI, GDB has not been adjusted to
3785 accommodate this. Either someone needs to
3786 demonstrate that the LE/O32 ABI specifies such a
3787 left shift OR this new ABI gets identified as
3788 such and GDB gets tweaked accordingly. */
3790 if (MIPS_SAVED_REGSIZE
< 8
3791 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3792 && partial_len
< MIPS_SAVED_REGSIZE
3793 && (typecode
== TYPE_CODE_STRUCT
||
3794 typecode
== TYPE_CODE_UNION
))
3795 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3799 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3801 phex (regval
, MIPS_SAVED_REGSIZE
));
3802 write_register (argreg
, regval
);
3805 /* Prevent subsequent floating point arguments from
3806 being passed in floating point registers. */
3807 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3813 /* Compute the the offset into the stack at which we
3814 will copy the next parameter.
3816 In older ABIs, the caller reserved space for
3817 registers that contained arguments. This was loosely
3818 refered to as their "home". Consequently, space is
3819 always allocated. */
3821 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3825 fprintf_unfiltered (gdb_stdlog
, "\n");
3828 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3830 /* Return adjusted stack pointer. */
3835 mips_pop_frame (void)
3838 struct frame_info
*frame
= get_current_frame ();
3839 CORE_ADDR new_sp
= get_frame_base (frame
);
3840 mips_extra_func_info_t proc_desc
;
3842 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
3844 generic_pop_dummy_frame ();
3845 flush_cached_frames ();
3849 proc_desc
= get_frame_extra_info (frame
)->proc_desc
;
3850 write_register (PC_REGNUM
, DEPRECATED_FRAME_SAVED_PC (frame
));
3851 mips_find_saved_regs (frame
);
3852 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
3853 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
3854 && deprecated_get_frame_saved_regs (frame
)[regnum
])
3856 /* Floating point registers must not be sign extended,
3857 in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */
3859 if (mips_regnum (current_gdbarch
)->fp0
<= regnum
&& regnum
< mips_regnum (current_gdbarch
)->fp0
+ 32)
3860 write_register (regnum
,
3861 read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3862 MIPS_SAVED_REGSIZE
));
3864 write_register (regnum
,
3865 read_memory_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3866 MIPS_SAVED_REGSIZE
));
3869 write_register (SP_REGNUM
, new_sp
);
3870 flush_cached_frames ();
3872 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
3874 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
3876 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
3878 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
3880 if (&pi_ptr
->info
== proc_desc
)
3885 error ("Can't locate dummy extra frame info\n");
3887 if (prev_ptr
!= NULL
)
3888 prev_ptr
->next
= pi_ptr
->next
;
3890 linked_proc_desc_table
= pi_ptr
->next
;
3894 write_register (mips_regnum (current_gdbarch
)->hi
,
3895 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
3896 MIPS_SAVED_REGSIZE
));
3897 write_register (mips_regnum (current_gdbarch
)->lo
,
3898 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
3899 MIPS_SAVED_REGSIZE
));
3900 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
3901 write_register (mips_regnum (current_gdbarch
)->fp_control_status
,
3902 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
3903 MIPS_SAVED_REGSIZE
));
3907 /* Floating point register management.
3909 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3910 64bit operations, these early MIPS cpus treat fp register pairs
3911 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3912 registers and offer a compatibility mode that emulates the MIPS2 fp
3913 model. When operating in MIPS2 fp compat mode, later cpu's split
3914 double precision floats into two 32-bit chunks and store them in
3915 consecutive fp regs. To display 64-bit floats stored in this
3916 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3917 Throw in user-configurable endianness and you have a real mess.
3919 The way this works is:
3920 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3921 double-precision value will be split across two logical registers.
3922 The lower-numbered logical register will hold the low-order bits,
3923 regardless of the processor's endianness.
3924 - If we are on a 64-bit processor, and we are looking for a
3925 single-precision value, it will be in the low ordered bits
3926 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3927 save slot in memory.
3928 - If we are in 64-bit mode, everything is straightforward.
3930 Note that this code only deals with "live" registers at the top of the
3931 stack. We will attempt to deal with saved registers later, when
3932 the raw/cooked register interface is in place. (We need a general
3933 interface that can deal with dynamic saved register sizes -- fp
3934 regs could be 32 bits wide in one frame and 64 on the frame above
3937 static struct type
*
3938 mips_float_register_type (void)
3940 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3941 return builtin_type_ieee_single_big
;
3943 return builtin_type_ieee_single_little
;
3946 static struct type
*
3947 mips_double_register_type (void)
3949 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3950 return builtin_type_ieee_double_big
;
3952 return builtin_type_ieee_double_little
;
3955 /* Copy a 32-bit single-precision value from the current frame
3956 into rare_buffer. */
3959 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3962 int raw_size
= register_size (current_gdbarch
, regno
);
3963 char *raw_buffer
= alloca (raw_size
);
3965 if (!frame_register_read (frame
, regno
, raw_buffer
))
3966 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3969 /* We have a 64-bit value for this register. Find the low-order
3973 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3978 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3982 memcpy (rare_buffer
, raw_buffer
, 4);
3986 /* Copy a 64-bit double-precision value from the current frame into
3987 rare_buffer. This may include getting half of it from the next
3991 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
3994 int raw_size
= register_size (current_gdbarch
, regno
);
3996 if (raw_size
== 8 && !mips2_fp_compat ())
3998 /* We have a 64-bit value for this register, and we should use
4000 if (!frame_register_read (frame
, regno
, rare_buffer
))
4001 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4005 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4006 internal_error (__FILE__
, __LINE__
,
4007 "mips_read_fp_register_double: bad access to "
4008 "odd-numbered FP register");
4010 /* mips_read_fp_register_single will find the correct 32 bits from
4012 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4014 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4015 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4019 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4020 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4026 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4028 { /* do values for FP (float) regs */
4030 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
4031 int inv1
, inv2
, namelen
;
4033 raw_buffer
= (char *) alloca (2 * register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
));
4035 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4036 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4039 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4041 /* 4-byte registers: Print hex and floating. Also print even
4042 numbered registers as doubles. */
4043 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4044 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4046 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w', file
);
4048 fprintf_filtered (file
, " flt: ");
4050 fprintf_filtered (file
, " <invalid float> ");
4052 fprintf_filtered (file
, "%-17.9g", flt1
);
4054 if (regnum
% 2 == 0)
4056 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4057 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4060 fprintf_filtered (file
, " dbl: ");
4062 fprintf_filtered (file
, "<invalid double>");
4064 fprintf_filtered (file
, "%-24.17g", doub
);
4069 /* Eight byte registers: print each one as hex, float and double. */
4070 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4071 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4073 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4074 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4077 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g', file
);
4079 fprintf_filtered (file
, " flt: ");
4081 fprintf_filtered (file
, "<invalid float>");
4083 fprintf_filtered (file
, "%-17.9g", flt1
);
4085 fprintf_filtered (file
, " dbl: ");
4087 fprintf_filtered (file
, "<invalid double>");
4089 fprintf_filtered (file
, "%-24.17g", doub
);
4094 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4095 int regnum
, int all
)
4097 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4098 char raw_buffer
[MAX_REGISTER_SIZE
];
4101 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4103 mips_print_fp_register (file
, frame
, regnum
);
4107 /* Get the data in raw format. */
4108 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4110 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4114 fputs_filtered (REGISTER_NAME (regnum
), file
);
4116 /* The problem with printing numeric register names (r26, etc.) is that
4117 the user can't use them on input. Probably the best solution is to
4118 fix it so that either the numeric or the funky (a2, etc.) names
4119 are accepted on input. */
4120 if (regnum
< MIPS_NUMREGS
)
4121 fprintf_filtered (file
, "(r%d): ", regnum
);
4123 fprintf_filtered (file
, ": ");
4125 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4126 offset
= register_size (current_gdbarch
, regnum
) - register_size (current_gdbarch
, regnum
);
4130 print_scalar_formatted (raw_buffer
+ offset
, gdbarch_register_type (gdbarch
, regnum
),
4134 /* Replacement for generic do_registers_info.
4135 Print regs in pretty columns. */
4138 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4141 fprintf_filtered (file
, " ");
4142 mips_print_fp_register (file
, frame
, regnum
);
4143 fprintf_filtered (file
, "\n");
4148 /* Print a row's worth of GP (int) registers, with name labels above */
4151 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4154 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4155 /* do values for GP (int) regs */
4156 char raw_buffer
[MAX_REGISTER_SIZE
];
4157 int ncols
= (mips_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4161 /* For GP registers, we print a separate row of names above the vals */
4162 fprintf_filtered (file
, " ");
4163 for (col
= 0, regnum
= start_regnum
;
4164 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4167 if (*REGISTER_NAME (regnum
) == '\0')
4168 continue; /* unused register */
4169 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4170 break; /* end the row: reached FP register */
4171 fprintf_filtered (file
, mips_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4172 REGISTER_NAME (regnum
));
4175 /* print the R0 to R31 names */
4176 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4177 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4179 fprintf_filtered (file
, "\n ");
4181 /* now print the values in hex, 4 or 8 to the row */
4182 for (col
= 0, regnum
= start_regnum
;
4183 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4186 if (*REGISTER_NAME (regnum
) == '\0')
4187 continue; /* unused register */
4188 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4189 break; /* end row: reached FP register */
4190 /* OK: get the data in raw format. */
4191 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4192 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4193 /* pad small registers */
4195 byte
< (mips_regsize (current_gdbarch
)
4196 - register_size (current_gdbarch
, regnum
));
4198 printf_filtered (" ");
4199 /* Now print the register value in hex, endian order. */
4200 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4201 for (byte
= register_size (current_gdbarch
, regnum
) - register_size (current_gdbarch
, regnum
);
4202 byte
< register_size (current_gdbarch
, regnum
);
4204 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4206 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4209 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4210 fprintf_filtered (file
, " ");
4213 if (col
> 0) /* ie. if we actually printed anything... */
4214 fprintf_filtered (file
, "\n");
4219 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4222 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4223 struct frame_info
*frame
, int regnum
, int all
)
4225 if (regnum
!= -1) /* do one specified register */
4227 gdb_assert (regnum
>= NUM_REGS
);
4228 if (*(REGISTER_NAME (regnum
)) == '\0')
4229 error ("Not a valid register for the current processor type");
4231 mips_print_register (file
, frame
, regnum
, 0);
4232 fprintf_filtered (file
, "\n");
4235 /* do all (or most) registers */
4238 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4240 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4242 if (all
) /* true for "INFO ALL-REGISTERS" command */
4243 regnum
= print_fp_register_row (file
, frame
, regnum
);
4245 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4248 regnum
= print_gp_register_row (file
, frame
, regnum
);
4253 /* Is this a branch with a delay slot? */
4255 static int is_delayed (unsigned long);
4258 is_delayed (unsigned long insn
)
4261 for (i
= 0; i
< NUMOPCODES
; ++i
)
4262 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4263 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4265 return (i
< NUMOPCODES
4266 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4267 | INSN_COND_BRANCH_DELAY
4268 | INSN_COND_BRANCH_LIKELY
)));
4272 mips_step_skips_delay (CORE_ADDR pc
)
4274 char buf
[MIPS_INSTLEN
];
4276 /* There is no branch delay slot on MIPS16. */
4277 if (pc_is_mips16 (pc
))
4280 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4281 /* If error reading memory, guess that it is not a delayed branch. */
4283 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4287 /* Given PC at the function's start address, attempt to find the
4288 prologue end using SAL information. Return zero if the skip fails.
4290 A non-optimized prologue traditionally has one SAL for the function
4291 and a second for the function body. A single line function has
4292 them both pointing at the same line.
4294 An optimized prologue is similar but the prologue may contain
4295 instructions (SALs) from the instruction body. Need to skip those
4296 while not getting into the function body.
4298 The functions end point and an increasing SAL line are used as
4299 indicators of the prologue's endpoint.
4301 This code is based on the function refine_prologue_limit (versions
4302 found in both ia64 and ppc). */
4305 skip_prologue_using_sal (CORE_ADDR func_addr
)
4307 struct symtab_and_line prologue_sal
;
4311 /* Get an initial range for the function. */
4312 find_pc_partial_function (func_addr
, NULL
, &start_pc
, &end_pc
);
4313 start_pc
+= FUNCTION_START_OFFSET
;
4315 prologue_sal
= find_pc_line (start_pc
, 0);
4316 if (prologue_sal
.line
!= 0)
4318 while (prologue_sal
.end
< end_pc
)
4320 struct symtab_and_line sal
;
4322 sal
= find_pc_line (prologue_sal
.end
, 0);
4325 /* Assume that a consecutive SAL for the same (or larger)
4326 line mark the prologue -> body transition. */
4327 if (sal
.line
>= prologue_sal
.line
)
4329 /* The case in which compiler's optimizer/scheduler has
4330 moved instructions into the prologue. We look ahead in
4331 the function looking for address ranges whose
4332 corresponding line number is less the first one that we
4333 found for the function. This is more conservative then
4334 refine_prologue_limit which scans a large number of SALs
4335 looking for any in the prologue */
4339 return prologue_sal
.end
;
4342 /* Skip the PC past function prologue instructions (32-bit version).
4343 This is a helper function for mips_skip_prologue. */
4346 mips32_skip_prologue (CORE_ADDR pc
)
4350 int seen_sp_adjust
= 0;
4351 int load_immediate_bytes
= 0;
4353 /* Find an upper bound on the prologue. */
4354 end_pc
= skip_prologue_using_sal (pc
);
4356 end_pc
= pc
+ 100; /* Magic. */
4358 /* Skip the typical prologue instructions. These are the stack adjustment
4359 instruction and the instructions that save registers on the stack
4360 or in the gcc frame. */
4361 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4363 unsigned long high_word
;
4365 inst
= mips_fetch_instruction (pc
);
4366 high_word
= (inst
>> 16) & 0xffff;
4368 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4369 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4371 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4372 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4374 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4375 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4376 && (inst
& 0x001F0000)) /* reg != $zero */
4379 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4381 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4383 continue; /* reg != $zero */
4385 /* move $s8,$sp. With different versions of gas this will be either
4386 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4387 Accept any one of these. */
4388 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4391 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4393 else if (high_word
== 0x3c1c) /* lui $gp,n */
4395 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4397 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4398 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4400 /* The following instructions load $at or $t0 with an immediate
4401 value in preparation for a stack adjustment via
4402 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4403 a local variable, so we accept them only before a stack adjustment
4404 instruction was seen. */
4405 else if (!seen_sp_adjust
)
4407 if (high_word
== 0x3c01 || /* lui $at,n */
4408 high_word
== 0x3c08) /* lui $t0,n */
4410 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4413 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4414 high_word
== 0x3508 || /* ori $t0,$t0,n */
4415 high_word
== 0x3401 || /* ori $at,$zero,n */
4416 high_word
== 0x3408) /* ori $t0,$zero,n */
4418 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4428 /* In a frameless function, we might have incorrectly
4429 skipped some load immediate instructions. Undo the skipping
4430 if the load immediate was not followed by a stack adjustment. */
4431 if (load_immediate_bytes
&& !seen_sp_adjust
)
4432 pc
-= load_immediate_bytes
;
4436 /* Skip the PC past function prologue instructions (16-bit version).
4437 This is a helper function for mips_skip_prologue. */
4440 mips16_skip_prologue (CORE_ADDR pc
)
4443 int extend_bytes
= 0;
4444 int prev_extend_bytes
;
4446 /* Table of instructions likely to be found in a function prologue. */
4449 unsigned short inst
;
4450 unsigned short mask
;
4457 , /* addiu $sp,offset */
4461 , /* daddiu $sp,offset */
4465 , /* sw reg,n($sp) */
4469 , /* sd reg,n($sp) */
4473 , /* sw $ra,n($sp) */
4477 , /* sd $ra,n($sp) */
4485 , /* sw $a0-$a3,n($s1) */
4489 , /* move reg,$a0-$a3 */
4493 , /* entry pseudo-op */
4497 , /* addiu $s1,$sp,n */
4500 } /* end of table marker */
4503 /* Find an upper bound on the prologue. */
4504 end_pc
= skip_prologue_using_sal (pc
);
4506 end_pc
= pc
+ 100; /* Magic. */
4508 /* Skip the typical prologue instructions. These are the stack adjustment
4509 instruction and the instructions that save registers on the stack
4510 or in the gcc frame. */
4511 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4513 unsigned short inst
;
4516 inst
= mips_fetch_instruction (pc
);
4518 /* Normally we ignore an extend instruction. However, if it is
4519 not followed by a valid prologue instruction, we must adjust
4520 the pc back over the extend so that it won't be considered
4521 part of the prologue. */
4522 if ((inst
& 0xf800) == 0xf000) /* extend */
4524 extend_bytes
= MIPS16_INSTLEN
;
4527 prev_extend_bytes
= extend_bytes
;
4530 /* Check for other valid prologue instructions besides extend. */
4531 for (i
= 0; table
[i
].mask
!= 0; i
++)
4532 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4534 if (table
[i
].mask
!= 0) /* it was in table? */
4535 continue; /* ignore it */
4539 /* Return the current pc, adjusted backwards by 2 if
4540 the previous instruction was an extend. */
4541 return pc
- prev_extend_bytes
;
4547 /* To skip prologues, I use this predicate. Returns either PC itself
4548 if the code at PC does not look like a function prologue; otherwise
4549 returns an address that (if we're lucky) follows the prologue. If
4550 LENIENT, then we must skip everything which is involved in setting
4551 up the frame (it's OK to skip more, just so long as we don't skip
4552 anything which might clobber the registers which are being saved.
4553 We must skip more in the case where part of the prologue is in the
4554 delay slot of a non-prologue instruction). */
4557 mips_skip_prologue (CORE_ADDR pc
)
4559 /* See if we can determine the end of the prologue via the symbol table.
4560 If so, then return either PC, or the PC after the prologue, whichever
4563 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4565 if (post_prologue_pc
!= 0)
4566 return max (pc
, post_prologue_pc
);
4568 /* Can't determine prologue from the symbol table, need to examine
4571 if (pc_is_mips16 (pc
))
4572 return mips16_skip_prologue (pc
);
4574 return mips32_skip_prologue (pc
);
4577 /* Determine how a return value is stored within the MIPS register
4578 file, given the return type `valtype'. */
4580 struct return_value_word
4589 return_value_location (struct type
*valtype
,
4590 struct return_value_word
*hi
,
4591 struct return_value_word
*lo
)
4593 int len
= TYPE_LENGTH (valtype
);
4595 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
4596 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
4597 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
4599 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4601 /* We need to break a 64bit float in two 32 bit halves and
4602 spread them across a floating-point register pair. */
4603 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4604 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
4605 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4606 && register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 8)
4608 hi
->reg_offset
= lo
->reg_offset
;
4609 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
4610 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
4616 /* The floating point value fits in a single floating-point
4618 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4619 && register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 8
4622 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
4633 /* Locate a result possibly spread across two registers. */
4635 lo
->reg
= regnum
+ 0;
4636 hi
->reg
= regnum
+ 1;
4637 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4638 && len
< MIPS_SAVED_REGSIZE
)
4640 /* "un-left-justify" the value in the low register */
4641 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
4646 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4647 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
4648 && len
< MIPS_SAVED_REGSIZE
* 2
4649 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
4650 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
4652 /* "un-left-justify" the value spread across two registers. */
4653 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
4654 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
4656 hi
->len
= len
- lo
->len
;
4660 /* Only perform a partial copy of the second register. */
4663 if (len
> MIPS_SAVED_REGSIZE
)
4665 lo
->len
= MIPS_SAVED_REGSIZE
;
4666 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
4674 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4675 && register_size (current_gdbarch
, regnum
) == 8
4676 && MIPS_SAVED_REGSIZE
== 4)
4678 /* Account for the fact that only the least-signficant part
4679 of the register is being used */
4680 lo
->reg_offset
+= 4;
4681 hi
->reg_offset
+= 4;
4684 hi
->buf_offset
= lo
->len
;
4688 /* Given a return value in `regbuf' with a type `valtype', extract and
4689 copy its value into `valbuf'. */
4692 mips_eabi_extract_return_value (struct type
*valtype
,
4696 struct return_value_word lo
;
4697 struct return_value_word hi
;
4698 return_value_location (valtype
, &hi
, &lo
);
4700 memcpy (valbuf
+ lo
.buf_offset
,
4701 regbuf
+ DEPRECATED_REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4705 memcpy (valbuf
+ hi
.buf_offset
,
4706 regbuf
+ DEPRECATED_REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4711 mips_o64_extract_return_value (struct type
*valtype
,
4715 struct return_value_word lo
;
4716 struct return_value_word hi
;
4717 return_value_location (valtype
, &hi
, &lo
);
4719 memcpy (valbuf
+ lo
.buf_offset
,
4720 regbuf
+ DEPRECATED_REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4724 memcpy (valbuf
+ hi
.buf_offset
,
4725 regbuf
+ DEPRECATED_REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4729 /* Given a return value in `valbuf' with a type `valtype', write it's
4730 value into the appropriate register. */
4733 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
4735 char raw_buffer
[MAX_REGISTER_SIZE
];
4736 struct return_value_word lo
;
4737 struct return_value_word hi
;
4738 return_value_location (valtype
, &hi
, &lo
);
4740 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4741 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4742 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4743 register_size (current_gdbarch
, lo
.reg
));
4747 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4748 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4749 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4750 register_size (current_gdbarch
, hi
.reg
));
4755 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4757 char raw_buffer
[MAX_REGISTER_SIZE
];
4758 struct return_value_word lo
;
4759 struct return_value_word hi
;
4760 return_value_location (valtype
, &hi
, &lo
);
4762 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4763 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4764 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4765 register_size (current_gdbarch
, lo
.reg
));
4769 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4770 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4771 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4772 register_size (current_gdbarch
, hi
.reg
));
4776 /* O32 ABI stuff. */
4778 static enum return_value_convention
4779 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4780 struct regcache
*regcache
,
4781 void *readbuf
, const void *writebuf
)
4783 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4785 if (TYPE_CODE (type
)== TYPE_CODE_STRUCT
4786 || TYPE_CODE (type
)== TYPE_CODE_UNION
4787 || TYPE_CODE (type
)== TYPE_CODE_ARRAY
)
4788 return RETURN_VALUE_STRUCT_CONVENTION
;
4789 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4790 && TYPE_LENGTH (type
) == 4
4791 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4793 /* A single-precision floating-point value. It fits in the
4794 least significant part of FP0. */
4796 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4797 mips_xfer_register (regcache
,
4798 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4800 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4801 return RETURN_VALUE_REGISTER_CONVENTION
;
4803 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4804 && TYPE_LENGTH (type
) == 8
4805 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4807 /* A double-precision floating-point value. The most
4808 significant part goes in FP1, and the least significant in
4811 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4812 switch (TARGET_BYTE_ORDER
)
4814 case BFD_ENDIAN_LITTLE
:
4815 mips_xfer_register (regcache
,
4816 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 0,
4817 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4818 mips_xfer_register (regcache
,
4819 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 1,
4820 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4822 case BFD_ENDIAN_BIG
:
4823 mips_xfer_register (regcache
,
4824 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 1,
4825 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4826 mips_xfer_register (regcache
,
4827 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 0,
4828 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4831 internal_error (__FILE__
, __LINE__
, "bad switch");
4833 return RETURN_VALUE_REGISTER_CONVENTION
;
4836 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4837 && TYPE_NFIELDS (type
) <= 2
4838 && TYPE_NFIELDS (type
) >= 1
4839 && ((TYPE_NFIELDS (type
) == 1
4840 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4842 || (TYPE_NFIELDS (type
) == 2
4843 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4845 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4847 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4849 /* A struct that contains one or two floats. Each value is part
4850 in the least significant part of their floating point
4852 bfd_byte reg
[MAX_REGISTER_SIZE
];
4855 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4856 field
< TYPE_NFIELDS (type
);
4857 field
++, regnum
+= 2)
4859 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4862 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4863 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4864 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4865 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4867 return RETURN_VALUE_REGISTER_CONVENTION
;
4871 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4872 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4874 /* A structure or union. Extract the left justified value,
4875 regardless of the byte order. I.e. DO NOT USE
4879 for (offset
= 0, regnum
= V0_REGNUM
;
4880 offset
< TYPE_LENGTH (type
);
4881 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4883 int xfer
= register_size (current_gdbarch
, regnum
);
4884 if (offset
+ xfer
> TYPE_LENGTH (type
))
4885 xfer
= TYPE_LENGTH (type
) - offset
;
4887 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4888 offset
, xfer
, regnum
);
4889 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4890 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4892 return RETURN_VALUE_REGISTER_CONVENTION
;
4897 /* A scalar extract each part but least-significant-byte
4898 justified. o32 thinks registers are 4 byte, regardless of
4899 the ISA. mips_stack_argsize controls this. */
4902 for (offset
= 0, regnum
= V0_REGNUM
;
4903 offset
< TYPE_LENGTH (type
);
4904 offset
+= mips_stack_argsize (), regnum
++)
4906 int xfer
= mips_stack_argsize ();
4908 if (offset
+ xfer
> TYPE_LENGTH (type
))
4909 xfer
= TYPE_LENGTH (type
) - offset
;
4911 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4912 offset
, xfer
, regnum
);
4913 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4914 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4916 return RETURN_VALUE_REGISTER_CONVENTION
;
4920 /* N32/N44 ABI stuff. */
4922 static enum return_value_convention
4923 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
4924 struct type
*type
, struct regcache
*regcache
,
4925 void *readbuf
, const void *writebuf
)
4927 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4928 if (TYPE_CODE (type
)== TYPE_CODE_STRUCT
4929 || TYPE_CODE (type
)== TYPE_CODE_UNION
4930 || TYPE_CODE (type
)== TYPE_CODE_ARRAY
4931 || TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
)
4932 return RETURN_VALUE_STRUCT_CONVENTION
;
4933 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4934 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4936 /* A floating-point value belongs in the least significant part
4939 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4940 mips_xfer_register (regcache
,
4941 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4943 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4944 return RETURN_VALUE_REGISTER_CONVENTION
;
4946 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4947 && TYPE_NFIELDS (type
) <= 2
4948 && TYPE_NFIELDS (type
) >= 1
4949 && ((TYPE_NFIELDS (type
) == 1
4950 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4952 || (TYPE_NFIELDS (type
) == 2
4953 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4955 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4957 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4959 /* A struct that contains one or two floats. Each value is part
4960 in the least significant part of their floating point
4962 bfd_byte reg
[MAX_REGISTER_SIZE
];
4965 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4966 field
< TYPE_NFIELDS (type
);
4967 field
++, regnum
+= 2)
4969 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4972 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4973 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4974 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4975 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4977 return RETURN_VALUE_REGISTER_CONVENTION
;
4979 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4980 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4982 /* A structure or union. Extract the left justified value,
4983 regardless of the byte order. I.e. DO NOT USE
4987 for (offset
= 0, regnum
= V0_REGNUM
;
4988 offset
< TYPE_LENGTH (type
);
4989 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4991 int xfer
= register_size (current_gdbarch
, regnum
);
4992 if (offset
+ xfer
> TYPE_LENGTH (type
))
4993 xfer
= TYPE_LENGTH (type
) - offset
;
4995 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4996 offset
, xfer
, regnum
);
4997 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4998 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5000 return RETURN_VALUE_REGISTER_CONVENTION
;
5004 /* A scalar extract each part but least-significant-byte
5008 for (offset
= 0, regnum
= V0_REGNUM
;
5009 offset
< TYPE_LENGTH (type
);
5010 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
5012 int xfer
= register_size (current_gdbarch
, regnum
);
5014 if (offset
+ xfer
> TYPE_LENGTH (type
))
5015 xfer
= TYPE_LENGTH (type
) - offset
;
5017 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5018 offset
, xfer
, regnum
);
5019 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
5020 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
5022 return RETURN_VALUE_REGISTER_CONVENTION
;
5027 mips_extract_struct_value_address (struct regcache
*regcache
)
5029 /* FIXME: This will only work at random. The caller passes the
5030 struct_return address in V0, but it is not preserved. It may
5031 still be there, or this may be a random value. */
5034 regcache_cooked_read_signed (regcache
, V0_REGNUM
, &val
);
5038 /* Exported procedure: Is PC in the signal trampoline code */
5041 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
5043 if (sigtramp_address
== 0)
5045 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
5048 /* Root of all "set mips "/"show mips " commands. This will eventually be
5049 used for all MIPS-specific commands. */
5052 show_mips_command (char *args
, int from_tty
)
5054 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5058 set_mips_command (char *args
, int from_tty
)
5060 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
5061 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5064 /* Commands to show/set the MIPS FPU type. */
5067 show_mipsfpu_command (char *args
, int from_tty
)
5070 switch (MIPS_FPU_TYPE
)
5072 case MIPS_FPU_SINGLE
:
5073 fpu
= "single-precision";
5075 case MIPS_FPU_DOUBLE
:
5076 fpu
= "double-precision";
5079 fpu
= "absent (none)";
5082 internal_error (__FILE__
, __LINE__
, "bad switch");
5084 if (mips_fpu_type_auto
)
5085 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5088 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
5094 set_mipsfpu_command (char *args
, int from_tty
)
5096 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5097 show_mipsfpu_command (args
, from_tty
);
5101 set_mipsfpu_single_command (char *args
, int from_tty
)
5103 mips_fpu_type
= MIPS_FPU_SINGLE
;
5104 mips_fpu_type_auto
= 0;
5105 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
5109 set_mipsfpu_double_command (char *args
, int from_tty
)
5111 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5112 mips_fpu_type_auto
= 0;
5113 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5117 set_mipsfpu_none_command (char *args
, int from_tty
)
5119 mips_fpu_type
= MIPS_FPU_NONE
;
5120 mips_fpu_type_auto
= 0;
5121 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
5125 set_mipsfpu_auto_command (char *args
, int from_tty
)
5127 mips_fpu_type_auto
= 1;
5130 /* Attempt to identify the particular processor model by reading the
5131 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5132 the relevant processor still exists (it dates back to '94) and
5133 secondly this is not the way to do this. The processor type should
5134 be set by forcing an architecture change. */
5137 deprecated_mips_set_processor_regs_hack (void)
5139 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5142 prid
= read_register (PRID_REGNUM
);
5144 if ((prid
& ~0xf) == 0x700)
5145 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5148 /* Just like reinit_frame_cache, but with the right arguments to be
5149 callable as an sfunc. */
5152 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5153 struct cmd_list_element
*c
)
5155 reinit_frame_cache ();
5159 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5161 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5162 mips_extra_func_info_t proc_desc
;
5164 /* Search for the function containing this address. Set the low bit
5165 of the address when searching, in case we were given an even address
5166 that is the start of a 16-bit function. If we didn't do this,
5167 the search would fail because the symbol table says the function
5168 starts at an odd address, i.e. 1 byte past the given address. */
5169 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5170 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5172 /* Make an attempt to determine if this is a 16-bit function. If
5173 the procedure descriptor exists and the address therein is odd,
5174 it's definitely a 16-bit function. Otherwise, we have to just
5175 guess that if the address passed in is odd, it's 16-bits. */
5176 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5177 disassembler needs to be able to locally determine the ISA, and
5178 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5182 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5183 info
->mach
= bfd_mach_mips16
;
5187 if (pc_is_mips16 (memaddr
))
5188 info
->mach
= bfd_mach_mips16
;
5191 /* Round down the instruction address to the appropriate boundary. */
5192 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5194 /* Set the disassembler options. */
5195 if (tdep
->mips_abi
== MIPS_ABI_N32
5196 || tdep
->mips_abi
== MIPS_ABI_N64
)
5198 /* Set up the disassembler info, so that we get the right
5199 register names from libopcodes. */
5200 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5201 info
->disassembler_options
= "gpr-names=n32";
5203 info
->disassembler_options
= "gpr-names=64";
5204 info
->flavour
= bfd_target_elf_flavour
;
5207 /* This string is not recognized explicitly by the disassembler,
5208 but it tells the disassembler to not try to guess the ABI from
5209 the bfd elf headers, such that, if the user overrides the ABI
5210 of a program linked as NewABI, the disassembly will follow the
5211 register naming conventions specified by the user. */
5212 info
->disassembler_options
= "gpr-names=32";
5214 /* Call the appropriate disassembler based on the target endian-ness. */
5215 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5216 return print_insn_big_mips (memaddr
, info
);
5218 return print_insn_little_mips (memaddr
, info
);
5221 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5222 counter value to determine whether a 16- or 32-bit breakpoint should be
5223 used. It returns a pointer to a string of bytes that encode a breakpoint
5224 instruction, stores the length of the string to *lenptr, and adjusts pc
5225 (if necessary) to point to the actual memory location where the
5226 breakpoint should be inserted. */
5228 static const unsigned char *
5229 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
5231 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5233 if (pc_is_mips16 (*pcptr
))
5235 static unsigned char mips16_big_breakpoint
[] = {0xe8, 0xa5};
5236 *pcptr
= unmake_mips16_addr (*pcptr
);
5237 *lenptr
= sizeof (mips16_big_breakpoint
);
5238 return mips16_big_breakpoint
;
5242 /* The IDT board uses an unusual breakpoint value, and
5243 sometimes gets confused when it sees the usual MIPS
5244 breakpoint instruction. */
5245 static unsigned char big_breakpoint
[] = {0, 0x5, 0, 0xd};
5246 static unsigned char pmon_big_breakpoint
[] = {0, 0, 0, 0xd};
5247 static unsigned char idt_big_breakpoint
[] = {0, 0, 0x0a, 0xd};
5249 *lenptr
= sizeof (big_breakpoint
);
5251 if (strcmp (target_shortname
, "mips") == 0)
5252 return idt_big_breakpoint
;
5253 else if (strcmp (target_shortname
, "ddb") == 0
5254 || strcmp (target_shortname
, "pmon") == 0
5255 || strcmp (target_shortname
, "lsi") == 0)
5256 return pmon_big_breakpoint
;
5258 return big_breakpoint
;
5263 if (pc_is_mips16 (*pcptr
))
5265 static unsigned char mips16_little_breakpoint
[] = {0xa5, 0xe8};
5266 *pcptr
= unmake_mips16_addr (*pcptr
);
5267 *lenptr
= sizeof (mips16_little_breakpoint
);
5268 return mips16_little_breakpoint
;
5272 static unsigned char little_breakpoint
[] = {0xd, 0, 0x5, 0};
5273 static unsigned char pmon_little_breakpoint
[] = {0xd, 0, 0, 0};
5274 static unsigned char idt_little_breakpoint
[] = {0xd, 0x0a, 0, 0};
5276 *lenptr
= sizeof (little_breakpoint
);
5278 if (strcmp (target_shortname
, "mips") == 0)
5279 return idt_little_breakpoint
;
5280 else if (strcmp (target_shortname
, "ddb") == 0
5281 || strcmp (target_shortname
, "pmon") == 0
5282 || strcmp (target_shortname
, "lsi") == 0)
5283 return pmon_little_breakpoint
;
5285 return little_breakpoint
;
5290 /* If PC is in a mips16 call or return stub, return the address of the target
5291 PC, which is either the callee or the caller. There are several
5292 cases which must be handled:
5294 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5295 target PC is in $31 ($ra).
5296 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5297 and the target PC is in $2.
5298 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5299 before the jal instruction, this is effectively a call stub
5300 and the the target PC is in $2. Otherwise this is effectively
5301 a return stub and the target PC is in $18.
5303 See the source code for the stubs in gcc/config/mips/mips16.S for
5306 This function implements the SKIP_TRAMPOLINE_CODE macro.
5310 mips_skip_stub (CORE_ADDR pc
)
5313 CORE_ADDR start_addr
;
5315 /* Find the starting address and name of the function containing the PC. */
5316 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5319 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5320 target PC is in $31 ($ra). */
5321 if (strcmp (name
, "__mips16_ret_sf") == 0
5322 || strcmp (name
, "__mips16_ret_df") == 0)
5323 return read_signed_register (RA_REGNUM
);
5325 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5327 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5328 and the target PC is in $2. */
5329 if (name
[19] >= '0' && name
[19] <= '9')
5330 return read_signed_register (2);
5332 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5333 before the jal instruction, this is effectively a call stub
5334 and the the target PC is in $2. Otherwise this is effectively
5335 a return stub and the target PC is in $18. */
5336 else if (name
[19] == 's' || name
[19] == 'd')
5338 if (pc
== start_addr
)
5340 /* Check if the target of the stub is a compiler-generated
5341 stub. Such a stub for a function bar might have a name
5342 like __fn_stub_bar, and might look like this:
5347 la $1,bar (becomes a lui/addiu pair)
5349 So scan down to the lui/addi and extract the target
5350 address from those two instructions. */
5352 CORE_ADDR target_pc
= read_signed_register (2);
5356 /* See if the name of the target function is __fn_stub_*. */
5357 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
5359 if (strncmp (name
, "__fn_stub_", 10) != 0
5360 && strcmp (name
, "etext") != 0
5361 && strcmp (name
, "_etext") != 0)
5364 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5365 The limit on the search is arbitrarily set to 20
5366 instructions. FIXME. */
5367 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5369 inst
= mips_fetch_instruction (target_pc
);
5370 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5371 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5372 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5373 return pc
| (inst
& 0xffff); /* low word */
5376 /* Couldn't find the lui/addui pair, so return stub address. */
5380 /* This is the 'return' part of a call stub. The return
5381 address is in $r18. */
5382 return read_signed_register (18);
5385 return 0; /* not a stub */
5389 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5390 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5393 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5395 CORE_ADDR start_addr
;
5397 /* Find the starting address of the function containing the PC. If the
5398 caller didn't give us a name, look it up at the same time. */
5399 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
5402 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5404 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5405 if (name
[19] >= '0' && name
[19] <= '9')
5407 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5408 before the jal instruction, this is effectively a call stub. */
5409 else if (name
[19] == 's' || name
[19] == 'd')
5410 return pc
== start_addr
;
5413 return 0; /* not a stub */
5417 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5418 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5421 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5423 CORE_ADDR start_addr
;
5425 /* Find the starting address of the function containing the PC. */
5426 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5429 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5430 if (strcmp (name
, "__mips16_ret_sf") == 0
5431 || strcmp (name
, "__mips16_ret_df") == 0)
5434 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5435 i.e. after the jal instruction, this is effectively a return stub. */
5436 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5437 && (name
[19] == 's' || name
[19] == 'd')
5438 && pc
!= start_addr
)
5441 return 0; /* not a stub */
5445 /* Return non-zero if the PC is in a library helper function that should
5446 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5449 mips_ignore_helper (CORE_ADDR pc
)
5453 /* Find the starting address and name of the function containing the PC. */
5454 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5457 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5458 that we want to ignore. */
5459 return (strcmp (name
, "__mips16_ret_sf") == 0
5460 || strcmp (name
, "__mips16_ret_df") == 0);
5464 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5465 the register stored on the stack (32) is different to its real raw
5466 size (64). The below ensures that registers are fetched from the
5467 stack using their ABI size and then stored into the RAW_BUFFER
5468 using their raw size.
5470 The alternative to adding this function would be to add an ABI
5471 macro - REGISTER_STACK_SIZE(). */
5474 mips_get_saved_register (char *raw_buffer
,
5477 struct frame_info
*frame
,
5479 enum lval_type
*lvalp
)
5482 enum lval_type lvalx
;
5486 /* Always a pseudo. */
5487 gdb_assert (regnum
>= NUM_REGS
);
5489 /* Make certain that all needed parameters are present. */
5494 if (optimizedp
== NULL
)
5495 optimizedp
= &optimizedx
;
5497 if ((regnum
% NUM_REGS
) == SP_REGNUM
)
5498 /* The SP_REGNUM is special, its value is stored in saved_regs.
5499 In fact, it is so special that it can even only be fetched
5500 using a raw register number! Once this code as been converted
5501 to frame-unwind the problem goes away. */
5502 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5503 regnum
% NUM_REGS
, optimizedp
, lvalp
, addrp
,
5504 &realnumx
, raw_buffer
);
5506 /* Get it from the next frame. */
5507 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5508 regnum
, optimizedp
, lvalp
, addrp
,
5509 &realnumx
, raw_buffer
);
5512 /* Immediately after a function call, return the saved pc.
5513 Can't always go through the frames for this because on some machines
5514 the new frame is not set up until the new function executes
5515 some instructions. */
5518 mips_saved_pc_after_call (struct frame_info
*frame
)
5520 return read_signed_register (RA_REGNUM
);
5524 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5525 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5528 mips_stab_reg_to_regnum (int num
)
5531 if (num
>= 0 && num
< 32)
5533 else if (num
>= 38 && num
< 70)
5534 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5536 regnum
= mips_regnum (current_gdbarch
)->hi
;
5538 regnum
= mips_regnum (current_gdbarch
)->lo
;
5540 /* This will hopefully (eventually) provoke a warning. Should
5541 we be calling complaint() here? */
5542 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5543 return NUM_REGS
+ regnum
;
5547 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5548 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5551 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5554 if (num
>= 0 && num
< 32)
5556 else if (num
>= 32 && num
< 64)
5557 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5559 regnum
= mips_regnum (current_gdbarch
)->hi
;
5561 regnum
= mips_regnum (current_gdbarch
)->lo
;
5563 /* This will hopefully (eventually) provoke a warning. Should we
5564 be calling complaint() here? */
5565 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5566 return NUM_REGS
+ regnum
;
5570 mips_register_sim_regno (int regnum
)
5572 /* Only makes sense to supply raw registers. */
5573 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5574 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5575 decide if it is valid. Should instead define a standard sim/gdb
5576 register numbering scheme. */
5577 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5578 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5581 return LEGACY_SIM_REGNO_IGNORE
;
5585 /* Convert an integer into an address. By first converting the value
5586 into a pointer and then extracting it signed, the address is
5587 guarenteed to be correctly sign extended. */
5590 mips_integer_to_address (struct type
*type
, void *buf
)
5592 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5593 LONGEST val
= unpack_long (type
, buf
);
5594 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5595 return extract_signed_integer (tmp
,
5596 TYPE_LENGTH (builtin_type_void_data_ptr
));
5600 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5602 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5603 const char *name
= bfd_get_section_name (abfd
, sect
);
5605 if (*abip
!= MIPS_ABI_UNKNOWN
)
5608 if (strncmp (name
, ".mdebug.", 8) != 0)
5611 if (strcmp (name
, ".mdebug.abi32") == 0)
5612 *abip
= MIPS_ABI_O32
;
5613 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5614 *abip
= MIPS_ABI_N32
;
5615 else if (strcmp (name
, ".mdebug.abi64") == 0)
5616 *abip
= MIPS_ABI_N64
;
5617 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5618 *abip
= MIPS_ABI_O64
;
5619 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5620 *abip
= MIPS_ABI_EABI32
;
5621 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5622 *abip
= MIPS_ABI_EABI64
;
5624 warning ("unsupported ABI %s.", name
+ 8);
5627 static enum mips_abi
5628 global_mips_abi (void)
5632 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5633 if (mips_abi_strings
[i
] == mips_abi_string
)
5634 return (enum mips_abi
) i
;
5636 internal_error (__FILE__
, __LINE__
,
5637 "unknown ABI string");
5640 static struct gdbarch
*
5641 mips_gdbarch_init (struct gdbarch_info info
,
5642 struct gdbarch_list
*arches
)
5644 struct gdbarch
*gdbarch
;
5645 struct gdbarch_tdep
*tdep
;
5647 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5654 /* First of all, extract the elf_flags, if available. */
5655 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5656 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5659 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5660 switch ((elf_flags
& EF_MIPS_ABI
))
5662 case E_MIPS_ABI_O32
:
5663 mips_abi
= MIPS_ABI_O32
;
5665 case E_MIPS_ABI_O64
:
5666 mips_abi
= MIPS_ABI_O64
;
5668 case E_MIPS_ABI_EABI32
:
5669 mips_abi
= MIPS_ABI_EABI32
;
5671 case E_MIPS_ABI_EABI64
:
5672 mips_abi
= MIPS_ABI_EABI64
;
5675 if ((elf_flags
& EF_MIPS_ABI2
))
5676 mips_abi
= MIPS_ABI_N32
;
5678 mips_abi
= MIPS_ABI_UNKNOWN
;
5682 /* GCC creates a pseudo-section whose name describes the ABI. */
5683 if (mips_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5684 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &mips_abi
);
5686 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
5687 Use the ABI from the last architecture if there is one. */
5688 if (info
.abfd
== NULL
&& arches
!= NULL
)
5689 mips_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5691 /* Try the architecture for any hint of the correct ABI. */
5692 if (mips_abi
== MIPS_ABI_UNKNOWN
5693 && info
.bfd_arch_info
!= NULL
5694 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5696 switch (info
.bfd_arch_info
->mach
)
5698 case bfd_mach_mips3900
:
5699 mips_abi
= MIPS_ABI_EABI32
;
5701 case bfd_mach_mips4100
:
5702 case bfd_mach_mips5000
:
5703 mips_abi
= MIPS_ABI_EABI64
;
5705 case bfd_mach_mips8000
:
5706 case bfd_mach_mips10000
:
5707 /* On Irix, ELF64 executables use the N64 ABI. The
5708 pseudo-sections which describe the ABI aren't present
5709 on IRIX. (Even for executables created by gcc.) */
5710 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5711 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5712 mips_abi
= MIPS_ABI_N64
;
5714 mips_abi
= MIPS_ABI_N32
;
5719 if (mips_abi
== MIPS_ABI_UNKNOWN
)
5720 mips_abi
= MIPS_ABI_O32
;
5722 /* Now that we have found what the ABI for this binary would be,
5723 check whether the user is overriding it. */
5724 found_abi
= mips_abi
;
5725 wanted_abi
= global_mips_abi ();
5726 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5727 mips_abi
= wanted_abi
;
5731 fprintf_unfiltered (gdb_stdlog
,
5732 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5734 fprintf_unfiltered (gdb_stdlog
,
5735 "mips_gdbarch_init: mips_abi = %d\n",
5737 fprintf_unfiltered (gdb_stdlog
,
5738 "mips_gdbarch_init: found_mips_abi = %d\n",
5742 /* try to find a pre-existing architecture */
5743 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5745 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5747 /* MIPS needs to be pedantic about which ABI the object is
5749 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5751 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5753 /* Need to be pedantic about which register virtual size is
5755 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5756 != mips64_transfers_32bit_regs_p
)
5758 return arches
->gdbarch
;
5761 /* Need a new architecture. Fill in a target specific vector. */
5762 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5763 gdbarch
= gdbarch_alloc (&info
, tdep
);
5764 tdep
->elf_flags
= elf_flags
;
5765 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5767 /* Initially set everything according to the default ABI/ISA. */
5768 set_gdbarch_short_bit (gdbarch
, 16);
5769 set_gdbarch_int_bit (gdbarch
, 32);
5770 set_gdbarch_float_bit (gdbarch
, 32);
5771 set_gdbarch_double_bit (gdbarch
, 64);
5772 set_gdbarch_long_double_bit (gdbarch
, 64);
5773 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5774 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5775 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5776 tdep
->found_abi
= found_abi
;
5777 tdep
->mips_abi
= mips_abi
;
5779 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5780 mips_elf_make_msymbol_special
);
5782 /* Fill in the OS dependant register numbers. */
5784 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5785 struct mips_regnum
);
5786 tdep
->regnum
= regnum
;
5787 if (info
.osabi
== GDB_OSABI_IRIX
)
5792 regnum
->badvaddr
= 66;
5795 regnum
->fp_control_status
= 69;
5796 regnum
->fp_implementation_revision
= 70;
5801 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5802 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5803 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5804 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5805 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5806 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5807 regnum
->fp_control_status
= 70;
5808 regnum
->fp_implementation_revision
= 71;
5811 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5812 replaced by read_pc? */
5813 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
);
5814 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5815 set_gdbarch_num_regs (gdbarch
, num_regs
);
5816 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5822 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5823 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5824 tdep
->mips_default_saved_regsize
= 4;
5825 tdep
->mips_default_stack_argsize
= 4;
5826 tdep
->mips_fp_register_double
= 0;
5827 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5828 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5829 tdep
->default_mask_address_p
= 0;
5830 set_gdbarch_long_bit (gdbarch
, 32);
5831 set_gdbarch_ptr_bit (gdbarch
, 32);
5832 set_gdbarch_long_long_bit (gdbarch
, 64);
5833 set_gdbarch_deprecated_reg_struct_has_addr
5834 (gdbarch
, mips_o32_reg_struct_has_addr
);
5837 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5838 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_o64_store_return_value
);
5839 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_o64_extract_return_value
);
5840 tdep
->mips_default_saved_regsize
= 8;
5841 tdep
->mips_default_stack_argsize
= 8;
5842 tdep
->mips_fp_register_double
= 1;
5843 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5844 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5845 tdep
->default_mask_address_p
= 0;
5846 set_gdbarch_long_bit (gdbarch
, 32);
5847 set_gdbarch_ptr_bit (gdbarch
, 32);
5848 set_gdbarch_long_long_bit (gdbarch
, 64);
5849 set_gdbarch_deprecated_reg_struct_has_addr
5850 (gdbarch
, mips_o32_reg_struct_has_addr
);
5851 set_gdbarch_use_struct_convention (gdbarch
, always_use_struct_convention
);
5853 case MIPS_ABI_EABI32
:
5854 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5855 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5856 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5857 tdep
->mips_default_saved_regsize
= 4;
5858 tdep
->mips_default_stack_argsize
= 4;
5859 tdep
->mips_fp_register_double
= 0;
5860 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5861 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5862 tdep
->default_mask_address_p
= 0;
5863 set_gdbarch_long_bit (gdbarch
, 32);
5864 set_gdbarch_ptr_bit (gdbarch
, 32);
5865 set_gdbarch_long_long_bit (gdbarch
, 64);
5866 set_gdbarch_deprecated_reg_struct_has_addr
5867 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5868 set_gdbarch_use_struct_convention (gdbarch
,
5869 mips_eabi_use_struct_convention
);
5871 case MIPS_ABI_EABI64
:
5872 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5873 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5874 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5875 tdep
->mips_default_saved_regsize
= 8;
5876 tdep
->mips_default_stack_argsize
= 8;
5877 tdep
->mips_fp_register_double
= 1;
5878 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5879 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5880 tdep
->default_mask_address_p
= 0;
5881 set_gdbarch_long_bit (gdbarch
, 64);
5882 set_gdbarch_ptr_bit (gdbarch
, 64);
5883 set_gdbarch_long_long_bit (gdbarch
, 64);
5884 set_gdbarch_deprecated_reg_struct_has_addr
5885 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5886 set_gdbarch_use_struct_convention (gdbarch
,
5887 mips_eabi_use_struct_convention
);
5890 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5891 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5892 tdep
->mips_default_saved_regsize
= 8;
5893 tdep
->mips_default_stack_argsize
= 8;
5894 tdep
->mips_fp_register_double
= 1;
5895 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5896 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5897 tdep
->default_mask_address_p
= 0;
5898 set_gdbarch_long_bit (gdbarch
, 32);
5899 set_gdbarch_ptr_bit (gdbarch
, 32);
5900 set_gdbarch_long_long_bit (gdbarch
, 64);
5901 set_gdbarch_deprecated_reg_struct_has_addr
5902 (gdbarch
, mips_n32n64_reg_struct_has_addr
);
5905 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5906 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5907 tdep
->mips_default_saved_regsize
= 8;
5908 tdep
->mips_default_stack_argsize
= 8;
5909 tdep
->mips_fp_register_double
= 1;
5910 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5911 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5912 tdep
->default_mask_address_p
= 0;
5913 set_gdbarch_long_bit (gdbarch
, 64);
5914 set_gdbarch_ptr_bit (gdbarch
, 64);
5915 set_gdbarch_long_long_bit (gdbarch
, 64);
5916 set_gdbarch_deprecated_reg_struct_has_addr
5917 (gdbarch
, mips_n32n64_reg_struct_has_addr
);
5920 internal_error (__FILE__
, __LINE__
,
5921 "unknown ABI in switch");
5924 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5925 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5928 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5929 flag in object files because to do so would make it impossible to
5930 link with libraries compiled without "-gp32". This is
5931 unnecessarily restrictive.
5933 We could solve this problem by adding "-gp32" multilibs to gcc,
5934 but to set this flag before gcc is built with such multilibs will
5935 break too many systems.''
5937 But even more unhelpfully, the default linker output target for
5938 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5939 for 64-bit programs - you need to change the ABI to change this,
5940 and not all gcc targets support that currently. Therefore using
5941 this flag to detect 32-bit mode would do the wrong thing given
5942 the current gcc - it would make GDB treat these 64-bit programs
5943 as 32-bit programs by default. */
5945 /* enable/disable the MIPS FPU */
5946 if (!mips_fpu_type_auto
)
5947 tdep
->mips_fpu_type
= mips_fpu_type
;
5948 else if (info
.bfd_arch_info
!= NULL
5949 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5950 switch (info
.bfd_arch_info
->mach
)
5952 case bfd_mach_mips3900
:
5953 case bfd_mach_mips4100
:
5954 case bfd_mach_mips4111
:
5955 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
5957 case bfd_mach_mips4650
:
5958 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
5961 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5965 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5967 /* MIPS version of register names. */
5968 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5969 if (info
.osabi
== GDB_OSABI_IRIX
)
5970 tdep
->mips_processor_reg_names
= mips_irix_reg_names
;
5971 else if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5972 tdep
->mips_processor_reg_names
= mips_tx39_reg_names
;
5974 tdep
->mips_processor_reg_names
= mips_generic_reg_names
;
5975 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5976 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
5977 set_gdbarch_deprecated_target_read_fp (gdbarch
, mips_read_sp
); /* Draft FRAME base. */
5978 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5980 /* Add/remove bits from an address. The MIPS needs be careful to
5981 ensure that all 32 bit addresses are sign extended to 64 bits. */
5982 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5984 /* There's a mess in stack frame creation. See comments in
5985 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
5986 set_gdbarch_deprecated_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
5988 /* Map debug register numbers onto internal register numbers. */
5989 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5990 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5991 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5992 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5993 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5995 /* Initialize a frame */
5996 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch
, mips_find_saved_regs
);
5997 set_gdbarch_deprecated_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
5999 /* MIPS version of CALL_DUMMY */
6001 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6002 replaced by a command, and all targets will default to on stack
6003 (regardless of the stack's execute status). */
6004 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6005 set_gdbarch_deprecated_pop_frame (gdbarch
, mips_pop_frame
);
6006 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6007 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
6009 set_gdbarch_deprecated_frame_chain (gdbarch
, mips_frame_chain
);
6010 set_gdbarch_frameless_function_invocation (gdbarch
,
6011 generic_frameless_function_invocation_not
);
6012 set_gdbarch_deprecated_frame_saved_pc (gdbarch
, mips_frame_saved_pc
);
6013 set_gdbarch_frame_args_skip (gdbarch
, 0);
6015 set_gdbarch_deprecated_get_saved_register (gdbarch
, mips_get_saved_register
);
6017 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6018 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6019 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
6021 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6022 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
6024 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6025 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6026 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6028 set_gdbarch_function_start_offset (gdbarch
, 0);
6030 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6032 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6033 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
6035 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6037 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6038 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6039 need to all be folded into the target vector. Since they are
6040 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6041 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6043 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6045 /* Hook in OS ABI-specific overrides, if they have been registered. */
6046 gdbarch_init_osabi (info
, gdbarch
);
6048 set_gdbarch_extract_struct_value_address (gdbarch
,
6049 mips_extract_struct_value_address
);
6051 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6053 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6054 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6060 mips_abi_update (char *ignore_args
, int from_tty
,
6061 struct cmd_list_element
*c
)
6063 struct gdbarch_info info
;
6065 /* Force the architecture to update, and (if it's a MIPS architecture)
6066 mips_gdbarch_init will take care of the rest. */
6067 gdbarch_info_init (&info
);
6068 gdbarch_update_p (info
);
6071 /* Print out which MIPS ABI is in use. */
6074 show_mips_abi (char *ignore_args
, int from_tty
)
6076 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6078 "The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6081 enum mips_abi global_abi
= global_mips_abi ();
6082 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6083 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6085 if (global_abi
== MIPS_ABI_UNKNOWN
)
6086 printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n",
6088 else if (global_abi
== actual_abi
)
6090 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6094 /* Probably shouldn't happen... */
6096 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6098 mips_abi_strings
[global_abi
]);
6104 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6106 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6110 int ef_mips_32bitmode
;
6111 /* determine the ISA */
6112 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6130 /* determine the size of a pointer */
6131 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6132 fprintf_unfiltered (file
,
6133 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6135 fprintf_unfiltered (file
,
6136 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6138 fprintf_unfiltered (file
,
6139 "mips_dump_tdep: ef_mips_arch = %d\n",
6141 fprintf_unfiltered (file
,
6142 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6144 mips_abi_strings
[tdep
->mips_abi
]);
6145 fprintf_unfiltered (file
,
6146 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6147 mips_mask_address_p (),
6148 tdep
->default_mask_address_p
);
6150 fprintf_unfiltered (file
,
6151 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6152 FP_REGISTER_DOUBLE
);
6153 fprintf_unfiltered (file
,
6154 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6155 MIPS_DEFAULT_FPU_TYPE
,
6156 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6157 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6158 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6160 fprintf_unfiltered (file
,
6161 "mips_dump_tdep: MIPS_EABI = %d\n",
6163 fprintf_unfiltered (file
,
6164 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6166 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6167 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6168 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6170 fprintf_unfiltered (file
,
6171 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
6172 MIPS_DEFAULT_SAVED_REGSIZE
);
6173 fprintf_unfiltered (file
,
6174 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6175 FP_REGISTER_DOUBLE
);
6176 fprintf_unfiltered (file
,
6177 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
6178 MIPS_DEFAULT_STACK_ARGSIZE
);
6179 fprintf_unfiltered (file
,
6180 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
6181 MIPS_STACK_ARGSIZE
);
6182 fprintf_unfiltered (file
,
6183 "mips_dump_tdep: A0_REGNUM = %d\n",
6185 fprintf_unfiltered (file
,
6186 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6187 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
6188 fprintf_unfiltered (file
,
6189 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6190 XSTRING (ATTACH_DETACH
));
6191 fprintf_unfiltered (file
,
6192 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6193 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6194 fprintf_unfiltered (file
,
6195 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6196 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6197 fprintf_unfiltered (file
,
6198 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6199 FIRST_EMBED_REGNUM
);
6200 fprintf_unfiltered (file
,
6201 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6202 XSTRING (IGNORE_HELPER_CALL (PC
)));
6203 fprintf_unfiltered (file
,
6204 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6205 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6206 fprintf_unfiltered (file
,
6207 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6208 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6209 fprintf_unfiltered (file
,
6210 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6212 #ifdef MACHINE_CPROC_FP_OFFSET
6213 fprintf_unfiltered (file
,
6214 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6215 MACHINE_CPROC_FP_OFFSET
);
6217 #ifdef MACHINE_CPROC_PC_OFFSET
6218 fprintf_unfiltered (file
,
6219 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6220 MACHINE_CPROC_PC_OFFSET
);
6222 #ifdef MACHINE_CPROC_SP_OFFSET
6223 fprintf_unfiltered (file
,
6224 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6225 MACHINE_CPROC_SP_OFFSET
);
6227 fprintf_unfiltered (file
,
6228 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6230 fprintf_unfiltered (file
,
6231 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6232 fprintf_unfiltered (file
,
6233 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6234 fprintf_unfiltered (file
,
6235 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6237 fprintf_unfiltered (file
,
6238 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6239 MIPS_LAST_ARG_REGNUM
,
6240 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6241 fprintf_unfiltered (file
,
6242 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6244 fprintf_unfiltered (file
,
6245 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
6246 MIPS_SAVED_REGSIZE
);
6247 fprintf_unfiltered (file
,
6248 "mips_dump_tdep: PRID_REGNUM = %d\n",
6250 fprintf_unfiltered (file
,
6251 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6252 fprintf_unfiltered (file
,
6253 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6254 fprintf_unfiltered (file
,
6255 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6256 fprintf_unfiltered (file
,
6257 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6258 fprintf_unfiltered (file
,
6259 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6260 fprintf_unfiltered (file
,
6261 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6262 fprintf_unfiltered (file
,
6263 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6264 fprintf_unfiltered (file
,
6265 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6266 fprintf_unfiltered (file
,
6267 "mips_dump_tdep: PROC_PC_REG = function?\n");
6268 fprintf_unfiltered (file
,
6269 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6270 fprintf_unfiltered (file
,
6271 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6272 fprintf_unfiltered (file
,
6273 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6274 fprintf_unfiltered (file
,
6275 "mips_dump_tdep: PS_REGNUM = %d\n",
6277 fprintf_unfiltered (file
,
6278 "mips_dump_tdep: RA_REGNUM = %d\n",
6281 fprintf_unfiltered (file
,
6282 "mips_dump_tdep: SAVED_BYTES = %d\n",
6286 fprintf_unfiltered (file
,
6287 "mips_dump_tdep: SAVED_FP = %d\n",
6291 fprintf_unfiltered (file
,
6292 "mips_dump_tdep: SAVED_PC = %d\n",
6295 fprintf_unfiltered (file
,
6296 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6297 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6298 fprintf_unfiltered (file
,
6299 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6300 fprintf_unfiltered (file
,
6301 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6303 fprintf_unfiltered (file
,
6304 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6305 SIGFRAME_FPREGSAVE_OFF
);
6306 fprintf_unfiltered (file
,
6307 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6309 fprintf_unfiltered (file
,
6310 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6311 SIGFRAME_REGSAVE_OFF
);
6312 fprintf_unfiltered (file
,
6313 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6314 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6315 fprintf_unfiltered (file
,
6316 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6317 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6318 fprintf_unfiltered (file
,
6319 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6320 SOFTWARE_SINGLE_STEP_P ());
6321 fprintf_unfiltered (file
,
6322 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6323 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6324 #ifdef STACK_END_ADDR
6325 fprintf_unfiltered (file
,
6326 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6329 fprintf_unfiltered (file
,
6330 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6331 XSTRING (STEP_SKIPS_DELAY (PC
)));
6332 fprintf_unfiltered (file
,
6333 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6334 STEP_SKIPS_DELAY_P
);
6335 fprintf_unfiltered (file
,
6336 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6337 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6338 fprintf_unfiltered (file
,
6339 "mips_dump_tdep: T9_REGNUM = %d\n",
6341 fprintf_unfiltered (file
,
6342 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6343 fprintf_unfiltered (file
,
6344 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6345 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
6346 fprintf_unfiltered (file
,
6347 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6348 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6350 fprintf_unfiltered (file
,
6351 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6352 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6355 fprintf_unfiltered (file
,
6356 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6359 #ifdef TRACE_FLAVOR_SIZE
6360 fprintf_unfiltered (file
,
6361 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6365 fprintf_unfiltered (file
,
6366 "mips_dump_tdep: TRACE_SET # %s\n",
6367 XSTRING (TRACE_SET (X
,STATE
)));
6369 #ifdef UNUSED_REGNUM
6370 fprintf_unfiltered (file
,
6371 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6374 fprintf_unfiltered (file
,
6375 "mips_dump_tdep: V0_REGNUM = %d\n",
6377 fprintf_unfiltered (file
,
6378 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6379 (long) VM_MIN_ADDRESS
);
6380 fprintf_unfiltered (file
,
6381 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6383 fprintf_unfiltered (file
,
6384 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6388 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6391 _initialize_mips_tdep (void)
6393 static struct cmd_list_element
*mipsfpulist
= NULL
;
6394 struct cmd_list_element
*c
;
6396 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6397 if (MIPS_ABI_LAST
+ 1
6398 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6399 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6401 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6403 /* Add root prefix command for all "set mips"/"show mips" commands */
6404 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6405 "Various MIPS specific commands.",
6406 &setmipscmdlist
, "set mips ", 0, &setlist
);
6408 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6409 "Various MIPS specific commands.",
6410 &showmipscmdlist
, "show mips ", 0, &showlist
);
6412 /* Allow the user to override the saved register size. */
6413 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6416 &mips_saved_regsize_string
, "\
6417 Set size of general purpose registers saved on the stack.\n\
6418 This option can be set to one of:\n\
6419 32 - Force GDB to treat saved GP registers as 32-bit\n\
6420 64 - Force GDB to treat saved GP registers as 64-bit\n\
6421 auto - Allow GDB to use the target's default setting or autodetect the\n\
6422 saved GP register size from information contained in the executable.\n\
6427 /* Allow the user to override the argument stack size. */
6428 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6431 &mips_stack_argsize_string
, "\
6432 Set the amount of stack space reserved for each argument.\n\
6433 This option can be set to one of:\n\
6434 32 - Force GDB to allocate 32-bit chunks per argument\n\
6435 64 - Force GDB to allocate 64-bit chunks per argument\n\
6436 auto - Allow GDB to determine the correct setting from the current\n\
6437 target and executable (default)",
6441 /* Allow the user to override the ABI. */
6442 c
= add_set_enum_cmd
6443 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6444 "Set the ABI used by this program.\n"
6445 "This option can be set to one of:\n"
6446 " auto - the default ABI associated with the current binary\n"
6454 set_cmd_sfunc (c
, mips_abi_update
);
6455 add_cmd ("abi", class_obscure
, show_mips_abi
,
6456 "Show ABI in use by MIPS target", &showmipscmdlist
);
6458 /* Let the user turn off floating point and set the fence post for
6459 heuristic_proc_start. */
6461 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6462 "Set use of MIPS floating-point coprocessor.",
6463 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6464 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6465 "Select single-precision MIPS floating-point coprocessor.",
6467 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6468 "Select double-precision MIPS floating-point coprocessor.",
6470 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6471 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6472 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6473 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6474 "Select no MIPS floating-point coprocessor.",
6476 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6477 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6478 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6479 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6480 "Select MIPS floating-point coprocessor automatically.",
6482 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6483 "Show current use of MIPS floating-point coprocessor target.",
6486 /* We really would like to have both "0" and "unlimited" work, but
6487 command.c doesn't deal with that. So make it a var_zinteger
6488 because the user can always use "999999" or some such for unlimited. */
6489 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6490 (char *) &heuristic_fence_post
,
6492 Set the distance searched for the start of a function.\n\
6493 If you are debugging a stripped executable, GDB needs to search through the\n\
6494 program for the start of a function. This command sets the distance of the\n\
6495 search. The only need to set it is when debugging a stripped executable.",
6497 /* We need to throw away the frame cache when we set this, since it
6498 might change our ability to get backtraces. */
6499 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6500 add_show_from_set (c
, &showlist
);
6502 /* Allow the user to control whether the upper bits of 64-bit
6503 addresses should be zeroed. */
6504 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6505 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6506 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6507 allow GDB to determine the correct value.\n", "\
6508 Show zeroing of upper 32 bits of 64-bit addresses.",
6509 NULL
, show_mask_address
,
6510 &setmipscmdlist
, &showmipscmdlist
);
6512 /* Allow the user to control the size of 32 bit registers within the
6513 raw remote packet. */
6514 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6515 var_boolean
, &mips64_transfers_32bit_regs_p
, "\
6516 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6517 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6518 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6519 64 bits for others. Use \"off\" to disable compatibility mode", "\
6520 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6521 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6522 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6523 64 bits for others. Use \"off\" to disable compatibility mode",
6524 set_mips64_transfers_32bit_regs
, NULL
,
6525 &setlist
, &showlist
);
6527 /* Debug this files internals. */
6528 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6529 &mips_debug
, "Set mips debugging.\n\
6530 When non-zero, mips specific debugging is enabled.", &setdebuglist
),