1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
62 static const struct objfile_data
*mips_pdr_data
;
64 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
66 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
67 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
68 #define ST0_FR (1 << 26)
70 /* The sizes of floating point registers. */
74 MIPS_FPU_SINGLE_REGSIZE
= 4,
75 MIPS_FPU_DOUBLE_REGSIZE
= 8
84 static const char *mips_abi_string
;
86 static const char *mips_abi_strings
[] = {
97 /* The standard register names, and all the valid aliases for them. */
104 /* Aliases for o32 and most other ABIs. */
105 const struct register_alias mips_o32_aliases
[] = {
112 /* Aliases for n32 and n64. */
113 const struct register_alias mips_n32_n64_aliases
[] = {
120 /* Aliases for ABI-independent registers. */
121 const struct register_alias mips_register_aliases
[] = {
122 /* The architecture manuals specify these ABI-independent names for
124 #define R(n) { "r" #n, n }
125 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
126 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
127 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
128 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
131 /* k0 and k1 are sometimes called these instead (for "kernel
136 /* This is the traditional GDB name for the CP0 status register. */
137 { "sr", MIPS_PS_REGNUM
},
139 /* This is the traditional GDB name for the CP0 BadVAddr register. */
140 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
142 /* This is the traditional GDB name for the FCSR. */
143 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
146 const struct register_alias mips_numeric_register_aliases
[] = {
147 #define R(n) { #n, n }
148 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
149 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
150 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
151 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto
= 1;
159 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
161 static int mips_debug
= 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc
*mips_tdesc_gp32
;
169 struct target_desc
*mips_tdesc_gp64
;
171 const struct mips_regnum
*
172 mips_regnum (struct gdbarch
*gdbarch
)
174 return gdbarch_tdep (gdbarch
)->regnum
;
178 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
180 return mips_regnum (gdbarch
)->fp0
+ 12;
183 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
185 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
187 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
189 #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
191 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
193 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
194 functions to test, set, or clear bit 0 of addresses. */
197 is_mips16_addr (CORE_ADDR addr
)
203 unmake_mips16_addr (CORE_ADDR addr
)
205 return ((addr
) & ~(CORE_ADDR
) 1);
209 make_mips16_addr (CORE_ADDR addr
)
211 return ((addr
) | (CORE_ADDR
) 1);
214 /* Return the MIPS ABI associated with GDBARCH. */
216 mips_abi (struct gdbarch
*gdbarch
)
218 return gdbarch_tdep (gdbarch
)->mips_abi
;
222 mips_isa_regsize (struct gdbarch
*gdbarch
)
224 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
226 /* If we know how big the registers are, use that size. */
227 if (tdep
->register_size_valid_p
)
228 return tdep
->register_size
;
230 /* Fall back to the previous behavior. */
231 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
232 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
235 /* Return the currently configured (or set) saved register size. */
238 mips_abi_regsize (struct gdbarch
*gdbarch
)
240 switch (mips_abi (gdbarch
))
242 case MIPS_ABI_EABI32
:
248 case MIPS_ABI_EABI64
:
250 case MIPS_ABI_UNKNOWN
:
253 internal_error (__FILE__
, __LINE__
, _("bad switch"));
257 /* Functions for setting and testing a bit in a minimal symbol that
258 marks it as 16-bit function. The MSB of the minimal symbol's
259 "info" field is used for this purpose.
261 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
262 i.e. refers to a 16-bit function, and sets a "special" bit in a
263 minimal symbol to mark it as a 16-bit function
265 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
268 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
270 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
272 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
277 msymbol_is_special (struct minimal_symbol
*msym
)
279 return MSYMBOL_TARGET_FLAG_1 (msym
);
282 /* XFER a value from the big/little/left end of the register.
283 Depending on the size of the value it might occupy the entire
284 register or just part of it. Make an allowance for this, aligning
285 things accordingly. */
288 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
289 int reg_num
, int length
,
290 enum bfd_endian endian
, gdb_byte
*in
,
291 const gdb_byte
*out
, int buf_offset
)
295 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
296 /* Need to transfer the left or right part of the register, based on
297 the targets byte order. */
301 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
303 case BFD_ENDIAN_LITTLE
:
306 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
310 internal_error (__FILE__
, __LINE__
, _("bad switch"));
313 fprintf_unfiltered (gdb_stderr
,
314 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
315 reg_num
, reg_offset
, buf_offset
, length
);
316 if (mips_debug
&& out
!= NULL
)
319 fprintf_unfiltered (gdb_stdlog
, "out ");
320 for (i
= 0; i
< length
; i
++)
321 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
324 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
327 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
329 if (mips_debug
&& in
!= NULL
)
332 fprintf_unfiltered (gdb_stdlog
, "in ");
333 for (i
= 0; i
< length
; i
++)
334 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
337 fprintf_unfiltered (gdb_stdlog
, "\n");
340 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
341 compatiblity mode. A return value of 1 means that we have
342 physical 64-bit registers, but should treat them as 32-bit registers. */
345 mips2_fp_compat (struct frame_info
*frame
)
347 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
348 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
350 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
354 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
355 in all the places we deal with FP registers. PR gdb/413. */
356 /* Otherwise check the FR bit in the status register - it controls
357 the FP compatiblity mode. If it is clear we are in compatibility
359 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
366 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
368 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
370 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
372 /* The list of available "set mips " and "show mips " commands */
374 static struct cmd_list_element
*setmipscmdlist
= NULL
;
375 static struct cmd_list_element
*showmipscmdlist
= NULL
;
377 /* Integer registers 0 thru 31 are handled explicitly by
378 mips_register_name(). Processor specific registers 32 and above
379 are listed in the following tables. */
382 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
386 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
387 "sr", "lo", "hi", "bad", "cause", "pc",
388 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
389 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
390 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
391 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
392 "fsr", "fir", "" /*"fp" */ , "",
393 "", "", "", "", "", "", "", "",
394 "", "", "", "", "", "", "", "",
397 /* Names of IDT R3041 registers. */
399 static const char *mips_r3041_reg_names
[] = {
400 "sr", "lo", "hi", "bad", "cause", "pc",
401 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
402 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
403 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
404 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
405 "fsr", "fir", "", /*"fp" */ "",
406 "", "", "bus", "ccfg", "", "", "", "",
407 "", "", "port", "cmp", "", "", "epc", "prid",
410 /* Names of tx39 registers. */
412 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
413 "sr", "lo", "hi", "bad", "cause", "pc",
414 "", "", "", "", "", "", "", "",
415 "", "", "", "", "", "", "", "",
416 "", "", "", "", "", "", "", "",
417 "", "", "", "", "", "", "", "",
419 "", "", "", "", "", "", "", "",
420 "", "", "config", "cache", "debug", "depc", "epc", ""
423 /* Names of IRIX registers. */
424 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
425 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
426 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
427 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
428 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
429 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
433 /* Return the name of the register corresponding to REGNO. */
435 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
437 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
438 /* GPR names for all ABIs other than n32/n64. */
439 static char *mips_gpr_names
[] = {
440 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
441 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
442 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
443 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
446 /* GPR names for n32 and n64 ABIs. */
447 static char *mips_n32_n64_gpr_names
[] = {
448 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
449 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
450 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
451 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
454 enum mips_abi abi
= mips_abi (gdbarch
);
456 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
457 but then don't make the raw register names visible. */
458 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
459 if (regno
< gdbarch_num_regs (gdbarch
))
462 /* The MIPS integer registers are always mapped from 0 to 31. The
463 names of the registers (which reflects the conventions regarding
464 register use) vary depending on the ABI. */
465 if (0 <= rawnum
&& rawnum
< 32)
467 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
468 return mips_n32_n64_gpr_names
[rawnum
];
470 return mips_gpr_names
[rawnum
];
472 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
473 return tdesc_register_name (gdbarch
, rawnum
);
474 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
476 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
477 return tdep
->mips_processor_reg_names
[rawnum
- 32];
480 internal_error (__FILE__
, __LINE__
,
481 _("mips_register_name: bad register number %d"), rawnum
);
484 /* Return the groups that a MIPS register can be categorised into. */
487 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
488 struct reggroup
*reggroup
)
493 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
494 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
495 if (reggroup
== all_reggroup
)
497 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
498 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
499 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
500 (gdbarch), as not all architectures are multi-arch. */
501 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
502 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
503 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
505 if (reggroup
== float_reggroup
)
506 return float_p
&& pseudo
;
507 if (reggroup
== vector_reggroup
)
508 return vector_p
&& pseudo
;
509 if (reggroup
== general_reggroup
)
510 return (!vector_p
&& !float_p
) && pseudo
;
511 /* Save the pseudo registers. Need to make certain that any code
512 extracting register values from a saved register cache also uses
514 if (reggroup
== save_reggroup
)
515 return raw_p
&& pseudo
;
516 /* Restore the same pseudo register. */
517 if (reggroup
== restore_reggroup
)
518 return raw_p
&& pseudo
;
522 /* Return the groups that a MIPS register can be categorised into.
523 This version is only used if we have a target description which
524 describes real registers (and their groups). */
527 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
528 struct reggroup
*reggroup
)
530 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
531 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
534 /* Only save, restore, and display the pseudo registers. Need to
535 make certain that any code extracting register values from a
536 saved register cache also uses pseudo registers.
538 Note: saving and restoring the pseudo registers is slightly
539 strange; if we have 64 bits, we should save and restore all
540 64 bits. But this is hard and has little benefit. */
544 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
548 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
551 /* Map the symbol table registers which live in the range [1 *
552 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
553 registers. Take care of alignment and size problems. */
556 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
557 int cookednum
, gdb_byte
*buf
)
559 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
560 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
561 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
562 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
563 regcache_raw_read (regcache
, rawnum
, buf
);
564 else if (register_size (gdbarch
, rawnum
) >
565 register_size (gdbarch
, cookednum
))
567 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
568 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
571 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
573 regcache_raw_read_signed (regcache
, rawnum
, ®val
);
574 store_signed_integer (buf
, 4, byte_order
, regval
);
578 internal_error (__FILE__
, __LINE__
, _("bad register size"));
582 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
583 struct regcache
*regcache
, int cookednum
,
586 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
587 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
588 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
589 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
590 regcache_raw_write (regcache
, rawnum
, buf
);
591 else if (register_size (gdbarch
, rawnum
) >
592 register_size (gdbarch
, cookednum
))
594 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
595 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
598 /* Sign extend the shortened version of the register prior
599 to placing it in the raw register. This is required for
600 some mips64 parts in order to avoid unpredictable behavior. */
601 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
602 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
603 regcache_raw_write_signed (regcache
, rawnum
, regval
);
607 internal_error (__FILE__
, __LINE__
, _("bad register size"));
610 /* Table to translate MIPS16 register field to actual register number. */
611 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
613 /* Heuristic_proc_start may hunt through the text section for a long
614 time across a 2400 baud serial line. Allows the user to limit this
617 static unsigned int heuristic_fence_post
= 0;
619 /* Number of bytes of storage in the actual machine representation for
620 register N. NOTE: This defines the pseudo register type so need to
621 rebuild the architecture vector. */
623 static int mips64_transfers_32bit_regs_p
= 0;
626 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
627 struct cmd_list_element
*c
)
629 struct gdbarch_info info
;
630 gdbarch_info_init (&info
);
631 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
632 instead of relying on globals. Doing that would let generic code
633 handle the search for this specific architecture. */
634 if (!gdbarch_update_p (info
))
636 mips64_transfers_32bit_regs_p
= 0;
637 error (_("32-bit compatibility mode not supported"));
641 /* Convert to/from a register and the corresponding memory value. */
643 /* This predicate tests for the case of an 8 byte floating point
644 value that is being transferred to or from a pair of floating point
645 registers each of which are (or are considered to be) only 4 bytes
648 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
651 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
652 && register_size (gdbarch
, regnum
) == 4
653 && (regnum
% gdbarch_num_regs (gdbarch
))
654 >= mips_regnum (gdbarch
)->fp0
655 && (regnum
% gdbarch_num_regs (gdbarch
))
656 < mips_regnum (gdbarch
)->fp0
+ 32
657 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
660 /* This predicate tests for the case of a value of less than 8
661 bytes in width that is being transfered to or from an 8 byte
662 general purpose register. */
664 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
667 int num_regs
= gdbarch_num_regs (gdbarch
);
669 return (register_size (gdbarch
, regnum
) == 8
670 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
671 && TYPE_LENGTH (type
) < 8);
675 mips_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
677 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
678 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
682 mips_register_to_value (struct frame_info
*frame
, int regnum
,
683 struct type
*type
, gdb_byte
*to
)
685 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
687 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
689 get_frame_register (frame
, regnum
+ 0, to
+ 4);
690 get_frame_register (frame
, regnum
+ 1, to
+ 0);
692 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
694 int len
= TYPE_LENGTH (type
);
695 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
696 get_frame_register_bytes (frame
, regnum
, 8 - len
, len
, to
);
698 get_frame_register_bytes (frame
, regnum
, 0, len
, to
);
702 internal_error (__FILE__
, __LINE__
,
703 _("mips_register_to_value: unrecognized case"));
708 mips_value_to_register (struct frame_info
*frame
, int regnum
,
709 struct type
*type
, const gdb_byte
*from
)
711 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
713 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
715 put_frame_register (frame
, regnum
+ 0, from
+ 4);
716 put_frame_register (frame
, regnum
+ 1, from
+ 0);
718 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
721 int len
= TYPE_LENGTH (type
);
723 /* Sign extend values, irrespective of type, that are stored to
724 a 64-bit general purpose register. (32-bit unsigned values
725 are stored as signed quantities within a 64-bit register.
726 When performing an operation, in compiled code, that combines
727 a 32-bit unsigned value with a signed 64-bit value, a type
728 conversion is first performed that zeroes out the high 32 bits.) */
729 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
732 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
734 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
735 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
736 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
740 if (from
[len
-1] & 0x80)
741 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
743 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
744 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
745 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
750 internal_error (__FILE__
, __LINE__
,
751 _("mips_value_to_register: unrecognized case"));
755 /* Return the GDB type object for the "standard" data type of data in
759 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
761 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
762 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
763 && (regnum
% gdbarch_num_regs (gdbarch
))
764 < mips_regnum (gdbarch
)->fp0
+ 32)
766 /* The floating-point registers raw, or cooked, always match
767 mips_isa_regsize(), and also map 1:1, byte for byte. */
768 if (mips_isa_regsize (gdbarch
) == 4)
769 return builtin_type (gdbarch
)->builtin_float
;
771 return builtin_type (gdbarch
)->builtin_double
;
773 else if (regnum
< gdbarch_num_regs (gdbarch
))
775 /* The raw or ISA registers. These are all sized according to
777 if (mips_isa_regsize (gdbarch
) == 4)
778 return builtin_type (gdbarch
)->builtin_int32
;
780 return builtin_type (gdbarch
)->builtin_int64
;
784 /* The cooked or ABI registers. These are sized according to
785 the ABI (with a few complications). */
786 if (regnum
>= (gdbarch_num_regs (gdbarch
)
787 + mips_regnum (gdbarch
)->fp_control_status
)
788 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
789 /* The pseudo/cooked view of the embedded registers is always
790 32-bit. The raw view is handled below. */
791 return builtin_type (gdbarch
)->builtin_int32
;
792 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
793 /* The target, while possibly using a 64-bit register buffer,
794 is only transfering 32-bits of each integer register.
795 Reflect this in the cooked/pseudo (ABI) register value. */
796 return builtin_type (gdbarch
)->builtin_int32
;
797 else if (mips_abi_regsize (gdbarch
) == 4)
798 /* The ABI is restricted to 32-bit registers (the ISA could be
800 return builtin_type (gdbarch
)->builtin_int32
;
803 return builtin_type (gdbarch
)->builtin_int64
;
807 /* Return the GDB type for the pseudo register REGNUM, which is the
808 ABI-level view. This function is only called if there is a target
809 description which includes registers, so we know precisely the
810 types of hardware registers. */
813 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
815 const int num_regs
= gdbarch_num_regs (gdbarch
);
816 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
817 int rawnum
= regnum
% num_regs
;
818 struct type
*rawtype
;
820 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
822 /* Absent registers are still absent. */
823 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
824 if (TYPE_LENGTH (rawtype
) == 0)
827 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
828 /* Present the floating point registers however the hardware did;
829 do not try to convert between FPU layouts. */
832 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
834 /* The pseudo/cooked view of embedded registers is always
835 32-bit, even if the target transfers 64-bit values for them.
836 New targets relying on XML descriptions should only transfer
837 the necessary 32 bits, but older versions of GDB expected 64,
838 so allow the target to provide 64 bits without interfering
839 with the displayed type. */
840 return builtin_type (gdbarch
)->builtin_int32
;
843 /* Use pointer types for registers if we can. For n32 we can not,
844 since we do not have a 64-bit pointer type. */
845 if (mips_abi_regsize (gdbarch
)
846 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
848 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
849 return builtin_type (gdbarch
)->builtin_data_ptr
;
850 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
851 return builtin_type (gdbarch
)->builtin_func_ptr
;
854 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
855 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
856 return builtin_type (gdbarch
)->builtin_int32
;
858 /* For all other registers, pass through the hardware type. */
862 /* Should the upper word of 64-bit addresses be zeroed? */
863 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
866 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
868 switch (mask_address_var
)
870 case AUTO_BOOLEAN_TRUE
:
872 case AUTO_BOOLEAN_FALSE
:
875 case AUTO_BOOLEAN_AUTO
:
876 return tdep
->default_mask_address_p
;
878 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
884 show_mask_address (struct ui_file
*file
, int from_tty
,
885 struct cmd_list_element
*c
, const char *value
)
887 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
889 deprecated_show_value_hack (file
, from_tty
, c
, value
);
890 switch (mask_address_var
)
892 case AUTO_BOOLEAN_TRUE
:
893 printf_filtered ("The 32 bit mips address mask is enabled\n");
895 case AUTO_BOOLEAN_FALSE
:
896 printf_filtered ("The 32 bit mips address mask is disabled\n");
898 case AUTO_BOOLEAN_AUTO
:
900 ("The 32 bit address mask is set automatically. Currently %s\n",
901 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
904 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
909 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
912 mips_pc_is_mips16 (CORE_ADDR memaddr
)
914 struct minimal_symbol
*sym
;
916 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
917 if (is_mips16_addr (memaddr
))
920 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
921 the high bit of the info field. Use this to decide if the function is
922 MIPS16 or normal MIPS. */
923 sym
= lookup_minimal_symbol_by_pc (memaddr
);
925 return msymbol_is_special (sym
);
930 /* MIPS believes that the PC has a sign extended value. Perhaps the
931 all registers should be sign extended for simplicity? */
934 mips_read_pc (struct regcache
*regcache
)
937 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
938 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
939 if (is_mips16_addr (pc
))
940 pc
= unmake_mips16_addr (pc
);
945 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
949 pc
= frame_unwind_register_signed
950 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
951 if (is_mips16_addr (pc
))
952 pc
= unmake_mips16_addr (pc
);
957 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
959 return frame_unwind_register_signed
960 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
963 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
964 dummy frame. The frame ID's base needs to match the TOS value
965 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
968 static struct frame_id
969 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
971 return frame_id_build
972 (get_frame_register_signed (this_frame
,
973 gdbarch_num_regs (gdbarch
)
975 get_frame_pc (this_frame
));
979 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
981 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
982 if (mips_pc_is_mips16 (pc
))
983 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
985 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
988 /* Fetch and return instruction from the specified location. If the PC
989 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
992 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
994 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
995 gdb_byte buf
[MIPS_INSN32_SIZE
];
999 if (mips_pc_is_mips16 (addr
))
1001 instlen
= MIPS_INSN16_SIZE
;
1002 addr
= unmake_mips16_addr (addr
);
1005 instlen
= MIPS_INSN32_SIZE
;
1006 status
= target_read_memory (addr
, buf
, instlen
);
1008 memory_error (status
, addr
);
1009 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1012 /* These the fields of 32 bit mips instructions */
1013 #define mips32_op(x) (x >> 26)
1014 #define itype_op(x) (x >> 26)
1015 #define itype_rs(x) ((x >> 21) & 0x1f)
1016 #define itype_rt(x) ((x >> 16) & 0x1f)
1017 #define itype_immediate(x) (x & 0xffff)
1019 #define jtype_op(x) (x >> 26)
1020 #define jtype_target(x) (x & 0x03ffffff)
1022 #define rtype_op(x) (x >> 26)
1023 #define rtype_rs(x) ((x >> 21) & 0x1f)
1024 #define rtype_rt(x) ((x >> 16) & 0x1f)
1025 #define rtype_rd(x) ((x >> 11) & 0x1f)
1026 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1027 #define rtype_funct(x) (x & 0x3f)
1030 mips32_relative_offset (ULONGEST inst
)
1032 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1035 /* Determine where to set a single step breakpoint while considering
1036 branch prediction. */
1038 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1040 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1043 inst
= mips_fetch_instruction (gdbarch
, pc
);
1044 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1046 if (itype_op (inst
) >> 2 == 5)
1047 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1049 op
= (itype_op (inst
) & 0x03);
1059 goto greater_branch
;
1064 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1065 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1067 int tf
= itype_rt (inst
) & 0x01;
1068 int cnum
= itype_rt (inst
) >> 2;
1070 get_frame_register_signed (frame
,
1071 mips_regnum (get_frame_arch (frame
))->
1073 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1075 if (((cond
>> cnum
) & 0x01) == tf
)
1076 pc
+= mips32_relative_offset (inst
) + 4;
1081 pc
+= 4; /* Not a branch, next instruction is easy */
1084 { /* This gets way messy */
1086 /* Further subdivide into SPECIAL, REGIMM and other */
1087 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1089 case 0: /* SPECIAL */
1090 op
= rtype_funct (inst
);
1095 /* Set PC to that address */
1096 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1098 case 12: /* SYSCALL */
1100 struct gdbarch_tdep
*tdep
;
1102 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1103 if (tdep
->syscall_next_pc
!= NULL
)
1104 pc
= tdep
->syscall_next_pc (frame
);
1113 break; /* end SPECIAL */
1114 case 1: /* REGIMM */
1116 op
= itype_rt (inst
); /* branch condition */
1121 case 16: /* BLTZAL */
1122 case 18: /* BLTZALL */
1124 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1125 pc
+= mips32_relative_offset (inst
) + 4;
1127 pc
+= 8; /* after the delay slot */
1131 case 17: /* BGEZAL */
1132 case 19: /* BGEZALL */
1133 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1134 pc
+= mips32_relative_offset (inst
) + 4;
1136 pc
+= 8; /* after the delay slot */
1138 /* All of the other instructions in the REGIMM category */
1143 break; /* end REGIMM */
1148 reg
= jtype_target (inst
) << 2;
1149 /* Upper four bits get never changed... */
1150 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1153 /* FIXME case JALX : */
1156 reg
= jtype_target (inst
) << 2;
1157 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1158 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1160 break; /* The new PC will be alternate mode */
1161 case 4: /* BEQ, BEQL */
1163 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1164 get_frame_register_signed (frame
, itype_rt (inst
)))
1165 pc
+= mips32_relative_offset (inst
) + 4;
1169 case 5: /* BNE, BNEL */
1171 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1172 get_frame_register_signed (frame
, itype_rt (inst
)))
1173 pc
+= mips32_relative_offset (inst
) + 4;
1177 case 6: /* BLEZ, BLEZL */
1178 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1179 pc
+= mips32_relative_offset (inst
) + 4;
1185 greater_branch
: /* BGTZ, BGTZL */
1186 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1187 pc
+= mips32_relative_offset (inst
) + 4;
1194 } /* mips32_next_pc */
1196 /* Decoding the next place to set a breakpoint is irregular for the
1197 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1198 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1199 We dont want to set a single step instruction on the extend instruction
1203 /* Lots of mips16 instruction formats */
1204 /* Predicting jumps requires itype,ritype,i8type
1205 and their extensions extItype,extritype,extI8type
1207 enum mips16_inst_fmts
1209 itype
, /* 0 immediate 5,10 */
1210 ritype
, /* 1 5,3,8 */
1211 rrtype
, /* 2 5,3,3,5 */
1212 rritype
, /* 3 5,3,3,5 */
1213 rrrtype
, /* 4 5,3,3,3,2 */
1214 rriatype
, /* 5 5,3,3,1,4 */
1215 shifttype
, /* 6 5,3,3,3,2 */
1216 i8type
, /* 7 5,3,8 */
1217 i8movtype
, /* 8 5,3,3,5 */
1218 i8mov32rtype
, /* 9 5,3,5,3 */
1219 i64type
, /* 10 5,3,8 */
1220 ri64type
, /* 11 5,3,3,5 */
1221 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1222 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1223 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1224 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1225 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1226 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1227 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1228 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1229 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1230 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1232 /* I am heaping all the fields of the formats into one structure and
1233 then, only the fields which are involved in instruction extension */
1237 unsigned int regx
; /* Function in i8 type */
1242 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1243 for the bits which make up the immediate extension. */
1246 extended_offset (unsigned int extension
)
1249 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1251 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1253 value
|= extension
& 0x01f; /* extract 4:0 */
1257 /* Only call this function if you know that this is an extendable
1258 instruction. It won't malfunction, but why make excess remote memory
1259 references? If the immediate operands get sign extended or something,
1260 do it after the extension is performed. */
1261 /* FIXME: Every one of these cases needs to worry about sign extension
1262 when the offset is to be used in relative addressing. */
1265 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1267 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1269 pc
&= 0xfffffffe; /* clear the low order bit */
1270 target_read_memory (pc
, buf
, 2);
1271 return extract_unsigned_integer (buf
, 2, byte_order
);
1275 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1276 unsigned int extension
,
1278 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1283 switch (insn_format
)
1290 value
= extended_offset (extension
);
1291 value
= value
<< 11; /* rom for the original value */
1292 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1296 value
= inst
& 0x7ff;
1297 /* FIXME : Consider sign extension */
1306 { /* A register identifier and an offset */
1307 /* Most of the fields are the same as I type but the
1308 immediate value is of a different length */
1312 value
= extended_offset (extension
);
1313 value
= value
<< 8; /* from the original instruction */
1314 value
|= inst
& 0xff; /* eleven bits from instruction */
1315 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1316 if (value
& 0x4000) /* test the sign bit , bit 26 */
1318 value
&= ~0x3fff; /* remove the sign bit */
1324 value
= inst
& 0xff; /* 8 bits */
1325 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1326 /* FIXME: Do sign extension , this format needs it */
1327 if (value
& 0x80) /* THIS CONFUSES ME */
1329 value
&= 0xef; /* remove the sign bit */
1339 unsigned long value
;
1340 unsigned int nexthalf
;
1341 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1342 value
= value
<< 16;
1343 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit still set */
1351 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1353 upk
->offset
= offset
;
1360 add_offset_16 (CORE_ADDR pc
, int offset
)
1362 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1366 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1367 unsigned int extension
, unsigned int insn
)
1369 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1370 int op
= (insn
>> 11);
1373 case 2: /* Branch */
1376 struct upk_mips16 upk
;
1377 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1378 offset
= upk
.offset
;
1384 pc
+= (offset
<< 1) + 2;
1387 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1389 struct upk_mips16 upk
;
1390 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1391 pc
= add_offset_16 (pc
, upk
.offset
);
1392 if ((insn
>> 10) & 0x01) /* Exchange mode */
1393 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1400 struct upk_mips16 upk
;
1402 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1403 reg
= get_frame_register_signed (frame
, upk
.regx
);
1405 pc
+= (upk
.offset
<< 1) + 2;
1412 struct upk_mips16 upk
;
1414 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1415 reg
= get_frame_register_signed (frame
, upk
.regx
);
1417 pc
+= (upk
.offset
<< 1) + 2;
1422 case 12: /* I8 Formats btez btnez */
1424 struct upk_mips16 upk
;
1426 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1427 /* upk.regx contains the opcode */
1428 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1429 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1430 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1431 /* pc = add_offset_16(pc,upk.offset) ; */
1432 pc
+= (upk
.offset
<< 1) + 2;
1437 case 29: /* RR Formats JR, JALR, JALR-RA */
1439 struct upk_mips16 upk
;
1440 /* upk.fmt = rrtype; */
1445 upk
.regx
= (insn
>> 8) & 0x07;
1446 upk
.regy
= (insn
>> 5) & 0x07;
1454 break; /* Function return instruction */
1460 break; /* BOGUS Guess */
1462 pc
= get_frame_register_signed (frame
, reg
);
1469 /* This is an instruction extension. Fetch the real instruction
1470 (which follows the extension) and decode things based on
1474 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1475 fetch_mips_16 (gdbarch
, pc
));
1488 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1490 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1491 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1492 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1495 /* The mips_next_pc function supports single_step when the remote
1496 target monitor or stub is not developed enough to do a single_step.
1497 It works by decoding the current instruction and predicting where a
1498 branch will go. This isnt hard because all the data is available.
1499 The MIPS32 and MIPS16 variants are quite different. */
1501 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1503 if (is_mips16_addr (pc
))
1504 return mips16_next_pc (frame
, pc
);
1506 return mips32_next_pc (frame
, pc
);
1509 struct mips_frame_cache
1512 struct trad_frame_saved_reg
*saved_regs
;
1515 /* Set a register's saved stack address in temp_saved_regs. If an
1516 address has already been set for this register, do nothing; this
1517 way we will only recognize the first save of a given register in a
1520 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1521 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1522 Strictly speaking, only the second range is used as it is only second
1523 range (the ABI instead of ISA registers) that comes into play when finding
1524 saved registers in a frame. */
1527 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1528 int regnum
, CORE_ADDR offset
)
1530 if (this_cache
!= NULL
1531 && this_cache
->saved_regs
[regnum
].addr
== -1)
1533 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1535 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1541 /* Fetch the immediate value from a MIPS16 instruction.
1542 If the previous instruction was an EXTEND, use it to extend
1543 the upper bits of the immediate value. This is a helper function
1544 for mips16_scan_prologue. */
1547 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1548 unsigned short inst
, /* current instruction */
1549 int nbits
, /* number of bits in imm field */
1550 int scale
, /* scale factor to be applied to imm */
1551 int is_signed
) /* is the imm field signed? */
1555 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1557 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1558 if (offset
& 0x8000) /* check for negative extend */
1559 offset
= 0 - (0x10000 - (offset
& 0xffff));
1560 return offset
| (inst
& 0x1f);
1564 int max_imm
= 1 << nbits
;
1565 int mask
= max_imm
- 1;
1566 int sign_bit
= max_imm
>> 1;
1568 offset
= inst
& mask
;
1569 if (is_signed
&& (offset
& sign_bit
))
1570 offset
= 0 - (max_imm
- offset
);
1571 return offset
* scale
;
1576 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1577 the associated FRAME_CACHE if not null.
1578 Return the address of the first instruction past the prologue. */
1581 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1582 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1583 struct frame_info
*this_frame
,
1584 struct mips_frame_cache
*this_cache
)
1587 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1589 long frame_offset
= 0; /* Size of stack frame. */
1590 long frame_adjust
= 0; /* Offset of FP from SP. */
1591 int frame_reg
= MIPS_SP_REGNUM
;
1592 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1593 unsigned inst
= 0; /* current instruction */
1594 unsigned entry_inst
= 0; /* the entry instruction */
1595 unsigned save_inst
= 0; /* the save instruction */
1598 int extend_bytes
= 0;
1599 int prev_extend_bytes
;
1600 CORE_ADDR end_prologue_addr
= 0;
1602 /* Can be called when there's no process, and hence when there's no
1604 if (this_frame
!= NULL
)
1605 sp
= get_frame_register_signed (this_frame
,
1606 gdbarch_num_regs (gdbarch
)
1611 if (limit_pc
> start_pc
+ 200)
1612 limit_pc
= start_pc
+ 200;
1614 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1616 /* Save the previous instruction. If it's an EXTEND, we'll extract
1617 the immediate offset extension from it in mips16_get_imm. */
1620 /* Fetch and decode the instruction. */
1621 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1623 /* Normally we ignore extend instructions. However, if it is
1624 not followed by a valid prologue instruction, then this
1625 instruction is not part of the prologue either. We must
1626 remember in this case to adjust the end_prologue_addr back
1628 if ((inst
& 0xf800) == 0xf000) /* extend */
1630 extend_bytes
= MIPS_INSN16_SIZE
;
1634 prev_extend_bytes
= extend_bytes
;
1637 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1638 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1640 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1641 if (offset
< 0) /* negative stack adjustment? */
1642 frame_offset
-= offset
;
1644 /* Exit loop if a positive stack adjustment is found, which
1645 usually means that the stack cleanup code in the function
1646 epilogue is reached. */
1649 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1651 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1652 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1653 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1655 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1657 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1658 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1659 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1661 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1663 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1664 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1666 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1668 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1669 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1671 else if (inst
== 0x673d) /* move $s1, $sp */
1676 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1678 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1679 frame_addr
= sp
+ offset
;
1681 frame_adjust
= offset
;
1683 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1685 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1686 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1687 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1689 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1691 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1692 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1693 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1695 else if ((inst
& 0xf81f) == 0xe809
1696 && (inst
& 0x700) != 0x700) /* entry */
1697 entry_inst
= inst
; /* save for later processing */
1698 else if ((inst
& 0xff80) == 0x6480) /* save */
1700 save_inst
= inst
; /* save for later processing */
1701 if (prev_extend_bytes
) /* extend */
1702 save_inst
|= prev_inst
<< 16;
1704 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1705 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1706 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1708 /* This instruction is part of the prologue, but we don't
1709 need to do anything special to handle it. */
1713 /* This instruction is not an instruction typically found
1714 in a prologue, so we must have reached the end of the
1716 if (end_prologue_addr
== 0)
1717 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1721 /* The entry instruction is typically the first instruction in a function,
1722 and it stores registers at offsets relative to the value of the old SP
1723 (before the prologue). But the value of the sp parameter to this
1724 function is the new SP (after the prologue has been executed). So we
1725 can't calculate those offsets until we've seen the entire prologue,
1726 and can calculate what the old SP must have been. */
1727 if (entry_inst
!= 0)
1729 int areg_count
= (entry_inst
>> 8) & 7;
1730 int sreg_count
= (entry_inst
>> 6) & 3;
1732 /* The entry instruction always subtracts 32 from the SP. */
1735 /* Now we can calculate what the SP must have been at the
1736 start of the function prologue. */
1739 /* Check if a0-a3 were saved in the caller's argument save area. */
1740 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1742 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1743 offset
+= mips_abi_regsize (gdbarch
);
1746 /* Check if the ra register was pushed on the stack. */
1748 if (entry_inst
& 0x20)
1750 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1751 offset
-= mips_abi_regsize (gdbarch
);
1754 /* Check if the s0 and s1 registers were pushed on the stack. */
1755 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1757 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1758 offset
-= mips_abi_regsize (gdbarch
);
1762 /* The SAVE instruction is similar to ENTRY, except that defined by the
1763 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1764 size of the frame is specified as an immediate field of instruction
1765 and an extended variation exists which lets additional registers and
1766 frame space to be specified. The instruction always treats registers
1767 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1768 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1770 static int args_table
[16] = {
1771 0, 0, 0, 0, 1, 1, 1, 1,
1772 2, 2, 2, 0, 3, 3, 4, -1,
1774 static int astatic_table
[16] = {
1775 0, 1, 2, 3, 0, 1, 2, 3,
1776 0, 1, 2, 4, 0, 1, 0, -1,
1778 int aregs
= (save_inst
>> 16) & 0xf;
1779 int xsregs
= (save_inst
>> 24) & 0x7;
1780 int args
= args_table
[aregs
];
1781 int astatic
= astatic_table
[aregs
];
1786 warning (_("Invalid number of argument registers encoded in SAVE."));
1791 warning (_("Invalid number of static registers encoded in SAVE."));
1795 /* For standard SAVE the frame size of 0 means 128. */
1796 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1797 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1800 frame_offset
+= frame_size
;
1802 /* Now we can calculate what the SP must have been at the
1803 start of the function prologue. */
1806 /* Check if A0-A3 were saved in the caller's argument save area. */
1807 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1809 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1810 offset
+= mips_abi_regsize (gdbarch
);
1815 /* Check if the RA register was pushed on the stack. */
1816 if (save_inst
& 0x40)
1818 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1819 offset
-= mips_abi_regsize (gdbarch
);
1822 /* Check if the S8 register was pushed on the stack. */
1825 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1826 offset
-= mips_abi_regsize (gdbarch
);
1829 /* Check if S2-S7 were pushed on the stack. */
1830 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1832 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1833 offset
-= mips_abi_regsize (gdbarch
);
1836 /* Check if the S1 register was pushed on the stack. */
1837 if (save_inst
& 0x10)
1839 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1840 offset
-= mips_abi_regsize (gdbarch
);
1842 /* Check if the S0 register was pushed on the stack. */
1843 if (save_inst
& 0x20)
1845 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1846 offset
-= mips_abi_regsize (gdbarch
);
1849 /* Check if A0-A3 were pushed on the stack. */
1850 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1852 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1853 offset
-= mips_abi_regsize (gdbarch
);
1857 if (this_cache
!= NULL
)
1860 (get_frame_register_signed (this_frame
,
1861 gdbarch_num_regs (gdbarch
) + frame_reg
)
1862 + frame_offset
- frame_adjust
);
1863 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1864 be able to get rid of the assignment below, evetually. But it's
1865 still needed for now. */
1866 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1867 + mips_regnum (gdbarch
)->pc
]
1868 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1871 /* If we didn't reach the end of the prologue when scanning the function
1872 instructions, then set end_prologue_addr to the address of the
1873 instruction immediately after the last one we scanned. */
1874 if (end_prologue_addr
== 0)
1875 end_prologue_addr
= cur_pc
;
1877 return end_prologue_addr
;
1880 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1881 Procedures that use the 32-bit instruction set are handled by the
1882 mips_insn32 unwinder. */
1884 static struct mips_frame_cache
*
1885 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1887 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1888 struct mips_frame_cache
*cache
;
1890 if ((*this_cache
) != NULL
)
1891 return (*this_cache
);
1892 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1893 (*this_cache
) = cache
;
1894 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1896 /* Analyze the function prologue. */
1898 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1899 CORE_ADDR start_addr
;
1901 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1902 if (start_addr
== 0)
1903 start_addr
= heuristic_proc_start (gdbarch
, pc
);
1904 /* We can't analyze the prologue if we couldn't find the begining
1906 if (start_addr
== 0)
1909 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
1912 /* gdbarch_sp_regnum contains the value and not the address. */
1913 trad_frame_set_value (cache
->saved_regs
,
1914 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
1917 return (*this_cache
);
1921 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1922 struct frame_id
*this_id
)
1924 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1926 /* This marks the outermost frame. */
1927 if (info
->base
== 0)
1929 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
1932 static struct value
*
1933 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
1934 void **this_cache
, int regnum
)
1936 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1938 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1942 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
1943 struct frame_info
*this_frame
, void **this_cache
)
1945 CORE_ADDR pc
= get_frame_pc (this_frame
);
1946 if (mips_pc_is_mips16 (pc
))
1951 static const struct frame_unwind mips_insn16_frame_unwind
=
1954 mips_insn16_frame_this_id
,
1955 mips_insn16_frame_prev_register
,
1957 mips_insn16_frame_sniffer
1961 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
1964 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1969 static const struct frame_base mips_insn16_frame_base
=
1971 &mips_insn16_frame_unwind
,
1972 mips_insn16_frame_base_address
,
1973 mips_insn16_frame_base_address
,
1974 mips_insn16_frame_base_address
1977 static const struct frame_base
*
1978 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
1980 CORE_ADDR pc
= get_frame_pc (this_frame
);
1981 if (mips_pc_is_mips16 (pc
))
1982 return &mips_insn16_frame_base
;
1987 /* Mark all the registers as unset in the saved_regs array
1988 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1991 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
1993 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1997 const int num_regs
= gdbarch_num_regs (gdbarch
);
2000 for (i
= 0; i
< num_regs
; i
++)
2002 this_cache
->saved_regs
[i
].addr
= -1;
2007 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2008 the associated FRAME_CACHE if not null.
2009 Return the address of the first instruction past the prologue. */
2012 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2013 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2014 struct frame_info
*this_frame
,
2015 struct mips_frame_cache
*this_cache
)
2018 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2021 int frame_reg
= MIPS_SP_REGNUM
;
2023 CORE_ADDR end_prologue_addr
= 0;
2024 int seen_sp_adjust
= 0;
2025 int load_immediate_bytes
= 0;
2026 int in_delay_slot
= 0;
2027 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2029 /* Can be called when there's no process, and hence when there's no
2031 if (this_frame
!= NULL
)
2032 sp
= get_frame_register_signed (this_frame
,
2033 gdbarch_num_regs (gdbarch
)
2038 if (limit_pc
> start_pc
+ 200)
2039 limit_pc
= start_pc
+ 200;
2044 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2046 unsigned long inst
, high_word
, low_word
;
2049 /* Fetch the instruction. */
2050 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2052 /* Save some code by pre-extracting some useful fields. */
2053 high_word
= (inst
>> 16) & 0xffff;
2054 low_word
= inst
& 0xffff;
2055 reg
= high_word
& 0x1f;
2057 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2058 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2059 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2061 if (low_word
& 0x8000) /* negative stack adjustment? */
2062 frame_offset
+= 0x10000 - low_word
;
2064 /* Exit loop if a positive stack adjustment is found, which
2065 usually means that the stack cleanup code in the function
2066 epilogue is reached. */
2070 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2071 && !regsize_is_64_bits
)
2073 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2075 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2076 && regsize_is_64_bits
)
2078 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2079 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2081 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2083 /* Old gcc frame, r30 is virtual frame pointer. */
2084 if ((long) low_word
!= frame_offset
)
2085 frame_addr
= sp
+ low_word
;
2086 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2088 unsigned alloca_adjust
;
2091 frame_addr
= get_frame_register_signed
2092 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2094 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2095 if (alloca_adjust
> 0)
2097 /* FP > SP + frame_size. This may be because of
2098 an alloca or somethings similar. Fix sp to
2099 "pre-alloca" value, and try again. */
2100 sp
+= alloca_adjust
;
2101 /* Need to reset the status of all registers. Otherwise,
2102 we will hit a guard that prevents the new address
2103 for each register to be recomputed during the second
2105 reset_saved_regs (gdbarch
, this_cache
);
2110 /* move $30,$sp. With different versions of gas this will be either
2111 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2112 Accept any one of these. */
2113 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2115 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2116 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2118 unsigned alloca_adjust
;
2121 frame_addr
= get_frame_register_signed
2122 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2124 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2125 if (alloca_adjust
> 0)
2127 /* FP > SP + frame_size. This may be because of
2128 an alloca or somethings similar. Fix sp to
2129 "pre-alloca" value, and try again. */
2131 /* Need to reset the status of all registers. Otherwise,
2132 we will hit a guard that prevents the new address
2133 for each register to be recomputed during the second
2135 reset_saved_regs (gdbarch
, this_cache
);
2140 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2141 && !regsize_is_64_bits
)
2143 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2145 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2146 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2147 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2148 || high_word
== 0x3c1c /* lui $gp,n */
2149 || high_word
== 0x279c /* addiu $gp,$gp,n */
2150 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2151 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2154 /* These instructions are part of the prologue, but we don't
2155 need to do anything special to handle them. */
2157 /* The instructions below load $at or $t0 with an immediate
2158 value in preparation for a stack adjustment via
2159 subu $sp,$sp,[$at,$t0]. These instructions could also
2160 initialize a local variable, so we accept them only before
2161 a stack adjustment instruction was seen. */
2162 else if (!seen_sp_adjust
2163 && (high_word
== 0x3c01 /* lui $at,n */
2164 || high_word
== 0x3c08 /* lui $t0,n */
2165 || high_word
== 0x3421 /* ori $at,$at,n */
2166 || high_word
== 0x3508 /* ori $t0,$t0,n */
2167 || high_word
== 0x3401 /* ori $at,$zero,n */
2168 || high_word
== 0x3408 /* ori $t0,$zero,n */
2171 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2175 /* This instruction is not an instruction typically found
2176 in a prologue, so we must have reached the end of the
2178 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2179 loop now? Why would we need to continue scanning the function
2181 if (end_prologue_addr
== 0)
2182 end_prologue_addr
= cur_pc
;
2184 /* Check for branches and jumps. For now, only jump to
2185 register are caught (i.e. returns). */
2186 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2190 /* If the previous instruction was a jump, we must have reached
2191 the end of the prologue by now. Stop scanning so that we do
2192 not go past the function return. */
2197 if (this_cache
!= NULL
)
2200 (get_frame_register_signed (this_frame
,
2201 gdbarch_num_regs (gdbarch
) + frame_reg
)
2203 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2204 this assignment below, eventually. But it's still needed
2206 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2207 + mips_regnum (gdbarch
)->pc
]
2208 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2212 /* If we didn't reach the end of the prologue when scanning the function
2213 instructions, then set end_prologue_addr to the address of the
2214 instruction immediately after the last one we scanned. */
2215 /* brobecker/2004-10-10: I don't think this would ever happen, but
2216 we may as well be careful and do our best if we have a null
2217 end_prologue_addr. */
2218 if (end_prologue_addr
== 0)
2219 end_prologue_addr
= cur_pc
;
2221 /* In a frameless function, we might have incorrectly
2222 skipped some load immediate instructions. Undo the skipping
2223 if the load immediate was not followed by a stack adjustment. */
2224 if (load_immediate_bytes
&& !seen_sp_adjust
)
2225 end_prologue_addr
-= load_immediate_bytes
;
2227 return end_prologue_addr
;
2230 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2231 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2232 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2235 static struct mips_frame_cache
*
2236 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2238 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2239 struct mips_frame_cache
*cache
;
2241 if ((*this_cache
) != NULL
)
2242 return (*this_cache
);
2244 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2245 (*this_cache
) = cache
;
2246 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2248 /* Analyze the function prologue. */
2250 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2251 CORE_ADDR start_addr
;
2253 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2254 if (start_addr
== 0)
2255 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2256 /* We can't analyze the prologue if we couldn't find the begining
2258 if (start_addr
== 0)
2261 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2264 /* gdbarch_sp_regnum contains the value and not the address. */
2265 trad_frame_set_value (cache
->saved_regs
,
2266 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2269 return (*this_cache
);
2273 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2274 struct frame_id
*this_id
)
2276 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2278 /* This marks the outermost frame. */
2279 if (info
->base
== 0)
2281 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2284 static struct value
*
2285 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2286 void **this_cache
, int regnum
)
2288 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2290 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2294 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2295 struct frame_info
*this_frame
, void **this_cache
)
2297 CORE_ADDR pc
= get_frame_pc (this_frame
);
2298 if (! mips_pc_is_mips16 (pc
))
2303 static const struct frame_unwind mips_insn32_frame_unwind
=
2306 mips_insn32_frame_this_id
,
2307 mips_insn32_frame_prev_register
,
2309 mips_insn32_frame_sniffer
2313 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2316 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2321 static const struct frame_base mips_insn32_frame_base
=
2323 &mips_insn32_frame_unwind
,
2324 mips_insn32_frame_base_address
,
2325 mips_insn32_frame_base_address
,
2326 mips_insn32_frame_base_address
2329 static const struct frame_base
*
2330 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2332 CORE_ADDR pc
= get_frame_pc (this_frame
);
2333 if (! mips_pc_is_mips16 (pc
))
2334 return &mips_insn32_frame_base
;
2339 static struct trad_frame_cache
*
2340 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2343 CORE_ADDR start_addr
;
2344 CORE_ADDR stack_addr
;
2345 struct trad_frame_cache
*this_trad_cache
;
2346 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2347 int num_regs
= gdbarch_num_regs (gdbarch
);
2349 if ((*this_cache
) != NULL
)
2350 return (*this_cache
);
2351 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2352 (*this_cache
) = this_trad_cache
;
2354 /* The return address is in the link register. */
2355 trad_frame_set_reg_realreg (this_trad_cache
,
2356 gdbarch_pc_regnum (gdbarch
),
2357 num_regs
+ MIPS_RA_REGNUM
);
2359 /* Frame ID, since it's a frameless / stackless function, no stack
2360 space is allocated and SP on entry is the current SP. */
2361 pc
= get_frame_pc (this_frame
);
2362 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2363 stack_addr
= get_frame_register_signed (this_frame
,
2364 num_regs
+ MIPS_SP_REGNUM
);
2365 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2367 /* Assume that the frame's base is the same as the
2369 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2371 return this_trad_cache
;
2375 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2376 struct frame_id
*this_id
)
2378 struct trad_frame_cache
*this_trad_cache
2379 = mips_stub_frame_cache (this_frame
, this_cache
);
2380 trad_frame_get_id (this_trad_cache
, this_id
);
2383 static struct value
*
2384 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2385 void **this_cache
, int regnum
)
2387 struct trad_frame_cache
*this_trad_cache
2388 = mips_stub_frame_cache (this_frame
, this_cache
);
2389 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2393 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2394 struct frame_info
*this_frame
, void **this_cache
)
2397 struct obj_section
*s
;
2398 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2399 struct minimal_symbol
*msym
;
2401 /* Use the stub unwinder for unreadable code. */
2402 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2405 if (in_plt_section (pc
, NULL
))
2408 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2409 s
= find_pc_section (pc
);
2412 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2413 ".MIPS.stubs") == 0)
2416 /* Calling a PIC function from a non-PIC function passes through a
2417 stub. The stub for foo is named ".pic.foo". */
2418 msym
= lookup_minimal_symbol_by_pc (pc
);
2420 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2421 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2427 static const struct frame_unwind mips_stub_frame_unwind
=
2430 mips_stub_frame_this_id
,
2431 mips_stub_frame_prev_register
,
2433 mips_stub_frame_sniffer
2437 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2440 struct trad_frame_cache
*this_trad_cache
2441 = mips_stub_frame_cache (this_frame
, this_cache
);
2442 return trad_frame_get_this_base (this_trad_cache
);
2445 static const struct frame_base mips_stub_frame_base
=
2447 &mips_stub_frame_unwind
,
2448 mips_stub_frame_base_address
,
2449 mips_stub_frame_base_address
,
2450 mips_stub_frame_base_address
2453 static const struct frame_base
*
2454 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2456 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2457 return &mips_stub_frame_base
;
2462 /* mips_addr_bits_remove - remove useless address bits */
2465 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2467 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2469 if (is_mips16_addr (addr
))
2470 addr
= unmake_mips16_addr (addr
);
2472 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2473 /* This hack is a work-around for existing boards using PMON, the
2474 simulator, and any other 64-bit targets that doesn't have true
2475 64-bit addressing. On these targets, the upper 32 bits of
2476 addresses are ignored by the hardware. Thus, the PC or SP are
2477 likely to have been sign extended to all 1s by instruction
2478 sequences that load 32-bit addresses. For example, a typical
2479 piece of code that loads an address is this:
2481 lui $r2, <upper 16 bits>
2482 ori $r2, <lower 16 bits>
2484 But the lui sign-extends the value such that the upper 32 bits
2485 may be all 1s. The workaround is simply to mask off these
2486 bits. In the future, gcc may be changed to support true 64-bit
2487 addressing, and this masking will have to be disabled. */
2488 return addr
&= 0xffffffffUL
;
2493 /* Instructions used during single-stepping of atomic sequences. */
2494 #define LL_OPCODE 0x30
2495 #define LLD_OPCODE 0x34
2496 #define SC_OPCODE 0x38
2497 #define SCD_OPCODE 0x3c
2499 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2500 instruction and ending with a SC/SCD instruction. If such a sequence
2501 is found, attempt to step through it. A breakpoint is placed at the end of
2505 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2506 struct address_space
*aspace
, CORE_ADDR pc
)
2508 CORE_ADDR breaks
[2] = {-1, -1};
2510 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2514 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2515 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2520 insn
= mips_fetch_instruction (gdbarch
, loc
);
2521 /* Assume all atomic sequences start with a ll/lld instruction. */
2522 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2525 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2527 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2530 loc
+= MIPS_INSN32_SIZE
;
2531 insn
= mips_fetch_instruction (gdbarch
, loc
);
2533 /* Assume that there is at most one branch in the atomic
2534 sequence. If a branch is found, put a breakpoint in its
2535 destination address. */
2536 switch (itype_op (insn
))
2538 case 0: /* SPECIAL */
2539 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2540 return 0; /* fallback to the standard single-step code. */
2542 case 1: /* REGIMM */
2543 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2547 return 0; /* fallback to the standard single-step code. */
2554 case 22: /* BLEZL */
2555 case 23: /* BGTTL */
2561 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2566 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2567 if (last_breakpoint
>= 1)
2568 return 0; /* More than one branch found, fallback to the
2569 standard single-step code. */
2570 breaks
[1] = branch_bp
;
2574 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2578 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2579 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2582 loc
+= MIPS_INSN32_SIZE
;
2584 /* Insert a breakpoint right after the end of the atomic sequence. */
2587 /* Check for duplicated breakpoints. Check also for a breakpoint
2588 placed (branch instruction's destination) in the atomic sequence */
2589 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2590 last_breakpoint
= 0;
2592 /* Effectively inserts the breakpoints. */
2593 for (index
= 0; index
<= last_breakpoint
; index
++)
2594 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2599 /* mips_software_single_step() is called just before we want to resume
2600 the inferior, if we want to single-step it but there is no hardware
2601 or kernel single-step support (MIPS on GNU/Linux for example). We find
2602 the target of the coming instruction and breakpoint it. */
2605 mips_software_single_step (struct frame_info
*frame
)
2607 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2608 struct address_space
*aspace
= get_frame_address_space (frame
);
2609 CORE_ADDR pc
, next_pc
;
2611 pc
= get_frame_pc (frame
);
2612 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2615 next_pc
= mips_next_pc (frame
, pc
);
2617 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2621 /* Test whether the PC points to the return instruction at the
2622 end of a function. */
2625 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2627 if (mips_pc_is_mips16 (pc
))
2628 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2629 generates a "jr $ra"; other times it generates code to load
2630 the return address from the stack to an accessible register (such
2631 as $a3), then a "jr" using that register. This second case
2632 is almost impossible to distinguish from an indirect jump
2633 used for switch statements, so we don't even try. */
2634 return mips_fetch_instruction (gdbarch
, pc
) == 0xe820; /* jr $ra */
2636 return mips_fetch_instruction (gdbarch
, pc
) == 0x3e00008; /* jr $ra */
2640 /* This fencepost looks highly suspicious to me. Removing it also
2641 seems suspicious as it could affect remote debugging across serial
2645 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2651 struct inferior
*inf
;
2653 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2655 fence
= start_pc
- heuristic_fence_post
;
2659 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2660 fence
= VM_MIN_ADDRESS
;
2662 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2664 inf
= current_inferior ();
2666 /* search back for previous return */
2667 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2668 if (start_pc
< fence
)
2670 /* It's not clear to me why we reach this point when
2671 stop_soon, but with this test, at least we
2672 don't print out warnings for every child forked (eg, on
2673 decstation). 22apr93 rich@cygnus.com. */
2674 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2676 static int blurb_printed
= 0;
2678 warning (_("GDB can't find the start of the function at %s."),
2679 paddress (gdbarch
, pc
));
2683 /* This actually happens frequently in embedded
2684 development, when you first connect to a board
2685 and your stack pointer and pc are nowhere in
2686 particular. This message needs to give people
2687 in that situation enough information to
2688 determine that it's no big deal. */
2689 printf_filtered ("\n\
2690 GDB is unable to find the start of the function at %s\n\
2691 and thus can't determine the size of that function's stack frame.\n\
2692 This means that GDB may be unable to access that stack frame, or\n\
2693 the frames below it.\n\
2694 This problem is most likely caused by an invalid program counter or\n\
2696 However, if you think GDB should simply search farther back\n\
2697 from %s for code which looks like the beginning of a\n\
2698 function, you can increase the range of the search using the `set\n\
2699 heuristic-fence-post' command.\n",
2700 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2707 else if (mips_pc_is_mips16 (start_pc
))
2709 unsigned short inst
;
2711 /* On MIPS16, any one of the following is likely to be the
2712 start of a function:
2718 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2719 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2720 if ((inst
& 0xff80) == 0x6480) /* save */
2722 if (start_pc
- instlen
>= fence
)
2724 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2725 if ((inst
& 0xf800) == 0xf000) /* extend */
2726 start_pc
-= instlen
;
2730 else if (((inst
& 0xf81f) == 0xe809
2731 && (inst
& 0x700) != 0x700) /* entry */
2732 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2733 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2734 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2736 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2737 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2742 else if (mips_about_to_return (gdbarch
, start_pc
))
2744 /* Skip return and its delay slot. */
2745 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2752 struct mips_objfile_private
2758 /* According to the current ABI, should the type be passed in a
2759 floating-point register (assuming that there is space)? When there
2760 is no FPU, FP are not even considered as possible candidates for
2761 FP registers and, consequently this returns false - forces FP
2762 arguments into integer registers. */
2765 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2766 struct type
*arg_type
)
2768 return ((typecode
== TYPE_CODE_FLT
2769 || (MIPS_EABI (gdbarch
)
2770 && (typecode
== TYPE_CODE_STRUCT
2771 || typecode
== TYPE_CODE_UNION
)
2772 && TYPE_NFIELDS (arg_type
) == 1
2773 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2775 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2778 /* On o32, argument passing in GPRs depends on the alignment of the type being
2779 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2782 mips_type_needs_double_align (struct type
*type
)
2784 enum type_code typecode
= TYPE_CODE (type
);
2786 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2788 else if (typecode
== TYPE_CODE_STRUCT
)
2790 if (TYPE_NFIELDS (type
) < 1)
2792 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2794 else if (typecode
== TYPE_CODE_UNION
)
2798 n
= TYPE_NFIELDS (type
);
2799 for (i
= 0; i
< n
; i
++)
2800 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2807 /* Adjust the address downward (direction of stack growth) so that it
2808 is correctly aligned for a new stack frame. */
2810 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2812 return align_down (addr
, 16);
2816 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2817 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2818 int nargs
, struct value
**args
, CORE_ADDR sp
,
2819 int struct_return
, CORE_ADDR struct_addr
)
2825 int stack_offset
= 0;
2826 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2827 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2828 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2829 int regsize
= mips_abi_regsize (gdbarch
);
2831 /* For shared libraries, "t9" needs to point at the function
2833 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2835 /* Set the return address register to point to the entry point of
2836 the program, where a breakpoint lies in wait. */
2837 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2839 /* First ensure that the stack and structure return address (if any)
2840 are properly aligned. The stack has to be at least 64-bit
2841 aligned even on 32-bit machines, because doubles must be 64-bit
2842 aligned. For n32 and n64, stack frames need to be 128-bit
2843 aligned, so we round to this widest known alignment. */
2845 sp
= align_down (sp
, 16);
2846 struct_addr
= align_down (struct_addr
, 16);
2848 /* Now make space on the stack for the args. We allocate more
2849 than necessary for EABI, because the first few arguments are
2850 passed in registers, but that's OK. */
2851 for (argnum
= 0; argnum
< nargs
; argnum
++)
2852 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2853 sp
-= align_up (len
, 16);
2856 fprintf_unfiltered (gdb_stdlog
,
2857 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2858 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2860 /* Initialize the integer and float register pointers. */
2861 argreg
= MIPS_A0_REGNUM
;
2862 float_argreg
= mips_fpa0_regnum (gdbarch
);
2864 /* The struct_return pointer occupies the first parameter-passing reg. */
2868 fprintf_unfiltered (gdb_stdlog
,
2869 "mips_eabi_push_dummy_call: struct_return reg=%d %s\n",
2870 argreg
, paddress (gdbarch
, struct_addr
));
2871 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2874 /* Now load as many as possible of the first arguments into
2875 registers, and push the rest onto the stack. Loop thru args
2876 from first to last. */
2877 for (argnum
= 0; argnum
< nargs
; argnum
++)
2879 const gdb_byte
*val
;
2880 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2881 struct value
*arg
= args
[argnum
];
2882 struct type
*arg_type
= check_typedef (value_type (arg
));
2883 int len
= TYPE_LENGTH (arg_type
);
2884 enum type_code typecode
= TYPE_CODE (arg_type
);
2887 fprintf_unfiltered (gdb_stdlog
,
2888 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2889 argnum
+ 1, len
, (int) typecode
);
2891 /* Function pointer arguments to mips16 code need to be made into
2893 if (typecode
== TYPE_CODE_PTR
2894 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
2896 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
2898 if (mips_pc_is_mips16 (addr
))
2900 store_signed_integer (valbuf
, len
, byte_order
,
2901 make_mips16_addr (addr
));
2905 val
= value_contents (arg
);
2907 /* The EABI passes structures that do not fit in a register by
2909 else if (len
> regsize
2910 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2912 store_unsigned_integer (valbuf
, regsize
, byte_order
,
2913 value_address (arg
));
2914 typecode
= TYPE_CODE_PTR
;
2918 fprintf_unfiltered (gdb_stdlog
, " push");
2921 val
= value_contents (arg
);
2923 /* 32-bit ABIs always start floating point arguments in an
2924 even-numbered floating point register. Round the FP register
2925 up before the check to see if there are any FP registers
2926 left. Non MIPS_EABI targets also pass the FP in the integer
2927 registers so also round up normal registers. */
2928 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2930 if ((float_argreg
& 1))
2934 /* Floating point arguments passed in registers have to be
2935 treated specially. On 32-bit architectures, doubles
2936 are passed in register pairs; the even register gets
2937 the low word, and the odd register gets the high word.
2938 On non-EABI processors, the first two floating point arguments are
2939 also copied to general registers, because MIPS16 functions
2940 don't use float registers for arguments. This duplication of
2941 arguments in general registers can't hurt non-MIPS16 functions
2942 because those registers are normally skipped. */
2943 /* MIPS_EABI squeezes a struct that contains a single floating
2944 point value into an FP register instead of pushing it onto the
2946 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
2947 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
2949 /* EABI32 will pass doubles in consecutive registers, even on
2950 64-bit cores. At one time, we used to check the size of
2951 `float_argreg' to determine whether or not to pass doubles
2952 in consecutive registers, but this is not sufficient for
2953 making the ABI determination. */
2954 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2956 int low_offset
= gdbarch_byte_order (gdbarch
)
2957 == BFD_ENDIAN_BIG
? 4 : 0;
2960 /* Write the low word of the double to the even register(s). */
2961 regval
= extract_signed_integer (val
+ low_offset
,
2964 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2965 float_argreg
, phex (regval
, 4));
2966 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
2968 /* Write the high word of the double to the odd register(s). */
2969 regval
= extract_signed_integer (val
+ 4 - low_offset
,
2972 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2973 float_argreg
, phex (regval
, 4));
2974 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
2978 /* This is a floating point value that fits entirely
2979 in a single register. */
2980 /* On 32 bit ABI's the float_argreg is further adjusted
2981 above to ensure that it is even register aligned. */
2982 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
2984 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2985 float_argreg
, phex (regval
, len
));
2986 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
2991 /* Copy the argument to general registers or the stack in
2992 register-sized pieces. Large arguments are split between
2993 registers and stack. */
2994 /* Note: structs whose size is not a multiple of regsize
2995 are treated specially: Irix cc passes
2996 them in registers where gcc sometimes puts them on the
2997 stack. For maximum compatibility, we will put them in
2999 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3001 /* Note: Floating-point values that didn't fit into an FP
3002 register are only written to memory. */
3005 /* Remember if the argument was written to the stack. */
3006 int stack_used_p
= 0;
3007 int partial_len
= (len
< regsize
? len
: regsize
);
3010 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3013 /* Write this portion of the argument to the stack. */
3014 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3016 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3018 /* Should shorter than int integer values be
3019 promoted to int before being stored? */
3020 int longword_offset
= 0;
3023 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3026 && (typecode
== TYPE_CODE_INT
3027 || typecode
== TYPE_CODE_PTR
3028 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3029 longword_offset
= regsize
- len
;
3030 else if ((typecode
== TYPE_CODE_STRUCT
3031 || typecode
== TYPE_CODE_UNION
)
3032 && TYPE_LENGTH (arg_type
) < regsize
)
3033 longword_offset
= regsize
- len
;
3038 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3039 paddress (gdbarch
, stack_offset
));
3040 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3041 paddress (gdbarch
, longword_offset
));
3044 addr
= sp
+ stack_offset
+ longword_offset
;
3049 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3050 paddress (gdbarch
, addr
));
3051 for (i
= 0; i
< partial_len
; i
++)
3053 fprintf_unfiltered (gdb_stdlog
, "%02x",
3057 write_memory (addr
, val
, partial_len
);
3060 /* Note!!! This is NOT an else clause. Odd sized
3061 structs may go thru BOTH paths. Floating point
3062 arguments will not. */
3063 /* Write this portion of the argument to a general
3064 purpose register. */
3065 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3066 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3069 extract_signed_integer (val
, partial_len
, byte_order
);
3072 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3074 phex (regval
, regsize
));
3075 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3082 /* Compute the the offset into the stack at which we
3083 will copy the next parameter.
3085 In the new EABI (and the NABI32), the stack_offset
3086 only needs to be adjusted when it has been used. */
3089 stack_offset
+= align_up (partial_len
, regsize
);
3093 fprintf_unfiltered (gdb_stdlog
, "\n");
3096 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3098 /* Return adjusted stack pointer. */
3102 /* Determine the return value convention being used. */
3104 static enum return_value_convention
3105 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3106 struct type
*type
, struct regcache
*regcache
,
3107 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3109 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3110 int fp_return_type
= 0;
3111 int offset
, regnum
, xfer
;
3113 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3114 return RETURN_VALUE_STRUCT_CONVENTION
;
3116 /* Floating point type? */
3117 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3119 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3121 /* Structs with a single field of float type
3122 are returned in a floating point register. */
3123 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3124 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3125 && TYPE_NFIELDS (type
) == 1)
3127 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3129 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3136 /* A floating-point value belongs in the least significant part
3139 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3140 regnum
= mips_regnum (gdbarch
)->fp0
;
3144 /* An integer value goes in V0/V1. */
3146 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3147 regnum
= MIPS_V0_REGNUM
;
3150 offset
< TYPE_LENGTH (type
);
3151 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3153 xfer
= mips_abi_regsize (gdbarch
);
3154 if (offset
+ xfer
> TYPE_LENGTH (type
))
3155 xfer
= TYPE_LENGTH (type
) - offset
;
3156 mips_xfer_register (gdbarch
, regcache
,
3157 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3158 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3162 return RETURN_VALUE_REGISTER_CONVENTION
;
3166 /* N32/N64 ABI stuff. */
3168 /* Search for a naturally aligned double at OFFSET inside a struct
3169 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3173 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3178 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3181 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3184 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3187 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3190 struct type
*field_type
;
3192 /* We're only looking at normal fields. */
3193 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3194 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3197 /* If we have gone past the offset, there is no double to pass. */
3198 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3202 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3204 /* If this field is entirely before the requested offset, go
3205 on to the next one. */
3206 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3209 /* If this is our special aligned double, we can stop. */
3210 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3211 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3214 /* This field starts at or before the requested offset, and
3215 overlaps it. If it is a structure, recurse inwards. */
3216 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3223 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3224 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3225 int nargs
, struct value
**args
, CORE_ADDR sp
,
3226 int struct_return
, CORE_ADDR struct_addr
)
3232 int stack_offset
= 0;
3233 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3234 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3235 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3237 /* For shared libraries, "t9" needs to point at the function
3239 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3241 /* Set the return address register to point to the entry point of
3242 the program, where a breakpoint lies in wait. */
3243 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3245 /* First ensure that the stack and structure return address (if any)
3246 are properly aligned. The stack has to be at least 64-bit
3247 aligned even on 32-bit machines, because doubles must be 64-bit
3248 aligned. For n32 and n64, stack frames need to be 128-bit
3249 aligned, so we round to this widest known alignment. */
3251 sp
= align_down (sp
, 16);
3252 struct_addr
= align_down (struct_addr
, 16);
3254 /* Now make space on the stack for the args. */
3255 for (argnum
= 0; argnum
< nargs
; argnum
++)
3256 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3257 sp
-= align_up (len
, 16);
3260 fprintf_unfiltered (gdb_stdlog
,
3261 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3262 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3264 /* Initialize the integer and float register pointers. */
3265 argreg
= MIPS_A0_REGNUM
;
3266 float_argreg
= mips_fpa0_regnum (gdbarch
);
3268 /* The struct_return pointer occupies the first parameter-passing reg. */
3272 fprintf_unfiltered (gdb_stdlog
,
3273 "mips_n32n64_push_dummy_call: struct_return reg=%d %s\n",
3274 argreg
, paddress (gdbarch
, struct_addr
));
3275 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3278 /* Now load as many as possible of the first arguments into
3279 registers, and push the rest onto the stack. Loop thru args
3280 from first to last. */
3281 for (argnum
= 0; argnum
< nargs
; argnum
++)
3283 const gdb_byte
*val
;
3284 struct value
*arg
= args
[argnum
];
3285 struct type
*arg_type
= check_typedef (value_type (arg
));
3286 int len
= TYPE_LENGTH (arg_type
);
3287 enum type_code typecode
= TYPE_CODE (arg_type
);
3290 fprintf_unfiltered (gdb_stdlog
,
3291 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3292 argnum
+ 1, len
, (int) typecode
);
3294 val
= value_contents (arg
);
3296 /* A 128-bit long double value requires an even-odd pair of
3297 floating-point registers. */
3299 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3300 && (float_argreg
& 1))
3306 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3307 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3309 /* This is a floating point value that fits entirely
3310 in a single register or a pair of registers. */
3311 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3312 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3314 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3315 float_argreg
, phex (regval
, reglen
));
3316 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3319 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3320 argreg
, phex (regval
, reglen
));
3321 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3326 regval
= extract_unsigned_integer (val
+ reglen
,
3327 reglen
, byte_order
);
3329 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3330 float_argreg
, phex (regval
, reglen
));
3331 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3334 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3335 argreg
, phex (regval
, reglen
));
3336 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3343 /* Copy the argument to general registers or the stack in
3344 register-sized pieces. Large arguments are split between
3345 registers and stack. */
3346 /* For N32/N64, structs, unions, or other composite types are
3347 treated as a sequence of doublewords, and are passed in integer
3348 or floating point registers as though they were simple scalar
3349 parameters to the extent that they fit, with any excess on the
3350 stack packed according to the normal memory layout of the
3352 The caller does not reserve space for the register arguments;
3353 the callee is responsible for reserving it if required. */
3354 /* Note: Floating-point values that didn't fit into an FP
3355 register are only written to memory. */
3358 /* Remember if the argument was written to the stack. */
3359 int stack_used_p
= 0;
3360 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3363 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3366 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3367 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3369 /* Write this portion of the argument to the stack. */
3370 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3372 /* Should shorter than int integer values be
3373 promoted to int before being stored? */
3374 int longword_offset
= 0;
3377 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3379 if ((typecode
== TYPE_CODE_INT
3380 || typecode
== TYPE_CODE_PTR
)
3382 longword_offset
= MIPS64_REGSIZE
- len
;
3387 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3388 paddress (gdbarch
, stack_offset
));
3389 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3390 paddress (gdbarch
, longword_offset
));
3393 addr
= sp
+ stack_offset
+ longword_offset
;
3398 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3399 paddress (gdbarch
, addr
));
3400 for (i
= 0; i
< partial_len
; i
++)
3402 fprintf_unfiltered (gdb_stdlog
, "%02x",
3406 write_memory (addr
, val
, partial_len
);
3409 /* Note!!! This is NOT an else clause. Odd sized
3410 structs may go thru BOTH paths. */
3411 /* Write this portion of the argument to a general
3412 purpose register. */
3413 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3417 /* Sign extend pointers, 32-bit integers and signed
3418 16-bit and 8-bit integers; everything else is taken
3421 if ((partial_len
== 4
3422 && (typecode
== TYPE_CODE_PTR
3423 || typecode
== TYPE_CODE_INT
))
3425 && typecode
== TYPE_CODE_INT
3426 && !TYPE_UNSIGNED (arg_type
)))
3427 regval
= extract_signed_integer (val
, partial_len
,
3430 regval
= extract_unsigned_integer (val
, partial_len
,
3433 /* A non-floating-point argument being passed in a
3434 general register. If a struct or union, and if
3435 the remaining length is smaller than the register
3436 size, we have to adjust the register value on
3439 It does not seem to be necessary to do the
3440 same for integral types. */
3442 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3443 && partial_len
< MIPS64_REGSIZE
3444 && (typecode
== TYPE_CODE_STRUCT
3445 || typecode
== TYPE_CODE_UNION
))
3446 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3450 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3452 phex (regval
, MIPS64_REGSIZE
));
3453 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3455 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3456 TYPE_LENGTH (arg_type
) - len
))
3459 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3461 phex (regval
, MIPS64_REGSIZE
));
3462 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3473 /* Compute the the offset into the stack at which we
3474 will copy the next parameter.
3476 In N32 (N64?), the stack_offset only needs to be
3477 adjusted when it has been used. */
3480 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3484 fprintf_unfiltered (gdb_stdlog
, "\n");
3487 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3489 /* Return adjusted stack pointer. */
3493 static enum return_value_convention
3494 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3495 struct type
*type
, struct regcache
*regcache
,
3496 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3498 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3500 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3502 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3503 if needed), as appropriate for the type. Composite results (struct,
3504 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3507 * A struct with only one or two floating point fields is returned in $f0
3508 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3511 * Any other composite results of at most 128 bits are returned in
3512 $2 (first 64 bits) and $3 (remainder, if necessary).
3514 * Larger composite results are handled by converting the function to a
3515 procedure with an implicit first parameter, which is a pointer to an area
3516 reserved by the caller to receive the result. [The o32-bit ABI requires
3517 that all composite results be handled by conversion to implicit first
3518 parameters. The MIPS/SGI Fortran implementation has always made a
3519 specific exception to return COMPLEX results in the floating point
3522 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3523 return RETURN_VALUE_STRUCT_CONVENTION
;
3524 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3525 && TYPE_LENGTH (type
) == 16
3526 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3528 /* A 128-bit floating-point value fills both $f0 and $f2. The
3529 two registers are used in the same as memory order, so the
3530 eight bytes with the lower memory address are in $f0. */
3532 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3533 mips_xfer_register (gdbarch
, regcache
,
3534 gdbarch_num_regs (gdbarch
)
3535 + mips_regnum (gdbarch
)->fp0
,
3536 8, gdbarch_byte_order (gdbarch
),
3537 readbuf
, writebuf
, 0);
3538 mips_xfer_register (gdbarch
, regcache
,
3539 gdbarch_num_regs (gdbarch
)
3540 + mips_regnum (gdbarch
)->fp0
+ 2,
3541 8, gdbarch_byte_order (gdbarch
),
3542 readbuf
? readbuf
+ 8 : readbuf
,
3543 writebuf
? writebuf
+ 8 : writebuf
, 0);
3544 return RETURN_VALUE_REGISTER_CONVENTION
;
3546 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3547 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3549 /* A single or double floating-point value that fits in FP0. */
3551 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3552 mips_xfer_register (gdbarch
, regcache
,
3553 gdbarch_num_regs (gdbarch
)
3554 + mips_regnum (gdbarch
)->fp0
,
3556 gdbarch_byte_order (gdbarch
),
3557 readbuf
, writebuf
, 0);
3558 return RETURN_VALUE_REGISTER_CONVENTION
;
3560 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3561 && TYPE_NFIELDS (type
) <= 2
3562 && TYPE_NFIELDS (type
) >= 1
3563 && ((TYPE_NFIELDS (type
) == 1
3564 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3566 || (TYPE_NFIELDS (type
) == 2
3567 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3569 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3570 == TYPE_CODE_FLT
))))
3572 /* A struct that contains one or two floats. Each value is part
3573 in the least significant part of their floating point
3574 register (or GPR, for soft float). */
3577 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3578 ? mips_regnum (gdbarch
)->fp0
3580 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3582 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3585 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3587 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3589 /* A 16-byte long double field goes in two consecutive
3591 mips_xfer_register (gdbarch
, regcache
,
3592 gdbarch_num_regs (gdbarch
) + regnum
,
3594 gdbarch_byte_order (gdbarch
),
3595 readbuf
, writebuf
, offset
);
3596 mips_xfer_register (gdbarch
, regcache
,
3597 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3599 gdbarch_byte_order (gdbarch
),
3600 readbuf
, writebuf
, offset
+ 8);
3603 mips_xfer_register (gdbarch
, regcache
,
3604 gdbarch_num_regs (gdbarch
) + regnum
,
3605 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3606 gdbarch_byte_order (gdbarch
),
3607 readbuf
, writebuf
, offset
);
3609 return RETURN_VALUE_REGISTER_CONVENTION
;
3611 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3612 || TYPE_CODE (type
) == TYPE_CODE_UNION
3613 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3615 /* A composite type. Extract the left justified value,
3616 regardless of the byte order. I.e. DO NOT USE
3620 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3621 offset
< TYPE_LENGTH (type
);
3622 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3624 int xfer
= register_size (gdbarch
, regnum
);
3625 if (offset
+ xfer
> TYPE_LENGTH (type
))
3626 xfer
= TYPE_LENGTH (type
) - offset
;
3628 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3629 offset
, xfer
, regnum
);
3630 mips_xfer_register (gdbarch
, regcache
,
3631 gdbarch_num_regs (gdbarch
) + regnum
,
3632 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3635 return RETURN_VALUE_REGISTER_CONVENTION
;
3639 /* A scalar extract each part but least-significant-byte
3643 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3644 offset
< TYPE_LENGTH (type
);
3645 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3647 int xfer
= register_size (gdbarch
, regnum
);
3648 if (offset
+ xfer
> TYPE_LENGTH (type
))
3649 xfer
= TYPE_LENGTH (type
) - offset
;
3651 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3652 offset
, xfer
, regnum
);
3653 mips_xfer_register (gdbarch
, regcache
,
3654 gdbarch_num_regs (gdbarch
) + regnum
,
3655 xfer
, gdbarch_byte_order (gdbarch
),
3656 readbuf
, writebuf
, offset
);
3658 return RETURN_VALUE_REGISTER_CONVENTION
;
3662 /* O32 ABI stuff. */
3665 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3666 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3667 int nargs
, struct value
**args
, CORE_ADDR sp
,
3668 int struct_return
, CORE_ADDR struct_addr
)
3674 int stack_offset
= 0;
3675 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3676 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3677 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3679 /* For shared libraries, "t9" needs to point at the function
3681 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3683 /* Set the return address register to point to the entry point of
3684 the program, where a breakpoint lies in wait. */
3685 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3687 /* First ensure that the stack and structure return address (if any)
3688 are properly aligned. The stack has to be at least 64-bit
3689 aligned even on 32-bit machines, because doubles must be 64-bit
3690 aligned. For n32 and n64, stack frames need to be 128-bit
3691 aligned, so we round to this widest known alignment. */
3693 sp
= align_down (sp
, 16);
3694 struct_addr
= align_down (struct_addr
, 16);
3696 /* Now make space on the stack for the args. */
3697 for (argnum
= 0; argnum
< nargs
; argnum
++)
3699 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3700 int arglen
= TYPE_LENGTH (arg_type
);
3702 /* Align to double-word if necessary. */
3703 if (mips_type_needs_double_align (arg_type
))
3704 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3705 /* Allocate space on the stack. */
3706 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3708 sp
-= align_up (len
, 16);
3711 fprintf_unfiltered (gdb_stdlog
,
3712 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3713 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3715 /* Initialize the integer and float register pointers. */
3716 argreg
= MIPS_A0_REGNUM
;
3717 float_argreg
= mips_fpa0_regnum (gdbarch
);
3719 /* The struct_return pointer occupies the first parameter-passing reg. */
3723 fprintf_unfiltered (gdb_stdlog
,
3724 "mips_o32_push_dummy_call: struct_return reg=%d %s\n",
3725 argreg
, paddress (gdbarch
, struct_addr
));
3726 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3727 stack_offset
+= MIPS32_REGSIZE
;
3730 /* Now load as many as possible of the first arguments into
3731 registers, and push the rest onto the stack. Loop thru args
3732 from first to last. */
3733 for (argnum
= 0; argnum
< nargs
; argnum
++)
3735 const gdb_byte
*val
;
3736 struct value
*arg
= args
[argnum
];
3737 struct type
*arg_type
= check_typedef (value_type (arg
));
3738 int len
= TYPE_LENGTH (arg_type
);
3739 enum type_code typecode
= TYPE_CODE (arg_type
);
3742 fprintf_unfiltered (gdb_stdlog
,
3743 "mips_o32_push_dummy_call: %d len=%d type=%d",
3744 argnum
+ 1, len
, (int) typecode
);
3746 val
= value_contents (arg
);
3748 /* 32-bit ABIs always start floating point arguments in an
3749 even-numbered floating point register. Round the FP register
3750 up before the check to see if there are any FP registers
3751 left. O32/O64 targets also pass the FP in the integer
3752 registers so also round up normal registers. */
3753 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3755 if ((float_argreg
& 1))
3759 /* Floating point arguments passed in registers have to be
3760 treated specially. On 32-bit architectures, doubles
3761 are passed in register pairs; the even register gets
3762 the low word, and the odd register gets the high word.
3763 On O32/O64, the first two floating point arguments are
3764 also copied to general registers, because MIPS16 functions
3765 don't use float registers for arguments. This duplication of
3766 arguments in general registers can't hurt non-MIPS16 functions
3767 because those registers are normally skipped. */
3769 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3770 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3772 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3774 int low_offset
= gdbarch_byte_order (gdbarch
)
3775 == BFD_ENDIAN_BIG
? 4 : 0;
3776 unsigned long regval
;
3778 /* Write the low word of the double to the even register(s). */
3779 regval
= extract_unsigned_integer (val
+ low_offset
,
3782 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3783 float_argreg
, phex (regval
, 4));
3784 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3786 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3787 argreg
, phex (regval
, 4));
3788 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3790 /* Write the high word of the double to the odd register(s). */
3791 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3794 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3795 float_argreg
, phex (regval
, 4));
3796 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3799 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3800 argreg
, phex (regval
, 4));
3801 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3805 /* This is a floating point value that fits entirely
3806 in a single register. */
3807 /* On 32 bit ABI's the float_argreg is further adjusted
3808 above to ensure that it is even register aligned. */
3809 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
3811 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3812 float_argreg
, phex (regval
, len
));
3813 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3814 /* Although two FP registers are reserved for each
3815 argument, only one corresponding integer register is
3818 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3819 argreg
, phex (regval
, len
));
3820 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3822 /* Reserve space for the FP register. */
3823 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3827 /* Copy the argument to general registers or the stack in
3828 register-sized pieces. Large arguments are split between
3829 registers and stack. */
3830 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3831 are treated specially: Irix cc passes
3832 them in registers where gcc sometimes puts them on the
3833 stack. For maximum compatibility, we will put them in
3835 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3836 && len
% MIPS32_REGSIZE
!= 0);
3837 /* Structures should be aligned to eight bytes (even arg registers)
3838 on MIPS_ABI_O32, if their first member has double precision. */
3839 if (mips_type_needs_double_align (arg_type
))
3844 stack_offset
+= MIPS32_REGSIZE
;
3849 /* Remember if the argument was written to the stack. */
3850 int stack_used_p
= 0;
3851 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3854 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3857 /* Write this portion of the argument to the stack. */
3858 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3859 || odd_sized_struct
)
3861 /* Should shorter than int integer values be
3862 promoted to int before being stored? */
3863 int longword_offset
= 0;
3869 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3870 paddress (gdbarch
, stack_offset
));
3871 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3872 paddress (gdbarch
, longword_offset
));
3875 addr
= sp
+ stack_offset
+ longword_offset
;
3880 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3881 paddress (gdbarch
, addr
));
3882 for (i
= 0; i
< partial_len
; i
++)
3884 fprintf_unfiltered (gdb_stdlog
, "%02x",
3888 write_memory (addr
, val
, partial_len
);
3891 /* Note!!! This is NOT an else clause. Odd sized
3892 structs may go thru BOTH paths. */
3893 /* Write this portion of the argument to a general
3894 purpose register. */
3895 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3897 LONGEST regval
= extract_signed_integer (val
, partial_len
,
3899 /* Value may need to be sign extended, because
3900 mips_isa_regsize() != mips_abi_regsize(). */
3902 /* A non-floating-point argument being passed in a
3903 general register. If a struct or union, and if
3904 the remaining length is smaller than the register
3905 size, we have to adjust the register value on
3908 It does not seem to be necessary to do the
3909 same for integral types.
3911 Also don't do this adjustment on O64 binaries.
3913 cagney/2001-07-23: gdb/179: Also, GCC, when
3914 outputting LE O32 with sizeof (struct) <
3915 mips_abi_regsize(), generates a left shift
3916 as part of storing the argument in a register
3917 (the left shift isn't generated when
3918 sizeof (struct) >= mips_abi_regsize()). Since
3919 it is quite possible that this is GCC
3920 contradicting the LE/O32 ABI, GDB has not been
3921 adjusted to accommodate this. Either someone
3922 needs to demonstrate that the LE/O32 ABI
3923 specifies such a left shift OR this new ABI gets
3924 identified as such and GDB gets tweaked
3927 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3928 && partial_len
< MIPS32_REGSIZE
3929 && (typecode
== TYPE_CODE_STRUCT
3930 || typecode
== TYPE_CODE_UNION
))
3931 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3935 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3937 phex (regval
, MIPS32_REGSIZE
));
3938 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3941 /* Prevent subsequent floating point arguments from
3942 being passed in floating point registers. */
3943 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
3949 /* Compute the the offset into the stack at which we
3950 will copy the next parameter.
3952 In older ABIs, the caller reserved space for
3953 registers that contained arguments. This was loosely
3954 refered to as their "home". Consequently, space is
3955 always allocated. */
3957 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3961 fprintf_unfiltered (gdb_stdlog
, "\n");
3964 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3966 /* Return adjusted stack pointer. */
3970 static enum return_value_convention
3971 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3972 struct type
*type
, struct regcache
*regcache
,
3973 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3975 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3977 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3978 || TYPE_CODE (type
) == TYPE_CODE_UNION
3979 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3980 return RETURN_VALUE_STRUCT_CONVENTION
;
3981 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3982 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3984 /* A single-precision floating-point value. It fits in the
3985 least significant part of FP0. */
3987 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3988 mips_xfer_register (gdbarch
, regcache
,
3989 gdbarch_num_regs (gdbarch
)
3990 + mips_regnum (gdbarch
)->fp0
,
3992 gdbarch_byte_order (gdbarch
),
3993 readbuf
, writebuf
, 0);
3994 return RETURN_VALUE_REGISTER_CONVENTION
;
3996 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3997 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3999 /* A double-precision floating-point value. The most
4000 significant part goes in FP1, and the least significant in
4003 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4004 switch (gdbarch_byte_order (gdbarch
))
4006 case BFD_ENDIAN_LITTLE
:
4007 mips_xfer_register (gdbarch
, regcache
,
4008 gdbarch_num_regs (gdbarch
)
4009 + mips_regnum (gdbarch
)->fp0
+
4010 0, 4, gdbarch_byte_order (gdbarch
),
4011 readbuf
, writebuf
, 0);
4012 mips_xfer_register (gdbarch
, regcache
,
4013 gdbarch_num_regs (gdbarch
)
4014 + mips_regnum (gdbarch
)->fp0
+ 1,
4015 4, gdbarch_byte_order (gdbarch
),
4016 readbuf
, writebuf
, 4);
4018 case BFD_ENDIAN_BIG
:
4019 mips_xfer_register (gdbarch
, regcache
,
4020 gdbarch_num_regs (gdbarch
)
4021 + mips_regnum (gdbarch
)->fp0
+ 1,
4022 4, gdbarch_byte_order (gdbarch
),
4023 readbuf
, writebuf
, 0);
4024 mips_xfer_register (gdbarch
, regcache
,
4025 gdbarch_num_regs (gdbarch
)
4026 + mips_regnum (gdbarch
)->fp0
+ 0,
4027 4, gdbarch_byte_order (gdbarch
),
4028 readbuf
, writebuf
, 4);
4031 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4033 return RETURN_VALUE_REGISTER_CONVENTION
;
4036 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4037 && TYPE_NFIELDS (type
) <= 2
4038 && TYPE_NFIELDS (type
) >= 1
4039 && ((TYPE_NFIELDS (type
) == 1
4040 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4042 || (TYPE_NFIELDS (type
) == 2
4043 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4045 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4047 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4049 /* A struct that contains one or two floats. Each value is part
4050 in the least significant part of their floating point
4052 gdb_byte reg
[MAX_REGISTER_SIZE
];
4055 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4056 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4058 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4061 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4063 mips_xfer_register (gdbarch
, regcache
,
4064 gdbarch_num_regs (gdbarch
) + regnum
,
4065 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4066 gdbarch_byte_order (gdbarch
),
4067 readbuf
, writebuf
, offset
);
4069 return RETURN_VALUE_REGISTER_CONVENTION
;
4073 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4074 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4076 /* A structure or union. Extract the left justified value,
4077 regardless of the byte order. I.e. DO NOT USE
4081 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4082 offset
< TYPE_LENGTH (type
);
4083 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4085 int xfer
= register_size (gdbarch
, regnum
);
4086 if (offset
+ xfer
> TYPE_LENGTH (type
))
4087 xfer
= TYPE_LENGTH (type
) - offset
;
4089 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4090 offset
, xfer
, regnum
);
4091 mips_xfer_register (gdbarch
, regcache
,
4092 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4093 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4095 return RETURN_VALUE_REGISTER_CONVENTION
;
4100 /* A scalar extract each part but least-significant-byte
4101 justified. o32 thinks registers are 4 byte, regardless of
4105 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4106 offset
< TYPE_LENGTH (type
);
4107 offset
+= MIPS32_REGSIZE
, regnum
++)
4109 int xfer
= MIPS32_REGSIZE
;
4110 if (offset
+ xfer
> TYPE_LENGTH (type
))
4111 xfer
= TYPE_LENGTH (type
) - offset
;
4113 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4114 offset
, xfer
, regnum
);
4115 mips_xfer_register (gdbarch
, regcache
,
4116 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4117 gdbarch_byte_order (gdbarch
),
4118 readbuf
, writebuf
, offset
);
4120 return RETURN_VALUE_REGISTER_CONVENTION
;
4124 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4128 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4129 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4131 struct value
**args
, CORE_ADDR sp
,
4132 int struct_return
, CORE_ADDR struct_addr
)
4138 int stack_offset
= 0;
4139 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4140 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4141 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4143 /* For shared libraries, "t9" needs to point at the function
4145 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4147 /* Set the return address register to point to the entry point of
4148 the program, where a breakpoint lies in wait. */
4149 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4151 /* First ensure that the stack and structure return address (if any)
4152 are properly aligned. The stack has to be at least 64-bit
4153 aligned even on 32-bit machines, because doubles must be 64-bit
4154 aligned. For n32 and n64, stack frames need to be 128-bit
4155 aligned, so we round to this widest known alignment. */
4157 sp
= align_down (sp
, 16);
4158 struct_addr
= align_down (struct_addr
, 16);
4160 /* Now make space on the stack for the args. */
4161 for (argnum
= 0; argnum
< nargs
; argnum
++)
4163 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4164 int arglen
= TYPE_LENGTH (arg_type
);
4166 /* Allocate space on the stack. */
4167 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4169 sp
-= align_up (len
, 16);
4172 fprintf_unfiltered (gdb_stdlog
,
4173 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4174 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4176 /* Initialize the integer and float register pointers. */
4177 argreg
= MIPS_A0_REGNUM
;
4178 float_argreg
= mips_fpa0_regnum (gdbarch
);
4180 /* The struct_return pointer occupies the first parameter-passing reg. */
4184 fprintf_unfiltered (gdb_stdlog
,
4185 "mips_o64_push_dummy_call: struct_return reg=%d %s\n",
4186 argreg
, paddress (gdbarch
, struct_addr
));
4187 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4188 stack_offset
+= MIPS64_REGSIZE
;
4191 /* Now load as many as possible of the first arguments into
4192 registers, and push the rest onto the stack. Loop thru args
4193 from first to last. */
4194 for (argnum
= 0; argnum
< nargs
; argnum
++)
4196 const gdb_byte
*val
;
4197 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4198 struct value
*arg
= args
[argnum
];
4199 struct type
*arg_type
= check_typedef (value_type (arg
));
4200 int len
= TYPE_LENGTH (arg_type
);
4201 enum type_code typecode
= TYPE_CODE (arg_type
);
4204 fprintf_unfiltered (gdb_stdlog
,
4205 "mips_o64_push_dummy_call: %d len=%d type=%d",
4206 argnum
+ 1, len
, (int) typecode
);
4208 val
= value_contents (arg
);
4210 /* Function pointer arguments to mips16 code need to be made into
4212 if (typecode
== TYPE_CODE_PTR
4213 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4215 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4217 if (mips_pc_is_mips16 (addr
))
4219 store_signed_integer (valbuf
, len
, byte_order
,
4220 make_mips16_addr (addr
));
4225 /* Floating point arguments passed in registers have to be
4226 treated specially. On 32-bit architectures, doubles
4227 are passed in register pairs; the even register gets
4228 the low word, and the odd register gets the high word.
4229 On O32/O64, the first two floating point arguments are
4230 also copied to general registers, because MIPS16 functions
4231 don't use float registers for arguments. This duplication of
4232 arguments in general registers can't hurt non-MIPS16 functions
4233 because those registers are normally skipped. */
4235 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4236 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4238 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4240 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4241 float_argreg
, phex (regval
, len
));
4242 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4244 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4245 argreg
, phex (regval
, len
));
4246 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4248 /* Reserve space for the FP register. */
4249 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4253 /* Copy the argument to general registers or the stack in
4254 register-sized pieces. Large arguments are split between
4255 registers and stack. */
4256 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4257 are treated specially: Irix cc passes them in registers
4258 where gcc sometimes puts them on the stack. For maximum
4259 compatibility, we will put them in both places. */
4260 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4261 && len
% MIPS64_REGSIZE
!= 0);
4264 /* Remember if the argument was written to the stack. */
4265 int stack_used_p
= 0;
4266 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4269 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4272 /* Write this portion of the argument to the stack. */
4273 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4274 || odd_sized_struct
)
4276 /* Should shorter than int integer values be
4277 promoted to int before being stored? */
4278 int longword_offset
= 0;
4281 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4283 if ((typecode
== TYPE_CODE_INT
4284 || typecode
== TYPE_CODE_PTR
4285 || typecode
== TYPE_CODE_FLT
)
4287 longword_offset
= MIPS64_REGSIZE
- len
;
4292 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4293 paddress (gdbarch
, stack_offset
));
4294 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4295 paddress (gdbarch
, longword_offset
));
4298 addr
= sp
+ stack_offset
+ longword_offset
;
4303 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4304 paddress (gdbarch
, addr
));
4305 for (i
= 0; i
< partial_len
; i
++)
4307 fprintf_unfiltered (gdb_stdlog
, "%02x",
4311 write_memory (addr
, val
, partial_len
);
4314 /* Note!!! This is NOT an else clause. Odd sized
4315 structs may go thru BOTH paths. */
4316 /* Write this portion of the argument to a general
4317 purpose register. */
4318 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4320 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4322 /* Value may need to be sign extended, because
4323 mips_isa_regsize() != mips_abi_regsize(). */
4325 /* A non-floating-point argument being passed in a
4326 general register. If a struct or union, and if
4327 the remaining length is smaller than the register
4328 size, we have to adjust the register value on
4331 It does not seem to be necessary to do the
4332 same for integral types. */
4334 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4335 && partial_len
< MIPS64_REGSIZE
4336 && (typecode
== TYPE_CODE_STRUCT
4337 || typecode
== TYPE_CODE_UNION
))
4338 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4342 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4344 phex (regval
, MIPS64_REGSIZE
));
4345 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4348 /* Prevent subsequent floating point arguments from
4349 being passed in floating point registers. */
4350 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4356 /* Compute the the offset into the stack at which we
4357 will copy the next parameter.
4359 In older ABIs, the caller reserved space for
4360 registers that contained arguments. This was loosely
4361 refered to as their "home". Consequently, space is
4362 always allocated. */
4364 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4368 fprintf_unfiltered (gdb_stdlog
, "\n");
4371 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4373 /* Return adjusted stack pointer. */
4377 static enum return_value_convention
4378 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4379 struct type
*type
, struct regcache
*regcache
,
4380 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4382 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4384 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4385 || TYPE_CODE (type
) == TYPE_CODE_UNION
4386 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4387 return RETURN_VALUE_STRUCT_CONVENTION
;
4388 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4390 /* A floating-point value. It fits in the least significant
4393 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4394 mips_xfer_register (gdbarch
, regcache
,
4395 gdbarch_num_regs (gdbarch
)
4396 + mips_regnum (gdbarch
)->fp0
,
4398 gdbarch_byte_order (gdbarch
),
4399 readbuf
, writebuf
, 0);
4400 return RETURN_VALUE_REGISTER_CONVENTION
;
4404 /* A scalar extract each part but least-significant-byte
4408 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4409 offset
< TYPE_LENGTH (type
);
4410 offset
+= MIPS64_REGSIZE
, regnum
++)
4412 int xfer
= MIPS64_REGSIZE
;
4413 if (offset
+ xfer
> TYPE_LENGTH (type
))
4414 xfer
= TYPE_LENGTH (type
) - offset
;
4416 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4417 offset
, xfer
, regnum
);
4418 mips_xfer_register (gdbarch
, regcache
,
4419 gdbarch_num_regs (gdbarch
) + regnum
,
4420 xfer
, gdbarch_byte_order (gdbarch
),
4421 readbuf
, writebuf
, offset
);
4423 return RETURN_VALUE_REGISTER_CONVENTION
;
4427 /* Floating point register management.
4429 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4430 64bit operations, these early MIPS cpus treat fp register pairs
4431 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4432 registers and offer a compatibility mode that emulates the MIPS2 fp
4433 model. When operating in MIPS2 fp compat mode, later cpu's split
4434 double precision floats into two 32-bit chunks and store them in
4435 consecutive fp regs. To display 64-bit floats stored in this
4436 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4437 Throw in user-configurable endianness and you have a real mess.
4439 The way this works is:
4440 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4441 double-precision value will be split across two logical registers.
4442 The lower-numbered logical register will hold the low-order bits,
4443 regardless of the processor's endianness.
4444 - If we are on a 64-bit processor, and we are looking for a
4445 single-precision value, it will be in the low ordered bits
4446 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4447 save slot in memory.
4448 - If we are in 64-bit mode, everything is straightforward.
4450 Note that this code only deals with "live" registers at the top of the
4451 stack. We will attempt to deal with saved registers later, when
4452 the raw/cooked register interface is in place. (We need a general
4453 interface that can deal with dynamic saved register sizes -- fp
4454 regs could be 32 bits wide in one frame and 64 on the frame above
4457 /* Copy a 32-bit single-precision value from the current frame
4458 into rare_buffer. */
4461 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4462 gdb_byte
*rare_buffer
)
4464 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4465 int raw_size
= register_size (gdbarch
, regno
);
4466 gdb_byte
*raw_buffer
= alloca (raw_size
);
4468 if (!frame_register_read (frame
, regno
, raw_buffer
))
4469 error (_("can't read register %d (%s)"),
4470 regno
, gdbarch_register_name (gdbarch
, regno
));
4473 /* We have a 64-bit value for this register. Find the low-order
4477 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4482 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4486 memcpy (rare_buffer
, raw_buffer
, 4);
4490 /* Copy a 64-bit double-precision value from the current frame into
4491 rare_buffer. This may include getting half of it from the next
4495 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4496 gdb_byte
*rare_buffer
)
4498 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4499 int raw_size
= register_size (gdbarch
, regno
);
4501 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4503 /* We have a 64-bit value for this register, and we should use
4505 if (!frame_register_read (frame
, regno
, rare_buffer
))
4506 error (_("can't read register %d (%s)"),
4507 regno
, gdbarch_register_name (gdbarch
, regno
));
4511 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4513 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4514 internal_error (__FILE__
, __LINE__
,
4515 _("mips_read_fp_register_double: bad access to "
4516 "odd-numbered FP register"));
4518 /* mips_read_fp_register_single will find the correct 32 bits from
4520 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4522 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4523 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4527 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4528 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4534 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4536 { /* do values for FP (float) regs */
4537 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4538 gdb_byte
*raw_buffer
;
4539 double doub
, flt1
; /* doubles extracted from raw hex data */
4542 raw_buffer
= alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
));
4544 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4545 fprintf_filtered (file
, "%*s",
4546 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4549 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4551 struct value_print_options opts
;
4553 /* 4-byte registers: Print hex and floating. Also print even
4554 numbered registers as doubles. */
4555 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4556 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
, raw_buffer
, &inv1
);
4558 get_formatted_print_options (&opts
, 'x');
4559 print_scalar_formatted (raw_buffer
,
4560 builtin_type (gdbarch
)->builtin_uint32
,
4563 fprintf_filtered (file
, " flt: ");
4565 fprintf_filtered (file
, " <invalid float> ");
4567 fprintf_filtered (file
, "%-17.9g", flt1
);
4569 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4571 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4572 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4575 fprintf_filtered (file
, " dbl: ");
4577 fprintf_filtered (file
, "<invalid double>");
4579 fprintf_filtered (file
, "%-24.17g", doub
);
4584 struct value_print_options opts
;
4586 /* Eight byte registers: print each one as hex, float and double. */
4587 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4588 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4591 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4592 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4595 get_formatted_print_options (&opts
, 'x');
4596 print_scalar_formatted (raw_buffer
,
4597 builtin_type (gdbarch
)->builtin_uint64
,
4600 fprintf_filtered (file
, " flt: ");
4602 fprintf_filtered (file
, "<invalid float>");
4604 fprintf_filtered (file
, "%-17.9g", flt1
);
4606 fprintf_filtered (file
, " dbl: ");
4608 fprintf_filtered (file
, "<invalid double>");
4610 fprintf_filtered (file
, "%-24.17g", doub
);
4615 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4618 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4619 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4621 struct value_print_options opts
;
4623 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4625 mips_print_fp_register (file
, frame
, regnum
);
4629 /* Get the data in raw format. */
4630 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4632 fprintf_filtered (file
, "%s: [Invalid]",
4633 gdbarch_register_name (gdbarch
, regnum
));
4637 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4639 /* The problem with printing numeric register names (r26, etc.) is that
4640 the user can't use them on input. Probably the best solution is to
4641 fix it so that either the numeric or the funky (a2, etc.) names
4642 are accepted on input. */
4643 if (regnum
< MIPS_NUMREGS
)
4644 fprintf_filtered (file
, "(r%d): ", regnum
);
4646 fprintf_filtered (file
, ": ");
4648 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4650 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4654 get_formatted_print_options (&opts
, 'x');
4655 print_scalar_formatted (raw_buffer
+ offset
,
4656 register_type (gdbarch
, regnum
), &opts
, 0,
4660 /* Replacement for generic do_registers_info.
4661 Print regs in pretty columns. */
4664 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4667 fprintf_filtered (file
, " ");
4668 mips_print_fp_register (file
, frame
, regnum
);
4669 fprintf_filtered (file
, "\n");
4674 /* Print a row's worth of GP (int) registers, with name labels above */
4677 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4680 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4681 /* do values for GP (int) regs */
4682 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4683 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4687 /* For GP registers, we print a separate row of names above the vals */
4688 for (col
= 0, regnum
= start_regnum
;
4689 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4690 + gdbarch_num_pseudo_regs (gdbarch
);
4693 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4694 continue; /* unused register */
4695 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4697 break; /* end the row: reached FP register */
4698 /* Large registers are handled separately. */
4699 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4702 break; /* End the row before this register. */
4704 /* Print this register on a row by itself. */
4705 mips_print_register (file
, frame
, regnum
);
4706 fprintf_filtered (file
, "\n");
4710 fprintf_filtered (file
, " ");
4711 fprintf_filtered (file
,
4712 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4713 gdbarch_register_name (gdbarch
, regnum
));
4720 /* print the R0 to R31 names */
4721 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4722 fprintf_filtered (file
, "\n R%-4d",
4723 start_regnum
% gdbarch_num_regs (gdbarch
));
4725 fprintf_filtered (file
, "\n ");
4727 /* now print the values in hex, 4 or 8 to the row */
4728 for (col
= 0, regnum
= start_regnum
;
4729 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4730 + gdbarch_num_pseudo_regs (gdbarch
);
4733 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4734 continue; /* unused register */
4735 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4737 break; /* end row: reached FP register */
4738 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4739 break; /* End row: large register. */
4741 /* OK: get the data in raw format. */
4742 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4743 error (_("can't read register %d (%s)"),
4744 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4745 /* pad small registers */
4747 byte
< (mips_abi_regsize (gdbarch
)
4748 - register_size (gdbarch
, regnum
)); byte
++)
4749 printf_filtered (" ");
4750 /* Now print the register value in hex, endian order. */
4751 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4753 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4754 byte
< register_size (gdbarch
, regnum
); byte
++)
4755 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4757 for (byte
= register_size (gdbarch
, regnum
) - 1;
4759 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4760 fprintf_filtered (file
, " ");
4763 if (col
> 0) /* ie. if we actually printed anything... */
4764 fprintf_filtered (file
, "\n");
4769 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4772 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4773 struct frame_info
*frame
, int regnum
, int all
)
4775 if (regnum
!= -1) /* do one specified register */
4777 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4778 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4779 error (_("Not a valid register for the current processor type"));
4781 mips_print_register (file
, frame
, regnum
);
4782 fprintf_filtered (file
, "\n");
4785 /* do all (or most) registers */
4787 regnum
= gdbarch_num_regs (gdbarch
);
4788 while (regnum
< gdbarch_num_regs (gdbarch
)
4789 + gdbarch_num_pseudo_regs (gdbarch
))
4791 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4794 if (all
) /* true for "INFO ALL-REGISTERS" command */
4795 regnum
= print_fp_register_row (file
, frame
, regnum
);
4797 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4800 regnum
= print_gp_register_row (file
, frame
, regnum
);
4805 /* Is this a branch with a delay slot? */
4808 is_delayed (unsigned long insn
)
4811 for (i
= 0; i
< NUMOPCODES
; ++i
)
4812 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4813 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4815 return (i
< NUMOPCODES
4816 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4817 | INSN_COND_BRANCH_DELAY
4818 | INSN_COND_BRANCH_LIKELY
)));
4822 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4823 struct frame_info
*frame
)
4825 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4826 CORE_ADDR pc
= get_frame_pc (frame
);
4827 gdb_byte buf
[MIPS_INSN32_SIZE
];
4829 /* There is no branch delay slot on MIPS16. */
4830 if (mips_pc_is_mips16 (pc
))
4833 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
4836 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4837 /* If error reading memory, guess that it is not a delayed
4840 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
4843 /* To skip prologues, I use this predicate. Returns either PC itself
4844 if the code at PC does not look like a function prologue; otherwise
4845 returns an address that (if we're lucky) follows the prologue. If
4846 LENIENT, then we must skip everything which is involved in setting
4847 up the frame (it's OK to skip more, just so long as we don't skip
4848 anything which might clobber the registers which are being saved.
4849 We must skip more in the case where part of the prologue is in the
4850 delay slot of a non-prologue instruction). */
4853 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4856 CORE_ADDR func_addr
;
4858 /* See if we can determine the end of the prologue via the symbol table.
4859 If so, then return either PC, or the PC after the prologue, whichever
4861 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4863 CORE_ADDR post_prologue_pc
4864 = skip_prologue_using_sal (gdbarch
, func_addr
);
4865 if (post_prologue_pc
!= 0)
4866 return max (pc
, post_prologue_pc
);
4869 /* Can't determine prologue from the symbol table, need to examine
4872 /* Find an upper limit on the function prologue using the debug
4873 information. If the debug information could not be used to provide
4874 that bound, then use an arbitrary large number as the upper bound. */
4875 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
4877 limit_pc
= pc
+ 100; /* Magic. */
4879 if (mips_pc_is_mips16 (pc
))
4880 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4882 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4885 /* Check whether the PC is in a function epilogue (32-bit version).
4886 This is a helper function for mips_in_function_epilogue_p. */
4888 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4890 CORE_ADDR func_addr
= 0, func_end
= 0;
4892 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4894 /* The MIPS epilogue is max. 12 bytes long. */
4895 CORE_ADDR addr
= func_end
- 12;
4897 if (addr
< func_addr
+ 4)
4898 addr
= func_addr
+ 4;
4902 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4904 unsigned long high_word
;
4907 inst
= mips_fetch_instruction (gdbarch
, pc
);
4908 high_word
= (inst
>> 16) & 0xffff;
4910 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4911 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4912 && inst
!= 0x03e00008 /* jr $ra */
4913 && inst
!= 0x00000000) /* nop */
4923 /* Check whether the PC is in a function epilogue (16-bit version).
4924 This is a helper function for mips_in_function_epilogue_p. */
4926 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4928 CORE_ADDR func_addr
= 0, func_end
= 0;
4930 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4932 /* The MIPS epilogue is max. 12 bytes long. */
4933 CORE_ADDR addr
= func_end
- 12;
4935 if (addr
< func_addr
+ 4)
4936 addr
= func_addr
+ 4;
4940 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4942 unsigned short inst
;
4944 inst
= mips_fetch_instruction (gdbarch
, pc
);
4946 if ((inst
& 0xf800) == 0xf000) /* extend */
4949 if (inst
!= 0x6300 /* addiu $sp,offset */
4950 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
4951 && inst
!= 0xe820 /* jr $ra */
4952 && inst
!= 0xe8a0 /* jrc $ra */
4953 && inst
!= 0x6500) /* nop */
4963 /* The epilogue is defined here as the area at the end of a function,
4964 after an instruction which destroys the function's stack frame. */
4966 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4968 if (mips_pc_is_mips16 (pc
))
4969 return mips16_in_function_epilogue_p (gdbarch
, pc
);
4971 return mips32_in_function_epilogue_p (gdbarch
, pc
);
4974 /* Root of all "set mips "/"show mips " commands. This will eventually be
4975 used for all MIPS-specific commands. */
4978 show_mips_command (char *args
, int from_tty
)
4980 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4984 set_mips_command (char *args
, int from_tty
)
4987 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4988 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4991 /* Commands to show/set the MIPS FPU type. */
4994 show_mipsfpu_command (char *args
, int from_tty
)
4998 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5001 ("The MIPS floating-point coprocessor is unknown "
5002 "because the current architecture is not MIPS.\n");
5006 switch (MIPS_FPU_TYPE (target_gdbarch
))
5008 case MIPS_FPU_SINGLE
:
5009 fpu
= "single-precision";
5011 case MIPS_FPU_DOUBLE
:
5012 fpu
= "double-precision";
5015 fpu
= "absent (none)";
5018 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5020 if (mips_fpu_type_auto
)
5022 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5026 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5031 set_mipsfpu_command (char *args
, int from_tty
)
5034 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5035 show_mipsfpu_command (args
, from_tty
);
5039 set_mipsfpu_single_command (char *args
, int from_tty
)
5041 struct gdbarch_info info
;
5042 gdbarch_info_init (&info
);
5043 mips_fpu_type
= MIPS_FPU_SINGLE
;
5044 mips_fpu_type_auto
= 0;
5045 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5046 instead of relying on globals. Doing that would let generic code
5047 handle the search for this specific architecture. */
5048 if (!gdbarch_update_p (info
))
5049 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5053 set_mipsfpu_double_command (char *args
, int from_tty
)
5055 struct gdbarch_info info
;
5056 gdbarch_info_init (&info
);
5057 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5058 mips_fpu_type_auto
= 0;
5059 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5060 instead of relying on globals. Doing that would let generic code
5061 handle the search for this specific architecture. */
5062 if (!gdbarch_update_p (info
))
5063 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5067 set_mipsfpu_none_command (char *args
, int from_tty
)
5069 struct gdbarch_info info
;
5070 gdbarch_info_init (&info
);
5071 mips_fpu_type
= MIPS_FPU_NONE
;
5072 mips_fpu_type_auto
= 0;
5073 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5074 instead of relying on globals. Doing that would let generic code
5075 handle the search for this specific architecture. */
5076 if (!gdbarch_update_p (info
))
5077 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5081 set_mipsfpu_auto_command (char *args
, int from_tty
)
5083 mips_fpu_type_auto
= 1;
5086 /* Attempt to identify the particular processor model by reading the
5087 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5088 the relevant processor still exists (it dates back to '94) and
5089 secondly this is not the way to do this. The processor type should
5090 be set by forcing an architecture change. */
5093 deprecated_mips_set_processor_regs_hack (void)
5095 struct regcache
*regcache
= get_current_regcache ();
5096 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5097 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5100 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5101 if ((prid
& ~0xf) == 0x700)
5102 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5105 /* Just like reinit_frame_cache, but with the right arguments to be
5106 callable as an sfunc. */
5109 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5110 struct cmd_list_element
*c
)
5112 reinit_frame_cache ();
5116 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5118 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5119 disassembler needs to be able to locally determine the ISA, and
5120 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5122 if (mips_pc_is_mips16 (memaddr
))
5123 info
->mach
= bfd_mach_mips16
;
5125 /* Round down the instruction address to the appropriate boundary. */
5126 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5128 /* Set the disassembler options. */
5129 if (!info
->disassembler_options
)
5130 /* This string is not recognized explicitly by the disassembler,
5131 but it tells the disassembler to not try to guess the ABI from
5132 the bfd elf headers, such that, if the user overrides the ABI
5133 of a program linked as NewABI, the disassembly will follow the
5134 register naming conventions specified by the user. */
5135 info
->disassembler_options
= "gpr-names=32";
5137 /* Call the appropriate disassembler based on the target endian-ness. */
5138 if (info
->endian
== BFD_ENDIAN_BIG
)
5139 return print_insn_big_mips (memaddr
, info
);
5141 return print_insn_little_mips (memaddr
, info
);
5145 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5147 /* Set up the disassembler info, so that we get the right
5148 register names from libopcodes. */
5149 info
->disassembler_options
= "gpr-names=n32";
5150 info
->flavour
= bfd_target_elf_flavour
;
5152 return gdb_print_insn_mips (memaddr
, info
);
5156 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5158 /* Set up the disassembler info, so that we get the right
5159 register names from libopcodes. */
5160 info
->disassembler_options
= "gpr-names=64";
5161 info
->flavour
= bfd_target_elf_flavour
;
5163 return gdb_print_insn_mips (memaddr
, info
);
5166 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
5167 counter value to determine whether a 16- or 32-bit breakpoint should be used.
5168 It returns a pointer to a string of bytes that encode a breakpoint
5169 instruction, stores the length of the string to *lenptr, and adjusts pc (if
5170 necessary) to point to the actual memory location where the breakpoint
5171 should be inserted. */
5173 static const gdb_byte
*
5174 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
5176 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5178 if (mips_pc_is_mips16 (*pcptr
))
5180 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5181 *pcptr
= unmake_mips16_addr (*pcptr
);
5182 *lenptr
= sizeof (mips16_big_breakpoint
);
5183 return mips16_big_breakpoint
;
5187 /* The IDT board uses an unusual breakpoint value, and
5188 sometimes gets confused when it sees the usual MIPS
5189 breakpoint instruction. */
5190 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5191 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5192 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5193 /* Likewise, IRIX appears to expect a different breakpoint,
5194 although this is not apparent until you try to use pthreads. */
5195 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5197 *lenptr
= sizeof (big_breakpoint
);
5199 if (strcmp (target_shortname
, "mips") == 0)
5200 return idt_big_breakpoint
;
5201 else if (strcmp (target_shortname
, "ddb") == 0
5202 || strcmp (target_shortname
, "pmon") == 0
5203 || strcmp (target_shortname
, "lsi") == 0)
5204 return pmon_big_breakpoint
;
5205 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5206 return irix_big_breakpoint
;
5208 return big_breakpoint
;
5213 if (mips_pc_is_mips16 (*pcptr
))
5215 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5216 *pcptr
= unmake_mips16_addr (*pcptr
);
5217 *lenptr
= sizeof (mips16_little_breakpoint
);
5218 return mips16_little_breakpoint
;
5222 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5223 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5224 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5226 *lenptr
= sizeof (little_breakpoint
);
5228 if (strcmp (target_shortname
, "mips") == 0)
5229 return idt_little_breakpoint
;
5230 else if (strcmp (target_shortname
, "ddb") == 0
5231 || strcmp (target_shortname
, "pmon") == 0
5232 || strcmp (target_shortname
, "lsi") == 0)
5233 return pmon_little_breakpoint
;
5235 return little_breakpoint
;
5240 /* If PC is in a mips16 call or return stub, return the address of the target
5241 PC, which is either the callee or the caller. There are several
5242 cases which must be handled:
5244 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5245 target PC is in $31 ($ra).
5246 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5247 and the target PC is in $2.
5248 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5249 before the jal instruction, this is effectively a call stub
5250 and the the target PC is in $2. Otherwise this is effectively
5251 a return stub and the target PC is in $18.
5253 See the source code for the stubs in gcc/config/mips/mips16.S for
5257 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5259 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5261 CORE_ADDR start_addr
;
5263 /* Find the starting address and name of the function containing the PC. */
5264 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5267 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5268 target PC is in $31 ($ra). */
5269 if (strcmp (name
, "__mips16_ret_sf") == 0
5270 || strcmp (name
, "__mips16_ret_df") == 0)
5271 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5273 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5275 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5276 and the target PC is in $2. */
5277 if (name
[19] >= '0' && name
[19] <= '9')
5278 return get_frame_register_signed (frame
, 2);
5280 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5281 before the jal instruction, this is effectively a call stub
5282 and the the target PC is in $2. Otherwise this is effectively
5283 a return stub and the target PC is in $18. */
5284 else if (name
[19] == 's' || name
[19] == 'd')
5286 if (pc
== start_addr
)
5288 /* Check if the target of the stub is a compiler-generated
5289 stub. Such a stub for a function bar might have a name
5290 like __fn_stub_bar, and might look like this:
5295 la $1,bar (becomes a lui/addiu pair)
5297 So scan down to the lui/addi and extract the target
5298 address from those two instructions. */
5300 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5304 /* See if the name of the target function is __fn_stub_*. */
5305 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5308 if (strncmp (name
, "__fn_stub_", 10) != 0
5309 && strcmp (name
, "etext") != 0
5310 && strcmp (name
, "_etext") != 0)
5313 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5314 The limit on the search is arbitrarily set to 20
5315 instructions. FIXME. */
5316 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5318 inst
= mips_fetch_instruction (gdbarch
, target_pc
);
5319 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5320 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5321 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5322 return pc
| (inst
& 0xffff); /* low word */
5325 /* Couldn't find the lui/addui pair, so return stub address. */
5329 /* This is the 'return' part of a call stub. The return
5330 address is in $r18. */
5331 return get_frame_register_signed (frame
, 18);
5334 return 0; /* not a stub */
5337 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5338 PC of the stub target. The stub just loads $t9 and jumps to it,
5339 so that $t9 has the correct value at function entry. */
5342 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5344 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5345 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5346 struct minimal_symbol
*msym
;
5348 gdb_byte stub_code
[16];
5349 int32_t stub_words
[4];
5351 /* The stub for foo is named ".pic.foo", and is either two
5352 instructions inserted before foo or a three instruction sequence
5353 which jumps to foo. */
5354 msym
= lookup_minimal_symbol_by_pc (pc
);
5356 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5357 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5358 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5361 /* A two-instruction header. */
5362 if (MSYMBOL_SIZE (msym
) == 8)
5365 /* A three-instruction (plus delay slot) trampoline. */
5366 if (MSYMBOL_SIZE (msym
) == 16)
5368 if (target_read_memory (pc
, stub_code
, 16) != 0)
5370 for (i
= 0; i
< 4; i
++)
5371 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
5374 /* A stub contains these instructions:
5377 addiu t9, t9, %lo(target)
5380 This works even for N64, since stubs are only generated with
5382 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5383 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5384 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5385 && stub_words
[3] == 0x00000000)
5386 return (((stub_words
[0] & 0x0000ffff) << 16)
5387 + (stub_words
[2] & 0x0000ffff));
5390 /* Not a recognized stub. */
5395 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5397 CORE_ADDR target_pc
;
5399 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5403 target_pc
= find_solib_trampoline_target (frame
, pc
);
5407 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5414 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5415 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5418 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5421 if (num
>= 0 && num
< 32)
5423 else if (num
>= 38 && num
< 70)
5424 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5426 regnum
= mips_regnum (gdbarch
)->hi
;
5428 regnum
= mips_regnum (gdbarch
)->lo
;
5430 /* This will hopefully (eventually) provoke a warning. Should
5431 we be calling complaint() here? */
5432 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5433 return gdbarch_num_regs (gdbarch
) + regnum
;
5437 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5438 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5441 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5444 if (num
>= 0 && num
< 32)
5446 else if (num
>= 32 && num
< 64)
5447 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5449 regnum
= mips_regnum (gdbarch
)->hi
;
5451 regnum
= mips_regnum (gdbarch
)->lo
;
5453 /* This will hopefully (eventually) provoke a warning. Should we
5454 be calling complaint() here? */
5455 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5456 return gdbarch_num_regs (gdbarch
) + regnum
;
5460 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5462 /* Only makes sense to supply raw registers. */
5463 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5464 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5465 decide if it is valid. Should instead define a standard sim/gdb
5466 register numbering scheme. */
5467 if (gdbarch_register_name (gdbarch
,
5468 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5469 && gdbarch_register_name (gdbarch
,
5470 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
5473 return LEGACY_SIM_REGNO_IGNORE
;
5477 /* Convert an integer into an address. Extracting the value signed
5478 guarantees a correctly sign extended address. */
5481 mips_integer_to_address (struct gdbarch
*gdbarch
,
5482 struct type
*type
, const gdb_byte
*buf
)
5484 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5485 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
5488 /* Dummy virtual frame pointer method. This is no more or less accurate
5489 than most other architectures; we just need to be explicit about it,
5490 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5491 an assertion failure. */
5494 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5495 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5497 *reg
= MIPS_SP_REGNUM
;
5502 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5504 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5505 const char *name
= bfd_get_section_name (abfd
, sect
);
5507 if (*abip
!= MIPS_ABI_UNKNOWN
)
5510 if (strncmp (name
, ".mdebug.", 8) != 0)
5513 if (strcmp (name
, ".mdebug.abi32") == 0)
5514 *abip
= MIPS_ABI_O32
;
5515 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5516 *abip
= MIPS_ABI_N32
;
5517 else if (strcmp (name
, ".mdebug.abi64") == 0)
5518 *abip
= MIPS_ABI_N64
;
5519 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5520 *abip
= MIPS_ABI_O64
;
5521 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5522 *abip
= MIPS_ABI_EABI32
;
5523 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5524 *abip
= MIPS_ABI_EABI64
;
5526 warning (_("unsupported ABI %s."), name
+ 8);
5530 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5532 int *lbp
= (int *) obj
;
5533 const char *name
= bfd_get_section_name (abfd
, sect
);
5535 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5537 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5539 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5540 warning (_("unrecognized .gcc_compiled_longXX"));
5543 static enum mips_abi
5544 global_mips_abi (void)
5548 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5549 if (mips_abi_strings
[i
] == mips_abi_string
)
5550 return (enum mips_abi
) i
;
5552 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5556 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5558 /* If the size matches the set of 32-bit or 64-bit integer registers,
5559 assume that's what we've got. */
5560 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5561 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5563 /* If the size matches the full set of registers GDB traditionally
5564 knows about, including floating point, for either 32-bit or
5565 64-bit, assume that's what we've got. */
5566 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5567 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5569 /* Otherwise we don't have a useful guess. */
5572 static struct value
*
5573 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5575 const int *reg_p
= baton
;
5576 return value_of_register (*reg_p
, frame
);
5579 static struct gdbarch
*
5580 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5582 struct gdbarch
*gdbarch
;
5583 struct gdbarch_tdep
*tdep
;
5585 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5587 enum mips_fpu_type fpu_type
;
5588 struct tdesc_arch_data
*tdesc_data
= NULL
;
5589 int elf_fpu_type
= 0;
5591 /* Check any target description for validity. */
5592 if (tdesc_has_registers (info
.target_desc
))
5594 static const char *const mips_gprs
[] = {
5595 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5596 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5597 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5598 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5600 static const char *const mips_fprs
[] = {
5601 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5602 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5603 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5604 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5607 const struct tdesc_feature
*feature
;
5610 feature
= tdesc_find_feature (info
.target_desc
,
5611 "org.gnu.gdb.mips.cpu");
5612 if (feature
== NULL
)
5615 tdesc_data
= tdesc_data_alloc ();
5618 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5619 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5623 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5624 MIPS_EMBED_LO_REGNUM
, "lo");
5625 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5626 MIPS_EMBED_HI_REGNUM
, "hi");
5627 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5628 MIPS_EMBED_PC_REGNUM
, "pc");
5632 tdesc_data_cleanup (tdesc_data
);
5636 feature
= tdesc_find_feature (info
.target_desc
,
5637 "org.gnu.gdb.mips.cp0");
5638 if (feature
== NULL
)
5640 tdesc_data_cleanup (tdesc_data
);
5645 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5646 MIPS_EMBED_BADVADDR_REGNUM
,
5648 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5649 MIPS_PS_REGNUM
, "status");
5650 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5651 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5655 tdesc_data_cleanup (tdesc_data
);
5659 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5660 backend is not prepared for that, though. */
5661 feature
= tdesc_find_feature (info
.target_desc
,
5662 "org.gnu.gdb.mips.fpu");
5663 if (feature
== NULL
)
5665 tdesc_data_cleanup (tdesc_data
);
5670 for (i
= 0; i
< 32; i
++)
5671 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5672 i
+ MIPS_EMBED_FP0_REGNUM
,
5675 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5676 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5677 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5678 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5682 tdesc_data_cleanup (tdesc_data
);
5686 /* It would be nice to detect an attempt to use a 64-bit ABI
5687 when only 32-bit registers are provided. */
5690 /* First of all, extract the elf_flags, if available. */
5691 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5692 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5693 else if (arches
!= NULL
)
5694 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5698 fprintf_unfiltered (gdb_stdlog
,
5699 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5701 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5702 switch ((elf_flags
& EF_MIPS_ABI
))
5704 case E_MIPS_ABI_O32
:
5705 found_abi
= MIPS_ABI_O32
;
5707 case E_MIPS_ABI_O64
:
5708 found_abi
= MIPS_ABI_O64
;
5710 case E_MIPS_ABI_EABI32
:
5711 found_abi
= MIPS_ABI_EABI32
;
5713 case E_MIPS_ABI_EABI64
:
5714 found_abi
= MIPS_ABI_EABI64
;
5717 if ((elf_flags
& EF_MIPS_ABI2
))
5718 found_abi
= MIPS_ABI_N32
;
5720 found_abi
= MIPS_ABI_UNKNOWN
;
5724 /* GCC creates a pseudo-section whose name describes the ABI. */
5725 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5726 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5728 /* If we have no useful BFD information, use the ABI from the last
5729 MIPS architecture (if there is one). */
5730 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5731 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5733 /* Try the architecture for any hint of the correct ABI. */
5734 if (found_abi
== MIPS_ABI_UNKNOWN
5735 && info
.bfd_arch_info
!= NULL
5736 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5738 switch (info
.bfd_arch_info
->mach
)
5740 case bfd_mach_mips3900
:
5741 found_abi
= MIPS_ABI_EABI32
;
5743 case bfd_mach_mips4100
:
5744 case bfd_mach_mips5000
:
5745 found_abi
= MIPS_ABI_EABI64
;
5747 case bfd_mach_mips8000
:
5748 case bfd_mach_mips10000
:
5749 /* On Irix, ELF64 executables use the N64 ABI. The
5750 pseudo-sections which describe the ABI aren't present
5751 on IRIX. (Even for executables created by gcc.) */
5752 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5753 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5754 found_abi
= MIPS_ABI_N64
;
5756 found_abi
= MIPS_ABI_N32
;
5761 /* Default 64-bit objects to N64 instead of O32. */
5762 if (found_abi
== MIPS_ABI_UNKNOWN
5763 && info
.abfd
!= NULL
5764 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5765 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5766 found_abi
= MIPS_ABI_N64
;
5769 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5772 /* What has the user specified from the command line? */
5773 wanted_abi
= global_mips_abi ();
5775 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5778 /* Now that we have found what the ABI for this binary would be,
5779 check whether the user is overriding it. */
5780 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5781 mips_abi
= wanted_abi
;
5782 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5783 mips_abi
= found_abi
;
5785 mips_abi
= MIPS_ABI_O32
;
5787 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5790 /* Also used when doing an architecture lookup. */
5792 fprintf_unfiltered (gdb_stdlog
,
5793 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5794 mips64_transfers_32bit_regs_p
);
5796 /* Determine the MIPS FPU type. */
5799 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5800 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5801 Tag_GNU_MIPS_ABI_FP
);
5802 #endif /* HAVE_ELF */
5804 if (!mips_fpu_type_auto
)
5805 fpu_type
= mips_fpu_type
;
5806 else if (elf_fpu_type
!= 0)
5808 switch (elf_fpu_type
)
5811 fpu_type
= MIPS_FPU_DOUBLE
;
5814 fpu_type
= MIPS_FPU_SINGLE
;
5818 /* Soft float or unknown. */
5819 fpu_type
= MIPS_FPU_NONE
;
5823 else if (info
.bfd_arch_info
!= NULL
5824 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5825 switch (info
.bfd_arch_info
->mach
)
5827 case bfd_mach_mips3900
:
5828 case bfd_mach_mips4100
:
5829 case bfd_mach_mips4111
:
5830 case bfd_mach_mips4120
:
5831 fpu_type
= MIPS_FPU_NONE
;
5833 case bfd_mach_mips4650
:
5834 fpu_type
= MIPS_FPU_SINGLE
;
5837 fpu_type
= MIPS_FPU_DOUBLE
;
5840 else if (arches
!= NULL
)
5841 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5843 fpu_type
= MIPS_FPU_DOUBLE
;
5845 fprintf_unfiltered (gdb_stdlog
,
5846 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5848 /* Check for blatant incompatibilities. */
5850 /* If we have only 32-bit registers, then we can't debug a 64-bit
5852 if (info
.target_desc
5853 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5854 && mips_abi
!= MIPS_ABI_EABI32
5855 && mips_abi
!= MIPS_ABI_O32
)
5857 if (tdesc_data
!= NULL
)
5858 tdesc_data_cleanup (tdesc_data
);
5862 /* try to find a pre-existing architecture */
5863 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5865 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5867 /* MIPS needs to be pedantic about which ABI the object is
5869 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5871 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5873 /* Need to be pedantic about which register virtual size is
5875 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5876 != mips64_transfers_32bit_regs_p
)
5878 /* Be pedantic about which FPU is selected. */
5879 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5882 if (tdesc_data
!= NULL
)
5883 tdesc_data_cleanup (tdesc_data
);
5884 return arches
->gdbarch
;
5887 /* Need a new architecture. Fill in a target specific vector. */
5888 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5889 gdbarch
= gdbarch_alloc (&info
, tdep
);
5890 tdep
->elf_flags
= elf_flags
;
5891 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5892 tdep
->found_abi
= found_abi
;
5893 tdep
->mips_abi
= mips_abi
;
5894 tdep
->mips_fpu_type
= fpu_type
;
5895 tdep
->register_size_valid_p
= 0;
5896 tdep
->register_size
= 0;
5897 tdep
->gregset
= NULL
;
5898 tdep
->gregset64
= NULL
;
5899 tdep
->fpregset
= NULL
;
5900 tdep
->fpregset64
= NULL
;
5902 if (info
.target_desc
)
5904 /* Some useful properties can be inferred from the target. */
5905 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5907 tdep
->register_size_valid_p
= 1;
5908 tdep
->register_size
= 4;
5910 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5912 tdep
->register_size_valid_p
= 1;
5913 tdep
->register_size
= 8;
5917 /* Initially set everything according to the default ABI/ISA. */
5918 set_gdbarch_short_bit (gdbarch
, 16);
5919 set_gdbarch_int_bit (gdbarch
, 32);
5920 set_gdbarch_float_bit (gdbarch
, 32);
5921 set_gdbarch_double_bit (gdbarch
, 64);
5922 set_gdbarch_long_double_bit (gdbarch
, 64);
5923 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5924 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5925 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5927 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5928 mips_elf_make_msymbol_special
);
5930 /* Fill in the OS dependant register numbers and names. */
5932 const char **reg_names
;
5933 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5934 struct mips_regnum
);
5935 if (tdesc_has_registers (info
.target_desc
))
5937 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5938 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5939 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5940 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5941 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5942 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5943 regnum
->fp_control_status
= 70;
5944 regnum
->fp_implementation_revision
= 71;
5945 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5948 else if (info
.osabi
== GDB_OSABI_IRIX
)
5953 regnum
->badvaddr
= 66;
5956 regnum
->fp_control_status
= 69;
5957 regnum
->fp_implementation_revision
= 70;
5959 reg_names
= mips_irix_reg_names
;
5963 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5964 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5965 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5966 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5967 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5968 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5969 regnum
->fp_control_status
= 70;
5970 regnum
->fp_implementation_revision
= 71;
5972 if (info
.bfd_arch_info
!= NULL
5973 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5974 reg_names
= mips_tx39_reg_names
;
5976 reg_names
= mips_generic_reg_names
;
5978 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5979 replaced by gdbarch_read_pc? */
5980 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5981 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5982 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5983 set_gdbarch_num_regs (gdbarch
, num_regs
);
5984 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5985 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5986 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
5987 tdep
->mips_processor_reg_names
= reg_names
;
5988 tdep
->regnum
= regnum
;
5994 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5995 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5996 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5997 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5998 tdep
->default_mask_address_p
= 0;
5999 set_gdbarch_long_bit (gdbarch
, 32);
6000 set_gdbarch_ptr_bit (gdbarch
, 32);
6001 set_gdbarch_long_long_bit (gdbarch
, 64);
6004 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6005 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6006 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6007 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6008 tdep
->default_mask_address_p
= 0;
6009 set_gdbarch_long_bit (gdbarch
, 32);
6010 set_gdbarch_ptr_bit (gdbarch
, 32);
6011 set_gdbarch_long_long_bit (gdbarch
, 64);
6013 case MIPS_ABI_EABI32
:
6014 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6015 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6016 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6017 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6018 tdep
->default_mask_address_p
= 0;
6019 set_gdbarch_long_bit (gdbarch
, 32);
6020 set_gdbarch_ptr_bit (gdbarch
, 32);
6021 set_gdbarch_long_long_bit (gdbarch
, 64);
6023 case MIPS_ABI_EABI64
:
6024 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6025 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6026 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6027 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6028 tdep
->default_mask_address_p
= 0;
6029 set_gdbarch_long_bit (gdbarch
, 64);
6030 set_gdbarch_ptr_bit (gdbarch
, 64);
6031 set_gdbarch_long_long_bit (gdbarch
, 64);
6034 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6035 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6036 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6037 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6038 tdep
->default_mask_address_p
= 0;
6039 set_gdbarch_long_bit (gdbarch
, 32);
6040 set_gdbarch_ptr_bit (gdbarch
, 32);
6041 set_gdbarch_long_long_bit (gdbarch
, 64);
6042 set_gdbarch_long_double_bit (gdbarch
, 128);
6043 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6046 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6047 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6048 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6049 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6050 tdep
->default_mask_address_p
= 0;
6051 set_gdbarch_long_bit (gdbarch
, 64);
6052 set_gdbarch_ptr_bit (gdbarch
, 64);
6053 set_gdbarch_long_long_bit (gdbarch
, 64);
6054 set_gdbarch_long_double_bit (gdbarch
, 128);
6055 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6058 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6061 /* GCC creates a pseudo-section whose name specifies the size of
6062 longs, since -mlong32 or -mlong64 may be used independent of
6063 other options. How those options affect pointer sizes is ABI and
6064 architecture dependent, so use them to override the default sizes
6065 set by the ABI. This table shows the relationship between ABI,
6066 -mlongXX, and size of pointers:
6068 ABI -mlongXX ptr bits
6069 --- -------- --------
6083 Note that for o32 and eabi32, pointers are always 32 bits
6084 regardless of any -mlongXX option. For all others, pointers and
6085 longs are the same, as set by -mlongXX or set by defaults.
6088 if (info
.abfd
!= NULL
)
6092 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6095 set_gdbarch_long_bit (gdbarch
, long_bit
);
6099 case MIPS_ABI_EABI32
:
6104 case MIPS_ABI_EABI64
:
6105 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6108 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6113 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6114 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6117 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6118 flag in object files because to do so would make it impossible to
6119 link with libraries compiled without "-gp32". This is
6120 unnecessarily restrictive.
6122 We could solve this problem by adding "-gp32" multilibs to gcc,
6123 but to set this flag before gcc is built with such multilibs will
6124 break too many systems.''
6126 But even more unhelpfully, the default linker output target for
6127 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6128 for 64-bit programs - you need to change the ABI to change this,
6129 and not all gcc targets support that currently. Therefore using
6130 this flag to detect 32-bit mode would do the wrong thing given
6131 the current gcc - it would make GDB treat these 64-bit programs
6132 as 32-bit programs by default. */
6134 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6135 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6137 /* Add/remove bits from an address. The MIPS needs be careful to
6138 ensure that all 32 bit addresses are sign extended to 64 bits. */
6139 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6141 /* Unwind the frame. */
6142 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6143 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
6144 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
6146 /* Map debug register numbers onto internal register numbers. */
6147 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6148 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6149 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6150 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6151 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6152 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6154 /* MIPS version of CALL_DUMMY */
6156 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6157 replaced by a command, and all targets will default to on stack
6158 (regardless of the stack's execute status). */
6159 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6160 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6162 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6163 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6164 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6166 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6167 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6169 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6171 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6173 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6174 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6175 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6177 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6179 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6181 if (mips_abi
== MIPS_ABI_N32
)
6182 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6183 else if (mips_abi
== MIPS_ABI_N64
)
6184 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6186 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6188 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6189 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6190 need to all be folded into the target vector. Since they are
6191 being used as guards for target_stopped_by_watchpoint, why not have
6192 target_stopped_by_watchpoint return the type of watchpoint that the code
6194 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6196 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6198 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
6200 /* Virtual tables. */
6201 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6203 mips_register_g_packet_guesses (gdbarch
);
6205 /* Hook in OS ABI-specific overrides, if they have been registered. */
6206 info
.tdep_info
= (void *) tdesc_data
;
6207 gdbarch_init_osabi (info
, gdbarch
);
6209 /* Unwind the frame. */
6210 dwarf2_append_unwinders (gdbarch
);
6211 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6212 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6213 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6214 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6215 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6216 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6217 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6221 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6222 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6224 /* Override the normal target description methods to handle our
6225 dual real and pseudo registers. */
6226 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6227 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
6229 num_regs
= gdbarch_num_regs (gdbarch
);
6230 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6231 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6232 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6235 /* Add ABI-specific aliases for the registers. */
6236 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6237 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6238 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6239 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6241 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6242 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6243 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6245 /* Add some other standard aliases. */
6246 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6247 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6248 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6250 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6251 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6252 value_of_mips_user_reg
,
6253 &mips_numeric_register_aliases
[i
].regnum
);
6259 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6261 struct gdbarch_info info
;
6263 /* Force the architecture to update, and (if it's a MIPS architecture)
6264 mips_gdbarch_init will take care of the rest. */
6265 gdbarch_info_init (&info
);
6266 gdbarch_update_p (info
);
6269 /* Print out which MIPS ABI is in use. */
6272 show_mips_abi (struct ui_file
*file
,
6274 struct cmd_list_element
*ignored_cmd
,
6275 const char *ignored_value
)
6277 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6280 "The MIPS ABI is unknown because the current architecture "
6284 enum mips_abi global_abi
= global_mips_abi ();
6285 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6286 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6288 if (global_abi
== MIPS_ABI_UNKNOWN
)
6291 "The MIPS ABI is set automatically (currently \"%s\").\n",
6293 else if (global_abi
== actual_abi
)
6296 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6300 /* Probably shouldn't happen... */
6303 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6304 actual_abi_str
, mips_abi_strings
[global_abi
]);
6310 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6312 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6316 int ef_mips_32bitmode
;
6317 /* Determine the ISA. */
6318 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6336 /* Determine the size of a pointer. */
6337 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6338 fprintf_unfiltered (file
,
6339 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6341 fprintf_unfiltered (file
,
6342 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6344 fprintf_unfiltered (file
,
6345 "mips_dump_tdep: ef_mips_arch = %d\n",
6347 fprintf_unfiltered (file
,
6348 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6349 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6350 fprintf_unfiltered (file
,
6351 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6352 mips_mask_address_p (tdep
),
6353 tdep
->default_mask_address_p
);
6355 fprintf_unfiltered (file
,
6356 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6357 MIPS_DEFAULT_FPU_TYPE
,
6358 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6359 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6360 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6362 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6363 MIPS_EABI (gdbarch
));
6364 fprintf_unfiltered (file
,
6365 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6366 MIPS_FPU_TYPE (gdbarch
),
6367 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6368 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6369 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6373 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6376 _initialize_mips_tdep (void)
6378 static struct cmd_list_element
*mipsfpulist
= NULL
;
6379 struct cmd_list_element
*c
;
6381 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6382 if (MIPS_ABI_LAST
+ 1
6383 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6384 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6386 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6388 mips_pdr_data
= register_objfile_data ();
6390 /* Create feature sets with the appropriate properties. The values
6391 are not important. */
6392 mips_tdesc_gp32
= allocate_target_description ();
6393 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6395 mips_tdesc_gp64
= allocate_target_description ();
6396 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6398 /* Add root prefix command for all "set mips"/"show mips" commands */
6399 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6400 _("Various MIPS specific commands."),
6401 &setmipscmdlist
, "set mips ", 0, &setlist
);
6403 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6404 _("Various MIPS specific commands."),
6405 &showmipscmdlist
, "show mips ", 0, &showlist
);
6407 /* Allow the user to override the ABI. */
6408 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6409 &mips_abi_string
, _("\
6410 Set the MIPS ABI used by this program."), _("\
6411 Show the MIPS ABI used by this program."), _("\
6412 This option can be set to one of:\n\
6413 auto - the default ABI associated with the current binary\n\
6422 &setmipscmdlist
, &showmipscmdlist
);
6424 /* Let the user turn off floating point and set the fence post for
6425 heuristic_proc_start. */
6427 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6428 _("Set use of MIPS floating-point coprocessor."),
6429 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6430 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6431 _("Select single-precision MIPS floating-point coprocessor."),
6433 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6434 _("Select double-precision MIPS floating-point coprocessor."),
6436 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6437 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6438 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6439 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6440 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6441 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6442 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6443 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6444 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6445 _("Select MIPS floating-point coprocessor automatically."),
6447 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6448 _("Show current use of MIPS floating-point coprocessor target."),
6451 /* We really would like to have both "0" and "unlimited" work, but
6452 command.c doesn't deal with that. So make it a var_zinteger
6453 because the user can always use "999999" or some such for unlimited. */
6454 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6455 &heuristic_fence_post
, _("\
6456 Set the distance searched for the start of a function."), _("\
6457 Show the distance searched for the start of a function."), _("\
6458 If you are debugging a stripped executable, GDB needs to search through the\n\
6459 program for the start of a function. This command sets the distance of the\n\
6460 search. The only need to set it is when debugging a stripped executable."),
6461 reinit_frame_cache_sfunc
,
6462 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
6463 &setlist
, &showlist
);
6465 /* Allow the user to control whether the upper bits of 64-bit
6466 addresses should be zeroed. */
6467 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6468 &mask_address_var
, _("\
6469 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6470 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6471 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
6472 allow GDB to determine the correct value."),
6473 NULL
, show_mask_address
,
6474 &setmipscmdlist
, &showmipscmdlist
);
6476 /* Allow the user to control the size of 32 bit registers within the
6477 raw remote packet. */
6478 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6479 &mips64_transfers_32bit_regs_p
, _("\
6480 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6482 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6484 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6485 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6486 64 bits for others. Use \"off\" to disable compatibility mode"),
6487 set_mips64_transfers_32bit_regs
,
6488 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6489 &setlist
, &showlist
);
6491 /* Debug this files internals. */
6492 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6494 Set mips debugging."), _("\
6495 Show mips debugging."), _("\
6496 When non-zero, mips specific debugging is enabled."),
6498 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
6499 &setdebuglist
, &showdebuglist
);