1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
52 #include "floatformat.h"
54 #include "target-descriptions.h"
55 #include "dwarf2-frame.h"
56 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
67 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
68 static int mips16_instruction_has_delay_slot (unsigned short inst
,
71 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
73 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
75 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
76 CORE_ADDR addr
, int mustbe32
);
78 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
79 struct frame_info
*, const char *);
81 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
82 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
83 #define ST0_FR (1 << 26)
85 /* The sizes of floating point registers. */
89 MIPS_FPU_SINGLE_REGSIZE
= 4,
90 MIPS_FPU_DOUBLE_REGSIZE
= 8
99 static const char *mips_abi_string
;
101 static const char *const mips_abi_strings
[] = {
112 /* Enum describing the different kinds of breakpoints. */
114 enum mips_breakpoint_kind
116 /* 16-bit MIPS16 mode breakpoint. */
117 MIPS_BP_KIND_MIPS16
= 2,
119 /* 16-bit microMIPS mode breakpoint. */
120 MIPS_BP_KIND_MICROMIPS16
= 3,
122 /* 32-bit standard MIPS mode breakpoint. */
123 MIPS_BP_KIND_MIPS32
= 4,
125 /* 32-bit microMIPS mode breakpoint. */
126 MIPS_BP_KIND_MICROMIPS32
= 5,
129 /* For backwards compatibility we default to MIPS16. This flag is
130 overridden as soon as unambiguous ELF file flags tell us the
131 compressed ISA encoding used. */
132 static const char mips_compression_mips16
[] = "mips16";
133 static const char mips_compression_micromips
[] = "micromips";
134 static const char *const mips_compression_strings
[] =
136 mips_compression_mips16
,
137 mips_compression_micromips
,
141 static const char *mips_compression_string
= mips_compression_mips16
;
143 /* The standard register names, and all the valid aliases for them. */
144 struct register_alias
150 /* Aliases for o32 and most other ABIs. */
151 const struct register_alias mips_o32_aliases
[] = {
158 /* Aliases for n32 and n64. */
159 const struct register_alias mips_n32_n64_aliases
[] = {
166 /* Aliases for ABI-independent registers. */
167 const struct register_alias mips_register_aliases
[] = {
168 /* The architecture manuals specify these ABI-independent names for
170 #define R(n) { "r" #n, n }
171 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
172 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
173 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
174 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
177 /* k0 and k1 are sometimes called these instead (for "kernel
182 /* This is the traditional GDB name for the CP0 status register. */
183 { "sr", MIPS_PS_REGNUM
},
185 /* This is the traditional GDB name for the CP0 BadVAddr register. */
186 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
188 /* This is the traditional GDB name for the FCSR. */
189 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
192 const struct register_alias mips_numeric_register_aliases
[] = {
193 #define R(n) { #n, n }
194 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
195 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
196 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
197 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
201 #ifndef MIPS_DEFAULT_FPU_TYPE
202 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
204 static int mips_fpu_type_auto
= 1;
205 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
207 static unsigned int mips_debug
= 0;
209 /* Properties (for struct target_desc) describing the g/G packet
211 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
212 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
214 struct target_desc
*mips_tdesc_gp32
;
215 struct target_desc
*mips_tdesc_gp64
;
217 const struct mips_regnum
*
218 mips_regnum (struct gdbarch
*gdbarch
)
220 return gdbarch_tdep (gdbarch
)->regnum
;
224 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
226 return mips_regnum (gdbarch
)->fp0
+ 12;
229 /* Return 1 if REGNUM refers to a floating-point general register, raw
230 or cooked. Otherwise return 0. */
233 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
235 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
237 return (rawnum
>= mips_regnum (gdbarch
)->fp0
238 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
241 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
243 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
245 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
246 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
248 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
249 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
251 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
253 /* Return the MIPS ABI associated with GDBARCH. */
255 mips_abi (struct gdbarch
*gdbarch
)
257 return gdbarch_tdep (gdbarch
)->mips_abi
;
261 mips_isa_regsize (struct gdbarch
*gdbarch
)
263 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
265 /* If we know how big the registers are, use that size. */
266 if (tdep
->register_size_valid_p
)
267 return tdep
->register_size
;
269 /* Fall back to the previous behavior. */
270 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
271 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
274 /* Return the currently configured (or set) saved register size. */
277 mips_abi_regsize (struct gdbarch
*gdbarch
)
279 switch (mips_abi (gdbarch
))
281 case MIPS_ABI_EABI32
:
287 case MIPS_ABI_EABI64
:
289 case MIPS_ABI_UNKNOWN
:
292 internal_error (__FILE__
, __LINE__
, _("bad switch"));
296 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
297 are some functions to handle addresses associated with compressed
298 code including but not limited to testing, setting, or clearing
299 bit 0 of such addresses. */
301 /* Return one iff compressed code is the MIPS16 instruction set. */
304 is_mips16_isa (struct gdbarch
*gdbarch
)
306 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
309 /* Return one iff compressed code is the microMIPS instruction set. */
312 is_micromips_isa (struct gdbarch
*gdbarch
)
314 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
317 /* Return one iff ADDR denotes compressed code. */
320 is_compact_addr (CORE_ADDR addr
)
325 /* Return one iff ADDR denotes standard ISA code. */
328 is_mips_addr (CORE_ADDR addr
)
330 return !is_compact_addr (addr
);
333 /* Return one iff ADDR denotes MIPS16 code. */
336 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
338 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
341 /* Return one iff ADDR denotes microMIPS code. */
344 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
346 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
349 /* Strip the ISA (compression) bit off from ADDR. */
352 unmake_compact_addr (CORE_ADDR addr
)
354 return ((addr
) & ~(CORE_ADDR
) 1);
357 /* Add the ISA (compression) bit to ADDR. */
360 make_compact_addr (CORE_ADDR addr
)
362 return ((addr
) | (CORE_ADDR
) 1);
365 /* Extern version of unmake_compact_addr; we use a separate function
366 so that unmake_compact_addr can be inlined throughout this file. */
369 mips_unmake_compact_addr (CORE_ADDR addr
)
371 return unmake_compact_addr (addr
);
374 /* Functions for setting and testing a bit in a minimal symbol that
375 marks it as MIPS16 or microMIPS function. The MSB of the minimal
376 symbol's "info" field is used for this purpose.
378 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
379 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
380 one of the "special" bits in a minimal symbol to mark it accordingly.
381 The test checks an ELF-private flag that is valid for true function
382 symbols only; for synthetic symbols such as for PLT stubs that have
383 no ELF-private part at all the MIPS BFD backend arranges for this
384 information to be carried in the asymbol's udata field instead.
386 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
387 in a minimal symbol. */
390 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
392 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
393 unsigned char st_other
;
395 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
396 st_other
= elfsym
->internal_elf_sym
.st_other
;
397 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
398 st_other
= sym
->udata
.i
;
402 if (ELF_ST_IS_MICROMIPS (st_other
))
404 MSYMBOL_TARGET_FLAG_MICROMIPS (msym
) = 1;
405 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
407 else if (ELF_ST_IS_MIPS16 (st_other
))
409 MSYMBOL_TARGET_FLAG_MIPS16 (msym
) = 1;
410 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
414 /* Return one iff MSYM refers to standard ISA code. */
417 msymbol_is_mips (struct minimal_symbol
*msym
)
419 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
420 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
423 /* Return one iff MSYM refers to MIPS16 code. */
426 msymbol_is_mips16 (struct minimal_symbol
*msym
)
428 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
431 /* Return one iff MSYM refers to microMIPS code. */
434 msymbol_is_micromips (struct minimal_symbol
*msym
)
436 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
439 /* Set the ISA bit in the main symbol too, complementing the corresponding
440 minimal symbol setting and reflecting the run-time value of the symbol.
441 The need for comes from the ISA bit having been cleared as code in
442 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
443 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
444 of symbols referring to compressed code different in GDB to the values
445 used by actual code. That in turn makes them evaluate incorrectly in
446 expressions, producing results different to what the same expressions
447 yield when compiled into the program being debugged. */
450 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
452 if (SYMBOL_CLASS (sym
) == LOC_BLOCK
)
454 /* We are in symbol reading so it is OK to cast away constness. */
455 struct block
*block
= (struct block
*) SYMBOL_BLOCK_VALUE (sym
);
456 CORE_ADDR compact_block_start
;
457 struct bound_minimal_symbol msym
;
459 compact_block_start
= BLOCK_START (block
) | 1;
460 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
461 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
463 BLOCK_START (block
) = compact_block_start
;
468 /* XFER a value from the big/little/left end of the register.
469 Depending on the size of the value it might occupy the entire
470 register or just part of it. Make an allowance for this, aligning
471 things accordingly. */
474 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
475 int reg_num
, int length
,
476 enum bfd_endian endian
, gdb_byte
*in
,
477 const gdb_byte
*out
, int buf_offset
)
481 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
482 /* Need to transfer the left or right part of the register, based on
483 the targets byte order. */
487 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
489 case BFD_ENDIAN_LITTLE
:
492 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
496 internal_error (__FILE__
, __LINE__
, _("bad switch"));
499 fprintf_unfiltered (gdb_stderr
,
500 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
501 reg_num
, reg_offset
, buf_offset
, length
);
502 if (mips_debug
&& out
!= NULL
)
505 fprintf_unfiltered (gdb_stdlog
, "out ");
506 for (i
= 0; i
< length
; i
++)
507 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
510 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
513 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
515 if (mips_debug
&& in
!= NULL
)
518 fprintf_unfiltered (gdb_stdlog
, "in ");
519 for (i
= 0; i
< length
; i
++)
520 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
523 fprintf_unfiltered (gdb_stdlog
, "\n");
526 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
527 compatiblity mode. A return value of 1 means that we have
528 physical 64-bit registers, but should treat them as 32-bit registers. */
531 mips2_fp_compat (struct frame_info
*frame
)
533 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
534 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
536 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
540 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
541 in all the places we deal with FP registers. PR gdb/413. */
542 /* Otherwise check the FR bit in the status register - it controls
543 the FP compatiblity mode. If it is clear we are in compatibility
545 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
552 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
554 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
556 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
558 /* The list of available "set mips " and "show mips " commands. */
560 static struct cmd_list_element
*setmipscmdlist
= NULL
;
561 static struct cmd_list_element
*showmipscmdlist
= NULL
;
563 /* Integer registers 0 thru 31 are handled explicitly by
564 mips_register_name(). Processor specific registers 32 and above
565 are listed in the following tables. */
568 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
572 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
573 "sr", "lo", "hi", "bad", "cause", "pc",
574 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
575 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
576 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
577 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
581 /* Names of tx39 registers. */
583 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
584 "sr", "lo", "hi", "bad", "cause", "pc",
585 "", "", "", "", "", "", "", "",
586 "", "", "", "", "", "", "", "",
587 "", "", "", "", "", "", "", "",
588 "", "", "", "", "", "", "", "",
590 "", "", "", "", "", "", "", "",
591 "", "", "config", "cache", "debug", "depc", "epc",
594 /* Names of registers with Linux kernels. */
595 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
596 "sr", "lo", "hi", "bad", "cause", "pc",
597 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
598 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
599 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
600 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
605 /* Return the name of the register corresponding to REGNO. */
607 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
609 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
610 /* GPR names for all ABIs other than n32/n64. */
611 static const char *mips_gpr_names
[] = {
612 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
613 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
614 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
615 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
618 /* GPR names for n32 and n64 ABIs. */
619 static const char *mips_n32_n64_gpr_names
[] = {
620 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
621 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
622 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
623 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
626 enum mips_abi abi
= mips_abi (gdbarch
);
628 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
629 but then don't make the raw register names visible. This (upper)
630 range of user visible register numbers are the pseudo-registers.
632 This approach was adopted accommodate the following scenario:
633 It is possible to debug a 64-bit device using a 32-bit
634 programming model. In such instances, the raw registers are
635 configured to be 64-bits wide, while the pseudo registers are
636 configured to be 32-bits wide. The registers that the user
637 sees - the pseudo registers - match the users expectations
638 given the programming model being used. */
639 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
640 if (regno
< gdbarch_num_regs (gdbarch
))
643 /* The MIPS integer registers are always mapped from 0 to 31. The
644 names of the registers (which reflects the conventions regarding
645 register use) vary depending on the ABI. */
646 if (0 <= rawnum
&& rawnum
< 32)
648 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
649 return mips_n32_n64_gpr_names
[rawnum
];
651 return mips_gpr_names
[rawnum
];
653 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
654 return tdesc_register_name (gdbarch
, rawnum
);
655 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
657 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
658 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
659 return tdep
->mips_processor_reg_names
[rawnum
- 32];
663 internal_error (__FILE__
, __LINE__
,
664 _("mips_register_name: bad register number %d"), rawnum
);
667 /* Return the groups that a MIPS register can be categorised into. */
670 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
671 struct reggroup
*reggroup
)
676 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
677 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
678 if (reggroup
== all_reggroup
)
680 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
681 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
682 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
683 (gdbarch), as not all architectures are multi-arch. */
684 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
685 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
686 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
688 if (reggroup
== float_reggroup
)
689 return float_p
&& pseudo
;
690 if (reggroup
== vector_reggroup
)
691 return vector_p
&& pseudo
;
692 if (reggroup
== general_reggroup
)
693 return (!vector_p
&& !float_p
) && pseudo
;
694 /* Save the pseudo registers. Need to make certain that any code
695 extracting register values from a saved register cache also uses
697 if (reggroup
== save_reggroup
)
698 return raw_p
&& pseudo
;
699 /* Restore the same pseudo register. */
700 if (reggroup
== restore_reggroup
)
701 return raw_p
&& pseudo
;
705 /* Return the groups that a MIPS register can be categorised into.
706 This version is only used if we have a target description which
707 describes real registers (and their groups). */
710 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
711 struct reggroup
*reggroup
)
713 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
714 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
717 /* Only save, restore, and display the pseudo registers. Need to
718 make certain that any code extracting register values from a
719 saved register cache also uses pseudo registers.
721 Note: saving and restoring the pseudo registers is slightly
722 strange; if we have 64 bits, we should save and restore all
723 64 bits. But this is hard and has little benefit. */
727 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
731 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
734 /* Map the symbol table registers which live in the range [1 *
735 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
736 registers. Take care of alignment and size problems. */
738 static enum register_status
739 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
740 int cookednum
, gdb_byte
*buf
)
742 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
743 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
744 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
745 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
746 return regcache_raw_read (regcache
, rawnum
, buf
);
747 else if (register_size (gdbarch
, rawnum
) >
748 register_size (gdbarch
, cookednum
))
750 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
751 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
754 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
756 enum register_status status
;
758 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
759 if (status
== REG_VALID
)
760 store_signed_integer (buf
, 4, byte_order
, regval
);
765 internal_error (__FILE__
, __LINE__
, _("bad register size"));
769 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
770 struct regcache
*regcache
, int cookednum
,
773 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
774 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
775 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
776 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
777 regcache_raw_write (regcache
, rawnum
, buf
);
778 else if (register_size (gdbarch
, rawnum
) >
779 register_size (gdbarch
, cookednum
))
781 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
782 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
785 /* Sign extend the shortened version of the register prior
786 to placing it in the raw register. This is required for
787 some mips64 parts in order to avoid unpredictable behavior. */
788 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
789 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
790 regcache_raw_write_signed (regcache
, rawnum
, regval
);
794 internal_error (__FILE__
, __LINE__
, _("bad register size"));
798 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
799 struct agent_expr
*ax
, int reg
)
801 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
802 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
803 && reg
< 2 * gdbarch_num_regs (gdbarch
));
805 ax_reg_mask (ax
, rawnum
);
811 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
812 struct agent_expr
*ax
, int reg
)
814 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
815 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
816 && reg
< 2 * gdbarch_num_regs (gdbarch
));
817 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
821 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
823 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
824 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
827 ax_simple (ax
, aop_lsh
);
830 ax_simple (ax
, aop_rsh_signed
);
834 internal_error (__FILE__
, __LINE__
, _("bad register size"));
839 /* Table to translate 3-bit register field to actual register number. */
840 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
842 /* Heuristic_proc_start may hunt through the text section for a long
843 time across a 2400 baud serial line. Allows the user to limit this
846 static int heuristic_fence_post
= 0;
848 /* Number of bytes of storage in the actual machine representation for
849 register N. NOTE: This defines the pseudo register type so need to
850 rebuild the architecture vector. */
852 static int mips64_transfers_32bit_regs_p
= 0;
855 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
856 struct cmd_list_element
*c
)
858 struct gdbarch_info info
;
859 gdbarch_info_init (&info
);
860 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
861 instead of relying on globals. Doing that would let generic code
862 handle the search for this specific architecture. */
863 if (!gdbarch_update_p (info
))
865 mips64_transfers_32bit_regs_p
= 0;
866 error (_("32-bit compatibility mode not supported"));
870 /* Convert to/from a register and the corresponding memory value. */
872 /* This predicate tests for the case of an 8 byte floating point
873 value that is being transferred to or from a pair of floating point
874 registers each of which are (or are considered to be) only 4 bytes
877 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
880 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
881 && register_size (gdbarch
, regnum
) == 4
882 && mips_float_register_p (gdbarch
, regnum
)
883 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
886 /* This predicate tests for the case of a value of less than 8
887 bytes in width that is being transfered to or from an 8 byte
888 general purpose register. */
890 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
893 int num_regs
= gdbarch_num_regs (gdbarch
);
895 return (register_size (gdbarch
, regnum
) == 8
896 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
897 && TYPE_LENGTH (type
) < 8);
901 mips_convert_register_p (struct gdbarch
*gdbarch
,
902 int regnum
, struct type
*type
)
904 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
905 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
909 mips_register_to_value (struct frame_info
*frame
, int regnum
,
910 struct type
*type
, gdb_byte
*to
,
911 int *optimizedp
, int *unavailablep
)
913 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
915 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
917 get_frame_register (frame
, regnum
+ 0, to
+ 4);
918 get_frame_register (frame
, regnum
+ 1, to
+ 0);
920 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
921 optimizedp
, unavailablep
))
924 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
925 optimizedp
, unavailablep
))
927 *optimizedp
= *unavailablep
= 0;
930 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
932 int len
= TYPE_LENGTH (type
);
935 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
936 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
937 optimizedp
, unavailablep
))
940 *optimizedp
= *unavailablep
= 0;
945 internal_error (__FILE__
, __LINE__
,
946 _("mips_register_to_value: unrecognized case"));
951 mips_value_to_register (struct frame_info
*frame
, int regnum
,
952 struct type
*type
, const gdb_byte
*from
)
954 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
956 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
958 put_frame_register (frame
, regnum
+ 0, from
+ 4);
959 put_frame_register (frame
, regnum
+ 1, from
+ 0);
961 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
964 int len
= TYPE_LENGTH (type
);
966 /* Sign extend values, irrespective of type, that are stored to
967 a 64-bit general purpose register. (32-bit unsigned values
968 are stored as signed quantities within a 64-bit register.
969 When performing an operation, in compiled code, that combines
970 a 32-bit unsigned value with a signed 64-bit value, a type
971 conversion is first performed that zeroes out the high 32 bits.) */
972 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
975 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
977 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
978 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
979 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
983 if (from
[len
-1] & 0x80)
984 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
986 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
987 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
988 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
993 internal_error (__FILE__
, __LINE__
,
994 _("mips_value_to_register: unrecognized case"));
998 /* Return the GDB type object for the "standard" data type of data in
1001 static struct type
*
1002 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1004 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1005 if (mips_float_register_p (gdbarch
, regnum
))
1007 /* The floating-point registers raw, or cooked, always match
1008 mips_isa_regsize(), and also map 1:1, byte for byte. */
1009 if (mips_isa_regsize (gdbarch
) == 4)
1010 return builtin_type (gdbarch
)->builtin_float
;
1012 return builtin_type (gdbarch
)->builtin_double
;
1014 else if (regnum
< gdbarch_num_regs (gdbarch
))
1016 /* The raw or ISA registers. These are all sized according to
1018 if (mips_isa_regsize (gdbarch
) == 4)
1019 return builtin_type (gdbarch
)->builtin_int32
;
1021 return builtin_type (gdbarch
)->builtin_int64
;
1025 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1027 /* The cooked or ABI registers. These are sized according to
1028 the ABI (with a few complications). */
1029 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1030 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1031 return builtin_type (gdbarch
)->builtin_int32
;
1032 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1033 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1034 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1035 /* The pseudo/cooked view of the embedded registers is always
1036 32-bit. The raw view is handled below. */
1037 return builtin_type (gdbarch
)->builtin_int32
;
1038 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
1039 /* The target, while possibly using a 64-bit register buffer,
1040 is only transfering 32-bits of each integer register.
1041 Reflect this in the cooked/pseudo (ABI) register value. */
1042 return builtin_type (gdbarch
)->builtin_int32
;
1043 else if (mips_abi_regsize (gdbarch
) == 4)
1044 /* The ABI is restricted to 32-bit registers (the ISA could be
1046 return builtin_type (gdbarch
)->builtin_int32
;
1049 return builtin_type (gdbarch
)->builtin_int64
;
1053 /* Return the GDB type for the pseudo register REGNUM, which is the
1054 ABI-level view. This function is only called if there is a target
1055 description which includes registers, so we know precisely the
1056 types of hardware registers. */
1058 static struct type
*
1059 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1061 const int num_regs
= gdbarch_num_regs (gdbarch
);
1062 int rawnum
= regnum
% num_regs
;
1063 struct type
*rawtype
;
1065 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1067 /* Absent registers are still absent. */
1068 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1069 if (TYPE_LENGTH (rawtype
) == 0)
1072 /* Present the floating point registers however the hardware did;
1073 do not try to convert between FPU layouts. */
1074 if (mips_float_register_p (gdbarch
, rawnum
))
1077 /* Floating-point control registers are always 32-bit even though for
1078 backwards compatibility reasons 64-bit targets will transfer them
1079 as 64-bit quantities even if using XML descriptions. */
1080 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1081 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1082 return builtin_type (gdbarch
)->builtin_int32
;
1084 /* Use pointer types for registers if we can. For n32 we can not,
1085 since we do not have a 64-bit pointer type. */
1086 if (mips_abi_regsize (gdbarch
)
1087 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1089 if (rawnum
== MIPS_SP_REGNUM
1090 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1091 return builtin_type (gdbarch
)->builtin_data_ptr
;
1092 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1093 return builtin_type (gdbarch
)->builtin_func_ptr
;
1096 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1097 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1098 || rawnum
== mips_regnum (gdbarch
)->lo
1099 || rawnum
== mips_regnum (gdbarch
)->hi
1100 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1101 || rawnum
== mips_regnum (gdbarch
)->cause
1102 || rawnum
== mips_regnum (gdbarch
)->pc
1103 || (mips_regnum (gdbarch
)->dspacc
!= -1
1104 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1105 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1106 return builtin_type (gdbarch
)->builtin_int32
;
1108 /* The pseudo/cooked view of embedded registers is always
1109 32-bit, even if the target transfers 64-bit values for them.
1110 New targets relying on XML descriptions should only transfer
1111 the necessary 32 bits, but older versions of GDB expected 64,
1112 so allow the target to provide 64 bits without interfering
1113 with the displayed type. */
1114 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1115 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1116 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1117 return builtin_type (gdbarch
)->builtin_int32
;
1119 /* For all other registers, pass through the hardware type. */
1123 /* Should the upper word of 64-bit addresses be zeroed? */
1124 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1127 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1129 switch (mask_address_var
)
1131 case AUTO_BOOLEAN_TRUE
:
1133 case AUTO_BOOLEAN_FALSE
:
1136 case AUTO_BOOLEAN_AUTO
:
1137 return tdep
->default_mask_address_p
;
1139 internal_error (__FILE__
, __LINE__
,
1140 _("mips_mask_address_p: bad switch"));
1146 show_mask_address (struct ui_file
*file
, int from_tty
,
1147 struct cmd_list_element
*c
, const char *value
)
1149 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1151 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1152 switch (mask_address_var
)
1154 case AUTO_BOOLEAN_TRUE
:
1155 printf_filtered ("The 32 bit mips address mask is enabled\n");
1157 case AUTO_BOOLEAN_FALSE
:
1158 printf_filtered ("The 32 bit mips address mask is disabled\n");
1160 case AUTO_BOOLEAN_AUTO
:
1162 ("The 32 bit address mask is set automatically. Currently %s\n",
1163 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1166 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1171 /* Tell if the program counter value in MEMADDR is in a standard ISA
1175 mips_pc_is_mips (CORE_ADDR memaddr
)
1177 struct bound_minimal_symbol sym
;
1179 /* Flags indicating that this is a MIPS16 or microMIPS function is
1180 stored by elfread.c in the high bit of the info field. Use this
1181 to decide if the function is standard MIPS. Otherwise if bit 0
1182 of the address is clear, then this is a standard MIPS function. */
1183 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1185 return msymbol_is_mips (sym
.minsym
);
1187 return is_mips_addr (memaddr
);
1190 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1193 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1195 struct bound_minimal_symbol sym
;
1197 /* A flag indicating that this is a MIPS16 function is stored by
1198 elfread.c in the high bit of the info field. Use this to decide
1199 if the function is MIPS16. Otherwise if bit 0 of the address is
1200 set, then ELF file flags will tell if this is a MIPS16 function. */
1201 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1203 return msymbol_is_mips16 (sym
.minsym
);
1205 return is_mips16_addr (gdbarch
, memaddr
);
1208 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1211 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1213 struct bound_minimal_symbol sym
;
1215 /* A flag indicating that this is a microMIPS function is stored by
1216 elfread.c in the high bit of the info field. Use this to decide
1217 if the function is microMIPS. Otherwise if bit 0 of the address
1218 is set, then ELF file flags will tell if this is a microMIPS
1220 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1222 return msymbol_is_micromips (sym
.minsym
);
1224 return is_micromips_addr (gdbarch
, memaddr
);
1227 /* Tell the ISA type of the function the program counter value in MEMADDR
1230 static enum mips_isa
1231 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1233 struct bound_minimal_symbol sym
;
1235 /* A flag indicating that this is a MIPS16 or a microMIPS function
1236 is stored by elfread.c in the high bit of the info field. Use
1237 this to decide if the function is MIPS16 or microMIPS or normal
1238 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1239 flags will tell if this is a MIPS16 or a microMIPS function. */
1240 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1243 if (msymbol_is_micromips (sym
.minsym
))
1244 return ISA_MICROMIPS
;
1245 else if (msymbol_is_mips16 (sym
.minsym
))
1252 if (is_mips_addr (memaddr
))
1254 else if (is_micromips_addr (gdbarch
, memaddr
))
1255 return ISA_MICROMIPS
;
1261 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1262 The need for comes from the ISA bit having been cleared, making
1263 addresses in FDE, range records, etc. referring to compressed code
1264 different to those in line information, the symbol table and finally
1265 the PC register. That in turn confuses many operations. */
1268 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1270 pc
= unmake_compact_addr (pc
);
1271 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1274 /* Recalculate the line record requested so that the resulting PC has
1275 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1276 this adjustment comes from some records associated with compressed
1277 code having the ISA bit cleared, most notably at function prologue
1278 ends. The ISA bit is in this context retrieved from the minimal
1279 symbol covering the address requested, which in turn has been
1280 constructed from the binary's symbol table rather than DWARF-2
1281 information. The correct setting of the ISA bit is required for
1282 breakpoint addresses to correctly match against the stop PC.
1284 As line entries can specify relative address adjustments we need to
1285 keep track of the absolute value of the last line address recorded
1286 in line information, so that we can calculate the actual address to
1287 apply the ISA bit adjustment to. We use PC for this tracking and
1288 keep the original address there.
1290 As such relative address adjustments can be odd within compressed
1291 code we need to keep track of the last line address with the ISA
1292 bit adjustment applied too, as the original address may or may not
1293 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1294 the adjusted address there.
1296 For relative address adjustments we then use these variables to
1297 calculate the address intended by line information, which will be
1298 PC-relative, and return an updated adjustment carrying ISA bit
1299 information, which will be ADJ_PC-relative. For absolute address
1300 adjustments we just return the same address that we store in ADJ_PC
1303 As the first line entry can be relative to an implied address value
1304 of 0 we need to have the initial address set up that we store in PC
1305 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1306 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1309 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1311 static CORE_ADDR adj_pc
;
1312 static CORE_ADDR pc
;
1315 pc
= rel
? pc
+ addr
: addr
;
1316 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1317 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1322 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1324 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1325 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1326 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1327 static const char mips_str_call_stub
[] = "__call_stub_";
1328 static const char mips_str_fn_stub
[] = "__fn_stub_";
1330 /* This is used as a PIC thunk prefix. */
1332 static const char mips_str_pic
[] = ".pic.";
1334 /* Return non-zero if the PC is inside a call thunk (aka stub or
1335 trampoline) that should be treated as a temporary frame. */
1338 mips_in_frame_stub (CORE_ADDR pc
)
1340 CORE_ADDR start_addr
;
1343 /* Find the starting address of the function containing the PC. */
1344 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1347 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1348 if (startswith (name
, mips_str_mips16_call_stub
))
1350 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1351 if (startswith (name
, mips_str_call_stub
))
1353 /* If the PC is in __fn_stub_*, this is a call stub. */
1354 if (startswith (name
, mips_str_fn_stub
))
1357 return 0; /* Not a stub. */
1360 /* MIPS believes that the PC has a sign extended value. Perhaps the
1361 all registers should be sign extended for simplicity? */
1364 mips_read_pc (struct regcache
*regcache
)
1366 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1369 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1374 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1378 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1379 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1380 intermediate frames. In this case we can get the caller's address
1381 from $ra, or if $ra contains an address within a thunk as well, then
1382 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1383 and thus the caller's address is in $s2. */
1384 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1386 pc
= frame_unwind_register_signed
1387 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1388 if (mips_in_frame_stub (pc
))
1389 pc
= frame_unwind_register_signed
1390 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1396 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1398 return frame_unwind_register_signed
1399 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1402 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1403 dummy frame. The frame ID's base needs to match the TOS value
1404 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1407 static struct frame_id
1408 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1410 return frame_id_build
1411 (get_frame_register_signed (this_frame
,
1412 gdbarch_num_regs (gdbarch
)
1414 get_frame_pc (this_frame
));
1417 /* Implement the "write_pc" gdbarch method. */
1420 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1422 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1424 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1427 /* Fetch and return instruction from the specified location. Handle
1428 MIPS16/microMIPS as appropriate. */
1431 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1432 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1434 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1435 gdb_byte buf
[MIPS_INSN32_SIZE
];
1443 instlen
= MIPS_INSN16_SIZE
;
1444 addr
= unmake_compact_addr (addr
);
1447 instlen
= MIPS_INSN32_SIZE
;
1450 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1453 err
= target_read_memory (addr
, buf
, instlen
);
1459 memory_error (TARGET_XFER_E_IO
, addr
);
1462 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1465 /* These are the fields of 32 bit mips instructions. */
1466 #define mips32_op(x) (x >> 26)
1467 #define itype_op(x) (x >> 26)
1468 #define itype_rs(x) ((x >> 21) & 0x1f)
1469 #define itype_rt(x) ((x >> 16) & 0x1f)
1470 #define itype_immediate(x) (x & 0xffff)
1472 #define jtype_op(x) (x >> 26)
1473 #define jtype_target(x) (x & 0x03ffffff)
1475 #define rtype_op(x) (x >> 26)
1476 #define rtype_rs(x) ((x >> 21) & 0x1f)
1477 #define rtype_rt(x) ((x >> 16) & 0x1f)
1478 #define rtype_rd(x) ((x >> 11) & 0x1f)
1479 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1480 #define rtype_funct(x) (x & 0x3f)
1482 /* MicroMIPS instruction fields. */
1483 #define micromips_op(x) ((x) >> 10)
1485 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1486 bit and the size respectively of the field extracted. */
1487 #define b0s4_imm(x) ((x) & 0xf)
1488 #define b0s5_imm(x) ((x) & 0x1f)
1489 #define b0s5_reg(x) ((x) & 0x1f)
1490 #define b0s7_imm(x) ((x) & 0x7f)
1491 #define b0s10_imm(x) ((x) & 0x3ff)
1492 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1493 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1494 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1495 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1496 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1497 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1498 #define b6s4_op(x) (((x) >> 6) & 0xf)
1499 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1501 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1502 respectively of the field extracted. */
1503 #define b0s6_op(x) ((x) & 0x3f)
1504 #define b0s11_op(x) ((x) & 0x7ff)
1505 #define b0s12_imm(x) ((x) & 0xfff)
1506 #define b0s16_imm(x) ((x) & 0xffff)
1507 #define b0s26_imm(x) ((x) & 0x3ffffff)
1508 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1509 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1510 #define b12s4_op(x) (((x) >> 12) & 0xf)
1512 /* Return the size in bytes of the instruction INSN encoded in the ISA
1516 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1521 if ((micromips_op (insn
) & 0x4) == 0x4
1522 || (micromips_op (insn
) & 0x7) == 0x0)
1523 return 2 * MIPS_INSN16_SIZE
;
1525 return MIPS_INSN16_SIZE
;
1527 if ((insn
& 0xf800) == 0xf000)
1528 return 2 * MIPS_INSN16_SIZE
;
1530 return MIPS_INSN16_SIZE
;
1532 return MIPS_INSN32_SIZE
;
1534 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1538 mips32_relative_offset (ULONGEST inst
)
1540 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1543 /* Determine the address of the next instruction executed after the INST
1544 floating condition branch instruction at PC. COUNT specifies the
1545 number of the floating condition bits tested by the branch. */
1548 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1549 ULONGEST inst
, CORE_ADDR pc
, int count
)
1551 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1552 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1553 int tf
= itype_rt (inst
) & 1;
1554 int mask
= (1 << count
) - 1;
1559 /* No way to handle; it'll most likely trap anyway. */
1562 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1563 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1565 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1566 pc
+= mips32_relative_offset (inst
);
1573 /* Return nonzero if the gdbarch is an Octeon series. */
1576 is_octeon (struct gdbarch
*gdbarch
)
1578 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1580 return (info
->mach
== bfd_mach_mips_octeon
1581 || info
->mach
== bfd_mach_mips_octeonp
1582 || info
->mach
== bfd_mach_mips_octeon2
);
1585 /* Return true if the OP represents the Octeon's BBIT instruction. */
1588 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1590 if (!is_octeon (gdbarch
))
1592 /* BBIT0 is encoded as LWC2: 110 010. */
1593 /* BBIT032 is encoded as LDC2: 110 110. */
1594 /* BBIT1 is encoded as SWC2: 111 010. */
1595 /* BBIT132 is encoded as SDC2: 111 110. */
1596 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1602 /* Determine where to set a single step breakpoint while considering
1603 branch prediction. */
1606 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1608 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1611 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1612 op
= itype_op (inst
);
1613 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1617 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1628 goto greater_branch
;
1633 else if (op
== 17 && itype_rs (inst
) == 8)
1634 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1635 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1636 else if (op
== 17 && itype_rs (inst
) == 9
1637 && (itype_rt (inst
) & 2) == 0)
1638 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1639 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1640 else if (op
== 17 && itype_rs (inst
) == 10
1641 && (itype_rt (inst
) & 2) == 0)
1642 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1643 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1646 /* The new PC will be alternate mode. */
1650 reg
= jtype_target (inst
) << 2;
1651 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1652 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1654 else if (is_octeon_bbit_op (op
, gdbarch
))
1658 branch_if
= op
== 58 || op
== 62;
1659 bit
= itype_rt (inst
);
1661 /* Take into account the *32 instructions. */
1662 if (op
== 54 || op
== 62)
1665 if (((regcache_raw_get_signed (regcache
,
1666 itype_rs (inst
)) >> bit
) & 1)
1668 pc
+= mips32_relative_offset (inst
) + 4;
1670 pc
+= 8; /* After the delay slot. */
1674 pc
+= 4; /* Not a branch, next instruction is easy. */
1677 { /* This gets way messy. */
1679 /* Further subdivide into SPECIAL, REGIMM and other. */
1680 switch (op
& 0x07) /* Extract bits 28,27,26. */
1682 case 0: /* SPECIAL */
1683 op
= rtype_funct (inst
);
1688 /* Set PC to that address. */
1689 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1691 case 12: /* SYSCALL */
1693 struct gdbarch_tdep
*tdep
;
1695 tdep
= gdbarch_tdep (gdbarch
);
1696 if (tdep
->syscall_next_pc
!= NULL
)
1697 pc
= tdep
->syscall_next_pc (get_current_frame ());
1706 break; /* end SPECIAL */
1707 case 1: /* REGIMM */
1709 op
= itype_rt (inst
); /* branch condition */
1714 case 16: /* BLTZAL */
1715 case 18: /* BLTZALL */
1717 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1718 pc
+= mips32_relative_offset (inst
) + 4;
1720 pc
+= 8; /* after the delay slot */
1724 case 17: /* BGEZAL */
1725 case 19: /* BGEZALL */
1726 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1727 pc
+= mips32_relative_offset (inst
) + 4;
1729 pc
+= 8; /* after the delay slot */
1731 case 0x1c: /* BPOSGE32 */
1732 case 0x1e: /* BPOSGE64 */
1734 if (itype_rs (inst
) == 0)
1736 unsigned int pos
= (op
& 2) ? 64 : 32;
1737 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1740 /* No way to handle; it'll most likely trap anyway. */
1743 if ((regcache_raw_get_unsigned (regcache
,
1744 dspctl
) & 0x7f) >= pos
)
1745 pc
+= mips32_relative_offset (inst
);
1750 /* All of the other instructions in the REGIMM category */
1755 break; /* end REGIMM */
1760 reg
= jtype_target (inst
) << 2;
1761 /* Upper four bits get never changed... */
1762 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1765 case 4: /* BEQ, BEQL */
1767 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1768 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1769 pc
+= mips32_relative_offset (inst
) + 4;
1773 case 5: /* BNE, BNEL */
1775 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1776 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1777 pc
+= mips32_relative_offset (inst
) + 4;
1781 case 6: /* BLEZ, BLEZL */
1782 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1783 pc
+= mips32_relative_offset (inst
) + 4;
1789 greater_branch
: /* BGTZ, BGTZL */
1790 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1791 pc
+= mips32_relative_offset (inst
) + 4;
1798 } /* mips32_next_pc */
1800 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1804 micromips_relative_offset7 (ULONGEST insn
)
1806 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1809 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1813 micromips_relative_offset10 (ULONGEST insn
)
1815 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1818 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1822 micromips_relative_offset16 (ULONGEST insn
)
1824 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1827 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1830 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1834 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1835 return mips_insn_size (ISA_MICROMIPS
, insn
);
1838 /* Calculate the address of the next microMIPS instruction to execute
1839 after the INSN coprocessor 1 conditional branch instruction at the
1840 address PC. COUNT denotes the number of coprocessor condition bits
1841 examined by the branch. */
1844 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1845 ULONGEST insn
, CORE_ADDR pc
, int count
)
1847 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1848 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1849 int tf
= b5s5_op (insn
>> 16) & 1;
1850 int mask
= (1 << count
) - 1;
1855 /* No way to handle; it'll most likely trap anyway. */
1858 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1859 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1861 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1862 pc
+= micromips_relative_offset16 (insn
);
1864 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1869 /* Calculate the address of the next microMIPS instruction to execute
1870 after the instruction at the address PC. */
1873 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1875 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1878 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1879 pc
+= MIPS_INSN16_SIZE
;
1880 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1882 /* 32-bit instructions. */
1883 case 2 * MIPS_INSN16_SIZE
:
1885 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1886 pc
+= MIPS_INSN16_SIZE
;
1887 switch (micromips_op (insn
>> 16))
1889 case 0x00: /* POOL32A: bits 000000 */
1890 if (b0s6_op (insn
) == 0x3c
1891 /* POOL32Axf: bits 000000 ... 111100 */
1892 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1893 /* JALR, JALR.HB: 000000 000x111100 111100 */
1894 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1895 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16));
1898 case 0x10: /* POOL32I: bits 010000 */
1899 switch (b5s5_op (insn
>> 16))
1901 case 0x00: /* BLTZ: bits 010000 00000 */
1902 case 0x01: /* BLTZAL: bits 010000 00001 */
1903 case 0x11: /* BLTZALS: bits 010000 10001 */
1904 if (regcache_raw_get_signed (regcache
,
1905 b0s5_reg (insn
>> 16)) < 0)
1906 pc
+= micromips_relative_offset16 (insn
);
1908 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1911 case 0x02: /* BGEZ: bits 010000 00010 */
1912 case 0x03: /* BGEZAL: bits 010000 00011 */
1913 case 0x13: /* BGEZALS: bits 010000 10011 */
1914 if (regcache_raw_get_signed (regcache
,
1915 b0s5_reg (insn
>> 16)) >= 0)
1916 pc
+= micromips_relative_offset16 (insn
);
1918 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1921 case 0x04: /* BLEZ: bits 010000 00100 */
1922 if (regcache_raw_get_signed (regcache
,
1923 b0s5_reg (insn
>> 16)) <= 0)
1924 pc
+= micromips_relative_offset16 (insn
);
1926 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1929 case 0x05: /* BNEZC: bits 010000 00101 */
1930 if (regcache_raw_get_signed (regcache
,
1931 b0s5_reg (insn
>> 16)) != 0)
1932 pc
+= micromips_relative_offset16 (insn
);
1935 case 0x06: /* BGTZ: bits 010000 00110 */
1936 if (regcache_raw_get_signed (regcache
,
1937 b0s5_reg (insn
>> 16)) > 0)
1938 pc
+= micromips_relative_offset16 (insn
);
1940 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1943 case 0x07: /* BEQZC: bits 010000 00111 */
1944 if (regcache_raw_get_signed (regcache
,
1945 b0s5_reg (insn
>> 16)) == 0)
1946 pc
+= micromips_relative_offset16 (insn
);
1949 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1950 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1951 if (((insn
>> 16) & 0x3) == 0x0)
1952 /* BC2F, BC2T: don't know how to handle these. */
1956 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1957 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1959 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1960 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1963 /* No way to handle; it'll most likely trap anyway. */
1966 if ((regcache_raw_get_unsigned (regcache
,
1967 dspctl
) & 0x7f) >= pos
)
1968 pc
+= micromips_relative_offset16 (insn
);
1970 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1974 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1975 /* BC1ANY2F: bits 010000 11100 xxx01 */
1976 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1977 /* BC1ANY2T: bits 010000 11101 xxx01 */
1978 if (((insn
>> 16) & 0x2) == 0x0)
1979 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
1980 ((insn
>> 16) & 0x1) + 1);
1983 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1984 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1985 if (((insn
>> 16) & 0x3) == 0x1)
1986 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
1991 case 0x1d: /* JALS: bits 011101 */
1992 case 0x35: /* J: bits 110101 */
1993 case 0x3d: /* JAL: bits 111101 */
1994 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
1997 case 0x25: /* BEQ: bits 100101 */
1998 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
1999 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2000 pc
+= micromips_relative_offset16 (insn
);
2002 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2005 case 0x2d: /* BNE: bits 101101 */
2006 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2007 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2008 pc
+= micromips_relative_offset16 (insn
);
2010 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2013 case 0x3c: /* JALX: bits 111100 */
2014 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2019 /* 16-bit instructions. */
2020 case MIPS_INSN16_SIZE
:
2021 switch (micromips_op (insn
))
2023 case 0x11: /* POOL16C: bits 010001 */
2024 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2025 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2026 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2027 else if (b5s5_op (insn
) == 0x18)
2028 /* JRADDIUSP: bits 010001 11000 */
2029 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2032 case 0x23: /* BEQZ16: bits 100011 */
2034 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2036 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2037 pc
+= micromips_relative_offset7 (insn
);
2039 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2043 case 0x2b: /* BNEZ16: bits 101011 */
2045 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2047 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2048 pc
+= micromips_relative_offset7 (insn
);
2050 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2054 case 0x33: /* B16: bits 110011 */
2055 pc
+= micromips_relative_offset10 (insn
);
2064 /* Decoding the next place to set a breakpoint is irregular for the
2065 mips 16 variant, but fortunately, there fewer instructions. We have
2066 to cope ith extensions for 16 bit instructions and a pair of actual
2067 32 bit instructions. We dont want to set a single step instruction
2068 on the extend instruction either. */
2070 /* Lots of mips16 instruction formats */
2071 /* Predicting jumps requires itype,ritype,i8type
2072 and their extensions extItype,extritype,extI8type. */
2073 enum mips16_inst_fmts
2075 itype
, /* 0 immediate 5,10 */
2076 ritype
, /* 1 5,3,8 */
2077 rrtype
, /* 2 5,3,3,5 */
2078 rritype
, /* 3 5,3,3,5 */
2079 rrrtype
, /* 4 5,3,3,3,2 */
2080 rriatype
, /* 5 5,3,3,1,4 */
2081 shifttype
, /* 6 5,3,3,3,2 */
2082 i8type
, /* 7 5,3,8 */
2083 i8movtype
, /* 8 5,3,3,5 */
2084 i8mov32rtype
, /* 9 5,3,5,3 */
2085 i64type
, /* 10 5,3,8 */
2086 ri64type
, /* 11 5,3,3,5 */
2087 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2088 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2089 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2090 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2091 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2092 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2093 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2094 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2095 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2096 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2098 /* I am heaping all the fields of the formats into one structure and
2099 then, only the fields which are involved in instruction extension. */
2103 unsigned int regx
; /* Function in i8 type. */
2108 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2109 for the bits which make up the immediate extension. */
2112 extended_offset (unsigned int extension
)
2116 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2118 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2120 value
|= extension
& 0x1f; /* Extract 4:0. */
2125 /* Only call this function if you know that this is an extendable
2126 instruction. It won't malfunction, but why make excess remote memory
2127 references? If the immediate operands get sign extended or something,
2128 do it after the extension is performed. */
2129 /* FIXME: Every one of these cases needs to worry about sign extension
2130 when the offset is to be used in relative addressing. */
2133 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2135 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2138 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2139 target_read_memory (pc
, buf
, 2);
2140 return extract_unsigned_integer (buf
, 2, byte_order
);
2144 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2145 unsigned int extension
,
2147 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2152 switch (insn_format
)
2159 value
= extended_offset ((extension
<< 16) | inst
);
2160 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2164 value
= inst
& 0x7ff;
2165 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2174 { /* A register identifier and an offset. */
2175 /* Most of the fields are the same as I type but the
2176 immediate value is of a different length. */
2180 value
= extended_offset ((extension
<< 16) | inst
);
2181 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2185 value
= inst
& 0xff; /* 8 bits */
2186 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2189 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2195 unsigned long value
;
2196 unsigned int nexthalf
;
2197 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2198 value
= value
<< 16;
2199 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2200 /* Low bit still set. */
2208 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2210 upk
->offset
= offset
;
2216 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2217 and having a signed 16-bit OFFSET. */
2220 add_offset_16 (CORE_ADDR pc
, int offset
)
2222 return pc
+ (offset
<< 1) + 2;
2226 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2227 unsigned int extension
, unsigned int insn
)
2229 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2230 int op
= (insn
>> 11);
2233 case 2: /* Branch */
2235 struct upk_mips16 upk
;
2236 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2237 pc
= add_offset_16 (pc
, upk
.offset
);
2240 case 3: /* JAL , JALX - Watch out, these are 32 bit
2243 struct upk_mips16 upk
;
2244 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2245 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2246 if ((insn
>> 10) & 0x01) /* Exchange mode */
2247 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2254 struct upk_mips16 upk
;
2256 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2257 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2259 pc
= add_offset_16 (pc
, upk
.offset
);
2266 struct upk_mips16 upk
;
2268 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2269 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2271 pc
= add_offset_16 (pc
, upk
.offset
);
2276 case 12: /* I8 Formats btez btnez */
2278 struct upk_mips16 upk
;
2280 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2281 /* upk.regx contains the opcode */
2282 /* Test register is 24 */
2283 reg
= regcache_raw_get_signed (regcache
, 24);
2284 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2285 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2286 pc
= add_offset_16 (pc
, upk
.offset
);
2291 case 29: /* RR Formats JR, JALR, JALR-RA */
2293 struct upk_mips16 upk
;
2294 /* upk.fmt = rrtype; */
2299 upk
.regx
= (insn
>> 8) & 0x07;
2300 upk
.regy
= (insn
>> 5) & 0x07;
2301 if ((upk
.regy
& 1) == 0)
2302 reg
= mips_reg3_to_reg
[upk
.regx
];
2304 reg
= 31; /* Function return instruction. */
2305 pc
= regcache_raw_get_signed (regcache
, reg
);
2312 /* This is an instruction extension. Fetch the real instruction
2313 (which follows the extension) and decode things based on
2317 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2318 fetch_mips_16 (gdbarch
, pc
));
2331 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2333 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2334 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2335 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2338 /* The mips_next_pc function supports single_step when the remote
2339 target monitor or stub is not developed enough to do a single_step.
2340 It works by decoding the current instruction and predicting where a
2341 branch will go. This isn't hard because all the data is available.
2342 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2344 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2346 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2348 if (mips_pc_is_mips16 (gdbarch
, pc
))
2349 return mips16_next_pc (regcache
, pc
);
2350 else if (mips_pc_is_micromips (gdbarch
, pc
))
2351 return micromips_next_pc (regcache
, pc
);
2353 return mips32_next_pc (regcache
, pc
);
2356 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2360 mips16_instruction_is_compact_branch (unsigned short insn
)
2362 switch (insn
& 0xf800)
2365 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2367 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2368 case 0x2800: /* BNEZ */
2369 case 0x2000: /* BEQZ */
2370 case 0x1000: /* B */
2377 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2381 micromips_instruction_is_compact_branch (unsigned short insn
)
2383 switch (micromips_op (insn
))
2385 case 0x11: /* POOL16C: bits 010001 */
2386 return (b5s5_op (insn
) == 0x18
2387 /* JRADDIUSP: bits 010001 11000 */
2388 || b5s5_op (insn
) == 0xd);
2389 /* JRC: bits 010011 01101 */
2390 case 0x10: /* POOL32I: bits 010000 */
2391 return (b5s5_op (insn
) & 0x1d) == 0x5;
2392 /* BEQZC/BNEZC: bits 010000 001x1 */
2398 struct mips_frame_cache
2401 struct trad_frame_saved_reg
*saved_regs
;
2404 /* Set a register's saved stack address in temp_saved_regs. If an
2405 address has already been set for this register, do nothing; this
2406 way we will only recognize the first save of a given register in a
2409 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2410 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2411 Strictly speaking, only the second range is used as it is only second
2412 range (the ABI instead of ISA registers) that comes into play when finding
2413 saved registers in a frame. */
2416 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2417 int regnum
, CORE_ADDR offset
)
2419 if (this_cache
!= NULL
2420 && this_cache
->saved_regs
[regnum
].addr
== -1)
2422 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2424 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2430 /* Fetch the immediate value from a MIPS16 instruction.
2431 If the previous instruction was an EXTEND, use it to extend
2432 the upper bits of the immediate value. This is a helper function
2433 for mips16_scan_prologue. */
2436 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2437 unsigned short inst
, /* current instruction */
2438 int nbits
, /* number of bits in imm field */
2439 int scale
, /* scale factor to be applied to imm */
2440 int is_signed
) /* is the imm field signed? */
2444 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2446 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2447 if (offset
& 0x8000) /* check for negative extend */
2448 offset
= 0 - (0x10000 - (offset
& 0xffff));
2449 return offset
| (inst
& 0x1f);
2453 int max_imm
= 1 << nbits
;
2454 int mask
= max_imm
- 1;
2455 int sign_bit
= max_imm
>> 1;
2457 offset
= inst
& mask
;
2458 if (is_signed
&& (offset
& sign_bit
))
2459 offset
= 0 - (max_imm
- offset
);
2460 return offset
* scale
;
2465 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2466 the associated FRAME_CACHE if not null.
2467 Return the address of the first instruction past the prologue. */
2470 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2471 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2472 struct frame_info
*this_frame
,
2473 struct mips_frame_cache
*this_cache
)
2475 int prev_non_prologue_insn
= 0;
2476 int this_non_prologue_insn
;
2477 int non_prologue_insns
= 0;
2480 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2482 long frame_offset
= 0; /* Size of stack frame. */
2483 long frame_adjust
= 0; /* Offset of FP from SP. */
2484 int frame_reg
= MIPS_SP_REGNUM
;
2485 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2486 unsigned inst
= 0; /* current instruction */
2487 unsigned entry_inst
= 0; /* the entry instruction */
2488 unsigned save_inst
= 0; /* the save instruction */
2489 int prev_delay_slot
= 0;
2493 int extend_bytes
= 0;
2494 int prev_extend_bytes
= 0;
2495 CORE_ADDR end_prologue_addr
;
2497 /* Can be called when there's no process, and hence when there's no
2499 if (this_frame
!= NULL
)
2500 sp
= get_frame_register_signed (this_frame
,
2501 gdbarch_num_regs (gdbarch
)
2506 if (limit_pc
> start_pc
+ 200)
2507 limit_pc
= start_pc
+ 200;
2510 /* Permit at most one non-prologue non-control-transfer instruction
2511 in the middle which may have been reordered by the compiler for
2513 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2515 this_non_prologue_insn
= 0;
2518 /* Save the previous instruction. If it's an EXTEND, we'll extract
2519 the immediate offset extension from it in mips16_get_imm. */
2522 /* Fetch and decode the instruction. */
2523 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2526 /* Normally we ignore extend instructions. However, if it is
2527 not followed by a valid prologue instruction, then this
2528 instruction is not part of the prologue either. We must
2529 remember in this case to adjust the end_prologue_addr back
2531 if ((inst
& 0xf800) == 0xf000) /* extend */
2533 extend_bytes
= MIPS_INSN16_SIZE
;
2537 prev_extend_bytes
= extend_bytes
;
2540 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2541 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2543 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2544 if (offset
< 0) /* Negative stack adjustment? */
2545 frame_offset
-= offset
;
2547 /* Exit loop if a positive stack adjustment is found, which
2548 usually means that the stack cleanup code in the function
2549 epilogue is reached. */
2552 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2554 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2555 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2556 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2558 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2560 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2561 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2562 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2564 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2566 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2567 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2569 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2571 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2572 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2574 else if (inst
== 0x673d) /* move $s1, $sp */
2579 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2581 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2582 frame_addr
= sp
+ offset
;
2584 frame_adjust
= offset
;
2586 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2588 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2589 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2590 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2592 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2594 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2595 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2596 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2598 else if ((inst
& 0xf81f) == 0xe809
2599 && (inst
& 0x700) != 0x700) /* entry */
2600 entry_inst
= inst
; /* Save for later processing. */
2601 else if ((inst
& 0xff80) == 0x6480) /* save */
2603 save_inst
= inst
; /* Save for later processing. */
2604 if (prev_extend_bytes
) /* extend */
2605 save_inst
|= prev_inst
<< 16;
2607 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2609 /* This instruction is part of the prologue, but we don't
2610 need to do anything special to handle it. */
2612 else if (mips16_instruction_has_delay_slot (inst
, 0))
2613 /* JAL/JALR/JALX/JR */
2615 /* The instruction in the delay slot can be a part
2616 of the prologue, so move forward once more. */
2618 if (mips16_instruction_has_delay_slot (inst
, 1))
2621 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2622 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2627 this_non_prologue_insn
= 1;
2630 non_prologue_insns
+= this_non_prologue_insn
;
2632 /* A jump or branch, or enough non-prologue insns seen? If so,
2633 then we must have reached the end of the prologue by now. */
2634 if (prev_delay_slot
|| non_prologue_insns
> 1
2635 || mips16_instruction_is_compact_branch (inst
))
2638 prev_non_prologue_insn
= this_non_prologue_insn
;
2639 prev_delay_slot
= in_delay_slot
;
2640 prev_pc
= cur_pc
- prev_extend_bytes
;
2643 /* The entry instruction is typically the first instruction in a function,
2644 and it stores registers at offsets relative to the value of the old SP
2645 (before the prologue). But the value of the sp parameter to this
2646 function is the new SP (after the prologue has been executed). So we
2647 can't calculate those offsets until we've seen the entire prologue,
2648 and can calculate what the old SP must have been. */
2649 if (entry_inst
!= 0)
2651 int areg_count
= (entry_inst
>> 8) & 7;
2652 int sreg_count
= (entry_inst
>> 6) & 3;
2654 /* The entry instruction always subtracts 32 from the SP. */
2657 /* Now we can calculate what the SP must have been at the
2658 start of the function prologue. */
2661 /* Check if a0-a3 were saved in the caller's argument save area. */
2662 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2664 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2665 offset
+= mips_abi_regsize (gdbarch
);
2668 /* Check if the ra register was pushed on the stack. */
2670 if (entry_inst
& 0x20)
2672 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2673 offset
-= mips_abi_regsize (gdbarch
);
2676 /* Check if the s0 and s1 registers were pushed on the stack. */
2677 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2679 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2680 offset
-= mips_abi_regsize (gdbarch
);
2684 /* The SAVE instruction is similar to ENTRY, except that defined by the
2685 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2686 size of the frame is specified as an immediate field of instruction
2687 and an extended variation exists which lets additional registers and
2688 frame space to be specified. The instruction always treats registers
2689 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2690 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2692 static int args_table
[16] = {
2693 0, 0, 0, 0, 1, 1, 1, 1,
2694 2, 2, 2, 0, 3, 3, 4, -1,
2696 static int astatic_table
[16] = {
2697 0, 1, 2, 3, 0, 1, 2, 3,
2698 0, 1, 2, 4, 0, 1, 0, -1,
2700 int aregs
= (save_inst
>> 16) & 0xf;
2701 int xsregs
= (save_inst
>> 24) & 0x7;
2702 int args
= args_table
[aregs
];
2703 int astatic
= astatic_table
[aregs
];
2708 warning (_("Invalid number of argument registers encoded in SAVE."));
2713 warning (_("Invalid number of static registers encoded in SAVE."));
2717 /* For standard SAVE the frame size of 0 means 128. */
2718 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2719 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2722 frame_offset
+= frame_size
;
2724 /* Now we can calculate what the SP must have been at the
2725 start of the function prologue. */
2728 /* Check if A0-A3 were saved in the caller's argument save area. */
2729 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2731 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2732 offset
+= mips_abi_regsize (gdbarch
);
2737 /* Check if the RA register was pushed on the stack. */
2738 if (save_inst
& 0x40)
2740 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2741 offset
-= mips_abi_regsize (gdbarch
);
2744 /* Check if the S8 register was pushed on the stack. */
2747 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2748 offset
-= mips_abi_regsize (gdbarch
);
2751 /* Check if S2-S7 were pushed on the stack. */
2752 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2754 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2755 offset
-= mips_abi_regsize (gdbarch
);
2758 /* Check if the S1 register was pushed on the stack. */
2759 if (save_inst
& 0x10)
2761 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2762 offset
-= mips_abi_regsize (gdbarch
);
2764 /* Check if the S0 register was pushed on the stack. */
2765 if (save_inst
& 0x20)
2767 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2768 offset
-= mips_abi_regsize (gdbarch
);
2771 /* Check if A0-A3 were pushed on the stack. */
2772 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2774 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2775 offset
-= mips_abi_regsize (gdbarch
);
2779 if (this_cache
!= NULL
)
2782 (get_frame_register_signed (this_frame
,
2783 gdbarch_num_regs (gdbarch
) + frame_reg
)
2784 + frame_offset
- frame_adjust
);
2785 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2786 be able to get rid of the assignment below, evetually. But it's
2787 still needed for now. */
2788 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2789 + mips_regnum (gdbarch
)->pc
]
2790 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2793 /* Set end_prologue_addr to the address of the instruction immediately
2794 after the last one we scanned. Unless the last one looked like a
2795 non-prologue instruction (and we looked ahead), in which case use
2796 its address instead. */
2797 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2798 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2800 return end_prologue_addr
;
2803 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2804 Procedures that use the 32-bit instruction set are handled by the
2805 mips_insn32 unwinder. */
2807 static struct mips_frame_cache
*
2808 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2810 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2811 struct mips_frame_cache
*cache
;
2813 if ((*this_cache
) != NULL
)
2814 return (struct mips_frame_cache
*) (*this_cache
);
2815 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2816 (*this_cache
) = cache
;
2817 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2819 /* Analyze the function prologue. */
2821 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2822 CORE_ADDR start_addr
;
2824 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2825 if (start_addr
== 0)
2826 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2827 /* We can't analyze the prologue if we couldn't find the begining
2829 if (start_addr
== 0)
2832 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2833 (struct mips_frame_cache
*) *this_cache
);
2836 /* gdbarch_sp_regnum contains the value and not the address. */
2837 trad_frame_set_value (cache
->saved_regs
,
2838 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2841 return (struct mips_frame_cache
*) (*this_cache
);
2845 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2846 struct frame_id
*this_id
)
2848 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2850 /* This marks the outermost frame. */
2851 if (info
->base
== 0)
2853 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2856 static struct value
*
2857 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2858 void **this_cache
, int regnum
)
2860 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2862 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2866 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2867 struct frame_info
*this_frame
, void **this_cache
)
2869 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2870 CORE_ADDR pc
= get_frame_pc (this_frame
);
2871 if (mips_pc_is_mips16 (gdbarch
, pc
))
2876 static const struct frame_unwind mips_insn16_frame_unwind
=
2879 default_frame_unwind_stop_reason
,
2880 mips_insn16_frame_this_id
,
2881 mips_insn16_frame_prev_register
,
2883 mips_insn16_frame_sniffer
2887 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2890 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2895 static const struct frame_base mips_insn16_frame_base
=
2897 &mips_insn16_frame_unwind
,
2898 mips_insn16_frame_base_address
,
2899 mips_insn16_frame_base_address
,
2900 mips_insn16_frame_base_address
2903 static const struct frame_base
*
2904 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2906 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2907 CORE_ADDR pc
= get_frame_pc (this_frame
);
2908 if (mips_pc_is_mips16 (gdbarch
, pc
))
2909 return &mips_insn16_frame_base
;
2914 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2915 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2916 interpreted directly, and then multiplied by 4. */
2919 micromips_decode_imm9 (int imm
)
2921 imm
= (imm
^ 0x100) - 0x100;
2922 if (imm
> -3 && imm
< 2)
2927 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2928 the address of the first instruction past the prologue. */
2931 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2932 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2933 struct frame_info
*this_frame
,
2934 struct mips_frame_cache
*this_cache
)
2936 CORE_ADDR end_prologue_addr
;
2937 int prev_non_prologue_insn
= 0;
2938 int frame_reg
= MIPS_SP_REGNUM
;
2939 int this_non_prologue_insn
;
2940 int non_prologue_insns
= 0;
2941 long frame_offset
= 0; /* Size of stack frame. */
2942 long frame_adjust
= 0; /* Offset of FP from SP. */
2943 int prev_delay_slot
= 0;
2947 ULONGEST insn
; /* current instruction */
2951 long v1_off
= 0; /* The assumption is LUI will replace it. */
2962 /* Can be called when there's no process, and hence when there's no
2964 if (this_frame
!= NULL
)
2965 sp
= get_frame_register_signed (this_frame
,
2966 gdbarch_num_regs (gdbarch
)
2971 if (limit_pc
> start_pc
+ 200)
2972 limit_pc
= start_pc
+ 200;
2975 /* Permit at most one non-prologue non-control-transfer instruction
2976 in the middle which may have been reordered by the compiler for
2978 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2980 this_non_prologue_insn
= 0;
2984 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2985 loc
+= MIPS_INSN16_SIZE
;
2986 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2988 /* 32-bit instructions. */
2989 case 2 * MIPS_INSN16_SIZE
:
2991 insn
|= mips_fetch_instruction (gdbarch
,
2992 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
2993 loc
+= MIPS_INSN16_SIZE
;
2994 switch (micromips_op (insn
>> 16))
2996 /* Record $sp/$fp adjustment. */
2997 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2998 case 0x0: /* POOL32A: bits 000000 */
2999 case 0x16: /* POOL32S: bits 010110 */
3000 op
= b0s11_op (insn
);
3001 sreg
= b0s5_reg (insn
>> 16);
3002 treg
= b5s5_reg (insn
>> 16);
3003 dreg
= b11s5_reg (insn
);
3005 /* SUBU: bits 000000 00111010000 */
3006 /* DSUBU: bits 010110 00111010000 */
3007 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3009 /* (D)SUBU $sp, $v1 */
3011 else if (op
!= 0x150
3012 /* ADDU: bits 000000 00101010000 */
3013 /* DADDU: bits 010110 00101010000 */
3014 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3015 this_non_prologue_insn
= 1;
3018 case 0x8: /* POOL32B: bits 001000 */
3019 op
= b12s4_op (insn
);
3020 breg
= b0s5_reg (insn
>> 16);
3021 reglist
= sreg
= b5s5_reg (insn
>> 16);
3022 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3023 if ((op
== 0x9 || op
== 0xc)
3024 /* SWP: bits 001000 1001 */
3025 /* SDP: bits 001000 1100 */
3026 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3027 /* S[DW]P reg,offset($sp) */
3029 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3030 set_reg_offset (gdbarch
, this_cache
,
3032 set_reg_offset (gdbarch
, this_cache
,
3033 sreg
+ 1, sp
+ offset
+ s
);
3035 else if ((op
== 0xd || op
== 0xf)
3036 /* SWM: bits 001000 1101 */
3037 /* SDM: bits 001000 1111 */
3038 && breg
== MIPS_SP_REGNUM
3039 /* SWM reglist,offset($sp) */
3040 && ((reglist
>= 1 && reglist
<= 9)
3041 || (reglist
>= 16 && reglist
<= 25)))
3043 int sreglist
= std::min(reglist
& 0xf, 8);
3045 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3046 for (i
= 0; i
< sreglist
; i
++)
3047 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3048 if ((reglist
& 0xf) > 8)
3049 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3050 if ((reglist
& 0x10) == 0x10)
3051 set_reg_offset (gdbarch
, this_cache
,
3052 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3055 this_non_prologue_insn
= 1;
3058 /* Record $sp/$fp adjustment. */
3059 /* Discard (D)ADDIU $gp used for PIC code. */
3060 case 0xc: /* ADDIU: bits 001100 */
3061 case 0x17: /* DADDIU: bits 010111 */
3062 sreg
= b0s5_reg (insn
>> 16);
3063 dreg
= b5s5_reg (insn
>> 16);
3064 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3065 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3066 /* (D)ADDIU $sp, imm */
3068 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3069 /* (D)ADDIU $fp, $sp, imm */
3071 frame_adjust
= offset
;
3074 else if (sreg
!= 28 || dreg
!= 28)
3075 /* (D)ADDIU $gp, imm */
3076 this_non_prologue_insn
= 1;
3079 /* LUI $v1 is used for larger $sp adjustments. */
3080 /* Discard LUI $gp used for PIC code. */
3081 case 0x10: /* POOL32I: bits 010000 */
3082 if (b5s5_op (insn
>> 16) == 0xd
3083 /* LUI: bits 010000 001101 */
3084 && b0s5_reg (insn
>> 16) == 3)
3086 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3087 else if (b5s5_op (insn
>> 16) != 0xd
3088 /* LUI: bits 010000 001101 */
3089 || b0s5_reg (insn
>> 16) != 28)
3091 this_non_prologue_insn
= 1;
3094 /* ORI $v1 is used for larger $sp adjustments. */
3095 case 0x14: /* ORI: bits 010100 */
3096 sreg
= b0s5_reg (insn
>> 16);
3097 dreg
= b5s5_reg (insn
>> 16);
3098 if (sreg
== 3 && dreg
== 3)
3100 v1_off
|= b0s16_imm (insn
);
3102 this_non_prologue_insn
= 1;
3105 case 0x26: /* SWC1: bits 100110 */
3106 case 0x2e: /* SDC1: bits 101110 */
3107 breg
= b0s5_reg (insn
>> 16);
3108 if (breg
!= MIPS_SP_REGNUM
)
3109 /* S[DW]C1 reg,offset($sp) */
3110 this_non_prologue_insn
= 1;
3113 case 0x36: /* SD: bits 110110 */
3114 case 0x3e: /* SW: bits 111110 */
3115 breg
= b0s5_reg (insn
>> 16);
3116 sreg
= b5s5_reg (insn
>> 16);
3117 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3118 if (breg
== MIPS_SP_REGNUM
)
3119 /* S[DW] reg,offset($sp) */
3120 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3122 this_non_prologue_insn
= 1;
3126 /* The instruction in the delay slot can be a part
3127 of the prologue, so move forward once more. */
3128 if (micromips_instruction_has_delay_slot (insn
, 0))
3131 this_non_prologue_insn
= 1;
3137 /* 16-bit instructions. */
3138 case MIPS_INSN16_SIZE
:
3139 switch (micromips_op (insn
))
3141 case 0x3: /* MOVE: bits 000011 */
3142 sreg
= b0s5_reg (insn
);
3143 dreg
= b5s5_reg (insn
);
3144 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3147 else if ((sreg
& 0x1c) != 0x4)
3148 /* MOVE reg, $a0-$a3 */
3149 this_non_prologue_insn
= 1;
3152 case 0x11: /* POOL16C: bits 010001 */
3153 if (b6s4_op (insn
) == 0x5)
3154 /* SWM: bits 010001 0101 */
3156 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3157 reglist
= b4s2_regl (insn
);
3158 for (i
= 0; i
<= reglist
; i
++)
3159 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3160 set_reg_offset (gdbarch
, this_cache
,
3161 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3164 this_non_prologue_insn
= 1;
3167 case 0x13: /* POOL16D: bits 010011 */
3168 if ((insn
& 0x1) == 0x1)
3169 /* ADDIUSP: bits 010011 1 */
3170 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3171 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3172 /* ADDIUS5: bits 010011 0 */
3173 /* ADDIUS5 $sp, imm */
3174 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3176 this_non_prologue_insn
= 1;
3179 case 0x32: /* SWSP: bits 110010 */
3180 offset
= b0s5_imm (insn
) << 2;
3181 sreg
= b5s5_reg (insn
);
3182 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3186 /* The instruction in the delay slot can be a part
3187 of the prologue, so move forward once more. */
3188 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3191 this_non_prologue_insn
= 1;
3197 frame_offset
-= sp_adj
;
3199 non_prologue_insns
+= this_non_prologue_insn
;
3201 /* A jump or branch, enough non-prologue insns seen or positive
3202 stack adjustment? If so, then we must have reached the end
3203 of the prologue by now. */
3204 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3205 || micromips_instruction_is_compact_branch (insn
))
3208 prev_non_prologue_insn
= this_non_prologue_insn
;
3209 prev_delay_slot
= in_delay_slot
;
3213 if (this_cache
!= NULL
)
3216 (get_frame_register_signed (this_frame
,
3217 gdbarch_num_regs (gdbarch
) + frame_reg
)
3218 + frame_offset
- frame_adjust
);
3219 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3220 be able to get rid of the assignment below, evetually. But it's
3221 still needed for now. */
3222 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3223 + mips_regnum (gdbarch
)->pc
]
3224 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3227 /* Set end_prologue_addr to the address of the instruction immediately
3228 after the last one we scanned. Unless the last one looked like a
3229 non-prologue instruction (and we looked ahead), in which case use
3230 its address instead. */
3232 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3234 return end_prologue_addr
;
3237 /* Heuristic unwinder for procedures using microMIPS instructions.
3238 Procedures that use the 32-bit instruction set are handled by the
3239 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3241 static struct mips_frame_cache
*
3242 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3244 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3245 struct mips_frame_cache
*cache
;
3247 if ((*this_cache
) != NULL
)
3248 return (struct mips_frame_cache
*) (*this_cache
);
3250 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3251 (*this_cache
) = cache
;
3252 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3254 /* Analyze the function prologue. */
3256 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3257 CORE_ADDR start_addr
;
3259 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3260 if (start_addr
== 0)
3261 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3262 /* We can't analyze the prologue if we couldn't find the begining
3264 if (start_addr
== 0)
3267 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3268 (struct mips_frame_cache
*) *this_cache
);
3271 /* gdbarch_sp_regnum contains the value and not the address. */
3272 trad_frame_set_value (cache
->saved_regs
,
3273 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3276 return (struct mips_frame_cache
*) (*this_cache
);
3280 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3281 struct frame_id
*this_id
)
3283 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3285 /* This marks the outermost frame. */
3286 if (info
->base
== 0)
3288 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3291 static struct value
*
3292 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3293 void **this_cache
, int regnum
)
3295 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3297 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3301 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3302 struct frame_info
*this_frame
, void **this_cache
)
3304 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3305 CORE_ADDR pc
= get_frame_pc (this_frame
);
3307 if (mips_pc_is_micromips (gdbarch
, pc
))
3312 static const struct frame_unwind mips_micro_frame_unwind
=
3315 default_frame_unwind_stop_reason
,
3316 mips_micro_frame_this_id
,
3317 mips_micro_frame_prev_register
,
3319 mips_micro_frame_sniffer
3323 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3326 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3331 static const struct frame_base mips_micro_frame_base
=
3333 &mips_micro_frame_unwind
,
3334 mips_micro_frame_base_address
,
3335 mips_micro_frame_base_address
,
3336 mips_micro_frame_base_address
3339 static const struct frame_base
*
3340 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3342 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3343 CORE_ADDR pc
= get_frame_pc (this_frame
);
3345 if (mips_pc_is_micromips (gdbarch
, pc
))
3346 return &mips_micro_frame_base
;
3351 /* Mark all the registers as unset in the saved_regs array
3352 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3355 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3357 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3361 const int num_regs
= gdbarch_num_regs (gdbarch
);
3364 for (i
= 0; i
< num_regs
; i
++)
3366 this_cache
->saved_regs
[i
].addr
= -1;
3371 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3372 the associated FRAME_CACHE if not null.
3373 Return the address of the first instruction past the prologue. */
3376 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3377 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3378 struct frame_info
*this_frame
,
3379 struct mips_frame_cache
*this_cache
)
3381 int prev_non_prologue_insn
;
3382 int this_non_prologue_insn
;
3383 int non_prologue_insns
;
3384 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3386 int prev_delay_slot
;
3391 int frame_reg
= MIPS_SP_REGNUM
;
3393 CORE_ADDR end_prologue_addr
;
3394 int seen_sp_adjust
= 0;
3395 int load_immediate_bytes
= 0;
3397 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3399 /* Can be called when there's no process, and hence when there's no
3401 if (this_frame
!= NULL
)
3402 sp
= get_frame_register_signed (this_frame
,
3403 gdbarch_num_regs (gdbarch
)
3408 if (limit_pc
> start_pc
+ 200)
3409 limit_pc
= start_pc
+ 200;
3412 prev_non_prologue_insn
= 0;
3413 non_prologue_insns
= 0;
3414 prev_delay_slot
= 0;
3417 /* Permit at most one non-prologue non-control-transfer instruction
3418 in the middle which may have been reordered by the compiler for
3421 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3423 unsigned long inst
, high_word
;
3427 this_non_prologue_insn
= 0;
3430 /* Fetch the instruction. */
3431 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3434 /* Save some code by pre-extracting some useful fields. */
3435 high_word
= (inst
>> 16) & 0xffff;
3436 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3437 reg
= high_word
& 0x1f;
3439 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3440 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3441 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3443 if (offset
< 0) /* Negative stack adjustment? */
3444 frame_offset
-= offset
;
3446 /* Exit loop if a positive stack adjustment is found, which
3447 usually means that the stack cleanup code in the function
3448 epilogue is reached. */
3452 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3453 && !regsize_is_64_bits
)
3455 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3457 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3458 && regsize_is_64_bits
)
3460 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3461 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3463 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3465 /* Old gcc frame, r30 is virtual frame pointer. */
3466 if (offset
!= frame_offset
)
3467 frame_addr
= sp
+ offset
;
3468 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3470 unsigned alloca_adjust
;
3473 frame_addr
= get_frame_register_signed
3474 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3477 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3478 if (alloca_adjust
> 0)
3480 /* FP > SP + frame_size. This may be because of
3481 an alloca or somethings similar. Fix sp to
3482 "pre-alloca" value, and try again. */
3483 sp
+= alloca_adjust
;
3484 /* Need to reset the status of all registers. Otherwise,
3485 we will hit a guard that prevents the new address
3486 for each register to be recomputed during the second
3488 reset_saved_regs (gdbarch
, this_cache
);
3493 /* move $30,$sp. With different versions of gas this will be either
3494 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3495 Accept any one of these. */
3496 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3498 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3499 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3501 unsigned alloca_adjust
;
3504 frame_addr
= get_frame_register_signed
3505 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3507 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3508 if (alloca_adjust
> 0)
3510 /* FP > SP + frame_size. This may be because of
3511 an alloca or somethings similar. Fix sp to
3512 "pre-alloca" value, and try again. */
3514 /* Need to reset the status of all registers. Otherwise,
3515 we will hit a guard that prevents the new address
3516 for each register to be recomputed during the second
3518 reset_saved_regs (gdbarch
, this_cache
);
3523 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3524 && !regsize_is_64_bits
)
3526 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3528 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3529 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3530 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3531 || high_word
== 0x3c1c /* lui $gp,n */
3532 || high_word
== 0x279c /* addiu $gp,$gp,n */
3533 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3534 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3537 /* These instructions are part of the prologue, but we don't
3538 need to do anything special to handle them. */
3540 /* The instructions below load $at or $t0 with an immediate
3541 value in preparation for a stack adjustment via
3542 subu $sp,$sp,[$at,$t0]. These instructions could also
3543 initialize a local variable, so we accept them only before
3544 a stack adjustment instruction was seen. */
3545 else if (!seen_sp_adjust
3547 && (high_word
== 0x3c01 /* lui $at,n */
3548 || high_word
== 0x3c08 /* lui $t0,n */
3549 || high_word
== 0x3421 /* ori $at,$at,n */
3550 || high_word
== 0x3508 /* ori $t0,$t0,n */
3551 || high_word
== 0x3401 /* ori $at,$zero,n */
3552 || high_word
== 0x3408 /* ori $t0,$zero,n */
3555 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3557 /* Check for branches and jumps. The instruction in the delay
3558 slot can be a part of the prologue, so move forward once more. */
3559 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3563 /* This instruction is not an instruction typically found
3564 in a prologue, so we must have reached the end of the
3568 this_non_prologue_insn
= 1;
3571 non_prologue_insns
+= this_non_prologue_insn
;
3573 /* A jump or branch, or enough non-prologue insns seen? If so,
3574 then we must have reached the end of the prologue by now. */
3575 if (prev_delay_slot
|| non_prologue_insns
> 1)
3578 prev_non_prologue_insn
= this_non_prologue_insn
;
3579 prev_delay_slot
= in_delay_slot
;
3583 if (this_cache
!= NULL
)
3586 (get_frame_register_signed (this_frame
,
3587 gdbarch_num_regs (gdbarch
) + frame_reg
)
3589 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3590 this assignment below, eventually. But it's still needed
3592 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3593 + mips_regnum (gdbarch
)->pc
]
3594 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3598 /* Set end_prologue_addr to the address of the instruction immediately
3599 after the last one we scanned. Unless the last one looked like a
3600 non-prologue instruction (and we looked ahead), in which case use
3601 its address instead. */
3603 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3605 /* In a frameless function, we might have incorrectly
3606 skipped some load immediate instructions. Undo the skipping
3607 if the load immediate was not followed by a stack adjustment. */
3608 if (load_immediate_bytes
&& !seen_sp_adjust
)
3609 end_prologue_addr
-= load_immediate_bytes
;
3611 return end_prologue_addr
;
3614 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3615 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3616 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3617 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3619 static struct mips_frame_cache
*
3620 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3622 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3623 struct mips_frame_cache
*cache
;
3625 if ((*this_cache
) != NULL
)
3626 return (struct mips_frame_cache
*) (*this_cache
);
3628 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3629 (*this_cache
) = cache
;
3630 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3632 /* Analyze the function prologue. */
3634 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3635 CORE_ADDR start_addr
;
3637 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3638 if (start_addr
== 0)
3639 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3640 /* We can't analyze the prologue if we couldn't find the begining
3642 if (start_addr
== 0)
3645 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3646 (struct mips_frame_cache
*) *this_cache
);
3649 /* gdbarch_sp_regnum contains the value and not the address. */
3650 trad_frame_set_value (cache
->saved_regs
,
3651 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3654 return (struct mips_frame_cache
*) (*this_cache
);
3658 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3659 struct frame_id
*this_id
)
3661 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3663 /* This marks the outermost frame. */
3664 if (info
->base
== 0)
3666 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3669 static struct value
*
3670 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3671 void **this_cache
, int regnum
)
3673 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3675 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3679 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3680 struct frame_info
*this_frame
, void **this_cache
)
3682 CORE_ADDR pc
= get_frame_pc (this_frame
);
3683 if (mips_pc_is_mips (pc
))
3688 static const struct frame_unwind mips_insn32_frame_unwind
=
3691 default_frame_unwind_stop_reason
,
3692 mips_insn32_frame_this_id
,
3693 mips_insn32_frame_prev_register
,
3695 mips_insn32_frame_sniffer
3699 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3702 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3707 static const struct frame_base mips_insn32_frame_base
=
3709 &mips_insn32_frame_unwind
,
3710 mips_insn32_frame_base_address
,
3711 mips_insn32_frame_base_address
,
3712 mips_insn32_frame_base_address
3715 static const struct frame_base
*
3716 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3718 CORE_ADDR pc
= get_frame_pc (this_frame
);
3719 if (mips_pc_is_mips (pc
))
3720 return &mips_insn32_frame_base
;
3725 static struct trad_frame_cache
*
3726 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3729 CORE_ADDR start_addr
;
3730 CORE_ADDR stack_addr
;
3731 struct trad_frame_cache
*this_trad_cache
;
3732 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3733 int num_regs
= gdbarch_num_regs (gdbarch
);
3735 if ((*this_cache
) != NULL
)
3736 return (struct trad_frame_cache
*) (*this_cache
);
3737 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3738 (*this_cache
) = this_trad_cache
;
3740 /* The return address is in the link register. */
3741 trad_frame_set_reg_realreg (this_trad_cache
,
3742 gdbarch_pc_regnum (gdbarch
),
3743 num_regs
+ MIPS_RA_REGNUM
);
3745 /* Frame ID, since it's a frameless / stackless function, no stack
3746 space is allocated and SP on entry is the current SP. */
3747 pc
= get_frame_pc (this_frame
);
3748 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3749 stack_addr
= get_frame_register_signed (this_frame
,
3750 num_regs
+ MIPS_SP_REGNUM
);
3751 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3753 /* Assume that the frame's base is the same as the
3755 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3757 return this_trad_cache
;
3761 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3762 struct frame_id
*this_id
)
3764 struct trad_frame_cache
*this_trad_cache
3765 = mips_stub_frame_cache (this_frame
, this_cache
);
3766 trad_frame_get_id (this_trad_cache
, this_id
);
3769 static struct value
*
3770 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3771 void **this_cache
, int regnum
)
3773 struct trad_frame_cache
*this_trad_cache
3774 = mips_stub_frame_cache (this_frame
, this_cache
);
3775 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3779 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3780 struct frame_info
*this_frame
, void **this_cache
)
3783 struct obj_section
*s
;
3784 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3785 struct bound_minimal_symbol msym
;
3787 /* Use the stub unwinder for unreadable code. */
3788 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3791 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3794 /* Calling a PIC function from a non-PIC function passes through a
3795 stub. The stub for foo is named ".pic.foo". */
3796 msym
= lookup_minimal_symbol_by_pc (pc
);
3797 if (msym
.minsym
!= NULL
3798 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
3799 && startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
3805 static const struct frame_unwind mips_stub_frame_unwind
=
3808 default_frame_unwind_stop_reason
,
3809 mips_stub_frame_this_id
,
3810 mips_stub_frame_prev_register
,
3812 mips_stub_frame_sniffer
3816 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3819 struct trad_frame_cache
*this_trad_cache
3820 = mips_stub_frame_cache (this_frame
, this_cache
);
3821 return trad_frame_get_this_base (this_trad_cache
);
3824 static const struct frame_base mips_stub_frame_base
=
3826 &mips_stub_frame_unwind
,
3827 mips_stub_frame_base_address
,
3828 mips_stub_frame_base_address
,
3829 mips_stub_frame_base_address
3832 static const struct frame_base
*
3833 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3835 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3836 return &mips_stub_frame_base
;
3841 /* mips_addr_bits_remove - remove useless address bits */
3844 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3846 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3848 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3849 /* This hack is a work-around for existing boards using PMON, the
3850 simulator, and any other 64-bit targets that doesn't have true
3851 64-bit addressing. On these targets, the upper 32 bits of
3852 addresses are ignored by the hardware. Thus, the PC or SP are
3853 likely to have been sign extended to all 1s by instruction
3854 sequences that load 32-bit addresses. For example, a typical
3855 piece of code that loads an address is this:
3857 lui $r2, <upper 16 bits>
3858 ori $r2, <lower 16 bits>
3860 But the lui sign-extends the value such that the upper 32 bits
3861 may be all 1s. The workaround is simply to mask off these
3862 bits. In the future, gcc may be changed to support true 64-bit
3863 addressing, and this masking will have to be disabled. */
3864 return addr
&= 0xffffffffUL
;
3870 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3871 instruction and ending with a SC/SCD instruction. If such a sequence
3872 is found, attempt to step through it. A breakpoint is placed at the end of
3875 /* Instructions used during single-stepping of atomic sequences, standard
3877 #define LL_OPCODE 0x30
3878 #define LLD_OPCODE 0x34
3879 #define SC_OPCODE 0x38
3880 #define SCD_OPCODE 0x3c
3882 static std::vector
<CORE_ADDR
>
3883 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3885 CORE_ADDR breaks
[2] = {-1, -1};
3887 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3891 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3892 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3894 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3895 /* Assume all atomic sequences start with a ll/lld instruction. */
3896 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3899 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3901 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3904 loc
+= MIPS_INSN32_SIZE
;
3905 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3907 /* Assume that there is at most one branch in the atomic
3908 sequence. If a branch is found, put a breakpoint in its
3909 destination address. */
3910 switch (itype_op (insn
))
3912 case 0: /* SPECIAL */
3913 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3914 return {}; /* fallback to the standard single-step code. */
3916 case 1: /* REGIMM */
3917 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3918 || ((itype_rt (insn
) & 0x1e) == 0
3919 && itype_rs (insn
) == 0)); /* BPOSGE* */
3923 return {}; /* fallback to the standard single-step code. */
3930 case 22: /* BLEZL */
3931 case 23: /* BGTTL */
3935 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3936 && (itype_rt (insn
) & 0x2) == 0);
3937 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3942 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3947 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3948 if (last_breakpoint
>= 1)
3949 return {}; /* More than one branch found, fallback to the
3950 standard single-step code. */
3951 breaks
[1] = branch_bp
;
3955 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3959 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3960 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3963 loc
+= MIPS_INSN32_SIZE
;
3965 /* Insert a breakpoint right after the end of the atomic sequence. */
3968 /* Check for duplicated breakpoints. Check also for a breakpoint
3969 placed (branch instruction's destination) in the atomic sequence. */
3970 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3971 last_breakpoint
= 0;
3973 std::vector
<CORE_ADDR
> next_pcs
;
3975 /* Effectively inserts the breakpoints. */
3976 for (index
= 0; index
<= last_breakpoint
; index
++)
3977 next_pcs
.push_back (breaks
[index
]);
3982 static std::vector
<CORE_ADDR
>
3983 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3986 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3987 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3988 CORE_ADDR breaks
[2] = {-1, -1};
3989 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
3997 /* Assume all atomic sequences start with a ll/lld instruction. */
3998 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3999 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4001 loc
+= MIPS_INSN16_SIZE
;
4003 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4004 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4006 loc
+= MIPS_INSN16_SIZE
;
4008 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4009 that no atomic sequence is longer than "atomic_sequence_length"
4011 for (insn_count
= 0;
4012 !sc_found
&& insn_count
< atomic_sequence_length
;
4017 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4018 loc
+= MIPS_INSN16_SIZE
;
4020 /* Assume that there is at most one conditional branch in the
4021 atomic sequence. If a branch is found, put a breakpoint in
4022 its destination address. */
4023 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4025 /* 32-bit instructions. */
4026 case 2 * MIPS_INSN16_SIZE
:
4027 switch (micromips_op (insn
))
4029 case 0x10: /* POOL32I: bits 010000 */
4030 if ((b5s5_op (insn
) & 0x18) != 0x0
4031 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4032 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4033 && (b5s5_op (insn
) & 0x1d) != 0x11
4034 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4035 && ((b5s5_op (insn
) & 0x1e) != 0x14
4036 || (insn
& 0x3) != 0x0)
4037 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4038 && (b5s5_op (insn
) & 0x1e) != 0x1a
4039 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4040 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4041 || (insn
& 0x3) != 0x0)
4042 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4043 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4044 || (insn
& 0x3) != 0x1))
4045 /* BC1ANY*: bits 010000 111xx xxx01 */
4049 case 0x25: /* BEQ: bits 100101 */
4050 case 0x2d: /* BNE: bits 101101 */
4052 insn
|= mips_fetch_instruction (gdbarch
,
4053 ISA_MICROMIPS
, loc
, NULL
);
4054 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4055 + micromips_relative_offset16 (insn
));
4059 case 0x00: /* POOL32A: bits 000000 */
4061 insn
|= mips_fetch_instruction (gdbarch
,
4062 ISA_MICROMIPS
, loc
, NULL
);
4063 if (b0s6_op (insn
) != 0x3c
4064 /* POOL32Axf: bits 000000 ... 111100 */
4065 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4066 /* JALR, JALR.HB: 000000 000x111100 111100 */
4067 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4071 case 0x1d: /* JALS: bits 011101 */
4072 case 0x35: /* J: bits 110101 */
4073 case 0x3d: /* JAL: bits 111101 */
4074 case 0x3c: /* JALX: bits 111100 */
4075 return {}; /* Fall back to the standard single-step code. */
4077 case 0x18: /* POOL32C: bits 011000 */
4078 if ((b12s4_op (insn
) & 0xb) == 0xb)
4079 /* SC, SCD: bits 011000 1x11 */
4083 loc
+= MIPS_INSN16_SIZE
;
4086 /* 16-bit instructions. */
4087 case MIPS_INSN16_SIZE
:
4088 switch (micromips_op (insn
))
4090 case 0x23: /* BEQZ16: bits 100011 */
4091 case 0x2b: /* BNEZ16: bits 101011 */
4092 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4096 case 0x11: /* POOL16C: bits 010001 */
4097 if ((b5s5_op (insn
) & 0x1c) != 0xc
4098 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4099 && b5s5_op (insn
) != 0x18)
4100 /* JRADDIUSP: bits 010001 11000 */
4102 return {}; /* Fall back to the standard single-step code. */
4104 case 0x33: /* B16: bits 110011 */
4105 return {}; /* Fall back to the standard single-step code. */
4111 if (last_breakpoint
>= 1)
4112 return {}; /* More than one branch found, fallback to the
4113 standard single-step code. */
4114 breaks
[1] = branch_bp
;
4121 /* Insert a breakpoint right after the end of the atomic sequence. */
4124 /* Check for duplicated breakpoints. Check also for a breakpoint
4125 placed (branch instruction's destination) in the atomic sequence */
4126 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4127 last_breakpoint
= 0;
4129 std::vector
<CORE_ADDR
> next_pcs
;
4131 /* Effectively inserts the breakpoints. */
4132 for (index
= 0; index
<= last_breakpoint
; index
++)
4133 next_pcs
.push_back (breaks
[index
]);
4138 static std::vector
<CORE_ADDR
>
4139 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4141 if (mips_pc_is_mips (pc
))
4142 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4143 else if (mips_pc_is_micromips (gdbarch
, pc
))
4144 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4149 /* mips_software_single_step() is called just before we want to resume
4150 the inferior, if we want to single-step it but there is no hardware
4151 or kernel single-step support (MIPS on GNU/Linux for example). We find
4152 the target of the coming instruction and breakpoint it. */
4154 std::vector
<CORE_ADDR
>
4155 mips_software_single_step (struct regcache
*regcache
)
4157 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
4158 CORE_ADDR pc
, next_pc
;
4160 pc
= regcache_read_pc (regcache
);
4161 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4163 if (!next_pcs
.empty ())
4166 next_pc
= mips_next_pc (regcache
, pc
);
4171 /* Test whether the PC points to the return instruction at the
4172 end of a function. */
4175 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4180 /* This used to check for MIPS16, but this piece of code is never
4181 called for MIPS16 functions. And likewise microMIPS ones. */
4182 gdb_assert (mips_pc_is_mips (pc
));
4184 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4186 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4190 /* This fencepost looks highly suspicious to me. Removing it also
4191 seems suspicious as it could affect remote debugging across serial
4195 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4201 struct inferior
*inf
;
4203 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4205 fence
= start_pc
- heuristic_fence_post
;
4209 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4210 fence
= VM_MIN_ADDRESS
;
4212 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4214 inf
= current_inferior ();
4216 /* Search back for previous return. */
4217 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4218 if (start_pc
< fence
)
4220 /* It's not clear to me why we reach this point when
4221 stop_soon, but with this test, at least we
4222 don't print out warnings for every child forked (eg, on
4223 decstation). 22apr93 rich@cygnus.com. */
4224 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4226 static int blurb_printed
= 0;
4228 warning (_("GDB can't find the start of the function at %s."),
4229 paddress (gdbarch
, pc
));
4233 /* This actually happens frequently in embedded
4234 development, when you first connect to a board
4235 and your stack pointer and pc are nowhere in
4236 particular. This message needs to give people
4237 in that situation enough information to
4238 determine that it's no big deal. */
4239 printf_filtered ("\n\
4240 GDB is unable to find the start of the function at %s\n\
4241 and thus can't determine the size of that function's stack frame.\n\
4242 This means that GDB may be unable to access that stack frame, or\n\
4243 the frames below it.\n\
4244 This problem is most likely caused by an invalid program counter or\n\
4246 However, if you think GDB should simply search farther back\n\
4247 from %s for code which looks like the beginning of a\n\
4248 function, you can increase the range of the search using the `set\n\
4249 heuristic-fence-post' command.\n",
4250 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4257 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4259 unsigned short inst
;
4261 /* On MIPS16, any one of the following is likely to be the
4262 start of a function:
4268 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4269 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4270 if ((inst
& 0xff80) == 0x6480) /* save */
4272 if (start_pc
- instlen
>= fence
)
4274 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4275 start_pc
- instlen
, NULL
);
4276 if ((inst
& 0xf800) == 0xf000) /* extend */
4277 start_pc
-= instlen
;
4281 else if (((inst
& 0xf81f) == 0xe809
4282 && (inst
& 0x700) != 0x700) /* entry */
4283 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4284 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4285 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4287 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4288 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4293 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4301 /* On microMIPS, any one of the following is likely to be the
4302 start of a function:
4306 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4307 switch (micromips_op (insn
))
4309 case 0xc: /* ADDIU: bits 001100 */
4310 case 0x17: /* DADDIU: bits 010111 */
4311 sreg
= b0s5_reg (insn
);
4312 dreg
= b5s5_reg (insn
);
4314 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4315 pc
+ MIPS_INSN16_SIZE
, NULL
);
4316 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4317 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4318 /* (D)ADDIU $sp, imm */
4323 case 0x10: /* POOL32I: bits 010000 */
4324 if (b5s5_op (insn
) == 0xd
4325 /* LUI: bits 010000 001101 */
4326 && b0s5_reg (insn
>> 16) == 28)
4331 case 0x13: /* POOL16D: bits 010011 */
4332 if ((insn
& 0x1) == 0x1)
4333 /* ADDIUSP: bits 010011 1 */
4335 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4341 /* ADDIUS5: bits 010011 0 */
4343 dreg
= b5s5_reg (insn
);
4344 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4345 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4346 /* ADDIUS5 $sp, -imm */
4354 else if (mips_about_to_return (gdbarch
, start_pc
))
4356 /* Skip return and its delay slot. */
4357 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4364 struct mips_objfile_private
4370 /* According to the current ABI, should the type be passed in a
4371 floating-point register (assuming that there is space)? When there
4372 is no FPU, FP are not even considered as possible candidates for
4373 FP registers and, consequently this returns false - forces FP
4374 arguments into integer registers. */
4377 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4378 struct type
*arg_type
)
4380 return ((typecode
== TYPE_CODE_FLT
4381 || (MIPS_EABI (gdbarch
)
4382 && (typecode
== TYPE_CODE_STRUCT
4383 || typecode
== TYPE_CODE_UNION
)
4384 && TYPE_NFIELDS (arg_type
) == 1
4385 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4387 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4390 /* On o32, argument passing in GPRs depends on the alignment of the type being
4391 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4394 mips_type_needs_double_align (struct type
*type
)
4396 enum type_code typecode
= TYPE_CODE (type
);
4398 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4400 else if (typecode
== TYPE_CODE_STRUCT
)
4402 if (TYPE_NFIELDS (type
) < 1)
4404 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4406 else if (typecode
== TYPE_CODE_UNION
)
4410 n
= TYPE_NFIELDS (type
);
4411 for (i
= 0; i
< n
; i
++)
4412 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4419 /* Adjust the address downward (direction of stack growth) so that it
4420 is correctly aligned for a new stack frame. */
4422 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4424 return align_down (addr
, 16);
4427 /* Implement the "push_dummy_code" gdbarch method. */
4430 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4431 CORE_ADDR funaddr
, struct value
**args
,
4432 int nargs
, struct type
*value_type
,
4433 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4434 struct regcache
*regcache
)
4436 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4440 /* Reserve enough room on the stack for our breakpoint instruction. */
4441 bp_slot
= sp
- sizeof (nop_insn
);
4443 /* Return to microMIPS mode if calling microMIPS code to avoid
4444 triggering an address error exception on processors that only
4445 support microMIPS execution. */
4446 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4447 ? make_compact_addr (bp_slot
) : bp_slot
);
4449 /* The breakpoint layer automatically adjusts the address of
4450 breakpoints inserted in a branch delay slot. With enough
4451 bad luck, the 4 bytes located just before our breakpoint
4452 instruction could look like a branch instruction, and thus
4453 trigger the adjustement, and break the function call entirely.
4454 So, we reserve those 4 bytes and write a nop instruction
4455 to prevent that from happening. */
4456 nop_addr
= bp_slot
- sizeof (nop_insn
);
4457 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4458 sp
= mips_frame_align (gdbarch
, nop_addr
);
4460 /* Inferior resumes at the function entry point. */
4467 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4468 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4469 int nargs
, struct value
**args
, CORE_ADDR sp
,
4470 int struct_return
, CORE_ADDR struct_addr
)
4476 int stack_offset
= 0;
4477 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4478 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4479 int regsize
= mips_abi_regsize (gdbarch
);
4481 /* For shared libraries, "t9" needs to point at the function
4483 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4485 /* Set the return address register to point to the entry point of
4486 the program, where a breakpoint lies in wait. */
4487 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4489 /* First ensure that the stack and structure return address (if any)
4490 are properly aligned. The stack has to be at least 64-bit
4491 aligned even on 32-bit machines, because doubles must be 64-bit
4492 aligned. For n32 and n64, stack frames need to be 128-bit
4493 aligned, so we round to this widest known alignment. */
4495 sp
= align_down (sp
, 16);
4496 struct_addr
= align_down (struct_addr
, 16);
4498 /* Now make space on the stack for the args. We allocate more
4499 than necessary for EABI, because the first few arguments are
4500 passed in registers, but that's OK. */
4501 for (argnum
= 0; argnum
< nargs
; argnum
++)
4502 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
4503 sp
-= align_up (len
, 16);
4506 fprintf_unfiltered (gdb_stdlog
,
4507 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4508 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4510 /* Initialize the integer and float register pointers. */
4511 argreg
= MIPS_A0_REGNUM
;
4512 float_argreg
= mips_fpa0_regnum (gdbarch
);
4514 /* The struct_return pointer occupies the first parameter-passing reg. */
4518 fprintf_unfiltered (gdb_stdlog
,
4519 "mips_eabi_push_dummy_call: "
4520 "struct_return reg=%d %s\n",
4521 argreg
, paddress (gdbarch
, struct_addr
));
4522 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4525 /* Now load as many as possible of the first arguments into
4526 registers, and push the rest onto the stack. Loop thru args
4527 from first to last. */
4528 for (argnum
= 0; argnum
< nargs
; argnum
++)
4530 const gdb_byte
*val
;
4531 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4532 struct value
*arg
= args
[argnum
];
4533 struct type
*arg_type
= check_typedef (value_type (arg
));
4534 int len
= TYPE_LENGTH (arg_type
);
4535 enum type_code typecode
= TYPE_CODE (arg_type
);
4538 fprintf_unfiltered (gdb_stdlog
,
4539 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4540 argnum
+ 1, len
, (int) typecode
);
4542 /* The EABI passes structures that do not fit in a register by
4545 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4547 store_unsigned_integer (valbuf
, regsize
, byte_order
,
4548 value_address (arg
));
4549 typecode
= TYPE_CODE_PTR
;
4553 fprintf_unfiltered (gdb_stdlog
, " push");
4556 val
= value_contents (arg
);
4558 /* 32-bit ABIs always start floating point arguments in an
4559 even-numbered floating point register. Round the FP register
4560 up before the check to see if there are any FP registers
4561 left. Non MIPS_EABI targets also pass the FP in the integer
4562 registers so also round up normal registers. */
4563 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4565 if ((float_argreg
& 1))
4569 /* Floating point arguments passed in registers have to be
4570 treated specially. On 32-bit architectures, doubles
4571 are passed in register pairs; the even register gets
4572 the low word, and the odd register gets the high word.
4573 On non-EABI processors, the first two floating point arguments are
4574 also copied to general registers, because MIPS16 functions
4575 don't use float registers for arguments. This duplication of
4576 arguments in general registers can't hurt non-MIPS16 functions
4577 because those registers are normally skipped. */
4578 /* MIPS_EABI squeezes a struct that contains a single floating
4579 point value into an FP register instead of pushing it onto the
4581 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4582 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4584 /* EABI32 will pass doubles in consecutive registers, even on
4585 64-bit cores. At one time, we used to check the size of
4586 `float_argreg' to determine whether or not to pass doubles
4587 in consecutive registers, but this is not sufficient for
4588 making the ABI determination. */
4589 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4591 int low_offset
= gdbarch_byte_order (gdbarch
)
4592 == BFD_ENDIAN_BIG
? 4 : 0;
4595 /* Write the low word of the double to the even register(s). */
4596 regval
= extract_signed_integer (val
+ low_offset
,
4599 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4600 float_argreg
, phex (regval
, 4));
4601 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4603 /* Write the high word of the double to the odd register(s). */
4604 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4607 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4608 float_argreg
, phex (regval
, 4));
4609 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4613 /* This is a floating point value that fits entirely
4614 in a single register. */
4615 /* On 32 bit ABI's the float_argreg is further adjusted
4616 above to ensure that it is even register aligned. */
4617 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4619 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4620 float_argreg
, phex (regval
, len
));
4621 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4626 /* Copy the argument to general registers or the stack in
4627 register-sized pieces. Large arguments are split between
4628 registers and stack. */
4629 /* Note: structs whose size is not a multiple of regsize
4630 are treated specially: Irix cc passes
4631 them in registers where gcc sometimes puts them on the
4632 stack. For maximum compatibility, we will put them in
4634 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
4636 /* Note: Floating-point values that didn't fit into an FP
4637 register are only written to memory. */
4640 /* Remember if the argument was written to the stack. */
4641 int stack_used_p
= 0;
4642 int partial_len
= (len
< regsize
? len
: regsize
);
4645 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4648 /* Write this portion of the argument to the stack. */
4649 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4651 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4653 /* Should shorter than int integer values be
4654 promoted to int before being stored? */
4655 int longword_offset
= 0;
4658 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4661 && (typecode
== TYPE_CODE_INT
4662 || typecode
== TYPE_CODE_PTR
4663 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4664 longword_offset
= regsize
- len
;
4665 else if ((typecode
== TYPE_CODE_STRUCT
4666 || typecode
== TYPE_CODE_UNION
)
4667 && TYPE_LENGTH (arg_type
) < regsize
)
4668 longword_offset
= regsize
- len
;
4673 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4674 paddress (gdbarch
, stack_offset
));
4675 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4676 paddress (gdbarch
, longword_offset
));
4679 addr
= sp
+ stack_offset
+ longword_offset
;
4684 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4685 paddress (gdbarch
, addr
));
4686 for (i
= 0; i
< partial_len
; i
++)
4688 fprintf_unfiltered (gdb_stdlog
, "%02x",
4692 write_memory (addr
, val
, partial_len
);
4695 /* Note!!! This is NOT an else clause. Odd sized
4696 structs may go thru BOTH paths. Floating point
4697 arguments will not. */
4698 /* Write this portion of the argument to a general
4699 purpose register. */
4700 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4701 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4704 extract_signed_integer (val
, partial_len
, byte_order
);
4707 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4709 phex (regval
, regsize
));
4710 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4717 /* Compute the offset into the stack at which we will
4718 copy the next parameter.
4720 In the new EABI (and the NABI32), the stack_offset
4721 only needs to be adjusted when it has been used. */
4724 stack_offset
+= align_up (partial_len
, regsize
);
4728 fprintf_unfiltered (gdb_stdlog
, "\n");
4731 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4733 /* Return adjusted stack pointer. */
4737 /* Determine the return value convention being used. */
4739 static enum return_value_convention
4740 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4741 struct type
*type
, struct regcache
*regcache
,
4742 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4744 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4745 int fp_return_type
= 0;
4746 int offset
, regnum
, xfer
;
4748 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4749 return RETURN_VALUE_STRUCT_CONVENTION
;
4751 /* Floating point type? */
4752 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4754 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4756 /* Structs with a single field of float type
4757 are returned in a floating point register. */
4758 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4759 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4760 && TYPE_NFIELDS (type
) == 1)
4762 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4764 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4771 /* A floating-point value belongs in the least significant part
4774 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4775 regnum
= mips_regnum (gdbarch
)->fp0
;
4779 /* An integer value goes in V0/V1. */
4781 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4782 regnum
= MIPS_V0_REGNUM
;
4785 offset
< TYPE_LENGTH (type
);
4786 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4788 xfer
= mips_abi_regsize (gdbarch
);
4789 if (offset
+ xfer
> TYPE_LENGTH (type
))
4790 xfer
= TYPE_LENGTH (type
) - offset
;
4791 mips_xfer_register (gdbarch
, regcache
,
4792 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4793 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4797 return RETURN_VALUE_REGISTER_CONVENTION
;
4801 /* N32/N64 ABI stuff. */
4803 /* Search for a naturally aligned double at OFFSET inside a struct
4804 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4808 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4813 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4816 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4819 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4822 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4825 struct type
*field_type
;
4827 /* We're only looking at normal fields. */
4828 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4829 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4832 /* If we have gone past the offset, there is no double to pass. */
4833 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4837 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4839 /* If this field is entirely before the requested offset, go
4840 on to the next one. */
4841 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4844 /* If this is our special aligned double, we can stop. */
4845 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4846 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4849 /* This field starts at or before the requested offset, and
4850 overlaps it. If it is a structure, recurse inwards. */
4851 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4858 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4859 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4860 int nargs
, struct value
**args
, CORE_ADDR sp
,
4861 int struct_return
, CORE_ADDR struct_addr
)
4867 int stack_offset
= 0;
4868 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4869 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4871 /* For shared libraries, "t9" needs to point at the function
4873 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4875 /* Set the return address register to point to the entry point of
4876 the program, where a breakpoint lies in wait. */
4877 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4879 /* First ensure that the stack and structure return address (if any)
4880 are properly aligned. The stack has to be at least 64-bit
4881 aligned even on 32-bit machines, because doubles must be 64-bit
4882 aligned. For n32 and n64, stack frames need to be 128-bit
4883 aligned, so we round to this widest known alignment. */
4885 sp
= align_down (sp
, 16);
4886 struct_addr
= align_down (struct_addr
, 16);
4888 /* Now make space on the stack for the args. */
4889 for (argnum
= 0; argnum
< nargs
; argnum
++)
4890 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4891 sp
-= align_up (len
, 16);
4894 fprintf_unfiltered (gdb_stdlog
,
4895 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4896 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4898 /* Initialize the integer and float register pointers. */
4899 argreg
= MIPS_A0_REGNUM
;
4900 float_argreg
= mips_fpa0_regnum (gdbarch
);
4902 /* The struct_return pointer occupies the first parameter-passing reg. */
4906 fprintf_unfiltered (gdb_stdlog
,
4907 "mips_n32n64_push_dummy_call: "
4908 "struct_return reg=%d %s\n",
4909 argreg
, paddress (gdbarch
, struct_addr
));
4910 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4913 /* Now load as many as possible of the first arguments into
4914 registers, and push the rest onto the stack. Loop thru args
4915 from first to last. */
4916 for (argnum
= 0; argnum
< nargs
; argnum
++)
4918 const gdb_byte
*val
;
4919 struct value
*arg
= args
[argnum
];
4920 struct type
*arg_type
= check_typedef (value_type (arg
));
4921 int len
= TYPE_LENGTH (arg_type
);
4922 enum type_code typecode
= TYPE_CODE (arg_type
);
4925 fprintf_unfiltered (gdb_stdlog
,
4926 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4927 argnum
+ 1, len
, (int) typecode
);
4929 val
= value_contents (arg
);
4931 /* A 128-bit long double value requires an even-odd pair of
4932 floating-point registers. */
4934 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4935 && (float_argreg
& 1))
4941 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4942 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4944 /* This is a floating point value that fits entirely
4945 in a single register or a pair of registers. */
4946 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4947 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4949 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4950 float_argreg
, phex (regval
, reglen
));
4951 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4954 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4955 argreg
, phex (regval
, reglen
));
4956 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4961 regval
= extract_unsigned_integer (val
+ reglen
,
4962 reglen
, byte_order
);
4964 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4965 float_argreg
, phex (regval
, reglen
));
4966 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4969 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4970 argreg
, phex (regval
, reglen
));
4971 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4978 /* Copy the argument to general registers or the stack in
4979 register-sized pieces. Large arguments are split between
4980 registers and stack. */
4981 /* For N32/N64, structs, unions, or other composite types are
4982 treated as a sequence of doublewords, and are passed in integer
4983 or floating point registers as though they were simple scalar
4984 parameters to the extent that they fit, with any excess on the
4985 stack packed according to the normal memory layout of the
4987 The caller does not reserve space for the register arguments;
4988 the callee is responsible for reserving it if required. */
4989 /* Note: Floating-point values that didn't fit into an FP
4990 register are only written to memory. */
4993 /* Remember if the argument was written to the stack. */
4994 int stack_used_p
= 0;
4995 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4998 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5001 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5002 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
5004 /* Write this portion of the argument to the stack. */
5005 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
5007 /* Should shorter than int integer values be
5008 promoted to int before being stored? */
5009 int longword_offset
= 0;
5012 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5014 if ((typecode
== TYPE_CODE_INT
5015 || typecode
== TYPE_CODE_PTR
)
5017 longword_offset
= MIPS64_REGSIZE
- len
;
5022 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5023 paddress (gdbarch
, stack_offset
));
5024 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5025 paddress (gdbarch
, longword_offset
));
5028 addr
= sp
+ stack_offset
+ longword_offset
;
5033 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5034 paddress (gdbarch
, addr
));
5035 for (i
= 0; i
< partial_len
; i
++)
5037 fprintf_unfiltered (gdb_stdlog
, "%02x",
5041 write_memory (addr
, val
, partial_len
);
5044 /* Note!!! This is NOT an else clause. Odd sized
5045 structs may go thru BOTH paths. */
5046 /* Write this portion of the argument to a general
5047 purpose register. */
5048 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5052 /* Sign extend pointers, 32-bit integers and signed
5053 16-bit and 8-bit integers; everything else is taken
5056 if ((partial_len
== 4
5057 && (typecode
== TYPE_CODE_PTR
5058 || typecode
== TYPE_CODE_INT
))
5060 && typecode
== TYPE_CODE_INT
5061 && !TYPE_UNSIGNED (arg_type
)))
5062 regval
= extract_signed_integer (val
, partial_len
,
5065 regval
= extract_unsigned_integer (val
, partial_len
,
5068 /* A non-floating-point argument being passed in a
5069 general register. If a struct or union, and if
5070 the remaining length is smaller than the register
5071 size, we have to adjust the register value on
5074 It does not seem to be necessary to do the
5075 same for integral types. */
5077 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5078 && partial_len
< MIPS64_REGSIZE
5079 && (typecode
== TYPE_CODE_STRUCT
5080 || typecode
== TYPE_CODE_UNION
))
5081 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5085 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5087 phex (regval
, MIPS64_REGSIZE
));
5088 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5090 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5091 TYPE_LENGTH (arg_type
) - len
))
5094 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5096 phex (regval
, MIPS64_REGSIZE
));
5097 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5108 /* Compute the offset into the stack at which we will
5109 copy the next parameter.
5111 In N32 (N64?), the stack_offset only needs to be
5112 adjusted when it has been used. */
5115 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5119 fprintf_unfiltered (gdb_stdlog
, "\n");
5122 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5124 /* Return adjusted stack pointer. */
5128 static enum return_value_convention
5129 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5130 struct type
*type
, struct regcache
*regcache
,
5131 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5133 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5135 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5137 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5138 if needed), as appropriate for the type. Composite results (struct,
5139 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5142 * A struct with only one or two floating point fields is returned in $f0
5143 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5146 * Any other composite results of at most 128 bits are returned in
5147 $2 (first 64 bits) and $3 (remainder, if necessary).
5149 * Larger composite results are handled by converting the function to a
5150 procedure with an implicit first parameter, which is a pointer to an area
5151 reserved by the caller to receive the result. [The o32-bit ABI requires
5152 that all composite results be handled by conversion to implicit first
5153 parameters. The MIPS/SGI Fortran implementation has always made a
5154 specific exception to return COMPLEX results in the floating point
5157 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5158 return RETURN_VALUE_STRUCT_CONVENTION
;
5159 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5160 && TYPE_LENGTH (type
) == 16
5161 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5163 /* A 128-bit floating-point value fills both $f0 and $f2. The
5164 two registers are used in the same as memory order, so the
5165 eight bytes with the lower memory address are in $f0. */
5167 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5168 mips_xfer_register (gdbarch
, regcache
,
5169 (gdbarch_num_regs (gdbarch
)
5170 + mips_regnum (gdbarch
)->fp0
),
5171 8, gdbarch_byte_order (gdbarch
),
5172 readbuf
, writebuf
, 0);
5173 mips_xfer_register (gdbarch
, regcache
,
5174 (gdbarch_num_regs (gdbarch
)
5175 + mips_regnum (gdbarch
)->fp0
+ 2),
5176 8, gdbarch_byte_order (gdbarch
),
5177 readbuf
? readbuf
+ 8 : readbuf
,
5178 writebuf
? writebuf
+ 8 : writebuf
, 0);
5179 return RETURN_VALUE_REGISTER_CONVENTION
;
5181 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5182 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5184 /* A single or double floating-point value that fits in FP0. */
5186 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5187 mips_xfer_register (gdbarch
, regcache
,
5188 (gdbarch_num_regs (gdbarch
)
5189 + mips_regnum (gdbarch
)->fp0
),
5191 gdbarch_byte_order (gdbarch
),
5192 readbuf
, writebuf
, 0);
5193 return RETURN_VALUE_REGISTER_CONVENTION
;
5195 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5196 && TYPE_NFIELDS (type
) <= 2
5197 && TYPE_NFIELDS (type
) >= 1
5198 && ((TYPE_NFIELDS (type
) == 1
5199 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5201 || (TYPE_NFIELDS (type
) == 2
5202 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5204 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
5205 == TYPE_CODE_FLT
))))
5207 /* A struct that contains one or two floats. Each value is part
5208 in the least significant part of their floating point
5209 register (or GPR, for soft float). */
5212 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5213 ? mips_regnum (gdbarch
)->fp0
5215 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5217 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5220 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5222 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5224 /* A 16-byte long double field goes in two consecutive
5226 mips_xfer_register (gdbarch
, regcache
,
5227 gdbarch_num_regs (gdbarch
) + regnum
,
5229 gdbarch_byte_order (gdbarch
),
5230 readbuf
, writebuf
, offset
);
5231 mips_xfer_register (gdbarch
, regcache
,
5232 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5234 gdbarch_byte_order (gdbarch
),
5235 readbuf
, writebuf
, offset
+ 8);
5238 mips_xfer_register (gdbarch
, regcache
,
5239 gdbarch_num_regs (gdbarch
) + regnum
,
5240 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5241 gdbarch_byte_order (gdbarch
),
5242 readbuf
, writebuf
, offset
);
5244 return RETURN_VALUE_REGISTER_CONVENTION
;
5246 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5247 || TYPE_CODE (type
) == TYPE_CODE_UNION
5248 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5250 /* A composite type. Extract the left justified value,
5251 regardless of the byte order. I.e. DO NOT USE
5255 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5256 offset
< TYPE_LENGTH (type
);
5257 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5259 int xfer
= register_size (gdbarch
, regnum
);
5260 if (offset
+ xfer
> TYPE_LENGTH (type
))
5261 xfer
= TYPE_LENGTH (type
) - offset
;
5263 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5264 offset
, xfer
, regnum
);
5265 mips_xfer_register (gdbarch
, regcache
,
5266 gdbarch_num_regs (gdbarch
) + regnum
,
5267 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5270 return RETURN_VALUE_REGISTER_CONVENTION
;
5274 /* A scalar extract each part but least-significant-byte
5278 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5279 offset
< TYPE_LENGTH (type
);
5280 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5282 int xfer
= register_size (gdbarch
, regnum
);
5283 if (offset
+ xfer
> TYPE_LENGTH (type
))
5284 xfer
= TYPE_LENGTH (type
) - offset
;
5286 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5287 offset
, xfer
, regnum
);
5288 mips_xfer_register (gdbarch
, regcache
,
5289 gdbarch_num_regs (gdbarch
) + regnum
,
5290 xfer
, gdbarch_byte_order (gdbarch
),
5291 readbuf
, writebuf
, offset
);
5293 return RETURN_VALUE_REGISTER_CONVENTION
;
5297 /* Which registers to use for passing floating-point values between
5298 function calls, one of floating-point, general and both kinds of
5299 registers. O32 and O64 use different register kinds for standard
5300 MIPS and MIPS16 code; to make the handling of cases where we may
5301 not know what kind of code is being used (e.g. no debug information)
5302 easier we sometimes use both kinds. */
5311 /* O32 ABI stuff. */
5314 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5315 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5316 int nargs
, struct value
**args
, CORE_ADDR sp
,
5317 int struct_return
, CORE_ADDR struct_addr
)
5323 int stack_offset
= 0;
5324 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5325 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5327 /* For shared libraries, "t9" needs to point at the function
5329 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5331 /* Set the return address register to point to the entry point of
5332 the program, where a breakpoint lies in wait. */
5333 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5335 /* First ensure that the stack and structure return address (if any)
5336 are properly aligned. The stack has to be at least 64-bit
5337 aligned even on 32-bit machines, because doubles must be 64-bit
5338 aligned. For n32 and n64, stack frames need to be 128-bit
5339 aligned, so we round to this widest known alignment. */
5341 sp
= align_down (sp
, 16);
5342 struct_addr
= align_down (struct_addr
, 16);
5344 /* Now make space on the stack for the args. */
5345 for (argnum
= 0; argnum
< nargs
; argnum
++)
5347 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5349 /* Align to double-word if necessary. */
5350 if (mips_type_needs_double_align (arg_type
))
5351 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5352 /* Allocate space on the stack. */
5353 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5355 sp
-= align_up (len
, 16);
5358 fprintf_unfiltered (gdb_stdlog
,
5359 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5360 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5362 /* Initialize the integer and float register pointers. */
5363 argreg
= MIPS_A0_REGNUM
;
5364 float_argreg
= mips_fpa0_regnum (gdbarch
);
5366 /* The struct_return pointer occupies the first parameter-passing reg. */
5370 fprintf_unfiltered (gdb_stdlog
,
5371 "mips_o32_push_dummy_call: "
5372 "struct_return reg=%d %s\n",
5373 argreg
, paddress (gdbarch
, struct_addr
));
5374 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5375 stack_offset
+= MIPS32_REGSIZE
;
5378 /* Now load as many as possible of the first arguments into
5379 registers, and push the rest onto the stack. Loop thru args
5380 from first to last. */
5381 for (argnum
= 0; argnum
< nargs
; argnum
++)
5383 const gdb_byte
*val
;
5384 struct value
*arg
= args
[argnum
];
5385 struct type
*arg_type
= check_typedef (value_type (arg
));
5386 int len
= TYPE_LENGTH (arg_type
);
5387 enum type_code typecode
= TYPE_CODE (arg_type
);
5390 fprintf_unfiltered (gdb_stdlog
,
5391 "mips_o32_push_dummy_call: %d len=%d type=%d",
5392 argnum
+ 1, len
, (int) typecode
);
5394 val
= value_contents (arg
);
5396 /* 32-bit ABIs always start floating point arguments in an
5397 even-numbered floating point register. Round the FP register
5398 up before the check to see if there are any FP registers
5399 left. O32 targets also pass the FP in the integer registers
5400 so also round up normal registers. */
5401 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5403 if ((float_argreg
& 1))
5407 /* Floating point arguments passed in registers have to be
5408 treated specially. On 32-bit architectures, doubles are
5409 passed in register pairs; the even FP register gets the
5410 low word, and the odd FP register gets the high word.
5411 On O32, the first two floating point arguments are also
5412 copied to general registers, following their memory order,
5413 because MIPS16 functions don't use float registers for
5414 arguments. This duplication of arguments in general
5415 registers can't hurt non-MIPS16 functions, because those
5416 registers are normally skipped. */
5418 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5419 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5421 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5423 int freg_offset
= gdbarch_byte_order (gdbarch
)
5424 == BFD_ENDIAN_BIG
? 1 : 0;
5425 unsigned long regval
;
5428 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5430 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5431 float_argreg
+ freg_offset
,
5433 regcache_cooked_write_unsigned (regcache
,
5434 float_argreg
++ + freg_offset
,
5437 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5438 argreg
, phex (regval
, 4));
5439 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5442 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5444 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5445 float_argreg
- freg_offset
,
5447 regcache_cooked_write_unsigned (regcache
,
5448 float_argreg
++ - freg_offset
,
5451 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5452 argreg
, phex (regval
, 4));
5453 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5457 /* This is a floating point value that fits entirely
5458 in a single register. */
5459 /* On 32 bit ABI's the float_argreg is further adjusted
5460 above to ensure that it is even register aligned. */
5461 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5463 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5464 float_argreg
, phex (regval
, len
));
5465 regcache_cooked_write_unsigned (regcache
,
5466 float_argreg
++, regval
);
5467 /* Although two FP registers are reserved for each
5468 argument, only one corresponding integer register is
5471 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5472 argreg
, phex (regval
, len
));
5473 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5475 /* Reserve space for the FP register. */
5476 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5480 /* Copy the argument to general registers or the stack in
5481 register-sized pieces. Large arguments are split between
5482 registers and stack. */
5483 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5484 are treated specially: Irix cc passes
5485 them in registers where gcc sometimes puts them on the
5486 stack. For maximum compatibility, we will put them in
5488 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5489 && len
% MIPS32_REGSIZE
!= 0);
5490 /* Structures should be aligned to eight bytes (even arg registers)
5491 on MIPS_ABI_O32, if their first member has double precision. */
5492 if (mips_type_needs_double_align (arg_type
))
5497 stack_offset
+= MIPS32_REGSIZE
;
5502 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5505 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5508 /* Write this portion of the argument to the stack. */
5509 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5510 || odd_sized_struct
)
5512 /* Should shorter than int integer values be
5513 promoted to int before being stored? */
5514 int longword_offset
= 0;
5519 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5520 paddress (gdbarch
, stack_offset
));
5521 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5522 paddress (gdbarch
, longword_offset
));
5525 addr
= sp
+ stack_offset
+ longword_offset
;
5530 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5531 paddress (gdbarch
, addr
));
5532 for (i
= 0; i
< partial_len
; i
++)
5534 fprintf_unfiltered (gdb_stdlog
, "%02x",
5538 write_memory (addr
, val
, partial_len
);
5541 /* Note!!! This is NOT an else clause. Odd sized
5542 structs may go thru BOTH paths. */
5543 /* Write this portion of the argument to a general
5544 purpose register. */
5545 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5547 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5549 /* Value may need to be sign extended, because
5550 mips_isa_regsize() != mips_abi_regsize(). */
5552 /* A non-floating-point argument being passed in a
5553 general register. If a struct or union, and if
5554 the remaining length is smaller than the register
5555 size, we have to adjust the register value on
5558 It does not seem to be necessary to do the
5559 same for integral types.
5561 Also don't do this adjustment on O64 binaries.
5563 cagney/2001-07-23: gdb/179: Also, GCC, when
5564 outputting LE O32 with sizeof (struct) <
5565 mips_abi_regsize(), generates a left shift
5566 as part of storing the argument in a register
5567 (the left shift isn't generated when
5568 sizeof (struct) >= mips_abi_regsize()). Since
5569 it is quite possible that this is GCC
5570 contradicting the LE/O32 ABI, GDB has not been
5571 adjusted to accommodate this. Either someone
5572 needs to demonstrate that the LE/O32 ABI
5573 specifies such a left shift OR this new ABI gets
5574 identified as such and GDB gets tweaked
5577 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5578 && partial_len
< MIPS32_REGSIZE
5579 && (typecode
== TYPE_CODE_STRUCT
5580 || typecode
== TYPE_CODE_UNION
))
5581 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5585 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5587 phex (regval
, MIPS32_REGSIZE
));
5588 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5591 /* Prevent subsequent floating point arguments from
5592 being passed in floating point registers. */
5593 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5599 /* Compute the offset into the stack at which we will
5600 copy the next parameter.
5602 In older ABIs, the caller reserved space for
5603 registers that contained arguments. This was loosely
5604 refered to as their "home". Consequently, space is
5605 always allocated. */
5607 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5611 fprintf_unfiltered (gdb_stdlog
, "\n");
5614 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5616 /* Return adjusted stack pointer. */
5620 static enum return_value_convention
5621 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5622 struct type
*type
, struct regcache
*regcache
,
5623 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5625 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5626 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5627 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5628 enum mips_fval_reg fval_reg
;
5630 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5631 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5632 || TYPE_CODE (type
) == TYPE_CODE_UNION
5633 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5634 return RETURN_VALUE_STRUCT_CONVENTION
;
5635 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5636 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5638 /* A single-precision floating-point value. If reading in or copying,
5639 then we get it from/put it to FP0 for standard MIPS code or GPR2
5640 for MIPS16 code. If writing out only, then we put it to both FP0
5641 and GPR2. We do not support reading in with no function known, if
5642 this safety check ever triggers, then we'll have to try harder. */
5643 gdb_assert (function
|| !readbuf
);
5648 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5651 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5653 case mips_fval_both
:
5654 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5657 if (fval_reg
!= mips_fval_gpr
)
5658 mips_xfer_register (gdbarch
, regcache
,
5659 (gdbarch_num_regs (gdbarch
)
5660 + mips_regnum (gdbarch
)->fp0
),
5662 gdbarch_byte_order (gdbarch
),
5663 readbuf
, writebuf
, 0);
5664 if (fval_reg
!= mips_fval_fpr
)
5665 mips_xfer_register (gdbarch
, regcache
,
5666 gdbarch_num_regs (gdbarch
) + 2,
5668 gdbarch_byte_order (gdbarch
),
5669 readbuf
, writebuf
, 0);
5670 return RETURN_VALUE_REGISTER_CONVENTION
;
5672 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5673 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5675 /* A double-precision floating-point value. If reading in or copying,
5676 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5677 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5678 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5679 no function known, if this safety check ever triggers, then we'll
5680 have to try harder. */
5681 gdb_assert (function
|| !readbuf
);
5686 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5689 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5691 case mips_fval_both
:
5692 fprintf_unfiltered (gdb_stderr
,
5693 "Return float in $fp1/$fp0 and $2/$3\n");
5696 if (fval_reg
!= mips_fval_gpr
)
5698 /* The most significant part goes in FP1, and the least significant
5700 switch (gdbarch_byte_order (gdbarch
))
5702 case BFD_ENDIAN_LITTLE
:
5703 mips_xfer_register (gdbarch
, regcache
,
5704 (gdbarch_num_regs (gdbarch
)
5705 + mips_regnum (gdbarch
)->fp0
+ 0),
5706 4, gdbarch_byte_order (gdbarch
),
5707 readbuf
, writebuf
, 0);
5708 mips_xfer_register (gdbarch
, regcache
,
5709 (gdbarch_num_regs (gdbarch
)
5710 + mips_regnum (gdbarch
)->fp0
+ 1),
5711 4, gdbarch_byte_order (gdbarch
),
5712 readbuf
, writebuf
, 4);
5714 case BFD_ENDIAN_BIG
:
5715 mips_xfer_register (gdbarch
, regcache
,
5716 (gdbarch_num_regs (gdbarch
)
5717 + mips_regnum (gdbarch
)->fp0
+ 1),
5718 4, gdbarch_byte_order (gdbarch
),
5719 readbuf
, writebuf
, 0);
5720 mips_xfer_register (gdbarch
, regcache
,
5721 (gdbarch_num_regs (gdbarch
)
5722 + mips_regnum (gdbarch
)->fp0
+ 0),
5723 4, gdbarch_byte_order (gdbarch
),
5724 readbuf
, writebuf
, 4);
5727 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5730 if (fval_reg
!= mips_fval_fpr
)
5732 /* The two 32-bit parts are always placed in GPR2 and GPR3
5733 following these registers' memory order. */
5734 mips_xfer_register (gdbarch
, regcache
,
5735 gdbarch_num_regs (gdbarch
) + 2,
5736 4, gdbarch_byte_order (gdbarch
),
5737 readbuf
, writebuf
, 0);
5738 mips_xfer_register (gdbarch
, regcache
,
5739 gdbarch_num_regs (gdbarch
) + 3,
5740 4, gdbarch_byte_order (gdbarch
),
5741 readbuf
, writebuf
, 4);
5743 return RETURN_VALUE_REGISTER_CONVENTION
;
5746 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5747 && TYPE_NFIELDS (type
) <= 2
5748 && TYPE_NFIELDS (type
) >= 1
5749 && ((TYPE_NFIELDS (type
) == 1
5750 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5752 || (TYPE_NFIELDS (type
) == 2
5753 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5755 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5757 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5759 /* A struct that contains one or two floats. Each value is part
5760 in the least significant part of their floating point
5764 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5765 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5767 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5770 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5772 mips_xfer_register (gdbarch
, regcache
,
5773 gdbarch_num_regs (gdbarch
) + regnum
,
5774 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5775 gdbarch_byte_order (gdbarch
),
5776 readbuf
, writebuf
, offset
);
5778 return RETURN_VALUE_REGISTER_CONVENTION
;
5782 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5783 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5785 /* A structure or union. Extract the left justified value,
5786 regardless of the byte order. I.e. DO NOT USE
5790 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5791 offset
< TYPE_LENGTH (type
);
5792 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5794 int xfer
= register_size (gdbarch
, regnum
);
5795 if (offset
+ xfer
> TYPE_LENGTH (type
))
5796 xfer
= TYPE_LENGTH (type
) - offset
;
5798 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5799 offset
, xfer
, regnum
);
5800 mips_xfer_register (gdbarch
, regcache
,
5801 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5802 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5804 return RETURN_VALUE_REGISTER_CONVENTION
;
5809 /* A scalar extract each part but least-significant-byte
5810 justified. o32 thinks registers are 4 byte, regardless of
5814 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5815 offset
< TYPE_LENGTH (type
);
5816 offset
+= MIPS32_REGSIZE
, regnum
++)
5818 int xfer
= MIPS32_REGSIZE
;
5819 if (offset
+ xfer
> TYPE_LENGTH (type
))
5820 xfer
= TYPE_LENGTH (type
) - offset
;
5822 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5823 offset
, xfer
, regnum
);
5824 mips_xfer_register (gdbarch
, regcache
,
5825 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5826 gdbarch_byte_order (gdbarch
),
5827 readbuf
, writebuf
, offset
);
5829 return RETURN_VALUE_REGISTER_CONVENTION
;
5833 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5837 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5838 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5840 struct value
**args
, CORE_ADDR sp
,
5841 int struct_return
, CORE_ADDR struct_addr
)
5847 int stack_offset
= 0;
5848 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5849 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5851 /* For shared libraries, "t9" needs to point at the function
5853 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5855 /* Set the return address register to point to the entry point of
5856 the program, where a breakpoint lies in wait. */
5857 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5859 /* First ensure that the stack and structure return address (if any)
5860 are properly aligned. The stack has to be at least 64-bit
5861 aligned even on 32-bit machines, because doubles must be 64-bit
5862 aligned. For n32 and n64, stack frames need to be 128-bit
5863 aligned, so we round to this widest known alignment. */
5865 sp
= align_down (sp
, 16);
5866 struct_addr
= align_down (struct_addr
, 16);
5868 /* Now make space on the stack for the args. */
5869 for (argnum
= 0; argnum
< nargs
; argnum
++)
5871 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5873 /* Allocate space on the stack. */
5874 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5876 sp
-= align_up (len
, 16);
5879 fprintf_unfiltered (gdb_stdlog
,
5880 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5881 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5883 /* Initialize the integer and float register pointers. */
5884 argreg
= MIPS_A0_REGNUM
;
5885 float_argreg
= mips_fpa0_regnum (gdbarch
);
5887 /* The struct_return pointer occupies the first parameter-passing reg. */
5891 fprintf_unfiltered (gdb_stdlog
,
5892 "mips_o64_push_dummy_call: "
5893 "struct_return reg=%d %s\n",
5894 argreg
, paddress (gdbarch
, struct_addr
));
5895 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5896 stack_offset
+= MIPS64_REGSIZE
;
5899 /* Now load as many as possible of the first arguments into
5900 registers, and push the rest onto the stack. Loop thru args
5901 from first to last. */
5902 for (argnum
= 0; argnum
< nargs
; argnum
++)
5904 const gdb_byte
*val
;
5905 struct value
*arg
= args
[argnum
];
5906 struct type
*arg_type
= check_typedef (value_type (arg
));
5907 int len
= TYPE_LENGTH (arg_type
);
5908 enum type_code typecode
= TYPE_CODE (arg_type
);
5911 fprintf_unfiltered (gdb_stdlog
,
5912 "mips_o64_push_dummy_call: %d len=%d type=%d",
5913 argnum
+ 1, len
, (int) typecode
);
5915 val
= value_contents (arg
);
5917 /* Floating point arguments passed in registers have to be
5918 treated specially. On 32-bit architectures, doubles are
5919 passed in register pairs; the even FP register gets the
5920 low word, and the odd FP register gets the high word.
5921 On O64, the first two floating point arguments are also
5922 copied to general registers, because MIPS16 functions
5923 don't use float registers for arguments. This duplication
5924 of arguments in general registers can't hurt non-MIPS16
5925 functions because those registers are normally skipped. */
5927 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5928 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5930 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5932 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5933 float_argreg
, phex (regval
, len
));
5934 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5936 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5937 argreg
, phex (regval
, len
));
5938 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5940 /* Reserve space for the FP register. */
5941 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5945 /* Copy the argument to general registers or the stack in
5946 register-sized pieces. Large arguments are split between
5947 registers and stack. */
5948 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5949 are treated specially: Irix cc passes them in registers
5950 where gcc sometimes puts them on the stack. For maximum
5951 compatibility, we will put them in both places. */
5952 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5953 && len
% MIPS64_REGSIZE
!= 0);
5956 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5959 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5962 /* Write this portion of the argument to the stack. */
5963 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5964 || odd_sized_struct
)
5966 /* Should shorter than int integer values be
5967 promoted to int before being stored? */
5968 int longword_offset
= 0;
5970 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5972 if ((typecode
== TYPE_CODE_INT
5973 || typecode
== TYPE_CODE_PTR
5974 || typecode
== TYPE_CODE_FLT
)
5976 longword_offset
= MIPS64_REGSIZE
- len
;
5981 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5982 paddress (gdbarch
, stack_offset
));
5983 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5984 paddress (gdbarch
, longword_offset
));
5987 addr
= sp
+ stack_offset
+ longword_offset
;
5992 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5993 paddress (gdbarch
, addr
));
5994 for (i
= 0; i
< partial_len
; i
++)
5996 fprintf_unfiltered (gdb_stdlog
, "%02x",
6000 write_memory (addr
, val
, partial_len
);
6003 /* Note!!! This is NOT an else clause. Odd sized
6004 structs may go thru BOTH paths. */
6005 /* Write this portion of the argument to a general
6006 purpose register. */
6007 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
6009 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6011 /* Value may need to be sign extended, because
6012 mips_isa_regsize() != mips_abi_regsize(). */
6014 /* A non-floating-point argument being passed in a
6015 general register. If a struct or union, and if
6016 the remaining length is smaller than the register
6017 size, we have to adjust the register value on
6020 It does not seem to be necessary to do the
6021 same for integral types. */
6023 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6024 && partial_len
< MIPS64_REGSIZE
6025 && (typecode
== TYPE_CODE_STRUCT
6026 || typecode
== TYPE_CODE_UNION
))
6027 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6031 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
6033 phex (regval
, MIPS64_REGSIZE
));
6034 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6037 /* Prevent subsequent floating point arguments from
6038 being passed in floating point registers. */
6039 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
6045 /* Compute the offset into the stack at which we will
6046 copy the next parameter.
6048 In older ABIs, the caller reserved space for
6049 registers that contained arguments. This was loosely
6050 refered to as their "home". Consequently, space is
6051 always allocated. */
6053 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6057 fprintf_unfiltered (gdb_stdlog
, "\n");
6060 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6062 /* Return adjusted stack pointer. */
6066 static enum return_value_convention
6067 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6068 struct type
*type
, struct regcache
*regcache
,
6069 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6071 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6072 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6073 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6074 enum mips_fval_reg fval_reg
;
6076 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6077 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
6078 || TYPE_CODE (type
) == TYPE_CODE_UNION
6079 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
6080 return RETURN_VALUE_STRUCT_CONVENTION
;
6081 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
6083 /* A floating-point value. If reading in or copying, then we get it
6084 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6085 If writing out only, then we put it to both FP0 and GPR2. We do
6086 not support reading in with no function known, if this safety
6087 check ever triggers, then we'll have to try harder. */
6088 gdb_assert (function
|| !readbuf
);
6093 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6096 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6098 case mips_fval_both
:
6099 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6102 if (fval_reg
!= mips_fval_gpr
)
6103 mips_xfer_register (gdbarch
, regcache
,
6104 (gdbarch_num_regs (gdbarch
)
6105 + mips_regnum (gdbarch
)->fp0
),
6107 gdbarch_byte_order (gdbarch
),
6108 readbuf
, writebuf
, 0);
6109 if (fval_reg
!= mips_fval_fpr
)
6110 mips_xfer_register (gdbarch
, regcache
,
6111 gdbarch_num_regs (gdbarch
) + 2,
6113 gdbarch_byte_order (gdbarch
),
6114 readbuf
, writebuf
, 0);
6115 return RETURN_VALUE_REGISTER_CONVENTION
;
6119 /* A scalar extract each part but least-significant-byte
6123 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6124 offset
< TYPE_LENGTH (type
);
6125 offset
+= MIPS64_REGSIZE
, regnum
++)
6127 int xfer
= MIPS64_REGSIZE
;
6128 if (offset
+ xfer
> TYPE_LENGTH (type
))
6129 xfer
= TYPE_LENGTH (type
) - offset
;
6131 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6132 offset
, xfer
, regnum
);
6133 mips_xfer_register (gdbarch
, regcache
,
6134 gdbarch_num_regs (gdbarch
) + regnum
,
6135 xfer
, gdbarch_byte_order (gdbarch
),
6136 readbuf
, writebuf
, offset
);
6138 return RETURN_VALUE_REGISTER_CONVENTION
;
6142 /* Floating point register management.
6144 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6145 64bit operations, these early MIPS cpus treat fp register pairs
6146 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6147 registers and offer a compatibility mode that emulates the MIPS2 fp
6148 model. When operating in MIPS2 fp compat mode, later cpu's split
6149 double precision floats into two 32-bit chunks and store them in
6150 consecutive fp regs. To display 64-bit floats stored in this
6151 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6152 Throw in user-configurable endianness and you have a real mess.
6154 The way this works is:
6155 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6156 double-precision value will be split across two logical registers.
6157 The lower-numbered logical register will hold the low-order bits,
6158 regardless of the processor's endianness.
6159 - If we are on a 64-bit processor, and we are looking for a
6160 single-precision value, it will be in the low ordered bits
6161 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6162 save slot in memory.
6163 - If we are in 64-bit mode, everything is straightforward.
6165 Note that this code only deals with "live" registers at the top of the
6166 stack. We will attempt to deal with saved registers later, when
6167 the raw/cooked register interface is in place. (We need a general
6168 interface that can deal with dynamic saved register sizes -- fp
6169 regs could be 32 bits wide in one frame and 64 on the frame above
6172 /* Copy a 32-bit single-precision value from the current frame
6173 into rare_buffer. */
6176 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6177 gdb_byte
*rare_buffer
)
6179 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6180 int raw_size
= register_size (gdbarch
, regno
);
6181 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6183 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6184 error (_("can't read register %d (%s)"),
6185 regno
, gdbarch_register_name (gdbarch
, regno
));
6188 /* We have a 64-bit value for this register. Find the low-order
6192 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6197 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6201 memcpy (rare_buffer
, raw_buffer
, 4);
6205 /* Copy a 64-bit double-precision value from the current frame into
6206 rare_buffer. This may include getting half of it from the next
6210 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6211 gdb_byte
*rare_buffer
)
6213 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6214 int raw_size
= register_size (gdbarch
, regno
);
6216 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6218 /* We have a 64-bit value for this register, and we should use
6220 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6221 error (_("can't read register %d (%s)"),
6222 regno
, gdbarch_register_name (gdbarch
, regno
));
6226 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6228 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6229 internal_error (__FILE__
, __LINE__
,
6230 _("mips_read_fp_register_double: bad access to "
6231 "odd-numbered FP register"));
6233 /* mips_read_fp_register_single will find the correct 32 bits from
6235 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6237 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6238 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6242 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6243 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6249 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6251 { /* Do values for FP (float) regs. */
6252 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6253 gdb_byte
*raw_buffer
;
6254 double doub
, flt1
; /* Doubles extracted from raw hex data. */
6259 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6261 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6262 fprintf_filtered (file
, "%*s",
6263 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6266 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6268 struct value_print_options opts
;
6270 /* 4-byte registers: Print hex and floating. Also print even
6271 numbered registers as doubles. */
6272 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6273 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6276 get_formatted_print_options (&opts
, 'x');
6277 print_scalar_formatted (raw_buffer
,
6278 builtin_type (gdbarch
)->builtin_uint32
,
6281 fprintf_filtered (file
, " flt: ");
6283 fprintf_filtered (file
, " <invalid float> ");
6285 fprintf_filtered (file
, "%-17.9g", flt1
);
6287 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6289 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6290 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6293 fprintf_filtered (file
, " dbl: ");
6295 fprintf_filtered (file
, "<invalid double>");
6297 fprintf_filtered (file
, "%-24.17g", doub
);
6302 struct value_print_options opts
;
6304 /* Eight byte registers: print each one as hex, float and double. */
6305 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6306 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6309 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6310 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6313 get_formatted_print_options (&opts
, 'x');
6314 print_scalar_formatted (raw_buffer
,
6315 builtin_type (gdbarch
)->builtin_uint64
,
6318 fprintf_filtered (file
, " flt: ");
6320 fprintf_filtered (file
, "<invalid float>");
6322 fprintf_filtered (file
, "%-17.9g", flt1
);
6324 fprintf_filtered (file
, " dbl: ");
6326 fprintf_filtered (file
, "<invalid double>");
6328 fprintf_filtered (file
, "%-24.17g", doub
);
6333 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6336 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6337 struct value_print_options opts
;
6340 if (mips_float_register_p (gdbarch
, regnum
))
6342 mips_print_fp_register (file
, frame
, regnum
);
6346 val
= get_frame_register_value (frame
, regnum
);
6348 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6350 /* The problem with printing numeric register names (r26, etc.) is that
6351 the user can't use them on input. Probably the best solution is to
6352 fix it so that either the numeric or the funky (a2, etc.) names
6353 are accepted on input. */
6354 if (regnum
< MIPS_NUMREGS
)
6355 fprintf_filtered (file
, "(r%d): ", regnum
);
6357 fprintf_filtered (file
, ": ");
6359 get_formatted_print_options (&opts
, 'x');
6360 val_print_scalar_formatted (value_type (val
),
6361 value_embedded_offset (val
),
6366 /* Print IEEE exception condition bits in FLAGS. */
6369 print_fpu_flags (struct ui_file
*file
, int flags
)
6371 if (flags
& (1 << 0))
6372 fputs_filtered (" inexact", file
);
6373 if (flags
& (1 << 1))
6374 fputs_filtered (" uflow", file
);
6375 if (flags
& (1 << 2))
6376 fputs_filtered (" oflow", file
);
6377 if (flags
& (1 << 3))
6378 fputs_filtered (" div0", file
);
6379 if (flags
& (1 << 4))
6380 fputs_filtered (" inval", file
);
6381 if (flags
& (1 << 5))
6382 fputs_filtered (" unimp", file
);
6383 fputc_filtered ('\n', file
);
6386 /* Print interesting information about the floating point processor
6387 (if present) or emulator. */
6390 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6391 struct frame_info
*frame
, const char *args
)
6393 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6394 enum mips_fpu_type type
= MIPS_FPU_TYPE (gdbarch
);
6398 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6399 type
= MIPS_FPU_NONE
;
6401 fprintf_filtered (file
, "fpu type: %s\n",
6402 type
== MIPS_FPU_DOUBLE
? "double-precision"
6403 : type
== MIPS_FPU_SINGLE
? "single-precision"
6406 if (type
== MIPS_FPU_NONE
)
6409 fprintf_filtered (file
, "reg size: %d bits\n",
6410 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6412 fputs_filtered ("cond :", file
);
6413 if (fcs
& (1 << 23))
6414 fputs_filtered (" 0", file
);
6415 for (i
= 1; i
<= 7; i
++)
6416 if (fcs
& (1 << (24 + i
)))
6417 fprintf_filtered (file
, " %d", i
);
6418 fputc_filtered ('\n', file
);
6420 fputs_filtered ("cause :", file
);
6421 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6422 fputs ("mask :", stdout
);
6423 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6424 fputs ("flags :", stdout
);
6425 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6427 fputs_filtered ("rounding: ", file
);
6430 case 0: fputs_filtered ("nearest\n", file
); break;
6431 case 1: fputs_filtered ("zero\n", file
); break;
6432 case 2: fputs_filtered ("+inf\n", file
); break;
6433 case 3: fputs_filtered ("-inf\n", file
); break;
6436 fputs_filtered ("flush :", file
);
6437 if (fcs
& (1 << 21))
6438 fputs_filtered (" nearest", file
);
6439 if (fcs
& (1 << 22))
6440 fputs_filtered (" override", file
);
6441 if (fcs
& (1 << 24))
6442 fputs_filtered (" zero", file
);
6443 if ((fcs
& (0xb << 21)) == 0)
6444 fputs_filtered (" no", file
);
6445 fputc_filtered ('\n', file
);
6447 fprintf_filtered (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6448 fprintf_filtered (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6449 fputc_filtered ('\n', file
);
6451 default_print_float_info (gdbarch
, file
, frame
, args
);
6454 /* Replacement for generic do_registers_info.
6455 Print regs in pretty columns. */
6458 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6461 fprintf_filtered (file
, " ");
6462 mips_print_fp_register (file
, frame
, regnum
);
6463 fprintf_filtered (file
, "\n");
6468 /* Print a row's worth of GP (int) registers, with name labels above. */
6471 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6474 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6475 /* Do values for GP (int) regs. */
6476 const gdb_byte
*raw_buffer
;
6477 struct value
*value
;
6478 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6483 /* For GP registers, we print a separate row of names above the vals. */
6484 for (col
= 0, regnum
= start_regnum
;
6485 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6486 + gdbarch_num_pseudo_regs (gdbarch
);
6489 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6490 continue; /* unused register */
6491 if (mips_float_register_p (gdbarch
, regnum
))
6492 break; /* End the row: reached FP register. */
6493 /* Large registers are handled separately. */
6494 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6497 break; /* End the row before this register. */
6499 /* Print this register on a row by itself. */
6500 mips_print_register (file
, frame
, regnum
);
6501 fprintf_filtered (file
, "\n");
6505 fprintf_filtered (file
, " ");
6506 fprintf_filtered (file
,
6507 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6508 gdbarch_register_name (gdbarch
, regnum
));
6515 /* Print the R0 to R31 names. */
6516 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6517 fprintf_filtered (file
, "\n R%-4d",
6518 start_regnum
% gdbarch_num_regs (gdbarch
));
6520 fprintf_filtered (file
, "\n ");
6522 /* Now print the values in hex, 4 or 8 to the row. */
6523 for (col
= 0, regnum
= start_regnum
;
6524 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6525 + gdbarch_num_pseudo_regs (gdbarch
);
6528 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6529 continue; /* unused register */
6530 if (mips_float_register_p (gdbarch
, regnum
))
6531 break; /* End row: reached FP register. */
6532 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6533 break; /* End row: large register. */
6535 /* OK: get the data in raw format. */
6536 value
= get_frame_register_value (frame
, regnum
);
6537 if (value_optimized_out (value
)
6538 || !value_entirely_available (value
))
6539 error (_("can't read register %d (%s)"),
6540 regnum
, gdbarch_register_name (gdbarch
, regnum
));
6541 raw_buffer
= value_contents_all (value
);
6542 /* pad small registers */
6544 byte
< (mips_abi_regsize (gdbarch
)
6545 - register_size (gdbarch
, regnum
)); byte
++)
6546 fprintf_filtered (file
, " ");
6547 /* Now print the register value in hex, endian order. */
6548 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6550 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6551 byte
< register_size (gdbarch
, regnum
); byte
++)
6552 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6554 for (byte
= register_size (gdbarch
, regnum
) - 1;
6556 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6557 fprintf_filtered (file
, " ");
6560 if (col
> 0) /* ie. if we actually printed anything... */
6561 fprintf_filtered (file
, "\n");
6566 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6569 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6570 struct frame_info
*frame
, int regnum
, int all
)
6572 if (regnum
!= -1) /* Do one specified register. */
6574 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6575 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6576 error (_("Not a valid register for the current processor type"));
6578 mips_print_register (file
, frame
, regnum
);
6579 fprintf_filtered (file
, "\n");
6582 /* Do all (or most) registers. */
6584 regnum
= gdbarch_num_regs (gdbarch
);
6585 while (regnum
< gdbarch_num_regs (gdbarch
)
6586 + gdbarch_num_pseudo_regs (gdbarch
))
6588 if (mips_float_register_p (gdbarch
, regnum
))
6590 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6591 regnum
= print_fp_register_row (file
, frame
, regnum
);
6593 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6596 regnum
= print_gp_register_row (file
, frame
, regnum
);
6602 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6603 struct frame_info
*frame
)
6605 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6606 CORE_ADDR pc
= get_frame_pc (frame
);
6607 struct address_space
*aspace
;
6613 if ((mips_pc_is_mips (pc
)
6614 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6615 || (mips_pc_is_micromips (gdbarch
, pc
)
6616 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6617 || (mips_pc_is_mips16 (gdbarch
, pc
)
6618 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6621 isa
= mips_pc_isa (gdbarch
, pc
);
6622 /* _has_delay_slot above will have validated the read. */
6623 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6624 size
= mips_insn_size (isa
, insn
);
6625 aspace
= get_frame_address_space (frame
);
6626 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6629 /* To skip prologues, I use this predicate. Returns either PC itself
6630 if the code at PC does not look like a function prologue; otherwise
6631 returns an address that (if we're lucky) follows the prologue. If
6632 LENIENT, then we must skip everything which is involved in setting
6633 up the frame (it's OK to skip more, just so long as we don't skip
6634 anything which might clobber the registers which are being saved.
6635 We must skip more in the case where part of the prologue is in the
6636 delay slot of a non-prologue instruction). */
6639 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6642 CORE_ADDR func_addr
;
6644 /* See if we can determine the end of the prologue via the symbol table.
6645 If so, then return either PC, or the PC after the prologue, whichever
6647 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6649 CORE_ADDR post_prologue_pc
6650 = skip_prologue_using_sal (gdbarch
, func_addr
);
6651 if (post_prologue_pc
!= 0)
6652 return std::max (pc
, post_prologue_pc
);
6655 /* Can't determine prologue from the symbol table, need to examine
6658 /* Find an upper limit on the function prologue using the debug
6659 information. If the debug information could not be used to provide
6660 that bound, then use an arbitrary large number as the upper bound. */
6661 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6663 limit_pc
= pc
+ 100; /* Magic. */
6665 if (mips_pc_is_mips16 (gdbarch
, pc
))
6666 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6667 else if (mips_pc_is_micromips (gdbarch
, pc
))
6668 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6670 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6673 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6674 This is a helper function for mips_stack_frame_destroyed_p. */
6677 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6679 CORE_ADDR func_addr
= 0, func_end
= 0;
6681 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6683 /* The MIPS epilogue is max. 12 bytes long. */
6684 CORE_ADDR addr
= func_end
- 12;
6686 if (addr
< func_addr
+ 4)
6687 addr
= func_addr
+ 4;
6691 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6693 unsigned long high_word
;
6696 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6697 high_word
= (inst
>> 16) & 0xffff;
6699 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6700 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6701 && inst
!= 0x03e00008 /* jr $ra */
6702 && inst
!= 0x00000000) /* nop */
6712 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6713 This is a helper function for mips_stack_frame_destroyed_p. */
6716 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6718 CORE_ADDR func_addr
= 0;
6719 CORE_ADDR func_end
= 0;
6727 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6730 /* The microMIPS epilogue is max. 12 bytes long. */
6731 addr
= func_end
- 12;
6733 if (addr
< func_addr
+ 2)
6734 addr
= func_addr
+ 2;
6738 for (; pc
< func_end
; pc
+= loc
)
6741 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6742 loc
+= MIPS_INSN16_SIZE
;
6743 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6745 /* 32-bit instructions. */
6746 case 2 * MIPS_INSN16_SIZE
:
6748 insn
|= mips_fetch_instruction (gdbarch
,
6749 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6750 loc
+= MIPS_INSN16_SIZE
;
6751 switch (micromips_op (insn
>> 16))
6753 case 0xc: /* ADDIU: bits 001100 */
6754 case 0x17: /* DADDIU: bits 010111 */
6755 sreg
= b0s5_reg (insn
>> 16);
6756 dreg
= b5s5_reg (insn
>> 16);
6757 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6758 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6759 /* (D)ADDIU $sp, imm */
6769 /* 16-bit instructions. */
6770 case MIPS_INSN16_SIZE
:
6771 switch (micromips_op (insn
))
6773 case 0x3: /* MOVE: bits 000011 */
6774 sreg
= b0s5_reg (insn
);
6775 dreg
= b5s5_reg (insn
);
6776 if (sreg
== 0 && dreg
== 0)
6777 /* MOVE $zero, $zero aka NOP */
6781 case 0x11: /* POOL16C: bits 010001 */
6782 if (b5s5_op (insn
) == 0x18
6783 /* JRADDIUSP: bits 010011 11000 */
6784 || (b5s5_op (insn
) == 0xd
6785 /* JRC: bits 010011 01101 */
6786 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6791 case 0x13: /* POOL16D: bits 010011 */
6792 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6793 if ((insn
& 0x1) == 0x1
6794 /* ADDIUSP: bits 010011 1 */
6808 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6809 This is a helper function for mips_stack_frame_destroyed_p. */
6812 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6814 CORE_ADDR func_addr
= 0, func_end
= 0;
6816 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6818 /* The MIPS epilogue is max. 12 bytes long. */
6819 CORE_ADDR addr
= func_end
- 12;
6821 if (addr
< func_addr
+ 4)
6822 addr
= func_addr
+ 4;
6826 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6828 unsigned short inst
;
6830 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6832 if ((inst
& 0xf800) == 0xf000) /* extend */
6835 if (inst
!= 0x6300 /* addiu $sp,offset */
6836 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6837 && inst
!= 0xe820 /* jr $ra */
6838 && inst
!= 0xe8a0 /* jrc $ra */
6839 && inst
!= 0x6500) /* nop */
6849 /* Implement the stack_frame_destroyed_p gdbarch method.
6851 The epilogue is defined here as the area at the end of a function,
6852 after an instruction which destroys the function's stack frame. */
6855 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6857 if (mips_pc_is_mips16 (gdbarch
, pc
))
6858 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6859 else if (mips_pc_is_micromips (gdbarch
, pc
))
6860 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6862 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6865 /* Root of all "set mips "/"show mips " commands. This will eventually be
6866 used for all MIPS-specific commands. */
6869 show_mips_command (char *args
, int from_tty
)
6871 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6875 set_mips_command (char *args
, int from_tty
)
6878 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6879 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6882 /* Commands to show/set the MIPS FPU type. */
6885 show_mipsfpu_command (char *args
, int from_tty
)
6889 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6892 ("The MIPS floating-point coprocessor is unknown "
6893 "because the current architecture is not MIPS.\n");
6897 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6899 case MIPS_FPU_SINGLE
:
6900 fpu
= "single-precision";
6902 case MIPS_FPU_DOUBLE
:
6903 fpu
= "double-precision";
6906 fpu
= "absent (none)";
6909 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6911 if (mips_fpu_type_auto
)
6912 printf_unfiltered ("The MIPS floating-point coprocessor "
6913 "is set automatically (currently %s)\n",
6917 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6922 set_mipsfpu_command (char *args
, int from_tty
)
6924 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6925 "\"single\",\"none\" or \"auto\".\n");
6926 show_mipsfpu_command (args
, from_tty
);
6930 set_mipsfpu_single_command (char *args
, int from_tty
)
6932 struct gdbarch_info info
;
6933 gdbarch_info_init (&info
);
6934 mips_fpu_type
= MIPS_FPU_SINGLE
;
6935 mips_fpu_type_auto
= 0;
6936 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6937 instead of relying on globals. Doing that would let generic code
6938 handle the search for this specific architecture. */
6939 if (!gdbarch_update_p (info
))
6940 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6944 set_mipsfpu_double_command (char *args
, int from_tty
)
6946 struct gdbarch_info info
;
6947 gdbarch_info_init (&info
);
6948 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6949 mips_fpu_type_auto
= 0;
6950 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6951 instead of relying on globals. Doing that would let generic code
6952 handle the search for this specific architecture. */
6953 if (!gdbarch_update_p (info
))
6954 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6958 set_mipsfpu_none_command (char *args
, int from_tty
)
6960 struct gdbarch_info info
;
6961 gdbarch_info_init (&info
);
6962 mips_fpu_type
= MIPS_FPU_NONE
;
6963 mips_fpu_type_auto
= 0;
6964 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6965 instead of relying on globals. Doing that would let generic code
6966 handle the search for this specific architecture. */
6967 if (!gdbarch_update_p (info
))
6968 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6972 set_mipsfpu_auto_command (char *args
, int from_tty
)
6974 mips_fpu_type_auto
= 1;
6977 /* Just like reinit_frame_cache, but with the right arguments to be
6978 callable as an sfunc. */
6981 reinit_frame_cache_sfunc (char *args
, int from_tty
,
6982 struct cmd_list_element
*c
)
6984 reinit_frame_cache ();
6988 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6990 gdb_disassembler
*di
6991 = static_cast<gdb_disassembler
*>(info
->application_data
);
6992 struct gdbarch
*gdbarch
= di
->arch ();
6994 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6995 disassembler needs to be able to locally determine the ISA, and
6996 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6998 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6999 info
->mach
= bfd_mach_mips16
;
7000 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
7001 info
->mach
= bfd_mach_mips_micromips
;
7003 /* Round down the instruction address to the appropriate boundary. */
7004 memaddr
&= (info
->mach
== bfd_mach_mips16
7005 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7007 /* Set the disassembler options. */
7008 if (!info
->disassembler_options
)
7009 /* This string is not recognized explicitly by the disassembler,
7010 but it tells the disassembler to not try to guess the ABI from
7011 the bfd elf headers, such that, if the user overrides the ABI
7012 of a program linked as NewABI, the disassembly will follow the
7013 register naming conventions specified by the user. */
7014 info
->disassembler_options
= "gpr-names=32";
7016 /* Call the appropriate disassembler based on the target endian-ness. */
7017 if (info
->endian
== BFD_ENDIAN_BIG
)
7018 return print_insn_big_mips (memaddr
, info
);
7020 return print_insn_little_mips (memaddr
, info
);
7024 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
7026 /* Set up the disassembler info, so that we get the right
7027 register names from libopcodes. */
7028 info
->disassembler_options
= "gpr-names=n32";
7029 info
->flavour
= bfd_target_elf_flavour
;
7031 return gdb_print_insn_mips (memaddr
, info
);
7035 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
7037 /* Set up the disassembler info, so that we get the right
7038 register names from libopcodes. */
7039 info
->disassembler_options
= "gpr-names=64";
7040 info
->flavour
= bfd_target_elf_flavour
;
7042 return gdb_print_insn_mips (memaddr
, info
);
7045 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7048 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7050 CORE_ADDR pc
= *pcptr
;
7052 if (mips_pc_is_mips16 (gdbarch
, pc
))
7054 *pcptr
= unmake_compact_addr (pc
);
7055 return MIPS_BP_KIND_MIPS16
;
7057 else if (mips_pc_is_micromips (gdbarch
, pc
))
7062 *pcptr
= unmake_compact_addr (pc
);
7063 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7064 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7065 return MIPS_BP_KIND_MICROMIPS16
;
7067 return MIPS_BP_KIND_MICROMIPS32
;
7070 return MIPS_BP_KIND_MIPS32
;
7073 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7075 static const gdb_byte
*
7076 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7078 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7082 case MIPS_BP_KIND_MIPS16
:
7084 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7085 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7088 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7089 return mips16_big_breakpoint
;
7091 return mips16_little_breakpoint
;
7093 case MIPS_BP_KIND_MICROMIPS16
:
7095 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7096 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7100 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7101 return micromips16_big_breakpoint
;
7103 return micromips16_little_breakpoint
;
7105 case MIPS_BP_KIND_MICROMIPS32
:
7107 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7108 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7111 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7112 return micromips32_big_breakpoint
;
7114 return micromips32_little_breakpoint
;
7116 case MIPS_BP_KIND_MIPS32
:
7118 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7119 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7122 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7123 return big_breakpoint
;
7125 return little_breakpoint
;
7128 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7132 /* Return non-zero if the standard MIPS instruction INST has a branch
7133 delay slot (i.e. it is a jump or branch instruction). This function
7134 is based on mips32_next_pc. */
7137 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7143 op
= itype_op (inst
);
7144 if ((inst
& 0xe0000000) != 0)
7146 rs
= itype_rs (inst
);
7147 rt
= itype_rt (inst
);
7148 return (is_octeon_bbit_op (op
, gdbarch
)
7149 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7150 || op
== 29 /* JALX: bits 011101 */
7153 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7154 || (rs
== 9 && (rt
& 0x2) == 0)
7155 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7156 || (rs
== 10 && (rt
& 0x2) == 0))));
7157 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7160 switch (op
& 0x07) /* extract bits 28,27,26 */
7162 case 0: /* SPECIAL */
7163 op
= rtype_funct (inst
);
7164 return (op
== 8 /* JR */
7165 || op
== 9); /* JALR */
7166 break; /* end SPECIAL */
7167 case 1: /* REGIMM */
7168 rs
= itype_rs (inst
);
7169 rt
= itype_rt (inst
); /* branch condition */
7170 return ((rt
& 0xc) == 0
7171 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7172 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7173 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7174 /* BPOSGE32, BPOSGE64: bits 1110x */
7175 break; /* end REGIMM */
7176 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7182 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7183 delay slot (i.e. it is a jump or branch instruction). */
7186 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7191 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7195 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7198 /* Return non-zero if the microMIPS instruction INSN, comprising the
7199 16-bit major opcode word in the high 16 bits and any second word
7200 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7201 jump or branch instruction). The instruction must be 32-bit if
7202 MUSTBE32 is set or can be any instruction otherwise. */
7205 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7207 ULONGEST major
= insn
>> 16;
7209 switch (micromips_op (major
))
7211 /* 16-bit instructions. */
7212 case 0x33: /* B16: bits 110011 */
7213 case 0x2b: /* BNEZ16: bits 101011 */
7214 case 0x23: /* BEQZ16: bits 100011 */
7216 case 0x11: /* POOL16C: bits 010001 */
7218 && ((b5s5_op (major
) == 0xc
7219 /* JR16: bits 010001 01100 */
7220 || (b5s5_op (major
) & 0x1e) == 0xe)));
7221 /* JALR16, JALRS16: bits 010001 0111x */
7222 /* 32-bit instructions. */
7223 case 0x3d: /* JAL: bits 111101 */
7224 case 0x3c: /* JALX: bits 111100 */
7225 case 0x35: /* J: bits 110101 */
7226 case 0x2d: /* BNE: bits 101101 */
7227 case 0x25: /* BEQ: bits 100101 */
7228 case 0x1d: /* JALS: bits 011101 */
7230 case 0x10: /* POOL32I: bits 010000 */
7231 return ((b5s5_op (major
) & 0x1c) == 0x0
7232 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7233 || (b5s5_op (major
) & 0x1d) == 0x4
7234 /* BLEZ, BGTZ: bits 010000 001x0 */
7235 || (b5s5_op (major
) & 0x1d) == 0x11
7236 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7237 || ((b5s5_op (major
) & 0x1e) == 0x14
7238 && (major
& 0x3) == 0x0)
7239 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7240 || (b5s5_op (major
) & 0x1e) == 0x1a
7241 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7242 || ((b5s5_op (major
) & 0x1e) == 0x1c
7243 && (major
& 0x3) == 0x0)
7244 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7245 || ((b5s5_op (major
) & 0x1c) == 0x1c
7246 && (major
& 0x3) == 0x1));
7247 /* BC1ANY*: bits 010000 111xx xxx01 */
7248 case 0x0: /* POOL32A: bits 000000 */
7249 return (b0s6_op (insn
) == 0x3c
7250 /* POOL32Axf: bits 000000 ... 111100 */
7251 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7252 /* JALR, JALR.HB: 000000 000x111100 111100 */
7253 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7259 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7260 slot (i.e. it is a non-compact jump instruction). The instruction
7261 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7264 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7265 CORE_ADDR addr
, int mustbe32
)
7271 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7274 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7276 if (size
== 2 * MIPS_INSN16_SIZE
)
7278 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7283 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7286 /* Return non-zero if the MIPS16 instruction INST, which must be
7287 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7288 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7289 instruction). This function is based on mips16_next_pc. */
7292 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7294 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7296 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7299 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7300 slot (i.e. it is a non-compact jump instruction). The instruction
7301 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7304 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7305 CORE_ADDR addr
, int mustbe32
)
7307 unsigned short insn
;
7310 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7314 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7317 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7318 This assumes KSSEG exists. */
7321 mips_segment_boundary (CORE_ADDR bpaddr
)
7323 CORE_ADDR mask
= CORE_ADDR_MAX
;
7326 if (sizeof (CORE_ADDR
) == 8)
7327 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7328 a compiler warning produced where CORE_ADDR is a 32-bit type even
7329 though in that case this is dead code). */
7330 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7333 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7334 segsize
= 29; /* 32-bit compatibility segment */
7336 segsize
= 62; /* xkseg */
7338 case 2: /* xkphys */
7341 default: /* xksseg (1), xkuseg/kuseg (0) */
7345 else if (bpaddr
& 0x80000000) /* kernel segment */
7348 segsize
= 31; /* user segment */
7350 return bpaddr
& mask
;
7353 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7354 it backwards if necessary. Return the address of the new location. */
7357 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7359 CORE_ADDR prev_addr
;
7361 CORE_ADDR func_addr
;
7363 /* If a breakpoint is set on the instruction in a branch delay slot,
7364 GDB gets confused. When the breakpoint is hit, the PC isn't on
7365 the instruction in the branch delay slot, the PC will point to
7366 the branch instruction. Since the PC doesn't match any known
7367 breakpoints, GDB reports a trap exception.
7369 There are two possible fixes for this problem.
7371 1) When the breakpoint gets hit, see if the BD bit is set in the
7372 Cause register (which indicates the last exception occurred in a
7373 branch delay slot). If the BD bit is set, fix the PC to point to
7374 the instruction in the branch delay slot.
7376 2) When the user sets the breakpoint, don't allow him to set the
7377 breakpoint on the instruction in the branch delay slot. Instead
7378 move the breakpoint to the branch instruction (which will have
7381 The problem with the first solution is that if the user then
7382 single-steps the processor, the branch instruction will get
7383 skipped (since GDB thinks the PC is on the instruction in the
7386 So, we'll use the second solution. To do this we need to know if
7387 the instruction we're trying to set the breakpoint on is in the
7388 branch delay slot. */
7390 boundary
= mips_segment_boundary (bpaddr
);
7392 /* Make sure we don't scan back before the beginning of the current
7393 function, since we may fetch constant data or insns that look like
7394 a jump. Of course we might do that anyway if the compiler has
7395 moved constants inline. :-( */
7396 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7397 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7398 boundary
= func_addr
;
7400 if (mips_pc_is_mips (bpaddr
))
7402 if (bpaddr
== boundary
)
7405 /* If the previous instruction has a branch delay slot, we have
7406 to move the breakpoint to the branch instruction. */
7407 prev_addr
= bpaddr
- 4;
7408 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7413 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7414 CORE_ADDR addr
, jmpaddr
;
7417 boundary
= unmake_compact_addr (boundary
);
7419 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7420 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7421 so try for that first, then try the 2 byte JALR/JR.
7422 The microMIPS ASE has a whole range of jumps and branches
7423 with delay slots, some of which take 4 bytes and some take
7424 2 bytes, so the idea is the same.
7425 FIXME: We have to assume that bpaddr is not the second half
7426 of an extended instruction. */
7427 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7428 ? micromips_insn_at_pc_has_delay_slot
7429 : mips16_insn_at_pc_has_delay_slot
);
7433 for (i
= 1; i
< 4; i
++)
7435 if (unmake_compact_addr (addr
) == boundary
)
7437 addr
-= MIPS_INSN16_SIZE
;
7438 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7439 /* Looks like a JR/JALR at [target-1], but it could be
7440 the second word of a previous JAL/JALX, so record it
7441 and check back one more. */
7443 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7446 /* Looks like a JAL/JALX at [target-2], but it could also
7447 be the second word of a previous JAL/JALX, record it,
7448 and check back one more. */
7451 /* Looks like a JAL/JALX at [target-3], so any previously
7452 recorded JAL/JALX or JR/JALR must be wrong, because:
7455 -2: JAL-ext (can't be JAL/JALX)
7456 -1: bdslot (can't be JR/JALR)
7459 Of course it could be another JAL-ext which looks
7460 like a JAL, but in that case we'd have broken out
7461 of this loop at [target-2]:
7465 -2: bdslot (can't be jmp)
7472 /* Not a jump instruction: if we're at [target-1] this
7473 could be the second word of a JAL/JALX, so continue;
7474 otherwise we're done. */
7487 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7488 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7491 mips_is_stub_suffix (const char *suffix
, int zero
)
7496 return zero
&& suffix
[1] == '\0';
7498 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7503 return suffix
[1] == '\0';
7509 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7510 call stubs, one of sf, df, sc, or dc. */
7513 mips_is_stub_mode (const char *mode
)
7515 return ((mode
[0] == 's' || mode
[0] == 'd')
7516 && (mode
[1] == 'f' || mode
[1] == 'c'));
7519 /* Code at PC is a compiler-generated stub. Such a stub for a function
7520 bar might have a name like __fn_stub_bar, and might look like this:
7527 followed by (or interspersed with):
7534 addiu $25, $25, %lo(bar)
7537 ($1 may be used in old code; for robustness we accept any register)
7540 lui $28, %hi(_gp_disp)
7541 addiu $28, $28, %lo(_gp_disp)
7544 addiu $25, $25, %lo(bar)
7547 In the case of a __call_stub_bar stub, the sequence to set up
7548 arguments might look like this:
7555 followed by (or interspersed with) one of the jump sequences above.
7557 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7558 of J or JR, respectively, followed by:
7564 We are at the beginning of the stub here, and scan down and extract
7565 the target address from the jump immediate instruction or, if a jump
7566 register instruction is used, from the register referred. Return
7567 the value of PC calculated or 0 if inconclusive.
7569 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7572 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7574 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7575 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7576 int addrreg
= MIPS_ZERO_REGNUM
;
7577 CORE_ADDR start_pc
= pc
;
7578 CORE_ADDR target_pc
= 0;
7585 status
== 0 && target_pc
== 0 && i
< 20;
7586 i
++, pc
+= MIPS_INSN32_SIZE
)
7588 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7594 switch (itype_op (inst
))
7596 case 0: /* SPECIAL */
7597 switch (rtype_funct (inst
))
7601 rs
= rtype_rs (inst
);
7602 if (rs
== MIPS_GP_REGNUM
)
7603 target_pc
= gp
; /* Hmm... */
7604 else if (rs
== addrreg
)
7608 case 0x21: /* ADDU */
7609 rt
= rtype_rt (inst
);
7610 rs
= rtype_rs (inst
);
7611 rd
= rtype_rd (inst
);
7612 if (rd
== MIPS_GP_REGNUM
7613 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7614 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7622 target_pc
= jtype_target (inst
) << 2;
7623 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7627 rt
= itype_rt (inst
);
7628 rs
= itype_rs (inst
);
7631 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7632 if (rt
== MIPS_GP_REGNUM
)
7634 else if (rt
== addrreg
)
7640 rt
= itype_rt (inst
);
7641 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7642 if (rt
== MIPS_GP_REGNUM
)
7644 else if (rt
!= MIPS_ZERO_REGNUM
)
7652 rt
= itype_rt (inst
);
7653 rs
= itype_rs (inst
);
7654 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7655 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7659 memset (buf
, 0, sizeof (buf
));
7660 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7662 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7671 /* If PC is in a MIPS16 call or return stub, return the address of the
7672 target PC, which is either the callee or the caller. There are several
7673 cases which must be handled:
7675 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7676 and the target PC is in $31 ($ra).
7677 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7678 and the target PC is in $2.
7679 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7680 i.e. before the JALR instruction, this is effectively a call stub
7681 and the target PC is in $2. Otherwise this is effectively
7682 a return stub and the target PC is in $18.
7683 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7684 JAL or JALR instruction, this is effectively a call stub and the
7685 target PC is buried in the instruction stream. Otherwise this
7686 is effectively a return stub and the target PC is in $18.
7687 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7688 stub and the target PC is buried in the instruction stream.
7690 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7691 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7695 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7697 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7698 CORE_ADDR start_addr
;
7702 /* Find the starting address and name of the function containing the PC. */
7703 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7706 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7707 and the target PC is in $31 ($ra). */
7708 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7709 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7710 && mips_is_stub_mode (name
+ prefixlen
)
7711 && name
[prefixlen
+ 2] == '\0')
7712 return get_frame_register_signed
7713 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7715 /* If the PC is in __mips16_call_stub_*, this is one of the call
7716 call/return stubs. */
7717 prefixlen
= strlen (mips_str_mips16_call_stub
);
7718 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7720 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7721 and the target PC is in $2. */
7722 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7723 return get_frame_register_signed
7724 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7726 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7727 i.e. before the JALR instruction, this is effectively a call stub
7728 and the target PC is in $2. Otherwise this is effectively
7729 a return stub and the target PC is in $18. */
7730 else if (mips_is_stub_mode (name
+ prefixlen
)
7731 && name
[prefixlen
+ 2] == '_'
7732 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7734 if (pc
== start_addr
)
7735 /* This is the 'call' part of a call stub. The return
7736 address is in $2. */
7737 return get_frame_register_signed
7738 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7740 /* This is the 'return' part of a call stub. The return
7741 address is in $18. */
7742 return get_frame_register_signed
7743 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7746 return 0; /* Not a stub. */
7749 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7750 compiler-generated call or call/return stubs. */
7751 if (startswith (name
, mips_str_fn_stub
)
7752 || startswith (name
, mips_str_call_stub
))
7754 if (pc
== start_addr
)
7755 /* This is the 'call' part of a call stub. Call this helper
7756 to scan through this code for interesting instructions
7757 and determine the final PC. */
7758 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7760 /* This is the 'return' part of a call stub. The return address
7762 return get_frame_register_signed
7763 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7766 return 0; /* Not a stub. */
7769 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7770 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7773 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7775 CORE_ADDR start_addr
;
7778 /* Find the starting address of the function containing the PC. */
7779 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7782 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7783 the start, i.e. after the JALR instruction, this is effectively
7785 prefixlen
= strlen (mips_str_mips16_call_stub
);
7786 if (pc
!= start_addr
7787 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7788 && mips_is_stub_mode (name
+ prefixlen
)
7789 && name
[prefixlen
+ 2] == '_'
7790 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7793 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7794 the JAL or JALR instruction, this is effectively a return stub. */
7795 prefixlen
= strlen (mips_str_call_fp_stub
);
7796 if (pc
!= start_addr
7797 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7800 /* Consume the .pic. prefix of any PIC stub, this function must return
7801 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7802 or the call stub path will trigger in handle_inferior_event causing
7804 prefixlen
= strlen (mips_str_pic
);
7805 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7808 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7809 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7810 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7811 && mips_is_stub_mode (name
+ prefixlen
)
7812 && name
[prefixlen
+ 2] == '\0')
7815 return 0; /* Not a stub. */
7818 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7819 PC of the stub target. The stub just loads $t9 and jumps to it,
7820 so that $t9 has the correct value at function entry. */
7823 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7825 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7826 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7827 struct bound_minimal_symbol msym
;
7829 gdb_byte stub_code
[16];
7830 int32_t stub_words
[4];
7832 /* The stub for foo is named ".pic.foo", and is either two
7833 instructions inserted before foo or a three instruction sequence
7834 which jumps to foo. */
7835 msym
= lookup_minimal_symbol_by_pc (pc
);
7836 if (msym
.minsym
== NULL
7837 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7838 || MSYMBOL_LINKAGE_NAME (msym
.minsym
) == NULL
7839 || !startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
7842 /* A two-instruction header. */
7843 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7846 /* A three-instruction (plus delay slot) trampoline. */
7847 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7849 if (target_read_memory (pc
, stub_code
, 16) != 0)
7851 for (i
= 0; i
< 4; i
++)
7852 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7855 /* A stub contains these instructions:
7858 addiu t9, t9, %lo(target)
7861 This works even for N64, since stubs are only generated with
7863 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7864 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7865 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7866 && stub_words
[3] == 0x00000000)
7867 return ((((stub_words
[0] & 0x0000ffff) << 16)
7868 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7871 /* Not a recognized stub. */
7876 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7878 CORE_ADDR requested_pc
= pc
;
7879 CORE_ADDR target_pc
;
7886 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7890 new_pc
= find_solib_trampoline_target (frame
, pc
);
7894 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7898 while (pc
!= target_pc
);
7900 return pc
!= requested_pc
? pc
: 0;
7903 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7904 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7907 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7910 if (num
>= 0 && num
< 32)
7912 else if (num
>= 38 && num
< 70)
7913 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7915 regnum
= mips_regnum (gdbarch
)->hi
;
7917 regnum
= mips_regnum (gdbarch
)->lo
;
7918 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7919 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7922 return gdbarch_num_regs (gdbarch
) + regnum
;
7926 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7927 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7930 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7933 if (num
>= 0 && num
< 32)
7935 else if (num
>= 32 && num
< 64)
7936 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7938 regnum
= mips_regnum (gdbarch
)->hi
;
7940 regnum
= mips_regnum (gdbarch
)->lo
;
7941 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7942 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7945 return gdbarch_num_regs (gdbarch
) + regnum
;
7949 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7951 /* Only makes sense to supply raw registers. */
7952 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7953 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7954 decide if it is valid. Should instead define a standard sim/gdb
7955 register numbering scheme. */
7956 if (gdbarch_register_name (gdbarch
,
7957 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7958 && gdbarch_register_name (gdbarch
,
7959 gdbarch_num_regs (gdbarch
)
7960 + regnum
)[0] != '\0')
7963 return LEGACY_SIM_REGNO_IGNORE
;
7967 /* Convert an integer into an address. Extracting the value signed
7968 guarantees a correctly sign extended address. */
7971 mips_integer_to_address (struct gdbarch
*gdbarch
,
7972 struct type
*type
, const gdb_byte
*buf
)
7974 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7975 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7978 /* Dummy virtual frame pointer method. This is no more or less accurate
7979 than most other architectures; we just need to be explicit about it,
7980 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7981 an assertion failure. */
7984 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7985 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7987 *reg
= MIPS_SP_REGNUM
;
7992 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7994 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7995 const char *name
= bfd_get_section_name (abfd
, sect
);
7997 if (*abip
!= MIPS_ABI_UNKNOWN
)
8000 if (!startswith (name
, ".mdebug."))
8003 if (strcmp (name
, ".mdebug.abi32") == 0)
8004 *abip
= MIPS_ABI_O32
;
8005 else if (strcmp (name
, ".mdebug.abiN32") == 0)
8006 *abip
= MIPS_ABI_N32
;
8007 else if (strcmp (name
, ".mdebug.abi64") == 0)
8008 *abip
= MIPS_ABI_N64
;
8009 else if (strcmp (name
, ".mdebug.abiO64") == 0)
8010 *abip
= MIPS_ABI_O64
;
8011 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8012 *abip
= MIPS_ABI_EABI32
;
8013 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8014 *abip
= MIPS_ABI_EABI64
;
8016 warning (_("unsupported ABI %s."), name
+ 8);
8020 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8022 int *lbp
= (int *) obj
;
8023 const char *name
= bfd_get_section_name (abfd
, sect
);
8025 if (startswith (name
, ".gcc_compiled_long32"))
8027 else if (startswith (name
, ".gcc_compiled_long64"))
8029 else if (startswith (name
, ".gcc_compiled_long"))
8030 warning (_("unrecognized .gcc_compiled_longXX"));
8033 static enum mips_abi
8034 global_mips_abi (void)
8038 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8039 if (mips_abi_strings
[i
] == mips_abi_string
)
8040 return (enum mips_abi
) i
;
8042 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8045 /* Return the default compressed instruction set, either of MIPS16
8046 or microMIPS, selected when none could have been determined from
8047 the ELF header of the binary being executed (or no binary has been
8050 static enum mips_isa
8051 global_mips_compression (void)
8055 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8056 if (mips_compression_strings
[i
] == mips_compression_string
)
8057 return (enum mips_isa
) i
;
8059 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8063 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8065 /* If the size matches the set of 32-bit or 64-bit integer registers,
8066 assume that's what we've got. */
8067 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8068 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8070 /* If the size matches the full set of registers GDB traditionally
8071 knows about, including floating point, for either 32-bit or
8072 64-bit, assume that's what we've got. */
8073 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8074 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8076 /* Otherwise we don't have a useful guess. */
8079 static struct value
*
8080 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8082 const int *reg_p
= (const int *) baton
;
8083 return value_of_register (*reg_p
, frame
);
8086 static struct gdbarch
*
8087 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8089 struct gdbarch
*gdbarch
;
8090 struct gdbarch_tdep
*tdep
;
8092 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8094 enum mips_fpu_type fpu_type
;
8095 struct tdesc_arch_data
*tdesc_data
= NULL
;
8096 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8097 const char **reg_names
;
8098 struct mips_regnum mips_regnum
, *regnum
;
8099 enum mips_isa mips_isa
;
8103 /* Fill in the OS dependent register numbers and names. */
8104 if (info
.osabi
== GDB_OSABI_LINUX
)
8106 mips_regnum
.fp0
= 38;
8107 mips_regnum
.pc
= 37;
8108 mips_regnum
.cause
= 36;
8109 mips_regnum
.badvaddr
= 35;
8110 mips_regnum
.hi
= 34;
8111 mips_regnum
.lo
= 33;
8112 mips_regnum
.fp_control_status
= 70;
8113 mips_regnum
.fp_implementation_revision
= 71;
8114 mips_regnum
.dspacc
= -1;
8115 mips_regnum
.dspctl
= -1;
8119 reg_names
= mips_linux_reg_names
;
8123 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8124 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8125 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8126 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8127 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8128 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8129 mips_regnum
.fp_control_status
= 70;
8130 mips_regnum
.fp_implementation_revision
= 71;
8131 mips_regnum
.dspacc
= dspacc
= -1;
8132 mips_regnum
.dspctl
= dspctl
= -1;
8133 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8134 if (info
.bfd_arch_info
!= NULL
8135 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8136 reg_names
= mips_tx39_reg_names
;
8138 reg_names
= mips_generic_reg_names
;
8141 /* Check any target description for validity. */
8142 if (tdesc_has_registers (info
.target_desc
))
8144 static const char *const mips_gprs
[] = {
8145 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8146 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8147 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8148 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8150 static const char *const mips_fprs
[] = {
8151 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8152 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8153 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8154 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8157 const struct tdesc_feature
*feature
;
8160 feature
= tdesc_find_feature (info
.target_desc
,
8161 "org.gnu.gdb.mips.cpu");
8162 if (feature
== NULL
)
8165 tdesc_data
= tdesc_data_alloc ();
8168 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8169 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
8173 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8174 mips_regnum
.lo
, "lo");
8175 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8176 mips_regnum
.hi
, "hi");
8177 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8178 mips_regnum
.pc
, "pc");
8182 tdesc_data_cleanup (tdesc_data
);
8186 feature
= tdesc_find_feature (info
.target_desc
,
8187 "org.gnu.gdb.mips.cp0");
8188 if (feature
== NULL
)
8190 tdesc_data_cleanup (tdesc_data
);
8195 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8196 mips_regnum
.badvaddr
, "badvaddr");
8197 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8198 MIPS_PS_REGNUM
, "status");
8199 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8200 mips_regnum
.cause
, "cause");
8204 tdesc_data_cleanup (tdesc_data
);
8208 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8209 backend is not prepared for that, though. */
8210 feature
= tdesc_find_feature (info
.target_desc
,
8211 "org.gnu.gdb.mips.fpu");
8212 if (feature
== NULL
)
8214 tdesc_data_cleanup (tdesc_data
);
8219 for (i
= 0; i
< 32; i
++)
8220 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8221 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8223 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8224 mips_regnum
.fp_control_status
,
8227 &= tdesc_numbered_register (feature
, tdesc_data
,
8228 mips_regnum
.fp_implementation_revision
,
8233 tdesc_data_cleanup (tdesc_data
);
8237 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8241 feature
= tdesc_find_feature (info
.target_desc
,
8242 "org.gnu.gdb.mips.dsp");
8243 /* The DSP registers are optional; it's OK if they are absent. */
8244 if (feature
!= NULL
)
8248 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8249 dspacc
+ i
++, "hi1");
8250 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8251 dspacc
+ i
++, "lo1");
8252 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8253 dspacc
+ i
++, "hi2");
8254 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8255 dspacc
+ i
++, "lo2");
8256 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8257 dspacc
+ i
++, "hi3");
8258 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8259 dspacc
+ i
++, "lo3");
8261 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8266 tdesc_data_cleanup (tdesc_data
);
8270 mips_regnum
.dspacc
= dspacc
;
8271 mips_regnum
.dspctl
= dspctl
;
8273 num_regs
= mips_regnum
.dspctl
+ 1;
8277 /* It would be nice to detect an attempt to use a 64-bit ABI
8278 when only 32-bit registers are provided. */
8282 /* First of all, extract the elf_flags, if available. */
8283 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8284 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8285 else if (arches
!= NULL
)
8286 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8290 fprintf_unfiltered (gdb_stdlog
,
8291 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8293 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8294 switch ((elf_flags
& EF_MIPS_ABI
))
8296 case E_MIPS_ABI_O32
:
8297 found_abi
= MIPS_ABI_O32
;
8299 case E_MIPS_ABI_O64
:
8300 found_abi
= MIPS_ABI_O64
;
8302 case E_MIPS_ABI_EABI32
:
8303 found_abi
= MIPS_ABI_EABI32
;
8305 case E_MIPS_ABI_EABI64
:
8306 found_abi
= MIPS_ABI_EABI64
;
8309 if ((elf_flags
& EF_MIPS_ABI2
))
8310 found_abi
= MIPS_ABI_N32
;
8312 found_abi
= MIPS_ABI_UNKNOWN
;
8316 /* GCC creates a pseudo-section whose name describes the ABI. */
8317 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8318 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8320 /* If we have no useful BFD information, use the ABI from the last
8321 MIPS architecture (if there is one). */
8322 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8323 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8325 /* Try the architecture for any hint of the correct ABI. */
8326 if (found_abi
== MIPS_ABI_UNKNOWN
8327 && info
.bfd_arch_info
!= NULL
8328 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8330 switch (info
.bfd_arch_info
->mach
)
8332 case bfd_mach_mips3900
:
8333 found_abi
= MIPS_ABI_EABI32
;
8335 case bfd_mach_mips4100
:
8336 case bfd_mach_mips5000
:
8337 found_abi
= MIPS_ABI_EABI64
;
8339 case bfd_mach_mips8000
:
8340 case bfd_mach_mips10000
:
8341 /* On Irix, ELF64 executables use the N64 ABI. The
8342 pseudo-sections which describe the ABI aren't present
8343 on IRIX. (Even for executables created by gcc.) */
8344 if (info
.abfd
!= NULL
8345 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8346 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8347 found_abi
= MIPS_ABI_N64
;
8349 found_abi
= MIPS_ABI_N32
;
8354 /* Default 64-bit objects to N64 instead of O32. */
8355 if (found_abi
== MIPS_ABI_UNKNOWN
8356 && info
.abfd
!= NULL
8357 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8358 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8359 found_abi
= MIPS_ABI_N64
;
8362 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8365 /* What has the user specified from the command line? */
8366 wanted_abi
= global_mips_abi ();
8368 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8371 /* Now that we have found what the ABI for this binary would be,
8372 check whether the user is overriding it. */
8373 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8374 mips_abi
= wanted_abi
;
8375 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8376 mips_abi
= found_abi
;
8378 mips_abi
= MIPS_ABI_O32
;
8380 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8383 /* Determine the default compressed ISA. */
8384 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8385 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8386 mips_isa
= ISA_MICROMIPS
;
8387 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8388 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8389 mips_isa
= ISA_MIPS16
;
8391 mips_isa
= global_mips_compression ();
8392 mips_compression_string
= mips_compression_strings
[mips_isa
];
8394 /* Also used when doing an architecture lookup. */
8396 fprintf_unfiltered (gdb_stdlog
,
8397 "mips_gdbarch_init: "
8398 "mips64_transfers_32bit_regs_p = %d\n",
8399 mips64_transfers_32bit_regs_p
);
8401 /* Determine the MIPS FPU type. */
8404 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8405 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8406 Tag_GNU_MIPS_ABI_FP
);
8407 #endif /* HAVE_ELF */
8409 if (!mips_fpu_type_auto
)
8410 fpu_type
= mips_fpu_type
;
8411 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8413 switch (elf_fpu_type
)
8415 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8416 fpu_type
= MIPS_FPU_DOUBLE
;
8418 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8419 fpu_type
= MIPS_FPU_SINGLE
;
8421 case Val_GNU_MIPS_ABI_FP_SOFT
:
8423 /* Soft float or unknown. */
8424 fpu_type
= MIPS_FPU_NONE
;
8428 else if (info
.bfd_arch_info
!= NULL
8429 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8430 switch (info
.bfd_arch_info
->mach
)
8432 case bfd_mach_mips3900
:
8433 case bfd_mach_mips4100
:
8434 case bfd_mach_mips4111
:
8435 case bfd_mach_mips4120
:
8436 fpu_type
= MIPS_FPU_NONE
;
8438 case bfd_mach_mips4650
:
8439 fpu_type
= MIPS_FPU_SINGLE
;
8442 fpu_type
= MIPS_FPU_DOUBLE
;
8445 else if (arches
!= NULL
)
8446 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
8448 fpu_type
= MIPS_FPU_DOUBLE
;
8450 fprintf_unfiltered (gdb_stdlog
,
8451 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8453 /* Check for blatant incompatibilities. */
8455 /* If we have only 32-bit registers, then we can't debug a 64-bit
8457 if (info
.target_desc
8458 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8459 && mips_abi
!= MIPS_ABI_EABI32
8460 && mips_abi
!= MIPS_ABI_O32
)
8462 if (tdesc_data
!= NULL
)
8463 tdesc_data_cleanup (tdesc_data
);
8467 /* Try to find a pre-existing architecture. */
8468 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8470 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8472 /* MIPS needs to be pedantic about which ABI and the compressed
8473 ISA variation the object is using. */
8474 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8476 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8478 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8480 /* Need to be pedantic about which register virtual size is
8482 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8483 != mips64_transfers_32bit_regs_p
)
8485 /* Be pedantic about which FPU is selected. */
8486 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
8489 if (tdesc_data
!= NULL
)
8490 tdesc_data_cleanup (tdesc_data
);
8491 return arches
->gdbarch
;
8494 /* Need a new architecture. Fill in a target specific vector. */
8495 tdep
= XCNEW (struct gdbarch_tdep
);
8496 gdbarch
= gdbarch_alloc (&info
, tdep
);
8497 tdep
->elf_flags
= elf_flags
;
8498 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8499 tdep
->found_abi
= found_abi
;
8500 tdep
->mips_abi
= mips_abi
;
8501 tdep
->mips_isa
= mips_isa
;
8502 tdep
->mips_fpu_type
= fpu_type
;
8503 tdep
->register_size_valid_p
= 0;
8504 tdep
->register_size
= 0;
8506 if (info
.target_desc
)
8508 /* Some useful properties can be inferred from the target. */
8509 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8511 tdep
->register_size_valid_p
= 1;
8512 tdep
->register_size
= 4;
8514 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8516 tdep
->register_size_valid_p
= 1;
8517 tdep
->register_size
= 8;
8521 /* Initially set everything according to the default ABI/ISA. */
8522 set_gdbarch_short_bit (gdbarch
, 16);
8523 set_gdbarch_int_bit (gdbarch
, 32);
8524 set_gdbarch_float_bit (gdbarch
, 32);
8525 set_gdbarch_double_bit (gdbarch
, 64);
8526 set_gdbarch_long_double_bit (gdbarch
, 64);
8527 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8528 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8529 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8531 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8532 mips_ax_pseudo_register_collect
);
8533 set_gdbarch_ax_pseudo_register_push_stack
8534 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8536 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8537 mips_elf_make_msymbol_special
);
8538 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8539 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8540 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8542 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8543 *regnum
= mips_regnum
;
8544 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8545 set_gdbarch_num_regs (gdbarch
, num_regs
);
8546 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8547 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8548 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8549 tdep
->mips_processor_reg_names
= reg_names
;
8550 tdep
->regnum
= regnum
;
8555 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8556 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8557 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8558 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8559 tdep
->default_mask_address_p
= 0;
8560 set_gdbarch_long_bit (gdbarch
, 32);
8561 set_gdbarch_ptr_bit (gdbarch
, 32);
8562 set_gdbarch_long_long_bit (gdbarch
, 64);
8565 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8566 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8567 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8568 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8569 tdep
->default_mask_address_p
= 0;
8570 set_gdbarch_long_bit (gdbarch
, 32);
8571 set_gdbarch_ptr_bit (gdbarch
, 32);
8572 set_gdbarch_long_long_bit (gdbarch
, 64);
8574 case MIPS_ABI_EABI32
:
8575 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8576 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8577 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8578 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8579 tdep
->default_mask_address_p
= 0;
8580 set_gdbarch_long_bit (gdbarch
, 32);
8581 set_gdbarch_ptr_bit (gdbarch
, 32);
8582 set_gdbarch_long_long_bit (gdbarch
, 64);
8584 case MIPS_ABI_EABI64
:
8585 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8586 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8587 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8588 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8589 tdep
->default_mask_address_p
= 0;
8590 set_gdbarch_long_bit (gdbarch
, 64);
8591 set_gdbarch_ptr_bit (gdbarch
, 64);
8592 set_gdbarch_long_long_bit (gdbarch
, 64);
8595 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8596 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8597 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8598 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8599 tdep
->default_mask_address_p
= 0;
8600 set_gdbarch_long_bit (gdbarch
, 32);
8601 set_gdbarch_ptr_bit (gdbarch
, 32);
8602 set_gdbarch_long_long_bit (gdbarch
, 64);
8603 set_gdbarch_long_double_bit (gdbarch
, 128);
8604 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8607 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8608 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8609 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8610 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8611 tdep
->default_mask_address_p
= 0;
8612 set_gdbarch_long_bit (gdbarch
, 64);
8613 set_gdbarch_ptr_bit (gdbarch
, 64);
8614 set_gdbarch_long_long_bit (gdbarch
, 64);
8615 set_gdbarch_long_double_bit (gdbarch
, 128);
8616 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8619 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8622 /* GCC creates a pseudo-section whose name specifies the size of
8623 longs, since -mlong32 or -mlong64 may be used independent of
8624 other options. How those options affect pointer sizes is ABI and
8625 architecture dependent, so use them to override the default sizes
8626 set by the ABI. This table shows the relationship between ABI,
8627 -mlongXX, and size of pointers:
8629 ABI -mlongXX ptr bits
8630 --- -------- --------
8644 Note that for o32 and eabi32, pointers are always 32 bits
8645 regardless of any -mlongXX option. For all others, pointers and
8646 longs are the same, as set by -mlongXX or set by defaults. */
8648 if (info
.abfd
!= NULL
)
8652 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8655 set_gdbarch_long_bit (gdbarch
, long_bit
);
8659 case MIPS_ABI_EABI32
:
8664 case MIPS_ABI_EABI64
:
8665 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8668 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8673 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8674 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8677 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8678 flag in object files because to do so would make it impossible to
8679 link with libraries compiled without "-gp32". This is
8680 unnecessarily restrictive.
8682 We could solve this problem by adding "-gp32" multilibs to gcc,
8683 but to set this flag before gcc is built with such multilibs will
8684 break too many systems.''
8686 But even more unhelpfully, the default linker output target for
8687 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8688 for 64-bit programs - you need to change the ABI to change this,
8689 and not all gcc targets support that currently. Therefore using
8690 this flag to detect 32-bit mode would do the wrong thing given
8691 the current gcc - it would make GDB treat these 64-bit programs
8692 as 32-bit programs by default. */
8694 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8695 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8697 /* Add/remove bits from an address. The MIPS needs be careful to
8698 ensure that all 32 bit addresses are sign extended to 64 bits. */
8699 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8701 /* Unwind the frame. */
8702 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8703 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8704 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8706 /* Map debug register numbers onto internal register numbers. */
8707 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8708 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8709 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8710 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8711 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8712 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8714 /* MIPS version of CALL_DUMMY. */
8716 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8717 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8718 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8720 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8722 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8723 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8724 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8726 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8727 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8728 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8729 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8730 mips_adjust_breakpoint_address
);
8732 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8734 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8736 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8737 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8738 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8740 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8742 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8744 if (mips_abi
== MIPS_ABI_N32
)
8745 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8746 else if (mips_abi
== MIPS_ABI_N64
)
8747 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8749 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8751 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8752 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8753 need to all be folded into the target vector. Since they are
8754 being used as guards for target_stopped_by_watchpoint, why not have
8755 target_stopped_by_watchpoint return the type of watchpoint that the code
8757 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8759 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8761 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8762 to support MIPS16. This is a bad thing. Make sure not to do it
8763 if we have an OS ABI that actually supports shared libraries, since
8764 shared library support is more important. If we have an OS someday
8765 that supports both shared libraries and MIPS16, we'll have to find
8766 a better place for these.
8767 macro/2012-04-25: But that applies to return trampolines only and
8768 currently no MIPS OS ABI uses shared libraries that have them. */
8769 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8771 set_gdbarch_single_step_through_delay (gdbarch
,
8772 mips_single_step_through_delay
);
8774 /* Virtual tables. */
8775 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8777 mips_register_g_packet_guesses (gdbarch
);
8779 /* Hook in OS ABI-specific overrides, if they have been registered. */
8780 info
.tdep_info
= tdesc_data
;
8781 gdbarch_init_osabi (info
, gdbarch
);
8783 /* The hook may have adjusted num_regs, fetch the final value and
8784 set pc_regnum and sp_regnum now that it has been fixed. */
8785 num_regs
= gdbarch_num_regs (gdbarch
);
8786 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8787 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8789 /* Unwind the frame. */
8790 dwarf2_append_unwinders (gdbarch
);
8791 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8792 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8793 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8794 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8795 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8796 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8797 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8798 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8799 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8803 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8804 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8806 /* Override the normal target description methods to handle our
8807 dual real and pseudo registers. */
8808 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8809 set_gdbarch_register_reggroup_p (gdbarch
,
8810 mips_tdesc_register_reggroup_p
);
8812 num_regs
= gdbarch_num_regs (gdbarch
);
8813 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8814 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8815 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8818 /* Add ABI-specific aliases for the registers. */
8819 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8820 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8821 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8822 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8824 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8825 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8826 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8828 /* Add some other standard aliases. */
8829 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8830 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8831 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8833 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8834 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8835 value_of_mips_user_reg
,
8836 &mips_numeric_register_aliases
[i
].regnum
);
8842 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
8844 struct gdbarch_info info
;
8846 /* Force the architecture to update, and (if it's a MIPS architecture)
8847 mips_gdbarch_init will take care of the rest. */
8848 gdbarch_info_init (&info
);
8849 gdbarch_update_p (info
);
8852 /* Print out which MIPS ABI is in use. */
8855 show_mips_abi (struct ui_file
*file
,
8857 struct cmd_list_element
*ignored_cmd
,
8858 const char *ignored_value
)
8860 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8863 "The MIPS ABI is unknown because the current architecture "
8867 enum mips_abi global_abi
= global_mips_abi ();
8868 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8869 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8871 if (global_abi
== MIPS_ABI_UNKNOWN
)
8874 "The MIPS ABI is set automatically (currently \"%s\").\n",
8876 else if (global_abi
== actual_abi
)
8879 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8883 /* Probably shouldn't happen... */
8884 fprintf_filtered (file
,
8885 "The (auto detected) MIPS ABI \"%s\" is in use "
8886 "even though the user setting was \"%s\".\n",
8887 actual_abi_str
, mips_abi_strings
[global_abi
]);
8892 /* Print out which MIPS compressed ISA encoding is used. */
8895 show_mips_compression (struct ui_file
*file
, int from_tty
,
8896 struct cmd_list_element
*c
, const char *value
)
8898 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8903 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8905 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8909 int ef_mips_32bitmode
;
8910 /* Determine the ISA. */
8911 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8929 /* Determine the size of a pointer. */
8930 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8931 fprintf_unfiltered (file
,
8932 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8934 fprintf_unfiltered (file
,
8935 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8937 fprintf_unfiltered (file
,
8938 "mips_dump_tdep: ef_mips_arch = %d\n",
8940 fprintf_unfiltered (file
,
8941 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8942 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8943 fprintf_unfiltered (file
,
8945 "mips_mask_address_p() %d (default %d)\n",
8946 mips_mask_address_p (tdep
),
8947 tdep
->default_mask_address_p
);
8949 fprintf_unfiltered (file
,
8950 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8951 MIPS_DEFAULT_FPU_TYPE
,
8952 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
8953 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
8954 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
8956 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8957 MIPS_EABI (gdbarch
));
8958 fprintf_unfiltered (file
,
8959 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8960 MIPS_FPU_TYPE (gdbarch
),
8961 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
8962 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
8963 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
8967 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
8970 _initialize_mips_tdep (void)
8972 static struct cmd_list_element
*mipsfpulist
= NULL
;
8973 struct cmd_list_element
*c
;
8975 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8976 if (MIPS_ABI_LAST
+ 1
8977 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8978 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8980 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8982 mips_pdr_data
= register_objfile_data ();
8984 /* Create feature sets with the appropriate properties. The values
8985 are not important. */
8986 mips_tdesc_gp32
= allocate_target_description ();
8987 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8989 mips_tdesc_gp64
= allocate_target_description ();
8990 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8992 /* Add root prefix command for all "set mips"/"show mips" commands. */
8993 add_prefix_cmd ("mips", no_class
, set_mips_command
,
8994 _("Various MIPS specific commands."),
8995 &setmipscmdlist
, "set mips ", 0, &setlist
);
8997 add_prefix_cmd ("mips", no_class
, show_mips_command
,
8998 _("Various MIPS specific commands."),
8999 &showmipscmdlist
, "show mips ", 0, &showlist
);
9001 /* Allow the user to override the ABI. */
9002 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9003 &mips_abi_string
, _("\
9004 Set the MIPS ABI used by this program."), _("\
9005 Show the MIPS ABI used by this program."), _("\
9006 This option can be set to one of:\n\
9007 auto - the default ABI associated with the current binary\n\
9016 &setmipscmdlist
, &showmipscmdlist
);
9018 /* Allow the user to set the ISA to assume for compressed code if ELF
9019 file flags don't tell or there is no program file selected. This
9020 setting is updated whenever unambiguous ELF file flags are interpreted,
9021 and carried over to subsequent sessions. */
9022 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9023 &mips_compression_string
, _("\
9024 Set the compressed ISA encoding used by MIPS code."), _("\
9025 Show the compressed ISA encoding used by MIPS code."), _("\
9026 Select the compressed ISA encoding used in functions that have no symbol\n\
9027 information available. The encoding can be set to either of:\n\
9030 and is updated automatically from ELF file flags if available."),
9032 show_mips_compression
,
9033 &setmipscmdlist
, &showmipscmdlist
);
9035 /* Let the user turn off floating point and set the fence post for
9036 heuristic_proc_start. */
9038 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
9039 _("Set use of MIPS floating-point coprocessor."),
9040 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
9041 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9042 _("Select single-precision MIPS floating-point coprocessor."),
9044 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9045 _("Select double-precision MIPS floating-point coprocessor."),
9047 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
9048 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
9049 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
9050 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9051 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9052 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
9053 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
9054 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
9055 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9056 _("Select MIPS floating-point coprocessor automatically."),
9058 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9059 _("Show current use of MIPS floating-point coprocessor target."),
9062 /* We really would like to have both "0" and "unlimited" work, but
9063 command.c doesn't deal with that. So make it a var_zinteger
9064 because the user can always use "999999" or some such for unlimited. */
9065 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9066 &heuristic_fence_post
, _("\
9067 Set the distance searched for the start of a function."), _("\
9068 Show the distance searched for the start of a function."), _("\
9069 If you are debugging a stripped executable, GDB needs to search through the\n\
9070 program for the start of a function. This command sets the distance of the\n\
9071 search. The only need to set it is when debugging a stripped executable."),
9072 reinit_frame_cache_sfunc
,
9073 NULL
, /* FIXME: i18n: The distance searched for
9074 the start of a function is %s. */
9075 &setlist
, &showlist
);
9077 /* Allow the user to control whether the upper bits of 64-bit
9078 addresses should be zeroed. */
9079 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9080 &mask_address_var
, _("\
9081 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9082 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9083 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9084 allow GDB to determine the correct value."),
9085 NULL
, show_mask_address
,
9086 &setmipscmdlist
, &showmipscmdlist
);
9088 /* Allow the user to control the size of 32 bit registers within the
9089 raw remote packet. */
9090 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9091 &mips64_transfers_32bit_regs_p
, _("\
9092 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9094 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9096 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9097 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9098 64 bits for others. Use \"off\" to disable compatibility mode"),
9099 set_mips64_transfers_32bit_regs
,
9100 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9101 MIPS target that transfers 32-bit
9102 quantities is %s. */
9103 &setlist
, &showlist
);
9105 /* Debug this files internals. */
9106 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9108 Set mips debugging."), _("\
9109 Show mips debugging."), _("\
9110 When non-zero, mips specific debugging is enabled."),
9112 NULL
, /* FIXME: i18n: Mips debugging is
9114 &setdebuglist
, &showdebuglist
);