1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2-frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
67 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
68 static int mips16_instruction_has_delay_slot (unsigned short inst
,
71 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
73 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
75 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
76 CORE_ADDR addr
, int mustbe32
);
78 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
79 struct frame_info
*, const char *);
81 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
82 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
83 #define ST0_FR (1 << 26)
85 /* The sizes of floating point registers. */
89 MIPS_FPU_SINGLE_REGSIZE
= 4,
90 MIPS_FPU_DOUBLE_REGSIZE
= 8
99 static const char *mips_abi_string
;
101 static const char *const mips_abi_strings
[] = {
112 /* Enum describing the different kinds of breakpoints. */
114 enum mips_breakpoint_kind
116 /* 16-bit MIPS16 mode breakpoint. */
117 MIPS_BP_KIND_MIPS16
= 2,
119 /* 16-bit microMIPS mode breakpoint. */
120 MIPS_BP_KIND_MICROMIPS16
= 3,
122 /* 32-bit standard MIPS mode breakpoint. */
123 MIPS_BP_KIND_MIPS32
= 4,
125 /* 32-bit microMIPS mode breakpoint. */
126 MIPS_BP_KIND_MICROMIPS32
= 5,
129 /* For backwards compatibility we default to MIPS16. This flag is
130 overridden as soon as unambiguous ELF file flags tell us the
131 compressed ISA encoding used. */
132 static const char mips_compression_mips16
[] = "mips16";
133 static const char mips_compression_micromips
[] = "micromips";
134 static const char *const mips_compression_strings
[] =
136 mips_compression_mips16
,
137 mips_compression_micromips
,
141 static const char *mips_compression_string
= mips_compression_mips16
;
143 /* The standard register names, and all the valid aliases for them. */
144 struct register_alias
150 /* Aliases for o32 and most other ABIs. */
151 const struct register_alias mips_o32_aliases
[] = {
158 /* Aliases for n32 and n64. */
159 const struct register_alias mips_n32_n64_aliases
[] = {
166 /* Aliases for ABI-independent registers. */
167 const struct register_alias mips_register_aliases
[] = {
168 /* The architecture manuals specify these ABI-independent names for
170 #define R(n) { "r" #n, n }
171 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
172 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
173 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
174 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
177 /* k0 and k1 are sometimes called these instead (for "kernel
182 /* This is the traditional GDB name for the CP0 status register. */
183 { "sr", MIPS_PS_REGNUM
},
185 /* This is the traditional GDB name for the CP0 BadVAddr register. */
186 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
188 /* This is the traditional GDB name for the FCSR. */
189 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
192 const struct register_alias mips_numeric_register_aliases
[] = {
193 #define R(n) { #n, n }
194 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
195 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
196 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
197 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
201 #ifndef MIPS_DEFAULT_FPU_TYPE
202 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
204 static int mips_fpu_type_auto
= 1;
205 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
207 static unsigned int mips_debug
= 0;
209 /* Properties (for struct target_desc) describing the g/G packet
211 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
212 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
214 struct target_desc
*mips_tdesc_gp32
;
215 struct target_desc
*mips_tdesc_gp64
;
217 const struct mips_regnum
*
218 mips_regnum (struct gdbarch
*gdbarch
)
220 return gdbarch_tdep (gdbarch
)->regnum
;
224 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
226 return mips_regnum (gdbarch
)->fp0
+ 12;
229 /* Return 1 if REGNUM refers to a floating-point general register, raw
230 or cooked. Otherwise return 0. */
233 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
235 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
237 return (rawnum
>= mips_regnum (gdbarch
)->fp0
238 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
241 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
243 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
245 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
246 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
248 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
249 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
251 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
253 /* Return the MIPS ABI associated with GDBARCH. */
255 mips_abi (struct gdbarch
*gdbarch
)
257 return gdbarch_tdep (gdbarch
)->mips_abi
;
261 mips_isa_regsize (struct gdbarch
*gdbarch
)
263 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
265 /* If we know how big the registers are, use that size. */
266 if (tdep
->register_size_valid_p
)
267 return tdep
->register_size
;
269 /* Fall back to the previous behavior. */
270 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
271 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
274 /* Max saved register size. */
275 #define MAX_MIPS_ABI_REGSIZE 8
277 /* Return the currently configured (or set) saved register size. */
280 mips_abi_regsize (struct gdbarch
*gdbarch
)
282 switch (mips_abi (gdbarch
))
284 case MIPS_ABI_EABI32
:
290 case MIPS_ABI_EABI64
:
292 case MIPS_ABI_UNKNOWN
:
295 internal_error (__FILE__
, __LINE__
, _("bad switch"));
299 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
300 are some functions to handle addresses associated with compressed
301 code including but not limited to testing, setting, or clearing
302 bit 0 of such addresses. */
304 /* Return one iff compressed code is the MIPS16 instruction set. */
307 is_mips16_isa (struct gdbarch
*gdbarch
)
309 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
312 /* Return one iff compressed code is the microMIPS instruction set. */
315 is_micromips_isa (struct gdbarch
*gdbarch
)
317 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
320 /* Return one iff ADDR denotes compressed code. */
323 is_compact_addr (CORE_ADDR addr
)
328 /* Return one iff ADDR denotes standard ISA code. */
331 is_mips_addr (CORE_ADDR addr
)
333 return !is_compact_addr (addr
);
336 /* Return one iff ADDR denotes MIPS16 code. */
339 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
341 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
344 /* Return one iff ADDR denotes microMIPS code. */
347 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
349 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
352 /* Strip the ISA (compression) bit off from ADDR. */
355 unmake_compact_addr (CORE_ADDR addr
)
357 return ((addr
) & ~(CORE_ADDR
) 1);
360 /* Add the ISA (compression) bit to ADDR. */
363 make_compact_addr (CORE_ADDR addr
)
365 return ((addr
) | (CORE_ADDR
) 1);
368 /* Extern version of unmake_compact_addr; we use a separate function
369 so that unmake_compact_addr can be inlined throughout this file. */
372 mips_unmake_compact_addr (CORE_ADDR addr
)
374 return unmake_compact_addr (addr
);
377 /* Functions for setting and testing a bit in a minimal symbol that
378 marks it as MIPS16 or microMIPS function. The MSB of the minimal
379 symbol's "info" field is used for this purpose.
381 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
382 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
383 one of the "special" bits in a minimal symbol to mark it accordingly.
384 The test checks an ELF-private flag that is valid for true function
385 symbols only; for synthetic symbols such as for PLT stubs that have
386 no ELF-private part at all the MIPS BFD backend arranges for this
387 information to be carried in the asymbol's udata field instead.
389 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
390 in a minimal symbol. */
393 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
395 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
396 unsigned char st_other
;
398 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
399 st_other
= elfsym
->internal_elf_sym
.st_other
;
400 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
401 st_other
= sym
->udata
.i
;
405 if (ELF_ST_IS_MICROMIPS (st_other
))
407 MSYMBOL_TARGET_FLAG_MICROMIPS (msym
) = 1;
408 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
410 else if (ELF_ST_IS_MIPS16 (st_other
))
412 MSYMBOL_TARGET_FLAG_MIPS16 (msym
) = 1;
413 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
417 /* Return one iff MSYM refers to standard ISA code. */
420 msymbol_is_mips (struct minimal_symbol
*msym
)
422 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
423 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
426 /* Return one iff MSYM refers to MIPS16 code. */
429 msymbol_is_mips16 (struct minimal_symbol
*msym
)
431 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
434 /* Return one iff MSYM refers to microMIPS code. */
437 msymbol_is_micromips (struct minimal_symbol
*msym
)
439 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
442 /* Set the ISA bit in the main symbol too, complementing the corresponding
443 minimal symbol setting and reflecting the run-time value of the symbol.
444 The need for comes from the ISA bit having been cleared as code in
445 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
446 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
447 of symbols referring to compressed code different in GDB to the values
448 used by actual code. That in turn makes them evaluate incorrectly in
449 expressions, producing results different to what the same expressions
450 yield when compiled into the program being debugged. */
453 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
455 if (SYMBOL_CLASS (sym
) == LOC_BLOCK
)
457 /* We are in symbol reading so it is OK to cast away constness. */
458 struct block
*block
= (struct block
*) SYMBOL_BLOCK_VALUE (sym
);
459 CORE_ADDR compact_block_start
;
460 struct bound_minimal_symbol msym
;
462 compact_block_start
= BLOCK_START (block
) | 1;
463 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
464 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
466 BLOCK_START (block
) = compact_block_start
;
471 /* XFER a value from the big/little/left end of the register.
472 Depending on the size of the value it might occupy the entire
473 register or just part of it. Make an allowance for this, aligning
474 things accordingly. */
477 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
478 int reg_num
, int length
,
479 enum bfd_endian endian
, gdb_byte
*in
,
480 const gdb_byte
*out
, int buf_offset
)
484 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
485 /* Need to transfer the left or right part of the register, based on
486 the targets byte order. */
490 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
492 case BFD_ENDIAN_LITTLE
:
495 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
499 internal_error (__FILE__
, __LINE__
, _("bad switch"));
502 fprintf_unfiltered (gdb_stderr
,
503 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
504 reg_num
, reg_offset
, buf_offset
, length
);
505 if (mips_debug
&& out
!= NULL
)
508 fprintf_unfiltered (gdb_stdlog
, "out ");
509 for (i
= 0; i
< length
; i
++)
510 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
513 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
516 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
518 if (mips_debug
&& in
!= NULL
)
521 fprintf_unfiltered (gdb_stdlog
, "in ");
522 for (i
= 0; i
< length
; i
++)
523 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
526 fprintf_unfiltered (gdb_stdlog
, "\n");
529 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
530 compatiblity mode. A return value of 1 means that we have
531 physical 64-bit registers, but should treat them as 32-bit registers. */
534 mips2_fp_compat (struct frame_info
*frame
)
536 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
537 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
539 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
543 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
544 in all the places we deal with FP registers. PR gdb/413. */
545 /* Otherwise check the FR bit in the status register - it controls
546 the FP compatiblity mode. If it is clear we are in compatibility
548 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
555 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
557 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
559 /* The list of available "set mips " and "show mips " commands. */
561 static struct cmd_list_element
*setmipscmdlist
= NULL
;
562 static struct cmd_list_element
*showmipscmdlist
= NULL
;
564 /* Integer registers 0 thru 31 are handled explicitly by
565 mips_register_name(). Processor specific registers 32 and above
566 are listed in the following tables. */
569 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
573 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
574 "sr", "lo", "hi", "bad", "cause", "pc",
575 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
576 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
577 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
578 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
582 /* Names of tx39 registers. */
584 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
585 "sr", "lo", "hi", "bad", "cause", "pc",
586 "", "", "", "", "", "", "", "",
587 "", "", "", "", "", "", "", "",
588 "", "", "", "", "", "", "", "",
589 "", "", "", "", "", "", "", "",
591 "", "", "", "", "", "", "", "",
592 "", "", "config", "cache", "debug", "depc", "epc",
595 /* Names of registers with Linux kernels. */
596 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
597 "sr", "lo", "hi", "bad", "cause", "pc",
598 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
599 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
600 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
601 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
606 /* Return the name of the register corresponding to REGNO. */
608 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
610 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
611 /* GPR names for all ABIs other than n32/n64. */
612 static const char *mips_gpr_names
[] = {
613 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
614 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
615 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
616 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
619 /* GPR names for n32 and n64 ABIs. */
620 static const char *mips_n32_n64_gpr_names
[] = {
621 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
622 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
623 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
624 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
627 enum mips_abi abi
= mips_abi (gdbarch
);
629 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
630 but then don't make the raw register names visible. This (upper)
631 range of user visible register numbers are the pseudo-registers.
633 This approach was adopted accommodate the following scenario:
634 It is possible to debug a 64-bit device using a 32-bit
635 programming model. In such instances, the raw registers are
636 configured to be 64-bits wide, while the pseudo registers are
637 configured to be 32-bits wide. The registers that the user
638 sees - the pseudo registers - match the users expectations
639 given the programming model being used. */
640 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
641 if (regno
< gdbarch_num_regs (gdbarch
))
644 /* The MIPS integer registers are always mapped from 0 to 31. The
645 names of the registers (which reflects the conventions regarding
646 register use) vary depending on the ABI. */
647 if (0 <= rawnum
&& rawnum
< 32)
649 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
650 return mips_n32_n64_gpr_names
[rawnum
];
652 return mips_gpr_names
[rawnum
];
654 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
655 return tdesc_register_name (gdbarch
, rawnum
);
656 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
658 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
659 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
660 return tdep
->mips_processor_reg_names
[rawnum
- 32];
664 internal_error (__FILE__
, __LINE__
,
665 _("mips_register_name: bad register number %d"), rawnum
);
668 /* Return the groups that a MIPS register can be categorised into. */
671 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
672 struct reggroup
*reggroup
)
677 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
678 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
679 if (reggroup
== all_reggroup
)
681 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
682 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
683 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
684 (gdbarch), as not all architectures are multi-arch. */
685 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
686 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
687 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
689 if (reggroup
== float_reggroup
)
690 return float_p
&& pseudo
;
691 if (reggroup
== vector_reggroup
)
692 return vector_p
&& pseudo
;
693 if (reggroup
== general_reggroup
)
694 return (!vector_p
&& !float_p
) && pseudo
;
695 /* Save the pseudo registers. Need to make certain that any code
696 extracting register values from a saved register cache also uses
698 if (reggroup
== save_reggroup
)
699 return raw_p
&& pseudo
;
700 /* Restore the same pseudo register. */
701 if (reggroup
== restore_reggroup
)
702 return raw_p
&& pseudo
;
706 /* Return the groups that a MIPS register can be categorised into.
707 This version is only used if we have a target description which
708 describes real registers (and their groups). */
711 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
712 struct reggroup
*reggroup
)
714 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
715 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
718 /* Only save, restore, and display the pseudo registers. Need to
719 make certain that any code extracting register values from a
720 saved register cache also uses pseudo registers.
722 Note: saving and restoring the pseudo registers is slightly
723 strange; if we have 64 bits, we should save and restore all
724 64 bits. But this is hard and has little benefit. */
728 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
732 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
735 /* Map the symbol table registers which live in the range [1 *
736 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
737 registers. Take care of alignment and size problems. */
739 static enum register_status
740 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
741 int cookednum
, gdb_byte
*buf
)
743 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
744 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
745 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
746 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
747 return regcache_raw_read (regcache
, rawnum
, buf
);
748 else if (register_size (gdbarch
, rawnum
) >
749 register_size (gdbarch
, cookednum
))
751 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
752 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
755 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
757 enum register_status status
;
759 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
760 if (status
== REG_VALID
)
761 store_signed_integer (buf
, 4, byte_order
, regval
);
766 internal_error (__FILE__
, __LINE__
, _("bad register size"));
770 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
771 struct regcache
*regcache
, int cookednum
,
774 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
775 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
776 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
777 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
778 regcache_raw_write (regcache
, rawnum
, buf
);
779 else if (register_size (gdbarch
, rawnum
) >
780 register_size (gdbarch
, cookednum
))
782 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
783 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
786 /* Sign extend the shortened version of the register prior
787 to placing it in the raw register. This is required for
788 some mips64 parts in order to avoid unpredictable behavior. */
789 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
790 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
791 regcache_raw_write_signed (regcache
, rawnum
, regval
);
795 internal_error (__FILE__
, __LINE__
, _("bad register size"));
799 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
800 struct agent_expr
*ax
, int reg
)
802 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
803 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
804 && reg
< 2 * gdbarch_num_regs (gdbarch
));
806 ax_reg_mask (ax
, rawnum
);
812 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
813 struct agent_expr
*ax
, int reg
)
815 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
816 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
817 && reg
< 2 * gdbarch_num_regs (gdbarch
));
818 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
822 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
824 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
825 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
828 ax_simple (ax
, aop_lsh
);
831 ax_simple (ax
, aop_rsh_signed
);
835 internal_error (__FILE__
, __LINE__
, _("bad register size"));
840 /* Table to translate 3-bit register field to actual register number. */
841 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
843 /* Heuristic_proc_start may hunt through the text section for a long
844 time across a 2400 baud serial line. Allows the user to limit this
847 static int heuristic_fence_post
= 0;
849 /* Number of bytes of storage in the actual machine representation for
850 register N. NOTE: This defines the pseudo register type so need to
851 rebuild the architecture vector. */
853 static int mips64_transfers_32bit_regs_p
= 0;
856 set_mips64_transfers_32bit_regs (const char *args
, int from_tty
,
857 struct cmd_list_element
*c
)
859 struct gdbarch_info info
;
860 gdbarch_info_init (&info
);
861 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
862 instead of relying on globals. Doing that would let generic code
863 handle the search for this specific architecture. */
864 if (!gdbarch_update_p (info
))
866 mips64_transfers_32bit_regs_p
= 0;
867 error (_("32-bit compatibility mode not supported"));
871 /* Convert to/from a register and the corresponding memory value. */
873 /* This predicate tests for the case of an 8 byte floating point
874 value that is being transferred to or from a pair of floating point
875 registers each of which are (or are considered to be) only 4 bytes
878 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
881 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
882 && register_size (gdbarch
, regnum
) == 4
883 && mips_float_register_p (gdbarch
, regnum
)
884 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
887 /* This predicate tests for the case of a value of less than 8
888 bytes in width that is being transfered to or from an 8 byte
889 general purpose register. */
891 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
894 int num_regs
= gdbarch_num_regs (gdbarch
);
896 return (register_size (gdbarch
, regnum
) == 8
897 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
898 && TYPE_LENGTH (type
) < 8);
902 mips_convert_register_p (struct gdbarch
*gdbarch
,
903 int regnum
, struct type
*type
)
905 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
906 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
910 mips_register_to_value (struct frame_info
*frame
, int regnum
,
911 struct type
*type
, gdb_byte
*to
,
912 int *optimizedp
, int *unavailablep
)
914 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
916 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
918 get_frame_register (frame
, regnum
+ 0, to
+ 4);
919 get_frame_register (frame
, regnum
+ 1, to
+ 0);
921 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
922 optimizedp
, unavailablep
))
925 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
926 optimizedp
, unavailablep
))
928 *optimizedp
= *unavailablep
= 0;
931 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
933 int len
= TYPE_LENGTH (type
);
936 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
937 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
938 optimizedp
, unavailablep
))
941 *optimizedp
= *unavailablep
= 0;
946 internal_error (__FILE__
, __LINE__
,
947 _("mips_register_to_value: unrecognized case"));
952 mips_value_to_register (struct frame_info
*frame
, int regnum
,
953 struct type
*type
, const gdb_byte
*from
)
955 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
957 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
959 put_frame_register (frame
, regnum
+ 0, from
+ 4);
960 put_frame_register (frame
, regnum
+ 1, from
+ 0);
962 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
965 int len
= TYPE_LENGTH (type
);
967 /* Sign extend values, irrespective of type, that are stored to
968 a 64-bit general purpose register. (32-bit unsigned values
969 are stored as signed quantities within a 64-bit register.
970 When performing an operation, in compiled code, that combines
971 a 32-bit unsigned value with a signed 64-bit value, a type
972 conversion is first performed that zeroes out the high 32 bits.) */
973 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
976 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
978 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
979 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
980 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
984 if (from
[len
-1] & 0x80)
985 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
987 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
988 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
989 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
994 internal_error (__FILE__
, __LINE__
,
995 _("mips_value_to_register: unrecognized case"));
999 /* Return the GDB type object for the "standard" data type of data in
1002 static struct type
*
1003 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1005 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1006 if (mips_float_register_p (gdbarch
, regnum
))
1008 /* The floating-point registers raw, or cooked, always match
1009 mips_isa_regsize(), and also map 1:1, byte for byte. */
1010 if (mips_isa_regsize (gdbarch
) == 4)
1011 return builtin_type (gdbarch
)->builtin_float
;
1013 return builtin_type (gdbarch
)->builtin_double
;
1015 else if (regnum
< gdbarch_num_regs (gdbarch
))
1017 /* The raw or ISA registers. These are all sized according to
1019 if (mips_isa_regsize (gdbarch
) == 4)
1020 return builtin_type (gdbarch
)->builtin_int32
;
1022 return builtin_type (gdbarch
)->builtin_int64
;
1026 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1028 /* The cooked or ABI registers. These are sized according to
1029 the ABI (with a few complications). */
1030 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1031 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1032 return builtin_type (gdbarch
)->builtin_int32
;
1033 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1034 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1035 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1036 /* The pseudo/cooked view of the embedded registers is always
1037 32-bit. The raw view is handled below. */
1038 return builtin_type (gdbarch
)->builtin_int32
;
1039 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
1040 /* The target, while possibly using a 64-bit register buffer,
1041 is only transfering 32-bits of each integer register.
1042 Reflect this in the cooked/pseudo (ABI) register value. */
1043 return builtin_type (gdbarch
)->builtin_int32
;
1044 else if (mips_abi_regsize (gdbarch
) == 4)
1045 /* The ABI is restricted to 32-bit registers (the ISA could be
1047 return builtin_type (gdbarch
)->builtin_int32
;
1050 return builtin_type (gdbarch
)->builtin_int64
;
1054 /* Return the GDB type for the pseudo register REGNUM, which is the
1055 ABI-level view. This function is only called if there is a target
1056 description which includes registers, so we know precisely the
1057 types of hardware registers. */
1059 static struct type
*
1060 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1062 const int num_regs
= gdbarch_num_regs (gdbarch
);
1063 int rawnum
= regnum
% num_regs
;
1064 struct type
*rawtype
;
1066 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1068 /* Absent registers are still absent. */
1069 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1070 if (TYPE_LENGTH (rawtype
) == 0)
1073 /* Present the floating point registers however the hardware did;
1074 do not try to convert between FPU layouts. */
1075 if (mips_float_register_p (gdbarch
, rawnum
))
1078 /* Floating-point control registers are always 32-bit even though for
1079 backwards compatibility reasons 64-bit targets will transfer them
1080 as 64-bit quantities even if using XML descriptions. */
1081 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1082 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1083 return builtin_type (gdbarch
)->builtin_int32
;
1085 /* Use pointer types for registers if we can. For n32 we can not,
1086 since we do not have a 64-bit pointer type. */
1087 if (mips_abi_regsize (gdbarch
)
1088 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1090 if (rawnum
== MIPS_SP_REGNUM
1091 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1092 return builtin_type (gdbarch
)->builtin_data_ptr
;
1093 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1094 return builtin_type (gdbarch
)->builtin_func_ptr
;
1097 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1098 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1099 || rawnum
== mips_regnum (gdbarch
)->lo
1100 || rawnum
== mips_regnum (gdbarch
)->hi
1101 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1102 || rawnum
== mips_regnum (gdbarch
)->cause
1103 || rawnum
== mips_regnum (gdbarch
)->pc
1104 || (mips_regnum (gdbarch
)->dspacc
!= -1
1105 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1106 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1107 return builtin_type (gdbarch
)->builtin_int32
;
1109 /* The pseudo/cooked view of embedded registers is always
1110 32-bit, even if the target transfers 64-bit values for them.
1111 New targets relying on XML descriptions should only transfer
1112 the necessary 32 bits, but older versions of GDB expected 64,
1113 so allow the target to provide 64 bits without interfering
1114 with the displayed type. */
1115 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1116 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1117 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1118 return builtin_type (gdbarch
)->builtin_int32
;
1120 /* For all other registers, pass through the hardware type. */
1124 /* Should the upper word of 64-bit addresses be zeroed? */
1125 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1128 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1130 switch (mask_address_var
)
1132 case AUTO_BOOLEAN_TRUE
:
1134 case AUTO_BOOLEAN_FALSE
:
1137 case AUTO_BOOLEAN_AUTO
:
1138 return tdep
->default_mask_address_p
;
1140 internal_error (__FILE__
, __LINE__
,
1141 _("mips_mask_address_p: bad switch"));
1147 show_mask_address (struct ui_file
*file
, int from_tty
,
1148 struct cmd_list_element
*c
, const char *value
)
1150 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1152 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1153 switch (mask_address_var
)
1155 case AUTO_BOOLEAN_TRUE
:
1156 printf_filtered ("The 32 bit mips address mask is enabled\n");
1158 case AUTO_BOOLEAN_FALSE
:
1159 printf_filtered ("The 32 bit mips address mask is disabled\n");
1161 case AUTO_BOOLEAN_AUTO
:
1163 ("The 32 bit address mask is set automatically. Currently %s\n",
1164 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1167 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1172 /* Tell if the program counter value in MEMADDR is in a standard ISA
1176 mips_pc_is_mips (CORE_ADDR memaddr
)
1178 struct bound_minimal_symbol sym
;
1180 /* Flags indicating that this is a MIPS16 or microMIPS function is
1181 stored by elfread.c in the high bit of the info field. Use this
1182 to decide if the function is standard MIPS. Otherwise if bit 0
1183 of the address is clear, then this is a standard MIPS function. */
1184 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1186 return msymbol_is_mips (sym
.minsym
);
1188 return is_mips_addr (memaddr
);
1191 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1194 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1196 struct bound_minimal_symbol sym
;
1198 /* A flag indicating that this is a MIPS16 function is stored by
1199 elfread.c in the high bit of the info field. Use this to decide
1200 if the function is MIPS16. Otherwise if bit 0 of the address is
1201 set, then ELF file flags will tell if this is a MIPS16 function. */
1202 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1204 return msymbol_is_mips16 (sym
.minsym
);
1206 return is_mips16_addr (gdbarch
, memaddr
);
1209 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1212 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1214 struct bound_minimal_symbol sym
;
1216 /* A flag indicating that this is a microMIPS function is stored by
1217 elfread.c in the high bit of the info field. Use this to decide
1218 if the function is microMIPS. Otherwise if bit 0 of the address
1219 is set, then ELF file flags will tell if this is a microMIPS
1221 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1223 return msymbol_is_micromips (sym
.minsym
);
1225 return is_micromips_addr (gdbarch
, memaddr
);
1228 /* Tell the ISA type of the function the program counter value in MEMADDR
1231 static enum mips_isa
1232 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1234 struct bound_minimal_symbol sym
;
1236 /* A flag indicating that this is a MIPS16 or a microMIPS function
1237 is stored by elfread.c in the high bit of the info field. Use
1238 this to decide if the function is MIPS16 or microMIPS or normal
1239 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1240 flags will tell if this is a MIPS16 or a microMIPS function. */
1241 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1244 if (msymbol_is_micromips (sym
.minsym
))
1245 return ISA_MICROMIPS
;
1246 else if (msymbol_is_mips16 (sym
.minsym
))
1253 if (is_mips_addr (memaddr
))
1255 else if (is_micromips_addr (gdbarch
, memaddr
))
1256 return ISA_MICROMIPS
;
1262 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1263 The need for comes from the ISA bit having been cleared, making
1264 addresses in FDE, range records, etc. referring to compressed code
1265 different to those in line information, the symbol table and finally
1266 the PC register. That in turn confuses many operations. */
1269 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1271 pc
= unmake_compact_addr (pc
);
1272 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1275 /* Recalculate the line record requested so that the resulting PC has
1276 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1277 this adjustment comes from some records associated with compressed
1278 code having the ISA bit cleared, most notably at function prologue
1279 ends. The ISA bit is in this context retrieved from the minimal
1280 symbol covering the address requested, which in turn has been
1281 constructed from the binary's symbol table rather than DWARF-2
1282 information. The correct setting of the ISA bit is required for
1283 breakpoint addresses to correctly match against the stop PC.
1285 As line entries can specify relative address adjustments we need to
1286 keep track of the absolute value of the last line address recorded
1287 in line information, so that we can calculate the actual address to
1288 apply the ISA bit adjustment to. We use PC for this tracking and
1289 keep the original address there.
1291 As such relative address adjustments can be odd within compressed
1292 code we need to keep track of the last line address with the ISA
1293 bit adjustment applied too, as the original address may or may not
1294 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1295 the adjusted address there.
1297 For relative address adjustments we then use these variables to
1298 calculate the address intended by line information, which will be
1299 PC-relative, and return an updated adjustment carrying ISA bit
1300 information, which will be ADJ_PC-relative. For absolute address
1301 adjustments we just return the same address that we store in ADJ_PC
1304 As the first line entry can be relative to an implied address value
1305 of 0 we need to have the initial address set up that we store in PC
1306 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1307 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1310 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1312 static CORE_ADDR adj_pc
;
1313 static CORE_ADDR pc
;
1316 pc
= rel
? pc
+ addr
: addr
;
1317 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1318 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1323 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1325 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1326 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1327 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1328 static const char mips_str_call_stub
[] = "__call_stub_";
1329 static const char mips_str_fn_stub
[] = "__fn_stub_";
1331 /* This is used as a PIC thunk prefix. */
1333 static const char mips_str_pic
[] = ".pic.";
1335 /* Return non-zero if the PC is inside a call thunk (aka stub or
1336 trampoline) that should be treated as a temporary frame. */
1339 mips_in_frame_stub (CORE_ADDR pc
)
1341 CORE_ADDR start_addr
;
1344 /* Find the starting address of the function containing the PC. */
1345 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1348 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1349 if (startswith (name
, mips_str_mips16_call_stub
))
1351 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1352 if (startswith (name
, mips_str_call_stub
))
1354 /* If the PC is in __fn_stub_*, this is a call stub. */
1355 if (startswith (name
, mips_str_fn_stub
))
1358 return 0; /* Not a stub. */
1361 /* MIPS believes that the PC has a sign extended value. Perhaps the
1362 all registers should be sign extended for simplicity? */
1365 mips_read_pc (struct regcache
*regcache
)
1367 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1370 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1375 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1379 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1380 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1381 intermediate frames. In this case we can get the caller's address
1382 from $ra, or if $ra contains an address within a thunk as well, then
1383 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1384 and thus the caller's address is in $s2. */
1385 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1387 pc
= frame_unwind_register_signed
1388 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1389 if (mips_in_frame_stub (pc
))
1390 pc
= frame_unwind_register_signed
1391 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1397 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1399 return frame_unwind_register_signed
1400 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1403 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1404 dummy frame. The frame ID's base needs to match the TOS value
1405 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1408 static struct frame_id
1409 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1411 return frame_id_build
1412 (get_frame_register_signed (this_frame
,
1413 gdbarch_num_regs (gdbarch
)
1415 get_frame_pc (this_frame
));
1418 /* Implement the "write_pc" gdbarch method. */
1421 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1423 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1425 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1428 /* Fetch and return instruction from the specified location. Handle
1429 MIPS16/microMIPS as appropriate. */
1432 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1433 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1435 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1436 gdb_byte buf
[MIPS_INSN32_SIZE
];
1444 instlen
= MIPS_INSN16_SIZE
;
1445 addr
= unmake_compact_addr (addr
);
1448 instlen
= MIPS_INSN32_SIZE
;
1451 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1454 err
= target_read_memory (addr
, buf
, instlen
);
1460 memory_error (TARGET_XFER_E_IO
, addr
);
1463 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1466 /* These are the fields of 32 bit mips instructions. */
1467 #define mips32_op(x) (x >> 26)
1468 #define itype_op(x) (x >> 26)
1469 #define itype_rs(x) ((x >> 21) & 0x1f)
1470 #define itype_rt(x) ((x >> 16) & 0x1f)
1471 #define itype_immediate(x) (x & 0xffff)
1473 #define jtype_op(x) (x >> 26)
1474 #define jtype_target(x) (x & 0x03ffffff)
1476 #define rtype_op(x) (x >> 26)
1477 #define rtype_rs(x) ((x >> 21) & 0x1f)
1478 #define rtype_rt(x) ((x >> 16) & 0x1f)
1479 #define rtype_rd(x) ((x >> 11) & 0x1f)
1480 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1481 #define rtype_funct(x) (x & 0x3f)
1483 /* MicroMIPS instruction fields. */
1484 #define micromips_op(x) ((x) >> 10)
1486 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1487 bit and the size respectively of the field extracted. */
1488 #define b0s4_imm(x) ((x) & 0xf)
1489 #define b0s5_imm(x) ((x) & 0x1f)
1490 #define b0s5_reg(x) ((x) & 0x1f)
1491 #define b0s7_imm(x) ((x) & 0x7f)
1492 #define b0s10_imm(x) ((x) & 0x3ff)
1493 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1494 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1495 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1496 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1497 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1498 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1499 #define b6s4_op(x) (((x) >> 6) & 0xf)
1500 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1502 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1503 respectively of the field extracted. */
1504 #define b0s6_op(x) ((x) & 0x3f)
1505 #define b0s11_op(x) ((x) & 0x7ff)
1506 #define b0s12_imm(x) ((x) & 0xfff)
1507 #define b0s16_imm(x) ((x) & 0xffff)
1508 #define b0s26_imm(x) ((x) & 0x3ffffff)
1509 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1510 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1511 #define b12s4_op(x) (((x) >> 12) & 0xf)
1513 /* Return the size in bytes of the instruction INSN encoded in the ISA
1517 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1522 if ((micromips_op (insn
) & 0x4) == 0x4
1523 || (micromips_op (insn
) & 0x7) == 0x0)
1524 return 2 * MIPS_INSN16_SIZE
;
1526 return MIPS_INSN16_SIZE
;
1528 if ((insn
& 0xf800) == 0xf000)
1529 return 2 * MIPS_INSN16_SIZE
;
1531 return MIPS_INSN16_SIZE
;
1533 return MIPS_INSN32_SIZE
;
1535 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1539 mips32_relative_offset (ULONGEST inst
)
1541 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1544 /* Determine the address of the next instruction executed after the INST
1545 floating condition branch instruction at PC. COUNT specifies the
1546 number of the floating condition bits tested by the branch. */
1549 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1550 ULONGEST inst
, CORE_ADDR pc
, int count
)
1552 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1553 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1554 int tf
= itype_rt (inst
) & 1;
1555 int mask
= (1 << count
) - 1;
1560 /* No way to handle; it'll most likely trap anyway. */
1563 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1564 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1566 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1567 pc
+= mips32_relative_offset (inst
);
1574 /* Return nonzero if the gdbarch is an Octeon series. */
1577 is_octeon (struct gdbarch
*gdbarch
)
1579 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1581 return (info
->mach
== bfd_mach_mips_octeon
1582 || info
->mach
== bfd_mach_mips_octeonp
1583 || info
->mach
== bfd_mach_mips_octeon2
);
1586 /* Return true if the OP represents the Octeon's BBIT instruction. */
1589 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1591 if (!is_octeon (gdbarch
))
1593 /* BBIT0 is encoded as LWC2: 110 010. */
1594 /* BBIT032 is encoded as LDC2: 110 110. */
1595 /* BBIT1 is encoded as SWC2: 111 010. */
1596 /* BBIT132 is encoded as SDC2: 111 110. */
1597 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1603 /* Determine where to set a single step breakpoint while considering
1604 branch prediction. */
1607 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1609 struct gdbarch
*gdbarch
= regcache
->arch ();
1612 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1613 op
= itype_op (inst
);
1614 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1618 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1629 goto greater_branch
;
1634 else if (op
== 17 && itype_rs (inst
) == 8)
1635 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1636 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1637 else if (op
== 17 && itype_rs (inst
) == 9
1638 && (itype_rt (inst
) & 2) == 0)
1639 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1640 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1641 else if (op
== 17 && itype_rs (inst
) == 10
1642 && (itype_rt (inst
) & 2) == 0)
1643 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1644 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1647 /* The new PC will be alternate mode. */
1651 reg
= jtype_target (inst
) << 2;
1652 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1653 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1655 else if (is_octeon_bbit_op (op
, gdbarch
))
1659 branch_if
= op
== 58 || op
== 62;
1660 bit
= itype_rt (inst
);
1662 /* Take into account the *32 instructions. */
1663 if (op
== 54 || op
== 62)
1666 if (((regcache_raw_get_signed (regcache
,
1667 itype_rs (inst
)) >> bit
) & 1)
1669 pc
+= mips32_relative_offset (inst
) + 4;
1671 pc
+= 8; /* After the delay slot. */
1675 pc
+= 4; /* Not a branch, next instruction is easy. */
1678 { /* This gets way messy. */
1680 /* Further subdivide into SPECIAL, REGIMM and other. */
1681 switch (op
& 0x07) /* Extract bits 28,27,26. */
1683 case 0: /* SPECIAL */
1684 op
= rtype_funct (inst
);
1689 /* Set PC to that address. */
1690 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1692 case 12: /* SYSCALL */
1694 struct gdbarch_tdep
*tdep
;
1696 tdep
= gdbarch_tdep (gdbarch
);
1697 if (tdep
->syscall_next_pc
!= NULL
)
1698 pc
= tdep
->syscall_next_pc (get_current_frame ());
1707 break; /* end SPECIAL */
1708 case 1: /* REGIMM */
1710 op
= itype_rt (inst
); /* branch condition */
1715 case 16: /* BLTZAL */
1716 case 18: /* BLTZALL */
1718 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1719 pc
+= mips32_relative_offset (inst
) + 4;
1721 pc
+= 8; /* after the delay slot */
1725 case 17: /* BGEZAL */
1726 case 19: /* BGEZALL */
1727 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1728 pc
+= mips32_relative_offset (inst
) + 4;
1730 pc
+= 8; /* after the delay slot */
1732 case 0x1c: /* BPOSGE32 */
1733 case 0x1e: /* BPOSGE64 */
1735 if (itype_rs (inst
) == 0)
1737 unsigned int pos
= (op
& 2) ? 64 : 32;
1738 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1741 /* No way to handle; it'll most likely trap anyway. */
1744 if ((regcache_raw_get_unsigned (regcache
,
1745 dspctl
) & 0x7f) >= pos
)
1746 pc
+= mips32_relative_offset (inst
);
1751 /* All of the other instructions in the REGIMM category */
1756 break; /* end REGIMM */
1761 reg
= jtype_target (inst
) << 2;
1762 /* Upper four bits get never changed... */
1763 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1766 case 4: /* BEQ, BEQL */
1768 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1769 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1770 pc
+= mips32_relative_offset (inst
) + 4;
1774 case 5: /* BNE, BNEL */
1776 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1777 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1778 pc
+= mips32_relative_offset (inst
) + 4;
1782 case 6: /* BLEZ, BLEZL */
1783 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1784 pc
+= mips32_relative_offset (inst
) + 4;
1790 greater_branch
: /* BGTZ, BGTZL */
1791 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1792 pc
+= mips32_relative_offset (inst
) + 4;
1799 } /* mips32_next_pc */
1801 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1805 micromips_relative_offset7 (ULONGEST insn
)
1807 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1810 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1814 micromips_relative_offset10 (ULONGEST insn
)
1816 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1819 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1823 micromips_relative_offset16 (ULONGEST insn
)
1825 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1828 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1831 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1835 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1836 return mips_insn_size (ISA_MICROMIPS
, insn
);
1839 /* Calculate the address of the next microMIPS instruction to execute
1840 after the INSN coprocessor 1 conditional branch instruction at the
1841 address PC. COUNT denotes the number of coprocessor condition bits
1842 examined by the branch. */
1845 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1846 ULONGEST insn
, CORE_ADDR pc
, int count
)
1848 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1849 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1850 int tf
= b5s5_op (insn
>> 16) & 1;
1851 int mask
= (1 << count
) - 1;
1856 /* No way to handle; it'll most likely trap anyway. */
1859 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1860 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1862 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1863 pc
+= micromips_relative_offset16 (insn
);
1865 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1870 /* Calculate the address of the next microMIPS instruction to execute
1871 after the instruction at the address PC. */
1874 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1876 struct gdbarch
*gdbarch
= regcache
->arch ();
1879 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1880 pc
+= MIPS_INSN16_SIZE
;
1881 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1883 /* 32-bit instructions. */
1884 case 2 * MIPS_INSN16_SIZE
:
1886 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1887 pc
+= MIPS_INSN16_SIZE
;
1888 switch (micromips_op (insn
>> 16))
1890 case 0x00: /* POOL32A: bits 000000 */
1891 if (b0s6_op (insn
) == 0x3c
1892 /* POOL32Axf: bits 000000 ... 111100 */
1893 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1894 /* JALR, JALR.HB: 000000 000x111100 111100 */
1895 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1896 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16));
1899 case 0x10: /* POOL32I: bits 010000 */
1900 switch (b5s5_op (insn
>> 16))
1902 case 0x00: /* BLTZ: bits 010000 00000 */
1903 case 0x01: /* BLTZAL: bits 010000 00001 */
1904 case 0x11: /* BLTZALS: bits 010000 10001 */
1905 if (regcache_raw_get_signed (regcache
,
1906 b0s5_reg (insn
>> 16)) < 0)
1907 pc
+= micromips_relative_offset16 (insn
);
1909 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1912 case 0x02: /* BGEZ: bits 010000 00010 */
1913 case 0x03: /* BGEZAL: bits 010000 00011 */
1914 case 0x13: /* BGEZALS: bits 010000 10011 */
1915 if (regcache_raw_get_signed (regcache
,
1916 b0s5_reg (insn
>> 16)) >= 0)
1917 pc
+= micromips_relative_offset16 (insn
);
1919 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1922 case 0x04: /* BLEZ: bits 010000 00100 */
1923 if (regcache_raw_get_signed (regcache
,
1924 b0s5_reg (insn
>> 16)) <= 0)
1925 pc
+= micromips_relative_offset16 (insn
);
1927 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1930 case 0x05: /* BNEZC: bits 010000 00101 */
1931 if (regcache_raw_get_signed (regcache
,
1932 b0s5_reg (insn
>> 16)) != 0)
1933 pc
+= micromips_relative_offset16 (insn
);
1936 case 0x06: /* BGTZ: bits 010000 00110 */
1937 if (regcache_raw_get_signed (regcache
,
1938 b0s5_reg (insn
>> 16)) > 0)
1939 pc
+= micromips_relative_offset16 (insn
);
1941 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1944 case 0x07: /* BEQZC: bits 010000 00111 */
1945 if (regcache_raw_get_signed (regcache
,
1946 b0s5_reg (insn
>> 16)) == 0)
1947 pc
+= micromips_relative_offset16 (insn
);
1950 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1951 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1952 if (((insn
>> 16) & 0x3) == 0x0)
1953 /* BC2F, BC2T: don't know how to handle these. */
1957 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1958 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1960 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1961 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1964 /* No way to handle; it'll most likely trap anyway. */
1967 if ((regcache_raw_get_unsigned (regcache
,
1968 dspctl
) & 0x7f) >= pos
)
1969 pc
+= micromips_relative_offset16 (insn
);
1971 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1975 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1976 /* BC1ANY2F: bits 010000 11100 xxx01 */
1977 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1978 /* BC1ANY2T: bits 010000 11101 xxx01 */
1979 if (((insn
>> 16) & 0x2) == 0x0)
1980 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
1981 ((insn
>> 16) & 0x1) + 1);
1984 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1985 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1986 if (((insn
>> 16) & 0x3) == 0x1)
1987 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
1992 case 0x1d: /* JALS: bits 011101 */
1993 case 0x35: /* J: bits 110101 */
1994 case 0x3d: /* JAL: bits 111101 */
1995 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
1998 case 0x25: /* BEQ: bits 100101 */
1999 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2000 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2001 pc
+= micromips_relative_offset16 (insn
);
2003 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2006 case 0x2d: /* BNE: bits 101101 */
2007 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2008 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2009 pc
+= micromips_relative_offset16 (insn
);
2011 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2014 case 0x3c: /* JALX: bits 111100 */
2015 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2020 /* 16-bit instructions. */
2021 case MIPS_INSN16_SIZE
:
2022 switch (micromips_op (insn
))
2024 case 0x11: /* POOL16C: bits 010001 */
2025 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2026 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2027 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2028 else if (b5s5_op (insn
) == 0x18)
2029 /* JRADDIUSP: bits 010001 11000 */
2030 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2033 case 0x23: /* BEQZ16: bits 100011 */
2035 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2037 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2038 pc
+= micromips_relative_offset7 (insn
);
2040 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2044 case 0x2b: /* BNEZ16: bits 101011 */
2046 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2048 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2049 pc
+= micromips_relative_offset7 (insn
);
2051 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2055 case 0x33: /* B16: bits 110011 */
2056 pc
+= micromips_relative_offset10 (insn
);
2065 /* Decoding the next place to set a breakpoint is irregular for the
2066 mips 16 variant, but fortunately, there fewer instructions. We have
2067 to cope ith extensions for 16 bit instructions and a pair of actual
2068 32 bit instructions. We dont want to set a single step instruction
2069 on the extend instruction either. */
2071 /* Lots of mips16 instruction formats */
2072 /* Predicting jumps requires itype,ritype,i8type
2073 and their extensions extItype,extritype,extI8type. */
2074 enum mips16_inst_fmts
2076 itype
, /* 0 immediate 5,10 */
2077 ritype
, /* 1 5,3,8 */
2078 rrtype
, /* 2 5,3,3,5 */
2079 rritype
, /* 3 5,3,3,5 */
2080 rrrtype
, /* 4 5,3,3,3,2 */
2081 rriatype
, /* 5 5,3,3,1,4 */
2082 shifttype
, /* 6 5,3,3,3,2 */
2083 i8type
, /* 7 5,3,8 */
2084 i8movtype
, /* 8 5,3,3,5 */
2085 i8mov32rtype
, /* 9 5,3,5,3 */
2086 i64type
, /* 10 5,3,8 */
2087 ri64type
, /* 11 5,3,3,5 */
2088 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2089 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2090 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2091 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2092 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2093 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2094 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2095 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2096 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2097 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2099 /* I am heaping all the fields of the formats into one structure and
2100 then, only the fields which are involved in instruction extension. */
2104 unsigned int regx
; /* Function in i8 type. */
2109 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2110 for the bits which make up the immediate extension. */
2113 extended_offset (unsigned int extension
)
2117 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2119 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2121 value
|= extension
& 0x1f; /* Extract 4:0. */
2126 /* Only call this function if you know that this is an extendable
2127 instruction. It won't malfunction, but why make excess remote memory
2128 references? If the immediate operands get sign extended or something,
2129 do it after the extension is performed. */
2130 /* FIXME: Every one of these cases needs to worry about sign extension
2131 when the offset is to be used in relative addressing. */
2134 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2136 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2139 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2140 target_read_memory (pc
, buf
, 2);
2141 return extract_unsigned_integer (buf
, 2, byte_order
);
2145 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2146 unsigned int extension
,
2148 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2153 switch (insn_format
)
2160 value
= extended_offset ((extension
<< 16) | inst
);
2161 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2165 value
= inst
& 0x7ff;
2166 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2175 { /* A register identifier and an offset. */
2176 /* Most of the fields are the same as I type but the
2177 immediate value is of a different length. */
2181 value
= extended_offset ((extension
<< 16) | inst
);
2182 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2186 value
= inst
& 0xff; /* 8 bits */
2187 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2190 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2196 unsigned long value
;
2197 unsigned int nexthalf
;
2198 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2199 value
= value
<< 16;
2200 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2201 /* Low bit still set. */
2209 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2211 upk
->offset
= offset
;
2217 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2218 and having a signed 16-bit OFFSET. */
2221 add_offset_16 (CORE_ADDR pc
, int offset
)
2223 return pc
+ (offset
<< 1) + 2;
2227 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2228 unsigned int extension
, unsigned int insn
)
2230 struct gdbarch
*gdbarch
= regcache
->arch ();
2231 int op
= (insn
>> 11);
2234 case 2: /* Branch */
2236 struct upk_mips16 upk
;
2237 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2238 pc
= add_offset_16 (pc
, upk
.offset
);
2241 case 3: /* JAL , JALX - Watch out, these are 32 bit
2244 struct upk_mips16 upk
;
2245 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2246 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2247 if ((insn
>> 10) & 0x01) /* Exchange mode */
2248 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2255 struct upk_mips16 upk
;
2257 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2258 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2260 pc
= add_offset_16 (pc
, upk
.offset
);
2267 struct upk_mips16 upk
;
2269 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2270 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2272 pc
= add_offset_16 (pc
, upk
.offset
);
2277 case 12: /* I8 Formats btez btnez */
2279 struct upk_mips16 upk
;
2281 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2282 /* upk.regx contains the opcode */
2283 /* Test register is 24 */
2284 reg
= regcache_raw_get_signed (regcache
, 24);
2285 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2286 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2287 pc
= add_offset_16 (pc
, upk
.offset
);
2292 case 29: /* RR Formats JR, JALR, JALR-RA */
2294 struct upk_mips16 upk
;
2295 /* upk.fmt = rrtype; */
2300 upk
.regx
= (insn
>> 8) & 0x07;
2301 upk
.regy
= (insn
>> 5) & 0x07;
2302 if ((upk
.regy
& 1) == 0)
2303 reg
= mips_reg3_to_reg
[upk
.regx
];
2305 reg
= 31; /* Function return instruction. */
2306 pc
= regcache_raw_get_signed (regcache
, reg
);
2313 /* This is an instruction extension. Fetch the real instruction
2314 (which follows the extension) and decode things based on
2318 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2319 fetch_mips_16 (gdbarch
, pc
));
2332 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2334 struct gdbarch
*gdbarch
= regcache
->arch ();
2335 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2336 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2339 /* The mips_next_pc function supports single_step when the remote
2340 target monitor or stub is not developed enough to do a single_step.
2341 It works by decoding the current instruction and predicting where a
2342 branch will go. This isn't hard because all the data is available.
2343 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2345 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2347 struct gdbarch
*gdbarch
= regcache
->arch ();
2349 if (mips_pc_is_mips16 (gdbarch
, pc
))
2350 return mips16_next_pc (regcache
, pc
);
2351 else if (mips_pc_is_micromips (gdbarch
, pc
))
2352 return micromips_next_pc (regcache
, pc
);
2354 return mips32_next_pc (regcache
, pc
);
2357 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2361 mips16_instruction_is_compact_branch (unsigned short insn
)
2363 switch (insn
& 0xf800)
2366 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2368 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2369 case 0x2800: /* BNEZ */
2370 case 0x2000: /* BEQZ */
2371 case 0x1000: /* B */
2378 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2382 micromips_instruction_is_compact_branch (unsigned short insn
)
2384 switch (micromips_op (insn
))
2386 case 0x11: /* POOL16C: bits 010001 */
2387 return (b5s5_op (insn
) == 0x18
2388 /* JRADDIUSP: bits 010001 11000 */
2389 || b5s5_op (insn
) == 0xd);
2390 /* JRC: bits 010011 01101 */
2391 case 0x10: /* POOL32I: bits 010000 */
2392 return (b5s5_op (insn
) & 0x1d) == 0x5;
2393 /* BEQZC/BNEZC: bits 010000 001x1 */
2399 struct mips_frame_cache
2402 struct trad_frame_saved_reg
*saved_regs
;
2405 /* Set a register's saved stack address in temp_saved_regs. If an
2406 address has already been set for this register, do nothing; this
2407 way we will only recognize the first save of a given register in a
2410 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2411 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2412 Strictly speaking, only the second range is used as it is only second
2413 range (the ABI instead of ISA registers) that comes into play when finding
2414 saved registers in a frame. */
2417 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2418 int regnum
, CORE_ADDR offset
)
2420 if (this_cache
!= NULL
2421 && this_cache
->saved_regs
[regnum
].addr
== -1)
2423 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2425 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2431 /* Fetch the immediate value from a MIPS16 instruction.
2432 If the previous instruction was an EXTEND, use it to extend
2433 the upper bits of the immediate value. This is a helper function
2434 for mips16_scan_prologue. */
2437 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2438 unsigned short inst
, /* current instruction */
2439 int nbits
, /* number of bits in imm field */
2440 int scale
, /* scale factor to be applied to imm */
2441 int is_signed
) /* is the imm field signed? */
2445 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2447 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2448 if (offset
& 0x8000) /* check for negative extend */
2449 offset
= 0 - (0x10000 - (offset
& 0xffff));
2450 return offset
| (inst
& 0x1f);
2454 int max_imm
= 1 << nbits
;
2455 int mask
= max_imm
- 1;
2456 int sign_bit
= max_imm
>> 1;
2458 offset
= inst
& mask
;
2459 if (is_signed
&& (offset
& sign_bit
))
2460 offset
= 0 - (max_imm
- offset
);
2461 return offset
* scale
;
2466 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2467 the associated FRAME_CACHE if not null.
2468 Return the address of the first instruction past the prologue. */
2471 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2472 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2473 struct frame_info
*this_frame
,
2474 struct mips_frame_cache
*this_cache
)
2476 int prev_non_prologue_insn
= 0;
2477 int this_non_prologue_insn
;
2478 int non_prologue_insns
= 0;
2481 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2483 long frame_offset
= 0; /* Size of stack frame. */
2484 long frame_adjust
= 0; /* Offset of FP from SP. */
2485 int frame_reg
= MIPS_SP_REGNUM
;
2486 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2487 unsigned inst
= 0; /* current instruction */
2488 unsigned entry_inst
= 0; /* the entry instruction */
2489 unsigned save_inst
= 0; /* the save instruction */
2490 int prev_delay_slot
= 0;
2494 int extend_bytes
= 0;
2495 int prev_extend_bytes
= 0;
2496 CORE_ADDR end_prologue_addr
;
2498 /* Can be called when there's no process, and hence when there's no
2500 if (this_frame
!= NULL
)
2501 sp
= get_frame_register_signed (this_frame
,
2502 gdbarch_num_regs (gdbarch
)
2507 if (limit_pc
> start_pc
+ 200)
2508 limit_pc
= start_pc
+ 200;
2511 /* Permit at most one non-prologue non-control-transfer instruction
2512 in the middle which may have been reordered by the compiler for
2514 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2516 this_non_prologue_insn
= 0;
2519 /* Save the previous instruction. If it's an EXTEND, we'll extract
2520 the immediate offset extension from it in mips16_get_imm. */
2523 /* Fetch and decode the instruction. */
2524 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2527 /* Normally we ignore extend instructions. However, if it is
2528 not followed by a valid prologue instruction, then this
2529 instruction is not part of the prologue either. We must
2530 remember in this case to adjust the end_prologue_addr back
2532 if ((inst
& 0xf800) == 0xf000) /* extend */
2534 extend_bytes
= MIPS_INSN16_SIZE
;
2538 prev_extend_bytes
= extend_bytes
;
2541 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2542 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2544 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2545 if (offset
< 0) /* Negative stack adjustment? */
2546 frame_offset
-= offset
;
2548 /* Exit loop if a positive stack adjustment is found, which
2549 usually means that the stack cleanup code in the function
2550 epilogue is reached. */
2553 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2555 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2556 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2557 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2559 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2561 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2562 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2563 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2565 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2567 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2568 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2570 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2572 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2573 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2575 else if (inst
== 0x673d) /* move $s1, $sp */
2580 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2582 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2583 frame_addr
= sp
+ offset
;
2585 frame_adjust
= offset
;
2587 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2589 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2590 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2591 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2593 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2595 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2596 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2597 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2599 else if ((inst
& 0xf81f) == 0xe809
2600 && (inst
& 0x700) != 0x700) /* entry */
2601 entry_inst
= inst
; /* Save for later processing. */
2602 else if ((inst
& 0xff80) == 0x6480) /* save */
2604 save_inst
= inst
; /* Save for later processing. */
2605 if (prev_extend_bytes
) /* extend */
2606 save_inst
|= prev_inst
<< 16;
2608 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2610 /* This instruction is part of the prologue, but we don't
2611 need to do anything special to handle it. */
2613 else if (mips16_instruction_has_delay_slot (inst
, 0))
2614 /* JAL/JALR/JALX/JR */
2616 /* The instruction in the delay slot can be a part
2617 of the prologue, so move forward once more. */
2619 if (mips16_instruction_has_delay_slot (inst
, 1))
2622 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2623 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2628 this_non_prologue_insn
= 1;
2631 non_prologue_insns
+= this_non_prologue_insn
;
2633 /* A jump or branch, or enough non-prologue insns seen? If so,
2634 then we must have reached the end of the prologue by now. */
2635 if (prev_delay_slot
|| non_prologue_insns
> 1
2636 || mips16_instruction_is_compact_branch (inst
))
2639 prev_non_prologue_insn
= this_non_prologue_insn
;
2640 prev_delay_slot
= in_delay_slot
;
2641 prev_pc
= cur_pc
- prev_extend_bytes
;
2644 /* The entry instruction is typically the first instruction in a function,
2645 and it stores registers at offsets relative to the value of the old SP
2646 (before the prologue). But the value of the sp parameter to this
2647 function is the new SP (after the prologue has been executed). So we
2648 can't calculate those offsets until we've seen the entire prologue,
2649 and can calculate what the old SP must have been. */
2650 if (entry_inst
!= 0)
2652 int areg_count
= (entry_inst
>> 8) & 7;
2653 int sreg_count
= (entry_inst
>> 6) & 3;
2655 /* The entry instruction always subtracts 32 from the SP. */
2658 /* Now we can calculate what the SP must have been at the
2659 start of the function prologue. */
2662 /* Check if a0-a3 were saved in the caller's argument save area. */
2663 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2665 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2666 offset
+= mips_abi_regsize (gdbarch
);
2669 /* Check if the ra register was pushed on the stack. */
2671 if (entry_inst
& 0x20)
2673 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2674 offset
-= mips_abi_regsize (gdbarch
);
2677 /* Check if the s0 and s1 registers were pushed on the stack. */
2678 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2680 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2681 offset
-= mips_abi_regsize (gdbarch
);
2685 /* The SAVE instruction is similar to ENTRY, except that defined by the
2686 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2687 size of the frame is specified as an immediate field of instruction
2688 and an extended variation exists which lets additional registers and
2689 frame space to be specified. The instruction always treats registers
2690 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2691 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2693 static int args_table
[16] = {
2694 0, 0, 0, 0, 1, 1, 1, 1,
2695 2, 2, 2, 0, 3, 3, 4, -1,
2697 static int astatic_table
[16] = {
2698 0, 1, 2, 3, 0, 1, 2, 3,
2699 0, 1, 2, 4, 0, 1, 0, -1,
2701 int aregs
= (save_inst
>> 16) & 0xf;
2702 int xsregs
= (save_inst
>> 24) & 0x7;
2703 int args
= args_table
[aregs
];
2704 int astatic
= astatic_table
[aregs
];
2709 warning (_("Invalid number of argument registers encoded in SAVE."));
2714 warning (_("Invalid number of static registers encoded in SAVE."));
2718 /* For standard SAVE the frame size of 0 means 128. */
2719 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2720 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2723 frame_offset
+= frame_size
;
2725 /* Now we can calculate what the SP must have been at the
2726 start of the function prologue. */
2729 /* Check if A0-A3 were saved in the caller's argument save area. */
2730 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2732 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2733 offset
+= mips_abi_regsize (gdbarch
);
2738 /* Check if the RA register was pushed on the stack. */
2739 if (save_inst
& 0x40)
2741 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2742 offset
-= mips_abi_regsize (gdbarch
);
2745 /* Check if the S8 register was pushed on the stack. */
2748 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2749 offset
-= mips_abi_regsize (gdbarch
);
2752 /* Check if S2-S7 were pushed on the stack. */
2753 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2755 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2756 offset
-= mips_abi_regsize (gdbarch
);
2759 /* Check if the S1 register was pushed on the stack. */
2760 if (save_inst
& 0x10)
2762 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2763 offset
-= mips_abi_regsize (gdbarch
);
2765 /* Check if the S0 register was pushed on the stack. */
2766 if (save_inst
& 0x20)
2768 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2769 offset
-= mips_abi_regsize (gdbarch
);
2772 /* Check if A0-A3 were pushed on the stack. */
2773 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2775 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2776 offset
-= mips_abi_regsize (gdbarch
);
2780 if (this_cache
!= NULL
)
2783 (get_frame_register_signed (this_frame
,
2784 gdbarch_num_regs (gdbarch
) + frame_reg
)
2785 + frame_offset
- frame_adjust
);
2786 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2787 be able to get rid of the assignment below, evetually. But it's
2788 still needed for now. */
2789 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2790 + mips_regnum (gdbarch
)->pc
]
2791 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2794 /* Set end_prologue_addr to the address of the instruction immediately
2795 after the last one we scanned. Unless the last one looked like a
2796 non-prologue instruction (and we looked ahead), in which case use
2797 its address instead. */
2798 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2799 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2801 return end_prologue_addr
;
2804 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2805 Procedures that use the 32-bit instruction set are handled by the
2806 mips_insn32 unwinder. */
2808 static struct mips_frame_cache
*
2809 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2811 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2812 struct mips_frame_cache
*cache
;
2814 if ((*this_cache
) != NULL
)
2815 return (struct mips_frame_cache
*) (*this_cache
);
2816 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2817 (*this_cache
) = cache
;
2818 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2820 /* Analyze the function prologue. */
2822 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2823 CORE_ADDR start_addr
;
2825 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2826 if (start_addr
== 0)
2827 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2828 /* We can't analyze the prologue if we couldn't find the begining
2830 if (start_addr
== 0)
2833 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2834 (struct mips_frame_cache
*) *this_cache
);
2837 /* gdbarch_sp_regnum contains the value and not the address. */
2838 trad_frame_set_value (cache
->saved_regs
,
2839 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2842 return (struct mips_frame_cache
*) (*this_cache
);
2846 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2847 struct frame_id
*this_id
)
2849 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2851 /* This marks the outermost frame. */
2852 if (info
->base
== 0)
2854 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2857 static struct value
*
2858 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2859 void **this_cache
, int regnum
)
2861 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2863 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2867 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2868 struct frame_info
*this_frame
, void **this_cache
)
2870 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2871 CORE_ADDR pc
= get_frame_pc (this_frame
);
2872 if (mips_pc_is_mips16 (gdbarch
, pc
))
2877 static const struct frame_unwind mips_insn16_frame_unwind
=
2880 default_frame_unwind_stop_reason
,
2881 mips_insn16_frame_this_id
,
2882 mips_insn16_frame_prev_register
,
2884 mips_insn16_frame_sniffer
2888 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2891 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2896 static const struct frame_base mips_insn16_frame_base
=
2898 &mips_insn16_frame_unwind
,
2899 mips_insn16_frame_base_address
,
2900 mips_insn16_frame_base_address
,
2901 mips_insn16_frame_base_address
2904 static const struct frame_base
*
2905 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2907 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2908 CORE_ADDR pc
= get_frame_pc (this_frame
);
2909 if (mips_pc_is_mips16 (gdbarch
, pc
))
2910 return &mips_insn16_frame_base
;
2915 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2916 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2917 interpreted directly, and then multiplied by 4. */
2920 micromips_decode_imm9 (int imm
)
2922 imm
= (imm
^ 0x100) - 0x100;
2923 if (imm
> -3 && imm
< 2)
2928 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2929 the address of the first instruction past the prologue. */
2932 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2933 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2934 struct frame_info
*this_frame
,
2935 struct mips_frame_cache
*this_cache
)
2937 CORE_ADDR end_prologue_addr
;
2938 int prev_non_prologue_insn
= 0;
2939 int frame_reg
= MIPS_SP_REGNUM
;
2940 int this_non_prologue_insn
;
2941 int non_prologue_insns
= 0;
2942 long frame_offset
= 0; /* Size of stack frame. */
2943 long frame_adjust
= 0; /* Offset of FP from SP. */
2944 int prev_delay_slot
= 0;
2948 ULONGEST insn
; /* current instruction */
2952 long v1_off
= 0; /* The assumption is LUI will replace it. */
2963 /* Can be called when there's no process, and hence when there's no
2965 if (this_frame
!= NULL
)
2966 sp
= get_frame_register_signed (this_frame
,
2967 gdbarch_num_regs (gdbarch
)
2972 if (limit_pc
> start_pc
+ 200)
2973 limit_pc
= start_pc
+ 200;
2976 /* Permit at most one non-prologue non-control-transfer instruction
2977 in the middle which may have been reordered by the compiler for
2979 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2981 this_non_prologue_insn
= 0;
2985 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2986 loc
+= MIPS_INSN16_SIZE
;
2987 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2989 /* 32-bit instructions. */
2990 case 2 * MIPS_INSN16_SIZE
:
2992 insn
|= mips_fetch_instruction (gdbarch
,
2993 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
2994 loc
+= MIPS_INSN16_SIZE
;
2995 switch (micromips_op (insn
>> 16))
2997 /* Record $sp/$fp adjustment. */
2998 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2999 case 0x0: /* POOL32A: bits 000000 */
3000 case 0x16: /* POOL32S: bits 010110 */
3001 op
= b0s11_op (insn
);
3002 sreg
= b0s5_reg (insn
>> 16);
3003 treg
= b5s5_reg (insn
>> 16);
3004 dreg
= b11s5_reg (insn
);
3006 /* SUBU: bits 000000 00111010000 */
3007 /* DSUBU: bits 010110 00111010000 */
3008 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3010 /* (D)SUBU $sp, $v1 */
3012 else if (op
!= 0x150
3013 /* ADDU: bits 000000 00101010000 */
3014 /* DADDU: bits 010110 00101010000 */
3015 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3016 this_non_prologue_insn
= 1;
3019 case 0x8: /* POOL32B: bits 001000 */
3020 op
= b12s4_op (insn
);
3021 breg
= b0s5_reg (insn
>> 16);
3022 reglist
= sreg
= b5s5_reg (insn
>> 16);
3023 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3024 if ((op
== 0x9 || op
== 0xc)
3025 /* SWP: bits 001000 1001 */
3026 /* SDP: bits 001000 1100 */
3027 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3028 /* S[DW]P reg,offset($sp) */
3030 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3031 set_reg_offset (gdbarch
, this_cache
,
3033 set_reg_offset (gdbarch
, this_cache
,
3034 sreg
+ 1, sp
+ offset
+ s
);
3036 else if ((op
== 0xd || op
== 0xf)
3037 /* SWM: bits 001000 1101 */
3038 /* SDM: bits 001000 1111 */
3039 && breg
== MIPS_SP_REGNUM
3040 /* SWM reglist,offset($sp) */
3041 && ((reglist
>= 1 && reglist
<= 9)
3042 || (reglist
>= 16 && reglist
<= 25)))
3044 int sreglist
= std::min(reglist
& 0xf, 8);
3046 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3047 for (i
= 0; i
< sreglist
; i
++)
3048 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3049 if ((reglist
& 0xf) > 8)
3050 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3051 if ((reglist
& 0x10) == 0x10)
3052 set_reg_offset (gdbarch
, this_cache
,
3053 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3056 this_non_prologue_insn
= 1;
3059 /* Record $sp/$fp adjustment. */
3060 /* Discard (D)ADDIU $gp used for PIC code. */
3061 case 0xc: /* ADDIU: bits 001100 */
3062 case 0x17: /* DADDIU: bits 010111 */
3063 sreg
= b0s5_reg (insn
>> 16);
3064 dreg
= b5s5_reg (insn
>> 16);
3065 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3066 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3067 /* (D)ADDIU $sp, imm */
3069 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3070 /* (D)ADDIU $fp, $sp, imm */
3072 frame_adjust
= offset
;
3075 else if (sreg
!= 28 || dreg
!= 28)
3076 /* (D)ADDIU $gp, imm */
3077 this_non_prologue_insn
= 1;
3080 /* LUI $v1 is used for larger $sp adjustments. */
3081 /* Discard LUI $gp used for PIC code. */
3082 case 0x10: /* POOL32I: bits 010000 */
3083 if (b5s5_op (insn
>> 16) == 0xd
3084 /* LUI: bits 010000 001101 */
3085 && b0s5_reg (insn
>> 16) == 3)
3087 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3088 else if (b5s5_op (insn
>> 16) != 0xd
3089 /* LUI: bits 010000 001101 */
3090 || b0s5_reg (insn
>> 16) != 28)
3092 this_non_prologue_insn
= 1;
3095 /* ORI $v1 is used for larger $sp adjustments. */
3096 case 0x14: /* ORI: bits 010100 */
3097 sreg
= b0s5_reg (insn
>> 16);
3098 dreg
= b5s5_reg (insn
>> 16);
3099 if (sreg
== 3 && dreg
== 3)
3101 v1_off
|= b0s16_imm (insn
);
3103 this_non_prologue_insn
= 1;
3106 case 0x26: /* SWC1: bits 100110 */
3107 case 0x2e: /* SDC1: bits 101110 */
3108 breg
= b0s5_reg (insn
>> 16);
3109 if (breg
!= MIPS_SP_REGNUM
)
3110 /* S[DW]C1 reg,offset($sp) */
3111 this_non_prologue_insn
= 1;
3114 case 0x36: /* SD: bits 110110 */
3115 case 0x3e: /* SW: bits 111110 */
3116 breg
= b0s5_reg (insn
>> 16);
3117 sreg
= b5s5_reg (insn
>> 16);
3118 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3119 if (breg
== MIPS_SP_REGNUM
)
3120 /* S[DW] reg,offset($sp) */
3121 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3123 this_non_prologue_insn
= 1;
3127 /* The instruction in the delay slot can be a part
3128 of the prologue, so move forward once more. */
3129 if (micromips_instruction_has_delay_slot (insn
, 0))
3132 this_non_prologue_insn
= 1;
3138 /* 16-bit instructions. */
3139 case MIPS_INSN16_SIZE
:
3140 switch (micromips_op (insn
))
3142 case 0x3: /* MOVE: bits 000011 */
3143 sreg
= b0s5_reg (insn
);
3144 dreg
= b5s5_reg (insn
);
3145 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3148 else if ((sreg
& 0x1c) != 0x4)
3149 /* MOVE reg, $a0-$a3 */
3150 this_non_prologue_insn
= 1;
3153 case 0x11: /* POOL16C: bits 010001 */
3154 if (b6s4_op (insn
) == 0x5)
3155 /* SWM: bits 010001 0101 */
3157 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3158 reglist
= b4s2_regl (insn
);
3159 for (i
= 0; i
<= reglist
; i
++)
3160 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3161 set_reg_offset (gdbarch
, this_cache
,
3162 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3165 this_non_prologue_insn
= 1;
3168 case 0x13: /* POOL16D: bits 010011 */
3169 if ((insn
& 0x1) == 0x1)
3170 /* ADDIUSP: bits 010011 1 */
3171 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3172 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3173 /* ADDIUS5: bits 010011 0 */
3174 /* ADDIUS5 $sp, imm */
3175 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3177 this_non_prologue_insn
= 1;
3180 case 0x32: /* SWSP: bits 110010 */
3181 offset
= b0s5_imm (insn
) << 2;
3182 sreg
= b5s5_reg (insn
);
3183 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3187 /* The instruction in the delay slot can be a part
3188 of the prologue, so move forward once more. */
3189 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3192 this_non_prologue_insn
= 1;
3198 frame_offset
-= sp_adj
;
3200 non_prologue_insns
+= this_non_prologue_insn
;
3202 /* A jump or branch, enough non-prologue insns seen or positive
3203 stack adjustment? If so, then we must have reached the end
3204 of the prologue by now. */
3205 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3206 || micromips_instruction_is_compact_branch (insn
))
3209 prev_non_prologue_insn
= this_non_prologue_insn
;
3210 prev_delay_slot
= in_delay_slot
;
3214 if (this_cache
!= NULL
)
3217 (get_frame_register_signed (this_frame
,
3218 gdbarch_num_regs (gdbarch
) + frame_reg
)
3219 + frame_offset
- frame_adjust
);
3220 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3221 be able to get rid of the assignment below, evetually. But it's
3222 still needed for now. */
3223 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3224 + mips_regnum (gdbarch
)->pc
]
3225 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3228 /* Set end_prologue_addr to the address of the instruction immediately
3229 after the last one we scanned. Unless the last one looked like a
3230 non-prologue instruction (and we looked ahead), in which case use
3231 its address instead. */
3233 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3235 return end_prologue_addr
;
3238 /* Heuristic unwinder for procedures using microMIPS instructions.
3239 Procedures that use the 32-bit instruction set are handled by the
3240 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3242 static struct mips_frame_cache
*
3243 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3245 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3246 struct mips_frame_cache
*cache
;
3248 if ((*this_cache
) != NULL
)
3249 return (struct mips_frame_cache
*) (*this_cache
);
3251 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3252 (*this_cache
) = cache
;
3253 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3255 /* Analyze the function prologue. */
3257 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3258 CORE_ADDR start_addr
;
3260 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3261 if (start_addr
== 0)
3262 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3263 /* We can't analyze the prologue if we couldn't find the begining
3265 if (start_addr
== 0)
3268 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3269 (struct mips_frame_cache
*) *this_cache
);
3272 /* gdbarch_sp_regnum contains the value and not the address. */
3273 trad_frame_set_value (cache
->saved_regs
,
3274 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3277 return (struct mips_frame_cache
*) (*this_cache
);
3281 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3282 struct frame_id
*this_id
)
3284 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3286 /* This marks the outermost frame. */
3287 if (info
->base
== 0)
3289 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3292 static struct value
*
3293 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3294 void **this_cache
, int regnum
)
3296 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3298 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3302 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3303 struct frame_info
*this_frame
, void **this_cache
)
3305 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3306 CORE_ADDR pc
= get_frame_pc (this_frame
);
3308 if (mips_pc_is_micromips (gdbarch
, pc
))
3313 static const struct frame_unwind mips_micro_frame_unwind
=
3316 default_frame_unwind_stop_reason
,
3317 mips_micro_frame_this_id
,
3318 mips_micro_frame_prev_register
,
3320 mips_micro_frame_sniffer
3324 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3327 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3332 static const struct frame_base mips_micro_frame_base
=
3334 &mips_micro_frame_unwind
,
3335 mips_micro_frame_base_address
,
3336 mips_micro_frame_base_address
,
3337 mips_micro_frame_base_address
3340 static const struct frame_base
*
3341 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3343 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3344 CORE_ADDR pc
= get_frame_pc (this_frame
);
3346 if (mips_pc_is_micromips (gdbarch
, pc
))
3347 return &mips_micro_frame_base
;
3352 /* Mark all the registers as unset in the saved_regs array
3353 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3356 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3358 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3362 const int num_regs
= gdbarch_num_regs (gdbarch
);
3365 for (i
= 0; i
< num_regs
; i
++)
3367 this_cache
->saved_regs
[i
].addr
= -1;
3372 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3373 the associated FRAME_CACHE if not null.
3374 Return the address of the first instruction past the prologue. */
3377 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3378 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3379 struct frame_info
*this_frame
,
3380 struct mips_frame_cache
*this_cache
)
3382 int prev_non_prologue_insn
;
3383 int this_non_prologue_insn
;
3384 int non_prologue_insns
;
3385 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3387 int prev_delay_slot
;
3392 int frame_reg
= MIPS_SP_REGNUM
;
3394 CORE_ADDR end_prologue_addr
;
3395 int seen_sp_adjust
= 0;
3396 int load_immediate_bytes
= 0;
3398 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3400 /* Can be called when there's no process, and hence when there's no
3402 if (this_frame
!= NULL
)
3403 sp
= get_frame_register_signed (this_frame
,
3404 gdbarch_num_regs (gdbarch
)
3409 if (limit_pc
> start_pc
+ 200)
3410 limit_pc
= start_pc
+ 200;
3413 prev_non_prologue_insn
= 0;
3414 non_prologue_insns
= 0;
3415 prev_delay_slot
= 0;
3418 /* Permit at most one non-prologue non-control-transfer instruction
3419 in the middle which may have been reordered by the compiler for
3422 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3424 unsigned long inst
, high_word
;
3428 this_non_prologue_insn
= 0;
3431 /* Fetch the instruction. */
3432 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3435 /* Save some code by pre-extracting some useful fields. */
3436 high_word
= (inst
>> 16) & 0xffff;
3437 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3438 reg
= high_word
& 0x1f;
3440 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3441 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3442 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3444 if (offset
< 0) /* Negative stack adjustment? */
3445 frame_offset
-= offset
;
3447 /* Exit loop if a positive stack adjustment is found, which
3448 usually means that the stack cleanup code in the function
3449 epilogue is reached. */
3453 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3454 && !regsize_is_64_bits
)
3456 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3458 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3459 && regsize_is_64_bits
)
3461 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3462 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3464 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3466 /* Old gcc frame, r30 is virtual frame pointer. */
3467 if (offset
!= frame_offset
)
3468 frame_addr
= sp
+ offset
;
3469 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3471 unsigned alloca_adjust
;
3474 frame_addr
= get_frame_register_signed
3475 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3478 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3479 if (alloca_adjust
> 0)
3481 /* FP > SP + frame_size. This may be because of
3482 an alloca or somethings similar. Fix sp to
3483 "pre-alloca" value, and try again. */
3484 sp
+= alloca_adjust
;
3485 /* Need to reset the status of all registers. Otherwise,
3486 we will hit a guard that prevents the new address
3487 for each register to be recomputed during the second
3489 reset_saved_regs (gdbarch
, this_cache
);
3494 /* move $30,$sp. With different versions of gas this will be either
3495 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3496 Accept any one of these. */
3497 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3499 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3500 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3502 unsigned alloca_adjust
;
3505 frame_addr
= get_frame_register_signed
3506 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3508 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3509 if (alloca_adjust
> 0)
3511 /* FP > SP + frame_size. This may be because of
3512 an alloca or somethings similar. Fix sp to
3513 "pre-alloca" value, and try again. */
3515 /* Need to reset the status of all registers. Otherwise,
3516 we will hit a guard that prevents the new address
3517 for each register to be recomputed during the second
3519 reset_saved_regs (gdbarch
, this_cache
);
3524 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3525 && !regsize_is_64_bits
)
3527 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3529 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3530 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3531 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3532 || high_word
== 0x3c1c /* lui $gp,n */
3533 || high_word
== 0x279c /* addiu $gp,$gp,n */
3534 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3535 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3538 /* These instructions are part of the prologue, but we don't
3539 need to do anything special to handle them. */
3541 /* The instructions below load $at or $t0 with an immediate
3542 value in preparation for a stack adjustment via
3543 subu $sp,$sp,[$at,$t0]. These instructions could also
3544 initialize a local variable, so we accept them only before
3545 a stack adjustment instruction was seen. */
3546 else if (!seen_sp_adjust
3548 && (high_word
== 0x3c01 /* lui $at,n */
3549 || high_word
== 0x3c08 /* lui $t0,n */
3550 || high_word
== 0x3421 /* ori $at,$at,n */
3551 || high_word
== 0x3508 /* ori $t0,$t0,n */
3552 || high_word
== 0x3401 /* ori $at,$zero,n */
3553 || high_word
== 0x3408 /* ori $t0,$zero,n */
3556 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3558 /* Check for branches and jumps. The instruction in the delay
3559 slot can be a part of the prologue, so move forward once more. */
3560 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3564 /* This instruction is not an instruction typically found
3565 in a prologue, so we must have reached the end of the
3569 this_non_prologue_insn
= 1;
3572 non_prologue_insns
+= this_non_prologue_insn
;
3574 /* A jump or branch, or enough non-prologue insns seen? If so,
3575 then we must have reached the end of the prologue by now. */
3576 if (prev_delay_slot
|| non_prologue_insns
> 1)
3579 prev_non_prologue_insn
= this_non_prologue_insn
;
3580 prev_delay_slot
= in_delay_slot
;
3584 if (this_cache
!= NULL
)
3587 (get_frame_register_signed (this_frame
,
3588 gdbarch_num_regs (gdbarch
) + frame_reg
)
3590 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3591 this assignment below, eventually. But it's still needed
3593 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3594 + mips_regnum (gdbarch
)->pc
]
3595 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3599 /* Set end_prologue_addr to the address of the instruction immediately
3600 after the last one we scanned. Unless the last one looked like a
3601 non-prologue instruction (and we looked ahead), in which case use
3602 its address instead. */
3604 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3606 /* In a frameless function, we might have incorrectly
3607 skipped some load immediate instructions. Undo the skipping
3608 if the load immediate was not followed by a stack adjustment. */
3609 if (load_immediate_bytes
&& !seen_sp_adjust
)
3610 end_prologue_addr
-= load_immediate_bytes
;
3612 return end_prologue_addr
;
3615 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3616 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3617 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3618 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3620 static struct mips_frame_cache
*
3621 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3623 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3624 struct mips_frame_cache
*cache
;
3626 if ((*this_cache
) != NULL
)
3627 return (struct mips_frame_cache
*) (*this_cache
);
3629 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3630 (*this_cache
) = cache
;
3631 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3633 /* Analyze the function prologue. */
3635 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3636 CORE_ADDR start_addr
;
3638 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3639 if (start_addr
== 0)
3640 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3641 /* We can't analyze the prologue if we couldn't find the begining
3643 if (start_addr
== 0)
3646 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3647 (struct mips_frame_cache
*) *this_cache
);
3650 /* gdbarch_sp_regnum contains the value and not the address. */
3651 trad_frame_set_value (cache
->saved_regs
,
3652 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3655 return (struct mips_frame_cache
*) (*this_cache
);
3659 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3660 struct frame_id
*this_id
)
3662 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3664 /* This marks the outermost frame. */
3665 if (info
->base
== 0)
3667 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3670 static struct value
*
3671 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3672 void **this_cache
, int regnum
)
3674 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3676 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3680 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3681 struct frame_info
*this_frame
, void **this_cache
)
3683 CORE_ADDR pc
= get_frame_pc (this_frame
);
3684 if (mips_pc_is_mips (pc
))
3689 static const struct frame_unwind mips_insn32_frame_unwind
=
3692 default_frame_unwind_stop_reason
,
3693 mips_insn32_frame_this_id
,
3694 mips_insn32_frame_prev_register
,
3696 mips_insn32_frame_sniffer
3700 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3703 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3708 static const struct frame_base mips_insn32_frame_base
=
3710 &mips_insn32_frame_unwind
,
3711 mips_insn32_frame_base_address
,
3712 mips_insn32_frame_base_address
,
3713 mips_insn32_frame_base_address
3716 static const struct frame_base
*
3717 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3719 CORE_ADDR pc
= get_frame_pc (this_frame
);
3720 if (mips_pc_is_mips (pc
))
3721 return &mips_insn32_frame_base
;
3726 static struct trad_frame_cache
*
3727 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3730 CORE_ADDR start_addr
;
3731 CORE_ADDR stack_addr
;
3732 struct trad_frame_cache
*this_trad_cache
;
3733 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3734 int num_regs
= gdbarch_num_regs (gdbarch
);
3736 if ((*this_cache
) != NULL
)
3737 return (struct trad_frame_cache
*) (*this_cache
);
3738 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3739 (*this_cache
) = this_trad_cache
;
3741 /* The return address is in the link register. */
3742 trad_frame_set_reg_realreg (this_trad_cache
,
3743 gdbarch_pc_regnum (gdbarch
),
3744 num_regs
+ MIPS_RA_REGNUM
);
3746 /* Frame ID, since it's a frameless / stackless function, no stack
3747 space is allocated and SP on entry is the current SP. */
3748 pc
= get_frame_pc (this_frame
);
3749 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3750 stack_addr
= get_frame_register_signed (this_frame
,
3751 num_regs
+ MIPS_SP_REGNUM
);
3752 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3754 /* Assume that the frame's base is the same as the
3756 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3758 return this_trad_cache
;
3762 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3763 struct frame_id
*this_id
)
3765 struct trad_frame_cache
*this_trad_cache
3766 = mips_stub_frame_cache (this_frame
, this_cache
);
3767 trad_frame_get_id (this_trad_cache
, this_id
);
3770 static struct value
*
3771 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3772 void **this_cache
, int regnum
)
3774 struct trad_frame_cache
*this_trad_cache
3775 = mips_stub_frame_cache (this_frame
, this_cache
);
3776 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3780 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3781 struct frame_info
*this_frame
, void **this_cache
)
3784 struct obj_section
*s
;
3785 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3786 struct bound_minimal_symbol msym
;
3788 /* Use the stub unwinder for unreadable code. */
3789 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3792 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3795 /* Calling a PIC function from a non-PIC function passes through a
3796 stub. The stub for foo is named ".pic.foo". */
3797 msym
= lookup_minimal_symbol_by_pc (pc
);
3798 if (msym
.minsym
!= NULL
3799 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
3800 && startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
3806 static const struct frame_unwind mips_stub_frame_unwind
=
3809 default_frame_unwind_stop_reason
,
3810 mips_stub_frame_this_id
,
3811 mips_stub_frame_prev_register
,
3813 mips_stub_frame_sniffer
3817 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3820 struct trad_frame_cache
*this_trad_cache
3821 = mips_stub_frame_cache (this_frame
, this_cache
);
3822 return trad_frame_get_this_base (this_trad_cache
);
3825 static const struct frame_base mips_stub_frame_base
=
3827 &mips_stub_frame_unwind
,
3828 mips_stub_frame_base_address
,
3829 mips_stub_frame_base_address
,
3830 mips_stub_frame_base_address
3833 static const struct frame_base
*
3834 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3836 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3837 return &mips_stub_frame_base
;
3842 /* mips_addr_bits_remove - remove useless address bits */
3845 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3847 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3849 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3850 /* This hack is a work-around for existing boards using PMON, the
3851 simulator, and any other 64-bit targets that doesn't have true
3852 64-bit addressing. On these targets, the upper 32 bits of
3853 addresses are ignored by the hardware. Thus, the PC or SP are
3854 likely to have been sign extended to all 1s by instruction
3855 sequences that load 32-bit addresses. For example, a typical
3856 piece of code that loads an address is this:
3858 lui $r2, <upper 16 bits>
3859 ori $r2, <lower 16 bits>
3861 But the lui sign-extends the value such that the upper 32 bits
3862 may be all 1s. The workaround is simply to mask off these
3863 bits. In the future, gcc may be changed to support true 64-bit
3864 addressing, and this masking will have to be disabled. */
3865 return addr
&= 0xffffffffUL
;
3871 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3872 instruction and ending with a SC/SCD instruction. If such a sequence
3873 is found, attempt to step through it. A breakpoint is placed at the end of
3876 /* Instructions used during single-stepping of atomic sequences, standard
3878 #define LL_OPCODE 0x30
3879 #define LLD_OPCODE 0x34
3880 #define SC_OPCODE 0x38
3881 #define SCD_OPCODE 0x3c
3883 static std::vector
<CORE_ADDR
>
3884 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3886 CORE_ADDR breaks
[2] = {-1, -1};
3888 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3892 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3893 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3895 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3896 /* Assume all atomic sequences start with a ll/lld instruction. */
3897 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3900 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3902 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3905 loc
+= MIPS_INSN32_SIZE
;
3906 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3908 /* Assume that there is at most one branch in the atomic
3909 sequence. If a branch is found, put a breakpoint in its
3910 destination address. */
3911 switch (itype_op (insn
))
3913 case 0: /* SPECIAL */
3914 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3915 return {}; /* fallback to the standard single-step code. */
3917 case 1: /* REGIMM */
3918 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3919 || ((itype_rt (insn
) & 0x1e) == 0
3920 && itype_rs (insn
) == 0)); /* BPOSGE* */
3924 return {}; /* fallback to the standard single-step code. */
3931 case 22: /* BLEZL */
3932 case 23: /* BGTTL */
3936 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3937 && (itype_rt (insn
) & 0x2) == 0);
3938 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3943 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3948 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3949 if (last_breakpoint
>= 1)
3950 return {}; /* More than one branch found, fallback to the
3951 standard single-step code. */
3952 breaks
[1] = branch_bp
;
3956 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3960 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3961 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3964 loc
+= MIPS_INSN32_SIZE
;
3966 /* Insert a breakpoint right after the end of the atomic sequence. */
3969 /* Check for duplicated breakpoints. Check also for a breakpoint
3970 placed (branch instruction's destination) in the atomic sequence. */
3971 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3972 last_breakpoint
= 0;
3974 std::vector
<CORE_ADDR
> next_pcs
;
3976 /* Effectively inserts the breakpoints. */
3977 for (index
= 0; index
<= last_breakpoint
; index
++)
3978 next_pcs
.push_back (breaks
[index
]);
3983 static std::vector
<CORE_ADDR
>
3984 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3987 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3988 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3989 CORE_ADDR breaks
[2] = {-1, -1};
3990 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
3998 /* Assume all atomic sequences start with a ll/lld instruction. */
3999 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4000 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4002 loc
+= MIPS_INSN16_SIZE
;
4004 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4005 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4007 loc
+= MIPS_INSN16_SIZE
;
4009 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4010 that no atomic sequence is longer than "atomic_sequence_length"
4012 for (insn_count
= 0;
4013 !sc_found
&& insn_count
< atomic_sequence_length
;
4018 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4019 loc
+= MIPS_INSN16_SIZE
;
4021 /* Assume that there is at most one conditional branch in the
4022 atomic sequence. If a branch is found, put a breakpoint in
4023 its destination address. */
4024 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4026 /* 32-bit instructions. */
4027 case 2 * MIPS_INSN16_SIZE
:
4028 switch (micromips_op (insn
))
4030 case 0x10: /* POOL32I: bits 010000 */
4031 if ((b5s5_op (insn
) & 0x18) != 0x0
4032 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4033 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4034 && (b5s5_op (insn
) & 0x1d) != 0x11
4035 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4036 && ((b5s5_op (insn
) & 0x1e) != 0x14
4037 || (insn
& 0x3) != 0x0)
4038 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4039 && (b5s5_op (insn
) & 0x1e) != 0x1a
4040 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4041 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4042 || (insn
& 0x3) != 0x0)
4043 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4044 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4045 || (insn
& 0x3) != 0x1))
4046 /* BC1ANY*: bits 010000 111xx xxx01 */
4050 case 0x25: /* BEQ: bits 100101 */
4051 case 0x2d: /* BNE: bits 101101 */
4053 insn
|= mips_fetch_instruction (gdbarch
,
4054 ISA_MICROMIPS
, loc
, NULL
);
4055 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4056 + micromips_relative_offset16 (insn
));
4060 case 0x00: /* POOL32A: bits 000000 */
4062 insn
|= mips_fetch_instruction (gdbarch
,
4063 ISA_MICROMIPS
, loc
, NULL
);
4064 if (b0s6_op (insn
) != 0x3c
4065 /* POOL32Axf: bits 000000 ... 111100 */
4066 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4067 /* JALR, JALR.HB: 000000 000x111100 111100 */
4068 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4072 case 0x1d: /* JALS: bits 011101 */
4073 case 0x35: /* J: bits 110101 */
4074 case 0x3d: /* JAL: bits 111101 */
4075 case 0x3c: /* JALX: bits 111100 */
4076 return {}; /* Fall back to the standard single-step code. */
4078 case 0x18: /* POOL32C: bits 011000 */
4079 if ((b12s4_op (insn
) & 0xb) == 0xb)
4080 /* SC, SCD: bits 011000 1x11 */
4084 loc
+= MIPS_INSN16_SIZE
;
4087 /* 16-bit instructions. */
4088 case MIPS_INSN16_SIZE
:
4089 switch (micromips_op (insn
))
4091 case 0x23: /* BEQZ16: bits 100011 */
4092 case 0x2b: /* BNEZ16: bits 101011 */
4093 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4097 case 0x11: /* POOL16C: bits 010001 */
4098 if ((b5s5_op (insn
) & 0x1c) != 0xc
4099 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4100 && b5s5_op (insn
) != 0x18)
4101 /* JRADDIUSP: bits 010001 11000 */
4103 return {}; /* Fall back to the standard single-step code. */
4105 case 0x33: /* B16: bits 110011 */
4106 return {}; /* Fall back to the standard single-step code. */
4112 if (last_breakpoint
>= 1)
4113 return {}; /* More than one branch found, fallback to the
4114 standard single-step code. */
4115 breaks
[1] = branch_bp
;
4122 /* Insert a breakpoint right after the end of the atomic sequence. */
4125 /* Check for duplicated breakpoints. Check also for a breakpoint
4126 placed (branch instruction's destination) in the atomic sequence */
4127 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4128 last_breakpoint
= 0;
4130 std::vector
<CORE_ADDR
> next_pcs
;
4132 /* Effectively inserts the breakpoints. */
4133 for (index
= 0; index
<= last_breakpoint
; index
++)
4134 next_pcs
.push_back (breaks
[index
]);
4139 static std::vector
<CORE_ADDR
>
4140 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4142 if (mips_pc_is_mips (pc
))
4143 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4144 else if (mips_pc_is_micromips (gdbarch
, pc
))
4145 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4150 /* mips_software_single_step() is called just before we want to resume
4151 the inferior, if we want to single-step it but there is no hardware
4152 or kernel single-step support (MIPS on GNU/Linux for example). We find
4153 the target of the coming instruction and breakpoint it. */
4155 std::vector
<CORE_ADDR
>
4156 mips_software_single_step (struct regcache
*regcache
)
4158 struct gdbarch
*gdbarch
= regcache
->arch ();
4159 CORE_ADDR pc
, next_pc
;
4161 pc
= regcache_read_pc (regcache
);
4162 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4164 if (!next_pcs
.empty ())
4167 next_pc
= mips_next_pc (regcache
, pc
);
4172 /* Test whether the PC points to the return instruction at the
4173 end of a function. */
4176 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4181 /* This used to check for MIPS16, but this piece of code is never
4182 called for MIPS16 functions. And likewise microMIPS ones. */
4183 gdb_assert (mips_pc_is_mips (pc
));
4185 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4187 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4191 /* This fencepost looks highly suspicious to me. Removing it also
4192 seems suspicious as it could affect remote debugging across serial
4196 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4202 struct inferior
*inf
;
4204 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4206 fence
= start_pc
- heuristic_fence_post
;
4210 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4211 fence
= VM_MIN_ADDRESS
;
4213 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4215 inf
= current_inferior ();
4217 /* Search back for previous return. */
4218 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4219 if (start_pc
< fence
)
4221 /* It's not clear to me why we reach this point when
4222 stop_soon, but with this test, at least we
4223 don't print out warnings for every child forked (eg, on
4224 decstation). 22apr93 rich@cygnus.com. */
4225 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4227 static int blurb_printed
= 0;
4229 warning (_("GDB can't find the start of the function at %s."),
4230 paddress (gdbarch
, pc
));
4234 /* This actually happens frequently in embedded
4235 development, when you first connect to a board
4236 and your stack pointer and pc are nowhere in
4237 particular. This message needs to give people
4238 in that situation enough information to
4239 determine that it's no big deal. */
4240 printf_filtered ("\n\
4241 GDB is unable to find the start of the function at %s\n\
4242 and thus can't determine the size of that function's stack frame.\n\
4243 This means that GDB may be unable to access that stack frame, or\n\
4244 the frames below it.\n\
4245 This problem is most likely caused by an invalid program counter or\n\
4247 However, if you think GDB should simply search farther back\n\
4248 from %s for code which looks like the beginning of a\n\
4249 function, you can increase the range of the search using the `set\n\
4250 heuristic-fence-post' command.\n",
4251 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4258 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4260 unsigned short inst
;
4262 /* On MIPS16, any one of the following is likely to be the
4263 start of a function:
4269 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4270 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4271 if ((inst
& 0xff80) == 0x6480) /* save */
4273 if (start_pc
- instlen
>= fence
)
4275 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4276 start_pc
- instlen
, NULL
);
4277 if ((inst
& 0xf800) == 0xf000) /* extend */
4278 start_pc
-= instlen
;
4282 else if (((inst
& 0xf81f) == 0xe809
4283 && (inst
& 0x700) != 0x700) /* entry */
4284 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4285 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4286 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4288 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4289 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4294 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4302 /* On microMIPS, any one of the following is likely to be the
4303 start of a function:
4307 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4308 switch (micromips_op (insn
))
4310 case 0xc: /* ADDIU: bits 001100 */
4311 case 0x17: /* DADDIU: bits 010111 */
4312 sreg
= b0s5_reg (insn
);
4313 dreg
= b5s5_reg (insn
);
4315 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4316 pc
+ MIPS_INSN16_SIZE
, NULL
);
4317 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4318 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4319 /* (D)ADDIU $sp, imm */
4324 case 0x10: /* POOL32I: bits 010000 */
4325 if (b5s5_op (insn
) == 0xd
4326 /* LUI: bits 010000 001101 */
4327 && b0s5_reg (insn
>> 16) == 28)
4332 case 0x13: /* POOL16D: bits 010011 */
4333 if ((insn
& 0x1) == 0x1)
4334 /* ADDIUSP: bits 010011 1 */
4336 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4342 /* ADDIUS5: bits 010011 0 */
4344 dreg
= b5s5_reg (insn
);
4345 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4346 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4347 /* ADDIUS5 $sp, -imm */
4355 else if (mips_about_to_return (gdbarch
, start_pc
))
4357 /* Skip return and its delay slot. */
4358 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4365 struct mips_objfile_private
4371 /* According to the current ABI, should the type be passed in a
4372 floating-point register (assuming that there is space)? When there
4373 is no FPU, FP are not even considered as possible candidates for
4374 FP registers and, consequently this returns false - forces FP
4375 arguments into integer registers. */
4378 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4379 struct type
*arg_type
)
4381 return ((typecode
== TYPE_CODE_FLT
4382 || (MIPS_EABI (gdbarch
)
4383 && (typecode
== TYPE_CODE_STRUCT
4384 || typecode
== TYPE_CODE_UNION
)
4385 && TYPE_NFIELDS (arg_type
) == 1
4386 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4388 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4391 /* On o32, argument passing in GPRs depends on the alignment of the type being
4392 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4395 mips_type_needs_double_align (struct type
*type
)
4397 enum type_code typecode
= TYPE_CODE (type
);
4399 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4401 else if (typecode
== TYPE_CODE_STRUCT
)
4403 if (TYPE_NFIELDS (type
) < 1)
4405 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4407 else if (typecode
== TYPE_CODE_UNION
)
4411 n
= TYPE_NFIELDS (type
);
4412 for (i
= 0; i
< n
; i
++)
4413 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4420 /* Adjust the address downward (direction of stack growth) so that it
4421 is correctly aligned for a new stack frame. */
4423 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4425 return align_down (addr
, 16);
4428 /* Implement the "push_dummy_code" gdbarch method. */
4431 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4432 CORE_ADDR funaddr
, struct value
**args
,
4433 int nargs
, struct type
*value_type
,
4434 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4435 struct regcache
*regcache
)
4437 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4441 /* Reserve enough room on the stack for our breakpoint instruction. */
4442 bp_slot
= sp
- sizeof (nop_insn
);
4444 /* Return to microMIPS mode if calling microMIPS code to avoid
4445 triggering an address error exception on processors that only
4446 support microMIPS execution. */
4447 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4448 ? make_compact_addr (bp_slot
) : bp_slot
);
4450 /* The breakpoint layer automatically adjusts the address of
4451 breakpoints inserted in a branch delay slot. With enough
4452 bad luck, the 4 bytes located just before our breakpoint
4453 instruction could look like a branch instruction, and thus
4454 trigger the adjustement, and break the function call entirely.
4455 So, we reserve those 4 bytes and write a nop instruction
4456 to prevent that from happening. */
4457 nop_addr
= bp_slot
- sizeof (nop_insn
);
4458 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4459 sp
= mips_frame_align (gdbarch
, nop_addr
);
4461 /* Inferior resumes at the function entry point. */
4468 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4469 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4470 int nargs
, struct value
**args
, CORE_ADDR sp
,
4471 int struct_return
, CORE_ADDR struct_addr
)
4477 int stack_offset
= 0;
4478 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4479 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4480 int abi_regsize
= mips_abi_regsize (gdbarch
);
4482 /* For shared libraries, "t9" needs to point at the function
4484 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4486 /* Set the return address register to point to the entry point of
4487 the program, where a breakpoint lies in wait. */
4488 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4490 /* First ensure that the stack and structure return address (if any)
4491 are properly aligned. The stack has to be at least 64-bit
4492 aligned even on 32-bit machines, because doubles must be 64-bit
4493 aligned. For n32 and n64, stack frames need to be 128-bit
4494 aligned, so we round to this widest known alignment. */
4496 sp
= align_down (sp
, 16);
4497 struct_addr
= align_down (struct_addr
, 16);
4499 /* Now make space on the stack for the args. We allocate more
4500 than necessary for EABI, because the first few arguments are
4501 passed in registers, but that's OK. */
4502 for (argnum
= 0; argnum
< nargs
; argnum
++)
4503 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), abi_regsize
);
4504 sp
-= align_up (len
, 16);
4507 fprintf_unfiltered (gdb_stdlog
,
4508 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4509 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4511 /* Initialize the integer and float register pointers. */
4512 argreg
= MIPS_A0_REGNUM
;
4513 float_argreg
= mips_fpa0_regnum (gdbarch
);
4515 /* The struct_return pointer occupies the first parameter-passing reg. */
4519 fprintf_unfiltered (gdb_stdlog
,
4520 "mips_eabi_push_dummy_call: "
4521 "struct_return reg=%d %s\n",
4522 argreg
, paddress (gdbarch
, struct_addr
));
4523 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4526 /* Now load as many as possible of the first arguments into
4527 registers, and push the rest onto the stack. Loop thru args
4528 from first to last. */
4529 for (argnum
= 0; argnum
< nargs
; argnum
++)
4531 const gdb_byte
*val
;
4532 /* This holds the address of structures that are passed by
4534 gdb_byte ref_valbuf
[MAX_MIPS_ABI_REGSIZE
];
4535 struct value
*arg
= args
[argnum
];
4536 struct type
*arg_type
= check_typedef (value_type (arg
));
4537 int len
= TYPE_LENGTH (arg_type
);
4538 enum type_code typecode
= TYPE_CODE (arg_type
);
4541 fprintf_unfiltered (gdb_stdlog
,
4542 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4543 argnum
+ 1, len
, (int) typecode
);
4545 /* The EABI passes structures that do not fit in a register by
4547 if (len
> abi_regsize
4548 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4550 gdb_assert (abi_regsize
<= ARRAY_SIZE (ref_valbuf
));
4551 store_unsigned_integer (ref_valbuf
, abi_regsize
, byte_order
,
4552 value_address (arg
));
4553 typecode
= TYPE_CODE_PTR
;
4557 fprintf_unfiltered (gdb_stdlog
, " push");
4560 val
= value_contents (arg
);
4562 /* 32-bit ABIs always start floating point arguments in an
4563 even-numbered floating point register. Round the FP register
4564 up before the check to see if there are any FP registers
4565 left. Non MIPS_EABI targets also pass the FP in the integer
4566 registers so also round up normal registers. */
4567 if (abi_regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4569 if ((float_argreg
& 1))
4573 /* Floating point arguments passed in registers have to be
4574 treated specially. On 32-bit architectures, doubles
4575 are passed in register pairs; the even register gets
4576 the low word, and the odd register gets the high word.
4577 On non-EABI processors, the first two floating point arguments are
4578 also copied to general registers, because MIPS16 functions
4579 don't use float registers for arguments. This duplication of
4580 arguments in general registers can't hurt non-MIPS16 functions
4581 because those registers are normally skipped. */
4582 /* MIPS_EABI squeezes a struct that contains a single floating
4583 point value into an FP register instead of pushing it onto the
4585 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4586 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4588 /* EABI32 will pass doubles in consecutive registers, even on
4589 64-bit cores. At one time, we used to check the size of
4590 `float_argreg' to determine whether or not to pass doubles
4591 in consecutive registers, but this is not sufficient for
4592 making the ABI determination. */
4593 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4595 int low_offset
= gdbarch_byte_order (gdbarch
)
4596 == BFD_ENDIAN_BIG
? 4 : 0;
4599 /* Write the low word of the double to the even register(s). */
4600 regval
= extract_signed_integer (val
+ low_offset
,
4603 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4604 float_argreg
, phex (regval
, 4));
4605 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4607 /* Write the high word of the double to the odd register(s). */
4608 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4611 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4612 float_argreg
, phex (regval
, 4));
4613 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4617 /* This is a floating point value that fits entirely
4618 in a single register. */
4619 /* On 32 bit ABI's the float_argreg is further adjusted
4620 above to ensure that it is even register aligned. */
4621 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4623 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4624 float_argreg
, phex (regval
, len
));
4625 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4630 /* Copy the argument to general registers or the stack in
4631 register-sized pieces. Large arguments are split between
4632 registers and stack. */
4633 /* Note: structs whose size is not a multiple of abi_regsize
4634 are treated specially: Irix cc passes
4635 them in registers where gcc sometimes puts them on the
4636 stack. For maximum compatibility, we will put them in
4638 int odd_sized_struct
= (len
> abi_regsize
&& len
% abi_regsize
!= 0);
4640 /* Note: Floating-point values that didn't fit into an FP
4641 register are only written to memory. */
4644 /* Remember if the argument was written to the stack. */
4645 int stack_used_p
= 0;
4646 int partial_len
= (len
< abi_regsize
? len
: abi_regsize
);
4649 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4652 /* Write this portion of the argument to the stack. */
4653 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4655 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4657 /* Should shorter than int integer values be
4658 promoted to int before being stored? */
4659 int longword_offset
= 0;
4662 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4664 if (abi_regsize
== 8
4665 && (typecode
== TYPE_CODE_INT
4666 || typecode
== TYPE_CODE_PTR
4667 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4668 longword_offset
= abi_regsize
- len
;
4669 else if ((typecode
== TYPE_CODE_STRUCT
4670 || typecode
== TYPE_CODE_UNION
)
4671 && TYPE_LENGTH (arg_type
) < abi_regsize
)
4672 longword_offset
= abi_regsize
- len
;
4677 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4678 paddress (gdbarch
, stack_offset
));
4679 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4680 paddress (gdbarch
, longword_offset
));
4683 addr
= sp
+ stack_offset
+ longword_offset
;
4688 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4689 paddress (gdbarch
, addr
));
4690 for (i
= 0; i
< partial_len
; i
++)
4692 fprintf_unfiltered (gdb_stdlog
, "%02x",
4696 write_memory (addr
, val
, partial_len
);
4699 /* Note!!! This is NOT an else clause. Odd sized
4700 structs may go thru BOTH paths. Floating point
4701 arguments will not. */
4702 /* Write this portion of the argument to a general
4703 purpose register. */
4704 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4705 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4708 extract_signed_integer (val
, partial_len
, byte_order
);
4711 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4713 phex (regval
, abi_regsize
));
4714 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4721 /* Compute the offset into the stack at which we will
4722 copy the next parameter.
4724 In the new EABI (and the NABI32), the stack_offset
4725 only needs to be adjusted when it has been used. */
4728 stack_offset
+= align_up (partial_len
, abi_regsize
);
4732 fprintf_unfiltered (gdb_stdlog
, "\n");
4735 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4737 /* Return adjusted stack pointer. */
4741 /* Determine the return value convention being used. */
4743 static enum return_value_convention
4744 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4745 struct type
*type
, struct regcache
*regcache
,
4746 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4748 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4749 int fp_return_type
= 0;
4750 int offset
, regnum
, xfer
;
4752 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4753 return RETURN_VALUE_STRUCT_CONVENTION
;
4755 /* Floating point type? */
4756 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4758 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4760 /* Structs with a single field of float type
4761 are returned in a floating point register. */
4762 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4763 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4764 && TYPE_NFIELDS (type
) == 1)
4766 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4768 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4775 /* A floating-point value belongs in the least significant part
4778 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4779 regnum
= mips_regnum (gdbarch
)->fp0
;
4783 /* An integer value goes in V0/V1. */
4785 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4786 regnum
= MIPS_V0_REGNUM
;
4789 offset
< TYPE_LENGTH (type
);
4790 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4792 xfer
= mips_abi_regsize (gdbarch
);
4793 if (offset
+ xfer
> TYPE_LENGTH (type
))
4794 xfer
= TYPE_LENGTH (type
) - offset
;
4795 mips_xfer_register (gdbarch
, regcache
,
4796 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4797 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4801 return RETURN_VALUE_REGISTER_CONVENTION
;
4805 /* N32/N64 ABI stuff. */
4807 /* Search for a naturally aligned double at OFFSET inside a struct
4808 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4812 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4817 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4820 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4823 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4826 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4829 struct type
*field_type
;
4831 /* We're only looking at normal fields. */
4832 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4833 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4836 /* If we have gone past the offset, there is no double to pass. */
4837 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4841 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4843 /* If this field is entirely before the requested offset, go
4844 on to the next one. */
4845 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4848 /* If this is our special aligned double, we can stop. */
4849 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4850 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4853 /* This field starts at or before the requested offset, and
4854 overlaps it. If it is a structure, recurse inwards. */
4855 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4862 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4863 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4864 int nargs
, struct value
**args
, CORE_ADDR sp
,
4865 int struct_return
, CORE_ADDR struct_addr
)
4871 int stack_offset
= 0;
4872 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4873 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4875 /* For shared libraries, "t9" needs to point at the function
4877 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4879 /* Set the return address register to point to the entry point of
4880 the program, where a breakpoint lies in wait. */
4881 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4883 /* First ensure that the stack and structure return address (if any)
4884 are properly aligned. The stack has to be at least 64-bit
4885 aligned even on 32-bit machines, because doubles must be 64-bit
4886 aligned. For n32 and n64, stack frames need to be 128-bit
4887 aligned, so we round to this widest known alignment. */
4889 sp
= align_down (sp
, 16);
4890 struct_addr
= align_down (struct_addr
, 16);
4892 /* Now make space on the stack for the args. */
4893 for (argnum
= 0; argnum
< nargs
; argnum
++)
4894 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4895 sp
-= align_up (len
, 16);
4898 fprintf_unfiltered (gdb_stdlog
,
4899 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4900 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4902 /* Initialize the integer and float register pointers. */
4903 argreg
= MIPS_A0_REGNUM
;
4904 float_argreg
= mips_fpa0_regnum (gdbarch
);
4906 /* The struct_return pointer occupies the first parameter-passing reg. */
4910 fprintf_unfiltered (gdb_stdlog
,
4911 "mips_n32n64_push_dummy_call: "
4912 "struct_return reg=%d %s\n",
4913 argreg
, paddress (gdbarch
, struct_addr
));
4914 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4917 /* Now load as many as possible of the first arguments into
4918 registers, and push the rest onto the stack. Loop thru args
4919 from first to last. */
4920 for (argnum
= 0; argnum
< nargs
; argnum
++)
4922 const gdb_byte
*val
;
4923 struct value
*arg
= args
[argnum
];
4924 struct type
*arg_type
= check_typedef (value_type (arg
));
4925 int len
= TYPE_LENGTH (arg_type
);
4926 enum type_code typecode
= TYPE_CODE (arg_type
);
4929 fprintf_unfiltered (gdb_stdlog
,
4930 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4931 argnum
+ 1, len
, (int) typecode
);
4933 val
= value_contents (arg
);
4935 /* A 128-bit long double value requires an even-odd pair of
4936 floating-point registers. */
4938 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4939 && (float_argreg
& 1))
4945 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4946 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4948 /* This is a floating point value that fits entirely
4949 in a single register or a pair of registers. */
4950 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4951 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4953 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4954 float_argreg
, phex (regval
, reglen
));
4955 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4958 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4959 argreg
, phex (regval
, reglen
));
4960 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4965 regval
= extract_unsigned_integer (val
+ reglen
,
4966 reglen
, byte_order
);
4968 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4969 float_argreg
, phex (regval
, reglen
));
4970 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4973 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4974 argreg
, phex (regval
, reglen
));
4975 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4982 /* Copy the argument to general registers or the stack in
4983 register-sized pieces. Large arguments are split between
4984 registers and stack. */
4985 /* For N32/N64, structs, unions, or other composite types are
4986 treated as a sequence of doublewords, and are passed in integer
4987 or floating point registers as though they were simple scalar
4988 parameters to the extent that they fit, with any excess on the
4989 stack packed according to the normal memory layout of the
4991 The caller does not reserve space for the register arguments;
4992 the callee is responsible for reserving it if required. */
4993 /* Note: Floating-point values that didn't fit into an FP
4994 register are only written to memory. */
4997 /* Remember if the argument was written to the stack. */
4998 int stack_used_p
= 0;
4999 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5002 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5005 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5006 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
5008 /* Write this portion of the argument to the stack. */
5009 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
5011 /* Should shorter than int integer values be
5012 promoted to int before being stored? */
5013 int longword_offset
= 0;
5016 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5018 if ((typecode
== TYPE_CODE_INT
5019 || typecode
== TYPE_CODE_PTR
)
5021 longword_offset
= MIPS64_REGSIZE
- len
;
5026 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5027 paddress (gdbarch
, stack_offset
));
5028 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5029 paddress (gdbarch
, longword_offset
));
5032 addr
= sp
+ stack_offset
+ longword_offset
;
5037 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5038 paddress (gdbarch
, addr
));
5039 for (i
= 0; i
< partial_len
; i
++)
5041 fprintf_unfiltered (gdb_stdlog
, "%02x",
5045 write_memory (addr
, val
, partial_len
);
5048 /* Note!!! This is NOT an else clause. Odd sized
5049 structs may go thru BOTH paths. */
5050 /* Write this portion of the argument to a general
5051 purpose register. */
5052 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5056 /* Sign extend pointers, 32-bit integers and signed
5057 16-bit and 8-bit integers; everything else is taken
5060 if ((partial_len
== 4
5061 && (typecode
== TYPE_CODE_PTR
5062 || typecode
== TYPE_CODE_INT
))
5064 && typecode
== TYPE_CODE_INT
5065 && !TYPE_UNSIGNED (arg_type
)))
5066 regval
= extract_signed_integer (val
, partial_len
,
5069 regval
= extract_unsigned_integer (val
, partial_len
,
5072 /* A non-floating-point argument being passed in a
5073 general register. If a struct or union, and if
5074 the remaining length is smaller than the register
5075 size, we have to adjust the register value on
5078 It does not seem to be necessary to do the
5079 same for integral types. */
5081 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5082 && partial_len
< MIPS64_REGSIZE
5083 && (typecode
== TYPE_CODE_STRUCT
5084 || typecode
== TYPE_CODE_UNION
))
5085 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5089 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5091 phex (regval
, MIPS64_REGSIZE
));
5092 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5094 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5095 TYPE_LENGTH (arg_type
) - len
))
5098 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5100 phex (regval
, MIPS64_REGSIZE
));
5101 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5112 /* Compute the offset into the stack at which we will
5113 copy the next parameter.
5115 In N32 (N64?), the stack_offset only needs to be
5116 adjusted when it has been used. */
5119 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5123 fprintf_unfiltered (gdb_stdlog
, "\n");
5126 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5128 /* Return adjusted stack pointer. */
5132 static enum return_value_convention
5133 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5134 struct type
*type
, struct regcache
*regcache
,
5135 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5137 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5139 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5141 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5142 if needed), as appropriate for the type. Composite results (struct,
5143 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5146 * A struct with only one or two floating point fields is returned in $f0
5147 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5150 * Any other composite results of at most 128 bits are returned in
5151 $2 (first 64 bits) and $3 (remainder, if necessary).
5153 * Larger composite results are handled by converting the function to a
5154 procedure with an implicit first parameter, which is a pointer to an area
5155 reserved by the caller to receive the result. [The o32-bit ABI requires
5156 that all composite results be handled by conversion to implicit first
5157 parameters. The MIPS/SGI Fortran implementation has always made a
5158 specific exception to return COMPLEX results in the floating point
5161 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5162 return RETURN_VALUE_STRUCT_CONVENTION
;
5163 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5164 && TYPE_LENGTH (type
) == 16
5165 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5167 /* A 128-bit floating-point value fills both $f0 and $f2. The
5168 two registers are used in the same as memory order, so the
5169 eight bytes with the lower memory address are in $f0. */
5171 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5172 mips_xfer_register (gdbarch
, regcache
,
5173 (gdbarch_num_regs (gdbarch
)
5174 + mips_regnum (gdbarch
)->fp0
),
5175 8, gdbarch_byte_order (gdbarch
),
5176 readbuf
, writebuf
, 0);
5177 mips_xfer_register (gdbarch
, regcache
,
5178 (gdbarch_num_regs (gdbarch
)
5179 + mips_regnum (gdbarch
)->fp0
+ 2),
5180 8, gdbarch_byte_order (gdbarch
),
5181 readbuf
? readbuf
+ 8 : readbuf
,
5182 writebuf
? writebuf
+ 8 : writebuf
, 0);
5183 return RETURN_VALUE_REGISTER_CONVENTION
;
5185 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5186 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5188 /* A single or double floating-point value that fits in FP0. */
5190 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5191 mips_xfer_register (gdbarch
, regcache
,
5192 (gdbarch_num_regs (gdbarch
)
5193 + mips_regnum (gdbarch
)->fp0
),
5195 gdbarch_byte_order (gdbarch
),
5196 readbuf
, writebuf
, 0);
5197 return RETURN_VALUE_REGISTER_CONVENTION
;
5199 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5200 && TYPE_NFIELDS (type
) <= 2
5201 && TYPE_NFIELDS (type
) >= 1
5202 && ((TYPE_NFIELDS (type
) == 1
5203 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5205 || (TYPE_NFIELDS (type
) == 2
5206 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5208 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
5209 == TYPE_CODE_FLT
))))
5211 /* A struct that contains one or two floats. Each value is part
5212 in the least significant part of their floating point
5213 register (or GPR, for soft float). */
5216 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5217 ? mips_regnum (gdbarch
)->fp0
5219 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5221 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5224 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5226 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5228 /* A 16-byte long double field goes in two consecutive
5230 mips_xfer_register (gdbarch
, regcache
,
5231 gdbarch_num_regs (gdbarch
) + regnum
,
5233 gdbarch_byte_order (gdbarch
),
5234 readbuf
, writebuf
, offset
);
5235 mips_xfer_register (gdbarch
, regcache
,
5236 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5238 gdbarch_byte_order (gdbarch
),
5239 readbuf
, writebuf
, offset
+ 8);
5242 mips_xfer_register (gdbarch
, regcache
,
5243 gdbarch_num_regs (gdbarch
) + regnum
,
5244 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5245 gdbarch_byte_order (gdbarch
),
5246 readbuf
, writebuf
, offset
);
5248 return RETURN_VALUE_REGISTER_CONVENTION
;
5250 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5251 || TYPE_CODE (type
) == TYPE_CODE_UNION
5252 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5254 /* A composite type. Extract the left justified value,
5255 regardless of the byte order. I.e. DO NOT USE
5259 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5260 offset
< TYPE_LENGTH (type
);
5261 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5263 int xfer
= register_size (gdbarch
, regnum
);
5264 if (offset
+ xfer
> TYPE_LENGTH (type
))
5265 xfer
= TYPE_LENGTH (type
) - offset
;
5267 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5268 offset
, xfer
, regnum
);
5269 mips_xfer_register (gdbarch
, regcache
,
5270 gdbarch_num_regs (gdbarch
) + regnum
,
5271 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5274 return RETURN_VALUE_REGISTER_CONVENTION
;
5278 /* A scalar extract each part but least-significant-byte
5282 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5283 offset
< TYPE_LENGTH (type
);
5284 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5286 int xfer
= register_size (gdbarch
, regnum
);
5287 if (offset
+ xfer
> TYPE_LENGTH (type
))
5288 xfer
= TYPE_LENGTH (type
) - offset
;
5290 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5291 offset
, xfer
, regnum
);
5292 mips_xfer_register (gdbarch
, regcache
,
5293 gdbarch_num_regs (gdbarch
) + regnum
,
5294 xfer
, gdbarch_byte_order (gdbarch
),
5295 readbuf
, writebuf
, offset
);
5297 return RETURN_VALUE_REGISTER_CONVENTION
;
5301 /* Which registers to use for passing floating-point values between
5302 function calls, one of floating-point, general and both kinds of
5303 registers. O32 and O64 use different register kinds for standard
5304 MIPS and MIPS16 code; to make the handling of cases where we may
5305 not know what kind of code is being used (e.g. no debug information)
5306 easier we sometimes use both kinds. */
5315 /* O32 ABI stuff. */
5318 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5319 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5320 int nargs
, struct value
**args
, CORE_ADDR sp
,
5321 int struct_return
, CORE_ADDR struct_addr
)
5327 int stack_offset
= 0;
5328 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5329 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5331 /* For shared libraries, "t9" needs to point at the function
5333 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5335 /* Set the return address register to point to the entry point of
5336 the program, where a breakpoint lies in wait. */
5337 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5339 /* First ensure that the stack and structure return address (if any)
5340 are properly aligned. The stack has to be at least 64-bit
5341 aligned even on 32-bit machines, because doubles must be 64-bit
5342 aligned. For n32 and n64, stack frames need to be 128-bit
5343 aligned, so we round to this widest known alignment. */
5345 sp
= align_down (sp
, 16);
5346 struct_addr
= align_down (struct_addr
, 16);
5348 /* Now make space on the stack for the args. */
5349 for (argnum
= 0; argnum
< nargs
; argnum
++)
5351 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5353 /* Align to double-word if necessary. */
5354 if (mips_type_needs_double_align (arg_type
))
5355 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5356 /* Allocate space on the stack. */
5357 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5359 sp
-= align_up (len
, 16);
5362 fprintf_unfiltered (gdb_stdlog
,
5363 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5364 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5366 /* Initialize the integer and float register pointers. */
5367 argreg
= MIPS_A0_REGNUM
;
5368 float_argreg
= mips_fpa0_regnum (gdbarch
);
5370 /* The struct_return pointer occupies the first parameter-passing reg. */
5374 fprintf_unfiltered (gdb_stdlog
,
5375 "mips_o32_push_dummy_call: "
5376 "struct_return reg=%d %s\n",
5377 argreg
, paddress (gdbarch
, struct_addr
));
5378 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5379 stack_offset
+= MIPS32_REGSIZE
;
5382 /* Now load as many as possible of the first arguments into
5383 registers, and push the rest onto the stack. Loop thru args
5384 from first to last. */
5385 for (argnum
= 0; argnum
< nargs
; argnum
++)
5387 const gdb_byte
*val
;
5388 struct value
*arg
= args
[argnum
];
5389 struct type
*arg_type
= check_typedef (value_type (arg
));
5390 int len
= TYPE_LENGTH (arg_type
);
5391 enum type_code typecode
= TYPE_CODE (arg_type
);
5394 fprintf_unfiltered (gdb_stdlog
,
5395 "mips_o32_push_dummy_call: %d len=%d type=%d",
5396 argnum
+ 1, len
, (int) typecode
);
5398 val
= value_contents (arg
);
5400 /* 32-bit ABIs always start floating point arguments in an
5401 even-numbered floating point register. Round the FP register
5402 up before the check to see if there are any FP registers
5403 left. O32 targets also pass the FP in the integer registers
5404 so also round up normal registers. */
5405 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5407 if ((float_argreg
& 1))
5411 /* Floating point arguments passed in registers have to be
5412 treated specially. On 32-bit architectures, doubles are
5413 passed in register pairs; the even FP register gets the
5414 low word, and the odd FP register gets the high word.
5415 On O32, the first two floating point arguments are also
5416 copied to general registers, following their memory order,
5417 because MIPS16 functions don't use float registers for
5418 arguments. This duplication of arguments in general
5419 registers can't hurt non-MIPS16 functions, because those
5420 registers are normally skipped. */
5422 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5423 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5425 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5427 int freg_offset
= gdbarch_byte_order (gdbarch
)
5428 == BFD_ENDIAN_BIG
? 1 : 0;
5429 unsigned long regval
;
5432 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5434 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5435 float_argreg
+ freg_offset
,
5437 regcache_cooked_write_unsigned (regcache
,
5438 float_argreg
++ + freg_offset
,
5441 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5442 argreg
, phex (regval
, 4));
5443 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5446 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5448 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5449 float_argreg
- freg_offset
,
5451 regcache_cooked_write_unsigned (regcache
,
5452 float_argreg
++ - freg_offset
,
5455 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5456 argreg
, phex (regval
, 4));
5457 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5461 /* This is a floating point value that fits entirely
5462 in a single register. */
5463 /* On 32 bit ABI's the float_argreg is further adjusted
5464 above to ensure that it is even register aligned. */
5465 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5467 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5468 float_argreg
, phex (regval
, len
));
5469 regcache_cooked_write_unsigned (regcache
,
5470 float_argreg
++, regval
);
5471 /* Although two FP registers are reserved for each
5472 argument, only one corresponding integer register is
5475 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5476 argreg
, phex (regval
, len
));
5477 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5479 /* Reserve space for the FP register. */
5480 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5484 /* Copy the argument to general registers or the stack in
5485 register-sized pieces. Large arguments are split between
5486 registers and stack. */
5487 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5488 are treated specially: Irix cc passes
5489 them in registers where gcc sometimes puts them on the
5490 stack. For maximum compatibility, we will put them in
5492 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5493 && len
% MIPS32_REGSIZE
!= 0);
5494 /* Structures should be aligned to eight bytes (even arg registers)
5495 on MIPS_ABI_O32, if their first member has double precision. */
5496 if (mips_type_needs_double_align (arg_type
))
5501 stack_offset
+= MIPS32_REGSIZE
;
5506 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5509 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5512 /* Write this portion of the argument to the stack. */
5513 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5514 || odd_sized_struct
)
5516 /* Should shorter than int integer values be
5517 promoted to int before being stored? */
5518 int longword_offset
= 0;
5523 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5524 paddress (gdbarch
, stack_offset
));
5525 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5526 paddress (gdbarch
, longword_offset
));
5529 addr
= sp
+ stack_offset
+ longword_offset
;
5534 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5535 paddress (gdbarch
, addr
));
5536 for (i
= 0; i
< partial_len
; i
++)
5538 fprintf_unfiltered (gdb_stdlog
, "%02x",
5542 write_memory (addr
, val
, partial_len
);
5545 /* Note!!! This is NOT an else clause. Odd sized
5546 structs may go thru BOTH paths. */
5547 /* Write this portion of the argument to a general
5548 purpose register. */
5549 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5551 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5553 /* Value may need to be sign extended, because
5554 mips_isa_regsize() != mips_abi_regsize(). */
5556 /* A non-floating-point argument being passed in a
5557 general register. If a struct or union, and if
5558 the remaining length is smaller than the register
5559 size, we have to adjust the register value on
5562 It does not seem to be necessary to do the
5563 same for integral types.
5565 Also don't do this adjustment on O64 binaries.
5567 cagney/2001-07-23: gdb/179: Also, GCC, when
5568 outputting LE O32 with sizeof (struct) <
5569 mips_abi_regsize(), generates a left shift
5570 as part of storing the argument in a register
5571 (the left shift isn't generated when
5572 sizeof (struct) >= mips_abi_regsize()). Since
5573 it is quite possible that this is GCC
5574 contradicting the LE/O32 ABI, GDB has not been
5575 adjusted to accommodate this. Either someone
5576 needs to demonstrate that the LE/O32 ABI
5577 specifies such a left shift OR this new ABI gets
5578 identified as such and GDB gets tweaked
5581 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5582 && partial_len
< MIPS32_REGSIZE
5583 && (typecode
== TYPE_CODE_STRUCT
5584 || typecode
== TYPE_CODE_UNION
))
5585 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5589 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5591 phex (regval
, MIPS32_REGSIZE
));
5592 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5595 /* Prevent subsequent floating point arguments from
5596 being passed in floating point registers. */
5597 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5603 /* Compute the offset into the stack at which we will
5604 copy the next parameter.
5606 In older ABIs, the caller reserved space for
5607 registers that contained arguments. This was loosely
5608 refered to as their "home". Consequently, space is
5609 always allocated. */
5611 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5615 fprintf_unfiltered (gdb_stdlog
, "\n");
5618 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5620 /* Return adjusted stack pointer. */
5624 static enum return_value_convention
5625 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5626 struct type
*type
, struct regcache
*regcache
,
5627 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5629 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5630 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5631 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5632 enum mips_fval_reg fval_reg
;
5634 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5635 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5636 || TYPE_CODE (type
) == TYPE_CODE_UNION
5637 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5638 return RETURN_VALUE_STRUCT_CONVENTION
;
5639 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5640 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5642 /* A single-precision floating-point value. If reading in or copying,
5643 then we get it from/put it to FP0 for standard MIPS code or GPR2
5644 for MIPS16 code. If writing out only, then we put it to both FP0
5645 and GPR2. We do not support reading in with no function known, if
5646 this safety check ever triggers, then we'll have to try harder. */
5647 gdb_assert (function
|| !readbuf
);
5652 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5655 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5657 case mips_fval_both
:
5658 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5661 if (fval_reg
!= mips_fval_gpr
)
5662 mips_xfer_register (gdbarch
, regcache
,
5663 (gdbarch_num_regs (gdbarch
)
5664 + mips_regnum (gdbarch
)->fp0
),
5666 gdbarch_byte_order (gdbarch
),
5667 readbuf
, writebuf
, 0);
5668 if (fval_reg
!= mips_fval_fpr
)
5669 mips_xfer_register (gdbarch
, regcache
,
5670 gdbarch_num_regs (gdbarch
) + 2,
5672 gdbarch_byte_order (gdbarch
),
5673 readbuf
, writebuf
, 0);
5674 return RETURN_VALUE_REGISTER_CONVENTION
;
5676 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5677 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5679 /* A double-precision floating-point value. If reading in or copying,
5680 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5681 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5682 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5683 no function known, if this safety check ever triggers, then we'll
5684 have to try harder. */
5685 gdb_assert (function
|| !readbuf
);
5690 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5693 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5695 case mips_fval_both
:
5696 fprintf_unfiltered (gdb_stderr
,
5697 "Return float in $fp1/$fp0 and $2/$3\n");
5700 if (fval_reg
!= mips_fval_gpr
)
5702 /* The most significant part goes in FP1, and the least significant
5704 switch (gdbarch_byte_order (gdbarch
))
5706 case BFD_ENDIAN_LITTLE
:
5707 mips_xfer_register (gdbarch
, regcache
,
5708 (gdbarch_num_regs (gdbarch
)
5709 + mips_regnum (gdbarch
)->fp0
+ 0),
5710 4, gdbarch_byte_order (gdbarch
),
5711 readbuf
, writebuf
, 0);
5712 mips_xfer_register (gdbarch
, regcache
,
5713 (gdbarch_num_regs (gdbarch
)
5714 + mips_regnum (gdbarch
)->fp0
+ 1),
5715 4, gdbarch_byte_order (gdbarch
),
5716 readbuf
, writebuf
, 4);
5718 case BFD_ENDIAN_BIG
:
5719 mips_xfer_register (gdbarch
, regcache
,
5720 (gdbarch_num_regs (gdbarch
)
5721 + mips_regnum (gdbarch
)->fp0
+ 1),
5722 4, gdbarch_byte_order (gdbarch
),
5723 readbuf
, writebuf
, 0);
5724 mips_xfer_register (gdbarch
, regcache
,
5725 (gdbarch_num_regs (gdbarch
)
5726 + mips_regnum (gdbarch
)->fp0
+ 0),
5727 4, gdbarch_byte_order (gdbarch
),
5728 readbuf
, writebuf
, 4);
5731 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5734 if (fval_reg
!= mips_fval_fpr
)
5736 /* The two 32-bit parts are always placed in GPR2 and GPR3
5737 following these registers' memory order. */
5738 mips_xfer_register (gdbarch
, regcache
,
5739 gdbarch_num_regs (gdbarch
) + 2,
5740 4, gdbarch_byte_order (gdbarch
),
5741 readbuf
, writebuf
, 0);
5742 mips_xfer_register (gdbarch
, regcache
,
5743 gdbarch_num_regs (gdbarch
) + 3,
5744 4, gdbarch_byte_order (gdbarch
),
5745 readbuf
, writebuf
, 4);
5747 return RETURN_VALUE_REGISTER_CONVENTION
;
5750 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5751 && TYPE_NFIELDS (type
) <= 2
5752 && TYPE_NFIELDS (type
) >= 1
5753 && ((TYPE_NFIELDS (type
) == 1
5754 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5756 || (TYPE_NFIELDS (type
) == 2
5757 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5759 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5761 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5763 /* A struct that contains one or two floats. Each value is part
5764 in the least significant part of their floating point
5768 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5769 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5771 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5774 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5776 mips_xfer_register (gdbarch
, regcache
,
5777 gdbarch_num_regs (gdbarch
) + regnum
,
5778 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5779 gdbarch_byte_order (gdbarch
),
5780 readbuf
, writebuf
, offset
);
5782 return RETURN_VALUE_REGISTER_CONVENTION
;
5786 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5787 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5789 /* A structure or union. Extract the left justified value,
5790 regardless of the byte order. I.e. DO NOT USE
5794 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5795 offset
< TYPE_LENGTH (type
);
5796 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5798 int xfer
= register_size (gdbarch
, regnum
);
5799 if (offset
+ xfer
> TYPE_LENGTH (type
))
5800 xfer
= TYPE_LENGTH (type
) - offset
;
5802 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5803 offset
, xfer
, regnum
);
5804 mips_xfer_register (gdbarch
, regcache
,
5805 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5806 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5808 return RETURN_VALUE_REGISTER_CONVENTION
;
5813 /* A scalar extract each part but least-significant-byte
5814 justified. o32 thinks registers are 4 byte, regardless of
5818 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5819 offset
< TYPE_LENGTH (type
);
5820 offset
+= MIPS32_REGSIZE
, regnum
++)
5822 int xfer
= MIPS32_REGSIZE
;
5823 if (offset
+ xfer
> TYPE_LENGTH (type
))
5824 xfer
= TYPE_LENGTH (type
) - offset
;
5826 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5827 offset
, xfer
, regnum
);
5828 mips_xfer_register (gdbarch
, regcache
,
5829 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5830 gdbarch_byte_order (gdbarch
),
5831 readbuf
, writebuf
, offset
);
5833 return RETURN_VALUE_REGISTER_CONVENTION
;
5837 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5841 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5842 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5844 struct value
**args
, CORE_ADDR sp
,
5845 int struct_return
, CORE_ADDR struct_addr
)
5851 int stack_offset
= 0;
5852 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5853 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5855 /* For shared libraries, "t9" needs to point at the function
5857 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5859 /* Set the return address register to point to the entry point of
5860 the program, where a breakpoint lies in wait. */
5861 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5863 /* First ensure that the stack and structure return address (if any)
5864 are properly aligned. The stack has to be at least 64-bit
5865 aligned even on 32-bit machines, because doubles must be 64-bit
5866 aligned. For n32 and n64, stack frames need to be 128-bit
5867 aligned, so we round to this widest known alignment. */
5869 sp
= align_down (sp
, 16);
5870 struct_addr
= align_down (struct_addr
, 16);
5872 /* Now make space on the stack for the args. */
5873 for (argnum
= 0; argnum
< nargs
; argnum
++)
5875 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5877 /* Allocate space on the stack. */
5878 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5880 sp
-= align_up (len
, 16);
5883 fprintf_unfiltered (gdb_stdlog
,
5884 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5885 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5887 /* Initialize the integer and float register pointers. */
5888 argreg
= MIPS_A0_REGNUM
;
5889 float_argreg
= mips_fpa0_regnum (gdbarch
);
5891 /* The struct_return pointer occupies the first parameter-passing reg. */
5895 fprintf_unfiltered (gdb_stdlog
,
5896 "mips_o64_push_dummy_call: "
5897 "struct_return reg=%d %s\n",
5898 argreg
, paddress (gdbarch
, struct_addr
));
5899 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5900 stack_offset
+= MIPS64_REGSIZE
;
5903 /* Now load as many as possible of the first arguments into
5904 registers, and push the rest onto the stack. Loop thru args
5905 from first to last. */
5906 for (argnum
= 0; argnum
< nargs
; argnum
++)
5908 const gdb_byte
*val
;
5909 struct value
*arg
= args
[argnum
];
5910 struct type
*arg_type
= check_typedef (value_type (arg
));
5911 int len
= TYPE_LENGTH (arg_type
);
5912 enum type_code typecode
= TYPE_CODE (arg_type
);
5915 fprintf_unfiltered (gdb_stdlog
,
5916 "mips_o64_push_dummy_call: %d len=%d type=%d",
5917 argnum
+ 1, len
, (int) typecode
);
5919 val
= value_contents (arg
);
5921 /* Floating point arguments passed in registers have to be
5922 treated specially. On 32-bit architectures, doubles are
5923 passed in register pairs; the even FP register gets the
5924 low word, and the odd FP register gets the high word.
5925 On O64, the first two floating point arguments are also
5926 copied to general registers, because MIPS16 functions
5927 don't use float registers for arguments. This duplication
5928 of arguments in general registers can't hurt non-MIPS16
5929 functions because those registers are normally skipped. */
5931 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5932 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5934 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5936 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5937 float_argreg
, phex (regval
, len
));
5938 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5940 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5941 argreg
, phex (regval
, len
));
5942 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5944 /* Reserve space for the FP register. */
5945 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5949 /* Copy the argument to general registers or the stack in
5950 register-sized pieces. Large arguments are split between
5951 registers and stack. */
5952 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5953 are treated specially: Irix cc passes them in registers
5954 where gcc sometimes puts them on the stack. For maximum
5955 compatibility, we will put them in both places. */
5956 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5957 && len
% MIPS64_REGSIZE
!= 0);
5960 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5963 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5966 /* Write this portion of the argument to the stack. */
5967 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5968 || odd_sized_struct
)
5970 /* Should shorter than int integer values be
5971 promoted to int before being stored? */
5972 int longword_offset
= 0;
5974 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5976 if ((typecode
== TYPE_CODE_INT
5977 || typecode
== TYPE_CODE_PTR
5978 || typecode
== TYPE_CODE_FLT
)
5980 longword_offset
= MIPS64_REGSIZE
- len
;
5985 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5986 paddress (gdbarch
, stack_offset
));
5987 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5988 paddress (gdbarch
, longword_offset
));
5991 addr
= sp
+ stack_offset
+ longword_offset
;
5996 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5997 paddress (gdbarch
, addr
));
5998 for (i
= 0; i
< partial_len
; i
++)
6000 fprintf_unfiltered (gdb_stdlog
, "%02x",
6004 write_memory (addr
, val
, partial_len
);
6007 /* Note!!! This is NOT an else clause. Odd sized
6008 structs may go thru BOTH paths. */
6009 /* Write this portion of the argument to a general
6010 purpose register. */
6011 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
6013 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6015 /* Value may need to be sign extended, because
6016 mips_isa_regsize() != mips_abi_regsize(). */
6018 /* A non-floating-point argument being passed in a
6019 general register. If a struct or union, and if
6020 the remaining length is smaller than the register
6021 size, we have to adjust the register value on
6024 It does not seem to be necessary to do the
6025 same for integral types. */
6027 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6028 && partial_len
< MIPS64_REGSIZE
6029 && (typecode
== TYPE_CODE_STRUCT
6030 || typecode
== TYPE_CODE_UNION
))
6031 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6035 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
6037 phex (regval
, MIPS64_REGSIZE
));
6038 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6041 /* Prevent subsequent floating point arguments from
6042 being passed in floating point registers. */
6043 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
6049 /* Compute the offset into the stack at which we will
6050 copy the next parameter.
6052 In older ABIs, the caller reserved space for
6053 registers that contained arguments. This was loosely
6054 refered to as their "home". Consequently, space is
6055 always allocated. */
6057 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6061 fprintf_unfiltered (gdb_stdlog
, "\n");
6064 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6066 /* Return adjusted stack pointer. */
6070 static enum return_value_convention
6071 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6072 struct type
*type
, struct regcache
*regcache
,
6073 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6075 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6076 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6077 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6078 enum mips_fval_reg fval_reg
;
6080 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6081 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
6082 || TYPE_CODE (type
) == TYPE_CODE_UNION
6083 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
6084 return RETURN_VALUE_STRUCT_CONVENTION
;
6085 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
6087 /* A floating-point value. If reading in or copying, then we get it
6088 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6089 If writing out only, then we put it to both FP0 and GPR2. We do
6090 not support reading in with no function known, if this safety
6091 check ever triggers, then we'll have to try harder. */
6092 gdb_assert (function
|| !readbuf
);
6097 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6100 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6102 case mips_fval_both
:
6103 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6106 if (fval_reg
!= mips_fval_gpr
)
6107 mips_xfer_register (gdbarch
, regcache
,
6108 (gdbarch_num_regs (gdbarch
)
6109 + mips_regnum (gdbarch
)->fp0
),
6111 gdbarch_byte_order (gdbarch
),
6112 readbuf
, writebuf
, 0);
6113 if (fval_reg
!= mips_fval_fpr
)
6114 mips_xfer_register (gdbarch
, regcache
,
6115 gdbarch_num_regs (gdbarch
) + 2,
6117 gdbarch_byte_order (gdbarch
),
6118 readbuf
, writebuf
, 0);
6119 return RETURN_VALUE_REGISTER_CONVENTION
;
6123 /* A scalar extract each part but least-significant-byte
6127 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6128 offset
< TYPE_LENGTH (type
);
6129 offset
+= MIPS64_REGSIZE
, regnum
++)
6131 int xfer
= MIPS64_REGSIZE
;
6132 if (offset
+ xfer
> TYPE_LENGTH (type
))
6133 xfer
= TYPE_LENGTH (type
) - offset
;
6135 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6136 offset
, xfer
, regnum
);
6137 mips_xfer_register (gdbarch
, regcache
,
6138 gdbarch_num_regs (gdbarch
) + regnum
,
6139 xfer
, gdbarch_byte_order (gdbarch
),
6140 readbuf
, writebuf
, offset
);
6142 return RETURN_VALUE_REGISTER_CONVENTION
;
6146 /* Floating point register management.
6148 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6149 64bit operations, these early MIPS cpus treat fp register pairs
6150 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6151 registers and offer a compatibility mode that emulates the MIPS2 fp
6152 model. When operating in MIPS2 fp compat mode, later cpu's split
6153 double precision floats into two 32-bit chunks and store them in
6154 consecutive fp regs. To display 64-bit floats stored in this
6155 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6156 Throw in user-configurable endianness and you have a real mess.
6158 The way this works is:
6159 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6160 double-precision value will be split across two logical registers.
6161 The lower-numbered logical register will hold the low-order bits,
6162 regardless of the processor's endianness.
6163 - If we are on a 64-bit processor, and we are looking for a
6164 single-precision value, it will be in the low ordered bits
6165 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6166 save slot in memory.
6167 - If we are in 64-bit mode, everything is straightforward.
6169 Note that this code only deals with "live" registers at the top of the
6170 stack. We will attempt to deal with saved registers later, when
6171 the raw/cooked register interface is in place. (We need a general
6172 interface that can deal with dynamic saved register sizes -- fp
6173 regs could be 32 bits wide in one frame and 64 on the frame above
6176 /* Copy a 32-bit single-precision value from the current frame
6177 into rare_buffer. */
6180 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6181 gdb_byte
*rare_buffer
)
6183 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6184 int raw_size
= register_size (gdbarch
, regno
);
6185 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6187 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6188 error (_("can't read register %d (%s)"),
6189 regno
, gdbarch_register_name (gdbarch
, regno
));
6192 /* We have a 64-bit value for this register. Find the low-order
6196 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6201 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6205 memcpy (rare_buffer
, raw_buffer
, 4);
6209 /* Copy a 64-bit double-precision value from the current frame into
6210 rare_buffer. This may include getting half of it from the next
6214 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6215 gdb_byte
*rare_buffer
)
6217 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6218 int raw_size
= register_size (gdbarch
, regno
);
6220 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6222 /* We have a 64-bit value for this register, and we should use
6224 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6225 error (_("can't read register %d (%s)"),
6226 regno
, gdbarch_register_name (gdbarch
, regno
));
6230 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6232 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6233 internal_error (__FILE__
, __LINE__
,
6234 _("mips_read_fp_register_double: bad access to "
6235 "odd-numbered FP register"));
6237 /* mips_read_fp_register_single will find the correct 32 bits from
6239 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6241 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6242 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6246 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6247 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6253 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6255 { /* Do values for FP (float) regs. */
6256 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6257 gdb_byte
*raw_buffer
;
6258 std::string flt_str
, dbl_str
;
6260 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
6261 const struct type
*dbl_type
= builtin_type (gdbarch
)->builtin_double
;
6265 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6267 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6268 fprintf_filtered (file
, "%*s",
6269 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6272 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6274 struct value_print_options opts
;
6276 /* 4-byte registers: Print hex and floating. Also print even
6277 numbered registers as doubles. */
6278 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6279 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6281 get_formatted_print_options (&opts
, 'x');
6282 print_scalar_formatted (raw_buffer
,
6283 builtin_type (gdbarch
)->builtin_uint32
,
6286 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6288 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6290 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6291 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6293 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6298 struct value_print_options opts
;
6300 /* Eight byte registers: print each one as hex, float and double. */
6301 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6302 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6304 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6305 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6307 get_formatted_print_options (&opts
, 'x');
6308 print_scalar_formatted (raw_buffer
,
6309 builtin_type (gdbarch
)->builtin_uint64
,
6312 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6313 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6318 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6321 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6322 struct value_print_options opts
;
6325 if (mips_float_register_p (gdbarch
, regnum
))
6327 mips_print_fp_register (file
, frame
, regnum
);
6331 val
= get_frame_register_value (frame
, regnum
);
6333 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6335 /* The problem with printing numeric register names (r26, etc.) is that
6336 the user can't use them on input. Probably the best solution is to
6337 fix it so that either the numeric or the funky (a2, etc.) names
6338 are accepted on input. */
6339 if (regnum
< MIPS_NUMREGS
)
6340 fprintf_filtered (file
, "(r%d): ", regnum
);
6342 fprintf_filtered (file
, ": ");
6344 get_formatted_print_options (&opts
, 'x');
6345 val_print_scalar_formatted (value_type (val
),
6346 value_embedded_offset (val
),
6351 /* Print IEEE exception condition bits in FLAGS. */
6354 print_fpu_flags (struct ui_file
*file
, int flags
)
6356 if (flags
& (1 << 0))
6357 fputs_filtered (" inexact", file
);
6358 if (flags
& (1 << 1))
6359 fputs_filtered (" uflow", file
);
6360 if (flags
& (1 << 2))
6361 fputs_filtered (" oflow", file
);
6362 if (flags
& (1 << 3))
6363 fputs_filtered (" div0", file
);
6364 if (flags
& (1 << 4))
6365 fputs_filtered (" inval", file
);
6366 if (flags
& (1 << 5))
6367 fputs_filtered (" unimp", file
);
6368 fputc_filtered ('\n', file
);
6371 /* Print interesting information about the floating point processor
6372 (if present) or emulator. */
6375 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6376 struct frame_info
*frame
, const char *args
)
6378 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6379 enum mips_fpu_type type
= MIPS_FPU_TYPE (gdbarch
);
6383 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6384 type
= MIPS_FPU_NONE
;
6386 fprintf_filtered (file
, "fpu type: %s\n",
6387 type
== MIPS_FPU_DOUBLE
? "double-precision"
6388 : type
== MIPS_FPU_SINGLE
? "single-precision"
6391 if (type
== MIPS_FPU_NONE
)
6394 fprintf_filtered (file
, "reg size: %d bits\n",
6395 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6397 fputs_filtered ("cond :", file
);
6398 if (fcs
& (1 << 23))
6399 fputs_filtered (" 0", file
);
6400 for (i
= 1; i
<= 7; i
++)
6401 if (fcs
& (1 << (24 + i
)))
6402 fprintf_filtered (file
, " %d", i
);
6403 fputc_filtered ('\n', file
);
6405 fputs_filtered ("cause :", file
);
6406 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6407 fputs ("mask :", stdout
);
6408 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6409 fputs ("flags :", stdout
);
6410 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6412 fputs_filtered ("rounding: ", file
);
6415 case 0: fputs_filtered ("nearest\n", file
); break;
6416 case 1: fputs_filtered ("zero\n", file
); break;
6417 case 2: fputs_filtered ("+inf\n", file
); break;
6418 case 3: fputs_filtered ("-inf\n", file
); break;
6421 fputs_filtered ("flush :", file
);
6422 if (fcs
& (1 << 21))
6423 fputs_filtered (" nearest", file
);
6424 if (fcs
& (1 << 22))
6425 fputs_filtered (" override", file
);
6426 if (fcs
& (1 << 24))
6427 fputs_filtered (" zero", file
);
6428 if ((fcs
& (0xb << 21)) == 0)
6429 fputs_filtered (" no", file
);
6430 fputc_filtered ('\n', file
);
6432 fprintf_filtered (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6433 fprintf_filtered (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6434 fputc_filtered ('\n', file
);
6436 default_print_float_info (gdbarch
, file
, frame
, args
);
6439 /* Replacement for generic do_registers_info.
6440 Print regs in pretty columns. */
6443 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6446 fprintf_filtered (file
, " ");
6447 mips_print_fp_register (file
, frame
, regnum
);
6448 fprintf_filtered (file
, "\n");
6453 /* Print a row's worth of GP (int) registers, with name labels above. */
6456 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6459 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6460 /* Do values for GP (int) regs. */
6461 const gdb_byte
*raw_buffer
;
6462 struct value
*value
;
6463 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6468 /* For GP registers, we print a separate row of names above the vals. */
6469 for (col
= 0, regnum
= start_regnum
;
6470 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6471 + gdbarch_num_pseudo_regs (gdbarch
);
6474 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6475 continue; /* unused register */
6476 if (mips_float_register_p (gdbarch
, regnum
))
6477 break; /* End the row: reached FP register. */
6478 /* Large registers are handled separately. */
6479 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6482 break; /* End the row before this register. */
6484 /* Print this register on a row by itself. */
6485 mips_print_register (file
, frame
, regnum
);
6486 fprintf_filtered (file
, "\n");
6490 fprintf_filtered (file
, " ");
6491 fprintf_filtered (file
,
6492 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6493 gdbarch_register_name (gdbarch
, regnum
));
6500 /* Print the R0 to R31 names. */
6501 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6502 fprintf_filtered (file
, "\n R%-4d",
6503 start_regnum
% gdbarch_num_regs (gdbarch
));
6505 fprintf_filtered (file
, "\n ");
6507 /* Now print the values in hex, 4 or 8 to the row. */
6508 for (col
= 0, regnum
= start_regnum
;
6509 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6510 + gdbarch_num_pseudo_regs (gdbarch
);
6513 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6514 continue; /* unused register */
6515 if (mips_float_register_p (gdbarch
, regnum
))
6516 break; /* End row: reached FP register. */
6517 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6518 break; /* End row: large register. */
6520 /* OK: get the data in raw format. */
6521 value
= get_frame_register_value (frame
, regnum
);
6522 if (value_optimized_out (value
)
6523 || !value_entirely_available (value
))
6525 fprintf_filtered (file
, "%*s ",
6526 (int) mips_abi_regsize (gdbarch
) * 2,
6527 (mips_abi_regsize (gdbarch
) == 4 ? "<unavl>"
6528 : "<unavailable>"));
6532 raw_buffer
= value_contents_all (value
);
6533 /* pad small registers */
6535 byte
< (mips_abi_regsize (gdbarch
)
6536 - register_size (gdbarch
, regnum
)); byte
++)
6537 fprintf_filtered (file
, " ");
6538 /* Now print the register value in hex, endian order. */
6539 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6541 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6542 byte
< register_size (gdbarch
, regnum
); byte
++)
6543 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6545 for (byte
= register_size (gdbarch
, regnum
) - 1;
6547 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6548 fprintf_filtered (file
, " ");
6551 if (col
> 0) /* ie. if we actually printed anything... */
6552 fprintf_filtered (file
, "\n");
6557 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6560 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6561 struct frame_info
*frame
, int regnum
, int all
)
6563 if (regnum
!= -1) /* Do one specified register. */
6565 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6566 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6567 error (_("Not a valid register for the current processor type"));
6569 mips_print_register (file
, frame
, regnum
);
6570 fprintf_filtered (file
, "\n");
6573 /* Do all (or most) registers. */
6575 regnum
= gdbarch_num_regs (gdbarch
);
6576 while (regnum
< gdbarch_num_regs (gdbarch
)
6577 + gdbarch_num_pseudo_regs (gdbarch
))
6579 if (mips_float_register_p (gdbarch
, regnum
))
6581 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6582 regnum
= print_fp_register_row (file
, frame
, regnum
);
6584 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6587 regnum
= print_gp_register_row (file
, frame
, regnum
);
6593 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6594 struct frame_info
*frame
)
6596 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6597 CORE_ADDR pc
= get_frame_pc (frame
);
6603 if ((mips_pc_is_mips (pc
)
6604 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6605 || (mips_pc_is_micromips (gdbarch
, pc
)
6606 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6607 || (mips_pc_is_mips16 (gdbarch
, pc
)
6608 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6611 isa
= mips_pc_isa (gdbarch
, pc
);
6612 /* _has_delay_slot above will have validated the read. */
6613 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6614 size
= mips_insn_size (isa
, insn
);
6616 const address_space
*aspace
= get_frame_address_space (frame
);
6618 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6621 /* To skip prologues, I use this predicate. Returns either PC itself
6622 if the code at PC does not look like a function prologue; otherwise
6623 returns an address that (if we're lucky) follows the prologue. If
6624 LENIENT, then we must skip everything which is involved in setting
6625 up the frame (it's OK to skip more, just so long as we don't skip
6626 anything which might clobber the registers which are being saved.
6627 We must skip more in the case where part of the prologue is in the
6628 delay slot of a non-prologue instruction). */
6631 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6634 CORE_ADDR func_addr
;
6636 /* See if we can determine the end of the prologue via the symbol table.
6637 If so, then return either PC, or the PC after the prologue, whichever
6639 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6641 CORE_ADDR post_prologue_pc
6642 = skip_prologue_using_sal (gdbarch
, func_addr
);
6643 if (post_prologue_pc
!= 0)
6644 return std::max (pc
, post_prologue_pc
);
6647 /* Can't determine prologue from the symbol table, need to examine
6650 /* Find an upper limit on the function prologue using the debug
6651 information. If the debug information could not be used to provide
6652 that bound, then use an arbitrary large number as the upper bound. */
6653 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6655 limit_pc
= pc
+ 100; /* Magic. */
6657 if (mips_pc_is_mips16 (gdbarch
, pc
))
6658 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6659 else if (mips_pc_is_micromips (gdbarch
, pc
))
6660 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6662 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6665 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6666 This is a helper function for mips_stack_frame_destroyed_p. */
6669 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6671 CORE_ADDR func_addr
= 0, func_end
= 0;
6673 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6675 /* The MIPS epilogue is max. 12 bytes long. */
6676 CORE_ADDR addr
= func_end
- 12;
6678 if (addr
< func_addr
+ 4)
6679 addr
= func_addr
+ 4;
6683 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6685 unsigned long high_word
;
6688 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6689 high_word
= (inst
>> 16) & 0xffff;
6691 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6692 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6693 && inst
!= 0x03e00008 /* jr $ra */
6694 && inst
!= 0x00000000) /* nop */
6704 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6705 This is a helper function for mips_stack_frame_destroyed_p. */
6708 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6710 CORE_ADDR func_addr
= 0;
6711 CORE_ADDR func_end
= 0;
6719 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6722 /* The microMIPS epilogue is max. 12 bytes long. */
6723 addr
= func_end
- 12;
6725 if (addr
< func_addr
+ 2)
6726 addr
= func_addr
+ 2;
6730 for (; pc
< func_end
; pc
+= loc
)
6733 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6734 loc
+= MIPS_INSN16_SIZE
;
6735 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6737 /* 32-bit instructions. */
6738 case 2 * MIPS_INSN16_SIZE
:
6740 insn
|= mips_fetch_instruction (gdbarch
,
6741 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6742 loc
+= MIPS_INSN16_SIZE
;
6743 switch (micromips_op (insn
>> 16))
6745 case 0xc: /* ADDIU: bits 001100 */
6746 case 0x17: /* DADDIU: bits 010111 */
6747 sreg
= b0s5_reg (insn
>> 16);
6748 dreg
= b5s5_reg (insn
>> 16);
6749 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6750 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6751 /* (D)ADDIU $sp, imm */
6761 /* 16-bit instructions. */
6762 case MIPS_INSN16_SIZE
:
6763 switch (micromips_op (insn
))
6765 case 0x3: /* MOVE: bits 000011 */
6766 sreg
= b0s5_reg (insn
);
6767 dreg
= b5s5_reg (insn
);
6768 if (sreg
== 0 && dreg
== 0)
6769 /* MOVE $zero, $zero aka NOP */
6773 case 0x11: /* POOL16C: bits 010001 */
6774 if (b5s5_op (insn
) == 0x18
6775 /* JRADDIUSP: bits 010011 11000 */
6776 || (b5s5_op (insn
) == 0xd
6777 /* JRC: bits 010011 01101 */
6778 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6783 case 0x13: /* POOL16D: bits 010011 */
6784 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6785 if ((insn
& 0x1) == 0x1
6786 /* ADDIUSP: bits 010011 1 */
6800 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6801 This is a helper function for mips_stack_frame_destroyed_p. */
6804 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6806 CORE_ADDR func_addr
= 0, func_end
= 0;
6808 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6810 /* The MIPS epilogue is max. 12 bytes long. */
6811 CORE_ADDR addr
= func_end
- 12;
6813 if (addr
< func_addr
+ 4)
6814 addr
= func_addr
+ 4;
6818 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6820 unsigned short inst
;
6822 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6824 if ((inst
& 0xf800) == 0xf000) /* extend */
6827 if (inst
!= 0x6300 /* addiu $sp,offset */
6828 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6829 && inst
!= 0xe820 /* jr $ra */
6830 && inst
!= 0xe8a0 /* jrc $ra */
6831 && inst
!= 0x6500) /* nop */
6841 /* Implement the stack_frame_destroyed_p gdbarch method.
6843 The epilogue is defined here as the area at the end of a function,
6844 after an instruction which destroys the function's stack frame. */
6847 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6849 if (mips_pc_is_mips16 (gdbarch
, pc
))
6850 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6851 else if (mips_pc_is_micromips (gdbarch
, pc
))
6852 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6854 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6857 /* Root of all "set mips "/"show mips " commands. This will eventually be
6858 used for all MIPS-specific commands. */
6861 show_mips_command (const char *args
, int from_tty
)
6863 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6867 set_mips_command (const char *args
, int from_tty
)
6870 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6871 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6874 /* Commands to show/set the MIPS FPU type. */
6877 show_mipsfpu_command (const char *args
, int from_tty
)
6881 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6884 ("The MIPS floating-point coprocessor is unknown "
6885 "because the current architecture is not MIPS.\n");
6889 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6891 case MIPS_FPU_SINGLE
:
6892 fpu
= "single-precision";
6894 case MIPS_FPU_DOUBLE
:
6895 fpu
= "double-precision";
6898 fpu
= "absent (none)";
6901 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6903 if (mips_fpu_type_auto
)
6904 printf_unfiltered ("The MIPS floating-point coprocessor "
6905 "is set automatically (currently %s)\n",
6909 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6914 set_mipsfpu_command (const char *args
, int from_tty
)
6916 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6917 "\"single\",\"none\" or \"auto\".\n");
6918 show_mipsfpu_command (args
, from_tty
);
6922 set_mipsfpu_single_command (const char *args
, int from_tty
)
6924 struct gdbarch_info info
;
6925 gdbarch_info_init (&info
);
6926 mips_fpu_type
= MIPS_FPU_SINGLE
;
6927 mips_fpu_type_auto
= 0;
6928 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6929 instead of relying on globals. Doing that would let generic code
6930 handle the search for this specific architecture. */
6931 if (!gdbarch_update_p (info
))
6932 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6936 set_mipsfpu_double_command (const char *args
, int from_tty
)
6938 struct gdbarch_info info
;
6939 gdbarch_info_init (&info
);
6940 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6941 mips_fpu_type_auto
= 0;
6942 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6943 instead of relying on globals. Doing that would let generic code
6944 handle the search for this specific architecture. */
6945 if (!gdbarch_update_p (info
))
6946 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6950 set_mipsfpu_none_command (const char *args
, int from_tty
)
6952 struct gdbarch_info info
;
6953 gdbarch_info_init (&info
);
6954 mips_fpu_type
= MIPS_FPU_NONE
;
6955 mips_fpu_type_auto
= 0;
6956 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6957 instead of relying on globals. Doing that would let generic code
6958 handle the search for this specific architecture. */
6959 if (!gdbarch_update_p (info
))
6960 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6964 set_mipsfpu_auto_command (const char *args
, int from_tty
)
6966 mips_fpu_type_auto
= 1;
6969 /* Just like reinit_frame_cache, but with the right arguments to be
6970 callable as an sfunc. */
6973 reinit_frame_cache_sfunc (const char *args
, int from_tty
,
6974 struct cmd_list_element
*c
)
6976 reinit_frame_cache ();
6980 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6982 gdb_disassembler
*di
6983 = static_cast<gdb_disassembler
*>(info
->application_data
);
6984 struct gdbarch
*gdbarch
= di
->arch ();
6986 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6987 disassembler needs to be able to locally determine the ISA, and
6988 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6990 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6991 info
->mach
= bfd_mach_mips16
;
6992 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6993 info
->mach
= bfd_mach_mips_micromips
;
6995 /* Round down the instruction address to the appropriate boundary. */
6996 memaddr
&= (info
->mach
== bfd_mach_mips16
6997 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
6999 /* Set the disassembler options. */
7000 if (!info
->disassembler_options
)
7001 /* This string is not recognized explicitly by the disassembler,
7002 but it tells the disassembler to not try to guess the ABI from
7003 the bfd elf headers, such that, if the user overrides the ABI
7004 of a program linked as NewABI, the disassembly will follow the
7005 register naming conventions specified by the user. */
7006 info
->disassembler_options
= "gpr-names=32";
7008 return default_print_insn (memaddr
, info
);
7012 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
7014 /* Set up the disassembler info, so that we get the right
7015 register names from libopcodes. */
7016 info
->disassembler_options
= "gpr-names=n32";
7017 info
->flavour
= bfd_target_elf_flavour
;
7019 return gdb_print_insn_mips (memaddr
, info
);
7023 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
7025 /* Set up the disassembler info, so that we get the right
7026 register names from libopcodes. */
7027 info
->disassembler_options
= "gpr-names=64";
7028 info
->flavour
= bfd_target_elf_flavour
;
7030 return gdb_print_insn_mips (memaddr
, info
);
7033 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7036 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7038 CORE_ADDR pc
= *pcptr
;
7040 if (mips_pc_is_mips16 (gdbarch
, pc
))
7042 *pcptr
= unmake_compact_addr (pc
);
7043 return MIPS_BP_KIND_MIPS16
;
7045 else if (mips_pc_is_micromips (gdbarch
, pc
))
7050 *pcptr
= unmake_compact_addr (pc
);
7051 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7052 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7053 return MIPS_BP_KIND_MICROMIPS16
;
7055 return MIPS_BP_KIND_MICROMIPS32
;
7058 return MIPS_BP_KIND_MIPS32
;
7061 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7063 static const gdb_byte
*
7064 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7066 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7070 case MIPS_BP_KIND_MIPS16
:
7072 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7073 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7076 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7077 return mips16_big_breakpoint
;
7079 return mips16_little_breakpoint
;
7081 case MIPS_BP_KIND_MICROMIPS16
:
7083 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7084 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7088 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7089 return micromips16_big_breakpoint
;
7091 return micromips16_little_breakpoint
;
7093 case MIPS_BP_KIND_MICROMIPS32
:
7095 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7096 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7099 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7100 return micromips32_big_breakpoint
;
7102 return micromips32_little_breakpoint
;
7104 case MIPS_BP_KIND_MIPS32
:
7106 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7107 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7110 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7111 return big_breakpoint
;
7113 return little_breakpoint
;
7116 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7120 /* Return non-zero if the standard MIPS instruction INST has a branch
7121 delay slot (i.e. it is a jump or branch instruction). This function
7122 is based on mips32_next_pc. */
7125 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7131 op
= itype_op (inst
);
7132 if ((inst
& 0xe0000000) != 0)
7134 rs
= itype_rs (inst
);
7135 rt
= itype_rt (inst
);
7136 return (is_octeon_bbit_op (op
, gdbarch
)
7137 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7138 || op
== 29 /* JALX: bits 011101 */
7141 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7142 || (rs
== 9 && (rt
& 0x2) == 0)
7143 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7144 || (rs
== 10 && (rt
& 0x2) == 0))));
7145 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7148 switch (op
& 0x07) /* extract bits 28,27,26 */
7150 case 0: /* SPECIAL */
7151 op
= rtype_funct (inst
);
7152 return (op
== 8 /* JR */
7153 || op
== 9); /* JALR */
7154 break; /* end SPECIAL */
7155 case 1: /* REGIMM */
7156 rs
= itype_rs (inst
);
7157 rt
= itype_rt (inst
); /* branch condition */
7158 return ((rt
& 0xc) == 0
7159 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7160 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7161 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7162 /* BPOSGE32, BPOSGE64: bits 1110x */
7163 break; /* end REGIMM */
7164 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7170 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7171 delay slot (i.e. it is a jump or branch instruction). */
7174 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7179 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7183 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7186 /* Return non-zero if the microMIPS instruction INSN, comprising the
7187 16-bit major opcode word in the high 16 bits and any second word
7188 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7189 jump or branch instruction). The instruction must be 32-bit if
7190 MUSTBE32 is set or can be any instruction otherwise. */
7193 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7195 ULONGEST major
= insn
>> 16;
7197 switch (micromips_op (major
))
7199 /* 16-bit instructions. */
7200 case 0x33: /* B16: bits 110011 */
7201 case 0x2b: /* BNEZ16: bits 101011 */
7202 case 0x23: /* BEQZ16: bits 100011 */
7204 case 0x11: /* POOL16C: bits 010001 */
7206 && ((b5s5_op (major
) == 0xc
7207 /* JR16: bits 010001 01100 */
7208 || (b5s5_op (major
) & 0x1e) == 0xe)));
7209 /* JALR16, JALRS16: bits 010001 0111x */
7210 /* 32-bit instructions. */
7211 case 0x3d: /* JAL: bits 111101 */
7212 case 0x3c: /* JALX: bits 111100 */
7213 case 0x35: /* J: bits 110101 */
7214 case 0x2d: /* BNE: bits 101101 */
7215 case 0x25: /* BEQ: bits 100101 */
7216 case 0x1d: /* JALS: bits 011101 */
7218 case 0x10: /* POOL32I: bits 010000 */
7219 return ((b5s5_op (major
) & 0x1c) == 0x0
7220 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7221 || (b5s5_op (major
) & 0x1d) == 0x4
7222 /* BLEZ, BGTZ: bits 010000 001x0 */
7223 || (b5s5_op (major
) & 0x1d) == 0x11
7224 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7225 || ((b5s5_op (major
) & 0x1e) == 0x14
7226 && (major
& 0x3) == 0x0)
7227 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7228 || (b5s5_op (major
) & 0x1e) == 0x1a
7229 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7230 || ((b5s5_op (major
) & 0x1e) == 0x1c
7231 && (major
& 0x3) == 0x0)
7232 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7233 || ((b5s5_op (major
) & 0x1c) == 0x1c
7234 && (major
& 0x3) == 0x1));
7235 /* BC1ANY*: bits 010000 111xx xxx01 */
7236 case 0x0: /* POOL32A: bits 000000 */
7237 return (b0s6_op (insn
) == 0x3c
7238 /* POOL32Axf: bits 000000 ... 111100 */
7239 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7240 /* JALR, JALR.HB: 000000 000x111100 111100 */
7241 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7247 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7248 slot (i.e. it is a non-compact jump instruction). The instruction
7249 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7252 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7253 CORE_ADDR addr
, int mustbe32
)
7259 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7262 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7264 if (size
== 2 * MIPS_INSN16_SIZE
)
7266 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7271 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7274 /* Return non-zero if the MIPS16 instruction INST, which must be
7275 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7276 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7277 instruction). This function is based on mips16_next_pc. */
7280 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7282 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7284 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7287 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7288 slot (i.e. it is a non-compact jump instruction). The instruction
7289 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7292 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7293 CORE_ADDR addr
, int mustbe32
)
7295 unsigned short insn
;
7298 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7302 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7305 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7306 This assumes KSSEG exists. */
7309 mips_segment_boundary (CORE_ADDR bpaddr
)
7311 CORE_ADDR mask
= CORE_ADDR_MAX
;
7314 if (sizeof (CORE_ADDR
) == 8)
7315 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7316 a compiler warning produced where CORE_ADDR is a 32-bit type even
7317 though in that case this is dead code). */
7318 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7321 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7322 segsize
= 29; /* 32-bit compatibility segment */
7324 segsize
= 62; /* xkseg */
7326 case 2: /* xkphys */
7329 default: /* xksseg (1), xkuseg/kuseg (0) */
7333 else if (bpaddr
& 0x80000000) /* kernel segment */
7336 segsize
= 31; /* user segment */
7338 return bpaddr
& mask
;
7341 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7342 it backwards if necessary. Return the address of the new location. */
7345 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7347 CORE_ADDR prev_addr
;
7349 CORE_ADDR func_addr
;
7351 /* If a breakpoint is set on the instruction in a branch delay slot,
7352 GDB gets confused. When the breakpoint is hit, the PC isn't on
7353 the instruction in the branch delay slot, the PC will point to
7354 the branch instruction. Since the PC doesn't match any known
7355 breakpoints, GDB reports a trap exception.
7357 There are two possible fixes for this problem.
7359 1) When the breakpoint gets hit, see if the BD bit is set in the
7360 Cause register (which indicates the last exception occurred in a
7361 branch delay slot). If the BD bit is set, fix the PC to point to
7362 the instruction in the branch delay slot.
7364 2) When the user sets the breakpoint, don't allow him to set the
7365 breakpoint on the instruction in the branch delay slot. Instead
7366 move the breakpoint to the branch instruction (which will have
7369 The problem with the first solution is that if the user then
7370 single-steps the processor, the branch instruction will get
7371 skipped (since GDB thinks the PC is on the instruction in the
7374 So, we'll use the second solution. To do this we need to know if
7375 the instruction we're trying to set the breakpoint on is in the
7376 branch delay slot. */
7378 boundary
= mips_segment_boundary (bpaddr
);
7380 /* Make sure we don't scan back before the beginning of the current
7381 function, since we may fetch constant data or insns that look like
7382 a jump. Of course we might do that anyway if the compiler has
7383 moved constants inline. :-( */
7384 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7385 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7386 boundary
= func_addr
;
7388 if (mips_pc_is_mips (bpaddr
))
7390 if (bpaddr
== boundary
)
7393 /* If the previous instruction has a branch delay slot, we have
7394 to move the breakpoint to the branch instruction. */
7395 prev_addr
= bpaddr
- 4;
7396 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7401 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7402 CORE_ADDR addr
, jmpaddr
;
7405 boundary
= unmake_compact_addr (boundary
);
7407 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7408 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7409 so try for that first, then try the 2 byte JALR/JR.
7410 The microMIPS ASE has a whole range of jumps and branches
7411 with delay slots, some of which take 4 bytes and some take
7412 2 bytes, so the idea is the same.
7413 FIXME: We have to assume that bpaddr is not the second half
7414 of an extended instruction. */
7415 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7416 ? micromips_insn_at_pc_has_delay_slot
7417 : mips16_insn_at_pc_has_delay_slot
);
7421 for (i
= 1; i
< 4; i
++)
7423 if (unmake_compact_addr (addr
) == boundary
)
7425 addr
-= MIPS_INSN16_SIZE
;
7426 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7427 /* Looks like a JR/JALR at [target-1], but it could be
7428 the second word of a previous JAL/JALX, so record it
7429 and check back one more. */
7431 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7434 /* Looks like a JAL/JALX at [target-2], but it could also
7435 be the second word of a previous JAL/JALX, record it,
7436 and check back one more. */
7439 /* Looks like a JAL/JALX at [target-3], so any previously
7440 recorded JAL/JALX or JR/JALR must be wrong, because:
7443 -2: JAL-ext (can't be JAL/JALX)
7444 -1: bdslot (can't be JR/JALR)
7447 Of course it could be another JAL-ext which looks
7448 like a JAL, but in that case we'd have broken out
7449 of this loop at [target-2]:
7453 -2: bdslot (can't be jmp)
7460 /* Not a jump instruction: if we're at [target-1] this
7461 could be the second word of a JAL/JALX, so continue;
7462 otherwise we're done. */
7475 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7476 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7479 mips_is_stub_suffix (const char *suffix
, int zero
)
7484 return zero
&& suffix
[1] == '\0';
7486 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7491 return suffix
[1] == '\0';
7497 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7498 call stubs, one of sf, df, sc, or dc. */
7501 mips_is_stub_mode (const char *mode
)
7503 return ((mode
[0] == 's' || mode
[0] == 'd')
7504 && (mode
[1] == 'f' || mode
[1] == 'c'));
7507 /* Code at PC is a compiler-generated stub. Such a stub for a function
7508 bar might have a name like __fn_stub_bar, and might look like this:
7515 followed by (or interspersed with):
7522 addiu $25, $25, %lo(bar)
7525 ($1 may be used in old code; for robustness we accept any register)
7528 lui $28, %hi(_gp_disp)
7529 addiu $28, $28, %lo(_gp_disp)
7532 addiu $25, $25, %lo(bar)
7535 In the case of a __call_stub_bar stub, the sequence to set up
7536 arguments might look like this:
7543 followed by (or interspersed with) one of the jump sequences above.
7545 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7546 of J or JR, respectively, followed by:
7552 We are at the beginning of the stub here, and scan down and extract
7553 the target address from the jump immediate instruction or, if a jump
7554 register instruction is used, from the register referred. Return
7555 the value of PC calculated or 0 if inconclusive.
7557 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7560 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7562 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7563 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7564 int addrreg
= MIPS_ZERO_REGNUM
;
7565 CORE_ADDR start_pc
= pc
;
7566 CORE_ADDR target_pc
= 0;
7573 status
== 0 && target_pc
== 0 && i
< 20;
7574 i
++, pc
+= MIPS_INSN32_SIZE
)
7576 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7582 switch (itype_op (inst
))
7584 case 0: /* SPECIAL */
7585 switch (rtype_funct (inst
))
7589 rs
= rtype_rs (inst
);
7590 if (rs
== MIPS_GP_REGNUM
)
7591 target_pc
= gp
; /* Hmm... */
7592 else if (rs
== addrreg
)
7596 case 0x21: /* ADDU */
7597 rt
= rtype_rt (inst
);
7598 rs
= rtype_rs (inst
);
7599 rd
= rtype_rd (inst
);
7600 if (rd
== MIPS_GP_REGNUM
7601 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7602 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7610 target_pc
= jtype_target (inst
) << 2;
7611 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7615 rt
= itype_rt (inst
);
7616 rs
= itype_rs (inst
);
7619 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7620 if (rt
== MIPS_GP_REGNUM
)
7622 else if (rt
== addrreg
)
7628 rt
= itype_rt (inst
);
7629 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7630 if (rt
== MIPS_GP_REGNUM
)
7632 else if (rt
!= MIPS_ZERO_REGNUM
)
7640 rt
= itype_rt (inst
);
7641 rs
= itype_rs (inst
);
7642 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7643 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7647 memset (buf
, 0, sizeof (buf
));
7648 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7650 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7659 /* If PC is in a MIPS16 call or return stub, return the address of the
7660 target PC, which is either the callee or the caller. There are several
7661 cases which must be handled:
7663 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7664 and the target PC is in $31 ($ra).
7665 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7666 and the target PC is in $2.
7667 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7668 i.e. before the JALR instruction, this is effectively a call stub
7669 and the target PC is in $2. Otherwise this is effectively
7670 a return stub and the target PC is in $18.
7671 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7672 JAL or JALR instruction, this is effectively a call stub and the
7673 target PC is buried in the instruction stream. Otherwise this
7674 is effectively a return stub and the target PC is in $18.
7675 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7676 stub and the target PC is buried in the instruction stream.
7678 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7679 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7683 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7685 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7686 CORE_ADDR start_addr
;
7690 /* Find the starting address and name of the function containing the PC. */
7691 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7694 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7695 and the target PC is in $31 ($ra). */
7696 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7697 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7698 && mips_is_stub_mode (name
+ prefixlen
)
7699 && name
[prefixlen
+ 2] == '\0')
7700 return get_frame_register_signed
7701 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7703 /* If the PC is in __mips16_call_stub_*, this is one of the call
7704 call/return stubs. */
7705 prefixlen
= strlen (mips_str_mips16_call_stub
);
7706 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7708 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7709 and the target PC is in $2. */
7710 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7711 return get_frame_register_signed
7712 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7714 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7715 i.e. before the JALR instruction, this is effectively a call stub
7716 and the target PC is in $2. Otherwise this is effectively
7717 a return stub and the target PC is in $18. */
7718 else if (mips_is_stub_mode (name
+ prefixlen
)
7719 && name
[prefixlen
+ 2] == '_'
7720 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7722 if (pc
== start_addr
)
7723 /* This is the 'call' part of a call stub. The return
7724 address is in $2. */
7725 return get_frame_register_signed
7726 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7728 /* This is the 'return' part of a call stub. The return
7729 address is in $18. */
7730 return get_frame_register_signed
7731 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7734 return 0; /* Not a stub. */
7737 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7738 compiler-generated call or call/return stubs. */
7739 if (startswith (name
, mips_str_fn_stub
)
7740 || startswith (name
, mips_str_call_stub
))
7742 if (pc
== start_addr
)
7743 /* This is the 'call' part of a call stub. Call this helper
7744 to scan through this code for interesting instructions
7745 and determine the final PC. */
7746 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7748 /* This is the 'return' part of a call stub. The return address
7750 return get_frame_register_signed
7751 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7754 return 0; /* Not a stub. */
7757 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7758 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7761 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7763 CORE_ADDR start_addr
;
7766 /* Find the starting address of the function containing the PC. */
7767 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7770 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7771 the start, i.e. after the JALR instruction, this is effectively
7773 prefixlen
= strlen (mips_str_mips16_call_stub
);
7774 if (pc
!= start_addr
7775 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7776 && mips_is_stub_mode (name
+ prefixlen
)
7777 && name
[prefixlen
+ 2] == '_'
7778 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7781 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7782 the JAL or JALR instruction, this is effectively a return stub. */
7783 prefixlen
= strlen (mips_str_call_fp_stub
);
7784 if (pc
!= start_addr
7785 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7788 /* Consume the .pic. prefix of any PIC stub, this function must return
7789 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7790 or the call stub path will trigger in handle_inferior_event causing
7792 prefixlen
= strlen (mips_str_pic
);
7793 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7796 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7797 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7798 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7799 && mips_is_stub_mode (name
+ prefixlen
)
7800 && name
[prefixlen
+ 2] == '\0')
7803 return 0; /* Not a stub. */
7806 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7807 PC of the stub target. The stub just loads $t9 and jumps to it,
7808 so that $t9 has the correct value at function entry. */
7811 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7813 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7814 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7815 struct bound_minimal_symbol msym
;
7817 gdb_byte stub_code
[16];
7818 int32_t stub_words
[4];
7820 /* The stub for foo is named ".pic.foo", and is either two
7821 instructions inserted before foo or a three instruction sequence
7822 which jumps to foo. */
7823 msym
= lookup_minimal_symbol_by_pc (pc
);
7824 if (msym
.minsym
== NULL
7825 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7826 || MSYMBOL_LINKAGE_NAME (msym
.minsym
) == NULL
7827 || !startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
7830 /* A two-instruction header. */
7831 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7834 /* A three-instruction (plus delay slot) trampoline. */
7835 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7837 if (target_read_memory (pc
, stub_code
, 16) != 0)
7839 for (i
= 0; i
< 4; i
++)
7840 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7843 /* A stub contains these instructions:
7846 addiu t9, t9, %lo(target)
7849 This works even for N64, since stubs are only generated with
7851 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7852 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7853 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7854 && stub_words
[3] == 0x00000000)
7855 return ((((stub_words
[0] & 0x0000ffff) << 16)
7856 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7859 /* Not a recognized stub. */
7864 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7866 CORE_ADDR requested_pc
= pc
;
7867 CORE_ADDR target_pc
;
7874 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7878 new_pc
= find_solib_trampoline_target (frame
, pc
);
7882 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7886 while (pc
!= target_pc
);
7888 return pc
!= requested_pc
? pc
: 0;
7891 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7892 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7895 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7898 if (num
>= 0 && num
< 32)
7900 else if (num
>= 38 && num
< 70)
7901 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7903 regnum
= mips_regnum (gdbarch
)->hi
;
7905 regnum
= mips_regnum (gdbarch
)->lo
;
7906 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7907 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7910 return gdbarch_num_regs (gdbarch
) + regnum
;
7914 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7915 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7918 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7921 if (num
>= 0 && num
< 32)
7923 else if (num
>= 32 && num
< 64)
7924 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7926 regnum
= mips_regnum (gdbarch
)->hi
;
7928 regnum
= mips_regnum (gdbarch
)->lo
;
7929 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7930 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7933 return gdbarch_num_regs (gdbarch
) + regnum
;
7937 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7939 /* Only makes sense to supply raw registers. */
7940 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7941 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7942 decide if it is valid. Should instead define a standard sim/gdb
7943 register numbering scheme. */
7944 if (gdbarch_register_name (gdbarch
,
7945 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7946 && gdbarch_register_name (gdbarch
,
7947 gdbarch_num_regs (gdbarch
)
7948 + regnum
)[0] != '\0')
7951 return LEGACY_SIM_REGNO_IGNORE
;
7955 /* Convert an integer into an address. Extracting the value signed
7956 guarantees a correctly sign extended address. */
7959 mips_integer_to_address (struct gdbarch
*gdbarch
,
7960 struct type
*type
, const gdb_byte
*buf
)
7962 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7963 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7966 /* Dummy virtual frame pointer method. This is no more or less accurate
7967 than most other architectures; we just need to be explicit about it,
7968 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7969 an assertion failure. */
7972 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7973 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7975 *reg
= MIPS_SP_REGNUM
;
7980 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7982 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7983 const char *name
= bfd_get_section_name (abfd
, sect
);
7985 if (*abip
!= MIPS_ABI_UNKNOWN
)
7988 if (!startswith (name
, ".mdebug."))
7991 if (strcmp (name
, ".mdebug.abi32") == 0)
7992 *abip
= MIPS_ABI_O32
;
7993 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7994 *abip
= MIPS_ABI_N32
;
7995 else if (strcmp (name
, ".mdebug.abi64") == 0)
7996 *abip
= MIPS_ABI_N64
;
7997 else if (strcmp (name
, ".mdebug.abiO64") == 0)
7998 *abip
= MIPS_ABI_O64
;
7999 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8000 *abip
= MIPS_ABI_EABI32
;
8001 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8002 *abip
= MIPS_ABI_EABI64
;
8004 warning (_("unsupported ABI %s."), name
+ 8);
8008 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8010 int *lbp
= (int *) obj
;
8011 const char *name
= bfd_get_section_name (abfd
, sect
);
8013 if (startswith (name
, ".gcc_compiled_long32"))
8015 else if (startswith (name
, ".gcc_compiled_long64"))
8017 else if (startswith (name
, ".gcc_compiled_long"))
8018 warning (_("unrecognized .gcc_compiled_longXX"));
8021 static enum mips_abi
8022 global_mips_abi (void)
8026 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8027 if (mips_abi_strings
[i
] == mips_abi_string
)
8028 return (enum mips_abi
) i
;
8030 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8033 /* Return the default compressed instruction set, either of MIPS16
8034 or microMIPS, selected when none could have been determined from
8035 the ELF header of the binary being executed (or no binary has been
8038 static enum mips_isa
8039 global_mips_compression (void)
8043 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8044 if (mips_compression_strings
[i
] == mips_compression_string
)
8045 return (enum mips_isa
) i
;
8047 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8051 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8053 /* If the size matches the set of 32-bit or 64-bit integer registers,
8054 assume that's what we've got. */
8055 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8056 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8058 /* If the size matches the full set of registers GDB traditionally
8059 knows about, including floating point, for either 32-bit or
8060 64-bit, assume that's what we've got. */
8061 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8062 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8064 /* Otherwise we don't have a useful guess. */
8067 static struct value
*
8068 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8070 const int *reg_p
= (const int *) baton
;
8071 return value_of_register (*reg_p
, frame
);
8074 static struct gdbarch
*
8075 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8077 struct gdbarch
*gdbarch
;
8078 struct gdbarch_tdep
*tdep
;
8080 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8082 enum mips_fpu_type fpu_type
;
8083 struct tdesc_arch_data
*tdesc_data
= NULL
;
8084 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8085 const char **reg_names
;
8086 struct mips_regnum mips_regnum
, *regnum
;
8087 enum mips_isa mips_isa
;
8091 /* Fill in the OS dependent register numbers and names. */
8092 if (info
.osabi
== GDB_OSABI_LINUX
)
8094 mips_regnum
.fp0
= 38;
8095 mips_regnum
.pc
= 37;
8096 mips_regnum
.cause
= 36;
8097 mips_regnum
.badvaddr
= 35;
8098 mips_regnum
.hi
= 34;
8099 mips_regnum
.lo
= 33;
8100 mips_regnum
.fp_control_status
= 70;
8101 mips_regnum
.fp_implementation_revision
= 71;
8102 mips_regnum
.dspacc
= -1;
8103 mips_regnum
.dspctl
= -1;
8107 reg_names
= mips_linux_reg_names
;
8111 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8112 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8113 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8114 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8115 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8116 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8117 mips_regnum
.fp_control_status
= 70;
8118 mips_regnum
.fp_implementation_revision
= 71;
8119 mips_regnum
.dspacc
= dspacc
= -1;
8120 mips_regnum
.dspctl
= dspctl
= -1;
8121 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8122 if (info
.bfd_arch_info
!= NULL
8123 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8124 reg_names
= mips_tx39_reg_names
;
8126 reg_names
= mips_generic_reg_names
;
8129 /* Check any target description for validity. */
8130 if (tdesc_has_registers (info
.target_desc
))
8132 static const char *const mips_gprs
[] = {
8133 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8134 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8135 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8136 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8138 static const char *const mips_fprs
[] = {
8139 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8140 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8141 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8142 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8145 const struct tdesc_feature
*feature
;
8148 feature
= tdesc_find_feature (info
.target_desc
,
8149 "org.gnu.gdb.mips.cpu");
8150 if (feature
== NULL
)
8153 tdesc_data
= tdesc_data_alloc ();
8156 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8157 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
8161 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8162 mips_regnum
.lo
, "lo");
8163 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8164 mips_regnum
.hi
, "hi");
8165 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8166 mips_regnum
.pc
, "pc");
8170 tdesc_data_cleanup (tdesc_data
);
8174 feature
= tdesc_find_feature (info
.target_desc
,
8175 "org.gnu.gdb.mips.cp0");
8176 if (feature
== NULL
)
8178 tdesc_data_cleanup (tdesc_data
);
8183 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8184 mips_regnum
.badvaddr
, "badvaddr");
8185 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8186 MIPS_PS_REGNUM
, "status");
8187 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8188 mips_regnum
.cause
, "cause");
8192 tdesc_data_cleanup (tdesc_data
);
8196 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8197 backend is not prepared for that, though. */
8198 feature
= tdesc_find_feature (info
.target_desc
,
8199 "org.gnu.gdb.mips.fpu");
8200 if (feature
== NULL
)
8202 tdesc_data_cleanup (tdesc_data
);
8207 for (i
= 0; i
< 32; i
++)
8208 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8209 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8211 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8212 mips_regnum
.fp_control_status
,
8215 &= tdesc_numbered_register (feature
, tdesc_data
,
8216 mips_regnum
.fp_implementation_revision
,
8221 tdesc_data_cleanup (tdesc_data
);
8225 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8229 feature
= tdesc_find_feature (info
.target_desc
,
8230 "org.gnu.gdb.mips.dsp");
8231 /* The DSP registers are optional; it's OK if they are absent. */
8232 if (feature
!= NULL
)
8236 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8237 dspacc
+ i
++, "hi1");
8238 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8239 dspacc
+ i
++, "lo1");
8240 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8241 dspacc
+ i
++, "hi2");
8242 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8243 dspacc
+ i
++, "lo2");
8244 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8245 dspacc
+ i
++, "hi3");
8246 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8247 dspacc
+ i
++, "lo3");
8249 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8254 tdesc_data_cleanup (tdesc_data
);
8258 mips_regnum
.dspacc
= dspacc
;
8259 mips_regnum
.dspctl
= dspctl
;
8261 num_regs
= mips_regnum
.dspctl
+ 1;
8265 /* It would be nice to detect an attempt to use a 64-bit ABI
8266 when only 32-bit registers are provided. */
8270 /* First of all, extract the elf_flags, if available. */
8271 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8272 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8273 else if (arches
!= NULL
)
8274 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8278 fprintf_unfiltered (gdb_stdlog
,
8279 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8281 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8282 switch ((elf_flags
& EF_MIPS_ABI
))
8284 case E_MIPS_ABI_O32
:
8285 found_abi
= MIPS_ABI_O32
;
8287 case E_MIPS_ABI_O64
:
8288 found_abi
= MIPS_ABI_O64
;
8290 case E_MIPS_ABI_EABI32
:
8291 found_abi
= MIPS_ABI_EABI32
;
8293 case E_MIPS_ABI_EABI64
:
8294 found_abi
= MIPS_ABI_EABI64
;
8297 if ((elf_flags
& EF_MIPS_ABI2
))
8298 found_abi
= MIPS_ABI_N32
;
8300 found_abi
= MIPS_ABI_UNKNOWN
;
8304 /* GCC creates a pseudo-section whose name describes the ABI. */
8305 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8306 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8308 /* If we have no useful BFD information, use the ABI from the last
8309 MIPS architecture (if there is one). */
8310 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8311 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8313 /* Try the architecture for any hint of the correct ABI. */
8314 if (found_abi
== MIPS_ABI_UNKNOWN
8315 && info
.bfd_arch_info
!= NULL
8316 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8318 switch (info
.bfd_arch_info
->mach
)
8320 case bfd_mach_mips3900
:
8321 found_abi
= MIPS_ABI_EABI32
;
8323 case bfd_mach_mips4100
:
8324 case bfd_mach_mips5000
:
8325 found_abi
= MIPS_ABI_EABI64
;
8327 case bfd_mach_mips8000
:
8328 case bfd_mach_mips10000
:
8329 /* On Irix, ELF64 executables use the N64 ABI. The
8330 pseudo-sections which describe the ABI aren't present
8331 on IRIX. (Even for executables created by gcc.) */
8332 if (info
.abfd
!= NULL
8333 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8334 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8335 found_abi
= MIPS_ABI_N64
;
8337 found_abi
= MIPS_ABI_N32
;
8342 /* Default 64-bit objects to N64 instead of O32. */
8343 if (found_abi
== MIPS_ABI_UNKNOWN
8344 && info
.abfd
!= NULL
8345 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8346 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8347 found_abi
= MIPS_ABI_N64
;
8350 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8353 /* What has the user specified from the command line? */
8354 wanted_abi
= global_mips_abi ();
8356 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8359 /* Now that we have found what the ABI for this binary would be,
8360 check whether the user is overriding it. */
8361 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8362 mips_abi
= wanted_abi
;
8363 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8364 mips_abi
= found_abi
;
8366 mips_abi
= MIPS_ABI_O32
;
8368 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8371 /* Determine the default compressed ISA. */
8372 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8373 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8374 mips_isa
= ISA_MICROMIPS
;
8375 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8376 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8377 mips_isa
= ISA_MIPS16
;
8379 mips_isa
= global_mips_compression ();
8380 mips_compression_string
= mips_compression_strings
[mips_isa
];
8382 /* Also used when doing an architecture lookup. */
8384 fprintf_unfiltered (gdb_stdlog
,
8385 "mips_gdbarch_init: "
8386 "mips64_transfers_32bit_regs_p = %d\n",
8387 mips64_transfers_32bit_regs_p
);
8389 /* Determine the MIPS FPU type. */
8392 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8393 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8394 Tag_GNU_MIPS_ABI_FP
);
8395 #endif /* HAVE_ELF */
8397 if (!mips_fpu_type_auto
)
8398 fpu_type
= mips_fpu_type
;
8399 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8401 switch (elf_fpu_type
)
8403 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8404 fpu_type
= MIPS_FPU_DOUBLE
;
8406 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8407 fpu_type
= MIPS_FPU_SINGLE
;
8409 case Val_GNU_MIPS_ABI_FP_SOFT
:
8411 /* Soft float or unknown. */
8412 fpu_type
= MIPS_FPU_NONE
;
8416 else if (info
.bfd_arch_info
!= NULL
8417 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8418 switch (info
.bfd_arch_info
->mach
)
8420 case bfd_mach_mips3900
:
8421 case bfd_mach_mips4100
:
8422 case bfd_mach_mips4111
:
8423 case bfd_mach_mips4120
:
8424 fpu_type
= MIPS_FPU_NONE
;
8426 case bfd_mach_mips4650
:
8427 fpu_type
= MIPS_FPU_SINGLE
;
8430 fpu_type
= MIPS_FPU_DOUBLE
;
8433 else if (arches
!= NULL
)
8434 fpu_type
= MIPS_FPU_TYPE (arches
->gdbarch
);
8436 fpu_type
= MIPS_FPU_DOUBLE
;
8438 fprintf_unfiltered (gdb_stdlog
,
8439 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8441 /* Check for blatant incompatibilities. */
8443 /* If we have only 32-bit registers, then we can't debug a 64-bit
8445 if (info
.target_desc
8446 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8447 && mips_abi
!= MIPS_ABI_EABI32
8448 && mips_abi
!= MIPS_ABI_O32
)
8450 if (tdesc_data
!= NULL
)
8451 tdesc_data_cleanup (tdesc_data
);
8455 /* Try to find a pre-existing architecture. */
8456 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8458 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8460 /* MIPS needs to be pedantic about which ABI and the compressed
8461 ISA variation the object is using. */
8462 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8464 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8466 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8468 /* Need to be pedantic about which register virtual size is
8470 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8471 != mips64_transfers_32bit_regs_p
)
8473 /* Be pedantic about which FPU is selected. */
8474 if (MIPS_FPU_TYPE (arches
->gdbarch
) != fpu_type
)
8477 if (tdesc_data
!= NULL
)
8478 tdesc_data_cleanup (tdesc_data
);
8479 return arches
->gdbarch
;
8482 /* Need a new architecture. Fill in a target specific vector. */
8483 tdep
= XCNEW (struct gdbarch_tdep
);
8484 gdbarch
= gdbarch_alloc (&info
, tdep
);
8485 tdep
->elf_flags
= elf_flags
;
8486 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8487 tdep
->found_abi
= found_abi
;
8488 tdep
->mips_abi
= mips_abi
;
8489 tdep
->mips_isa
= mips_isa
;
8490 tdep
->mips_fpu_type
= fpu_type
;
8491 tdep
->register_size_valid_p
= 0;
8492 tdep
->register_size
= 0;
8494 if (info
.target_desc
)
8496 /* Some useful properties can be inferred from the target. */
8497 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8499 tdep
->register_size_valid_p
= 1;
8500 tdep
->register_size
= 4;
8502 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8504 tdep
->register_size_valid_p
= 1;
8505 tdep
->register_size
= 8;
8509 /* Initially set everything according to the default ABI/ISA. */
8510 set_gdbarch_short_bit (gdbarch
, 16);
8511 set_gdbarch_int_bit (gdbarch
, 32);
8512 set_gdbarch_float_bit (gdbarch
, 32);
8513 set_gdbarch_double_bit (gdbarch
, 64);
8514 set_gdbarch_long_double_bit (gdbarch
, 64);
8515 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8516 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8517 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8519 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8520 mips_ax_pseudo_register_collect
);
8521 set_gdbarch_ax_pseudo_register_push_stack
8522 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8524 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8525 mips_elf_make_msymbol_special
);
8526 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8527 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8528 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8530 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8531 *regnum
= mips_regnum
;
8532 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8533 set_gdbarch_num_regs (gdbarch
, num_regs
);
8534 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8535 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8536 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8537 tdep
->mips_processor_reg_names
= reg_names
;
8538 tdep
->regnum
= regnum
;
8543 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8544 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8545 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8546 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8547 tdep
->default_mask_address_p
= 0;
8548 set_gdbarch_long_bit (gdbarch
, 32);
8549 set_gdbarch_ptr_bit (gdbarch
, 32);
8550 set_gdbarch_long_long_bit (gdbarch
, 64);
8553 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8554 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8555 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8556 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8557 tdep
->default_mask_address_p
= 0;
8558 set_gdbarch_long_bit (gdbarch
, 32);
8559 set_gdbarch_ptr_bit (gdbarch
, 32);
8560 set_gdbarch_long_long_bit (gdbarch
, 64);
8562 case MIPS_ABI_EABI32
:
8563 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8564 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8565 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8566 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8567 tdep
->default_mask_address_p
= 0;
8568 set_gdbarch_long_bit (gdbarch
, 32);
8569 set_gdbarch_ptr_bit (gdbarch
, 32);
8570 set_gdbarch_long_long_bit (gdbarch
, 64);
8572 case MIPS_ABI_EABI64
:
8573 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8574 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8575 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8576 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8577 tdep
->default_mask_address_p
= 0;
8578 set_gdbarch_long_bit (gdbarch
, 64);
8579 set_gdbarch_ptr_bit (gdbarch
, 64);
8580 set_gdbarch_long_long_bit (gdbarch
, 64);
8583 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8584 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8585 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8586 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8587 tdep
->default_mask_address_p
= 0;
8588 set_gdbarch_long_bit (gdbarch
, 32);
8589 set_gdbarch_ptr_bit (gdbarch
, 32);
8590 set_gdbarch_long_long_bit (gdbarch
, 64);
8591 set_gdbarch_long_double_bit (gdbarch
, 128);
8592 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8595 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8596 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8597 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8598 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8599 tdep
->default_mask_address_p
= 0;
8600 set_gdbarch_long_bit (gdbarch
, 64);
8601 set_gdbarch_ptr_bit (gdbarch
, 64);
8602 set_gdbarch_long_long_bit (gdbarch
, 64);
8603 set_gdbarch_long_double_bit (gdbarch
, 128);
8604 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8607 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8610 /* GCC creates a pseudo-section whose name specifies the size of
8611 longs, since -mlong32 or -mlong64 may be used independent of
8612 other options. How those options affect pointer sizes is ABI and
8613 architecture dependent, so use them to override the default sizes
8614 set by the ABI. This table shows the relationship between ABI,
8615 -mlongXX, and size of pointers:
8617 ABI -mlongXX ptr bits
8618 --- -------- --------
8632 Note that for o32 and eabi32, pointers are always 32 bits
8633 regardless of any -mlongXX option. For all others, pointers and
8634 longs are the same, as set by -mlongXX or set by defaults. */
8636 if (info
.abfd
!= NULL
)
8640 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8643 set_gdbarch_long_bit (gdbarch
, long_bit
);
8647 case MIPS_ABI_EABI32
:
8652 case MIPS_ABI_EABI64
:
8653 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8656 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8661 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8662 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8665 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8666 flag in object files because to do so would make it impossible to
8667 link with libraries compiled without "-gp32". This is
8668 unnecessarily restrictive.
8670 We could solve this problem by adding "-gp32" multilibs to gcc,
8671 but to set this flag before gcc is built with such multilibs will
8672 break too many systems.''
8674 But even more unhelpfully, the default linker output target for
8675 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8676 for 64-bit programs - you need to change the ABI to change this,
8677 and not all gcc targets support that currently. Therefore using
8678 this flag to detect 32-bit mode would do the wrong thing given
8679 the current gcc - it would make GDB treat these 64-bit programs
8680 as 32-bit programs by default. */
8682 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8683 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8685 /* Add/remove bits from an address. The MIPS needs be careful to
8686 ensure that all 32 bit addresses are sign extended to 64 bits. */
8687 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8689 /* Unwind the frame. */
8690 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8691 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8692 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8694 /* Map debug register numbers onto internal register numbers. */
8695 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8696 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8697 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8698 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8699 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8700 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8702 /* MIPS version of CALL_DUMMY. */
8704 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8705 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8706 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8708 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8710 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8711 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8712 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8714 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8715 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8716 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8717 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8718 mips_adjust_breakpoint_address
);
8720 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8722 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8724 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8725 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8726 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8728 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8730 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8732 if (mips_abi
== MIPS_ABI_N32
)
8733 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8734 else if (mips_abi
== MIPS_ABI_N64
)
8735 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8737 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8739 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8740 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8741 need to all be folded into the target vector. Since they are
8742 being used as guards for target_stopped_by_watchpoint, why not have
8743 target_stopped_by_watchpoint return the type of watchpoint that the code
8745 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8747 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8749 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8750 to support MIPS16. This is a bad thing. Make sure not to do it
8751 if we have an OS ABI that actually supports shared libraries, since
8752 shared library support is more important. If we have an OS someday
8753 that supports both shared libraries and MIPS16, we'll have to find
8754 a better place for these.
8755 macro/2012-04-25: But that applies to return trampolines only and
8756 currently no MIPS OS ABI uses shared libraries that have them. */
8757 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8759 set_gdbarch_single_step_through_delay (gdbarch
,
8760 mips_single_step_through_delay
);
8762 /* Virtual tables. */
8763 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8765 mips_register_g_packet_guesses (gdbarch
);
8767 /* Hook in OS ABI-specific overrides, if they have been registered. */
8768 info
.tdesc_data
= tdesc_data
;
8769 gdbarch_init_osabi (info
, gdbarch
);
8771 /* The hook may have adjusted num_regs, fetch the final value and
8772 set pc_regnum and sp_regnum now that it has been fixed. */
8773 num_regs
= gdbarch_num_regs (gdbarch
);
8774 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8775 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8777 /* Unwind the frame. */
8778 dwarf2_append_unwinders (gdbarch
);
8779 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8780 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8781 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8782 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8783 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8784 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8785 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8786 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8787 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8791 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8792 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8794 /* Override the normal target description methods to handle our
8795 dual real and pseudo registers. */
8796 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8797 set_gdbarch_register_reggroup_p (gdbarch
,
8798 mips_tdesc_register_reggroup_p
);
8800 num_regs
= gdbarch_num_regs (gdbarch
);
8801 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8802 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8803 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8806 /* Add ABI-specific aliases for the registers. */
8807 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8808 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8809 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8810 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8812 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8813 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8814 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8816 /* Add some other standard aliases. */
8817 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8818 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8819 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8821 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8822 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8823 value_of_mips_user_reg
,
8824 &mips_numeric_register_aliases
[i
].regnum
);
8830 mips_abi_update (const char *ignore_args
,
8831 int from_tty
, struct cmd_list_element
*c
)
8833 struct gdbarch_info info
;
8835 /* Force the architecture to update, and (if it's a MIPS architecture)
8836 mips_gdbarch_init will take care of the rest. */
8837 gdbarch_info_init (&info
);
8838 gdbarch_update_p (info
);
8841 /* Print out which MIPS ABI is in use. */
8844 show_mips_abi (struct ui_file
*file
,
8846 struct cmd_list_element
*ignored_cmd
,
8847 const char *ignored_value
)
8849 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8852 "The MIPS ABI is unknown because the current architecture "
8856 enum mips_abi global_abi
= global_mips_abi ();
8857 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8858 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8860 if (global_abi
== MIPS_ABI_UNKNOWN
)
8863 "The MIPS ABI is set automatically (currently \"%s\").\n",
8865 else if (global_abi
== actual_abi
)
8868 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8872 /* Probably shouldn't happen... */
8873 fprintf_filtered (file
,
8874 "The (auto detected) MIPS ABI \"%s\" is in use "
8875 "even though the user setting was \"%s\".\n",
8876 actual_abi_str
, mips_abi_strings
[global_abi
]);
8881 /* Print out which MIPS compressed ISA encoding is used. */
8884 show_mips_compression (struct ui_file
*file
, int from_tty
,
8885 struct cmd_list_element
*c
, const char *value
)
8887 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8891 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8894 mips_fpu_type_str (enum mips_fpu_type fpu_type
)
8900 case MIPS_FPU_SINGLE
:
8902 case MIPS_FPU_DOUBLE
:
8910 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8912 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8916 int ef_mips_32bitmode
;
8917 /* Determine the ISA. */
8918 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8936 /* Determine the size of a pointer. */
8937 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8938 fprintf_unfiltered (file
,
8939 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8941 fprintf_unfiltered (file
,
8942 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8944 fprintf_unfiltered (file
,
8945 "mips_dump_tdep: ef_mips_arch = %d\n",
8947 fprintf_unfiltered (file
,
8948 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8949 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8950 fprintf_unfiltered (file
,
8952 "mips_mask_address_p() %d (default %d)\n",
8953 mips_mask_address_p (tdep
),
8954 tdep
->default_mask_address_p
);
8956 fprintf_unfiltered (file
,
8957 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8958 MIPS_DEFAULT_FPU_TYPE
,
8959 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE
));
8960 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8961 MIPS_EABI (gdbarch
));
8962 fprintf_unfiltered (file
,
8963 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8964 MIPS_FPU_TYPE (gdbarch
),
8965 mips_fpu_type_str (MIPS_FPU_TYPE (gdbarch
)));
8969 _initialize_mips_tdep (void)
8971 static struct cmd_list_element
*mipsfpulist
= NULL
;
8972 struct cmd_list_element
*c
;
8974 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8975 if (MIPS_ABI_LAST
+ 1
8976 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8977 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8979 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8981 mips_pdr_data
= register_objfile_data ();
8983 /* Create feature sets with the appropriate properties. The values
8984 are not important. */
8985 mips_tdesc_gp32
= allocate_target_description ();
8986 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8988 mips_tdesc_gp64
= allocate_target_description ();
8989 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8991 /* Add root prefix command for all "set mips"/"show mips" commands. */
8992 add_prefix_cmd ("mips", no_class
, set_mips_command
,
8993 _("Various MIPS specific commands."),
8994 &setmipscmdlist
, "set mips ", 0, &setlist
);
8996 add_prefix_cmd ("mips", no_class
, show_mips_command
,
8997 _("Various MIPS specific commands."),
8998 &showmipscmdlist
, "show mips ", 0, &showlist
);
9000 /* Allow the user to override the ABI. */
9001 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9002 &mips_abi_string
, _("\
9003 Set the MIPS ABI used by this program."), _("\
9004 Show the MIPS ABI used by this program."), _("\
9005 This option can be set to one of:\n\
9006 auto - the default ABI associated with the current binary\n\
9015 &setmipscmdlist
, &showmipscmdlist
);
9017 /* Allow the user to set the ISA to assume for compressed code if ELF
9018 file flags don't tell or there is no program file selected. This
9019 setting is updated whenever unambiguous ELF file flags are interpreted,
9020 and carried over to subsequent sessions. */
9021 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9022 &mips_compression_string
, _("\
9023 Set the compressed ISA encoding used by MIPS code."), _("\
9024 Show the compressed ISA encoding used by MIPS code."), _("\
9025 Select the compressed ISA encoding used in functions that have no symbol\n\
9026 information available. The encoding can be set to either of:\n\
9029 and is updated automatically from ELF file flags if available."),
9031 show_mips_compression
,
9032 &setmipscmdlist
, &showmipscmdlist
);
9034 /* Let the user turn off floating point and set the fence post for
9035 heuristic_proc_start. */
9037 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
9038 _("Set use of MIPS floating-point coprocessor."),
9039 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
9040 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9041 _("Select single-precision MIPS floating-point coprocessor."),
9043 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9044 _("Select double-precision MIPS floating-point coprocessor."),
9046 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
9047 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
9048 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
9049 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9050 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9051 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
9052 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
9053 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
9054 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9055 _("Select MIPS floating-point coprocessor automatically."),
9057 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9058 _("Show current use of MIPS floating-point coprocessor target."),
9061 /* We really would like to have both "0" and "unlimited" work, but
9062 command.c doesn't deal with that. So make it a var_zinteger
9063 because the user can always use "999999" or some such for unlimited. */
9064 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9065 &heuristic_fence_post
, _("\
9066 Set the distance searched for the start of a function."), _("\
9067 Show the distance searched for the start of a function."), _("\
9068 If you are debugging a stripped executable, GDB needs to search through the\n\
9069 program for the start of a function. This command sets the distance of the\n\
9070 search. The only need to set it is when debugging a stripped executable."),
9071 reinit_frame_cache_sfunc
,
9072 NULL
, /* FIXME: i18n: The distance searched for
9073 the start of a function is %s. */
9074 &setlist
, &showlist
);
9076 /* Allow the user to control whether the upper bits of 64-bit
9077 addresses should be zeroed. */
9078 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9079 &mask_address_var
, _("\
9080 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9081 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9082 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9083 allow GDB to determine the correct value."),
9084 NULL
, show_mask_address
,
9085 &setmipscmdlist
, &showmipscmdlist
);
9087 /* Allow the user to control the size of 32 bit registers within the
9088 raw remote packet. */
9089 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9090 &mips64_transfers_32bit_regs_p
, _("\
9091 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9093 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9095 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9096 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9097 64 bits for others. Use \"off\" to disable compatibility mode"),
9098 set_mips64_transfers_32bit_regs
,
9099 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9100 MIPS target that transfers 32-bit
9101 quantities is %s. */
9102 &setlist
, &showlist
);
9104 /* Debug this files internals. */
9105 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9107 Set mips debugging."), _("\
9108 Show mips debugging."), _("\
9109 When non-zero, mips specific debugging is enabled."),
9111 NULL
, /* FIXME: i18n: Mips debugging is
9113 &setdebuglist
, &showdebuglist
);