1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
47 #include "frame-unwind.h"
48 #include "frame-base.h"
49 #include "trad-frame.h"
51 #include "floatformat.h"
53 #include "target-descriptions.h"
54 #include "dwarf2-frame.h"
55 #include "user-regs.h"
60 static const struct objfile_data
*mips_pdr_data
;
62 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
64 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
66 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
67 static int mips16_instruction_has_delay_slot (unsigned short inst
,
70 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
73 CORE_ADDR addr
, int mustbe32
);
74 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
75 CORE_ADDR addr
, int mustbe32
);
77 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
78 struct frame_info
*, const char *);
80 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
81 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
82 #define ST0_FR (1 << 26)
84 /* The sizes of floating point registers. */
88 MIPS_FPU_SINGLE_REGSIZE
= 4,
89 MIPS_FPU_DOUBLE_REGSIZE
= 8
98 static const char *mips_abi_string
;
100 static const char *const mips_abi_strings
[] = {
111 /* For backwards compatibility we default to MIPS16. This flag is
112 overridden as soon as unambiguous ELF file flags tell us the
113 compressed ISA encoding used. */
114 static const char mips_compression_mips16
[] = "mips16";
115 static const char mips_compression_micromips
[] = "micromips";
116 static const char *const mips_compression_strings
[] =
118 mips_compression_mips16
,
119 mips_compression_micromips
,
123 static const char *mips_compression_string
= mips_compression_mips16
;
125 /* The standard register names, and all the valid aliases for them. */
126 struct register_alias
132 /* Aliases for o32 and most other ABIs. */
133 const struct register_alias mips_o32_aliases
[] = {
140 /* Aliases for n32 and n64. */
141 const struct register_alias mips_n32_n64_aliases
[] = {
148 /* Aliases for ABI-independent registers. */
149 const struct register_alias mips_register_aliases
[] = {
150 /* The architecture manuals specify these ABI-independent names for
152 #define R(n) { "r" #n, n }
153 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
154 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
155 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
156 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
159 /* k0 and k1 are sometimes called these instead (for "kernel
164 /* This is the traditional GDB name for the CP0 status register. */
165 { "sr", MIPS_PS_REGNUM
},
167 /* This is the traditional GDB name for the CP0 BadVAddr register. */
168 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
170 /* This is the traditional GDB name for the FCSR. */
171 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
174 const struct register_alias mips_numeric_register_aliases
[] = {
175 #define R(n) { #n, n }
176 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
177 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
178 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
179 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
183 #ifndef MIPS_DEFAULT_FPU_TYPE
184 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
186 static int mips_fpu_type_auto
= 1;
187 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
189 static unsigned int mips_debug
= 0;
191 /* Properties (for struct target_desc) describing the g/G packet
193 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
194 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
196 struct target_desc
*mips_tdesc_gp32
;
197 struct target_desc
*mips_tdesc_gp64
;
199 const struct mips_regnum
*
200 mips_regnum (struct gdbarch
*gdbarch
)
202 return gdbarch_tdep (gdbarch
)->regnum
;
206 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
208 return mips_regnum (gdbarch
)->fp0
+ 12;
211 /* Return 1 if REGNUM refers to a floating-point general register, raw
212 or cooked. Otherwise return 0. */
215 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
217 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
219 return (rawnum
>= mips_regnum (gdbarch
)->fp0
220 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
223 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
225 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
227 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
228 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
230 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
231 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
233 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
235 /* Return the MIPS ABI associated with GDBARCH. */
237 mips_abi (struct gdbarch
*gdbarch
)
239 return gdbarch_tdep (gdbarch
)->mips_abi
;
243 mips_isa_regsize (struct gdbarch
*gdbarch
)
245 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
247 /* If we know how big the registers are, use that size. */
248 if (tdep
->register_size_valid_p
)
249 return tdep
->register_size
;
251 /* Fall back to the previous behavior. */
252 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
253 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
256 /* Return the currently configured (or set) saved register size. */
259 mips_abi_regsize (struct gdbarch
*gdbarch
)
261 switch (mips_abi (gdbarch
))
263 case MIPS_ABI_EABI32
:
269 case MIPS_ABI_EABI64
:
271 case MIPS_ABI_UNKNOWN
:
274 internal_error (__FILE__
, __LINE__
, _("bad switch"));
278 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
279 are some functions to handle addresses associated with compressed
280 code including but not limited to testing, setting, or clearing
281 bit 0 of such addresses. */
283 /* Return one iff compressed code is the MIPS16 instruction set. */
286 is_mips16_isa (struct gdbarch
*gdbarch
)
288 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
291 /* Return one iff compressed code is the microMIPS instruction set. */
294 is_micromips_isa (struct gdbarch
*gdbarch
)
296 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
299 /* Return one iff ADDR denotes compressed code. */
302 is_compact_addr (CORE_ADDR addr
)
307 /* Return one iff ADDR denotes standard ISA code. */
310 is_mips_addr (CORE_ADDR addr
)
312 return !is_compact_addr (addr
);
315 /* Return one iff ADDR denotes MIPS16 code. */
318 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
320 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
323 /* Return one iff ADDR denotes microMIPS code. */
326 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
328 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
331 /* Strip the ISA (compression) bit off from ADDR. */
334 unmake_compact_addr (CORE_ADDR addr
)
336 return ((addr
) & ~(CORE_ADDR
) 1);
339 /* Add the ISA (compression) bit to ADDR. */
342 make_compact_addr (CORE_ADDR addr
)
344 return ((addr
) | (CORE_ADDR
) 1);
347 /* Extern version of unmake_compact_addr; we use a separate function
348 so that unmake_compact_addr can be inlined throughout this file. */
351 mips_unmake_compact_addr (CORE_ADDR addr
)
353 return unmake_compact_addr (addr
);
356 /* Functions for setting and testing a bit in a minimal symbol that
357 marks it as MIPS16 or microMIPS function. The MSB of the minimal
358 symbol's "info" field is used for this purpose.
360 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
361 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
362 one of the "special" bits in a minimal symbol to mark it accordingly.
363 The test checks an ELF-private flag that is valid for true function
364 symbols only; for synthetic symbols such as for PLT stubs that have
365 no ELF-private part at all the MIPS BFD backend arranges for this
366 information to be carried in the asymbol's udata field instead.
368 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
369 in a minimal symbol. */
372 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
374 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
375 unsigned char st_other
;
377 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
378 st_other
= elfsym
->internal_elf_sym
.st_other
;
379 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
380 st_other
= sym
->udata
.i
;
384 if (ELF_ST_IS_MICROMIPS (st_other
))
386 MSYMBOL_TARGET_FLAG_MICROMIPS (msym
) = 1;
387 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
389 else if (ELF_ST_IS_MIPS16 (st_other
))
391 MSYMBOL_TARGET_FLAG_MIPS16 (msym
) = 1;
392 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
396 /* Return one iff MSYM refers to standard ISA code. */
399 msymbol_is_mips (struct minimal_symbol
*msym
)
401 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
402 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
405 /* Return one iff MSYM refers to MIPS16 code. */
408 msymbol_is_mips16 (struct minimal_symbol
*msym
)
410 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
413 /* Return one iff MSYM refers to microMIPS code. */
416 msymbol_is_micromips (struct minimal_symbol
*msym
)
418 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
421 /* Set the ISA bit in the main symbol too, complementing the corresponding
422 minimal symbol setting and reflecting the run-time value of the symbol.
423 The need for comes from the ISA bit having been cleared as code in
424 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
425 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
426 of symbols referring to compressed code different in GDB to the values
427 used by actual code. That in turn makes them evaluate incorrectly in
428 expressions, producing results different to what the same expressions
429 yield when compiled into the program being debugged. */
432 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
434 if (SYMBOL_CLASS (sym
) == LOC_BLOCK
)
436 /* We are in symbol reading so it is OK to cast away constness. */
437 struct block
*block
= (struct block
*) SYMBOL_BLOCK_VALUE (sym
);
438 CORE_ADDR compact_block_start
;
439 struct bound_minimal_symbol msym
;
441 compact_block_start
= BLOCK_START (block
) | 1;
442 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
443 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
445 BLOCK_START (block
) = compact_block_start
;
450 /* XFER a value from the big/little/left end of the register.
451 Depending on the size of the value it might occupy the entire
452 register or just part of it. Make an allowance for this, aligning
453 things accordingly. */
456 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
457 int reg_num
, int length
,
458 enum bfd_endian endian
, gdb_byte
*in
,
459 const gdb_byte
*out
, int buf_offset
)
463 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
464 /* Need to transfer the left or right part of the register, based on
465 the targets byte order. */
469 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
471 case BFD_ENDIAN_LITTLE
:
474 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
478 internal_error (__FILE__
, __LINE__
, _("bad switch"));
481 fprintf_unfiltered (gdb_stderr
,
482 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
483 reg_num
, reg_offset
, buf_offset
, length
);
484 if (mips_debug
&& out
!= NULL
)
487 fprintf_unfiltered (gdb_stdlog
, "out ");
488 for (i
= 0; i
< length
; i
++)
489 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
492 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
495 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
497 if (mips_debug
&& in
!= NULL
)
500 fprintf_unfiltered (gdb_stdlog
, "in ");
501 for (i
= 0; i
< length
; i
++)
502 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
505 fprintf_unfiltered (gdb_stdlog
, "\n");
508 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
509 compatiblity mode. A return value of 1 means that we have
510 physical 64-bit registers, but should treat them as 32-bit registers. */
513 mips2_fp_compat (struct frame_info
*frame
)
515 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
516 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
518 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
522 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
523 in all the places we deal with FP registers. PR gdb/413. */
524 /* Otherwise check the FR bit in the status register - it controls
525 the FP compatiblity mode. If it is clear we are in compatibility
527 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
534 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
536 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
538 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
540 /* The list of available "set mips " and "show mips " commands. */
542 static struct cmd_list_element
*setmipscmdlist
= NULL
;
543 static struct cmd_list_element
*showmipscmdlist
= NULL
;
545 /* Integer registers 0 thru 31 are handled explicitly by
546 mips_register_name(). Processor specific registers 32 and above
547 are listed in the following tables. */
550 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
554 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
555 "sr", "lo", "hi", "bad", "cause", "pc",
556 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
557 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
558 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
559 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
563 /* Names of IDT R3041 registers. */
565 static const char *mips_r3041_reg_names
[] = {
566 "sr", "lo", "hi", "bad", "cause", "pc",
567 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
568 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
569 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
570 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
571 "fsr", "fir", "", /*"fp" */ "",
572 "", "", "bus", "ccfg", "", "", "", "",
573 "", "", "port", "cmp", "", "", "epc", "prid",
576 /* Names of tx39 registers. */
578 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
579 "sr", "lo", "hi", "bad", "cause", "pc",
580 "", "", "", "", "", "", "", "",
581 "", "", "", "", "", "", "", "",
582 "", "", "", "", "", "", "", "",
583 "", "", "", "", "", "", "", "",
585 "", "", "", "", "", "", "", "",
586 "", "", "config", "cache", "debug", "depc", "epc",
589 /* Names of IRIX registers. */
590 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
591 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
592 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
593 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
594 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
595 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
598 /* Names of registers with Linux kernels. */
599 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
600 "sr", "lo", "hi", "bad", "cause", "pc",
601 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
602 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
603 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
604 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
609 /* Return the name of the register corresponding to REGNO. */
611 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
613 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
614 /* GPR names for all ABIs other than n32/n64. */
615 static char *mips_gpr_names
[] = {
616 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
617 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
618 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
619 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
622 /* GPR names for n32 and n64 ABIs. */
623 static char *mips_n32_n64_gpr_names
[] = {
624 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
625 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
626 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
627 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
630 enum mips_abi abi
= mips_abi (gdbarch
);
632 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
633 but then don't make the raw register names visible. This (upper)
634 range of user visible register numbers are the pseudo-registers.
636 This approach was adopted accommodate the following scenario:
637 It is possible to debug a 64-bit device using a 32-bit
638 programming model. In such instances, the raw registers are
639 configured to be 64-bits wide, while the pseudo registers are
640 configured to be 32-bits wide. The registers that the user
641 sees - the pseudo registers - match the users expectations
642 given the programming model being used. */
643 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
644 if (regno
< gdbarch_num_regs (gdbarch
))
647 /* The MIPS integer registers are always mapped from 0 to 31. The
648 names of the registers (which reflects the conventions regarding
649 register use) vary depending on the ABI. */
650 if (0 <= rawnum
&& rawnum
< 32)
652 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
653 return mips_n32_n64_gpr_names
[rawnum
];
655 return mips_gpr_names
[rawnum
];
657 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
658 return tdesc_register_name (gdbarch
, rawnum
);
659 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
661 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
662 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
663 return tdep
->mips_processor_reg_names
[rawnum
- 32];
667 internal_error (__FILE__
, __LINE__
,
668 _("mips_register_name: bad register number %d"), rawnum
);
671 /* Return the groups that a MIPS register can be categorised into. */
674 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
675 struct reggroup
*reggroup
)
680 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
681 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
682 if (reggroup
== all_reggroup
)
684 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
685 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
686 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
687 (gdbarch), as not all architectures are multi-arch. */
688 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
689 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
690 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
692 if (reggroup
== float_reggroup
)
693 return float_p
&& pseudo
;
694 if (reggroup
== vector_reggroup
)
695 return vector_p
&& pseudo
;
696 if (reggroup
== general_reggroup
)
697 return (!vector_p
&& !float_p
) && pseudo
;
698 /* Save the pseudo registers. Need to make certain that any code
699 extracting register values from a saved register cache also uses
701 if (reggroup
== save_reggroup
)
702 return raw_p
&& pseudo
;
703 /* Restore the same pseudo register. */
704 if (reggroup
== restore_reggroup
)
705 return raw_p
&& pseudo
;
709 /* Return the groups that a MIPS register can be categorised into.
710 This version is only used if we have a target description which
711 describes real registers (and their groups). */
714 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
715 struct reggroup
*reggroup
)
717 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
718 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
721 /* Only save, restore, and display the pseudo registers. Need to
722 make certain that any code extracting register values from a
723 saved register cache also uses pseudo registers.
725 Note: saving and restoring the pseudo registers is slightly
726 strange; if we have 64 bits, we should save and restore all
727 64 bits. But this is hard and has little benefit. */
731 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
735 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
738 /* Map the symbol table registers which live in the range [1 *
739 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
740 registers. Take care of alignment and size problems. */
742 static enum register_status
743 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
744 int cookednum
, gdb_byte
*buf
)
746 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
747 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
748 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
749 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
750 return regcache_raw_read (regcache
, rawnum
, buf
);
751 else if (register_size (gdbarch
, rawnum
) >
752 register_size (gdbarch
, cookednum
))
754 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
755 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
758 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
760 enum register_status status
;
762 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
763 if (status
== REG_VALID
)
764 store_signed_integer (buf
, 4, byte_order
, regval
);
769 internal_error (__FILE__
, __LINE__
, _("bad register size"));
773 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
774 struct regcache
*regcache
, int cookednum
,
777 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
778 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
779 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
780 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
781 regcache_raw_write (regcache
, rawnum
, buf
);
782 else if (register_size (gdbarch
, rawnum
) >
783 register_size (gdbarch
, cookednum
))
785 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
786 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
789 /* Sign extend the shortened version of the register prior
790 to placing it in the raw register. This is required for
791 some mips64 parts in order to avoid unpredictable behavior. */
792 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
793 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
794 regcache_raw_write_signed (regcache
, rawnum
, regval
);
798 internal_error (__FILE__
, __LINE__
, _("bad register size"));
802 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
803 struct agent_expr
*ax
, int reg
)
805 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
806 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
807 && reg
< 2 * gdbarch_num_regs (gdbarch
));
809 ax_reg_mask (ax
, rawnum
);
815 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
816 struct agent_expr
*ax
, int reg
)
818 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
819 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
820 && reg
< 2 * gdbarch_num_regs (gdbarch
));
821 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
825 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
827 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
828 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
831 ax_simple (ax
, aop_lsh
);
834 ax_simple (ax
, aop_rsh_signed
);
838 internal_error (__FILE__
, __LINE__
, _("bad register size"));
843 /* Table to translate 3-bit register field to actual register number. */
844 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
846 /* Heuristic_proc_start may hunt through the text section for a long
847 time across a 2400 baud serial line. Allows the user to limit this
850 static int heuristic_fence_post
= 0;
852 /* Number of bytes of storage in the actual machine representation for
853 register N. NOTE: This defines the pseudo register type so need to
854 rebuild the architecture vector. */
856 static int mips64_transfers_32bit_regs_p
= 0;
859 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
860 struct cmd_list_element
*c
)
862 struct gdbarch_info info
;
863 gdbarch_info_init (&info
);
864 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
865 instead of relying on globals. Doing that would let generic code
866 handle the search for this specific architecture. */
867 if (!gdbarch_update_p (info
))
869 mips64_transfers_32bit_regs_p
= 0;
870 error (_("32-bit compatibility mode not supported"));
874 /* Convert to/from a register and the corresponding memory value. */
876 /* This predicate tests for the case of an 8 byte floating point
877 value that is being transferred to or from a pair of floating point
878 registers each of which are (or are considered to be) only 4 bytes
881 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
884 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
885 && register_size (gdbarch
, regnum
) == 4
886 && mips_float_register_p (gdbarch
, regnum
)
887 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
890 /* This predicate tests for the case of a value of less than 8
891 bytes in width that is being transfered to or from an 8 byte
892 general purpose register. */
894 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
897 int num_regs
= gdbarch_num_regs (gdbarch
);
899 return (register_size (gdbarch
, regnum
) == 8
900 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
901 && TYPE_LENGTH (type
) < 8);
905 mips_convert_register_p (struct gdbarch
*gdbarch
,
906 int regnum
, struct type
*type
)
908 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
909 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
913 mips_register_to_value (struct frame_info
*frame
, int regnum
,
914 struct type
*type
, gdb_byte
*to
,
915 int *optimizedp
, int *unavailablep
)
917 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
919 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
921 get_frame_register (frame
, regnum
+ 0, to
+ 4);
922 get_frame_register (frame
, regnum
+ 1, to
+ 0);
924 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
925 optimizedp
, unavailablep
))
928 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
929 optimizedp
, unavailablep
))
931 *optimizedp
= *unavailablep
= 0;
934 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
936 int len
= TYPE_LENGTH (type
);
939 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
940 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
941 optimizedp
, unavailablep
))
944 *optimizedp
= *unavailablep
= 0;
949 internal_error (__FILE__
, __LINE__
,
950 _("mips_register_to_value: unrecognized case"));
955 mips_value_to_register (struct frame_info
*frame
, int regnum
,
956 struct type
*type
, const gdb_byte
*from
)
958 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
960 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
962 put_frame_register (frame
, regnum
+ 0, from
+ 4);
963 put_frame_register (frame
, regnum
+ 1, from
+ 0);
965 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
968 int len
= TYPE_LENGTH (type
);
970 /* Sign extend values, irrespective of type, that are stored to
971 a 64-bit general purpose register. (32-bit unsigned values
972 are stored as signed quantities within a 64-bit register.
973 When performing an operation, in compiled code, that combines
974 a 32-bit unsigned value with a signed 64-bit value, a type
975 conversion is first performed that zeroes out the high 32 bits.) */
976 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
979 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
981 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
982 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
983 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
987 if (from
[len
-1] & 0x80)
988 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
990 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
991 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
992 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
997 internal_error (__FILE__
, __LINE__
,
998 _("mips_value_to_register: unrecognized case"));
1002 /* Return the GDB type object for the "standard" data type of data in
1005 static struct type
*
1006 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1008 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1009 if (mips_float_register_p (gdbarch
, regnum
))
1011 /* The floating-point registers raw, or cooked, always match
1012 mips_isa_regsize(), and also map 1:1, byte for byte. */
1013 if (mips_isa_regsize (gdbarch
) == 4)
1014 return builtin_type (gdbarch
)->builtin_float
;
1016 return builtin_type (gdbarch
)->builtin_double
;
1018 else if (regnum
< gdbarch_num_regs (gdbarch
))
1020 /* The raw or ISA registers. These are all sized according to
1022 if (mips_isa_regsize (gdbarch
) == 4)
1023 return builtin_type (gdbarch
)->builtin_int32
;
1025 return builtin_type (gdbarch
)->builtin_int64
;
1029 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1031 /* The cooked or ABI registers. These are sized according to
1032 the ABI (with a few complications). */
1033 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1034 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1035 return builtin_type (gdbarch
)->builtin_int32
;
1036 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
1037 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1038 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1039 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1040 /* The pseudo/cooked view of the embedded registers is always
1041 32-bit. The raw view is handled below. */
1042 return builtin_type (gdbarch
)->builtin_int32
;
1043 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
1044 /* The target, while possibly using a 64-bit register buffer,
1045 is only transfering 32-bits of each integer register.
1046 Reflect this in the cooked/pseudo (ABI) register value. */
1047 return builtin_type (gdbarch
)->builtin_int32
;
1048 else if (mips_abi_regsize (gdbarch
) == 4)
1049 /* The ABI is restricted to 32-bit registers (the ISA could be
1051 return builtin_type (gdbarch
)->builtin_int32
;
1054 return builtin_type (gdbarch
)->builtin_int64
;
1058 /* Return the GDB type for the pseudo register REGNUM, which is the
1059 ABI-level view. This function is only called if there is a target
1060 description which includes registers, so we know precisely the
1061 types of hardware registers. */
1063 static struct type
*
1064 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1066 const int num_regs
= gdbarch_num_regs (gdbarch
);
1067 int rawnum
= regnum
% num_regs
;
1068 struct type
*rawtype
;
1070 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1072 /* Absent registers are still absent. */
1073 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1074 if (TYPE_LENGTH (rawtype
) == 0)
1077 if (mips_float_register_p (gdbarch
, rawnum
))
1078 /* Present the floating point registers however the hardware did;
1079 do not try to convert between FPU layouts. */
1082 /* Use pointer types for registers if we can. For n32 we can not,
1083 since we do not have a 64-bit pointer type. */
1084 if (mips_abi_regsize (gdbarch
)
1085 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1087 if (rawnum
== MIPS_SP_REGNUM
1088 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1089 return builtin_type (gdbarch
)->builtin_data_ptr
;
1090 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1091 return builtin_type (gdbarch
)->builtin_func_ptr
;
1094 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1095 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1096 || rawnum
== mips_regnum (gdbarch
)->lo
1097 || rawnum
== mips_regnum (gdbarch
)->hi
1098 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1099 || rawnum
== mips_regnum (gdbarch
)->cause
1100 || rawnum
== mips_regnum (gdbarch
)->pc
1101 || (mips_regnum (gdbarch
)->dspacc
!= -1
1102 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1103 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1104 return builtin_type (gdbarch
)->builtin_int32
;
1106 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
1107 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1108 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
1109 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1111 /* The pseudo/cooked view of embedded registers is always
1112 32-bit, even if the target transfers 64-bit values for them.
1113 New targets relying on XML descriptions should only transfer
1114 the necessary 32 bits, but older versions of GDB expected 64,
1115 so allow the target to provide 64 bits without interfering
1116 with the displayed type. */
1117 return builtin_type (gdbarch
)->builtin_int32
;
1120 /* For all other registers, pass through the hardware type. */
1124 /* Should the upper word of 64-bit addresses be zeroed? */
1125 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1128 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1130 switch (mask_address_var
)
1132 case AUTO_BOOLEAN_TRUE
:
1134 case AUTO_BOOLEAN_FALSE
:
1137 case AUTO_BOOLEAN_AUTO
:
1138 return tdep
->default_mask_address_p
;
1140 internal_error (__FILE__
, __LINE__
,
1141 _("mips_mask_address_p: bad switch"));
1147 show_mask_address (struct ui_file
*file
, int from_tty
,
1148 struct cmd_list_element
*c
, const char *value
)
1150 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1152 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1153 switch (mask_address_var
)
1155 case AUTO_BOOLEAN_TRUE
:
1156 printf_filtered ("The 32 bit mips address mask is enabled\n");
1158 case AUTO_BOOLEAN_FALSE
:
1159 printf_filtered ("The 32 bit mips address mask is disabled\n");
1161 case AUTO_BOOLEAN_AUTO
:
1163 ("The 32 bit address mask is set automatically. Currently %s\n",
1164 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1167 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1172 /* Tell if the program counter value in MEMADDR is in a standard ISA
1176 mips_pc_is_mips (CORE_ADDR memaddr
)
1178 struct bound_minimal_symbol sym
;
1180 /* Flags indicating that this is a MIPS16 or microMIPS function is
1181 stored by elfread.c in the high bit of the info field. Use this
1182 to decide if the function is standard MIPS. Otherwise if bit 0
1183 of the address is clear, then this is a standard MIPS function. */
1184 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1186 return msymbol_is_mips (sym
.minsym
);
1188 return is_mips_addr (memaddr
);
1191 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1194 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1196 struct bound_minimal_symbol sym
;
1198 /* A flag indicating that this is a MIPS16 function is stored by
1199 elfread.c in the high bit of the info field. Use this to decide
1200 if the function is MIPS16. Otherwise if bit 0 of the address is
1201 set, then ELF file flags will tell if this is a MIPS16 function. */
1202 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1204 return msymbol_is_mips16 (sym
.minsym
);
1206 return is_mips16_addr (gdbarch
, memaddr
);
1209 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1212 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1214 struct bound_minimal_symbol sym
;
1216 /* A flag indicating that this is a microMIPS function is stored by
1217 elfread.c in the high bit of the info field. Use this to decide
1218 if the function is microMIPS. Otherwise if bit 0 of the address
1219 is set, then ELF file flags will tell if this is a microMIPS
1221 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1223 return msymbol_is_micromips (sym
.minsym
);
1225 return is_micromips_addr (gdbarch
, memaddr
);
1228 /* Tell the ISA type of the function the program counter value in MEMADDR
1231 static enum mips_isa
1232 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1234 struct bound_minimal_symbol sym
;
1236 /* A flag indicating that this is a MIPS16 or a microMIPS function
1237 is stored by elfread.c in the high bit of the info field. Use
1238 this to decide if the function is MIPS16 or microMIPS or normal
1239 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1240 flags will tell if this is a MIPS16 or a microMIPS function. */
1241 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1244 if (msymbol_is_micromips (sym
.minsym
))
1245 return ISA_MICROMIPS
;
1246 else if (msymbol_is_mips16 (sym
.minsym
))
1253 if (is_mips_addr (memaddr
))
1255 else if (is_micromips_addr (gdbarch
, memaddr
))
1256 return ISA_MICROMIPS
;
1262 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1263 The need for comes from the ISA bit having been cleared, making
1264 addresses in FDE, range records, etc. referring to compressed code
1265 different to those in line information, the symbol table and finally
1266 the PC register. That in turn confuses many operations. */
1269 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1271 pc
= unmake_compact_addr (pc
);
1272 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1275 /* Recalculate the line record requested so that the resulting PC has
1276 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1277 this adjustment comes from some records associated with compressed
1278 code having the ISA bit cleared, most notably at function prologue
1279 ends. The ISA bit is in this context retrieved from the minimal
1280 symbol covering the address requested, which in turn has been
1281 constructed from the binary's symbol table rather than DWARF-2
1282 information. The correct setting of the ISA bit is required for
1283 breakpoint addresses to correctly match against the stop PC.
1285 As line entries can specify relative address adjustments we need to
1286 keep track of the absolute value of the last line address recorded
1287 in line information, so that we can calculate the actual address to
1288 apply the ISA bit adjustment to. We use PC for this tracking and
1289 keep the original address there.
1291 As such relative address adjustments can be odd within compressed
1292 code we need to keep track of the last line address with the ISA
1293 bit adjustment applied too, as the original address may or may not
1294 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1295 the adjusted address there.
1297 For relative address adjustments we then use these variables to
1298 calculate the address intended by line information, which will be
1299 PC-relative, and return an updated adjustment carrying ISA bit
1300 information, which will be ADJ_PC-relative. For absolute address
1301 adjustments we just return the same address that we store in ADJ_PC
1304 As the first line entry can be relative to an implied address value
1305 of 0 we need to have the initial address set up that we store in PC
1306 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1307 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1310 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1312 static CORE_ADDR adj_pc
;
1313 static CORE_ADDR pc
;
1316 pc
= rel
? pc
+ addr
: addr
;
1317 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1318 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1323 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1325 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1326 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1327 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1328 static const char mips_str_call_stub
[] = "__call_stub_";
1329 static const char mips_str_fn_stub
[] = "__fn_stub_";
1331 /* This is used as a PIC thunk prefix. */
1333 static const char mips_str_pic
[] = ".pic.";
1335 /* Return non-zero if the PC is inside a call thunk (aka stub or
1336 trampoline) that should be treated as a temporary frame. */
1339 mips_in_frame_stub (CORE_ADDR pc
)
1341 CORE_ADDR start_addr
;
1344 /* Find the starting address of the function containing the PC. */
1345 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1348 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1349 if (startswith (name
, mips_str_mips16_call_stub
))
1351 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1352 if (startswith (name
, mips_str_call_stub
))
1354 /* If the PC is in __fn_stub_*, this is a call stub. */
1355 if (startswith (name
, mips_str_fn_stub
))
1358 return 0; /* Not a stub. */
1361 /* MIPS believes that the PC has a sign extended value. Perhaps the
1362 all registers should be sign extended for simplicity? */
1365 mips_read_pc (struct regcache
*regcache
)
1367 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1370 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1375 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1379 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1380 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1381 intermediate frames. In this case we can get the caller's address
1382 from $ra, or if $ra contains an address within a thunk as well, then
1383 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1384 and thus the caller's address is in $s2. */
1385 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1387 pc
= frame_unwind_register_signed
1388 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1389 if (mips_in_frame_stub (pc
))
1390 pc
= frame_unwind_register_signed
1391 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1397 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1399 return frame_unwind_register_signed
1400 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1403 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1404 dummy frame. The frame ID's base needs to match the TOS value
1405 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1408 static struct frame_id
1409 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1411 return frame_id_build
1412 (get_frame_register_signed (this_frame
,
1413 gdbarch_num_regs (gdbarch
)
1415 get_frame_pc (this_frame
));
1418 /* Implement the "write_pc" gdbarch method. */
1421 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1423 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1425 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1428 /* Fetch and return instruction from the specified location. Handle
1429 MIPS16/microMIPS as appropriate. */
1432 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1433 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1435 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1436 gdb_byte buf
[MIPS_INSN32_SIZE
];
1444 instlen
= MIPS_INSN16_SIZE
;
1445 addr
= unmake_compact_addr (addr
);
1448 instlen
= MIPS_INSN32_SIZE
;
1451 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1454 err
= target_read_memory (addr
, buf
, instlen
);
1460 memory_error (TARGET_XFER_E_IO
, addr
);
1463 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1466 /* These are the fields of 32 bit mips instructions. */
1467 #define mips32_op(x) (x >> 26)
1468 #define itype_op(x) (x >> 26)
1469 #define itype_rs(x) ((x >> 21) & 0x1f)
1470 #define itype_rt(x) ((x >> 16) & 0x1f)
1471 #define itype_immediate(x) (x & 0xffff)
1473 #define jtype_op(x) (x >> 26)
1474 #define jtype_target(x) (x & 0x03ffffff)
1476 #define rtype_op(x) (x >> 26)
1477 #define rtype_rs(x) ((x >> 21) & 0x1f)
1478 #define rtype_rt(x) ((x >> 16) & 0x1f)
1479 #define rtype_rd(x) ((x >> 11) & 0x1f)
1480 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1481 #define rtype_funct(x) (x & 0x3f)
1483 /* MicroMIPS instruction fields. */
1484 #define micromips_op(x) ((x) >> 10)
1486 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1487 bit and the size respectively of the field extracted. */
1488 #define b0s4_imm(x) ((x) & 0xf)
1489 #define b0s5_imm(x) ((x) & 0x1f)
1490 #define b0s5_reg(x) ((x) & 0x1f)
1491 #define b0s7_imm(x) ((x) & 0x7f)
1492 #define b0s10_imm(x) ((x) & 0x3ff)
1493 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1494 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1495 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1496 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1497 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1498 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1499 #define b6s4_op(x) (((x) >> 6) & 0xf)
1500 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1502 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1503 respectively of the field extracted. */
1504 #define b0s6_op(x) ((x) & 0x3f)
1505 #define b0s11_op(x) ((x) & 0x7ff)
1506 #define b0s12_imm(x) ((x) & 0xfff)
1507 #define b0s16_imm(x) ((x) & 0xffff)
1508 #define b0s26_imm(x) ((x) & 0x3ffffff)
1509 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1510 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1511 #define b12s4_op(x) (((x) >> 12) & 0xf)
1513 /* Return the size in bytes of the instruction INSN encoded in the ISA
1517 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1522 if ((micromips_op (insn
) & 0x4) == 0x4
1523 || (micromips_op (insn
) & 0x7) == 0x0)
1524 return 2 * MIPS_INSN16_SIZE
;
1526 return MIPS_INSN16_SIZE
;
1528 if ((insn
& 0xf800) == 0xf000)
1529 return 2 * MIPS_INSN16_SIZE
;
1531 return MIPS_INSN16_SIZE
;
1533 return MIPS_INSN32_SIZE
;
1535 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1539 mips32_relative_offset (ULONGEST inst
)
1541 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1544 /* Determine the address of the next instruction executed after the INST
1545 floating condition branch instruction at PC. COUNT specifies the
1546 number of the floating condition bits tested by the branch. */
1549 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1550 ULONGEST inst
, CORE_ADDR pc
, int count
)
1552 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1553 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1554 int tf
= itype_rt (inst
) & 1;
1555 int mask
= (1 << count
) - 1;
1560 /* No way to handle; it'll most likely trap anyway. */
1563 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1564 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1566 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1567 pc
+= mips32_relative_offset (inst
);
1574 /* Return nonzero if the gdbarch is an Octeon series. */
1577 is_octeon (struct gdbarch
*gdbarch
)
1579 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1581 return (info
->mach
== bfd_mach_mips_octeon
1582 || info
->mach
== bfd_mach_mips_octeonp
1583 || info
->mach
== bfd_mach_mips_octeon2
);
1586 /* Return true if the OP represents the Octeon's BBIT instruction. */
1589 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1591 if (!is_octeon (gdbarch
))
1593 /* BBIT0 is encoded as LWC2: 110 010. */
1594 /* BBIT032 is encoded as LDC2: 110 110. */
1595 /* BBIT1 is encoded as SWC2: 111 010. */
1596 /* BBIT132 is encoded as SDC2: 111 110. */
1597 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1603 /* Determine where to set a single step breakpoint while considering
1604 branch prediction. */
1607 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1609 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1612 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1613 op
= itype_op (inst
);
1614 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1618 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1629 goto greater_branch
;
1634 else if (op
== 17 && itype_rs (inst
) == 8)
1635 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1636 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1637 else if (op
== 17 && itype_rs (inst
) == 9
1638 && (itype_rt (inst
) & 2) == 0)
1639 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1640 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1641 else if (op
== 17 && itype_rs (inst
) == 10
1642 && (itype_rt (inst
) & 2) == 0)
1643 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1644 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1647 /* The new PC will be alternate mode. */
1651 reg
= jtype_target (inst
) << 2;
1652 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1653 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1655 else if (is_octeon_bbit_op (op
, gdbarch
))
1659 branch_if
= op
== 58 || op
== 62;
1660 bit
= itype_rt (inst
);
1662 /* Take into account the *32 instructions. */
1663 if (op
== 54 || op
== 62)
1666 if (((get_frame_register_signed (frame
,
1667 itype_rs (inst
)) >> bit
) & 1)
1669 pc
+= mips32_relative_offset (inst
) + 4;
1671 pc
+= 8; /* After the delay slot. */
1675 pc
+= 4; /* Not a branch, next instruction is easy. */
1678 { /* This gets way messy. */
1680 /* Further subdivide into SPECIAL, REGIMM and other. */
1681 switch (op
& 0x07) /* Extract bits 28,27,26. */
1683 case 0: /* SPECIAL */
1684 op
= rtype_funct (inst
);
1689 /* Set PC to that address. */
1690 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1692 case 12: /* SYSCALL */
1694 struct gdbarch_tdep
*tdep
;
1696 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1697 if (tdep
->syscall_next_pc
!= NULL
)
1698 pc
= tdep
->syscall_next_pc (frame
);
1707 break; /* end SPECIAL */
1708 case 1: /* REGIMM */
1710 op
= itype_rt (inst
); /* branch condition */
1715 case 16: /* BLTZAL */
1716 case 18: /* BLTZALL */
1718 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1719 pc
+= mips32_relative_offset (inst
) + 4;
1721 pc
+= 8; /* after the delay slot */
1725 case 17: /* BGEZAL */
1726 case 19: /* BGEZALL */
1727 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1728 pc
+= mips32_relative_offset (inst
) + 4;
1730 pc
+= 8; /* after the delay slot */
1732 case 0x1c: /* BPOSGE32 */
1733 case 0x1e: /* BPOSGE64 */
1735 if (itype_rs (inst
) == 0)
1737 unsigned int pos
= (op
& 2) ? 64 : 32;
1738 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1741 /* No way to handle; it'll most likely trap anyway. */
1744 if ((get_frame_register_unsigned (frame
,
1745 dspctl
) & 0x7f) >= pos
)
1746 pc
+= mips32_relative_offset (inst
);
1751 /* All of the other instructions in the REGIMM category */
1756 break; /* end REGIMM */
1761 reg
= jtype_target (inst
) << 2;
1762 /* Upper four bits get never changed... */
1763 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1766 case 4: /* BEQ, BEQL */
1768 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1769 get_frame_register_signed (frame
, itype_rt (inst
)))
1770 pc
+= mips32_relative_offset (inst
) + 4;
1774 case 5: /* BNE, BNEL */
1776 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1777 get_frame_register_signed (frame
, itype_rt (inst
)))
1778 pc
+= mips32_relative_offset (inst
) + 4;
1782 case 6: /* BLEZ, BLEZL */
1783 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1784 pc
+= mips32_relative_offset (inst
) + 4;
1790 greater_branch
: /* BGTZ, BGTZL */
1791 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1792 pc
+= mips32_relative_offset (inst
) + 4;
1799 } /* mips32_next_pc */
1801 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1805 micromips_relative_offset7 (ULONGEST insn
)
1807 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1810 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1814 micromips_relative_offset10 (ULONGEST insn
)
1816 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1819 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1823 micromips_relative_offset16 (ULONGEST insn
)
1825 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1828 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1831 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1835 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1836 return mips_insn_size (ISA_MICROMIPS
, insn
);
1839 /* Calculate the address of the next microMIPS instruction to execute
1840 after the INSN coprocessor 1 conditional branch instruction at the
1841 address PC. COUNT denotes the number of coprocessor condition bits
1842 examined by the branch. */
1845 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1846 ULONGEST insn
, CORE_ADDR pc
, int count
)
1848 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1849 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1850 int tf
= b5s5_op (insn
>> 16) & 1;
1851 int mask
= (1 << count
) - 1;
1856 /* No way to handle; it'll most likely trap anyway. */
1859 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1860 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1862 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1863 pc
+= micromips_relative_offset16 (insn
);
1865 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1870 /* Calculate the address of the next microMIPS instruction to execute
1871 after the instruction at the address PC. */
1874 micromips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1876 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1879 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1880 pc
+= MIPS_INSN16_SIZE
;
1881 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1883 /* 32-bit instructions. */
1884 case 2 * MIPS_INSN16_SIZE
:
1886 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1887 pc
+= MIPS_INSN16_SIZE
;
1888 switch (micromips_op (insn
>> 16))
1890 case 0x00: /* POOL32A: bits 000000 */
1891 if (b0s6_op (insn
) == 0x3c
1892 /* POOL32Axf: bits 000000 ... 111100 */
1893 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1894 /* JALR, JALR.HB: 000000 000x111100 111100 */
1895 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1896 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
>> 16));
1899 case 0x10: /* POOL32I: bits 010000 */
1900 switch (b5s5_op (insn
>> 16))
1902 case 0x00: /* BLTZ: bits 010000 00000 */
1903 case 0x01: /* BLTZAL: bits 010000 00001 */
1904 case 0x11: /* BLTZALS: bits 010000 10001 */
1905 if (get_frame_register_signed (frame
,
1906 b0s5_reg (insn
>> 16)) < 0)
1907 pc
+= micromips_relative_offset16 (insn
);
1909 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1912 case 0x02: /* BGEZ: bits 010000 00010 */
1913 case 0x03: /* BGEZAL: bits 010000 00011 */
1914 case 0x13: /* BGEZALS: bits 010000 10011 */
1915 if (get_frame_register_signed (frame
,
1916 b0s5_reg (insn
>> 16)) >= 0)
1917 pc
+= micromips_relative_offset16 (insn
);
1919 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1922 case 0x04: /* BLEZ: bits 010000 00100 */
1923 if (get_frame_register_signed (frame
,
1924 b0s5_reg (insn
>> 16)) <= 0)
1925 pc
+= micromips_relative_offset16 (insn
);
1927 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1930 case 0x05: /* BNEZC: bits 010000 00101 */
1931 if (get_frame_register_signed (frame
,
1932 b0s5_reg (insn
>> 16)) != 0)
1933 pc
+= micromips_relative_offset16 (insn
);
1936 case 0x06: /* BGTZ: bits 010000 00110 */
1937 if (get_frame_register_signed (frame
,
1938 b0s5_reg (insn
>> 16)) > 0)
1939 pc
+= micromips_relative_offset16 (insn
);
1941 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1944 case 0x07: /* BEQZC: bits 010000 00111 */
1945 if (get_frame_register_signed (frame
,
1946 b0s5_reg (insn
>> 16)) == 0)
1947 pc
+= micromips_relative_offset16 (insn
);
1950 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1951 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1952 if (((insn
>> 16) & 0x3) == 0x0)
1953 /* BC2F, BC2T: don't know how to handle these. */
1957 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1958 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1960 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1961 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1964 /* No way to handle; it'll most likely trap anyway. */
1967 if ((get_frame_register_unsigned (frame
,
1968 dspctl
) & 0x7f) >= pos
)
1969 pc
+= micromips_relative_offset16 (insn
);
1971 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1975 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1976 /* BC1ANY2F: bits 010000 11100 xxx01 */
1977 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1978 /* BC1ANY2T: bits 010000 11101 xxx01 */
1979 if (((insn
>> 16) & 0x2) == 0x0)
1980 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
,
1981 ((insn
>> 16) & 0x1) + 1);
1984 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1985 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1986 if (((insn
>> 16) & 0x3) == 0x1)
1987 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
, 4);
1992 case 0x1d: /* JALS: bits 011101 */
1993 case 0x35: /* J: bits 110101 */
1994 case 0x3d: /* JAL: bits 111101 */
1995 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
1998 case 0x25: /* BEQ: bits 100101 */
1999 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
2000 == get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
2001 pc
+= micromips_relative_offset16 (insn
);
2003 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2006 case 0x2d: /* BNE: bits 101101 */
2007 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
2008 != get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
2009 pc
+= micromips_relative_offset16 (insn
);
2011 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2014 case 0x3c: /* JALX: bits 111100 */
2015 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2020 /* 16-bit instructions. */
2021 case MIPS_INSN16_SIZE
:
2022 switch (micromips_op (insn
))
2024 case 0x11: /* POOL16C: bits 010001 */
2025 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2026 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2027 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
));
2028 else if (b5s5_op (insn
) == 0x18)
2029 /* JRADDIUSP: bits 010001 11000 */
2030 pc
= get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
2033 case 0x23: /* BEQZ16: bits 100011 */
2035 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2037 if (get_frame_register_signed (frame
, rs
) == 0)
2038 pc
+= micromips_relative_offset7 (insn
);
2040 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2044 case 0x2b: /* BNEZ16: bits 101011 */
2046 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2048 if (get_frame_register_signed (frame
, rs
) != 0)
2049 pc
+= micromips_relative_offset7 (insn
);
2051 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2055 case 0x33: /* B16: bits 110011 */
2056 pc
+= micromips_relative_offset10 (insn
);
2065 /* Decoding the next place to set a breakpoint is irregular for the
2066 mips 16 variant, but fortunately, there fewer instructions. We have
2067 to cope ith extensions for 16 bit instructions and a pair of actual
2068 32 bit instructions. We dont want to set a single step instruction
2069 on the extend instruction either. */
2071 /* Lots of mips16 instruction formats */
2072 /* Predicting jumps requires itype,ritype,i8type
2073 and their extensions extItype,extritype,extI8type. */
2074 enum mips16_inst_fmts
2076 itype
, /* 0 immediate 5,10 */
2077 ritype
, /* 1 5,3,8 */
2078 rrtype
, /* 2 5,3,3,5 */
2079 rritype
, /* 3 5,3,3,5 */
2080 rrrtype
, /* 4 5,3,3,3,2 */
2081 rriatype
, /* 5 5,3,3,1,4 */
2082 shifttype
, /* 6 5,3,3,3,2 */
2083 i8type
, /* 7 5,3,8 */
2084 i8movtype
, /* 8 5,3,3,5 */
2085 i8mov32rtype
, /* 9 5,3,5,3 */
2086 i64type
, /* 10 5,3,8 */
2087 ri64type
, /* 11 5,3,3,5 */
2088 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2089 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2090 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2091 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2092 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2093 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2094 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2095 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2096 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2097 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2099 /* I am heaping all the fields of the formats into one structure and
2100 then, only the fields which are involved in instruction extension. */
2104 unsigned int regx
; /* Function in i8 type. */
2109 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2110 for the bits which make up the immediate extension. */
2113 extended_offset (unsigned int extension
)
2117 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2119 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2121 value
|= extension
& 0x1f; /* Extract 4:0. */
2126 /* Only call this function if you know that this is an extendable
2127 instruction. It won't malfunction, but why make excess remote memory
2128 references? If the immediate operands get sign extended or something,
2129 do it after the extension is performed. */
2130 /* FIXME: Every one of these cases needs to worry about sign extension
2131 when the offset is to be used in relative addressing. */
2134 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2136 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2139 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2140 target_read_memory (pc
, buf
, 2);
2141 return extract_unsigned_integer (buf
, 2, byte_order
);
2145 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2146 unsigned int extension
,
2148 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2153 switch (insn_format
)
2160 value
= extended_offset ((extension
<< 16) | inst
);
2161 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2165 value
= inst
& 0x7ff;
2166 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2175 { /* A register identifier and an offset. */
2176 /* Most of the fields are the same as I type but the
2177 immediate value is of a different length. */
2181 value
= extended_offset ((extension
<< 16) | inst
);
2182 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2186 value
= inst
& 0xff; /* 8 bits */
2187 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2190 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2196 unsigned long value
;
2197 unsigned int nexthalf
;
2198 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2199 value
= value
<< 16;
2200 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2201 /* Low bit still set. */
2209 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2211 upk
->offset
= offset
;
2217 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2218 and having a signed 16-bit OFFSET. */
2221 add_offset_16 (CORE_ADDR pc
, int offset
)
2223 return pc
+ (offset
<< 1) + 2;
2227 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
2228 unsigned int extension
, unsigned int insn
)
2230 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2231 int op
= (insn
>> 11);
2234 case 2: /* Branch */
2236 struct upk_mips16 upk
;
2237 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2238 pc
= add_offset_16 (pc
, upk
.offset
);
2241 case 3: /* JAL , JALX - Watch out, these are 32 bit
2244 struct upk_mips16 upk
;
2245 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2246 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2247 if ((insn
>> 10) & 0x01) /* Exchange mode */
2248 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2255 struct upk_mips16 upk
;
2257 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2258 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2260 pc
= add_offset_16 (pc
, upk
.offset
);
2267 struct upk_mips16 upk
;
2269 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2270 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2272 pc
= add_offset_16 (pc
, upk
.offset
);
2277 case 12: /* I8 Formats btez btnez */
2279 struct upk_mips16 upk
;
2281 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2282 /* upk.regx contains the opcode */
2283 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
2284 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2285 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2286 pc
= add_offset_16 (pc
, upk
.offset
);
2291 case 29: /* RR Formats JR, JALR, JALR-RA */
2293 struct upk_mips16 upk
;
2294 /* upk.fmt = rrtype; */
2299 upk
.regx
= (insn
>> 8) & 0x07;
2300 upk
.regy
= (insn
>> 5) & 0x07;
2301 if ((upk
.regy
& 1) == 0)
2302 reg
= mips_reg3_to_reg
[upk
.regx
];
2304 reg
= 31; /* Function return instruction. */
2305 pc
= get_frame_register_signed (frame
, reg
);
2312 /* This is an instruction extension. Fetch the real instruction
2313 (which follows the extension) and decode things based on
2317 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
2318 fetch_mips_16 (gdbarch
, pc
));
2331 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2333 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2334 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2335 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
2338 /* The mips_next_pc function supports single_step when the remote
2339 target monitor or stub is not developed enough to do a single_step.
2340 It works by decoding the current instruction and predicting where a
2341 branch will go. This isn't hard because all the data is available.
2342 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2344 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2346 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2348 if (mips_pc_is_mips16 (gdbarch
, pc
))
2349 return mips16_next_pc (frame
, pc
);
2350 else if (mips_pc_is_micromips (gdbarch
, pc
))
2351 return micromips_next_pc (frame
, pc
);
2353 return mips32_next_pc (frame
, pc
);
2356 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2360 mips16_instruction_is_compact_branch (unsigned short insn
)
2362 switch (insn
& 0xf800)
2365 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2367 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2368 case 0x2800: /* BNEZ */
2369 case 0x2000: /* BEQZ */
2370 case 0x1000: /* B */
2377 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2381 micromips_instruction_is_compact_branch (unsigned short insn
)
2383 switch (micromips_op (insn
))
2385 case 0x11: /* POOL16C: bits 010001 */
2386 return (b5s5_op (insn
) == 0x18
2387 /* JRADDIUSP: bits 010001 11000 */
2388 || b5s5_op (insn
) == 0xd);
2389 /* JRC: bits 010011 01101 */
2390 case 0x10: /* POOL32I: bits 010000 */
2391 return (b5s5_op (insn
) & 0x1d) == 0x5;
2392 /* BEQZC/BNEZC: bits 010000 001x1 */
2398 struct mips_frame_cache
2401 struct trad_frame_saved_reg
*saved_regs
;
2404 /* Set a register's saved stack address in temp_saved_regs. If an
2405 address has already been set for this register, do nothing; this
2406 way we will only recognize the first save of a given register in a
2409 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2410 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2411 Strictly speaking, only the second range is used as it is only second
2412 range (the ABI instead of ISA registers) that comes into play when finding
2413 saved registers in a frame. */
2416 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2417 int regnum
, CORE_ADDR offset
)
2419 if (this_cache
!= NULL
2420 && this_cache
->saved_regs
[regnum
].addr
== -1)
2422 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2424 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2430 /* Fetch the immediate value from a MIPS16 instruction.
2431 If the previous instruction was an EXTEND, use it to extend
2432 the upper bits of the immediate value. This is a helper function
2433 for mips16_scan_prologue. */
2436 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2437 unsigned short inst
, /* current instruction */
2438 int nbits
, /* number of bits in imm field */
2439 int scale
, /* scale factor to be applied to imm */
2440 int is_signed
) /* is the imm field signed? */
2444 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2446 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2447 if (offset
& 0x8000) /* check for negative extend */
2448 offset
= 0 - (0x10000 - (offset
& 0xffff));
2449 return offset
| (inst
& 0x1f);
2453 int max_imm
= 1 << nbits
;
2454 int mask
= max_imm
- 1;
2455 int sign_bit
= max_imm
>> 1;
2457 offset
= inst
& mask
;
2458 if (is_signed
&& (offset
& sign_bit
))
2459 offset
= 0 - (max_imm
- offset
);
2460 return offset
* scale
;
2465 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2466 the associated FRAME_CACHE if not null.
2467 Return the address of the first instruction past the prologue. */
2470 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2471 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2472 struct frame_info
*this_frame
,
2473 struct mips_frame_cache
*this_cache
)
2475 int prev_non_prologue_insn
= 0;
2476 int this_non_prologue_insn
;
2477 int non_prologue_insns
= 0;
2480 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2482 long frame_offset
= 0; /* Size of stack frame. */
2483 long frame_adjust
= 0; /* Offset of FP from SP. */
2484 int frame_reg
= MIPS_SP_REGNUM
;
2485 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2486 unsigned inst
= 0; /* current instruction */
2487 unsigned entry_inst
= 0; /* the entry instruction */
2488 unsigned save_inst
= 0; /* the save instruction */
2489 int prev_delay_slot
= 0;
2493 int extend_bytes
= 0;
2494 int prev_extend_bytes
= 0;
2495 CORE_ADDR end_prologue_addr
;
2497 /* Can be called when there's no process, and hence when there's no
2499 if (this_frame
!= NULL
)
2500 sp
= get_frame_register_signed (this_frame
,
2501 gdbarch_num_regs (gdbarch
)
2506 if (limit_pc
> start_pc
+ 200)
2507 limit_pc
= start_pc
+ 200;
2510 /* Permit at most one non-prologue non-control-transfer instruction
2511 in the middle which may have been reordered by the compiler for
2513 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2515 this_non_prologue_insn
= 0;
2518 /* Save the previous instruction. If it's an EXTEND, we'll extract
2519 the immediate offset extension from it in mips16_get_imm. */
2522 /* Fetch and decode the instruction. */
2523 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2526 /* Normally we ignore extend instructions. However, if it is
2527 not followed by a valid prologue instruction, then this
2528 instruction is not part of the prologue either. We must
2529 remember in this case to adjust the end_prologue_addr back
2531 if ((inst
& 0xf800) == 0xf000) /* extend */
2533 extend_bytes
= MIPS_INSN16_SIZE
;
2537 prev_extend_bytes
= extend_bytes
;
2540 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2541 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2543 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2544 if (offset
< 0) /* Negative stack adjustment? */
2545 frame_offset
-= offset
;
2547 /* Exit loop if a positive stack adjustment is found, which
2548 usually means that the stack cleanup code in the function
2549 epilogue is reached. */
2552 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2554 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2555 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2556 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2558 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2560 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2561 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2562 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2564 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2566 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2567 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2569 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2571 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2572 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2574 else if (inst
== 0x673d) /* move $s1, $sp */
2579 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2581 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2582 frame_addr
= sp
+ offset
;
2584 frame_adjust
= offset
;
2586 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2588 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2589 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2590 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2592 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2594 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2595 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2596 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2598 else if ((inst
& 0xf81f) == 0xe809
2599 && (inst
& 0x700) != 0x700) /* entry */
2600 entry_inst
= inst
; /* Save for later processing. */
2601 else if ((inst
& 0xff80) == 0x6480) /* save */
2603 save_inst
= inst
; /* Save for later processing. */
2604 if (prev_extend_bytes
) /* extend */
2605 save_inst
|= prev_inst
<< 16;
2607 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2609 /* This instruction is part of the prologue, but we don't
2610 need to do anything special to handle it. */
2612 else if (mips16_instruction_has_delay_slot (inst
, 0))
2613 /* JAL/JALR/JALX/JR */
2615 /* The instruction in the delay slot can be a part
2616 of the prologue, so move forward once more. */
2618 if (mips16_instruction_has_delay_slot (inst
, 1))
2621 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2622 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2627 this_non_prologue_insn
= 1;
2630 non_prologue_insns
+= this_non_prologue_insn
;
2632 /* A jump or branch, or enough non-prologue insns seen? If so,
2633 then we must have reached the end of the prologue by now. */
2634 if (prev_delay_slot
|| non_prologue_insns
> 1
2635 || mips16_instruction_is_compact_branch (inst
))
2638 prev_non_prologue_insn
= this_non_prologue_insn
;
2639 prev_delay_slot
= in_delay_slot
;
2640 prev_pc
= cur_pc
- prev_extend_bytes
;
2643 /* The entry instruction is typically the first instruction in a function,
2644 and it stores registers at offsets relative to the value of the old SP
2645 (before the prologue). But the value of the sp parameter to this
2646 function is the new SP (after the prologue has been executed). So we
2647 can't calculate those offsets until we've seen the entire prologue,
2648 and can calculate what the old SP must have been. */
2649 if (entry_inst
!= 0)
2651 int areg_count
= (entry_inst
>> 8) & 7;
2652 int sreg_count
= (entry_inst
>> 6) & 3;
2654 /* The entry instruction always subtracts 32 from the SP. */
2657 /* Now we can calculate what the SP must have been at the
2658 start of the function prologue. */
2661 /* Check if a0-a3 were saved in the caller's argument save area. */
2662 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2664 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2665 offset
+= mips_abi_regsize (gdbarch
);
2668 /* Check if the ra register was pushed on the stack. */
2670 if (entry_inst
& 0x20)
2672 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2673 offset
-= mips_abi_regsize (gdbarch
);
2676 /* Check if the s0 and s1 registers were pushed on the stack. */
2677 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2679 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2680 offset
-= mips_abi_regsize (gdbarch
);
2684 /* The SAVE instruction is similar to ENTRY, except that defined by the
2685 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2686 size of the frame is specified as an immediate field of instruction
2687 and an extended variation exists which lets additional registers and
2688 frame space to be specified. The instruction always treats registers
2689 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2690 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2692 static int args_table
[16] = {
2693 0, 0, 0, 0, 1, 1, 1, 1,
2694 2, 2, 2, 0, 3, 3, 4, -1,
2696 static int astatic_table
[16] = {
2697 0, 1, 2, 3, 0, 1, 2, 3,
2698 0, 1, 2, 4, 0, 1, 0, -1,
2700 int aregs
= (save_inst
>> 16) & 0xf;
2701 int xsregs
= (save_inst
>> 24) & 0x7;
2702 int args
= args_table
[aregs
];
2703 int astatic
= astatic_table
[aregs
];
2708 warning (_("Invalid number of argument registers encoded in SAVE."));
2713 warning (_("Invalid number of static registers encoded in SAVE."));
2717 /* For standard SAVE the frame size of 0 means 128. */
2718 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2719 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2722 frame_offset
+= frame_size
;
2724 /* Now we can calculate what the SP must have been at the
2725 start of the function prologue. */
2728 /* Check if A0-A3 were saved in the caller's argument save area. */
2729 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2731 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2732 offset
+= mips_abi_regsize (gdbarch
);
2737 /* Check if the RA register was pushed on the stack. */
2738 if (save_inst
& 0x40)
2740 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2741 offset
-= mips_abi_regsize (gdbarch
);
2744 /* Check if the S8 register was pushed on the stack. */
2747 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2748 offset
-= mips_abi_regsize (gdbarch
);
2751 /* Check if S2-S7 were pushed on the stack. */
2752 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2754 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2755 offset
-= mips_abi_regsize (gdbarch
);
2758 /* Check if the S1 register was pushed on the stack. */
2759 if (save_inst
& 0x10)
2761 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2762 offset
-= mips_abi_regsize (gdbarch
);
2764 /* Check if the S0 register was pushed on the stack. */
2765 if (save_inst
& 0x20)
2767 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2768 offset
-= mips_abi_regsize (gdbarch
);
2771 /* Check if A0-A3 were pushed on the stack. */
2772 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2774 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2775 offset
-= mips_abi_regsize (gdbarch
);
2779 if (this_cache
!= NULL
)
2782 (get_frame_register_signed (this_frame
,
2783 gdbarch_num_regs (gdbarch
) + frame_reg
)
2784 + frame_offset
- frame_adjust
);
2785 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2786 be able to get rid of the assignment below, evetually. But it's
2787 still needed for now. */
2788 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2789 + mips_regnum (gdbarch
)->pc
]
2790 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2793 /* Set end_prologue_addr to the address of the instruction immediately
2794 after the last one we scanned. Unless the last one looked like a
2795 non-prologue instruction (and we looked ahead), in which case use
2796 its address instead. */
2797 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2798 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2800 return end_prologue_addr
;
2803 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2804 Procedures that use the 32-bit instruction set are handled by the
2805 mips_insn32 unwinder. */
2807 static struct mips_frame_cache
*
2808 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2810 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2811 struct mips_frame_cache
*cache
;
2813 if ((*this_cache
) != NULL
)
2814 return (struct mips_frame_cache
*) (*this_cache
);
2815 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2816 (*this_cache
) = cache
;
2817 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2819 /* Analyze the function prologue. */
2821 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2822 CORE_ADDR start_addr
;
2824 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2825 if (start_addr
== 0)
2826 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2827 /* We can't analyze the prologue if we couldn't find the begining
2829 if (start_addr
== 0)
2832 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2833 (struct mips_frame_cache
*) *this_cache
);
2836 /* gdbarch_sp_regnum contains the value and not the address. */
2837 trad_frame_set_value (cache
->saved_regs
,
2838 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2841 return (struct mips_frame_cache
*) (*this_cache
);
2845 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2846 struct frame_id
*this_id
)
2848 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2850 /* This marks the outermost frame. */
2851 if (info
->base
== 0)
2853 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2856 static struct value
*
2857 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2858 void **this_cache
, int regnum
)
2860 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2862 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2866 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2867 struct frame_info
*this_frame
, void **this_cache
)
2869 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2870 CORE_ADDR pc
= get_frame_pc (this_frame
);
2871 if (mips_pc_is_mips16 (gdbarch
, pc
))
2876 static const struct frame_unwind mips_insn16_frame_unwind
=
2879 default_frame_unwind_stop_reason
,
2880 mips_insn16_frame_this_id
,
2881 mips_insn16_frame_prev_register
,
2883 mips_insn16_frame_sniffer
2887 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2890 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2895 static const struct frame_base mips_insn16_frame_base
=
2897 &mips_insn16_frame_unwind
,
2898 mips_insn16_frame_base_address
,
2899 mips_insn16_frame_base_address
,
2900 mips_insn16_frame_base_address
2903 static const struct frame_base
*
2904 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2906 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2907 CORE_ADDR pc
= get_frame_pc (this_frame
);
2908 if (mips_pc_is_mips16 (gdbarch
, pc
))
2909 return &mips_insn16_frame_base
;
2914 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2915 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2916 interpreted directly, and then multiplied by 4. */
2919 micromips_decode_imm9 (int imm
)
2921 imm
= (imm
^ 0x100) - 0x100;
2922 if (imm
> -3 && imm
< 2)
2927 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2928 the address of the first instruction past the prologue. */
2931 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2932 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2933 struct frame_info
*this_frame
,
2934 struct mips_frame_cache
*this_cache
)
2936 CORE_ADDR end_prologue_addr
;
2937 int prev_non_prologue_insn
= 0;
2938 int frame_reg
= MIPS_SP_REGNUM
;
2939 int this_non_prologue_insn
;
2940 int non_prologue_insns
= 0;
2941 long frame_offset
= 0; /* Size of stack frame. */
2942 long frame_adjust
= 0; /* Offset of FP from SP. */
2943 int prev_delay_slot
= 0;
2947 ULONGEST insn
; /* current instruction */
2951 long v1_off
= 0; /* The assumption is LUI will replace it. */
2962 /* Can be called when there's no process, and hence when there's no
2964 if (this_frame
!= NULL
)
2965 sp
= get_frame_register_signed (this_frame
,
2966 gdbarch_num_regs (gdbarch
)
2971 if (limit_pc
> start_pc
+ 200)
2972 limit_pc
= start_pc
+ 200;
2975 /* Permit at most one non-prologue non-control-transfer instruction
2976 in the middle which may have been reordered by the compiler for
2978 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2980 this_non_prologue_insn
= 0;
2984 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2985 loc
+= MIPS_INSN16_SIZE
;
2986 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2988 /* 32-bit instructions. */
2989 case 2 * MIPS_INSN16_SIZE
:
2991 insn
|= mips_fetch_instruction (gdbarch
,
2992 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
2993 loc
+= MIPS_INSN16_SIZE
;
2994 switch (micromips_op (insn
>> 16))
2996 /* Record $sp/$fp adjustment. */
2997 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2998 case 0x0: /* POOL32A: bits 000000 */
2999 case 0x16: /* POOL32S: bits 010110 */
3000 op
= b0s11_op (insn
);
3001 sreg
= b0s5_reg (insn
>> 16);
3002 treg
= b5s5_reg (insn
>> 16);
3003 dreg
= b11s5_reg (insn
);
3005 /* SUBU: bits 000000 00111010000 */
3006 /* DSUBU: bits 010110 00111010000 */
3007 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3009 /* (D)SUBU $sp, $v1 */
3011 else if (op
!= 0x150
3012 /* ADDU: bits 000000 00101010000 */
3013 /* DADDU: bits 010110 00101010000 */
3014 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3015 this_non_prologue_insn
= 1;
3018 case 0x8: /* POOL32B: bits 001000 */
3019 op
= b12s4_op (insn
);
3020 breg
= b0s5_reg (insn
>> 16);
3021 reglist
= sreg
= b5s5_reg (insn
>> 16);
3022 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3023 if ((op
== 0x9 || op
== 0xc)
3024 /* SWP: bits 001000 1001 */
3025 /* SDP: bits 001000 1100 */
3026 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3027 /* S[DW]P reg,offset($sp) */
3029 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3030 set_reg_offset (gdbarch
, this_cache
,
3032 set_reg_offset (gdbarch
, this_cache
,
3033 sreg
+ 1, sp
+ offset
+ s
);
3035 else if ((op
== 0xd || op
== 0xf)
3036 /* SWM: bits 001000 1101 */
3037 /* SDM: bits 001000 1111 */
3038 && breg
== MIPS_SP_REGNUM
3039 /* SWM reglist,offset($sp) */
3040 && ((reglist
>= 1 && reglist
<= 9)
3041 || (reglist
>= 16 && reglist
<= 25)))
3043 int sreglist
= std::min(reglist
& 0xf, 8);
3045 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3046 for (i
= 0; i
< sreglist
; i
++)
3047 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3048 if ((reglist
& 0xf) > 8)
3049 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3050 if ((reglist
& 0x10) == 0x10)
3051 set_reg_offset (gdbarch
, this_cache
,
3052 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3055 this_non_prologue_insn
= 1;
3058 /* Record $sp/$fp adjustment. */
3059 /* Discard (D)ADDIU $gp used for PIC code. */
3060 case 0xc: /* ADDIU: bits 001100 */
3061 case 0x17: /* DADDIU: bits 010111 */
3062 sreg
= b0s5_reg (insn
>> 16);
3063 dreg
= b5s5_reg (insn
>> 16);
3064 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3065 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3066 /* (D)ADDIU $sp, imm */
3068 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3069 /* (D)ADDIU $fp, $sp, imm */
3071 frame_adjust
= offset
;
3074 else if (sreg
!= 28 || dreg
!= 28)
3075 /* (D)ADDIU $gp, imm */
3076 this_non_prologue_insn
= 1;
3079 /* LUI $v1 is used for larger $sp adjustments. */
3080 /* Discard LUI $gp used for PIC code. */
3081 case 0x10: /* POOL32I: bits 010000 */
3082 if (b5s5_op (insn
>> 16) == 0xd
3083 /* LUI: bits 010000 001101 */
3084 && b0s5_reg (insn
>> 16) == 3)
3086 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3087 else if (b5s5_op (insn
>> 16) != 0xd
3088 /* LUI: bits 010000 001101 */
3089 || b0s5_reg (insn
>> 16) != 28)
3091 this_non_prologue_insn
= 1;
3094 /* ORI $v1 is used for larger $sp adjustments. */
3095 case 0x14: /* ORI: bits 010100 */
3096 sreg
= b0s5_reg (insn
>> 16);
3097 dreg
= b5s5_reg (insn
>> 16);
3098 if (sreg
== 3 && dreg
== 3)
3100 v1_off
|= b0s16_imm (insn
);
3102 this_non_prologue_insn
= 1;
3105 case 0x26: /* SWC1: bits 100110 */
3106 case 0x2e: /* SDC1: bits 101110 */
3107 breg
= b0s5_reg (insn
>> 16);
3108 if (breg
!= MIPS_SP_REGNUM
)
3109 /* S[DW]C1 reg,offset($sp) */
3110 this_non_prologue_insn
= 1;
3113 case 0x36: /* SD: bits 110110 */
3114 case 0x3e: /* SW: bits 111110 */
3115 breg
= b0s5_reg (insn
>> 16);
3116 sreg
= b5s5_reg (insn
>> 16);
3117 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3118 if (breg
== MIPS_SP_REGNUM
)
3119 /* S[DW] reg,offset($sp) */
3120 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3122 this_non_prologue_insn
= 1;
3126 /* The instruction in the delay slot can be a part
3127 of the prologue, so move forward once more. */
3128 if (micromips_instruction_has_delay_slot (insn
, 0))
3131 this_non_prologue_insn
= 1;
3137 /* 16-bit instructions. */
3138 case MIPS_INSN16_SIZE
:
3139 switch (micromips_op (insn
))
3141 case 0x3: /* MOVE: bits 000011 */
3142 sreg
= b0s5_reg (insn
);
3143 dreg
= b5s5_reg (insn
);
3144 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3147 else if ((sreg
& 0x1c) != 0x4)
3148 /* MOVE reg, $a0-$a3 */
3149 this_non_prologue_insn
= 1;
3152 case 0x11: /* POOL16C: bits 010001 */
3153 if (b6s4_op (insn
) == 0x5)
3154 /* SWM: bits 010001 0101 */
3156 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3157 reglist
= b4s2_regl (insn
);
3158 for (i
= 0; i
<= reglist
; i
++)
3159 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3160 set_reg_offset (gdbarch
, this_cache
,
3161 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3164 this_non_prologue_insn
= 1;
3167 case 0x13: /* POOL16D: bits 010011 */
3168 if ((insn
& 0x1) == 0x1)
3169 /* ADDIUSP: bits 010011 1 */
3170 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3171 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3172 /* ADDIUS5: bits 010011 0 */
3173 /* ADDIUS5 $sp, imm */
3174 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3176 this_non_prologue_insn
= 1;
3179 case 0x32: /* SWSP: bits 110010 */
3180 offset
= b0s5_imm (insn
) << 2;
3181 sreg
= b5s5_reg (insn
);
3182 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3186 /* The instruction in the delay slot can be a part
3187 of the prologue, so move forward once more. */
3188 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3191 this_non_prologue_insn
= 1;
3197 frame_offset
-= sp_adj
;
3199 non_prologue_insns
+= this_non_prologue_insn
;
3201 /* A jump or branch, enough non-prologue insns seen or positive
3202 stack adjustment? If so, then we must have reached the end
3203 of the prologue by now. */
3204 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3205 || micromips_instruction_is_compact_branch (insn
))
3208 prev_non_prologue_insn
= this_non_prologue_insn
;
3209 prev_delay_slot
= in_delay_slot
;
3213 if (this_cache
!= NULL
)
3216 (get_frame_register_signed (this_frame
,
3217 gdbarch_num_regs (gdbarch
) + frame_reg
)
3218 + frame_offset
- frame_adjust
);
3219 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3220 be able to get rid of the assignment below, evetually. But it's
3221 still needed for now. */
3222 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3223 + mips_regnum (gdbarch
)->pc
]
3224 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3227 /* Set end_prologue_addr to the address of the instruction immediately
3228 after the last one we scanned. Unless the last one looked like a
3229 non-prologue instruction (and we looked ahead), in which case use
3230 its address instead. */
3232 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3234 return end_prologue_addr
;
3237 /* Heuristic unwinder for procedures using microMIPS instructions.
3238 Procedures that use the 32-bit instruction set are handled by the
3239 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3241 static struct mips_frame_cache
*
3242 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3244 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3245 struct mips_frame_cache
*cache
;
3247 if ((*this_cache
) != NULL
)
3248 return (struct mips_frame_cache
*) (*this_cache
);
3250 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3251 (*this_cache
) = cache
;
3252 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3254 /* Analyze the function prologue. */
3256 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3257 CORE_ADDR start_addr
;
3259 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3260 if (start_addr
== 0)
3261 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3262 /* We can't analyze the prologue if we couldn't find the begining
3264 if (start_addr
== 0)
3267 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3268 (struct mips_frame_cache
*) *this_cache
);
3271 /* gdbarch_sp_regnum contains the value and not the address. */
3272 trad_frame_set_value (cache
->saved_regs
,
3273 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3276 return (struct mips_frame_cache
*) (*this_cache
);
3280 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3281 struct frame_id
*this_id
)
3283 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3285 /* This marks the outermost frame. */
3286 if (info
->base
== 0)
3288 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3291 static struct value
*
3292 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3293 void **this_cache
, int regnum
)
3295 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3297 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3301 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3302 struct frame_info
*this_frame
, void **this_cache
)
3304 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3305 CORE_ADDR pc
= get_frame_pc (this_frame
);
3307 if (mips_pc_is_micromips (gdbarch
, pc
))
3312 static const struct frame_unwind mips_micro_frame_unwind
=
3315 default_frame_unwind_stop_reason
,
3316 mips_micro_frame_this_id
,
3317 mips_micro_frame_prev_register
,
3319 mips_micro_frame_sniffer
3323 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3326 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3331 static const struct frame_base mips_micro_frame_base
=
3333 &mips_micro_frame_unwind
,
3334 mips_micro_frame_base_address
,
3335 mips_micro_frame_base_address
,
3336 mips_micro_frame_base_address
3339 static const struct frame_base
*
3340 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3342 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3343 CORE_ADDR pc
= get_frame_pc (this_frame
);
3345 if (mips_pc_is_micromips (gdbarch
, pc
))
3346 return &mips_micro_frame_base
;
3351 /* Mark all the registers as unset in the saved_regs array
3352 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3355 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3357 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3361 const int num_regs
= gdbarch_num_regs (gdbarch
);
3364 for (i
= 0; i
< num_regs
; i
++)
3366 this_cache
->saved_regs
[i
].addr
= -1;
3371 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3372 the associated FRAME_CACHE if not null.
3373 Return the address of the first instruction past the prologue. */
3376 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3377 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3378 struct frame_info
*this_frame
,
3379 struct mips_frame_cache
*this_cache
)
3381 int prev_non_prologue_insn
;
3382 int this_non_prologue_insn
;
3383 int non_prologue_insns
;
3384 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3386 int prev_delay_slot
;
3391 int frame_reg
= MIPS_SP_REGNUM
;
3393 CORE_ADDR end_prologue_addr
;
3394 int seen_sp_adjust
= 0;
3395 int load_immediate_bytes
= 0;
3397 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3399 /* Can be called when there's no process, and hence when there's no
3401 if (this_frame
!= NULL
)
3402 sp
= get_frame_register_signed (this_frame
,
3403 gdbarch_num_regs (gdbarch
)
3408 if (limit_pc
> start_pc
+ 200)
3409 limit_pc
= start_pc
+ 200;
3412 prev_non_prologue_insn
= 0;
3413 non_prologue_insns
= 0;
3414 prev_delay_slot
= 0;
3417 /* Permit at most one non-prologue non-control-transfer instruction
3418 in the middle which may have been reordered by the compiler for
3421 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3423 unsigned long inst
, high_word
;
3427 this_non_prologue_insn
= 0;
3430 /* Fetch the instruction. */
3431 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3434 /* Save some code by pre-extracting some useful fields. */
3435 high_word
= (inst
>> 16) & 0xffff;
3436 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3437 reg
= high_word
& 0x1f;
3439 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3440 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3441 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3443 if (offset
< 0) /* Negative stack adjustment? */
3444 frame_offset
-= offset
;
3446 /* Exit loop if a positive stack adjustment is found, which
3447 usually means that the stack cleanup code in the function
3448 epilogue is reached. */
3452 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3453 && !regsize_is_64_bits
)
3455 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3457 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3458 && regsize_is_64_bits
)
3460 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3461 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3463 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3465 /* Old gcc frame, r30 is virtual frame pointer. */
3466 if (offset
!= frame_offset
)
3467 frame_addr
= sp
+ offset
;
3468 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3470 unsigned alloca_adjust
;
3473 frame_addr
= get_frame_register_signed
3474 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3477 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3478 if (alloca_adjust
> 0)
3480 /* FP > SP + frame_size. This may be because of
3481 an alloca or somethings similar. Fix sp to
3482 "pre-alloca" value, and try again. */
3483 sp
+= alloca_adjust
;
3484 /* Need to reset the status of all registers. Otherwise,
3485 we will hit a guard that prevents the new address
3486 for each register to be recomputed during the second
3488 reset_saved_regs (gdbarch
, this_cache
);
3493 /* move $30,$sp. With different versions of gas this will be either
3494 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3495 Accept any one of these. */
3496 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3498 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3499 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3501 unsigned alloca_adjust
;
3504 frame_addr
= get_frame_register_signed
3505 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3507 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3508 if (alloca_adjust
> 0)
3510 /* FP > SP + frame_size. This may be because of
3511 an alloca or somethings similar. Fix sp to
3512 "pre-alloca" value, and try again. */
3514 /* Need to reset the status of all registers. Otherwise,
3515 we will hit a guard that prevents the new address
3516 for each register to be recomputed during the second
3518 reset_saved_regs (gdbarch
, this_cache
);
3523 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3524 && !regsize_is_64_bits
)
3526 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3528 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3529 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3530 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3531 || high_word
== 0x3c1c /* lui $gp,n */
3532 || high_word
== 0x279c /* addiu $gp,$gp,n */
3533 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3534 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3537 /* These instructions are part of the prologue, but we don't
3538 need to do anything special to handle them. */
3540 /* The instructions below load $at or $t0 with an immediate
3541 value in preparation for a stack adjustment via
3542 subu $sp,$sp,[$at,$t0]. These instructions could also
3543 initialize a local variable, so we accept them only before
3544 a stack adjustment instruction was seen. */
3545 else if (!seen_sp_adjust
3547 && (high_word
== 0x3c01 /* lui $at,n */
3548 || high_word
== 0x3c08 /* lui $t0,n */
3549 || high_word
== 0x3421 /* ori $at,$at,n */
3550 || high_word
== 0x3508 /* ori $t0,$t0,n */
3551 || high_word
== 0x3401 /* ori $at,$zero,n */
3552 || high_word
== 0x3408 /* ori $t0,$zero,n */
3555 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3557 /* Check for branches and jumps. The instruction in the delay
3558 slot can be a part of the prologue, so move forward once more. */
3559 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3563 /* This instruction is not an instruction typically found
3564 in a prologue, so we must have reached the end of the
3568 this_non_prologue_insn
= 1;
3571 non_prologue_insns
+= this_non_prologue_insn
;
3573 /* A jump or branch, or enough non-prologue insns seen? If so,
3574 then we must have reached the end of the prologue by now. */
3575 if (prev_delay_slot
|| non_prologue_insns
> 1)
3578 prev_non_prologue_insn
= this_non_prologue_insn
;
3579 prev_delay_slot
= in_delay_slot
;
3583 if (this_cache
!= NULL
)
3586 (get_frame_register_signed (this_frame
,
3587 gdbarch_num_regs (gdbarch
) + frame_reg
)
3589 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3590 this assignment below, eventually. But it's still needed
3592 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3593 + mips_regnum (gdbarch
)->pc
]
3594 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3598 /* Set end_prologue_addr to the address of the instruction immediately
3599 after the last one we scanned. Unless the last one looked like a
3600 non-prologue instruction (and we looked ahead), in which case use
3601 its address instead. */
3603 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3605 /* In a frameless function, we might have incorrectly
3606 skipped some load immediate instructions. Undo the skipping
3607 if the load immediate was not followed by a stack adjustment. */
3608 if (load_immediate_bytes
&& !seen_sp_adjust
)
3609 end_prologue_addr
-= load_immediate_bytes
;
3611 return end_prologue_addr
;
3614 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3615 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3616 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3617 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3619 static struct mips_frame_cache
*
3620 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3622 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3623 struct mips_frame_cache
*cache
;
3625 if ((*this_cache
) != NULL
)
3626 return (struct mips_frame_cache
*) (*this_cache
);
3628 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3629 (*this_cache
) = cache
;
3630 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3632 /* Analyze the function prologue. */
3634 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3635 CORE_ADDR start_addr
;
3637 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3638 if (start_addr
== 0)
3639 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3640 /* We can't analyze the prologue if we couldn't find the begining
3642 if (start_addr
== 0)
3645 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3646 (struct mips_frame_cache
*) *this_cache
);
3649 /* gdbarch_sp_regnum contains the value and not the address. */
3650 trad_frame_set_value (cache
->saved_regs
,
3651 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3654 return (struct mips_frame_cache
*) (*this_cache
);
3658 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3659 struct frame_id
*this_id
)
3661 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3663 /* This marks the outermost frame. */
3664 if (info
->base
== 0)
3666 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3669 static struct value
*
3670 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3671 void **this_cache
, int regnum
)
3673 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3675 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3679 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3680 struct frame_info
*this_frame
, void **this_cache
)
3682 CORE_ADDR pc
= get_frame_pc (this_frame
);
3683 if (mips_pc_is_mips (pc
))
3688 static const struct frame_unwind mips_insn32_frame_unwind
=
3691 default_frame_unwind_stop_reason
,
3692 mips_insn32_frame_this_id
,
3693 mips_insn32_frame_prev_register
,
3695 mips_insn32_frame_sniffer
3699 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3702 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3707 static const struct frame_base mips_insn32_frame_base
=
3709 &mips_insn32_frame_unwind
,
3710 mips_insn32_frame_base_address
,
3711 mips_insn32_frame_base_address
,
3712 mips_insn32_frame_base_address
3715 static const struct frame_base
*
3716 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3718 CORE_ADDR pc
= get_frame_pc (this_frame
);
3719 if (mips_pc_is_mips (pc
))
3720 return &mips_insn32_frame_base
;
3725 static struct trad_frame_cache
*
3726 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3729 CORE_ADDR start_addr
;
3730 CORE_ADDR stack_addr
;
3731 struct trad_frame_cache
*this_trad_cache
;
3732 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3733 int num_regs
= gdbarch_num_regs (gdbarch
);
3735 if ((*this_cache
) != NULL
)
3736 return (struct trad_frame_cache
*) (*this_cache
);
3737 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3738 (*this_cache
) = this_trad_cache
;
3740 /* The return address is in the link register. */
3741 trad_frame_set_reg_realreg (this_trad_cache
,
3742 gdbarch_pc_regnum (gdbarch
),
3743 num_regs
+ MIPS_RA_REGNUM
);
3745 /* Frame ID, since it's a frameless / stackless function, no stack
3746 space is allocated and SP on entry is the current SP. */
3747 pc
= get_frame_pc (this_frame
);
3748 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3749 stack_addr
= get_frame_register_signed (this_frame
,
3750 num_regs
+ MIPS_SP_REGNUM
);
3751 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3753 /* Assume that the frame's base is the same as the
3755 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3757 return this_trad_cache
;
3761 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3762 struct frame_id
*this_id
)
3764 struct trad_frame_cache
*this_trad_cache
3765 = mips_stub_frame_cache (this_frame
, this_cache
);
3766 trad_frame_get_id (this_trad_cache
, this_id
);
3769 static struct value
*
3770 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3771 void **this_cache
, int regnum
)
3773 struct trad_frame_cache
*this_trad_cache
3774 = mips_stub_frame_cache (this_frame
, this_cache
);
3775 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3779 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3780 struct frame_info
*this_frame
, void **this_cache
)
3783 struct obj_section
*s
;
3784 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3785 struct bound_minimal_symbol msym
;
3787 /* Use the stub unwinder for unreadable code. */
3788 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3791 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3794 /* Calling a PIC function from a non-PIC function passes through a
3795 stub. The stub for foo is named ".pic.foo". */
3796 msym
= lookup_minimal_symbol_by_pc (pc
);
3797 if (msym
.minsym
!= NULL
3798 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
3799 && startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
3805 static const struct frame_unwind mips_stub_frame_unwind
=
3808 default_frame_unwind_stop_reason
,
3809 mips_stub_frame_this_id
,
3810 mips_stub_frame_prev_register
,
3812 mips_stub_frame_sniffer
3816 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3819 struct trad_frame_cache
*this_trad_cache
3820 = mips_stub_frame_cache (this_frame
, this_cache
);
3821 return trad_frame_get_this_base (this_trad_cache
);
3824 static const struct frame_base mips_stub_frame_base
=
3826 &mips_stub_frame_unwind
,
3827 mips_stub_frame_base_address
,
3828 mips_stub_frame_base_address
,
3829 mips_stub_frame_base_address
3832 static const struct frame_base
*
3833 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3835 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3836 return &mips_stub_frame_base
;
3841 /* mips_addr_bits_remove - remove useless address bits */
3844 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3846 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3848 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3849 /* This hack is a work-around for existing boards using PMON, the
3850 simulator, and any other 64-bit targets that doesn't have true
3851 64-bit addressing. On these targets, the upper 32 bits of
3852 addresses are ignored by the hardware. Thus, the PC or SP are
3853 likely to have been sign extended to all 1s by instruction
3854 sequences that load 32-bit addresses. For example, a typical
3855 piece of code that loads an address is this:
3857 lui $r2, <upper 16 bits>
3858 ori $r2, <lower 16 bits>
3860 But the lui sign-extends the value such that the upper 32 bits
3861 may be all 1s. The workaround is simply to mask off these
3862 bits. In the future, gcc may be changed to support true 64-bit
3863 addressing, and this masking will have to be disabled. */
3864 return addr
&= 0xffffffffUL
;
3870 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3871 instruction and ending with a SC/SCD instruction. If such a sequence
3872 is found, attempt to step through it. A breakpoint is placed at the end of
3875 /* Instructions used during single-stepping of atomic sequences, standard
3877 #define LL_OPCODE 0x30
3878 #define LLD_OPCODE 0x34
3879 #define SC_OPCODE 0x38
3880 #define SCD_OPCODE 0x3c
3883 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3884 struct address_space
*aspace
, CORE_ADDR pc
)
3886 CORE_ADDR breaks
[2] = {-1, -1};
3888 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3892 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3893 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3895 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3896 /* Assume all atomic sequences start with a ll/lld instruction. */
3897 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3900 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3902 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3905 loc
+= MIPS_INSN32_SIZE
;
3906 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3908 /* Assume that there is at most one branch in the atomic
3909 sequence. If a branch is found, put a breakpoint in its
3910 destination address. */
3911 switch (itype_op (insn
))
3913 case 0: /* SPECIAL */
3914 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3915 return 0; /* fallback to the standard single-step code. */
3917 case 1: /* REGIMM */
3918 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3919 || ((itype_rt (insn
) & 0x1e) == 0
3920 && itype_rs (insn
) == 0)); /* BPOSGE* */
3924 return 0; /* fallback to the standard single-step code. */
3931 case 22: /* BLEZL */
3932 case 23: /* BGTTL */
3936 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3937 && (itype_rt (insn
) & 0x2) == 0);
3938 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3943 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3948 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3949 if (last_breakpoint
>= 1)
3950 return 0; /* More than one branch found, fallback to the
3951 standard single-step code. */
3952 breaks
[1] = branch_bp
;
3956 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3960 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3961 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3964 loc
+= MIPS_INSN32_SIZE
;
3966 /* Insert a breakpoint right after the end of the atomic sequence. */
3969 /* Check for duplicated breakpoints. Check also for a breakpoint
3970 placed (branch instruction's destination) in the atomic sequence. */
3971 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3972 last_breakpoint
= 0;
3974 /* Effectively inserts the breakpoints. */
3975 for (index
= 0; index
<= last_breakpoint
; index
++)
3976 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3982 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3983 struct address_space
*aspace
,
3986 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3987 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3988 CORE_ADDR breaks
[2] = {-1, -1};
3989 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
3997 /* Assume all atomic sequences start with a ll/lld instruction. */
3998 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3999 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4001 loc
+= MIPS_INSN16_SIZE
;
4003 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4004 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4006 loc
+= MIPS_INSN16_SIZE
;
4008 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4009 that no atomic sequence is longer than "atomic_sequence_length"
4011 for (insn_count
= 0;
4012 !sc_found
&& insn_count
< atomic_sequence_length
;
4017 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4018 loc
+= MIPS_INSN16_SIZE
;
4020 /* Assume that there is at most one conditional branch in the
4021 atomic sequence. If a branch is found, put a breakpoint in
4022 its destination address. */
4023 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4025 /* 32-bit instructions. */
4026 case 2 * MIPS_INSN16_SIZE
:
4027 switch (micromips_op (insn
))
4029 case 0x10: /* POOL32I: bits 010000 */
4030 if ((b5s5_op (insn
) & 0x18) != 0x0
4031 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4032 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4033 && (b5s5_op (insn
) & 0x1d) != 0x11
4034 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4035 && ((b5s5_op (insn
) & 0x1e) != 0x14
4036 || (insn
& 0x3) != 0x0)
4037 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4038 && (b5s5_op (insn
) & 0x1e) != 0x1a
4039 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4040 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4041 || (insn
& 0x3) != 0x0)
4042 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4043 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4044 || (insn
& 0x3) != 0x1))
4045 /* BC1ANY*: bits 010000 111xx xxx01 */
4049 case 0x25: /* BEQ: bits 100101 */
4050 case 0x2d: /* BNE: bits 101101 */
4052 insn
|= mips_fetch_instruction (gdbarch
,
4053 ISA_MICROMIPS
, loc
, NULL
);
4054 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4055 + micromips_relative_offset16 (insn
));
4059 case 0x00: /* POOL32A: bits 000000 */
4061 insn
|= mips_fetch_instruction (gdbarch
,
4062 ISA_MICROMIPS
, loc
, NULL
);
4063 if (b0s6_op (insn
) != 0x3c
4064 /* POOL32Axf: bits 000000 ... 111100 */
4065 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4066 /* JALR, JALR.HB: 000000 000x111100 111100 */
4067 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4071 case 0x1d: /* JALS: bits 011101 */
4072 case 0x35: /* J: bits 110101 */
4073 case 0x3d: /* JAL: bits 111101 */
4074 case 0x3c: /* JALX: bits 111100 */
4075 return 0; /* Fall back to the standard single-step code. */
4077 case 0x18: /* POOL32C: bits 011000 */
4078 if ((b12s4_op (insn
) & 0xb) == 0xb)
4079 /* SC, SCD: bits 011000 1x11 */
4083 loc
+= MIPS_INSN16_SIZE
;
4086 /* 16-bit instructions. */
4087 case MIPS_INSN16_SIZE
:
4088 switch (micromips_op (insn
))
4090 case 0x23: /* BEQZ16: bits 100011 */
4091 case 0x2b: /* BNEZ16: bits 101011 */
4092 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4096 case 0x11: /* POOL16C: bits 010001 */
4097 if ((b5s5_op (insn
) & 0x1c) != 0xc
4098 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4099 && b5s5_op (insn
) != 0x18)
4100 /* JRADDIUSP: bits 010001 11000 */
4102 return 0; /* Fall back to the standard single-step code. */
4104 case 0x33: /* B16: bits 110011 */
4105 return 0; /* Fall back to the standard single-step code. */
4111 if (last_breakpoint
>= 1)
4112 return 0; /* More than one branch found, fallback to the
4113 standard single-step code. */
4114 breaks
[1] = branch_bp
;
4121 /* Insert a breakpoint right after the end of the atomic sequence. */
4124 /* Check for duplicated breakpoints. Check also for a breakpoint
4125 placed (branch instruction's destination) in the atomic sequence */
4126 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4127 last_breakpoint
= 0;
4129 /* Effectively inserts the breakpoints. */
4130 for (index
= 0; index
<= last_breakpoint
; index
++)
4131 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
4137 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4138 struct address_space
*aspace
, CORE_ADDR pc
)
4140 if (mips_pc_is_mips (pc
))
4141 return mips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4142 else if (mips_pc_is_micromips (gdbarch
, pc
))
4143 return micromips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4148 /* mips_software_single_step() is called just before we want to resume
4149 the inferior, if we want to single-step it but there is no hardware
4150 or kernel single-step support (MIPS on GNU/Linux for example). We find
4151 the target of the coming instruction and breakpoint it. */
4154 mips_software_single_step (struct frame_info
*frame
)
4156 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4157 struct address_space
*aspace
= get_frame_address_space (frame
);
4158 CORE_ADDR pc
, next_pc
;
4160 pc
= get_frame_pc (frame
);
4161 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
4164 next_pc
= mips_next_pc (frame
, pc
);
4166 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
4170 /* Test whether the PC points to the return instruction at the
4171 end of a function. */
4174 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4179 /* This used to check for MIPS16, but this piece of code is never
4180 called for MIPS16 functions. And likewise microMIPS ones. */
4181 gdb_assert (mips_pc_is_mips (pc
));
4183 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4185 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4189 /* This fencepost looks highly suspicious to me. Removing it also
4190 seems suspicious as it could affect remote debugging across serial
4194 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4200 struct inferior
*inf
;
4202 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4204 fence
= start_pc
- heuristic_fence_post
;
4208 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4209 fence
= VM_MIN_ADDRESS
;
4211 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4213 inf
= current_inferior ();
4215 /* Search back for previous return. */
4216 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4217 if (start_pc
< fence
)
4219 /* It's not clear to me why we reach this point when
4220 stop_soon, but with this test, at least we
4221 don't print out warnings for every child forked (eg, on
4222 decstation). 22apr93 rich@cygnus.com. */
4223 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4225 static int blurb_printed
= 0;
4227 warning (_("GDB can't find the start of the function at %s."),
4228 paddress (gdbarch
, pc
));
4232 /* This actually happens frequently in embedded
4233 development, when you first connect to a board
4234 and your stack pointer and pc are nowhere in
4235 particular. This message needs to give people
4236 in that situation enough information to
4237 determine that it's no big deal. */
4238 printf_filtered ("\n\
4239 GDB is unable to find the start of the function at %s\n\
4240 and thus can't determine the size of that function's stack frame.\n\
4241 This means that GDB may be unable to access that stack frame, or\n\
4242 the frames below it.\n\
4243 This problem is most likely caused by an invalid program counter or\n\
4245 However, if you think GDB should simply search farther back\n\
4246 from %s for code which looks like the beginning of a\n\
4247 function, you can increase the range of the search using the `set\n\
4248 heuristic-fence-post' command.\n",
4249 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4256 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4258 unsigned short inst
;
4260 /* On MIPS16, any one of the following is likely to be the
4261 start of a function:
4267 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4268 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4269 if ((inst
& 0xff80) == 0x6480) /* save */
4271 if (start_pc
- instlen
>= fence
)
4273 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4274 start_pc
- instlen
, NULL
);
4275 if ((inst
& 0xf800) == 0xf000) /* extend */
4276 start_pc
-= instlen
;
4280 else if (((inst
& 0xf81f) == 0xe809
4281 && (inst
& 0x700) != 0x700) /* entry */
4282 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4283 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4284 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4286 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4287 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4292 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4300 /* On microMIPS, any one of the following is likely to be the
4301 start of a function:
4305 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4306 switch (micromips_op (insn
))
4308 case 0xc: /* ADDIU: bits 001100 */
4309 case 0x17: /* DADDIU: bits 010111 */
4310 sreg
= b0s5_reg (insn
);
4311 dreg
= b5s5_reg (insn
);
4313 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4314 pc
+ MIPS_INSN16_SIZE
, NULL
);
4315 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4316 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4317 /* (D)ADDIU $sp, imm */
4322 case 0x10: /* POOL32I: bits 010000 */
4323 if (b5s5_op (insn
) == 0xd
4324 /* LUI: bits 010000 001101 */
4325 && b0s5_reg (insn
>> 16) == 28)
4330 case 0x13: /* POOL16D: bits 010011 */
4331 if ((insn
& 0x1) == 0x1)
4332 /* ADDIUSP: bits 010011 1 */
4334 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4340 /* ADDIUS5: bits 010011 0 */
4342 dreg
= b5s5_reg (insn
);
4343 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4344 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4345 /* ADDIUS5 $sp, -imm */
4353 else if (mips_about_to_return (gdbarch
, start_pc
))
4355 /* Skip return and its delay slot. */
4356 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4363 struct mips_objfile_private
4369 /* According to the current ABI, should the type be passed in a
4370 floating-point register (assuming that there is space)? When there
4371 is no FPU, FP are not even considered as possible candidates for
4372 FP registers and, consequently this returns false - forces FP
4373 arguments into integer registers. */
4376 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4377 struct type
*arg_type
)
4379 return ((typecode
== TYPE_CODE_FLT
4380 || (MIPS_EABI (gdbarch
)
4381 && (typecode
== TYPE_CODE_STRUCT
4382 || typecode
== TYPE_CODE_UNION
)
4383 && TYPE_NFIELDS (arg_type
) == 1
4384 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4386 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4389 /* On o32, argument passing in GPRs depends on the alignment of the type being
4390 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4393 mips_type_needs_double_align (struct type
*type
)
4395 enum type_code typecode
= TYPE_CODE (type
);
4397 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4399 else if (typecode
== TYPE_CODE_STRUCT
)
4401 if (TYPE_NFIELDS (type
) < 1)
4403 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4405 else if (typecode
== TYPE_CODE_UNION
)
4409 n
= TYPE_NFIELDS (type
);
4410 for (i
= 0; i
< n
; i
++)
4411 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4418 /* Adjust the address downward (direction of stack growth) so that it
4419 is correctly aligned for a new stack frame. */
4421 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4423 return align_down (addr
, 16);
4426 /* Implement the "push_dummy_code" gdbarch method. */
4429 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4430 CORE_ADDR funaddr
, struct value
**args
,
4431 int nargs
, struct type
*value_type
,
4432 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4433 struct regcache
*regcache
)
4435 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4439 /* Reserve enough room on the stack for our breakpoint instruction. */
4440 bp_slot
= sp
- sizeof (nop_insn
);
4442 /* Return to microMIPS mode if calling microMIPS code to avoid
4443 triggering an address error exception on processors that only
4444 support microMIPS execution. */
4445 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4446 ? make_compact_addr (bp_slot
) : bp_slot
);
4448 /* The breakpoint layer automatically adjusts the address of
4449 breakpoints inserted in a branch delay slot. With enough
4450 bad luck, the 4 bytes located just before our breakpoint
4451 instruction could look like a branch instruction, and thus
4452 trigger the adjustement, and break the function call entirely.
4453 So, we reserve those 4 bytes and write a nop instruction
4454 to prevent that from happening. */
4455 nop_addr
= bp_slot
- sizeof (nop_insn
);
4456 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4457 sp
= mips_frame_align (gdbarch
, nop_addr
);
4459 /* Inferior resumes at the function entry point. */
4466 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4467 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4468 int nargs
, struct value
**args
, CORE_ADDR sp
,
4469 int struct_return
, CORE_ADDR struct_addr
)
4475 int stack_offset
= 0;
4476 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4477 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4478 int regsize
= mips_abi_regsize (gdbarch
);
4480 /* For shared libraries, "t9" needs to point at the function
4482 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4484 /* Set the return address register to point to the entry point of
4485 the program, where a breakpoint lies in wait. */
4486 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4488 /* First ensure that the stack and structure return address (if any)
4489 are properly aligned. The stack has to be at least 64-bit
4490 aligned even on 32-bit machines, because doubles must be 64-bit
4491 aligned. For n32 and n64, stack frames need to be 128-bit
4492 aligned, so we round to this widest known alignment. */
4494 sp
= align_down (sp
, 16);
4495 struct_addr
= align_down (struct_addr
, 16);
4497 /* Now make space on the stack for the args. We allocate more
4498 than necessary for EABI, because the first few arguments are
4499 passed in registers, but that's OK. */
4500 for (argnum
= 0; argnum
< nargs
; argnum
++)
4501 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
4502 sp
-= align_up (len
, 16);
4505 fprintf_unfiltered (gdb_stdlog
,
4506 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4507 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4509 /* Initialize the integer and float register pointers. */
4510 argreg
= MIPS_A0_REGNUM
;
4511 float_argreg
= mips_fpa0_regnum (gdbarch
);
4513 /* The struct_return pointer occupies the first parameter-passing reg. */
4517 fprintf_unfiltered (gdb_stdlog
,
4518 "mips_eabi_push_dummy_call: "
4519 "struct_return reg=%d %s\n",
4520 argreg
, paddress (gdbarch
, struct_addr
));
4521 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4524 /* Now load as many as possible of the first arguments into
4525 registers, and push the rest onto the stack. Loop thru args
4526 from first to last. */
4527 for (argnum
= 0; argnum
< nargs
; argnum
++)
4529 const gdb_byte
*val
;
4530 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4531 struct value
*arg
= args
[argnum
];
4532 struct type
*arg_type
= check_typedef (value_type (arg
));
4533 int len
= TYPE_LENGTH (arg_type
);
4534 enum type_code typecode
= TYPE_CODE (arg_type
);
4537 fprintf_unfiltered (gdb_stdlog
,
4538 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4539 argnum
+ 1, len
, (int) typecode
);
4541 /* The EABI passes structures that do not fit in a register by
4544 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4546 store_unsigned_integer (valbuf
, regsize
, byte_order
,
4547 value_address (arg
));
4548 typecode
= TYPE_CODE_PTR
;
4552 fprintf_unfiltered (gdb_stdlog
, " push");
4555 val
= value_contents (arg
);
4557 /* 32-bit ABIs always start floating point arguments in an
4558 even-numbered floating point register. Round the FP register
4559 up before the check to see if there are any FP registers
4560 left. Non MIPS_EABI targets also pass the FP in the integer
4561 registers so also round up normal registers. */
4562 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4564 if ((float_argreg
& 1))
4568 /* Floating point arguments passed in registers have to be
4569 treated specially. On 32-bit architectures, doubles
4570 are passed in register pairs; the even register gets
4571 the low word, and the odd register gets the high word.
4572 On non-EABI processors, the first two floating point arguments are
4573 also copied to general registers, because MIPS16 functions
4574 don't use float registers for arguments. This duplication of
4575 arguments in general registers can't hurt non-MIPS16 functions
4576 because those registers are normally skipped. */
4577 /* MIPS_EABI squeezes a struct that contains a single floating
4578 point value into an FP register instead of pushing it onto the
4580 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4581 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4583 /* EABI32 will pass doubles in consecutive registers, even on
4584 64-bit cores. At one time, we used to check the size of
4585 `float_argreg' to determine whether or not to pass doubles
4586 in consecutive registers, but this is not sufficient for
4587 making the ABI determination. */
4588 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4590 int low_offset
= gdbarch_byte_order (gdbarch
)
4591 == BFD_ENDIAN_BIG
? 4 : 0;
4594 /* Write the low word of the double to the even register(s). */
4595 regval
= extract_signed_integer (val
+ low_offset
,
4598 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4599 float_argreg
, phex (regval
, 4));
4600 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4602 /* Write the high word of the double to the odd register(s). */
4603 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4606 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4607 float_argreg
, phex (regval
, 4));
4608 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4612 /* This is a floating point value that fits entirely
4613 in a single register. */
4614 /* On 32 bit ABI's the float_argreg is further adjusted
4615 above to ensure that it is even register aligned. */
4616 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4618 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4619 float_argreg
, phex (regval
, len
));
4620 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4625 /* Copy the argument to general registers or the stack in
4626 register-sized pieces. Large arguments are split between
4627 registers and stack. */
4628 /* Note: structs whose size is not a multiple of regsize
4629 are treated specially: Irix cc passes
4630 them in registers where gcc sometimes puts them on the
4631 stack. For maximum compatibility, we will put them in
4633 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
4635 /* Note: Floating-point values that didn't fit into an FP
4636 register are only written to memory. */
4639 /* Remember if the argument was written to the stack. */
4640 int stack_used_p
= 0;
4641 int partial_len
= (len
< regsize
? len
: regsize
);
4644 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4647 /* Write this portion of the argument to the stack. */
4648 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4650 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4652 /* Should shorter than int integer values be
4653 promoted to int before being stored? */
4654 int longword_offset
= 0;
4657 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4660 && (typecode
== TYPE_CODE_INT
4661 || typecode
== TYPE_CODE_PTR
4662 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4663 longword_offset
= regsize
- len
;
4664 else if ((typecode
== TYPE_CODE_STRUCT
4665 || typecode
== TYPE_CODE_UNION
)
4666 && TYPE_LENGTH (arg_type
) < regsize
)
4667 longword_offset
= regsize
- len
;
4672 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4673 paddress (gdbarch
, stack_offset
));
4674 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4675 paddress (gdbarch
, longword_offset
));
4678 addr
= sp
+ stack_offset
+ longword_offset
;
4683 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4684 paddress (gdbarch
, addr
));
4685 for (i
= 0; i
< partial_len
; i
++)
4687 fprintf_unfiltered (gdb_stdlog
, "%02x",
4691 write_memory (addr
, val
, partial_len
);
4694 /* Note!!! This is NOT an else clause. Odd sized
4695 structs may go thru BOTH paths. Floating point
4696 arguments will not. */
4697 /* Write this portion of the argument to a general
4698 purpose register. */
4699 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4700 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4703 extract_signed_integer (val
, partial_len
, byte_order
);
4706 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4708 phex (regval
, regsize
));
4709 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4716 /* Compute the offset into the stack at which we will
4717 copy the next parameter.
4719 In the new EABI (and the NABI32), the stack_offset
4720 only needs to be adjusted when it has been used. */
4723 stack_offset
+= align_up (partial_len
, regsize
);
4727 fprintf_unfiltered (gdb_stdlog
, "\n");
4730 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4732 /* Return adjusted stack pointer. */
4736 /* Determine the return value convention being used. */
4738 static enum return_value_convention
4739 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4740 struct type
*type
, struct regcache
*regcache
,
4741 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4743 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4744 int fp_return_type
= 0;
4745 int offset
, regnum
, xfer
;
4747 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4748 return RETURN_VALUE_STRUCT_CONVENTION
;
4750 /* Floating point type? */
4751 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4753 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4755 /* Structs with a single field of float type
4756 are returned in a floating point register. */
4757 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4758 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4759 && TYPE_NFIELDS (type
) == 1)
4761 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4763 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4770 /* A floating-point value belongs in the least significant part
4773 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4774 regnum
= mips_regnum (gdbarch
)->fp0
;
4778 /* An integer value goes in V0/V1. */
4780 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4781 regnum
= MIPS_V0_REGNUM
;
4784 offset
< TYPE_LENGTH (type
);
4785 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4787 xfer
= mips_abi_regsize (gdbarch
);
4788 if (offset
+ xfer
> TYPE_LENGTH (type
))
4789 xfer
= TYPE_LENGTH (type
) - offset
;
4790 mips_xfer_register (gdbarch
, regcache
,
4791 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4792 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4796 return RETURN_VALUE_REGISTER_CONVENTION
;
4800 /* N32/N64 ABI stuff. */
4802 /* Search for a naturally aligned double at OFFSET inside a struct
4803 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4807 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4812 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4815 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4818 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4821 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4824 struct type
*field_type
;
4826 /* We're only looking at normal fields. */
4827 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4828 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4831 /* If we have gone past the offset, there is no double to pass. */
4832 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4836 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4838 /* If this field is entirely before the requested offset, go
4839 on to the next one. */
4840 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4843 /* If this is our special aligned double, we can stop. */
4844 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4845 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4848 /* This field starts at or before the requested offset, and
4849 overlaps it. If it is a structure, recurse inwards. */
4850 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4857 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4858 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4859 int nargs
, struct value
**args
, CORE_ADDR sp
,
4860 int struct_return
, CORE_ADDR struct_addr
)
4866 int stack_offset
= 0;
4867 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4868 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4870 /* For shared libraries, "t9" needs to point at the function
4872 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4874 /* Set the return address register to point to the entry point of
4875 the program, where a breakpoint lies in wait. */
4876 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4878 /* First ensure that the stack and structure return address (if any)
4879 are properly aligned. The stack has to be at least 64-bit
4880 aligned even on 32-bit machines, because doubles must be 64-bit
4881 aligned. For n32 and n64, stack frames need to be 128-bit
4882 aligned, so we round to this widest known alignment. */
4884 sp
= align_down (sp
, 16);
4885 struct_addr
= align_down (struct_addr
, 16);
4887 /* Now make space on the stack for the args. */
4888 for (argnum
= 0; argnum
< nargs
; argnum
++)
4889 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4890 sp
-= align_up (len
, 16);
4893 fprintf_unfiltered (gdb_stdlog
,
4894 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4895 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4897 /* Initialize the integer and float register pointers. */
4898 argreg
= MIPS_A0_REGNUM
;
4899 float_argreg
= mips_fpa0_regnum (gdbarch
);
4901 /* The struct_return pointer occupies the first parameter-passing reg. */
4905 fprintf_unfiltered (gdb_stdlog
,
4906 "mips_n32n64_push_dummy_call: "
4907 "struct_return reg=%d %s\n",
4908 argreg
, paddress (gdbarch
, struct_addr
));
4909 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4912 /* Now load as many as possible of the first arguments into
4913 registers, and push the rest onto the stack. Loop thru args
4914 from first to last. */
4915 for (argnum
= 0; argnum
< nargs
; argnum
++)
4917 const gdb_byte
*val
;
4918 struct value
*arg
= args
[argnum
];
4919 struct type
*arg_type
= check_typedef (value_type (arg
));
4920 int len
= TYPE_LENGTH (arg_type
);
4921 enum type_code typecode
= TYPE_CODE (arg_type
);
4924 fprintf_unfiltered (gdb_stdlog
,
4925 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4926 argnum
+ 1, len
, (int) typecode
);
4928 val
= value_contents (arg
);
4930 /* A 128-bit long double value requires an even-odd pair of
4931 floating-point registers. */
4933 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4934 && (float_argreg
& 1))
4940 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4941 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4943 /* This is a floating point value that fits entirely
4944 in a single register or a pair of registers. */
4945 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4946 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4948 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4949 float_argreg
, phex (regval
, reglen
));
4950 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4953 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4954 argreg
, phex (regval
, reglen
));
4955 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4960 regval
= extract_unsigned_integer (val
+ reglen
,
4961 reglen
, byte_order
);
4963 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4964 float_argreg
, phex (regval
, reglen
));
4965 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4968 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4969 argreg
, phex (regval
, reglen
));
4970 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4977 /* Copy the argument to general registers or the stack in
4978 register-sized pieces. Large arguments are split between
4979 registers and stack. */
4980 /* For N32/N64, structs, unions, or other composite types are
4981 treated as a sequence of doublewords, and are passed in integer
4982 or floating point registers as though they were simple scalar
4983 parameters to the extent that they fit, with any excess on the
4984 stack packed according to the normal memory layout of the
4986 The caller does not reserve space for the register arguments;
4987 the callee is responsible for reserving it if required. */
4988 /* Note: Floating-point values that didn't fit into an FP
4989 register are only written to memory. */
4992 /* Remember if the argument was written to the stack. */
4993 int stack_used_p
= 0;
4994 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4997 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5000 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5001 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
5003 /* Write this portion of the argument to the stack. */
5004 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
5006 /* Should shorter than int integer values be
5007 promoted to int before being stored? */
5008 int longword_offset
= 0;
5011 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5013 if ((typecode
== TYPE_CODE_INT
5014 || typecode
== TYPE_CODE_PTR
)
5016 longword_offset
= MIPS64_REGSIZE
- len
;
5021 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5022 paddress (gdbarch
, stack_offset
));
5023 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5024 paddress (gdbarch
, longword_offset
));
5027 addr
= sp
+ stack_offset
+ longword_offset
;
5032 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5033 paddress (gdbarch
, addr
));
5034 for (i
= 0; i
< partial_len
; i
++)
5036 fprintf_unfiltered (gdb_stdlog
, "%02x",
5040 write_memory (addr
, val
, partial_len
);
5043 /* Note!!! This is NOT an else clause. Odd sized
5044 structs may go thru BOTH paths. */
5045 /* Write this portion of the argument to a general
5046 purpose register. */
5047 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5051 /* Sign extend pointers, 32-bit integers and signed
5052 16-bit and 8-bit integers; everything else is taken
5055 if ((partial_len
== 4
5056 && (typecode
== TYPE_CODE_PTR
5057 || typecode
== TYPE_CODE_INT
))
5059 && typecode
== TYPE_CODE_INT
5060 && !TYPE_UNSIGNED (arg_type
)))
5061 regval
= extract_signed_integer (val
, partial_len
,
5064 regval
= extract_unsigned_integer (val
, partial_len
,
5067 /* A non-floating-point argument being passed in a
5068 general register. If a struct or union, and if
5069 the remaining length is smaller than the register
5070 size, we have to adjust the register value on
5073 It does not seem to be necessary to do the
5074 same for integral types. */
5076 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5077 && partial_len
< MIPS64_REGSIZE
5078 && (typecode
== TYPE_CODE_STRUCT
5079 || typecode
== TYPE_CODE_UNION
))
5080 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5084 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5086 phex (regval
, MIPS64_REGSIZE
));
5087 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5089 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5090 TYPE_LENGTH (arg_type
) - len
))
5093 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5095 phex (regval
, MIPS64_REGSIZE
));
5096 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5107 /* Compute the offset into the stack at which we will
5108 copy the next parameter.
5110 In N32 (N64?), the stack_offset only needs to be
5111 adjusted when it has been used. */
5114 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5118 fprintf_unfiltered (gdb_stdlog
, "\n");
5121 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5123 /* Return adjusted stack pointer. */
5127 static enum return_value_convention
5128 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5129 struct type
*type
, struct regcache
*regcache
,
5130 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5132 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5134 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5136 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5137 if needed), as appropriate for the type. Composite results (struct,
5138 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5141 * A struct with only one or two floating point fields is returned in $f0
5142 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5145 * Any other composite results of at most 128 bits are returned in
5146 $2 (first 64 bits) and $3 (remainder, if necessary).
5148 * Larger composite results are handled by converting the function to a
5149 procedure with an implicit first parameter, which is a pointer to an area
5150 reserved by the caller to receive the result. [The o32-bit ABI requires
5151 that all composite results be handled by conversion to implicit first
5152 parameters. The MIPS/SGI Fortran implementation has always made a
5153 specific exception to return COMPLEX results in the floating point
5156 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5157 return RETURN_VALUE_STRUCT_CONVENTION
;
5158 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5159 && TYPE_LENGTH (type
) == 16
5160 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5162 /* A 128-bit floating-point value fills both $f0 and $f2. The
5163 two registers are used in the same as memory order, so the
5164 eight bytes with the lower memory address are in $f0. */
5166 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5167 mips_xfer_register (gdbarch
, regcache
,
5168 (gdbarch_num_regs (gdbarch
)
5169 + mips_regnum (gdbarch
)->fp0
),
5170 8, gdbarch_byte_order (gdbarch
),
5171 readbuf
, writebuf
, 0);
5172 mips_xfer_register (gdbarch
, regcache
,
5173 (gdbarch_num_regs (gdbarch
)
5174 + mips_regnum (gdbarch
)->fp0
+ 2),
5175 8, gdbarch_byte_order (gdbarch
),
5176 readbuf
? readbuf
+ 8 : readbuf
,
5177 writebuf
? writebuf
+ 8 : writebuf
, 0);
5178 return RETURN_VALUE_REGISTER_CONVENTION
;
5180 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5181 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5183 /* A single or double floating-point value that fits in FP0. */
5185 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5186 mips_xfer_register (gdbarch
, regcache
,
5187 (gdbarch_num_regs (gdbarch
)
5188 + mips_regnum (gdbarch
)->fp0
),
5190 gdbarch_byte_order (gdbarch
),
5191 readbuf
, writebuf
, 0);
5192 return RETURN_VALUE_REGISTER_CONVENTION
;
5194 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5195 && TYPE_NFIELDS (type
) <= 2
5196 && TYPE_NFIELDS (type
) >= 1
5197 && ((TYPE_NFIELDS (type
) == 1
5198 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5200 || (TYPE_NFIELDS (type
) == 2
5201 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5203 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
5204 == TYPE_CODE_FLT
))))
5206 /* A struct that contains one or two floats. Each value is part
5207 in the least significant part of their floating point
5208 register (or GPR, for soft float). */
5211 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5212 ? mips_regnum (gdbarch
)->fp0
5214 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5216 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5219 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5221 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5223 /* A 16-byte long double field goes in two consecutive
5225 mips_xfer_register (gdbarch
, regcache
,
5226 gdbarch_num_regs (gdbarch
) + regnum
,
5228 gdbarch_byte_order (gdbarch
),
5229 readbuf
, writebuf
, offset
);
5230 mips_xfer_register (gdbarch
, regcache
,
5231 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5233 gdbarch_byte_order (gdbarch
),
5234 readbuf
, writebuf
, offset
+ 8);
5237 mips_xfer_register (gdbarch
, regcache
,
5238 gdbarch_num_regs (gdbarch
) + regnum
,
5239 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5240 gdbarch_byte_order (gdbarch
),
5241 readbuf
, writebuf
, offset
);
5243 return RETURN_VALUE_REGISTER_CONVENTION
;
5245 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5246 || TYPE_CODE (type
) == TYPE_CODE_UNION
5247 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5249 /* A composite type. Extract the left justified value,
5250 regardless of the byte order. I.e. DO NOT USE
5254 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5255 offset
< TYPE_LENGTH (type
);
5256 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5258 int xfer
= register_size (gdbarch
, regnum
);
5259 if (offset
+ xfer
> TYPE_LENGTH (type
))
5260 xfer
= TYPE_LENGTH (type
) - offset
;
5262 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5263 offset
, xfer
, regnum
);
5264 mips_xfer_register (gdbarch
, regcache
,
5265 gdbarch_num_regs (gdbarch
) + regnum
,
5266 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5269 return RETURN_VALUE_REGISTER_CONVENTION
;
5273 /* A scalar extract each part but least-significant-byte
5277 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5278 offset
< TYPE_LENGTH (type
);
5279 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5281 int xfer
= register_size (gdbarch
, regnum
);
5282 if (offset
+ xfer
> TYPE_LENGTH (type
))
5283 xfer
= TYPE_LENGTH (type
) - offset
;
5285 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5286 offset
, xfer
, regnum
);
5287 mips_xfer_register (gdbarch
, regcache
,
5288 gdbarch_num_regs (gdbarch
) + regnum
,
5289 xfer
, gdbarch_byte_order (gdbarch
),
5290 readbuf
, writebuf
, offset
);
5292 return RETURN_VALUE_REGISTER_CONVENTION
;
5296 /* Which registers to use for passing floating-point values between
5297 function calls, one of floating-point, general and both kinds of
5298 registers. O32 and O64 use different register kinds for standard
5299 MIPS and MIPS16 code; to make the handling of cases where we may
5300 not know what kind of code is being used (e.g. no debug information)
5301 easier we sometimes use both kinds. */
5310 /* O32 ABI stuff. */
5313 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5314 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5315 int nargs
, struct value
**args
, CORE_ADDR sp
,
5316 int struct_return
, CORE_ADDR struct_addr
)
5322 int stack_offset
= 0;
5323 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5324 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5326 /* For shared libraries, "t9" needs to point at the function
5328 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5330 /* Set the return address register to point to the entry point of
5331 the program, where a breakpoint lies in wait. */
5332 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5334 /* First ensure that the stack and structure return address (if any)
5335 are properly aligned. The stack has to be at least 64-bit
5336 aligned even on 32-bit machines, because doubles must be 64-bit
5337 aligned. For n32 and n64, stack frames need to be 128-bit
5338 aligned, so we round to this widest known alignment. */
5340 sp
= align_down (sp
, 16);
5341 struct_addr
= align_down (struct_addr
, 16);
5343 /* Now make space on the stack for the args. */
5344 for (argnum
= 0; argnum
< nargs
; argnum
++)
5346 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5348 /* Align to double-word if necessary. */
5349 if (mips_type_needs_double_align (arg_type
))
5350 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5351 /* Allocate space on the stack. */
5352 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5354 sp
-= align_up (len
, 16);
5357 fprintf_unfiltered (gdb_stdlog
,
5358 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5359 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5361 /* Initialize the integer and float register pointers. */
5362 argreg
= MIPS_A0_REGNUM
;
5363 float_argreg
= mips_fpa0_regnum (gdbarch
);
5365 /* The struct_return pointer occupies the first parameter-passing reg. */
5369 fprintf_unfiltered (gdb_stdlog
,
5370 "mips_o32_push_dummy_call: "
5371 "struct_return reg=%d %s\n",
5372 argreg
, paddress (gdbarch
, struct_addr
));
5373 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5374 stack_offset
+= MIPS32_REGSIZE
;
5377 /* Now load as many as possible of the first arguments into
5378 registers, and push the rest onto the stack. Loop thru args
5379 from first to last. */
5380 for (argnum
= 0; argnum
< nargs
; argnum
++)
5382 const gdb_byte
*val
;
5383 struct value
*arg
= args
[argnum
];
5384 struct type
*arg_type
= check_typedef (value_type (arg
));
5385 int len
= TYPE_LENGTH (arg_type
);
5386 enum type_code typecode
= TYPE_CODE (arg_type
);
5389 fprintf_unfiltered (gdb_stdlog
,
5390 "mips_o32_push_dummy_call: %d len=%d type=%d",
5391 argnum
+ 1, len
, (int) typecode
);
5393 val
= value_contents (arg
);
5395 /* 32-bit ABIs always start floating point arguments in an
5396 even-numbered floating point register. Round the FP register
5397 up before the check to see if there are any FP registers
5398 left. O32 targets also pass the FP in the integer registers
5399 so also round up normal registers. */
5400 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5402 if ((float_argreg
& 1))
5406 /* Floating point arguments passed in registers have to be
5407 treated specially. On 32-bit architectures, doubles are
5408 passed in register pairs; the even FP register gets the
5409 low word, and the odd FP register gets the high word.
5410 On O32, the first two floating point arguments are also
5411 copied to general registers, following their memory order,
5412 because MIPS16 functions don't use float registers for
5413 arguments. This duplication of arguments in general
5414 registers can't hurt non-MIPS16 functions, because those
5415 registers are normally skipped. */
5417 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5418 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5420 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5422 int freg_offset
= gdbarch_byte_order (gdbarch
)
5423 == BFD_ENDIAN_BIG
? 1 : 0;
5424 unsigned long regval
;
5427 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5429 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5430 float_argreg
+ freg_offset
,
5432 regcache_cooked_write_unsigned (regcache
,
5433 float_argreg
++ + freg_offset
,
5436 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5437 argreg
, phex (regval
, 4));
5438 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5441 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5443 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5444 float_argreg
- freg_offset
,
5446 regcache_cooked_write_unsigned (regcache
,
5447 float_argreg
++ - freg_offset
,
5450 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5451 argreg
, phex (regval
, 4));
5452 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5456 /* This is a floating point value that fits entirely
5457 in a single register. */
5458 /* On 32 bit ABI's the float_argreg is further adjusted
5459 above to ensure that it is even register aligned. */
5460 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5462 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5463 float_argreg
, phex (regval
, len
));
5464 regcache_cooked_write_unsigned (regcache
,
5465 float_argreg
++, regval
);
5466 /* Although two FP registers are reserved for each
5467 argument, only one corresponding integer register is
5470 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5471 argreg
, phex (regval
, len
));
5472 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5474 /* Reserve space for the FP register. */
5475 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5479 /* Copy the argument to general registers or the stack in
5480 register-sized pieces. Large arguments are split between
5481 registers and stack. */
5482 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5483 are treated specially: Irix cc passes
5484 them in registers where gcc sometimes puts them on the
5485 stack. For maximum compatibility, we will put them in
5487 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5488 && len
% MIPS32_REGSIZE
!= 0);
5489 /* Structures should be aligned to eight bytes (even arg registers)
5490 on MIPS_ABI_O32, if their first member has double precision. */
5491 if (mips_type_needs_double_align (arg_type
))
5496 stack_offset
+= MIPS32_REGSIZE
;
5501 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5504 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5507 /* Write this portion of the argument to the stack. */
5508 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5509 || odd_sized_struct
)
5511 /* Should shorter than int integer values be
5512 promoted to int before being stored? */
5513 int longword_offset
= 0;
5518 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5519 paddress (gdbarch
, stack_offset
));
5520 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5521 paddress (gdbarch
, longword_offset
));
5524 addr
= sp
+ stack_offset
+ longword_offset
;
5529 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5530 paddress (gdbarch
, addr
));
5531 for (i
= 0; i
< partial_len
; i
++)
5533 fprintf_unfiltered (gdb_stdlog
, "%02x",
5537 write_memory (addr
, val
, partial_len
);
5540 /* Note!!! This is NOT an else clause. Odd sized
5541 structs may go thru BOTH paths. */
5542 /* Write this portion of the argument to a general
5543 purpose register. */
5544 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5546 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5548 /* Value may need to be sign extended, because
5549 mips_isa_regsize() != mips_abi_regsize(). */
5551 /* A non-floating-point argument being passed in a
5552 general register. If a struct or union, and if
5553 the remaining length is smaller than the register
5554 size, we have to adjust the register value on
5557 It does not seem to be necessary to do the
5558 same for integral types.
5560 Also don't do this adjustment on O64 binaries.
5562 cagney/2001-07-23: gdb/179: Also, GCC, when
5563 outputting LE O32 with sizeof (struct) <
5564 mips_abi_regsize(), generates a left shift
5565 as part of storing the argument in a register
5566 (the left shift isn't generated when
5567 sizeof (struct) >= mips_abi_regsize()). Since
5568 it is quite possible that this is GCC
5569 contradicting the LE/O32 ABI, GDB has not been
5570 adjusted to accommodate this. Either someone
5571 needs to demonstrate that the LE/O32 ABI
5572 specifies such a left shift OR this new ABI gets
5573 identified as such and GDB gets tweaked
5576 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5577 && partial_len
< MIPS32_REGSIZE
5578 && (typecode
== TYPE_CODE_STRUCT
5579 || typecode
== TYPE_CODE_UNION
))
5580 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5584 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5586 phex (regval
, MIPS32_REGSIZE
));
5587 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5590 /* Prevent subsequent floating point arguments from
5591 being passed in floating point registers. */
5592 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5598 /* Compute the offset into the stack at which we will
5599 copy the next parameter.
5601 In older ABIs, the caller reserved space for
5602 registers that contained arguments. This was loosely
5603 refered to as their "home". Consequently, space is
5604 always allocated. */
5606 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5610 fprintf_unfiltered (gdb_stdlog
, "\n");
5613 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5615 /* Return adjusted stack pointer. */
5619 static enum return_value_convention
5620 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5621 struct type
*type
, struct regcache
*regcache
,
5622 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5624 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5625 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5626 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5627 enum mips_fval_reg fval_reg
;
5629 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5630 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5631 || TYPE_CODE (type
) == TYPE_CODE_UNION
5632 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5633 return RETURN_VALUE_STRUCT_CONVENTION
;
5634 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5635 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5637 /* A single-precision floating-point value. If reading in or copying,
5638 then we get it from/put it to FP0 for standard MIPS code or GPR2
5639 for MIPS16 code. If writing out only, then we put it to both FP0
5640 and GPR2. We do not support reading in with no function known, if
5641 this safety check ever triggers, then we'll have to try harder. */
5642 gdb_assert (function
|| !readbuf
);
5647 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5650 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5652 case mips_fval_both
:
5653 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5656 if (fval_reg
!= mips_fval_gpr
)
5657 mips_xfer_register (gdbarch
, regcache
,
5658 (gdbarch_num_regs (gdbarch
)
5659 + mips_regnum (gdbarch
)->fp0
),
5661 gdbarch_byte_order (gdbarch
),
5662 readbuf
, writebuf
, 0);
5663 if (fval_reg
!= mips_fval_fpr
)
5664 mips_xfer_register (gdbarch
, regcache
,
5665 gdbarch_num_regs (gdbarch
) + 2,
5667 gdbarch_byte_order (gdbarch
),
5668 readbuf
, writebuf
, 0);
5669 return RETURN_VALUE_REGISTER_CONVENTION
;
5671 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5672 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5674 /* A double-precision floating-point value. If reading in or copying,
5675 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5676 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5677 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5678 no function known, if this safety check ever triggers, then we'll
5679 have to try harder. */
5680 gdb_assert (function
|| !readbuf
);
5685 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5688 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5690 case mips_fval_both
:
5691 fprintf_unfiltered (gdb_stderr
,
5692 "Return float in $fp1/$fp0 and $2/$3\n");
5695 if (fval_reg
!= mips_fval_gpr
)
5697 /* The most significant part goes in FP1, and the least significant
5699 switch (gdbarch_byte_order (gdbarch
))
5701 case BFD_ENDIAN_LITTLE
:
5702 mips_xfer_register (gdbarch
, regcache
,
5703 (gdbarch_num_regs (gdbarch
)
5704 + mips_regnum (gdbarch
)->fp0
+ 0),
5705 4, gdbarch_byte_order (gdbarch
),
5706 readbuf
, writebuf
, 0);
5707 mips_xfer_register (gdbarch
, regcache
,
5708 (gdbarch_num_regs (gdbarch
)
5709 + mips_regnum (gdbarch
)->fp0
+ 1),
5710 4, gdbarch_byte_order (gdbarch
),
5711 readbuf
, writebuf
, 4);
5713 case BFD_ENDIAN_BIG
:
5714 mips_xfer_register (gdbarch
, regcache
,
5715 (gdbarch_num_regs (gdbarch
)
5716 + mips_regnum (gdbarch
)->fp0
+ 1),
5717 4, gdbarch_byte_order (gdbarch
),
5718 readbuf
, writebuf
, 0);
5719 mips_xfer_register (gdbarch
, regcache
,
5720 (gdbarch_num_regs (gdbarch
)
5721 + mips_regnum (gdbarch
)->fp0
+ 0),
5722 4, gdbarch_byte_order (gdbarch
),
5723 readbuf
, writebuf
, 4);
5726 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5729 if (fval_reg
!= mips_fval_fpr
)
5731 /* The two 32-bit parts are always placed in GPR2 and GPR3
5732 following these registers' memory order. */
5733 mips_xfer_register (gdbarch
, regcache
,
5734 gdbarch_num_regs (gdbarch
) + 2,
5735 4, gdbarch_byte_order (gdbarch
),
5736 readbuf
, writebuf
, 0);
5737 mips_xfer_register (gdbarch
, regcache
,
5738 gdbarch_num_regs (gdbarch
) + 3,
5739 4, gdbarch_byte_order (gdbarch
),
5740 readbuf
, writebuf
, 4);
5742 return RETURN_VALUE_REGISTER_CONVENTION
;
5745 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5746 && TYPE_NFIELDS (type
) <= 2
5747 && TYPE_NFIELDS (type
) >= 1
5748 && ((TYPE_NFIELDS (type
) == 1
5749 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5751 || (TYPE_NFIELDS (type
) == 2
5752 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5754 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5756 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5758 /* A struct that contains one or two floats. Each value is part
5759 in the least significant part of their floating point
5761 gdb_byte reg
[MAX_REGISTER_SIZE
];
5764 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5765 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5767 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5770 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5772 mips_xfer_register (gdbarch
, regcache
,
5773 gdbarch_num_regs (gdbarch
) + regnum
,
5774 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5775 gdbarch_byte_order (gdbarch
),
5776 readbuf
, writebuf
, offset
);
5778 return RETURN_VALUE_REGISTER_CONVENTION
;
5782 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5783 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5785 /* A structure or union. Extract the left justified value,
5786 regardless of the byte order. I.e. DO NOT USE
5790 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5791 offset
< TYPE_LENGTH (type
);
5792 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5794 int xfer
= register_size (gdbarch
, regnum
);
5795 if (offset
+ xfer
> TYPE_LENGTH (type
))
5796 xfer
= TYPE_LENGTH (type
) - offset
;
5798 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5799 offset
, xfer
, regnum
);
5800 mips_xfer_register (gdbarch
, regcache
,
5801 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5802 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5804 return RETURN_VALUE_REGISTER_CONVENTION
;
5809 /* A scalar extract each part but least-significant-byte
5810 justified. o32 thinks registers are 4 byte, regardless of
5814 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5815 offset
< TYPE_LENGTH (type
);
5816 offset
+= MIPS32_REGSIZE
, regnum
++)
5818 int xfer
= MIPS32_REGSIZE
;
5819 if (offset
+ xfer
> TYPE_LENGTH (type
))
5820 xfer
= TYPE_LENGTH (type
) - offset
;
5822 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5823 offset
, xfer
, regnum
);
5824 mips_xfer_register (gdbarch
, regcache
,
5825 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5826 gdbarch_byte_order (gdbarch
),
5827 readbuf
, writebuf
, offset
);
5829 return RETURN_VALUE_REGISTER_CONVENTION
;
5833 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5837 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5838 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5840 struct value
**args
, CORE_ADDR sp
,
5841 int struct_return
, CORE_ADDR struct_addr
)
5847 int stack_offset
= 0;
5848 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5849 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5851 /* For shared libraries, "t9" needs to point at the function
5853 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5855 /* Set the return address register to point to the entry point of
5856 the program, where a breakpoint lies in wait. */
5857 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5859 /* First ensure that the stack and structure return address (if any)
5860 are properly aligned. The stack has to be at least 64-bit
5861 aligned even on 32-bit machines, because doubles must be 64-bit
5862 aligned. For n32 and n64, stack frames need to be 128-bit
5863 aligned, so we round to this widest known alignment. */
5865 sp
= align_down (sp
, 16);
5866 struct_addr
= align_down (struct_addr
, 16);
5868 /* Now make space on the stack for the args. */
5869 for (argnum
= 0; argnum
< nargs
; argnum
++)
5871 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5873 /* Allocate space on the stack. */
5874 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5876 sp
-= align_up (len
, 16);
5879 fprintf_unfiltered (gdb_stdlog
,
5880 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5881 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5883 /* Initialize the integer and float register pointers. */
5884 argreg
= MIPS_A0_REGNUM
;
5885 float_argreg
= mips_fpa0_regnum (gdbarch
);
5887 /* The struct_return pointer occupies the first parameter-passing reg. */
5891 fprintf_unfiltered (gdb_stdlog
,
5892 "mips_o64_push_dummy_call: "
5893 "struct_return reg=%d %s\n",
5894 argreg
, paddress (gdbarch
, struct_addr
));
5895 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5896 stack_offset
+= MIPS64_REGSIZE
;
5899 /* Now load as many as possible of the first arguments into
5900 registers, and push the rest onto the stack. Loop thru args
5901 from first to last. */
5902 for (argnum
= 0; argnum
< nargs
; argnum
++)
5904 const gdb_byte
*val
;
5905 struct value
*arg
= args
[argnum
];
5906 struct type
*arg_type
= check_typedef (value_type (arg
));
5907 int len
= TYPE_LENGTH (arg_type
);
5908 enum type_code typecode
= TYPE_CODE (arg_type
);
5911 fprintf_unfiltered (gdb_stdlog
,
5912 "mips_o64_push_dummy_call: %d len=%d type=%d",
5913 argnum
+ 1, len
, (int) typecode
);
5915 val
= value_contents (arg
);
5917 /* Floating point arguments passed in registers have to be
5918 treated specially. On 32-bit architectures, doubles are
5919 passed in register pairs; the even FP register gets the
5920 low word, and the odd FP register gets the high word.
5921 On O64, the first two floating point arguments are also
5922 copied to general registers, because MIPS16 functions
5923 don't use float registers for arguments. This duplication
5924 of arguments in general registers can't hurt non-MIPS16
5925 functions because those registers are normally skipped. */
5927 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5928 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5930 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5932 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5933 float_argreg
, phex (regval
, len
));
5934 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5936 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5937 argreg
, phex (regval
, len
));
5938 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5940 /* Reserve space for the FP register. */
5941 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5945 /* Copy the argument to general registers or the stack in
5946 register-sized pieces. Large arguments are split between
5947 registers and stack. */
5948 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5949 are treated specially: Irix cc passes them in registers
5950 where gcc sometimes puts them on the stack. For maximum
5951 compatibility, we will put them in both places. */
5952 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5953 && len
% MIPS64_REGSIZE
!= 0);
5956 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5959 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5962 /* Write this portion of the argument to the stack. */
5963 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5964 || odd_sized_struct
)
5966 /* Should shorter than int integer values be
5967 promoted to int before being stored? */
5968 int longword_offset
= 0;
5970 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5972 if ((typecode
== TYPE_CODE_INT
5973 || typecode
== TYPE_CODE_PTR
5974 || typecode
== TYPE_CODE_FLT
)
5976 longword_offset
= MIPS64_REGSIZE
- len
;
5981 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5982 paddress (gdbarch
, stack_offset
));
5983 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5984 paddress (gdbarch
, longword_offset
));
5987 addr
= sp
+ stack_offset
+ longword_offset
;
5992 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5993 paddress (gdbarch
, addr
));
5994 for (i
= 0; i
< partial_len
; i
++)
5996 fprintf_unfiltered (gdb_stdlog
, "%02x",
6000 write_memory (addr
, val
, partial_len
);
6003 /* Note!!! This is NOT an else clause. Odd sized
6004 structs may go thru BOTH paths. */
6005 /* Write this portion of the argument to a general
6006 purpose register. */
6007 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
6009 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6011 /* Value may need to be sign extended, because
6012 mips_isa_regsize() != mips_abi_regsize(). */
6014 /* A non-floating-point argument being passed in a
6015 general register. If a struct or union, and if
6016 the remaining length is smaller than the register
6017 size, we have to adjust the register value on
6020 It does not seem to be necessary to do the
6021 same for integral types. */
6023 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6024 && partial_len
< MIPS64_REGSIZE
6025 && (typecode
== TYPE_CODE_STRUCT
6026 || typecode
== TYPE_CODE_UNION
))
6027 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6031 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
6033 phex (regval
, MIPS64_REGSIZE
));
6034 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6037 /* Prevent subsequent floating point arguments from
6038 being passed in floating point registers. */
6039 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
6045 /* Compute the offset into the stack at which we will
6046 copy the next parameter.
6048 In older ABIs, the caller reserved space for
6049 registers that contained arguments. This was loosely
6050 refered to as their "home". Consequently, space is
6051 always allocated. */
6053 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6057 fprintf_unfiltered (gdb_stdlog
, "\n");
6060 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6062 /* Return adjusted stack pointer. */
6066 static enum return_value_convention
6067 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6068 struct type
*type
, struct regcache
*regcache
,
6069 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6071 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6072 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6073 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6074 enum mips_fval_reg fval_reg
;
6076 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6077 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
6078 || TYPE_CODE (type
) == TYPE_CODE_UNION
6079 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
6080 return RETURN_VALUE_STRUCT_CONVENTION
;
6081 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
6083 /* A floating-point value. If reading in or copying, then we get it
6084 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6085 If writing out only, then we put it to both FP0 and GPR2. We do
6086 not support reading in with no function known, if this safety
6087 check ever triggers, then we'll have to try harder. */
6088 gdb_assert (function
|| !readbuf
);
6093 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6096 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6098 case mips_fval_both
:
6099 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6102 if (fval_reg
!= mips_fval_gpr
)
6103 mips_xfer_register (gdbarch
, regcache
,
6104 (gdbarch_num_regs (gdbarch
)
6105 + mips_regnum (gdbarch
)->fp0
),
6107 gdbarch_byte_order (gdbarch
),
6108 readbuf
, writebuf
, 0);
6109 if (fval_reg
!= mips_fval_fpr
)
6110 mips_xfer_register (gdbarch
, regcache
,
6111 gdbarch_num_regs (gdbarch
) + 2,
6113 gdbarch_byte_order (gdbarch
),
6114 readbuf
, writebuf
, 0);
6115 return RETURN_VALUE_REGISTER_CONVENTION
;
6119 /* A scalar extract each part but least-significant-byte
6123 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6124 offset
< TYPE_LENGTH (type
);
6125 offset
+= MIPS64_REGSIZE
, regnum
++)
6127 int xfer
= MIPS64_REGSIZE
;
6128 if (offset
+ xfer
> TYPE_LENGTH (type
))
6129 xfer
= TYPE_LENGTH (type
) - offset
;
6131 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6132 offset
, xfer
, regnum
);
6133 mips_xfer_register (gdbarch
, regcache
,
6134 gdbarch_num_regs (gdbarch
) + regnum
,
6135 xfer
, gdbarch_byte_order (gdbarch
),
6136 readbuf
, writebuf
, offset
);
6138 return RETURN_VALUE_REGISTER_CONVENTION
;
6142 /* Floating point register management.
6144 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6145 64bit operations, these early MIPS cpus treat fp register pairs
6146 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6147 registers and offer a compatibility mode that emulates the MIPS2 fp
6148 model. When operating in MIPS2 fp compat mode, later cpu's split
6149 double precision floats into two 32-bit chunks and store them in
6150 consecutive fp regs. To display 64-bit floats stored in this
6151 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6152 Throw in user-configurable endianness and you have a real mess.
6154 The way this works is:
6155 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6156 double-precision value will be split across two logical registers.
6157 The lower-numbered logical register will hold the low-order bits,
6158 regardless of the processor's endianness.
6159 - If we are on a 64-bit processor, and we are looking for a
6160 single-precision value, it will be in the low ordered bits
6161 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6162 save slot in memory.
6163 - If we are in 64-bit mode, everything is straightforward.
6165 Note that this code only deals with "live" registers at the top of the
6166 stack. We will attempt to deal with saved registers later, when
6167 the raw/cooked register interface is in place. (We need a general
6168 interface that can deal with dynamic saved register sizes -- fp
6169 regs could be 32 bits wide in one frame and 64 on the frame above
6172 /* Copy a 32-bit single-precision value from the current frame
6173 into rare_buffer. */
6176 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6177 gdb_byte
*rare_buffer
)
6179 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6180 int raw_size
= register_size (gdbarch
, regno
);
6181 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6183 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6184 error (_("can't read register %d (%s)"),
6185 regno
, gdbarch_register_name (gdbarch
, regno
));
6188 /* We have a 64-bit value for this register. Find the low-order
6192 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6197 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6201 memcpy (rare_buffer
, raw_buffer
, 4);
6205 /* Copy a 64-bit double-precision value from the current frame into
6206 rare_buffer. This may include getting half of it from the next
6210 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6211 gdb_byte
*rare_buffer
)
6213 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6214 int raw_size
= register_size (gdbarch
, regno
);
6216 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6218 /* We have a 64-bit value for this register, and we should use
6220 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6221 error (_("can't read register %d (%s)"),
6222 regno
, gdbarch_register_name (gdbarch
, regno
));
6226 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6228 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6229 internal_error (__FILE__
, __LINE__
,
6230 _("mips_read_fp_register_double: bad access to "
6231 "odd-numbered FP register"));
6233 /* mips_read_fp_register_single will find the correct 32 bits from
6235 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6237 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6238 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6242 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6243 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6249 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6251 { /* Do values for FP (float) regs. */
6252 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6253 gdb_byte
*raw_buffer
;
6254 double doub
, flt1
; /* Doubles extracted from raw hex data. */
6259 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6261 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6262 fprintf_filtered (file
, "%*s",
6263 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6266 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6268 struct value_print_options opts
;
6270 /* 4-byte registers: Print hex and floating. Also print even
6271 numbered registers as doubles. */
6272 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6273 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6276 get_formatted_print_options (&opts
, 'x');
6277 print_scalar_formatted (raw_buffer
,
6278 builtin_type (gdbarch
)->builtin_uint32
,
6281 fprintf_filtered (file
, " flt: ");
6283 fprintf_filtered (file
, " <invalid float> ");
6285 fprintf_filtered (file
, "%-17.9g", flt1
);
6287 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6289 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6290 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6293 fprintf_filtered (file
, " dbl: ");
6295 fprintf_filtered (file
, "<invalid double>");
6297 fprintf_filtered (file
, "%-24.17g", doub
);
6302 struct value_print_options opts
;
6304 /* Eight byte registers: print each one as hex, float and double. */
6305 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6306 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6309 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6310 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6313 get_formatted_print_options (&opts
, 'x');
6314 print_scalar_formatted (raw_buffer
,
6315 builtin_type (gdbarch
)->builtin_uint64
,
6318 fprintf_filtered (file
, " flt: ");
6320 fprintf_filtered (file
, "<invalid float>");
6322 fprintf_filtered (file
, "%-17.9g", flt1
);
6324 fprintf_filtered (file
, " dbl: ");
6326 fprintf_filtered (file
, "<invalid double>");
6328 fprintf_filtered (file
, "%-24.17g", doub
);
6333 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6336 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6337 struct value_print_options opts
;
6340 if (mips_float_register_p (gdbarch
, regnum
))
6342 mips_print_fp_register (file
, frame
, regnum
);
6346 val
= get_frame_register_value (frame
, regnum
);
6348 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6350 /* The problem with printing numeric register names (r26, etc.) is that
6351 the user can't use them on input. Probably the best solution is to
6352 fix it so that either the numeric or the funky (a2, etc.) names
6353 are accepted on input. */
6354 if (regnum
< MIPS_NUMREGS
)
6355 fprintf_filtered (file
, "(r%d): ", regnum
);
6357 fprintf_filtered (file
, ": ");
6359 get_formatted_print_options (&opts
, 'x');
6360 val_print_scalar_formatted (value_type (val
),
6361 value_contents_for_printing (val
),
6362 value_embedded_offset (val
),
6367 /* Print IEEE exception condition bits in FLAGS. */
6370 print_fpu_flags (struct ui_file
*file
, int flags
)
6372 if (flags
& (1 << 0))
6373 fputs_filtered (" inexact", file
);
6374 if (flags
& (1 << 1))
6375 fputs_filtered (" uflow", file
);
6376 if (flags
& (1 << 2))
6377 fputs_filtered (" oflow", file
);
6378 if (flags
& (1 << 3))
6379 fputs_filtered (" div0", file
);
6380 if (flags
& (1 << 4))
6381 fputs_filtered (" inval", file
);
6382 if (flags
& (1 << 5))
6383 fputs_filtered (" unimp", file
);
6384 fputc_filtered ('\n', file
);
6387 /* Print interesting information about the floating point processor
6388 (if present) or emulator. */
6391 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6392 struct frame_info
*frame
, const char *args
)
6394 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6395 enum mips_fpu_type type
= MIPS_FPU_TYPE (gdbarch
);
6399 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6400 type
= MIPS_FPU_NONE
;
6402 fprintf_filtered (file
, "fpu type: %s\n",
6403 type
== MIPS_FPU_DOUBLE
? "double-precision"
6404 : type
== MIPS_FPU_SINGLE
? "single-precision"
6407 if (type
== MIPS_FPU_NONE
)
6410 fprintf_filtered (file
, "reg size: %d bits\n",
6411 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6413 fputs_filtered ("cond :", file
);
6414 if (fcs
& (1 << 23))
6415 fputs_filtered (" 0", file
);
6416 for (i
= 1; i
<= 7; i
++)
6417 if (fcs
& (1 << (24 + i
)))
6418 fprintf_filtered (file
, " %d", i
);
6419 fputc_filtered ('\n', file
);
6421 fputs_filtered ("cause :", file
);
6422 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6423 fputs ("mask :", stdout
);
6424 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6425 fputs ("flags :", stdout
);
6426 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6428 fputs_filtered ("rounding: ", file
);
6431 case 0: fputs_filtered ("nearest\n", file
); break;
6432 case 1: fputs_filtered ("zero\n", file
); break;
6433 case 2: fputs_filtered ("+inf\n", file
); break;
6434 case 3: fputs_filtered ("-inf\n", file
); break;
6437 fputs_filtered ("flush :", file
);
6438 if (fcs
& (1 << 21))
6439 fputs_filtered (" nearest", file
);
6440 if (fcs
& (1 << 22))
6441 fputs_filtered (" override", file
);
6442 if (fcs
& (1 << 24))
6443 fputs_filtered (" zero", file
);
6444 if ((fcs
& (0xb << 21)) == 0)
6445 fputs_filtered (" no", file
);
6446 fputc_filtered ('\n', file
);
6448 fprintf_filtered (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6449 fprintf_filtered (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6450 fputc_filtered ('\n', file
);
6452 default_print_float_info (gdbarch
, file
, frame
, args
);
6455 /* Replacement for generic do_registers_info.
6456 Print regs in pretty columns. */
6459 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6462 fprintf_filtered (file
, " ");
6463 mips_print_fp_register (file
, frame
, regnum
);
6464 fprintf_filtered (file
, "\n");
6469 /* Print a row's worth of GP (int) registers, with name labels above. */
6472 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6475 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6476 /* Do values for GP (int) regs. */
6477 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
6478 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6483 /* For GP registers, we print a separate row of names above the vals. */
6484 for (col
= 0, regnum
= start_regnum
;
6485 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6486 + gdbarch_num_pseudo_regs (gdbarch
);
6489 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6490 continue; /* unused register */
6491 if (mips_float_register_p (gdbarch
, regnum
))
6492 break; /* End the row: reached FP register. */
6493 /* Large registers are handled separately. */
6494 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6497 break; /* End the row before this register. */
6499 /* Print this register on a row by itself. */
6500 mips_print_register (file
, frame
, regnum
);
6501 fprintf_filtered (file
, "\n");
6505 fprintf_filtered (file
, " ");
6506 fprintf_filtered (file
,
6507 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6508 gdbarch_register_name (gdbarch
, regnum
));
6515 /* Print the R0 to R31 names. */
6516 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6517 fprintf_filtered (file
, "\n R%-4d",
6518 start_regnum
% gdbarch_num_regs (gdbarch
));
6520 fprintf_filtered (file
, "\n ");
6522 /* Now print the values in hex, 4 or 8 to the row. */
6523 for (col
= 0, regnum
= start_regnum
;
6524 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6525 + gdbarch_num_pseudo_regs (gdbarch
);
6528 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6529 continue; /* unused register */
6530 if (mips_float_register_p (gdbarch
, regnum
))
6531 break; /* End row: reached FP register. */
6532 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6533 break; /* End row: large register. */
6535 /* OK: get the data in raw format. */
6536 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
6537 error (_("can't read register %d (%s)"),
6538 regnum
, gdbarch_register_name (gdbarch
, regnum
));
6539 /* pad small registers */
6541 byte
< (mips_abi_regsize (gdbarch
)
6542 - register_size (gdbarch
, regnum
)); byte
++)
6543 printf_filtered (" ");
6544 /* Now print the register value in hex, endian order. */
6545 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6547 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6548 byte
< register_size (gdbarch
, regnum
); byte
++)
6549 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6551 for (byte
= register_size (gdbarch
, regnum
) - 1;
6553 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6554 fprintf_filtered (file
, " ");
6557 if (col
> 0) /* ie. if we actually printed anything... */
6558 fprintf_filtered (file
, "\n");
6563 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6566 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6567 struct frame_info
*frame
, int regnum
, int all
)
6569 if (regnum
!= -1) /* Do one specified register. */
6571 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6572 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6573 error (_("Not a valid register for the current processor type"));
6575 mips_print_register (file
, frame
, regnum
);
6576 fprintf_filtered (file
, "\n");
6579 /* Do all (or most) registers. */
6581 regnum
= gdbarch_num_regs (gdbarch
);
6582 while (regnum
< gdbarch_num_regs (gdbarch
)
6583 + gdbarch_num_pseudo_regs (gdbarch
))
6585 if (mips_float_register_p (gdbarch
, regnum
))
6587 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6588 regnum
= print_fp_register_row (file
, frame
, regnum
);
6590 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6593 regnum
= print_gp_register_row (file
, frame
, regnum
);
6599 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6600 struct frame_info
*frame
)
6602 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6603 CORE_ADDR pc
= get_frame_pc (frame
);
6604 struct address_space
*aspace
;
6610 if ((mips_pc_is_mips (pc
)
6611 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6612 || (mips_pc_is_micromips (gdbarch
, pc
)
6613 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6614 || (mips_pc_is_mips16 (gdbarch
, pc
)
6615 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6618 isa
= mips_pc_isa (gdbarch
, pc
);
6619 /* _has_delay_slot above will have validated the read. */
6620 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6621 size
= mips_insn_size (isa
, insn
);
6622 aspace
= get_frame_address_space (frame
);
6623 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6626 /* To skip prologues, I use this predicate. Returns either PC itself
6627 if the code at PC does not look like a function prologue; otherwise
6628 returns an address that (if we're lucky) follows the prologue. If
6629 LENIENT, then we must skip everything which is involved in setting
6630 up the frame (it's OK to skip more, just so long as we don't skip
6631 anything which might clobber the registers which are being saved.
6632 We must skip more in the case where part of the prologue is in the
6633 delay slot of a non-prologue instruction). */
6636 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6639 CORE_ADDR func_addr
;
6641 /* See if we can determine the end of the prologue via the symbol table.
6642 If so, then return either PC, or the PC after the prologue, whichever
6644 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6646 CORE_ADDR post_prologue_pc
6647 = skip_prologue_using_sal (gdbarch
, func_addr
);
6648 if (post_prologue_pc
!= 0)
6649 return std::max (pc
, post_prologue_pc
);
6652 /* Can't determine prologue from the symbol table, need to examine
6655 /* Find an upper limit on the function prologue using the debug
6656 information. If the debug information could not be used to provide
6657 that bound, then use an arbitrary large number as the upper bound. */
6658 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6660 limit_pc
= pc
+ 100; /* Magic. */
6662 if (mips_pc_is_mips16 (gdbarch
, pc
))
6663 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6664 else if (mips_pc_is_micromips (gdbarch
, pc
))
6665 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6667 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6670 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6671 This is a helper function for mips_stack_frame_destroyed_p. */
6674 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6676 CORE_ADDR func_addr
= 0, func_end
= 0;
6678 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6680 /* The MIPS epilogue is max. 12 bytes long. */
6681 CORE_ADDR addr
= func_end
- 12;
6683 if (addr
< func_addr
+ 4)
6684 addr
= func_addr
+ 4;
6688 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6690 unsigned long high_word
;
6693 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6694 high_word
= (inst
>> 16) & 0xffff;
6696 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6697 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6698 && inst
!= 0x03e00008 /* jr $ra */
6699 && inst
!= 0x00000000) /* nop */
6709 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6710 This is a helper function for mips_stack_frame_destroyed_p. */
6713 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6715 CORE_ADDR func_addr
= 0;
6716 CORE_ADDR func_end
= 0;
6724 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6727 /* The microMIPS epilogue is max. 12 bytes long. */
6728 addr
= func_end
- 12;
6730 if (addr
< func_addr
+ 2)
6731 addr
= func_addr
+ 2;
6735 for (; pc
< func_end
; pc
+= loc
)
6738 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6739 loc
+= MIPS_INSN16_SIZE
;
6740 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6742 /* 32-bit instructions. */
6743 case 2 * MIPS_INSN16_SIZE
:
6745 insn
|= mips_fetch_instruction (gdbarch
,
6746 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6747 loc
+= MIPS_INSN16_SIZE
;
6748 switch (micromips_op (insn
>> 16))
6750 case 0xc: /* ADDIU: bits 001100 */
6751 case 0x17: /* DADDIU: bits 010111 */
6752 sreg
= b0s5_reg (insn
>> 16);
6753 dreg
= b5s5_reg (insn
>> 16);
6754 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6755 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6756 /* (D)ADDIU $sp, imm */
6766 /* 16-bit instructions. */
6767 case MIPS_INSN16_SIZE
:
6768 switch (micromips_op (insn
))
6770 case 0x3: /* MOVE: bits 000011 */
6771 sreg
= b0s5_reg (insn
);
6772 dreg
= b5s5_reg (insn
);
6773 if (sreg
== 0 && dreg
== 0)
6774 /* MOVE $zero, $zero aka NOP */
6778 case 0x11: /* POOL16C: bits 010001 */
6779 if (b5s5_op (insn
) == 0x18
6780 /* JRADDIUSP: bits 010011 11000 */
6781 || (b5s5_op (insn
) == 0xd
6782 /* JRC: bits 010011 01101 */
6783 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6788 case 0x13: /* POOL16D: bits 010011 */
6789 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6790 if ((insn
& 0x1) == 0x1
6791 /* ADDIUSP: bits 010011 1 */
6805 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6806 This is a helper function for mips_stack_frame_destroyed_p. */
6809 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6811 CORE_ADDR func_addr
= 0, func_end
= 0;
6813 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6815 /* The MIPS epilogue is max. 12 bytes long. */
6816 CORE_ADDR addr
= func_end
- 12;
6818 if (addr
< func_addr
+ 4)
6819 addr
= func_addr
+ 4;
6823 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6825 unsigned short inst
;
6827 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6829 if ((inst
& 0xf800) == 0xf000) /* extend */
6832 if (inst
!= 0x6300 /* addiu $sp,offset */
6833 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6834 && inst
!= 0xe820 /* jr $ra */
6835 && inst
!= 0xe8a0 /* jrc $ra */
6836 && inst
!= 0x6500) /* nop */
6846 /* Implement the stack_frame_destroyed_p gdbarch method.
6848 The epilogue is defined here as the area at the end of a function,
6849 after an instruction which destroys the function's stack frame. */
6852 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6854 if (mips_pc_is_mips16 (gdbarch
, pc
))
6855 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6856 else if (mips_pc_is_micromips (gdbarch
, pc
))
6857 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6859 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6862 /* Root of all "set mips "/"show mips " commands. This will eventually be
6863 used for all MIPS-specific commands. */
6866 show_mips_command (char *args
, int from_tty
)
6868 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6872 set_mips_command (char *args
, int from_tty
)
6875 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6876 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6879 /* Commands to show/set the MIPS FPU type. */
6882 show_mipsfpu_command (char *args
, int from_tty
)
6886 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6889 ("The MIPS floating-point coprocessor is unknown "
6890 "because the current architecture is not MIPS.\n");
6894 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6896 case MIPS_FPU_SINGLE
:
6897 fpu
= "single-precision";
6899 case MIPS_FPU_DOUBLE
:
6900 fpu
= "double-precision";
6903 fpu
= "absent (none)";
6906 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6908 if (mips_fpu_type_auto
)
6909 printf_unfiltered ("The MIPS floating-point coprocessor "
6910 "is set automatically (currently %s)\n",
6914 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6919 set_mipsfpu_command (char *args
, int from_tty
)
6921 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6922 "\"single\",\"none\" or \"auto\".\n");
6923 show_mipsfpu_command (args
, from_tty
);
6927 set_mipsfpu_single_command (char *args
, int from_tty
)
6929 struct gdbarch_info info
;
6930 gdbarch_info_init (&info
);
6931 mips_fpu_type
= MIPS_FPU_SINGLE
;
6932 mips_fpu_type_auto
= 0;
6933 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6934 instead of relying on globals. Doing that would let generic code
6935 handle the search for this specific architecture. */
6936 if (!gdbarch_update_p (info
))
6937 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6941 set_mipsfpu_double_command (char *args
, int from_tty
)
6943 struct gdbarch_info info
;
6944 gdbarch_info_init (&info
);
6945 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6946 mips_fpu_type_auto
= 0;
6947 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6948 instead of relying on globals. Doing that would let generic code
6949 handle the search for this specific architecture. */
6950 if (!gdbarch_update_p (info
))
6951 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6955 set_mipsfpu_none_command (char *args
, int from_tty
)
6957 struct gdbarch_info info
;
6958 gdbarch_info_init (&info
);
6959 mips_fpu_type
= MIPS_FPU_NONE
;
6960 mips_fpu_type_auto
= 0;
6961 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6962 instead of relying on globals. Doing that would let generic code
6963 handle the search for this specific architecture. */
6964 if (!gdbarch_update_p (info
))
6965 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6969 set_mipsfpu_auto_command (char *args
, int from_tty
)
6971 mips_fpu_type_auto
= 1;
6974 /* Just like reinit_frame_cache, but with the right arguments to be
6975 callable as an sfunc. */
6978 reinit_frame_cache_sfunc (char *args
, int from_tty
,
6979 struct cmd_list_element
*c
)
6981 reinit_frame_cache ();
6985 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6987 struct gdbarch
*gdbarch
= (struct gdbarch
*) info
->application_data
;
6989 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6990 disassembler needs to be able to locally determine the ISA, and
6991 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6993 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6994 info
->mach
= bfd_mach_mips16
;
6995 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6996 info
->mach
= bfd_mach_mips_micromips
;
6998 /* Round down the instruction address to the appropriate boundary. */
6999 memaddr
&= (info
->mach
== bfd_mach_mips16
7000 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7002 /* Set the disassembler options. */
7003 if (!info
->disassembler_options
)
7004 /* This string is not recognized explicitly by the disassembler,
7005 but it tells the disassembler to not try to guess the ABI from
7006 the bfd elf headers, such that, if the user overrides the ABI
7007 of a program linked as NewABI, the disassembly will follow the
7008 register naming conventions specified by the user. */
7009 info
->disassembler_options
= "gpr-names=32";
7011 /* Call the appropriate disassembler based on the target endian-ness. */
7012 if (info
->endian
== BFD_ENDIAN_BIG
)
7013 return print_insn_big_mips (memaddr
, info
);
7015 return print_insn_little_mips (memaddr
, info
);
7019 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
7021 /* Set up the disassembler info, so that we get the right
7022 register names from libopcodes. */
7023 info
->disassembler_options
= "gpr-names=n32";
7024 info
->flavour
= bfd_target_elf_flavour
;
7026 return gdb_print_insn_mips (memaddr
, info
);
7030 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
7032 /* Set up the disassembler info, so that we get the right
7033 register names from libopcodes. */
7034 info
->disassembler_options
= "gpr-names=64";
7035 info
->flavour
= bfd_target_elf_flavour
;
7037 return gdb_print_insn_mips (memaddr
, info
);
7040 /* This function implements gdbarch_breakpoint_from_pc. It uses the
7041 program counter value to determine whether a 16- or 32-bit breakpoint
7042 should be used. It returns a pointer to a string of bytes that encode a
7043 breakpoint instruction, stores the length of the string to *lenptr, and
7044 adjusts pc (if necessary) to point to the actual memory location where
7045 the breakpoint should be inserted. */
7047 static const gdb_byte
*
7048 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
7049 CORE_ADDR
*pcptr
, int *lenptr
)
7051 CORE_ADDR pc
= *pcptr
;
7053 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
7055 if (mips_pc_is_mips16 (gdbarch
, pc
))
7057 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7058 *pcptr
= unmake_compact_addr (pc
);
7059 *lenptr
= sizeof (mips16_big_breakpoint
);
7060 return mips16_big_breakpoint
;
7062 else if (mips_pc_is_micromips (gdbarch
, pc
))
7064 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7065 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7070 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &err
);
7071 size
= err
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
);
7072 *pcptr
= unmake_compact_addr (pc
);
7074 return (size
== 2) ? micromips16_big_breakpoint
7075 : micromips32_big_breakpoint
;
7079 /* The IDT board uses an unusual breakpoint value, and
7080 sometimes gets confused when it sees the usual MIPS
7081 breakpoint instruction. */
7082 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7083 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
7084 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
7085 /* Likewise, IRIX appears to expect a different breakpoint,
7086 although this is not apparent until you try to use pthreads. */
7087 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
7089 *lenptr
= sizeof (big_breakpoint
);
7091 if (strcmp (target_shortname
, "mips") == 0)
7092 return idt_big_breakpoint
;
7093 else if (strcmp (target_shortname
, "ddb") == 0
7094 || strcmp (target_shortname
, "pmon") == 0
7095 || strcmp (target_shortname
, "lsi") == 0)
7096 return pmon_big_breakpoint
;
7097 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
7098 return irix_big_breakpoint
;
7100 return big_breakpoint
;
7105 if (mips_pc_is_mips16 (gdbarch
, pc
))
7107 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7108 *pcptr
= unmake_compact_addr (pc
);
7109 *lenptr
= sizeof (mips16_little_breakpoint
);
7110 return mips16_little_breakpoint
;
7112 else if (mips_pc_is_micromips (gdbarch
, pc
))
7114 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7115 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7120 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &err
);
7121 size
= err
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
);
7122 *pcptr
= unmake_compact_addr (pc
);
7124 return (size
== 2) ? micromips16_little_breakpoint
7125 : micromips32_little_breakpoint
;
7129 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7130 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
7131 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
7133 *lenptr
= sizeof (little_breakpoint
);
7135 if (strcmp (target_shortname
, "mips") == 0)
7136 return idt_little_breakpoint
;
7137 else if (strcmp (target_shortname
, "ddb") == 0
7138 || strcmp (target_shortname
, "pmon") == 0
7139 || strcmp (target_shortname
, "lsi") == 0)
7140 return pmon_little_breakpoint
;
7142 return little_breakpoint
;
7147 /* Determine the remote breakpoint kind suitable for the PC. The following
7150 * 2 -- 16-bit MIPS16 mode breakpoint,
7152 * 3 -- 16-bit microMIPS mode breakpoint,
7154 * 4 -- 32-bit standard MIPS mode breakpoint,
7156 * 5 -- 32-bit microMIPS mode breakpoint. */
7159 mips_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
7162 CORE_ADDR pc
= *pcptr
;
7164 if (mips_pc_is_mips16 (gdbarch
, pc
))
7166 *pcptr
= unmake_compact_addr (pc
);
7169 else if (mips_pc_is_micromips (gdbarch
, pc
))
7175 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7176 size
= status
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
7177 *pcptr
= unmake_compact_addr (pc
);
7178 *kindptr
= size
| 1;
7184 /* Return non-zero if the standard MIPS instruction INST has a branch
7185 delay slot (i.e. it is a jump or branch instruction). This function
7186 is based on mips32_next_pc. */
7189 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7195 op
= itype_op (inst
);
7196 if ((inst
& 0xe0000000) != 0)
7198 rs
= itype_rs (inst
);
7199 rt
= itype_rt (inst
);
7200 return (is_octeon_bbit_op (op
, gdbarch
)
7201 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7202 || op
== 29 /* JALX: bits 011101 */
7205 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7206 || (rs
== 9 && (rt
& 0x2) == 0)
7207 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7208 || (rs
== 10 && (rt
& 0x2) == 0))));
7209 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7212 switch (op
& 0x07) /* extract bits 28,27,26 */
7214 case 0: /* SPECIAL */
7215 op
= rtype_funct (inst
);
7216 return (op
== 8 /* JR */
7217 || op
== 9); /* JALR */
7218 break; /* end SPECIAL */
7219 case 1: /* REGIMM */
7220 rs
= itype_rs (inst
);
7221 rt
= itype_rt (inst
); /* branch condition */
7222 return ((rt
& 0xc) == 0
7223 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7224 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7225 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7226 /* BPOSGE32, BPOSGE64: bits 1110x */
7227 break; /* end REGIMM */
7228 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7234 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7235 delay slot (i.e. it is a jump or branch instruction). */
7238 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7243 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7247 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7250 /* Return non-zero if the microMIPS instruction INSN, comprising the
7251 16-bit major opcode word in the high 16 bits and any second word
7252 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7253 jump or branch instruction). The instruction must be 32-bit if
7254 MUSTBE32 is set or can be any instruction otherwise. */
7257 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7259 ULONGEST major
= insn
>> 16;
7261 switch (micromips_op (major
))
7263 /* 16-bit instructions. */
7264 case 0x33: /* B16: bits 110011 */
7265 case 0x2b: /* BNEZ16: bits 101011 */
7266 case 0x23: /* BEQZ16: bits 100011 */
7268 case 0x11: /* POOL16C: bits 010001 */
7270 && ((b5s5_op (major
) == 0xc
7271 /* JR16: bits 010001 01100 */
7272 || (b5s5_op (major
) & 0x1e) == 0xe)));
7273 /* JALR16, JALRS16: bits 010001 0111x */
7274 /* 32-bit instructions. */
7275 case 0x3d: /* JAL: bits 111101 */
7276 case 0x3c: /* JALX: bits 111100 */
7277 case 0x35: /* J: bits 110101 */
7278 case 0x2d: /* BNE: bits 101101 */
7279 case 0x25: /* BEQ: bits 100101 */
7280 case 0x1d: /* JALS: bits 011101 */
7282 case 0x10: /* POOL32I: bits 010000 */
7283 return ((b5s5_op (major
) & 0x1c) == 0x0
7284 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7285 || (b5s5_op (major
) & 0x1d) == 0x4
7286 /* BLEZ, BGTZ: bits 010000 001x0 */
7287 || (b5s5_op (major
) & 0x1d) == 0x11
7288 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7289 || ((b5s5_op (major
) & 0x1e) == 0x14
7290 && (major
& 0x3) == 0x0)
7291 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7292 || (b5s5_op (major
) & 0x1e) == 0x1a
7293 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7294 || ((b5s5_op (major
) & 0x1e) == 0x1c
7295 && (major
& 0x3) == 0x0)
7296 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7297 || ((b5s5_op (major
) & 0x1c) == 0x1c
7298 && (major
& 0x3) == 0x1));
7299 /* BC1ANY*: bits 010000 111xx xxx01 */
7300 case 0x0: /* POOL32A: bits 000000 */
7301 return (b0s6_op (insn
) == 0x3c
7302 /* POOL32Axf: bits 000000 ... 111100 */
7303 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7304 /* JALR, JALR.HB: 000000 000x111100 111100 */
7305 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7311 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7312 slot (i.e. it is a non-compact jump instruction). The instruction
7313 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7316 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7317 CORE_ADDR addr
, int mustbe32
)
7323 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7326 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7328 if (size
== 2 * MIPS_INSN16_SIZE
)
7330 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7335 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7338 /* Return non-zero if the MIPS16 instruction INST, which must be
7339 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7340 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7341 instruction). This function is based on mips16_next_pc. */
7344 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7346 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7348 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7351 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7352 slot (i.e. it is a non-compact jump instruction). The instruction
7353 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7356 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7357 CORE_ADDR addr
, int mustbe32
)
7359 unsigned short insn
;
7362 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7366 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7369 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7370 This assumes KSSEG exists. */
7373 mips_segment_boundary (CORE_ADDR bpaddr
)
7375 CORE_ADDR mask
= CORE_ADDR_MAX
;
7378 if (sizeof (CORE_ADDR
) == 8)
7379 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7380 a compiler warning produced where CORE_ADDR is a 32-bit type even
7381 though in that case this is dead code). */
7382 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7385 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7386 segsize
= 29; /* 32-bit compatibility segment */
7388 segsize
= 62; /* xkseg */
7390 case 2: /* xkphys */
7393 default: /* xksseg (1), xkuseg/kuseg (0) */
7397 else if (bpaddr
& 0x80000000) /* kernel segment */
7400 segsize
= 31; /* user segment */
7402 return bpaddr
& mask
;
7405 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7406 it backwards if necessary. Return the address of the new location. */
7409 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7411 CORE_ADDR prev_addr
;
7413 CORE_ADDR func_addr
;
7415 /* If a breakpoint is set on the instruction in a branch delay slot,
7416 GDB gets confused. When the breakpoint is hit, the PC isn't on
7417 the instruction in the branch delay slot, the PC will point to
7418 the branch instruction. Since the PC doesn't match any known
7419 breakpoints, GDB reports a trap exception.
7421 There are two possible fixes for this problem.
7423 1) When the breakpoint gets hit, see if the BD bit is set in the
7424 Cause register (which indicates the last exception occurred in a
7425 branch delay slot). If the BD bit is set, fix the PC to point to
7426 the instruction in the branch delay slot.
7428 2) When the user sets the breakpoint, don't allow him to set the
7429 breakpoint on the instruction in the branch delay slot. Instead
7430 move the breakpoint to the branch instruction (which will have
7433 The problem with the first solution is that if the user then
7434 single-steps the processor, the branch instruction will get
7435 skipped (since GDB thinks the PC is on the instruction in the
7438 So, we'll use the second solution. To do this we need to know if
7439 the instruction we're trying to set the breakpoint on is in the
7440 branch delay slot. */
7442 boundary
= mips_segment_boundary (bpaddr
);
7444 /* Make sure we don't scan back before the beginning of the current
7445 function, since we may fetch constant data or insns that look like
7446 a jump. Of course we might do that anyway if the compiler has
7447 moved constants inline. :-( */
7448 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7449 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7450 boundary
= func_addr
;
7452 if (mips_pc_is_mips (bpaddr
))
7454 if (bpaddr
== boundary
)
7457 /* If the previous instruction has a branch delay slot, we have
7458 to move the breakpoint to the branch instruction. */
7459 prev_addr
= bpaddr
- 4;
7460 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7465 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7466 CORE_ADDR addr
, jmpaddr
;
7469 boundary
= unmake_compact_addr (boundary
);
7471 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7472 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7473 so try for that first, then try the 2 byte JALR/JR.
7474 The microMIPS ASE has a whole range of jumps and branches
7475 with delay slots, some of which take 4 bytes and some take
7476 2 bytes, so the idea is the same.
7477 FIXME: We have to assume that bpaddr is not the second half
7478 of an extended instruction. */
7479 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7480 ? micromips_insn_at_pc_has_delay_slot
7481 : mips16_insn_at_pc_has_delay_slot
);
7485 for (i
= 1; i
< 4; i
++)
7487 if (unmake_compact_addr (addr
) == boundary
)
7489 addr
-= MIPS_INSN16_SIZE
;
7490 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7491 /* Looks like a JR/JALR at [target-1], but it could be
7492 the second word of a previous JAL/JALX, so record it
7493 and check back one more. */
7495 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7498 /* Looks like a JAL/JALX at [target-2], but it could also
7499 be the second word of a previous JAL/JALX, record it,
7500 and check back one more. */
7503 /* Looks like a JAL/JALX at [target-3], so any previously
7504 recorded JAL/JALX or JR/JALR must be wrong, because:
7507 -2: JAL-ext (can't be JAL/JALX)
7508 -1: bdslot (can't be JR/JALR)
7511 Of course it could be another JAL-ext which looks
7512 like a JAL, but in that case we'd have broken out
7513 of this loop at [target-2]:
7517 -2: bdslot (can't be jmp)
7524 /* Not a jump instruction: if we're at [target-1] this
7525 could be the second word of a JAL/JALX, so continue;
7526 otherwise we're done. */
7539 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7540 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7543 mips_is_stub_suffix (const char *suffix
, int zero
)
7548 return zero
&& suffix
[1] == '\0';
7550 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7555 return suffix
[1] == '\0';
7561 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7562 call stubs, one of sf, df, sc, or dc. */
7565 mips_is_stub_mode (const char *mode
)
7567 return ((mode
[0] == 's' || mode
[0] == 'd')
7568 && (mode
[1] == 'f' || mode
[1] == 'c'));
7571 /* Code at PC is a compiler-generated stub. Such a stub for a function
7572 bar might have a name like __fn_stub_bar, and might look like this:
7579 followed by (or interspersed with):
7586 addiu $25, $25, %lo(bar)
7589 ($1 may be used in old code; for robustness we accept any register)
7592 lui $28, %hi(_gp_disp)
7593 addiu $28, $28, %lo(_gp_disp)
7596 addiu $25, $25, %lo(bar)
7599 In the case of a __call_stub_bar stub, the sequence to set up
7600 arguments might look like this:
7607 followed by (or interspersed with) one of the jump sequences above.
7609 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7610 of J or JR, respectively, followed by:
7616 We are at the beginning of the stub here, and scan down and extract
7617 the target address from the jump immediate instruction or, if a jump
7618 register instruction is used, from the register referred. Return
7619 the value of PC calculated or 0 if inconclusive.
7621 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7624 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7626 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7627 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7628 int addrreg
= MIPS_ZERO_REGNUM
;
7629 CORE_ADDR start_pc
= pc
;
7630 CORE_ADDR target_pc
= 0;
7637 status
== 0 && target_pc
== 0 && i
< 20;
7638 i
++, pc
+= MIPS_INSN32_SIZE
)
7640 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7646 switch (itype_op (inst
))
7648 case 0: /* SPECIAL */
7649 switch (rtype_funct (inst
))
7653 rs
= rtype_rs (inst
);
7654 if (rs
== MIPS_GP_REGNUM
)
7655 target_pc
= gp
; /* Hmm... */
7656 else if (rs
== addrreg
)
7660 case 0x21: /* ADDU */
7661 rt
= rtype_rt (inst
);
7662 rs
= rtype_rs (inst
);
7663 rd
= rtype_rd (inst
);
7664 if (rd
== MIPS_GP_REGNUM
7665 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7666 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7674 target_pc
= jtype_target (inst
) << 2;
7675 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7679 rt
= itype_rt (inst
);
7680 rs
= itype_rs (inst
);
7683 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7684 if (rt
== MIPS_GP_REGNUM
)
7686 else if (rt
== addrreg
)
7692 rt
= itype_rt (inst
);
7693 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7694 if (rt
== MIPS_GP_REGNUM
)
7696 else if (rt
!= MIPS_ZERO_REGNUM
)
7704 rt
= itype_rt (inst
);
7705 rs
= itype_rs (inst
);
7706 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7707 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7711 memset (buf
, 0, sizeof (buf
));
7712 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7714 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7723 /* If PC is in a MIPS16 call or return stub, return the address of the
7724 target PC, which is either the callee or the caller. There are several
7725 cases which must be handled:
7727 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7728 and the target PC is in $31 ($ra).
7729 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7730 and the target PC is in $2.
7731 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7732 i.e. before the JALR instruction, this is effectively a call stub
7733 and the target PC is in $2. Otherwise this is effectively
7734 a return stub and the target PC is in $18.
7735 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7736 JAL or JALR instruction, this is effectively a call stub and the
7737 target PC is buried in the instruction stream. Otherwise this
7738 is effectively a return stub and the target PC is in $18.
7739 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7740 stub and the target PC is buried in the instruction stream.
7742 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7743 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7747 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7749 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7750 CORE_ADDR start_addr
;
7754 /* Find the starting address and name of the function containing the PC. */
7755 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7758 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7759 and the target PC is in $31 ($ra). */
7760 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7761 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7762 && mips_is_stub_mode (name
+ prefixlen
)
7763 && name
[prefixlen
+ 2] == '\0')
7764 return get_frame_register_signed
7765 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7767 /* If the PC is in __mips16_call_stub_*, this is one of the call
7768 call/return stubs. */
7769 prefixlen
= strlen (mips_str_mips16_call_stub
);
7770 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7772 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7773 and the target PC is in $2. */
7774 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7775 return get_frame_register_signed
7776 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7778 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7779 i.e. before the JALR instruction, this is effectively a call stub
7780 and the target PC is in $2. Otherwise this is effectively
7781 a return stub and the target PC is in $18. */
7782 else if (mips_is_stub_mode (name
+ prefixlen
)
7783 && name
[prefixlen
+ 2] == '_'
7784 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7786 if (pc
== start_addr
)
7787 /* This is the 'call' part of a call stub. The return
7788 address is in $2. */
7789 return get_frame_register_signed
7790 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7792 /* This is the 'return' part of a call stub. The return
7793 address is in $18. */
7794 return get_frame_register_signed
7795 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7798 return 0; /* Not a stub. */
7801 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7802 compiler-generated call or call/return stubs. */
7803 if (startswith (name
, mips_str_fn_stub
)
7804 || startswith (name
, mips_str_call_stub
))
7806 if (pc
== start_addr
)
7807 /* This is the 'call' part of a call stub. Call this helper
7808 to scan through this code for interesting instructions
7809 and determine the final PC. */
7810 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7812 /* This is the 'return' part of a call stub. The return address
7814 return get_frame_register_signed
7815 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7818 return 0; /* Not a stub. */
7821 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7822 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7825 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7827 CORE_ADDR start_addr
;
7830 /* Find the starting address of the function containing the PC. */
7831 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7834 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7835 the start, i.e. after the JALR instruction, this is effectively
7837 prefixlen
= strlen (mips_str_mips16_call_stub
);
7838 if (pc
!= start_addr
7839 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7840 && mips_is_stub_mode (name
+ prefixlen
)
7841 && name
[prefixlen
+ 2] == '_'
7842 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7845 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7846 the JAL or JALR instruction, this is effectively a return stub. */
7847 prefixlen
= strlen (mips_str_call_fp_stub
);
7848 if (pc
!= start_addr
7849 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7852 /* Consume the .pic. prefix of any PIC stub, this function must return
7853 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7854 or the call stub path will trigger in handle_inferior_event causing
7856 prefixlen
= strlen (mips_str_pic
);
7857 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7860 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7861 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7862 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7863 && mips_is_stub_mode (name
+ prefixlen
)
7864 && name
[prefixlen
+ 2] == '\0')
7867 return 0; /* Not a stub. */
7870 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7871 PC of the stub target. The stub just loads $t9 and jumps to it,
7872 so that $t9 has the correct value at function entry. */
7875 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7877 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7878 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7879 struct bound_minimal_symbol msym
;
7881 gdb_byte stub_code
[16];
7882 int32_t stub_words
[4];
7884 /* The stub for foo is named ".pic.foo", and is either two
7885 instructions inserted before foo or a three instruction sequence
7886 which jumps to foo. */
7887 msym
= lookup_minimal_symbol_by_pc (pc
);
7888 if (msym
.minsym
== NULL
7889 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7890 || MSYMBOL_LINKAGE_NAME (msym
.minsym
) == NULL
7891 || !startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
7894 /* A two-instruction header. */
7895 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7898 /* A three-instruction (plus delay slot) trampoline. */
7899 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7901 if (target_read_memory (pc
, stub_code
, 16) != 0)
7903 for (i
= 0; i
< 4; i
++)
7904 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7907 /* A stub contains these instructions:
7910 addiu t9, t9, %lo(target)
7913 This works even for N64, since stubs are only generated with
7915 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7916 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7917 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7918 && stub_words
[3] == 0x00000000)
7919 return ((((stub_words
[0] & 0x0000ffff) << 16)
7920 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7923 /* Not a recognized stub. */
7928 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7930 CORE_ADDR requested_pc
= pc
;
7931 CORE_ADDR target_pc
;
7938 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7942 new_pc
= find_solib_trampoline_target (frame
, pc
);
7946 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7950 while (pc
!= target_pc
);
7952 return pc
!= requested_pc
? pc
: 0;
7955 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7956 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7959 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7962 if (num
>= 0 && num
< 32)
7964 else if (num
>= 38 && num
< 70)
7965 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7967 regnum
= mips_regnum (gdbarch
)->hi
;
7969 regnum
= mips_regnum (gdbarch
)->lo
;
7970 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7971 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7974 return gdbarch_num_regs (gdbarch
) + regnum
;
7978 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7979 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7982 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7985 if (num
>= 0 && num
< 32)
7987 else if (num
>= 32 && num
< 64)
7988 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7990 regnum
= mips_regnum (gdbarch
)->hi
;
7992 regnum
= mips_regnum (gdbarch
)->lo
;
7993 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7994 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7997 return gdbarch_num_regs (gdbarch
) + regnum
;
8001 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
8003 /* Only makes sense to supply raw registers. */
8004 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
8005 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
8006 decide if it is valid. Should instead define a standard sim/gdb
8007 register numbering scheme. */
8008 if (gdbarch_register_name (gdbarch
,
8009 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
8010 && gdbarch_register_name (gdbarch
,
8011 gdbarch_num_regs (gdbarch
)
8012 + regnum
)[0] != '\0')
8015 return LEGACY_SIM_REGNO_IGNORE
;
8019 /* Convert an integer into an address. Extracting the value signed
8020 guarantees a correctly sign extended address. */
8023 mips_integer_to_address (struct gdbarch
*gdbarch
,
8024 struct type
*type
, const gdb_byte
*buf
)
8026 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8027 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
8030 /* Dummy virtual frame pointer method. This is no more or less accurate
8031 than most other architectures; we just need to be explicit about it,
8032 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
8033 an assertion failure. */
8036 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
8037 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
8039 *reg
= MIPS_SP_REGNUM
;
8044 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
8046 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
8047 const char *name
= bfd_get_section_name (abfd
, sect
);
8049 if (*abip
!= MIPS_ABI_UNKNOWN
)
8052 if (!startswith (name
, ".mdebug."))
8055 if (strcmp (name
, ".mdebug.abi32") == 0)
8056 *abip
= MIPS_ABI_O32
;
8057 else if (strcmp (name
, ".mdebug.abiN32") == 0)
8058 *abip
= MIPS_ABI_N32
;
8059 else if (strcmp (name
, ".mdebug.abi64") == 0)
8060 *abip
= MIPS_ABI_N64
;
8061 else if (strcmp (name
, ".mdebug.abiO64") == 0)
8062 *abip
= MIPS_ABI_O64
;
8063 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8064 *abip
= MIPS_ABI_EABI32
;
8065 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8066 *abip
= MIPS_ABI_EABI64
;
8068 warning (_("unsupported ABI %s."), name
+ 8);
8072 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8074 int *lbp
= (int *) obj
;
8075 const char *name
= bfd_get_section_name (abfd
, sect
);
8077 if (startswith (name
, ".gcc_compiled_long32"))
8079 else if (startswith (name
, ".gcc_compiled_long64"))
8081 else if (startswith (name
, ".gcc_compiled_long"))
8082 warning (_("unrecognized .gcc_compiled_longXX"));
8085 static enum mips_abi
8086 global_mips_abi (void)
8090 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8091 if (mips_abi_strings
[i
] == mips_abi_string
)
8092 return (enum mips_abi
) i
;
8094 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8097 /* Return the default compressed instruction set, either of MIPS16
8098 or microMIPS, selected when none could have been determined from
8099 the ELF header of the binary being executed (or no binary has been
8102 static enum mips_isa
8103 global_mips_compression (void)
8107 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8108 if (mips_compression_strings
[i
] == mips_compression_string
)
8109 return (enum mips_isa
) i
;
8111 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8115 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8117 /* If the size matches the set of 32-bit or 64-bit integer registers,
8118 assume that's what we've got. */
8119 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8120 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8122 /* If the size matches the full set of registers GDB traditionally
8123 knows about, including floating point, for either 32-bit or
8124 64-bit, assume that's what we've got. */
8125 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8126 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8128 /* Otherwise we don't have a useful guess. */
8131 static struct value
*
8132 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8134 const int *reg_p
= (const int *) baton
;
8135 return value_of_register (*reg_p
, frame
);
8138 static struct gdbarch
*
8139 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8141 struct gdbarch
*gdbarch
;
8142 struct gdbarch_tdep
*tdep
;
8144 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8146 enum mips_fpu_type fpu_type
;
8147 struct tdesc_arch_data
*tdesc_data
= NULL
;
8148 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8149 const char **reg_names
;
8150 struct mips_regnum mips_regnum
, *regnum
;
8151 enum mips_isa mips_isa
;
8155 /* Fill in the OS dependent register numbers and names. */
8156 if (info
.osabi
== GDB_OSABI_IRIX
)
8158 mips_regnum
.fp0
= 32;
8159 mips_regnum
.pc
= 64;
8160 mips_regnum
.cause
= 65;
8161 mips_regnum
.badvaddr
= 66;
8162 mips_regnum
.hi
= 67;
8163 mips_regnum
.lo
= 68;
8164 mips_regnum
.fp_control_status
= 69;
8165 mips_regnum
.fp_implementation_revision
= 70;
8166 mips_regnum
.dspacc
= dspacc
= -1;
8167 mips_regnum
.dspctl
= dspctl
= -1;
8169 reg_names
= mips_irix_reg_names
;
8171 else if (info
.osabi
== GDB_OSABI_LINUX
)
8173 mips_regnum
.fp0
= 38;
8174 mips_regnum
.pc
= 37;
8175 mips_regnum
.cause
= 36;
8176 mips_regnum
.badvaddr
= 35;
8177 mips_regnum
.hi
= 34;
8178 mips_regnum
.lo
= 33;
8179 mips_regnum
.fp_control_status
= 70;
8180 mips_regnum
.fp_implementation_revision
= 71;
8181 mips_regnum
.dspacc
= -1;
8182 mips_regnum
.dspctl
= -1;
8186 reg_names
= mips_linux_reg_names
;
8190 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8191 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8192 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8193 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8194 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8195 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8196 mips_regnum
.fp_control_status
= 70;
8197 mips_regnum
.fp_implementation_revision
= 71;
8198 mips_regnum
.dspacc
= dspacc
= -1;
8199 mips_regnum
.dspctl
= dspctl
= -1;
8200 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8201 if (info
.bfd_arch_info
!= NULL
8202 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8203 reg_names
= mips_tx39_reg_names
;
8205 reg_names
= mips_generic_reg_names
;
8208 /* Check any target description for validity. */
8209 if (tdesc_has_registers (info
.target_desc
))
8211 static const char *const mips_gprs
[] = {
8212 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8213 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8214 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8215 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8217 static const char *const mips_fprs
[] = {
8218 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8219 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8220 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8221 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8224 const struct tdesc_feature
*feature
;
8227 feature
= tdesc_find_feature (info
.target_desc
,
8228 "org.gnu.gdb.mips.cpu");
8229 if (feature
== NULL
)
8232 tdesc_data
= tdesc_data_alloc ();
8235 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8236 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
8240 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8241 mips_regnum
.lo
, "lo");
8242 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8243 mips_regnum
.hi
, "hi");
8244 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8245 mips_regnum
.pc
, "pc");
8249 tdesc_data_cleanup (tdesc_data
);
8253 feature
= tdesc_find_feature (info
.target_desc
,
8254 "org.gnu.gdb.mips.cp0");
8255 if (feature
== NULL
)
8257 tdesc_data_cleanup (tdesc_data
);
8262 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8263 mips_regnum
.badvaddr
, "badvaddr");
8264 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8265 MIPS_PS_REGNUM
, "status");
8266 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8267 mips_regnum
.cause
, "cause");
8271 tdesc_data_cleanup (tdesc_data
);
8275 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8276 backend is not prepared for that, though. */
8277 feature
= tdesc_find_feature (info
.target_desc
,
8278 "org.gnu.gdb.mips.fpu");
8279 if (feature
== NULL
)
8281 tdesc_data_cleanup (tdesc_data
);
8286 for (i
= 0; i
< 32; i
++)
8287 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8288 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8290 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8291 mips_regnum
.fp_control_status
,
8294 &= tdesc_numbered_register (feature
, tdesc_data
,
8295 mips_regnum
.fp_implementation_revision
,
8300 tdesc_data_cleanup (tdesc_data
);
8304 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8308 feature
= tdesc_find_feature (info
.target_desc
,
8309 "org.gnu.gdb.mips.dsp");
8310 /* The DSP registers are optional; it's OK if they are absent. */
8311 if (feature
!= NULL
)
8315 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8316 dspacc
+ i
++, "hi1");
8317 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8318 dspacc
+ i
++, "lo1");
8319 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8320 dspacc
+ i
++, "hi2");
8321 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8322 dspacc
+ i
++, "lo2");
8323 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8324 dspacc
+ i
++, "hi3");
8325 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8326 dspacc
+ i
++, "lo3");
8328 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8333 tdesc_data_cleanup (tdesc_data
);
8337 mips_regnum
.dspacc
= dspacc
;
8338 mips_regnum
.dspctl
= dspctl
;
8340 num_regs
= mips_regnum
.dspctl
+ 1;
8344 /* It would be nice to detect an attempt to use a 64-bit ABI
8345 when only 32-bit registers are provided. */
8349 /* First of all, extract the elf_flags, if available. */
8350 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8351 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8352 else if (arches
!= NULL
)
8353 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8357 fprintf_unfiltered (gdb_stdlog
,
8358 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8360 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8361 switch ((elf_flags
& EF_MIPS_ABI
))
8363 case E_MIPS_ABI_O32
:
8364 found_abi
= MIPS_ABI_O32
;
8366 case E_MIPS_ABI_O64
:
8367 found_abi
= MIPS_ABI_O64
;
8369 case E_MIPS_ABI_EABI32
:
8370 found_abi
= MIPS_ABI_EABI32
;
8372 case E_MIPS_ABI_EABI64
:
8373 found_abi
= MIPS_ABI_EABI64
;
8376 if ((elf_flags
& EF_MIPS_ABI2
))
8377 found_abi
= MIPS_ABI_N32
;
8379 found_abi
= MIPS_ABI_UNKNOWN
;
8383 /* GCC creates a pseudo-section whose name describes the ABI. */
8384 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8385 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8387 /* If we have no useful BFD information, use the ABI from the last
8388 MIPS architecture (if there is one). */
8389 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8390 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8392 /* Try the architecture for any hint of the correct ABI. */
8393 if (found_abi
== MIPS_ABI_UNKNOWN
8394 && info
.bfd_arch_info
!= NULL
8395 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8397 switch (info
.bfd_arch_info
->mach
)
8399 case bfd_mach_mips3900
:
8400 found_abi
= MIPS_ABI_EABI32
;
8402 case bfd_mach_mips4100
:
8403 case bfd_mach_mips5000
:
8404 found_abi
= MIPS_ABI_EABI64
;
8406 case bfd_mach_mips8000
:
8407 case bfd_mach_mips10000
:
8408 /* On Irix, ELF64 executables use the N64 ABI. The
8409 pseudo-sections which describe the ABI aren't present
8410 on IRIX. (Even for executables created by gcc.) */
8411 if (info
.abfd
!= NULL
8412 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8413 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8414 found_abi
= MIPS_ABI_N64
;
8416 found_abi
= MIPS_ABI_N32
;
8421 /* Default 64-bit objects to N64 instead of O32. */
8422 if (found_abi
== MIPS_ABI_UNKNOWN
8423 && info
.abfd
!= NULL
8424 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8425 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8426 found_abi
= MIPS_ABI_N64
;
8429 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8432 /* What has the user specified from the command line? */
8433 wanted_abi
= global_mips_abi ();
8435 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8438 /* Now that we have found what the ABI for this binary would be,
8439 check whether the user is overriding it. */
8440 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8441 mips_abi
= wanted_abi
;
8442 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8443 mips_abi
= found_abi
;
8445 mips_abi
= MIPS_ABI_O32
;
8447 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8450 /* Determine the default compressed ISA. */
8451 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8452 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8453 mips_isa
= ISA_MICROMIPS
;
8454 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8455 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8456 mips_isa
= ISA_MIPS16
;
8458 mips_isa
= global_mips_compression ();
8459 mips_compression_string
= mips_compression_strings
[mips_isa
];
8461 /* Also used when doing an architecture lookup. */
8463 fprintf_unfiltered (gdb_stdlog
,
8464 "mips_gdbarch_init: "
8465 "mips64_transfers_32bit_regs_p = %d\n",
8466 mips64_transfers_32bit_regs_p
);
8468 /* Determine the MIPS FPU type. */
8471 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8472 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8473 Tag_GNU_MIPS_ABI_FP
);
8474 #endif /* HAVE_ELF */
8476 if (!mips_fpu_type_auto
)
8477 fpu_type
= mips_fpu_type
;
8478 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8480 switch (elf_fpu_type
)
8482 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8483 fpu_type
= MIPS_FPU_DOUBLE
;
8485 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8486 fpu_type
= MIPS_FPU_SINGLE
;
8488 case Val_GNU_MIPS_ABI_FP_SOFT
:
8490 /* Soft float or unknown. */
8491 fpu_type
= MIPS_FPU_NONE
;
8495 else if (info
.bfd_arch_info
!= NULL
8496 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8497 switch (info
.bfd_arch_info
->mach
)
8499 case bfd_mach_mips3900
:
8500 case bfd_mach_mips4100
:
8501 case bfd_mach_mips4111
:
8502 case bfd_mach_mips4120
:
8503 fpu_type
= MIPS_FPU_NONE
;
8505 case bfd_mach_mips4650
:
8506 fpu_type
= MIPS_FPU_SINGLE
;
8509 fpu_type
= MIPS_FPU_DOUBLE
;
8512 else if (arches
!= NULL
)
8513 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
8515 fpu_type
= MIPS_FPU_DOUBLE
;
8517 fprintf_unfiltered (gdb_stdlog
,
8518 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8520 /* Check for blatant incompatibilities. */
8522 /* If we have only 32-bit registers, then we can't debug a 64-bit
8524 if (info
.target_desc
8525 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8526 && mips_abi
!= MIPS_ABI_EABI32
8527 && mips_abi
!= MIPS_ABI_O32
)
8529 if (tdesc_data
!= NULL
)
8530 tdesc_data_cleanup (tdesc_data
);
8534 /* Try to find a pre-existing architecture. */
8535 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8537 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8539 /* MIPS needs to be pedantic about which ABI and the compressed
8540 ISA variation the object is using. */
8541 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8543 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8545 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8547 /* Need to be pedantic about which register virtual size is
8549 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8550 != mips64_transfers_32bit_regs_p
)
8552 /* Be pedantic about which FPU is selected. */
8553 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
8556 if (tdesc_data
!= NULL
)
8557 tdesc_data_cleanup (tdesc_data
);
8558 return arches
->gdbarch
;
8561 /* Need a new architecture. Fill in a target specific vector. */
8562 tdep
= XNEW (struct gdbarch_tdep
);
8563 gdbarch
= gdbarch_alloc (&info
, tdep
);
8564 tdep
->elf_flags
= elf_flags
;
8565 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8566 tdep
->found_abi
= found_abi
;
8567 tdep
->mips_abi
= mips_abi
;
8568 tdep
->mips_isa
= mips_isa
;
8569 tdep
->mips_fpu_type
= fpu_type
;
8570 tdep
->register_size_valid_p
= 0;
8571 tdep
->register_size
= 0;
8573 if (info
.target_desc
)
8575 /* Some useful properties can be inferred from the target. */
8576 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8578 tdep
->register_size_valid_p
= 1;
8579 tdep
->register_size
= 4;
8581 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8583 tdep
->register_size_valid_p
= 1;
8584 tdep
->register_size
= 8;
8588 /* Initially set everything according to the default ABI/ISA. */
8589 set_gdbarch_short_bit (gdbarch
, 16);
8590 set_gdbarch_int_bit (gdbarch
, 32);
8591 set_gdbarch_float_bit (gdbarch
, 32);
8592 set_gdbarch_double_bit (gdbarch
, 64);
8593 set_gdbarch_long_double_bit (gdbarch
, 64);
8594 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8595 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8596 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8598 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8599 mips_ax_pseudo_register_collect
);
8600 set_gdbarch_ax_pseudo_register_push_stack
8601 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8603 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8604 mips_elf_make_msymbol_special
);
8605 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8606 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8607 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8609 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8610 *regnum
= mips_regnum
;
8611 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8612 set_gdbarch_num_regs (gdbarch
, num_regs
);
8613 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8614 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8615 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8616 tdep
->mips_processor_reg_names
= reg_names
;
8617 tdep
->regnum
= regnum
;
8622 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8623 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8624 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8625 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8626 tdep
->default_mask_address_p
= 0;
8627 set_gdbarch_long_bit (gdbarch
, 32);
8628 set_gdbarch_ptr_bit (gdbarch
, 32);
8629 set_gdbarch_long_long_bit (gdbarch
, 64);
8632 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8633 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8634 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8635 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8636 tdep
->default_mask_address_p
= 0;
8637 set_gdbarch_long_bit (gdbarch
, 32);
8638 set_gdbarch_ptr_bit (gdbarch
, 32);
8639 set_gdbarch_long_long_bit (gdbarch
, 64);
8641 case MIPS_ABI_EABI32
:
8642 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8643 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8644 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8645 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8646 tdep
->default_mask_address_p
= 0;
8647 set_gdbarch_long_bit (gdbarch
, 32);
8648 set_gdbarch_ptr_bit (gdbarch
, 32);
8649 set_gdbarch_long_long_bit (gdbarch
, 64);
8651 case MIPS_ABI_EABI64
:
8652 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8653 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8654 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8655 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8656 tdep
->default_mask_address_p
= 0;
8657 set_gdbarch_long_bit (gdbarch
, 64);
8658 set_gdbarch_ptr_bit (gdbarch
, 64);
8659 set_gdbarch_long_long_bit (gdbarch
, 64);
8662 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8663 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8664 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8665 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8666 tdep
->default_mask_address_p
= 0;
8667 set_gdbarch_long_bit (gdbarch
, 32);
8668 set_gdbarch_ptr_bit (gdbarch
, 32);
8669 set_gdbarch_long_long_bit (gdbarch
, 64);
8670 set_gdbarch_long_double_bit (gdbarch
, 128);
8671 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8674 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8675 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8676 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8677 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8678 tdep
->default_mask_address_p
= 0;
8679 set_gdbarch_long_bit (gdbarch
, 64);
8680 set_gdbarch_ptr_bit (gdbarch
, 64);
8681 set_gdbarch_long_long_bit (gdbarch
, 64);
8682 set_gdbarch_long_double_bit (gdbarch
, 128);
8683 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8686 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8689 /* GCC creates a pseudo-section whose name specifies the size of
8690 longs, since -mlong32 or -mlong64 may be used independent of
8691 other options. How those options affect pointer sizes is ABI and
8692 architecture dependent, so use them to override the default sizes
8693 set by the ABI. This table shows the relationship between ABI,
8694 -mlongXX, and size of pointers:
8696 ABI -mlongXX ptr bits
8697 --- -------- --------
8711 Note that for o32 and eabi32, pointers are always 32 bits
8712 regardless of any -mlongXX option. For all others, pointers and
8713 longs are the same, as set by -mlongXX or set by defaults. */
8715 if (info
.abfd
!= NULL
)
8719 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8722 set_gdbarch_long_bit (gdbarch
, long_bit
);
8726 case MIPS_ABI_EABI32
:
8731 case MIPS_ABI_EABI64
:
8732 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8735 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8740 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8741 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8744 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8745 flag in object files because to do so would make it impossible to
8746 link with libraries compiled without "-gp32". This is
8747 unnecessarily restrictive.
8749 We could solve this problem by adding "-gp32" multilibs to gcc,
8750 but to set this flag before gcc is built with such multilibs will
8751 break too many systems.''
8753 But even more unhelpfully, the default linker output target for
8754 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8755 for 64-bit programs - you need to change the ABI to change this,
8756 and not all gcc targets support that currently. Therefore using
8757 this flag to detect 32-bit mode would do the wrong thing given
8758 the current gcc - it would make GDB treat these 64-bit programs
8759 as 32-bit programs by default. */
8761 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8762 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8764 /* Add/remove bits from an address. The MIPS needs be careful to
8765 ensure that all 32 bit addresses are sign extended to 64 bits. */
8766 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8768 /* Unwind the frame. */
8769 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8770 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8771 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8773 /* Map debug register numbers onto internal register numbers. */
8774 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8775 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8776 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8777 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8778 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8779 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8781 /* MIPS version of CALL_DUMMY. */
8783 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8784 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8785 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8787 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8789 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8790 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8791 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8793 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8794 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
8795 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
8796 mips_remote_breakpoint_from_pc
);
8797 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8798 mips_adjust_breakpoint_address
);
8800 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8802 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8804 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8805 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8806 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8808 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8810 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8812 if (mips_abi
== MIPS_ABI_N32
)
8813 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8814 else if (mips_abi
== MIPS_ABI_N64
)
8815 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8817 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8819 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8820 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8821 need to all be folded into the target vector. Since they are
8822 being used as guards for target_stopped_by_watchpoint, why not have
8823 target_stopped_by_watchpoint return the type of watchpoint that the code
8825 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8827 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8829 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8830 to support MIPS16. This is a bad thing. Make sure not to do it
8831 if we have an OS ABI that actually supports shared libraries, since
8832 shared library support is more important. If we have an OS someday
8833 that supports both shared libraries and MIPS16, we'll have to find
8834 a better place for these.
8835 macro/2012-04-25: But that applies to return trampolines only and
8836 currently no MIPS OS ABI uses shared libraries that have them. */
8837 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8839 set_gdbarch_single_step_through_delay (gdbarch
,
8840 mips_single_step_through_delay
);
8842 /* Virtual tables. */
8843 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8845 mips_register_g_packet_guesses (gdbarch
);
8847 /* Hook in OS ABI-specific overrides, if they have been registered. */
8848 info
.tdep_info
= tdesc_data
;
8849 gdbarch_init_osabi (info
, gdbarch
);
8851 /* The hook may have adjusted num_regs, fetch the final value and
8852 set pc_regnum and sp_regnum now that it has been fixed. */
8853 num_regs
= gdbarch_num_regs (gdbarch
);
8854 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8855 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8857 /* Unwind the frame. */
8858 dwarf2_append_unwinders (gdbarch
);
8859 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8860 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8861 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8862 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8863 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8864 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8865 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8866 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8867 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8871 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8872 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8874 /* Override the normal target description methods to handle our
8875 dual real and pseudo registers. */
8876 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8877 set_gdbarch_register_reggroup_p (gdbarch
,
8878 mips_tdesc_register_reggroup_p
);
8880 num_regs
= gdbarch_num_regs (gdbarch
);
8881 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8882 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8883 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8886 /* Add ABI-specific aliases for the registers. */
8887 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8888 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8889 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8890 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8892 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8893 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8894 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8896 /* Add some other standard aliases. */
8897 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8898 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8899 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8901 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8902 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8903 value_of_mips_user_reg
,
8904 &mips_numeric_register_aliases
[i
].regnum
);
8910 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
8912 struct gdbarch_info info
;
8914 /* Force the architecture to update, and (if it's a MIPS architecture)
8915 mips_gdbarch_init will take care of the rest. */
8916 gdbarch_info_init (&info
);
8917 gdbarch_update_p (info
);
8920 /* Print out which MIPS ABI is in use. */
8923 show_mips_abi (struct ui_file
*file
,
8925 struct cmd_list_element
*ignored_cmd
,
8926 const char *ignored_value
)
8928 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8931 "The MIPS ABI is unknown because the current architecture "
8935 enum mips_abi global_abi
= global_mips_abi ();
8936 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8937 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8939 if (global_abi
== MIPS_ABI_UNKNOWN
)
8942 "The MIPS ABI is set automatically (currently \"%s\").\n",
8944 else if (global_abi
== actual_abi
)
8947 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8951 /* Probably shouldn't happen... */
8952 fprintf_filtered (file
,
8953 "The (auto detected) MIPS ABI \"%s\" is in use "
8954 "even though the user setting was \"%s\".\n",
8955 actual_abi_str
, mips_abi_strings
[global_abi
]);
8960 /* Print out which MIPS compressed ISA encoding is used. */
8963 show_mips_compression (struct ui_file
*file
, int from_tty
,
8964 struct cmd_list_element
*c
, const char *value
)
8966 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8971 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8973 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8977 int ef_mips_32bitmode
;
8978 /* Determine the ISA. */
8979 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8997 /* Determine the size of a pointer. */
8998 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8999 fprintf_unfiltered (file
,
9000 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
9002 fprintf_unfiltered (file
,
9003 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
9005 fprintf_unfiltered (file
,
9006 "mips_dump_tdep: ef_mips_arch = %d\n",
9008 fprintf_unfiltered (file
,
9009 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
9010 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
9011 fprintf_unfiltered (file
,
9013 "mips_mask_address_p() %d (default %d)\n",
9014 mips_mask_address_p (tdep
),
9015 tdep
->default_mask_address_p
);
9017 fprintf_unfiltered (file
,
9018 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
9019 MIPS_DEFAULT_FPU_TYPE
,
9020 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
9021 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
9022 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
9024 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
9025 MIPS_EABI (gdbarch
));
9026 fprintf_unfiltered (file
,
9027 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
9028 MIPS_FPU_TYPE (gdbarch
),
9029 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
9030 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
9031 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
9035 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
9038 _initialize_mips_tdep (void)
9040 static struct cmd_list_element
*mipsfpulist
= NULL
;
9041 struct cmd_list_element
*c
;
9043 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
9044 if (MIPS_ABI_LAST
+ 1
9045 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
9046 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
9048 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
9050 mips_pdr_data
= register_objfile_data ();
9052 /* Create feature sets with the appropriate properties. The values
9053 are not important. */
9054 mips_tdesc_gp32
= allocate_target_description ();
9055 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
9057 mips_tdesc_gp64
= allocate_target_description ();
9058 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
9060 /* Add root prefix command for all "set mips"/"show mips" commands. */
9061 add_prefix_cmd ("mips", no_class
, set_mips_command
,
9062 _("Various MIPS specific commands."),
9063 &setmipscmdlist
, "set mips ", 0, &setlist
);
9065 add_prefix_cmd ("mips", no_class
, show_mips_command
,
9066 _("Various MIPS specific commands."),
9067 &showmipscmdlist
, "show mips ", 0, &showlist
);
9069 /* Allow the user to override the ABI. */
9070 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9071 &mips_abi_string
, _("\
9072 Set the MIPS ABI used by this program."), _("\
9073 Show the MIPS ABI used by this program."), _("\
9074 This option can be set to one of:\n\
9075 auto - the default ABI associated with the current binary\n\
9084 &setmipscmdlist
, &showmipscmdlist
);
9086 /* Allow the user to set the ISA to assume for compressed code if ELF
9087 file flags don't tell or there is no program file selected. This
9088 setting is updated whenever unambiguous ELF file flags are interpreted,
9089 and carried over to subsequent sessions. */
9090 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9091 &mips_compression_string
, _("\
9092 Set the compressed ISA encoding used by MIPS code."), _("\
9093 Show the compressed ISA encoding used by MIPS code."), _("\
9094 Select the compressed ISA encoding used in functions that have no symbol\n\
9095 information available. The encoding can be set to either of:\n\
9098 and is updated automatically from ELF file flags if available."),
9100 show_mips_compression
,
9101 &setmipscmdlist
, &showmipscmdlist
);
9103 /* Let the user turn off floating point and set the fence post for
9104 heuristic_proc_start. */
9106 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
9107 _("Set use of MIPS floating-point coprocessor."),
9108 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
9109 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9110 _("Select single-precision MIPS floating-point coprocessor."),
9112 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9113 _("Select double-precision MIPS floating-point coprocessor."),
9115 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
9116 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
9117 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
9118 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9119 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9120 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
9121 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
9122 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
9123 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9124 _("Select MIPS floating-point coprocessor automatically."),
9126 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9127 _("Show current use of MIPS floating-point coprocessor target."),
9130 /* We really would like to have both "0" and "unlimited" work, but
9131 command.c doesn't deal with that. So make it a var_zinteger
9132 because the user can always use "999999" or some such for unlimited. */
9133 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9134 &heuristic_fence_post
, _("\
9135 Set the distance searched for the start of a function."), _("\
9136 Show the distance searched for the start of a function."), _("\
9137 If you are debugging a stripped executable, GDB needs to search through the\n\
9138 program for the start of a function. This command sets the distance of the\n\
9139 search. The only need to set it is when debugging a stripped executable."),
9140 reinit_frame_cache_sfunc
,
9141 NULL
, /* FIXME: i18n: The distance searched for
9142 the start of a function is %s. */
9143 &setlist
, &showlist
);
9145 /* Allow the user to control whether the upper bits of 64-bit
9146 addresses should be zeroed. */
9147 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9148 &mask_address_var
, _("\
9149 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9150 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9151 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9152 allow GDB to determine the correct value."),
9153 NULL
, show_mask_address
,
9154 &setmipscmdlist
, &showmipscmdlist
);
9156 /* Allow the user to control the size of 32 bit registers within the
9157 raw remote packet. */
9158 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9159 &mips64_transfers_32bit_regs_p
, _("\
9160 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9162 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9164 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9165 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9166 64 bits for others. Use \"off\" to disable compatibility mode"),
9167 set_mips64_transfers_32bit_regs
,
9168 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9169 MIPS target that transfers 32-bit
9170 quantities is %s. */
9171 &setlist
, &showlist
);
9173 /* Debug this files internals. */
9174 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9176 Set mips debugging."), _("\
9177 Show mips debugging."), _("\
9178 When non-zero, mips specific debugging is enabled."),
9180 NULL
, /* FIXME: i18n: Mips debugging is
9182 &setdebuglist
, &showdebuglist
);