1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 #include "target-descriptions.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
78 static const char *mips_abi_string
;
80 static const char *mips_abi_strings
[] = {
91 /* Various MIPS ISA options (related to stack analysis) can be
92 overridden dynamically. Establish an enum/array for managing
95 static const char size_auto
[] = "auto";
96 static const char size_32
[] = "32";
97 static const char size_64
[] = "64";
99 static const char *size_enums
[] = {
106 /* Some MIPS boards don't support floating point while others only
107 support single-precision floating-point operations. */
111 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
112 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
113 MIPS_FPU_NONE
/* No floating point. */
116 #ifndef MIPS_DEFAULT_FPU_TYPE
117 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
119 static int mips_fpu_type_auto
= 1;
120 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
122 static int mips_debug
= 0;
124 /* Properties (for struct target_desc) describing the g/G packet
126 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
127 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
129 /* MIPS specific per-architecture information */
132 /* from the elf header */
136 enum mips_abi mips_abi
;
137 enum mips_abi found_abi
;
138 enum mips_fpu_type mips_fpu_type
;
139 int mips_last_arg_regnum
;
140 int mips_last_fp_arg_regnum
;
141 int default_mask_address_p
;
142 /* Is the target using 64-bit raw integer registers but only
143 storing a left-aligned 32-bit value in each? */
144 int mips64_transfers_32bit_regs_p
;
145 /* Indexes for various registers. IRIX and embedded have
146 different values. This contains the "public" fields. Don't
147 add any that do not need to be public. */
148 const struct mips_regnum
*regnum
;
149 /* Register names table for the current register set. */
150 const char **mips_processor_reg_names
;
152 /* The size of register data available from the target, if known.
153 This doesn't quite obsolete the manual
154 mips64_transfers_32bit_regs_p, since that is documented to force
155 left alignment even for big endian (very strange). */
156 int register_size_valid_p
;
161 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
167 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
168 They are implemented as a pair of 64bit doubles where the high
169 part holds the result of the operation rounded to double, and
170 the low double holds the difference between the exact result and
171 the rounded result. So "high" + "low" contains the result with
172 added precision. Unfortunately, the floatformat structure used
173 by GDB is not powerful enough to describe this format. As a temporary
174 measure, we define a 128bit floatformat that only uses the high part.
175 We lose a bit of precision but that's probably the best we can do
176 for now with the current infrastructure. */
178 static const struct floatformat floatformat_n32n64_long_double_big
=
180 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
181 floatformat_intbit_no
,
182 "floatformat_ieee_double_big",
183 n32n64_floatformat_always_valid
186 const struct mips_regnum
*
187 mips_regnum (struct gdbarch
*gdbarch
)
189 return gdbarch_tdep (gdbarch
)->regnum
;
193 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
195 return mips_regnum (gdbarch
)->fp0
+ 12;
198 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
199 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
201 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
203 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
205 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
207 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
208 functions to test, set, or clear bit 0 of addresses. */
211 is_mips16_addr (CORE_ADDR addr
)
217 unmake_mips16_addr (CORE_ADDR addr
)
219 return ((addr
) & ~(CORE_ADDR
) 1);
222 /* Return the contents of register REGNUM as a signed integer. */
225 read_signed_register (int regnum
)
228 regcache_cooked_read_signed (current_regcache
, regnum
, &val
);
233 read_signed_register_pid (int regnum
, ptid_t ptid
)
238 if (ptid_equal (ptid
, inferior_ptid
))
239 return read_signed_register (regnum
);
241 save_ptid
= inferior_ptid
;
243 inferior_ptid
= ptid
;
245 retval
= read_signed_register (regnum
);
247 inferior_ptid
= save_ptid
;
252 /* Return the MIPS ABI associated with GDBARCH. */
254 mips_abi (struct gdbarch
*gdbarch
)
256 return gdbarch_tdep (gdbarch
)->mips_abi
;
260 mips_isa_regsize (struct gdbarch
*gdbarch
)
262 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
264 /* If we know how big the registers are, use that size. */
265 if (tdep
->register_size_valid_p
)
266 return tdep
->register_size
;
268 /* Fall back to the previous behavior. */
269 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
270 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
273 /* Return the currently configured (or set) saved register size. */
275 static const char *mips_abi_regsize_string
= size_auto
;
278 mips_abi_regsize (struct gdbarch
*gdbarch
)
280 if (mips_abi_regsize_string
== size_auto
)
281 switch (mips_abi (gdbarch
))
283 case MIPS_ABI_EABI32
:
289 case MIPS_ABI_EABI64
:
291 case MIPS_ABI_UNKNOWN
:
294 internal_error (__FILE__
, __LINE__
, _("bad switch"));
296 else if (mips_abi_regsize_string
== size_64
)
298 else /* if (mips_abi_regsize_string == size_32) */
302 /* Functions for setting and testing a bit in a minimal symbol that
303 marks it as 16-bit function. The MSB of the minimal symbol's
304 "info" field is used for this purpose.
306 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
307 i.e. refers to a 16-bit function, and sets a "special" bit in a
308 minimal symbol to mark it as a 16-bit function
310 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
313 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
315 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
317 MSYMBOL_INFO (msym
) = (char *)
318 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
319 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
324 msymbol_is_special (struct minimal_symbol
*msym
)
326 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
329 /* XFER a value from the big/little/left end of the register.
330 Depending on the size of the value it might occupy the entire
331 register or just part of it. Make an allowance for this, aligning
332 things accordingly. */
335 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
336 enum bfd_endian endian
, gdb_byte
*in
,
337 const gdb_byte
*out
, int buf_offset
)
340 gdb_assert (reg_num
>= NUM_REGS
);
341 /* Need to transfer the left or right part of the register, based on
342 the targets byte order. */
346 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
348 case BFD_ENDIAN_LITTLE
:
351 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
355 internal_error (__FILE__
, __LINE__
, _("bad switch"));
358 fprintf_unfiltered (gdb_stderr
,
359 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
360 reg_num
, reg_offset
, buf_offset
, length
);
361 if (mips_debug
&& out
!= NULL
)
364 fprintf_unfiltered (gdb_stdlog
, "out ");
365 for (i
= 0; i
< length
; i
++)
366 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
369 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
372 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
374 if (mips_debug
&& in
!= NULL
)
377 fprintf_unfiltered (gdb_stdlog
, "in ");
378 for (i
= 0; i
< length
; i
++)
379 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
382 fprintf_unfiltered (gdb_stdlog
, "\n");
385 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
386 compatiblity mode. A return value of 1 means that we have
387 physical 64-bit registers, but should treat them as 32-bit registers. */
390 mips2_fp_compat (void)
392 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
394 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
399 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
400 in all the places we deal with FP registers. PR gdb/413. */
401 /* Otherwise check the FR bit in the status register - it controls
402 the FP compatiblity mode. If it is clear we are in compatibility
404 if ((read_register (MIPS_PS_REGNUM
) & ST0_FR
) == 0)
411 /* The amount of space reserved on the stack for registers. This is
412 different to MIPS_ABI_REGSIZE as it determines the alignment of
413 data allocated after the registers have run out. */
415 static const char *mips_stack_argsize_string
= size_auto
;
418 mips_stack_argsize (struct gdbarch
*gdbarch
)
420 if (mips_stack_argsize_string
== size_auto
)
421 return mips_abi_regsize (gdbarch
);
422 else if (mips_stack_argsize_string
== size_64
)
424 else /* if (mips_stack_argsize_string == size_32) */
428 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
430 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
432 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
434 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
436 static struct type
*mips_float_register_type (void);
437 static struct type
*mips_double_register_type (void);
439 /* The list of available "set mips " and "show mips " commands */
441 static struct cmd_list_element
*setmipscmdlist
= NULL
;
442 static struct cmd_list_element
*showmipscmdlist
= NULL
;
444 /* Integer registers 0 thru 31 are handled explicitly by
445 mips_register_name(). Processor specific registers 32 and above
446 are listed in the followign tables. */
449 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
453 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
454 "sr", "lo", "hi", "bad", "cause", "pc",
455 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
456 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
457 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
458 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
459 "fsr", "fir", "" /*"fp" */ , "",
460 "", "", "", "", "", "", "", "",
461 "", "", "", "", "", "", "", "",
464 /* Names of IDT R3041 registers. */
466 static const char *mips_r3041_reg_names
[] = {
467 "sr", "lo", "hi", "bad", "cause", "pc",
468 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
469 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
470 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
471 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
472 "fsr", "fir", "", /*"fp" */ "",
473 "", "", "bus", "ccfg", "", "", "", "",
474 "", "", "port", "cmp", "", "", "epc", "prid",
477 /* Names of tx39 registers. */
479 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
480 "sr", "lo", "hi", "bad", "cause", "pc",
481 "", "", "", "", "", "", "", "",
482 "", "", "", "", "", "", "", "",
483 "", "", "", "", "", "", "", "",
484 "", "", "", "", "", "", "", "",
486 "", "", "", "", "", "", "", "",
487 "", "", "config", "cache", "debug", "depc", "epc", ""
490 /* Names of IRIX registers. */
491 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
492 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
493 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
494 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
495 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
496 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
500 /* Return the name of the register corresponding to REGNO. */
502 mips_register_name (int regno
)
504 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
505 /* GPR names for all ABIs other than n32/n64. */
506 static char *mips_gpr_names
[] = {
507 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
508 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
509 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
510 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
513 /* GPR names for n32 and n64 ABIs. */
514 static char *mips_n32_n64_gpr_names
[] = {
515 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
516 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
517 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
518 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
521 enum mips_abi abi
= mips_abi (current_gdbarch
);
523 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
524 don't make the raw register names visible. */
525 int rawnum
= regno
% NUM_REGS
;
526 if (regno
< NUM_REGS
)
529 /* The MIPS integer registers are always mapped from 0 to 31. The
530 names of the registers (which reflects the conventions regarding
531 register use) vary depending on the ABI. */
532 if (0 <= rawnum
&& rawnum
< 32)
534 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
535 return mips_n32_n64_gpr_names
[rawnum
];
537 return mips_gpr_names
[rawnum
];
539 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
541 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
542 return tdep
->mips_processor_reg_names
[rawnum
- 32];
545 internal_error (__FILE__
, __LINE__
,
546 _("mips_register_name: bad register number %d"), rawnum
);
549 /* Return the groups that a MIPS register can be categorised into. */
552 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
553 struct reggroup
*reggroup
)
558 int rawnum
= regnum
% NUM_REGS
;
559 int pseudo
= regnum
/ NUM_REGS
;
560 if (reggroup
== all_reggroup
)
562 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
563 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
564 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
565 (gdbarch), as not all architectures are multi-arch. */
566 raw_p
= rawnum
< NUM_REGS
;
567 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
569 if (reggroup
== float_reggroup
)
570 return float_p
&& pseudo
;
571 if (reggroup
== vector_reggroup
)
572 return vector_p
&& pseudo
;
573 if (reggroup
== general_reggroup
)
574 return (!vector_p
&& !float_p
) && pseudo
;
575 /* Save the pseudo registers. Need to make certain that any code
576 extracting register values from a saved register cache also uses
578 if (reggroup
== save_reggroup
)
579 return raw_p
&& pseudo
;
580 /* Restore the same pseudo register. */
581 if (reggroup
== restore_reggroup
)
582 return raw_p
&& pseudo
;
586 /* Map the symbol table registers which live in the range [1 *
587 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
588 registers. Take care of alignment and size problems. */
591 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
592 int cookednum
, gdb_byte
*buf
)
594 int rawnum
= cookednum
% NUM_REGS
;
595 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
596 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
597 regcache_raw_read (regcache
, rawnum
, buf
);
598 else if (register_size (gdbarch
, rawnum
) >
599 register_size (gdbarch
, cookednum
))
601 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
602 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
603 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
605 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
608 internal_error (__FILE__
, __LINE__
, _("bad register size"));
612 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
613 struct regcache
*regcache
, int cookednum
,
616 int rawnum
= cookednum
% NUM_REGS
;
617 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
618 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
619 regcache_raw_write (regcache
, rawnum
, buf
);
620 else if (register_size (gdbarch
, rawnum
) >
621 register_size (gdbarch
, cookednum
))
623 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
624 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
625 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
627 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
630 internal_error (__FILE__
, __LINE__
, _("bad register size"));
633 /* Table to translate MIPS16 register field to actual register number. */
634 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
636 /* Heuristic_proc_start may hunt through the text section for a long
637 time across a 2400 baud serial line. Allows the user to limit this
640 static unsigned int heuristic_fence_post
= 0;
642 /* Number of bytes of storage in the actual machine representation for
643 register N. NOTE: This defines the pseudo register type so need to
644 rebuild the architecture vector. */
646 static int mips64_transfers_32bit_regs_p
= 0;
649 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
650 struct cmd_list_element
*c
)
652 struct gdbarch_info info
;
653 gdbarch_info_init (&info
);
654 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
655 instead of relying on globals. Doing that would let generic code
656 handle the search for this specific architecture. */
657 if (!gdbarch_update_p (info
))
659 mips64_transfers_32bit_regs_p
= 0;
660 error (_("32-bit compatibility mode not supported"));
664 /* Convert to/from a register and the corresponding memory value. */
667 mips_convert_register_p (int regnum
, struct type
*type
)
669 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
670 && register_size (current_gdbarch
, regnum
) == 4
671 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
672 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
673 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
677 mips_register_to_value (struct frame_info
*frame
, int regnum
,
678 struct type
*type
, gdb_byte
*to
)
680 get_frame_register (frame
, regnum
+ 0, to
+ 4);
681 get_frame_register (frame
, regnum
+ 1, to
+ 0);
685 mips_value_to_register (struct frame_info
*frame
, int regnum
,
686 struct type
*type
, const gdb_byte
*from
)
688 put_frame_register (frame
, regnum
+ 0, from
+ 4);
689 put_frame_register (frame
, regnum
+ 1, from
+ 0);
692 /* Return the GDB type object for the "standard" data type of data in
696 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
698 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
699 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
700 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
702 /* The floating-point registers raw, or cooked, always match
703 mips_isa_regsize(), and also map 1:1, byte for byte. */
704 switch (gdbarch_byte_order (gdbarch
))
707 if (mips_isa_regsize (gdbarch
) == 4)
708 return builtin_type_ieee_single_big
;
710 return builtin_type_ieee_double_big
;
711 case BFD_ENDIAN_LITTLE
:
712 if (mips_isa_regsize (gdbarch
) == 4)
713 return builtin_type_ieee_single_little
;
715 return builtin_type_ieee_double_little
;
716 case BFD_ENDIAN_UNKNOWN
:
718 internal_error (__FILE__
, __LINE__
, _("bad switch"));
721 else if (regnum
< NUM_REGS
)
723 /* The raw or ISA registers. These are all sized according to
725 if (mips_isa_regsize (gdbarch
) == 4)
726 return builtin_type_int32
;
728 return builtin_type_int64
;
732 /* The cooked or ABI registers. These are sized according to
733 the ABI (with a few complications). */
734 if (regnum
>= (NUM_REGS
735 + mips_regnum (current_gdbarch
)->fp_control_status
)
736 && regnum
<= NUM_REGS
+ MIPS_LAST_EMBED_REGNUM
)
737 /* The pseudo/cooked view of the embedded registers is always
738 32-bit. The raw view is handled below. */
739 return builtin_type_int32
;
740 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
741 /* The target, while possibly using a 64-bit register buffer,
742 is only transfering 32-bits of each integer register.
743 Reflect this in the cooked/pseudo (ABI) register value. */
744 return builtin_type_int32
;
745 else if (mips_abi_regsize (gdbarch
) == 4)
746 /* The ABI is restricted to 32-bit registers (the ISA could be
748 return builtin_type_int32
;
751 return builtin_type_int64
;
755 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
760 return read_signed_register (MIPS_SP_REGNUM
);
763 /* Should the upper word of 64-bit addresses be zeroed? */
764 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
767 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
769 switch (mask_address_var
)
771 case AUTO_BOOLEAN_TRUE
:
773 case AUTO_BOOLEAN_FALSE
:
776 case AUTO_BOOLEAN_AUTO
:
777 return tdep
->default_mask_address_p
;
779 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
785 show_mask_address (struct ui_file
*file
, int from_tty
,
786 struct cmd_list_element
*c
, const char *value
)
788 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
790 deprecated_show_value_hack (file
, from_tty
, c
, value
);
791 switch (mask_address_var
)
793 case AUTO_BOOLEAN_TRUE
:
794 printf_filtered ("The 32 bit mips address mask is enabled\n");
796 case AUTO_BOOLEAN_FALSE
:
797 printf_filtered ("The 32 bit mips address mask is disabled\n");
799 case AUTO_BOOLEAN_AUTO
:
801 ("The 32 bit address mask is set automatically. Currently %s\n",
802 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
805 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
810 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
813 mips_pc_is_mips16 (CORE_ADDR memaddr
)
815 struct minimal_symbol
*sym
;
817 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
818 if (is_mips16_addr (memaddr
))
821 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
822 the high bit of the info field. Use this to decide if the function is
823 MIPS16 or normal MIPS. */
824 sym
= lookup_minimal_symbol_by_pc (memaddr
);
826 return msymbol_is_special (sym
);
831 /* MIPS believes that the PC has a sign extended value. Perhaps the
832 all registers should be sign extended for simplicity? */
835 mips_read_pc (ptid_t ptid
)
837 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
841 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
843 return frame_unwind_register_signed (next_frame
,
844 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
847 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
848 dummy frame. The frame ID's base needs to match the TOS value
849 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
852 static struct frame_id
853 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
855 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
856 frame_pc_unwind (next_frame
));
860 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
862 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
865 /* Fetch and return instruction from the specified location. If the PC
866 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
869 mips_fetch_instruction (CORE_ADDR addr
)
871 gdb_byte buf
[MIPS_INSN32_SIZE
];
875 if (mips_pc_is_mips16 (addr
))
877 instlen
= MIPS_INSN16_SIZE
;
878 addr
= unmake_mips16_addr (addr
);
881 instlen
= MIPS_INSN32_SIZE
;
882 status
= read_memory_nobpt (addr
, buf
, instlen
);
884 memory_error (status
, addr
);
885 return extract_unsigned_integer (buf
, instlen
);
888 /* These the fields of 32 bit mips instructions */
889 #define mips32_op(x) (x >> 26)
890 #define itype_op(x) (x >> 26)
891 #define itype_rs(x) ((x >> 21) & 0x1f)
892 #define itype_rt(x) ((x >> 16) & 0x1f)
893 #define itype_immediate(x) (x & 0xffff)
895 #define jtype_op(x) (x >> 26)
896 #define jtype_target(x) (x & 0x03ffffff)
898 #define rtype_op(x) (x >> 26)
899 #define rtype_rs(x) ((x >> 21) & 0x1f)
900 #define rtype_rt(x) ((x >> 16) & 0x1f)
901 #define rtype_rd(x) ((x >> 11) & 0x1f)
902 #define rtype_shamt(x) ((x >> 6) & 0x1f)
903 #define rtype_funct(x) (x & 0x3f)
906 mips32_relative_offset (ULONGEST inst
)
908 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
911 /* Determine where to set a single step breakpoint while considering
912 branch prediction. */
914 mips32_next_pc (CORE_ADDR pc
)
918 inst
= mips_fetch_instruction (pc
);
919 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
921 if (itype_op (inst
) >> 2 == 5)
922 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
924 op
= (itype_op (inst
) & 0x03);
939 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
940 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
942 int tf
= itype_rt (inst
) & 0x01;
943 int cnum
= itype_rt (inst
) >> 2;
945 read_signed_register (mips_regnum (current_gdbarch
)->
947 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
949 if (((cond
>> cnum
) & 0x01) == tf
)
950 pc
+= mips32_relative_offset (inst
) + 4;
955 pc
+= 4; /* Not a branch, next instruction is easy */
958 { /* This gets way messy */
960 /* Further subdivide into SPECIAL, REGIMM and other */
961 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
963 case 0: /* SPECIAL */
964 op
= rtype_funct (inst
);
969 /* Set PC to that address */
970 pc
= read_signed_register (rtype_rs (inst
));
976 break; /* end SPECIAL */
979 op
= itype_rt (inst
); /* branch condition */
984 case 16: /* BLTZAL */
985 case 18: /* BLTZALL */
987 if (read_signed_register (itype_rs (inst
)) < 0)
988 pc
+= mips32_relative_offset (inst
) + 4;
990 pc
+= 8; /* after the delay slot */
994 case 17: /* BGEZAL */
995 case 19: /* BGEZALL */
996 if (read_signed_register (itype_rs (inst
)) >= 0)
997 pc
+= mips32_relative_offset (inst
) + 4;
999 pc
+= 8; /* after the delay slot */
1001 /* All of the other instructions in the REGIMM category */
1006 break; /* end REGIMM */
1011 reg
= jtype_target (inst
) << 2;
1012 /* Upper four bits get never changed... */
1013 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1016 /* FIXME case JALX : */
1019 reg
= jtype_target (inst
) << 2;
1020 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1021 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1023 break; /* The new PC will be alternate mode */
1024 case 4: /* BEQ, BEQL */
1026 if (read_signed_register (itype_rs (inst
)) ==
1027 read_signed_register (itype_rt (inst
)))
1028 pc
+= mips32_relative_offset (inst
) + 4;
1032 case 5: /* BNE, BNEL */
1034 if (read_signed_register (itype_rs (inst
)) !=
1035 read_signed_register (itype_rt (inst
)))
1036 pc
+= mips32_relative_offset (inst
) + 4;
1040 case 6: /* BLEZ, BLEZL */
1041 if (read_signed_register (itype_rs (inst
)) <= 0)
1042 pc
+= mips32_relative_offset (inst
) + 4;
1048 greater_branch
: /* BGTZ, BGTZL */
1049 if (read_signed_register (itype_rs (inst
)) > 0)
1050 pc
+= mips32_relative_offset (inst
) + 4;
1057 } /* mips32_next_pc */
1059 /* Decoding the next place to set a breakpoint is irregular for the
1060 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1061 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1062 We dont want to set a single step instruction on the extend instruction
1066 /* Lots of mips16 instruction formats */
1067 /* Predicting jumps requires itype,ritype,i8type
1068 and their extensions extItype,extritype,extI8type
1070 enum mips16_inst_fmts
1072 itype
, /* 0 immediate 5,10 */
1073 ritype
, /* 1 5,3,8 */
1074 rrtype
, /* 2 5,3,3,5 */
1075 rritype
, /* 3 5,3,3,5 */
1076 rrrtype
, /* 4 5,3,3,3,2 */
1077 rriatype
, /* 5 5,3,3,1,4 */
1078 shifttype
, /* 6 5,3,3,3,2 */
1079 i8type
, /* 7 5,3,8 */
1080 i8movtype
, /* 8 5,3,3,5 */
1081 i8mov32rtype
, /* 9 5,3,5,3 */
1082 i64type
, /* 10 5,3,8 */
1083 ri64type
, /* 11 5,3,3,5 */
1084 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1085 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1086 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1087 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1088 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1089 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1090 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1091 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1092 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1093 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1095 /* I am heaping all the fields of the formats into one structure and
1096 then, only the fields which are involved in instruction extension */
1100 unsigned int regx
; /* Function in i8 type */
1105 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1106 for the bits which make up the immediatate extension. */
1109 extended_offset (unsigned int extension
)
1112 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1114 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1116 value
|= extension
& 0x01f; /* extract 4:0 */
1120 /* Only call this function if you know that this is an extendable
1121 instruction, It wont malfunction, but why make excess remote memory references?
1122 If the immediate operands get sign extended or somthing, do it after
1123 the extension is performed.
1125 /* FIXME: Every one of these cases needs to worry about sign extension
1126 when the offset is to be used in relative addressing */
1130 fetch_mips_16 (CORE_ADDR pc
)
1133 pc
&= 0xfffffffe; /* clear the low order bit */
1134 target_read_memory (pc
, buf
, 2);
1135 return extract_unsigned_integer (buf
, 2);
1139 unpack_mips16 (CORE_ADDR pc
,
1140 unsigned int extension
,
1142 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1147 switch (insn_format
)
1154 value
= extended_offset (extension
);
1155 value
= value
<< 11; /* rom for the original value */
1156 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1160 value
= inst
& 0x7ff;
1161 /* FIXME : Consider sign extension */
1170 { /* A register identifier and an offset */
1171 /* Most of the fields are the same as I type but the
1172 immediate value is of a different length */
1176 value
= extended_offset (extension
);
1177 value
= value
<< 8; /* from the original instruction */
1178 value
|= inst
& 0xff; /* eleven bits from instruction */
1179 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1180 if (value
& 0x4000) /* test the sign bit , bit 26 */
1182 value
&= ~0x3fff; /* remove the sign bit */
1188 value
= inst
& 0xff; /* 8 bits */
1189 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1190 /* FIXME: Do sign extension , this format needs it */
1191 if (value
& 0x80) /* THIS CONFUSES ME */
1193 value
&= 0xef; /* remove the sign bit */
1203 unsigned long value
;
1204 unsigned int nexthalf
;
1205 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1206 value
= value
<< 16;
1207 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1215 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1217 upk
->offset
= offset
;
1224 add_offset_16 (CORE_ADDR pc
, int offset
)
1226 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1230 extended_mips16_next_pc (CORE_ADDR pc
,
1231 unsigned int extension
, unsigned int insn
)
1233 int op
= (insn
>> 11);
1236 case 2: /* Branch */
1239 struct upk_mips16 upk
;
1240 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1241 offset
= upk
.offset
;
1247 pc
+= (offset
<< 1) + 2;
1250 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1252 struct upk_mips16 upk
;
1253 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1254 pc
= add_offset_16 (pc
, upk
.offset
);
1255 if ((insn
>> 10) & 0x01) /* Exchange mode */
1256 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1263 struct upk_mips16 upk
;
1265 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1266 reg
= read_signed_register (upk
.regx
);
1268 pc
+= (upk
.offset
<< 1) + 2;
1275 struct upk_mips16 upk
;
1277 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1278 reg
= read_signed_register (upk
.regx
);
1280 pc
+= (upk
.offset
<< 1) + 2;
1285 case 12: /* I8 Formats btez btnez */
1287 struct upk_mips16 upk
;
1289 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1290 /* upk.regx contains the opcode */
1291 reg
= read_signed_register (24); /* Test register is 24 */
1292 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1293 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1294 /* pc = add_offset_16(pc,upk.offset) ; */
1295 pc
+= (upk
.offset
<< 1) + 2;
1300 case 29: /* RR Formats JR, JALR, JALR-RA */
1302 struct upk_mips16 upk
;
1303 /* upk.fmt = rrtype; */
1308 upk
.regx
= (insn
>> 8) & 0x07;
1309 upk
.regy
= (insn
>> 5) & 0x07;
1317 break; /* Function return instruction */
1323 break; /* BOGUS Guess */
1325 pc
= read_signed_register (reg
);
1332 /* This is an instruction extension. Fetch the real instruction
1333 (which follows the extension) and decode things based on
1337 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1350 mips16_next_pc (CORE_ADDR pc
)
1352 unsigned int insn
= fetch_mips_16 (pc
);
1353 return extended_mips16_next_pc (pc
, 0, insn
);
1356 /* The mips_next_pc function supports single_step when the remote
1357 target monitor or stub is not developed enough to do a single_step.
1358 It works by decoding the current instruction and predicting where a
1359 branch will go. This isnt hard because all the data is available.
1360 The MIPS32 and MIPS16 variants are quite different */
1362 mips_next_pc (CORE_ADDR pc
)
1365 return mips16_next_pc (pc
);
1367 return mips32_next_pc (pc
);
1370 struct mips_frame_cache
1373 struct trad_frame_saved_reg
*saved_regs
;
1376 /* Set a register's saved stack address in temp_saved_regs. If an
1377 address has already been set for this register, do nothing; this
1378 way we will only recognize the first save of a given register in a
1381 For simplicity, save the address in both [0 .. NUM_REGS) and
1382 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1383 is used as it is only second range (the ABI instead of ISA
1384 registers) that comes into play when finding saved registers in a
1388 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1391 if (this_cache
!= NULL
1392 && this_cache
->saved_regs
[regnum
].addr
== -1)
1394 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
1395 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
1400 /* Fetch the immediate value from a MIPS16 instruction.
1401 If the previous instruction was an EXTEND, use it to extend
1402 the upper bits of the immediate value. This is a helper function
1403 for mips16_scan_prologue. */
1406 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1407 unsigned short inst
, /* current instruction */
1408 int nbits
, /* number of bits in imm field */
1409 int scale
, /* scale factor to be applied to imm */
1410 int is_signed
) /* is the imm field signed? */
1414 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1416 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1417 if (offset
& 0x8000) /* check for negative extend */
1418 offset
= 0 - (0x10000 - (offset
& 0xffff));
1419 return offset
| (inst
& 0x1f);
1423 int max_imm
= 1 << nbits
;
1424 int mask
= max_imm
- 1;
1425 int sign_bit
= max_imm
>> 1;
1427 offset
= inst
& mask
;
1428 if (is_signed
&& (offset
& sign_bit
))
1429 offset
= 0 - (max_imm
- offset
);
1430 return offset
* scale
;
1435 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1436 the associated FRAME_CACHE if not null.
1437 Return the address of the first instruction past the prologue. */
1440 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1441 struct frame_info
*next_frame
,
1442 struct mips_frame_cache
*this_cache
)
1445 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1447 long frame_offset
= 0; /* Size of stack frame. */
1448 long frame_adjust
= 0; /* Offset of FP from SP. */
1449 int frame_reg
= MIPS_SP_REGNUM
;
1450 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1451 unsigned inst
= 0; /* current instruction */
1452 unsigned entry_inst
= 0; /* the entry instruction */
1455 int extend_bytes
= 0;
1456 int prev_extend_bytes
;
1457 CORE_ADDR end_prologue_addr
= 0;
1459 /* Can be called when there's no process, and hence when there's no
1461 if (next_frame
!= NULL
)
1462 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1466 if (limit_pc
> start_pc
+ 200)
1467 limit_pc
= start_pc
+ 200;
1469 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1471 /* Save the previous instruction. If it's an EXTEND, we'll extract
1472 the immediate offset extension from it in mips16_get_imm. */
1475 /* Fetch and decode the instruction. */
1476 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1478 /* Normally we ignore extend instructions. However, if it is
1479 not followed by a valid prologue instruction, then this
1480 instruction is not part of the prologue either. We must
1481 remember in this case to adjust the end_prologue_addr back
1483 if ((inst
& 0xf800) == 0xf000) /* extend */
1485 extend_bytes
= MIPS_INSN16_SIZE
;
1489 prev_extend_bytes
= extend_bytes
;
1492 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1493 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1495 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1496 if (offset
< 0) /* negative stack adjustment? */
1497 frame_offset
-= offset
;
1499 /* Exit loop if a positive stack adjustment is found, which
1500 usually means that the stack cleanup code in the function
1501 epilogue is reached. */
1504 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1506 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1507 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1508 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1510 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1512 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1513 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1514 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1516 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1518 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1519 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1521 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1523 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1524 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1526 else if (inst
== 0x673d) /* move $s1, $sp */
1531 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1533 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1534 frame_addr
= sp
+ offset
;
1536 frame_adjust
= offset
;
1538 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1540 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1541 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1542 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1544 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1546 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1547 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1548 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1550 else if ((inst
& 0xf81f) == 0xe809
1551 && (inst
& 0x700) != 0x700) /* entry */
1552 entry_inst
= inst
; /* save for later processing */
1553 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1554 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1555 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1557 /* This instruction is part of the prologue, but we don't
1558 need to do anything special to handle it. */
1562 /* This instruction is not an instruction typically found
1563 in a prologue, so we must have reached the end of the
1565 if (end_prologue_addr
== 0)
1566 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1570 /* The entry instruction is typically the first instruction in a function,
1571 and it stores registers at offsets relative to the value of the old SP
1572 (before the prologue). But the value of the sp parameter to this
1573 function is the new SP (after the prologue has been executed). So we
1574 can't calculate those offsets until we've seen the entire prologue,
1575 and can calculate what the old SP must have been. */
1576 if (entry_inst
!= 0)
1578 int areg_count
= (entry_inst
>> 8) & 7;
1579 int sreg_count
= (entry_inst
>> 6) & 3;
1581 /* The entry instruction always subtracts 32 from the SP. */
1584 /* Now we can calculate what the SP must have been at the
1585 start of the function prologue. */
1588 /* Check if a0-a3 were saved in the caller's argument save area. */
1589 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1591 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1592 offset
+= mips_abi_regsize (current_gdbarch
);
1595 /* Check if the ra register was pushed on the stack. */
1597 if (entry_inst
& 0x20)
1599 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1600 offset
-= mips_abi_regsize (current_gdbarch
);
1603 /* Check if the s0 and s1 registers were pushed on the stack. */
1604 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1606 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1607 offset
-= mips_abi_regsize (current_gdbarch
);
1611 if (this_cache
!= NULL
)
1614 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1615 + frame_offset
- frame_adjust
);
1616 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1617 be able to get rid of the assignment below, evetually. But it's
1618 still needed for now. */
1619 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1620 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1623 /* If we didn't reach the end of the prologue when scanning the function
1624 instructions, then set end_prologue_addr to the address of the
1625 instruction immediately after the last one we scanned. */
1626 if (end_prologue_addr
== 0)
1627 end_prologue_addr
= cur_pc
;
1629 return end_prologue_addr
;
1632 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1633 Procedures that use the 32-bit instruction set are handled by the
1634 mips_insn32 unwinder. */
1636 static struct mips_frame_cache
*
1637 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1639 struct mips_frame_cache
*cache
;
1641 if ((*this_cache
) != NULL
)
1642 return (*this_cache
);
1643 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1644 (*this_cache
) = cache
;
1645 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1647 /* Analyze the function prologue. */
1649 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1650 CORE_ADDR start_addr
;
1652 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1653 if (start_addr
== 0)
1654 start_addr
= heuristic_proc_start (pc
);
1655 /* We can't analyze the prologue if we couldn't find the begining
1657 if (start_addr
== 0)
1660 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1663 /* SP_REGNUM, contains the value and not the address. */
1664 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1666 return (*this_cache
);
1670 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1671 struct frame_id
*this_id
)
1673 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1675 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1679 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1681 int regnum
, int *optimizedp
,
1682 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1683 int *realnump
, gdb_byte
*valuep
)
1685 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1687 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1688 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1691 static const struct frame_unwind mips_insn16_frame_unwind
=
1694 mips_insn16_frame_this_id
,
1695 mips_insn16_frame_prev_register
1698 static const struct frame_unwind
*
1699 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1701 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1702 if (mips_pc_is_mips16 (pc
))
1703 return &mips_insn16_frame_unwind
;
1708 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1711 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1716 static const struct frame_base mips_insn16_frame_base
=
1718 &mips_insn16_frame_unwind
,
1719 mips_insn16_frame_base_address
,
1720 mips_insn16_frame_base_address
,
1721 mips_insn16_frame_base_address
1724 static const struct frame_base
*
1725 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1727 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1728 return &mips_insn16_frame_base
;
1733 /* Mark all the registers as unset in the saved_regs array
1734 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1737 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1739 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1743 const int num_regs
= NUM_REGS
;
1746 for (i
= 0; i
< num_regs
; i
++)
1748 this_cache
->saved_regs
[i
].addr
= -1;
1753 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1754 the associated FRAME_CACHE if not null.
1755 Return the address of the first instruction past the prologue. */
1758 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1759 struct frame_info
*next_frame
,
1760 struct mips_frame_cache
*this_cache
)
1763 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1766 int frame_reg
= MIPS_SP_REGNUM
;
1768 CORE_ADDR end_prologue_addr
= 0;
1769 int seen_sp_adjust
= 0;
1770 int load_immediate_bytes
= 0;
1772 /* Can be called when there's no process, and hence when there's no
1774 if (next_frame
!= NULL
)
1775 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1779 if (limit_pc
> start_pc
+ 200)
1780 limit_pc
= start_pc
+ 200;
1785 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1787 unsigned long inst
, high_word
, low_word
;
1790 /* Fetch the instruction. */
1791 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1793 /* Save some code by pre-extracting some useful fields. */
1794 high_word
= (inst
>> 16) & 0xffff;
1795 low_word
= inst
& 0xffff;
1796 reg
= high_word
& 0x1f;
1798 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1799 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1800 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1802 if (low_word
& 0x8000) /* negative stack adjustment? */
1803 frame_offset
+= 0x10000 - low_word
;
1805 /* Exit loop if a positive stack adjustment is found, which
1806 usually means that the stack cleanup code in the function
1807 epilogue is reached. */
1811 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1813 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1815 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1817 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1818 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1820 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1822 /* Old gcc frame, r30 is virtual frame pointer. */
1823 if ((long) low_word
!= frame_offset
)
1824 frame_addr
= sp
+ low_word
;
1825 else if (frame_reg
== MIPS_SP_REGNUM
)
1827 unsigned alloca_adjust
;
1830 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
1831 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1832 if (alloca_adjust
> 0)
1834 /* FP > SP + frame_size. This may be because of
1835 an alloca or somethings similar. Fix sp to
1836 "pre-alloca" value, and try again. */
1837 sp
+= alloca_adjust
;
1838 /* Need to reset the status of all registers. Otherwise,
1839 we will hit a guard that prevents the new address
1840 for each register to be recomputed during the second
1842 reset_saved_regs (this_cache
);
1847 /* move $30,$sp. With different versions of gas this will be either
1848 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1849 Accept any one of these. */
1850 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1852 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1853 if (frame_reg
== MIPS_SP_REGNUM
)
1855 unsigned alloca_adjust
;
1858 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
1859 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1860 if (alloca_adjust
> 0)
1862 /* FP > SP + frame_size. This may be because of
1863 an alloca or somethings similar. Fix sp to
1864 "pre-alloca" value, and try again. */
1866 /* Need to reset the status of all registers. Otherwise,
1867 we will hit a guard that prevents the new address
1868 for each register to be recomputed during the second
1870 reset_saved_regs (this_cache
);
1875 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1877 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
1879 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1880 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1881 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1882 || high_word
== 0x3c1c /* lui $gp,n */
1883 || high_word
== 0x279c /* addiu $gp,$gp,n */
1884 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1885 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
1888 /* These instructions are part of the prologue, but we don't
1889 need to do anything special to handle them. */
1891 /* The instructions below load $at or $t0 with an immediate
1892 value in preparation for a stack adjustment via
1893 subu $sp,$sp,[$at,$t0]. These instructions could also
1894 initialize a local variable, so we accept them only before
1895 a stack adjustment instruction was seen. */
1896 else if (!seen_sp_adjust
1897 && (high_word
== 0x3c01 /* lui $at,n */
1898 || high_word
== 0x3c08 /* lui $t0,n */
1899 || high_word
== 0x3421 /* ori $at,$at,n */
1900 || high_word
== 0x3508 /* ori $t0,$t0,n */
1901 || high_word
== 0x3401 /* ori $at,$zero,n */
1902 || high_word
== 0x3408 /* ori $t0,$zero,n */
1905 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
1909 /* This instruction is not an instruction typically found
1910 in a prologue, so we must have reached the end of the
1912 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
1913 loop now? Why would we need to continue scanning the function
1915 if (end_prologue_addr
== 0)
1916 end_prologue_addr
= cur_pc
;
1920 if (this_cache
!= NULL
)
1923 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1925 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
1926 this assignment below, eventually. But it's still needed
1928 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1929 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1932 /* If we didn't reach the end of the prologue when scanning the function
1933 instructions, then set end_prologue_addr to the address of the
1934 instruction immediately after the last one we scanned. */
1935 /* brobecker/2004-10-10: I don't think this would ever happen, but
1936 we may as well be careful and do our best if we have a null
1937 end_prologue_addr. */
1938 if (end_prologue_addr
== 0)
1939 end_prologue_addr
= cur_pc
;
1941 /* In a frameless function, we might have incorrectly
1942 skipped some load immediate instructions. Undo the skipping
1943 if the load immediate was not followed by a stack adjustment. */
1944 if (load_immediate_bytes
&& !seen_sp_adjust
)
1945 end_prologue_addr
-= load_immediate_bytes
;
1947 return end_prologue_addr
;
1950 /* Heuristic unwinder for procedures using 32-bit instructions (covers
1951 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
1952 instructions (a.k.a. MIPS16) are handled by the mips_insn16
1955 static struct mips_frame_cache
*
1956 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1958 struct mips_frame_cache
*cache
;
1960 if ((*this_cache
) != NULL
)
1961 return (*this_cache
);
1963 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1964 (*this_cache
) = cache
;
1965 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1967 /* Analyze the function prologue. */
1969 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1970 CORE_ADDR start_addr
;
1972 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1973 if (start_addr
== 0)
1974 start_addr
= heuristic_proc_start (pc
);
1975 /* We can't analyze the prologue if we couldn't find the begining
1977 if (start_addr
== 0)
1980 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1983 /* SP_REGNUM, contains the value and not the address. */
1984 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1986 return (*this_cache
);
1990 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1991 struct frame_id
*this_id
)
1993 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1995 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1999 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2001 int regnum
, int *optimizedp
,
2002 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2003 int *realnump
, gdb_byte
*valuep
)
2005 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2007 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2008 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2011 static const struct frame_unwind mips_insn32_frame_unwind
=
2014 mips_insn32_frame_this_id
,
2015 mips_insn32_frame_prev_register
2018 static const struct frame_unwind
*
2019 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2021 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2022 if (! mips_pc_is_mips16 (pc
))
2023 return &mips_insn32_frame_unwind
;
2028 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2031 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2036 static const struct frame_base mips_insn32_frame_base
=
2038 &mips_insn32_frame_unwind
,
2039 mips_insn32_frame_base_address
,
2040 mips_insn32_frame_base_address
,
2041 mips_insn32_frame_base_address
2044 static const struct frame_base
*
2045 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2047 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2048 return &mips_insn32_frame_base
;
2053 static struct trad_frame_cache
*
2054 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2057 CORE_ADDR start_addr
;
2058 CORE_ADDR stack_addr
;
2059 struct trad_frame_cache
*this_trad_cache
;
2061 if ((*this_cache
) != NULL
)
2062 return (*this_cache
);
2063 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2064 (*this_cache
) = this_trad_cache
;
2066 /* The return address is in the link register. */
2067 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, MIPS_RA_REGNUM
);
2069 /* Frame ID, since it's a frameless / stackless function, no stack
2070 space is allocated and SP on entry is the current SP. */
2071 pc
= frame_pc_unwind (next_frame
);
2072 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2073 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2074 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2076 /* Assume that the frame's base is the same as the
2078 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2080 return this_trad_cache
;
2084 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2085 struct frame_id
*this_id
)
2087 struct trad_frame_cache
*this_trad_cache
2088 = mips_stub_frame_cache (next_frame
, this_cache
);
2089 trad_frame_get_id (this_trad_cache
, this_id
);
2093 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2095 int regnum
, int *optimizedp
,
2096 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2097 int *realnump
, gdb_byte
*valuep
)
2099 struct trad_frame_cache
*this_trad_cache
2100 = mips_stub_frame_cache (next_frame
, this_cache
);
2101 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2102 lvalp
, addrp
, realnump
, valuep
);
2105 static const struct frame_unwind mips_stub_frame_unwind
=
2108 mips_stub_frame_this_id
,
2109 mips_stub_frame_prev_register
2112 static const struct frame_unwind
*
2113 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2115 struct obj_section
*s
;
2116 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2118 if (in_plt_section (pc
, NULL
))
2119 return &mips_stub_frame_unwind
;
2121 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2122 s
= find_pc_section (pc
);
2125 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2126 ".MIPS.stubs") == 0)
2127 return &mips_stub_frame_unwind
;
2133 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2136 struct trad_frame_cache
*this_trad_cache
2137 = mips_stub_frame_cache (next_frame
, this_cache
);
2138 return trad_frame_get_this_base (this_trad_cache
);
2141 static const struct frame_base mips_stub_frame_base
=
2143 &mips_stub_frame_unwind
,
2144 mips_stub_frame_base_address
,
2145 mips_stub_frame_base_address
,
2146 mips_stub_frame_base_address
2149 static const struct frame_base
*
2150 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2152 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2153 return &mips_stub_frame_base
;
2159 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2161 /* Always a pseudo. */
2162 gdb_assert (regno
>= NUM_REGS
);
2166 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2170 return frame_unwind_register_signed (fi
, regno
);
2174 /* mips_addr_bits_remove - remove useless address bits */
2177 mips_addr_bits_remove (CORE_ADDR addr
)
2179 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2180 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2181 /* This hack is a work-around for existing boards using PMON, the
2182 simulator, and any other 64-bit targets that doesn't have true
2183 64-bit addressing. On these targets, the upper 32 bits of
2184 addresses are ignored by the hardware. Thus, the PC or SP are
2185 likely to have been sign extended to all 1s by instruction
2186 sequences that load 32-bit addresses. For example, a typical
2187 piece of code that loads an address is this:
2189 lui $r2, <upper 16 bits>
2190 ori $r2, <lower 16 bits>
2192 But the lui sign-extends the value such that the upper 32 bits
2193 may be all 1s. The workaround is simply to mask off these
2194 bits. In the future, gcc may be changed to support true 64-bit
2195 addressing, and this masking will have to be disabled. */
2196 return addr
&= 0xffffffffUL
;
2201 /* mips_software_single_step() is called just before we want to resume
2202 the inferior, if we want to single-step it but there is no hardware
2203 or kernel single-step support (MIPS on GNU/Linux for example). We find
2204 the target of the coming instruction and breakpoint it.
2206 single_step is also called just after the inferior stops. If we had
2207 set up a simulated single-step, we undo our damage. */
2210 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2212 CORE_ADDR pc
, next_pc
;
2214 if (insert_breakpoints_p
)
2216 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2217 next_pc
= mips_next_pc (pc
);
2219 insert_single_step_breakpoint (next_pc
);
2222 remove_single_step_breakpoints ();
2225 /* Test whether the PC points to the return instruction at the
2226 end of a function. */
2229 mips_about_to_return (CORE_ADDR pc
)
2231 if (mips_pc_is_mips16 (pc
))
2232 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2233 generates a "jr $ra"; other times it generates code to load
2234 the return address from the stack to an accessible register (such
2235 as $a3), then a "jr" using that register. This second case
2236 is almost impossible to distinguish from an indirect jump
2237 used for switch statements, so we don't even try. */
2238 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2240 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2244 /* This fencepost looks highly suspicious to me. Removing it also
2245 seems suspicious as it could affect remote debugging across serial
2249 heuristic_proc_start (CORE_ADDR pc
)
2256 pc
= ADDR_BITS_REMOVE (pc
);
2258 fence
= start_pc
- heuristic_fence_post
;
2262 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2263 fence
= VM_MIN_ADDRESS
;
2265 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2267 /* search back for previous return */
2268 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2269 if (start_pc
< fence
)
2271 /* It's not clear to me why we reach this point when
2272 stop_soon, but with this test, at least we
2273 don't print out warnings for every child forked (eg, on
2274 decstation). 22apr93 rich@cygnus.com. */
2275 if (stop_soon
== NO_STOP_QUIETLY
)
2277 static int blurb_printed
= 0;
2279 warning (_("GDB can't find the start of the function at 0x%s."),
2284 /* This actually happens frequently in embedded
2285 development, when you first connect to a board
2286 and your stack pointer and pc are nowhere in
2287 particular. This message needs to give people
2288 in that situation enough information to
2289 determine that it's no big deal. */
2290 printf_filtered ("\n\
2291 GDB is unable to find the start of the function at 0x%s\n\
2292 and thus can't determine the size of that function's stack frame.\n\
2293 This means that GDB may be unable to access that stack frame, or\n\
2294 the frames below it.\n\
2295 This problem is most likely caused by an invalid program counter or\n\
2297 However, if you think GDB should simply search farther back\n\
2298 from 0x%s for code which looks like the beginning of a\n\
2299 function, you can increase the range of the search using the `set\n\
2300 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2307 else if (mips_pc_is_mips16 (start_pc
))
2309 unsigned short inst
;
2311 /* On MIPS16, any one of the following is likely to be the
2312 start of a function:
2316 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2317 inst
= mips_fetch_instruction (start_pc
);
2318 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2319 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2320 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2321 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2323 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2324 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2329 else if (mips_about_to_return (start_pc
))
2331 /* Skip return and its delay slot. */
2332 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2339 struct mips_objfile_private
2345 /* According to the current ABI, should the type be passed in a
2346 floating-point register (assuming that there is space)? When there
2347 is no FPU, FP are not even considered as possible candidates for
2348 FP registers and, consequently this returns false - forces FP
2349 arguments into integer registers. */
2352 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2354 return ((typecode
== TYPE_CODE_FLT
2356 && (typecode
== TYPE_CODE_STRUCT
2357 || typecode
== TYPE_CODE_UNION
)
2358 && TYPE_NFIELDS (arg_type
) == 1
2359 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2361 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2364 /* On o32, argument passing in GPRs depends on the alignment of the type being
2365 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2368 mips_type_needs_double_align (struct type
*type
)
2370 enum type_code typecode
= TYPE_CODE (type
);
2372 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2374 else if (typecode
== TYPE_CODE_STRUCT
)
2376 if (TYPE_NFIELDS (type
) < 1)
2378 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2380 else if (typecode
== TYPE_CODE_UNION
)
2384 n
= TYPE_NFIELDS (type
);
2385 for (i
= 0; i
< n
; i
++)
2386 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2393 /* Adjust the address downward (direction of stack growth) so that it
2394 is correctly aligned for a new stack frame. */
2396 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2398 return align_down (addr
, 16);
2402 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2403 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2404 int nargs
, struct value
**args
, CORE_ADDR sp
,
2405 int struct_return
, CORE_ADDR struct_addr
)
2411 int stack_offset
= 0;
2412 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2413 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2415 /* For shared libraries, "t9" needs to point at the function
2417 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2419 /* Set the return address register to point to the entry point of
2420 the program, where a breakpoint lies in wait. */
2421 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2423 /* First ensure that the stack and structure return address (if any)
2424 are properly aligned. The stack has to be at least 64-bit
2425 aligned even on 32-bit machines, because doubles must be 64-bit
2426 aligned. For n32 and n64, stack frames need to be 128-bit
2427 aligned, so we round to this widest known alignment. */
2429 sp
= align_down (sp
, 16);
2430 struct_addr
= align_down (struct_addr
, 16);
2432 /* Now make space on the stack for the args. We allocate more
2433 than necessary for EABI, because the first few arguments are
2434 passed in registers, but that's OK. */
2435 for (argnum
= 0; argnum
< nargs
; argnum
++)
2436 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])),
2437 mips_stack_argsize (gdbarch
));
2438 sp
-= align_up (len
, 16);
2441 fprintf_unfiltered (gdb_stdlog
,
2442 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2443 paddr_nz (sp
), (long) align_up (len
, 16));
2445 /* Initialize the integer and float register pointers. */
2446 argreg
= MIPS_A0_REGNUM
;
2447 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2449 /* The struct_return pointer occupies the first parameter-passing reg. */
2453 fprintf_unfiltered (gdb_stdlog
,
2454 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2455 argreg
, paddr_nz (struct_addr
));
2456 write_register (argreg
++, struct_addr
);
2459 /* Now load as many as possible of the first arguments into
2460 registers, and push the rest onto the stack. Loop thru args
2461 from first to last. */
2462 for (argnum
= 0; argnum
< nargs
; argnum
++)
2464 const gdb_byte
*val
;
2465 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2466 struct value
*arg
= args
[argnum
];
2467 struct type
*arg_type
= check_typedef (value_type (arg
));
2468 int len
= TYPE_LENGTH (arg_type
);
2469 enum type_code typecode
= TYPE_CODE (arg_type
);
2472 fprintf_unfiltered (gdb_stdlog
,
2473 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2474 argnum
+ 1, len
, (int) typecode
);
2476 /* The EABI passes structures that do not fit in a register by
2478 if (len
> mips_abi_regsize (gdbarch
)
2479 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2481 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
2482 VALUE_ADDRESS (arg
));
2483 typecode
= TYPE_CODE_PTR
;
2484 len
= mips_abi_regsize (gdbarch
);
2487 fprintf_unfiltered (gdb_stdlog
, " push");
2490 val
= value_contents (arg
);
2492 /* 32-bit ABIs always start floating point arguments in an
2493 even-numbered floating point register. Round the FP register
2494 up before the check to see if there are any FP registers
2495 left. Non MIPS_EABI targets also pass the FP in the integer
2496 registers so also round up normal registers. */
2497 if (mips_abi_regsize (gdbarch
) < 8
2498 && fp_register_arg_p (typecode
, arg_type
))
2500 if ((float_argreg
& 1))
2504 /* Floating point arguments passed in registers have to be
2505 treated specially. On 32-bit architectures, doubles
2506 are passed in register pairs; the even register gets
2507 the low word, and the odd register gets the high word.
2508 On non-EABI processors, the first two floating point arguments are
2509 also copied to general registers, because MIPS16 functions
2510 don't use float registers for arguments. This duplication of
2511 arguments in general registers can't hurt non-MIPS16 functions
2512 because those registers are normally skipped. */
2513 /* MIPS_EABI squeezes a struct that contains a single floating
2514 point value into an FP register instead of pushing it onto the
2516 if (fp_register_arg_p (typecode
, arg_type
)
2517 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2519 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
2521 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2522 unsigned long regval
;
2524 /* Write the low word of the double to the even register(s). */
2525 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2527 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2528 float_argreg
, phex (regval
, 4));
2529 write_register (float_argreg
++, regval
);
2531 /* Write the high word of the double to the odd register(s). */
2532 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2534 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2535 float_argreg
, phex (regval
, 4));
2536 write_register (float_argreg
++, regval
);
2540 /* This is a floating point value that fits entirely
2541 in a single register. */
2542 /* On 32 bit ABI's the float_argreg is further adjusted
2543 above to ensure that it is even register aligned. */
2544 LONGEST regval
= extract_unsigned_integer (val
, len
);
2546 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2547 float_argreg
, phex (regval
, len
));
2548 write_register (float_argreg
++, regval
);
2553 /* Copy the argument to general registers or the stack in
2554 register-sized pieces. Large arguments are split between
2555 registers and stack. */
2556 /* Note: structs whose size is not a multiple of
2557 mips_abi_regsize() are treated specially: Irix cc passes
2558 them in registers where gcc sometimes puts them on the
2559 stack. For maximum compatibility, we will put them in
2561 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
2562 && (len
% mips_abi_regsize (gdbarch
) != 0));
2564 /* Note: Floating-point values that didn't fit into an FP
2565 register are only written to memory. */
2568 /* Remember if the argument was written to the stack. */
2569 int stack_used_p
= 0;
2570 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
2571 ? len
: mips_abi_regsize (gdbarch
));
2574 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2577 /* Write this portion of the argument to the stack. */
2578 if (argreg
> MIPS_LAST_ARG_REGNUM
2580 || fp_register_arg_p (typecode
, arg_type
))
2582 /* Should shorter than int integer values be
2583 promoted to int before being stored? */
2584 int longword_offset
= 0;
2587 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2589 if (mips_stack_argsize (gdbarch
) == 8
2590 && (typecode
== TYPE_CODE_INT
2591 || typecode
== TYPE_CODE_PTR
2592 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2593 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2594 else if ((typecode
== TYPE_CODE_STRUCT
2595 || typecode
== TYPE_CODE_UNION
)
2596 && (TYPE_LENGTH (arg_type
)
2597 < mips_stack_argsize (gdbarch
)))
2598 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2603 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2604 paddr_nz (stack_offset
));
2605 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2606 paddr_nz (longword_offset
));
2609 addr
= sp
+ stack_offset
+ longword_offset
;
2614 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2616 for (i
= 0; i
< partial_len
; i
++)
2618 fprintf_unfiltered (gdb_stdlog
, "%02x",
2622 write_memory (addr
, val
, partial_len
);
2625 /* Note!!! This is NOT an else clause. Odd sized
2626 structs may go thru BOTH paths. Floating point
2627 arguments will not. */
2628 /* Write this portion of the argument to a general
2629 purpose register. */
2630 if (argreg
<= MIPS_LAST_ARG_REGNUM
2631 && !fp_register_arg_p (typecode
, arg_type
))
2634 extract_unsigned_integer (val
, partial_len
);
2637 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2640 mips_abi_regsize (gdbarch
)));
2641 write_register (argreg
, regval
);
2648 /* Compute the the offset into the stack at which we
2649 will copy the next parameter.
2651 In the new EABI (and the NABI32), the stack_offset
2652 only needs to be adjusted when it has been used. */
2655 stack_offset
+= align_up (partial_len
,
2656 mips_stack_argsize (gdbarch
));
2660 fprintf_unfiltered (gdb_stdlog
, "\n");
2663 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2665 /* Return adjusted stack pointer. */
2669 /* Determine the return value convention being used. */
2671 static enum return_value_convention
2672 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2673 struct type
*type
, struct regcache
*regcache
,
2674 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2676 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2677 return RETURN_VALUE_STRUCT_CONVENTION
;
2679 memset (readbuf
, 0, TYPE_LENGTH (type
));
2680 return RETURN_VALUE_REGISTER_CONVENTION
;
2684 /* N32/N64 ABI stuff. */
2687 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2688 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2689 int nargs
, struct value
**args
, CORE_ADDR sp
,
2690 int struct_return
, CORE_ADDR struct_addr
)
2696 int stack_offset
= 0;
2697 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2698 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2700 /* For shared libraries, "t9" needs to point at the function
2702 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2704 /* Set the return address register to point to the entry point of
2705 the program, where a breakpoint lies in wait. */
2706 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2708 /* First ensure that the stack and structure return address (if any)
2709 are properly aligned. The stack has to be at least 64-bit
2710 aligned even on 32-bit machines, because doubles must be 64-bit
2711 aligned. For n32 and n64, stack frames need to be 128-bit
2712 aligned, so we round to this widest known alignment. */
2714 sp
= align_down (sp
, 16);
2715 struct_addr
= align_down (struct_addr
, 16);
2717 /* Now make space on the stack for the args. */
2718 for (argnum
= 0; argnum
< nargs
; argnum
++)
2719 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])),
2720 mips_stack_argsize (gdbarch
));
2721 sp
-= align_up (len
, 16);
2724 fprintf_unfiltered (gdb_stdlog
,
2725 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2726 paddr_nz (sp
), (long) align_up (len
, 16));
2728 /* Initialize the integer and float register pointers. */
2729 argreg
= MIPS_A0_REGNUM
;
2730 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2732 /* The struct_return pointer occupies the first parameter-passing reg. */
2736 fprintf_unfiltered (gdb_stdlog
,
2737 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2738 argreg
, paddr_nz (struct_addr
));
2739 write_register (argreg
++, struct_addr
);
2742 /* Now load as many as possible of the first arguments into
2743 registers, and push the rest onto the stack. Loop thru args
2744 from first to last. */
2745 for (argnum
= 0; argnum
< nargs
; argnum
++)
2747 const gdb_byte
*val
;
2748 struct value
*arg
= args
[argnum
];
2749 struct type
*arg_type
= check_typedef (value_type (arg
));
2750 int len
= TYPE_LENGTH (arg_type
);
2751 enum type_code typecode
= TYPE_CODE (arg_type
);
2754 fprintf_unfiltered (gdb_stdlog
,
2755 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2756 argnum
+ 1, len
, (int) typecode
);
2758 val
= value_contents (arg
);
2760 if (fp_register_arg_p (typecode
, arg_type
)
2761 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2763 /* This is a floating point value that fits entirely
2764 in a single register. */
2765 /* On 32 bit ABI's the float_argreg is further adjusted
2766 above to ensure that it is even register aligned. */
2767 LONGEST regval
= extract_unsigned_integer (val
, len
);
2769 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2770 float_argreg
, phex (regval
, len
));
2771 write_register (float_argreg
++, regval
);
2774 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2775 argreg
, phex (regval
, len
));
2776 write_register (argreg
, regval
);
2781 /* Copy the argument to general registers or the stack in
2782 register-sized pieces. Large arguments are split between
2783 registers and stack. */
2784 /* Note: structs whose size is not a multiple of
2785 mips_abi_regsize() are treated specially: Irix cc passes
2786 them in registers where gcc sometimes puts them on the
2787 stack. For maximum compatibility, we will put them in
2789 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
2790 && (len
% mips_abi_regsize (gdbarch
) != 0));
2791 /* Note: Floating-point values that didn't fit into an FP
2792 register are only written to memory. */
2795 /* Rememer if the argument was written to the stack. */
2796 int stack_used_p
= 0;
2797 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
2798 ? len
: mips_abi_regsize (gdbarch
));
2801 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2804 /* Write this portion of the argument to the stack. */
2805 if (argreg
> MIPS_LAST_ARG_REGNUM
2807 || fp_register_arg_p (typecode
, arg_type
))
2809 /* Should shorter than int integer values be
2810 promoted to int before being stored? */
2811 int longword_offset
= 0;
2814 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2816 if (mips_stack_argsize (gdbarch
) == 8
2817 && (typecode
== TYPE_CODE_INT
2818 || typecode
== TYPE_CODE_PTR
2819 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2820 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2825 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2826 paddr_nz (stack_offset
));
2827 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2828 paddr_nz (longword_offset
));
2831 addr
= sp
+ stack_offset
+ longword_offset
;
2836 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2838 for (i
= 0; i
< partial_len
; i
++)
2840 fprintf_unfiltered (gdb_stdlog
, "%02x",
2844 write_memory (addr
, val
, partial_len
);
2847 /* Note!!! This is NOT an else clause. Odd sized
2848 structs may go thru BOTH paths. Floating point
2849 arguments will not. */
2850 /* Write this portion of the argument to a general
2851 purpose register. */
2852 if (argreg
<= MIPS_LAST_ARG_REGNUM
2853 && !fp_register_arg_p (typecode
, arg_type
))
2856 extract_unsigned_integer (val
, partial_len
);
2858 /* A non-floating-point argument being passed in a
2859 general register. If a struct or union, and if
2860 the remaining length is smaller than the register
2861 size, we have to adjust the register value on
2864 It does not seem to be necessary to do the
2865 same for integral types.
2867 cagney/2001-07-23: gdb/179: Also, GCC, when
2868 outputting LE O32 with sizeof (struct) <
2869 mips_abi_regsize(), generates a left shift as
2870 part of storing the argument in a register a
2871 register (the left shift isn't generated when
2872 sizeof (struct) >= mips_abi_regsize()). Since
2873 it is quite possible that this is GCC
2874 contradicting the LE/O32 ABI, GDB has not been
2875 adjusted to accommodate this. Either someone
2876 needs to demonstrate that the LE/O32 ABI
2877 specifies such a left shift OR this new ABI gets
2878 identified as such and GDB gets tweaked
2881 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2882 && partial_len
< mips_abi_regsize (gdbarch
)
2883 && (typecode
== TYPE_CODE_STRUCT
||
2884 typecode
== TYPE_CODE_UNION
))
2885 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
2889 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2892 mips_abi_regsize (gdbarch
)));
2893 write_register (argreg
, regval
);
2900 /* Compute the the offset into the stack at which we
2901 will copy the next parameter.
2903 In N32 (N64?), the stack_offset only needs to be
2904 adjusted when it has been used. */
2907 stack_offset
+= align_up (partial_len
,
2908 mips_stack_argsize (gdbarch
));
2912 fprintf_unfiltered (gdb_stdlog
, "\n");
2915 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2917 /* Return adjusted stack pointer. */
2921 static enum return_value_convention
2922 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
2923 struct type
*type
, struct regcache
*regcache
,
2924 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2926 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2927 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2928 || TYPE_CODE (type
) == TYPE_CODE_UNION
2929 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
2930 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2931 return RETURN_VALUE_STRUCT_CONVENTION
;
2932 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2933 && TYPE_LENGTH (type
) == 16
2934 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2936 /* A 128-bit floating-point value fills both $f0 and $f2. The
2937 two registers are used in the same as memory order, so the
2938 eight bytes with the lower memory address are in $f0. */
2940 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
2941 mips_xfer_register (regcache
,
2942 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
2943 8, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
2944 mips_xfer_register (regcache
,
2945 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 2,
2946 8, TARGET_BYTE_ORDER
, readbuf
? readbuf
+ 8 : readbuf
,
2947 writebuf
? writebuf
+ 8 : writebuf
, 0);
2948 return RETURN_VALUE_REGISTER_CONVENTION
;
2950 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2951 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2953 /* A floating-point value belongs in the least significant part
2956 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
2957 mips_xfer_register (regcache
,
2958 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
2960 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
2961 return RETURN_VALUE_REGISTER_CONVENTION
;
2963 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2964 && TYPE_NFIELDS (type
) <= 2
2965 && TYPE_NFIELDS (type
) >= 1
2966 && ((TYPE_NFIELDS (type
) == 1
2967 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2969 || (TYPE_NFIELDS (type
) == 2
2970 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2972 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
2974 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2976 /* A struct that contains one or two floats. Each value is part
2977 in the least significant part of their floating point
2981 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
2982 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
2984 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
2987 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
2989 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
2990 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
2991 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
2993 return RETURN_VALUE_REGISTER_CONVENTION
;
2995 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2996 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2998 /* A structure or union. Extract the left justified value,
2999 regardless of the byte order. I.e. DO NOT USE
3003 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3004 offset
< TYPE_LENGTH (type
);
3005 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3007 int xfer
= register_size (current_gdbarch
, regnum
);
3008 if (offset
+ xfer
> TYPE_LENGTH (type
))
3009 xfer
= TYPE_LENGTH (type
) - offset
;
3011 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3012 offset
, xfer
, regnum
);
3013 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3014 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3016 return RETURN_VALUE_REGISTER_CONVENTION
;
3020 /* A scalar extract each part but least-significant-byte
3024 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3025 offset
< TYPE_LENGTH (type
);
3026 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3028 int xfer
= register_size (current_gdbarch
, regnum
);
3029 if (offset
+ xfer
> TYPE_LENGTH (type
))
3030 xfer
= TYPE_LENGTH (type
) - offset
;
3032 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3033 offset
, xfer
, regnum
);
3034 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3035 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3037 return RETURN_VALUE_REGISTER_CONVENTION
;
3041 /* O32 ABI stuff. */
3044 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3045 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3046 int nargs
, struct value
**args
, CORE_ADDR sp
,
3047 int struct_return
, CORE_ADDR struct_addr
)
3053 int stack_offset
= 0;
3054 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3055 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3057 /* For shared libraries, "t9" needs to point at the function
3059 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3061 /* Set the return address register to point to the entry point of
3062 the program, where a breakpoint lies in wait. */
3063 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3065 /* First ensure that the stack and structure return address (if any)
3066 are properly aligned. The stack has to be at least 64-bit
3067 aligned even on 32-bit machines, because doubles must be 64-bit
3068 aligned. For n32 and n64, stack frames need to be 128-bit
3069 aligned, so we round to this widest known alignment. */
3071 sp
= align_down (sp
, 16);
3072 struct_addr
= align_down (struct_addr
, 16);
3074 /* Now make space on the stack for the args. */
3075 for (argnum
= 0; argnum
< nargs
; argnum
++)
3076 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])),
3077 mips_stack_argsize (gdbarch
));
3078 sp
-= align_up (len
, 16);
3081 fprintf_unfiltered (gdb_stdlog
,
3082 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3083 paddr_nz (sp
), (long) align_up (len
, 16));
3085 /* Initialize the integer and float register pointers. */
3086 argreg
= MIPS_A0_REGNUM
;
3087 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3089 /* The struct_return pointer occupies the first parameter-passing reg. */
3093 fprintf_unfiltered (gdb_stdlog
,
3094 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3095 argreg
, paddr_nz (struct_addr
));
3096 write_register (argreg
++, struct_addr
);
3097 stack_offset
+= mips_stack_argsize (gdbarch
);
3100 /* Now load as many as possible of the first arguments into
3101 registers, and push the rest onto the stack. Loop thru args
3102 from first to last. */
3103 for (argnum
= 0; argnum
< nargs
; argnum
++)
3105 const gdb_byte
*val
;
3106 struct value
*arg
= args
[argnum
];
3107 struct type
*arg_type
= check_typedef (value_type (arg
));
3108 int len
= TYPE_LENGTH (arg_type
);
3109 enum type_code typecode
= TYPE_CODE (arg_type
);
3112 fprintf_unfiltered (gdb_stdlog
,
3113 "mips_o32_push_dummy_call: %d len=%d type=%d",
3114 argnum
+ 1, len
, (int) typecode
);
3116 val
= value_contents (arg
);
3118 /* 32-bit ABIs always start floating point arguments in an
3119 even-numbered floating point register. Round the FP register
3120 up before the check to see if there are any FP registers
3121 left. O32/O64 targets also pass the FP in the integer
3122 registers so also round up normal registers. */
3123 if (mips_abi_regsize (gdbarch
) < 8
3124 && fp_register_arg_p (typecode
, arg_type
))
3126 if ((float_argreg
& 1))
3130 /* Floating point arguments passed in registers have to be
3131 treated specially. On 32-bit architectures, doubles
3132 are passed in register pairs; the even register gets
3133 the low word, and the odd register gets the high word.
3134 On O32/O64, the first two floating point arguments are
3135 also copied to general registers, because MIPS16 functions
3136 don't use float registers for arguments. This duplication of
3137 arguments in general registers can't hurt non-MIPS16 functions
3138 because those registers are normally skipped. */
3140 if (fp_register_arg_p (typecode
, arg_type
)
3141 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3143 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3145 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3146 unsigned long regval
;
3148 /* Write the low word of the double to the even register(s). */
3149 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3151 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3152 float_argreg
, phex (regval
, 4));
3153 write_register (float_argreg
++, regval
);
3155 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3156 argreg
, phex (regval
, 4));
3157 write_register (argreg
++, regval
);
3159 /* Write the high word of the double to the odd register(s). */
3160 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3162 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3163 float_argreg
, phex (regval
, 4));
3164 write_register (float_argreg
++, regval
);
3167 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3168 argreg
, phex (regval
, 4));
3169 write_register (argreg
++, regval
);
3173 /* This is a floating point value that fits entirely
3174 in a single register. */
3175 /* On 32 bit ABI's the float_argreg is further adjusted
3176 above to ensure that it is even register aligned. */
3177 LONGEST regval
= extract_unsigned_integer (val
, len
);
3179 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3180 float_argreg
, phex (regval
, len
));
3181 write_register (float_argreg
++, regval
);
3182 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3183 registers for each argument. The below is (my
3184 guess) to ensure that the corresponding integer
3185 register has reserved the same space. */
3187 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3188 argreg
, phex (regval
, len
));
3189 write_register (argreg
, regval
);
3190 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3192 /* Reserve space for the FP register. */
3193 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3197 /* Copy the argument to general registers or the stack in
3198 register-sized pieces. Large arguments are split between
3199 registers and stack. */
3200 /* Note: structs whose size is not a multiple of
3201 mips_abi_regsize() are treated specially: Irix cc passes
3202 them in registers where gcc sometimes puts them on the
3203 stack. For maximum compatibility, we will put them in
3205 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3206 && (len
% mips_abi_regsize (gdbarch
) != 0));
3207 /* Structures should be aligned to eight bytes (even arg registers)
3208 on MIPS_ABI_O32, if their first member has double precision. */
3209 if (mips_abi_regsize (gdbarch
) < 8
3210 && mips_type_needs_double_align (arg_type
))
3215 /* Note: Floating-point values that didn't fit into an FP
3216 register are only written to memory. */
3219 /* Remember if the argument was written to the stack. */
3220 int stack_used_p
= 0;
3221 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3222 ? len
: mips_abi_regsize (gdbarch
));
3225 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3228 /* Write this portion of the argument to the stack. */
3229 if (argreg
> MIPS_LAST_ARG_REGNUM
3231 || fp_register_arg_p (typecode
, arg_type
))
3233 /* Should shorter than int integer values be
3234 promoted to int before being stored? */
3235 int longword_offset
= 0;
3238 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3240 if (mips_stack_argsize (gdbarch
) == 8
3241 && (typecode
== TYPE_CODE_INT
3242 || typecode
== TYPE_CODE_PTR
3243 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3244 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3249 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3250 paddr_nz (stack_offset
));
3251 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3252 paddr_nz (longword_offset
));
3255 addr
= sp
+ stack_offset
+ longword_offset
;
3260 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3262 for (i
= 0; i
< partial_len
; i
++)
3264 fprintf_unfiltered (gdb_stdlog
, "%02x",
3268 write_memory (addr
, val
, partial_len
);
3271 /* Note!!! This is NOT an else clause. Odd sized
3272 structs may go thru BOTH paths. Floating point
3273 arguments will not. */
3274 /* Write this portion of the argument to a general
3275 purpose register. */
3276 if (argreg
<= MIPS_LAST_ARG_REGNUM
3277 && !fp_register_arg_p (typecode
, arg_type
))
3279 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3280 /* Value may need to be sign extended, because
3281 mips_isa_regsize() != mips_abi_regsize(). */
3283 /* A non-floating-point argument being passed in a
3284 general register. If a struct or union, and if
3285 the remaining length is smaller than the register
3286 size, we have to adjust the register value on
3289 It does not seem to be necessary to do the
3290 same for integral types.
3292 Also don't do this adjustment on O64 binaries.
3294 cagney/2001-07-23: gdb/179: Also, GCC, when
3295 outputting LE O32 with sizeof (struct) <
3296 mips_abi_regsize(), generates a left shift as
3297 part of storing the argument in a register a
3298 register (the left shift isn't generated when
3299 sizeof (struct) >= mips_abi_regsize()). Since
3300 it is quite possible that this is GCC
3301 contradicting the LE/O32 ABI, GDB has not been
3302 adjusted to accommodate this. Either someone
3303 needs to demonstrate that the LE/O32 ABI
3304 specifies such a left shift OR this new ABI gets
3305 identified as such and GDB gets tweaked
3308 if (mips_abi_regsize (gdbarch
) < 8
3309 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3310 && partial_len
< mips_abi_regsize (gdbarch
)
3311 && (typecode
== TYPE_CODE_STRUCT
||
3312 typecode
== TYPE_CODE_UNION
))
3313 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3317 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3320 mips_abi_regsize (gdbarch
)));
3321 write_register (argreg
, regval
);
3324 /* Prevent subsequent floating point arguments from
3325 being passed in floating point registers. */
3326 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3332 /* Compute the the offset into the stack at which we
3333 will copy the next parameter.
3335 In older ABIs, the caller reserved space for
3336 registers that contained arguments. This was loosely
3337 refered to as their "home". Consequently, space is
3338 always allocated. */
3340 stack_offset
+= align_up (partial_len
,
3341 mips_stack_argsize (gdbarch
));
3345 fprintf_unfiltered (gdb_stdlog
, "\n");
3348 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3350 /* Return adjusted stack pointer. */
3354 static enum return_value_convention
3355 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3356 struct regcache
*regcache
,
3357 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3359 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3361 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3362 || TYPE_CODE (type
) == TYPE_CODE_UNION
3363 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3364 return RETURN_VALUE_STRUCT_CONVENTION
;
3365 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3366 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3368 /* A single-precision floating-point value. It fits in the
3369 least significant part of FP0. */
3371 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3372 mips_xfer_register (regcache
,
3373 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3375 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3376 return RETURN_VALUE_REGISTER_CONVENTION
;
3378 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3379 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3381 /* A double-precision floating-point value. The most
3382 significant part goes in FP1, and the least significant in
3385 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3386 switch (TARGET_BYTE_ORDER
)
3388 case BFD_ENDIAN_LITTLE
:
3389 mips_xfer_register (regcache
,
3390 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3391 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3392 mips_xfer_register (regcache
,
3393 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3394 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3396 case BFD_ENDIAN_BIG
:
3397 mips_xfer_register (regcache
,
3398 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3399 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3400 mips_xfer_register (regcache
,
3401 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3402 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3405 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3407 return RETURN_VALUE_REGISTER_CONVENTION
;
3410 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3411 && TYPE_NFIELDS (type
) <= 2
3412 && TYPE_NFIELDS (type
) >= 1
3413 && ((TYPE_NFIELDS (type
) == 1
3414 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3416 || (TYPE_NFIELDS (type
) == 2
3417 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3419 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3421 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3423 /* A struct that contains one or two floats. Each value is part
3424 in the least significant part of their floating point
3426 gdb_byte reg
[MAX_REGISTER_SIZE
];
3429 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3430 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3432 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3435 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3437 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3438 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3439 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3441 return RETURN_VALUE_REGISTER_CONVENTION
;
3445 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3446 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3448 /* A structure or union. Extract the left justified value,
3449 regardless of the byte order. I.e. DO NOT USE
3453 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3454 offset
< TYPE_LENGTH (type
);
3455 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3457 int xfer
= register_size (current_gdbarch
, regnum
);
3458 if (offset
+ xfer
> TYPE_LENGTH (type
))
3459 xfer
= TYPE_LENGTH (type
) - offset
;
3461 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3462 offset
, xfer
, regnum
);
3463 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3464 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3466 return RETURN_VALUE_REGISTER_CONVENTION
;
3471 /* A scalar extract each part but least-significant-byte
3472 justified. o32 thinks registers are 4 byte, regardless of
3473 the ISA. mips_stack_argsize controls this. */
3476 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3477 offset
< TYPE_LENGTH (type
);
3478 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
3480 int xfer
= mips_stack_argsize (gdbarch
);
3481 if (offset
+ xfer
> TYPE_LENGTH (type
))
3482 xfer
= TYPE_LENGTH (type
) - offset
;
3484 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3485 offset
, xfer
, regnum
);
3486 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3487 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3489 return RETURN_VALUE_REGISTER_CONVENTION
;
3493 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3497 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3498 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3500 struct value
**args
, CORE_ADDR sp
,
3501 int struct_return
, CORE_ADDR struct_addr
)
3507 int stack_offset
= 0;
3508 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3509 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3511 /* For shared libraries, "t9" needs to point at the function
3513 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3515 /* Set the return address register to point to the entry point of
3516 the program, where a breakpoint lies in wait. */
3517 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3519 /* First ensure that the stack and structure return address (if any)
3520 are properly aligned. The stack has to be at least 64-bit
3521 aligned even on 32-bit machines, because doubles must be 64-bit
3522 aligned. For n32 and n64, stack frames need to be 128-bit
3523 aligned, so we round to this widest known alignment. */
3525 sp
= align_down (sp
, 16);
3526 struct_addr
= align_down (struct_addr
, 16);
3528 /* Now make space on the stack for the args. */
3529 for (argnum
= 0; argnum
< nargs
; argnum
++)
3530 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])),
3531 mips_stack_argsize (gdbarch
));
3532 sp
-= align_up (len
, 16);
3535 fprintf_unfiltered (gdb_stdlog
,
3536 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3537 paddr_nz (sp
), (long) align_up (len
, 16));
3539 /* Initialize the integer and float register pointers. */
3540 argreg
= MIPS_A0_REGNUM
;
3541 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3543 /* The struct_return pointer occupies the first parameter-passing reg. */
3547 fprintf_unfiltered (gdb_stdlog
,
3548 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3549 argreg
, paddr_nz (struct_addr
));
3550 write_register (argreg
++, struct_addr
);
3551 stack_offset
+= mips_stack_argsize (gdbarch
);
3554 /* Now load as many as possible of the first arguments into
3555 registers, and push the rest onto the stack. Loop thru args
3556 from first to last. */
3557 for (argnum
= 0; argnum
< nargs
; argnum
++)
3559 const gdb_byte
*val
;
3560 struct value
*arg
= args
[argnum
];
3561 struct type
*arg_type
= check_typedef (value_type (arg
));
3562 int len
= TYPE_LENGTH (arg_type
);
3563 enum type_code typecode
= TYPE_CODE (arg_type
);
3566 fprintf_unfiltered (gdb_stdlog
,
3567 "mips_o64_push_dummy_call: %d len=%d type=%d",
3568 argnum
+ 1, len
, (int) typecode
);
3570 val
= value_contents (arg
);
3572 /* 32-bit ABIs always start floating point arguments in an
3573 even-numbered floating point register. Round the FP register
3574 up before the check to see if there are any FP registers
3575 left. O32/O64 targets also pass the FP in the integer
3576 registers so also round up normal registers. */
3577 if (mips_abi_regsize (gdbarch
) < 8
3578 && fp_register_arg_p (typecode
, arg_type
))
3580 if ((float_argreg
& 1))
3584 /* Floating point arguments passed in registers have to be
3585 treated specially. On 32-bit architectures, doubles
3586 are passed in register pairs; the even register gets
3587 the low word, and the odd register gets the high word.
3588 On O32/O64, the first two floating point arguments are
3589 also copied to general registers, because MIPS16 functions
3590 don't use float registers for arguments. This duplication of
3591 arguments in general registers can't hurt non-MIPS16 functions
3592 because those registers are normally skipped. */
3594 if (fp_register_arg_p (typecode
, arg_type
)
3595 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3597 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3599 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3600 unsigned long regval
;
3602 /* Write the low word of the double to the even register(s). */
3603 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3605 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3606 float_argreg
, phex (regval
, 4));
3607 write_register (float_argreg
++, regval
);
3609 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3610 argreg
, phex (regval
, 4));
3611 write_register (argreg
++, regval
);
3613 /* Write the high word of the double to the odd register(s). */
3614 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3616 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3617 float_argreg
, phex (regval
, 4));
3618 write_register (float_argreg
++, regval
);
3621 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3622 argreg
, phex (regval
, 4));
3623 write_register (argreg
++, regval
);
3627 /* This is a floating point value that fits entirely
3628 in a single register. */
3629 /* On 32 bit ABI's the float_argreg is further adjusted
3630 above to ensure that it is even register aligned. */
3631 LONGEST regval
= extract_unsigned_integer (val
, len
);
3633 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3634 float_argreg
, phex (regval
, len
));
3635 write_register (float_argreg
++, regval
);
3636 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3637 registers for each argument. The below is (my
3638 guess) to ensure that the corresponding integer
3639 register has reserved the same space. */
3641 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3642 argreg
, phex (regval
, len
));
3643 write_register (argreg
, regval
);
3644 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3646 /* Reserve space for the FP register. */
3647 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3651 /* Copy the argument to general registers or the stack in
3652 register-sized pieces. Large arguments are split between
3653 registers and stack. */
3654 /* Note: structs whose size is not a multiple of
3655 mips_abi_regsize() are treated specially: Irix cc passes
3656 them in registers where gcc sometimes puts them on the
3657 stack. For maximum compatibility, we will put them in
3659 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3660 && (len
% mips_abi_regsize (gdbarch
) != 0));
3661 /* Structures should be aligned to eight bytes (even arg registers)
3662 on MIPS_ABI_O32, if their first member has double precision. */
3663 if (mips_abi_regsize (gdbarch
) < 8
3664 && mips_type_needs_double_align (arg_type
))
3669 /* Note: Floating-point values that didn't fit into an FP
3670 register are only written to memory. */
3673 /* Remember if the argument was written to the stack. */
3674 int stack_used_p
= 0;
3675 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3676 ? len
: mips_abi_regsize (gdbarch
));
3679 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3682 /* Write this portion of the argument to the stack. */
3683 if (argreg
> MIPS_LAST_ARG_REGNUM
3685 || fp_register_arg_p (typecode
, arg_type
))
3687 /* Should shorter than int integer values be
3688 promoted to int before being stored? */
3689 int longword_offset
= 0;
3692 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3694 if (mips_stack_argsize (gdbarch
) == 8
3695 && (typecode
== TYPE_CODE_INT
3696 || typecode
== TYPE_CODE_PTR
3697 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3698 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3703 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3704 paddr_nz (stack_offset
));
3705 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3706 paddr_nz (longword_offset
));
3709 addr
= sp
+ stack_offset
+ longword_offset
;
3714 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3716 for (i
= 0; i
< partial_len
; i
++)
3718 fprintf_unfiltered (gdb_stdlog
, "%02x",
3722 write_memory (addr
, val
, partial_len
);
3725 /* Note!!! This is NOT an else clause. Odd sized
3726 structs may go thru BOTH paths. Floating point
3727 arguments will not. */
3728 /* Write this portion of the argument to a general
3729 purpose register. */
3730 if (argreg
<= MIPS_LAST_ARG_REGNUM
3731 && !fp_register_arg_p (typecode
, arg_type
))
3733 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3734 /* Value may need to be sign extended, because
3735 mips_isa_regsize() != mips_abi_regsize(). */
3737 /* A non-floating-point argument being passed in a
3738 general register. If a struct or union, and if
3739 the remaining length is smaller than the register
3740 size, we have to adjust the register value on
3743 It does not seem to be necessary to do the
3744 same for integral types. */
3746 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3747 && partial_len
< mips_abi_regsize (gdbarch
)
3748 && (typecode
== TYPE_CODE_STRUCT
||
3749 typecode
== TYPE_CODE_UNION
))
3750 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3754 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3757 mips_abi_regsize (gdbarch
)));
3758 write_register (argreg
, regval
);
3761 /* Prevent subsequent floating point arguments from
3762 being passed in floating point registers. */
3763 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3769 /* Compute the the offset into the stack at which we
3770 will copy the next parameter.
3772 In older ABIs, the caller reserved space for
3773 registers that contained arguments. This was loosely
3774 refered to as their "home". Consequently, space is
3775 always allocated. */
3777 stack_offset
+= align_up (partial_len
,
3778 mips_stack_argsize (gdbarch
));
3782 fprintf_unfiltered (gdb_stdlog
, "\n");
3785 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3787 /* Return adjusted stack pointer. */
3791 static enum return_value_convention
3792 mips_o64_return_value (struct gdbarch
*gdbarch
,
3793 struct type
*type
, struct regcache
*regcache
,
3794 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3796 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3798 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3799 || TYPE_CODE (type
) == TYPE_CODE_UNION
3800 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3801 return RETURN_VALUE_STRUCT_CONVENTION
;
3802 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
3804 /* A floating-point value. It fits in the least significant
3807 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3808 mips_xfer_register (regcache
,
3809 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3811 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3812 return RETURN_VALUE_REGISTER_CONVENTION
;
3816 /* A scalar extract each part but least-significant-byte
3820 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3821 offset
< TYPE_LENGTH (type
);
3822 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
3824 int xfer
= mips_stack_argsize (gdbarch
);
3825 if (offset
+ xfer
> TYPE_LENGTH (type
))
3826 xfer
= TYPE_LENGTH (type
) - offset
;
3828 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3829 offset
, xfer
, regnum
);
3830 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3831 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3833 return RETURN_VALUE_REGISTER_CONVENTION
;
3837 /* Floating point register management.
3839 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3840 64bit operations, these early MIPS cpus treat fp register pairs
3841 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3842 registers and offer a compatibility mode that emulates the MIPS2 fp
3843 model. When operating in MIPS2 fp compat mode, later cpu's split
3844 double precision floats into two 32-bit chunks and store them in
3845 consecutive fp regs. To display 64-bit floats stored in this
3846 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3847 Throw in user-configurable endianness and you have a real mess.
3849 The way this works is:
3850 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3851 double-precision value will be split across two logical registers.
3852 The lower-numbered logical register will hold the low-order bits,
3853 regardless of the processor's endianness.
3854 - If we are on a 64-bit processor, and we are looking for a
3855 single-precision value, it will be in the low ordered bits
3856 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3857 save slot in memory.
3858 - If we are in 64-bit mode, everything is straightforward.
3860 Note that this code only deals with "live" registers at the top of the
3861 stack. We will attempt to deal with saved registers later, when
3862 the raw/cooked register interface is in place. (We need a general
3863 interface that can deal with dynamic saved register sizes -- fp
3864 regs could be 32 bits wide in one frame and 64 on the frame above
3867 static struct type
*
3868 mips_float_register_type (void)
3870 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3871 return builtin_type_ieee_single_big
;
3873 return builtin_type_ieee_single_little
;
3876 static struct type
*
3877 mips_double_register_type (void)
3879 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3880 return builtin_type_ieee_double_big
;
3882 return builtin_type_ieee_double_little
;
3885 /* Copy a 32-bit single-precision value from the current frame
3886 into rare_buffer. */
3889 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3890 gdb_byte
*rare_buffer
)
3892 int raw_size
= register_size (current_gdbarch
, regno
);
3893 gdb_byte
*raw_buffer
= alloca (raw_size
);
3895 if (!frame_register_read (frame
, regno
, raw_buffer
))
3896 error (_("can't read register %d (%s)"), regno
, REGISTER_NAME (regno
));
3899 /* We have a 64-bit value for this register. Find the low-order
3903 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3908 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3912 memcpy (rare_buffer
, raw_buffer
, 4);
3916 /* Copy a 64-bit double-precision value from the current frame into
3917 rare_buffer. This may include getting half of it from the next
3921 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
3922 gdb_byte
*rare_buffer
)
3924 int raw_size
= register_size (current_gdbarch
, regno
);
3926 if (raw_size
== 8 && !mips2_fp_compat ())
3928 /* We have a 64-bit value for this register, and we should use
3930 if (!frame_register_read (frame
, regno
, rare_buffer
))
3931 error (_("can't read register %d (%s)"), regno
, REGISTER_NAME (regno
));
3935 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
3936 internal_error (__FILE__
, __LINE__
,
3937 _("mips_read_fp_register_double: bad access to "
3938 "odd-numbered FP register"));
3940 /* mips_read_fp_register_single will find the correct 32 bits from
3942 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3944 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
3945 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
3949 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
3950 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
3956 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
3958 { /* do values for FP (float) regs */
3959 gdb_byte
*raw_buffer
;
3960 double doub
, flt1
; /* doubles extracted from raw hex data */
3963 raw_buffer
= alloca (2 * register_size (current_gdbarch
,
3964 mips_regnum (current_gdbarch
)->fp0
));
3966 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
3967 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
3970 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
3972 /* 4-byte registers: Print hex and floating. Also print even
3973 numbered registers as doubles. */
3974 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3975 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3977 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
3980 fprintf_filtered (file
, " flt: ");
3982 fprintf_filtered (file
, " <invalid float> ");
3984 fprintf_filtered (file
, "%-17.9g", flt1
);
3986 if (regnum
% 2 == 0)
3988 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3989 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
3992 fprintf_filtered (file
, " dbl: ");
3994 fprintf_filtered (file
, "<invalid double>");
3996 fprintf_filtered (file
, "%-24.17g", doub
);
4001 /* Eight byte registers: print each one as hex, float and double. */
4002 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4003 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4005 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4006 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4009 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4012 fprintf_filtered (file
, " flt: ");
4014 fprintf_filtered (file
, "<invalid float>");
4016 fprintf_filtered (file
, "%-17.9g", flt1
);
4018 fprintf_filtered (file
, " dbl: ");
4020 fprintf_filtered (file
, "<invalid double>");
4022 fprintf_filtered (file
, "%-24.17g", doub
);
4027 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4028 int regnum
, int all
)
4030 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4031 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4034 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4036 mips_print_fp_register (file
, frame
, regnum
);
4040 /* Get the data in raw format. */
4041 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4043 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4047 fputs_filtered (REGISTER_NAME (regnum
), file
);
4049 /* The problem with printing numeric register names (r26, etc.) is that
4050 the user can't use them on input. Probably the best solution is to
4051 fix it so that either the numeric or the funky (a2, etc.) names
4052 are accepted on input. */
4053 if (regnum
< MIPS_NUMREGS
)
4054 fprintf_filtered (file
, "(r%d): ", regnum
);
4056 fprintf_filtered (file
, ": ");
4058 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4060 register_size (current_gdbarch
,
4061 regnum
) - register_size (current_gdbarch
, regnum
);
4065 print_scalar_formatted (raw_buffer
+ offset
,
4066 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4070 /* Replacement for generic do_registers_info.
4071 Print regs in pretty columns. */
4074 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4077 fprintf_filtered (file
, " ");
4078 mips_print_fp_register (file
, frame
, regnum
);
4079 fprintf_filtered (file
, "\n");
4084 /* Print a row's worth of GP (int) registers, with name labels above */
4087 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4090 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4091 /* do values for GP (int) regs */
4092 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4093 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4097 /* For GP registers, we print a separate row of names above the vals */
4098 for (col
= 0, regnum
= start_regnum
;
4099 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4101 if (*REGISTER_NAME (regnum
) == '\0')
4102 continue; /* unused register */
4103 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4105 break; /* end the row: reached FP register */
4107 fprintf_filtered (file
, " ");
4108 fprintf_filtered (file
,
4109 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4110 REGISTER_NAME (regnum
));
4117 /* print the R0 to R31 names */
4118 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4119 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4121 fprintf_filtered (file
, "\n ");
4123 /* now print the values in hex, 4 or 8 to the row */
4124 for (col
= 0, regnum
= start_regnum
;
4125 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4127 if (*REGISTER_NAME (regnum
) == '\0')
4128 continue; /* unused register */
4129 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4131 break; /* end row: reached FP register */
4132 /* OK: get the data in raw format. */
4133 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4134 error (_("can't read register %d (%s)"), regnum
, REGISTER_NAME (regnum
));
4135 /* pad small registers */
4137 byte
< (mips_abi_regsize (current_gdbarch
)
4138 - register_size (current_gdbarch
, regnum
)); byte
++)
4139 printf_filtered (" ");
4140 /* Now print the register value in hex, endian order. */
4141 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4143 register_size (current_gdbarch
,
4144 regnum
) - register_size (current_gdbarch
, regnum
);
4145 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4146 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4148 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4150 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4151 fprintf_filtered (file
, " ");
4154 if (col
> 0) /* ie. if we actually printed anything... */
4155 fprintf_filtered (file
, "\n");
4160 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4163 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4164 struct frame_info
*frame
, int regnum
, int all
)
4166 if (regnum
!= -1) /* do one specified register */
4168 gdb_assert (regnum
>= NUM_REGS
);
4169 if (*(REGISTER_NAME (regnum
)) == '\0')
4170 error (_("Not a valid register for the current processor type"));
4172 mips_print_register (file
, frame
, regnum
, 0);
4173 fprintf_filtered (file
, "\n");
4176 /* do all (or most) registers */
4179 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4181 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4184 if (all
) /* true for "INFO ALL-REGISTERS" command */
4185 regnum
= print_fp_register_row (file
, frame
, regnum
);
4187 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4190 regnum
= print_gp_register_row (file
, frame
, regnum
);
4195 /* Is this a branch with a delay slot? */
4198 is_delayed (unsigned long insn
)
4201 for (i
= 0; i
< NUMOPCODES
; ++i
)
4202 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4203 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4205 return (i
< NUMOPCODES
4206 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4207 | INSN_COND_BRANCH_DELAY
4208 | INSN_COND_BRANCH_LIKELY
)));
4212 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4213 struct frame_info
*frame
)
4215 CORE_ADDR pc
= get_frame_pc (frame
);
4216 gdb_byte buf
[MIPS_INSN32_SIZE
];
4218 /* There is no branch delay slot on MIPS16. */
4219 if (mips_pc_is_mips16 (pc
))
4222 if (!breakpoint_here_p (pc
+ 4))
4225 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4226 /* If error reading memory, guess that it is not a delayed
4229 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4232 /* To skip prologues, I use this predicate. Returns either PC itself
4233 if the code at PC does not look like a function prologue; otherwise
4234 returns an address that (if we're lucky) follows the prologue. If
4235 LENIENT, then we must skip everything which is involved in setting
4236 up the frame (it's OK to skip more, just so long as we don't skip
4237 anything which might clobber the registers which are being saved.
4238 We must skip more in the case where part of the prologue is in the
4239 delay slot of a non-prologue instruction). */
4242 mips_skip_prologue (CORE_ADDR pc
)
4245 CORE_ADDR func_addr
;
4247 /* See if we can determine the end of the prologue via the symbol table.
4248 If so, then return either PC, or the PC after the prologue, whichever
4250 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4252 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4253 if (post_prologue_pc
!= 0)
4254 return max (pc
, post_prologue_pc
);
4257 /* Can't determine prologue from the symbol table, need to examine
4260 /* Find an upper limit on the function prologue using the debug
4261 information. If the debug information could not be used to provide
4262 that bound, then use an arbitrary large number as the upper bound. */
4263 limit_pc
= skip_prologue_using_sal (pc
);
4265 limit_pc
= pc
+ 100; /* Magic. */
4267 if (mips_pc_is_mips16 (pc
))
4268 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4270 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4273 /* Root of all "set mips "/"show mips " commands. This will eventually be
4274 used for all MIPS-specific commands. */
4277 show_mips_command (char *args
, int from_tty
)
4279 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4283 set_mips_command (char *args
, int from_tty
)
4286 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4287 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4290 /* Commands to show/set the MIPS FPU type. */
4293 show_mipsfpu_command (char *args
, int from_tty
)
4296 switch (MIPS_FPU_TYPE
)
4298 case MIPS_FPU_SINGLE
:
4299 fpu
= "single-precision";
4301 case MIPS_FPU_DOUBLE
:
4302 fpu
= "double-precision";
4305 fpu
= "absent (none)";
4308 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4310 if (mips_fpu_type_auto
)
4312 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4316 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4321 set_mipsfpu_command (char *args
, int from_tty
)
4324 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4325 show_mipsfpu_command (args
, from_tty
);
4329 set_mipsfpu_single_command (char *args
, int from_tty
)
4331 struct gdbarch_info info
;
4332 gdbarch_info_init (&info
);
4333 mips_fpu_type
= MIPS_FPU_SINGLE
;
4334 mips_fpu_type_auto
= 0;
4335 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4336 instead of relying on globals. Doing that would let generic code
4337 handle the search for this specific architecture. */
4338 if (!gdbarch_update_p (info
))
4339 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4343 set_mipsfpu_double_command (char *args
, int from_tty
)
4345 struct gdbarch_info info
;
4346 gdbarch_info_init (&info
);
4347 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4348 mips_fpu_type_auto
= 0;
4349 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4350 instead of relying on globals. Doing that would let generic code
4351 handle the search for this specific architecture. */
4352 if (!gdbarch_update_p (info
))
4353 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4357 set_mipsfpu_none_command (char *args
, int from_tty
)
4359 struct gdbarch_info info
;
4360 gdbarch_info_init (&info
);
4361 mips_fpu_type
= MIPS_FPU_NONE
;
4362 mips_fpu_type_auto
= 0;
4363 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4364 instead of relying on globals. Doing that would let generic code
4365 handle the search for this specific architecture. */
4366 if (!gdbarch_update_p (info
))
4367 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4371 set_mipsfpu_auto_command (char *args
, int from_tty
)
4373 mips_fpu_type_auto
= 1;
4376 /* Attempt to identify the particular processor model by reading the
4377 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4378 the relevant processor still exists (it dates back to '94) and
4379 secondly this is not the way to do this. The processor type should
4380 be set by forcing an architecture change. */
4383 deprecated_mips_set_processor_regs_hack (void)
4385 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4388 prid
= read_register (MIPS_PRID_REGNUM
);
4390 if ((prid
& ~0xf) == 0x700)
4391 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4394 /* Just like reinit_frame_cache, but with the right arguments to be
4395 callable as an sfunc. */
4398 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4399 struct cmd_list_element
*c
)
4401 reinit_frame_cache ();
4405 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4407 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4409 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4410 disassembler needs to be able to locally determine the ISA, and
4411 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4413 if (mips_pc_is_mips16 (memaddr
))
4414 info
->mach
= bfd_mach_mips16
;
4416 /* Round down the instruction address to the appropriate boundary. */
4417 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4419 /* Set the disassembler options. */
4420 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4422 /* Set up the disassembler info, so that we get the right
4423 register names from libopcodes. */
4424 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4425 info
->disassembler_options
= "gpr-names=n32";
4427 info
->disassembler_options
= "gpr-names=64";
4428 info
->flavour
= bfd_target_elf_flavour
;
4431 /* This string is not recognized explicitly by the disassembler,
4432 but it tells the disassembler to not try to guess the ABI from
4433 the bfd elf headers, such that, if the user overrides the ABI
4434 of a program linked as NewABI, the disassembly will follow the
4435 register naming conventions specified by the user. */
4436 info
->disassembler_options
= "gpr-names=32";
4438 /* Call the appropriate disassembler based on the target endian-ness. */
4439 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4440 return print_insn_big_mips (memaddr
, info
);
4442 return print_insn_little_mips (memaddr
, info
);
4445 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4446 counter value to determine whether a 16- or 32-bit breakpoint should be
4447 used. It returns a pointer to a string of bytes that encode a breakpoint
4448 instruction, stores the length of the string to *lenptr, and adjusts pc
4449 (if necessary) to point to the actual memory location where the
4450 breakpoint should be inserted. */
4452 static const gdb_byte
*
4453 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4455 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4457 if (mips_pc_is_mips16 (*pcptr
))
4459 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4460 *pcptr
= unmake_mips16_addr (*pcptr
);
4461 *lenptr
= sizeof (mips16_big_breakpoint
);
4462 return mips16_big_breakpoint
;
4466 /* The IDT board uses an unusual breakpoint value, and
4467 sometimes gets confused when it sees the usual MIPS
4468 breakpoint instruction. */
4469 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4470 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4471 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4473 *lenptr
= sizeof (big_breakpoint
);
4475 if (strcmp (target_shortname
, "mips") == 0)
4476 return idt_big_breakpoint
;
4477 else if (strcmp (target_shortname
, "ddb") == 0
4478 || strcmp (target_shortname
, "pmon") == 0
4479 || strcmp (target_shortname
, "lsi") == 0)
4480 return pmon_big_breakpoint
;
4482 return big_breakpoint
;
4487 if (mips_pc_is_mips16 (*pcptr
))
4489 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4490 *pcptr
= unmake_mips16_addr (*pcptr
);
4491 *lenptr
= sizeof (mips16_little_breakpoint
);
4492 return mips16_little_breakpoint
;
4496 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4497 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4498 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4500 *lenptr
= sizeof (little_breakpoint
);
4502 if (strcmp (target_shortname
, "mips") == 0)
4503 return idt_little_breakpoint
;
4504 else if (strcmp (target_shortname
, "ddb") == 0
4505 || strcmp (target_shortname
, "pmon") == 0
4506 || strcmp (target_shortname
, "lsi") == 0)
4507 return pmon_little_breakpoint
;
4509 return little_breakpoint
;
4514 /* If PC is in a mips16 call or return stub, return the address of the target
4515 PC, which is either the callee or the caller. There are several
4516 cases which must be handled:
4518 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4519 target PC is in $31 ($ra).
4520 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4521 and the target PC is in $2.
4522 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4523 before the jal instruction, this is effectively a call stub
4524 and the the target PC is in $2. Otherwise this is effectively
4525 a return stub and the target PC is in $18.
4527 See the source code for the stubs in gcc/config/mips/mips16.S for
4531 mips_skip_trampoline_code (CORE_ADDR pc
)
4534 CORE_ADDR start_addr
;
4536 /* Find the starting address and name of the function containing the PC. */
4537 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4540 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4541 target PC is in $31 ($ra). */
4542 if (strcmp (name
, "__mips16_ret_sf") == 0
4543 || strcmp (name
, "__mips16_ret_df") == 0)
4544 return read_signed_register (MIPS_RA_REGNUM
);
4546 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4548 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4549 and the target PC is in $2. */
4550 if (name
[19] >= '0' && name
[19] <= '9')
4551 return read_signed_register (2);
4553 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4554 before the jal instruction, this is effectively a call stub
4555 and the the target PC is in $2. Otherwise this is effectively
4556 a return stub and the target PC is in $18. */
4557 else if (name
[19] == 's' || name
[19] == 'd')
4559 if (pc
== start_addr
)
4561 /* Check if the target of the stub is a compiler-generated
4562 stub. Such a stub for a function bar might have a name
4563 like __fn_stub_bar, and might look like this:
4568 la $1,bar (becomes a lui/addiu pair)
4570 So scan down to the lui/addi and extract the target
4571 address from those two instructions. */
4573 CORE_ADDR target_pc
= read_signed_register (2);
4577 /* See if the name of the target function is __fn_stub_*. */
4578 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4581 if (strncmp (name
, "__fn_stub_", 10) != 0
4582 && strcmp (name
, "etext") != 0
4583 && strcmp (name
, "_etext") != 0)
4586 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4587 The limit on the search is arbitrarily set to 20
4588 instructions. FIXME. */
4589 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
4591 inst
= mips_fetch_instruction (target_pc
);
4592 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4593 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4594 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4595 return pc
| (inst
& 0xffff); /* low word */
4598 /* Couldn't find the lui/addui pair, so return stub address. */
4602 /* This is the 'return' part of a call stub. The return
4603 address is in $r18. */
4604 return read_signed_register (18);
4607 return 0; /* not a stub */
4610 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4611 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4614 mips_stab_reg_to_regnum (int num
)
4617 if (num
>= 0 && num
< 32)
4619 else if (num
>= 38 && num
< 70)
4620 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4622 regnum
= mips_regnum (current_gdbarch
)->hi
;
4624 regnum
= mips_regnum (current_gdbarch
)->lo
;
4626 /* This will hopefully (eventually) provoke a warning. Should
4627 we be calling complaint() here? */
4628 return NUM_REGS
+ NUM_PSEUDO_REGS
;
4629 return NUM_REGS
+ regnum
;
4633 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4634 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4637 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4640 if (num
>= 0 && num
< 32)
4642 else if (num
>= 32 && num
< 64)
4643 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4645 regnum
= mips_regnum (current_gdbarch
)->hi
;
4647 regnum
= mips_regnum (current_gdbarch
)->lo
;
4649 /* This will hopefully (eventually) provoke a warning. Should we
4650 be calling complaint() here? */
4651 return NUM_REGS
+ NUM_PSEUDO_REGS
;
4652 return NUM_REGS
+ regnum
;
4656 mips_register_sim_regno (int regnum
)
4658 /* Only makes sense to supply raw registers. */
4659 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
4660 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4661 decide if it is valid. Should instead define a standard sim/gdb
4662 register numbering scheme. */
4663 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
4664 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
4667 return LEGACY_SIM_REGNO_IGNORE
;
4671 /* Convert an integer into an address. Extracting the value signed
4672 guarantees a correctly sign extended address. */
4675 mips_integer_to_address (struct gdbarch
*gdbarch
,
4676 struct type
*type
, const gdb_byte
*buf
)
4678 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
4682 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4684 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4685 const char *name
= bfd_get_section_name (abfd
, sect
);
4687 if (*abip
!= MIPS_ABI_UNKNOWN
)
4690 if (strncmp (name
, ".mdebug.", 8) != 0)
4693 if (strcmp (name
, ".mdebug.abi32") == 0)
4694 *abip
= MIPS_ABI_O32
;
4695 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4696 *abip
= MIPS_ABI_N32
;
4697 else if (strcmp (name
, ".mdebug.abi64") == 0)
4698 *abip
= MIPS_ABI_N64
;
4699 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4700 *abip
= MIPS_ABI_O64
;
4701 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4702 *abip
= MIPS_ABI_EABI32
;
4703 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4704 *abip
= MIPS_ABI_EABI64
;
4706 warning (_("unsupported ABI %s."), name
+ 8);
4710 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
4712 int *lbp
= (int *) obj
;
4713 const char *name
= bfd_get_section_name (abfd
, sect
);
4715 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
4717 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
4719 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
4720 warning (_("unrecognized .gcc_compiled_longXX"));
4723 static enum mips_abi
4724 global_mips_abi (void)
4728 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4729 if (mips_abi_strings
[i
] == mips_abi_string
)
4730 return (enum mips_abi
) i
;
4732 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
4736 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
4738 static struct target_desc
*tdesc_gp32
, *tdesc_gp64
;
4740 if (tdesc_gp32
== NULL
)
4742 /* Create feature sets with the appropriate properties. The values
4743 are not important. */
4745 tdesc_gp32
= allocate_target_description ();
4746 set_tdesc_property (tdesc_gp32
, PROPERTY_GP32
, "");
4748 tdesc_gp64
= allocate_target_description ();
4749 set_tdesc_property (tdesc_gp64
, PROPERTY_GP64
, "");
4752 /* If the size matches the set of 32-bit or 64-bit integer registers,
4753 assume that's what we've got. */
4754 register_remote_g_packet_guess (gdbarch
, 38 * 4, tdesc_gp32
);
4755 register_remote_g_packet_guess (gdbarch
, 38 * 8, tdesc_gp64
);
4757 /* If the size matches the full set of registers GDB traditionally
4758 knows about, including floating point, for either 32-bit or
4759 64-bit, assume that's what we've got. */
4760 register_remote_g_packet_guess (gdbarch
, 90 * 4, tdesc_gp32
);
4761 register_remote_g_packet_guess (gdbarch
, 90 * 8, tdesc_gp64
);
4763 /* Otherwise we don't have a useful guess. */
4766 static struct gdbarch
*
4767 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4769 struct gdbarch
*gdbarch
;
4770 struct gdbarch_tdep
*tdep
;
4772 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4774 enum mips_fpu_type fpu_type
;
4776 /* First of all, extract the elf_flags, if available. */
4777 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4778 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4779 else if (arches
!= NULL
)
4780 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
4784 fprintf_unfiltered (gdb_stdlog
,
4785 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
4787 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4788 switch ((elf_flags
& EF_MIPS_ABI
))
4790 case E_MIPS_ABI_O32
:
4791 found_abi
= MIPS_ABI_O32
;
4793 case E_MIPS_ABI_O64
:
4794 found_abi
= MIPS_ABI_O64
;
4796 case E_MIPS_ABI_EABI32
:
4797 found_abi
= MIPS_ABI_EABI32
;
4799 case E_MIPS_ABI_EABI64
:
4800 found_abi
= MIPS_ABI_EABI64
;
4803 if ((elf_flags
& EF_MIPS_ABI2
))
4804 found_abi
= MIPS_ABI_N32
;
4806 found_abi
= MIPS_ABI_UNKNOWN
;
4810 /* GCC creates a pseudo-section whose name describes the ABI. */
4811 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4812 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
4814 /* If we have no useful BFD information, use the ABI from the last
4815 MIPS architecture (if there is one). */
4816 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
4817 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
4819 /* Try the architecture for any hint of the correct ABI. */
4820 if (found_abi
== MIPS_ABI_UNKNOWN
4821 && info
.bfd_arch_info
!= NULL
4822 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4824 switch (info
.bfd_arch_info
->mach
)
4826 case bfd_mach_mips3900
:
4827 found_abi
= MIPS_ABI_EABI32
;
4829 case bfd_mach_mips4100
:
4830 case bfd_mach_mips5000
:
4831 found_abi
= MIPS_ABI_EABI64
;
4833 case bfd_mach_mips8000
:
4834 case bfd_mach_mips10000
:
4835 /* On Irix, ELF64 executables use the N64 ABI. The
4836 pseudo-sections which describe the ABI aren't present
4837 on IRIX. (Even for executables created by gcc.) */
4838 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4839 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4840 found_abi
= MIPS_ABI_N64
;
4842 found_abi
= MIPS_ABI_N32
;
4847 /* Default 64-bit objects to N64 instead of O32. */
4848 if (found_abi
== MIPS_ABI_UNKNOWN
4849 && info
.abfd
!= NULL
4850 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4851 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4852 found_abi
= MIPS_ABI_N64
;
4855 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
4858 /* What has the user specified from the command line? */
4859 wanted_abi
= global_mips_abi ();
4861 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
4864 /* Now that we have found what the ABI for this binary would be,
4865 check whether the user is overriding it. */
4866 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
4867 mips_abi
= wanted_abi
;
4868 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
4869 mips_abi
= found_abi
;
4871 mips_abi
= MIPS_ABI_O32
;
4873 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
4876 /* Also used when doing an architecture lookup. */
4878 fprintf_unfiltered (gdb_stdlog
,
4879 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
4880 mips64_transfers_32bit_regs_p
);
4882 /* Determine the MIPS FPU type. */
4883 if (!mips_fpu_type_auto
)
4884 fpu_type
= mips_fpu_type
;
4885 else if (info
.bfd_arch_info
!= NULL
4886 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4887 switch (info
.bfd_arch_info
->mach
)
4889 case bfd_mach_mips3900
:
4890 case bfd_mach_mips4100
:
4891 case bfd_mach_mips4111
:
4892 case bfd_mach_mips4120
:
4893 fpu_type
= MIPS_FPU_NONE
;
4895 case bfd_mach_mips4650
:
4896 fpu_type
= MIPS_FPU_SINGLE
;
4899 fpu_type
= MIPS_FPU_DOUBLE
;
4902 else if (arches
!= NULL
)
4903 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
4905 fpu_type
= MIPS_FPU_DOUBLE
;
4907 fprintf_unfiltered (gdb_stdlog
,
4908 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
4910 /* Check for blatant incompatibilities. */
4912 /* If we have only 32-bit registers, then we can't debug a 64-bit
4914 if (info
.target_desc
4915 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
4916 && mips_abi
!= MIPS_ABI_EABI32
4917 && mips_abi
!= MIPS_ABI_O32
)
4920 /* try to find a pre-existing architecture */
4921 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4923 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4925 /* MIPS needs to be pedantic about which ABI the object is
4927 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4929 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4931 /* Need to be pedantic about which register virtual size is
4933 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
4934 != mips64_transfers_32bit_regs_p
)
4936 /* Be pedantic about which FPU is selected. */
4937 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
4939 return arches
->gdbarch
;
4942 /* Need a new architecture. Fill in a target specific vector. */
4943 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4944 gdbarch
= gdbarch_alloc (&info
, tdep
);
4945 tdep
->elf_flags
= elf_flags
;
4946 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
4947 tdep
->found_abi
= found_abi
;
4948 tdep
->mips_abi
= mips_abi
;
4949 tdep
->mips_fpu_type
= fpu_type
;
4950 tdep
->register_size_valid_p
= 0;
4951 tdep
->register_size
= 0;
4953 if (info
.target_desc
)
4955 /* Some useful properties can be inferred from the target. */
4956 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
4958 tdep
->register_size_valid_p
= 1;
4959 tdep
->register_size
= 4;
4961 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
4963 tdep
->register_size_valid_p
= 1;
4964 tdep
->register_size
= 8;
4968 /* Initially set everything according to the default ABI/ISA. */
4969 set_gdbarch_short_bit (gdbarch
, 16);
4970 set_gdbarch_int_bit (gdbarch
, 32);
4971 set_gdbarch_float_bit (gdbarch
, 32);
4972 set_gdbarch_double_bit (gdbarch
, 64);
4973 set_gdbarch_long_double_bit (gdbarch
, 64);
4974 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
4975 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
4976 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
4978 set_gdbarch_elf_make_msymbol_special (gdbarch
,
4979 mips_elf_make_msymbol_special
);
4981 /* Fill in the OS dependant register numbers and names. */
4983 const char **reg_names
;
4984 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
4985 struct mips_regnum
);
4986 if (info
.osabi
== GDB_OSABI_IRIX
)
4991 regnum
->badvaddr
= 66;
4994 regnum
->fp_control_status
= 69;
4995 regnum
->fp_implementation_revision
= 70;
4997 reg_names
= mips_irix_reg_names
;
5001 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5002 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5003 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5004 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5005 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5006 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5007 regnum
->fp_control_status
= 70;
5008 regnum
->fp_implementation_revision
= 71;
5010 if (info
.bfd_arch_info
!= NULL
5011 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5012 reg_names
= mips_tx39_reg_names
;
5014 reg_names
= mips_generic_reg_names
;
5016 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5017 replaced by read_pc? */
5018 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5019 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5020 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5021 set_gdbarch_num_regs (gdbarch
, num_regs
);
5022 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5023 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5024 tdep
->mips_processor_reg_names
= reg_names
;
5025 tdep
->regnum
= regnum
;
5031 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5032 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5033 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5034 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5035 tdep
->default_mask_address_p
= 0;
5036 set_gdbarch_long_bit (gdbarch
, 32);
5037 set_gdbarch_ptr_bit (gdbarch
, 32);
5038 set_gdbarch_long_long_bit (gdbarch
, 64);
5041 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5042 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5043 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5044 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5045 tdep
->default_mask_address_p
= 0;
5046 set_gdbarch_long_bit (gdbarch
, 32);
5047 set_gdbarch_ptr_bit (gdbarch
, 32);
5048 set_gdbarch_long_long_bit (gdbarch
, 64);
5050 case MIPS_ABI_EABI32
:
5051 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5052 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5053 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5054 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5055 tdep
->default_mask_address_p
= 0;
5056 set_gdbarch_long_bit (gdbarch
, 32);
5057 set_gdbarch_ptr_bit (gdbarch
, 32);
5058 set_gdbarch_long_long_bit (gdbarch
, 64);
5060 case MIPS_ABI_EABI64
:
5061 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5062 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5063 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5064 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5065 tdep
->default_mask_address_p
= 0;
5066 set_gdbarch_long_bit (gdbarch
, 64);
5067 set_gdbarch_ptr_bit (gdbarch
, 64);
5068 set_gdbarch_long_long_bit (gdbarch
, 64);
5071 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5072 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5073 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5074 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5075 tdep
->default_mask_address_p
= 0;
5076 set_gdbarch_long_bit (gdbarch
, 32);
5077 set_gdbarch_ptr_bit (gdbarch
, 32);
5078 set_gdbarch_long_long_bit (gdbarch
, 64);
5079 set_gdbarch_long_double_bit (gdbarch
, 128);
5080 set_gdbarch_long_double_format (gdbarch
,
5081 &floatformat_n32n64_long_double_big
);
5084 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5085 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5086 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5087 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5088 tdep
->default_mask_address_p
= 0;
5089 set_gdbarch_long_bit (gdbarch
, 64);
5090 set_gdbarch_ptr_bit (gdbarch
, 64);
5091 set_gdbarch_long_long_bit (gdbarch
, 64);
5092 set_gdbarch_long_double_bit (gdbarch
, 128);
5093 set_gdbarch_long_double_format (gdbarch
,
5094 &floatformat_n32n64_long_double_big
);
5097 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5100 /* GCC creates a pseudo-section whose name specifies the size of
5101 longs, since -mlong32 or -mlong64 may be used independent of
5102 other options. How those options affect pointer sizes is ABI and
5103 architecture dependent, so use them to override the default sizes
5104 set by the ABI. This table shows the relationship between ABI,
5105 -mlongXX, and size of pointers:
5107 ABI -mlongXX ptr bits
5108 --- -------- --------
5122 Note that for o32 and eabi32, pointers are always 32 bits
5123 regardless of any -mlongXX option. For all others, pointers and
5124 longs are the same, as set by -mlongXX or set by defaults.
5127 if (info
.abfd
!= NULL
)
5131 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5134 set_gdbarch_long_bit (gdbarch
, long_bit
);
5138 case MIPS_ABI_EABI32
:
5143 case MIPS_ABI_EABI64
:
5144 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5147 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5152 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5153 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5156 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5157 flag in object files because to do so would make it impossible to
5158 link with libraries compiled without "-gp32". This is
5159 unnecessarily restrictive.
5161 We could solve this problem by adding "-gp32" multilibs to gcc,
5162 but to set this flag before gcc is built with such multilibs will
5163 break too many systems.''
5165 But even more unhelpfully, the default linker output target for
5166 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5167 for 64-bit programs - you need to change the ABI to change this,
5168 and not all gcc targets support that currently. Therefore using
5169 this flag to detect 32-bit mode would do the wrong thing given
5170 the current gcc - it would make GDB treat these 64-bit programs
5171 as 32-bit programs by default. */
5173 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5174 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5175 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5177 /* Add/remove bits from an address. The MIPS needs be careful to
5178 ensure that all 32 bit addresses are sign extended to 64 bits. */
5179 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5181 /* Unwind the frame. */
5182 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5183 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5185 /* Map debug register numbers onto internal register numbers. */
5186 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5187 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5188 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5189 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5190 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5191 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5192 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5193 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5195 /* MIPS version of CALL_DUMMY */
5197 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5198 replaced by a command, and all targets will default to on stack
5199 (regardless of the stack's execute status). */
5200 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5201 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5203 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5204 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5205 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5207 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5208 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5210 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5212 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5213 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5214 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5216 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5218 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5220 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5222 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5223 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5224 need to all be folded into the target vector. Since they are
5225 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5226 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5228 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5230 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5232 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5234 mips_register_g_packet_guesses (gdbarch
);
5236 /* Hook in OS ABI-specific overrides, if they have been registered. */
5237 gdbarch_init_osabi (info
, gdbarch
);
5239 /* Unwind the frame. */
5240 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5241 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5242 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5243 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5244 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5245 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5251 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5253 struct gdbarch_info info
;
5255 /* Force the architecture to update, and (if it's a MIPS architecture)
5256 mips_gdbarch_init will take care of the rest. */
5257 gdbarch_info_init (&info
);
5258 gdbarch_update_p (info
);
5261 /* Print out which MIPS ABI is in use. */
5264 show_mips_abi (struct ui_file
*file
,
5266 struct cmd_list_element
*ignored_cmd
,
5267 const char *ignored_value
)
5269 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5272 "The MIPS ABI is unknown because the current architecture "
5276 enum mips_abi global_abi
= global_mips_abi ();
5277 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5278 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5280 if (global_abi
== MIPS_ABI_UNKNOWN
)
5283 "The MIPS ABI is set automatically (currently \"%s\").\n",
5285 else if (global_abi
== actual_abi
)
5288 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5292 /* Probably shouldn't happen... */
5295 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5296 actual_abi_str
, mips_abi_strings
[global_abi
]);
5302 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5304 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5308 int ef_mips_32bitmode
;
5309 /* Determine the ISA. */
5310 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5328 /* Determine the size of a pointer. */
5329 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5330 fprintf_unfiltered (file
,
5331 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5333 fprintf_unfiltered (file
,
5334 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5336 fprintf_unfiltered (file
,
5337 "mips_dump_tdep: ef_mips_arch = %d\n",
5339 fprintf_unfiltered (file
,
5340 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5341 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5342 fprintf_unfiltered (file
,
5343 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5344 mips_mask_address_p (tdep
),
5345 tdep
->default_mask_address_p
);
5347 fprintf_unfiltered (file
,
5348 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5349 MIPS_DEFAULT_FPU_TYPE
,
5350 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5351 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5352 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5354 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5355 fprintf_unfiltered (file
,
5356 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5358 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5359 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5360 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5362 fprintf_unfiltered (file
,
5363 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5364 mips_stack_argsize (current_gdbarch
));
5367 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5370 _initialize_mips_tdep (void)
5372 static struct cmd_list_element
*mipsfpulist
= NULL
;
5373 struct cmd_list_element
*c
;
5375 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5376 if (MIPS_ABI_LAST
+ 1
5377 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5378 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
5380 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5382 mips_pdr_data
= register_objfile_data ();
5384 /* Add root prefix command for all "set mips"/"show mips" commands */
5385 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5386 _("Various MIPS specific commands."),
5387 &setmipscmdlist
, "set mips ", 0, &setlist
);
5389 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5390 _("Various MIPS specific commands."),
5391 &showmipscmdlist
, "show mips ", 0, &showlist
);
5393 /* Allow the user to override the saved register size. */
5394 add_setshow_enum_cmd ("saved-gpreg-size", class_obscure
,
5395 size_enums
, &mips_abi_regsize_string
, _("\
5396 Set size of general purpose registers saved on the stack."), _("\
5397 Show size of general purpose registers saved on the stack."), _("\
5398 This option can be set to one of:\n\
5399 32 - Force GDB to treat saved GP registers as 32-bit\n\
5400 64 - Force GDB to treat saved GP registers as 64-bit\n\
5401 auto - Allow GDB to use the target's default setting or autodetect the\n\
5402 saved GP register size from information contained in the\n\
5403 executable (default)."),
5405 NULL
, /* FIXME: i18n: Size of general purpose registers saved on the stack is %s. */
5406 &setmipscmdlist
, &showmipscmdlist
);
5408 /* Allow the user to override the argument stack size. */
5409 add_setshow_enum_cmd ("stack-arg-size", class_obscure
,
5410 size_enums
, &mips_stack_argsize_string
, _("\
5411 Set the amount of stack space reserved for each argument."), _("\
5412 Show the amount of stack space reserved for each argument."), _("\
5413 This option can be set to one of:\n\
5414 32 - Force GDB to allocate 32-bit chunks per argument\n\
5415 64 - Force GDB to allocate 64-bit chunks per argument\n\
5416 auto - Allow GDB to determine the correct setting from the current\n\
5417 target and executable (default)"),
5419 NULL
, /* FIXME: i18n: The amount of stack space reserved for each argument is %s. */
5420 &setmipscmdlist
, &showmipscmdlist
);
5422 /* Allow the user to override the ABI. */
5423 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
5424 &mips_abi_string
, _("\
5425 Set the MIPS ABI used by this program."), _("\
5426 Show the MIPS ABI used by this program."), _("\
5427 This option can be set to one of:\n\
5428 auto - the default ABI associated with the current binary\n\
5437 &setmipscmdlist
, &showmipscmdlist
);
5439 /* Let the user turn off floating point and set the fence post for
5440 heuristic_proc_start. */
5442 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5443 _("Set use of MIPS floating-point coprocessor."),
5444 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5445 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5446 _("Select single-precision MIPS floating-point coprocessor."),
5448 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5449 _("Select double-precision MIPS floating-point coprocessor."),
5451 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5452 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5453 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5454 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5455 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
5456 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5457 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5458 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5459 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5460 _("Select MIPS floating-point coprocessor automatically."),
5462 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5463 _("Show current use of MIPS floating-point coprocessor target."),
5466 /* We really would like to have both "0" and "unlimited" work, but
5467 command.c doesn't deal with that. So make it a var_zinteger
5468 because the user can always use "999999" or some such for unlimited. */
5469 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5470 &heuristic_fence_post
, _("\
5471 Set the distance searched for the start of a function."), _("\
5472 Show the distance searched for the start of a function."), _("\
5473 If you are debugging a stripped executable, GDB needs to search through the\n\
5474 program for the start of a function. This command sets the distance of the\n\
5475 search. The only need to set it is when debugging a stripped executable."),
5476 reinit_frame_cache_sfunc
,
5477 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5478 &setlist
, &showlist
);
5480 /* Allow the user to control whether the upper bits of 64-bit
5481 addresses should be zeroed. */
5482 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
5483 &mask_address_var
, _("\
5484 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5485 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5486 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5487 allow GDB to determine the correct value."),
5488 NULL
, show_mask_address
,
5489 &setmipscmdlist
, &showmipscmdlist
);
5491 /* Allow the user to control the size of 32 bit registers within the
5492 raw remote packet. */
5493 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
5494 &mips64_transfers_32bit_regs_p
, _("\
5495 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5497 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5499 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5500 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5501 64 bits for others. Use \"off\" to disable compatibility mode"),
5502 set_mips64_transfers_32bit_regs
,
5503 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
5504 &setlist
, &showlist
);
5506 /* Debug this files internals. */
5507 add_setshow_zinteger_cmd ("mips", class_maintenance
,
5509 Set mips debugging."), _("\
5510 Show mips debugging."), _("\
5511 When non-zero, mips specific debugging is enabled."),
5513 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
5514 &setdebuglist
, &showdebuglist
);