1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 /* Some MIPS boards don't support floating point while others only
146 support single-precision floating-point operations. */
150 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
151 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
152 MIPS_FPU_NONE
/* No floating point. */
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto
= 1;
159 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
161 static int mips_debug
= 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc
*mips_tdesc_gp32
;
169 struct target_desc
*mips_tdesc_gp64
;
171 /* MIPS specific per-architecture information */
174 /* from the elf header */
178 enum mips_abi mips_abi
;
179 enum mips_abi found_abi
;
180 enum mips_fpu_type mips_fpu_type
;
181 int mips_last_arg_regnum
;
182 int mips_last_fp_arg_regnum
;
183 int default_mask_address_p
;
184 /* Is the target using 64-bit raw integer registers but only
185 storing a left-aligned 32-bit value in each? */
186 int mips64_transfers_32bit_regs_p
;
187 /* Indexes for various registers. IRIX and embedded have
188 different values. This contains the "public" fields. Don't
189 add any that do not need to be public. */
190 const struct mips_regnum
*regnum
;
191 /* Register names table for the current register set. */
192 const char **mips_processor_reg_names
;
194 /* The size of register data available from the target, if known.
195 This doesn't quite obsolete the manual
196 mips64_transfers_32bit_regs_p, since that is documented to force
197 left alignment even for big endian (very strange). */
198 int register_size_valid_p
;
202 const struct mips_regnum
*
203 mips_regnum (struct gdbarch
*gdbarch
)
205 return gdbarch_tdep (gdbarch
)->regnum
;
209 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
211 return mips_regnum (gdbarch
)->fp0
+ 12;
214 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
215 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
217 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
219 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
221 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
223 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
224 functions to test, set, or clear bit 0 of addresses. */
227 is_mips16_addr (CORE_ADDR addr
)
233 unmake_mips16_addr (CORE_ADDR addr
)
235 return ((addr
) & ~(CORE_ADDR
) 1);
238 /* Return the MIPS ABI associated with GDBARCH. */
240 mips_abi (struct gdbarch
*gdbarch
)
242 return gdbarch_tdep (gdbarch
)->mips_abi
;
246 mips_isa_regsize (struct gdbarch
*gdbarch
)
248 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
250 /* If we know how big the registers are, use that size. */
251 if (tdep
->register_size_valid_p
)
252 return tdep
->register_size
;
254 /* Fall back to the previous behavior. */
255 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
256 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
259 /* Return the currently configured (or set) saved register size. */
262 mips_abi_regsize (struct gdbarch
*gdbarch
)
264 switch (mips_abi (gdbarch
))
266 case MIPS_ABI_EABI32
:
272 case MIPS_ABI_EABI64
:
274 case MIPS_ABI_UNKNOWN
:
277 internal_error (__FILE__
, __LINE__
, _("bad switch"));
281 /* Functions for setting and testing a bit in a minimal symbol that
282 marks it as 16-bit function. The MSB of the minimal symbol's
283 "info" field is used for this purpose.
285 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
286 i.e. refers to a 16-bit function, and sets a "special" bit in a
287 minimal symbol to mark it as a 16-bit function
289 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
292 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
294 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
296 MSYMBOL_INFO (msym
) = (char *)
297 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
298 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
303 msymbol_is_special (struct minimal_symbol
*msym
)
305 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
308 /* XFER a value from the big/little/left end of the register.
309 Depending on the size of the value it might occupy the entire
310 register or just part of it. Make an allowance for this, aligning
311 things accordingly. */
314 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
315 int reg_num
, int length
,
316 enum bfd_endian endian
, gdb_byte
*in
,
317 const gdb_byte
*out
, int buf_offset
)
321 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
322 /* Need to transfer the left or right part of the register, based on
323 the targets byte order. */
327 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
329 case BFD_ENDIAN_LITTLE
:
332 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
336 internal_error (__FILE__
, __LINE__
, _("bad switch"));
339 fprintf_unfiltered (gdb_stderr
,
340 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
341 reg_num
, reg_offset
, buf_offset
, length
);
342 if (mips_debug
&& out
!= NULL
)
345 fprintf_unfiltered (gdb_stdlog
, "out ");
346 for (i
= 0; i
< length
; i
++)
347 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
350 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
353 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
355 if (mips_debug
&& in
!= NULL
)
358 fprintf_unfiltered (gdb_stdlog
, "in ");
359 for (i
= 0; i
< length
; i
++)
360 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
363 fprintf_unfiltered (gdb_stdlog
, "\n");
366 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
367 compatiblity mode. A return value of 1 means that we have
368 physical 64-bit registers, but should treat them as 32-bit registers. */
371 mips2_fp_compat (struct frame_info
*frame
)
373 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
374 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
376 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
380 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
381 in all the places we deal with FP registers. PR gdb/413. */
382 /* Otherwise check the FR bit in the status register - it controls
383 the FP compatiblity mode. If it is clear we are in compatibility
385 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
392 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
394 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
396 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
398 static struct type
*mips_float_register_type (void);
399 static struct type
*mips_double_register_type (void);
401 /* The list of available "set mips " and "show mips " commands */
403 static struct cmd_list_element
*setmipscmdlist
= NULL
;
404 static struct cmd_list_element
*showmipscmdlist
= NULL
;
406 /* Integer registers 0 thru 31 are handled explicitly by
407 mips_register_name(). Processor specific registers 32 and above
408 are listed in the following tables. */
411 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
415 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
416 "sr", "lo", "hi", "bad", "cause", "pc",
417 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
418 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
419 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
420 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
421 "fsr", "fir", "" /*"fp" */ , "",
422 "", "", "", "", "", "", "", "",
423 "", "", "", "", "", "", "", "",
426 /* Names of IDT R3041 registers. */
428 static const char *mips_r3041_reg_names
[] = {
429 "sr", "lo", "hi", "bad", "cause", "pc",
430 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
431 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
432 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
433 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
434 "fsr", "fir", "", /*"fp" */ "",
435 "", "", "bus", "ccfg", "", "", "", "",
436 "", "", "port", "cmp", "", "", "epc", "prid",
439 /* Names of tx39 registers. */
441 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
442 "sr", "lo", "hi", "bad", "cause", "pc",
443 "", "", "", "", "", "", "", "",
444 "", "", "", "", "", "", "", "",
445 "", "", "", "", "", "", "", "",
446 "", "", "", "", "", "", "", "",
448 "", "", "", "", "", "", "", "",
449 "", "", "config", "cache", "debug", "depc", "epc", ""
452 /* Names of IRIX registers. */
453 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
454 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
455 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
456 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
457 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
458 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
462 /* Return the name of the register corresponding to REGNO. */
464 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
466 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
467 /* GPR names for all ABIs other than n32/n64. */
468 static char *mips_gpr_names
[] = {
469 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
470 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
471 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
472 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
475 /* GPR names for n32 and n64 ABIs. */
476 static char *mips_n32_n64_gpr_names
[] = {
477 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
478 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
479 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
480 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
483 enum mips_abi abi
= mips_abi (gdbarch
);
485 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
486 but then don't make the raw register names visible. */
487 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
488 if (regno
< gdbarch_num_regs (gdbarch
))
491 /* The MIPS integer registers are always mapped from 0 to 31. The
492 names of the registers (which reflects the conventions regarding
493 register use) vary depending on the ABI. */
494 if (0 <= rawnum
&& rawnum
< 32)
496 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
497 return mips_n32_n64_gpr_names
[rawnum
];
499 return mips_gpr_names
[rawnum
];
501 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
502 return tdesc_register_name (gdbarch
, rawnum
);
503 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
505 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
506 return tdep
->mips_processor_reg_names
[rawnum
- 32];
509 internal_error (__FILE__
, __LINE__
,
510 _("mips_register_name: bad register number %d"), rawnum
);
513 /* Return the groups that a MIPS register can be categorised into. */
516 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
517 struct reggroup
*reggroup
)
522 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
523 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
524 if (reggroup
== all_reggroup
)
526 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
527 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
528 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
529 (gdbarch), as not all architectures are multi-arch. */
530 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
531 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
532 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
534 if (reggroup
== float_reggroup
)
535 return float_p
&& pseudo
;
536 if (reggroup
== vector_reggroup
)
537 return vector_p
&& pseudo
;
538 if (reggroup
== general_reggroup
)
539 return (!vector_p
&& !float_p
) && pseudo
;
540 /* Save the pseudo registers. Need to make certain that any code
541 extracting register values from a saved register cache also uses
543 if (reggroup
== save_reggroup
)
544 return raw_p
&& pseudo
;
545 /* Restore the same pseudo register. */
546 if (reggroup
== restore_reggroup
)
547 return raw_p
&& pseudo
;
551 /* Return the groups that a MIPS register can be categorised into.
552 This version is only used if we have a target description which
553 describes real registers (and their groups). */
556 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
557 struct reggroup
*reggroup
)
559 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
560 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
563 /* Only save, restore, and display the pseudo registers. Need to
564 make certain that any code extracting register values from a
565 saved register cache also uses pseudo registers.
567 Note: saving and restoring the pseudo registers is slightly
568 strange; if we have 64 bits, we should save and restore all
569 64 bits. But this is hard and has little benefit. */
573 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
577 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
580 /* Map the symbol table registers which live in the range [1 *
581 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
582 registers. Take care of alignment and size problems. */
585 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
586 int cookednum
, gdb_byte
*buf
)
588 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
589 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
590 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
591 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
592 regcache_raw_read (regcache
, rawnum
, buf
);
593 else if (register_size (gdbarch
, rawnum
) >
594 register_size (gdbarch
, cookednum
))
596 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
597 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
598 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
600 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
603 internal_error (__FILE__
, __LINE__
, _("bad register size"));
607 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
608 struct regcache
*regcache
, int cookednum
,
611 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
612 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
613 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
614 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
615 regcache_raw_write (regcache
, rawnum
, buf
);
616 else if (register_size (gdbarch
, rawnum
) >
617 register_size (gdbarch
, cookednum
))
619 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
620 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
621 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
623 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
626 internal_error (__FILE__
, __LINE__
, _("bad register size"));
629 /* Table to translate MIPS16 register field to actual register number. */
630 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
632 /* Heuristic_proc_start may hunt through the text section for a long
633 time across a 2400 baud serial line. Allows the user to limit this
636 static unsigned int heuristic_fence_post
= 0;
638 /* Number of bytes of storage in the actual machine representation for
639 register N. NOTE: This defines the pseudo register type so need to
640 rebuild the architecture vector. */
642 static int mips64_transfers_32bit_regs_p
= 0;
645 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
646 struct cmd_list_element
*c
)
648 struct gdbarch_info info
;
649 gdbarch_info_init (&info
);
650 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
651 instead of relying on globals. Doing that would let generic code
652 handle the search for this specific architecture. */
653 if (!gdbarch_update_p (info
))
655 mips64_transfers_32bit_regs_p
= 0;
656 error (_("32-bit compatibility mode not supported"));
660 /* Convert to/from a register and the corresponding memory value. */
663 mips_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
665 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
666 && register_size (gdbarch
, regnum
) == 4
667 && (regnum
% gdbarch_num_regs (gdbarch
))
668 >= mips_regnum (gdbarch
)->fp0
669 && (regnum
% gdbarch_num_regs (gdbarch
))
670 < mips_regnum (gdbarch
)->fp0
+ 32
671 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
675 mips_register_to_value (struct frame_info
*frame
, int regnum
,
676 struct type
*type
, gdb_byte
*to
)
678 get_frame_register (frame
, regnum
+ 0, to
+ 4);
679 get_frame_register (frame
, regnum
+ 1, to
+ 0);
683 mips_value_to_register (struct frame_info
*frame
, int regnum
,
684 struct type
*type
, const gdb_byte
*from
)
686 put_frame_register (frame
, regnum
+ 0, from
+ 4);
687 put_frame_register (frame
, regnum
+ 1, from
+ 0);
690 /* Return the GDB type object for the "standard" data type of data in
694 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
696 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
697 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
698 && (regnum
% gdbarch_num_regs (gdbarch
))
699 < mips_regnum (gdbarch
)->fp0
+ 32)
701 /* The floating-point registers raw, or cooked, always match
702 mips_isa_regsize(), and also map 1:1, byte for byte. */
703 if (mips_isa_regsize (gdbarch
) == 4)
704 return builtin_type_ieee_single
;
706 return builtin_type_ieee_double
;
708 else if (regnum
< gdbarch_num_regs (gdbarch
))
710 /* The raw or ISA registers. These are all sized according to
712 if (mips_isa_regsize (gdbarch
) == 4)
713 return builtin_type_int32
;
715 return builtin_type_int64
;
719 /* The cooked or ABI registers. These are sized according to
720 the ABI (with a few complications). */
721 if (regnum
>= (gdbarch_num_regs (gdbarch
)
722 + mips_regnum (gdbarch
)->fp_control_status
)
723 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
724 /* The pseudo/cooked view of the embedded registers is always
725 32-bit. The raw view is handled below. */
726 return builtin_type_int32
;
727 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
728 /* The target, while possibly using a 64-bit register buffer,
729 is only transfering 32-bits of each integer register.
730 Reflect this in the cooked/pseudo (ABI) register value. */
731 return builtin_type_int32
;
732 else if (mips_abi_regsize (gdbarch
) == 4)
733 /* The ABI is restricted to 32-bit registers (the ISA could be
735 return builtin_type_int32
;
738 return builtin_type_int64
;
742 /* Return the GDB type for the pseudo register REGNUM, which is the
743 ABI-level view. This function is only called if there is a target
744 description which includes registers, so we know precisely the
745 types of hardware registers. */
748 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
750 const int num_regs
= gdbarch_num_regs (gdbarch
);
751 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
752 int rawnum
= regnum
% num_regs
;
753 struct type
*rawtype
;
755 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
757 /* Absent registers are still absent. */
758 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
759 if (TYPE_LENGTH (rawtype
) == 0)
762 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
763 /* Present the floating point registers however the hardware did;
764 do not try to convert between FPU layouts. */
767 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
769 /* The pseudo/cooked view of embedded registers is always
770 32-bit, even if the target transfers 64-bit values for them.
771 New targets relying on XML descriptions should only transfer
772 the necessary 32 bits, but older versions of GDB expected 64,
773 so allow the target to provide 64 bits without interfering
774 with the displayed type. */
775 return builtin_type_int32
;
778 /* Use pointer types for registers if we can. For n32 we can not,
779 since we do not have a 64-bit pointer type. */
780 if (mips_abi_regsize (gdbarch
) == TYPE_LENGTH (builtin_type_void_data_ptr
))
782 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
783 return builtin_type_void_data_ptr
;
784 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
785 return builtin_type_void_func_ptr
;
788 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
789 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
790 return builtin_type_int32
;
792 /* For all other registers, pass through the hardware type. */
796 /* Should the upper word of 64-bit addresses be zeroed? */
797 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
800 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
802 switch (mask_address_var
)
804 case AUTO_BOOLEAN_TRUE
:
806 case AUTO_BOOLEAN_FALSE
:
809 case AUTO_BOOLEAN_AUTO
:
810 return tdep
->default_mask_address_p
;
812 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
818 show_mask_address (struct ui_file
*file
, int from_tty
,
819 struct cmd_list_element
*c
, const char *value
)
821 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
823 deprecated_show_value_hack (file
, from_tty
, c
, value
);
824 switch (mask_address_var
)
826 case AUTO_BOOLEAN_TRUE
:
827 printf_filtered ("The 32 bit mips address mask is enabled\n");
829 case AUTO_BOOLEAN_FALSE
:
830 printf_filtered ("The 32 bit mips address mask is disabled\n");
832 case AUTO_BOOLEAN_AUTO
:
834 ("The 32 bit address mask is set automatically. Currently %s\n",
835 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
838 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
843 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
846 mips_pc_is_mips16 (CORE_ADDR memaddr
)
848 struct minimal_symbol
*sym
;
850 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
851 if (is_mips16_addr (memaddr
))
854 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
855 the high bit of the info field. Use this to decide if the function is
856 MIPS16 or normal MIPS. */
857 sym
= lookup_minimal_symbol_by_pc (memaddr
);
859 return msymbol_is_special (sym
);
864 /* MIPS believes that the PC has a sign extended value. Perhaps the
865 all registers should be sign extended for simplicity? */
868 mips_read_pc (struct regcache
*regcache
)
871 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
872 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
877 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
879 return frame_unwind_register_signed
880 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
884 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
886 return frame_unwind_register_signed
887 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
890 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
891 dummy frame. The frame ID's base needs to match the TOS value
892 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
895 static struct frame_id
896 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
898 return frame_id_build
899 (frame_unwind_register_signed (next_frame
,
900 gdbarch_num_regs (gdbarch
)
902 frame_pc_unwind (next_frame
));
906 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
908 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
909 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
912 /* Fetch and return instruction from the specified location. If the PC
913 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
916 mips_fetch_instruction (CORE_ADDR addr
)
918 gdb_byte buf
[MIPS_INSN32_SIZE
];
922 if (mips_pc_is_mips16 (addr
))
924 instlen
= MIPS_INSN16_SIZE
;
925 addr
= unmake_mips16_addr (addr
);
928 instlen
= MIPS_INSN32_SIZE
;
929 status
= read_memory_nobpt (addr
, buf
, instlen
);
931 memory_error (status
, addr
);
932 return extract_unsigned_integer (buf
, instlen
);
935 /* These the fields of 32 bit mips instructions */
936 #define mips32_op(x) (x >> 26)
937 #define itype_op(x) (x >> 26)
938 #define itype_rs(x) ((x >> 21) & 0x1f)
939 #define itype_rt(x) ((x >> 16) & 0x1f)
940 #define itype_immediate(x) (x & 0xffff)
942 #define jtype_op(x) (x >> 26)
943 #define jtype_target(x) (x & 0x03ffffff)
945 #define rtype_op(x) (x >> 26)
946 #define rtype_rs(x) ((x >> 21) & 0x1f)
947 #define rtype_rt(x) ((x >> 16) & 0x1f)
948 #define rtype_rd(x) ((x >> 11) & 0x1f)
949 #define rtype_shamt(x) ((x >> 6) & 0x1f)
950 #define rtype_funct(x) (x & 0x3f)
953 mips32_relative_offset (ULONGEST inst
)
955 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
958 /* Determine where to set a single step breakpoint while considering
959 branch prediction. */
961 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
965 inst
= mips_fetch_instruction (pc
);
966 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
968 if (itype_op (inst
) >> 2 == 5)
969 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
971 op
= (itype_op (inst
) & 0x03);
986 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
987 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
989 int tf
= itype_rt (inst
) & 0x01;
990 int cnum
= itype_rt (inst
) >> 2;
992 get_frame_register_signed (frame
,
993 mips_regnum (get_frame_arch (frame
))->
995 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
997 if (((cond
>> cnum
) & 0x01) == tf
)
998 pc
+= mips32_relative_offset (inst
) + 4;
1003 pc
+= 4; /* Not a branch, next instruction is easy */
1006 { /* This gets way messy */
1008 /* Further subdivide into SPECIAL, REGIMM and other */
1009 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1011 case 0: /* SPECIAL */
1012 op
= rtype_funct (inst
);
1017 /* Set PC to that address */
1018 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1024 break; /* end SPECIAL */
1025 case 1: /* REGIMM */
1027 op
= itype_rt (inst
); /* branch condition */
1032 case 16: /* BLTZAL */
1033 case 18: /* BLTZALL */
1035 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1036 pc
+= mips32_relative_offset (inst
) + 4;
1038 pc
+= 8; /* after the delay slot */
1042 case 17: /* BGEZAL */
1043 case 19: /* BGEZALL */
1044 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1045 pc
+= mips32_relative_offset (inst
) + 4;
1047 pc
+= 8; /* after the delay slot */
1049 /* All of the other instructions in the REGIMM category */
1054 break; /* end REGIMM */
1059 reg
= jtype_target (inst
) << 2;
1060 /* Upper four bits get never changed... */
1061 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1064 /* FIXME case JALX : */
1067 reg
= jtype_target (inst
) << 2;
1068 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1069 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1071 break; /* The new PC will be alternate mode */
1072 case 4: /* BEQ, BEQL */
1074 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1075 get_frame_register_signed (frame
, itype_rt (inst
)))
1076 pc
+= mips32_relative_offset (inst
) + 4;
1080 case 5: /* BNE, BNEL */
1082 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1083 get_frame_register_signed (frame
, itype_rt (inst
)))
1084 pc
+= mips32_relative_offset (inst
) + 4;
1088 case 6: /* BLEZ, BLEZL */
1089 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1090 pc
+= mips32_relative_offset (inst
) + 4;
1096 greater_branch
: /* BGTZ, BGTZL */
1097 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1098 pc
+= mips32_relative_offset (inst
) + 4;
1105 } /* mips32_next_pc */
1107 /* Decoding the next place to set a breakpoint is irregular for the
1108 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1109 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1110 We dont want to set a single step instruction on the extend instruction
1114 /* Lots of mips16 instruction formats */
1115 /* Predicting jumps requires itype,ritype,i8type
1116 and their extensions extItype,extritype,extI8type
1118 enum mips16_inst_fmts
1120 itype
, /* 0 immediate 5,10 */
1121 ritype
, /* 1 5,3,8 */
1122 rrtype
, /* 2 5,3,3,5 */
1123 rritype
, /* 3 5,3,3,5 */
1124 rrrtype
, /* 4 5,3,3,3,2 */
1125 rriatype
, /* 5 5,3,3,1,4 */
1126 shifttype
, /* 6 5,3,3,3,2 */
1127 i8type
, /* 7 5,3,8 */
1128 i8movtype
, /* 8 5,3,3,5 */
1129 i8mov32rtype
, /* 9 5,3,5,3 */
1130 i64type
, /* 10 5,3,8 */
1131 ri64type
, /* 11 5,3,3,5 */
1132 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1133 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1134 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1135 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1136 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1137 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1138 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1139 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1140 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1141 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1143 /* I am heaping all the fields of the formats into one structure and
1144 then, only the fields which are involved in instruction extension */
1148 unsigned int regx
; /* Function in i8 type */
1153 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1154 for the bits which make up the immediatate extension. */
1157 extended_offset (unsigned int extension
)
1160 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1162 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1164 value
|= extension
& 0x01f; /* extract 4:0 */
1168 /* Only call this function if you know that this is an extendable
1169 instruction. It won't malfunction, but why make excess remote memory
1170 references? If the immediate operands get sign extended or something,
1171 do it after the extension is performed. */
1172 /* FIXME: Every one of these cases needs to worry about sign extension
1173 when the offset is to be used in relative addressing. */
1176 fetch_mips_16 (CORE_ADDR pc
)
1179 pc
&= 0xfffffffe; /* clear the low order bit */
1180 target_read_memory (pc
, buf
, 2);
1181 return extract_unsigned_integer (buf
, 2);
1185 unpack_mips16 (CORE_ADDR pc
,
1186 unsigned int extension
,
1188 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1193 switch (insn_format
)
1200 value
= extended_offset (extension
);
1201 value
= value
<< 11; /* rom for the original value */
1202 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1206 value
= inst
& 0x7ff;
1207 /* FIXME : Consider sign extension */
1216 { /* A register identifier and an offset */
1217 /* Most of the fields are the same as I type but the
1218 immediate value is of a different length */
1222 value
= extended_offset (extension
);
1223 value
= value
<< 8; /* from the original instruction */
1224 value
|= inst
& 0xff; /* eleven bits from instruction */
1225 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1226 if (value
& 0x4000) /* test the sign bit , bit 26 */
1228 value
&= ~0x3fff; /* remove the sign bit */
1234 value
= inst
& 0xff; /* 8 bits */
1235 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1236 /* FIXME: Do sign extension , this format needs it */
1237 if (value
& 0x80) /* THIS CONFUSES ME */
1239 value
&= 0xef; /* remove the sign bit */
1249 unsigned long value
;
1250 unsigned int nexthalf
;
1251 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1252 value
= value
<< 16;
1253 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1261 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1263 upk
->offset
= offset
;
1270 add_offset_16 (CORE_ADDR pc
, int offset
)
1272 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1276 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1277 unsigned int extension
, unsigned int insn
)
1279 int op
= (insn
>> 11);
1282 case 2: /* Branch */
1285 struct upk_mips16 upk
;
1286 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1287 offset
= upk
.offset
;
1293 pc
+= (offset
<< 1) + 2;
1296 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1298 struct upk_mips16 upk
;
1299 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1300 pc
= add_offset_16 (pc
, upk
.offset
);
1301 if ((insn
>> 10) & 0x01) /* Exchange mode */
1302 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1309 struct upk_mips16 upk
;
1311 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1312 reg
= get_frame_register_signed (frame
, upk
.regx
);
1314 pc
+= (upk
.offset
<< 1) + 2;
1321 struct upk_mips16 upk
;
1323 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1324 reg
= get_frame_register_signed (frame
, upk
.regx
);
1326 pc
+= (upk
.offset
<< 1) + 2;
1331 case 12: /* I8 Formats btez btnez */
1333 struct upk_mips16 upk
;
1335 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1336 /* upk.regx contains the opcode */
1337 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1338 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1339 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1340 /* pc = add_offset_16(pc,upk.offset) ; */
1341 pc
+= (upk
.offset
<< 1) + 2;
1346 case 29: /* RR Formats JR, JALR, JALR-RA */
1348 struct upk_mips16 upk
;
1349 /* upk.fmt = rrtype; */
1354 upk
.regx
= (insn
>> 8) & 0x07;
1355 upk
.regy
= (insn
>> 5) & 0x07;
1363 break; /* Function return instruction */
1369 break; /* BOGUS Guess */
1371 pc
= get_frame_register_signed (frame
, reg
);
1378 /* This is an instruction extension. Fetch the real instruction
1379 (which follows the extension) and decode things based on
1383 pc
= extended_mips16_next_pc (frame
, pc
, insn
, fetch_mips_16 (pc
));
1396 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1398 unsigned int insn
= fetch_mips_16 (pc
);
1399 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1402 /* The mips_next_pc function supports single_step when the remote
1403 target monitor or stub is not developed enough to do a single_step.
1404 It works by decoding the current instruction and predicting where a
1405 branch will go. This isnt hard because all the data is available.
1406 The MIPS32 and MIPS16 variants are quite different. */
1408 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1410 if (is_mips16_addr (pc
))
1411 return mips16_next_pc (frame
, pc
);
1413 return mips32_next_pc (frame
, pc
);
1416 struct mips_frame_cache
1419 struct trad_frame_saved_reg
*saved_regs
;
1422 /* Set a register's saved stack address in temp_saved_regs. If an
1423 address has already been set for this register, do nothing; this
1424 way we will only recognize the first save of a given register in a
1427 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1428 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1429 Strictly speaking, only the second range is used as it is only second
1430 range (the ABI instead of ISA registers) that comes into play when finding
1431 saved registers in a frame. */
1434 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1437 if (this_cache
!= NULL
1438 && this_cache
->saved_regs
[regnum
].addr
== -1)
1440 this_cache
->saved_regs
[regnum
1441 + 0 * gdbarch_num_regs (current_gdbarch
)].addr
1443 this_cache
->saved_regs
[regnum
1444 + 1 * gdbarch_num_regs (current_gdbarch
)].addr
1450 /* Fetch the immediate value from a MIPS16 instruction.
1451 If the previous instruction was an EXTEND, use it to extend
1452 the upper bits of the immediate value. This is a helper function
1453 for mips16_scan_prologue. */
1456 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1457 unsigned short inst
, /* current instruction */
1458 int nbits
, /* number of bits in imm field */
1459 int scale
, /* scale factor to be applied to imm */
1460 int is_signed
) /* is the imm field signed? */
1464 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1466 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1467 if (offset
& 0x8000) /* check for negative extend */
1468 offset
= 0 - (0x10000 - (offset
& 0xffff));
1469 return offset
| (inst
& 0x1f);
1473 int max_imm
= 1 << nbits
;
1474 int mask
= max_imm
- 1;
1475 int sign_bit
= max_imm
>> 1;
1477 offset
= inst
& mask
;
1478 if (is_signed
&& (offset
& sign_bit
))
1479 offset
= 0 - (max_imm
- offset
);
1480 return offset
* scale
;
1485 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1486 the associated FRAME_CACHE if not null.
1487 Return the address of the first instruction past the prologue. */
1490 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1491 struct frame_info
*next_frame
,
1492 struct mips_frame_cache
*this_cache
)
1495 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1497 long frame_offset
= 0; /* Size of stack frame. */
1498 long frame_adjust
= 0; /* Offset of FP from SP. */
1499 int frame_reg
= MIPS_SP_REGNUM
;
1500 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1501 unsigned inst
= 0; /* current instruction */
1502 unsigned entry_inst
= 0; /* the entry instruction */
1503 unsigned save_inst
= 0; /* the save instruction */
1506 int extend_bytes
= 0;
1507 int prev_extend_bytes
;
1508 CORE_ADDR end_prologue_addr
= 0;
1509 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1511 /* Can be called when there's no process, and hence when there's no
1513 if (next_frame
!= NULL
)
1514 sp
= frame_unwind_register_signed (next_frame
,
1515 gdbarch_num_regs (gdbarch
)
1520 if (limit_pc
> start_pc
+ 200)
1521 limit_pc
= start_pc
+ 200;
1523 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1525 /* Save the previous instruction. If it's an EXTEND, we'll extract
1526 the immediate offset extension from it in mips16_get_imm. */
1529 /* Fetch and decode the instruction. */
1530 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1532 /* Normally we ignore extend instructions. However, if it is
1533 not followed by a valid prologue instruction, then this
1534 instruction is not part of the prologue either. We must
1535 remember in this case to adjust the end_prologue_addr back
1537 if ((inst
& 0xf800) == 0xf000) /* extend */
1539 extend_bytes
= MIPS_INSN16_SIZE
;
1543 prev_extend_bytes
= extend_bytes
;
1546 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1547 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1549 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1550 if (offset
< 0) /* negative stack adjustment? */
1551 frame_offset
-= offset
;
1553 /* Exit loop if a positive stack adjustment is found, which
1554 usually means that the stack cleanup code in the function
1555 epilogue is reached. */
1558 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1560 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1561 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1562 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1564 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1566 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1567 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1568 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1570 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1572 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1573 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1575 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1577 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1578 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1580 else if (inst
== 0x673d) /* move $s1, $sp */
1585 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1587 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1588 frame_addr
= sp
+ offset
;
1590 frame_adjust
= offset
;
1592 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1594 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1595 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1596 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1598 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1600 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1601 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1602 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1604 else if ((inst
& 0xf81f) == 0xe809
1605 && (inst
& 0x700) != 0x700) /* entry */
1606 entry_inst
= inst
; /* save for later processing */
1607 else if ((inst
& 0xff80) == 0x6480) /* save */
1609 save_inst
= inst
; /* save for later processing */
1610 if (prev_extend_bytes
) /* extend */
1611 save_inst
|= prev_inst
<< 16;
1613 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1614 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1615 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1617 /* This instruction is part of the prologue, but we don't
1618 need to do anything special to handle it. */
1622 /* This instruction is not an instruction typically found
1623 in a prologue, so we must have reached the end of the
1625 if (end_prologue_addr
== 0)
1626 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1630 /* The entry instruction is typically the first instruction in a function,
1631 and it stores registers at offsets relative to the value of the old SP
1632 (before the prologue). But the value of the sp parameter to this
1633 function is the new SP (after the prologue has been executed). So we
1634 can't calculate those offsets until we've seen the entire prologue,
1635 and can calculate what the old SP must have been. */
1636 if (entry_inst
!= 0)
1638 int areg_count
= (entry_inst
>> 8) & 7;
1639 int sreg_count
= (entry_inst
>> 6) & 3;
1641 /* The entry instruction always subtracts 32 from the SP. */
1644 /* Now we can calculate what the SP must have been at the
1645 start of the function prologue. */
1648 /* Check if a0-a3 were saved in the caller's argument save area. */
1649 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1651 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1652 offset
+= mips_abi_regsize (gdbarch
);
1655 /* Check if the ra register was pushed on the stack. */
1657 if (entry_inst
& 0x20)
1659 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1660 offset
-= mips_abi_regsize (gdbarch
);
1663 /* Check if the s0 and s1 registers were pushed on the stack. */
1664 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1666 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1667 offset
-= mips_abi_regsize (gdbarch
);
1671 /* The SAVE instruction is similar to ENTRY, except that defined by the
1672 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1673 size of the frame is specified as an immediate field of instruction
1674 and an extended variation exists which lets additional registers and
1675 frame space to be specified. The instruction always treats registers
1676 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1677 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1679 static int args_table
[16] = {
1680 0, 0, 0, 0, 1, 1, 1, 1,
1681 2, 2, 2, 0, 3, 3, 4, -1,
1683 static int astatic_table
[16] = {
1684 0, 1, 2, 3, 0, 1, 2, 3,
1685 0, 1, 2, 4, 0, 1, 0, -1,
1687 int aregs
= (save_inst
>> 16) & 0xf;
1688 int xsregs
= (save_inst
>> 24) & 0x7;
1689 int args
= args_table
[aregs
];
1690 int astatic
= astatic_table
[aregs
];
1695 warning (_("Invalid number of argument registers encoded in SAVE."));
1700 warning (_("Invalid number of static registers encoded in SAVE."));
1704 /* For standard SAVE the frame size of 0 means 128. */
1705 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1706 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1709 frame_offset
+= frame_size
;
1711 /* Now we can calculate what the SP must have been at the
1712 start of the function prologue. */
1715 /* Check if A0-A3 were saved in the caller's argument save area. */
1716 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1718 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1719 offset
+= mips_abi_regsize (gdbarch
);
1724 /* Check if the RA register was pushed on the stack. */
1725 if (save_inst
& 0x40)
1727 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1728 offset
-= mips_abi_regsize (gdbarch
);
1731 /* Check if the S8 register was pushed on the stack. */
1734 set_reg_offset (this_cache
, 30, sp
+ offset
);
1735 offset
-= mips_abi_regsize (gdbarch
);
1738 /* Check if S2-S7 were pushed on the stack. */
1739 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1741 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1742 offset
-= mips_abi_regsize (gdbarch
);
1745 /* Check if the S1 register was pushed on the stack. */
1746 if (save_inst
& 0x10)
1748 set_reg_offset (this_cache
, 17, sp
+ offset
);
1749 offset
-= mips_abi_regsize (gdbarch
);
1751 /* Check if the S0 register was pushed on the stack. */
1752 if (save_inst
& 0x20)
1754 set_reg_offset (this_cache
, 16, sp
+ offset
);
1755 offset
-= mips_abi_regsize (gdbarch
);
1758 /* Check if A0-A3 were pushed on the stack. */
1759 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1761 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1762 offset
-= mips_abi_regsize (gdbarch
);
1766 if (this_cache
!= NULL
)
1769 (frame_unwind_register_signed (next_frame
,
1770 gdbarch_num_regs (gdbarch
) + frame_reg
)
1771 + frame_offset
- frame_adjust
);
1772 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1773 be able to get rid of the assignment below, evetually. But it's
1774 still needed for now. */
1775 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1776 + mips_regnum (gdbarch
)->pc
]
1777 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1780 /* If we didn't reach the end of the prologue when scanning the function
1781 instructions, then set end_prologue_addr to the address of the
1782 instruction immediately after the last one we scanned. */
1783 if (end_prologue_addr
== 0)
1784 end_prologue_addr
= cur_pc
;
1786 return end_prologue_addr
;
1789 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1790 Procedures that use the 32-bit instruction set are handled by the
1791 mips_insn32 unwinder. */
1793 static struct mips_frame_cache
*
1794 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1796 struct mips_frame_cache
*cache
;
1798 if ((*this_cache
) != NULL
)
1799 return (*this_cache
);
1800 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1801 (*this_cache
) = cache
;
1802 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1804 /* Analyze the function prologue. */
1806 const CORE_ADDR pc
=
1807 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1808 CORE_ADDR start_addr
;
1810 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1811 if (start_addr
== 0)
1812 start_addr
= heuristic_proc_start (pc
);
1813 /* We can't analyze the prologue if we couldn't find the begining
1815 if (start_addr
== 0)
1818 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1821 /* gdbarch_sp_regnum contains the value and not the address. */
1822 trad_frame_set_value (cache
->saved_regs
,
1823 gdbarch_num_regs (get_frame_arch (next_frame
))
1827 return (*this_cache
);
1831 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1832 struct frame_id
*this_id
)
1834 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1836 (*this_id
) = frame_id_build (info
->base
,
1837 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1841 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1843 int regnum
, int *optimizedp
,
1844 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1845 int *realnump
, gdb_byte
*valuep
)
1847 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1849 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1850 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1853 static const struct frame_unwind mips_insn16_frame_unwind
=
1856 mips_insn16_frame_this_id
,
1857 mips_insn16_frame_prev_register
1860 static const struct frame_unwind
*
1861 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1863 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1864 if (mips_pc_is_mips16 (pc
))
1865 return &mips_insn16_frame_unwind
;
1870 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1873 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1878 static const struct frame_base mips_insn16_frame_base
=
1880 &mips_insn16_frame_unwind
,
1881 mips_insn16_frame_base_address
,
1882 mips_insn16_frame_base_address
,
1883 mips_insn16_frame_base_address
1886 static const struct frame_base
*
1887 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1889 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1890 return &mips_insn16_frame_base
;
1895 /* Mark all the registers as unset in the saved_regs array
1896 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1899 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1901 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1905 const int num_regs
= gdbarch_num_regs (current_gdbarch
);
1908 for (i
= 0; i
< num_regs
; i
++)
1910 this_cache
->saved_regs
[i
].addr
= -1;
1915 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1916 the associated FRAME_CACHE if not null.
1917 Return the address of the first instruction past the prologue. */
1920 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1921 struct frame_info
*next_frame
,
1922 struct mips_frame_cache
*this_cache
)
1925 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1928 int frame_reg
= MIPS_SP_REGNUM
;
1930 CORE_ADDR end_prologue_addr
= 0;
1931 int seen_sp_adjust
= 0;
1932 int load_immediate_bytes
= 0;
1933 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1935 /* Can be called when there's no process, and hence when there's no
1937 if (next_frame
!= NULL
)
1938 sp
= frame_unwind_register_signed (next_frame
,
1939 gdbarch_num_regs (gdbarch
)
1944 if (limit_pc
> start_pc
+ 200)
1945 limit_pc
= start_pc
+ 200;
1950 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1952 unsigned long inst
, high_word
, low_word
;
1955 /* Fetch the instruction. */
1956 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1958 /* Save some code by pre-extracting some useful fields. */
1959 high_word
= (inst
>> 16) & 0xffff;
1960 low_word
= inst
& 0xffff;
1961 reg
= high_word
& 0x1f;
1963 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1964 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1965 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1967 if (low_word
& 0x8000) /* negative stack adjustment? */
1968 frame_offset
+= 0x10000 - low_word
;
1970 /* Exit loop if a positive stack adjustment is found, which
1971 usually means that the stack cleanup code in the function
1972 epilogue is reached. */
1976 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1978 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1980 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1982 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1983 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1985 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1987 /* Old gcc frame, r30 is virtual frame pointer. */
1988 if ((long) low_word
!= frame_offset
)
1989 frame_addr
= sp
+ low_word
;
1990 else if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1992 unsigned alloca_adjust
;
1995 frame_addr
= frame_unwind_register_signed
1996 (next_frame
, gdbarch_num_regs (gdbarch
) + 30);
1998 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1999 if (alloca_adjust
> 0)
2001 /* FP > SP + frame_size. This may be because of
2002 an alloca or somethings similar. Fix sp to
2003 "pre-alloca" value, and try again. */
2004 sp
+= alloca_adjust
;
2005 /* Need to reset the status of all registers. Otherwise,
2006 we will hit a guard that prevents the new address
2007 for each register to be recomputed during the second
2009 reset_saved_regs (this_cache
);
2014 /* move $30,$sp. With different versions of gas this will be either
2015 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2016 Accept any one of these. */
2017 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2019 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2020 if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2022 unsigned alloca_adjust
;
2025 frame_addr
= frame_unwind_register_signed
2026 (next_frame
, gdbarch_num_regs (gdbarch
) + 30);
2028 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2029 if (alloca_adjust
> 0)
2031 /* FP > SP + frame_size. This may be because of
2032 an alloca or somethings similar. Fix sp to
2033 "pre-alloca" value, and try again. */
2035 /* Need to reset the status of all registers. Otherwise,
2036 we will hit a guard that prevents the new address
2037 for each register to be recomputed during the second
2039 reset_saved_regs (this_cache
);
2044 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2046 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
2048 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2049 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2050 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2051 || high_word
== 0x3c1c /* lui $gp,n */
2052 || high_word
== 0x279c /* addiu $gp,$gp,n */
2053 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2054 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2057 /* These instructions are part of the prologue, but we don't
2058 need to do anything special to handle them. */
2060 /* The instructions below load $at or $t0 with an immediate
2061 value in preparation for a stack adjustment via
2062 subu $sp,$sp,[$at,$t0]. These instructions could also
2063 initialize a local variable, so we accept them only before
2064 a stack adjustment instruction was seen. */
2065 else if (!seen_sp_adjust
2066 && (high_word
== 0x3c01 /* lui $at,n */
2067 || high_word
== 0x3c08 /* lui $t0,n */
2068 || high_word
== 0x3421 /* ori $at,$at,n */
2069 || high_word
== 0x3508 /* ori $t0,$t0,n */
2070 || high_word
== 0x3401 /* ori $at,$zero,n */
2071 || high_word
== 0x3408 /* ori $t0,$zero,n */
2074 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2078 /* This instruction is not an instruction typically found
2079 in a prologue, so we must have reached the end of the
2081 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2082 loop now? Why would we need to continue scanning the function
2084 if (end_prologue_addr
== 0)
2085 end_prologue_addr
= cur_pc
;
2089 if (this_cache
!= NULL
)
2092 (frame_unwind_register_signed (next_frame
,
2093 gdbarch_num_regs (gdbarch
) + frame_reg
)
2095 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2096 this assignment below, eventually. But it's still needed
2098 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2099 + mips_regnum (gdbarch
)->pc
]
2100 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2104 /* If we didn't reach the end of the prologue when scanning the function
2105 instructions, then set end_prologue_addr to the address of the
2106 instruction immediately after the last one we scanned. */
2107 /* brobecker/2004-10-10: I don't think this would ever happen, but
2108 we may as well be careful and do our best if we have a null
2109 end_prologue_addr. */
2110 if (end_prologue_addr
== 0)
2111 end_prologue_addr
= cur_pc
;
2113 /* In a frameless function, we might have incorrectly
2114 skipped some load immediate instructions. Undo the skipping
2115 if the load immediate was not followed by a stack adjustment. */
2116 if (load_immediate_bytes
&& !seen_sp_adjust
)
2117 end_prologue_addr
-= load_immediate_bytes
;
2119 return end_prologue_addr
;
2122 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2123 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2124 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2127 static struct mips_frame_cache
*
2128 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2130 struct mips_frame_cache
*cache
;
2132 if ((*this_cache
) != NULL
)
2133 return (*this_cache
);
2135 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2136 (*this_cache
) = cache
;
2137 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2139 /* Analyze the function prologue. */
2141 const CORE_ADDR pc
=
2142 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2143 CORE_ADDR start_addr
;
2145 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2146 if (start_addr
== 0)
2147 start_addr
= heuristic_proc_start (pc
);
2148 /* We can't analyze the prologue if we couldn't find the begining
2150 if (start_addr
== 0)
2153 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
2156 /* gdbarch_sp_regnum contains the value and not the address. */
2157 trad_frame_set_value (cache
->saved_regs
,
2158 gdbarch_num_regs (get_frame_arch (next_frame
))
2162 return (*this_cache
);
2166 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2167 struct frame_id
*this_id
)
2169 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2171 (*this_id
) = frame_id_build (info
->base
,
2172 frame_func_unwind (next_frame
, NORMAL_FRAME
));
2176 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2178 int regnum
, int *optimizedp
,
2179 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2180 int *realnump
, gdb_byte
*valuep
)
2182 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2184 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2185 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2188 static const struct frame_unwind mips_insn32_frame_unwind
=
2191 mips_insn32_frame_this_id
,
2192 mips_insn32_frame_prev_register
2195 static const struct frame_unwind
*
2196 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2198 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2199 if (! mips_pc_is_mips16 (pc
))
2200 return &mips_insn32_frame_unwind
;
2205 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2208 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2213 static const struct frame_base mips_insn32_frame_base
=
2215 &mips_insn32_frame_unwind
,
2216 mips_insn32_frame_base_address
,
2217 mips_insn32_frame_base_address
,
2218 mips_insn32_frame_base_address
2221 static const struct frame_base
*
2222 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2224 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2225 return &mips_insn32_frame_base
;
2230 static struct trad_frame_cache
*
2231 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2234 CORE_ADDR start_addr
;
2235 CORE_ADDR stack_addr
;
2236 struct trad_frame_cache
*this_trad_cache
;
2237 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2239 if ((*this_cache
) != NULL
)
2240 return (*this_cache
);
2241 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2242 (*this_cache
) = this_trad_cache
;
2244 /* The return address is in the link register. */
2245 trad_frame_set_reg_realreg (this_trad_cache
,
2246 gdbarch_pc_regnum (gdbarch
),
2247 (gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
));
2249 /* Frame ID, since it's a frameless / stackless function, no stack
2250 space is allocated and SP on entry is the current SP. */
2251 pc
= frame_pc_unwind (next_frame
);
2252 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2253 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2254 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2256 /* Assume that the frame's base is the same as the
2258 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2260 return this_trad_cache
;
2264 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2265 struct frame_id
*this_id
)
2267 struct trad_frame_cache
*this_trad_cache
2268 = mips_stub_frame_cache (next_frame
, this_cache
);
2269 trad_frame_get_id (this_trad_cache
, this_id
);
2273 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2275 int regnum
, int *optimizedp
,
2276 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2277 int *realnump
, gdb_byte
*valuep
)
2279 struct trad_frame_cache
*this_trad_cache
2280 = mips_stub_frame_cache (next_frame
, this_cache
);
2281 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2282 lvalp
, addrp
, realnump
, valuep
);
2285 static const struct frame_unwind mips_stub_frame_unwind
=
2288 mips_stub_frame_this_id
,
2289 mips_stub_frame_prev_register
2292 static const struct frame_unwind
*
2293 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2296 struct obj_section
*s
;
2297 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2299 /* Use the stub unwinder for unreadable code. */
2300 if (target_read_memory (frame_pc_unwind (next_frame
), dummy
, 4) != 0)
2301 return &mips_stub_frame_unwind
;
2303 if (in_plt_section (pc
, NULL
))
2304 return &mips_stub_frame_unwind
;
2306 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2307 s
= find_pc_section (pc
);
2310 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2311 ".MIPS.stubs") == 0)
2312 return &mips_stub_frame_unwind
;
2318 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2321 struct trad_frame_cache
*this_trad_cache
2322 = mips_stub_frame_cache (next_frame
, this_cache
);
2323 return trad_frame_get_this_base (this_trad_cache
);
2326 static const struct frame_base mips_stub_frame_base
=
2328 &mips_stub_frame_unwind
,
2329 mips_stub_frame_base_address
,
2330 mips_stub_frame_base_address
,
2331 mips_stub_frame_base_address
2334 static const struct frame_base
*
2335 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2337 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2338 return &mips_stub_frame_base
;
2343 /* mips_addr_bits_remove - remove useless address bits */
2346 mips_addr_bits_remove (CORE_ADDR addr
)
2348 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2349 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2350 /* This hack is a work-around for existing boards using PMON, the
2351 simulator, and any other 64-bit targets that doesn't have true
2352 64-bit addressing. On these targets, the upper 32 bits of
2353 addresses are ignored by the hardware. Thus, the PC or SP are
2354 likely to have been sign extended to all 1s by instruction
2355 sequences that load 32-bit addresses. For example, a typical
2356 piece of code that loads an address is this:
2358 lui $r2, <upper 16 bits>
2359 ori $r2, <lower 16 bits>
2361 But the lui sign-extends the value such that the upper 32 bits
2362 may be all 1s. The workaround is simply to mask off these
2363 bits. In the future, gcc may be changed to support true 64-bit
2364 addressing, and this masking will have to be disabled. */
2365 return addr
&= 0xffffffffUL
;
2370 /* Instructions used during single-stepping of atomic sequences. */
2371 #define LL_OPCODE 0x30
2372 #define LLD_OPCODE 0x34
2373 #define SC_OPCODE 0x38
2374 #define SCD_OPCODE 0x3c
2376 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2377 instruction and ending with a SC/SCD instruction. If such a sequence
2378 is found, attempt to step through it. A breakpoint is placed at the end of
2382 deal_with_atomic_sequence (CORE_ADDR pc
)
2384 CORE_ADDR breaks
[2] = {-1, -1};
2386 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2390 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2391 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2396 insn
= mips_fetch_instruction (loc
);
2397 /* Assume all atomic sequences start with a ll/lld instruction. */
2398 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2401 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2403 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2406 loc
+= MIPS_INSN32_SIZE
;
2407 insn
= mips_fetch_instruction (loc
);
2409 /* Assume that there is at most one branch in the atomic
2410 sequence. If a branch is found, put a breakpoint in its
2411 destination address. */
2412 switch (itype_op (insn
))
2414 case 0: /* SPECIAL */
2415 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2416 return 0; /* fallback to the standard single-step code. */
2418 case 1: /* REGIMM */
2419 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2423 return 0; /* fallback to the standard single-step code. */
2430 case 22: /* BLEZL */
2431 case 23: /* BGTTL */
2437 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2442 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2443 if (last_breakpoint
>= 1)
2444 return 0; /* More than one branch found, fallback to the
2445 standard single-step code. */
2446 breaks
[1] = branch_bp
;
2450 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2454 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2455 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2458 loc
+= MIPS_INSN32_SIZE
;
2460 /* Insert a breakpoint right after the end of the atomic sequence. */
2463 /* Check for duplicated breakpoints. Check also for a breakpoint
2464 placed (branch instruction's destination) in the atomic sequence */
2465 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2466 last_breakpoint
= 0;
2468 /* Effectively inserts the breakpoints. */
2469 for (index
= 0; index
<= last_breakpoint
; index
++)
2470 insert_single_step_breakpoint (breaks
[index
]);
2475 /* mips_software_single_step() is called just before we want to resume
2476 the inferior, if we want to single-step it but there is no hardware
2477 or kernel single-step support (MIPS on GNU/Linux for example). We find
2478 the target of the coming instruction and breakpoint it. */
2481 mips_software_single_step (struct frame_info
*frame
)
2483 CORE_ADDR pc
, next_pc
;
2485 pc
= get_frame_pc (frame
);
2486 if (deal_with_atomic_sequence (pc
))
2489 next_pc
= mips_next_pc (frame
, pc
);
2491 insert_single_step_breakpoint (next_pc
);
2495 /* Test whether the PC points to the return instruction at the
2496 end of a function. */
2499 mips_about_to_return (CORE_ADDR pc
)
2501 if (mips_pc_is_mips16 (pc
))
2502 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2503 generates a "jr $ra"; other times it generates code to load
2504 the return address from the stack to an accessible register (such
2505 as $a3), then a "jr" using that register. This second case
2506 is almost impossible to distinguish from an indirect jump
2507 used for switch statements, so we don't even try. */
2508 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2510 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2514 /* This fencepost looks highly suspicious to me. Removing it also
2515 seems suspicious as it could affect remote debugging across serial
2519 heuristic_proc_start (CORE_ADDR pc
)
2526 pc
= gdbarch_addr_bits_remove (current_gdbarch
, pc
);
2528 fence
= start_pc
- heuristic_fence_post
;
2532 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2533 fence
= VM_MIN_ADDRESS
;
2535 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2537 /* search back for previous return */
2538 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2539 if (start_pc
< fence
)
2541 /* It's not clear to me why we reach this point when
2542 stop_soon, but with this test, at least we
2543 don't print out warnings for every child forked (eg, on
2544 decstation). 22apr93 rich@cygnus.com. */
2545 if (stop_soon
== NO_STOP_QUIETLY
)
2547 static int blurb_printed
= 0;
2549 warning (_("GDB can't find the start of the function at 0x%s."),
2554 /* This actually happens frequently in embedded
2555 development, when you first connect to a board
2556 and your stack pointer and pc are nowhere in
2557 particular. This message needs to give people
2558 in that situation enough information to
2559 determine that it's no big deal. */
2560 printf_filtered ("\n\
2561 GDB is unable to find the start of the function at 0x%s\n\
2562 and thus can't determine the size of that function's stack frame.\n\
2563 This means that GDB may be unable to access that stack frame, or\n\
2564 the frames below it.\n\
2565 This problem is most likely caused by an invalid program counter or\n\
2567 However, if you think GDB should simply search farther back\n\
2568 from 0x%s for code which looks like the beginning of a\n\
2569 function, you can increase the range of the search using the `set\n\
2570 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2577 else if (mips_pc_is_mips16 (start_pc
))
2579 unsigned short inst
;
2581 /* On MIPS16, any one of the following is likely to be the
2582 start of a function:
2588 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2589 inst
= mips_fetch_instruction (start_pc
);
2590 if ((inst
& 0xff80) == 0x6480) /* save */
2592 if (start_pc
- instlen
>= fence
)
2594 inst
= mips_fetch_instruction (start_pc
- instlen
);
2595 if ((inst
& 0xf800) == 0xf000) /* extend */
2596 start_pc
-= instlen
;
2600 else if (((inst
& 0xf81f) == 0xe809
2601 && (inst
& 0x700) != 0x700) /* entry */
2602 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2603 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2604 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2606 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2607 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2612 else if (mips_about_to_return (start_pc
))
2614 /* Skip return and its delay slot. */
2615 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2622 struct mips_objfile_private
2628 /* According to the current ABI, should the type be passed in a
2629 floating-point register (assuming that there is space)? When there
2630 is no FPU, FP are not even considered as possible candidates for
2631 FP registers and, consequently this returns false - forces FP
2632 arguments into integer registers. */
2635 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2637 return ((typecode
== TYPE_CODE_FLT
2639 && (typecode
== TYPE_CODE_STRUCT
2640 || typecode
== TYPE_CODE_UNION
)
2641 && TYPE_NFIELDS (arg_type
) == 1
2642 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2644 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2647 /* On o32, argument passing in GPRs depends on the alignment of the type being
2648 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2651 mips_type_needs_double_align (struct type
*type
)
2653 enum type_code typecode
= TYPE_CODE (type
);
2655 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2657 else if (typecode
== TYPE_CODE_STRUCT
)
2659 if (TYPE_NFIELDS (type
) < 1)
2661 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2663 else if (typecode
== TYPE_CODE_UNION
)
2667 n
= TYPE_NFIELDS (type
);
2668 for (i
= 0; i
< n
; i
++)
2669 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2676 /* Adjust the address downward (direction of stack growth) so that it
2677 is correctly aligned for a new stack frame. */
2679 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2681 return align_down (addr
, 16);
2685 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2686 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2687 int nargs
, struct value
**args
, CORE_ADDR sp
,
2688 int struct_return
, CORE_ADDR struct_addr
)
2694 int stack_offset
= 0;
2695 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2696 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2697 int regsize
= mips_abi_regsize (gdbarch
);
2699 /* For shared libraries, "t9" needs to point at the function
2701 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2703 /* Set the return address register to point to the entry point of
2704 the program, where a breakpoint lies in wait. */
2705 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2707 /* First ensure that the stack and structure return address (if any)
2708 are properly aligned. The stack has to be at least 64-bit
2709 aligned even on 32-bit machines, because doubles must be 64-bit
2710 aligned. For n32 and n64, stack frames need to be 128-bit
2711 aligned, so we round to this widest known alignment. */
2713 sp
= align_down (sp
, 16);
2714 struct_addr
= align_down (struct_addr
, 16);
2716 /* Now make space on the stack for the args. We allocate more
2717 than necessary for EABI, because the first few arguments are
2718 passed in registers, but that's OK. */
2719 for (argnum
= 0; argnum
< nargs
; argnum
++)
2720 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2721 sp
-= align_up (len
, 16);
2724 fprintf_unfiltered (gdb_stdlog
,
2725 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2726 paddr_nz (sp
), (long) align_up (len
, 16));
2728 /* Initialize the integer and float register pointers. */
2729 argreg
= MIPS_A0_REGNUM
;
2730 float_argreg
= mips_fpa0_regnum (gdbarch
);
2732 /* The struct_return pointer occupies the first parameter-passing reg. */
2736 fprintf_unfiltered (gdb_stdlog
,
2737 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2738 argreg
, paddr_nz (struct_addr
));
2739 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2742 /* Now load as many as possible of the first arguments into
2743 registers, and push the rest onto the stack. Loop thru args
2744 from first to last. */
2745 for (argnum
= 0; argnum
< nargs
; argnum
++)
2747 const gdb_byte
*val
;
2748 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2749 struct value
*arg
= args
[argnum
];
2750 struct type
*arg_type
= check_typedef (value_type (arg
));
2751 int len
= TYPE_LENGTH (arg_type
);
2752 enum type_code typecode
= TYPE_CODE (arg_type
);
2755 fprintf_unfiltered (gdb_stdlog
,
2756 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2757 argnum
+ 1, len
, (int) typecode
);
2759 /* The EABI passes structures that do not fit in a register by
2762 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2764 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2765 typecode
= TYPE_CODE_PTR
;
2769 fprintf_unfiltered (gdb_stdlog
, " push");
2772 val
= value_contents (arg
);
2774 /* 32-bit ABIs always start floating point arguments in an
2775 even-numbered floating point register. Round the FP register
2776 up before the check to see if there are any FP registers
2777 left. Non MIPS_EABI targets also pass the FP in the integer
2778 registers so also round up normal registers. */
2779 if (regsize
< 8 && fp_register_arg_p (typecode
, arg_type
))
2781 if ((float_argreg
& 1))
2785 /* Floating point arguments passed in registers have to be
2786 treated specially. On 32-bit architectures, doubles
2787 are passed in register pairs; the even register gets
2788 the low word, and the odd register gets the high word.
2789 On non-EABI processors, the first two floating point arguments are
2790 also copied to general registers, because MIPS16 functions
2791 don't use float registers for arguments. This duplication of
2792 arguments in general registers can't hurt non-MIPS16 functions
2793 because those registers are normally skipped. */
2794 /* MIPS_EABI squeezes a struct that contains a single floating
2795 point value into an FP register instead of pushing it onto the
2797 if (fp_register_arg_p (typecode
, arg_type
)
2798 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2800 /* EABI32 will pass doubles in consecutive registers, even on
2801 64-bit cores. At one time, we used to check the size of
2802 `float_argreg' to determine whether or not to pass doubles
2803 in consecutive registers, but this is not sufficient for
2804 making the ABI determination. */
2805 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2807 int low_offset
= gdbarch_byte_order (gdbarch
)
2808 == BFD_ENDIAN_BIG
? 4 : 0;
2809 unsigned long regval
;
2811 /* Write the low word of the double to the even register(s). */
2812 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2814 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2815 float_argreg
, phex (regval
, 4));
2816 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2818 /* Write the high word of the double to the odd register(s). */
2819 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2821 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2822 float_argreg
, phex (regval
, 4));
2823 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2827 /* This is a floating point value that fits entirely
2828 in a single register. */
2829 /* On 32 bit ABI's the float_argreg is further adjusted
2830 above to ensure that it is even register aligned. */
2831 LONGEST regval
= extract_unsigned_integer (val
, len
);
2833 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2834 float_argreg
, phex (regval
, len
));
2835 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2840 /* Copy the argument to general registers or the stack in
2841 register-sized pieces. Large arguments are split between
2842 registers and stack. */
2843 /* Note: structs whose size is not a multiple of regsize
2844 are treated specially: Irix cc passes
2845 them in registers where gcc sometimes puts them on the
2846 stack. For maximum compatibility, we will put them in
2848 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2850 /* Note: Floating-point values that didn't fit into an FP
2851 register are only written to memory. */
2854 /* Remember if the argument was written to the stack. */
2855 int stack_used_p
= 0;
2856 int partial_len
= (len
< regsize
? len
: regsize
);
2859 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2862 /* Write this portion of the argument to the stack. */
2863 if (argreg
> MIPS_LAST_ARG_REGNUM
2865 || fp_register_arg_p (typecode
, arg_type
))
2867 /* Should shorter than int integer values be
2868 promoted to int before being stored? */
2869 int longword_offset
= 0;
2872 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2875 && (typecode
== TYPE_CODE_INT
2876 || typecode
== TYPE_CODE_PTR
2877 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2878 longword_offset
= regsize
- len
;
2879 else if ((typecode
== TYPE_CODE_STRUCT
2880 || typecode
== TYPE_CODE_UNION
)
2881 && TYPE_LENGTH (arg_type
) < regsize
)
2882 longword_offset
= regsize
- len
;
2887 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2888 paddr_nz (stack_offset
));
2889 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2890 paddr_nz (longword_offset
));
2893 addr
= sp
+ stack_offset
+ longword_offset
;
2898 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2900 for (i
= 0; i
< partial_len
; i
++)
2902 fprintf_unfiltered (gdb_stdlog
, "%02x",
2906 write_memory (addr
, val
, partial_len
);
2909 /* Note!!! This is NOT an else clause. Odd sized
2910 structs may go thru BOTH paths. Floating point
2911 arguments will not. */
2912 /* Write this portion of the argument to a general
2913 purpose register. */
2914 if (argreg
<= MIPS_LAST_ARG_REGNUM
2915 && !fp_register_arg_p (typecode
, arg_type
))
2918 extract_unsigned_integer (val
, partial_len
);
2921 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2923 phex (regval
, regsize
));
2924 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2931 /* Compute the the offset into the stack at which we
2932 will copy the next parameter.
2934 In the new EABI (and the NABI32), the stack_offset
2935 only needs to be adjusted when it has been used. */
2938 stack_offset
+= align_up (partial_len
, regsize
);
2942 fprintf_unfiltered (gdb_stdlog
, "\n");
2945 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2947 /* Return adjusted stack pointer. */
2951 /* Determine the return value convention being used. */
2953 static enum return_value_convention
2954 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2955 struct type
*type
, struct regcache
*regcache
,
2956 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2958 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2959 return RETURN_VALUE_STRUCT_CONVENTION
;
2961 memset (readbuf
, 0, TYPE_LENGTH (type
));
2962 return RETURN_VALUE_REGISTER_CONVENTION
;
2966 /* N32/N64 ABI stuff. */
2968 /* Search for a naturally aligned double at OFFSET inside a struct
2969 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
2973 mips_n32n64_fp_arg_chunk_p (struct type
*arg_type
, int offset
)
2977 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
2980 if (MIPS_FPU_TYPE
!= MIPS_FPU_DOUBLE
)
2983 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
2986 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
2989 struct type
*field_type
;
2991 /* We're only looking at normal fields. */
2992 if (TYPE_FIELD_STATIC (arg_type
, i
)
2993 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
2996 /* If we have gone past the offset, there is no double to pass. */
2997 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3001 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3003 /* If this field is entirely before the requested offset, go
3004 on to the next one. */
3005 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3008 /* If this is our special aligned double, we can stop. */
3009 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3010 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3013 /* This field starts at or before the requested offset, and
3014 overlaps it. If it is a structure, recurse inwards. */
3015 return mips_n32n64_fp_arg_chunk_p (field_type
, offset
- pos
);
3022 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3023 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3024 int nargs
, struct value
**args
, CORE_ADDR sp
,
3025 int struct_return
, CORE_ADDR struct_addr
)
3031 int stack_offset
= 0;
3032 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3033 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3035 /* For shared libraries, "t9" needs to point at the function
3037 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3039 /* Set the return address register to point to the entry point of
3040 the program, where a breakpoint lies in wait. */
3041 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3043 /* First ensure that the stack and structure return address (if any)
3044 are properly aligned. The stack has to be at least 64-bit
3045 aligned even on 32-bit machines, because doubles must be 64-bit
3046 aligned. For n32 and n64, stack frames need to be 128-bit
3047 aligned, so we round to this widest known alignment. */
3049 sp
= align_down (sp
, 16);
3050 struct_addr
= align_down (struct_addr
, 16);
3052 /* Now make space on the stack for the args. */
3053 for (argnum
= 0; argnum
< nargs
; argnum
++)
3054 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3055 sp
-= align_up (len
, 16);
3058 fprintf_unfiltered (gdb_stdlog
,
3059 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3060 paddr_nz (sp
), (long) align_up (len
, 16));
3062 /* Initialize the integer and float register pointers. */
3063 argreg
= MIPS_A0_REGNUM
;
3064 float_argreg
= mips_fpa0_regnum (gdbarch
);
3066 /* The struct_return pointer occupies the first parameter-passing reg. */
3070 fprintf_unfiltered (gdb_stdlog
,
3071 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3072 argreg
, paddr_nz (struct_addr
));
3073 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3076 /* Now load as many as possible of the first arguments into
3077 registers, and push the rest onto the stack. Loop thru args
3078 from first to last. */
3079 for (argnum
= 0; argnum
< nargs
; argnum
++)
3081 const gdb_byte
*val
;
3082 struct value
*arg
= args
[argnum
];
3083 struct type
*arg_type
= check_typedef (value_type (arg
));
3084 int len
= TYPE_LENGTH (arg_type
);
3085 enum type_code typecode
= TYPE_CODE (arg_type
);
3088 fprintf_unfiltered (gdb_stdlog
,
3089 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3090 argnum
+ 1, len
, (int) typecode
);
3092 val
= value_contents (arg
);
3094 if (fp_register_arg_p (typecode
, arg_type
)
3095 && argreg
<= MIPS_LAST_ARG_REGNUM
)
3097 /* This is a floating point value that fits entirely
3098 in a single register. */
3099 LONGEST regval
= extract_unsigned_integer (val
, len
);
3101 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3102 float_argreg
, phex (regval
, len
));
3103 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3106 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3107 argreg
, phex (regval
, len
));
3108 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3114 /* Copy the argument to general registers or the stack in
3115 register-sized pieces. Large arguments are split between
3116 registers and stack. */
3117 /* For N32/N64, structs, unions, or other composite types are
3118 treated as a sequence of doublewords, and are passed in integer
3119 or floating point registers as though they were simple scalar
3120 parameters to the extent that they fit, with any excess on the
3121 stack packed according to the normal memory layout of the
3123 The caller does not reserve space for the register arguments;
3124 the callee is responsible for reserving it if required. */
3125 /* Note: Floating-point values that didn't fit into an FP
3126 register are only written to memory. */
3129 /* Remember if the argument was written to the stack. */
3130 int stack_used_p
= 0;
3131 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3134 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3137 if (fp_register_arg_p (typecode
, arg_type
))
3138 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM
);
3140 /* Write this portion of the argument to the stack. */
3141 if (argreg
> MIPS_LAST_ARG_REGNUM
)
3143 /* Should shorter than int integer values be
3144 promoted to int before being stored? */
3145 int longword_offset
= 0;
3148 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3150 if ((typecode
== TYPE_CODE_INT
3151 || typecode
== TYPE_CODE_PTR
3152 || typecode
== TYPE_CODE_FLT
)
3154 longword_offset
= MIPS64_REGSIZE
- len
;
3159 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3160 paddr_nz (stack_offset
));
3161 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3162 paddr_nz (longword_offset
));
3165 addr
= sp
+ stack_offset
+ longword_offset
;
3170 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3172 for (i
= 0; i
< partial_len
; i
++)
3174 fprintf_unfiltered (gdb_stdlog
, "%02x",
3178 write_memory (addr
, val
, partial_len
);
3181 /* Note!!! This is NOT an else clause. Odd sized
3182 structs may go thru BOTH paths. */
3183 /* Write this portion of the argument to a general
3184 purpose register. */
3185 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3188 extract_unsigned_integer (val
, partial_len
);
3190 /* A non-floating-point argument being passed in a
3191 general register. If a struct or union, and if
3192 the remaining length is smaller than the register
3193 size, we have to adjust the register value on
3196 It does not seem to be necessary to do the
3197 same for integral types. */
3199 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3200 && partial_len
< MIPS64_REGSIZE
3201 && (typecode
== TYPE_CODE_STRUCT
3202 || typecode
== TYPE_CODE_UNION
))
3203 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3207 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3209 phex (regval
, MIPS64_REGSIZE
));
3210 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3212 if (mips_n32n64_fp_arg_chunk_p (arg_type
,
3213 TYPE_LENGTH (arg_type
) - len
))
3216 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3218 phex (regval
, MIPS64_REGSIZE
));
3219 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3230 /* Compute the the offset into the stack at which we
3231 will copy the next parameter.
3233 In N32 (N64?), the stack_offset only needs to be
3234 adjusted when it has been used. */
3237 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3241 fprintf_unfiltered (gdb_stdlog
, "\n");
3244 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3246 /* Return adjusted stack pointer. */
3250 static enum return_value_convention
3251 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3252 struct type
*type
, struct regcache
*regcache
,
3253 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3255 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3257 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3259 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3260 if needed), as appropriate for the type. Composite results (struct,
3261 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3264 * A struct with only one or two floating point fields is returned in $f0
3265 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3268 * Any other struct or union results of at most 128 bits are returned in
3269 $2 (first 64 bits) and $3 (remainder, if necessary).
3271 * Larger composite results are handled by converting the function to a
3272 procedure with an implicit first parameter, which is a pointer to an area
3273 reserved by the caller to receive the result. [The o32-bit ABI requires
3274 that all composite results be handled by conversion to implicit first
3275 parameters. The MIPS/SGI Fortran implementation has always made a
3276 specific exception to return COMPLEX results in the floating point
3279 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
3280 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3281 return RETURN_VALUE_STRUCT_CONVENTION
;
3282 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3283 && TYPE_LENGTH (type
) == 16
3284 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3286 /* A 128-bit floating-point value fills both $f0 and $f2. The
3287 two registers are used in the same as memory order, so the
3288 eight bytes with the lower memory address are in $f0. */
3290 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3291 mips_xfer_register (gdbarch
, regcache
,
3292 gdbarch_num_regs (gdbarch
)
3293 + mips_regnum (gdbarch
)->fp0
,
3294 8, gdbarch_byte_order (gdbarch
),
3295 readbuf
, writebuf
, 0);
3296 mips_xfer_register (gdbarch
, regcache
,
3297 gdbarch_num_regs (gdbarch
)
3298 + mips_regnum (gdbarch
)->fp0
+ 2,
3299 8, gdbarch_byte_order (gdbarch
),
3300 readbuf
? readbuf
+ 8 : readbuf
,
3301 writebuf
? writebuf
+ 8 : writebuf
, 0);
3302 return RETURN_VALUE_REGISTER_CONVENTION
;
3304 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3305 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3307 /* A single or double floating-point value that fits in FP0. */
3309 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3310 mips_xfer_register (gdbarch
, regcache
,
3311 gdbarch_num_regs (gdbarch
)
3312 + mips_regnum (gdbarch
)->fp0
,
3314 gdbarch_byte_order (gdbarch
),
3315 readbuf
, writebuf
, 0);
3316 return RETURN_VALUE_REGISTER_CONVENTION
;
3318 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3319 && TYPE_NFIELDS (type
) <= 2
3320 && TYPE_NFIELDS (type
) >= 1
3321 && ((TYPE_NFIELDS (type
) == 1
3322 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3324 || (TYPE_NFIELDS (type
) == 2
3325 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3327 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3329 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3331 /* A struct that contains one or two floats. Each value is part
3332 in the least significant part of their floating point
3336 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3337 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3339 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3342 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3344 mips_xfer_register (gdbarch
, regcache
,
3345 gdbarch_num_regs (gdbarch
) + regnum
,
3346 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3347 gdbarch_byte_order (gdbarch
),
3348 readbuf
, writebuf
, offset
);
3350 return RETURN_VALUE_REGISTER_CONVENTION
;
3352 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3353 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3355 /* A structure or union. Extract the left justified value,
3356 regardless of the byte order. I.e. DO NOT USE
3360 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3361 offset
< TYPE_LENGTH (type
);
3362 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3364 int xfer
= register_size (gdbarch
, regnum
);
3365 if (offset
+ xfer
> TYPE_LENGTH (type
))
3366 xfer
= TYPE_LENGTH (type
) - offset
;
3368 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3369 offset
, xfer
, regnum
);
3370 mips_xfer_register (gdbarch
, regcache
,
3371 gdbarch_num_regs (gdbarch
) + regnum
,
3372 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3375 return RETURN_VALUE_REGISTER_CONVENTION
;
3379 /* A scalar extract each part but least-significant-byte
3383 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3384 offset
< TYPE_LENGTH (type
);
3385 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3387 int xfer
= register_size (gdbarch
, regnum
);
3388 if (offset
+ xfer
> TYPE_LENGTH (type
))
3389 xfer
= TYPE_LENGTH (type
) - offset
;
3391 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3392 offset
, xfer
, regnum
);
3393 mips_xfer_register (gdbarch
, regcache
,
3394 gdbarch_num_regs (gdbarch
) + regnum
,
3395 xfer
, gdbarch_byte_order (gdbarch
),
3396 readbuf
, writebuf
, offset
);
3398 return RETURN_VALUE_REGISTER_CONVENTION
;
3402 /* O32 ABI stuff. */
3405 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3406 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3407 int nargs
, struct value
**args
, CORE_ADDR sp
,
3408 int struct_return
, CORE_ADDR struct_addr
)
3414 int stack_offset
= 0;
3415 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3416 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3418 /* For shared libraries, "t9" needs to point at the function
3420 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3422 /* Set the return address register to point to the entry point of
3423 the program, where a breakpoint lies in wait. */
3424 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3426 /* First ensure that the stack and structure return address (if any)
3427 are properly aligned. The stack has to be at least 64-bit
3428 aligned even on 32-bit machines, because doubles must be 64-bit
3429 aligned. For n32 and n64, stack frames need to be 128-bit
3430 aligned, so we round to this widest known alignment. */
3432 sp
= align_down (sp
, 16);
3433 struct_addr
= align_down (struct_addr
, 16);
3435 /* Now make space on the stack for the args. */
3436 for (argnum
= 0; argnum
< nargs
; argnum
++)
3438 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3439 int arglen
= TYPE_LENGTH (arg_type
);
3441 /* Align to double-word if necessary. */
3442 if (mips_type_needs_double_align (arg_type
))
3443 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3444 /* Allocate space on the stack. */
3445 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3447 sp
-= align_up (len
, 16);
3450 fprintf_unfiltered (gdb_stdlog
,
3451 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3452 paddr_nz (sp
), (long) align_up (len
, 16));
3454 /* Initialize the integer and float register pointers. */
3455 argreg
= MIPS_A0_REGNUM
;
3456 float_argreg
= mips_fpa0_regnum (gdbarch
);
3458 /* The struct_return pointer occupies the first parameter-passing reg. */
3462 fprintf_unfiltered (gdb_stdlog
,
3463 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3464 argreg
, paddr_nz (struct_addr
));
3465 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3466 stack_offset
+= MIPS32_REGSIZE
;
3469 /* Now load as many as possible of the first arguments into
3470 registers, and push the rest onto the stack. Loop thru args
3471 from first to last. */
3472 for (argnum
= 0; argnum
< nargs
; argnum
++)
3474 const gdb_byte
*val
;
3475 struct value
*arg
= args
[argnum
];
3476 struct type
*arg_type
= check_typedef (value_type (arg
));
3477 int len
= TYPE_LENGTH (arg_type
);
3478 enum type_code typecode
= TYPE_CODE (arg_type
);
3481 fprintf_unfiltered (gdb_stdlog
,
3482 "mips_o32_push_dummy_call: %d len=%d type=%d",
3483 argnum
+ 1, len
, (int) typecode
);
3485 val
= value_contents (arg
);
3487 /* 32-bit ABIs always start floating point arguments in an
3488 even-numbered floating point register. Round the FP register
3489 up before the check to see if there are any FP registers
3490 left. O32/O64 targets also pass the FP in the integer
3491 registers so also round up normal registers. */
3492 if (fp_register_arg_p (typecode
, arg_type
))
3494 if ((float_argreg
& 1))
3498 /* Floating point arguments passed in registers have to be
3499 treated specially. On 32-bit architectures, doubles
3500 are passed in register pairs; the even register gets
3501 the low word, and the odd register gets the high word.
3502 On O32/O64, the first two floating point arguments are
3503 also copied to general registers, because MIPS16 functions
3504 don't use float registers for arguments. This duplication of
3505 arguments in general registers can't hurt non-MIPS16 functions
3506 because those registers are normally skipped. */
3508 if (fp_register_arg_p (typecode
, arg_type
)
3509 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3511 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3513 int low_offset
= gdbarch_byte_order (gdbarch
)
3514 == BFD_ENDIAN_BIG
? 4 : 0;
3515 unsigned long regval
;
3517 /* Write the low word of the double to the even register(s). */
3518 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3520 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3521 float_argreg
, phex (regval
, 4));
3522 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3524 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3525 argreg
, phex (regval
, 4));
3526 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3528 /* Write the high word of the double to the odd register(s). */
3529 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3531 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3532 float_argreg
, phex (regval
, 4));
3533 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3536 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3537 argreg
, phex (regval
, 4));
3538 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3542 /* This is a floating point value that fits entirely
3543 in a single register. */
3544 /* On 32 bit ABI's the float_argreg is further adjusted
3545 above to ensure that it is even register aligned. */
3546 LONGEST regval
= extract_unsigned_integer (val
, len
);
3548 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3549 float_argreg
, phex (regval
, len
));
3550 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3551 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3552 registers for each argument. The below is (my
3553 guess) to ensure that the corresponding integer
3554 register has reserved the same space. */
3556 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3557 argreg
, phex (regval
, len
));
3558 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3561 /* Reserve space for the FP register. */
3562 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3566 /* Copy the argument to general registers or the stack in
3567 register-sized pieces. Large arguments are split between
3568 registers and stack. */
3569 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3570 are treated specially: Irix cc passes
3571 them in registers where gcc sometimes puts them on the
3572 stack. For maximum compatibility, we will put them in
3574 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3575 && len
% MIPS32_REGSIZE
!= 0);
3576 /* Structures should be aligned to eight bytes (even arg registers)
3577 on MIPS_ABI_O32, if their first member has double precision. */
3578 if (mips_type_needs_double_align (arg_type
))
3583 stack_offset
+= MIPS32_REGSIZE
;
3588 /* Remember if the argument was written to the stack. */
3589 int stack_used_p
= 0;
3590 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3593 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3596 /* Write this portion of the argument to the stack. */
3597 if (argreg
> MIPS_LAST_ARG_REGNUM
3598 || odd_sized_struct
)
3600 /* Should shorter than int integer values be
3601 promoted to int before being stored? */
3602 int longword_offset
= 0;
3608 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3609 paddr_nz (stack_offset
));
3610 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3611 paddr_nz (longword_offset
));
3614 addr
= sp
+ stack_offset
+ longword_offset
;
3619 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3621 for (i
= 0; i
< partial_len
; i
++)
3623 fprintf_unfiltered (gdb_stdlog
, "%02x",
3627 write_memory (addr
, val
, partial_len
);
3630 /* Note!!! This is NOT an else clause. Odd sized
3631 structs may go thru BOTH paths. */
3632 /* Write this portion of the argument to a general
3633 purpose register. */
3634 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3636 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3637 /* Value may need to be sign extended, because
3638 mips_isa_regsize() != mips_abi_regsize(). */
3640 /* A non-floating-point argument being passed in a
3641 general register. If a struct or union, and if
3642 the remaining length is smaller than the register
3643 size, we have to adjust the register value on
3646 It does not seem to be necessary to do the
3647 same for integral types.
3649 Also don't do this adjustment on O64 binaries.
3651 cagney/2001-07-23: gdb/179: Also, GCC, when
3652 outputting LE O32 with sizeof (struct) <
3653 mips_abi_regsize(), generates a left shift
3654 as part of storing the argument in a register
3655 (the left shift isn't generated when
3656 sizeof (struct) >= mips_abi_regsize()). Since
3657 it is quite possible that this is GCC
3658 contradicting the LE/O32 ABI, GDB has not been
3659 adjusted to accommodate this. Either someone
3660 needs to demonstrate that the LE/O32 ABI
3661 specifies such a left shift OR this new ABI gets
3662 identified as such and GDB gets tweaked
3665 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3666 && partial_len
< MIPS32_REGSIZE
3667 && (typecode
== TYPE_CODE_STRUCT
3668 || typecode
== TYPE_CODE_UNION
))
3669 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3673 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3675 phex (regval
, MIPS32_REGSIZE
));
3676 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3679 /* Prevent subsequent floating point arguments from
3680 being passed in floating point registers. */
3681 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3687 /* Compute the the offset into the stack at which we
3688 will copy the next parameter.
3690 In older ABIs, the caller reserved space for
3691 registers that contained arguments. This was loosely
3692 refered to as their "home". Consequently, space is
3693 always allocated. */
3695 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3699 fprintf_unfiltered (gdb_stdlog
, "\n");
3702 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3704 /* Return adjusted stack pointer. */
3708 static enum return_value_convention
3709 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3710 struct regcache
*regcache
,
3711 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3713 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3715 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3716 || TYPE_CODE (type
) == TYPE_CODE_UNION
3717 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3718 return RETURN_VALUE_STRUCT_CONVENTION
;
3719 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3720 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3722 /* A single-precision floating-point value. It fits in the
3723 least significant part of FP0. */
3725 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3726 mips_xfer_register (gdbarch
, regcache
,
3727 gdbarch_num_regs (gdbarch
)
3728 + mips_regnum (gdbarch
)->fp0
,
3730 gdbarch_byte_order (gdbarch
),
3731 readbuf
, writebuf
, 0);
3732 return RETURN_VALUE_REGISTER_CONVENTION
;
3734 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3735 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3737 /* A double-precision floating-point value. The most
3738 significant part goes in FP1, and the least significant in
3741 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3742 switch (gdbarch_byte_order (gdbarch
))
3744 case BFD_ENDIAN_LITTLE
:
3745 mips_xfer_register (gdbarch
, regcache
,
3746 gdbarch_num_regs (gdbarch
)
3747 + mips_regnum (gdbarch
)->fp0
+
3748 0, 4, gdbarch_byte_order (gdbarch
),
3749 readbuf
, writebuf
, 0);
3750 mips_xfer_register (gdbarch
, regcache
,
3751 gdbarch_num_regs (gdbarch
)
3752 + mips_regnum (gdbarch
)->fp0
+ 1,
3753 4, gdbarch_byte_order (gdbarch
),
3754 readbuf
, writebuf
, 4);
3756 case BFD_ENDIAN_BIG
:
3757 mips_xfer_register (gdbarch
, regcache
,
3758 gdbarch_num_regs (gdbarch
)
3759 + mips_regnum (gdbarch
)->fp0
+ 1,
3760 4, gdbarch_byte_order (gdbarch
),
3761 readbuf
, writebuf
, 0);
3762 mips_xfer_register (gdbarch
, regcache
,
3763 gdbarch_num_regs (gdbarch
)
3764 + mips_regnum (gdbarch
)->fp0
+ 0,
3765 4, gdbarch_byte_order (gdbarch
),
3766 readbuf
, writebuf
, 4);
3769 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3771 return RETURN_VALUE_REGISTER_CONVENTION
;
3774 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3775 && TYPE_NFIELDS (type
) <= 2
3776 && TYPE_NFIELDS (type
) >= 1
3777 && ((TYPE_NFIELDS (type
) == 1
3778 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3780 || (TYPE_NFIELDS (type
) == 2
3781 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3783 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3785 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3787 /* A struct that contains one or two floats. Each value is part
3788 in the least significant part of their floating point
3790 gdb_byte reg
[MAX_REGISTER_SIZE
];
3793 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3794 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3796 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3799 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3801 mips_xfer_register (gdbarch
, regcache
,
3802 gdbarch_num_regs (gdbarch
) + regnum
,
3803 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3804 gdbarch_byte_order (gdbarch
),
3805 readbuf
, writebuf
, offset
);
3807 return RETURN_VALUE_REGISTER_CONVENTION
;
3811 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3812 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3814 /* A structure or union. Extract the left justified value,
3815 regardless of the byte order. I.e. DO NOT USE
3819 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3820 offset
< TYPE_LENGTH (type
);
3821 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3823 int xfer
= register_size (gdbarch
, regnum
);
3824 if (offset
+ xfer
> TYPE_LENGTH (type
))
3825 xfer
= TYPE_LENGTH (type
) - offset
;
3827 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3828 offset
, xfer
, regnum
);
3829 mips_xfer_register (gdbarch
, regcache
,
3830 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3831 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3833 return RETURN_VALUE_REGISTER_CONVENTION
;
3838 /* A scalar extract each part but least-significant-byte
3839 justified. o32 thinks registers are 4 byte, regardless of
3843 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3844 offset
< TYPE_LENGTH (type
);
3845 offset
+= MIPS32_REGSIZE
, regnum
++)
3847 int xfer
= MIPS32_REGSIZE
;
3848 if (offset
+ xfer
> TYPE_LENGTH (type
))
3849 xfer
= TYPE_LENGTH (type
) - offset
;
3851 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3852 offset
, xfer
, regnum
);
3853 mips_xfer_register (gdbarch
, regcache
,
3854 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3855 gdbarch_byte_order (gdbarch
),
3856 readbuf
, writebuf
, offset
);
3858 return RETURN_VALUE_REGISTER_CONVENTION
;
3862 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3866 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3867 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3869 struct value
**args
, CORE_ADDR sp
,
3870 int struct_return
, CORE_ADDR struct_addr
)
3876 int stack_offset
= 0;
3877 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3878 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3880 /* For shared libraries, "t9" needs to point at the function
3882 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3884 /* Set the return address register to point to the entry point of
3885 the program, where a breakpoint lies in wait. */
3886 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3888 /* First ensure that the stack and structure return address (if any)
3889 are properly aligned. The stack has to be at least 64-bit
3890 aligned even on 32-bit machines, because doubles must be 64-bit
3891 aligned. For n32 and n64, stack frames need to be 128-bit
3892 aligned, so we round to this widest known alignment. */
3894 sp
= align_down (sp
, 16);
3895 struct_addr
= align_down (struct_addr
, 16);
3897 /* Now make space on the stack for the args. */
3898 for (argnum
= 0; argnum
< nargs
; argnum
++)
3900 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3901 int arglen
= TYPE_LENGTH (arg_type
);
3903 /* Allocate space on the stack. */
3904 len
+= align_up (arglen
, MIPS64_REGSIZE
);
3906 sp
-= align_up (len
, 16);
3909 fprintf_unfiltered (gdb_stdlog
,
3910 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3911 paddr_nz (sp
), (long) align_up (len
, 16));
3913 /* Initialize the integer and float register pointers. */
3914 argreg
= MIPS_A0_REGNUM
;
3915 float_argreg
= mips_fpa0_regnum (gdbarch
);
3917 /* The struct_return pointer occupies the first parameter-passing reg. */
3921 fprintf_unfiltered (gdb_stdlog
,
3922 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3923 argreg
, paddr_nz (struct_addr
));
3924 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3925 stack_offset
+= MIPS64_REGSIZE
;
3928 /* Now load as many as possible of the first arguments into
3929 registers, and push the rest onto the stack. Loop thru args
3930 from first to last. */
3931 for (argnum
= 0; argnum
< nargs
; argnum
++)
3933 const gdb_byte
*val
;
3934 struct value
*arg
= args
[argnum
];
3935 struct type
*arg_type
= check_typedef (value_type (arg
));
3936 int len
= TYPE_LENGTH (arg_type
);
3937 enum type_code typecode
= TYPE_CODE (arg_type
);
3940 fprintf_unfiltered (gdb_stdlog
,
3941 "mips_o64_push_dummy_call: %d len=%d type=%d",
3942 argnum
+ 1, len
, (int) typecode
);
3944 val
= value_contents (arg
);
3946 /* Floating point arguments passed in registers have to be
3947 treated specially. On 32-bit architectures, doubles
3948 are passed in register pairs; the even register gets
3949 the low word, and the odd register gets the high word.
3950 On O32/O64, the first two floating point arguments are
3951 also copied to general registers, because MIPS16 functions
3952 don't use float registers for arguments. This duplication of
3953 arguments in general registers can't hurt non-MIPS16 functions
3954 because those registers are normally skipped. */
3956 if (fp_register_arg_p (typecode
, arg_type
)
3957 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3959 LONGEST regval
= extract_unsigned_integer (val
, len
);
3961 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3962 float_argreg
, phex (regval
, len
));
3963 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3965 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3966 argreg
, phex (regval
, len
));
3967 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3969 /* Reserve space for the FP register. */
3970 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
3974 /* Copy the argument to general registers or the stack in
3975 register-sized pieces. Large arguments are split between
3976 registers and stack. */
3977 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
3978 are treated specially: Irix cc passes them in registers
3979 where gcc sometimes puts them on the stack. For maximum
3980 compatibility, we will put them in both places. */
3981 int odd_sized_struct
= (len
> MIPS64_REGSIZE
3982 && len
% MIPS64_REGSIZE
!= 0);
3985 /* Remember if the argument was written to the stack. */
3986 int stack_used_p
= 0;
3987 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3990 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3993 /* Write this portion of the argument to the stack. */
3994 if (argreg
> MIPS_LAST_ARG_REGNUM
3995 || odd_sized_struct
)
3997 /* Should shorter than int integer values be
3998 promoted to int before being stored? */
3999 int longword_offset
= 0;
4002 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4004 if ((typecode
== TYPE_CODE_INT
4005 || typecode
== TYPE_CODE_PTR
4006 || typecode
== TYPE_CODE_FLT
)
4008 longword_offset
= MIPS64_REGSIZE
- len
;
4013 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4014 paddr_nz (stack_offset
));
4015 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4016 paddr_nz (longword_offset
));
4019 addr
= sp
+ stack_offset
+ longword_offset
;
4024 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4026 for (i
= 0; i
< partial_len
; i
++)
4028 fprintf_unfiltered (gdb_stdlog
, "%02x",
4032 write_memory (addr
, val
, partial_len
);
4035 /* Note!!! This is NOT an else clause. Odd sized
4036 structs may go thru BOTH paths. */
4037 /* Write this portion of the argument to a general
4038 purpose register. */
4039 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
4041 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4042 /* Value may need to be sign extended, because
4043 mips_isa_regsize() != mips_abi_regsize(). */
4045 /* A non-floating-point argument being passed in a
4046 general register. If a struct or union, and if
4047 the remaining length is smaller than the register
4048 size, we have to adjust the register value on
4051 It does not seem to be necessary to do the
4052 same for integral types. */
4054 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4055 && partial_len
< MIPS64_REGSIZE
4056 && (typecode
== TYPE_CODE_STRUCT
4057 || typecode
== TYPE_CODE_UNION
))
4058 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4062 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4064 phex (regval
, MIPS64_REGSIZE
));
4065 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4068 /* Prevent subsequent floating point arguments from
4069 being passed in floating point registers. */
4070 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4076 /* Compute the the offset into the stack at which we
4077 will copy the next parameter.
4079 In older ABIs, the caller reserved space for
4080 registers that contained arguments. This was loosely
4081 refered to as their "home". Consequently, space is
4082 always allocated. */
4084 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4088 fprintf_unfiltered (gdb_stdlog
, "\n");
4091 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4093 /* Return adjusted stack pointer. */
4097 static enum return_value_convention
4098 mips_o64_return_value (struct gdbarch
*gdbarch
,
4099 struct type
*type
, struct regcache
*regcache
,
4100 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4102 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4104 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4105 || TYPE_CODE (type
) == TYPE_CODE_UNION
4106 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4107 return RETURN_VALUE_STRUCT_CONVENTION
;
4108 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
4110 /* A floating-point value. It fits in the least significant
4113 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4114 mips_xfer_register (gdbarch
, regcache
,
4115 gdbarch_num_regs (gdbarch
)
4116 + mips_regnum (gdbarch
)->fp0
,
4118 gdbarch_byte_order (gdbarch
),
4119 readbuf
, writebuf
, 0);
4120 return RETURN_VALUE_REGISTER_CONVENTION
;
4124 /* A scalar extract each part but least-significant-byte
4128 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4129 offset
< TYPE_LENGTH (type
);
4130 offset
+= MIPS64_REGSIZE
, regnum
++)
4132 int xfer
= MIPS64_REGSIZE
;
4133 if (offset
+ xfer
> TYPE_LENGTH (type
))
4134 xfer
= TYPE_LENGTH (type
) - offset
;
4136 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4137 offset
, xfer
, regnum
);
4138 mips_xfer_register (gdbarch
, regcache
,
4139 gdbarch_num_regs (gdbarch
) + regnum
,
4140 xfer
, gdbarch_byte_order (gdbarch
),
4141 readbuf
, writebuf
, offset
);
4143 return RETURN_VALUE_REGISTER_CONVENTION
;
4147 /* Floating point register management.
4149 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4150 64bit operations, these early MIPS cpus treat fp register pairs
4151 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4152 registers and offer a compatibility mode that emulates the MIPS2 fp
4153 model. When operating in MIPS2 fp compat mode, later cpu's split
4154 double precision floats into two 32-bit chunks and store them in
4155 consecutive fp regs. To display 64-bit floats stored in this
4156 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4157 Throw in user-configurable endianness and you have a real mess.
4159 The way this works is:
4160 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4161 double-precision value will be split across two logical registers.
4162 The lower-numbered logical register will hold the low-order bits,
4163 regardless of the processor's endianness.
4164 - If we are on a 64-bit processor, and we are looking for a
4165 single-precision value, it will be in the low ordered bits
4166 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4167 save slot in memory.
4168 - If we are in 64-bit mode, everything is straightforward.
4170 Note that this code only deals with "live" registers at the top of the
4171 stack. We will attempt to deal with saved registers later, when
4172 the raw/cooked register interface is in place. (We need a general
4173 interface that can deal with dynamic saved register sizes -- fp
4174 regs could be 32 bits wide in one frame and 64 on the frame above
4177 static struct type
*
4178 mips_float_register_type (void)
4180 return builtin_type_ieee_single
;
4183 static struct type
*
4184 mips_double_register_type (void)
4186 return builtin_type_ieee_double
;
4189 /* Copy a 32-bit single-precision value from the current frame
4190 into rare_buffer. */
4193 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4194 gdb_byte
*rare_buffer
)
4196 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4197 int raw_size
= register_size (gdbarch
, regno
);
4198 gdb_byte
*raw_buffer
= alloca (raw_size
);
4200 if (!frame_register_read (frame
, regno
, raw_buffer
))
4201 error (_("can't read register %d (%s)"),
4202 regno
, gdbarch_register_name (gdbarch
, regno
));
4205 /* We have a 64-bit value for this register. Find the low-order
4209 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4214 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4218 memcpy (rare_buffer
, raw_buffer
, 4);
4222 /* Copy a 64-bit double-precision value from the current frame into
4223 rare_buffer. This may include getting half of it from the next
4227 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4228 gdb_byte
*rare_buffer
)
4230 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4231 int raw_size
= register_size (gdbarch
, regno
);
4233 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4235 /* We have a 64-bit value for this register, and we should use
4237 if (!frame_register_read (frame
, regno
, rare_buffer
))
4238 error (_("can't read register %d (%s)"),
4239 regno
, gdbarch_register_name (gdbarch
, regno
));
4243 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4245 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4246 internal_error (__FILE__
, __LINE__
,
4247 _("mips_read_fp_register_double: bad access to "
4248 "odd-numbered FP register"));
4250 /* mips_read_fp_register_single will find the correct 32 bits from
4252 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4254 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4255 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4259 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4260 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4266 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4268 { /* do values for FP (float) regs */
4269 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4270 gdb_byte
*raw_buffer
;
4271 double doub
, flt1
; /* doubles extracted from raw hex data */
4274 raw_buffer
= alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
));
4276 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4277 fprintf_filtered (file
, "%*s",
4278 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4281 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4283 /* 4-byte registers: Print hex and floating. Also print even
4284 numbered registers as doubles. */
4285 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4286 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4288 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4291 fprintf_filtered (file
, " flt: ");
4293 fprintf_filtered (file
, " <invalid float> ");
4295 fprintf_filtered (file
, "%-17.9g", flt1
);
4297 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4299 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4300 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4303 fprintf_filtered (file
, " dbl: ");
4305 fprintf_filtered (file
, "<invalid double>");
4307 fprintf_filtered (file
, "%-24.17g", doub
);
4312 /* Eight byte registers: print each one as hex, float and double. */
4313 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4314 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4316 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4317 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4320 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4323 fprintf_filtered (file
, " flt: ");
4325 fprintf_filtered (file
, "<invalid float>");
4327 fprintf_filtered (file
, "%-17.9g", flt1
);
4329 fprintf_filtered (file
, " dbl: ");
4331 fprintf_filtered (file
, "<invalid double>");
4333 fprintf_filtered (file
, "%-24.17g", doub
);
4338 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4341 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4342 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4345 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4347 mips_print_fp_register (file
, frame
, regnum
);
4351 /* Get the data in raw format. */
4352 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4354 fprintf_filtered (file
, "%s: [Invalid]",
4355 gdbarch_register_name (gdbarch
, regnum
));
4359 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4361 /* The problem with printing numeric register names (r26, etc.) is that
4362 the user can't use them on input. Probably the best solution is to
4363 fix it so that either the numeric or the funky (a2, etc.) names
4364 are accepted on input. */
4365 if (regnum
< MIPS_NUMREGS
)
4366 fprintf_filtered (file
, "(r%d): ", regnum
);
4368 fprintf_filtered (file
, ": ");
4370 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4372 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4376 print_scalar_formatted (raw_buffer
+ offset
,
4377 register_type (gdbarch
, regnum
), 'x', 0,
4381 /* Replacement for generic do_registers_info.
4382 Print regs in pretty columns. */
4385 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4388 fprintf_filtered (file
, " ");
4389 mips_print_fp_register (file
, frame
, regnum
);
4390 fprintf_filtered (file
, "\n");
4395 /* Print a row's worth of GP (int) registers, with name labels above */
4398 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4401 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4402 /* do values for GP (int) regs */
4403 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4404 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4408 /* For GP registers, we print a separate row of names above the vals */
4409 for (col
= 0, regnum
= start_regnum
;
4410 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4411 + gdbarch_num_pseudo_regs (gdbarch
);
4414 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4415 continue; /* unused register */
4416 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4418 break; /* end the row: reached FP register */
4419 /* Large registers are handled separately. */
4420 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4423 break; /* End the row before this register. */
4425 /* Print this register on a row by itself. */
4426 mips_print_register (file
, frame
, regnum
);
4427 fprintf_filtered (file
, "\n");
4431 fprintf_filtered (file
, " ");
4432 fprintf_filtered (file
,
4433 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4434 gdbarch_register_name (gdbarch
, regnum
));
4441 /* print the R0 to R31 names */
4442 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4443 fprintf_filtered (file
, "\n R%-4d",
4444 start_regnum
% gdbarch_num_regs (gdbarch
));
4446 fprintf_filtered (file
, "\n ");
4448 /* now print the values in hex, 4 or 8 to the row */
4449 for (col
= 0, regnum
= start_regnum
;
4450 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4451 + gdbarch_num_pseudo_regs (gdbarch
);
4454 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4455 continue; /* unused register */
4456 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4458 break; /* end row: reached FP register */
4459 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4460 break; /* End row: large register. */
4462 /* OK: get the data in raw format. */
4463 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4464 error (_("can't read register %d (%s)"),
4465 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4466 /* pad small registers */
4468 byte
< (mips_abi_regsize (gdbarch
)
4469 - register_size (gdbarch
, regnum
)); byte
++)
4470 printf_filtered (" ");
4471 /* Now print the register value in hex, endian order. */
4472 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4474 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4475 byte
< register_size (gdbarch
, regnum
); byte
++)
4476 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4478 for (byte
= register_size (gdbarch
, regnum
) - 1;
4480 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4481 fprintf_filtered (file
, " ");
4484 if (col
> 0) /* ie. if we actually printed anything... */
4485 fprintf_filtered (file
, "\n");
4490 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4493 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4494 struct frame_info
*frame
, int regnum
, int all
)
4496 if (regnum
!= -1) /* do one specified register */
4498 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4499 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4500 error (_("Not a valid register for the current processor type"));
4502 mips_print_register (file
, frame
, regnum
);
4503 fprintf_filtered (file
, "\n");
4506 /* do all (or most) registers */
4508 regnum
= gdbarch_num_regs (gdbarch
);
4509 while (regnum
< gdbarch_num_regs (gdbarch
)
4510 + gdbarch_num_pseudo_regs (gdbarch
))
4512 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4515 if (all
) /* true for "INFO ALL-REGISTERS" command */
4516 regnum
= print_fp_register_row (file
, frame
, regnum
);
4518 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4521 regnum
= print_gp_register_row (file
, frame
, regnum
);
4526 /* Is this a branch with a delay slot? */
4529 is_delayed (unsigned long insn
)
4532 for (i
= 0; i
< NUMOPCODES
; ++i
)
4533 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4534 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4536 return (i
< NUMOPCODES
4537 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4538 | INSN_COND_BRANCH_DELAY
4539 | INSN_COND_BRANCH_LIKELY
)));
4543 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4544 struct frame_info
*frame
)
4546 CORE_ADDR pc
= get_frame_pc (frame
);
4547 gdb_byte buf
[MIPS_INSN32_SIZE
];
4549 /* There is no branch delay slot on MIPS16. */
4550 if (mips_pc_is_mips16 (pc
))
4553 if (!breakpoint_here_p (pc
+ 4))
4556 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4557 /* If error reading memory, guess that it is not a delayed
4560 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4563 /* To skip prologues, I use this predicate. Returns either PC itself
4564 if the code at PC does not look like a function prologue; otherwise
4565 returns an address that (if we're lucky) follows the prologue. If
4566 LENIENT, then we must skip everything which is involved in setting
4567 up the frame (it's OK to skip more, just so long as we don't skip
4568 anything which might clobber the registers which are being saved.
4569 We must skip more in the case where part of the prologue is in the
4570 delay slot of a non-prologue instruction). */
4573 mips_skip_prologue (CORE_ADDR pc
)
4576 CORE_ADDR func_addr
;
4578 /* See if we can determine the end of the prologue via the symbol table.
4579 If so, then return either PC, or the PC after the prologue, whichever
4581 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4583 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4584 if (post_prologue_pc
!= 0)
4585 return max (pc
, post_prologue_pc
);
4588 /* Can't determine prologue from the symbol table, need to examine
4591 /* Find an upper limit on the function prologue using the debug
4592 information. If the debug information could not be used to provide
4593 that bound, then use an arbitrary large number as the upper bound. */
4594 limit_pc
= skip_prologue_using_sal (pc
);
4596 limit_pc
= pc
+ 100; /* Magic. */
4598 if (mips_pc_is_mips16 (pc
))
4599 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4601 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4604 /* Check whether the PC is in a function epilogue (32-bit version).
4605 This is a helper function for mips_in_function_epilogue_p. */
4607 mips32_in_function_epilogue_p (CORE_ADDR pc
)
4609 CORE_ADDR func_addr
= 0, func_end
= 0;
4611 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4613 /* The MIPS epilogue is max. 12 bytes long. */
4614 CORE_ADDR addr
= func_end
- 12;
4616 if (addr
< func_addr
+ 4)
4617 addr
= func_addr
+ 4;
4621 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4623 unsigned long high_word
;
4626 inst
= mips_fetch_instruction (pc
);
4627 high_word
= (inst
>> 16) & 0xffff;
4629 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4630 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4631 && inst
!= 0x03e00008 /* jr $ra */
4632 && inst
!= 0x00000000) /* nop */
4642 /* Check whether the PC is in a function epilogue (16-bit version).
4643 This is a helper function for mips_in_function_epilogue_p. */
4645 mips16_in_function_epilogue_p (CORE_ADDR pc
)
4647 CORE_ADDR func_addr
= 0, func_end
= 0;
4649 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4651 /* The MIPS epilogue is max. 12 bytes long. */
4652 CORE_ADDR addr
= func_end
- 12;
4654 if (addr
< func_addr
+ 4)
4655 addr
= func_addr
+ 4;
4659 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4661 unsigned short inst
;
4663 inst
= mips_fetch_instruction (pc
);
4665 if ((inst
& 0xf800) == 0xf000) /* extend */
4668 if (inst
!= 0x6300 /* addiu $sp,offset */
4669 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
4670 && inst
!= 0xe820 /* jr $ra */
4671 && inst
!= 0xe8a0 /* jrc $ra */
4672 && inst
!= 0x6500) /* nop */
4682 /* The epilogue is defined here as the area at the end of a function,
4683 after an instruction which destroys the function's stack frame. */
4685 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4687 if (mips_pc_is_mips16 (pc
))
4688 return mips16_in_function_epilogue_p (pc
);
4690 return mips32_in_function_epilogue_p (pc
);
4693 /* Root of all "set mips "/"show mips " commands. This will eventually be
4694 used for all MIPS-specific commands. */
4697 show_mips_command (char *args
, int from_tty
)
4699 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4703 set_mips_command (char *args
, int from_tty
)
4706 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4707 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4710 /* Commands to show/set the MIPS FPU type. */
4713 show_mipsfpu_command (char *args
, int from_tty
)
4717 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
4720 ("The MIPS floating-point coprocessor is unknown "
4721 "because the current architecture is not MIPS.\n");
4725 switch (MIPS_FPU_TYPE
)
4727 case MIPS_FPU_SINGLE
:
4728 fpu
= "single-precision";
4730 case MIPS_FPU_DOUBLE
:
4731 fpu
= "double-precision";
4734 fpu
= "absent (none)";
4737 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4739 if (mips_fpu_type_auto
)
4741 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4745 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4750 set_mipsfpu_command (char *args
, int from_tty
)
4753 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4754 show_mipsfpu_command (args
, from_tty
);
4758 set_mipsfpu_single_command (char *args
, int from_tty
)
4760 struct gdbarch_info info
;
4761 gdbarch_info_init (&info
);
4762 mips_fpu_type
= MIPS_FPU_SINGLE
;
4763 mips_fpu_type_auto
= 0;
4764 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4765 instead of relying on globals. Doing that would let generic code
4766 handle the search for this specific architecture. */
4767 if (!gdbarch_update_p (info
))
4768 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4772 set_mipsfpu_double_command (char *args
, int from_tty
)
4774 struct gdbarch_info info
;
4775 gdbarch_info_init (&info
);
4776 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4777 mips_fpu_type_auto
= 0;
4778 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4779 instead of relying on globals. Doing that would let generic code
4780 handle the search for this specific architecture. */
4781 if (!gdbarch_update_p (info
))
4782 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4786 set_mipsfpu_none_command (char *args
, int from_tty
)
4788 struct gdbarch_info info
;
4789 gdbarch_info_init (&info
);
4790 mips_fpu_type
= MIPS_FPU_NONE
;
4791 mips_fpu_type_auto
= 0;
4792 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4793 instead of relying on globals. Doing that would let generic code
4794 handle the search for this specific architecture. */
4795 if (!gdbarch_update_p (info
))
4796 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4800 set_mipsfpu_auto_command (char *args
, int from_tty
)
4802 mips_fpu_type_auto
= 1;
4805 /* Attempt to identify the particular processor model by reading the
4806 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4807 the relevant processor still exists (it dates back to '94) and
4808 secondly this is not the way to do this. The processor type should
4809 be set by forcing an architecture change. */
4812 deprecated_mips_set_processor_regs_hack (void)
4814 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4817 regcache_cooked_read_unsigned (get_current_regcache (),
4818 MIPS_PRID_REGNUM
, &prid
);
4819 if ((prid
& ~0xf) == 0x700)
4820 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4823 /* Just like reinit_frame_cache, but with the right arguments to be
4824 callable as an sfunc. */
4827 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4828 struct cmd_list_element
*c
)
4830 reinit_frame_cache ();
4834 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4836 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4838 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4839 disassembler needs to be able to locally determine the ISA, and
4840 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4842 if (mips_pc_is_mips16 (memaddr
))
4843 info
->mach
= bfd_mach_mips16
;
4845 /* Round down the instruction address to the appropriate boundary. */
4846 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4848 /* Set the disassembler options. */
4849 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4851 /* Set up the disassembler info, so that we get the right
4852 register names from libopcodes. */
4853 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4854 info
->disassembler_options
= "gpr-names=n32";
4856 info
->disassembler_options
= "gpr-names=64";
4857 info
->flavour
= bfd_target_elf_flavour
;
4860 /* This string is not recognized explicitly by the disassembler,
4861 but it tells the disassembler to not try to guess the ABI from
4862 the bfd elf headers, such that, if the user overrides the ABI
4863 of a program linked as NewABI, the disassembly will follow the
4864 register naming conventions specified by the user. */
4865 info
->disassembler_options
= "gpr-names=32";
4867 /* Call the appropriate disassembler based on the target endian-ness. */
4868 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4869 return print_insn_big_mips (memaddr
, info
);
4871 return print_insn_little_mips (memaddr
, info
);
4874 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4875 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4876 It returns a pointer to a string of bytes that encode a breakpoint
4877 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4878 necessary) to point to the actual memory location where the breakpoint
4879 should be inserted. */
4881 static const gdb_byte
*
4882 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
4884 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4886 if (mips_pc_is_mips16 (*pcptr
))
4888 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4889 *pcptr
= unmake_mips16_addr (*pcptr
);
4890 *lenptr
= sizeof (mips16_big_breakpoint
);
4891 return mips16_big_breakpoint
;
4895 /* The IDT board uses an unusual breakpoint value, and
4896 sometimes gets confused when it sees the usual MIPS
4897 breakpoint instruction. */
4898 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4899 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4900 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4902 *lenptr
= sizeof (big_breakpoint
);
4904 if (strcmp (target_shortname
, "mips") == 0)
4905 return idt_big_breakpoint
;
4906 else if (strcmp (target_shortname
, "ddb") == 0
4907 || strcmp (target_shortname
, "pmon") == 0
4908 || strcmp (target_shortname
, "lsi") == 0)
4909 return pmon_big_breakpoint
;
4911 return big_breakpoint
;
4916 if (mips_pc_is_mips16 (*pcptr
))
4918 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4919 *pcptr
= unmake_mips16_addr (*pcptr
);
4920 *lenptr
= sizeof (mips16_little_breakpoint
);
4921 return mips16_little_breakpoint
;
4925 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4926 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4927 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4929 *lenptr
= sizeof (little_breakpoint
);
4931 if (strcmp (target_shortname
, "mips") == 0)
4932 return idt_little_breakpoint
;
4933 else if (strcmp (target_shortname
, "ddb") == 0
4934 || strcmp (target_shortname
, "pmon") == 0
4935 || strcmp (target_shortname
, "lsi") == 0)
4936 return pmon_little_breakpoint
;
4938 return little_breakpoint
;
4943 /* If PC is in a mips16 call or return stub, return the address of the target
4944 PC, which is either the callee or the caller. There are several
4945 cases which must be handled:
4947 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4948 target PC is in $31 ($ra).
4949 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4950 and the target PC is in $2.
4951 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4952 before the jal instruction, this is effectively a call stub
4953 and the the target PC is in $2. Otherwise this is effectively
4954 a return stub and the target PC is in $18.
4956 See the source code for the stubs in gcc/config/mips/mips16.S for
4960 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
4963 CORE_ADDR start_addr
;
4965 /* Find the starting address and name of the function containing the PC. */
4966 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4969 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4970 target PC is in $31 ($ra). */
4971 if (strcmp (name
, "__mips16_ret_sf") == 0
4972 || strcmp (name
, "__mips16_ret_df") == 0)
4973 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
4975 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4977 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4978 and the target PC is in $2. */
4979 if (name
[19] >= '0' && name
[19] <= '9')
4980 return get_frame_register_signed (frame
, 2);
4982 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4983 before the jal instruction, this is effectively a call stub
4984 and the the target PC is in $2. Otherwise this is effectively
4985 a return stub and the target PC is in $18. */
4986 else if (name
[19] == 's' || name
[19] == 'd')
4988 if (pc
== start_addr
)
4990 /* Check if the target of the stub is a compiler-generated
4991 stub. Such a stub for a function bar might have a name
4992 like __fn_stub_bar, and might look like this:
4997 la $1,bar (becomes a lui/addiu pair)
4999 So scan down to the lui/addi and extract the target
5000 address from those two instructions. */
5002 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5006 /* See if the name of the target function is __fn_stub_*. */
5007 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5010 if (strncmp (name
, "__fn_stub_", 10) != 0
5011 && strcmp (name
, "etext") != 0
5012 && strcmp (name
, "_etext") != 0)
5015 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5016 The limit on the search is arbitrarily set to 20
5017 instructions. FIXME. */
5018 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5020 inst
= mips_fetch_instruction (target_pc
);
5021 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5022 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5023 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5024 return pc
| (inst
& 0xffff); /* low word */
5027 /* Couldn't find the lui/addui pair, so return stub address. */
5031 /* This is the 'return' part of a call stub. The return
5032 address is in $r18. */
5033 return get_frame_register_signed (frame
, 18);
5036 return 0; /* not a stub */
5039 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5040 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5043 mips_stab_reg_to_regnum (int num
)
5046 if (num
>= 0 && num
< 32)
5048 else if (num
>= 38 && num
< 70)
5049 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5051 regnum
= mips_regnum (current_gdbarch
)->hi
;
5053 regnum
= mips_regnum (current_gdbarch
)->lo
;
5055 /* This will hopefully (eventually) provoke a warning. Should
5056 we be calling complaint() here? */
5057 return gdbarch_num_regs (current_gdbarch
)
5058 + gdbarch_num_pseudo_regs (current_gdbarch
);
5059 return gdbarch_num_regs (current_gdbarch
) + regnum
;
5063 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5064 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5067 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5070 if (num
>= 0 && num
< 32)
5072 else if (num
>= 32 && num
< 64)
5073 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5075 regnum
= mips_regnum (current_gdbarch
)->hi
;
5077 regnum
= mips_regnum (current_gdbarch
)->lo
;
5079 /* This will hopefully (eventually) provoke a warning. Should we
5080 be calling complaint() here? */
5081 return gdbarch_num_regs (current_gdbarch
)
5082 + gdbarch_num_pseudo_regs (current_gdbarch
);
5083 return gdbarch_num_regs (current_gdbarch
) + regnum
;
5087 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5089 /* Only makes sense to supply raw registers. */
5090 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5091 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5092 decide if it is valid. Should instead define a standard sim/gdb
5093 register numbering scheme. */
5094 if (gdbarch_register_name (gdbarch
,
5095 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5096 && gdbarch_register_name (gdbarch
,
5097 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
5100 return LEGACY_SIM_REGNO_IGNORE
;
5104 /* Convert an integer into an address. Extracting the value signed
5105 guarantees a correctly sign extended address. */
5108 mips_integer_to_address (struct gdbarch
*gdbarch
,
5109 struct type
*type
, const gdb_byte
*buf
)
5111 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
5114 /* Dummy virtual frame pointer method. This is no more or less accurate
5115 than most other architectures; we just need to be explicit about it,
5116 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5117 an assertion failure. */
5120 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5121 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5123 *reg
= MIPS_SP_REGNUM
;
5128 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5130 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5131 const char *name
= bfd_get_section_name (abfd
, sect
);
5133 if (*abip
!= MIPS_ABI_UNKNOWN
)
5136 if (strncmp (name
, ".mdebug.", 8) != 0)
5139 if (strcmp (name
, ".mdebug.abi32") == 0)
5140 *abip
= MIPS_ABI_O32
;
5141 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5142 *abip
= MIPS_ABI_N32
;
5143 else if (strcmp (name
, ".mdebug.abi64") == 0)
5144 *abip
= MIPS_ABI_N64
;
5145 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5146 *abip
= MIPS_ABI_O64
;
5147 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5148 *abip
= MIPS_ABI_EABI32
;
5149 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5150 *abip
= MIPS_ABI_EABI64
;
5152 warning (_("unsupported ABI %s."), name
+ 8);
5156 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5158 int *lbp
= (int *) obj
;
5159 const char *name
= bfd_get_section_name (abfd
, sect
);
5161 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5163 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5165 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5166 warning (_("unrecognized .gcc_compiled_longXX"));
5169 static enum mips_abi
5170 global_mips_abi (void)
5174 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5175 if (mips_abi_strings
[i
] == mips_abi_string
)
5176 return (enum mips_abi
) i
;
5178 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5182 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5184 /* If the size matches the set of 32-bit or 64-bit integer registers,
5185 assume that's what we've got. */
5186 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5187 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5189 /* If the size matches the full set of registers GDB traditionally
5190 knows about, including floating point, for either 32-bit or
5191 64-bit, assume that's what we've got. */
5192 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5193 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5195 /* Otherwise we don't have a useful guess. */
5198 static struct value
*
5199 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5201 const int *reg_p
= baton
;
5202 return value_of_register (*reg_p
, frame
);
5205 static struct gdbarch
*
5206 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5208 struct gdbarch
*gdbarch
;
5209 struct gdbarch_tdep
*tdep
;
5211 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5213 enum mips_fpu_type fpu_type
;
5214 struct tdesc_arch_data
*tdesc_data
= NULL
;
5215 int elf_fpu_type
= 0;
5217 /* Check any target description for validity. */
5218 if (tdesc_has_registers (info
.target_desc
))
5220 static const char *const mips_gprs
[] = {
5221 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5222 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5223 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5224 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5226 static const char *const mips_fprs
[] = {
5227 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5228 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5229 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5230 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5233 const struct tdesc_feature
*feature
;
5236 feature
= tdesc_find_feature (info
.target_desc
,
5237 "org.gnu.gdb.mips.cpu");
5238 if (feature
== NULL
)
5241 tdesc_data
= tdesc_data_alloc ();
5244 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5245 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5249 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5250 MIPS_EMBED_LO_REGNUM
, "lo");
5251 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5252 MIPS_EMBED_HI_REGNUM
, "hi");
5253 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5254 MIPS_EMBED_PC_REGNUM
, "pc");
5258 tdesc_data_cleanup (tdesc_data
);
5262 feature
= tdesc_find_feature (info
.target_desc
,
5263 "org.gnu.gdb.mips.cp0");
5264 if (feature
== NULL
)
5266 tdesc_data_cleanup (tdesc_data
);
5271 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5272 MIPS_EMBED_BADVADDR_REGNUM
,
5274 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5275 MIPS_PS_REGNUM
, "status");
5276 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5277 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5281 tdesc_data_cleanup (tdesc_data
);
5285 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5286 backend is not prepared for that, though. */
5287 feature
= tdesc_find_feature (info
.target_desc
,
5288 "org.gnu.gdb.mips.fpu");
5289 if (feature
== NULL
)
5291 tdesc_data_cleanup (tdesc_data
);
5296 for (i
= 0; i
< 32; i
++)
5297 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5298 i
+ MIPS_EMBED_FP0_REGNUM
,
5301 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5302 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5303 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5304 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5308 tdesc_data_cleanup (tdesc_data
);
5312 /* It would be nice to detect an attempt to use a 64-bit ABI
5313 when only 32-bit registers are provided. */
5316 /* First of all, extract the elf_flags, if available. */
5317 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5318 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5319 else if (arches
!= NULL
)
5320 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5324 fprintf_unfiltered (gdb_stdlog
,
5325 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5327 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5328 switch ((elf_flags
& EF_MIPS_ABI
))
5330 case E_MIPS_ABI_O32
:
5331 found_abi
= MIPS_ABI_O32
;
5333 case E_MIPS_ABI_O64
:
5334 found_abi
= MIPS_ABI_O64
;
5336 case E_MIPS_ABI_EABI32
:
5337 found_abi
= MIPS_ABI_EABI32
;
5339 case E_MIPS_ABI_EABI64
:
5340 found_abi
= MIPS_ABI_EABI64
;
5343 if ((elf_flags
& EF_MIPS_ABI2
))
5344 found_abi
= MIPS_ABI_N32
;
5346 found_abi
= MIPS_ABI_UNKNOWN
;
5350 /* GCC creates a pseudo-section whose name describes the ABI. */
5351 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5352 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5354 /* If we have no useful BFD information, use the ABI from the last
5355 MIPS architecture (if there is one). */
5356 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5357 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5359 /* Try the architecture for any hint of the correct ABI. */
5360 if (found_abi
== MIPS_ABI_UNKNOWN
5361 && info
.bfd_arch_info
!= NULL
5362 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5364 switch (info
.bfd_arch_info
->mach
)
5366 case bfd_mach_mips3900
:
5367 found_abi
= MIPS_ABI_EABI32
;
5369 case bfd_mach_mips4100
:
5370 case bfd_mach_mips5000
:
5371 found_abi
= MIPS_ABI_EABI64
;
5373 case bfd_mach_mips8000
:
5374 case bfd_mach_mips10000
:
5375 /* On Irix, ELF64 executables use the N64 ABI. The
5376 pseudo-sections which describe the ABI aren't present
5377 on IRIX. (Even for executables created by gcc.) */
5378 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5379 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5380 found_abi
= MIPS_ABI_N64
;
5382 found_abi
= MIPS_ABI_N32
;
5387 /* Default 64-bit objects to N64 instead of O32. */
5388 if (found_abi
== MIPS_ABI_UNKNOWN
5389 && info
.abfd
!= NULL
5390 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5391 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5392 found_abi
= MIPS_ABI_N64
;
5395 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5398 /* What has the user specified from the command line? */
5399 wanted_abi
= global_mips_abi ();
5401 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5404 /* Now that we have found what the ABI for this binary would be,
5405 check whether the user is overriding it. */
5406 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5407 mips_abi
= wanted_abi
;
5408 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5409 mips_abi
= found_abi
;
5411 mips_abi
= MIPS_ABI_O32
;
5413 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5416 /* Also used when doing an architecture lookup. */
5418 fprintf_unfiltered (gdb_stdlog
,
5419 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5420 mips64_transfers_32bit_regs_p
);
5422 /* Determine the MIPS FPU type. */
5425 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5426 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5427 Tag_GNU_MIPS_ABI_FP
);
5428 #endif /* HAVE_ELF */
5430 if (!mips_fpu_type_auto
)
5431 fpu_type
= mips_fpu_type
;
5432 else if (elf_fpu_type
!= 0)
5434 switch (elf_fpu_type
)
5437 fpu_type
= MIPS_FPU_DOUBLE
;
5440 fpu_type
= MIPS_FPU_SINGLE
;
5444 /* Soft float or unknown. */
5445 fpu_type
= MIPS_FPU_NONE
;
5449 else if (info
.bfd_arch_info
!= NULL
5450 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5451 switch (info
.bfd_arch_info
->mach
)
5453 case bfd_mach_mips3900
:
5454 case bfd_mach_mips4100
:
5455 case bfd_mach_mips4111
:
5456 case bfd_mach_mips4120
:
5457 fpu_type
= MIPS_FPU_NONE
;
5459 case bfd_mach_mips4650
:
5460 fpu_type
= MIPS_FPU_SINGLE
;
5463 fpu_type
= MIPS_FPU_DOUBLE
;
5466 else if (arches
!= NULL
)
5467 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5469 fpu_type
= MIPS_FPU_DOUBLE
;
5471 fprintf_unfiltered (gdb_stdlog
,
5472 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5474 /* Check for blatant incompatibilities. */
5476 /* If we have only 32-bit registers, then we can't debug a 64-bit
5478 if (info
.target_desc
5479 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5480 && mips_abi
!= MIPS_ABI_EABI32
5481 && mips_abi
!= MIPS_ABI_O32
)
5483 if (tdesc_data
!= NULL
)
5484 tdesc_data_cleanup (tdesc_data
);
5488 /* try to find a pre-existing architecture */
5489 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5491 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5493 /* MIPS needs to be pedantic about which ABI the object is
5495 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5497 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5499 /* Need to be pedantic about which register virtual size is
5501 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5502 != mips64_transfers_32bit_regs_p
)
5504 /* Be pedantic about which FPU is selected. */
5505 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5508 if (tdesc_data
!= NULL
)
5509 tdesc_data_cleanup (tdesc_data
);
5510 return arches
->gdbarch
;
5513 /* Need a new architecture. Fill in a target specific vector. */
5514 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5515 gdbarch
= gdbarch_alloc (&info
, tdep
);
5516 tdep
->elf_flags
= elf_flags
;
5517 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5518 tdep
->found_abi
= found_abi
;
5519 tdep
->mips_abi
= mips_abi
;
5520 tdep
->mips_fpu_type
= fpu_type
;
5521 tdep
->register_size_valid_p
= 0;
5522 tdep
->register_size
= 0;
5524 if (info
.target_desc
)
5526 /* Some useful properties can be inferred from the target. */
5527 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5529 tdep
->register_size_valid_p
= 1;
5530 tdep
->register_size
= 4;
5532 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5534 tdep
->register_size_valid_p
= 1;
5535 tdep
->register_size
= 8;
5539 /* Initially set everything according to the default ABI/ISA. */
5540 set_gdbarch_short_bit (gdbarch
, 16);
5541 set_gdbarch_int_bit (gdbarch
, 32);
5542 set_gdbarch_float_bit (gdbarch
, 32);
5543 set_gdbarch_double_bit (gdbarch
, 64);
5544 set_gdbarch_long_double_bit (gdbarch
, 64);
5545 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5546 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5547 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5549 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5550 mips_elf_make_msymbol_special
);
5552 /* Fill in the OS dependant register numbers and names. */
5554 const char **reg_names
;
5555 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5556 struct mips_regnum
);
5557 if (tdesc_has_registers (info
.target_desc
))
5559 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5560 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5561 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5562 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5563 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5564 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5565 regnum
->fp_control_status
= 70;
5566 regnum
->fp_implementation_revision
= 71;
5567 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5570 else if (info
.osabi
== GDB_OSABI_IRIX
)
5575 regnum
->badvaddr
= 66;
5578 regnum
->fp_control_status
= 69;
5579 regnum
->fp_implementation_revision
= 70;
5581 reg_names
= mips_irix_reg_names
;
5585 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5586 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5587 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5588 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5589 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5590 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5591 regnum
->fp_control_status
= 70;
5592 regnum
->fp_implementation_revision
= 71;
5594 if (info
.bfd_arch_info
!= NULL
5595 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5596 reg_names
= mips_tx39_reg_names
;
5598 reg_names
= mips_generic_reg_names
;
5600 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5601 replaced by read_pc? */
5602 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5603 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5604 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5605 set_gdbarch_num_regs (gdbarch
, num_regs
);
5606 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5607 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5608 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
5609 tdep
->mips_processor_reg_names
= reg_names
;
5610 tdep
->regnum
= regnum
;
5616 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5617 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5618 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5619 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5620 tdep
->default_mask_address_p
= 0;
5621 set_gdbarch_long_bit (gdbarch
, 32);
5622 set_gdbarch_ptr_bit (gdbarch
, 32);
5623 set_gdbarch_long_long_bit (gdbarch
, 64);
5626 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5627 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5628 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5629 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5630 tdep
->default_mask_address_p
= 0;
5631 set_gdbarch_long_bit (gdbarch
, 32);
5632 set_gdbarch_ptr_bit (gdbarch
, 32);
5633 set_gdbarch_long_long_bit (gdbarch
, 64);
5635 case MIPS_ABI_EABI32
:
5636 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5637 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5638 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5639 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5640 tdep
->default_mask_address_p
= 0;
5641 set_gdbarch_long_bit (gdbarch
, 32);
5642 set_gdbarch_ptr_bit (gdbarch
, 32);
5643 set_gdbarch_long_long_bit (gdbarch
, 64);
5645 case MIPS_ABI_EABI64
:
5646 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5647 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5648 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5649 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5650 tdep
->default_mask_address_p
= 0;
5651 set_gdbarch_long_bit (gdbarch
, 64);
5652 set_gdbarch_ptr_bit (gdbarch
, 64);
5653 set_gdbarch_long_long_bit (gdbarch
, 64);
5656 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5657 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5658 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5659 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5660 tdep
->default_mask_address_p
= 0;
5661 set_gdbarch_long_bit (gdbarch
, 32);
5662 set_gdbarch_ptr_bit (gdbarch
, 32);
5663 set_gdbarch_long_long_bit (gdbarch
, 64);
5664 set_gdbarch_long_double_bit (gdbarch
, 128);
5665 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5668 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5669 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5670 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5671 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5672 tdep
->default_mask_address_p
= 0;
5673 set_gdbarch_long_bit (gdbarch
, 64);
5674 set_gdbarch_ptr_bit (gdbarch
, 64);
5675 set_gdbarch_long_long_bit (gdbarch
, 64);
5676 set_gdbarch_long_double_bit (gdbarch
, 128);
5677 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5680 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5683 /* GCC creates a pseudo-section whose name specifies the size of
5684 longs, since -mlong32 or -mlong64 may be used independent of
5685 other options. How those options affect pointer sizes is ABI and
5686 architecture dependent, so use them to override the default sizes
5687 set by the ABI. This table shows the relationship between ABI,
5688 -mlongXX, and size of pointers:
5690 ABI -mlongXX ptr bits
5691 --- -------- --------
5705 Note that for o32 and eabi32, pointers are always 32 bits
5706 regardless of any -mlongXX option. For all others, pointers and
5707 longs are the same, as set by -mlongXX or set by defaults.
5710 if (info
.abfd
!= NULL
)
5714 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5717 set_gdbarch_long_bit (gdbarch
, long_bit
);
5721 case MIPS_ABI_EABI32
:
5726 case MIPS_ABI_EABI64
:
5727 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5730 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5735 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5736 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5739 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5740 flag in object files because to do so would make it impossible to
5741 link with libraries compiled without "-gp32". This is
5742 unnecessarily restrictive.
5744 We could solve this problem by adding "-gp32" multilibs to gcc,
5745 but to set this flag before gcc is built with such multilibs will
5746 break too many systems.''
5748 But even more unhelpfully, the default linker output target for
5749 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5750 for 64-bit programs - you need to change the ABI to change this,
5751 and not all gcc targets support that currently. Therefore using
5752 this flag to detect 32-bit mode would do the wrong thing given
5753 the current gcc - it would make GDB treat these 64-bit programs
5754 as 32-bit programs by default. */
5756 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5757 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5759 /* Add/remove bits from an address. The MIPS needs be careful to
5760 ensure that all 32 bit addresses are sign extended to 64 bits. */
5761 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5763 /* Unwind the frame. */
5764 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5765 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5766 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5768 /* Map debug register numbers onto internal register numbers. */
5769 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5770 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5771 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5772 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5773 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5774 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5775 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5776 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5778 /* MIPS version of CALL_DUMMY */
5780 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5781 replaced by a command, and all targets will default to on stack
5782 (regardless of the stack's execute status). */
5783 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5784 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5786 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5787 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5788 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5790 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5791 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5793 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5795 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
5797 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5798 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5799 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5801 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5803 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5805 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5807 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5808 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5809 need to all be folded into the target vector. Since they are
5810 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5811 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5813 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5815 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5817 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5819 /* Virtual tables. */
5820 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5822 mips_register_g_packet_guesses (gdbarch
);
5824 /* Hook in OS ABI-specific overrides, if they have been registered. */
5825 info
.tdep_info
= (void *) tdesc_data
;
5826 gdbarch_init_osabi (info
, gdbarch
);
5828 /* Unwind the frame. */
5829 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
5830 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5831 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5832 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5833 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
5834 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5835 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5836 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5840 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
5841 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
5843 /* Override the normal target description methods to handle our
5844 dual real and pseudo registers. */
5845 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5846 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
5848 num_regs
= gdbarch_num_regs (gdbarch
);
5849 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5850 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
5851 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5854 /* Add ABI-specific aliases for the registers. */
5855 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
5856 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
5857 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
5858 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
5860 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
5861 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
5862 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
5864 /* Add some other standard aliases. */
5865 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
5866 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
5867 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
5873 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5875 struct gdbarch_info info
;
5877 /* Force the architecture to update, and (if it's a MIPS architecture)
5878 mips_gdbarch_init will take care of the rest. */
5879 gdbarch_info_init (&info
);
5880 gdbarch_update_p (info
);
5883 /* Print out which MIPS ABI is in use. */
5886 show_mips_abi (struct ui_file
*file
,
5888 struct cmd_list_element
*ignored_cmd
,
5889 const char *ignored_value
)
5891 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5894 "The MIPS ABI is unknown because the current architecture "
5898 enum mips_abi global_abi
= global_mips_abi ();
5899 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5900 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5902 if (global_abi
== MIPS_ABI_UNKNOWN
)
5905 "The MIPS ABI is set automatically (currently \"%s\").\n",
5907 else if (global_abi
== actual_abi
)
5910 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5914 /* Probably shouldn't happen... */
5917 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5918 actual_abi_str
, mips_abi_strings
[global_abi
]);
5924 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
5926 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5930 int ef_mips_32bitmode
;
5931 /* Determine the ISA. */
5932 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5950 /* Determine the size of a pointer. */
5951 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5952 fprintf_unfiltered (file
,
5953 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5955 fprintf_unfiltered (file
,
5956 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5958 fprintf_unfiltered (file
,
5959 "mips_dump_tdep: ef_mips_arch = %d\n",
5961 fprintf_unfiltered (file
,
5962 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5963 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5964 fprintf_unfiltered (file
,
5965 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5966 mips_mask_address_p (tdep
),
5967 tdep
->default_mask_address_p
);
5969 fprintf_unfiltered (file
,
5970 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5971 MIPS_DEFAULT_FPU_TYPE
,
5972 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5973 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5974 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5976 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5977 fprintf_unfiltered (file
,
5978 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5980 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5981 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5982 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5986 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5989 _initialize_mips_tdep (void)
5991 static struct cmd_list_element
*mipsfpulist
= NULL
;
5992 struct cmd_list_element
*c
;
5994 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5995 if (MIPS_ABI_LAST
+ 1
5996 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5997 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
5999 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6001 mips_pdr_data
= register_objfile_data ();
6003 /* Create feature sets with the appropriate properties. The values
6004 are not important. */
6005 mips_tdesc_gp32
= allocate_target_description ();
6006 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6008 mips_tdesc_gp64
= allocate_target_description ();
6009 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6011 /* Add root prefix command for all "set mips"/"show mips" commands */
6012 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6013 _("Various MIPS specific commands."),
6014 &setmipscmdlist
, "set mips ", 0, &setlist
);
6016 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6017 _("Various MIPS specific commands."),
6018 &showmipscmdlist
, "show mips ", 0, &showlist
);
6020 /* Allow the user to override the ABI. */
6021 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6022 &mips_abi_string
, _("\
6023 Set the MIPS ABI used by this program."), _("\
6024 Show the MIPS ABI used by this program."), _("\
6025 This option can be set to one of:\n\
6026 auto - the default ABI associated with the current binary\n\
6035 &setmipscmdlist
, &showmipscmdlist
);
6037 /* Let the user turn off floating point and set the fence post for
6038 heuristic_proc_start. */
6040 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6041 _("Set use of MIPS floating-point coprocessor."),
6042 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6043 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6044 _("Select single-precision MIPS floating-point coprocessor."),
6046 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6047 _("Select double-precision MIPS floating-point coprocessor."),
6049 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6050 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6051 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6052 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6053 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6054 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6055 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6056 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6057 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6058 _("Select MIPS floating-point coprocessor automatically."),
6060 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6061 _("Show current use of MIPS floating-point coprocessor target."),
6064 /* We really would like to have both "0" and "unlimited" work, but
6065 command.c doesn't deal with that. So make it a var_zinteger
6066 because the user can always use "999999" or some such for unlimited. */
6067 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6068 &heuristic_fence_post
, _("\
6069 Set the distance searched for the start of a function."), _("\
6070 Show the distance searched for the start of a function."), _("\
6071 If you are debugging a stripped executable, GDB needs to search through the\n\
6072 program for the start of a function. This command sets the distance of the\n\
6073 search. The only need to set it is when debugging a stripped executable."),
6074 reinit_frame_cache_sfunc
,
6075 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
6076 &setlist
, &showlist
);
6078 /* Allow the user to control whether the upper bits of 64-bit
6079 addresses should be zeroed. */
6080 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6081 &mask_address_var
, _("\
6082 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6083 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6084 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6085 allow GDB to determine the correct value."),
6086 NULL
, show_mask_address
,
6087 &setmipscmdlist
, &showmipscmdlist
);
6089 /* Allow the user to control the size of 32 bit registers within the
6090 raw remote packet. */
6091 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6092 &mips64_transfers_32bit_regs_p
, _("\
6093 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6095 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6097 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6098 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6099 64 bits for others. Use \"off\" to disable compatibility mode"),
6100 set_mips64_transfers_32bit_regs
,
6101 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6102 &setlist
, &showlist
);
6104 /* Debug this files internals. */
6105 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6107 Set mips debugging."), _("\
6108 Show mips debugging."), _("\
6109 When non-zero, mips specific debugging is enabled."),
6111 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
6112 &setdebuglist
, &showdebuglist
);