1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_string.h"
25 #include "gdb_assert.h"
37 #include "arch-utils.h"
40 #include "mips-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/mips.h"
47 #include "sim-regno.h"
49 #include "frame-unwind.h"
50 #include "frame-base.h"
51 #include "trad-frame.h"
53 #include "floatformat.h"
55 #include "target-descriptions.h"
56 #include "dwarf2-frame.h"
57 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *const mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 const struct register_alias mips_numeric_register_aliases
[] = {
146 #define R(n) { #n, n }
147 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
148 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
149 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
150 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
154 #ifndef MIPS_DEFAULT_FPU_TYPE
155 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
157 static int mips_fpu_type_auto
= 1;
158 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
160 static int mips_debug
= 0;
162 /* Properties (for struct target_desc) describing the g/G packet
164 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
165 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
167 struct target_desc
*mips_tdesc_gp32
;
168 struct target_desc
*mips_tdesc_gp64
;
170 const struct mips_regnum
*
171 mips_regnum (struct gdbarch
*gdbarch
)
173 return gdbarch_tdep (gdbarch
)->regnum
;
177 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
179 return mips_regnum (gdbarch
)->fp0
+ 12;
182 /* Return 1 if REGNUM refers to a floating-point general register, raw
183 or cooked. Otherwise return 0. */
186 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
188 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
190 return (rawnum
>= mips_regnum (gdbarch
)->fp0
191 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
194 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
196 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
198 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
199 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
201 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
202 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
204 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
206 /* Return the MIPS ABI associated with GDBARCH. */
208 mips_abi (struct gdbarch
*gdbarch
)
210 return gdbarch_tdep (gdbarch
)->mips_abi
;
214 mips_isa_regsize (struct gdbarch
*gdbarch
)
216 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
218 /* If we know how big the registers are, use that size. */
219 if (tdep
->register_size_valid_p
)
220 return tdep
->register_size
;
222 /* Fall back to the previous behavior. */
223 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
224 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
227 /* Return the currently configured (or set) saved register size. */
230 mips_abi_regsize (struct gdbarch
*gdbarch
)
232 switch (mips_abi (gdbarch
))
234 case MIPS_ABI_EABI32
:
240 case MIPS_ABI_EABI64
:
242 case MIPS_ABI_UNKNOWN
:
245 internal_error (__FILE__
, __LINE__
, _("bad switch"));
249 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
250 functions to test, set, or clear bit 0 of addresses. */
253 is_mips16_addr (CORE_ADDR addr
)
259 unmake_mips16_addr (CORE_ADDR addr
)
261 return ((addr
) & ~(CORE_ADDR
) 1);
265 make_mips16_addr (CORE_ADDR addr
)
267 return ((addr
) | (CORE_ADDR
) 1);
270 /* Functions for setting and testing a bit in a minimal symbol that
271 marks it as 16-bit function. The MSB of the minimal symbol's
272 "info" field is used for this purpose.
274 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
275 i.e. refers to a 16-bit function, and sets a "special" bit in a
276 minimal symbol to mark it as a 16-bit function
278 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
281 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
283 if (ELF_ST_IS_MIPS16 (((elf_symbol_type
*)
284 (sym
))->internal_elf_sym
.st_other
))
286 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
291 msymbol_is_special (struct minimal_symbol
*msym
)
293 return MSYMBOL_TARGET_FLAG_1 (msym
);
296 /* XFER a value from the big/little/left end of the register.
297 Depending on the size of the value it might occupy the entire
298 register or just part of it. Make an allowance for this, aligning
299 things accordingly. */
302 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
303 int reg_num
, int length
,
304 enum bfd_endian endian
, gdb_byte
*in
,
305 const gdb_byte
*out
, int buf_offset
)
309 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
310 /* Need to transfer the left or right part of the register, based on
311 the targets byte order. */
315 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
317 case BFD_ENDIAN_LITTLE
:
320 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
324 internal_error (__FILE__
, __LINE__
, _("bad switch"));
327 fprintf_unfiltered (gdb_stderr
,
328 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
329 reg_num
, reg_offset
, buf_offset
, length
);
330 if (mips_debug
&& out
!= NULL
)
333 fprintf_unfiltered (gdb_stdlog
, "out ");
334 for (i
= 0; i
< length
; i
++)
335 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
338 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
341 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
343 if (mips_debug
&& in
!= NULL
)
346 fprintf_unfiltered (gdb_stdlog
, "in ");
347 for (i
= 0; i
< length
; i
++)
348 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
351 fprintf_unfiltered (gdb_stdlog
, "\n");
354 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
355 compatiblity mode. A return value of 1 means that we have
356 physical 64-bit registers, but should treat them as 32-bit registers. */
359 mips2_fp_compat (struct frame_info
*frame
)
361 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
362 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
364 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
368 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
369 in all the places we deal with FP registers. PR gdb/413. */
370 /* Otherwise check the FR bit in the status register - it controls
371 the FP compatiblity mode. If it is clear we are in compatibility
373 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
380 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
382 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
384 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
386 /* The list of available "set mips " and "show mips " commands. */
388 static struct cmd_list_element
*setmipscmdlist
= NULL
;
389 static struct cmd_list_element
*showmipscmdlist
= NULL
;
391 /* Integer registers 0 thru 31 are handled explicitly by
392 mips_register_name(). Processor specific registers 32 and above
393 are listed in the following tables. */
396 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
400 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
401 "sr", "lo", "hi", "bad", "cause", "pc",
402 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
403 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
404 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
405 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
409 /* Names of IDT R3041 registers. */
411 static const char *mips_r3041_reg_names
[] = {
412 "sr", "lo", "hi", "bad", "cause", "pc",
413 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
414 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
415 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
416 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
417 "fsr", "fir", "", /*"fp" */ "",
418 "", "", "bus", "ccfg", "", "", "", "",
419 "", "", "port", "cmp", "", "", "epc", "prid",
422 /* Names of tx39 registers. */
424 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
425 "sr", "lo", "hi", "bad", "cause", "pc",
426 "", "", "", "", "", "", "", "",
427 "", "", "", "", "", "", "", "",
428 "", "", "", "", "", "", "", "",
429 "", "", "", "", "", "", "", "",
431 "", "", "", "", "", "", "", "",
432 "", "", "config", "cache", "debug", "depc", "epc",
435 /* Names of IRIX registers. */
436 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
437 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
438 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
439 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
440 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
441 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
444 /* Names of registers with Linux kernels. */
445 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
446 "sr", "lo", "hi", "bad", "cause", "pc",
447 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
448 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
449 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
450 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
455 /* Return the name of the register corresponding to REGNO. */
457 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
459 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
460 /* GPR names for all ABIs other than n32/n64. */
461 static char *mips_gpr_names
[] = {
462 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
463 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
464 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
465 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
468 /* GPR names for n32 and n64 ABIs. */
469 static char *mips_n32_n64_gpr_names
[] = {
470 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
471 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
472 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
473 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
476 enum mips_abi abi
= mips_abi (gdbarch
);
478 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
479 but then don't make the raw register names visible. This (upper)
480 range of user visible register numbers are the pseudo-registers.
482 This approach was adopted accommodate the following scenario:
483 It is possible to debug a 64-bit device using a 32-bit
484 programming model. In such instances, the raw registers are
485 configured to be 64-bits wide, while the pseudo registers are
486 configured to be 32-bits wide. The registers that the user
487 sees - the pseudo registers - match the users expectations
488 given the programming model being used. */
489 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
490 if (regno
< gdbarch_num_regs (gdbarch
))
493 /* The MIPS integer registers are always mapped from 0 to 31. The
494 names of the registers (which reflects the conventions regarding
495 register use) vary depending on the ABI. */
496 if (0 <= rawnum
&& rawnum
< 32)
498 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
499 return mips_n32_n64_gpr_names
[rawnum
];
501 return mips_gpr_names
[rawnum
];
503 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
504 return tdesc_register_name (gdbarch
, rawnum
);
505 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
507 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
508 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
509 return tdep
->mips_processor_reg_names
[rawnum
- 32];
513 internal_error (__FILE__
, __LINE__
,
514 _("mips_register_name: bad register number %d"), rawnum
);
517 /* Return the groups that a MIPS register can be categorised into. */
520 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
521 struct reggroup
*reggroup
)
526 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
527 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
528 if (reggroup
== all_reggroup
)
530 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
531 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
532 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
533 (gdbarch), as not all architectures are multi-arch. */
534 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
535 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
536 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
538 if (reggroup
== float_reggroup
)
539 return float_p
&& pseudo
;
540 if (reggroup
== vector_reggroup
)
541 return vector_p
&& pseudo
;
542 if (reggroup
== general_reggroup
)
543 return (!vector_p
&& !float_p
) && pseudo
;
544 /* Save the pseudo registers. Need to make certain that any code
545 extracting register values from a saved register cache also uses
547 if (reggroup
== save_reggroup
)
548 return raw_p
&& pseudo
;
549 /* Restore the same pseudo register. */
550 if (reggroup
== restore_reggroup
)
551 return raw_p
&& pseudo
;
555 /* Return the groups that a MIPS register can be categorised into.
556 This version is only used if we have a target description which
557 describes real registers (and their groups). */
560 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
561 struct reggroup
*reggroup
)
563 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
564 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
567 /* Only save, restore, and display the pseudo registers. Need to
568 make certain that any code extracting register values from a
569 saved register cache also uses pseudo registers.
571 Note: saving and restoring the pseudo registers is slightly
572 strange; if we have 64 bits, we should save and restore all
573 64 bits. But this is hard and has little benefit. */
577 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
581 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
584 /* Map the symbol table registers which live in the range [1 *
585 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
586 registers. Take care of alignment and size problems. */
588 static enum register_status
589 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
590 int cookednum
, gdb_byte
*buf
)
592 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
593 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
594 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
595 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
596 return regcache_raw_read (regcache
, rawnum
, buf
);
597 else if (register_size (gdbarch
, rawnum
) >
598 register_size (gdbarch
, cookednum
))
600 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
601 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
604 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
606 enum register_status status
;
608 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
609 if (status
== REG_VALID
)
610 store_signed_integer (buf
, 4, byte_order
, regval
);
615 internal_error (__FILE__
, __LINE__
, _("bad register size"));
619 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
620 struct regcache
*regcache
, int cookednum
,
623 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
624 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
625 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
626 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
627 regcache_raw_write (regcache
, rawnum
, buf
);
628 else if (register_size (gdbarch
, rawnum
) >
629 register_size (gdbarch
, cookednum
))
631 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
632 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
635 /* Sign extend the shortened version of the register prior
636 to placing it in the raw register. This is required for
637 some mips64 parts in order to avoid unpredictable behavior. */
638 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
639 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
640 regcache_raw_write_signed (regcache
, rawnum
, regval
);
644 internal_error (__FILE__
, __LINE__
, _("bad register size"));
648 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
649 struct agent_expr
*ax
, int reg
)
651 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
652 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
653 && reg
< 2 * gdbarch_num_regs (gdbarch
));
655 ax_reg_mask (ax
, rawnum
);
661 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
662 struct agent_expr
*ax
, int reg
)
664 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
665 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
666 && reg
< 2 * gdbarch_num_regs (gdbarch
));
667 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
671 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
673 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
674 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
677 ax_simple (ax
, aop_lsh
);
680 ax_simple (ax
, aop_rsh_signed
);
684 internal_error (__FILE__
, __LINE__
, _("bad register size"));
689 /* Table to translate MIPS16 register field to actual register number. */
690 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
692 /* Heuristic_proc_start may hunt through the text section for a long
693 time across a 2400 baud serial line. Allows the user to limit this
696 static unsigned int heuristic_fence_post
= 0;
698 /* Number of bytes of storage in the actual machine representation for
699 register N. NOTE: This defines the pseudo register type so need to
700 rebuild the architecture vector. */
702 static int mips64_transfers_32bit_regs_p
= 0;
705 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
706 struct cmd_list_element
*c
)
708 struct gdbarch_info info
;
709 gdbarch_info_init (&info
);
710 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
711 instead of relying on globals. Doing that would let generic code
712 handle the search for this specific architecture. */
713 if (!gdbarch_update_p (info
))
715 mips64_transfers_32bit_regs_p
= 0;
716 error (_("32-bit compatibility mode not supported"));
720 /* Convert to/from a register and the corresponding memory value. */
722 /* This predicate tests for the case of an 8 byte floating point
723 value that is being transferred to or from a pair of floating point
724 registers each of which are (or are considered to be) only 4 bytes
727 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
730 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
731 && register_size (gdbarch
, regnum
) == 4
732 && mips_float_register_p (gdbarch
, regnum
)
733 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
736 /* This predicate tests for the case of a value of less than 8
737 bytes in width that is being transfered to or from an 8 byte
738 general purpose register. */
740 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
743 int num_regs
= gdbarch_num_regs (gdbarch
);
745 return (register_size (gdbarch
, regnum
) == 8
746 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
747 && TYPE_LENGTH (type
) < 8);
751 mips_convert_register_p (struct gdbarch
*gdbarch
,
752 int regnum
, struct type
*type
)
754 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
755 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
759 mips_register_to_value (struct frame_info
*frame
, int regnum
,
760 struct type
*type
, gdb_byte
*to
,
761 int *optimizedp
, int *unavailablep
)
763 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
765 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
767 get_frame_register (frame
, regnum
+ 0, to
+ 4);
768 get_frame_register (frame
, regnum
+ 1, to
+ 0);
770 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
771 optimizedp
, unavailablep
))
774 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
775 optimizedp
, unavailablep
))
777 *optimizedp
= *unavailablep
= 0;
780 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
782 int len
= TYPE_LENGTH (type
);
785 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
786 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
787 optimizedp
, unavailablep
))
790 *optimizedp
= *unavailablep
= 0;
795 internal_error (__FILE__
, __LINE__
,
796 _("mips_register_to_value: unrecognized case"));
801 mips_value_to_register (struct frame_info
*frame
, int regnum
,
802 struct type
*type
, const gdb_byte
*from
)
804 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
806 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
808 put_frame_register (frame
, regnum
+ 0, from
+ 4);
809 put_frame_register (frame
, regnum
+ 1, from
+ 0);
811 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
814 int len
= TYPE_LENGTH (type
);
816 /* Sign extend values, irrespective of type, that are stored to
817 a 64-bit general purpose register. (32-bit unsigned values
818 are stored as signed quantities within a 64-bit register.
819 When performing an operation, in compiled code, that combines
820 a 32-bit unsigned value with a signed 64-bit value, a type
821 conversion is first performed that zeroes out the high 32 bits.) */
822 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
825 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
827 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
828 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
829 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
833 if (from
[len
-1] & 0x80)
834 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
836 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
837 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
838 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
843 internal_error (__FILE__
, __LINE__
,
844 _("mips_value_to_register: unrecognized case"));
848 /* Return the GDB type object for the "standard" data type of data in
852 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
854 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
855 if (mips_float_register_p (gdbarch
, regnum
))
857 /* The floating-point registers raw, or cooked, always match
858 mips_isa_regsize(), and also map 1:1, byte for byte. */
859 if (mips_isa_regsize (gdbarch
) == 4)
860 return builtin_type (gdbarch
)->builtin_float
;
862 return builtin_type (gdbarch
)->builtin_double
;
864 else if (regnum
< gdbarch_num_regs (gdbarch
))
866 /* The raw or ISA registers. These are all sized according to
868 if (mips_isa_regsize (gdbarch
) == 4)
869 return builtin_type (gdbarch
)->builtin_int32
;
871 return builtin_type (gdbarch
)->builtin_int64
;
875 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
877 /* The cooked or ABI registers. These are sized according to
878 the ABI (with a few complications). */
879 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
880 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
881 return builtin_type (gdbarch
)->builtin_int32
;
882 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
883 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
884 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
885 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
886 /* The pseudo/cooked view of the embedded registers is always
887 32-bit. The raw view is handled below. */
888 return builtin_type (gdbarch
)->builtin_int32
;
889 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
890 /* The target, while possibly using a 64-bit register buffer,
891 is only transfering 32-bits of each integer register.
892 Reflect this in the cooked/pseudo (ABI) register value. */
893 return builtin_type (gdbarch
)->builtin_int32
;
894 else if (mips_abi_regsize (gdbarch
) == 4)
895 /* The ABI is restricted to 32-bit registers (the ISA could be
897 return builtin_type (gdbarch
)->builtin_int32
;
900 return builtin_type (gdbarch
)->builtin_int64
;
904 /* Return the GDB type for the pseudo register REGNUM, which is the
905 ABI-level view. This function is only called if there is a target
906 description which includes registers, so we know precisely the
907 types of hardware registers. */
910 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
912 const int num_regs
= gdbarch_num_regs (gdbarch
);
913 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
914 int rawnum
= regnum
% num_regs
;
915 struct type
*rawtype
;
917 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
919 /* Absent registers are still absent. */
920 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
921 if (TYPE_LENGTH (rawtype
) == 0)
924 if (rawnum
>= mips_regnum (gdbarch
)->fp0
925 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32)
926 /* Present the floating point registers however the hardware did;
927 do not try to convert between FPU layouts. */
930 /* Use pointer types for registers if we can. For n32 we can not,
931 since we do not have a 64-bit pointer type. */
932 if (mips_abi_regsize (gdbarch
)
933 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
935 if (rawnum
== MIPS_SP_REGNUM
936 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
937 return builtin_type (gdbarch
)->builtin_data_ptr
;
938 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
939 return builtin_type (gdbarch
)->builtin_func_ptr
;
942 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
943 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
944 || rawnum
== mips_regnum (gdbarch
)->lo
945 || rawnum
== mips_regnum (gdbarch
)->hi
946 || rawnum
== mips_regnum (gdbarch
)->badvaddr
947 || rawnum
== mips_regnum (gdbarch
)->cause
948 || rawnum
== mips_regnum (gdbarch
)->pc
949 || (mips_regnum (gdbarch
)->dspacc
!= -1
950 && rawnum
>= mips_regnum (gdbarch
)->dspacc
951 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
952 return builtin_type (gdbarch
)->builtin_int32
;
954 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
955 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
956 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
957 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
959 /* The pseudo/cooked view of embedded registers is always
960 32-bit, even if the target transfers 64-bit values for them.
961 New targets relying on XML descriptions should only transfer
962 the necessary 32 bits, but older versions of GDB expected 64,
963 so allow the target to provide 64 bits without interfering
964 with the displayed type. */
965 return builtin_type (gdbarch
)->builtin_int32
;
968 /* For all other registers, pass through the hardware type. */
972 /* Should the upper word of 64-bit addresses be zeroed? */
973 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
976 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
978 switch (mask_address_var
)
980 case AUTO_BOOLEAN_TRUE
:
982 case AUTO_BOOLEAN_FALSE
:
985 case AUTO_BOOLEAN_AUTO
:
986 return tdep
->default_mask_address_p
;
988 internal_error (__FILE__
, __LINE__
,
989 _("mips_mask_address_p: bad switch"));
995 show_mask_address (struct ui_file
*file
, int from_tty
,
996 struct cmd_list_element
*c
, const char *value
)
998 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
1000 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1001 switch (mask_address_var
)
1003 case AUTO_BOOLEAN_TRUE
:
1004 printf_filtered ("The 32 bit mips address mask is enabled\n");
1006 case AUTO_BOOLEAN_FALSE
:
1007 printf_filtered ("The 32 bit mips address mask is disabled\n");
1009 case AUTO_BOOLEAN_AUTO
:
1011 ("The 32 bit address mask is set automatically. Currently %s\n",
1012 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1015 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1020 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1023 mips_pc_is_mips16 (CORE_ADDR memaddr
)
1025 struct minimal_symbol
*sym
;
1027 /* A flag indicating that this is a MIPS16 function is stored by
1028 elfread.c in the high bit of the info field. Use this to decide
1029 if the function is MIPS16 or normal MIPS. Otherwise if bit 0 of
1030 the address is set, assume this is a MIPS16 address. */
1031 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1033 return msymbol_is_special (sym
);
1035 return is_mips16_addr (memaddr
);
1038 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1040 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1041 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1042 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1043 static const char mips_str_call_stub
[] = "__call_stub_";
1044 static const char mips_str_fn_stub
[] = "__fn_stub_";
1046 /* This is used as a PIC thunk prefix. */
1048 static const char mips_str_pic
[] = ".pic.";
1050 /* Return non-zero if the PC is inside a call thunk (aka stub or
1051 trampoline) that should be treated as a temporary frame. */
1054 mips_in_frame_stub (CORE_ADDR pc
)
1056 CORE_ADDR start_addr
;
1059 /* Find the starting address of the function containing the PC. */
1060 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1063 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1064 if (strncmp (name
, mips_str_mips16_call_stub
,
1065 strlen (mips_str_mips16_call_stub
)) == 0)
1067 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1068 if (strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
1070 /* If the PC is in __fn_stub_*, this is a call stub. */
1071 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0)
1074 return 0; /* Not a stub. */
1077 /* MIPS believes that the PC has a sign extended value. Perhaps the
1078 all registers should be sign extended for simplicity? */
1081 mips_read_pc (struct regcache
*regcache
)
1084 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1085 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1086 if (is_mips16_addr (pc
))
1087 pc
= unmake_mips16_addr (pc
);
1092 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1096 pc
= frame_unwind_register_signed
1097 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
1098 if (is_mips16_addr (pc
))
1099 pc
= unmake_mips16_addr (pc
);
1100 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1101 intermediate frames. In this case we can get the caller's address
1102 from $ra, or if $ra contains an address within a thunk as well, then
1103 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1104 and thus the caller's address is in $s2. */
1105 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1107 pc
= frame_unwind_register_signed
1108 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1109 if (is_mips16_addr (pc
))
1110 pc
= unmake_mips16_addr (pc
);
1111 if (mips_in_frame_stub (pc
))
1113 pc
= frame_unwind_register_signed
1114 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1115 if (is_mips16_addr (pc
))
1116 pc
= unmake_mips16_addr (pc
);
1123 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1125 return frame_unwind_register_signed
1126 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1129 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1130 dummy frame. The frame ID's base needs to match the TOS value
1131 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1134 static struct frame_id
1135 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1137 return frame_id_build
1138 (get_frame_register_signed (this_frame
,
1139 gdbarch_num_regs (gdbarch
)
1141 get_frame_pc (this_frame
));
1145 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1147 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1148 if (mips_pc_is_mips16 (pc
))
1149 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
1151 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1154 /* Fetch and return instruction from the specified location. If the PC
1155 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1158 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1160 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1161 gdb_byte buf
[MIPS_INSN32_SIZE
];
1165 if (mips_pc_is_mips16 (addr
))
1167 instlen
= MIPS_INSN16_SIZE
;
1168 addr
= unmake_mips16_addr (addr
);
1171 instlen
= MIPS_INSN32_SIZE
;
1172 status
= target_read_memory (addr
, buf
, instlen
);
1174 memory_error (status
, addr
);
1175 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1178 /* These are the fields of 32 bit mips instructions. */
1179 #define mips32_op(x) (x >> 26)
1180 #define itype_op(x) (x >> 26)
1181 #define itype_rs(x) ((x >> 21) & 0x1f)
1182 #define itype_rt(x) ((x >> 16) & 0x1f)
1183 #define itype_immediate(x) (x & 0xffff)
1185 #define jtype_op(x) (x >> 26)
1186 #define jtype_target(x) (x & 0x03ffffff)
1188 #define rtype_op(x) (x >> 26)
1189 #define rtype_rs(x) ((x >> 21) & 0x1f)
1190 #define rtype_rt(x) ((x >> 16) & 0x1f)
1191 #define rtype_rd(x) ((x >> 11) & 0x1f)
1192 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1193 #define rtype_funct(x) (x & 0x3f)
1196 mips32_relative_offset (ULONGEST inst
)
1198 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1201 /* Determine the address of the next instruction executed after the INST
1202 floating condition branch instruction at PC. COUNT specifies the
1203 number of the floating condition bits tested by the branch. */
1206 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1207 ULONGEST inst
, CORE_ADDR pc
, int count
)
1209 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1210 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1211 int tf
= itype_rt (inst
) & 1;
1212 int mask
= (1 << count
) - 1;
1217 /* No way to handle; it'll most likely trap anyway. */
1220 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1221 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1223 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1224 pc
+= mips32_relative_offset (inst
);
1231 /* Determine where to set a single step breakpoint while considering
1232 branch prediction. */
1234 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1236 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1239 inst
= mips_fetch_instruction (gdbarch
, pc
);
1240 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1243 if (itype_op (inst
) >> 2 == 5)
1244 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1246 op
= (itype_op (inst
) & 0x03);
1256 goto greater_branch
;
1261 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1262 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1263 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1264 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 9
1265 && (itype_rt (inst
) & 2) == 0)
1266 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1267 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1268 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 10
1269 && (itype_rt (inst
) & 2) == 0)
1270 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1271 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1272 else if (itype_op (inst
) == 29)
1274 /* The new PC will be alternate mode. */
1278 reg
= jtype_target (inst
) << 2;
1279 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1280 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1283 pc
+= 4; /* Not a branch, next instruction is easy. */
1286 { /* This gets way messy. */
1288 /* Further subdivide into SPECIAL, REGIMM and other. */
1289 switch (op
= itype_op (inst
) & 0x07) /* Extract bits 28,27,26. */
1291 case 0: /* SPECIAL */
1292 op
= rtype_funct (inst
);
1297 /* Set PC to that address. */
1298 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1300 case 12: /* SYSCALL */
1302 struct gdbarch_tdep
*tdep
;
1304 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1305 if (tdep
->syscall_next_pc
!= NULL
)
1306 pc
= tdep
->syscall_next_pc (frame
);
1315 break; /* end SPECIAL */
1316 case 1: /* REGIMM */
1318 op
= itype_rt (inst
); /* branch condition */
1323 case 16: /* BLTZAL */
1324 case 18: /* BLTZALL */
1326 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1327 pc
+= mips32_relative_offset (inst
) + 4;
1329 pc
+= 8; /* after the delay slot */
1333 case 17: /* BGEZAL */
1334 case 19: /* BGEZALL */
1335 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1336 pc
+= mips32_relative_offset (inst
) + 4;
1338 pc
+= 8; /* after the delay slot */
1340 case 0x1c: /* BPOSGE32 */
1341 case 0x1e: /* BPOSGE64 */
1343 if (itype_rs (inst
) == 0)
1345 unsigned int pos
= (op
& 2) ? 64 : 32;
1346 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1349 /* No way to handle; it'll most likely trap anyway. */
1352 if ((get_frame_register_unsigned (frame
,
1353 dspctl
) & 0x7f) >= pos
)
1354 pc
+= mips32_relative_offset (inst
);
1359 /* All of the other instructions in the REGIMM category */
1364 break; /* end REGIMM */
1369 reg
= jtype_target (inst
) << 2;
1370 /* Upper four bits get never changed... */
1371 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1374 case 4: /* BEQ, BEQL */
1376 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1377 get_frame_register_signed (frame
, itype_rt (inst
)))
1378 pc
+= mips32_relative_offset (inst
) + 4;
1382 case 5: /* BNE, BNEL */
1384 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1385 get_frame_register_signed (frame
, itype_rt (inst
)))
1386 pc
+= mips32_relative_offset (inst
) + 4;
1390 case 6: /* BLEZ, BLEZL */
1391 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1392 pc
+= mips32_relative_offset (inst
) + 4;
1398 greater_branch
: /* BGTZ, BGTZL */
1399 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1400 pc
+= mips32_relative_offset (inst
) + 4;
1407 } /* mips32_next_pc */
1409 /* Decoding the next place to set a breakpoint is irregular for the
1410 mips 16 variant, but fortunately, there fewer instructions. We have
1411 to cope ith extensions for 16 bit instructions and a pair of actual
1412 32 bit instructions. We dont want to set a single step instruction
1413 on the extend instruction either. */
1415 /* Lots of mips16 instruction formats */
1416 /* Predicting jumps requires itype,ritype,i8type
1417 and their extensions extItype,extritype,extI8type. */
1418 enum mips16_inst_fmts
1420 itype
, /* 0 immediate 5,10 */
1421 ritype
, /* 1 5,3,8 */
1422 rrtype
, /* 2 5,3,3,5 */
1423 rritype
, /* 3 5,3,3,5 */
1424 rrrtype
, /* 4 5,3,3,3,2 */
1425 rriatype
, /* 5 5,3,3,1,4 */
1426 shifttype
, /* 6 5,3,3,3,2 */
1427 i8type
, /* 7 5,3,8 */
1428 i8movtype
, /* 8 5,3,3,5 */
1429 i8mov32rtype
, /* 9 5,3,5,3 */
1430 i64type
, /* 10 5,3,8 */
1431 ri64type
, /* 11 5,3,3,5 */
1432 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1433 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1434 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1435 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1436 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1437 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1438 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1439 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1440 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1441 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1443 /* I am heaping all the fields of the formats into one structure and
1444 then, only the fields which are involved in instruction extension. */
1448 unsigned int regx
; /* Function in i8 type. */
1453 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1454 for the bits which make up the immediate extension. */
1457 extended_offset (unsigned int extension
)
1461 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
1463 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
1465 value
|= extension
& 0x1f; /* Extract 4:0. */
1470 /* Only call this function if you know that this is an extendable
1471 instruction. It won't malfunction, but why make excess remote memory
1472 references? If the immediate operands get sign extended or something,
1473 do it after the extension is performed. */
1474 /* FIXME: Every one of these cases needs to worry about sign extension
1475 when the offset is to be used in relative addressing. */
1478 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1480 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1482 pc
&= 0xfffffffe; /* Clear the low order bit. */
1483 target_read_memory (pc
, buf
, 2);
1484 return extract_unsigned_integer (buf
, 2, byte_order
);
1488 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1489 unsigned int extension
,
1491 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1496 switch (insn_format
)
1503 value
= extended_offset ((extension
<< 16) | inst
);
1504 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1508 value
= inst
& 0x7ff;
1509 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
1518 { /* A register identifier and an offset. */
1519 /* Most of the fields are the same as I type but the
1520 immediate value is of a different length. */
1524 value
= extended_offset ((extension
<< 16) | inst
);
1525 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1529 value
= inst
& 0xff; /* 8 bits */
1530 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
1533 regx
= (inst
>> 8) & 0x07; /* i8 funct */
1539 unsigned long value
;
1540 unsigned int nexthalf
;
1541 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1542 value
= value
<< 16;
1543 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit
1552 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1554 upk
->offset
= offset
;
1561 add_offset_16 (CORE_ADDR pc
, int offset
)
1563 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1567 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1568 unsigned int extension
, unsigned int insn
)
1570 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1571 int op
= (insn
>> 11);
1574 case 2: /* Branch */
1577 struct upk_mips16 upk
;
1578 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1579 pc
+= (upk
.offset
<< 1) + 2;
1582 case 3: /* JAL , JALX - Watch out, these are 32 bit
1585 struct upk_mips16 upk
;
1586 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1587 pc
= add_offset_16 (pc
, upk
.offset
);
1588 if ((insn
>> 10) & 0x01) /* Exchange mode */
1589 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
1596 struct upk_mips16 upk
;
1598 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1599 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1601 pc
+= (upk
.offset
<< 1) + 2;
1608 struct upk_mips16 upk
;
1610 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1611 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1613 pc
+= (upk
.offset
<< 1) + 2;
1618 case 12: /* I8 Formats btez btnez */
1620 struct upk_mips16 upk
;
1622 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1623 /* upk.regx contains the opcode */
1624 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1625 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1626 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1627 /* pc = add_offset_16(pc,upk.offset) ; */
1628 pc
+= (upk
.offset
<< 1) + 2;
1633 case 29: /* RR Formats JR, JALR, JALR-RA */
1635 struct upk_mips16 upk
;
1636 /* upk.fmt = rrtype; */
1641 upk
.regx
= (insn
>> 8) & 0x07;
1642 upk
.regy
= (insn
>> 5) & 0x07;
1643 if ((upk
.regy
& 1) == 0)
1644 reg
= mips16_to_32_reg
[upk
.regx
];
1646 reg
= 31; /* Function return instruction. */
1647 pc
= get_frame_register_signed (frame
, reg
);
1654 /* This is an instruction extension. Fetch the real instruction
1655 (which follows the extension) and decode things based on
1659 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1660 fetch_mips_16 (gdbarch
, pc
));
1673 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1675 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1676 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1677 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1680 /* The mips_next_pc function supports single_step when the remote
1681 target monitor or stub is not developed enough to do a single_step.
1682 It works by decoding the current instruction and predicting where a
1683 branch will go. This isnt hard because all the data is available.
1684 The MIPS32 and MIPS16 variants are quite different. */
1686 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1688 if (mips_pc_is_mips16 (pc
))
1689 return mips16_next_pc (frame
, pc
);
1691 return mips32_next_pc (frame
, pc
);
1694 struct mips_frame_cache
1697 struct trad_frame_saved_reg
*saved_regs
;
1700 /* Set a register's saved stack address in temp_saved_regs. If an
1701 address has already been set for this register, do nothing; this
1702 way we will only recognize the first save of a given register in a
1705 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1706 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1707 Strictly speaking, only the second range is used as it is only second
1708 range (the ABI instead of ISA registers) that comes into play when finding
1709 saved registers in a frame. */
1712 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1713 int regnum
, CORE_ADDR offset
)
1715 if (this_cache
!= NULL
1716 && this_cache
->saved_regs
[regnum
].addr
== -1)
1718 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1720 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1726 /* Fetch the immediate value from a MIPS16 instruction.
1727 If the previous instruction was an EXTEND, use it to extend
1728 the upper bits of the immediate value. This is a helper function
1729 for mips16_scan_prologue. */
1732 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1733 unsigned short inst
, /* current instruction */
1734 int nbits
, /* number of bits in imm field */
1735 int scale
, /* scale factor to be applied to imm */
1736 int is_signed
) /* is the imm field signed? */
1740 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1742 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1743 if (offset
& 0x8000) /* check for negative extend */
1744 offset
= 0 - (0x10000 - (offset
& 0xffff));
1745 return offset
| (inst
& 0x1f);
1749 int max_imm
= 1 << nbits
;
1750 int mask
= max_imm
- 1;
1751 int sign_bit
= max_imm
>> 1;
1753 offset
= inst
& mask
;
1754 if (is_signed
&& (offset
& sign_bit
))
1755 offset
= 0 - (max_imm
- offset
);
1756 return offset
* scale
;
1761 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1762 the associated FRAME_CACHE if not null.
1763 Return the address of the first instruction past the prologue. */
1766 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1767 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1768 struct frame_info
*this_frame
,
1769 struct mips_frame_cache
*this_cache
)
1772 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
1774 long frame_offset
= 0; /* Size of stack frame. */
1775 long frame_adjust
= 0; /* Offset of FP from SP. */
1776 int frame_reg
= MIPS_SP_REGNUM
;
1777 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
1778 unsigned inst
= 0; /* current instruction */
1779 unsigned entry_inst
= 0; /* the entry instruction */
1780 unsigned save_inst
= 0; /* the save instruction */
1783 int extend_bytes
= 0;
1784 int prev_extend_bytes
;
1785 CORE_ADDR end_prologue_addr
= 0;
1787 /* Can be called when there's no process, and hence when there's no
1789 if (this_frame
!= NULL
)
1790 sp
= get_frame_register_signed (this_frame
,
1791 gdbarch_num_regs (gdbarch
)
1796 if (limit_pc
> start_pc
+ 200)
1797 limit_pc
= start_pc
+ 200;
1799 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1801 /* Save the previous instruction. If it's an EXTEND, we'll extract
1802 the immediate offset extension from it in mips16_get_imm. */
1805 /* Fetch and decode the instruction. */
1806 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1808 /* Normally we ignore extend instructions. However, if it is
1809 not followed by a valid prologue instruction, then this
1810 instruction is not part of the prologue either. We must
1811 remember in this case to adjust the end_prologue_addr back
1813 if ((inst
& 0xf800) == 0xf000) /* extend */
1815 extend_bytes
= MIPS_INSN16_SIZE
;
1819 prev_extend_bytes
= extend_bytes
;
1822 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1823 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1825 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1826 if (offset
< 0) /* Negative stack adjustment? */
1827 frame_offset
-= offset
;
1829 /* Exit loop if a positive stack adjustment is found, which
1830 usually means that the stack cleanup code in the function
1831 epilogue is reached. */
1834 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1836 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1837 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1838 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1840 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1842 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1843 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1844 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1846 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1848 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1849 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1851 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1853 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1854 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1856 else if (inst
== 0x673d) /* move $s1, $sp */
1861 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1863 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1864 frame_addr
= sp
+ offset
;
1866 frame_adjust
= offset
;
1868 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1870 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1871 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1872 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1874 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1876 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1877 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1878 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1880 else if ((inst
& 0xf81f) == 0xe809
1881 && (inst
& 0x700) != 0x700) /* entry */
1882 entry_inst
= inst
; /* Save for later processing. */
1883 else if ((inst
& 0xff80) == 0x6480) /* save */
1885 save_inst
= inst
; /* Save for later processing. */
1886 if (prev_extend_bytes
) /* extend */
1887 save_inst
|= prev_inst
<< 16;
1889 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1890 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1891 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1893 /* This instruction is part of the prologue, but we don't
1894 need to do anything special to handle it. */
1898 /* This instruction is not an instruction typically found
1899 in a prologue, so we must have reached the end of the
1901 if (end_prologue_addr
== 0)
1902 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1906 /* The entry instruction is typically the first instruction in a function,
1907 and it stores registers at offsets relative to the value of the old SP
1908 (before the prologue). But the value of the sp parameter to this
1909 function is the new SP (after the prologue has been executed). So we
1910 can't calculate those offsets until we've seen the entire prologue,
1911 and can calculate what the old SP must have been. */
1912 if (entry_inst
!= 0)
1914 int areg_count
= (entry_inst
>> 8) & 7;
1915 int sreg_count
= (entry_inst
>> 6) & 3;
1917 /* The entry instruction always subtracts 32 from the SP. */
1920 /* Now we can calculate what the SP must have been at the
1921 start of the function prologue. */
1924 /* Check if a0-a3 were saved in the caller's argument save area. */
1925 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1927 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1928 offset
+= mips_abi_regsize (gdbarch
);
1931 /* Check if the ra register was pushed on the stack. */
1933 if (entry_inst
& 0x20)
1935 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1936 offset
-= mips_abi_regsize (gdbarch
);
1939 /* Check if the s0 and s1 registers were pushed on the stack. */
1940 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1942 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1943 offset
-= mips_abi_regsize (gdbarch
);
1947 /* The SAVE instruction is similar to ENTRY, except that defined by the
1948 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1949 size of the frame is specified as an immediate field of instruction
1950 and an extended variation exists which lets additional registers and
1951 frame space to be specified. The instruction always treats registers
1952 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1953 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1955 static int args_table
[16] = {
1956 0, 0, 0, 0, 1, 1, 1, 1,
1957 2, 2, 2, 0, 3, 3, 4, -1,
1959 static int astatic_table
[16] = {
1960 0, 1, 2, 3, 0, 1, 2, 3,
1961 0, 1, 2, 4, 0, 1, 0, -1,
1963 int aregs
= (save_inst
>> 16) & 0xf;
1964 int xsregs
= (save_inst
>> 24) & 0x7;
1965 int args
= args_table
[aregs
];
1966 int astatic
= astatic_table
[aregs
];
1971 warning (_("Invalid number of argument registers encoded in SAVE."));
1976 warning (_("Invalid number of static registers encoded in SAVE."));
1980 /* For standard SAVE the frame size of 0 means 128. */
1981 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1982 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1985 frame_offset
+= frame_size
;
1987 /* Now we can calculate what the SP must have been at the
1988 start of the function prologue. */
1991 /* Check if A0-A3 were saved in the caller's argument save area. */
1992 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1994 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1995 offset
+= mips_abi_regsize (gdbarch
);
2000 /* Check if the RA register was pushed on the stack. */
2001 if (save_inst
& 0x40)
2003 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2004 offset
-= mips_abi_regsize (gdbarch
);
2007 /* Check if the S8 register was pushed on the stack. */
2010 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2011 offset
-= mips_abi_regsize (gdbarch
);
2014 /* Check if S2-S7 were pushed on the stack. */
2015 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2017 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2018 offset
-= mips_abi_regsize (gdbarch
);
2021 /* Check if the S1 register was pushed on the stack. */
2022 if (save_inst
& 0x10)
2024 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2025 offset
-= mips_abi_regsize (gdbarch
);
2027 /* Check if the S0 register was pushed on the stack. */
2028 if (save_inst
& 0x20)
2030 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2031 offset
-= mips_abi_regsize (gdbarch
);
2034 /* Check if A0-A3 were pushed on the stack. */
2035 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2037 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2038 offset
-= mips_abi_regsize (gdbarch
);
2042 if (this_cache
!= NULL
)
2045 (get_frame_register_signed (this_frame
,
2046 gdbarch_num_regs (gdbarch
) + frame_reg
)
2047 + frame_offset
- frame_adjust
);
2048 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2049 be able to get rid of the assignment below, evetually. But it's
2050 still needed for now. */
2051 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2052 + mips_regnum (gdbarch
)->pc
]
2053 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2056 /* If we didn't reach the end of the prologue when scanning the function
2057 instructions, then set end_prologue_addr to the address of the
2058 instruction immediately after the last one we scanned. */
2059 if (end_prologue_addr
== 0)
2060 end_prologue_addr
= cur_pc
;
2062 return end_prologue_addr
;
2065 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2066 Procedures that use the 32-bit instruction set are handled by the
2067 mips_insn32 unwinder. */
2069 static struct mips_frame_cache
*
2070 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2072 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2073 struct mips_frame_cache
*cache
;
2075 if ((*this_cache
) != NULL
)
2076 return (*this_cache
);
2077 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2078 (*this_cache
) = cache
;
2079 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2081 /* Analyze the function prologue. */
2083 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2084 CORE_ADDR start_addr
;
2086 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2087 if (start_addr
== 0)
2088 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2089 /* We can't analyze the prologue if we couldn't find the begining
2091 if (start_addr
== 0)
2094 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2097 /* gdbarch_sp_regnum contains the value and not the address. */
2098 trad_frame_set_value (cache
->saved_regs
,
2099 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2102 return (*this_cache
);
2106 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2107 struct frame_id
*this_id
)
2109 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2111 /* This marks the outermost frame. */
2112 if (info
->base
== 0)
2114 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2117 static struct value
*
2118 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2119 void **this_cache
, int regnum
)
2121 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2123 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2127 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2128 struct frame_info
*this_frame
, void **this_cache
)
2130 CORE_ADDR pc
= get_frame_pc (this_frame
);
2131 if (mips_pc_is_mips16 (pc
))
2136 static const struct frame_unwind mips_insn16_frame_unwind
=
2139 default_frame_unwind_stop_reason
,
2140 mips_insn16_frame_this_id
,
2141 mips_insn16_frame_prev_register
,
2143 mips_insn16_frame_sniffer
2147 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2150 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2155 static const struct frame_base mips_insn16_frame_base
=
2157 &mips_insn16_frame_unwind
,
2158 mips_insn16_frame_base_address
,
2159 mips_insn16_frame_base_address
,
2160 mips_insn16_frame_base_address
2163 static const struct frame_base
*
2164 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2166 CORE_ADDR pc
= get_frame_pc (this_frame
);
2167 if (mips_pc_is_mips16 (pc
))
2168 return &mips_insn16_frame_base
;
2173 /* Mark all the registers as unset in the saved_regs array
2174 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2177 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
2179 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2183 const int num_regs
= gdbarch_num_regs (gdbarch
);
2186 for (i
= 0; i
< num_regs
; i
++)
2188 this_cache
->saved_regs
[i
].addr
= -1;
2193 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2194 the associated FRAME_CACHE if not null.
2195 Return the address of the first instruction past the prologue. */
2198 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2199 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2200 struct frame_info
*this_frame
,
2201 struct mips_frame_cache
*this_cache
)
2204 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
2208 int frame_reg
= MIPS_SP_REGNUM
;
2210 CORE_ADDR end_prologue_addr
= 0;
2211 int seen_sp_adjust
= 0;
2212 int load_immediate_bytes
= 0;
2213 int in_delay_slot
= 0;
2214 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2216 /* Can be called when there's no process, and hence when there's no
2218 if (this_frame
!= NULL
)
2219 sp
= get_frame_register_signed (this_frame
,
2220 gdbarch_num_regs (gdbarch
)
2225 if (limit_pc
> start_pc
+ 200)
2226 limit_pc
= start_pc
+ 200;
2231 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2233 unsigned long inst
, high_word
, low_word
;
2236 /* Fetch the instruction. */
2237 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2239 /* Save some code by pre-extracting some useful fields. */
2240 high_word
= (inst
>> 16) & 0xffff;
2241 low_word
= inst
& 0xffff;
2242 reg
= high_word
& 0x1f;
2244 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2245 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2246 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2248 if (low_word
& 0x8000) /* Negative stack adjustment? */
2249 frame_offset
+= 0x10000 - low_word
;
2251 /* Exit loop if a positive stack adjustment is found, which
2252 usually means that the stack cleanup code in the function
2253 epilogue is reached. */
2257 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2258 && !regsize_is_64_bits
)
2260 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2262 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2263 && regsize_is_64_bits
)
2265 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2266 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2268 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2270 /* Old gcc frame, r30 is virtual frame pointer. */
2271 if ((long) low_word
!= frame_offset
)
2272 frame_addr
= sp
+ low_word
;
2273 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2275 unsigned alloca_adjust
;
2278 frame_addr
= get_frame_register_signed
2279 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2281 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2282 if (alloca_adjust
> 0)
2284 /* FP > SP + frame_size. This may be because of
2285 an alloca or somethings similar. Fix sp to
2286 "pre-alloca" value, and try again. */
2287 sp
+= alloca_adjust
;
2288 /* Need to reset the status of all registers. Otherwise,
2289 we will hit a guard that prevents the new address
2290 for each register to be recomputed during the second
2292 reset_saved_regs (gdbarch
, this_cache
);
2297 /* move $30,$sp. With different versions of gas this will be either
2298 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2299 Accept any one of these. */
2300 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2302 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2303 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2305 unsigned alloca_adjust
;
2308 frame_addr
= get_frame_register_signed
2309 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2311 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2312 if (alloca_adjust
> 0)
2314 /* FP > SP + frame_size. This may be because of
2315 an alloca or somethings similar. Fix sp to
2316 "pre-alloca" value, and try again. */
2318 /* Need to reset the status of all registers. Otherwise,
2319 we will hit a guard that prevents the new address
2320 for each register to be recomputed during the second
2322 reset_saved_regs (gdbarch
, this_cache
);
2327 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2328 && !regsize_is_64_bits
)
2330 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2332 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2333 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2334 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2335 || high_word
== 0x3c1c /* lui $gp,n */
2336 || high_word
== 0x279c /* addiu $gp,$gp,n */
2337 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2338 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2341 /* These instructions are part of the prologue, but we don't
2342 need to do anything special to handle them. */
2344 /* The instructions below load $at or $t0 with an immediate
2345 value in preparation for a stack adjustment via
2346 subu $sp,$sp,[$at,$t0]. These instructions could also
2347 initialize a local variable, so we accept them only before
2348 a stack adjustment instruction was seen. */
2349 else if (!seen_sp_adjust
2350 && (high_word
== 0x3c01 /* lui $at,n */
2351 || high_word
== 0x3c08 /* lui $t0,n */
2352 || high_word
== 0x3421 /* ori $at,$at,n */
2353 || high_word
== 0x3508 /* ori $t0,$t0,n */
2354 || high_word
== 0x3401 /* ori $at,$zero,n */
2355 || high_word
== 0x3408 /* ori $t0,$zero,n */
2358 if (end_prologue_addr
== 0)
2359 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2363 /* This instruction is not an instruction typically found
2364 in a prologue, so we must have reached the end of the
2366 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2367 loop now? Why would we need to continue scanning the function
2369 if (end_prologue_addr
== 0)
2370 end_prologue_addr
= cur_pc
;
2372 /* Check for branches and jumps. For now, only jump to
2373 register are caught (i.e. returns). */
2374 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2378 /* If the previous instruction was a jump, we must have reached
2379 the end of the prologue by now. Stop scanning so that we do
2380 not go past the function return. */
2385 if (this_cache
!= NULL
)
2388 (get_frame_register_signed (this_frame
,
2389 gdbarch_num_regs (gdbarch
) + frame_reg
)
2391 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2392 this assignment below, eventually. But it's still needed
2394 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2395 + mips_regnum (gdbarch
)->pc
]
2396 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2400 /* If we didn't reach the end of the prologue when scanning the function
2401 instructions, then set end_prologue_addr to the address of the
2402 instruction immediately after the last one we scanned. */
2403 /* brobecker/2004-10-10: I don't think this would ever happen, but
2404 we may as well be careful and do our best if we have a null
2405 end_prologue_addr. */
2406 if (end_prologue_addr
== 0)
2407 end_prologue_addr
= cur_pc
;
2409 /* In a frameless function, we might have incorrectly
2410 skipped some load immediate instructions. Undo the skipping
2411 if the load immediate was not followed by a stack adjustment. */
2412 if (load_immediate_bytes
&& !seen_sp_adjust
)
2413 end_prologue_addr
-= load_immediate_bytes
;
2415 return end_prologue_addr
;
2418 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2419 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2420 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2423 static struct mips_frame_cache
*
2424 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2426 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2427 struct mips_frame_cache
*cache
;
2429 if ((*this_cache
) != NULL
)
2430 return (*this_cache
);
2432 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2433 (*this_cache
) = cache
;
2434 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2436 /* Analyze the function prologue. */
2438 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2439 CORE_ADDR start_addr
;
2441 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2442 if (start_addr
== 0)
2443 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2444 /* We can't analyze the prologue if we couldn't find the begining
2446 if (start_addr
== 0)
2449 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2452 /* gdbarch_sp_regnum contains the value and not the address. */
2453 trad_frame_set_value (cache
->saved_regs
,
2454 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2457 return (*this_cache
);
2461 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2462 struct frame_id
*this_id
)
2464 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2466 /* This marks the outermost frame. */
2467 if (info
->base
== 0)
2469 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2472 static struct value
*
2473 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2474 void **this_cache
, int regnum
)
2476 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2478 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2482 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2483 struct frame_info
*this_frame
, void **this_cache
)
2485 CORE_ADDR pc
= get_frame_pc (this_frame
);
2486 if (! mips_pc_is_mips16 (pc
))
2491 static const struct frame_unwind mips_insn32_frame_unwind
=
2494 default_frame_unwind_stop_reason
,
2495 mips_insn32_frame_this_id
,
2496 mips_insn32_frame_prev_register
,
2498 mips_insn32_frame_sniffer
2502 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2505 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2510 static const struct frame_base mips_insn32_frame_base
=
2512 &mips_insn32_frame_unwind
,
2513 mips_insn32_frame_base_address
,
2514 mips_insn32_frame_base_address
,
2515 mips_insn32_frame_base_address
2518 static const struct frame_base
*
2519 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2521 CORE_ADDR pc
= get_frame_pc (this_frame
);
2522 if (! mips_pc_is_mips16 (pc
))
2523 return &mips_insn32_frame_base
;
2528 static struct trad_frame_cache
*
2529 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2532 CORE_ADDR start_addr
;
2533 CORE_ADDR stack_addr
;
2534 struct trad_frame_cache
*this_trad_cache
;
2535 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2536 int num_regs
= gdbarch_num_regs (gdbarch
);
2538 if ((*this_cache
) != NULL
)
2539 return (*this_cache
);
2540 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2541 (*this_cache
) = this_trad_cache
;
2543 /* The return address is in the link register. */
2544 trad_frame_set_reg_realreg (this_trad_cache
,
2545 gdbarch_pc_regnum (gdbarch
),
2546 num_regs
+ MIPS_RA_REGNUM
);
2548 /* Frame ID, since it's a frameless / stackless function, no stack
2549 space is allocated and SP on entry is the current SP. */
2550 pc
= get_frame_pc (this_frame
);
2551 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2552 stack_addr
= get_frame_register_signed (this_frame
,
2553 num_regs
+ MIPS_SP_REGNUM
);
2554 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2556 /* Assume that the frame's base is the same as the
2558 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2560 return this_trad_cache
;
2564 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2565 struct frame_id
*this_id
)
2567 struct trad_frame_cache
*this_trad_cache
2568 = mips_stub_frame_cache (this_frame
, this_cache
);
2569 trad_frame_get_id (this_trad_cache
, this_id
);
2572 static struct value
*
2573 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2574 void **this_cache
, int regnum
)
2576 struct trad_frame_cache
*this_trad_cache
2577 = mips_stub_frame_cache (this_frame
, this_cache
);
2578 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2582 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2583 struct frame_info
*this_frame
, void **this_cache
)
2586 struct obj_section
*s
;
2587 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2588 struct minimal_symbol
*msym
;
2590 /* Use the stub unwinder for unreadable code. */
2591 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2594 if (in_plt_section (pc
, NULL
))
2597 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2598 s
= find_pc_section (pc
);
2601 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2602 ".MIPS.stubs") == 0)
2605 /* Calling a PIC function from a non-PIC function passes through a
2606 stub. The stub for foo is named ".pic.foo". */
2607 msym
= lookup_minimal_symbol_by_pc (pc
);
2609 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2610 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2616 static const struct frame_unwind mips_stub_frame_unwind
=
2619 default_frame_unwind_stop_reason
,
2620 mips_stub_frame_this_id
,
2621 mips_stub_frame_prev_register
,
2623 mips_stub_frame_sniffer
2627 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2630 struct trad_frame_cache
*this_trad_cache
2631 = mips_stub_frame_cache (this_frame
, this_cache
);
2632 return trad_frame_get_this_base (this_trad_cache
);
2635 static const struct frame_base mips_stub_frame_base
=
2637 &mips_stub_frame_unwind
,
2638 mips_stub_frame_base_address
,
2639 mips_stub_frame_base_address
,
2640 mips_stub_frame_base_address
2643 static const struct frame_base
*
2644 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2646 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2647 return &mips_stub_frame_base
;
2652 /* mips_addr_bits_remove - remove useless address bits */
2655 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2657 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2659 if (is_mips16_addr (addr
))
2660 addr
= unmake_mips16_addr (addr
);
2662 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2663 /* This hack is a work-around for existing boards using PMON, the
2664 simulator, and any other 64-bit targets that doesn't have true
2665 64-bit addressing. On these targets, the upper 32 bits of
2666 addresses are ignored by the hardware. Thus, the PC or SP are
2667 likely to have been sign extended to all 1s by instruction
2668 sequences that load 32-bit addresses. For example, a typical
2669 piece of code that loads an address is this:
2671 lui $r2, <upper 16 bits>
2672 ori $r2, <lower 16 bits>
2674 But the lui sign-extends the value such that the upper 32 bits
2675 may be all 1s. The workaround is simply to mask off these
2676 bits. In the future, gcc may be changed to support true 64-bit
2677 addressing, and this masking will have to be disabled. */
2678 return addr
&= 0xffffffffUL
;
2683 /* Instructions used during single-stepping of atomic sequences. */
2684 #define LL_OPCODE 0x30
2685 #define LLD_OPCODE 0x34
2686 #define SC_OPCODE 0x38
2687 #define SCD_OPCODE 0x3c
2689 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2690 instruction and ending with a SC/SCD instruction. If such a sequence
2691 is found, attempt to step through it. A breakpoint is placed at the end of
2695 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2696 struct address_space
*aspace
, CORE_ADDR pc
)
2698 CORE_ADDR breaks
[2] = {-1, -1};
2700 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2704 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2705 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2710 insn
= mips_fetch_instruction (gdbarch
, loc
);
2711 /* Assume all atomic sequences start with a ll/lld instruction. */
2712 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2715 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2717 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2720 loc
+= MIPS_INSN32_SIZE
;
2721 insn
= mips_fetch_instruction (gdbarch
, loc
);
2723 /* Assume that there is at most one branch in the atomic
2724 sequence. If a branch is found, put a breakpoint in its
2725 destination address. */
2726 switch (itype_op (insn
))
2728 case 0: /* SPECIAL */
2729 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2730 return 0; /* fallback to the standard single-step code. */
2732 case 1: /* REGIMM */
2733 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
2734 || ((itype_rt (insn
) & 0x1e) == 0
2735 && itype_rs (insn
) == 0)); /* BPOSGE* */
2739 return 0; /* fallback to the standard single-step code. */
2746 case 22: /* BLEZL */
2747 case 23: /* BGTTL */
2751 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
2752 && (itype_rt (insn
) & 0x2) == 0);
2753 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
2758 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2763 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2764 if (last_breakpoint
>= 1)
2765 return 0; /* More than one branch found, fallback to the
2766 standard single-step code. */
2767 breaks
[1] = branch_bp
;
2771 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2775 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2776 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2779 loc
+= MIPS_INSN32_SIZE
;
2781 /* Insert a breakpoint right after the end of the atomic sequence. */
2784 /* Check for duplicated breakpoints. Check also for a breakpoint
2785 placed (branch instruction's destination) in the atomic sequence. */
2786 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2787 last_breakpoint
= 0;
2789 /* Effectively inserts the breakpoints. */
2790 for (index
= 0; index
<= last_breakpoint
; index
++)
2791 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2796 /* mips_software_single_step() is called just before we want to resume
2797 the inferior, if we want to single-step it but there is no hardware
2798 or kernel single-step support (MIPS on GNU/Linux for example). We find
2799 the target of the coming instruction and breakpoint it. */
2802 mips_software_single_step (struct frame_info
*frame
)
2804 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2805 struct address_space
*aspace
= get_frame_address_space (frame
);
2806 CORE_ADDR pc
, next_pc
;
2808 pc
= get_frame_pc (frame
);
2809 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2812 next_pc
= mips_next_pc (frame
, pc
);
2814 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2818 /* Test whether the PC points to the return instruction at the
2819 end of a function. */
2822 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2827 /* This used to check for MIPS16, but this piece of code is never
2828 called for MIPS16 functions. */
2829 gdb_assert (!mips_pc_is_mips16 (pc
));
2831 insn
= mips_fetch_instruction (gdbarch
, pc
);
2833 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
2837 /* This fencepost looks highly suspicious to me. Removing it also
2838 seems suspicious as it could affect remote debugging across serial
2842 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2848 struct inferior
*inf
;
2850 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2852 fence
= start_pc
- heuristic_fence_post
;
2856 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2857 fence
= VM_MIN_ADDRESS
;
2859 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2861 inf
= current_inferior ();
2863 /* Search back for previous return. */
2864 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2865 if (start_pc
< fence
)
2867 /* It's not clear to me why we reach this point when
2868 stop_soon, but with this test, at least we
2869 don't print out warnings for every child forked (eg, on
2870 decstation). 22apr93 rich@cygnus.com. */
2871 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2873 static int blurb_printed
= 0;
2875 warning (_("GDB can't find the start of the function at %s."),
2876 paddress (gdbarch
, pc
));
2880 /* This actually happens frequently in embedded
2881 development, when you first connect to a board
2882 and your stack pointer and pc are nowhere in
2883 particular. This message needs to give people
2884 in that situation enough information to
2885 determine that it's no big deal. */
2886 printf_filtered ("\n\
2887 GDB is unable to find the start of the function at %s\n\
2888 and thus can't determine the size of that function's stack frame.\n\
2889 This means that GDB may be unable to access that stack frame, or\n\
2890 the frames below it.\n\
2891 This problem is most likely caused by an invalid program counter or\n\
2893 However, if you think GDB should simply search farther back\n\
2894 from %s for code which looks like the beginning of a\n\
2895 function, you can increase the range of the search using the `set\n\
2896 heuristic-fence-post' command.\n",
2897 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2904 else if (mips_pc_is_mips16 (start_pc
))
2906 unsigned short inst
;
2908 /* On MIPS16, any one of the following is likely to be the
2909 start of a function:
2915 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
2916 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2917 if ((inst
& 0xff80) == 0x6480) /* save */
2919 if (start_pc
- instlen
>= fence
)
2921 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2922 if ((inst
& 0xf800) == 0xf000) /* extend */
2923 start_pc
-= instlen
;
2927 else if (((inst
& 0xf81f) == 0xe809
2928 && (inst
& 0x700) != 0x700) /* entry */
2929 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2930 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2931 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2933 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2934 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2939 else if (mips_about_to_return (gdbarch
, start_pc
))
2941 /* Skip return and its delay slot. */
2942 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2949 struct mips_objfile_private
2955 /* According to the current ABI, should the type be passed in a
2956 floating-point register (assuming that there is space)? When there
2957 is no FPU, FP are not even considered as possible candidates for
2958 FP registers and, consequently this returns false - forces FP
2959 arguments into integer registers. */
2962 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2963 struct type
*arg_type
)
2965 return ((typecode
== TYPE_CODE_FLT
2966 || (MIPS_EABI (gdbarch
)
2967 && (typecode
== TYPE_CODE_STRUCT
2968 || typecode
== TYPE_CODE_UNION
)
2969 && TYPE_NFIELDS (arg_type
) == 1
2970 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2972 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2975 /* On o32, argument passing in GPRs depends on the alignment of the type being
2976 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2979 mips_type_needs_double_align (struct type
*type
)
2981 enum type_code typecode
= TYPE_CODE (type
);
2983 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2985 else if (typecode
== TYPE_CODE_STRUCT
)
2987 if (TYPE_NFIELDS (type
) < 1)
2989 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2991 else if (typecode
== TYPE_CODE_UNION
)
2995 n
= TYPE_NFIELDS (type
);
2996 for (i
= 0; i
< n
; i
++)
2997 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
3004 /* Adjust the address downward (direction of stack growth) so that it
3005 is correctly aligned for a new stack frame. */
3007 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3009 return align_down (addr
, 16);
3013 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3014 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3015 int nargs
, struct value
**args
, CORE_ADDR sp
,
3016 int struct_return
, CORE_ADDR struct_addr
)
3022 int stack_offset
= 0;
3023 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3024 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3025 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3026 int regsize
= mips_abi_regsize (gdbarch
);
3028 /* For shared libraries, "t9" needs to point at the function
3030 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3032 /* Set the return address register to point to the entry point of
3033 the program, where a breakpoint lies in wait. */
3034 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3036 /* First ensure that the stack and structure return address (if any)
3037 are properly aligned. The stack has to be at least 64-bit
3038 aligned even on 32-bit machines, because doubles must be 64-bit
3039 aligned. For n32 and n64, stack frames need to be 128-bit
3040 aligned, so we round to this widest known alignment. */
3042 sp
= align_down (sp
, 16);
3043 struct_addr
= align_down (struct_addr
, 16);
3045 /* Now make space on the stack for the args. We allocate more
3046 than necessary for EABI, because the first few arguments are
3047 passed in registers, but that's OK. */
3048 for (argnum
= 0; argnum
< nargs
; argnum
++)
3049 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
3050 sp
-= align_up (len
, 16);
3053 fprintf_unfiltered (gdb_stdlog
,
3054 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
3055 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3057 /* Initialize the integer and float register pointers. */
3058 argreg
= MIPS_A0_REGNUM
;
3059 float_argreg
= mips_fpa0_regnum (gdbarch
);
3061 /* The struct_return pointer occupies the first parameter-passing reg. */
3065 fprintf_unfiltered (gdb_stdlog
,
3066 "mips_eabi_push_dummy_call: "
3067 "struct_return reg=%d %s\n",
3068 argreg
, paddress (gdbarch
, struct_addr
));
3069 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3072 /* Now load as many as possible of the first arguments into
3073 registers, and push the rest onto the stack. Loop thru args
3074 from first to last. */
3075 for (argnum
= 0; argnum
< nargs
; argnum
++)
3077 const gdb_byte
*val
;
3078 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
3079 struct value
*arg
= args
[argnum
];
3080 struct type
*arg_type
= check_typedef (value_type (arg
));
3081 int len
= TYPE_LENGTH (arg_type
);
3082 enum type_code typecode
= TYPE_CODE (arg_type
);
3085 fprintf_unfiltered (gdb_stdlog
,
3086 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3087 argnum
+ 1, len
, (int) typecode
);
3089 /* Function pointer arguments to mips16 code need to be made into
3091 if (typecode
== TYPE_CODE_PTR
3092 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
3094 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
3096 if (mips_pc_is_mips16 (addr
))
3098 store_signed_integer (valbuf
, len
, byte_order
,
3099 make_mips16_addr (addr
));
3103 val
= value_contents (arg
);
3105 /* The EABI passes structures that do not fit in a register by
3107 else if (len
> regsize
3108 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3110 store_unsigned_integer (valbuf
, regsize
, byte_order
,
3111 value_address (arg
));
3112 typecode
= TYPE_CODE_PTR
;
3116 fprintf_unfiltered (gdb_stdlog
, " push");
3119 val
= value_contents (arg
);
3121 /* 32-bit ABIs always start floating point arguments in an
3122 even-numbered floating point register. Round the FP register
3123 up before the check to see if there are any FP registers
3124 left. Non MIPS_EABI targets also pass the FP in the integer
3125 registers so also round up normal registers. */
3126 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3128 if ((float_argreg
& 1))
3132 /* Floating point arguments passed in registers have to be
3133 treated specially. On 32-bit architectures, doubles
3134 are passed in register pairs; the even register gets
3135 the low word, and the odd register gets the high word.
3136 On non-EABI processors, the first two floating point arguments are
3137 also copied to general registers, because MIPS16 functions
3138 don't use float registers for arguments. This duplication of
3139 arguments in general registers can't hurt non-MIPS16 functions
3140 because those registers are normally skipped. */
3141 /* MIPS_EABI squeezes a struct that contains a single floating
3142 point value into an FP register instead of pushing it onto the
3144 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3145 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3147 /* EABI32 will pass doubles in consecutive registers, even on
3148 64-bit cores. At one time, we used to check the size of
3149 `float_argreg' to determine whether or not to pass doubles
3150 in consecutive registers, but this is not sufficient for
3151 making the ABI determination. */
3152 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
3154 int low_offset
= gdbarch_byte_order (gdbarch
)
3155 == BFD_ENDIAN_BIG
? 4 : 0;
3158 /* Write the low word of the double to the even register(s). */
3159 regval
= extract_signed_integer (val
+ low_offset
,
3162 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3163 float_argreg
, phex (regval
, 4));
3164 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3166 /* Write the high word of the double to the odd register(s). */
3167 regval
= extract_signed_integer (val
+ 4 - low_offset
,
3170 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3171 float_argreg
, phex (regval
, 4));
3172 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3176 /* This is a floating point value that fits entirely
3177 in a single register. */
3178 /* On 32 bit ABI's the float_argreg is further adjusted
3179 above to ensure that it is even register aligned. */
3180 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
3182 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3183 float_argreg
, phex (regval
, len
));
3184 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3189 /* Copy the argument to general registers or the stack in
3190 register-sized pieces. Large arguments are split between
3191 registers and stack. */
3192 /* Note: structs whose size is not a multiple of regsize
3193 are treated specially: Irix cc passes
3194 them in registers where gcc sometimes puts them on the
3195 stack. For maximum compatibility, we will put them in
3197 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3199 /* Note: Floating-point values that didn't fit into an FP
3200 register are only written to memory. */
3203 /* Remember if the argument was written to the stack. */
3204 int stack_used_p
= 0;
3205 int partial_len
= (len
< regsize
? len
: regsize
);
3208 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3211 /* Write this portion of the argument to the stack. */
3212 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3214 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3216 /* Should shorter than int integer values be
3217 promoted to int before being stored? */
3218 int longword_offset
= 0;
3221 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3224 && (typecode
== TYPE_CODE_INT
3225 || typecode
== TYPE_CODE_PTR
3226 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3227 longword_offset
= regsize
- len
;
3228 else if ((typecode
== TYPE_CODE_STRUCT
3229 || typecode
== TYPE_CODE_UNION
)
3230 && TYPE_LENGTH (arg_type
) < regsize
)
3231 longword_offset
= regsize
- len
;
3236 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3237 paddress (gdbarch
, stack_offset
));
3238 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3239 paddress (gdbarch
, longword_offset
));
3242 addr
= sp
+ stack_offset
+ longword_offset
;
3247 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3248 paddress (gdbarch
, addr
));
3249 for (i
= 0; i
< partial_len
; i
++)
3251 fprintf_unfiltered (gdb_stdlog
, "%02x",
3255 write_memory (addr
, val
, partial_len
);
3258 /* Note!!! This is NOT an else clause. Odd sized
3259 structs may go thru BOTH paths. Floating point
3260 arguments will not. */
3261 /* Write this portion of the argument to a general
3262 purpose register. */
3263 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3264 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3267 extract_signed_integer (val
, partial_len
, byte_order
);
3270 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3272 phex (regval
, regsize
));
3273 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3280 /* Compute the offset into the stack at which we will
3281 copy the next parameter.
3283 In the new EABI (and the NABI32), the stack_offset
3284 only needs to be adjusted when it has been used. */
3287 stack_offset
+= align_up (partial_len
, regsize
);
3291 fprintf_unfiltered (gdb_stdlog
, "\n");
3294 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3296 /* Return adjusted stack pointer. */
3300 /* Determine the return value convention being used. */
3302 static enum return_value_convention
3303 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3304 struct type
*type
, struct regcache
*regcache
,
3305 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3307 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3308 int fp_return_type
= 0;
3309 int offset
, regnum
, xfer
;
3311 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3312 return RETURN_VALUE_STRUCT_CONVENTION
;
3314 /* Floating point type? */
3315 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3317 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3319 /* Structs with a single field of float type
3320 are returned in a floating point register. */
3321 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3322 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3323 && TYPE_NFIELDS (type
) == 1)
3325 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3327 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3334 /* A floating-point value belongs in the least significant part
3337 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3338 regnum
= mips_regnum (gdbarch
)->fp0
;
3342 /* An integer value goes in V0/V1. */
3344 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3345 regnum
= MIPS_V0_REGNUM
;
3348 offset
< TYPE_LENGTH (type
);
3349 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3351 xfer
= mips_abi_regsize (gdbarch
);
3352 if (offset
+ xfer
> TYPE_LENGTH (type
))
3353 xfer
= TYPE_LENGTH (type
) - offset
;
3354 mips_xfer_register (gdbarch
, regcache
,
3355 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3356 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3360 return RETURN_VALUE_REGISTER_CONVENTION
;
3364 /* N32/N64 ABI stuff. */
3366 /* Search for a naturally aligned double at OFFSET inside a struct
3367 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3371 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3376 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3379 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3382 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3385 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3388 struct type
*field_type
;
3390 /* We're only looking at normal fields. */
3391 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3392 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3395 /* If we have gone past the offset, there is no double to pass. */
3396 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3400 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3402 /* If this field is entirely before the requested offset, go
3403 on to the next one. */
3404 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3407 /* If this is our special aligned double, we can stop. */
3408 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3409 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3412 /* This field starts at or before the requested offset, and
3413 overlaps it. If it is a structure, recurse inwards. */
3414 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3421 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3422 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3423 int nargs
, struct value
**args
, CORE_ADDR sp
,
3424 int struct_return
, CORE_ADDR struct_addr
)
3430 int stack_offset
= 0;
3431 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3432 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3433 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3435 /* For shared libraries, "t9" needs to point at the function
3437 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3439 /* Set the return address register to point to the entry point of
3440 the program, where a breakpoint lies in wait. */
3441 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3443 /* First ensure that the stack and structure return address (if any)
3444 are properly aligned. The stack has to be at least 64-bit
3445 aligned even on 32-bit machines, because doubles must be 64-bit
3446 aligned. For n32 and n64, stack frames need to be 128-bit
3447 aligned, so we round to this widest known alignment. */
3449 sp
= align_down (sp
, 16);
3450 struct_addr
= align_down (struct_addr
, 16);
3452 /* Now make space on the stack for the args. */
3453 for (argnum
= 0; argnum
< nargs
; argnum
++)
3454 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3455 sp
-= align_up (len
, 16);
3458 fprintf_unfiltered (gdb_stdlog
,
3459 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3460 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3462 /* Initialize the integer and float register pointers. */
3463 argreg
= MIPS_A0_REGNUM
;
3464 float_argreg
= mips_fpa0_regnum (gdbarch
);
3466 /* The struct_return pointer occupies the first parameter-passing reg. */
3470 fprintf_unfiltered (gdb_stdlog
,
3471 "mips_n32n64_push_dummy_call: "
3472 "struct_return reg=%d %s\n",
3473 argreg
, paddress (gdbarch
, struct_addr
));
3474 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3477 /* Now load as many as possible of the first arguments into
3478 registers, and push the rest onto the stack. Loop thru args
3479 from first to last. */
3480 for (argnum
= 0; argnum
< nargs
; argnum
++)
3482 const gdb_byte
*val
;
3483 struct value
*arg
= args
[argnum
];
3484 struct type
*arg_type
= check_typedef (value_type (arg
));
3485 int len
= TYPE_LENGTH (arg_type
);
3486 enum type_code typecode
= TYPE_CODE (arg_type
);
3489 fprintf_unfiltered (gdb_stdlog
,
3490 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3491 argnum
+ 1, len
, (int) typecode
);
3493 val
= value_contents (arg
);
3495 /* A 128-bit long double value requires an even-odd pair of
3496 floating-point registers. */
3498 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3499 && (float_argreg
& 1))
3505 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3506 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3508 /* This is a floating point value that fits entirely
3509 in a single register or a pair of registers. */
3510 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3511 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3513 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3514 float_argreg
, phex (regval
, reglen
));
3515 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3518 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3519 argreg
, phex (regval
, reglen
));
3520 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3525 regval
= extract_unsigned_integer (val
+ reglen
,
3526 reglen
, byte_order
);
3528 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3529 float_argreg
, phex (regval
, reglen
));
3530 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3533 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3534 argreg
, phex (regval
, reglen
));
3535 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3542 /* Copy the argument to general registers or the stack in
3543 register-sized pieces. Large arguments are split between
3544 registers and stack. */
3545 /* For N32/N64, structs, unions, or other composite types are
3546 treated as a sequence of doublewords, and are passed in integer
3547 or floating point registers as though they were simple scalar
3548 parameters to the extent that they fit, with any excess on the
3549 stack packed according to the normal memory layout of the
3551 The caller does not reserve space for the register arguments;
3552 the callee is responsible for reserving it if required. */
3553 /* Note: Floating-point values that didn't fit into an FP
3554 register are only written to memory. */
3557 /* Remember if the argument was written to the stack. */
3558 int stack_used_p
= 0;
3559 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3562 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3565 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3566 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3568 /* Write this portion of the argument to the stack. */
3569 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3571 /* Should shorter than int integer values be
3572 promoted to int before being stored? */
3573 int longword_offset
= 0;
3576 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3578 if ((typecode
== TYPE_CODE_INT
3579 || typecode
== TYPE_CODE_PTR
)
3581 longword_offset
= MIPS64_REGSIZE
- len
;
3586 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3587 paddress (gdbarch
, stack_offset
));
3588 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3589 paddress (gdbarch
, longword_offset
));
3592 addr
= sp
+ stack_offset
+ longword_offset
;
3597 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3598 paddress (gdbarch
, addr
));
3599 for (i
= 0; i
< partial_len
; i
++)
3601 fprintf_unfiltered (gdb_stdlog
, "%02x",
3605 write_memory (addr
, val
, partial_len
);
3608 /* Note!!! This is NOT an else clause. Odd sized
3609 structs may go thru BOTH paths. */
3610 /* Write this portion of the argument to a general
3611 purpose register. */
3612 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3616 /* Sign extend pointers, 32-bit integers and signed
3617 16-bit and 8-bit integers; everything else is taken
3620 if ((partial_len
== 4
3621 && (typecode
== TYPE_CODE_PTR
3622 || typecode
== TYPE_CODE_INT
))
3624 && typecode
== TYPE_CODE_INT
3625 && !TYPE_UNSIGNED (arg_type
)))
3626 regval
= extract_signed_integer (val
, partial_len
,
3629 regval
= extract_unsigned_integer (val
, partial_len
,
3632 /* A non-floating-point argument being passed in a
3633 general register. If a struct or union, and if
3634 the remaining length is smaller than the register
3635 size, we have to adjust the register value on
3638 It does not seem to be necessary to do the
3639 same for integral types. */
3641 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3642 && partial_len
< MIPS64_REGSIZE
3643 && (typecode
== TYPE_CODE_STRUCT
3644 || typecode
== TYPE_CODE_UNION
))
3645 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3649 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3651 phex (regval
, MIPS64_REGSIZE
));
3652 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3654 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3655 TYPE_LENGTH (arg_type
) - len
))
3658 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3660 phex (regval
, MIPS64_REGSIZE
));
3661 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3672 /* Compute the offset into the stack at which we will
3673 copy the next parameter.
3675 In N32 (N64?), the stack_offset only needs to be
3676 adjusted when it has been used. */
3679 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3683 fprintf_unfiltered (gdb_stdlog
, "\n");
3686 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3688 /* Return adjusted stack pointer. */
3692 static enum return_value_convention
3693 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3694 struct type
*type
, struct regcache
*regcache
,
3695 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3697 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3699 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3701 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3702 if needed), as appropriate for the type. Composite results (struct,
3703 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3706 * A struct with only one or two floating point fields is returned in $f0
3707 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3710 * Any other composite results of at most 128 bits are returned in
3711 $2 (first 64 bits) and $3 (remainder, if necessary).
3713 * Larger composite results are handled by converting the function to a
3714 procedure with an implicit first parameter, which is a pointer to an area
3715 reserved by the caller to receive the result. [The o32-bit ABI requires
3716 that all composite results be handled by conversion to implicit first
3717 parameters. The MIPS/SGI Fortran implementation has always made a
3718 specific exception to return COMPLEX results in the floating point
3721 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3722 return RETURN_VALUE_STRUCT_CONVENTION
;
3723 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3724 && TYPE_LENGTH (type
) == 16
3725 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3727 /* A 128-bit floating-point value fills both $f0 and $f2. The
3728 two registers are used in the same as memory order, so the
3729 eight bytes with the lower memory address are in $f0. */
3731 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3732 mips_xfer_register (gdbarch
, regcache
,
3733 (gdbarch_num_regs (gdbarch
)
3734 + mips_regnum (gdbarch
)->fp0
),
3735 8, gdbarch_byte_order (gdbarch
),
3736 readbuf
, writebuf
, 0);
3737 mips_xfer_register (gdbarch
, regcache
,
3738 (gdbarch_num_regs (gdbarch
)
3739 + mips_regnum (gdbarch
)->fp0
+ 2),
3740 8, gdbarch_byte_order (gdbarch
),
3741 readbuf
? readbuf
+ 8 : readbuf
,
3742 writebuf
? writebuf
+ 8 : writebuf
, 0);
3743 return RETURN_VALUE_REGISTER_CONVENTION
;
3745 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3746 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3748 /* A single or double floating-point value that fits in FP0. */
3750 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3751 mips_xfer_register (gdbarch
, regcache
,
3752 (gdbarch_num_regs (gdbarch
)
3753 + mips_regnum (gdbarch
)->fp0
),
3755 gdbarch_byte_order (gdbarch
),
3756 readbuf
, writebuf
, 0);
3757 return RETURN_VALUE_REGISTER_CONVENTION
;
3759 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3760 && TYPE_NFIELDS (type
) <= 2
3761 && TYPE_NFIELDS (type
) >= 1
3762 && ((TYPE_NFIELDS (type
) == 1
3763 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3765 || (TYPE_NFIELDS (type
) == 2
3766 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3768 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3769 == TYPE_CODE_FLT
))))
3771 /* A struct that contains one or two floats. Each value is part
3772 in the least significant part of their floating point
3773 register (or GPR, for soft float). */
3776 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3777 ? mips_regnum (gdbarch
)->fp0
3779 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3781 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3784 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3786 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3788 /* A 16-byte long double field goes in two consecutive
3790 mips_xfer_register (gdbarch
, regcache
,
3791 gdbarch_num_regs (gdbarch
) + regnum
,
3793 gdbarch_byte_order (gdbarch
),
3794 readbuf
, writebuf
, offset
);
3795 mips_xfer_register (gdbarch
, regcache
,
3796 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3798 gdbarch_byte_order (gdbarch
),
3799 readbuf
, writebuf
, offset
+ 8);
3802 mips_xfer_register (gdbarch
, regcache
,
3803 gdbarch_num_regs (gdbarch
) + regnum
,
3804 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3805 gdbarch_byte_order (gdbarch
),
3806 readbuf
, writebuf
, offset
);
3808 return RETURN_VALUE_REGISTER_CONVENTION
;
3810 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3811 || TYPE_CODE (type
) == TYPE_CODE_UNION
3812 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3814 /* A composite type. Extract the left justified value,
3815 regardless of the byte order. I.e. DO NOT USE
3819 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3820 offset
< TYPE_LENGTH (type
);
3821 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3823 int xfer
= register_size (gdbarch
, regnum
);
3824 if (offset
+ xfer
> TYPE_LENGTH (type
))
3825 xfer
= TYPE_LENGTH (type
) - offset
;
3827 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3828 offset
, xfer
, regnum
);
3829 mips_xfer_register (gdbarch
, regcache
,
3830 gdbarch_num_regs (gdbarch
) + regnum
,
3831 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3834 return RETURN_VALUE_REGISTER_CONVENTION
;
3838 /* A scalar extract each part but least-significant-byte
3842 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3843 offset
< TYPE_LENGTH (type
);
3844 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3846 int xfer
= register_size (gdbarch
, regnum
);
3847 if (offset
+ xfer
> TYPE_LENGTH (type
))
3848 xfer
= TYPE_LENGTH (type
) - offset
;
3850 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3851 offset
, xfer
, regnum
);
3852 mips_xfer_register (gdbarch
, regcache
,
3853 gdbarch_num_regs (gdbarch
) + regnum
,
3854 xfer
, gdbarch_byte_order (gdbarch
),
3855 readbuf
, writebuf
, offset
);
3857 return RETURN_VALUE_REGISTER_CONVENTION
;
3861 /* O32 ABI stuff. */
3864 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3865 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3866 int nargs
, struct value
**args
, CORE_ADDR sp
,
3867 int struct_return
, CORE_ADDR struct_addr
)
3873 int stack_offset
= 0;
3874 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3875 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3876 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3878 /* For shared libraries, "t9" needs to point at the function
3880 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3882 /* Set the return address register to point to the entry point of
3883 the program, where a breakpoint lies in wait. */
3884 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3886 /* First ensure that the stack and structure return address (if any)
3887 are properly aligned. The stack has to be at least 64-bit
3888 aligned even on 32-bit machines, because doubles must be 64-bit
3889 aligned. For n32 and n64, stack frames need to be 128-bit
3890 aligned, so we round to this widest known alignment. */
3892 sp
= align_down (sp
, 16);
3893 struct_addr
= align_down (struct_addr
, 16);
3895 /* Now make space on the stack for the args. */
3896 for (argnum
= 0; argnum
< nargs
; argnum
++)
3898 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3899 int arglen
= TYPE_LENGTH (arg_type
);
3901 /* Align to double-word if necessary. */
3902 if (mips_type_needs_double_align (arg_type
))
3903 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3904 /* Allocate space on the stack. */
3905 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3907 sp
-= align_up (len
, 16);
3910 fprintf_unfiltered (gdb_stdlog
,
3911 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3912 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3914 /* Initialize the integer and float register pointers. */
3915 argreg
= MIPS_A0_REGNUM
;
3916 float_argreg
= mips_fpa0_regnum (gdbarch
);
3918 /* The struct_return pointer occupies the first parameter-passing reg. */
3922 fprintf_unfiltered (gdb_stdlog
,
3923 "mips_o32_push_dummy_call: "
3924 "struct_return reg=%d %s\n",
3925 argreg
, paddress (gdbarch
, struct_addr
));
3926 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3927 stack_offset
+= MIPS32_REGSIZE
;
3930 /* Now load as many as possible of the first arguments into
3931 registers, and push the rest onto the stack. Loop thru args
3932 from first to last. */
3933 for (argnum
= 0; argnum
< nargs
; argnum
++)
3935 const gdb_byte
*val
;
3936 struct value
*arg
= args
[argnum
];
3937 struct type
*arg_type
= check_typedef (value_type (arg
));
3938 int len
= TYPE_LENGTH (arg_type
);
3939 enum type_code typecode
= TYPE_CODE (arg_type
);
3942 fprintf_unfiltered (gdb_stdlog
,
3943 "mips_o32_push_dummy_call: %d len=%d type=%d",
3944 argnum
+ 1, len
, (int) typecode
);
3946 val
= value_contents (arg
);
3948 /* 32-bit ABIs always start floating point arguments in an
3949 even-numbered floating point register. Round the FP register
3950 up before the check to see if there are any FP registers
3951 left. O32/O64 targets also pass the FP in the integer
3952 registers so also round up normal registers. */
3953 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3955 if ((float_argreg
& 1))
3959 /* Floating point arguments passed in registers have to be
3960 treated specially. On 32-bit architectures, doubles
3961 are passed in register pairs; the even register gets
3962 the low word, and the odd register gets the high word.
3963 On O32/O64, the first two floating point arguments are
3964 also copied to general registers, because MIPS16 functions
3965 don't use float registers for arguments. This duplication of
3966 arguments in general registers can't hurt non-MIPS16 functions
3967 because those registers are normally skipped. */
3969 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3970 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3972 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3974 int low_offset
= gdbarch_byte_order (gdbarch
)
3975 == BFD_ENDIAN_BIG
? 4 : 0;
3976 unsigned long regval
;
3978 /* Write the low word of the double to the even register(s). */
3979 regval
= extract_unsigned_integer (val
+ low_offset
,
3982 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3983 float_argreg
, phex (regval
, 4));
3984 regcache_cooked_write_unsigned (regcache
,
3985 float_argreg
++, regval
);
3987 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3988 argreg
, phex (regval
, 4));
3989 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3991 /* Write the high word of the double to the odd register(s). */
3992 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3995 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3996 float_argreg
, phex (regval
, 4));
3997 regcache_cooked_write_unsigned (regcache
,
3998 float_argreg
++, regval
);
4001 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4002 argreg
, phex (regval
, 4));
4003 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
4007 /* This is a floating point value that fits entirely
4008 in a single register. */
4009 /* On 32 bit ABI's the float_argreg is further adjusted
4010 above to ensure that it is even register aligned. */
4011 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4013 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4014 float_argreg
, phex (regval
, len
));
4015 regcache_cooked_write_unsigned (regcache
,
4016 float_argreg
++, regval
);
4017 /* Although two FP registers are reserved for each
4018 argument, only one corresponding integer register is
4021 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4022 argreg
, phex (regval
, len
));
4023 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
4025 /* Reserve space for the FP register. */
4026 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
4030 /* Copy the argument to general registers or the stack in
4031 register-sized pieces. Large arguments are split between
4032 registers and stack. */
4033 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
4034 are treated specially: Irix cc passes
4035 them in registers where gcc sometimes puts them on the
4036 stack. For maximum compatibility, we will put them in
4038 int odd_sized_struct
= (len
> MIPS32_REGSIZE
4039 && len
% MIPS32_REGSIZE
!= 0);
4040 /* Structures should be aligned to eight bytes (even arg registers)
4041 on MIPS_ABI_O32, if their first member has double precision. */
4042 if (mips_type_needs_double_align (arg_type
))
4047 stack_offset
+= MIPS32_REGSIZE
;
4052 /* Remember if the argument was written to the stack. */
4053 int stack_used_p
= 0;
4054 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
4057 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4060 /* Write this portion of the argument to the stack. */
4061 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4062 || odd_sized_struct
)
4064 /* Should shorter than int integer values be
4065 promoted to int before being stored? */
4066 int longword_offset
= 0;
4072 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4073 paddress (gdbarch
, stack_offset
));
4074 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4075 paddress (gdbarch
, longword_offset
));
4078 addr
= sp
+ stack_offset
+ longword_offset
;
4083 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4084 paddress (gdbarch
, addr
));
4085 for (i
= 0; i
< partial_len
; i
++)
4087 fprintf_unfiltered (gdb_stdlog
, "%02x",
4091 write_memory (addr
, val
, partial_len
);
4094 /* Note!!! This is NOT an else clause. Odd sized
4095 structs may go thru BOTH paths. */
4096 /* Write this portion of the argument to a general
4097 purpose register. */
4098 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4100 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4102 /* Value may need to be sign extended, because
4103 mips_isa_regsize() != mips_abi_regsize(). */
4105 /* A non-floating-point argument being passed in a
4106 general register. If a struct or union, and if
4107 the remaining length is smaller than the register
4108 size, we have to adjust the register value on
4111 It does not seem to be necessary to do the
4112 same for integral types.
4114 Also don't do this adjustment on O64 binaries.
4116 cagney/2001-07-23: gdb/179: Also, GCC, when
4117 outputting LE O32 with sizeof (struct) <
4118 mips_abi_regsize(), generates a left shift
4119 as part of storing the argument in a register
4120 (the left shift isn't generated when
4121 sizeof (struct) >= mips_abi_regsize()). Since
4122 it is quite possible that this is GCC
4123 contradicting the LE/O32 ABI, GDB has not been
4124 adjusted to accommodate this. Either someone
4125 needs to demonstrate that the LE/O32 ABI
4126 specifies such a left shift OR this new ABI gets
4127 identified as such and GDB gets tweaked
4130 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4131 && partial_len
< MIPS32_REGSIZE
4132 && (typecode
== TYPE_CODE_STRUCT
4133 || typecode
== TYPE_CODE_UNION
))
4134 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
4138 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4140 phex (regval
, MIPS32_REGSIZE
));
4141 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4144 /* Prevent subsequent floating point arguments from
4145 being passed in floating point registers. */
4146 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4152 /* Compute the offset into the stack at which we will
4153 copy the next parameter.
4155 In older ABIs, the caller reserved space for
4156 registers that contained arguments. This was loosely
4157 refered to as their "home". Consequently, space is
4158 always allocated. */
4160 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
4164 fprintf_unfiltered (gdb_stdlog
, "\n");
4167 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4169 /* Return adjusted stack pointer. */
4173 static enum return_value_convention
4174 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4175 struct type
*type
, struct regcache
*regcache
,
4176 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4178 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4180 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4181 || TYPE_CODE (type
) == TYPE_CODE_UNION
4182 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4183 return RETURN_VALUE_STRUCT_CONVENTION
;
4184 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4185 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4187 /* A single-precision floating-point value. It fits in the
4188 least significant part of FP0. */
4190 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4191 mips_xfer_register (gdbarch
, regcache
,
4192 (gdbarch_num_regs (gdbarch
)
4193 + mips_regnum (gdbarch
)->fp0
),
4195 gdbarch_byte_order (gdbarch
),
4196 readbuf
, writebuf
, 0);
4197 return RETURN_VALUE_REGISTER_CONVENTION
;
4199 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4200 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4202 /* A double-precision floating-point value. The most
4203 significant part goes in FP1, and the least significant in
4206 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4207 switch (gdbarch_byte_order (gdbarch
))
4209 case BFD_ENDIAN_LITTLE
:
4210 mips_xfer_register (gdbarch
, regcache
,
4211 (gdbarch_num_regs (gdbarch
)
4212 + mips_regnum (gdbarch
)->fp0
+ 0),
4213 4, gdbarch_byte_order (gdbarch
),
4214 readbuf
, writebuf
, 0);
4215 mips_xfer_register (gdbarch
, regcache
,
4216 (gdbarch_num_regs (gdbarch
)
4217 + mips_regnum (gdbarch
)->fp0
+ 1),
4218 4, gdbarch_byte_order (gdbarch
),
4219 readbuf
, writebuf
, 4);
4221 case BFD_ENDIAN_BIG
:
4222 mips_xfer_register (gdbarch
, regcache
,
4223 (gdbarch_num_regs (gdbarch
)
4224 + mips_regnum (gdbarch
)->fp0
+ 1),
4225 4, gdbarch_byte_order (gdbarch
),
4226 readbuf
, writebuf
, 0);
4227 mips_xfer_register (gdbarch
, regcache
,
4228 (gdbarch_num_regs (gdbarch
)
4229 + mips_regnum (gdbarch
)->fp0
+ 0),
4230 4, gdbarch_byte_order (gdbarch
),
4231 readbuf
, writebuf
, 4);
4234 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4236 return RETURN_VALUE_REGISTER_CONVENTION
;
4239 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4240 && TYPE_NFIELDS (type
) <= 2
4241 && TYPE_NFIELDS (type
) >= 1
4242 && ((TYPE_NFIELDS (type
) == 1
4243 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4245 || (TYPE_NFIELDS (type
) == 2
4246 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4248 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4250 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4252 /* A struct that contains one or two floats. Each value is part
4253 in the least significant part of their floating point
4255 gdb_byte reg
[MAX_REGISTER_SIZE
];
4258 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4259 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4261 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4264 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4266 mips_xfer_register (gdbarch
, regcache
,
4267 gdbarch_num_regs (gdbarch
) + regnum
,
4268 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4269 gdbarch_byte_order (gdbarch
),
4270 readbuf
, writebuf
, offset
);
4272 return RETURN_VALUE_REGISTER_CONVENTION
;
4276 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4277 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4279 /* A structure or union. Extract the left justified value,
4280 regardless of the byte order. I.e. DO NOT USE
4284 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4285 offset
< TYPE_LENGTH (type
);
4286 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4288 int xfer
= register_size (gdbarch
, regnum
);
4289 if (offset
+ xfer
> TYPE_LENGTH (type
))
4290 xfer
= TYPE_LENGTH (type
) - offset
;
4292 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4293 offset
, xfer
, regnum
);
4294 mips_xfer_register (gdbarch
, regcache
,
4295 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4296 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4298 return RETURN_VALUE_REGISTER_CONVENTION
;
4303 /* A scalar extract each part but least-significant-byte
4304 justified. o32 thinks registers are 4 byte, regardless of
4308 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4309 offset
< TYPE_LENGTH (type
);
4310 offset
+= MIPS32_REGSIZE
, regnum
++)
4312 int xfer
= MIPS32_REGSIZE
;
4313 if (offset
+ xfer
> TYPE_LENGTH (type
))
4314 xfer
= TYPE_LENGTH (type
) - offset
;
4316 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4317 offset
, xfer
, regnum
);
4318 mips_xfer_register (gdbarch
, regcache
,
4319 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4320 gdbarch_byte_order (gdbarch
),
4321 readbuf
, writebuf
, offset
);
4323 return RETURN_VALUE_REGISTER_CONVENTION
;
4327 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4331 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4332 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4334 struct value
**args
, CORE_ADDR sp
,
4335 int struct_return
, CORE_ADDR struct_addr
)
4341 int stack_offset
= 0;
4342 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4343 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4344 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4346 /* For shared libraries, "t9" needs to point at the function
4348 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4350 /* Set the return address register to point to the entry point of
4351 the program, where a breakpoint lies in wait. */
4352 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4354 /* First ensure that the stack and structure return address (if any)
4355 are properly aligned. The stack has to be at least 64-bit
4356 aligned even on 32-bit machines, because doubles must be 64-bit
4357 aligned. For n32 and n64, stack frames need to be 128-bit
4358 aligned, so we round to this widest known alignment. */
4360 sp
= align_down (sp
, 16);
4361 struct_addr
= align_down (struct_addr
, 16);
4363 /* Now make space on the stack for the args. */
4364 for (argnum
= 0; argnum
< nargs
; argnum
++)
4366 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4367 int arglen
= TYPE_LENGTH (arg_type
);
4369 /* Allocate space on the stack. */
4370 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4372 sp
-= align_up (len
, 16);
4375 fprintf_unfiltered (gdb_stdlog
,
4376 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4377 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4379 /* Initialize the integer and float register pointers. */
4380 argreg
= MIPS_A0_REGNUM
;
4381 float_argreg
= mips_fpa0_regnum (gdbarch
);
4383 /* The struct_return pointer occupies the first parameter-passing reg. */
4387 fprintf_unfiltered (gdb_stdlog
,
4388 "mips_o64_push_dummy_call: "
4389 "struct_return reg=%d %s\n",
4390 argreg
, paddress (gdbarch
, struct_addr
));
4391 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4392 stack_offset
+= MIPS64_REGSIZE
;
4395 /* Now load as many as possible of the first arguments into
4396 registers, and push the rest onto the stack. Loop thru args
4397 from first to last. */
4398 for (argnum
= 0; argnum
< nargs
; argnum
++)
4400 const gdb_byte
*val
;
4401 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4402 struct value
*arg
= args
[argnum
];
4403 struct type
*arg_type
= check_typedef (value_type (arg
));
4404 int len
= TYPE_LENGTH (arg_type
);
4405 enum type_code typecode
= TYPE_CODE (arg_type
);
4408 fprintf_unfiltered (gdb_stdlog
,
4409 "mips_o64_push_dummy_call: %d len=%d type=%d",
4410 argnum
+ 1, len
, (int) typecode
);
4412 val
= value_contents (arg
);
4414 /* Function pointer arguments to mips16 code need to be made into
4416 if (typecode
== TYPE_CODE_PTR
4417 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4419 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4421 if (mips_pc_is_mips16 (addr
))
4423 store_signed_integer (valbuf
, len
, byte_order
,
4424 make_mips16_addr (addr
));
4429 /* Floating point arguments passed in registers have to be
4430 treated specially. On 32-bit architectures, doubles
4431 are passed in register pairs; the even register gets
4432 the low word, and the odd register gets the high word.
4433 On O32/O64, the first two floating point arguments are
4434 also copied to general registers, because MIPS16 functions
4435 don't use float registers for arguments. This duplication of
4436 arguments in general registers can't hurt non-MIPS16 functions
4437 because those registers are normally skipped. */
4439 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4440 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4442 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4444 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4445 float_argreg
, phex (regval
, len
));
4446 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4448 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4449 argreg
, phex (regval
, len
));
4450 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4452 /* Reserve space for the FP register. */
4453 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4457 /* Copy the argument to general registers or the stack in
4458 register-sized pieces. Large arguments are split between
4459 registers and stack. */
4460 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4461 are treated specially: Irix cc passes them in registers
4462 where gcc sometimes puts them on the stack. For maximum
4463 compatibility, we will put them in both places. */
4464 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4465 && len
% MIPS64_REGSIZE
!= 0);
4468 /* Remember if the argument was written to the stack. */
4469 int stack_used_p
= 0;
4470 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4473 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4476 /* Write this portion of the argument to the stack. */
4477 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4478 || odd_sized_struct
)
4480 /* Should shorter than int integer values be
4481 promoted to int before being stored? */
4482 int longword_offset
= 0;
4485 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4487 if ((typecode
== TYPE_CODE_INT
4488 || typecode
== TYPE_CODE_PTR
4489 || typecode
== TYPE_CODE_FLT
)
4491 longword_offset
= MIPS64_REGSIZE
- len
;
4496 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4497 paddress (gdbarch
, stack_offset
));
4498 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4499 paddress (gdbarch
, longword_offset
));
4502 addr
= sp
+ stack_offset
+ longword_offset
;
4507 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4508 paddress (gdbarch
, addr
));
4509 for (i
= 0; i
< partial_len
; i
++)
4511 fprintf_unfiltered (gdb_stdlog
, "%02x",
4515 write_memory (addr
, val
, partial_len
);
4518 /* Note!!! This is NOT an else clause. Odd sized
4519 structs may go thru BOTH paths. */
4520 /* Write this portion of the argument to a general
4521 purpose register. */
4522 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4524 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4526 /* Value may need to be sign extended, because
4527 mips_isa_regsize() != mips_abi_regsize(). */
4529 /* A non-floating-point argument being passed in a
4530 general register. If a struct or union, and if
4531 the remaining length is smaller than the register
4532 size, we have to adjust the register value on
4535 It does not seem to be necessary to do the
4536 same for integral types. */
4538 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4539 && partial_len
< MIPS64_REGSIZE
4540 && (typecode
== TYPE_CODE_STRUCT
4541 || typecode
== TYPE_CODE_UNION
))
4542 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4546 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4548 phex (regval
, MIPS64_REGSIZE
));
4549 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4552 /* Prevent subsequent floating point arguments from
4553 being passed in floating point registers. */
4554 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4560 /* Compute the offset into the stack at which we will
4561 copy the next parameter.
4563 In older ABIs, the caller reserved space for
4564 registers that contained arguments. This was loosely
4565 refered to as their "home". Consequently, space is
4566 always allocated. */
4568 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4572 fprintf_unfiltered (gdb_stdlog
, "\n");
4575 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4577 /* Return adjusted stack pointer. */
4581 static enum return_value_convention
4582 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4583 struct type
*type
, struct regcache
*regcache
,
4584 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4586 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4588 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4589 || TYPE_CODE (type
) == TYPE_CODE_UNION
4590 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4591 return RETURN_VALUE_STRUCT_CONVENTION
;
4592 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4594 /* A floating-point value. It fits in the least significant
4597 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4598 mips_xfer_register (gdbarch
, regcache
,
4599 (gdbarch_num_regs (gdbarch
)
4600 + mips_regnum (gdbarch
)->fp0
),
4602 gdbarch_byte_order (gdbarch
),
4603 readbuf
, writebuf
, 0);
4604 return RETURN_VALUE_REGISTER_CONVENTION
;
4608 /* A scalar extract each part but least-significant-byte
4612 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4613 offset
< TYPE_LENGTH (type
);
4614 offset
+= MIPS64_REGSIZE
, regnum
++)
4616 int xfer
= MIPS64_REGSIZE
;
4617 if (offset
+ xfer
> TYPE_LENGTH (type
))
4618 xfer
= TYPE_LENGTH (type
) - offset
;
4620 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4621 offset
, xfer
, regnum
);
4622 mips_xfer_register (gdbarch
, regcache
,
4623 gdbarch_num_regs (gdbarch
) + regnum
,
4624 xfer
, gdbarch_byte_order (gdbarch
),
4625 readbuf
, writebuf
, offset
);
4627 return RETURN_VALUE_REGISTER_CONVENTION
;
4631 /* Floating point register management.
4633 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4634 64bit operations, these early MIPS cpus treat fp register pairs
4635 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4636 registers and offer a compatibility mode that emulates the MIPS2 fp
4637 model. When operating in MIPS2 fp compat mode, later cpu's split
4638 double precision floats into two 32-bit chunks and store them in
4639 consecutive fp regs. To display 64-bit floats stored in this
4640 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4641 Throw in user-configurable endianness and you have a real mess.
4643 The way this works is:
4644 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4645 double-precision value will be split across two logical registers.
4646 The lower-numbered logical register will hold the low-order bits,
4647 regardless of the processor's endianness.
4648 - If we are on a 64-bit processor, and we are looking for a
4649 single-precision value, it will be in the low ordered bits
4650 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4651 save slot in memory.
4652 - If we are in 64-bit mode, everything is straightforward.
4654 Note that this code only deals with "live" registers at the top of the
4655 stack. We will attempt to deal with saved registers later, when
4656 the raw/cooked register interface is in place. (We need a general
4657 interface that can deal with dynamic saved register sizes -- fp
4658 regs could be 32 bits wide in one frame and 64 on the frame above
4661 /* Copy a 32-bit single-precision value from the current frame
4662 into rare_buffer. */
4665 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4666 gdb_byte
*rare_buffer
)
4668 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4669 int raw_size
= register_size (gdbarch
, regno
);
4670 gdb_byte
*raw_buffer
= alloca (raw_size
);
4672 if (!frame_register_read (frame
, regno
, raw_buffer
))
4673 error (_("can't read register %d (%s)"),
4674 regno
, gdbarch_register_name (gdbarch
, regno
));
4677 /* We have a 64-bit value for this register. Find the low-order
4681 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4686 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4690 memcpy (rare_buffer
, raw_buffer
, 4);
4694 /* Copy a 64-bit double-precision value from the current frame into
4695 rare_buffer. This may include getting half of it from the next
4699 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4700 gdb_byte
*rare_buffer
)
4702 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4703 int raw_size
= register_size (gdbarch
, regno
);
4705 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4707 /* We have a 64-bit value for this register, and we should use
4709 if (!frame_register_read (frame
, regno
, rare_buffer
))
4710 error (_("can't read register %d (%s)"),
4711 regno
, gdbarch_register_name (gdbarch
, regno
));
4715 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4717 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4718 internal_error (__FILE__
, __LINE__
,
4719 _("mips_read_fp_register_double: bad access to "
4720 "odd-numbered FP register"));
4722 /* mips_read_fp_register_single will find the correct 32 bits from
4724 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4726 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4727 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4731 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4732 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4738 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4740 { /* Do values for FP (float) regs. */
4741 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4742 gdb_byte
*raw_buffer
;
4743 double doub
, flt1
; /* Doubles extracted from raw hex data. */
4746 raw_buffer
= alloca (2 * register_size (gdbarch
,
4747 mips_regnum (gdbarch
)->fp0
));
4749 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4750 fprintf_filtered (file
, "%*s",
4751 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4754 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4756 struct value_print_options opts
;
4758 /* 4-byte registers: Print hex and floating. Also print even
4759 numbered registers as doubles. */
4760 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4761 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4764 get_formatted_print_options (&opts
, 'x');
4765 print_scalar_formatted (raw_buffer
,
4766 builtin_type (gdbarch
)->builtin_uint32
,
4769 fprintf_filtered (file
, " flt: ");
4771 fprintf_filtered (file
, " <invalid float> ");
4773 fprintf_filtered (file
, "%-17.9g", flt1
);
4775 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4777 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4778 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4781 fprintf_filtered (file
, " dbl: ");
4783 fprintf_filtered (file
, "<invalid double>");
4785 fprintf_filtered (file
, "%-24.17g", doub
);
4790 struct value_print_options opts
;
4792 /* Eight byte registers: print each one as hex, float and double. */
4793 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4794 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4797 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4798 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4801 get_formatted_print_options (&opts
, 'x');
4802 print_scalar_formatted (raw_buffer
,
4803 builtin_type (gdbarch
)->builtin_uint64
,
4806 fprintf_filtered (file
, " flt: ");
4808 fprintf_filtered (file
, "<invalid float>");
4810 fprintf_filtered (file
, "%-17.9g", flt1
);
4812 fprintf_filtered (file
, " dbl: ");
4814 fprintf_filtered (file
, "<invalid double>");
4816 fprintf_filtered (file
, "%-24.17g", doub
);
4821 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4824 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4826 struct value_print_options opts
;
4829 if (mips_float_register_p (gdbarch
, regnum
))
4831 mips_print_fp_register (file
, frame
, regnum
);
4835 val
= get_frame_register_value (frame
, regnum
);
4836 if (value_optimized_out (val
))
4838 fprintf_filtered (file
, "%s: [Invalid]",
4839 gdbarch_register_name (gdbarch
, regnum
));
4843 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4845 /* The problem with printing numeric register names (r26, etc.) is that
4846 the user can't use them on input. Probably the best solution is to
4847 fix it so that either the numeric or the funky (a2, etc.) names
4848 are accepted on input. */
4849 if (regnum
< MIPS_NUMREGS
)
4850 fprintf_filtered (file
, "(r%d): ", regnum
);
4852 fprintf_filtered (file
, ": ");
4854 get_formatted_print_options (&opts
, 'x');
4855 val_print_scalar_formatted (value_type (val
),
4856 value_contents_for_printing (val
),
4857 value_embedded_offset (val
),
4862 /* Replacement for generic do_registers_info.
4863 Print regs in pretty columns. */
4866 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4869 fprintf_filtered (file
, " ");
4870 mips_print_fp_register (file
, frame
, regnum
);
4871 fprintf_filtered (file
, "\n");
4876 /* Print a row's worth of GP (int) registers, with name labels above. */
4879 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4882 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4883 /* Do values for GP (int) regs. */
4884 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4885 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
4890 /* For GP registers, we print a separate row of names above the vals. */
4891 for (col
= 0, regnum
= start_regnum
;
4892 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4893 + gdbarch_num_pseudo_regs (gdbarch
);
4896 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4897 continue; /* unused register */
4898 if (mips_float_register_p (gdbarch
, regnum
))
4899 break; /* End the row: reached FP register. */
4900 /* Large registers are handled separately. */
4901 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4904 break; /* End the row before this register. */
4906 /* Print this register on a row by itself. */
4907 mips_print_register (file
, frame
, regnum
);
4908 fprintf_filtered (file
, "\n");
4912 fprintf_filtered (file
, " ");
4913 fprintf_filtered (file
,
4914 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4915 gdbarch_register_name (gdbarch
, regnum
));
4922 /* Print the R0 to R31 names. */
4923 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4924 fprintf_filtered (file
, "\n R%-4d",
4925 start_regnum
% gdbarch_num_regs (gdbarch
));
4927 fprintf_filtered (file
, "\n ");
4929 /* Now print the values in hex, 4 or 8 to the row. */
4930 for (col
= 0, regnum
= start_regnum
;
4931 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4932 + gdbarch_num_pseudo_regs (gdbarch
);
4935 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4936 continue; /* unused register */
4937 if (mips_float_register_p (gdbarch
, regnum
))
4938 break; /* End row: reached FP register. */
4939 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4940 break; /* End row: large register. */
4942 /* OK: get the data in raw format. */
4943 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4944 error (_("can't read register %d (%s)"),
4945 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4946 /* pad small registers */
4948 byte
< (mips_abi_regsize (gdbarch
)
4949 - register_size (gdbarch
, regnum
)); byte
++)
4950 printf_filtered (" ");
4951 /* Now print the register value in hex, endian order. */
4952 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4954 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4955 byte
< register_size (gdbarch
, regnum
); byte
++)
4956 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4958 for (byte
= register_size (gdbarch
, regnum
) - 1;
4960 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4961 fprintf_filtered (file
, " ");
4964 if (col
> 0) /* ie. if we actually printed anything... */
4965 fprintf_filtered (file
, "\n");
4970 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
4973 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4974 struct frame_info
*frame
, int regnum
, int all
)
4976 if (regnum
!= -1) /* Do one specified register. */
4978 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4979 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4980 error (_("Not a valid register for the current processor type"));
4982 mips_print_register (file
, frame
, regnum
);
4983 fprintf_filtered (file
, "\n");
4986 /* Do all (or most) registers. */
4988 regnum
= gdbarch_num_regs (gdbarch
);
4989 while (regnum
< gdbarch_num_regs (gdbarch
)
4990 + gdbarch_num_pseudo_regs (gdbarch
))
4992 if (mips_float_register_p (gdbarch
, regnum
))
4994 if (all
) /* True for "INFO ALL-REGISTERS" command. */
4995 regnum
= print_fp_register_row (file
, frame
, regnum
);
4997 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
5000 regnum
= print_gp_register_row (file
, frame
, regnum
);
5005 /* Is this a branch with a delay slot? */
5008 is_delayed (unsigned long insn
)
5011 for (i
= 0; i
< NUMOPCODES
; ++i
)
5012 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
5013 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
5015 return (i
< NUMOPCODES
5016 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
5017 | INSN_COND_BRANCH_DELAY
5018 | INSN_COND_BRANCH_LIKELY
)));
5022 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
5023 struct frame_info
*frame
)
5025 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5026 CORE_ADDR pc
= get_frame_pc (frame
);
5027 gdb_byte buf
[MIPS_INSN32_SIZE
];
5029 /* There is no branch delay slot on MIPS16. */
5030 if (mips_pc_is_mips16 (pc
))
5033 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
5036 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
5037 /* If error reading memory, guess that it is not a delayed
5040 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
5043 /* To skip prologues, I use this predicate. Returns either PC itself
5044 if the code at PC does not look like a function prologue; otherwise
5045 returns an address that (if we're lucky) follows the prologue. If
5046 LENIENT, then we must skip everything which is involved in setting
5047 up the frame (it's OK to skip more, just so long as we don't skip
5048 anything which might clobber the registers which are being saved.
5049 We must skip more in the case where part of the prologue is in the
5050 delay slot of a non-prologue instruction). */
5053 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5056 CORE_ADDR func_addr
;
5058 /* See if we can determine the end of the prologue via the symbol table.
5059 If so, then return either PC, or the PC after the prologue, whichever
5061 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
5063 CORE_ADDR post_prologue_pc
5064 = skip_prologue_using_sal (gdbarch
, func_addr
);
5065 if (post_prologue_pc
!= 0)
5066 return max (pc
, post_prologue_pc
);
5069 /* Can't determine prologue from the symbol table, need to examine
5072 /* Find an upper limit on the function prologue using the debug
5073 information. If the debug information could not be used to provide
5074 that bound, then use an arbitrary large number as the upper bound. */
5075 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
5077 limit_pc
= pc
+ 100; /* Magic. */
5079 if (mips_pc_is_mips16 (pc
))
5080 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
5082 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
5085 /* Check whether the PC is in a function epilogue (32-bit version).
5086 This is a helper function for mips_in_function_epilogue_p. */
5088 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5090 CORE_ADDR func_addr
= 0, func_end
= 0;
5092 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5094 /* The MIPS epilogue is max. 12 bytes long. */
5095 CORE_ADDR addr
= func_end
- 12;
5097 if (addr
< func_addr
+ 4)
5098 addr
= func_addr
+ 4;
5102 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
5104 unsigned long high_word
;
5107 inst
= mips_fetch_instruction (gdbarch
, pc
);
5108 high_word
= (inst
>> 16) & 0xffff;
5110 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
5111 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
5112 && inst
!= 0x03e00008 /* jr $ra */
5113 && inst
!= 0x00000000) /* nop */
5123 /* Check whether the PC is in a function epilogue (16-bit version).
5124 This is a helper function for mips_in_function_epilogue_p. */
5126 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5128 CORE_ADDR func_addr
= 0, func_end
= 0;
5130 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5132 /* The MIPS epilogue is max. 12 bytes long. */
5133 CORE_ADDR addr
= func_end
- 12;
5135 if (addr
< func_addr
+ 4)
5136 addr
= func_addr
+ 4;
5140 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
5142 unsigned short inst
;
5144 inst
= mips_fetch_instruction (gdbarch
, pc
);
5146 if ((inst
& 0xf800) == 0xf000) /* extend */
5149 if (inst
!= 0x6300 /* addiu $sp,offset */
5150 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
5151 && inst
!= 0xe820 /* jr $ra */
5152 && inst
!= 0xe8a0 /* jrc $ra */
5153 && inst
!= 0x6500) /* nop */
5163 /* The epilogue is defined here as the area at the end of a function,
5164 after an instruction which destroys the function's stack frame. */
5166 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5168 if (mips_pc_is_mips16 (pc
))
5169 return mips16_in_function_epilogue_p (gdbarch
, pc
);
5171 return mips32_in_function_epilogue_p (gdbarch
, pc
);
5174 /* Root of all "set mips "/"show mips " commands. This will eventually be
5175 used for all MIPS-specific commands. */
5178 show_mips_command (char *args
, int from_tty
)
5180 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5184 set_mips_command (char *args
, int from_tty
)
5187 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5188 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5191 /* Commands to show/set the MIPS FPU type. */
5194 show_mipsfpu_command (char *args
, int from_tty
)
5198 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5201 ("The MIPS floating-point coprocessor is unknown "
5202 "because the current architecture is not MIPS.\n");
5206 switch (MIPS_FPU_TYPE (target_gdbarch
))
5208 case MIPS_FPU_SINGLE
:
5209 fpu
= "single-precision";
5211 case MIPS_FPU_DOUBLE
:
5212 fpu
= "double-precision";
5215 fpu
= "absent (none)";
5218 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5220 if (mips_fpu_type_auto
)
5221 printf_unfiltered ("The MIPS floating-point coprocessor "
5222 "is set automatically (currently %s)\n",
5226 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5231 set_mipsfpu_command (char *args
, int from_tty
)
5233 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
5234 "\"single\",\"none\" or \"auto\".\n");
5235 show_mipsfpu_command (args
, from_tty
);
5239 set_mipsfpu_single_command (char *args
, int from_tty
)
5241 struct gdbarch_info info
;
5242 gdbarch_info_init (&info
);
5243 mips_fpu_type
= MIPS_FPU_SINGLE
;
5244 mips_fpu_type_auto
= 0;
5245 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5246 instead of relying on globals. Doing that would let generic code
5247 handle the search for this specific architecture. */
5248 if (!gdbarch_update_p (info
))
5249 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5253 set_mipsfpu_double_command (char *args
, int from_tty
)
5255 struct gdbarch_info info
;
5256 gdbarch_info_init (&info
);
5257 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5258 mips_fpu_type_auto
= 0;
5259 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5260 instead of relying on globals. Doing that would let generic code
5261 handle the search for this specific architecture. */
5262 if (!gdbarch_update_p (info
))
5263 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5267 set_mipsfpu_none_command (char *args
, int from_tty
)
5269 struct gdbarch_info info
;
5270 gdbarch_info_init (&info
);
5271 mips_fpu_type
= MIPS_FPU_NONE
;
5272 mips_fpu_type_auto
= 0;
5273 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5274 instead of relying on globals. Doing that would let generic code
5275 handle the search for this specific architecture. */
5276 if (!gdbarch_update_p (info
))
5277 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5281 set_mipsfpu_auto_command (char *args
, int from_tty
)
5283 mips_fpu_type_auto
= 1;
5286 /* Attempt to identify the particular processor model by reading the
5287 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5288 the relevant processor still exists (it dates back to '94) and
5289 secondly this is not the way to do this. The processor type should
5290 be set by forcing an architecture change. */
5293 deprecated_mips_set_processor_regs_hack (void)
5295 struct regcache
*regcache
= get_current_regcache ();
5296 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5297 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5300 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5301 if ((prid
& ~0xf) == 0x700)
5302 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5305 /* Just like reinit_frame_cache, but with the right arguments to be
5306 callable as an sfunc. */
5309 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5310 struct cmd_list_element
*c
)
5312 reinit_frame_cache ();
5316 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5318 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5319 disassembler needs to be able to locally determine the ISA, and
5320 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5322 if (mips_pc_is_mips16 (memaddr
))
5323 info
->mach
= bfd_mach_mips16
;
5325 /* Round down the instruction address to the appropriate boundary. */
5326 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5328 /* Set the disassembler options. */
5329 if (!info
->disassembler_options
)
5330 /* This string is not recognized explicitly by the disassembler,
5331 but it tells the disassembler to not try to guess the ABI from
5332 the bfd elf headers, such that, if the user overrides the ABI
5333 of a program linked as NewABI, the disassembly will follow the
5334 register naming conventions specified by the user. */
5335 info
->disassembler_options
= "gpr-names=32";
5337 /* Call the appropriate disassembler based on the target endian-ness. */
5338 if (info
->endian
== BFD_ENDIAN_BIG
)
5339 return print_insn_big_mips (memaddr
, info
);
5341 return print_insn_little_mips (memaddr
, info
);
5345 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5347 /* Set up the disassembler info, so that we get the right
5348 register names from libopcodes. */
5349 info
->disassembler_options
= "gpr-names=n32";
5350 info
->flavour
= bfd_target_elf_flavour
;
5352 return gdb_print_insn_mips (memaddr
, info
);
5356 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5358 /* Set up the disassembler info, so that we get the right
5359 register names from libopcodes. */
5360 info
->disassembler_options
= "gpr-names=64";
5361 info
->flavour
= bfd_target_elf_flavour
;
5363 return gdb_print_insn_mips (memaddr
, info
);
5366 /* This function implements gdbarch_breakpoint_from_pc. It uses the
5367 program counter value to determine whether a 16- or 32-bit breakpoint
5368 should be used. It returns a pointer to a string of bytes that encode a
5369 breakpoint instruction, stores the length of the string to *lenptr, and
5370 adjusts pc (if necessary) to point to the actual memory location where
5371 the breakpoint should be inserted. */
5373 static const gdb_byte
*
5374 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
5375 CORE_ADDR
*pcptr
, int *lenptr
)
5377 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5379 if (mips_pc_is_mips16 (*pcptr
))
5381 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5382 *pcptr
= unmake_mips16_addr (*pcptr
);
5383 *lenptr
= sizeof (mips16_big_breakpoint
);
5384 return mips16_big_breakpoint
;
5388 /* The IDT board uses an unusual breakpoint value, and
5389 sometimes gets confused when it sees the usual MIPS
5390 breakpoint instruction. */
5391 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5392 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5393 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5394 /* Likewise, IRIX appears to expect a different breakpoint,
5395 although this is not apparent until you try to use pthreads. */
5396 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5398 *lenptr
= sizeof (big_breakpoint
);
5400 if (strcmp (target_shortname
, "mips") == 0)
5401 return idt_big_breakpoint
;
5402 else if (strcmp (target_shortname
, "ddb") == 0
5403 || strcmp (target_shortname
, "pmon") == 0
5404 || strcmp (target_shortname
, "lsi") == 0)
5405 return pmon_big_breakpoint
;
5406 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5407 return irix_big_breakpoint
;
5409 return big_breakpoint
;
5414 if (mips_pc_is_mips16 (*pcptr
))
5416 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5417 *pcptr
= unmake_mips16_addr (*pcptr
);
5418 *lenptr
= sizeof (mips16_little_breakpoint
);
5419 return mips16_little_breakpoint
;
5423 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5424 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5425 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5427 *lenptr
= sizeof (little_breakpoint
);
5429 if (strcmp (target_shortname
, "mips") == 0)
5430 return idt_little_breakpoint
;
5431 else if (strcmp (target_shortname
, "ddb") == 0
5432 || strcmp (target_shortname
, "pmon") == 0
5433 || strcmp (target_shortname
, "lsi") == 0)
5434 return pmon_little_breakpoint
;
5436 return little_breakpoint
;
5441 /* Return non-zero if the ADDR instruction has a branch delay slot
5442 (i.e. it is a jump or branch instruction). This function is based
5443 on mips32_next_pc. */
5446 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
5448 gdb_byte buf
[MIPS_INSN32_SIZE
];
5455 status
= target_read_memory (addr
, buf
, MIPS_INSN32_SIZE
);
5459 inst
= mips_fetch_instruction (gdbarch
, addr
);
5460 op
= itype_op (inst
);
5461 if ((inst
& 0xe0000000) != 0)
5463 rs
= itype_rs (inst
);
5464 rt
= itype_rt (inst
);
5465 return (op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
5466 || op
== 29 /* JALX: bits 011101 */
5469 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
5470 || (rs
== 9 && (rt
& 0x2) == 0)
5471 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
5472 || (rs
== 10 && (rt
& 0x2) == 0))));
5473 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
5476 switch (op
& 0x07) /* extract bits 28,27,26 */
5478 case 0: /* SPECIAL */
5479 op
= rtype_funct (inst
);
5480 return (op
== 8 /* JR */
5481 || op
== 9); /* JALR */
5482 break; /* end SPECIAL */
5483 case 1: /* REGIMM */
5484 rs
= itype_rs (inst
);
5485 rt
= itype_rt (inst
); /* branch condition */
5486 return ((rt
& 0xc) == 0
5487 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
5488 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
5489 || ((rt
& 0x1e) == 0x1c && rs
== 0));
5490 /* BPOSGE32, BPOSGE64: bits 1110x */
5491 break; /* end REGIMM */
5492 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
5498 /* Return non-zero if the ADDR instruction, which must be a 32-bit
5499 instruction if MUSTBE32 is set or can be any instruction otherwise,
5500 has a branch delay slot (i.e. it is a non-compact jump instruction). */
5503 mips16_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
5506 gdb_byte buf
[MIPS_INSN16_SIZE
];
5507 unsigned short inst
;
5510 status
= target_read_memory (addr
, buf
, MIPS_INSN16_SIZE
);
5514 inst
= mips_fetch_instruction (gdbarch
, addr
);
5516 return (inst
& 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
5517 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
5520 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
5521 This assumes KSSEG exists. */
5524 mips_segment_boundary (CORE_ADDR bpaddr
)
5526 CORE_ADDR mask
= CORE_ADDR_MAX
;
5529 if (sizeof (CORE_ADDR
) == 8)
5530 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
5531 a compiler warning produced where CORE_ADDR is a 32-bit type even
5532 though in that case this is dead code). */
5533 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
5536 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
5537 segsize
= 29; /* 32-bit compatibility segment */
5539 segsize
= 62; /* xkseg */
5541 case 2: /* xkphys */
5544 default: /* xksseg (1), xkuseg/kuseg (0) */
5548 else if (bpaddr
& 0x80000000) /* kernel segment */
5551 segsize
= 31; /* user segment */
5553 return bpaddr
& mask
;
5556 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
5557 it backwards if necessary. Return the address of the new location. */
5560 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5562 CORE_ADDR prev_addr
, next_addr
;
5564 CORE_ADDR func_addr
;
5566 /* If a breakpoint is set on the instruction in a branch delay slot,
5567 GDB gets confused. When the breakpoint is hit, the PC isn't on
5568 the instruction in the branch delay slot, the PC will point to
5569 the branch instruction. Since the PC doesn't match any known
5570 breakpoints, GDB reports a trap exception.
5572 There are two possible fixes for this problem.
5574 1) When the breakpoint gets hit, see if the BD bit is set in the
5575 Cause register (which indicates the last exception occurred in a
5576 branch delay slot). If the BD bit is set, fix the PC to point to
5577 the instruction in the branch delay slot.
5579 2) When the user sets the breakpoint, don't allow him to set the
5580 breakpoint on the instruction in the branch delay slot. Instead
5581 move the breakpoint to the branch instruction (which will have
5584 The problem with the first solution is that if the user then
5585 single-steps the processor, the branch instruction will get
5586 skipped (since GDB thinks the PC is on the instruction in the
5589 So, we'll use the second solution. To do this we need to know if
5590 the instruction we're trying to set the breakpoint on is in the
5591 branch delay slot. */
5593 boundary
= mips_segment_boundary (bpaddr
);
5595 /* Make sure we don't scan back before the beginning of the current
5596 function, since we may fetch constant data or insns that look like
5597 a jump. Of course we might do that anyway if the compiler has
5598 moved constants inline. :-( */
5599 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
5600 && func_addr
> boundary
&& func_addr
<= bpaddr
)
5601 boundary
= func_addr
;
5603 if (!mips_pc_is_mips16 (bpaddr
))
5605 if (bpaddr
== boundary
)
5608 /* If the previous instruction has a branch delay slot, we have
5609 to move the breakpoint to the branch instruction. */
5610 prev_addr
= bpaddr
- 4;
5611 if (mips32_instruction_has_delay_slot (gdbarch
, prev_addr
))
5616 struct minimal_symbol
*sym
;
5617 CORE_ADDR addr
, jmpaddr
;
5620 boundary
= unmake_mips16_addr (boundary
);
5622 /* The only MIPS16 instructions with delay slots are JAL, JALX,
5623 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
5624 so try for that first, then try the 2 byte JALR/JR.
5625 FIXME: We have to assume that bpaddr is not the second half
5626 of an extended instruction. */
5630 for (i
= 1; i
< 4; i
++)
5632 if (unmake_mips16_addr (addr
) == boundary
)
5635 if (i
== 1 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 0))
5636 /* Looks like a JR/JALR at [target-1], but it could be
5637 the second word of a previous JAL/JALX, so record it
5638 and check back one more. */
5641 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 1))
5644 /* Looks like a JAL/JALX at [target-2], but it could also
5645 be the second word of a previous JAL/JALX, record it,
5646 and check back one more. */
5649 /* Looks like a JAL/JALX at [target-3], so any previously
5650 recorded JAL/JALX or JR/JALR must be wrong, because:
5653 -2: JAL-ext (can't be JAL/JALX)
5654 -1: bdslot (can't be JR/JALR)
5657 Of course it could be another JAL-ext which looks
5658 like a JAL, but in that case we'd have broken out
5659 of this loop at [target-2]:
5663 -2: bdslot (can't be jmp)
5670 /* Not a jump instruction: if we're at [target-1] this
5671 could be the second word of a JAL/JALX, so continue;
5672 otherwise we're done. */
5685 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
5686 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
5689 mips_is_stub_suffix (const char *suffix
, int zero
)
5694 return zero
&& suffix
[1] == '\0';
5696 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
5701 return suffix
[1] == '\0';
5707 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
5708 call stubs, one of sf, df, sc, or dc. */
5711 mips_is_stub_mode (const char *mode
)
5713 return ((mode
[0] == 's' || mode
[0] == 'd')
5714 && (mode
[1] == 'f' || mode
[1] == 'c'));
5717 /* Code at PC is a compiler-generated stub. Such a stub for a function
5718 bar might have a name like __fn_stub_bar, and might look like this:
5725 followed by (or interspersed with):
5732 addiu $25, $25, %lo(bar)
5735 ($1 may be used in old code; for robustness we accept any register)
5738 lui $28, %hi(_gp_disp)
5739 addiu $28, $28, %lo(_gp_disp)
5742 addiu $25, $25, %lo(bar)
5745 In the case of a __call_stub_bar stub, the sequence to set up
5746 arguments might look like this:
5753 followed by (or interspersed with) one of the jump sequences above.
5755 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
5756 of J or JR, respectively, followed by:
5762 We are at the beginning of the stub here, and scan down and extract
5763 the target address from the jump immediate instruction or, if a jump
5764 register instruction is used, from the register referred. Return
5765 the value of PC calculated or 0 if inconclusive.
5767 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
5770 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
5772 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5773 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5774 int addrreg
= MIPS_ZERO_REGNUM
;
5775 CORE_ADDR start_pc
= pc
;
5776 CORE_ADDR target_pc
= 0;
5783 status
== 0 && target_pc
== 0 && i
< 20;
5784 i
++, pc
+= MIPS_INSN32_SIZE
)
5786 ULONGEST inst
= mips_fetch_instruction (gdbarch
, pc
);
5792 switch (itype_op (inst
))
5794 case 0: /* SPECIAL */
5795 switch (rtype_funct (inst
))
5799 rs
= rtype_rs (inst
);
5800 if (rs
== MIPS_GP_REGNUM
)
5801 target_pc
= gp
; /* Hmm... */
5802 else if (rs
== addrreg
)
5806 case 0x21: /* ADDU */
5807 rt
= rtype_rt (inst
);
5808 rs
= rtype_rs (inst
);
5809 rd
= rtype_rd (inst
);
5810 if (rd
== MIPS_GP_REGNUM
5811 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
5812 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
5820 target_pc
= jtype_target (inst
) << 2;
5821 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
5825 rt
= itype_rt (inst
);
5826 rs
= itype_rs (inst
);
5829 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
5830 if (rt
== MIPS_GP_REGNUM
)
5832 else if (rt
== addrreg
)
5838 rt
= itype_rt (inst
);
5839 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
5840 if (rt
== MIPS_GP_REGNUM
)
5842 else if (rt
!= MIPS_ZERO_REGNUM
)
5850 rt
= itype_rt (inst
);
5851 rs
= itype_rs (inst
);
5852 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
5853 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
5857 memset (buf
, 0, sizeof (buf
));
5858 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
5860 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
5869 /* If PC is in a MIPS16 call or return stub, return the address of the
5870 target PC, which is either the callee or the caller. There are several
5871 cases which must be handled:
5873 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
5874 and the target PC is in $31 ($ra).
5875 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5876 and the target PC is in $2.
5877 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
5878 i.e. before the JALR instruction, this is effectively a call stub
5879 and the target PC is in $2. Otherwise this is effectively
5880 a return stub and the target PC is in $18.
5881 * If the PC is at the start of __call_stub_fp_*, i.e. before the
5882 JAL or JALR instruction, this is effectively a call stub and the
5883 target PC is buried in the instruction stream. Otherwise this
5884 is effectively a return stub and the target PC is in $18.
5885 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
5886 stub and the target PC is buried in the instruction stream.
5888 See the source code for the stubs in gcc/config/mips/mips16.S, or the
5889 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
5893 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5895 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5896 CORE_ADDR start_addr
;
5900 /* Find the starting address and name of the function containing the PC. */
5901 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5904 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
5905 and the target PC is in $31 ($ra). */
5906 prefixlen
= strlen (mips_str_mips16_ret_stub
);
5907 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
5908 && mips_is_stub_mode (name
+ prefixlen
)
5909 && name
[prefixlen
+ 2] == '\0')
5910 return get_frame_register_signed
5911 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
5913 /* If the PC is in __mips16_call_stub_*, this is one of the call
5914 call/return stubs. */
5915 prefixlen
= strlen (mips_str_mips16_call_stub
);
5916 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
5918 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5919 and the target PC is in $2. */
5920 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
5921 return get_frame_register_signed
5922 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
5924 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
5925 i.e. before the JALR instruction, this is effectively a call stub
5926 and the target PC is in $2. Otherwise this is effectively
5927 a return stub and the target PC is in $18. */
5928 else if (mips_is_stub_mode (name
+ prefixlen
)
5929 && name
[prefixlen
+ 2] == '_'
5930 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
5932 if (pc
== start_addr
)
5933 /* This is the 'call' part of a call stub. The return
5934 address is in $2. */
5935 return get_frame_register_signed
5936 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
5938 /* This is the 'return' part of a call stub. The return
5939 address is in $18. */
5940 return get_frame_register_signed
5941 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
5944 return 0; /* Not a stub. */
5947 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
5948 compiler-generated call or call/return stubs. */
5949 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0
5950 || strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
5952 if (pc
== start_addr
)
5953 /* This is the 'call' part of a call stub. Call this helper
5954 to scan through this code for interesting instructions
5955 and determine the final PC. */
5956 return mips_get_mips16_fn_stub_pc (frame
, pc
);
5958 /* This is the 'return' part of a call stub. The return address
5960 return get_frame_register_signed
5961 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
5964 return 0; /* Not a stub. */
5967 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5968 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5971 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
5973 CORE_ADDR start_addr
;
5976 /* Find the starting address of the function containing the PC. */
5977 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5980 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
5981 the start, i.e. after the JALR instruction, this is effectively
5983 prefixlen
= strlen (mips_str_mips16_call_stub
);
5984 if (pc
!= start_addr
5985 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
5986 && mips_is_stub_mode (name
+ prefixlen
)
5987 && name
[prefixlen
+ 2] == '_'
5988 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
5991 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
5992 the JAL or JALR instruction, this is effectively a return stub. */
5993 prefixlen
= strlen (mips_str_call_fp_stub
);
5994 if (pc
!= start_addr
5995 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
5998 /* Consume the .pic. prefix of any PIC stub, this function must return
5999 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
6000 or the call stub path will trigger in handle_inferior_event causing
6002 prefixlen
= strlen (mips_str_pic
);
6003 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
6006 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
6007 prefixlen
= strlen (mips_str_mips16_ret_stub
);
6008 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
6009 && mips_is_stub_mode (name
+ prefixlen
)
6010 && name
[prefixlen
+ 2] == '\0')
6013 return 0; /* Not a stub. */
6016 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
6017 PC of the stub target. The stub just loads $t9 and jumps to it,
6018 so that $t9 has the correct value at function entry. */
6021 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
6023 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6024 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6025 struct minimal_symbol
*msym
;
6027 gdb_byte stub_code
[16];
6028 int32_t stub_words
[4];
6030 /* The stub for foo is named ".pic.foo", and is either two
6031 instructions inserted before foo or a three instruction sequence
6032 which jumps to foo. */
6033 msym
= lookup_minimal_symbol_by_pc (pc
);
6035 || SYMBOL_VALUE_ADDRESS (msym
) != pc
6036 || SYMBOL_LINKAGE_NAME (msym
) == NULL
6037 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
6040 /* A two-instruction header. */
6041 if (MSYMBOL_SIZE (msym
) == 8)
6044 /* A three-instruction (plus delay slot) trampoline. */
6045 if (MSYMBOL_SIZE (msym
) == 16)
6047 if (target_read_memory (pc
, stub_code
, 16) != 0)
6049 for (i
= 0; i
< 4; i
++)
6050 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
6053 /* A stub contains these instructions:
6056 addiu t9, t9, %lo(target)
6059 This works even for N64, since stubs are only generated with
6061 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
6062 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
6063 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
6064 && stub_words
[3] == 0x00000000)
6065 return ((((stub_words
[0] & 0x0000ffff) << 16)
6066 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
6069 /* Not a recognized stub. */
6074 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
6076 CORE_ADDR requested_pc
= pc
;
6077 CORE_ADDR target_pc
;
6084 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
6088 if (is_mips16_addr (pc
))
6089 pc
= unmake_mips16_addr (pc
);
6092 new_pc
= find_solib_trampoline_target (frame
, pc
);
6096 if (is_mips16_addr (pc
))
6097 pc
= unmake_mips16_addr (pc
);
6100 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
6104 if (is_mips16_addr (pc
))
6105 pc
= unmake_mips16_addr (pc
);
6108 while (pc
!= target_pc
);
6110 return pc
!= requested_pc
? pc
: 0;
6113 /* Convert a dbx stab register number (from `r' declaration) to a GDB
6114 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
6117 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
6120 if (num
>= 0 && num
< 32)
6122 else if (num
>= 38 && num
< 70)
6123 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
6125 regnum
= mips_regnum (gdbarch
)->hi
;
6127 regnum
= mips_regnum (gdbarch
)->lo
;
6128 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
6129 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
6131 /* This will hopefully (eventually) provoke a warning. Should
6132 we be calling complaint() here? */
6133 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
6134 return gdbarch_num_regs (gdbarch
) + regnum
;
6138 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
6139 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
6142 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
6145 if (num
>= 0 && num
< 32)
6147 else if (num
>= 32 && num
< 64)
6148 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
6150 regnum
= mips_regnum (gdbarch
)->hi
;
6152 regnum
= mips_regnum (gdbarch
)->lo
;
6153 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
6154 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
6156 /* This will hopefully (eventually) provoke a warning. Should we
6157 be calling complaint() here? */
6158 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
6159 return gdbarch_num_regs (gdbarch
) + regnum
;
6163 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
6165 /* Only makes sense to supply raw registers. */
6166 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
6167 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
6168 decide if it is valid. Should instead define a standard sim/gdb
6169 register numbering scheme. */
6170 if (gdbarch_register_name (gdbarch
,
6171 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
6172 && gdbarch_register_name (gdbarch
,
6173 gdbarch_num_regs (gdbarch
)
6174 + regnum
)[0] != '\0')
6177 return LEGACY_SIM_REGNO_IGNORE
;
6181 /* Convert an integer into an address. Extracting the value signed
6182 guarantees a correctly sign extended address. */
6185 mips_integer_to_address (struct gdbarch
*gdbarch
,
6186 struct type
*type
, const gdb_byte
*buf
)
6188 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6189 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
6192 /* Dummy virtual frame pointer method. This is no more or less accurate
6193 than most other architectures; we just need to be explicit about it,
6194 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
6195 an assertion failure. */
6198 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
6199 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
6201 *reg
= MIPS_SP_REGNUM
;
6206 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
6208 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
6209 const char *name
= bfd_get_section_name (abfd
, sect
);
6211 if (*abip
!= MIPS_ABI_UNKNOWN
)
6214 if (strncmp (name
, ".mdebug.", 8) != 0)
6217 if (strcmp (name
, ".mdebug.abi32") == 0)
6218 *abip
= MIPS_ABI_O32
;
6219 else if (strcmp (name
, ".mdebug.abiN32") == 0)
6220 *abip
= MIPS_ABI_N32
;
6221 else if (strcmp (name
, ".mdebug.abi64") == 0)
6222 *abip
= MIPS_ABI_N64
;
6223 else if (strcmp (name
, ".mdebug.abiO64") == 0)
6224 *abip
= MIPS_ABI_O64
;
6225 else if (strcmp (name
, ".mdebug.eabi32") == 0)
6226 *abip
= MIPS_ABI_EABI32
;
6227 else if (strcmp (name
, ".mdebug.eabi64") == 0)
6228 *abip
= MIPS_ABI_EABI64
;
6230 warning (_("unsupported ABI %s."), name
+ 8);
6234 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
6236 int *lbp
= (int *) obj
;
6237 const char *name
= bfd_get_section_name (abfd
, sect
);
6239 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
6241 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
6243 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
6244 warning (_("unrecognized .gcc_compiled_longXX"));
6247 static enum mips_abi
6248 global_mips_abi (void)
6252 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
6253 if (mips_abi_strings
[i
] == mips_abi_string
)
6254 return (enum mips_abi
) i
;
6256 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
6260 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
6262 /* If the size matches the set of 32-bit or 64-bit integer registers,
6263 assume that's what we've got. */
6264 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
6265 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
6267 /* If the size matches the full set of registers GDB traditionally
6268 knows about, including floating point, for either 32-bit or
6269 64-bit, assume that's what we've got. */
6270 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
6271 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
6273 /* Otherwise we don't have a useful guess. */
6276 static struct value
*
6277 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
6279 const int *reg_p
= baton
;
6280 return value_of_register (*reg_p
, frame
);
6283 static struct gdbarch
*
6284 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6286 struct gdbarch
*gdbarch
;
6287 struct gdbarch_tdep
*tdep
;
6289 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
6291 enum mips_fpu_type fpu_type
;
6292 struct tdesc_arch_data
*tdesc_data
= NULL
;
6293 int elf_fpu_type
= 0;
6294 const char **reg_names
;
6295 struct mips_regnum mips_regnum
, *regnum
;
6299 /* Fill in the OS dependent register numbers and names. */
6300 if (info
.osabi
== GDB_OSABI_IRIX
)
6302 mips_regnum
.fp0
= 32;
6303 mips_regnum
.pc
= 64;
6304 mips_regnum
.cause
= 65;
6305 mips_regnum
.badvaddr
= 66;
6306 mips_regnum
.hi
= 67;
6307 mips_regnum
.lo
= 68;
6308 mips_regnum
.fp_control_status
= 69;
6309 mips_regnum
.fp_implementation_revision
= 70;
6310 mips_regnum
.dspacc
= dspacc
= -1;
6311 mips_regnum
.dspctl
= dspctl
= -1;
6313 reg_names
= mips_irix_reg_names
;
6315 else if (info
.osabi
== GDB_OSABI_LINUX
)
6317 mips_regnum
.fp0
= 38;
6318 mips_regnum
.pc
= 37;
6319 mips_regnum
.cause
= 36;
6320 mips_regnum
.badvaddr
= 35;
6321 mips_regnum
.hi
= 34;
6322 mips_regnum
.lo
= 33;
6323 mips_regnum
.fp_control_status
= 70;
6324 mips_regnum
.fp_implementation_revision
= 71;
6325 mips_regnum
.dspacc
= -1;
6326 mips_regnum
.dspctl
= -1;
6330 reg_names
= mips_linux_reg_names
;
6334 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
6335 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
6336 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6337 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
6338 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
6339 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
6340 mips_regnum
.fp_control_status
= 70;
6341 mips_regnum
.fp_implementation_revision
= 71;
6342 mips_regnum
.dspacc
= dspacc
= -1;
6343 mips_regnum
.dspctl
= dspctl
= -1;
6344 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
6345 if (info
.bfd_arch_info
!= NULL
6346 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6347 reg_names
= mips_tx39_reg_names
;
6349 reg_names
= mips_generic_reg_names
;
6352 /* Check any target description for validity. */
6353 if (tdesc_has_registers (info
.target_desc
))
6355 static const char *const mips_gprs
[] = {
6356 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6357 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6358 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6359 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6361 static const char *const mips_fprs
[] = {
6362 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6363 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6364 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6365 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
6368 const struct tdesc_feature
*feature
;
6371 feature
= tdesc_find_feature (info
.target_desc
,
6372 "org.gnu.gdb.mips.cpu");
6373 if (feature
== NULL
)
6376 tdesc_data
= tdesc_data_alloc ();
6379 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
6380 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6384 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6385 mips_regnum
.lo
, "lo");
6386 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6387 mips_regnum
.hi
, "hi");
6388 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6389 mips_regnum
.pc
, "pc");
6393 tdesc_data_cleanup (tdesc_data
);
6397 feature
= tdesc_find_feature (info
.target_desc
,
6398 "org.gnu.gdb.mips.cp0");
6399 if (feature
== NULL
)
6401 tdesc_data_cleanup (tdesc_data
);
6406 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6407 mips_regnum
.badvaddr
, "badvaddr");
6408 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6409 MIPS_PS_REGNUM
, "status");
6410 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6411 mips_regnum
.cause
, "cause");
6415 tdesc_data_cleanup (tdesc_data
);
6419 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
6420 backend is not prepared for that, though. */
6421 feature
= tdesc_find_feature (info
.target_desc
,
6422 "org.gnu.gdb.mips.fpu");
6423 if (feature
== NULL
)
6425 tdesc_data_cleanup (tdesc_data
);
6430 for (i
= 0; i
< 32; i
++)
6431 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6432 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
6434 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6435 mips_regnum
.fp_control_status
,
6438 &= tdesc_numbered_register (feature
, tdesc_data
,
6439 mips_regnum
.fp_implementation_revision
,
6444 tdesc_data_cleanup (tdesc_data
);
6450 feature
= tdesc_find_feature (info
.target_desc
,
6451 "org.gnu.gdb.mips.dsp");
6452 /* The DSP registers are optional; it's OK if they are absent. */
6453 if (feature
!= NULL
)
6457 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6458 dspacc
+ i
++, "hi1");
6459 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6460 dspacc
+ i
++, "lo1");
6461 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6462 dspacc
+ i
++, "hi2");
6463 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6464 dspacc
+ i
++, "lo2");
6465 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6466 dspacc
+ i
++, "hi3");
6467 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6468 dspacc
+ i
++, "lo3");
6470 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6475 tdesc_data_cleanup (tdesc_data
);
6479 mips_regnum
.dspacc
= dspacc
;
6480 mips_regnum
.dspctl
= dspctl
;
6484 /* It would be nice to detect an attempt to use a 64-bit ABI
6485 when only 32-bit registers are provided. */
6489 /* First of all, extract the elf_flags, if available. */
6490 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6491 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6492 else if (arches
!= NULL
)
6493 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
6497 fprintf_unfiltered (gdb_stdlog
,
6498 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
6500 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
6501 switch ((elf_flags
& EF_MIPS_ABI
))
6503 case E_MIPS_ABI_O32
:
6504 found_abi
= MIPS_ABI_O32
;
6506 case E_MIPS_ABI_O64
:
6507 found_abi
= MIPS_ABI_O64
;
6509 case E_MIPS_ABI_EABI32
:
6510 found_abi
= MIPS_ABI_EABI32
;
6512 case E_MIPS_ABI_EABI64
:
6513 found_abi
= MIPS_ABI_EABI64
;
6516 if ((elf_flags
& EF_MIPS_ABI2
))
6517 found_abi
= MIPS_ABI_N32
;
6519 found_abi
= MIPS_ABI_UNKNOWN
;
6523 /* GCC creates a pseudo-section whose name describes the ABI. */
6524 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
6525 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6527 /* If we have no useful BFD information, use the ABI from the last
6528 MIPS architecture (if there is one). */
6529 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6530 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6532 /* Try the architecture for any hint of the correct ABI. */
6533 if (found_abi
== MIPS_ABI_UNKNOWN
6534 && info
.bfd_arch_info
!= NULL
6535 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6537 switch (info
.bfd_arch_info
->mach
)
6539 case bfd_mach_mips3900
:
6540 found_abi
= MIPS_ABI_EABI32
;
6542 case bfd_mach_mips4100
:
6543 case bfd_mach_mips5000
:
6544 found_abi
= MIPS_ABI_EABI64
;
6546 case bfd_mach_mips8000
:
6547 case bfd_mach_mips10000
:
6548 /* On Irix, ELF64 executables use the N64 ABI. The
6549 pseudo-sections which describe the ABI aren't present
6550 on IRIX. (Even for executables created by gcc.) */
6551 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6552 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6553 found_abi
= MIPS_ABI_N64
;
6555 found_abi
= MIPS_ABI_N32
;
6560 /* Default 64-bit objects to N64 instead of O32. */
6561 if (found_abi
== MIPS_ABI_UNKNOWN
6562 && info
.abfd
!= NULL
6563 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6564 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6565 found_abi
= MIPS_ABI_N64
;
6568 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6571 /* What has the user specified from the command line? */
6572 wanted_abi
= global_mips_abi ();
6574 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6577 /* Now that we have found what the ABI for this binary would be,
6578 check whether the user is overriding it. */
6579 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6580 mips_abi
= wanted_abi
;
6581 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6582 mips_abi
= found_abi
;
6584 mips_abi
= MIPS_ABI_O32
;
6586 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6589 /* Also used when doing an architecture lookup. */
6591 fprintf_unfiltered (gdb_stdlog
,
6592 "mips_gdbarch_init: "
6593 "mips64_transfers_32bit_regs_p = %d\n",
6594 mips64_transfers_32bit_regs_p
);
6596 /* Determine the MIPS FPU type. */
6599 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6600 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6601 Tag_GNU_MIPS_ABI_FP
);
6602 #endif /* HAVE_ELF */
6604 if (!mips_fpu_type_auto
)
6605 fpu_type
= mips_fpu_type
;
6606 else if (elf_fpu_type
!= 0)
6608 switch (elf_fpu_type
)
6611 fpu_type
= MIPS_FPU_DOUBLE
;
6614 fpu_type
= MIPS_FPU_SINGLE
;
6618 /* Soft float or unknown. */
6619 fpu_type
= MIPS_FPU_NONE
;
6623 else if (info
.bfd_arch_info
!= NULL
6624 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6625 switch (info
.bfd_arch_info
->mach
)
6627 case bfd_mach_mips3900
:
6628 case bfd_mach_mips4100
:
6629 case bfd_mach_mips4111
:
6630 case bfd_mach_mips4120
:
6631 fpu_type
= MIPS_FPU_NONE
;
6633 case bfd_mach_mips4650
:
6634 fpu_type
= MIPS_FPU_SINGLE
;
6637 fpu_type
= MIPS_FPU_DOUBLE
;
6640 else if (arches
!= NULL
)
6641 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6643 fpu_type
= MIPS_FPU_DOUBLE
;
6645 fprintf_unfiltered (gdb_stdlog
,
6646 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6648 /* Check for blatant incompatibilities. */
6650 /* If we have only 32-bit registers, then we can't debug a 64-bit
6652 if (info
.target_desc
6653 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
6654 && mips_abi
!= MIPS_ABI_EABI32
6655 && mips_abi
!= MIPS_ABI_O32
)
6657 if (tdesc_data
!= NULL
)
6658 tdesc_data_cleanup (tdesc_data
);
6662 /* Try to find a pre-existing architecture. */
6663 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6665 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6667 /* MIPS needs to be pedantic about which ABI the object is
6669 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6671 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6673 /* Need to be pedantic about which register virtual size is
6675 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6676 != mips64_transfers_32bit_regs_p
)
6678 /* Be pedantic about which FPU is selected. */
6679 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6682 if (tdesc_data
!= NULL
)
6683 tdesc_data_cleanup (tdesc_data
);
6684 return arches
->gdbarch
;
6687 /* Need a new architecture. Fill in a target specific vector. */
6688 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6689 gdbarch
= gdbarch_alloc (&info
, tdep
);
6690 tdep
->elf_flags
= elf_flags
;
6691 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6692 tdep
->found_abi
= found_abi
;
6693 tdep
->mips_abi
= mips_abi
;
6694 tdep
->mips_fpu_type
= fpu_type
;
6695 tdep
->register_size_valid_p
= 0;
6696 tdep
->register_size
= 0;
6697 tdep
->gregset
= NULL
;
6698 tdep
->gregset64
= NULL
;
6699 tdep
->fpregset
= NULL
;
6700 tdep
->fpregset64
= NULL
;
6702 if (info
.target_desc
)
6704 /* Some useful properties can be inferred from the target. */
6705 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
6707 tdep
->register_size_valid_p
= 1;
6708 tdep
->register_size
= 4;
6710 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
6712 tdep
->register_size_valid_p
= 1;
6713 tdep
->register_size
= 8;
6717 /* Initially set everything according to the default ABI/ISA. */
6718 set_gdbarch_short_bit (gdbarch
, 16);
6719 set_gdbarch_int_bit (gdbarch
, 32);
6720 set_gdbarch_float_bit (gdbarch
, 32);
6721 set_gdbarch_double_bit (gdbarch
, 64);
6722 set_gdbarch_long_double_bit (gdbarch
, 64);
6723 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6724 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6725 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6727 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6728 mips_ax_pseudo_register_collect
);
6729 set_gdbarch_ax_pseudo_register_push_stack
6730 (gdbarch
, mips_ax_pseudo_register_push_stack
);
6732 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6733 mips_elf_make_msymbol_special
);
6735 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
6736 *regnum
= mips_regnum
;
6737 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6738 set_gdbarch_num_regs (gdbarch
, num_regs
);
6739 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6740 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6741 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
6742 tdep
->mips_processor_reg_names
= reg_names
;
6743 tdep
->regnum
= regnum
;
6748 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6749 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6750 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6751 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6752 tdep
->default_mask_address_p
= 0;
6753 set_gdbarch_long_bit (gdbarch
, 32);
6754 set_gdbarch_ptr_bit (gdbarch
, 32);
6755 set_gdbarch_long_long_bit (gdbarch
, 64);
6758 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6759 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6760 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6761 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6762 tdep
->default_mask_address_p
= 0;
6763 set_gdbarch_long_bit (gdbarch
, 32);
6764 set_gdbarch_ptr_bit (gdbarch
, 32);
6765 set_gdbarch_long_long_bit (gdbarch
, 64);
6767 case MIPS_ABI_EABI32
:
6768 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6769 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6770 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6771 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6772 tdep
->default_mask_address_p
= 0;
6773 set_gdbarch_long_bit (gdbarch
, 32);
6774 set_gdbarch_ptr_bit (gdbarch
, 32);
6775 set_gdbarch_long_long_bit (gdbarch
, 64);
6777 case MIPS_ABI_EABI64
:
6778 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6779 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6780 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6781 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6782 tdep
->default_mask_address_p
= 0;
6783 set_gdbarch_long_bit (gdbarch
, 64);
6784 set_gdbarch_ptr_bit (gdbarch
, 64);
6785 set_gdbarch_long_long_bit (gdbarch
, 64);
6788 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6789 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6790 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6791 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6792 tdep
->default_mask_address_p
= 0;
6793 set_gdbarch_long_bit (gdbarch
, 32);
6794 set_gdbarch_ptr_bit (gdbarch
, 32);
6795 set_gdbarch_long_long_bit (gdbarch
, 64);
6796 set_gdbarch_long_double_bit (gdbarch
, 128);
6797 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6800 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6801 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6802 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6803 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6804 tdep
->default_mask_address_p
= 0;
6805 set_gdbarch_long_bit (gdbarch
, 64);
6806 set_gdbarch_ptr_bit (gdbarch
, 64);
6807 set_gdbarch_long_long_bit (gdbarch
, 64);
6808 set_gdbarch_long_double_bit (gdbarch
, 128);
6809 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6812 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6815 /* GCC creates a pseudo-section whose name specifies the size of
6816 longs, since -mlong32 or -mlong64 may be used independent of
6817 other options. How those options affect pointer sizes is ABI and
6818 architecture dependent, so use them to override the default sizes
6819 set by the ABI. This table shows the relationship between ABI,
6820 -mlongXX, and size of pointers:
6822 ABI -mlongXX ptr bits
6823 --- -------- --------
6837 Note that for o32 and eabi32, pointers are always 32 bits
6838 regardless of any -mlongXX option. For all others, pointers and
6839 longs are the same, as set by -mlongXX or set by defaults. */
6841 if (info
.abfd
!= NULL
)
6845 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6848 set_gdbarch_long_bit (gdbarch
, long_bit
);
6852 case MIPS_ABI_EABI32
:
6857 case MIPS_ABI_EABI64
:
6858 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6861 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6866 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6867 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6870 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6871 flag in object files because to do so would make it impossible to
6872 link with libraries compiled without "-gp32". This is
6873 unnecessarily restrictive.
6875 We could solve this problem by adding "-gp32" multilibs to gcc,
6876 but to set this flag before gcc is built with such multilibs will
6877 break too many systems.''
6879 But even more unhelpfully, the default linker output target for
6880 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6881 for 64-bit programs - you need to change the ABI to change this,
6882 and not all gcc targets support that currently. Therefore using
6883 this flag to detect 32-bit mode would do the wrong thing given
6884 the current gcc - it would make GDB treat these 64-bit programs
6885 as 32-bit programs by default. */
6887 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6888 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6890 /* Add/remove bits from an address. The MIPS needs be careful to
6891 ensure that all 32 bit addresses are sign extended to 64 bits. */
6892 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6894 /* Unwind the frame. */
6895 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6896 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
6897 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
6899 /* Map debug register numbers onto internal register numbers. */
6900 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6901 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6902 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6903 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6904 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6905 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6907 /* MIPS version of CALL_DUMMY. */
6909 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6910 replaced by a command, and all targets will default to on stack
6911 (regardless of the stack's execute status). */
6912 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6913 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6915 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6916 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6917 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6919 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6920 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6921 set_gdbarch_adjust_breakpoint_address (gdbarch
,
6922 mips_adjust_breakpoint_address
);
6924 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6926 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6928 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6929 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6930 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6932 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6934 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6936 if (mips_abi
== MIPS_ABI_N32
)
6937 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6938 else if (mips_abi
== MIPS_ABI_N64
)
6939 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6941 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6943 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6944 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6945 need to all be folded into the target vector. Since they are
6946 being used as guards for target_stopped_by_watchpoint, why not have
6947 target_stopped_by_watchpoint return the type of watchpoint that the code
6949 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6951 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6953 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
6954 to support MIPS16. This is a bad thing. Make sure not to do it
6955 if we have an OS ABI that actually supports shared libraries, since
6956 shared library support is more important. If we have an OS someday
6957 that supports both shared libraries and MIPS16, we'll have to find
6958 a better place for these.
6959 macro/2012-04-25: But that applies to return trampolines only and
6960 currently no MIPS OS ABI uses shared libraries that have them. */
6961 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6963 set_gdbarch_single_step_through_delay (gdbarch
,
6964 mips_single_step_through_delay
);
6966 /* Virtual tables. */
6967 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6969 mips_register_g_packet_guesses (gdbarch
);
6971 /* Hook in OS ABI-specific overrides, if they have been registered. */
6972 info
.tdep_info
= (void *) tdesc_data
;
6973 gdbarch_init_osabi (info
, gdbarch
);
6975 /* The hook may have adjusted num_regs, fetch the final value and
6976 set pc_regnum and sp_regnum now that it has been fixed. */
6977 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
6978 replaced by gdbarch_read_pc? */
6979 num_regs
= gdbarch_num_regs (gdbarch
);
6980 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6981 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6983 /* Unwind the frame. */
6984 dwarf2_append_unwinders (gdbarch
);
6985 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6986 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6987 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6988 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6989 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6990 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6991 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6995 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6996 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6998 /* Override the normal target description methods to handle our
6999 dual real and pseudo registers. */
7000 set_gdbarch_register_name (gdbarch
, mips_register_name
);
7001 set_gdbarch_register_reggroup_p (gdbarch
,
7002 mips_tdesc_register_reggroup_p
);
7004 num_regs
= gdbarch_num_regs (gdbarch
);
7005 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
7006 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
7007 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
7010 /* Add ABI-specific aliases for the registers. */
7011 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
7012 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
7013 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
7014 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
7016 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
7017 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
7018 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
7020 /* Add some other standard aliases. */
7021 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
7022 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
7023 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
7025 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
7026 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
7027 value_of_mips_user_reg
,
7028 &mips_numeric_register_aliases
[i
].regnum
);
7034 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
7036 struct gdbarch_info info
;
7038 /* Force the architecture to update, and (if it's a MIPS architecture)
7039 mips_gdbarch_init will take care of the rest. */
7040 gdbarch_info_init (&info
);
7041 gdbarch_update_p (info
);
7044 /* Print out which MIPS ABI is in use. */
7047 show_mips_abi (struct ui_file
*file
,
7049 struct cmd_list_element
*ignored_cmd
,
7050 const char *ignored_value
)
7052 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
7055 "The MIPS ABI is unknown because the current architecture "
7059 enum mips_abi global_abi
= global_mips_abi ();
7060 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
7061 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
7063 if (global_abi
== MIPS_ABI_UNKNOWN
)
7066 "The MIPS ABI is set automatically (currently \"%s\").\n",
7068 else if (global_abi
== actual_abi
)
7071 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
7075 /* Probably shouldn't happen... */
7076 fprintf_filtered (file
,
7077 "The (auto detected) MIPS ABI \"%s\" is in use "
7078 "even though the user setting was \"%s\".\n",
7079 actual_abi_str
, mips_abi_strings
[global_abi
]);
7085 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
7087 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7091 int ef_mips_32bitmode
;
7092 /* Determine the ISA. */
7093 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
7111 /* Determine the size of a pointer. */
7112 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
7113 fprintf_unfiltered (file
,
7114 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
7116 fprintf_unfiltered (file
,
7117 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
7119 fprintf_unfiltered (file
,
7120 "mips_dump_tdep: ef_mips_arch = %d\n",
7122 fprintf_unfiltered (file
,
7123 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
7124 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
7125 fprintf_unfiltered (file
,
7127 "mips_mask_address_p() %d (default %d)\n",
7128 mips_mask_address_p (tdep
),
7129 tdep
->default_mask_address_p
);
7131 fprintf_unfiltered (file
,
7132 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
7133 MIPS_DEFAULT_FPU_TYPE
,
7134 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
7135 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
7136 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
7138 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
7139 MIPS_EABI (gdbarch
));
7140 fprintf_unfiltered (file
,
7141 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
7142 MIPS_FPU_TYPE (gdbarch
),
7143 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
7144 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
7145 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
7149 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
7152 _initialize_mips_tdep (void)
7154 static struct cmd_list_element
*mipsfpulist
= NULL
;
7155 struct cmd_list_element
*c
;
7157 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
7158 if (MIPS_ABI_LAST
+ 1
7159 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
7160 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
7162 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
7164 mips_pdr_data
= register_objfile_data ();
7166 /* Create feature sets with the appropriate properties. The values
7167 are not important. */
7168 mips_tdesc_gp32
= allocate_target_description ();
7169 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
7171 mips_tdesc_gp64
= allocate_target_description ();
7172 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
7174 /* Add root prefix command for all "set mips"/"show mips" commands. */
7175 add_prefix_cmd ("mips", no_class
, set_mips_command
,
7176 _("Various MIPS specific commands."),
7177 &setmipscmdlist
, "set mips ", 0, &setlist
);
7179 add_prefix_cmd ("mips", no_class
, show_mips_command
,
7180 _("Various MIPS specific commands."),
7181 &showmipscmdlist
, "show mips ", 0, &showlist
);
7183 /* Allow the user to override the ABI. */
7184 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
7185 &mips_abi_string
, _("\
7186 Set the MIPS ABI used by this program."), _("\
7187 Show the MIPS ABI used by this program."), _("\
7188 This option can be set to one of:\n\
7189 auto - the default ABI associated with the current binary\n\
7198 &setmipscmdlist
, &showmipscmdlist
);
7200 /* Let the user turn off floating point and set the fence post for
7201 heuristic_proc_start. */
7203 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
7204 _("Set use of MIPS floating-point coprocessor."),
7205 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
7206 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
7207 _("Select single-precision MIPS floating-point coprocessor."),
7209 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
7210 _("Select double-precision MIPS floating-point coprocessor."),
7212 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
7213 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
7214 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
7215 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
7216 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
7217 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
7218 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
7219 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
7220 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
7221 _("Select MIPS floating-point coprocessor automatically."),
7223 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
7224 _("Show current use of MIPS floating-point coprocessor target."),
7227 /* We really would like to have both "0" and "unlimited" work, but
7228 command.c doesn't deal with that. So make it a var_zinteger
7229 because the user can always use "999999" or some such for unlimited. */
7230 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
7231 &heuristic_fence_post
, _("\
7232 Set the distance searched for the start of a function."), _("\
7233 Show the distance searched for the start of a function."), _("\
7234 If you are debugging a stripped executable, GDB needs to search through the\n\
7235 program for the start of a function. This command sets the distance of the\n\
7236 search. The only need to set it is when debugging a stripped executable."),
7237 reinit_frame_cache_sfunc
,
7238 NULL
, /* FIXME: i18n: The distance searched for
7239 the start of a function is %s. */
7240 &setlist
, &showlist
);
7242 /* Allow the user to control whether the upper bits of 64-bit
7243 addresses should be zeroed. */
7244 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
7245 &mask_address_var
, _("\
7246 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
7247 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
7248 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
7249 allow GDB to determine the correct value."),
7250 NULL
, show_mask_address
,
7251 &setmipscmdlist
, &showmipscmdlist
);
7253 /* Allow the user to control the size of 32 bit registers within the
7254 raw remote packet. */
7255 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
7256 &mips64_transfers_32bit_regs_p
, _("\
7257 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
7259 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
7261 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
7262 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
7263 64 bits for others. Use \"off\" to disable compatibility mode"),
7264 set_mips64_transfers_32bit_regs
,
7265 NULL
, /* FIXME: i18n: Compatibility with 64-bit
7266 MIPS target that transfers 32-bit
7267 quantities is %s. */
7268 &setlist
, &showlist
);
7270 /* Debug this files internals. */
7271 add_setshow_zinteger_cmd ("mips", class_maintenance
,
7273 Set mips debugging."), _("\
7274 Show mips debugging."), _("\
7275 When non-zero, mips specific debugging is enabled."),
7277 NULL
, /* FIXME: i18n: Mips debugging is
7279 &setdebuglist
, &showdebuglist
);