1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
54 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
55 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
57 /* A useful bit in the CP0 status register (PS_REGNUM). */
58 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
59 #define ST0_FR (1 << 26)
61 /* The sizes of floating point registers. */
65 MIPS_FPU_SINGLE_REGSIZE
= 4,
66 MIPS_FPU_DOUBLE_REGSIZE
= 8
70 static const char *mips_abi_string
;
72 static const char *mips_abi_strings
[] = {
83 struct frame_extra_info
85 mips_extra_func_info_t proc_desc
;
89 /* Various MIPS ISA options (related to stack analysis) can be
90 overridden dynamically. Establish an enum/array for managing
93 static const char size_auto
[] = "auto";
94 static const char size_32
[] = "32";
95 static const char size_64
[] = "64";
97 static const char *size_enums
[] = {
104 /* Some MIPS boards don't support floating point while others only
105 support single-precision floating-point operations. See also
106 FP_REGISTER_DOUBLE. */
110 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
111 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
112 MIPS_FPU_NONE
/* No floating point. */
115 #ifndef MIPS_DEFAULT_FPU_TYPE
116 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
118 static int mips_fpu_type_auto
= 1;
119 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
121 static int mips_debug
= 0;
123 /* MIPS specific per-architecture information */
126 /* from the elf header */
130 enum mips_abi mips_abi
;
131 enum mips_abi found_abi
;
132 enum mips_fpu_type mips_fpu_type
;
133 int mips_last_arg_regnum
;
134 int mips_last_fp_arg_regnum
;
135 int mips_default_saved_regsize
;
136 int mips_fp_register_double
;
137 int mips_default_stack_argsize
;
138 int default_mask_address_p
;
139 /* Is the target using 64-bit raw integer registers but only
140 storing a left-aligned 32-bit value in each? */
141 int mips64_transfers_32bit_regs_p
;
142 /* Indexes for various registers. IRIX and embedded have
143 different values. This contains the "public" fields. Don't
144 add any that do not need to be public. */
145 const struct mips_regnum
*regnum
;
146 /* Register names table for the current register set. */
147 const char **mips_processor_reg_names
;
150 const struct mips_regnum
*
151 mips_regnum (struct gdbarch
*gdbarch
)
153 return gdbarch_tdep (gdbarch
)->regnum
;
157 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
159 return mips_regnum (gdbarch
)->fp0
+ 12;
162 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
163 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
165 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
167 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
169 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
171 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
172 functions to test, set, or clear bit 0 of addresses. */
175 is_mips16_addr (CORE_ADDR addr
)
181 make_mips16_addr (CORE_ADDR addr
)
187 unmake_mips16_addr (CORE_ADDR addr
)
189 return ((addr
) & ~1);
192 /* Return the contents of register REGNUM as a signed integer. */
195 read_signed_register (int regnum
)
197 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
198 deprecated_read_register_gen (regnum
, buf
);
199 return (extract_signed_integer (buf
, register_size (current_gdbarch
, regnum
)));
203 read_signed_register_pid (int regnum
, ptid_t ptid
)
208 if (ptid_equal (ptid
, inferior_ptid
))
209 return read_signed_register (regnum
);
211 save_ptid
= inferior_ptid
;
213 inferior_ptid
= ptid
;
215 retval
= read_signed_register (regnum
);
217 inferior_ptid
= save_ptid
;
222 /* Return the MIPS ABI associated with GDBARCH. */
224 mips_abi (struct gdbarch
*gdbarch
)
226 return gdbarch_tdep (gdbarch
)->mips_abi
;
230 mips_regsize (struct gdbarch
*gdbarch
)
232 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
233 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
236 /* Return the currently configured (or set) saved register size. */
238 static const char *mips_saved_regsize_string
= size_auto
;
241 mips_saved_regsize (struct gdbarch_tdep
*tdep
)
243 if (mips_saved_regsize_string
== size_auto
)
244 return tdep
->mips_default_saved_regsize
;
245 else if (mips_saved_regsize_string
== size_64
)
247 else /* if (mips_saved_regsize_string == size_32) */
251 /* Functions for setting and testing a bit in a minimal symbol that
252 marks it as 16-bit function. The MSB of the minimal symbol's
253 "info" field is used for this purpose.
255 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
256 i.e. refers to a 16-bit function, and sets a "special" bit in a
257 minimal symbol to mark it as a 16-bit function
259 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
262 mips_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
264 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
266 MSYMBOL_INFO (msym
) = (char *)
267 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
268 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
273 msymbol_is_special (struct minimal_symbol
*msym
)
275 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
278 /* XFER a value from the big/little/left end of the register.
279 Depending on the size of the value it might occupy the entire
280 register or just part of it. Make an allowance for this, aligning
281 things accordingly. */
284 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
285 enum bfd_endian endian
, bfd_byte
*in
, const bfd_byte
*out
,
288 bfd_byte reg
[MAX_REGISTER_SIZE
];
290 gdb_assert (reg_num
>= NUM_REGS
);
291 /* Need to transfer the left or right part of the register, based on
292 the targets byte order. */
296 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
298 case BFD_ENDIAN_LITTLE
:
301 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
305 internal_error (__FILE__
, __LINE__
, "bad switch");
308 fprintf_unfiltered (gdb_stderr
,
309 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
310 reg_num
, reg_offset
, buf_offset
, length
);
311 if (mips_debug
&& out
!= NULL
)
314 fprintf_unfiltered (gdb_stdlog
, "out ");
315 for (i
= 0; i
< length
; i
++)
316 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
319 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
, in
+ buf_offset
);
321 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
, out
+ buf_offset
);
322 if (mips_debug
&& in
!= NULL
)
325 fprintf_unfiltered (gdb_stdlog
, "in ");
326 for (i
= 0; i
< length
; i
++)
327 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
330 fprintf_unfiltered (gdb_stdlog
, "\n");
333 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
334 compatiblity mode. A return value of 1 means that we have
335 physical 64-bit registers, but should treat them as 32-bit registers. */
338 mips2_fp_compat (void)
340 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
342 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 4)
346 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
347 in all the places we deal with FP registers. PR gdb/413. */
348 /* Otherwise check the FR bit in the status register - it controls
349 the FP compatiblity mode. If it is clear we are in compatibility
351 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
358 /* Indicate that the ABI makes use of double-precision registers
359 provided by the FPU (rather than combining pairs of registers to
360 form double-precision values). See also MIPS_FPU_TYPE. */
361 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
363 /* The amount of space reserved on the stack for registers. This is
364 different to MIPS_SAVED_REGSIZE as it determines the alignment of
365 data allocated after the registers have run out. */
367 static const char *mips_stack_argsize_string
= size_auto
;
370 mips_stack_argsize (struct gdbarch_tdep
*tdep
)
372 if (mips_stack_argsize_string
== size_auto
)
373 return tdep
->mips_default_stack_argsize
;
374 else if (mips_stack_argsize_string
== size_64
)
376 else /* if (mips_stack_argsize_string == size_32) */
380 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
382 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
383 struct frame_info
*, int);
385 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
387 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
389 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
391 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
392 struct frame_info
*next_frame
,
395 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
396 mips_extra_func_info_t proc_desc
);
398 static struct type
*mips_float_register_type (void);
399 static struct type
*mips_double_register_type (void);
401 /* The list of available "set mips " and "show mips " commands */
403 static struct cmd_list_element
*setmipscmdlist
= NULL
;
404 static struct cmd_list_element
*showmipscmdlist
= NULL
;
406 /* Integer registers 0 thru 31 are handled explicitly by
407 mips_register_name(). Processor specific registers 32 and above
408 are listed in the followign tables. */
410 enum { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
414 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
415 "sr", "lo", "hi", "bad", "cause","pc",
416 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
417 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
418 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
419 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
420 "fsr", "fir", ""/*"fp"*/, "",
421 "", "", "", "", "", "", "", "",
422 "", "", "", "", "", "", "", "",
425 /* Names of IDT R3041 registers. */
427 static const char *mips_r3041_reg_names
[] = {
428 "sr", "lo", "hi", "bad", "cause","pc",
429 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
430 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
431 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
432 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
433 "fsr", "fir", "",/*"fp"*/ "",
434 "", "", "bus", "ccfg", "", "", "", "",
435 "", "", "port", "cmp", "", "", "epc", "prid",
438 /* Names of tx39 registers. */
440 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
441 "sr", "lo", "hi", "bad", "cause","pc",
442 "", "", "", "", "", "", "", "",
443 "", "", "", "", "", "", "", "",
444 "", "", "", "", "", "", "", "",
445 "", "", "", "", "", "", "", "",
447 "", "", "", "", "", "", "", "",
448 "", "", "config", "cache", "debug", "depc", "epc", ""
451 /* Names of IRIX registers. */
452 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
453 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
454 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
455 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
456 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
457 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
461 /* Return the name of the register corresponding to REGNO. */
463 mips_register_name (int regno
)
465 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
466 /* GPR names for all ABIs other than n32/n64. */
467 static char *mips_gpr_names
[] = {
468 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
469 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
470 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
471 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
474 /* GPR names for n32 and n64 ABIs. */
475 static char *mips_n32_n64_gpr_names
[] = {
476 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
477 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
478 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
479 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
482 enum mips_abi abi
= mips_abi (current_gdbarch
);
484 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
485 don't make the raw register names visible. */
486 int rawnum
= regno
% NUM_REGS
;
487 if (regno
< NUM_REGS
)
490 /* The MIPS integer registers are always mapped from 0 to 31. The
491 names of the registers (which reflects the conventions regarding
492 register use) vary depending on the ABI. */
493 if (0 <= rawnum
&& rawnum
< 32)
495 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
496 return mips_n32_n64_gpr_names
[rawnum
];
498 return mips_gpr_names
[rawnum
];
500 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
502 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
503 return tdep
->mips_processor_reg_names
[rawnum
- 32];
506 internal_error (__FILE__
, __LINE__
,
507 "mips_register_name: bad register number %d", rawnum
);
510 /* Return the groups that a MIPS register can be categorised into. */
513 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
514 struct reggroup
*reggroup
)
519 int rawnum
= regnum
% NUM_REGS
;
520 int pseudo
= regnum
/ NUM_REGS
;
521 if (reggroup
== all_reggroup
)
523 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
524 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
525 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
526 (gdbarch), as not all architectures are multi-arch. */
527 raw_p
= rawnum
< NUM_REGS
;
528 if (REGISTER_NAME (regnum
) == NULL
529 || REGISTER_NAME (regnum
)[0] == '\0')
531 if (reggroup
== float_reggroup
)
532 return float_p
&& pseudo
;
533 if (reggroup
== vector_reggroup
)
534 return vector_p
&& pseudo
;
535 if (reggroup
== general_reggroup
)
536 return (!vector_p
&& !float_p
) && pseudo
;
537 /* Save the pseudo registers. Need to make certain that any code
538 extracting register values from a saved register cache also uses
540 if (reggroup
== save_reggroup
)
541 return raw_p
&& pseudo
;
542 /* Restore the same pseudo register. */
543 if (reggroup
== restore_reggroup
)
544 return raw_p
&& pseudo
;
548 /* Map the symbol table registers which live in the range [1 *
549 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
550 registers. Take care of alignment and size problems. */
553 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
554 int cookednum
, void *buf
)
556 int rawnum
= cookednum
% NUM_REGS
;
557 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
558 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
559 return regcache_raw_read (regcache
, rawnum
, buf
);
560 else if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, cookednum
))
562 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
563 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
564 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
566 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
569 internal_error (__FILE__
, __LINE__
, "bad register size");
573 mips_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
574 int cookednum
, const void *buf
)
576 int rawnum
= cookednum
% NUM_REGS
;
577 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
578 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
579 return regcache_raw_write (regcache
, rawnum
, buf
);
580 else if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, cookednum
))
582 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
583 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
584 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
586 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
589 internal_error (__FILE__
, __LINE__
, "bad register size");
592 /* Table to translate MIPS16 register field to actual register number. */
593 static int mips16_to_32_reg
[8] =
594 {16, 17, 2, 3, 4, 5, 6, 7};
596 /* Heuristic_proc_start may hunt through the text section for a long
597 time across a 2400 baud serial line. Allows the user to limit this
600 static unsigned int heuristic_fence_post
= 0;
602 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
603 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
604 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
605 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
606 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
607 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
608 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
609 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
610 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
611 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
612 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
613 this will corrupt pdr.iline. Fortunately we don't use it. */
614 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
615 #define _PROC_MAGIC_ 0x0F0F0F0F
616 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
617 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
619 struct linked_proc_info
621 struct mips_extra_func_info info
;
622 struct linked_proc_info
*next
;
624 *linked_proc_desc_table
= NULL
;
626 /* Number of bytes of storage in the actual machine representation for
627 register N. NOTE: This defines the pseudo register type so need to
628 rebuild the architecture vector. */
630 static int mips64_transfers_32bit_regs_p
= 0;
633 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
634 struct cmd_list_element
*c
)
636 struct gdbarch_info info
;
637 gdbarch_info_init (&info
);
638 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
639 instead of relying on globals. Doing that would let generic code
640 handle the search for this specific architecture. */
641 if (!gdbarch_update_p (info
))
643 mips64_transfers_32bit_regs_p
= 0;
644 error ("32-bit compatibility mode not supported");
648 /* Convert to/from a register and the corresponding memory value. */
651 mips_convert_register_p (int regnum
, struct type
*type
)
653 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
654 && register_size (current_gdbarch
, regnum
) == 4
655 && (regnum
) >= mips_regnum (current_gdbarch
)->fp0
&& (regnum
) < mips_regnum (current_gdbarch
)->fp0
+ 32
656 && TYPE_CODE(type
) == TYPE_CODE_FLT
657 && TYPE_LENGTH(type
) == 8);
661 mips_register_to_value (struct frame_info
*frame
, int regnum
,
662 struct type
*type
, void *to
)
664 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
665 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
669 mips_value_to_register (struct frame_info
*frame
, int regnum
,
670 struct type
*type
, const void *from
)
672 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
673 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
676 /* Return the GDB type object for the "standard" data type of data in
680 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
682 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
683 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
684 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
686 /* The floating-point registers raw, or cooked, always match
687 mips_regsize(), and also map 1:1, byte for byte. */
688 switch (gdbarch_byte_order (gdbarch
))
691 if (mips_regsize (gdbarch
) == 4)
692 return builtin_type_ieee_single_big
;
694 return builtin_type_ieee_double_big
;
695 case BFD_ENDIAN_LITTLE
:
696 if (mips_regsize (gdbarch
) == 4)
697 return builtin_type_ieee_single_little
;
699 return builtin_type_ieee_double_little
;
700 case BFD_ENDIAN_UNKNOWN
:
702 internal_error (__FILE__
, __LINE__
, "bad switch");
705 else if (regnum
>= (NUM_REGS
+ mips_regnum (current_gdbarch
)->fp_control_status
)
706 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
707 /* The pseudo/cooked view of the embedded registers is always
708 32-bit. The raw view is handled below. */
709 return builtin_type_int32
;
710 else if (regnum
>= NUM_REGS
&& mips_regsize (gdbarch
)
711 && gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
712 /* The target, while using a 64-bit register buffer, is only
713 transfering 32-bits of each integer register. Reflect this in
714 the cooked/pseudo register value. */
715 return builtin_type_int32
;
716 else if (mips_regsize (gdbarch
) == 8)
718 return builtin_type_int64
;
721 return builtin_type_int32
;
724 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
729 return read_signed_register (SP_REGNUM
);
732 /* Should the upper word of 64-bit addresses be zeroed? */
733 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
736 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
738 switch (mask_address_var
)
740 case AUTO_BOOLEAN_TRUE
:
742 case AUTO_BOOLEAN_FALSE
:
745 case AUTO_BOOLEAN_AUTO
:
746 return tdep
->default_mask_address_p
;
748 internal_error (__FILE__
, __LINE__
,
749 "mips_mask_address_p: bad switch");
755 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
757 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
758 switch (mask_address_var
)
760 case AUTO_BOOLEAN_TRUE
:
761 printf_filtered ("The 32 bit mips address mask is enabled\n");
763 case AUTO_BOOLEAN_FALSE
:
764 printf_filtered ("The 32 bit mips address mask is disabled\n");
766 case AUTO_BOOLEAN_AUTO
:
767 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
768 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
771 internal_error (__FILE__
, __LINE__
,
772 "show_mask_address: bad switch");
777 /* Should call_function allocate stack space for a struct return? */
780 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
782 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
783 return (TYPE_LENGTH (type
) > 2 * mips_saved_regsize (tdep
));
786 /* Should call_function pass struct by reference?
787 For each architecture, structs are passed either by
788 value or by reference, depending on their size. */
791 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
793 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
794 int len
= TYPE_LENGTH (check_typedef (type
));
795 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
797 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
798 return (len
> mips_saved_regsize (tdep
));
803 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
806 pc_is_mips16 (bfd_vma memaddr
)
808 struct minimal_symbol
*sym
;
810 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
811 if (is_mips16_addr (memaddr
))
814 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
815 the high bit of the info field. Use this to decide if the function is
816 MIPS16 or normal MIPS. */
817 sym
= lookup_minimal_symbol_by_pc (memaddr
);
819 return msymbol_is_special (sym
);
824 /* MIPS believes that the PC has a sign extended value. Perhaphs the
825 all registers should be sign extended for simplicity? */
828 mips_read_pc (ptid_t ptid
)
830 return read_signed_register_pid (PC_REGNUM
, ptid
);
833 /* This returns the PC of the first inst after the prologue. If we can't
834 find the prologue, then return 0. */
837 after_prologue (CORE_ADDR pc
,
838 mips_extra_func_info_t proc_desc
)
840 struct symtab_and_line sal
;
841 CORE_ADDR func_addr
, func_end
;
843 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
844 to read the stack pointer from the current machine state, because
845 the current machine state has nothing to do with the information
846 we need from the proc_desc; and the process may or may not exist
849 proc_desc
= find_proc_desc (pc
, NULL
, 0);
853 /* If function is frameless, then we need to do it the hard way. I
854 strongly suspect that frameless always means prologueless... */
855 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
856 && PROC_FRAME_OFFSET (proc_desc
) == 0)
860 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
861 return 0; /* Unknown */
863 sal
= find_pc_line (func_addr
, 0);
865 if (sal
.end
< func_end
)
868 /* The line after the prologue is after the end of the function. In this
869 case, tell the caller to find the prologue the hard way. */
874 /* Decode a MIPS32 instruction that saves a register in the stack, and
875 set the appropriate bit in the general register mask or float register mask
876 to indicate which register is saved. This is a helper function
877 for mips_find_saved_regs. */
880 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
881 unsigned long *float_mask
)
885 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
886 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
887 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
889 /* It might be possible to use the instruction to
890 find the offset, rather than the code below which
891 is based on things being in a certain order in the
892 frame, but figuring out what the instruction's offset
893 is relative to might be a little tricky. */
894 reg
= (inst
& 0x001f0000) >> 16;
895 *gen_mask
|= (1 << reg
);
897 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
898 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
899 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
902 reg
= ((inst
& 0x001f0000) >> 16);
903 *float_mask
|= (1 << reg
);
907 /* Decode a MIPS16 instruction that saves a register in the stack, and
908 set the appropriate bit in the general register or float register mask
909 to indicate which register is saved. This is a helper function
910 for mips_find_saved_regs. */
913 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
915 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
917 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
918 *gen_mask
|= (1 << reg
);
920 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
922 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
923 *gen_mask
|= (1 << reg
);
925 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
926 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
927 *gen_mask
|= (1 << RA_REGNUM
);
931 /* Fetch and return instruction from the specified location. If the PC
932 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
935 mips_fetch_instruction (CORE_ADDR addr
)
937 char buf
[MIPS_INSTLEN
];
941 if (pc_is_mips16 (addr
))
943 instlen
= MIPS16_INSTLEN
;
944 addr
= unmake_mips16_addr (addr
);
947 instlen
= MIPS_INSTLEN
;
948 status
= read_memory_nobpt (addr
, buf
, instlen
);
950 memory_error (status
, addr
);
951 return extract_unsigned_integer (buf
, instlen
);
955 /* These the fields of 32 bit mips instructions */
956 #define mips32_op(x) (x >> 26)
957 #define itype_op(x) (x >> 26)
958 #define itype_rs(x) ((x >> 21) & 0x1f)
959 #define itype_rt(x) ((x >> 16) & 0x1f)
960 #define itype_immediate(x) (x & 0xffff)
962 #define jtype_op(x) (x >> 26)
963 #define jtype_target(x) (x & 0x03ffffff)
965 #define rtype_op(x) (x >> 26)
966 #define rtype_rs(x) ((x >> 21) & 0x1f)
967 #define rtype_rt(x) ((x >> 16) & 0x1f)
968 #define rtype_rd(x) ((x >> 11) & 0x1f)
969 #define rtype_shamt(x) ((x >> 6) & 0x1f)
970 #define rtype_funct(x) (x & 0x3f)
973 mips32_relative_offset (unsigned long inst
)
976 x
= itype_immediate (inst
);
977 if (x
& 0x8000) /* sign bit set */
979 x
|= 0xffff0000; /* sign extension */
985 /* Determine whate to set a single step breakpoint while considering
988 mips32_next_pc (CORE_ADDR pc
)
992 inst
= mips_fetch_instruction (pc
);
993 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
995 if (itype_op (inst
) >> 2 == 5)
996 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
998 op
= (itype_op (inst
) & 0x03);
1008 goto greater_branch
;
1013 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1014 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1016 int tf
= itype_rt (inst
) & 0x01;
1017 int cnum
= itype_rt (inst
) >> 2;
1018 int fcrcs
= read_signed_register (mips_regnum (current_gdbarch
)->fp_control_status
);
1019 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1021 if (((cond
>> cnum
) & 0x01) == tf
)
1022 pc
+= mips32_relative_offset (inst
) + 4;
1027 pc
+= 4; /* Not a branch, next instruction is easy */
1030 { /* This gets way messy */
1032 /* Further subdivide into SPECIAL, REGIMM and other */
1033 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1035 case 0: /* SPECIAL */
1036 op
= rtype_funct (inst
);
1041 /* Set PC to that address */
1042 pc
= read_signed_register (rtype_rs (inst
));
1048 break; /* end SPECIAL */
1049 case 1: /* REGIMM */
1051 op
= itype_rt (inst
); /* branch condition */
1056 case 16: /* BLTZAL */
1057 case 18: /* BLTZALL */
1059 if (read_signed_register (itype_rs (inst
)) < 0)
1060 pc
+= mips32_relative_offset (inst
) + 4;
1062 pc
+= 8; /* after the delay slot */
1066 case 17: /* BGEZAL */
1067 case 19: /* BGEZALL */
1068 if (read_signed_register (itype_rs (inst
)) >= 0)
1069 pc
+= mips32_relative_offset (inst
) + 4;
1071 pc
+= 8; /* after the delay slot */
1073 /* All of the other instructions in the REGIMM category */
1078 break; /* end REGIMM */
1083 reg
= jtype_target (inst
) << 2;
1084 /* Upper four bits get never changed... */
1085 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1088 /* FIXME case JALX : */
1091 reg
= jtype_target (inst
) << 2;
1092 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1093 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1095 break; /* The new PC will be alternate mode */
1096 case 4: /* BEQ, BEQL */
1098 if (read_signed_register (itype_rs (inst
)) ==
1099 read_signed_register (itype_rt (inst
)))
1100 pc
+= mips32_relative_offset (inst
) + 4;
1104 case 5: /* BNE, BNEL */
1106 if (read_signed_register (itype_rs (inst
)) !=
1107 read_signed_register (itype_rt (inst
)))
1108 pc
+= mips32_relative_offset (inst
) + 4;
1112 case 6: /* BLEZ, BLEZL */
1113 if (read_signed_register (itype_rs (inst
) <= 0))
1114 pc
+= mips32_relative_offset (inst
) + 4;
1120 greater_branch
: /* BGTZ, BGTZL */
1121 if (read_signed_register (itype_rs (inst
) > 0))
1122 pc
+= mips32_relative_offset (inst
) + 4;
1129 } /* mips32_next_pc */
1131 /* Decoding the next place to set a breakpoint is irregular for the
1132 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1133 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1134 We dont want to set a single step instruction on the extend instruction
1138 /* Lots of mips16 instruction formats */
1139 /* Predicting jumps requires itype,ritype,i8type
1140 and their extensions extItype,extritype,extI8type
1142 enum mips16_inst_fmts
1144 itype
, /* 0 immediate 5,10 */
1145 ritype
, /* 1 5,3,8 */
1146 rrtype
, /* 2 5,3,3,5 */
1147 rritype
, /* 3 5,3,3,5 */
1148 rrrtype
, /* 4 5,3,3,3,2 */
1149 rriatype
, /* 5 5,3,3,1,4 */
1150 shifttype
, /* 6 5,3,3,3,2 */
1151 i8type
, /* 7 5,3,8 */
1152 i8movtype
, /* 8 5,3,3,5 */
1153 i8mov32rtype
, /* 9 5,3,5,3 */
1154 i64type
, /* 10 5,3,8 */
1155 ri64type
, /* 11 5,3,3,5 */
1156 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1157 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1158 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1159 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1160 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1161 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1162 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1163 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1164 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1165 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1167 /* I am heaping all the fields of the formats into one structure and
1168 then, only the fields which are involved in instruction extension */
1172 unsigned int regx
; /* Function in i8 type */
1177 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1178 for the bits which make up the immediatate extension. */
1181 extended_offset (unsigned int extension
)
1184 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1186 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1188 value
|= extension
& 0x01f; /* extract 4:0 */
1192 /* Only call this function if you know that this is an extendable
1193 instruction, It wont malfunction, but why make excess remote memory references?
1194 If the immediate operands get sign extended or somthing, do it after
1195 the extension is performed.
1197 /* FIXME: Every one of these cases needs to worry about sign extension
1198 when the offset is to be used in relative addressing */
1202 fetch_mips_16 (CORE_ADDR pc
)
1205 pc
&= 0xfffffffe; /* clear the low order bit */
1206 target_read_memory (pc
, buf
, 2);
1207 return extract_unsigned_integer (buf
, 2);
1211 unpack_mips16 (CORE_ADDR pc
,
1212 unsigned int extension
,
1214 enum mips16_inst_fmts insn_format
,
1215 struct upk_mips16
*upk
)
1220 switch (insn_format
)
1227 value
= extended_offset (extension
);
1228 value
= value
<< 11; /* rom for the original value */
1229 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1233 value
= inst
& 0x7ff;
1234 /* FIXME : Consider sign extension */
1243 { /* A register identifier and an offset */
1244 /* Most of the fields are the same as I type but the
1245 immediate value is of a different length */
1249 value
= extended_offset (extension
);
1250 value
= value
<< 8; /* from the original instruction */
1251 value
|= inst
& 0xff; /* eleven bits from instruction */
1252 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1253 if (value
& 0x4000) /* test the sign bit , bit 26 */
1255 value
&= ~0x3fff; /* remove the sign bit */
1261 value
= inst
& 0xff; /* 8 bits */
1262 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1263 /* FIXME: Do sign extension , this format needs it */
1264 if (value
& 0x80) /* THIS CONFUSES ME */
1266 value
&= 0xef; /* remove the sign bit */
1276 unsigned long value
;
1277 unsigned int nexthalf
;
1278 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1279 value
= value
<< 16;
1280 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1288 internal_error (__FILE__
, __LINE__
,
1291 upk
->offset
= offset
;
1298 add_offset_16 (CORE_ADDR pc
, int offset
)
1300 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1304 extended_mips16_next_pc (CORE_ADDR pc
,
1305 unsigned int extension
,
1308 int op
= (insn
>> 11);
1311 case 2: /* Branch */
1314 struct upk_mips16 upk
;
1315 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1316 offset
= upk
.offset
;
1322 pc
+= (offset
<< 1) + 2;
1325 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1327 struct upk_mips16 upk
;
1328 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1329 pc
= add_offset_16 (pc
, upk
.offset
);
1330 if ((insn
>> 10) & 0x01) /* Exchange mode */
1331 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1338 struct upk_mips16 upk
;
1340 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1341 reg
= read_signed_register (upk
.regx
);
1343 pc
+= (upk
.offset
<< 1) + 2;
1350 struct upk_mips16 upk
;
1352 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1353 reg
= read_signed_register (upk
.regx
);
1355 pc
+= (upk
.offset
<< 1) + 2;
1360 case 12: /* I8 Formats btez btnez */
1362 struct upk_mips16 upk
;
1364 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1365 /* upk.regx contains the opcode */
1366 reg
= read_signed_register (24); /* Test register is 24 */
1367 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1368 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1369 /* pc = add_offset_16(pc,upk.offset) ; */
1370 pc
+= (upk
.offset
<< 1) + 2;
1375 case 29: /* RR Formats JR, JALR, JALR-RA */
1377 struct upk_mips16 upk
;
1378 /* upk.fmt = rrtype; */
1383 upk
.regx
= (insn
>> 8) & 0x07;
1384 upk
.regy
= (insn
>> 5) & 0x07;
1392 break; /* Function return instruction */
1398 break; /* BOGUS Guess */
1400 pc
= read_signed_register (reg
);
1407 /* This is an instruction extension. Fetch the real instruction
1408 (which follows the extension) and decode things based on
1412 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1425 mips16_next_pc (CORE_ADDR pc
)
1427 unsigned int insn
= fetch_mips_16 (pc
);
1428 return extended_mips16_next_pc (pc
, 0, insn
);
1431 /* The mips_next_pc function supports single_step when the remote
1432 target monitor or stub is not developed enough to do a single_step.
1433 It works by decoding the current instruction and predicting where a
1434 branch will go. This isnt hard because all the data is available.
1435 The MIPS32 and MIPS16 variants are quite different */
1437 mips_next_pc (CORE_ADDR pc
)
1440 return mips16_next_pc (pc
);
1442 return mips32_next_pc (pc
);
1445 /* Set up the 'saved_regs' array. This is a data structure containing
1446 the addresses on the stack where each register has been saved, for
1447 each stack frame. Registers that have not been saved will have
1448 zero here. The stack pointer register is special: rather than the
1449 address where the stack register has been saved,
1450 saved_regs[SP_REGNUM] will have the actual value of the previous
1451 frame's stack register. */
1454 mips_find_saved_regs (struct frame_info
*fci
)
1457 /* r0 bit means kernel trap */
1459 /* What registers have been saved? Bitmasks. */
1460 unsigned long gen_mask
, float_mask
;
1461 mips_extra_func_info_t proc_desc
;
1463 CORE_ADDR
*saved_regs
;
1464 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1466 if (deprecated_get_frame_saved_regs (fci
) != NULL
)
1468 saved_regs
= frame_saved_regs_zalloc (fci
);
1470 /* If it is the frame for sigtramp, the saved registers are located
1471 in a sigcontext structure somewhere on the stack. If the stack
1472 layout for sigtramp changes we might have to change these
1473 constants and the companion fixup_sigtramp in mdebugread.c */
1474 #ifndef SIGFRAME_BASE
1475 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1476 above the sigtramp frame. */
1477 #define SIGFRAME_BASE mips_regsize (current_gdbarch)
1478 /* FIXME! Are these correct?? */
1479 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch))
1480 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch))
1481 #define SIGFRAME_FPREGSAVE_OFF \
1482 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch))
1484 if ((get_frame_type (fci
) == SIGTRAMP_FRAME
))
1486 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1488 CORE_ADDR reg_position
= (get_frame_base (fci
) + SIGFRAME_REGSAVE_OFF
1489 + ireg
* mips_regsize (current_gdbarch
));
1490 set_reg_offset (saved_regs
, ireg
, reg_position
);
1492 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1494 CORE_ADDR reg_position
= (get_frame_base (fci
)
1495 + SIGFRAME_FPREGSAVE_OFF
1496 + ireg
* mips_regsize (current_gdbarch
));
1497 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
, reg_position
);
1500 set_reg_offset (saved_regs
, PC_REGNUM
, get_frame_base (fci
) + SIGFRAME_PC_OFF
);
1501 /* SP_REGNUM, contains the value and not the address. */
1502 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1506 proc_desc
= get_frame_extra_info (fci
)->proc_desc
;
1507 if (proc_desc
== NULL
)
1508 /* I'm not sure how/whether this can happen. Normally when we
1509 can't find a proc_desc, we "synthesize" one using
1510 heuristic_proc_desc and set the saved_regs right away. */
1513 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1514 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1515 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1517 if (/* In any frame other than the innermost or a frame interrupted
1518 by a signal, we assume that all registers have been saved.
1519 This assumes that all register saves in a function happen
1520 before the first function call. */
1521 (get_next_frame (fci
) == NULL
1522 || (get_frame_type (get_next_frame (fci
)) == SIGTRAMP_FRAME
))
1524 /* In a dummy frame we know exactly where things are saved. */
1525 && !PROC_DESC_IS_DUMMY (proc_desc
)
1527 /* Don't bother unless we are inside a function prologue.
1528 Outside the prologue, we know where everything is. */
1530 && in_prologue (get_frame_pc (fci
), PROC_LOW_ADDR (proc_desc
))
1532 /* Not sure exactly what kernel_trap means, but if it means the
1533 kernel saves the registers without a prologue doing it, we
1534 better not examine the prologue to see whether registers
1535 have been saved yet. */
1538 /* We need to figure out whether the registers that the
1539 proc_desc claims are saved have been saved yet. */
1543 /* Bitmasks; set if we have found a save for the register. */
1544 unsigned long gen_save_found
= 0;
1545 unsigned long float_save_found
= 0;
1548 /* If the address is odd, assume this is MIPS16 code. */
1549 addr
= PROC_LOW_ADDR (proc_desc
);
1550 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1552 /* Scan through this function's instructions preceding the
1553 current PC, and look for those that save registers. */
1554 while (addr
< get_frame_pc (fci
))
1556 inst
= mips_fetch_instruction (addr
);
1557 if (pc_is_mips16 (addr
))
1558 mips16_decode_reg_save (inst
, &gen_save_found
);
1560 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1563 gen_mask
= gen_save_found
;
1564 float_mask
= float_save_found
;
1567 /* Fill in the offsets for the registers which gen_mask says were
1570 CORE_ADDR reg_position
= (get_frame_base (fci
)
1571 + PROC_REG_OFFSET (proc_desc
));
1572 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1573 if (gen_mask
& 0x80000000)
1575 set_reg_offset (saved_regs
, ireg
, reg_position
);
1576 reg_position
-= mips_saved_regsize (tdep
);
1580 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1581 order of that normally used by gcc. Therefore, we have to fetch
1582 the first instruction of the function, and if it's an entry
1583 instruction that saves $s0 or $s1, correct their saved addresses. */
1584 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1586 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1587 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1591 int sreg_count
= (inst
>> 6) & 3;
1593 /* Check if the ra register was pushed on the stack. */
1594 CORE_ADDR reg_position
= (get_frame_base (fci
)
1595 + PROC_REG_OFFSET (proc_desc
));
1597 reg_position
-= mips_saved_regsize (tdep
);
1599 /* Check if the s0 and s1 registers were pushed on the
1601 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1603 set_reg_offset (saved_regs
, reg
, reg_position
);
1604 reg_position
-= mips_saved_regsize (tdep
);
1609 /* Fill in the offsets for the registers which float_mask says were
1612 CORE_ADDR reg_position
= (get_frame_base (fci
)
1613 + PROC_FREG_OFFSET (proc_desc
));
1615 /* Fill in the offsets for the float registers which float_mask
1617 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1618 if (float_mask
& 0x80000000)
1620 if (mips_saved_regsize (tdep
) == 4
1621 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1623 /* On a big endian 32 bit ABI, floating point registers
1624 are paired to form doubles such that the most
1625 significant part is in $f[N+1] and the least
1626 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1627 registers are also spilled as a pair and stored as a
1630 When little-endian the least significant part is
1631 stored first leading to the memory order $f[N] and
1634 Unfortunately, when big-endian the most significant
1635 part of the double is stored first, and the least
1636 significant is stored second. This leads to the
1637 registers being ordered in memory as firt $f[N+1] and
1640 For the big-endian case make certain that the
1641 addresses point at the correct (swapped) locations
1642 $f[N] and $f[N+1] pair (keep in mind that
1643 reg_position is decremented each time through the
1646 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1647 reg_position
- mips_saved_regsize (tdep
));
1649 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1650 reg_position
+ mips_saved_regsize (tdep
));
1653 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
, reg_position
);
1654 reg_position
-= mips_saved_regsize (tdep
);
1657 set_reg_offset (saved_regs
, PC_REGNUM
, saved_regs
[RA_REGNUM
]);
1660 /* SP_REGNUM, contains the value and not the address. */
1661 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1665 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1667 /* Always a pseudo. */
1668 gdb_assert (regno
>= NUM_REGS
);
1672 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1675 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1676 /* The SP_REGNUM is special, its value is stored in saved_regs.
1677 In fact, it is so special that it can even only be fetched
1678 using a raw register number! Once this code as been converted
1679 to frame-unwind the problem goes away. */
1680 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1682 return frame_unwind_register_signed (fi
, regno
);
1686 /* mips_addr_bits_remove - remove useless address bits */
1689 mips_addr_bits_remove (CORE_ADDR addr
)
1691 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1692 if (mips_mask_address_p (tdep
)
1693 && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
1694 /* This hack is a work-around for existing boards using PMON, the
1695 simulator, and any other 64-bit targets that doesn't have true
1696 64-bit addressing. On these targets, the upper 32 bits of
1697 addresses are ignored by the hardware. Thus, the PC or SP are
1698 likely to have been sign extended to all 1s by instruction
1699 sequences that load 32-bit addresses. For example, a typical
1700 piece of code that loads an address is this:
1702 lui $r2, <upper 16 bits>
1703 ori $r2, <lower 16 bits>
1705 But the lui sign-extends the value such that the upper 32 bits
1706 may be all 1s. The workaround is simply to mask off these
1707 bits. In the future, gcc may be changed to support true 64-bit
1708 addressing, and this masking will have to be disabled. */
1709 return addr
&= 0xffffffffUL
;
1714 /* mips_software_single_step() is called just before we want to resume
1715 the inferior, if we want to single-step it but there is no hardware
1716 or kernel single-step support (MIPS on GNU/Linux for example). We find
1717 the target of the coming instruction and breakpoint it.
1719 single_step is also called just after the inferior stops. If we had
1720 set up a simulated single-step, we undo our damage. */
1723 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1725 static CORE_ADDR next_pc
;
1726 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1727 static binsn_quantum break_mem
;
1730 if (insert_breakpoints_p
)
1732 pc
= read_register (PC_REGNUM
);
1733 next_pc
= mips_next_pc (pc
);
1735 target_insert_breakpoint (next_pc
, break_mem
);
1738 target_remove_breakpoint (next_pc
, break_mem
);
1742 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1747 ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev
))
1748 : get_next_frame (prev
)
1749 ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev
))
1751 tmp
= SKIP_TRAMPOLINE_CODE (pc
);
1752 return tmp
? tmp
: pc
;
1757 mips_frame_saved_pc (struct frame_info
*frame
)
1760 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1762 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
1764 /* Always unwind the cooked PC register value. */
1765 saved_pc
= frame_unwind_register_signed (frame
, NUM_REGS
+ PC_REGNUM
);
1769 mips_extra_func_info_t proc_desc
1770 = get_frame_extra_info (frame
)->proc_desc
;
1771 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1772 saved_pc
= read_memory_integer ((get_frame_base (frame
)
1773 - mips_saved_regsize (tdep
))
1774 , mips_saved_regsize (tdep
));
1777 /* We have to get the saved pc from the sigcontext if it is
1778 a signal handler frame. */
1779 int pcreg
= (get_frame_type (frame
) == SIGTRAMP_FRAME
? PC_REGNUM
1780 : proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1781 saved_pc
= read_next_frame_reg (frame
, NUM_REGS
+ pcreg
);
1784 return ADDR_BITS_REMOVE (saved_pc
);
1787 static struct mips_extra_func_info temp_proc_desc
;
1789 /* This hack will go away once the get_prev_frame() code has been
1790 modified to set the frame's type first. That is BEFORE init extra
1791 frame info et.al. is called. This is because it will become
1792 possible to skip the init extra info call for sigtramp and dummy
1794 static CORE_ADDR
*temp_saved_regs
;
1796 /* Set a register's saved stack address in temp_saved_regs. If an
1797 address has already been set for this register, do nothing; this
1798 way we will only recognize the first save of a given register in a
1801 For simplicity, save the address in both [0 .. NUM_REGS) and
1802 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1803 is used as it is only second range (the ABI instead of ISA
1804 registers) that comes into play when finding saved registers in a
1808 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
1810 if (saved_regs
[regno
] == 0)
1812 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
1813 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
1818 /* Test whether the PC points to the return instruction at the
1819 end of a function. */
1822 mips_about_to_return (CORE_ADDR pc
)
1824 if (pc_is_mips16 (pc
))
1825 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1826 generates a "jr $ra"; other times it generates code to load
1827 the return address from the stack to an accessible register (such
1828 as $a3), then a "jr" using that register. This second case
1829 is almost impossible to distinguish from an indirect jump
1830 used for switch statements, so we don't even try. */
1831 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1833 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1837 /* This fencepost looks highly suspicious to me. Removing it also
1838 seems suspicious as it could affect remote debugging across serial
1842 heuristic_proc_start (CORE_ADDR pc
)
1849 pc
= ADDR_BITS_REMOVE (pc
);
1851 fence
= start_pc
- heuristic_fence_post
;
1855 if (heuristic_fence_post
== UINT_MAX
1856 || fence
< VM_MIN_ADDRESS
)
1857 fence
= VM_MIN_ADDRESS
;
1859 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1861 /* search back for previous return */
1862 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1863 if (start_pc
< fence
)
1865 /* It's not clear to me why we reach this point when
1866 stop_soon, but with this test, at least we
1867 don't print out warnings for every child forked (eg, on
1868 decstation). 22apr93 rich@cygnus.com. */
1869 if (stop_soon
== NO_STOP_QUIETLY
)
1871 static int blurb_printed
= 0;
1873 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1878 /* This actually happens frequently in embedded
1879 development, when you first connect to a board
1880 and your stack pointer and pc are nowhere in
1881 particular. This message needs to give people
1882 in that situation enough information to
1883 determine that it's no big deal. */
1884 printf_filtered ("\n\
1885 GDB is unable to find the start of the function at 0x%s\n\
1886 and thus can't determine the size of that function's stack frame.\n\
1887 This means that GDB may be unable to access that stack frame, or\n\
1888 the frames below it.\n\
1889 This problem is most likely caused by an invalid program counter or\n\
1891 However, if you think GDB should simply search farther back\n\
1892 from 0x%s for code which looks like the beginning of a\n\
1893 function, you can increase the range of the search using the `set\n\
1894 heuristic-fence-post' command.\n",
1895 paddr_nz (pc
), paddr_nz (pc
));
1902 else if (pc_is_mips16 (start_pc
))
1904 unsigned short inst
;
1906 /* On MIPS16, any one of the following is likely to be the
1907 start of a function:
1911 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1912 inst
= mips_fetch_instruction (start_pc
);
1913 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1914 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1915 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1916 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1918 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1919 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1924 else if (mips_about_to_return (start_pc
))
1926 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1933 /* Fetch the immediate value from a MIPS16 instruction.
1934 If the previous instruction was an EXTEND, use it to extend
1935 the upper bits of the immediate value. This is a helper function
1936 for mips16_heuristic_proc_desc. */
1939 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1940 unsigned short inst
, /* current instruction */
1941 int nbits
, /* number of bits in imm field */
1942 int scale
, /* scale factor to be applied to imm */
1943 int is_signed
) /* is the imm field signed? */
1947 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1949 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1950 if (offset
& 0x8000) /* check for negative extend */
1951 offset
= 0 - (0x10000 - (offset
& 0xffff));
1952 return offset
| (inst
& 0x1f);
1956 int max_imm
= 1 << nbits
;
1957 int mask
= max_imm
- 1;
1958 int sign_bit
= max_imm
>> 1;
1960 offset
= inst
& mask
;
1961 if (is_signed
&& (offset
& sign_bit
))
1962 offset
= 0 - (max_imm
- offset
);
1963 return offset
* scale
;
1968 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1969 stream from start_pc to limit_pc. */
1972 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1973 struct frame_info
*next_frame
, CORE_ADDR sp
)
1976 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1977 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1978 unsigned inst
= 0; /* current instruction */
1979 unsigned entry_inst
= 0; /* the entry instruction */
1981 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1983 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1984 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1986 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1988 /* Save the previous instruction. If it's an EXTEND, we'll extract
1989 the immediate offset extension from it in mips16_get_imm. */
1992 /* Fetch and decode the instruction. */
1993 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1994 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1995 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1997 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1998 if (offset
< 0) /* negative stack adjustment? */
1999 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2001 /* Exit loop if a positive stack adjustment is found, which
2002 usually means that the stack cleanup code in the function
2003 epilogue is reached. */
2006 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2008 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2009 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2010 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2011 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2013 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2015 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2016 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2017 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2018 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2020 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2022 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2023 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2024 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2026 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2028 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2029 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2030 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2032 else if (inst
== 0x673d) /* move $s1, $sp */
2035 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2037 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2039 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2040 frame_addr
= sp
+ offset
;
2041 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2042 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2044 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2046 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2047 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2048 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2049 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2051 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2053 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2054 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2055 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2056 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2058 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2059 entry_inst
= inst
; /* save for later processing */
2060 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2061 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2064 /* The entry instruction is typically the first instruction in a function,
2065 and it stores registers at offsets relative to the value of the old SP
2066 (before the prologue). But the value of the sp parameter to this
2067 function is the new SP (after the prologue has been executed). So we
2068 can't calculate those offsets until we've seen the entire prologue,
2069 and can calculate what the old SP must have been. */
2070 if (entry_inst
!= 0)
2072 int areg_count
= (entry_inst
>> 8) & 7;
2073 int sreg_count
= (entry_inst
>> 6) & 3;
2075 /* The entry instruction always subtracts 32 from the SP. */
2076 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2078 /* Now we can calculate what the SP must have been at the
2079 start of the function prologue. */
2080 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2082 /* Check if a0-a3 were saved in the caller's argument save area. */
2083 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2085 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2086 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2087 offset
+= mips_saved_regsize (tdep
);
2090 /* Check if the ra register was pushed on the stack. */
2092 if (entry_inst
& 0x20)
2094 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2095 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2096 offset
-= mips_saved_regsize (tdep
);
2099 /* Check if the s0 and s1 registers were pushed on the stack. */
2100 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2102 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2103 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2104 offset
-= mips_saved_regsize (tdep
);
2110 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2111 struct frame_info
*next_frame
, CORE_ADDR sp
)
2114 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2116 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2117 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2118 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2119 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2120 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2122 unsigned long inst
, high_word
, low_word
;
2125 /* Fetch the instruction. */
2126 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2128 /* Save some code by pre-extracting some useful fields. */
2129 high_word
= (inst
>> 16) & 0xffff;
2130 low_word
= inst
& 0xffff;
2131 reg
= high_word
& 0x1f;
2133 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2134 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2135 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2137 if (low_word
& 0x8000) /* negative stack adjustment? */
2138 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2140 /* Exit loop if a positive stack adjustment is found, which
2141 usually means that the stack cleanup code in the function
2142 epilogue is reached. */
2145 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2147 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2148 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2150 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2152 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2153 but the register size used is only 32 bits. Make the address
2154 for the saved register point to the lower 32 bits. */
2155 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2156 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
+ 8 - mips_regsize (current_gdbarch
));
2158 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2160 /* Old gcc frame, r30 is virtual frame pointer. */
2161 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2162 frame_addr
= sp
+ low_word
;
2163 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2165 unsigned alloca_adjust
;
2166 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2167 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2168 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2169 if (alloca_adjust
> 0)
2171 /* FP > SP + frame_size. This may be because
2172 * of an alloca or somethings similar.
2173 * Fix sp to "pre-alloca" value, and try again.
2175 sp
+= alloca_adjust
;
2180 /* move $30,$sp. With different versions of gas this will be either
2181 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2182 Accept any one of these. */
2183 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2185 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2186 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2188 unsigned alloca_adjust
;
2189 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2190 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2191 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2192 if (alloca_adjust
> 0)
2194 /* FP > SP + frame_size. This may be because
2195 * of an alloca or somethings similar.
2196 * Fix sp to "pre-alloca" value, and try again.
2198 sp
+= alloca_adjust
;
2203 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2205 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2206 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2211 static mips_extra_func_info_t
2212 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2213 struct frame_info
*next_frame
, int cur_frame
)
2218 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2224 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2225 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2226 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2227 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2228 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2229 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2231 if (start_pc
+ 200 < limit_pc
)
2232 limit_pc
= start_pc
+ 200;
2233 if (pc_is_mips16 (start_pc
))
2234 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2236 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2237 return &temp_proc_desc
;
2240 struct mips_objfile_private
2246 /* Global used to communicate between non_heuristic_proc_desc and
2247 compare_pdr_entries within qsort (). */
2248 static bfd
*the_bfd
;
2251 compare_pdr_entries (const void *a
, const void *b
)
2253 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2254 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2258 else if (lhs
== rhs
)
2264 static mips_extra_func_info_t
2265 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2267 CORE_ADDR startaddr
;
2268 mips_extra_func_info_t proc_desc
;
2269 struct block
*b
= block_for_pc (pc
);
2271 struct obj_section
*sec
;
2272 struct mips_objfile_private
*priv
;
2274 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2277 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2279 *addrptr
= startaddr
;
2283 sec
= find_pc_section (pc
);
2286 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2288 /* Search the ".pdr" section generated by GAS. This includes most of
2289 the information normally found in ECOFF PDRs. */
2291 the_bfd
= sec
->objfile
->obfd
;
2293 && (the_bfd
->format
== bfd_object
2294 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2295 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2297 /* Right now GAS only outputs the address as a four-byte sequence.
2298 This means that we should not bother with this method on 64-bit
2299 targets (until that is fixed). */
2301 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2302 sizeof (struct mips_objfile_private
));
2304 sec
->objfile
->obj_private
= priv
;
2306 else if (priv
== NULL
)
2310 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2311 sizeof (struct mips_objfile_private
));
2313 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2316 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2317 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2319 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2320 priv
->contents
, 0, priv
->size
);
2322 /* In general, the .pdr section is sorted. However, in the
2323 presence of multiple code sections (and other corner cases)
2324 it can become unsorted. Sort it so that we can use a faster
2326 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
2331 sec
->objfile
->obj_private
= priv
;
2335 if (priv
->size
!= 0)
2341 high
= priv
->size
/ 32;
2347 mid
= (low
+ high
) / 2;
2349 ptr
= priv
->contents
+ mid
* 32;
2350 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2351 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2352 SECT_OFF_TEXT (sec
->objfile
));
2353 if (pdr_pc
== startaddr
)
2355 if (pdr_pc
> startaddr
)
2360 while (low
!= high
);
2364 struct symbol
*sym
= find_pc_function (pc
);
2366 /* Fill in what we need of the proc_desc. */
2367 proc_desc
= (mips_extra_func_info_t
)
2368 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2369 sizeof (struct mips_extra_func_info
));
2370 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2372 /* Only used for dummy frames. */
2373 PROC_HIGH_ADDR (proc_desc
) = 0;
2375 PROC_FRAME_OFFSET (proc_desc
)
2376 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2377 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2379 PROC_FRAME_ADJUST (proc_desc
) = 0;
2380 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2382 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2384 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2386 PROC_FREG_OFFSET (proc_desc
)
2387 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2388 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2390 proc_desc
->pdr
.isym
= (long) sym
;
2400 if (startaddr
> BLOCK_START (b
))
2402 /* This is the "pathological" case referred to in a comment in
2403 print_frame_info. It might be better to move this check into
2408 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2410 /* If we never found a PDR for this function in symbol reading, then
2411 examine prologues to find the information. */
2414 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2415 if (PROC_FRAME_REG (proc_desc
) == -1)
2425 static mips_extra_func_info_t
2426 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2428 mips_extra_func_info_t proc_desc
;
2429 CORE_ADDR startaddr
= 0;
2431 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2435 /* IF this is the topmost frame AND
2436 * (this proc does not have debugging information OR
2437 * the PC is in the procedure prologue)
2438 * THEN create a "heuristic" proc_desc (by analyzing
2439 * the actual code) to replace the "official" proc_desc.
2441 if (next_frame
== NULL
)
2443 struct symtab_and_line val
;
2444 struct symbol
*proc_symbol
=
2445 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2449 val
= find_pc_line (BLOCK_START
2450 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2452 val
.pc
= val
.end
? val
.end
: pc
;
2454 if (!proc_symbol
|| pc
< val
.pc
)
2456 mips_extra_func_info_t found_heuristic
=
2457 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2458 pc
, next_frame
, cur_frame
);
2459 if (found_heuristic
)
2460 proc_desc
= found_heuristic
;
2466 /* Is linked_proc_desc_table really necessary? It only seems to be used
2467 by procedure call dummys. However, the procedures being called ought
2468 to have their own proc_descs, and even if they don't,
2469 heuristic_proc_desc knows how to create them! */
2471 struct linked_proc_info
*link
;
2473 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2474 if (PROC_LOW_ADDR (&link
->info
) <= pc
2475 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2479 startaddr
= heuristic_proc_start (pc
);
2482 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2488 get_frame_pointer (struct frame_info
*frame
,
2489 mips_extra_func_info_t proc_desc
)
2491 return (read_next_frame_reg (frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2492 + PROC_FRAME_OFFSET (proc_desc
)
2493 - PROC_FRAME_ADJUST (proc_desc
));
2496 static mips_extra_func_info_t cached_proc_desc
;
2499 mips_frame_chain (struct frame_info
*frame
)
2501 mips_extra_func_info_t proc_desc
;
2503 CORE_ADDR saved_pc
= DEPRECATED_FRAME_SAVED_PC (frame
);
2505 /* Check if the PC is inside a call stub. If it is, fetch the
2506 PC of the caller of that stub. */
2507 if ((tmp
= SKIP_TRAMPOLINE_CODE (saved_pc
)) != 0)
2510 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc
, 0, 0))
2512 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2513 is well, frame->frame the bottom of the current frame will
2514 contain that value. */
2515 return get_frame_base (frame
);
2518 /* Look up the procedure descriptor for this PC. */
2519 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2523 cached_proc_desc
= proc_desc
;
2525 /* If no frame pointer and frame size is zero, we must be at end
2526 of stack (or otherwise hosed). If we don't check frame size,
2527 we loop forever if we see a zero size frame. */
2528 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2529 && PROC_FRAME_OFFSET (proc_desc
) == 0
2530 /* The previous frame from a sigtramp frame might be frameless
2531 and have frame size zero. */
2532 && !(get_frame_type (frame
) == SIGTRAMP_FRAME
)
2533 /* For a generic dummy frame, let get_frame_pointer() unwind a
2534 register value saved as part of the dummy frame call. */
2535 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0)))
2538 return get_frame_pointer (frame
, proc_desc
);
2542 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2545 mips_extra_func_info_t proc_desc
;
2547 if (get_frame_type (fci
) == DUMMY_FRAME
)
2550 /* Use proc_desc calculated in frame_chain. When there is no
2551 next frame, i.e, get_next_frame (fci) == NULL, we call
2552 find_proc_desc () to calculate it, passing an explicit
2553 NULL as the frame parameter. */
2555 get_next_frame (fci
)
2557 : find_proc_desc (get_frame_pc (fci
),
2558 NULL
/* i.e, get_next_frame (fci) */,
2561 frame_extra_info_zalloc (fci
, sizeof (struct frame_extra_info
));
2563 get_frame_extra_info (fci
)->proc_desc
=
2564 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2567 /* Fixup frame-pointer - only needed for top frame */
2568 /* This may not be quite right, if proc has a real frame register.
2569 Get the value of the frame relative sp, procedure might have been
2570 interrupted by a signal at it's very start. */
2571 if (get_frame_pc (fci
) == PROC_LOW_ADDR (proc_desc
)
2572 && !PROC_DESC_IS_DUMMY (proc_desc
))
2573 deprecated_update_frame_base_hack (fci
, read_next_frame_reg (get_next_frame (fci
), NUM_REGS
+ SP_REGNUM
));
2574 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci
), 0, 0))
2575 /* Do not ``fix'' fci->frame. It will have the value of the
2576 generic dummy frame's top-of-stack (since the draft
2577 fci->frame is obtained by returning the unwound stack
2578 pointer) and that is what we want. That way the fci->frame
2579 value will match the top-of-stack value that was saved as
2580 part of the dummy frames data. */
2583 deprecated_update_frame_base_hack (fci
, get_frame_pointer (get_next_frame (fci
), proc_desc
));
2585 if (proc_desc
== &temp_proc_desc
)
2589 /* Do not set the saved registers for a sigtramp frame,
2590 mips_find_saved_registers will do that for us. We can't
2591 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2593 /* FIXME: cagney/2002-11-18: This problem will go away once
2594 frame.c:get_prev_frame() is modified to set the frame's
2595 type before calling functions like this. */
2596 find_pc_partial_function (get_frame_pc (fci
), &name
,
2597 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2598 if (!PC_IN_SIGTRAMP (get_frame_pc (fci
), name
))
2600 frame_saved_regs_zalloc (fci
);
2601 /* Set value of previous frame's stack pointer.
2602 Remember that saved_regs[SP_REGNUM] is special in
2603 that it contains the value of the stack pointer
2604 register. The other saved_regs values are addresses
2605 (in the inferior) at which a given register's value
2607 set_reg_offset (temp_saved_regs
, SP_REGNUM
,
2608 get_frame_base (fci
));
2609 set_reg_offset (temp_saved_regs
, PC_REGNUM
,
2610 temp_saved_regs
[RA_REGNUM
]);
2611 memcpy (deprecated_get_frame_saved_regs (fci
), temp_saved_regs
,
2612 SIZEOF_FRAME_SAVED_REGS
);
2616 /* hack: if argument regs are saved, guess these contain args */
2617 /* assume we can't tell how many args for now */
2618 get_frame_extra_info (fci
)->num_args
= -1;
2619 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2621 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2623 get_frame_extra_info (fci
)->num_args
= regnum
- A0_REGNUM
+ 1;
2630 /* MIPS stack frames are almost impenetrable. When execution stops,
2631 we basically have to look at symbol information for the function
2632 that we stopped in, which tells us *which* register (if any) is
2633 the base of the frame pointer, and what offset from that register
2634 the frame itself is at.
2636 This presents a problem when trying to examine a stack in memory
2637 (that isn't executing at the moment), using the "frame" command. We
2638 don't have a PC, nor do we have any registers except SP.
2640 This routine takes two arguments, SP and PC, and tries to make the
2641 cached frames look as if these two arguments defined a frame on the
2642 cache. This allows the rest of info frame to extract the important
2643 arguments without difficulty. */
2646 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2649 error ("MIPS frame specifications require two arguments: sp and pc");
2651 return create_new_frame (argv
[0], argv
[1]);
2654 /* According to the current ABI, should the type be passed in a
2655 floating-point register (assuming that there is space)? When there
2656 is no FPU, FP are not even considered as possibile candidates for
2657 FP registers and, consequently this returns false - forces FP
2658 arguments into integer registers. */
2661 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2663 return ((typecode
== TYPE_CODE_FLT
2665 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2666 && TYPE_NFIELDS (arg_type
) == 1
2667 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2668 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2671 /* On o32, argument passing in GPRs depends on the alignment of the type being
2672 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2675 mips_type_needs_double_align (struct type
*type
)
2677 enum type_code typecode
= TYPE_CODE (type
);
2679 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2681 else if (typecode
== TYPE_CODE_STRUCT
)
2683 if (TYPE_NFIELDS (type
) < 1)
2685 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2687 else if (typecode
== TYPE_CODE_UNION
)
2691 n
= TYPE_NFIELDS (type
);
2692 for (i
= 0; i
< n
; i
++)
2693 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2700 /* Adjust the address downward (direction of stack growth) so that it
2701 is correctly aligned for a new stack frame. */
2703 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2705 return align_down (addr
, 16);
2709 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2710 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2711 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2712 CORE_ADDR struct_addr
)
2718 int stack_offset
= 0;
2719 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2721 /* For shared libraries, "t9" needs to point at the function
2723 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2725 /* Set the return address register to point to the entry point of
2726 the program, where a breakpoint lies in wait. */
2727 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2729 /* First ensure that the stack and structure return address (if any)
2730 are properly aligned. The stack has to be at least 64-bit
2731 aligned even on 32-bit machines, because doubles must be 64-bit
2732 aligned. For n32 and n64, stack frames need to be 128-bit
2733 aligned, so we round to this widest known alignment. */
2735 sp
= align_down (sp
, 16);
2736 struct_addr
= align_down (struct_addr
, 16);
2738 /* Now make space on the stack for the args. We allocate more
2739 than necessary for EABI, because the first few arguments are
2740 passed in registers, but that's OK. */
2741 for (argnum
= 0; argnum
< nargs
; argnum
++)
2742 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2743 mips_stack_argsize (tdep
));
2744 sp
-= align_up (len
, 16);
2747 fprintf_unfiltered (gdb_stdlog
,
2748 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2749 paddr_nz (sp
), (long) align_up (len
, 16));
2751 /* Initialize the integer and float register pointers. */
2753 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2755 /* The struct_return pointer occupies the first parameter-passing reg. */
2759 fprintf_unfiltered (gdb_stdlog
,
2760 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2761 argreg
, paddr_nz (struct_addr
));
2762 write_register (argreg
++, struct_addr
);
2765 /* Now load as many as possible of the first arguments into
2766 registers, and push the rest onto the stack. Loop thru args
2767 from first to last. */
2768 for (argnum
= 0; argnum
< nargs
; argnum
++)
2771 char valbuf
[MAX_REGISTER_SIZE
];
2772 struct value
*arg
= args
[argnum
];
2773 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2774 int len
= TYPE_LENGTH (arg_type
);
2775 enum type_code typecode
= TYPE_CODE (arg_type
);
2778 fprintf_unfiltered (gdb_stdlog
,
2779 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2780 argnum
+ 1, len
, (int) typecode
);
2782 /* The EABI passes structures that do not fit in a register by
2784 if (len
> mips_saved_regsize (tdep
)
2785 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2787 store_unsigned_integer (valbuf
, mips_saved_regsize (tdep
),
2788 VALUE_ADDRESS (arg
));
2789 typecode
= TYPE_CODE_PTR
;
2790 len
= mips_saved_regsize (tdep
);
2793 fprintf_unfiltered (gdb_stdlog
, " push");
2796 val
= (char *) VALUE_CONTENTS (arg
);
2798 /* 32-bit ABIs always start floating point arguments in an
2799 even-numbered floating point register. Round the FP register
2800 up before the check to see if there are any FP registers
2801 left. Non MIPS_EABI targets also pass the FP in the integer
2802 registers so also round up normal registers. */
2803 if (!FP_REGISTER_DOUBLE
2804 && fp_register_arg_p (typecode
, arg_type
))
2806 if ((float_argreg
& 1))
2810 /* Floating point arguments passed in registers have to be
2811 treated specially. On 32-bit architectures, doubles
2812 are passed in register pairs; the even register gets
2813 the low word, and the odd register gets the high word.
2814 On non-EABI processors, the first two floating point arguments are
2815 also copied to general registers, because MIPS16 functions
2816 don't use float registers for arguments. This duplication of
2817 arguments in general registers can't hurt non-MIPS16 functions
2818 because those registers are normally skipped. */
2819 /* MIPS_EABI squeezes a struct that contains a single floating
2820 point value into an FP register instead of pushing it onto the
2822 if (fp_register_arg_p (typecode
, arg_type
)
2823 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2825 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2827 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2828 unsigned long regval
;
2830 /* Write the low word of the double to the even register(s). */
2831 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2833 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2834 float_argreg
, phex (regval
, 4));
2835 write_register (float_argreg
++, regval
);
2837 /* Write the high word of the double to the odd register(s). */
2838 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2840 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2841 float_argreg
, phex (regval
, 4));
2842 write_register (float_argreg
++, regval
);
2846 /* This is a floating point value that fits entirely
2847 in a single register. */
2848 /* On 32 bit ABI's the float_argreg is further adjusted
2849 above to ensure that it is even register aligned. */
2850 LONGEST regval
= extract_unsigned_integer (val
, len
);
2852 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2853 float_argreg
, phex (regval
, len
));
2854 write_register (float_argreg
++, regval
);
2859 /* Copy the argument to general registers or the stack in
2860 register-sized pieces. Large arguments are split between
2861 registers and stack. */
2862 /* Note: structs whose size is not a multiple of
2863 mips_regsize() are treated specially: Irix cc passes them
2864 in registers where gcc sometimes puts them on the stack.
2865 For maximum compatibility, we will put them in both
2867 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
2868 && (len
% mips_saved_regsize (tdep
) != 0));
2870 /* Note: Floating-point values that didn't fit into an FP
2871 register are only written to memory. */
2874 /* Remember if the argument was written to the stack. */
2875 int stack_used_p
= 0;
2876 int partial_len
= (len
< mips_saved_regsize (tdep
)
2877 ? len
: mips_saved_regsize (tdep
));
2880 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2883 /* Write this portion of the argument to the stack. */
2884 if (argreg
> MIPS_LAST_ARG_REGNUM
2886 || fp_register_arg_p (typecode
, arg_type
))
2888 /* Should shorter than int integer values be
2889 promoted to int before being stored? */
2890 int longword_offset
= 0;
2893 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2895 if (mips_stack_argsize (tdep
) == 8
2896 && (typecode
== TYPE_CODE_INT
2897 || typecode
== TYPE_CODE_PTR
2898 || typecode
== TYPE_CODE_FLT
)
2900 longword_offset
= mips_stack_argsize (tdep
) - len
;
2901 else if ((typecode
== TYPE_CODE_STRUCT
2902 || typecode
== TYPE_CODE_UNION
)
2903 && (TYPE_LENGTH (arg_type
)
2904 < mips_stack_argsize (tdep
)))
2905 longword_offset
= mips_stack_argsize (tdep
) - len
;
2910 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2911 paddr_nz (stack_offset
));
2912 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2913 paddr_nz (longword_offset
));
2916 addr
= sp
+ stack_offset
+ longword_offset
;
2921 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2923 for (i
= 0; i
< partial_len
; i
++)
2925 fprintf_unfiltered (gdb_stdlog
, "%02x",
2929 write_memory (addr
, val
, partial_len
);
2932 /* Note!!! This is NOT an else clause. Odd sized
2933 structs may go thru BOTH paths. Floating point
2934 arguments will not. */
2935 /* Write this portion of the argument to a general
2936 purpose register. */
2937 if (argreg
<= MIPS_LAST_ARG_REGNUM
2938 && !fp_register_arg_p (typecode
, arg_type
))
2940 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2943 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2945 phex (regval
, mips_saved_regsize (tdep
)));
2946 write_register (argreg
, regval
);
2953 /* Compute the the offset into the stack at which we
2954 will copy the next parameter.
2956 In the new EABI (and the NABI32), the stack_offset
2957 only needs to be adjusted when it has been used. */
2960 stack_offset
+= align_up (partial_len
,
2961 mips_stack_argsize (tdep
));
2965 fprintf_unfiltered (gdb_stdlog
, "\n");
2968 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
2970 /* Return adjusted stack pointer. */
2974 /* N32/N64 version of push_dummy_call. */
2977 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2978 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2979 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2980 CORE_ADDR struct_addr
)
2986 int stack_offset
= 0;
2987 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2989 /* For shared libraries, "t9" needs to point at the function
2991 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2993 /* Set the return address register to point to the entry point of
2994 the program, where a breakpoint lies in wait. */
2995 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2997 /* First ensure that the stack and structure return address (if any)
2998 are properly aligned. The stack has to be at least 64-bit
2999 aligned even on 32-bit machines, because doubles must be 64-bit
3000 aligned. For n32 and n64, stack frames need to be 128-bit
3001 aligned, so we round to this widest known alignment. */
3003 sp
= align_down (sp
, 16);
3004 struct_addr
= align_down (struct_addr
, 16);
3006 /* Now make space on the stack for the args. */
3007 for (argnum
= 0; argnum
< nargs
; argnum
++)
3008 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3009 mips_stack_argsize (tdep
));
3010 sp
-= align_up (len
, 16);
3013 fprintf_unfiltered (gdb_stdlog
,
3014 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3015 paddr_nz (sp
), (long) align_up (len
, 16));
3017 /* Initialize the integer and float register pointers. */
3019 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3021 /* The struct_return pointer occupies the first parameter-passing reg. */
3025 fprintf_unfiltered (gdb_stdlog
,
3026 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3027 argreg
, paddr_nz (struct_addr
));
3028 write_register (argreg
++, struct_addr
);
3031 /* Now load as many as possible of the first arguments into
3032 registers, and push the rest onto the stack. Loop thru args
3033 from first to last. */
3034 for (argnum
= 0; argnum
< nargs
; argnum
++)
3037 char valbuf
[MAX_REGISTER_SIZE
];
3038 struct value
*arg
= args
[argnum
];
3039 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3040 int len
= TYPE_LENGTH (arg_type
);
3041 enum type_code typecode
= TYPE_CODE (arg_type
);
3044 fprintf_unfiltered (gdb_stdlog
,
3045 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3046 argnum
+ 1, len
, (int) typecode
);
3048 val
= (char *) VALUE_CONTENTS (arg
);
3050 if (fp_register_arg_p (typecode
, arg_type
)
3051 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3053 /* This is a floating point value that fits entirely
3054 in a single register. */
3055 /* On 32 bit ABI's the float_argreg is further adjusted
3056 above to ensure that it is even register aligned. */
3057 LONGEST regval
= extract_unsigned_integer (val
, len
);
3059 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3060 float_argreg
, phex (regval
, len
));
3061 write_register (float_argreg
++, regval
);
3064 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3065 argreg
, phex (regval
, len
));
3066 write_register (argreg
, regval
);
3071 /* Copy the argument to general registers or the stack in
3072 register-sized pieces. Large arguments are split between
3073 registers and stack. */
3074 /* Note: structs whose size is not a multiple of
3075 mips_regsize() are treated specially: Irix cc passes them
3076 in registers where gcc sometimes puts them on the stack.
3077 For maximum compatibility, we will put them in both
3079 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3080 && (len
% mips_saved_regsize (tdep
) != 0));
3081 /* Note: Floating-point values that didn't fit into an FP
3082 register are only written to memory. */
3085 /* Rememer if the argument was written to the stack. */
3086 int stack_used_p
= 0;
3087 int partial_len
= (len
< mips_saved_regsize (tdep
)
3088 ? len
: mips_saved_regsize (tdep
));
3091 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3094 /* Write this portion of the argument to the stack. */
3095 if (argreg
> MIPS_LAST_ARG_REGNUM
3097 || fp_register_arg_p (typecode
, arg_type
))
3099 /* Should shorter than int integer values be
3100 promoted to int before being stored? */
3101 int longword_offset
= 0;
3104 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3106 if (mips_stack_argsize (tdep
) == 8
3107 && (typecode
== TYPE_CODE_INT
3108 || typecode
== TYPE_CODE_PTR
3109 || typecode
== TYPE_CODE_FLT
)
3111 longword_offset
= mips_stack_argsize (tdep
) - len
;
3116 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3117 paddr_nz (stack_offset
));
3118 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3119 paddr_nz (longword_offset
));
3122 addr
= sp
+ stack_offset
+ longword_offset
;
3127 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3129 for (i
= 0; i
< partial_len
; i
++)
3131 fprintf_unfiltered (gdb_stdlog
, "%02x",
3135 write_memory (addr
, val
, partial_len
);
3138 /* Note!!! This is NOT an else clause. Odd sized
3139 structs may go thru BOTH paths. Floating point
3140 arguments will not. */
3141 /* Write this portion of the argument to a general
3142 purpose register. */
3143 if (argreg
<= MIPS_LAST_ARG_REGNUM
3144 && !fp_register_arg_p (typecode
, arg_type
))
3146 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
3148 /* A non-floating-point argument being passed in a
3149 general register. If a struct or union, and if
3150 the remaining length is smaller than the register
3151 size, we have to adjust the register value on
3154 It does not seem to be necessary to do the
3155 same for integral types.
3157 cagney/2001-07-23: gdb/179: Also, GCC, when
3158 outputting LE O32 with sizeof (struct) <
3159 mips_saved_regsize(), generates a left shift as
3160 part of storing the argument in a register a
3161 register (the left shift isn't generated when
3162 sizeof (struct) >= mips_saved_regsize()). Since
3163 it is quite possible that this is GCC
3164 contradicting the LE/O32 ABI, GDB has not been
3165 adjusted to accommodate this. Either someone
3166 needs to demonstrate that the LE/O32 ABI
3167 specifies such a left shift OR this new ABI gets
3168 identified as such and GDB gets tweaked
3171 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3172 && partial_len
< mips_saved_regsize (tdep
)
3173 && (typecode
== TYPE_CODE_STRUCT
||
3174 typecode
== TYPE_CODE_UNION
))
3175 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3179 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3181 phex (regval
, mips_saved_regsize (tdep
)));
3182 write_register (argreg
, regval
);
3189 /* Compute the the offset into the stack at which we
3190 will copy the next parameter.
3192 In N32 (N64?), the stack_offset only needs to be
3193 adjusted when it has been used. */
3196 stack_offset
+= align_up (partial_len
,
3197 mips_stack_argsize (tdep
));
3201 fprintf_unfiltered (gdb_stdlog
, "\n");
3204 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3206 /* Return adjusted stack pointer. */
3210 /* O32 version of push_dummy_call. */
3213 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3214 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3215 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3216 CORE_ADDR struct_addr
)
3222 int stack_offset
= 0;
3223 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3225 /* For shared libraries, "t9" needs to point at the function
3227 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3229 /* Set the return address register to point to the entry point of
3230 the program, where a breakpoint lies in wait. */
3231 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3233 /* First ensure that the stack and structure return address (if any)
3234 are properly aligned. The stack has to be at least 64-bit
3235 aligned even on 32-bit machines, because doubles must be 64-bit
3236 aligned. For n32 and n64, stack frames need to be 128-bit
3237 aligned, so we round to this widest known alignment. */
3239 sp
= align_down (sp
, 16);
3240 struct_addr
= align_down (struct_addr
, 16);
3242 /* Now make space on the stack for the args. */
3243 for (argnum
= 0; argnum
< nargs
; argnum
++)
3244 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3245 mips_stack_argsize (tdep
));
3246 sp
-= align_up (len
, 16);
3249 fprintf_unfiltered (gdb_stdlog
,
3250 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3251 paddr_nz (sp
), (long) align_up (len
, 16));
3253 /* Initialize the integer and float register pointers. */
3255 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3257 /* The struct_return pointer occupies the first parameter-passing reg. */
3261 fprintf_unfiltered (gdb_stdlog
,
3262 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3263 argreg
, paddr_nz (struct_addr
));
3264 write_register (argreg
++, struct_addr
);
3265 stack_offset
+= mips_stack_argsize (tdep
);
3268 /* Now load as many as possible of the first arguments into
3269 registers, and push the rest onto the stack. Loop thru args
3270 from first to last. */
3271 for (argnum
= 0; argnum
< nargs
; argnum
++)
3274 char valbuf
[MAX_REGISTER_SIZE
];
3275 struct value
*arg
= args
[argnum
];
3276 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3277 int len
= TYPE_LENGTH (arg_type
);
3278 enum type_code typecode
= TYPE_CODE (arg_type
);
3281 fprintf_unfiltered (gdb_stdlog
,
3282 "mips_o32_push_dummy_call: %d len=%d type=%d",
3283 argnum
+ 1, len
, (int) typecode
);
3285 val
= (char *) VALUE_CONTENTS (arg
);
3287 /* 32-bit ABIs always start floating point arguments in an
3288 even-numbered floating point register. Round the FP register
3289 up before the check to see if there are any FP registers
3290 left. O32/O64 targets also pass the FP in the integer
3291 registers so also round up normal registers. */
3292 if (!FP_REGISTER_DOUBLE
3293 && fp_register_arg_p (typecode
, arg_type
))
3295 if ((float_argreg
& 1))
3299 /* Floating point arguments passed in registers have to be
3300 treated specially. On 32-bit architectures, doubles
3301 are passed in register pairs; the even register gets
3302 the low word, and the odd register gets the high word.
3303 On O32/O64, the first two floating point arguments are
3304 also copied to general registers, because MIPS16 functions
3305 don't use float registers for arguments. This duplication of
3306 arguments in general registers can't hurt non-MIPS16 functions
3307 because those registers are normally skipped. */
3309 if (fp_register_arg_p (typecode
, arg_type
)
3310 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3312 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3314 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3315 unsigned long regval
;
3317 /* Write the low word of the double to the even register(s). */
3318 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3320 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3321 float_argreg
, phex (regval
, 4));
3322 write_register (float_argreg
++, regval
);
3324 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3325 argreg
, phex (regval
, 4));
3326 write_register (argreg
++, regval
);
3328 /* Write the high word of the double to the odd register(s). */
3329 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3331 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3332 float_argreg
, phex (regval
, 4));
3333 write_register (float_argreg
++, regval
);
3336 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3337 argreg
, phex (regval
, 4));
3338 write_register (argreg
++, regval
);
3342 /* This is a floating point value that fits entirely
3343 in a single register. */
3344 /* On 32 bit ABI's the float_argreg is further adjusted
3345 above to ensure that it is even register aligned. */
3346 LONGEST regval
= extract_unsigned_integer (val
, len
);
3348 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3349 float_argreg
, phex (regval
, len
));
3350 write_register (float_argreg
++, regval
);
3351 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3352 registers for each argument. The below is (my
3353 guess) to ensure that the corresponding integer
3354 register has reserved the same space. */
3356 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3357 argreg
, phex (regval
, len
));
3358 write_register (argreg
, regval
);
3359 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3361 /* Reserve space for the FP register. */
3362 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
3366 /* Copy the argument to general registers or the stack in
3367 register-sized pieces. Large arguments are split between
3368 registers and stack. */
3369 /* Note: structs whose size is not a multiple of
3370 mips_regsize() are treated specially: Irix cc passes them
3371 in registers where gcc sometimes puts them on the stack.
3372 For maximum compatibility, we will put them in both
3374 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3375 && (len
% mips_saved_regsize (tdep
) != 0));
3376 /* Structures should be aligned to eight bytes (even arg registers)
3377 on MIPS_ABI_O32, if their first member has double precision. */
3378 if (mips_saved_regsize (tdep
) < 8
3379 && mips_type_needs_double_align (arg_type
))
3384 /* Note: Floating-point values that didn't fit into an FP
3385 register are only written to memory. */
3388 /* Remember if the argument was written to the stack. */
3389 int stack_used_p
= 0;
3390 int partial_len
= (len
< mips_saved_regsize (tdep
)
3391 ? len
: mips_saved_regsize (tdep
));
3394 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3397 /* Write this portion of the argument to the stack. */
3398 if (argreg
> MIPS_LAST_ARG_REGNUM
3400 || fp_register_arg_p (typecode
, arg_type
))
3402 /* Should shorter than int integer values be
3403 promoted to int before being stored? */
3404 int longword_offset
= 0;
3407 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3409 if (mips_stack_argsize (tdep
) == 8
3410 && (typecode
== TYPE_CODE_INT
3411 || typecode
== TYPE_CODE_PTR
3412 || typecode
== TYPE_CODE_FLT
)
3414 longword_offset
= mips_stack_argsize (tdep
) - len
;
3419 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3420 paddr_nz (stack_offset
));
3421 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3422 paddr_nz (longword_offset
));
3425 addr
= sp
+ stack_offset
+ longword_offset
;
3430 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3432 for (i
= 0; i
< partial_len
; i
++)
3434 fprintf_unfiltered (gdb_stdlog
, "%02x",
3438 write_memory (addr
, val
, partial_len
);
3441 /* Note!!! This is NOT an else clause. Odd sized
3442 structs may go thru BOTH paths. Floating point
3443 arguments will not. */
3444 /* Write this portion of the argument to a general
3445 purpose register. */
3446 if (argreg
<= MIPS_LAST_ARG_REGNUM
3447 && !fp_register_arg_p (typecode
, arg_type
))
3449 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3450 /* Value may need to be sign extended, because
3451 mips_regsize() != mips_saved_regsize(). */
3453 /* A non-floating-point argument being passed in a
3454 general register. If a struct or union, and if
3455 the remaining length is smaller than the register
3456 size, we have to adjust the register value on
3459 It does not seem to be necessary to do the
3460 same for integral types.
3462 Also don't do this adjustment on O64 binaries.
3464 cagney/2001-07-23: gdb/179: Also, GCC, when
3465 outputting LE O32 with sizeof (struct) <
3466 mips_saved_regsize(), generates a left shift as
3467 part of storing the argument in a register a
3468 register (the left shift isn't generated when
3469 sizeof (struct) >= mips_saved_regsize()). Since
3470 it is quite possible that this is GCC
3471 contradicting the LE/O32 ABI, GDB has not been
3472 adjusted to accommodate this. Either someone
3473 needs to demonstrate that the LE/O32 ABI
3474 specifies such a left shift OR this new ABI gets
3475 identified as such and GDB gets tweaked
3478 if (mips_saved_regsize (tdep
) < 8
3479 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3480 && partial_len
< mips_saved_regsize (tdep
)
3481 && (typecode
== TYPE_CODE_STRUCT
||
3482 typecode
== TYPE_CODE_UNION
))
3483 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3487 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3489 phex (regval
, mips_saved_regsize (tdep
)));
3490 write_register (argreg
, regval
);
3493 /* Prevent subsequent floating point arguments from
3494 being passed in floating point registers. */
3495 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3501 /* Compute the the offset into the stack at which we
3502 will copy the next parameter.
3504 In older ABIs, the caller reserved space for
3505 registers that contained arguments. This was loosely
3506 refered to as their "home". Consequently, space is
3507 always allocated. */
3509 stack_offset
+= align_up (partial_len
,
3510 mips_stack_argsize (tdep
));
3514 fprintf_unfiltered (gdb_stdlog
, "\n");
3517 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3519 /* Return adjusted stack pointer. */
3523 /* O64 version of push_dummy_call. */
3526 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3527 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3528 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3529 CORE_ADDR struct_addr
)
3535 int stack_offset
= 0;
3536 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3538 /* For shared libraries, "t9" needs to point at the function
3540 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3542 /* Set the return address register to point to the entry point of
3543 the program, where a breakpoint lies in wait. */
3544 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3546 /* First ensure that the stack and structure return address (if any)
3547 are properly aligned. The stack has to be at least 64-bit
3548 aligned even on 32-bit machines, because doubles must be 64-bit
3549 aligned. For n32 and n64, stack frames need to be 128-bit
3550 aligned, so we round to this widest known alignment. */
3552 sp
= align_down (sp
, 16);
3553 struct_addr
= align_down (struct_addr
, 16);
3555 /* Now make space on the stack for the args. */
3556 for (argnum
= 0; argnum
< nargs
; argnum
++)
3557 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3558 mips_stack_argsize (tdep
));
3559 sp
-= align_up (len
, 16);
3562 fprintf_unfiltered (gdb_stdlog
,
3563 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3564 paddr_nz (sp
), (long) align_up (len
, 16));
3566 /* Initialize the integer and float register pointers. */
3568 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3570 /* The struct_return pointer occupies the first parameter-passing reg. */
3574 fprintf_unfiltered (gdb_stdlog
,
3575 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3576 argreg
, paddr_nz (struct_addr
));
3577 write_register (argreg
++, struct_addr
);
3578 stack_offset
+= mips_stack_argsize (tdep
);
3581 /* Now load as many as possible of the first arguments into
3582 registers, and push the rest onto the stack. Loop thru args
3583 from first to last. */
3584 for (argnum
= 0; argnum
< nargs
; argnum
++)
3587 char valbuf
[MAX_REGISTER_SIZE
];
3588 struct value
*arg
= args
[argnum
];
3589 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3590 int len
= TYPE_LENGTH (arg_type
);
3591 enum type_code typecode
= TYPE_CODE (arg_type
);
3594 fprintf_unfiltered (gdb_stdlog
,
3595 "mips_o64_push_dummy_call: %d len=%d type=%d",
3596 argnum
+ 1, len
, (int) typecode
);
3598 val
= (char *) VALUE_CONTENTS (arg
);
3600 /* 32-bit ABIs always start floating point arguments in an
3601 even-numbered floating point register. Round the FP register
3602 up before the check to see if there are any FP registers
3603 left. O32/O64 targets also pass the FP in the integer
3604 registers so also round up normal registers. */
3605 if (!FP_REGISTER_DOUBLE
3606 && fp_register_arg_p (typecode
, arg_type
))
3608 if ((float_argreg
& 1))
3612 /* Floating point arguments passed in registers have to be
3613 treated specially. On 32-bit architectures, doubles
3614 are passed in register pairs; the even register gets
3615 the low word, and the odd register gets the high word.
3616 On O32/O64, the first two floating point arguments are
3617 also copied to general registers, because MIPS16 functions
3618 don't use float registers for arguments. This duplication of
3619 arguments in general registers can't hurt non-MIPS16 functions
3620 because those registers are normally skipped. */
3622 if (fp_register_arg_p (typecode
, arg_type
)
3623 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3625 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3627 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3628 unsigned long regval
;
3630 /* Write the low word of the double to the even register(s). */
3631 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3633 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3634 float_argreg
, phex (regval
, 4));
3635 write_register (float_argreg
++, regval
);
3637 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3638 argreg
, phex (regval
, 4));
3639 write_register (argreg
++, regval
);
3641 /* Write the high word of the double to the odd register(s). */
3642 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3644 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3645 float_argreg
, phex (regval
, 4));
3646 write_register (float_argreg
++, regval
);
3649 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3650 argreg
, phex (regval
, 4));
3651 write_register (argreg
++, regval
);
3655 /* This is a floating point value that fits entirely
3656 in a single register. */
3657 /* On 32 bit ABI's the float_argreg is further adjusted
3658 above to ensure that it is even register aligned. */
3659 LONGEST regval
= extract_unsigned_integer (val
, len
);
3661 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3662 float_argreg
, phex (regval
, len
));
3663 write_register (float_argreg
++, regval
);
3664 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3665 registers for each argument. The below is (my
3666 guess) to ensure that the corresponding integer
3667 register has reserved the same space. */
3669 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3670 argreg
, phex (regval
, len
));
3671 write_register (argreg
, regval
);
3672 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3674 /* Reserve space for the FP register. */
3675 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
3679 /* Copy the argument to general registers or the stack in
3680 register-sized pieces. Large arguments are split between
3681 registers and stack. */
3682 /* Note: structs whose size is not a multiple of
3683 mips_regsize() are treated specially: Irix cc passes them
3684 in registers where gcc sometimes puts them on the stack.
3685 For maximum compatibility, we will put them in both
3687 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3688 && (len
% mips_saved_regsize (tdep
) != 0));
3689 /* Structures should be aligned to eight bytes (even arg registers)
3690 on MIPS_ABI_O32, if their first member has double precision. */
3691 if (mips_saved_regsize (tdep
) < 8
3692 && mips_type_needs_double_align (arg_type
))
3697 /* Note: Floating-point values that didn't fit into an FP
3698 register are only written to memory. */
3701 /* Remember if the argument was written to the stack. */
3702 int stack_used_p
= 0;
3703 int partial_len
= (len
< mips_saved_regsize (tdep
)
3704 ? len
: mips_saved_regsize (tdep
));
3707 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3710 /* Write this portion of the argument to the stack. */
3711 if (argreg
> MIPS_LAST_ARG_REGNUM
3713 || fp_register_arg_p (typecode
, arg_type
))
3715 /* Should shorter than int integer values be
3716 promoted to int before being stored? */
3717 int longword_offset
= 0;
3720 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3722 if (mips_stack_argsize (tdep
) == 8
3723 && (typecode
== TYPE_CODE_INT
3724 || typecode
== TYPE_CODE_PTR
3725 || typecode
== TYPE_CODE_FLT
)
3727 longword_offset
= mips_stack_argsize (tdep
) - len
;
3732 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3733 paddr_nz (stack_offset
));
3734 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3735 paddr_nz (longword_offset
));
3738 addr
= sp
+ stack_offset
+ longword_offset
;
3743 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3745 for (i
= 0; i
< partial_len
; i
++)
3747 fprintf_unfiltered (gdb_stdlog
, "%02x",
3751 write_memory (addr
, val
, partial_len
);
3754 /* Note!!! This is NOT an else clause. Odd sized
3755 structs may go thru BOTH paths. Floating point
3756 arguments will not. */
3757 /* Write this portion of the argument to a general
3758 purpose register. */
3759 if (argreg
<= MIPS_LAST_ARG_REGNUM
3760 && !fp_register_arg_p (typecode
, arg_type
))
3762 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3763 /* Value may need to be sign extended, because
3764 mips_regsize() != mips_saved_regsize(). */
3766 /* A non-floating-point argument being passed in a
3767 general register. If a struct or union, and if
3768 the remaining length is smaller than the register
3769 size, we have to adjust the register value on
3772 It does not seem to be necessary to do the
3773 same for integral types.
3775 Also don't do this adjustment on O64 binaries.
3777 cagney/2001-07-23: gdb/179: Also, GCC, when
3778 outputting LE O32 with sizeof (struct) <
3779 mips_saved_regsize(), generates a left shift as
3780 part of storing the argument in a register a
3781 register (the left shift isn't generated when
3782 sizeof (struct) >= mips_saved_regsize()). Since
3783 it is quite possible that this is GCC
3784 contradicting the LE/O32 ABI, GDB has not been
3785 adjusted to accommodate this. Either someone
3786 needs to demonstrate that the LE/O32 ABI
3787 specifies such a left shift OR this new ABI gets
3788 identified as such and GDB gets tweaked
3791 if (mips_saved_regsize (tdep
) < 8
3792 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3793 && partial_len
< mips_saved_regsize (tdep
)
3794 && (typecode
== TYPE_CODE_STRUCT
||
3795 typecode
== TYPE_CODE_UNION
))
3796 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3800 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3802 phex (regval
, mips_saved_regsize (tdep
)));
3803 write_register (argreg
, regval
);
3806 /* Prevent subsequent floating point arguments from
3807 being passed in floating point registers. */
3808 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3814 /* Compute the the offset into the stack at which we
3815 will copy the next parameter.
3817 In older ABIs, the caller reserved space for
3818 registers that contained arguments. This was loosely
3819 refered to as their "home". Consequently, space is
3820 always allocated. */
3822 stack_offset
+= align_up (partial_len
,
3823 mips_stack_argsize (tdep
));
3827 fprintf_unfiltered (gdb_stdlog
, "\n");
3830 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3832 /* Return adjusted stack pointer. */
3837 mips_pop_frame (void)
3840 struct frame_info
*frame
= get_current_frame ();
3841 CORE_ADDR new_sp
= get_frame_base (frame
);
3842 mips_extra_func_info_t proc_desc
;
3843 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3845 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
3847 generic_pop_dummy_frame ();
3848 flush_cached_frames ();
3852 proc_desc
= get_frame_extra_info (frame
)->proc_desc
;
3853 write_register (PC_REGNUM
, DEPRECATED_FRAME_SAVED_PC (frame
));
3854 mips_find_saved_regs (frame
);
3855 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
3856 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
3857 && deprecated_get_frame_saved_regs (frame
)[regnum
])
3859 /* Floating point registers must not be sign extended, in case
3860 mips_saved_regsize() = 4 but sizeof (FP0_REGNUM) == 8. */
3862 if (mips_regnum (current_gdbarch
)->fp0
<= regnum
&& regnum
< mips_regnum (current_gdbarch
)->fp0
+ 32)
3863 write_register (regnum
,
3864 read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3865 mips_saved_regsize (tdep
)));
3867 write_register (regnum
,
3868 read_memory_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3869 mips_saved_regsize (tdep
)));
3872 write_register (SP_REGNUM
, new_sp
);
3873 flush_cached_frames ();
3875 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
3877 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
3879 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
3881 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
3883 if (&pi_ptr
->info
== proc_desc
)
3888 error ("Can't locate dummy extra frame info\n");
3890 if (prev_ptr
!= NULL
)
3891 prev_ptr
->next
= pi_ptr
->next
;
3893 linked_proc_desc_table
= pi_ptr
->next
;
3897 write_register (mips_regnum (current_gdbarch
)->hi
,
3898 read_memory_integer ((new_sp
3899 - 2 * mips_saved_regsize (tdep
)),
3900 mips_saved_regsize (tdep
)));
3901 write_register (mips_regnum (current_gdbarch
)->lo
,
3902 read_memory_integer ((new_sp
3903 - 3 * mips_saved_regsize (tdep
)),
3904 mips_saved_regsize (tdep
)));
3905 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
3906 write_register (mips_regnum (current_gdbarch
)->fp_control_status
,
3907 read_memory_integer ((new_sp
3908 - 4 * mips_saved_regsize (tdep
)),
3909 mips_saved_regsize (tdep
)));
3913 /* Floating point register management.
3915 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3916 64bit operations, these early MIPS cpus treat fp register pairs
3917 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3918 registers and offer a compatibility mode that emulates the MIPS2 fp
3919 model. When operating in MIPS2 fp compat mode, later cpu's split
3920 double precision floats into two 32-bit chunks and store them in
3921 consecutive fp regs. To display 64-bit floats stored in this
3922 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3923 Throw in user-configurable endianness and you have a real mess.
3925 The way this works is:
3926 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3927 double-precision value will be split across two logical registers.
3928 The lower-numbered logical register will hold the low-order bits,
3929 regardless of the processor's endianness.
3930 - If we are on a 64-bit processor, and we are looking for a
3931 single-precision value, it will be in the low ordered bits
3932 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3933 save slot in memory.
3934 - If we are in 64-bit mode, everything is straightforward.
3936 Note that this code only deals with "live" registers at the top of the
3937 stack. We will attempt to deal with saved registers later, when
3938 the raw/cooked register interface is in place. (We need a general
3939 interface that can deal with dynamic saved register sizes -- fp
3940 regs could be 32 bits wide in one frame and 64 on the frame above
3943 static struct type
*
3944 mips_float_register_type (void)
3946 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3947 return builtin_type_ieee_single_big
;
3949 return builtin_type_ieee_single_little
;
3952 static struct type
*
3953 mips_double_register_type (void)
3955 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3956 return builtin_type_ieee_double_big
;
3958 return builtin_type_ieee_double_little
;
3961 /* Copy a 32-bit single-precision value from the current frame
3962 into rare_buffer. */
3965 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3968 int raw_size
= register_size (current_gdbarch
, regno
);
3969 char *raw_buffer
= alloca (raw_size
);
3971 if (!frame_register_read (frame
, regno
, raw_buffer
))
3972 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3975 /* We have a 64-bit value for this register. Find the low-order
3979 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3984 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3988 memcpy (rare_buffer
, raw_buffer
, 4);
3992 /* Copy a 64-bit double-precision value from the current frame into
3993 rare_buffer. This may include getting half of it from the next
3997 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4000 int raw_size
= register_size (current_gdbarch
, regno
);
4002 if (raw_size
== 8 && !mips2_fp_compat ())
4004 /* We have a 64-bit value for this register, and we should use
4006 if (!frame_register_read (frame
, regno
, rare_buffer
))
4007 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4011 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4012 internal_error (__FILE__
, __LINE__
,
4013 "mips_read_fp_register_double: bad access to "
4014 "odd-numbered FP register");
4016 /* mips_read_fp_register_single will find the correct 32 bits from
4018 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4020 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4021 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4025 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4026 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4032 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4034 { /* do values for FP (float) regs */
4036 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
4037 int inv1
, inv2
, namelen
;
4039 raw_buffer
= (char *) alloca (2 * register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
));
4041 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4042 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4045 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4047 /* 4-byte registers: Print hex and floating. Also print even
4048 numbered registers as doubles. */
4049 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4050 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4052 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w', file
);
4054 fprintf_filtered (file
, " flt: ");
4056 fprintf_filtered (file
, " <invalid float> ");
4058 fprintf_filtered (file
, "%-17.9g", flt1
);
4060 if (regnum
% 2 == 0)
4062 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4063 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4066 fprintf_filtered (file
, " dbl: ");
4068 fprintf_filtered (file
, "<invalid double>");
4070 fprintf_filtered (file
, "%-24.17g", doub
);
4075 /* Eight byte registers: print each one as hex, float and double. */
4076 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4077 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4079 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4080 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4083 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g', file
);
4085 fprintf_filtered (file
, " flt: ");
4087 fprintf_filtered (file
, "<invalid float>");
4089 fprintf_filtered (file
, "%-17.9g", flt1
);
4091 fprintf_filtered (file
, " dbl: ");
4093 fprintf_filtered (file
, "<invalid double>");
4095 fprintf_filtered (file
, "%-24.17g", doub
);
4100 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4101 int regnum
, int all
)
4103 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4104 char raw_buffer
[MAX_REGISTER_SIZE
];
4107 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4109 mips_print_fp_register (file
, frame
, regnum
);
4113 /* Get the data in raw format. */
4114 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4116 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4120 fputs_filtered (REGISTER_NAME (regnum
), file
);
4122 /* The problem with printing numeric register names (r26, etc.) is that
4123 the user can't use them on input. Probably the best solution is to
4124 fix it so that either the numeric or the funky (a2, etc.) names
4125 are accepted on input. */
4126 if (regnum
< MIPS_NUMREGS
)
4127 fprintf_filtered (file
, "(r%d): ", regnum
);
4129 fprintf_filtered (file
, ": ");
4131 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4132 offset
= register_size (current_gdbarch
, regnum
) - register_size (current_gdbarch
, regnum
);
4136 print_scalar_formatted (raw_buffer
+ offset
, gdbarch_register_type (gdbarch
, regnum
),
4140 /* Replacement for generic do_registers_info.
4141 Print regs in pretty columns. */
4144 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4147 fprintf_filtered (file
, " ");
4148 mips_print_fp_register (file
, frame
, regnum
);
4149 fprintf_filtered (file
, "\n");
4154 /* Print a row's worth of GP (int) registers, with name labels above */
4157 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4160 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4161 /* do values for GP (int) regs */
4162 char raw_buffer
[MAX_REGISTER_SIZE
];
4163 int ncols
= (mips_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4167 /* For GP registers, we print a separate row of names above the vals */
4168 fprintf_filtered (file
, " ");
4169 for (col
= 0, regnum
= start_regnum
;
4170 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4173 if (*REGISTER_NAME (regnum
) == '\0')
4174 continue; /* unused register */
4175 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4176 break; /* end the row: reached FP register */
4177 fprintf_filtered (file
, mips_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4178 REGISTER_NAME (regnum
));
4181 /* print the R0 to R31 names */
4182 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4183 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4185 fprintf_filtered (file
, "\n ");
4187 /* now print the values in hex, 4 or 8 to the row */
4188 for (col
= 0, regnum
= start_regnum
;
4189 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4192 if (*REGISTER_NAME (regnum
) == '\0')
4193 continue; /* unused register */
4194 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4195 break; /* end row: reached FP register */
4196 /* OK: get the data in raw format. */
4197 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4198 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4199 /* pad small registers */
4201 byte
< (mips_regsize (current_gdbarch
)
4202 - register_size (current_gdbarch
, regnum
));
4204 printf_filtered (" ");
4205 /* Now print the register value in hex, endian order. */
4206 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4207 for (byte
= register_size (current_gdbarch
, regnum
) - register_size (current_gdbarch
, regnum
);
4208 byte
< register_size (current_gdbarch
, regnum
);
4210 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4212 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4215 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4216 fprintf_filtered (file
, " ");
4219 if (col
> 0) /* ie. if we actually printed anything... */
4220 fprintf_filtered (file
, "\n");
4225 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4228 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4229 struct frame_info
*frame
, int regnum
, int all
)
4231 if (regnum
!= -1) /* do one specified register */
4233 gdb_assert (regnum
>= NUM_REGS
);
4234 if (*(REGISTER_NAME (regnum
)) == '\0')
4235 error ("Not a valid register for the current processor type");
4237 mips_print_register (file
, frame
, regnum
, 0);
4238 fprintf_filtered (file
, "\n");
4241 /* do all (or most) registers */
4244 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4246 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4248 if (all
) /* true for "INFO ALL-REGISTERS" command */
4249 regnum
= print_fp_register_row (file
, frame
, regnum
);
4251 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4254 regnum
= print_gp_register_row (file
, frame
, regnum
);
4259 /* Is this a branch with a delay slot? */
4261 static int is_delayed (unsigned long);
4264 is_delayed (unsigned long insn
)
4267 for (i
= 0; i
< NUMOPCODES
; ++i
)
4268 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4269 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4271 return (i
< NUMOPCODES
4272 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4273 | INSN_COND_BRANCH_DELAY
4274 | INSN_COND_BRANCH_LIKELY
)));
4278 mips_step_skips_delay (CORE_ADDR pc
)
4280 char buf
[MIPS_INSTLEN
];
4282 /* There is no branch delay slot on MIPS16. */
4283 if (pc_is_mips16 (pc
))
4286 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4287 /* If error reading memory, guess that it is not a delayed branch. */
4289 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4293 /* Given PC at the function's start address, attempt to find the
4294 prologue end using SAL information. Return zero if the skip fails.
4296 A non-optimized prologue traditionally has one SAL for the function
4297 and a second for the function body. A single line function has
4298 them both pointing at the same line.
4300 An optimized prologue is similar but the prologue may contain
4301 instructions (SALs) from the instruction body. Need to skip those
4302 while not getting into the function body.
4304 The functions end point and an increasing SAL line are used as
4305 indicators of the prologue's endpoint.
4307 This code is based on the function refine_prologue_limit (versions
4308 found in both ia64 and ppc). */
4311 skip_prologue_using_sal (CORE_ADDR func_addr
)
4313 struct symtab_and_line prologue_sal
;
4317 /* Get an initial range for the function. */
4318 find_pc_partial_function (func_addr
, NULL
, &start_pc
, &end_pc
);
4319 start_pc
+= FUNCTION_START_OFFSET
;
4321 prologue_sal
= find_pc_line (start_pc
, 0);
4322 if (prologue_sal
.line
!= 0)
4324 while (prologue_sal
.end
< end_pc
)
4326 struct symtab_and_line sal
;
4328 sal
= find_pc_line (prologue_sal
.end
, 0);
4331 /* Assume that a consecutive SAL for the same (or larger)
4332 line mark the prologue -> body transition. */
4333 if (sal
.line
>= prologue_sal
.line
)
4335 /* The case in which compiler's optimizer/scheduler has
4336 moved instructions into the prologue. We look ahead in
4337 the function looking for address ranges whose
4338 corresponding line number is less the first one that we
4339 found for the function. This is more conservative then
4340 refine_prologue_limit which scans a large number of SALs
4341 looking for any in the prologue */
4345 return prologue_sal
.end
;
4348 /* Skip the PC past function prologue instructions (32-bit version).
4349 This is a helper function for mips_skip_prologue. */
4352 mips32_skip_prologue (CORE_ADDR pc
)
4356 int seen_sp_adjust
= 0;
4357 int load_immediate_bytes
= 0;
4359 /* Find an upper bound on the prologue. */
4360 end_pc
= skip_prologue_using_sal (pc
);
4362 end_pc
= pc
+ 100; /* Magic. */
4364 /* Skip the typical prologue instructions. These are the stack adjustment
4365 instruction and the instructions that save registers on the stack
4366 or in the gcc frame. */
4367 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4369 unsigned long high_word
;
4371 inst
= mips_fetch_instruction (pc
);
4372 high_word
= (inst
>> 16) & 0xffff;
4374 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4375 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4377 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4378 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4380 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4381 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4382 && (inst
& 0x001F0000)) /* reg != $zero */
4385 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4387 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4389 continue; /* reg != $zero */
4391 /* move $s8,$sp. With different versions of gas this will be either
4392 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4393 Accept any one of these. */
4394 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4397 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4399 else if (high_word
== 0x3c1c) /* lui $gp,n */
4401 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4403 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4404 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4406 /* The following instructions load $at or $t0 with an immediate
4407 value in preparation for a stack adjustment via
4408 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4409 a local variable, so we accept them only before a stack adjustment
4410 instruction was seen. */
4411 else if (!seen_sp_adjust
)
4413 if (high_word
== 0x3c01 || /* lui $at,n */
4414 high_word
== 0x3c08) /* lui $t0,n */
4416 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4419 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4420 high_word
== 0x3508 || /* ori $t0,$t0,n */
4421 high_word
== 0x3401 || /* ori $at,$zero,n */
4422 high_word
== 0x3408) /* ori $t0,$zero,n */
4424 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4434 /* In a frameless function, we might have incorrectly
4435 skipped some load immediate instructions. Undo the skipping
4436 if the load immediate was not followed by a stack adjustment. */
4437 if (load_immediate_bytes
&& !seen_sp_adjust
)
4438 pc
-= load_immediate_bytes
;
4442 /* Skip the PC past function prologue instructions (16-bit version).
4443 This is a helper function for mips_skip_prologue. */
4446 mips16_skip_prologue (CORE_ADDR pc
)
4449 int extend_bytes
= 0;
4450 int prev_extend_bytes
;
4452 /* Table of instructions likely to be found in a function prologue. */
4455 unsigned short inst
;
4456 unsigned short mask
;
4463 , /* addiu $sp,offset */
4467 , /* daddiu $sp,offset */
4471 , /* sw reg,n($sp) */
4475 , /* sd reg,n($sp) */
4479 , /* sw $ra,n($sp) */
4483 , /* sd $ra,n($sp) */
4491 , /* sw $a0-$a3,n($s1) */
4495 , /* move reg,$a0-$a3 */
4499 , /* entry pseudo-op */
4503 , /* addiu $s1,$sp,n */
4506 } /* end of table marker */
4509 /* Find an upper bound on the prologue. */
4510 end_pc
= skip_prologue_using_sal (pc
);
4512 end_pc
= pc
+ 100; /* Magic. */
4514 /* Skip the typical prologue instructions. These are the stack adjustment
4515 instruction and the instructions that save registers on the stack
4516 or in the gcc frame. */
4517 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4519 unsigned short inst
;
4522 inst
= mips_fetch_instruction (pc
);
4524 /* Normally we ignore an extend instruction. However, if it is
4525 not followed by a valid prologue instruction, we must adjust
4526 the pc back over the extend so that it won't be considered
4527 part of the prologue. */
4528 if ((inst
& 0xf800) == 0xf000) /* extend */
4530 extend_bytes
= MIPS16_INSTLEN
;
4533 prev_extend_bytes
= extend_bytes
;
4536 /* Check for other valid prologue instructions besides extend. */
4537 for (i
= 0; table
[i
].mask
!= 0; i
++)
4538 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4540 if (table
[i
].mask
!= 0) /* it was in table? */
4541 continue; /* ignore it */
4545 /* Return the current pc, adjusted backwards by 2 if
4546 the previous instruction was an extend. */
4547 return pc
- prev_extend_bytes
;
4553 /* To skip prologues, I use this predicate. Returns either PC itself
4554 if the code at PC does not look like a function prologue; otherwise
4555 returns an address that (if we're lucky) follows the prologue. If
4556 LENIENT, then we must skip everything which is involved in setting
4557 up the frame (it's OK to skip more, just so long as we don't skip
4558 anything which might clobber the registers which are being saved.
4559 We must skip more in the case where part of the prologue is in the
4560 delay slot of a non-prologue instruction). */
4563 mips_skip_prologue (CORE_ADDR pc
)
4565 /* See if we can determine the end of the prologue via the symbol table.
4566 If so, then return either PC, or the PC after the prologue, whichever
4569 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4571 if (post_prologue_pc
!= 0)
4572 return max (pc
, post_prologue_pc
);
4574 /* Can't determine prologue from the symbol table, need to examine
4577 if (pc_is_mips16 (pc
))
4578 return mips16_skip_prologue (pc
);
4580 return mips32_skip_prologue (pc
);
4583 /* Determine how a return value is stored within the MIPS register
4584 file, given the return type `valtype'. */
4586 struct return_value_word
4595 return_value_location (struct type
*valtype
,
4596 struct return_value_word
*hi
,
4597 struct return_value_word
*lo
)
4599 int len
= TYPE_LENGTH (valtype
);
4600 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4602 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
4603 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
4604 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
4606 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4608 /* We need to break a 64bit float in two 32 bit halves and
4609 spread them across a floating-point register pair. */
4610 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4611 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
4612 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4613 && register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 8)
4615 hi
->reg_offset
= lo
->reg_offset
;
4616 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
4617 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
4623 /* The floating point value fits in a single floating-point
4625 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4626 && register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 8
4629 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
4640 /* Locate a result possibly spread across two registers. */
4642 lo
->reg
= regnum
+ 0;
4643 hi
->reg
= regnum
+ 1;
4644 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4645 && len
< mips_saved_regsize (tdep
))
4647 /* "un-left-justify" the value in the low register */
4648 lo
->reg_offset
= mips_saved_regsize (tdep
) - len
;
4653 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4654 && len
> mips_saved_regsize (tdep
) /* odd-size structs */
4655 && len
< mips_saved_regsize (tdep
) * 2
4656 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
4657 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
4659 /* "un-left-justify" the value spread across two registers. */
4660 lo
->reg_offset
= 2 * mips_saved_regsize (tdep
) - len
;
4661 lo
->len
= mips_saved_regsize (tdep
) - lo
->reg_offset
;
4663 hi
->len
= len
- lo
->len
;
4667 /* Only perform a partial copy of the second register. */
4670 if (len
> mips_saved_regsize (tdep
))
4672 lo
->len
= mips_saved_regsize (tdep
);
4673 hi
->len
= len
- mips_saved_regsize (tdep
);
4681 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4682 && register_size (current_gdbarch
, regnum
) == 8
4683 && mips_saved_regsize (tdep
) == 4)
4685 /* Account for the fact that only the least-signficant part
4686 of the register is being used */
4687 lo
->reg_offset
+= 4;
4688 hi
->reg_offset
+= 4;
4691 hi
->buf_offset
= lo
->len
;
4695 /* Given a return value in `regbuf' with a type `valtype', extract and
4696 copy its value into `valbuf'. */
4699 mips_eabi_extract_return_value (struct type
*valtype
,
4703 struct return_value_word lo
;
4704 struct return_value_word hi
;
4705 return_value_location (valtype
, &hi
, &lo
);
4707 memcpy (valbuf
+ lo
.buf_offset
,
4708 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) + lo
.reg_offset
,
4712 memcpy (valbuf
+ hi
.buf_offset
,
4713 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) + hi
.reg_offset
,
4718 mips_o64_extract_return_value (struct type
*valtype
,
4722 struct return_value_word lo
;
4723 struct return_value_word hi
;
4724 return_value_location (valtype
, &hi
, &lo
);
4726 memcpy (valbuf
+ lo
.buf_offset
,
4727 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) + lo
.reg_offset
,
4731 memcpy (valbuf
+ hi
.buf_offset
,
4732 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) + hi
.reg_offset
,
4736 /* Given a return value in `valbuf' with a type `valtype', write it's
4737 value into the appropriate register. */
4740 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
4742 char raw_buffer
[MAX_REGISTER_SIZE
];
4743 struct return_value_word lo
;
4744 struct return_value_word hi
;
4745 return_value_location (valtype
, &hi
, &lo
);
4747 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4748 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4749 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4750 register_size (current_gdbarch
, lo
.reg
));
4754 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4755 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4756 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4757 register_size (current_gdbarch
, hi
.reg
));
4762 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4764 char raw_buffer
[MAX_REGISTER_SIZE
];
4765 struct return_value_word lo
;
4766 struct return_value_word hi
;
4767 return_value_location (valtype
, &hi
, &lo
);
4769 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4770 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4771 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4772 register_size (current_gdbarch
, lo
.reg
));
4776 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4777 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4778 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4779 register_size (current_gdbarch
, hi
.reg
));
4783 /* O32 ABI stuff. */
4785 static enum return_value_convention
4786 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4787 struct regcache
*regcache
,
4788 void *readbuf
, const void *writebuf
)
4790 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4792 if (TYPE_CODE (type
)== TYPE_CODE_STRUCT
4793 || TYPE_CODE (type
)== TYPE_CODE_UNION
4794 || TYPE_CODE (type
)== TYPE_CODE_ARRAY
)
4795 return RETURN_VALUE_STRUCT_CONVENTION
;
4796 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4797 && TYPE_LENGTH (type
) == 4
4798 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4800 /* A single-precision floating-point value. It fits in the
4801 least significant part of FP0. */
4803 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4804 mips_xfer_register (regcache
,
4805 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4807 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4808 return RETURN_VALUE_REGISTER_CONVENTION
;
4810 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4811 && TYPE_LENGTH (type
) == 8
4812 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4814 /* A double-precision floating-point value. The most
4815 significant part goes in FP1, and the least significant in
4818 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4819 switch (TARGET_BYTE_ORDER
)
4821 case BFD_ENDIAN_LITTLE
:
4822 mips_xfer_register (regcache
,
4823 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 0,
4824 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4825 mips_xfer_register (regcache
,
4826 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 1,
4827 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4829 case BFD_ENDIAN_BIG
:
4830 mips_xfer_register (regcache
,
4831 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 1,
4832 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4833 mips_xfer_register (regcache
,
4834 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 0,
4835 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4838 internal_error (__FILE__
, __LINE__
, "bad switch");
4840 return RETURN_VALUE_REGISTER_CONVENTION
;
4843 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4844 && TYPE_NFIELDS (type
) <= 2
4845 && TYPE_NFIELDS (type
) >= 1
4846 && ((TYPE_NFIELDS (type
) == 1
4847 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4849 || (TYPE_NFIELDS (type
) == 2
4850 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4852 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4854 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4856 /* A struct that contains one or two floats. Each value is part
4857 in the least significant part of their floating point
4859 bfd_byte reg
[MAX_REGISTER_SIZE
];
4862 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4863 field
< TYPE_NFIELDS (type
);
4864 field
++, regnum
+= 2)
4866 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4869 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4870 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4871 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4872 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4874 return RETURN_VALUE_REGISTER_CONVENTION
;
4878 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4879 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4881 /* A structure or union. Extract the left justified value,
4882 regardless of the byte order. I.e. DO NOT USE
4886 for (offset
= 0, regnum
= V0_REGNUM
;
4887 offset
< TYPE_LENGTH (type
);
4888 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4890 int xfer
= register_size (current_gdbarch
, regnum
);
4891 if (offset
+ xfer
> TYPE_LENGTH (type
))
4892 xfer
= TYPE_LENGTH (type
) - offset
;
4894 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4895 offset
, xfer
, regnum
);
4896 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4897 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4899 return RETURN_VALUE_REGISTER_CONVENTION
;
4904 /* A scalar extract each part but least-significant-byte
4905 justified. o32 thinks registers are 4 byte, regardless of
4906 the ISA. mips_stack_argsize controls this. */
4909 for (offset
= 0, regnum
= V0_REGNUM
;
4910 offset
< TYPE_LENGTH (type
);
4911 offset
+= mips_stack_argsize (tdep
), regnum
++)
4913 int xfer
= mips_stack_argsize (tdep
);
4915 if (offset
+ xfer
> TYPE_LENGTH (type
))
4916 xfer
= TYPE_LENGTH (type
) - offset
;
4918 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4919 offset
, xfer
, regnum
);
4920 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4921 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4923 return RETURN_VALUE_REGISTER_CONVENTION
;
4927 /* N32/N44 ABI stuff. */
4929 static enum return_value_convention
4930 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
4931 struct type
*type
, struct regcache
*regcache
,
4932 void *readbuf
, const void *writebuf
)
4934 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4935 if (TYPE_CODE (type
)== TYPE_CODE_STRUCT
4936 || TYPE_CODE (type
)== TYPE_CODE_UNION
4937 || TYPE_CODE (type
)== TYPE_CODE_ARRAY
4938 || TYPE_LENGTH (type
) > 2 * mips_saved_regsize (tdep
))
4939 return RETURN_VALUE_STRUCT_CONVENTION
;
4940 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4941 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4943 /* A floating-point value belongs in the least significant part
4946 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4947 mips_xfer_register (regcache
,
4948 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4950 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4951 return RETURN_VALUE_REGISTER_CONVENTION
;
4953 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4954 && TYPE_NFIELDS (type
) <= 2
4955 && TYPE_NFIELDS (type
) >= 1
4956 && ((TYPE_NFIELDS (type
) == 1
4957 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4959 || (TYPE_NFIELDS (type
) == 2
4960 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4962 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4964 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4966 /* A struct that contains one or two floats. Each value is part
4967 in the least significant part of their floating point
4969 bfd_byte reg
[MAX_REGISTER_SIZE
];
4972 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4973 field
< TYPE_NFIELDS (type
);
4974 field
++, regnum
+= 2)
4976 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4979 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4980 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4981 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4982 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4984 return RETURN_VALUE_REGISTER_CONVENTION
;
4986 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4987 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4989 /* A structure or union. Extract the left justified value,
4990 regardless of the byte order. I.e. DO NOT USE
4994 for (offset
= 0, regnum
= V0_REGNUM
;
4995 offset
< TYPE_LENGTH (type
);
4996 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4998 int xfer
= register_size (current_gdbarch
, regnum
);
4999 if (offset
+ xfer
> TYPE_LENGTH (type
))
5000 xfer
= TYPE_LENGTH (type
) - offset
;
5002 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5003 offset
, xfer
, regnum
);
5004 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
5005 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5007 return RETURN_VALUE_REGISTER_CONVENTION
;
5011 /* A scalar extract each part but least-significant-byte
5015 for (offset
= 0, regnum
= V0_REGNUM
;
5016 offset
< TYPE_LENGTH (type
);
5017 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
5019 int xfer
= register_size (current_gdbarch
, regnum
);
5021 if (offset
+ xfer
> TYPE_LENGTH (type
))
5022 xfer
= TYPE_LENGTH (type
) - offset
;
5024 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5025 offset
, xfer
, regnum
);
5026 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
5027 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
5029 return RETURN_VALUE_REGISTER_CONVENTION
;
5033 /* Exported procedure: Is PC in the signal trampoline code */
5036 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
5038 if (sigtramp_address
== 0)
5040 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
5043 /* Root of all "set mips "/"show mips " commands. This will eventually be
5044 used for all MIPS-specific commands. */
5047 show_mips_command (char *args
, int from_tty
)
5049 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5053 set_mips_command (char *args
, int from_tty
)
5055 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
5056 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5059 /* Commands to show/set the MIPS FPU type. */
5062 show_mipsfpu_command (char *args
, int from_tty
)
5065 switch (MIPS_FPU_TYPE
)
5067 case MIPS_FPU_SINGLE
:
5068 fpu
= "single-precision";
5070 case MIPS_FPU_DOUBLE
:
5071 fpu
= "double-precision";
5074 fpu
= "absent (none)";
5077 internal_error (__FILE__
, __LINE__
, "bad switch");
5079 if (mips_fpu_type_auto
)
5080 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5083 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
5089 set_mipsfpu_command (char *args
, int from_tty
)
5091 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5092 show_mipsfpu_command (args
, from_tty
);
5096 set_mipsfpu_single_command (char *args
, int from_tty
)
5098 struct gdbarch_info info
;
5099 gdbarch_info_init (&info
);
5100 mips_fpu_type
= MIPS_FPU_SINGLE
;
5101 mips_fpu_type_auto
= 0;
5102 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5103 instead of relying on globals. Doing that would let generic code
5104 handle the search for this specific architecture. */
5105 if (!gdbarch_update_p (info
))
5106 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5110 set_mipsfpu_double_command (char *args
, int from_tty
)
5112 struct gdbarch_info info
;
5113 gdbarch_info_init (&info
);
5114 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5115 mips_fpu_type_auto
= 0;
5116 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5117 instead of relying on globals. Doing that would let generic code
5118 handle the search for this specific architecture. */
5119 if (!gdbarch_update_p (info
))
5120 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5124 set_mipsfpu_none_command (char *args
, int from_tty
)
5126 struct gdbarch_info info
;
5127 gdbarch_info_init (&info
);
5128 mips_fpu_type
= MIPS_FPU_NONE
;
5129 mips_fpu_type_auto
= 0;
5130 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5131 instead of relying on globals. Doing that would let generic code
5132 handle the search for this specific architecture. */
5133 if (!gdbarch_update_p (info
))
5134 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5138 set_mipsfpu_auto_command (char *args
, int from_tty
)
5140 mips_fpu_type_auto
= 1;
5143 /* Attempt to identify the particular processor model by reading the
5144 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5145 the relevant processor still exists (it dates back to '94) and
5146 secondly this is not the way to do this. The processor type should
5147 be set by forcing an architecture change. */
5150 deprecated_mips_set_processor_regs_hack (void)
5152 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5155 prid
= read_register (PRID_REGNUM
);
5157 if ((prid
& ~0xf) == 0x700)
5158 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5161 /* Just like reinit_frame_cache, but with the right arguments to be
5162 callable as an sfunc. */
5165 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5166 struct cmd_list_element
*c
)
5168 reinit_frame_cache ();
5172 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5174 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5175 mips_extra_func_info_t proc_desc
;
5177 /* Search for the function containing this address. Set the low bit
5178 of the address when searching, in case we were given an even address
5179 that is the start of a 16-bit function. If we didn't do this,
5180 the search would fail because the symbol table says the function
5181 starts at an odd address, i.e. 1 byte past the given address. */
5182 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5183 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5185 /* Make an attempt to determine if this is a 16-bit function. If
5186 the procedure descriptor exists and the address therein is odd,
5187 it's definitely a 16-bit function. Otherwise, we have to just
5188 guess that if the address passed in is odd, it's 16-bits. */
5189 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5190 disassembler needs to be able to locally determine the ISA, and
5191 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5195 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5196 info
->mach
= bfd_mach_mips16
;
5200 if (pc_is_mips16 (memaddr
))
5201 info
->mach
= bfd_mach_mips16
;
5204 /* Round down the instruction address to the appropriate boundary. */
5205 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5207 /* Set the disassembler options. */
5208 if (tdep
->mips_abi
== MIPS_ABI_N32
5209 || tdep
->mips_abi
== MIPS_ABI_N64
)
5211 /* Set up the disassembler info, so that we get the right
5212 register names from libopcodes. */
5213 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5214 info
->disassembler_options
= "gpr-names=n32";
5216 info
->disassembler_options
= "gpr-names=64";
5217 info
->flavour
= bfd_target_elf_flavour
;
5220 /* This string is not recognized explicitly by the disassembler,
5221 but it tells the disassembler to not try to guess the ABI from
5222 the bfd elf headers, such that, if the user overrides the ABI
5223 of a program linked as NewABI, the disassembly will follow the
5224 register naming conventions specified by the user. */
5225 info
->disassembler_options
= "gpr-names=32";
5227 /* Call the appropriate disassembler based on the target endian-ness. */
5228 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5229 return print_insn_big_mips (memaddr
, info
);
5231 return print_insn_little_mips (memaddr
, info
);
5234 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5235 counter value to determine whether a 16- or 32-bit breakpoint should be
5236 used. It returns a pointer to a string of bytes that encode a breakpoint
5237 instruction, stores the length of the string to *lenptr, and adjusts pc
5238 (if necessary) to point to the actual memory location where the
5239 breakpoint should be inserted. */
5241 static const unsigned char *
5242 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
5244 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5246 if (pc_is_mips16 (*pcptr
))
5248 static unsigned char mips16_big_breakpoint
[] = {0xe8, 0xa5};
5249 *pcptr
= unmake_mips16_addr (*pcptr
);
5250 *lenptr
= sizeof (mips16_big_breakpoint
);
5251 return mips16_big_breakpoint
;
5255 /* The IDT board uses an unusual breakpoint value, and
5256 sometimes gets confused when it sees the usual MIPS
5257 breakpoint instruction. */
5258 static unsigned char big_breakpoint
[] = {0, 0x5, 0, 0xd};
5259 static unsigned char pmon_big_breakpoint
[] = {0, 0, 0, 0xd};
5260 static unsigned char idt_big_breakpoint
[] = {0, 0, 0x0a, 0xd};
5262 *lenptr
= sizeof (big_breakpoint
);
5264 if (strcmp (target_shortname
, "mips") == 0)
5265 return idt_big_breakpoint
;
5266 else if (strcmp (target_shortname
, "ddb") == 0
5267 || strcmp (target_shortname
, "pmon") == 0
5268 || strcmp (target_shortname
, "lsi") == 0)
5269 return pmon_big_breakpoint
;
5271 return big_breakpoint
;
5276 if (pc_is_mips16 (*pcptr
))
5278 static unsigned char mips16_little_breakpoint
[] = {0xa5, 0xe8};
5279 *pcptr
= unmake_mips16_addr (*pcptr
);
5280 *lenptr
= sizeof (mips16_little_breakpoint
);
5281 return mips16_little_breakpoint
;
5285 static unsigned char little_breakpoint
[] = {0xd, 0, 0x5, 0};
5286 static unsigned char pmon_little_breakpoint
[] = {0xd, 0, 0, 0};
5287 static unsigned char idt_little_breakpoint
[] = {0xd, 0x0a, 0, 0};
5289 *lenptr
= sizeof (little_breakpoint
);
5291 if (strcmp (target_shortname
, "mips") == 0)
5292 return idt_little_breakpoint
;
5293 else if (strcmp (target_shortname
, "ddb") == 0
5294 || strcmp (target_shortname
, "pmon") == 0
5295 || strcmp (target_shortname
, "lsi") == 0)
5296 return pmon_little_breakpoint
;
5298 return little_breakpoint
;
5303 /* If PC is in a mips16 call or return stub, return the address of the target
5304 PC, which is either the callee or the caller. There are several
5305 cases which must be handled:
5307 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5308 target PC is in $31 ($ra).
5309 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5310 and the target PC is in $2.
5311 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5312 before the jal instruction, this is effectively a call stub
5313 and the the target PC is in $2. Otherwise this is effectively
5314 a return stub and the target PC is in $18.
5316 See the source code for the stubs in gcc/config/mips/mips16.S for
5319 This function implements the SKIP_TRAMPOLINE_CODE macro.
5323 mips_skip_stub (CORE_ADDR pc
)
5326 CORE_ADDR start_addr
;
5328 /* Find the starting address and name of the function containing the PC. */
5329 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5332 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5333 target PC is in $31 ($ra). */
5334 if (strcmp (name
, "__mips16_ret_sf") == 0
5335 || strcmp (name
, "__mips16_ret_df") == 0)
5336 return read_signed_register (RA_REGNUM
);
5338 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5340 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5341 and the target PC is in $2. */
5342 if (name
[19] >= '0' && name
[19] <= '9')
5343 return read_signed_register (2);
5345 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5346 before the jal instruction, this is effectively a call stub
5347 and the the target PC is in $2. Otherwise this is effectively
5348 a return stub and the target PC is in $18. */
5349 else if (name
[19] == 's' || name
[19] == 'd')
5351 if (pc
== start_addr
)
5353 /* Check if the target of the stub is a compiler-generated
5354 stub. Such a stub for a function bar might have a name
5355 like __fn_stub_bar, and might look like this:
5360 la $1,bar (becomes a lui/addiu pair)
5362 So scan down to the lui/addi and extract the target
5363 address from those two instructions. */
5365 CORE_ADDR target_pc
= read_signed_register (2);
5369 /* See if the name of the target function is __fn_stub_*. */
5370 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
5372 if (strncmp (name
, "__fn_stub_", 10) != 0
5373 && strcmp (name
, "etext") != 0
5374 && strcmp (name
, "_etext") != 0)
5377 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5378 The limit on the search is arbitrarily set to 20
5379 instructions. FIXME. */
5380 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5382 inst
= mips_fetch_instruction (target_pc
);
5383 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5384 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5385 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5386 return pc
| (inst
& 0xffff); /* low word */
5389 /* Couldn't find the lui/addui pair, so return stub address. */
5393 /* This is the 'return' part of a call stub. The return
5394 address is in $r18. */
5395 return read_signed_register (18);
5398 return 0; /* not a stub */
5402 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5403 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5406 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5408 CORE_ADDR start_addr
;
5410 /* Find the starting address of the function containing the PC. If the
5411 caller didn't give us a name, look it up at the same time. */
5412 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
5415 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5417 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5418 if (name
[19] >= '0' && name
[19] <= '9')
5420 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5421 before the jal instruction, this is effectively a call stub. */
5422 else if (name
[19] == 's' || name
[19] == 'd')
5423 return pc
== start_addr
;
5426 return 0; /* not a stub */
5430 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5431 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5434 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5436 CORE_ADDR start_addr
;
5438 /* Find the starting address of the function containing the PC. */
5439 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5442 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5443 if (strcmp (name
, "__mips16_ret_sf") == 0
5444 || strcmp (name
, "__mips16_ret_df") == 0)
5447 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5448 i.e. after the jal instruction, this is effectively a return stub. */
5449 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5450 && (name
[19] == 's' || name
[19] == 'd')
5451 && pc
!= start_addr
)
5454 return 0; /* not a stub */
5458 /* Return non-zero if the PC is in a library helper function that should
5459 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5462 mips_ignore_helper (CORE_ADDR pc
)
5466 /* Find the starting address and name of the function containing the PC. */
5467 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5470 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5471 that we want to ignore. */
5472 return (strcmp (name
, "__mips16_ret_sf") == 0
5473 || strcmp (name
, "__mips16_ret_df") == 0);
5477 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5478 the register stored on the stack (32) is different to its real raw
5479 size (64). The below ensures that registers are fetched from the
5480 stack using their ABI size and then stored into the RAW_BUFFER
5481 using their raw size.
5483 The alternative to adding this function would be to add an ABI
5484 macro - REGISTER_STACK_SIZE(). */
5487 mips_get_saved_register (char *raw_buffer
,
5490 struct frame_info
*frame
,
5492 enum lval_type
*lvalp
)
5495 enum lval_type lvalx
;
5499 /* Always a pseudo. */
5500 gdb_assert (regnum
>= NUM_REGS
);
5502 /* Make certain that all needed parameters are present. */
5507 if (optimizedp
== NULL
)
5508 optimizedp
= &optimizedx
;
5510 if ((regnum
% NUM_REGS
) == SP_REGNUM
)
5511 /* The SP_REGNUM is special, its value is stored in saved_regs.
5512 In fact, it is so special that it can even only be fetched
5513 using a raw register number! Once this code as been converted
5514 to frame-unwind the problem goes away. */
5515 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5516 regnum
% NUM_REGS
, optimizedp
, lvalp
, addrp
,
5517 &realnumx
, raw_buffer
);
5519 /* Get it from the next frame. */
5520 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5521 regnum
, optimizedp
, lvalp
, addrp
,
5522 &realnumx
, raw_buffer
);
5525 /* Immediately after a function call, return the saved pc.
5526 Can't always go through the frames for this because on some machines
5527 the new frame is not set up until the new function executes
5528 some instructions. */
5531 mips_saved_pc_after_call (struct frame_info
*frame
)
5533 return read_signed_register (RA_REGNUM
);
5537 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5538 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5541 mips_stab_reg_to_regnum (int num
)
5544 if (num
>= 0 && num
< 32)
5546 else if (num
>= 38 && num
< 70)
5547 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5549 regnum
= mips_regnum (current_gdbarch
)->hi
;
5551 regnum
= mips_regnum (current_gdbarch
)->lo
;
5553 /* This will hopefully (eventually) provoke a warning. Should
5554 we be calling complaint() here? */
5555 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5556 return NUM_REGS
+ regnum
;
5560 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5561 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5564 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5567 if (num
>= 0 && num
< 32)
5569 else if (num
>= 32 && num
< 64)
5570 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5572 regnum
= mips_regnum (current_gdbarch
)->hi
;
5574 regnum
= mips_regnum (current_gdbarch
)->lo
;
5576 /* This will hopefully (eventually) provoke a warning. Should we
5577 be calling complaint() here? */
5578 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5579 return NUM_REGS
+ regnum
;
5583 mips_register_sim_regno (int regnum
)
5585 /* Only makes sense to supply raw registers. */
5586 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5587 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5588 decide if it is valid. Should instead define a standard sim/gdb
5589 register numbering scheme. */
5590 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5591 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5594 return LEGACY_SIM_REGNO_IGNORE
;
5598 /* Convert an integer into an address. By first converting the value
5599 into a pointer and then extracting it signed, the address is
5600 guarenteed to be correctly sign extended. */
5603 mips_integer_to_address (struct type
*type
, void *buf
)
5605 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5606 LONGEST val
= unpack_long (type
, buf
);
5607 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5608 return extract_signed_integer (tmp
,
5609 TYPE_LENGTH (builtin_type_void_data_ptr
));
5613 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5615 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5616 const char *name
= bfd_get_section_name (abfd
, sect
);
5618 if (*abip
!= MIPS_ABI_UNKNOWN
)
5621 if (strncmp (name
, ".mdebug.", 8) != 0)
5624 if (strcmp (name
, ".mdebug.abi32") == 0)
5625 *abip
= MIPS_ABI_O32
;
5626 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5627 *abip
= MIPS_ABI_N32
;
5628 else if (strcmp (name
, ".mdebug.abi64") == 0)
5629 *abip
= MIPS_ABI_N64
;
5630 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5631 *abip
= MIPS_ABI_O64
;
5632 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5633 *abip
= MIPS_ABI_EABI32
;
5634 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5635 *abip
= MIPS_ABI_EABI64
;
5637 warning ("unsupported ABI %s.", name
+ 8);
5640 static enum mips_abi
5641 global_mips_abi (void)
5645 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5646 if (mips_abi_strings
[i
] == mips_abi_string
)
5647 return (enum mips_abi
) i
;
5649 internal_error (__FILE__
, __LINE__
,
5650 "unknown ABI string");
5653 static struct gdbarch
*
5654 mips_gdbarch_init (struct gdbarch_info info
,
5655 struct gdbarch_list
*arches
)
5657 struct gdbarch
*gdbarch
;
5658 struct gdbarch_tdep
*tdep
;
5660 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5662 enum mips_fpu_type fpu_type
;
5664 /* First of all, extract the elf_flags, if available. */
5665 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5666 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5667 else if (arches
!= NULL
)
5668 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5672 fprintf_unfiltered (gdb_stdlog
,
5673 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5676 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5677 switch ((elf_flags
& EF_MIPS_ABI
))
5679 case E_MIPS_ABI_O32
:
5680 found_abi
= MIPS_ABI_O32
;
5682 case E_MIPS_ABI_O64
:
5683 found_abi
= MIPS_ABI_O64
;
5685 case E_MIPS_ABI_EABI32
:
5686 found_abi
= MIPS_ABI_EABI32
;
5688 case E_MIPS_ABI_EABI64
:
5689 found_abi
= MIPS_ABI_EABI64
;
5692 if ((elf_flags
& EF_MIPS_ABI2
))
5693 found_abi
= MIPS_ABI_N32
;
5695 found_abi
= MIPS_ABI_UNKNOWN
;
5699 /* GCC creates a pseudo-section whose name describes the ABI. */
5700 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5701 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5703 /* If we have no usefu BFD information, use the ABI from the last
5704 MIPS architecture (if there is one). */
5705 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5706 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5708 /* Try the architecture for any hint of the correct ABI. */
5709 if (found_abi
== MIPS_ABI_UNKNOWN
5710 && info
.bfd_arch_info
!= NULL
5711 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5713 switch (info
.bfd_arch_info
->mach
)
5715 case bfd_mach_mips3900
:
5716 found_abi
= MIPS_ABI_EABI32
;
5718 case bfd_mach_mips4100
:
5719 case bfd_mach_mips5000
:
5720 found_abi
= MIPS_ABI_EABI64
;
5722 case bfd_mach_mips8000
:
5723 case bfd_mach_mips10000
:
5724 /* On Irix, ELF64 executables use the N64 ABI. The
5725 pseudo-sections which describe the ABI aren't present
5726 on IRIX. (Even for executables created by gcc.) */
5727 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5728 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5729 found_abi
= MIPS_ABI_N64
;
5731 found_abi
= MIPS_ABI_N32
;
5737 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5740 /* What has the user specified from the command line? */
5741 wanted_abi
= global_mips_abi ();
5743 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5746 /* Now that we have found what the ABI for this binary would be,
5747 check whether the user is overriding it. */
5748 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5749 mips_abi
= wanted_abi
;
5750 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5751 mips_abi
= found_abi
;
5753 mips_abi
= MIPS_ABI_O32
;
5755 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5758 /* Also used when doing an architecture lookup. */
5760 fprintf_unfiltered (gdb_stdlog
,
5761 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5762 mips64_transfers_32bit_regs_p
);
5764 /* Determine the MIPS FPU type. */
5765 if (!mips_fpu_type_auto
)
5766 fpu_type
= mips_fpu_type
;
5767 else if (info
.bfd_arch_info
!= NULL
5768 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5769 switch (info
.bfd_arch_info
->mach
)
5771 case bfd_mach_mips3900
:
5772 case bfd_mach_mips4100
:
5773 case bfd_mach_mips4111
:
5774 fpu_type
= MIPS_FPU_NONE
;
5776 case bfd_mach_mips4650
:
5777 fpu_type
= MIPS_FPU_SINGLE
;
5780 fpu_type
= MIPS_FPU_DOUBLE
;
5783 else if (arches
!= NULL
)
5784 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5786 fpu_type
= MIPS_FPU_DOUBLE
;
5788 fprintf_unfiltered (gdb_stdlog
,
5789 "mips_gdbarch_init: fpu_type = %d\n",
5792 /* try to find a pre-existing architecture */
5793 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5795 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5797 /* MIPS needs to be pedantic about which ABI the object is
5799 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5801 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5803 /* Need to be pedantic about which register virtual size is
5805 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5806 != mips64_transfers_32bit_regs_p
)
5808 /* Be pedantic about which FPU is selected. */
5809 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5811 return arches
->gdbarch
;
5814 /* Need a new architecture. Fill in a target specific vector. */
5815 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5816 gdbarch
= gdbarch_alloc (&info
, tdep
);
5817 tdep
->elf_flags
= elf_flags
;
5818 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5819 tdep
->found_abi
= found_abi
;
5820 tdep
->mips_abi
= mips_abi
;
5821 tdep
->mips_fpu_type
= fpu_type
;
5823 /* Initially set everything according to the default ABI/ISA. */
5824 set_gdbarch_short_bit (gdbarch
, 16);
5825 set_gdbarch_int_bit (gdbarch
, 32);
5826 set_gdbarch_float_bit (gdbarch
, 32);
5827 set_gdbarch_double_bit (gdbarch
, 64);
5828 set_gdbarch_long_double_bit (gdbarch
, 64);
5829 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5830 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5831 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5833 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5834 mips_elf_make_msymbol_special
);
5836 /* Fill in the OS dependant register numbers and names. */
5838 const char **reg_names
;
5839 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5840 struct mips_regnum
);
5841 if (info
.osabi
== GDB_OSABI_IRIX
)
5846 regnum
->badvaddr
= 66;
5849 regnum
->fp_control_status
= 69;
5850 regnum
->fp_implementation_revision
= 70;
5852 reg_names
= mips_irix_reg_names
;
5856 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5857 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5858 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5859 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5860 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5861 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5862 regnum
->fp_control_status
= 70;
5863 regnum
->fp_implementation_revision
= 71;
5865 if (info
.bfd_arch_info
!= NULL
5866 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5867 reg_names
= mips_tx39_reg_names
;
5869 reg_names
= mips_generic_reg_names
;
5871 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5872 replaced by read_pc? */
5873 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
);
5874 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5875 set_gdbarch_num_regs (gdbarch
, num_regs
);
5876 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5877 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5878 tdep
->mips_processor_reg_names
= reg_names
;
5879 tdep
->regnum
= regnum
;
5885 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5886 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5887 tdep
->mips_default_saved_regsize
= 4;
5888 tdep
->mips_default_stack_argsize
= 4;
5889 tdep
->mips_fp_register_double
= 0;
5890 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5891 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5892 tdep
->default_mask_address_p
= 0;
5893 set_gdbarch_long_bit (gdbarch
, 32);
5894 set_gdbarch_ptr_bit (gdbarch
, 32);
5895 set_gdbarch_long_long_bit (gdbarch
, 64);
5898 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5899 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_o64_store_return_value
);
5900 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_o64_extract_return_value
);
5901 tdep
->mips_default_saved_regsize
= 8;
5902 tdep
->mips_default_stack_argsize
= 8;
5903 tdep
->mips_fp_register_double
= 1;
5904 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5905 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5906 tdep
->default_mask_address_p
= 0;
5907 set_gdbarch_long_bit (gdbarch
, 32);
5908 set_gdbarch_ptr_bit (gdbarch
, 32);
5909 set_gdbarch_long_long_bit (gdbarch
, 64);
5910 set_gdbarch_use_struct_convention (gdbarch
, always_use_struct_convention
);
5912 case MIPS_ABI_EABI32
:
5913 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5914 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5915 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5916 tdep
->mips_default_saved_regsize
= 4;
5917 tdep
->mips_default_stack_argsize
= 4;
5918 tdep
->mips_fp_register_double
= 0;
5919 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5920 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5921 tdep
->default_mask_address_p
= 0;
5922 set_gdbarch_long_bit (gdbarch
, 32);
5923 set_gdbarch_ptr_bit (gdbarch
, 32);
5924 set_gdbarch_long_long_bit (gdbarch
, 64);
5925 set_gdbarch_deprecated_reg_struct_has_addr
5926 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5927 set_gdbarch_use_struct_convention (gdbarch
,
5928 mips_eabi_use_struct_convention
);
5930 case MIPS_ABI_EABI64
:
5931 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5932 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5933 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5934 tdep
->mips_default_saved_regsize
= 8;
5935 tdep
->mips_default_stack_argsize
= 8;
5936 tdep
->mips_fp_register_double
= 1;
5937 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5938 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5939 tdep
->default_mask_address_p
= 0;
5940 set_gdbarch_long_bit (gdbarch
, 64);
5941 set_gdbarch_ptr_bit (gdbarch
, 64);
5942 set_gdbarch_long_long_bit (gdbarch
, 64);
5943 set_gdbarch_deprecated_reg_struct_has_addr
5944 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5945 set_gdbarch_use_struct_convention (gdbarch
,
5946 mips_eabi_use_struct_convention
);
5949 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5950 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5951 tdep
->mips_default_saved_regsize
= 8;
5952 tdep
->mips_default_stack_argsize
= 8;
5953 tdep
->mips_fp_register_double
= 1;
5954 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5955 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5956 tdep
->default_mask_address_p
= 0;
5957 set_gdbarch_long_bit (gdbarch
, 32);
5958 set_gdbarch_ptr_bit (gdbarch
, 32);
5959 set_gdbarch_long_long_bit (gdbarch
, 64);
5962 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5963 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5964 tdep
->mips_default_saved_regsize
= 8;
5965 tdep
->mips_default_stack_argsize
= 8;
5966 tdep
->mips_fp_register_double
= 1;
5967 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5968 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5969 tdep
->default_mask_address_p
= 0;
5970 set_gdbarch_long_bit (gdbarch
, 64);
5971 set_gdbarch_ptr_bit (gdbarch
, 64);
5972 set_gdbarch_long_long_bit (gdbarch
, 64);
5975 internal_error (__FILE__
, __LINE__
,
5976 "unknown ABI in switch");
5979 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5980 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5983 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5984 flag in object files because to do so would make it impossible to
5985 link with libraries compiled without "-gp32". This is
5986 unnecessarily restrictive.
5988 We could solve this problem by adding "-gp32" multilibs to gcc,
5989 but to set this flag before gcc is built with such multilibs will
5990 break too many systems.''
5992 But even more unhelpfully, the default linker output target for
5993 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5994 for 64-bit programs - you need to change the ABI to change this,
5995 and not all gcc targets support that currently. Therefore using
5996 this flag to detect 32-bit mode would do the wrong thing given
5997 the current gcc - it would make GDB treat these 64-bit programs
5998 as 32-bit programs by default. */
6000 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6001 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
6002 set_gdbarch_deprecated_target_read_fp (gdbarch
, mips_read_sp
); /* Draft FRAME base. */
6003 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6005 /* Add/remove bits from an address. The MIPS needs be careful to
6006 ensure that all 32 bit addresses are sign extended to 64 bits. */
6007 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6009 /* There's a mess in stack frame creation. See comments in
6010 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
6011 set_gdbarch_deprecated_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
6013 /* Map debug register numbers onto internal register numbers. */
6014 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6015 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6016 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6017 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6018 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6020 /* Initialize a frame */
6021 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch
, mips_find_saved_regs
);
6022 set_gdbarch_deprecated_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
6024 /* MIPS version of CALL_DUMMY */
6026 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6027 replaced by a command, and all targets will default to on stack
6028 (regardless of the stack's execute status). */
6029 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6030 set_gdbarch_deprecated_pop_frame (gdbarch
, mips_pop_frame
);
6031 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6032 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
6034 set_gdbarch_deprecated_frame_chain (gdbarch
, mips_frame_chain
);
6035 set_gdbarch_frameless_function_invocation (gdbarch
,
6036 generic_frameless_function_invocation_not
);
6037 set_gdbarch_deprecated_frame_saved_pc (gdbarch
, mips_frame_saved_pc
);
6038 set_gdbarch_frame_args_skip (gdbarch
, 0);
6040 set_gdbarch_deprecated_get_saved_register (gdbarch
, mips_get_saved_register
);
6042 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6043 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6044 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
6046 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6047 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
6049 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6050 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6051 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6053 set_gdbarch_function_start_offset (gdbarch
, 0);
6055 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6057 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6058 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
6060 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6062 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6063 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6064 need to all be folded into the target vector. Since they are
6065 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6066 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6068 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6070 /* Hook in OS ABI-specific overrides, if they have been registered. */
6071 gdbarch_init_osabi (info
, gdbarch
);
6073 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6075 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6076 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6082 mips_abi_update (char *ignore_args
, int from_tty
,
6083 struct cmd_list_element
*c
)
6085 struct gdbarch_info info
;
6087 /* Force the architecture to update, and (if it's a MIPS architecture)
6088 mips_gdbarch_init will take care of the rest. */
6089 gdbarch_info_init (&info
);
6090 gdbarch_update_p (info
);
6093 /* Print out which MIPS ABI is in use. */
6096 show_mips_abi (char *ignore_args
, int from_tty
)
6098 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6100 "The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6103 enum mips_abi global_abi
= global_mips_abi ();
6104 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6105 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6107 if (global_abi
== MIPS_ABI_UNKNOWN
)
6108 printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n",
6110 else if (global_abi
== actual_abi
)
6112 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6116 /* Probably shouldn't happen... */
6118 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6120 mips_abi_strings
[global_abi
]);
6126 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6128 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6132 int ef_mips_32bitmode
;
6133 /* determine the ISA */
6134 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6152 /* determine the size of a pointer */
6153 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6154 fprintf_unfiltered (file
,
6155 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6157 fprintf_unfiltered (file
,
6158 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6160 fprintf_unfiltered (file
,
6161 "mips_dump_tdep: ef_mips_arch = %d\n",
6163 fprintf_unfiltered (file
,
6164 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6166 mips_abi_strings
[tdep
->mips_abi
]);
6167 fprintf_unfiltered (file
,
6168 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6169 mips_mask_address_p (tdep
),
6170 tdep
->default_mask_address_p
);
6172 fprintf_unfiltered (file
,
6173 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6174 FP_REGISTER_DOUBLE
);
6175 fprintf_unfiltered (file
,
6176 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6177 MIPS_DEFAULT_FPU_TYPE
,
6178 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6179 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6180 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6182 fprintf_unfiltered (file
,
6183 "mips_dump_tdep: MIPS_EABI = %d\n",
6185 fprintf_unfiltered (file
,
6186 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6188 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6189 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6190 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6192 fprintf_unfiltered (file
,
6193 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6194 FP_REGISTER_DOUBLE
);
6195 fprintf_unfiltered (file
,
6196 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6197 mips_stack_argsize (tdep
));
6198 fprintf_unfiltered (file
,
6199 "mips_dump_tdep: A0_REGNUM = %d\n",
6201 fprintf_unfiltered (file
,
6202 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6203 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
6204 fprintf_unfiltered (file
,
6205 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6206 XSTRING (ATTACH_DETACH
));
6207 fprintf_unfiltered (file
,
6208 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6209 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6210 fprintf_unfiltered (file
,
6211 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6212 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6213 fprintf_unfiltered (file
,
6214 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6215 FIRST_EMBED_REGNUM
);
6216 fprintf_unfiltered (file
,
6217 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6218 XSTRING (IGNORE_HELPER_CALL (PC
)));
6219 fprintf_unfiltered (file
,
6220 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6221 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6222 fprintf_unfiltered (file
,
6223 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6224 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6225 fprintf_unfiltered (file
,
6226 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6228 #ifdef MACHINE_CPROC_FP_OFFSET
6229 fprintf_unfiltered (file
,
6230 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6231 MACHINE_CPROC_FP_OFFSET
);
6233 #ifdef MACHINE_CPROC_PC_OFFSET
6234 fprintf_unfiltered (file
,
6235 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6236 MACHINE_CPROC_PC_OFFSET
);
6238 #ifdef MACHINE_CPROC_SP_OFFSET
6239 fprintf_unfiltered (file
,
6240 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6241 MACHINE_CPROC_SP_OFFSET
);
6243 fprintf_unfiltered (file
,
6244 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6246 fprintf_unfiltered (file
,
6247 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6248 fprintf_unfiltered (file
,
6249 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6250 fprintf_unfiltered (file
,
6251 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6253 fprintf_unfiltered (file
,
6254 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6255 MIPS_LAST_ARG_REGNUM
,
6256 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6257 fprintf_unfiltered (file
,
6258 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6260 fprintf_unfiltered (file
,
6261 "mips_dump_tdep: mips_saved_regsize() = %d\n",
6262 mips_saved_regsize (tdep
));
6263 fprintf_unfiltered (file
,
6264 "mips_dump_tdep: PRID_REGNUM = %d\n",
6266 fprintf_unfiltered (file
,
6267 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6268 fprintf_unfiltered (file
,
6269 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6270 fprintf_unfiltered (file
,
6271 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6272 fprintf_unfiltered (file
,
6273 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6274 fprintf_unfiltered (file
,
6275 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6276 fprintf_unfiltered (file
,
6277 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6278 fprintf_unfiltered (file
,
6279 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6280 fprintf_unfiltered (file
,
6281 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6282 fprintf_unfiltered (file
,
6283 "mips_dump_tdep: PROC_PC_REG = function?\n");
6284 fprintf_unfiltered (file
,
6285 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6286 fprintf_unfiltered (file
,
6287 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6288 fprintf_unfiltered (file
,
6289 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6290 fprintf_unfiltered (file
,
6291 "mips_dump_tdep: PS_REGNUM = %d\n",
6293 fprintf_unfiltered (file
,
6294 "mips_dump_tdep: RA_REGNUM = %d\n",
6297 fprintf_unfiltered (file
,
6298 "mips_dump_tdep: SAVED_BYTES = %d\n",
6302 fprintf_unfiltered (file
,
6303 "mips_dump_tdep: SAVED_FP = %d\n",
6307 fprintf_unfiltered (file
,
6308 "mips_dump_tdep: SAVED_PC = %d\n",
6311 fprintf_unfiltered (file
,
6312 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6313 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6314 fprintf_unfiltered (file
,
6315 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6316 fprintf_unfiltered (file
,
6317 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6319 fprintf_unfiltered (file
,
6320 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6321 SIGFRAME_FPREGSAVE_OFF
);
6322 fprintf_unfiltered (file
,
6323 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6325 fprintf_unfiltered (file
,
6326 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6327 SIGFRAME_REGSAVE_OFF
);
6328 fprintf_unfiltered (file
,
6329 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6330 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6331 fprintf_unfiltered (file
,
6332 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6333 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6334 fprintf_unfiltered (file
,
6335 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6336 SOFTWARE_SINGLE_STEP_P ());
6337 fprintf_unfiltered (file
,
6338 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6339 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6340 #ifdef STACK_END_ADDR
6341 fprintf_unfiltered (file
,
6342 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6345 fprintf_unfiltered (file
,
6346 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6347 XSTRING (STEP_SKIPS_DELAY (PC
)));
6348 fprintf_unfiltered (file
,
6349 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6350 STEP_SKIPS_DELAY_P
);
6351 fprintf_unfiltered (file
,
6352 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6353 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6354 fprintf_unfiltered (file
,
6355 "mips_dump_tdep: T9_REGNUM = %d\n",
6357 fprintf_unfiltered (file
,
6358 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6359 fprintf_unfiltered (file
,
6360 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6361 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
6362 fprintf_unfiltered (file
,
6363 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6364 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6366 fprintf_unfiltered (file
,
6367 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6368 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6371 fprintf_unfiltered (file
,
6372 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6375 #ifdef TRACE_FLAVOR_SIZE
6376 fprintf_unfiltered (file
,
6377 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6381 fprintf_unfiltered (file
,
6382 "mips_dump_tdep: TRACE_SET # %s\n",
6383 XSTRING (TRACE_SET (X
,STATE
)));
6385 #ifdef UNUSED_REGNUM
6386 fprintf_unfiltered (file
,
6387 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6390 fprintf_unfiltered (file
,
6391 "mips_dump_tdep: V0_REGNUM = %d\n",
6393 fprintf_unfiltered (file
,
6394 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6395 (long) VM_MIN_ADDRESS
);
6396 fprintf_unfiltered (file
,
6397 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6399 fprintf_unfiltered (file
,
6400 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6404 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6407 _initialize_mips_tdep (void)
6409 static struct cmd_list_element
*mipsfpulist
= NULL
;
6410 struct cmd_list_element
*c
;
6412 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6413 if (MIPS_ABI_LAST
+ 1
6414 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6415 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6417 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6419 /* Add root prefix command for all "set mips"/"show mips" commands */
6420 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6421 "Various MIPS specific commands.",
6422 &setmipscmdlist
, "set mips ", 0, &setlist
);
6424 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6425 "Various MIPS specific commands.",
6426 &showmipscmdlist
, "show mips ", 0, &showlist
);
6428 /* Allow the user to override the saved register size. */
6429 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6432 &mips_saved_regsize_string
, "\
6433 Set size of general purpose registers saved on the stack.\n\
6434 This option can be set to one of:\n\
6435 32 - Force GDB to treat saved GP registers as 32-bit\n\
6436 64 - Force GDB to treat saved GP registers as 64-bit\n\
6437 auto - Allow GDB to use the target's default setting or autodetect the\n\
6438 saved GP register size from information contained in the executable.\n\
6443 /* Allow the user to override the argument stack size. */
6444 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6447 &mips_stack_argsize_string
, "\
6448 Set the amount of stack space reserved for each argument.\n\
6449 This option can be set to one of:\n\
6450 32 - Force GDB to allocate 32-bit chunks per argument\n\
6451 64 - Force GDB to allocate 64-bit chunks per argument\n\
6452 auto - Allow GDB to determine the correct setting from the current\n\
6453 target and executable (default)",
6457 /* Allow the user to override the ABI. */
6458 c
= add_set_enum_cmd
6459 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6460 "Set the ABI used by this program.\n"
6461 "This option can be set to one of:\n"
6462 " auto - the default ABI associated with the current binary\n"
6470 set_cmd_sfunc (c
, mips_abi_update
);
6471 add_cmd ("abi", class_obscure
, show_mips_abi
,
6472 "Show ABI in use by MIPS target", &showmipscmdlist
);
6474 /* Let the user turn off floating point and set the fence post for
6475 heuristic_proc_start. */
6477 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6478 "Set use of MIPS floating-point coprocessor.",
6479 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6480 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6481 "Select single-precision MIPS floating-point coprocessor.",
6483 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6484 "Select double-precision MIPS floating-point coprocessor.",
6486 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6487 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6488 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6489 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6490 "Select no MIPS floating-point coprocessor.",
6492 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6493 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6494 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6495 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6496 "Select MIPS floating-point coprocessor automatically.",
6498 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6499 "Show current use of MIPS floating-point coprocessor target.",
6502 /* We really would like to have both "0" and "unlimited" work, but
6503 command.c doesn't deal with that. So make it a var_zinteger
6504 because the user can always use "999999" or some such for unlimited. */
6505 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6506 (char *) &heuristic_fence_post
,
6508 Set the distance searched for the start of a function.\n\
6509 If you are debugging a stripped executable, GDB needs to search through the\n\
6510 program for the start of a function. This command sets the distance of the\n\
6511 search. The only need to set it is when debugging a stripped executable.",
6513 /* We need to throw away the frame cache when we set this, since it
6514 might change our ability to get backtraces. */
6515 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6516 add_show_from_set (c
, &showlist
);
6518 /* Allow the user to control whether the upper bits of 64-bit
6519 addresses should be zeroed. */
6520 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6521 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6522 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6523 allow GDB to determine the correct value.\n", "\
6524 Show zeroing of upper 32 bits of 64-bit addresses.",
6525 NULL
, show_mask_address
,
6526 &setmipscmdlist
, &showmipscmdlist
);
6528 /* Allow the user to control the size of 32 bit registers within the
6529 raw remote packet. */
6530 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6531 var_boolean
, &mips64_transfers_32bit_regs_p
, "\
6532 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6533 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6534 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6535 64 bits for others. Use \"off\" to disable compatibility mode", "\
6536 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6537 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6538 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6539 64 bits for others. Use \"off\" to disable compatibility mode",
6540 set_mips64_transfers_32bit_regs
, NULL
,
6541 &setlist
, &showlist
);
6543 /* Debug this files internals. */
6544 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6545 &mips_debug
, "Set mips debugging.\n\
6546 When non-zero, mips specific debugging is enabled.", &setdebuglist
),