1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
62 static const struct objfile_data
*mips_pdr_data
;
64 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
66 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
67 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
68 #define ST0_FR (1 << 26)
70 /* The sizes of floating point registers. */
74 MIPS_FPU_SINGLE_REGSIZE
= 4,
75 MIPS_FPU_DOUBLE_REGSIZE
= 8
84 static const char *mips_abi_string
;
86 static const char *mips_abi_strings
[] = {
97 /* The standard register names, and all the valid aliases for them. */
104 /* Aliases for o32 and most other ABIs. */
105 const struct register_alias mips_o32_aliases
[] = {
112 /* Aliases for n32 and n64. */
113 const struct register_alias mips_n32_n64_aliases
[] = {
120 /* Aliases for ABI-independent registers. */
121 const struct register_alias mips_register_aliases
[] = {
122 /* The architecture manuals specify these ABI-independent names for
124 #define R(n) { "r" #n, n }
125 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
126 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
127 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
128 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
131 /* k0 and k1 are sometimes called these instead (for "kernel
136 /* This is the traditional GDB name for the CP0 status register. */
137 { "sr", MIPS_PS_REGNUM
},
139 /* This is the traditional GDB name for the CP0 BadVAddr register. */
140 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
142 /* This is the traditional GDB name for the FCSR. */
143 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
146 const struct register_alias mips_numeric_register_aliases
[] = {
147 #define R(n) { #n, n }
148 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
149 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
150 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
151 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto
= 1;
159 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
161 static int mips_debug
= 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc
*mips_tdesc_gp32
;
169 struct target_desc
*mips_tdesc_gp64
;
171 const struct mips_regnum
*
172 mips_regnum (struct gdbarch
*gdbarch
)
174 return gdbarch_tdep (gdbarch
)->regnum
;
178 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
180 return mips_regnum (gdbarch
)->fp0
+ 12;
183 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
185 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
187 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
189 #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
191 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
193 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
194 functions to test, set, or clear bit 0 of addresses. */
197 is_mips16_addr (CORE_ADDR addr
)
203 unmake_mips16_addr (CORE_ADDR addr
)
205 return ((addr
) & ~(CORE_ADDR
) 1);
208 /* Return the MIPS ABI associated with GDBARCH. */
210 mips_abi (struct gdbarch
*gdbarch
)
212 return gdbarch_tdep (gdbarch
)->mips_abi
;
216 mips_isa_regsize (struct gdbarch
*gdbarch
)
218 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
220 /* If we know how big the registers are, use that size. */
221 if (tdep
->register_size_valid_p
)
222 return tdep
->register_size
;
224 /* Fall back to the previous behavior. */
225 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
226 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
229 /* Return the currently configured (or set) saved register size. */
232 mips_abi_regsize (struct gdbarch
*gdbarch
)
234 switch (mips_abi (gdbarch
))
236 case MIPS_ABI_EABI32
:
242 case MIPS_ABI_EABI64
:
244 case MIPS_ABI_UNKNOWN
:
247 internal_error (__FILE__
, __LINE__
, _("bad switch"));
251 /* Functions for setting and testing a bit in a minimal symbol that
252 marks it as 16-bit function. The MSB of the minimal symbol's
253 "info" field is used for this purpose.
255 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
256 i.e. refers to a 16-bit function, and sets a "special" bit in a
257 minimal symbol to mark it as a 16-bit function
259 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
262 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
264 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
266 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
267 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
272 msymbol_is_special (struct minimal_symbol
*msym
)
274 return MSYMBOL_TARGET_FLAG_1 (msym
);
277 /* XFER a value from the big/little/left end of the register.
278 Depending on the size of the value it might occupy the entire
279 register or just part of it. Make an allowance for this, aligning
280 things accordingly. */
283 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
284 int reg_num
, int length
,
285 enum bfd_endian endian
, gdb_byte
*in
,
286 const gdb_byte
*out
, int buf_offset
)
290 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
291 /* Need to transfer the left or right part of the register, based on
292 the targets byte order. */
296 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
298 case BFD_ENDIAN_LITTLE
:
301 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
305 internal_error (__FILE__
, __LINE__
, _("bad switch"));
308 fprintf_unfiltered (gdb_stderr
,
309 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
310 reg_num
, reg_offset
, buf_offset
, length
);
311 if (mips_debug
&& out
!= NULL
)
314 fprintf_unfiltered (gdb_stdlog
, "out ");
315 for (i
= 0; i
< length
; i
++)
316 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
319 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
322 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
324 if (mips_debug
&& in
!= NULL
)
327 fprintf_unfiltered (gdb_stdlog
, "in ");
328 for (i
= 0; i
< length
; i
++)
329 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
332 fprintf_unfiltered (gdb_stdlog
, "\n");
335 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
336 compatiblity mode. A return value of 1 means that we have
337 physical 64-bit registers, but should treat them as 32-bit registers. */
340 mips2_fp_compat (struct frame_info
*frame
)
342 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
343 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
345 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
349 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
350 in all the places we deal with FP registers. PR gdb/413. */
351 /* Otherwise check the FR bit in the status register - it controls
352 the FP compatiblity mode. If it is clear we are in compatibility
354 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
361 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
363 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
365 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
367 /* The list of available "set mips " and "show mips " commands */
369 static struct cmd_list_element
*setmipscmdlist
= NULL
;
370 static struct cmd_list_element
*showmipscmdlist
= NULL
;
372 /* Integer registers 0 thru 31 are handled explicitly by
373 mips_register_name(). Processor specific registers 32 and above
374 are listed in the following tables. */
377 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
381 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
382 "sr", "lo", "hi", "bad", "cause", "pc",
383 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
384 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
385 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
386 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
387 "fsr", "fir", "" /*"fp" */ , "",
388 "", "", "", "", "", "", "", "",
389 "", "", "", "", "", "", "", "",
392 /* Names of IDT R3041 registers. */
394 static const char *mips_r3041_reg_names
[] = {
395 "sr", "lo", "hi", "bad", "cause", "pc",
396 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
397 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
398 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
399 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
400 "fsr", "fir", "", /*"fp" */ "",
401 "", "", "bus", "ccfg", "", "", "", "",
402 "", "", "port", "cmp", "", "", "epc", "prid",
405 /* Names of tx39 registers. */
407 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
408 "sr", "lo", "hi", "bad", "cause", "pc",
409 "", "", "", "", "", "", "", "",
410 "", "", "", "", "", "", "", "",
411 "", "", "", "", "", "", "", "",
412 "", "", "", "", "", "", "", "",
414 "", "", "", "", "", "", "", "",
415 "", "", "config", "cache", "debug", "depc", "epc", ""
418 /* Names of IRIX registers. */
419 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
420 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
421 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
422 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
423 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
424 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
428 /* Return the name of the register corresponding to REGNO. */
430 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
432 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
433 /* GPR names for all ABIs other than n32/n64. */
434 static char *mips_gpr_names
[] = {
435 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
436 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
437 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
438 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
441 /* GPR names for n32 and n64 ABIs. */
442 static char *mips_n32_n64_gpr_names
[] = {
443 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
444 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
445 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
446 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
449 enum mips_abi abi
= mips_abi (gdbarch
);
451 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
452 but then don't make the raw register names visible. */
453 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
454 if (regno
< gdbarch_num_regs (gdbarch
))
457 /* The MIPS integer registers are always mapped from 0 to 31. The
458 names of the registers (which reflects the conventions regarding
459 register use) vary depending on the ABI. */
460 if (0 <= rawnum
&& rawnum
< 32)
462 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
463 return mips_n32_n64_gpr_names
[rawnum
];
465 return mips_gpr_names
[rawnum
];
467 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
468 return tdesc_register_name (gdbarch
, rawnum
);
469 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
471 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
472 return tdep
->mips_processor_reg_names
[rawnum
- 32];
475 internal_error (__FILE__
, __LINE__
,
476 _("mips_register_name: bad register number %d"), rawnum
);
479 /* Return the groups that a MIPS register can be categorised into. */
482 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
483 struct reggroup
*reggroup
)
488 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
489 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
490 if (reggroup
== all_reggroup
)
492 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
493 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
494 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
495 (gdbarch), as not all architectures are multi-arch. */
496 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
497 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
498 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
500 if (reggroup
== float_reggroup
)
501 return float_p
&& pseudo
;
502 if (reggroup
== vector_reggroup
)
503 return vector_p
&& pseudo
;
504 if (reggroup
== general_reggroup
)
505 return (!vector_p
&& !float_p
) && pseudo
;
506 /* Save the pseudo registers. Need to make certain that any code
507 extracting register values from a saved register cache also uses
509 if (reggroup
== save_reggroup
)
510 return raw_p
&& pseudo
;
511 /* Restore the same pseudo register. */
512 if (reggroup
== restore_reggroup
)
513 return raw_p
&& pseudo
;
517 /* Return the groups that a MIPS register can be categorised into.
518 This version is only used if we have a target description which
519 describes real registers (and their groups). */
522 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
523 struct reggroup
*reggroup
)
525 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
526 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
529 /* Only save, restore, and display the pseudo registers. Need to
530 make certain that any code extracting register values from a
531 saved register cache also uses pseudo registers.
533 Note: saving and restoring the pseudo registers is slightly
534 strange; if we have 64 bits, we should save and restore all
535 64 bits. But this is hard and has little benefit. */
539 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
543 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
546 /* Map the symbol table registers which live in the range [1 *
547 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
548 registers. Take care of alignment and size problems. */
551 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
552 int cookednum
, gdb_byte
*buf
)
554 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
555 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
556 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
557 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
558 regcache_raw_read (regcache
, rawnum
, buf
);
559 else if (register_size (gdbarch
, rawnum
) >
560 register_size (gdbarch
, cookednum
))
562 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
563 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
564 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
566 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
569 internal_error (__FILE__
, __LINE__
, _("bad register size"));
573 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
574 struct regcache
*regcache
, int cookednum
,
577 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
578 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
579 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
580 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
581 regcache_raw_write (regcache
, rawnum
, buf
);
582 else if (register_size (gdbarch
, rawnum
) >
583 register_size (gdbarch
, cookednum
))
585 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
586 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
587 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
589 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
592 internal_error (__FILE__
, __LINE__
, _("bad register size"));
595 /* Table to translate MIPS16 register field to actual register number. */
596 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
598 /* Heuristic_proc_start may hunt through the text section for a long
599 time across a 2400 baud serial line. Allows the user to limit this
602 static unsigned int heuristic_fence_post
= 0;
604 /* Number of bytes of storage in the actual machine representation for
605 register N. NOTE: This defines the pseudo register type so need to
606 rebuild the architecture vector. */
608 static int mips64_transfers_32bit_regs_p
= 0;
611 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
612 struct cmd_list_element
*c
)
614 struct gdbarch_info info
;
615 gdbarch_info_init (&info
);
616 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
617 instead of relying on globals. Doing that would let generic code
618 handle the search for this specific architecture. */
619 if (!gdbarch_update_p (info
))
621 mips64_transfers_32bit_regs_p
= 0;
622 error (_("32-bit compatibility mode not supported"));
626 /* Convert to/from a register and the corresponding memory value. */
629 mips_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
631 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
632 && register_size (gdbarch
, regnum
) == 4
633 && (regnum
% gdbarch_num_regs (gdbarch
))
634 >= mips_regnum (gdbarch
)->fp0
635 && (regnum
% gdbarch_num_regs (gdbarch
))
636 < mips_regnum (gdbarch
)->fp0
+ 32
637 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
641 mips_register_to_value (struct frame_info
*frame
, int regnum
,
642 struct type
*type
, gdb_byte
*to
)
644 get_frame_register (frame
, regnum
+ 0, to
+ 4);
645 get_frame_register (frame
, regnum
+ 1, to
+ 0);
649 mips_value_to_register (struct frame_info
*frame
, int regnum
,
650 struct type
*type
, const gdb_byte
*from
)
652 put_frame_register (frame
, regnum
+ 0, from
+ 4);
653 put_frame_register (frame
, regnum
+ 1, from
+ 0);
656 /* Return the GDB type object for the "standard" data type of data in
660 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
662 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
663 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
664 && (regnum
% gdbarch_num_regs (gdbarch
))
665 < mips_regnum (gdbarch
)->fp0
+ 32)
667 /* The floating-point registers raw, or cooked, always match
668 mips_isa_regsize(), and also map 1:1, byte for byte. */
669 if (mips_isa_regsize (gdbarch
) == 4)
670 return builtin_type (gdbarch
)->builtin_float
;
672 return builtin_type (gdbarch
)->builtin_double
;
674 else if (regnum
< gdbarch_num_regs (gdbarch
))
676 /* The raw or ISA registers. These are all sized according to
678 if (mips_isa_regsize (gdbarch
) == 4)
679 return builtin_type (gdbarch
)->builtin_int32
;
681 return builtin_type (gdbarch
)->builtin_int64
;
685 /* The cooked or ABI registers. These are sized according to
686 the ABI (with a few complications). */
687 if (regnum
>= (gdbarch_num_regs (gdbarch
)
688 + mips_regnum (gdbarch
)->fp_control_status
)
689 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
690 /* The pseudo/cooked view of the embedded registers is always
691 32-bit. The raw view is handled below. */
692 return builtin_type (gdbarch
)->builtin_int32
;
693 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
694 /* The target, while possibly using a 64-bit register buffer,
695 is only transfering 32-bits of each integer register.
696 Reflect this in the cooked/pseudo (ABI) register value. */
697 return builtin_type (gdbarch
)->builtin_int32
;
698 else if (mips_abi_regsize (gdbarch
) == 4)
699 /* The ABI is restricted to 32-bit registers (the ISA could be
701 return builtin_type (gdbarch
)->builtin_int32
;
704 return builtin_type (gdbarch
)->builtin_int64
;
708 /* Return the GDB type for the pseudo register REGNUM, which is the
709 ABI-level view. This function is only called if there is a target
710 description which includes registers, so we know precisely the
711 types of hardware registers. */
714 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
716 const int num_regs
= gdbarch_num_regs (gdbarch
);
717 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
718 int rawnum
= regnum
% num_regs
;
719 struct type
*rawtype
;
721 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
723 /* Absent registers are still absent. */
724 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
725 if (TYPE_LENGTH (rawtype
) == 0)
728 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
729 /* Present the floating point registers however the hardware did;
730 do not try to convert between FPU layouts. */
733 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
735 /* The pseudo/cooked view of embedded registers is always
736 32-bit, even if the target transfers 64-bit values for them.
737 New targets relying on XML descriptions should only transfer
738 the necessary 32 bits, but older versions of GDB expected 64,
739 so allow the target to provide 64 bits without interfering
740 with the displayed type. */
741 return builtin_type (gdbarch
)->builtin_int32
;
744 /* Use pointer types for registers if we can. For n32 we can not,
745 since we do not have a 64-bit pointer type. */
746 if (mips_abi_regsize (gdbarch
)
747 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
749 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
750 return builtin_type (gdbarch
)->builtin_data_ptr
;
751 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
752 return builtin_type (gdbarch
)->builtin_func_ptr
;
755 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
756 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
757 return builtin_type (gdbarch
)->builtin_int32
;
759 /* For all other registers, pass through the hardware type. */
763 /* Should the upper word of 64-bit addresses be zeroed? */
764 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
767 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
769 switch (mask_address_var
)
771 case AUTO_BOOLEAN_TRUE
:
773 case AUTO_BOOLEAN_FALSE
:
776 case AUTO_BOOLEAN_AUTO
:
777 return tdep
->default_mask_address_p
;
779 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
785 show_mask_address (struct ui_file
*file
, int from_tty
,
786 struct cmd_list_element
*c
, const char *value
)
788 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
790 deprecated_show_value_hack (file
, from_tty
, c
, value
);
791 switch (mask_address_var
)
793 case AUTO_BOOLEAN_TRUE
:
794 printf_filtered ("The 32 bit mips address mask is enabled\n");
796 case AUTO_BOOLEAN_FALSE
:
797 printf_filtered ("The 32 bit mips address mask is disabled\n");
799 case AUTO_BOOLEAN_AUTO
:
801 ("The 32 bit address mask is set automatically. Currently %s\n",
802 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
805 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
810 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
813 mips_pc_is_mips16 (CORE_ADDR memaddr
)
815 struct minimal_symbol
*sym
;
817 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
818 if (is_mips16_addr (memaddr
))
821 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
822 the high bit of the info field. Use this to decide if the function is
823 MIPS16 or normal MIPS. */
824 sym
= lookup_minimal_symbol_by_pc (memaddr
);
826 return msymbol_is_special (sym
);
831 /* MIPS believes that the PC has a sign extended value. Perhaps the
832 all registers should be sign extended for simplicity? */
835 mips_read_pc (struct regcache
*regcache
)
838 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
839 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
844 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
846 return frame_unwind_register_signed
847 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
851 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
853 return frame_unwind_register_signed
854 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
857 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
858 dummy frame. The frame ID's base needs to match the TOS value
859 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
862 static struct frame_id
863 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
865 return frame_id_build
866 (get_frame_register_signed (this_frame
,
867 gdbarch_num_regs (gdbarch
)
869 get_frame_pc (this_frame
));
873 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
875 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
876 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
879 /* Fetch and return instruction from the specified location. If the PC
880 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
883 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
885 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
886 gdb_byte buf
[MIPS_INSN32_SIZE
];
890 if (mips_pc_is_mips16 (addr
))
892 instlen
= MIPS_INSN16_SIZE
;
893 addr
= unmake_mips16_addr (addr
);
896 instlen
= MIPS_INSN32_SIZE
;
897 status
= target_read_memory (addr
, buf
, instlen
);
899 memory_error (status
, addr
);
900 return extract_unsigned_integer (buf
, instlen
, byte_order
);
903 /* These the fields of 32 bit mips instructions */
904 #define mips32_op(x) (x >> 26)
905 #define itype_op(x) (x >> 26)
906 #define itype_rs(x) ((x >> 21) & 0x1f)
907 #define itype_rt(x) ((x >> 16) & 0x1f)
908 #define itype_immediate(x) (x & 0xffff)
910 #define jtype_op(x) (x >> 26)
911 #define jtype_target(x) (x & 0x03ffffff)
913 #define rtype_op(x) (x >> 26)
914 #define rtype_rs(x) ((x >> 21) & 0x1f)
915 #define rtype_rt(x) ((x >> 16) & 0x1f)
916 #define rtype_rd(x) ((x >> 11) & 0x1f)
917 #define rtype_shamt(x) ((x >> 6) & 0x1f)
918 #define rtype_funct(x) (x & 0x3f)
921 mips32_relative_offset (ULONGEST inst
)
923 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
926 /* Determine where to set a single step breakpoint while considering
927 branch prediction. */
929 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
931 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
934 inst
= mips_fetch_instruction (gdbarch
, pc
);
935 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
937 if (itype_op (inst
) >> 2 == 5)
938 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
940 op
= (itype_op (inst
) & 0x03);
955 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
956 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
958 int tf
= itype_rt (inst
) & 0x01;
959 int cnum
= itype_rt (inst
) >> 2;
961 get_frame_register_signed (frame
,
962 mips_regnum (get_frame_arch (frame
))->
964 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
966 if (((cond
>> cnum
) & 0x01) == tf
)
967 pc
+= mips32_relative_offset (inst
) + 4;
972 pc
+= 4; /* Not a branch, next instruction is easy */
975 { /* This gets way messy */
977 /* Further subdivide into SPECIAL, REGIMM and other */
978 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
980 case 0: /* SPECIAL */
981 op
= rtype_funct (inst
);
986 /* Set PC to that address */
987 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
989 case 12: /* SYSCALL */
991 struct gdbarch_tdep
*tdep
;
993 tdep
= gdbarch_tdep (get_frame_arch (frame
));
994 if (tdep
->syscall_next_pc
!= NULL
)
995 pc
= tdep
->syscall_next_pc (frame
);
1004 break; /* end SPECIAL */
1005 case 1: /* REGIMM */
1007 op
= itype_rt (inst
); /* branch condition */
1012 case 16: /* BLTZAL */
1013 case 18: /* BLTZALL */
1015 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1016 pc
+= mips32_relative_offset (inst
) + 4;
1018 pc
+= 8; /* after the delay slot */
1022 case 17: /* BGEZAL */
1023 case 19: /* BGEZALL */
1024 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1025 pc
+= mips32_relative_offset (inst
) + 4;
1027 pc
+= 8; /* after the delay slot */
1029 /* All of the other instructions in the REGIMM category */
1034 break; /* end REGIMM */
1039 reg
= jtype_target (inst
) << 2;
1040 /* Upper four bits get never changed... */
1041 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1044 /* FIXME case JALX : */
1047 reg
= jtype_target (inst
) << 2;
1048 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1049 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1051 break; /* The new PC will be alternate mode */
1052 case 4: /* BEQ, BEQL */
1054 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1055 get_frame_register_signed (frame
, itype_rt (inst
)))
1056 pc
+= mips32_relative_offset (inst
) + 4;
1060 case 5: /* BNE, BNEL */
1062 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1063 get_frame_register_signed (frame
, itype_rt (inst
)))
1064 pc
+= mips32_relative_offset (inst
) + 4;
1068 case 6: /* BLEZ, BLEZL */
1069 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1070 pc
+= mips32_relative_offset (inst
) + 4;
1076 greater_branch
: /* BGTZ, BGTZL */
1077 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1078 pc
+= mips32_relative_offset (inst
) + 4;
1085 } /* mips32_next_pc */
1087 /* Decoding the next place to set a breakpoint is irregular for the
1088 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1089 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1090 We dont want to set a single step instruction on the extend instruction
1094 /* Lots of mips16 instruction formats */
1095 /* Predicting jumps requires itype,ritype,i8type
1096 and their extensions extItype,extritype,extI8type
1098 enum mips16_inst_fmts
1100 itype
, /* 0 immediate 5,10 */
1101 ritype
, /* 1 5,3,8 */
1102 rrtype
, /* 2 5,3,3,5 */
1103 rritype
, /* 3 5,3,3,5 */
1104 rrrtype
, /* 4 5,3,3,3,2 */
1105 rriatype
, /* 5 5,3,3,1,4 */
1106 shifttype
, /* 6 5,3,3,3,2 */
1107 i8type
, /* 7 5,3,8 */
1108 i8movtype
, /* 8 5,3,3,5 */
1109 i8mov32rtype
, /* 9 5,3,5,3 */
1110 i64type
, /* 10 5,3,8 */
1111 ri64type
, /* 11 5,3,3,5 */
1112 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1113 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1114 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1115 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1116 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1117 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1118 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1119 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1120 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1121 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1123 /* I am heaping all the fields of the formats into one structure and
1124 then, only the fields which are involved in instruction extension */
1128 unsigned int regx
; /* Function in i8 type */
1133 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1134 for the bits which make up the immediate extension. */
1137 extended_offset (unsigned int extension
)
1140 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1142 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1144 value
|= extension
& 0x01f; /* extract 4:0 */
1148 /* Only call this function if you know that this is an extendable
1149 instruction. It won't malfunction, but why make excess remote memory
1150 references? If the immediate operands get sign extended or something,
1151 do it after the extension is performed. */
1152 /* FIXME: Every one of these cases needs to worry about sign extension
1153 when the offset is to be used in relative addressing. */
1156 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1158 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1160 pc
&= 0xfffffffe; /* clear the low order bit */
1161 target_read_memory (pc
, buf
, 2);
1162 return extract_unsigned_integer (buf
, 2, byte_order
);
1166 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1167 unsigned int extension
,
1169 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1174 switch (insn_format
)
1181 value
= extended_offset (extension
);
1182 value
= value
<< 11; /* rom for the original value */
1183 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1187 value
= inst
& 0x7ff;
1188 /* FIXME : Consider sign extension */
1197 { /* A register identifier and an offset */
1198 /* Most of the fields are the same as I type but the
1199 immediate value is of a different length */
1203 value
= extended_offset (extension
);
1204 value
= value
<< 8; /* from the original instruction */
1205 value
|= inst
& 0xff; /* eleven bits from instruction */
1206 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1207 if (value
& 0x4000) /* test the sign bit , bit 26 */
1209 value
&= ~0x3fff; /* remove the sign bit */
1215 value
= inst
& 0xff; /* 8 bits */
1216 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1217 /* FIXME: Do sign extension , this format needs it */
1218 if (value
& 0x80) /* THIS CONFUSES ME */
1220 value
&= 0xef; /* remove the sign bit */
1230 unsigned long value
;
1231 unsigned int nexthalf
;
1232 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1233 value
= value
<< 16;
1234 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit still set */
1242 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1244 upk
->offset
= offset
;
1251 add_offset_16 (CORE_ADDR pc
, int offset
)
1253 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1257 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1258 unsigned int extension
, unsigned int insn
)
1260 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1261 int op
= (insn
>> 11);
1264 case 2: /* Branch */
1267 struct upk_mips16 upk
;
1268 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1269 offset
= upk
.offset
;
1275 pc
+= (offset
<< 1) + 2;
1278 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1280 struct upk_mips16 upk
;
1281 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1282 pc
= add_offset_16 (pc
, upk
.offset
);
1283 if ((insn
>> 10) & 0x01) /* Exchange mode */
1284 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1291 struct upk_mips16 upk
;
1293 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1294 reg
= get_frame_register_signed (frame
, upk
.regx
);
1296 pc
+= (upk
.offset
<< 1) + 2;
1303 struct upk_mips16 upk
;
1305 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1306 reg
= get_frame_register_signed (frame
, upk
.regx
);
1308 pc
+= (upk
.offset
<< 1) + 2;
1313 case 12: /* I8 Formats btez btnez */
1315 struct upk_mips16 upk
;
1317 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1318 /* upk.regx contains the opcode */
1319 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1320 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1321 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1322 /* pc = add_offset_16(pc,upk.offset) ; */
1323 pc
+= (upk
.offset
<< 1) + 2;
1328 case 29: /* RR Formats JR, JALR, JALR-RA */
1330 struct upk_mips16 upk
;
1331 /* upk.fmt = rrtype; */
1336 upk
.regx
= (insn
>> 8) & 0x07;
1337 upk
.regy
= (insn
>> 5) & 0x07;
1345 break; /* Function return instruction */
1351 break; /* BOGUS Guess */
1353 pc
= get_frame_register_signed (frame
, reg
);
1360 /* This is an instruction extension. Fetch the real instruction
1361 (which follows the extension) and decode things based on
1365 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1366 fetch_mips_16 (gdbarch
, pc
));
1379 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1381 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1382 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1383 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1386 /* The mips_next_pc function supports single_step when the remote
1387 target monitor or stub is not developed enough to do a single_step.
1388 It works by decoding the current instruction and predicting where a
1389 branch will go. This isnt hard because all the data is available.
1390 The MIPS32 and MIPS16 variants are quite different. */
1392 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1394 if (is_mips16_addr (pc
))
1395 return mips16_next_pc (frame
, pc
);
1397 return mips32_next_pc (frame
, pc
);
1400 struct mips_frame_cache
1403 struct trad_frame_saved_reg
*saved_regs
;
1406 /* Set a register's saved stack address in temp_saved_regs. If an
1407 address has already been set for this register, do nothing; this
1408 way we will only recognize the first save of a given register in a
1411 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1412 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1413 Strictly speaking, only the second range is used as it is only second
1414 range (the ABI instead of ISA registers) that comes into play when finding
1415 saved registers in a frame. */
1418 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1419 int regnum
, CORE_ADDR offset
)
1421 if (this_cache
!= NULL
1422 && this_cache
->saved_regs
[regnum
].addr
== -1)
1424 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1426 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1432 /* Fetch the immediate value from a MIPS16 instruction.
1433 If the previous instruction was an EXTEND, use it to extend
1434 the upper bits of the immediate value. This is a helper function
1435 for mips16_scan_prologue. */
1438 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1439 unsigned short inst
, /* current instruction */
1440 int nbits
, /* number of bits in imm field */
1441 int scale
, /* scale factor to be applied to imm */
1442 int is_signed
) /* is the imm field signed? */
1446 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1448 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1449 if (offset
& 0x8000) /* check for negative extend */
1450 offset
= 0 - (0x10000 - (offset
& 0xffff));
1451 return offset
| (inst
& 0x1f);
1455 int max_imm
= 1 << nbits
;
1456 int mask
= max_imm
- 1;
1457 int sign_bit
= max_imm
>> 1;
1459 offset
= inst
& mask
;
1460 if (is_signed
&& (offset
& sign_bit
))
1461 offset
= 0 - (max_imm
- offset
);
1462 return offset
* scale
;
1467 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1468 the associated FRAME_CACHE if not null.
1469 Return the address of the first instruction past the prologue. */
1472 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1473 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1474 struct frame_info
*this_frame
,
1475 struct mips_frame_cache
*this_cache
)
1478 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1480 long frame_offset
= 0; /* Size of stack frame. */
1481 long frame_adjust
= 0; /* Offset of FP from SP. */
1482 int frame_reg
= MIPS_SP_REGNUM
;
1483 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1484 unsigned inst
= 0; /* current instruction */
1485 unsigned entry_inst
= 0; /* the entry instruction */
1486 unsigned save_inst
= 0; /* the save instruction */
1489 int extend_bytes
= 0;
1490 int prev_extend_bytes
;
1491 CORE_ADDR end_prologue_addr
= 0;
1493 /* Can be called when there's no process, and hence when there's no
1495 if (this_frame
!= NULL
)
1496 sp
= get_frame_register_signed (this_frame
,
1497 gdbarch_num_regs (gdbarch
)
1502 if (limit_pc
> start_pc
+ 200)
1503 limit_pc
= start_pc
+ 200;
1505 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1507 /* Save the previous instruction. If it's an EXTEND, we'll extract
1508 the immediate offset extension from it in mips16_get_imm. */
1511 /* Fetch and decode the instruction. */
1512 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1514 /* Normally we ignore extend instructions. However, if it is
1515 not followed by a valid prologue instruction, then this
1516 instruction is not part of the prologue either. We must
1517 remember in this case to adjust the end_prologue_addr back
1519 if ((inst
& 0xf800) == 0xf000) /* extend */
1521 extend_bytes
= MIPS_INSN16_SIZE
;
1525 prev_extend_bytes
= extend_bytes
;
1528 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1529 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1531 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1532 if (offset
< 0) /* negative stack adjustment? */
1533 frame_offset
-= offset
;
1535 /* Exit loop if a positive stack adjustment is found, which
1536 usually means that the stack cleanup code in the function
1537 epilogue is reached. */
1540 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1542 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1543 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1544 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1546 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1548 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1549 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1550 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1552 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1554 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1555 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1557 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1559 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1560 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1562 else if (inst
== 0x673d) /* move $s1, $sp */
1567 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1569 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1570 frame_addr
= sp
+ offset
;
1572 frame_adjust
= offset
;
1574 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1576 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1577 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1578 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1580 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1582 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1583 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1584 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1586 else if ((inst
& 0xf81f) == 0xe809
1587 && (inst
& 0x700) != 0x700) /* entry */
1588 entry_inst
= inst
; /* save for later processing */
1589 else if ((inst
& 0xff80) == 0x6480) /* save */
1591 save_inst
= inst
; /* save for later processing */
1592 if (prev_extend_bytes
) /* extend */
1593 save_inst
|= prev_inst
<< 16;
1595 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1596 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1597 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1599 /* This instruction is part of the prologue, but we don't
1600 need to do anything special to handle it. */
1604 /* This instruction is not an instruction typically found
1605 in a prologue, so we must have reached the end of the
1607 if (end_prologue_addr
== 0)
1608 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1612 /* The entry instruction is typically the first instruction in a function,
1613 and it stores registers at offsets relative to the value of the old SP
1614 (before the prologue). But the value of the sp parameter to this
1615 function is the new SP (after the prologue has been executed). So we
1616 can't calculate those offsets until we've seen the entire prologue,
1617 and can calculate what the old SP must have been. */
1618 if (entry_inst
!= 0)
1620 int areg_count
= (entry_inst
>> 8) & 7;
1621 int sreg_count
= (entry_inst
>> 6) & 3;
1623 /* The entry instruction always subtracts 32 from the SP. */
1626 /* Now we can calculate what the SP must have been at the
1627 start of the function prologue. */
1630 /* Check if a0-a3 were saved in the caller's argument save area. */
1631 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1633 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1634 offset
+= mips_abi_regsize (gdbarch
);
1637 /* Check if the ra register was pushed on the stack. */
1639 if (entry_inst
& 0x20)
1641 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1642 offset
-= mips_abi_regsize (gdbarch
);
1645 /* Check if the s0 and s1 registers were pushed on the stack. */
1646 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1648 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1649 offset
-= mips_abi_regsize (gdbarch
);
1653 /* The SAVE instruction is similar to ENTRY, except that defined by the
1654 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1655 size of the frame is specified as an immediate field of instruction
1656 and an extended variation exists which lets additional registers and
1657 frame space to be specified. The instruction always treats registers
1658 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1659 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1661 static int args_table
[16] = {
1662 0, 0, 0, 0, 1, 1, 1, 1,
1663 2, 2, 2, 0, 3, 3, 4, -1,
1665 static int astatic_table
[16] = {
1666 0, 1, 2, 3, 0, 1, 2, 3,
1667 0, 1, 2, 4, 0, 1, 0, -1,
1669 int aregs
= (save_inst
>> 16) & 0xf;
1670 int xsregs
= (save_inst
>> 24) & 0x7;
1671 int args
= args_table
[aregs
];
1672 int astatic
= astatic_table
[aregs
];
1677 warning (_("Invalid number of argument registers encoded in SAVE."));
1682 warning (_("Invalid number of static registers encoded in SAVE."));
1686 /* For standard SAVE the frame size of 0 means 128. */
1687 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1688 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1691 frame_offset
+= frame_size
;
1693 /* Now we can calculate what the SP must have been at the
1694 start of the function prologue. */
1697 /* Check if A0-A3 were saved in the caller's argument save area. */
1698 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1700 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1701 offset
+= mips_abi_regsize (gdbarch
);
1706 /* Check if the RA register was pushed on the stack. */
1707 if (save_inst
& 0x40)
1709 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1710 offset
-= mips_abi_regsize (gdbarch
);
1713 /* Check if the S8 register was pushed on the stack. */
1716 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1717 offset
-= mips_abi_regsize (gdbarch
);
1720 /* Check if S2-S7 were pushed on the stack. */
1721 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1723 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1724 offset
-= mips_abi_regsize (gdbarch
);
1727 /* Check if the S1 register was pushed on the stack. */
1728 if (save_inst
& 0x10)
1730 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1731 offset
-= mips_abi_regsize (gdbarch
);
1733 /* Check if the S0 register was pushed on the stack. */
1734 if (save_inst
& 0x20)
1736 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1737 offset
-= mips_abi_regsize (gdbarch
);
1740 /* Check if A0-A3 were pushed on the stack. */
1741 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1743 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1744 offset
-= mips_abi_regsize (gdbarch
);
1748 if (this_cache
!= NULL
)
1751 (get_frame_register_signed (this_frame
,
1752 gdbarch_num_regs (gdbarch
) + frame_reg
)
1753 + frame_offset
- frame_adjust
);
1754 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1755 be able to get rid of the assignment below, evetually. But it's
1756 still needed for now. */
1757 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1758 + mips_regnum (gdbarch
)->pc
]
1759 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1762 /* If we didn't reach the end of the prologue when scanning the function
1763 instructions, then set end_prologue_addr to the address of the
1764 instruction immediately after the last one we scanned. */
1765 if (end_prologue_addr
== 0)
1766 end_prologue_addr
= cur_pc
;
1768 return end_prologue_addr
;
1771 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1772 Procedures that use the 32-bit instruction set are handled by the
1773 mips_insn32 unwinder. */
1775 static struct mips_frame_cache
*
1776 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1778 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1779 struct mips_frame_cache
*cache
;
1781 if ((*this_cache
) != NULL
)
1782 return (*this_cache
);
1783 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1784 (*this_cache
) = cache
;
1785 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1787 /* Analyze the function prologue. */
1789 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1790 CORE_ADDR start_addr
;
1792 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1793 if (start_addr
== 0)
1794 start_addr
= heuristic_proc_start (gdbarch
, pc
);
1795 /* We can't analyze the prologue if we couldn't find the begining
1797 if (start_addr
== 0)
1800 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
1803 /* gdbarch_sp_regnum contains the value and not the address. */
1804 trad_frame_set_value (cache
->saved_regs
,
1805 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
1808 return (*this_cache
);
1812 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1813 struct frame_id
*this_id
)
1815 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1817 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
1820 static struct value
*
1821 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
1822 void **this_cache
, int regnum
)
1824 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1826 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1830 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
1831 struct frame_info
*this_frame
, void **this_cache
)
1833 CORE_ADDR pc
= get_frame_pc (this_frame
);
1834 if (mips_pc_is_mips16 (pc
))
1839 static const struct frame_unwind mips_insn16_frame_unwind
=
1842 mips_insn16_frame_this_id
,
1843 mips_insn16_frame_prev_register
,
1845 mips_insn16_frame_sniffer
1849 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
1852 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1857 static const struct frame_base mips_insn16_frame_base
=
1859 &mips_insn16_frame_unwind
,
1860 mips_insn16_frame_base_address
,
1861 mips_insn16_frame_base_address
,
1862 mips_insn16_frame_base_address
1865 static const struct frame_base
*
1866 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
1868 CORE_ADDR pc
= get_frame_pc (this_frame
);
1869 if (mips_pc_is_mips16 (pc
))
1870 return &mips_insn16_frame_base
;
1875 /* Mark all the registers as unset in the saved_regs array
1876 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1879 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
1881 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1885 const int num_regs
= gdbarch_num_regs (gdbarch
);
1888 for (i
= 0; i
< num_regs
; i
++)
1890 this_cache
->saved_regs
[i
].addr
= -1;
1895 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1896 the associated FRAME_CACHE if not null.
1897 Return the address of the first instruction past the prologue. */
1900 mips32_scan_prologue (struct gdbarch
*gdbarch
,
1901 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1902 struct frame_info
*this_frame
,
1903 struct mips_frame_cache
*this_cache
)
1906 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1909 int frame_reg
= MIPS_SP_REGNUM
;
1911 CORE_ADDR end_prologue_addr
= 0;
1912 int seen_sp_adjust
= 0;
1913 int load_immediate_bytes
= 0;
1914 int in_delay_slot
= 0;
1915 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
1917 /* Can be called when there's no process, and hence when there's no
1919 if (this_frame
!= NULL
)
1920 sp
= get_frame_register_signed (this_frame
,
1921 gdbarch_num_regs (gdbarch
)
1926 if (limit_pc
> start_pc
+ 200)
1927 limit_pc
= start_pc
+ 200;
1932 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1934 unsigned long inst
, high_word
, low_word
;
1937 /* Fetch the instruction. */
1938 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
1940 /* Save some code by pre-extracting some useful fields. */
1941 high_word
= (inst
>> 16) & 0xffff;
1942 low_word
= inst
& 0xffff;
1943 reg
= high_word
& 0x1f;
1945 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1946 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1947 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1949 if (low_word
& 0x8000) /* negative stack adjustment? */
1950 frame_offset
+= 0x10000 - low_word
;
1952 /* Exit loop if a positive stack adjustment is found, which
1953 usually means that the stack cleanup code in the function
1954 epilogue is reached. */
1958 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1959 && !regsize_is_64_bits
)
1961 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
1963 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1964 && regsize_is_64_bits
)
1966 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1967 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
1969 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1971 /* Old gcc frame, r30 is virtual frame pointer. */
1972 if ((long) low_word
!= frame_offset
)
1973 frame_addr
= sp
+ low_word
;
1974 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1976 unsigned alloca_adjust
;
1979 frame_addr
= get_frame_register_signed
1980 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
1982 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1983 if (alloca_adjust
> 0)
1985 /* FP > SP + frame_size. This may be because of
1986 an alloca or somethings similar. Fix sp to
1987 "pre-alloca" value, and try again. */
1988 sp
+= alloca_adjust
;
1989 /* Need to reset the status of all registers. Otherwise,
1990 we will hit a guard that prevents the new address
1991 for each register to be recomputed during the second
1993 reset_saved_regs (gdbarch
, this_cache
);
1998 /* move $30,$sp. With different versions of gas this will be either
1999 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2000 Accept any one of these. */
2001 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2003 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2004 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2006 unsigned alloca_adjust
;
2009 frame_addr
= get_frame_register_signed
2010 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2012 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2013 if (alloca_adjust
> 0)
2015 /* FP > SP + frame_size. This may be because of
2016 an alloca or somethings similar. Fix sp to
2017 "pre-alloca" value, and try again. */
2019 /* Need to reset the status of all registers. Otherwise,
2020 we will hit a guard that prevents the new address
2021 for each register to be recomputed during the second
2023 reset_saved_regs (gdbarch
, this_cache
);
2028 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2029 && !regsize_is_64_bits
)
2031 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2033 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2034 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2035 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2036 || high_word
== 0x3c1c /* lui $gp,n */
2037 || high_word
== 0x279c /* addiu $gp,$gp,n */
2038 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2039 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2042 /* These instructions are part of the prologue, but we don't
2043 need to do anything special to handle them. */
2045 /* The instructions below load $at or $t0 with an immediate
2046 value in preparation for a stack adjustment via
2047 subu $sp,$sp,[$at,$t0]. These instructions could also
2048 initialize a local variable, so we accept them only before
2049 a stack adjustment instruction was seen. */
2050 else if (!seen_sp_adjust
2051 && (high_word
== 0x3c01 /* lui $at,n */
2052 || high_word
== 0x3c08 /* lui $t0,n */
2053 || high_word
== 0x3421 /* ori $at,$at,n */
2054 || high_word
== 0x3508 /* ori $t0,$t0,n */
2055 || high_word
== 0x3401 /* ori $at,$zero,n */
2056 || high_word
== 0x3408 /* ori $t0,$zero,n */
2059 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2063 /* This instruction is not an instruction typically found
2064 in a prologue, so we must have reached the end of the
2066 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2067 loop now? Why would we need to continue scanning the function
2069 if (end_prologue_addr
== 0)
2070 end_prologue_addr
= cur_pc
;
2072 /* Check for branches and jumps. For now, only jump to
2073 register are caught (i.e. returns). */
2074 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2078 /* If the previous instruction was a jump, we must have reached
2079 the end of the prologue by now. Stop scanning so that we do
2080 not go past the function return. */
2085 if (this_cache
!= NULL
)
2088 (get_frame_register_signed (this_frame
,
2089 gdbarch_num_regs (gdbarch
) + frame_reg
)
2091 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2092 this assignment below, eventually. But it's still needed
2094 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2095 + mips_regnum (gdbarch
)->pc
]
2096 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2100 /* If we didn't reach the end of the prologue when scanning the function
2101 instructions, then set end_prologue_addr to the address of the
2102 instruction immediately after the last one we scanned. */
2103 /* brobecker/2004-10-10: I don't think this would ever happen, but
2104 we may as well be careful and do our best if we have a null
2105 end_prologue_addr. */
2106 if (end_prologue_addr
== 0)
2107 end_prologue_addr
= cur_pc
;
2109 /* In a frameless function, we might have incorrectly
2110 skipped some load immediate instructions. Undo the skipping
2111 if the load immediate was not followed by a stack adjustment. */
2112 if (load_immediate_bytes
&& !seen_sp_adjust
)
2113 end_prologue_addr
-= load_immediate_bytes
;
2115 return end_prologue_addr
;
2118 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2119 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2120 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2123 static struct mips_frame_cache
*
2124 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2126 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2127 struct mips_frame_cache
*cache
;
2129 if ((*this_cache
) != NULL
)
2130 return (*this_cache
);
2132 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2133 (*this_cache
) = cache
;
2134 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2136 /* Analyze the function prologue. */
2138 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2139 CORE_ADDR start_addr
;
2141 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2142 if (start_addr
== 0)
2143 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2144 /* We can't analyze the prologue if we couldn't find the begining
2146 if (start_addr
== 0)
2149 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2152 /* gdbarch_sp_regnum contains the value and not the address. */
2153 trad_frame_set_value (cache
->saved_regs
,
2154 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2157 return (*this_cache
);
2161 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2162 struct frame_id
*this_id
)
2164 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2166 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2169 static struct value
*
2170 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2171 void **this_cache
, int regnum
)
2173 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2175 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2179 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2180 struct frame_info
*this_frame
, void **this_cache
)
2182 CORE_ADDR pc
= get_frame_pc (this_frame
);
2183 if (! mips_pc_is_mips16 (pc
))
2188 static const struct frame_unwind mips_insn32_frame_unwind
=
2191 mips_insn32_frame_this_id
,
2192 mips_insn32_frame_prev_register
,
2194 mips_insn32_frame_sniffer
2198 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2201 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2206 static const struct frame_base mips_insn32_frame_base
=
2208 &mips_insn32_frame_unwind
,
2209 mips_insn32_frame_base_address
,
2210 mips_insn32_frame_base_address
,
2211 mips_insn32_frame_base_address
2214 static const struct frame_base
*
2215 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2217 CORE_ADDR pc
= get_frame_pc (this_frame
);
2218 if (! mips_pc_is_mips16 (pc
))
2219 return &mips_insn32_frame_base
;
2224 static struct trad_frame_cache
*
2225 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2228 CORE_ADDR start_addr
;
2229 CORE_ADDR stack_addr
;
2230 struct trad_frame_cache
*this_trad_cache
;
2231 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2232 int num_regs
= gdbarch_num_regs (gdbarch
);
2234 if ((*this_cache
) != NULL
)
2235 return (*this_cache
);
2236 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2237 (*this_cache
) = this_trad_cache
;
2239 /* The return address is in the link register. */
2240 trad_frame_set_reg_realreg (this_trad_cache
,
2241 gdbarch_pc_regnum (gdbarch
),
2242 num_regs
+ MIPS_RA_REGNUM
);
2244 /* Frame ID, since it's a frameless / stackless function, no stack
2245 space is allocated and SP on entry is the current SP. */
2246 pc
= get_frame_pc (this_frame
);
2247 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2248 stack_addr
= get_frame_register_signed (this_frame
,
2249 num_regs
+ MIPS_SP_REGNUM
);
2250 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2252 /* Assume that the frame's base is the same as the
2254 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2256 return this_trad_cache
;
2260 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2261 struct frame_id
*this_id
)
2263 struct trad_frame_cache
*this_trad_cache
2264 = mips_stub_frame_cache (this_frame
, this_cache
);
2265 trad_frame_get_id (this_trad_cache
, this_id
);
2268 static struct value
*
2269 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2270 void **this_cache
, int regnum
)
2272 struct trad_frame_cache
*this_trad_cache
2273 = mips_stub_frame_cache (this_frame
, this_cache
);
2274 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2278 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2279 struct frame_info
*this_frame
, void **this_cache
)
2282 struct obj_section
*s
;
2283 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2284 struct minimal_symbol
*msym
;
2286 /* Use the stub unwinder for unreadable code. */
2287 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2290 if (in_plt_section (pc
, NULL
))
2293 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2294 s
= find_pc_section (pc
);
2297 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2298 ".MIPS.stubs") == 0)
2301 /* Calling a PIC function from a non-PIC function passes through a
2302 stub. The stub for foo is named ".pic.foo". */
2303 msym
= lookup_minimal_symbol_by_pc (pc
);
2305 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2306 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2312 static const struct frame_unwind mips_stub_frame_unwind
=
2315 mips_stub_frame_this_id
,
2316 mips_stub_frame_prev_register
,
2318 mips_stub_frame_sniffer
2322 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2325 struct trad_frame_cache
*this_trad_cache
2326 = mips_stub_frame_cache (this_frame
, this_cache
);
2327 return trad_frame_get_this_base (this_trad_cache
);
2330 static const struct frame_base mips_stub_frame_base
=
2332 &mips_stub_frame_unwind
,
2333 mips_stub_frame_base_address
,
2334 mips_stub_frame_base_address
,
2335 mips_stub_frame_base_address
2338 static const struct frame_base
*
2339 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2341 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2342 return &mips_stub_frame_base
;
2347 /* mips_addr_bits_remove - remove useless address bits */
2350 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2352 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2353 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2354 /* This hack is a work-around for existing boards using PMON, the
2355 simulator, and any other 64-bit targets that doesn't have true
2356 64-bit addressing. On these targets, the upper 32 bits of
2357 addresses are ignored by the hardware. Thus, the PC or SP are
2358 likely to have been sign extended to all 1s by instruction
2359 sequences that load 32-bit addresses. For example, a typical
2360 piece of code that loads an address is this:
2362 lui $r2, <upper 16 bits>
2363 ori $r2, <lower 16 bits>
2365 But the lui sign-extends the value such that the upper 32 bits
2366 may be all 1s. The workaround is simply to mask off these
2367 bits. In the future, gcc may be changed to support true 64-bit
2368 addressing, and this masking will have to be disabled. */
2369 return addr
&= 0xffffffffUL
;
2374 /* Instructions used during single-stepping of atomic sequences. */
2375 #define LL_OPCODE 0x30
2376 #define LLD_OPCODE 0x34
2377 #define SC_OPCODE 0x38
2378 #define SCD_OPCODE 0x3c
2380 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2381 instruction and ending with a SC/SCD instruction. If such a sequence
2382 is found, attempt to step through it. A breakpoint is placed at the end of
2386 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2387 struct address_space
*aspace
, CORE_ADDR pc
)
2389 CORE_ADDR breaks
[2] = {-1, -1};
2391 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2395 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2396 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2401 insn
= mips_fetch_instruction (gdbarch
, loc
);
2402 /* Assume all atomic sequences start with a ll/lld instruction. */
2403 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2406 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2408 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2411 loc
+= MIPS_INSN32_SIZE
;
2412 insn
= mips_fetch_instruction (gdbarch
, loc
);
2414 /* Assume that there is at most one branch in the atomic
2415 sequence. If a branch is found, put a breakpoint in its
2416 destination address. */
2417 switch (itype_op (insn
))
2419 case 0: /* SPECIAL */
2420 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2421 return 0; /* fallback to the standard single-step code. */
2423 case 1: /* REGIMM */
2424 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2428 return 0; /* fallback to the standard single-step code. */
2435 case 22: /* BLEZL */
2436 case 23: /* BGTTL */
2442 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2447 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2448 if (last_breakpoint
>= 1)
2449 return 0; /* More than one branch found, fallback to the
2450 standard single-step code. */
2451 breaks
[1] = branch_bp
;
2455 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2459 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2460 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2463 loc
+= MIPS_INSN32_SIZE
;
2465 /* Insert a breakpoint right after the end of the atomic sequence. */
2468 /* Check for duplicated breakpoints. Check also for a breakpoint
2469 placed (branch instruction's destination) in the atomic sequence */
2470 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2471 last_breakpoint
= 0;
2473 /* Effectively inserts the breakpoints. */
2474 for (index
= 0; index
<= last_breakpoint
; index
++)
2475 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2480 /* mips_software_single_step() is called just before we want to resume
2481 the inferior, if we want to single-step it but there is no hardware
2482 or kernel single-step support (MIPS on GNU/Linux for example). We find
2483 the target of the coming instruction and breakpoint it. */
2486 mips_software_single_step (struct frame_info
*frame
)
2488 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2489 struct address_space
*aspace
= get_frame_address_space (frame
);
2490 CORE_ADDR pc
, next_pc
;
2492 pc
= get_frame_pc (frame
);
2493 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2496 next_pc
= mips_next_pc (frame
, pc
);
2498 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2502 /* Test whether the PC points to the return instruction at the
2503 end of a function. */
2506 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2508 if (mips_pc_is_mips16 (pc
))
2509 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2510 generates a "jr $ra"; other times it generates code to load
2511 the return address from the stack to an accessible register (such
2512 as $a3), then a "jr" using that register. This second case
2513 is almost impossible to distinguish from an indirect jump
2514 used for switch statements, so we don't even try. */
2515 return mips_fetch_instruction (gdbarch
, pc
) == 0xe820; /* jr $ra */
2517 return mips_fetch_instruction (gdbarch
, pc
) == 0x3e00008; /* jr $ra */
2521 /* This fencepost looks highly suspicious to me. Removing it also
2522 seems suspicious as it could affect remote debugging across serial
2526 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2532 struct inferior
*inf
;
2534 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2536 fence
= start_pc
- heuristic_fence_post
;
2540 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2541 fence
= VM_MIN_ADDRESS
;
2543 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2545 inf
= current_inferior ();
2547 /* search back for previous return */
2548 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2549 if (start_pc
< fence
)
2551 /* It's not clear to me why we reach this point when
2552 stop_soon, but with this test, at least we
2553 don't print out warnings for every child forked (eg, on
2554 decstation). 22apr93 rich@cygnus.com. */
2555 if (inf
->stop_soon
== NO_STOP_QUIETLY
)
2557 static int blurb_printed
= 0;
2559 warning (_("GDB can't find the start of the function at %s."),
2560 paddress (gdbarch
, pc
));
2564 /* This actually happens frequently in embedded
2565 development, when you first connect to a board
2566 and your stack pointer and pc are nowhere in
2567 particular. This message needs to give people
2568 in that situation enough information to
2569 determine that it's no big deal. */
2570 printf_filtered ("\n\
2571 GDB is unable to find the start of the function at %s\n\
2572 and thus can't determine the size of that function's stack frame.\n\
2573 This means that GDB may be unable to access that stack frame, or\n\
2574 the frames below it.\n\
2575 This problem is most likely caused by an invalid program counter or\n\
2577 However, if you think GDB should simply search farther back\n\
2578 from %s for code which looks like the beginning of a\n\
2579 function, you can increase the range of the search using the `set\n\
2580 heuristic-fence-post' command.\n",
2581 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2588 else if (mips_pc_is_mips16 (start_pc
))
2590 unsigned short inst
;
2592 /* On MIPS16, any one of the following is likely to be the
2593 start of a function:
2599 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2600 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2601 if ((inst
& 0xff80) == 0x6480) /* save */
2603 if (start_pc
- instlen
>= fence
)
2605 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2606 if ((inst
& 0xf800) == 0xf000) /* extend */
2607 start_pc
-= instlen
;
2611 else if (((inst
& 0xf81f) == 0xe809
2612 && (inst
& 0x700) != 0x700) /* entry */
2613 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2614 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2615 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2617 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2618 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2623 else if (mips_about_to_return (gdbarch
, start_pc
))
2625 /* Skip return and its delay slot. */
2626 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2633 struct mips_objfile_private
2639 /* According to the current ABI, should the type be passed in a
2640 floating-point register (assuming that there is space)? When there
2641 is no FPU, FP are not even considered as possible candidates for
2642 FP registers and, consequently this returns false - forces FP
2643 arguments into integer registers. */
2646 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2647 struct type
*arg_type
)
2649 return ((typecode
== TYPE_CODE_FLT
2650 || (MIPS_EABI (gdbarch
)
2651 && (typecode
== TYPE_CODE_STRUCT
2652 || typecode
== TYPE_CODE_UNION
)
2653 && TYPE_NFIELDS (arg_type
) == 1
2654 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2656 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2659 /* On o32, argument passing in GPRs depends on the alignment of the type being
2660 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2663 mips_type_needs_double_align (struct type
*type
)
2665 enum type_code typecode
= TYPE_CODE (type
);
2667 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2669 else if (typecode
== TYPE_CODE_STRUCT
)
2671 if (TYPE_NFIELDS (type
) < 1)
2673 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2675 else if (typecode
== TYPE_CODE_UNION
)
2679 n
= TYPE_NFIELDS (type
);
2680 for (i
= 0; i
< n
; i
++)
2681 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2688 /* Adjust the address downward (direction of stack growth) so that it
2689 is correctly aligned for a new stack frame. */
2691 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2693 return align_down (addr
, 16);
2697 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2698 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2699 int nargs
, struct value
**args
, CORE_ADDR sp
,
2700 int struct_return
, CORE_ADDR struct_addr
)
2706 int stack_offset
= 0;
2707 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2708 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2709 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2710 int regsize
= mips_abi_regsize (gdbarch
);
2712 /* For shared libraries, "t9" needs to point at the function
2714 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2716 /* Set the return address register to point to the entry point of
2717 the program, where a breakpoint lies in wait. */
2718 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2720 /* First ensure that the stack and structure return address (if any)
2721 are properly aligned. The stack has to be at least 64-bit
2722 aligned even on 32-bit machines, because doubles must be 64-bit
2723 aligned. For n32 and n64, stack frames need to be 128-bit
2724 aligned, so we round to this widest known alignment. */
2726 sp
= align_down (sp
, 16);
2727 struct_addr
= align_down (struct_addr
, 16);
2729 /* Now make space on the stack for the args. We allocate more
2730 than necessary for EABI, because the first few arguments are
2731 passed in registers, but that's OK. */
2732 for (argnum
= 0; argnum
< nargs
; argnum
++)
2733 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2734 sp
-= align_up (len
, 16);
2737 fprintf_unfiltered (gdb_stdlog
,
2738 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2739 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2741 /* Initialize the integer and float register pointers. */
2742 argreg
= MIPS_A0_REGNUM
;
2743 float_argreg
= mips_fpa0_regnum (gdbarch
);
2745 /* The struct_return pointer occupies the first parameter-passing reg. */
2749 fprintf_unfiltered (gdb_stdlog
,
2750 "mips_eabi_push_dummy_call: struct_return reg=%d %s\n",
2751 argreg
, paddress (gdbarch
, struct_addr
));
2752 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2755 /* Now load as many as possible of the first arguments into
2756 registers, and push the rest onto the stack. Loop thru args
2757 from first to last. */
2758 for (argnum
= 0; argnum
< nargs
; argnum
++)
2760 const gdb_byte
*val
;
2761 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2762 struct value
*arg
= args
[argnum
];
2763 struct type
*arg_type
= check_typedef (value_type (arg
));
2764 int len
= TYPE_LENGTH (arg_type
);
2765 enum type_code typecode
= TYPE_CODE (arg_type
);
2768 fprintf_unfiltered (gdb_stdlog
,
2769 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2770 argnum
+ 1, len
, (int) typecode
);
2772 /* The EABI passes structures that do not fit in a register by
2775 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2777 store_unsigned_integer (valbuf
, regsize
, byte_order
,
2778 value_address (arg
));
2779 typecode
= TYPE_CODE_PTR
;
2783 fprintf_unfiltered (gdb_stdlog
, " push");
2786 val
= value_contents (arg
);
2788 /* 32-bit ABIs always start floating point arguments in an
2789 even-numbered floating point register. Round the FP register
2790 up before the check to see if there are any FP registers
2791 left. Non MIPS_EABI targets also pass the FP in the integer
2792 registers so also round up normal registers. */
2793 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2795 if ((float_argreg
& 1))
2799 /* Floating point arguments passed in registers have to be
2800 treated specially. On 32-bit architectures, doubles
2801 are passed in register pairs; the even register gets
2802 the low word, and the odd register gets the high word.
2803 On non-EABI processors, the first two floating point arguments are
2804 also copied to general registers, because MIPS16 functions
2805 don't use float registers for arguments. This duplication of
2806 arguments in general registers can't hurt non-MIPS16 functions
2807 because those registers are normally skipped. */
2808 /* MIPS_EABI squeezes a struct that contains a single floating
2809 point value into an FP register instead of pushing it onto the
2811 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
2812 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
2814 /* EABI32 will pass doubles in consecutive registers, even on
2815 64-bit cores. At one time, we used to check the size of
2816 `float_argreg' to determine whether or not to pass doubles
2817 in consecutive registers, but this is not sufficient for
2818 making the ABI determination. */
2819 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2821 int low_offset
= gdbarch_byte_order (gdbarch
)
2822 == BFD_ENDIAN_BIG
? 4 : 0;
2823 unsigned long regval
;
2825 /* Write the low word of the double to the even register(s). */
2826 regval
= extract_unsigned_integer (val
+ low_offset
,
2829 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2830 float_argreg
, phex (regval
, 4));
2831 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2833 /* Write the high word of the double to the odd register(s). */
2834 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
2837 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2838 float_argreg
, phex (regval
, 4));
2839 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2843 /* This is a floating point value that fits entirely
2844 in a single register. */
2845 /* On 32 bit ABI's the float_argreg is further adjusted
2846 above to ensure that it is even register aligned. */
2847 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
2849 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2850 float_argreg
, phex (regval
, len
));
2851 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2856 /* Copy the argument to general registers or the stack in
2857 register-sized pieces. Large arguments are split between
2858 registers and stack. */
2859 /* Note: structs whose size is not a multiple of regsize
2860 are treated specially: Irix cc passes
2861 them in registers where gcc sometimes puts them on the
2862 stack. For maximum compatibility, we will put them in
2864 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2866 /* Note: Floating-point values that didn't fit into an FP
2867 register are only written to memory. */
2870 /* Remember if the argument was written to the stack. */
2871 int stack_used_p
= 0;
2872 int partial_len
= (len
< regsize
? len
: regsize
);
2875 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2878 /* Write this portion of the argument to the stack. */
2879 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
2881 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2883 /* Should shorter than int integer values be
2884 promoted to int before being stored? */
2885 int longword_offset
= 0;
2888 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2891 && (typecode
== TYPE_CODE_INT
2892 || typecode
== TYPE_CODE_PTR
2893 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2894 longword_offset
= regsize
- len
;
2895 else if ((typecode
== TYPE_CODE_STRUCT
2896 || typecode
== TYPE_CODE_UNION
)
2897 && TYPE_LENGTH (arg_type
) < regsize
)
2898 longword_offset
= regsize
- len
;
2903 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
2904 paddress (gdbarch
, stack_offset
));
2905 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
2906 paddress (gdbarch
, longword_offset
));
2909 addr
= sp
+ stack_offset
+ longword_offset
;
2914 fprintf_unfiltered (gdb_stdlog
, " @%s ",
2915 paddress (gdbarch
, addr
));
2916 for (i
= 0; i
< partial_len
; i
++)
2918 fprintf_unfiltered (gdb_stdlog
, "%02x",
2922 write_memory (addr
, val
, partial_len
);
2925 /* Note!!! This is NOT an else clause. Odd sized
2926 structs may go thru BOTH paths. Floating point
2927 arguments will not. */
2928 /* Write this portion of the argument to a general
2929 purpose register. */
2930 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
2931 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2934 extract_unsigned_integer (val
, partial_len
, byte_order
);
2937 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2939 phex (regval
, regsize
));
2940 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2947 /* Compute the the offset into the stack at which we
2948 will copy the next parameter.
2950 In the new EABI (and the NABI32), the stack_offset
2951 only needs to be adjusted when it has been used. */
2954 stack_offset
+= align_up (partial_len
, regsize
);
2958 fprintf_unfiltered (gdb_stdlog
, "\n");
2961 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2963 /* Return adjusted stack pointer. */
2967 /* Determine the return value convention being used. */
2969 static enum return_value_convention
2970 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2971 struct type
*type
, struct regcache
*regcache
,
2972 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2974 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2975 int fp_return_type
= 0;
2976 int offset
, regnum
, xfer
;
2978 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2979 return RETURN_VALUE_STRUCT_CONVENTION
;
2981 /* Floating point type? */
2982 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2984 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2986 /* Structs with a single field of float type
2987 are returned in a floating point register. */
2988 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
2989 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2990 && TYPE_NFIELDS (type
) == 1)
2992 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
2994 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3001 /* A floating-point value belongs in the least significant part
3004 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3005 regnum
= mips_regnum (gdbarch
)->fp0
;
3009 /* An integer value goes in V0/V1. */
3011 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3012 regnum
= MIPS_V0_REGNUM
;
3015 offset
< TYPE_LENGTH (type
);
3016 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3018 xfer
= mips_abi_regsize (gdbarch
);
3019 if (offset
+ xfer
> TYPE_LENGTH (type
))
3020 xfer
= TYPE_LENGTH (type
) - offset
;
3021 mips_xfer_register (gdbarch
, regcache
,
3022 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3023 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3027 return RETURN_VALUE_REGISTER_CONVENTION
;
3031 /* N32/N64 ABI stuff. */
3033 /* Search for a naturally aligned double at OFFSET inside a struct
3034 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3038 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3043 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3046 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3049 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3052 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3055 struct type
*field_type
;
3057 /* We're only looking at normal fields. */
3058 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3059 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3062 /* If we have gone past the offset, there is no double to pass. */
3063 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3067 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3069 /* If this field is entirely before the requested offset, go
3070 on to the next one. */
3071 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3074 /* If this is our special aligned double, we can stop. */
3075 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3076 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3079 /* This field starts at or before the requested offset, and
3080 overlaps it. If it is a structure, recurse inwards. */
3081 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3088 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3089 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3090 int nargs
, struct value
**args
, CORE_ADDR sp
,
3091 int struct_return
, CORE_ADDR struct_addr
)
3097 int stack_offset
= 0;
3098 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3099 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3100 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3102 /* For shared libraries, "t9" needs to point at the function
3104 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3106 /* Set the return address register to point to the entry point of
3107 the program, where a breakpoint lies in wait. */
3108 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3110 /* First ensure that the stack and structure return address (if any)
3111 are properly aligned. The stack has to be at least 64-bit
3112 aligned even on 32-bit machines, because doubles must be 64-bit
3113 aligned. For n32 and n64, stack frames need to be 128-bit
3114 aligned, so we round to this widest known alignment. */
3116 sp
= align_down (sp
, 16);
3117 struct_addr
= align_down (struct_addr
, 16);
3119 /* Now make space on the stack for the args. */
3120 for (argnum
= 0; argnum
< nargs
; argnum
++)
3121 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3122 sp
-= align_up (len
, 16);
3125 fprintf_unfiltered (gdb_stdlog
,
3126 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3127 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3129 /* Initialize the integer and float register pointers. */
3130 argreg
= MIPS_A0_REGNUM
;
3131 float_argreg
= mips_fpa0_regnum (gdbarch
);
3133 /* The struct_return pointer occupies the first parameter-passing reg. */
3137 fprintf_unfiltered (gdb_stdlog
,
3138 "mips_n32n64_push_dummy_call: struct_return reg=%d %s\n",
3139 argreg
, paddress (gdbarch
, struct_addr
));
3140 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3143 /* Now load as many as possible of the first arguments into
3144 registers, and push the rest onto the stack. Loop thru args
3145 from first to last. */
3146 for (argnum
= 0; argnum
< nargs
; argnum
++)
3148 const gdb_byte
*val
;
3149 struct value
*arg
= args
[argnum
];
3150 struct type
*arg_type
= check_typedef (value_type (arg
));
3151 int len
= TYPE_LENGTH (arg_type
);
3152 enum type_code typecode
= TYPE_CODE (arg_type
);
3155 fprintf_unfiltered (gdb_stdlog
,
3156 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3157 argnum
+ 1, len
, (int) typecode
);
3159 val
= value_contents (arg
);
3161 /* A 128-bit long double value requires an even-odd pair of
3162 floating-point registers. */
3164 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3165 && (float_argreg
& 1))
3171 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3172 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3174 /* This is a floating point value that fits entirely
3175 in a single register or a pair of registers. */
3176 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3177 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3179 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3180 float_argreg
, phex (regval
, reglen
));
3181 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3184 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3185 argreg
, phex (regval
, reglen
));
3186 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3191 regval
= extract_unsigned_integer (val
+ reglen
,
3192 reglen
, byte_order
);
3194 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3195 float_argreg
, phex (regval
, reglen
));
3196 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3199 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3200 argreg
, phex (regval
, reglen
));
3201 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3208 /* Copy the argument to general registers or the stack in
3209 register-sized pieces. Large arguments are split between
3210 registers and stack. */
3211 /* For N32/N64, structs, unions, or other composite types are
3212 treated as a sequence of doublewords, and are passed in integer
3213 or floating point registers as though they were simple scalar
3214 parameters to the extent that they fit, with any excess on the
3215 stack packed according to the normal memory layout of the
3217 The caller does not reserve space for the register arguments;
3218 the callee is responsible for reserving it if required. */
3219 /* Note: Floating-point values that didn't fit into an FP
3220 register are only written to memory. */
3223 /* Remember if the argument was written to the stack. */
3224 int stack_used_p
= 0;
3225 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3228 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3231 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3232 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3234 /* Write this portion of the argument to the stack. */
3235 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3237 /* Should shorter than int integer values be
3238 promoted to int before being stored? */
3239 int longword_offset
= 0;
3242 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3244 if ((typecode
== TYPE_CODE_INT
3245 || typecode
== TYPE_CODE_PTR
)
3247 longword_offset
= MIPS64_REGSIZE
- len
;
3252 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3253 paddress (gdbarch
, stack_offset
));
3254 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3255 paddress (gdbarch
, longword_offset
));
3258 addr
= sp
+ stack_offset
+ longword_offset
;
3263 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3264 paddress (gdbarch
, addr
));
3265 for (i
= 0; i
< partial_len
; i
++)
3267 fprintf_unfiltered (gdb_stdlog
, "%02x",
3271 write_memory (addr
, val
, partial_len
);
3274 /* Note!!! This is NOT an else clause. Odd sized
3275 structs may go thru BOTH paths. */
3276 /* Write this portion of the argument to a general
3277 purpose register. */
3278 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3282 /* Sign extend pointers, 32-bit integers and signed
3283 16-bit and 8-bit integers; everything else is taken
3286 if ((partial_len
== 4
3287 && (typecode
== TYPE_CODE_PTR
3288 || typecode
== TYPE_CODE_INT
))
3290 && typecode
== TYPE_CODE_INT
3291 && !TYPE_UNSIGNED (arg_type
)))
3292 regval
= extract_signed_integer (val
, partial_len
,
3295 regval
= extract_unsigned_integer (val
, partial_len
,
3298 /* A non-floating-point argument being passed in a
3299 general register. If a struct or union, and if
3300 the remaining length is smaller than the register
3301 size, we have to adjust the register value on
3304 It does not seem to be necessary to do the
3305 same for integral types. */
3307 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3308 && partial_len
< MIPS64_REGSIZE
3309 && (typecode
== TYPE_CODE_STRUCT
3310 || typecode
== TYPE_CODE_UNION
))
3311 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3315 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3317 phex (regval
, MIPS64_REGSIZE
));
3318 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3320 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3321 TYPE_LENGTH (arg_type
) - len
))
3324 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3326 phex (regval
, MIPS64_REGSIZE
));
3327 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3338 /* Compute the the offset into the stack at which we
3339 will copy the next parameter.
3341 In N32 (N64?), the stack_offset only needs to be
3342 adjusted when it has been used. */
3345 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3349 fprintf_unfiltered (gdb_stdlog
, "\n");
3352 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3354 /* Return adjusted stack pointer. */
3358 static enum return_value_convention
3359 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3360 struct type
*type
, struct regcache
*regcache
,
3361 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3363 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3365 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3367 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3368 if needed), as appropriate for the type. Composite results (struct,
3369 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3372 * A struct with only one or two floating point fields is returned in $f0
3373 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3376 * Any other struct or union results of at most 128 bits are returned in
3377 $2 (first 64 bits) and $3 (remainder, if necessary).
3379 * Larger composite results are handled by converting the function to a
3380 procedure with an implicit first parameter, which is a pointer to an area
3381 reserved by the caller to receive the result. [The o32-bit ABI requires
3382 that all composite results be handled by conversion to implicit first
3383 parameters. The MIPS/SGI Fortran implementation has always made a
3384 specific exception to return COMPLEX results in the floating point
3387 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
3388 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3389 return RETURN_VALUE_STRUCT_CONVENTION
;
3390 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3391 && TYPE_LENGTH (type
) == 16
3392 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3394 /* A 128-bit floating-point value fills both $f0 and $f2. The
3395 two registers are used in the same as memory order, so the
3396 eight bytes with the lower memory address are in $f0. */
3398 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3399 mips_xfer_register (gdbarch
, regcache
,
3400 gdbarch_num_regs (gdbarch
)
3401 + mips_regnum (gdbarch
)->fp0
,
3402 8, gdbarch_byte_order (gdbarch
),
3403 readbuf
, writebuf
, 0);
3404 mips_xfer_register (gdbarch
, regcache
,
3405 gdbarch_num_regs (gdbarch
)
3406 + mips_regnum (gdbarch
)->fp0
+ 2,
3407 8, gdbarch_byte_order (gdbarch
),
3408 readbuf
? readbuf
+ 8 : readbuf
,
3409 writebuf
? writebuf
+ 8 : writebuf
, 0);
3410 return RETURN_VALUE_REGISTER_CONVENTION
;
3412 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3413 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3415 /* A single or double floating-point value that fits in FP0. */
3417 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3418 mips_xfer_register (gdbarch
, regcache
,
3419 gdbarch_num_regs (gdbarch
)
3420 + mips_regnum (gdbarch
)->fp0
,
3422 gdbarch_byte_order (gdbarch
),
3423 readbuf
, writebuf
, 0);
3424 return RETURN_VALUE_REGISTER_CONVENTION
;
3426 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3427 && TYPE_NFIELDS (type
) <= 2
3428 && TYPE_NFIELDS (type
) >= 1
3429 && ((TYPE_NFIELDS (type
) == 1
3430 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3432 || (TYPE_NFIELDS (type
) == 2
3433 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3435 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3436 == TYPE_CODE_FLT
))))
3438 /* A struct that contains one or two floats. Each value is part
3439 in the least significant part of their floating point
3440 register (or GPR, for soft float). */
3443 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3444 ? mips_regnum (gdbarch
)->fp0
3446 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3448 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3451 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3453 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3455 /* A 16-byte long double field goes in two consecutive
3457 mips_xfer_register (gdbarch
, regcache
,
3458 gdbarch_num_regs (gdbarch
) + regnum
,
3460 gdbarch_byte_order (gdbarch
),
3461 readbuf
, writebuf
, offset
);
3462 mips_xfer_register (gdbarch
, regcache
,
3463 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3465 gdbarch_byte_order (gdbarch
),
3466 readbuf
, writebuf
, offset
+ 8);
3469 mips_xfer_register (gdbarch
, regcache
,
3470 gdbarch_num_regs (gdbarch
) + regnum
,
3471 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3472 gdbarch_byte_order (gdbarch
),
3473 readbuf
, writebuf
, offset
);
3475 return RETURN_VALUE_REGISTER_CONVENTION
;
3477 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3478 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3480 /* A structure or union. Extract the left justified value,
3481 regardless of the byte order. I.e. DO NOT USE
3485 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3486 offset
< TYPE_LENGTH (type
);
3487 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3489 int xfer
= register_size (gdbarch
, regnum
);
3490 if (offset
+ xfer
> TYPE_LENGTH (type
))
3491 xfer
= TYPE_LENGTH (type
) - offset
;
3493 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3494 offset
, xfer
, regnum
);
3495 mips_xfer_register (gdbarch
, regcache
,
3496 gdbarch_num_regs (gdbarch
) + regnum
,
3497 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3500 return RETURN_VALUE_REGISTER_CONVENTION
;
3504 /* A scalar extract each part but least-significant-byte
3508 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3509 offset
< TYPE_LENGTH (type
);
3510 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3512 int xfer
= register_size (gdbarch
, regnum
);
3513 if (offset
+ xfer
> TYPE_LENGTH (type
))
3514 xfer
= TYPE_LENGTH (type
) - offset
;
3516 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3517 offset
, xfer
, regnum
);
3518 mips_xfer_register (gdbarch
, regcache
,
3519 gdbarch_num_regs (gdbarch
) + regnum
,
3520 xfer
, gdbarch_byte_order (gdbarch
),
3521 readbuf
, writebuf
, offset
);
3523 return RETURN_VALUE_REGISTER_CONVENTION
;
3527 /* O32 ABI stuff. */
3530 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3531 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3532 int nargs
, struct value
**args
, CORE_ADDR sp
,
3533 int struct_return
, CORE_ADDR struct_addr
)
3539 int stack_offset
= 0;
3540 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3541 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3542 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3544 /* For shared libraries, "t9" needs to point at the function
3546 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3548 /* Set the return address register to point to the entry point of
3549 the program, where a breakpoint lies in wait. */
3550 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3552 /* First ensure that the stack and structure return address (if any)
3553 are properly aligned. The stack has to be at least 64-bit
3554 aligned even on 32-bit machines, because doubles must be 64-bit
3555 aligned. For n32 and n64, stack frames need to be 128-bit
3556 aligned, so we round to this widest known alignment. */
3558 sp
= align_down (sp
, 16);
3559 struct_addr
= align_down (struct_addr
, 16);
3561 /* Now make space on the stack for the args. */
3562 for (argnum
= 0; argnum
< nargs
; argnum
++)
3564 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3565 int arglen
= TYPE_LENGTH (arg_type
);
3567 /* Align to double-word if necessary. */
3568 if (mips_type_needs_double_align (arg_type
))
3569 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3570 /* Allocate space on the stack. */
3571 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3573 sp
-= align_up (len
, 16);
3576 fprintf_unfiltered (gdb_stdlog
,
3577 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3578 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3580 /* Initialize the integer and float register pointers. */
3581 argreg
= MIPS_A0_REGNUM
;
3582 float_argreg
= mips_fpa0_regnum (gdbarch
);
3584 /* The struct_return pointer occupies the first parameter-passing reg. */
3588 fprintf_unfiltered (gdb_stdlog
,
3589 "mips_o32_push_dummy_call: struct_return reg=%d %s\n",
3590 argreg
, paddress (gdbarch
, struct_addr
));
3591 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3592 stack_offset
+= MIPS32_REGSIZE
;
3595 /* Now load as many as possible of the first arguments into
3596 registers, and push the rest onto the stack. Loop thru args
3597 from first to last. */
3598 for (argnum
= 0; argnum
< nargs
; argnum
++)
3600 const gdb_byte
*val
;
3601 struct value
*arg
= args
[argnum
];
3602 struct type
*arg_type
= check_typedef (value_type (arg
));
3603 int len
= TYPE_LENGTH (arg_type
);
3604 enum type_code typecode
= TYPE_CODE (arg_type
);
3607 fprintf_unfiltered (gdb_stdlog
,
3608 "mips_o32_push_dummy_call: %d len=%d type=%d",
3609 argnum
+ 1, len
, (int) typecode
);
3611 val
= value_contents (arg
);
3613 /* 32-bit ABIs always start floating point arguments in an
3614 even-numbered floating point register. Round the FP register
3615 up before the check to see if there are any FP registers
3616 left. O32/O64 targets also pass the FP in the integer
3617 registers so also round up normal registers. */
3618 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3620 if ((float_argreg
& 1))
3624 /* Floating point arguments passed in registers have to be
3625 treated specially. On 32-bit architectures, doubles
3626 are passed in register pairs; the even register gets
3627 the low word, and the odd register gets the high word.
3628 On O32/O64, the first two floating point arguments are
3629 also copied to general registers, because MIPS16 functions
3630 don't use float registers for arguments. This duplication of
3631 arguments in general registers can't hurt non-MIPS16 functions
3632 because those registers are normally skipped. */
3634 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3635 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3637 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3639 int low_offset
= gdbarch_byte_order (gdbarch
)
3640 == BFD_ENDIAN_BIG
? 4 : 0;
3641 unsigned long regval
;
3643 /* Write the low word of the double to the even register(s). */
3644 regval
= extract_unsigned_integer (val
+ low_offset
,
3647 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3648 float_argreg
, phex (regval
, 4));
3649 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3651 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3652 argreg
, phex (regval
, 4));
3653 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3655 /* Write the high word of the double to the odd register(s). */
3656 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3659 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3660 float_argreg
, phex (regval
, 4));
3661 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3664 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3665 argreg
, phex (regval
, 4));
3666 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3670 /* This is a floating point value that fits entirely
3671 in a single register. */
3672 /* On 32 bit ABI's the float_argreg is further adjusted
3673 above to ensure that it is even register aligned. */
3674 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
3676 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3677 float_argreg
, phex (regval
, len
));
3678 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3679 /* Although two FP registers are reserved for each
3680 argument, only one corresponding integer register is
3683 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3684 argreg
, phex (regval
, len
));
3685 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3687 /* Reserve space for the FP register. */
3688 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3692 /* Copy the argument to general registers or the stack in
3693 register-sized pieces. Large arguments are split between
3694 registers and stack. */
3695 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3696 are treated specially: Irix cc passes
3697 them in registers where gcc sometimes puts them on the
3698 stack. For maximum compatibility, we will put them in
3700 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3701 && len
% MIPS32_REGSIZE
!= 0);
3702 /* Structures should be aligned to eight bytes (even arg registers)
3703 on MIPS_ABI_O32, if their first member has double precision. */
3704 if (mips_type_needs_double_align (arg_type
))
3709 stack_offset
+= MIPS32_REGSIZE
;
3714 /* Remember if the argument was written to the stack. */
3715 int stack_used_p
= 0;
3716 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3719 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3722 /* Write this portion of the argument to the stack. */
3723 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3724 || odd_sized_struct
)
3726 /* Should shorter than int integer values be
3727 promoted to int before being stored? */
3728 int longword_offset
= 0;
3734 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3735 paddress (gdbarch
, stack_offset
));
3736 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3737 paddress (gdbarch
, longword_offset
));
3740 addr
= sp
+ stack_offset
+ longword_offset
;
3745 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3746 paddress (gdbarch
, addr
));
3747 for (i
= 0; i
< partial_len
; i
++)
3749 fprintf_unfiltered (gdb_stdlog
, "%02x",
3753 write_memory (addr
, val
, partial_len
);
3756 /* Note!!! This is NOT an else clause. Odd sized
3757 structs may go thru BOTH paths. */
3758 /* Write this portion of the argument to a general
3759 purpose register. */
3760 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3762 LONGEST regval
= extract_signed_integer (val
, partial_len
,
3764 /* Value may need to be sign extended, because
3765 mips_isa_regsize() != mips_abi_regsize(). */
3767 /* A non-floating-point argument being passed in a
3768 general register. If a struct or union, and if
3769 the remaining length is smaller than the register
3770 size, we have to adjust the register value on
3773 It does not seem to be necessary to do the
3774 same for integral types.
3776 Also don't do this adjustment on O64 binaries.
3778 cagney/2001-07-23: gdb/179: Also, GCC, when
3779 outputting LE O32 with sizeof (struct) <
3780 mips_abi_regsize(), generates a left shift
3781 as part of storing the argument in a register
3782 (the left shift isn't generated when
3783 sizeof (struct) >= mips_abi_regsize()). Since
3784 it is quite possible that this is GCC
3785 contradicting the LE/O32 ABI, GDB has not been
3786 adjusted to accommodate this. Either someone
3787 needs to demonstrate that the LE/O32 ABI
3788 specifies such a left shift OR this new ABI gets
3789 identified as such and GDB gets tweaked
3792 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3793 && partial_len
< MIPS32_REGSIZE
3794 && (typecode
== TYPE_CODE_STRUCT
3795 || typecode
== TYPE_CODE_UNION
))
3796 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3800 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3802 phex (regval
, MIPS32_REGSIZE
));
3803 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3806 /* Prevent subsequent floating point arguments from
3807 being passed in floating point registers. */
3808 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
3814 /* Compute the the offset into the stack at which we
3815 will copy the next parameter.
3817 In older ABIs, the caller reserved space for
3818 registers that contained arguments. This was loosely
3819 refered to as their "home". Consequently, space is
3820 always allocated. */
3822 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3826 fprintf_unfiltered (gdb_stdlog
, "\n");
3829 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3831 /* Return adjusted stack pointer. */
3835 static enum return_value_convention
3836 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3837 struct type
*type
, struct regcache
*regcache
,
3838 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3840 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3842 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3843 || TYPE_CODE (type
) == TYPE_CODE_UNION
3844 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3845 return RETURN_VALUE_STRUCT_CONVENTION
;
3846 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3847 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3849 /* A single-precision floating-point value. It fits in the
3850 least significant part of FP0. */
3852 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3853 mips_xfer_register (gdbarch
, regcache
,
3854 gdbarch_num_regs (gdbarch
)
3855 + mips_regnum (gdbarch
)->fp0
,
3857 gdbarch_byte_order (gdbarch
),
3858 readbuf
, writebuf
, 0);
3859 return RETURN_VALUE_REGISTER_CONVENTION
;
3861 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3862 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3864 /* A double-precision floating-point value. The most
3865 significant part goes in FP1, and the least significant in
3868 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3869 switch (gdbarch_byte_order (gdbarch
))
3871 case BFD_ENDIAN_LITTLE
:
3872 mips_xfer_register (gdbarch
, regcache
,
3873 gdbarch_num_regs (gdbarch
)
3874 + mips_regnum (gdbarch
)->fp0
+
3875 0, 4, gdbarch_byte_order (gdbarch
),
3876 readbuf
, writebuf
, 0);
3877 mips_xfer_register (gdbarch
, regcache
,
3878 gdbarch_num_regs (gdbarch
)
3879 + mips_regnum (gdbarch
)->fp0
+ 1,
3880 4, gdbarch_byte_order (gdbarch
),
3881 readbuf
, writebuf
, 4);
3883 case BFD_ENDIAN_BIG
:
3884 mips_xfer_register (gdbarch
, regcache
,
3885 gdbarch_num_regs (gdbarch
)
3886 + mips_regnum (gdbarch
)->fp0
+ 1,
3887 4, gdbarch_byte_order (gdbarch
),
3888 readbuf
, writebuf
, 0);
3889 mips_xfer_register (gdbarch
, regcache
,
3890 gdbarch_num_regs (gdbarch
)
3891 + mips_regnum (gdbarch
)->fp0
+ 0,
3892 4, gdbarch_byte_order (gdbarch
),
3893 readbuf
, writebuf
, 4);
3896 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3898 return RETURN_VALUE_REGISTER_CONVENTION
;
3901 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3902 && TYPE_NFIELDS (type
) <= 2
3903 && TYPE_NFIELDS (type
) >= 1
3904 && ((TYPE_NFIELDS (type
) == 1
3905 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3907 || (TYPE_NFIELDS (type
) == 2
3908 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3910 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3912 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3914 /* A struct that contains one or two floats. Each value is part
3915 in the least significant part of their floating point
3917 gdb_byte reg
[MAX_REGISTER_SIZE
];
3920 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3921 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3923 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3926 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3928 mips_xfer_register (gdbarch
, regcache
,
3929 gdbarch_num_regs (gdbarch
) + regnum
,
3930 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3931 gdbarch_byte_order (gdbarch
),
3932 readbuf
, writebuf
, offset
);
3934 return RETURN_VALUE_REGISTER_CONVENTION
;
3938 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3939 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3941 /* A structure or union. Extract the left justified value,
3942 regardless of the byte order. I.e. DO NOT USE
3946 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3947 offset
< TYPE_LENGTH (type
);
3948 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3950 int xfer
= register_size (gdbarch
, regnum
);
3951 if (offset
+ xfer
> TYPE_LENGTH (type
))
3952 xfer
= TYPE_LENGTH (type
) - offset
;
3954 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3955 offset
, xfer
, regnum
);
3956 mips_xfer_register (gdbarch
, regcache
,
3957 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3958 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3960 return RETURN_VALUE_REGISTER_CONVENTION
;
3965 /* A scalar extract each part but least-significant-byte
3966 justified. o32 thinks registers are 4 byte, regardless of
3970 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3971 offset
< TYPE_LENGTH (type
);
3972 offset
+= MIPS32_REGSIZE
, regnum
++)
3974 int xfer
= MIPS32_REGSIZE
;
3975 if (offset
+ xfer
> TYPE_LENGTH (type
))
3976 xfer
= TYPE_LENGTH (type
) - offset
;
3978 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3979 offset
, xfer
, regnum
);
3980 mips_xfer_register (gdbarch
, regcache
,
3981 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3982 gdbarch_byte_order (gdbarch
),
3983 readbuf
, writebuf
, offset
);
3985 return RETURN_VALUE_REGISTER_CONVENTION
;
3989 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3993 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3994 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3996 struct value
**args
, CORE_ADDR sp
,
3997 int struct_return
, CORE_ADDR struct_addr
)
4003 int stack_offset
= 0;
4004 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4005 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4006 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4008 /* For shared libraries, "t9" needs to point at the function
4010 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4012 /* Set the return address register to point to the entry point of
4013 the program, where a breakpoint lies in wait. */
4014 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4016 /* First ensure that the stack and structure return address (if any)
4017 are properly aligned. The stack has to be at least 64-bit
4018 aligned even on 32-bit machines, because doubles must be 64-bit
4019 aligned. For n32 and n64, stack frames need to be 128-bit
4020 aligned, so we round to this widest known alignment. */
4022 sp
= align_down (sp
, 16);
4023 struct_addr
= align_down (struct_addr
, 16);
4025 /* Now make space on the stack for the args. */
4026 for (argnum
= 0; argnum
< nargs
; argnum
++)
4028 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4029 int arglen
= TYPE_LENGTH (arg_type
);
4031 /* Allocate space on the stack. */
4032 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4034 sp
-= align_up (len
, 16);
4037 fprintf_unfiltered (gdb_stdlog
,
4038 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4039 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4041 /* Initialize the integer and float register pointers. */
4042 argreg
= MIPS_A0_REGNUM
;
4043 float_argreg
= mips_fpa0_regnum (gdbarch
);
4045 /* The struct_return pointer occupies the first parameter-passing reg. */
4049 fprintf_unfiltered (gdb_stdlog
,
4050 "mips_o64_push_dummy_call: struct_return reg=%d %s\n",
4051 argreg
, paddress (gdbarch
, struct_addr
));
4052 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4053 stack_offset
+= MIPS64_REGSIZE
;
4056 /* Now load as many as possible of the first arguments into
4057 registers, and push the rest onto the stack. Loop thru args
4058 from first to last. */
4059 for (argnum
= 0; argnum
< nargs
; argnum
++)
4061 const gdb_byte
*val
;
4062 struct value
*arg
= args
[argnum
];
4063 struct type
*arg_type
= check_typedef (value_type (arg
));
4064 int len
= TYPE_LENGTH (arg_type
);
4065 enum type_code typecode
= TYPE_CODE (arg_type
);
4068 fprintf_unfiltered (gdb_stdlog
,
4069 "mips_o64_push_dummy_call: %d len=%d type=%d",
4070 argnum
+ 1, len
, (int) typecode
);
4072 val
= value_contents (arg
);
4074 /* Floating point arguments passed in registers have to be
4075 treated specially. On 32-bit architectures, doubles
4076 are passed in register pairs; the even register gets
4077 the low word, and the odd register gets the high word.
4078 On O32/O64, the first two floating point arguments are
4079 also copied to general registers, because MIPS16 functions
4080 don't use float registers for arguments. This duplication of
4081 arguments in general registers can't hurt non-MIPS16 functions
4082 because those registers are normally skipped. */
4084 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4085 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4087 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4089 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4090 float_argreg
, phex (regval
, len
));
4091 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4093 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4094 argreg
, phex (regval
, len
));
4095 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4097 /* Reserve space for the FP register. */
4098 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4102 /* Copy the argument to general registers or the stack in
4103 register-sized pieces. Large arguments are split between
4104 registers and stack. */
4105 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4106 are treated specially: Irix cc passes them in registers
4107 where gcc sometimes puts them on the stack. For maximum
4108 compatibility, we will put them in both places. */
4109 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4110 && len
% MIPS64_REGSIZE
!= 0);
4113 /* Remember if the argument was written to the stack. */
4114 int stack_used_p
= 0;
4115 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4118 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4121 /* Write this portion of the argument to the stack. */
4122 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4123 || odd_sized_struct
)
4125 /* Should shorter than int integer values be
4126 promoted to int before being stored? */
4127 int longword_offset
= 0;
4130 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4132 if ((typecode
== TYPE_CODE_INT
4133 || typecode
== TYPE_CODE_PTR
4134 || typecode
== TYPE_CODE_FLT
)
4136 longword_offset
= MIPS64_REGSIZE
- len
;
4141 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4142 paddress (gdbarch
, stack_offset
));
4143 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4144 paddress (gdbarch
, longword_offset
));
4147 addr
= sp
+ stack_offset
+ longword_offset
;
4152 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4153 paddress (gdbarch
, addr
));
4154 for (i
= 0; i
< partial_len
; i
++)
4156 fprintf_unfiltered (gdb_stdlog
, "%02x",
4160 write_memory (addr
, val
, partial_len
);
4163 /* Note!!! This is NOT an else clause. Odd sized
4164 structs may go thru BOTH paths. */
4165 /* Write this portion of the argument to a general
4166 purpose register. */
4167 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4169 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4171 /* Value may need to be sign extended, because
4172 mips_isa_regsize() != mips_abi_regsize(). */
4174 /* A non-floating-point argument being passed in a
4175 general register. If a struct or union, and if
4176 the remaining length is smaller than the register
4177 size, we have to adjust the register value on
4180 It does not seem to be necessary to do the
4181 same for integral types. */
4183 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4184 && partial_len
< MIPS64_REGSIZE
4185 && (typecode
== TYPE_CODE_STRUCT
4186 || typecode
== TYPE_CODE_UNION
))
4187 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4191 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4193 phex (regval
, MIPS64_REGSIZE
));
4194 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4197 /* Prevent subsequent floating point arguments from
4198 being passed in floating point registers. */
4199 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4205 /* Compute the the offset into the stack at which we
4206 will copy the next parameter.
4208 In older ABIs, the caller reserved space for
4209 registers that contained arguments. This was loosely
4210 refered to as their "home". Consequently, space is
4211 always allocated. */
4213 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4217 fprintf_unfiltered (gdb_stdlog
, "\n");
4220 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4222 /* Return adjusted stack pointer. */
4226 static enum return_value_convention
4227 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4228 struct type
*type
, struct regcache
*regcache
,
4229 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4231 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4233 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4234 || TYPE_CODE (type
) == TYPE_CODE_UNION
4235 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4236 return RETURN_VALUE_STRUCT_CONVENTION
;
4237 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4239 /* A floating-point value. It fits in the least significant
4242 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4243 mips_xfer_register (gdbarch
, regcache
,
4244 gdbarch_num_regs (gdbarch
)
4245 + mips_regnum (gdbarch
)->fp0
,
4247 gdbarch_byte_order (gdbarch
),
4248 readbuf
, writebuf
, 0);
4249 return RETURN_VALUE_REGISTER_CONVENTION
;
4253 /* A scalar extract each part but least-significant-byte
4257 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4258 offset
< TYPE_LENGTH (type
);
4259 offset
+= MIPS64_REGSIZE
, regnum
++)
4261 int xfer
= MIPS64_REGSIZE
;
4262 if (offset
+ xfer
> TYPE_LENGTH (type
))
4263 xfer
= TYPE_LENGTH (type
) - offset
;
4265 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4266 offset
, xfer
, regnum
);
4267 mips_xfer_register (gdbarch
, regcache
,
4268 gdbarch_num_regs (gdbarch
) + regnum
,
4269 xfer
, gdbarch_byte_order (gdbarch
),
4270 readbuf
, writebuf
, offset
);
4272 return RETURN_VALUE_REGISTER_CONVENTION
;
4276 /* Floating point register management.
4278 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4279 64bit operations, these early MIPS cpus treat fp register pairs
4280 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4281 registers and offer a compatibility mode that emulates the MIPS2 fp
4282 model. When operating in MIPS2 fp compat mode, later cpu's split
4283 double precision floats into two 32-bit chunks and store them in
4284 consecutive fp regs. To display 64-bit floats stored in this
4285 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4286 Throw in user-configurable endianness and you have a real mess.
4288 The way this works is:
4289 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4290 double-precision value will be split across two logical registers.
4291 The lower-numbered logical register will hold the low-order bits,
4292 regardless of the processor's endianness.
4293 - If we are on a 64-bit processor, and we are looking for a
4294 single-precision value, it will be in the low ordered bits
4295 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4296 save slot in memory.
4297 - If we are in 64-bit mode, everything is straightforward.
4299 Note that this code only deals with "live" registers at the top of the
4300 stack. We will attempt to deal with saved registers later, when
4301 the raw/cooked register interface is in place. (We need a general
4302 interface that can deal with dynamic saved register sizes -- fp
4303 regs could be 32 bits wide in one frame and 64 on the frame above
4306 /* Copy a 32-bit single-precision value from the current frame
4307 into rare_buffer. */
4310 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4311 gdb_byte
*rare_buffer
)
4313 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4314 int raw_size
= register_size (gdbarch
, regno
);
4315 gdb_byte
*raw_buffer
= alloca (raw_size
);
4317 if (!frame_register_read (frame
, regno
, raw_buffer
))
4318 error (_("can't read register %d (%s)"),
4319 regno
, gdbarch_register_name (gdbarch
, regno
));
4322 /* We have a 64-bit value for this register. Find the low-order
4326 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4331 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4335 memcpy (rare_buffer
, raw_buffer
, 4);
4339 /* Copy a 64-bit double-precision value from the current frame into
4340 rare_buffer. This may include getting half of it from the next
4344 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4345 gdb_byte
*rare_buffer
)
4347 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4348 int raw_size
= register_size (gdbarch
, regno
);
4350 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4352 /* We have a 64-bit value for this register, and we should use
4354 if (!frame_register_read (frame
, regno
, rare_buffer
))
4355 error (_("can't read register %d (%s)"),
4356 regno
, gdbarch_register_name (gdbarch
, regno
));
4360 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4362 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4363 internal_error (__FILE__
, __LINE__
,
4364 _("mips_read_fp_register_double: bad access to "
4365 "odd-numbered FP register"));
4367 /* mips_read_fp_register_single will find the correct 32 bits from
4369 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4371 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4372 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4376 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4377 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4383 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4385 { /* do values for FP (float) regs */
4386 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4387 gdb_byte
*raw_buffer
;
4388 double doub
, flt1
; /* doubles extracted from raw hex data */
4391 raw_buffer
= alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
));
4393 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4394 fprintf_filtered (file
, "%*s",
4395 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4398 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4400 struct value_print_options opts
;
4402 /* 4-byte registers: Print hex and floating. Also print even
4403 numbered registers as doubles. */
4404 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4405 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
, raw_buffer
, &inv1
);
4407 get_formatted_print_options (&opts
, 'x');
4408 print_scalar_formatted (raw_buffer
,
4409 builtin_type (gdbarch
)->builtin_uint32
,
4412 fprintf_filtered (file
, " flt: ");
4414 fprintf_filtered (file
, " <invalid float> ");
4416 fprintf_filtered (file
, "%-17.9g", flt1
);
4418 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4420 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4421 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4424 fprintf_filtered (file
, " dbl: ");
4426 fprintf_filtered (file
, "<invalid double>");
4428 fprintf_filtered (file
, "%-24.17g", doub
);
4433 struct value_print_options opts
;
4435 /* Eight byte registers: print each one as hex, float and double. */
4436 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4437 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4440 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4441 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4444 get_formatted_print_options (&opts
, 'x');
4445 print_scalar_formatted (raw_buffer
,
4446 builtin_type (gdbarch
)->builtin_uint64
,
4449 fprintf_filtered (file
, " flt: ");
4451 fprintf_filtered (file
, "<invalid float>");
4453 fprintf_filtered (file
, "%-17.9g", flt1
);
4455 fprintf_filtered (file
, " dbl: ");
4457 fprintf_filtered (file
, "<invalid double>");
4459 fprintf_filtered (file
, "%-24.17g", doub
);
4464 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4467 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4468 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4470 struct value_print_options opts
;
4472 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4474 mips_print_fp_register (file
, frame
, regnum
);
4478 /* Get the data in raw format. */
4479 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4481 fprintf_filtered (file
, "%s: [Invalid]",
4482 gdbarch_register_name (gdbarch
, regnum
));
4486 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4488 /* The problem with printing numeric register names (r26, etc.) is that
4489 the user can't use them on input. Probably the best solution is to
4490 fix it so that either the numeric or the funky (a2, etc.) names
4491 are accepted on input. */
4492 if (regnum
< MIPS_NUMREGS
)
4493 fprintf_filtered (file
, "(r%d): ", regnum
);
4495 fprintf_filtered (file
, ": ");
4497 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4499 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4503 get_formatted_print_options (&opts
, 'x');
4504 print_scalar_formatted (raw_buffer
+ offset
,
4505 register_type (gdbarch
, regnum
), &opts
, 0,
4509 /* Replacement for generic do_registers_info.
4510 Print regs in pretty columns. */
4513 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4516 fprintf_filtered (file
, " ");
4517 mips_print_fp_register (file
, frame
, regnum
);
4518 fprintf_filtered (file
, "\n");
4523 /* Print a row's worth of GP (int) registers, with name labels above */
4526 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4529 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4530 /* do values for GP (int) regs */
4531 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4532 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4536 /* For GP registers, we print a separate row of names above the vals */
4537 for (col
= 0, regnum
= start_regnum
;
4538 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4539 + gdbarch_num_pseudo_regs (gdbarch
);
4542 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4543 continue; /* unused register */
4544 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4546 break; /* end the row: reached FP register */
4547 /* Large registers are handled separately. */
4548 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4551 break; /* End the row before this register. */
4553 /* Print this register on a row by itself. */
4554 mips_print_register (file
, frame
, regnum
);
4555 fprintf_filtered (file
, "\n");
4559 fprintf_filtered (file
, " ");
4560 fprintf_filtered (file
,
4561 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4562 gdbarch_register_name (gdbarch
, regnum
));
4569 /* print the R0 to R31 names */
4570 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4571 fprintf_filtered (file
, "\n R%-4d",
4572 start_regnum
% gdbarch_num_regs (gdbarch
));
4574 fprintf_filtered (file
, "\n ");
4576 /* now print the values in hex, 4 or 8 to the row */
4577 for (col
= 0, regnum
= start_regnum
;
4578 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4579 + gdbarch_num_pseudo_regs (gdbarch
);
4582 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4583 continue; /* unused register */
4584 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4586 break; /* end row: reached FP register */
4587 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4588 break; /* End row: large register. */
4590 /* OK: get the data in raw format. */
4591 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4592 error (_("can't read register %d (%s)"),
4593 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4594 /* pad small registers */
4596 byte
< (mips_abi_regsize (gdbarch
)
4597 - register_size (gdbarch
, regnum
)); byte
++)
4598 printf_filtered (" ");
4599 /* Now print the register value in hex, endian order. */
4600 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4602 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4603 byte
< register_size (gdbarch
, regnum
); byte
++)
4604 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4606 for (byte
= register_size (gdbarch
, regnum
) - 1;
4608 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4609 fprintf_filtered (file
, " ");
4612 if (col
> 0) /* ie. if we actually printed anything... */
4613 fprintf_filtered (file
, "\n");
4618 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4621 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4622 struct frame_info
*frame
, int regnum
, int all
)
4624 if (regnum
!= -1) /* do one specified register */
4626 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4627 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4628 error (_("Not a valid register for the current processor type"));
4630 mips_print_register (file
, frame
, regnum
);
4631 fprintf_filtered (file
, "\n");
4634 /* do all (or most) registers */
4636 regnum
= gdbarch_num_regs (gdbarch
);
4637 while (regnum
< gdbarch_num_regs (gdbarch
)
4638 + gdbarch_num_pseudo_regs (gdbarch
))
4640 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4643 if (all
) /* true for "INFO ALL-REGISTERS" command */
4644 regnum
= print_fp_register_row (file
, frame
, regnum
);
4646 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4649 regnum
= print_gp_register_row (file
, frame
, regnum
);
4654 /* Is this a branch with a delay slot? */
4657 is_delayed (unsigned long insn
)
4660 for (i
= 0; i
< NUMOPCODES
; ++i
)
4661 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4662 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4664 return (i
< NUMOPCODES
4665 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4666 | INSN_COND_BRANCH_DELAY
4667 | INSN_COND_BRANCH_LIKELY
)));
4671 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4672 struct frame_info
*frame
)
4674 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4675 CORE_ADDR pc
= get_frame_pc (frame
);
4676 gdb_byte buf
[MIPS_INSN32_SIZE
];
4678 /* There is no branch delay slot on MIPS16. */
4679 if (mips_pc_is_mips16 (pc
))
4682 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
4685 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4686 /* If error reading memory, guess that it is not a delayed
4689 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
4692 /* To skip prologues, I use this predicate. Returns either PC itself
4693 if the code at PC does not look like a function prologue; otherwise
4694 returns an address that (if we're lucky) follows the prologue. If
4695 LENIENT, then we must skip everything which is involved in setting
4696 up the frame (it's OK to skip more, just so long as we don't skip
4697 anything which might clobber the registers which are being saved.
4698 We must skip more in the case where part of the prologue is in the
4699 delay slot of a non-prologue instruction). */
4702 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4705 CORE_ADDR func_addr
;
4707 /* See if we can determine the end of the prologue via the symbol table.
4708 If so, then return either PC, or the PC after the prologue, whichever
4710 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4712 CORE_ADDR post_prologue_pc
4713 = skip_prologue_using_sal (gdbarch
, func_addr
);
4714 if (post_prologue_pc
!= 0)
4715 return max (pc
, post_prologue_pc
);
4718 /* Can't determine prologue from the symbol table, need to examine
4721 /* Find an upper limit on the function prologue using the debug
4722 information. If the debug information could not be used to provide
4723 that bound, then use an arbitrary large number as the upper bound. */
4724 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
4726 limit_pc
= pc
+ 100; /* Magic. */
4728 if (mips_pc_is_mips16 (pc
))
4729 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4731 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4734 /* Check whether the PC is in a function epilogue (32-bit version).
4735 This is a helper function for mips_in_function_epilogue_p. */
4737 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4739 CORE_ADDR func_addr
= 0, func_end
= 0;
4741 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4743 /* The MIPS epilogue is max. 12 bytes long. */
4744 CORE_ADDR addr
= func_end
- 12;
4746 if (addr
< func_addr
+ 4)
4747 addr
= func_addr
+ 4;
4751 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4753 unsigned long high_word
;
4756 inst
= mips_fetch_instruction (gdbarch
, pc
);
4757 high_word
= (inst
>> 16) & 0xffff;
4759 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4760 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4761 && inst
!= 0x03e00008 /* jr $ra */
4762 && inst
!= 0x00000000) /* nop */
4772 /* Check whether the PC is in a function epilogue (16-bit version).
4773 This is a helper function for mips_in_function_epilogue_p. */
4775 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4777 CORE_ADDR func_addr
= 0, func_end
= 0;
4779 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4781 /* The MIPS epilogue is max. 12 bytes long. */
4782 CORE_ADDR addr
= func_end
- 12;
4784 if (addr
< func_addr
+ 4)
4785 addr
= func_addr
+ 4;
4789 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4791 unsigned short inst
;
4793 inst
= mips_fetch_instruction (gdbarch
, pc
);
4795 if ((inst
& 0xf800) == 0xf000) /* extend */
4798 if (inst
!= 0x6300 /* addiu $sp,offset */
4799 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
4800 && inst
!= 0xe820 /* jr $ra */
4801 && inst
!= 0xe8a0 /* jrc $ra */
4802 && inst
!= 0x6500) /* nop */
4812 /* The epilogue is defined here as the area at the end of a function,
4813 after an instruction which destroys the function's stack frame. */
4815 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4817 if (mips_pc_is_mips16 (pc
))
4818 return mips16_in_function_epilogue_p (gdbarch
, pc
);
4820 return mips32_in_function_epilogue_p (gdbarch
, pc
);
4823 /* Root of all "set mips "/"show mips " commands. This will eventually be
4824 used for all MIPS-specific commands. */
4827 show_mips_command (char *args
, int from_tty
)
4829 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4833 set_mips_command (char *args
, int from_tty
)
4836 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4837 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4840 /* Commands to show/set the MIPS FPU type. */
4843 show_mipsfpu_command (char *args
, int from_tty
)
4847 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
4850 ("The MIPS floating-point coprocessor is unknown "
4851 "because the current architecture is not MIPS.\n");
4855 switch (MIPS_FPU_TYPE (target_gdbarch
))
4857 case MIPS_FPU_SINGLE
:
4858 fpu
= "single-precision";
4860 case MIPS_FPU_DOUBLE
:
4861 fpu
= "double-precision";
4864 fpu
= "absent (none)";
4867 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4869 if (mips_fpu_type_auto
)
4871 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4875 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4880 set_mipsfpu_command (char *args
, int from_tty
)
4883 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4884 show_mipsfpu_command (args
, from_tty
);
4888 set_mipsfpu_single_command (char *args
, int from_tty
)
4890 struct gdbarch_info info
;
4891 gdbarch_info_init (&info
);
4892 mips_fpu_type
= MIPS_FPU_SINGLE
;
4893 mips_fpu_type_auto
= 0;
4894 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4895 instead of relying on globals. Doing that would let generic code
4896 handle the search for this specific architecture. */
4897 if (!gdbarch_update_p (info
))
4898 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4902 set_mipsfpu_double_command (char *args
, int from_tty
)
4904 struct gdbarch_info info
;
4905 gdbarch_info_init (&info
);
4906 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4907 mips_fpu_type_auto
= 0;
4908 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4909 instead of relying on globals. Doing that would let generic code
4910 handle the search for this specific architecture. */
4911 if (!gdbarch_update_p (info
))
4912 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4916 set_mipsfpu_none_command (char *args
, int from_tty
)
4918 struct gdbarch_info info
;
4919 gdbarch_info_init (&info
);
4920 mips_fpu_type
= MIPS_FPU_NONE
;
4921 mips_fpu_type_auto
= 0;
4922 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4923 instead of relying on globals. Doing that would let generic code
4924 handle the search for this specific architecture. */
4925 if (!gdbarch_update_p (info
))
4926 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4930 set_mipsfpu_auto_command (char *args
, int from_tty
)
4932 mips_fpu_type_auto
= 1;
4935 /* Attempt to identify the particular processor model by reading the
4936 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4937 the relevant processor still exists (it dates back to '94) and
4938 secondly this is not the way to do this. The processor type should
4939 be set by forcing an architecture change. */
4942 deprecated_mips_set_processor_regs_hack (void)
4944 struct regcache
*regcache
= get_current_regcache ();
4945 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
4946 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4949 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
4950 if ((prid
& ~0xf) == 0x700)
4951 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4954 /* Just like reinit_frame_cache, but with the right arguments to be
4955 callable as an sfunc. */
4958 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4959 struct cmd_list_element
*c
)
4961 reinit_frame_cache ();
4965 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4967 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4968 disassembler needs to be able to locally determine the ISA, and
4969 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4971 if (mips_pc_is_mips16 (memaddr
))
4972 info
->mach
= bfd_mach_mips16
;
4974 /* Round down the instruction address to the appropriate boundary. */
4975 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4977 /* Set the disassembler options. */
4978 if (!info
->disassembler_options
)
4979 /* This string is not recognized explicitly by the disassembler,
4980 but it tells the disassembler to not try to guess the ABI from
4981 the bfd elf headers, such that, if the user overrides the ABI
4982 of a program linked as NewABI, the disassembly will follow the
4983 register naming conventions specified by the user. */
4984 info
->disassembler_options
= "gpr-names=32";
4986 /* Call the appropriate disassembler based on the target endian-ness. */
4987 if (info
->endian
== BFD_ENDIAN_BIG
)
4988 return print_insn_big_mips (memaddr
, info
);
4990 return print_insn_little_mips (memaddr
, info
);
4994 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
4996 /* Set up the disassembler info, so that we get the right
4997 register names from libopcodes. */
4998 info
->disassembler_options
= "gpr-names=n32";
4999 info
->flavour
= bfd_target_elf_flavour
;
5001 return gdb_print_insn_mips (memaddr
, info
);
5005 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5007 /* Set up the disassembler info, so that we get the right
5008 register names from libopcodes. */
5009 info
->disassembler_options
= "gpr-names=64";
5010 info
->flavour
= bfd_target_elf_flavour
;
5012 return gdb_print_insn_mips (memaddr
, info
);
5015 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
5016 counter value to determine whether a 16- or 32-bit breakpoint should be used.
5017 It returns a pointer to a string of bytes that encode a breakpoint
5018 instruction, stores the length of the string to *lenptr, and adjusts pc (if
5019 necessary) to point to the actual memory location where the breakpoint
5020 should be inserted. */
5022 static const gdb_byte
*
5023 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
5025 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5027 if (mips_pc_is_mips16 (*pcptr
))
5029 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5030 *pcptr
= unmake_mips16_addr (*pcptr
);
5031 *lenptr
= sizeof (mips16_big_breakpoint
);
5032 return mips16_big_breakpoint
;
5036 /* The IDT board uses an unusual breakpoint value, and
5037 sometimes gets confused when it sees the usual MIPS
5038 breakpoint instruction. */
5039 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5040 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5041 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5043 *lenptr
= sizeof (big_breakpoint
);
5045 if (strcmp (target_shortname
, "mips") == 0)
5046 return idt_big_breakpoint
;
5047 else if (strcmp (target_shortname
, "ddb") == 0
5048 || strcmp (target_shortname
, "pmon") == 0
5049 || strcmp (target_shortname
, "lsi") == 0)
5050 return pmon_big_breakpoint
;
5052 return big_breakpoint
;
5057 if (mips_pc_is_mips16 (*pcptr
))
5059 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5060 *pcptr
= unmake_mips16_addr (*pcptr
);
5061 *lenptr
= sizeof (mips16_little_breakpoint
);
5062 return mips16_little_breakpoint
;
5066 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5067 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5068 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5070 *lenptr
= sizeof (little_breakpoint
);
5072 if (strcmp (target_shortname
, "mips") == 0)
5073 return idt_little_breakpoint
;
5074 else if (strcmp (target_shortname
, "ddb") == 0
5075 || strcmp (target_shortname
, "pmon") == 0
5076 || strcmp (target_shortname
, "lsi") == 0)
5077 return pmon_little_breakpoint
;
5079 return little_breakpoint
;
5084 /* If PC is in a mips16 call or return stub, return the address of the target
5085 PC, which is either the callee or the caller. There are several
5086 cases which must be handled:
5088 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5089 target PC is in $31 ($ra).
5090 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5091 and the target PC is in $2.
5092 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5093 before the jal instruction, this is effectively a call stub
5094 and the the target PC is in $2. Otherwise this is effectively
5095 a return stub and the target PC is in $18.
5097 See the source code for the stubs in gcc/config/mips/mips16.S for
5101 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5103 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5105 CORE_ADDR start_addr
;
5107 /* Find the starting address and name of the function containing the PC. */
5108 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5111 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5112 target PC is in $31 ($ra). */
5113 if (strcmp (name
, "__mips16_ret_sf") == 0
5114 || strcmp (name
, "__mips16_ret_df") == 0)
5115 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5117 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5119 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5120 and the target PC is in $2. */
5121 if (name
[19] >= '0' && name
[19] <= '9')
5122 return get_frame_register_signed (frame
, 2);
5124 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5125 before the jal instruction, this is effectively a call stub
5126 and the the target PC is in $2. Otherwise this is effectively
5127 a return stub and the target PC is in $18. */
5128 else if (name
[19] == 's' || name
[19] == 'd')
5130 if (pc
== start_addr
)
5132 /* Check if the target of the stub is a compiler-generated
5133 stub. Such a stub for a function bar might have a name
5134 like __fn_stub_bar, and might look like this:
5139 la $1,bar (becomes a lui/addiu pair)
5141 So scan down to the lui/addi and extract the target
5142 address from those two instructions. */
5144 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5148 /* See if the name of the target function is __fn_stub_*. */
5149 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5152 if (strncmp (name
, "__fn_stub_", 10) != 0
5153 && strcmp (name
, "etext") != 0
5154 && strcmp (name
, "_etext") != 0)
5157 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5158 The limit on the search is arbitrarily set to 20
5159 instructions. FIXME. */
5160 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5162 inst
= mips_fetch_instruction (gdbarch
, target_pc
);
5163 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5164 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5165 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5166 return pc
| (inst
& 0xffff); /* low word */
5169 /* Couldn't find the lui/addui pair, so return stub address. */
5173 /* This is the 'return' part of a call stub. The return
5174 address is in $r18. */
5175 return get_frame_register_signed (frame
, 18);
5178 return 0; /* not a stub */
5181 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5182 PC of the stub target. The stub just loads $t9 and jumps to it,
5183 so that $t9 has the correct value at function entry. */
5186 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5188 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5189 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5190 struct minimal_symbol
*msym
;
5192 gdb_byte stub_code
[16];
5193 int32_t stub_words
[4];
5195 /* The stub for foo is named ".pic.foo", and is either two
5196 instructions inserted before foo or a three instruction sequence
5197 which jumps to foo. */
5198 msym
= lookup_minimal_symbol_by_pc (pc
);
5200 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5201 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5202 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5205 /* A two-instruction header. */
5206 if (MSYMBOL_SIZE (msym
) == 8)
5209 /* A three-instruction (plus delay slot) trampoline. */
5210 if (MSYMBOL_SIZE (msym
) == 16)
5212 if (target_read_memory (pc
, stub_code
, 16) != 0)
5214 for (i
= 0; i
< 4; i
++)
5215 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
5218 /* A stub contains these instructions:
5221 addiu t9, t9, %lo(target)
5224 This works even for N64, since stubs are only generated with
5226 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5227 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5228 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5229 && stub_words
[3] == 0x00000000)
5230 return (((stub_words
[0] & 0x0000ffff) << 16)
5231 + (stub_words
[2] & 0x0000ffff));
5234 /* Not a recognized stub. */
5239 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5241 CORE_ADDR target_pc
;
5243 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5247 target_pc
= find_solib_trampoline_target (frame
, pc
);
5251 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5258 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5259 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5262 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5265 if (num
>= 0 && num
< 32)
5267 else if (num
>= 38 && num
< 70)
5268 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5270 regnum
= mips_regnum (gdbarch
)->hi
;
5272 regnum
= mips_regnum (gdbarch
)->lo
;
5274 /* This will hopefully (eventually) provoke a warning. Should
5275 we be calling complaint() here? */
5276 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5277 return gdbarch_num_regs (gdbarch
) + regnum
;
5281 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5282 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5285 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5288 if (num
>= 0 && num
< 32)
5290 else if (num
>= 32 && num
< 64)
5291 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5293 regnum
= mips_regnum (gdbarch
)->hi
;
5295 regnum
= mips_regnum (gdbarch
)->lo
;
5297 /* This will hopefully (eventually) provoke a warning. Should we
5298 be calling complaint() here? */
5299 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5300 return gdbarch_num_regs (gdbarch
) + regnum
;
5304 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5306 /* Only makes sense to supply raw registers. */
5307 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5308 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5309 decide if it is valid. Should instead define a standard sim/gdb
5310 register numbering scheme. */
5311 if (gdbarch_register_name (gdbarch
,
5312 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5313 && gdbarch_register_name (gdbarch
,
5314 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
5317 return LEGACY_SIM_REGNO_IGNORE
;
5321 /* Convert an integer into an address. Extracting the value signed
5322 guarantees a correctly sign extended address. */
5325 mips_integer_to_address (struct gdbarch
*gdbarch
,
5326 struct type
*type
, const gdb_byte
*buf
)
5328 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5329 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
5332 /* Dummy virtual frame pointer method. This is no more or less accurate
5333 than most other architectures; we just need to be explicit about it,
5334 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5335 an assertion failure. */
5338 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5339 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5341 *reg
= MIPS_SP_REGNUM
;
5346 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5348 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5349 const char *name
= bfd_get_section_name (abfd
, sect
);
5351 if (*abip
!= MIPS_ABI_UNKNOWN
)
5354 if (strncmp (name
, ".mdebug.", 8) != 0)
5357 if (strcmp (name
, ".mdebug.abi32") == 0)
5358 *abip
= MIPS_ABI_O32
;
5359 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5360 *abip
= MIPS_ABI_N32
;
5361 else if (strcmp (name
, ".mdebug.abi64") == 0)
5362 *abip
= MIPS_ABI_N64
;
5363 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5364 *abip
= MIPS_ABI_O64
;
5365 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5366 *abip
= MIPS_ABI_EABI32
;
5367 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5368 *abip
= MIPS_ABI_EABI64
;
5370 warning (_("unsupported ABI %s."), name
+ 8);
5374 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5376 int *lbp
= (int *) obj
;
5377 const char *name
= bfd_get_section_name (abfd
, sect
);
5379 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5381 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5383 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5384 warning (_("unrecognized .gcc_compiled_longXX"));
5387 static enum mips_abi
5388 global_mips_abi (void)
5392 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5393 if (mips_abi_strings
[i
] == mips_abi_string
)
5394 return (enum mips_abi
) i
;
5396 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5400 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5402 /* If the size matches the set of 32-bit or 64-bit integer registers,
5403 assume that's what we've got. */
5404 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5405 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5407 /* If the size matches the full set of registers GDB traditionally
5408 knows about, including floating point, for either 32-bit or
5409 64-bit, assume that's what we've got. */
5410 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5411 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5413 /* Otherwise we don't have a useful guess. */
5416 static struct value
*
5417 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5419 const int *reg_p
= baton
;
5420 return value_of_register (*reg_p
, frame
);
5423 static struct gdbarch
*
5424 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5426 struct gdbarch
*gdbarch
;
5427 struct gdbarch_tdep
*tdep
;
5429 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5431 enum mips_fpu_type fpu_type
;
5432 struct tdesc_arch_data
*tdesc_data
= NULL
;
5433 int elf_fpu_type
= 0;
5435 /* Check any target description for validity. */
5436 if (tdesc_has_registers (info
.target_desc
))
5438 static const char *const mips_gprs
[] = {
5439 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5440 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5441 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5442 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5444 static const char *const mips_fprs
[] = {
5445 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5446 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5447 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5448 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5451 const struct tdesc_feature
*feature
;
5454 feature
= tdesc_find_feature (info
.target_desc
,
5455 "org.gnu.gdb.mips.cpu");
5456 if (feature
== NULL
)
5459 tdesc_data
= tdesc_data_alloc ();
5462 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5463 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5467 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5468 MIPS_EMBED_LO_REGNUM
, "lo");
5469 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5470 MIPS_EMBED_HI_REGNUM
, "hi");
5471 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5472 MIPS_EMBED_PC_REGNUM
, "pc");
5476 tdesc_data_cleanup (tdesc_data
);
5480 feature
= tdesc_find_feature (info
.target_desc
,
5481 "org.gnu.gdb.mips.cp0");
5482 if (feature
== NULL
)
5484 tdesc_data_cleanup (tdesc_data
);
5489 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5490 MIPS_EMBED_BADVADDR_REGNUM
,
5492 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5493 MIPS_PS_REGNUM
, "status");
5494 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5495 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5499 tdesc_data_cleanup (tdesc_data
);
5503 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5504 backend is not prepared for that, though. */
5505 feature
= tdesc_find_feature (info
.target_desc
,
5506 "org.gnu.gdb.mips.fpu");
5507 if (feature
== NULL
)
5509 tdesc_data_cleanup (tdesc_data
);
5514 for (i
= 0; i
< 32; i
++)
5515 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5516 i
+ MIPS_EMBED_FP0_REGNUM
,
5519 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5520 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5521 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5522 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5526 tdesc_data_cleanup (tdesc_data
);
5530 /* It would be nice to detect an attempt to use a 64-bit ABI
5531 when only 32-bit registers are provided. */
5534 /* First of all, extract the elf_flags, if available. */
5535 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5536 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5537 else if (arches
!= NULL
)
5538 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5542 fprintf_unfiltered (gdb_stdlog
,
5543 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5545 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5546 switch ((elf_flags
& EF_MIPS_ABI
))
5548 case E_MIPS_ABI_O32
:
5549 found_abi
= MIPS_ABI_O32
;
5551 case E_MIPS_ABI_O64
:
5552 found_abi
= MIPS_ABI_O64
;
5554 case E_MIPS_ABI_EABI32
:
5555 found_abi
= MIPS_ABI_EABI32
;
5557 case E_MIPS_ABI_EABI64
:
5558 found_abi
= MIPS_ABI_EABI64
;
5561 if ((elf_flags
& EF_MIPS_ABI2
))
5562 found_abi
= MIPS_ABI_N32
;
5564 found_abi
= MIPS_ABI_UNKNOWN
;
5568 /* GCC creates a pseudo-section whose name describes the ABI. */
5569 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5570 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5572 /* If we have no useful BFD information, use the ABI from the last
5573 MIPS architecture (if there is one). */
5574 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5575 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5577 /* Try the architecture for any hint of the correct ABI. */
5578 if (found_abi
== MIPS_ABI_UNKNOWN
5579 && info
.bfd_arch_info
!= NULL
5580 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5582 switch (info
.bfd_arch_info
->mach
)
5584 case bfd_mach_mips3900
:
5585 found_abi
= MIPS_ABI_EABI32
;
5587 case bfd_mach_mips4100
:
5588 case bfd_mach_mips5000
:
5589 found_abi
= MIPS_ABI_EABI64
;
5591 case bfd_mach_mips8000
:
5592 case bfd_mach_mips10000
:
5593 /* On Irix, ELF64 executables use the N64 ABI. The
5594 pseudo-sections which describe the ABI aren't present
5595 on IRIX. (Even for executables created by gcc.) */
5596 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5597 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5598 found_abi
= MIPS_ABI_N64
;
5600 found_abi
= MIPS_ABI_N32
;
5605 /* Default 64-bit objects to N64 instead of O32. */
5606 if (found_abi
== MIPS_ABI_UNKNOWN
5607 && info
.abfd
!= NULL
5608 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5609 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5610 found_abi
= MIPS_ABI_N64
;
5613 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5616 /* What has the user specified from the command line? */
5617 wanted_abi
= global_mips_abi ();
5619 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5622 /* Now that we have found what the ABI for this binary would be,
5623 check whether the user is overriding it. */
5624 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5625 mips_abi
= wanted_abi
;
5626 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5627 mips_abi
= found_abi
;
5629 mips_abi
= MIPS_ABI_O32
;
5631 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5634 /* Also used when doing an architecture lookup. */
5636 fprintf_unfiltered (gdb_stdlog
,
5637 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5638 mips64_transfers_32bit_regs_p
);
5640 /* Determine the MIPS FPU type. */
5643 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5644 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5645 Tag_GNU_MIPS_ABI_FP
);
5646 #endif /* HAVE_ELF */
5648 if (!mips_fpu_type_auto
)
5649 fpu_type
= mips_fpu_type
;
5650 else if (elf_fpu_type
!= 0)
5652 switch (elf_fpu_type
)
5655 fpu_type
= MIPS_FPU_DOUBLE
;
5658 fpu_type
= MIPS_FPU_SINGLE
;
5662 /* Soft float or unknown. */
5663 fpu_type
= MIPS_FPU_NONE
;
5667 else if (info
.bfd_arch_info
!= NULL
5668 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5669 switch (info
.bfd_arch_info
->mach
)
5671 case bfd_mach_mips3900
:
5672 case bfd_mach_mips4100
:
5673 case bfd_mach_mips4111
:
5674 case bfd_mach_mips4120
:
5675 fpu_type
= MIPS_FPU_NONE
;
5677 case bfd_mach_mips4650
:
5678 fpu_type
= MIPS_FPU_SINGLE
;
5681 fpu_type
= MIPS_FPU_DOUBLE
;
5684 else if (arches
!= NULL
)
5685 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5687 fpu_type
= MIPS_FPU_DOUBLE
;
5689 fprintf_unfiltered (gdb_stdlog
,
5690 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5692 /* Check for blatant incompatibilities. */
5694 /* If we have only 32-bit registers, then we can't debug a 64-bit
5696 if (info
.target_desc
5697 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5698 && mips_abi
!= MIPS_ABI_EABI32
5699 && mips_abi
!= MIPS_ABI_O32
)
5701 if (tdesc_data
!= NULL
)
5702 tdesc_data_cleanup (tdesc_data
);
5706 /* try to find a pre-existing architecture */
5707 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5709 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5711 /* MIPS needs to be pedantic about which ABI the object is
5713 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5715 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5717 /* Need to be pedantic about which register virtual size is
5719 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5720 != mips64_transfers_32bit_regs_p
)
5722 /* Be pedantic about which FPU is selected. */
5723 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5726 if (tdesc_data
!= NULL
)
5727 tdesc_data_cleanup (tdesc_data
);
5728 return arches
->gdbarch
;
5731 /* Need a new architecture. Fill in a target specific vector. */
5732 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5733 gdbarch
= gdbarch_alloc (&info
, tdep
);
5734 tdep
->elf_flags
= elf_flags
;
5735 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5736 tdep
->found_abi
= found_abi
;
5737 tdep
->mips_abi
= mips_abi
;
5738 tdep
->mips_fpu_type
= fpu_type
;
5739 tdep
->register_size_valid_p
= 0;
5740 tdep
->register_size
= 0;
5742 if (info
.target_desc
)
5744 /* Some useful properties can be inferred from the target. */
5745 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5747 tdep
->register_size_valid_p
= 1;
5748 tdep
->register_size
= 4;
5750 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5752 tdep
->register_size_valid_p
= 1;
5753 tdep
->register_size
= 8;
5757 /* Initially set everything according to the default ABI/ISA. */
5758 set_gdbarch_short_bit (gdbarch
, 16);
5759 set_gdbarch_int_bit (gdbarch
, 32);
5760 set_gdbarch_float_bit (gdbarch
, 32);
5761 set_gdbarch_double_bit (gdbarch
, 64);
5762 set_gdbarch_long_double_bit (gdbarch
, 64);
5763 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5764 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5765 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5767 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5768 mips_elf_make_msymbol_special
);
5770 /* Fill in the OS dependant register numbers and names. */
5772 const char **reg_names
;
5773 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5774 struct mips_regnum
);
5775 if (tdesc_has_registers (info
.target_desc
))
5777 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5778 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5779 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5780 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5781 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5782 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5783 regnum
->fp_control_status
= 70;
5784 regnum
->fp_implementation_revision
= 71;
5785 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5788 else if (info
.osabi
== GDB_OSABI_IRIX
)
5793 regnum
->badvaddr
= 66;
5796 regnum
->fp_control_status
= 69;
5797 regnum
->fp_implementation_revision
= 70;
5799 reg_names
= mips_irix_reg_names
;
5803 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5804 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5805 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5806 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5807 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5808 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5809 regnum
->fp_control_status
= 70;
5810 regnum
->fp_implementation_revision
= 71;
5812 if (info
.bfd_arch_info
!= NULL
5813 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5814 reg_names
= mips_tx39_reg_names
;
5816 reg_names
= mips_generic_reg_names
;
5818 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5819 replaced by gdbarch_read_pc? */
5820 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5821 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5822 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5823 set_gdbarch_num_regs (gdbarch
, num_regs
);
5824 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5825 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5826 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
5827 tdep
->mips_processor_reg_names
= reg_names
;
5828 tdep
->regnum
= regnum
;
5834 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5835 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5836 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5837 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5838 tdep
->default_mask_address_p
= 0;
5839 set_gdbarch_long_bit (gdbarch
, 32);
5840 set_gdbarch_ptr_bit (gdbarch
, 32);
5841 set_gdbarch_long_long_bit (gdbarch
, 64);
5844 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5845 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5846 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5847 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5848 tdep
->default_mask_address_p
= 0;
5849 set_gdbarch_long_bit (gdbarch
, 32);
5850 set_gdbarch_ptr_bit (gdbarch
, 32);
5851 set_gdbarch_long_long_bit (gdbarch
, 64);
5853 case MIPS_ABI_EABI32
:
5854 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5855 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5856 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5857 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5858 tdep
->default_mask_address_p
= 0;
5859 set_gdbarch_long_bit (gdbarch
, 32);
5860 set_gdbarch_ptr_bit (gdbarch
, 32);
5861 set_gdbarch_long_long_bit (gdbarch
, 64);
5863 case MIPS_ABI_EABI64
:
5864 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5865 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5866 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5867 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5868 tdep
->default_mask_address_p
= 0;
5869 set_gdbarch_long_bit (gdbarch
, 64);
5870 set_gdbarch_ptr_bit (gdbarch
, 64);
5871 set_gdbarch_long_long_bit (gdbarch
, 64);
5874 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5875 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5876 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5877 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5878 tdep
->default_mask_address_p
= 0;
5879 set_gdbarch_long_bit (gdbarch
, 32);
5880 set_gdbarch_ptr_bit (gdbarch
, 32);
5881 set_gdbarch_long_long_bit (gdbarch
, 64);
5882 set_gdbarch_long_double_bit (gdbarch
, 128);
5883 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5886 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5887 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5888 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5889 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5890 tdep
->default_mask_address_p
= 0;
5891 set_gdbarch_long_bit (gdbarch
, 64);
5892 set_gdbarch_ptr_bit (gdbarch
, 64);
5893 set_gdbarch_long_long_bit (gdbarch
, 64);
5894 set_gdbarch_long_double_bit (gdbarch
, 128);
5895 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5898 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5901 /* GCC creates a pseudo-section whose name specifies the size of
5902 longs, since -mlong32 or -mlong64 may be used independent of
5903 other options. How those options affect pointer sizes is ABI and
5904 architecture dependent, so use them to override the default sizes
5905 set by the ABI. This table shows the relationship between ABI,
5906 -mlongXX, and size of pointers:
5908 ABI -mlongXX ptr bits
5909 --- -------- --------
5923 Note that for o32 and eabi32, pointers are always 32 bits
5924 regardless of any -mlongXX option. For all others, pointers and
5925 longs are the same, as set by -mlongXX or set by defaults.
5928 if (info
.abfd
!= NULL
)
5932 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5935 set_gdbarch_long_bit (gdbarch
, long_bit
);
5939 case MIPS_ABI_EABI32
:
5944 case MIPS_ABI_EABI64
:
5945 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5948 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5953 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5954 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5957 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5958 flag in object files because to do so would make it impossible to
5959 link with libraries compiled without "-gp32". This is
5960 unnecessarily restrictive.
5962 We could solve this problem by adding "-gp32" multilibs to gcc,
5963 but to set this flag before gcc is built with such multilibs will
5964 break too many systems.''
5966 But even more unhelpfully, the default linker output target for
5967 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5968 for 64-bit programs - you need to change the ABI to change this,
5969 and not all gcc targets support that currently. Therefore using
5970 this flag to detect 32-bit mode would do the wrong thing given
5971 the current gcc - it would make GDB treat these 64-bit programs
5972 as 32-bit programs by default. */
5974 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5975 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5977 /* Add/remove bits from an address. The MIPS needs be careful to
5978 ensure that all 32 bit addresses are sign extended to 64 bits. */
5979 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5981 /* Unwind the frame. */
5982 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5983 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5984 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
5986 /* Map debug register numbers onto internal register numbers. */
5987 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5988 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5989 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5990 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5991 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5992 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5994 /* MIPS version of CALL_DUMMY */
5996 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5997 replaced by a command, and all targets will default to on stack
5998 (regardless of the stack's execute status). */
5999 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6000 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6002 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6003 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6004 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6006 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6007 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6009 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6011 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6013 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6014 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6015 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6017 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6019 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6021 if (mips_abi
== MIPS_ABI_N32
)
6022 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6023 else if (mips_abi
== MIPS_ABI_N64
)
6024 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6026 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6028 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6029 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6030 need to all be folded into the target vector. Since they are
6031 being used as guards for target_stopped_by_watchpoint, why not have
6032 target_stopped_by_watchpoint return the type of watchpoint that the code
6034 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6036 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6038 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
6040 /* Virtual tables. */
6041 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6043 mips_register_g_packet_guesses (gdbarch
);
6045 /* Hook in OS ABI-specific overrides, if they have been registered. */
6046 info
.tdep_info
= (void *) tdesc_data
;
6047 gdbarch_init_osabi (info
, gdbarch
);
6049 /* Unwind the frame. */
6050 dwarf2_append_unwinders (gdbarch
);
6051 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6052 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6053 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6054 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6055 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6056 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6057 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6061 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6062 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6064 /* Override the normal target description methods to handle our
6065 dual real and pseudo registers. */
6066 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6067 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
6069 num_regs
= gdbarch_num_regs (gdbarch
);
6070 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6071 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6072 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6075 /* Add ABI-specific aliases for the registers. */
6076 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6077 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6078 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6079 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6081 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6082 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6083 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6085 /* Add some other standard aliases. */
6086 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6087 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6088 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6090 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6091 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6092 value_of_mips_user_reg
,
6093 &mips_numeric_register_aliases
[i
].regnum
);
6099 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6101 struct gdbarch_info info
;
6103 /* Force the architecture to update, and (if it's a MIPS architecture)
6104 mips_gdbarch_init will take care of the rest. */
6105 gdbarch_info_init (&info
);
6106 gdbarch_update_p (info
);
6109 /* Print out which MIPS ABI is in use. */
6112 show_mips_abi (struct ui_file
*file
,
6114 struct cmd_list_element
*ignored_cmd
,
6115 const char *ignored_value
)
6117 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6120 "The MIPS ABI is unknown because the current architecture "
6124 enum mips_abi global_abi
= global_mips_abi ();
6125 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6126 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6128 if (global_abi
== MIPS_ABI_UNKNOWN
)
6131 "The MIPS ABI is set automatically (currently \"%s\").\n",
6133 else if (global_abi
== actual_abi
)
6136 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6140 /* Probably shouldn't happen... */
6143 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6144 actual_abi_str
, mips_abi_strings
[global_abi
]);
6150 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6152 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6156 int ef_mips_32bitmode
;
6157 /* Determine the ISA. */
6158 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6176 /* Determine the size of a pointer. */
6177 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6178 fprintf_unfiltered (file
,
6179 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6181 fprintf_unfiltered (file
,
6182 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6184 fprintf_unfiltered (file
,
6185 "mips_dump_tdep: ef_mips_arch = %d\n",
6187 fprintf_unfiltered (file
,
6188 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6189 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6190 fprintf_unfiltered (file
,
6191 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6192 mips_mask_address_p (tdep
),
6193 tdep
->default_mask_address_p
);
6195 fprintf_unfiltered (file
,
6196 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6197 MIPS_DEFAULT_FPU_TYPE
,
6198 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6199 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6200 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6202 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6203 MIPS_EABI (gdbarch
));
6204 fprintf_unfiltered (file
,
6205 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6206 MIPS_FPU_TYPE (gdbarch
),
6207 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6208 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6209 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6213 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6216 _initialize_mips_tdep (void)
6218 static struct cmd_list_element
*mipsfpulist
= NULL
;
6219 struct cmd_list_element
*c
;
6221 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6222 if (MIPS_ABI_LAST
+ 1
6223 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6224 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6226 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6228 mips_pdr_data
= register_objfile_data ();
6230 /* Create feature sets with the appropriate properties. The values
6231 are not important. */
6232 mips_tdesc_gp32
= allocate_target_description ();
6233 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6235 mips_tdesc_gp64
= allocate_target_description ();
6236 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6238 /* Add root prefix command for all "set mips"/"show mips" commands */
6239 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6240 _("Various MIPS specific commands."),
6241 &setmipscmdlist
, "set mips ", 0, &setlist
);
6243 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6244 _("Various MIPS specific commands."),
6245 &showmipscmdlist
, "show mips ", 0, &showlist
);
6247 /* Allow the user to override the ABI. */
6248 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6249 &mips_abi_string
, _("\
6250 Set the MIPS ABI used by this program."), _("\
6251 Show the MIPS ABI used by this program."), _("\
6252 This option can be set to one of:\n\
6253 auto - the default ABI associated with the current binary\n\
6262 &setmipscmdlist
, &showmipscmdlist
);
6264 /* Let the user turn off floating point and set the fence post for
6265 heuristic_proc_start. */
6267 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6268 _("Set use of MIPS floating-point coprocessor."),
6269 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6270 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6271 _("Select single-precision MIPS floating-point coprocessor."),
6273 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6274 _("Select double-precision MIPS floating-point coprocessor."),
6276 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6277 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6278 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6279 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6280 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6281 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6282 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6283 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6284 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6285 _("Select MIPS floating-point coprocessor automatically."),
6287 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6288 _("Show current use of MIPS floating-point coprocessor target."),
6291 /* We really would like to have both "0" and "unlimited" work, but
6292 command.c doesn't deal with that. So make it a var_zinteger
6293 because the user can always use "999999" or some such for unlimited. */
6294 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6295 &heuristic_fence_post
, _("\
6296 Set the distance searched for the start of a function."), _("\
6297 Show the distance searched for the start of a function."), _("\
6298 If you are debugging a stripped executable, GDB needs to search through the\n\
6299 program for the start of a function. This command sets the distance of the\n\
6300 search. The only need to set it is when debugging a stripped executable."),
6301 reinit_frame_cache_sfunc
,
6302 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
6303 &setlist
, &showlist
);
6305 /* Allow the user to control whether the upper bits of 64-bit
6306 addresses should be zeroed. */
6307 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6308 &mask_address_var
, _("\
6309 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6310 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6311 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6312 allow GDB to determine the correct value."),
6313 NULL
, show_mask_address
,
6314 &setmipscmdlist
, &showmipscmdlist
);
6316 /* Allow the user to control the size of 32 bit registers within the
6317 raw remote packet. */
6318 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6319 &mips64_transfers_32bit_regs_p
, _("\
6320 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6322 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6324 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6325 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6326 64 bits for others. Use \"off\" to disable compatibility mode"),
6327 set_mips64_transfers_32bit_regs
,
6328 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6329 &setlist
, &showlist
);
6331 /* Debug this files internals. */
6332 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6334 Set mips debugging."), _("\
6335 Show mips debugging."), _("\
6336 When non-zero, mips specific debugging is enabled."),
6338 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
6339 &setdebuglist
, &showdebuglist
);