1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
54 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
55 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
57 /* A useful bit in the CP0 status register (PS_REGNUM). */
58 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
59 #define ST0_FR (1 << 26)
61 /* The sizes of floating point registers. */
65 MIPS_FPU_SINGLE_REGSIZE
= 4,
66 MIPS_FPU_DOUBLE_REGSIZE
= 8
70 static const char *mips_abi_string
;
72 static const char *mips_abi_strings
[] = {
83 struct frame_extra_info
85 mips_extra_func_info_t proc_desc
;
89 /* Various MIPS ISA options (related to stack analysis) can be
90 overridden dynamically. Establish an enum/array for managing
93 static const char size_auto
[] = "auto";
94 static const char size_32
[] = "32";
95 static const char size_64
[] = "64";
97 static const char *size_enums
[] = {
104 /* Some MIPS boards don't support floating point while others only
105 support single-precision floating-point operations. See also
106 FP_REGISTER_DOUBLE. */
110 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
111 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
112 MIPS_FPU_NONE
/* No floating point. */
115 #ifndef MIPS_DEFAULT_FPU_TYPE
116 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
118 static int mips_fpu_type_auto
= 1;
119 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
121 static int mips_debug
= 0;
123 /* MIPS specific per-architecture information */
126 /* from the elf header */
130 enum mips_abi mips_abi
;
131 enum mips_abi found_abi
;
132 enum mips_fpu_type mips_fpu_type
;
133 int mips_last_arg_regnum
;
134 int mips_last_fp_arg_regnum
;
135 int mips_default_saved_regsize
;
136 int mips_fp_register_double
;
137 int mips_default_stack_argsize
;
138 int default_mask_address_p
;
139 /* Is the target using 64-bit raw integer registers but only
140 storing a left-aligned 32-bit value in each? */
141 int mips64_transfers_32bit_regs_p
;
142 /* Indexes for various registers. IRIX and embedded have
143 different values. This contains the "public" fields. Don't
144 add any that do not need to be public. */
145 const struct mips_regnum
*regnum
;
146 /* Register names table for the current register set. */
147 const char **mips_processor_reg_names
;
150 const struct mips_regnum
*
151 mips_regnum (struct gdbarch
*gdbarch
)
153 return gdbarch_tdep (gdbarch
)->regnum
;
157 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
159 return mips_regnum (gdbarch
)->fp0
+ 12;
162 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
163 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
165 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
167 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
169 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
171 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
172 functions to test, set, or clear bit 0 of addresses. */
175 is_mips16_addr (CORE_ADDR addr
)
181 make_mips16_addr (CORE_ADDR addr
)
187 unmake_mips16_addr (CORE_ADDR addr
)
189 return ((addr
) & ~1);
192 /* Return the contents of register REGNUM as a signed integer. */
195 read_signed_register (int regnum
)
197 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
198 deprecated_read_register_gen (regnum
, buf
);
199 return (extract_signed_integer (buf
, register_size (current_gdbarch
, regnum
)));
203 read_signed_register_pid (int regnum
, ptid_t ptid
)
208 if (ptid_equal (ptid
, inferior_ptid
))
209 return read_signed_register (regnum
);
211 save_ptid
= inferior_ptid
;
213 inferior_ptid
= ptid
;
215 retval
= read_signed_register (regnum
);
217 inferior_ptid
= save_ptid
;
222 /* Return the MIPS ABI associated with GDBARCH. */
224 mips_abi (struct gdbarch
*gdbarch
)
226 return gdbarch_tdep (gdbarch
)->mips_abi
;
230 mips_regsize (struct gdbarch
*gdbarch
)
232 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
233 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
236 /* Return the currently configured (or set) saved register size. */
238 static const char *mips_saved_regsize_string
= size_auto
;
241 mips_saved_regsize (struct gdbarch_tdep
*tdep
)
243 if (mips_saved_regsize_string
== size_auto
)
244 return tdep
->mips_default_saved_regsize
;
245 else if (mips_saved_regsize_string
== size_64
)
247 else /* if (mips_saved_regsize_string == size_32) */
251 /* Functions for setting and testing a bit in a minimal symbol that
252 marks it as 16-bit function. The MSB of the minimal symbol's
253 "info" field is used for this purpose.
255 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
256 i.e. refers to a 16-bit function, and sets a "special" bit in a
257 minimal symbol to mark it as a 16-bit function
259 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
262 mips_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
264 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
266 MSYMBOL_INFO (msym
) = (char *)
267 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
268 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
273 msymbol_is_special (struct minimal_symbol
*msym
)
275 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
278 /* XFER a value from the big/little/left end of the register.
279 Depending on the size of the value it might occupy the entire
280 register or just part of it. Make an allowance for this, aligning
281 things accordingly. */
284 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
285 enum bfd_endian endian
, bfd_byte
*in
, const bfd_byte
*out
,
288 bfd_byte reg
[MAX_REGISTER_SIZE
];
290 gdb_assert (reg_num
>= NUM_REGS
);
291 /* Need to transfer the left or right part of the register, based on
292 the targets byte order. */
296 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
298 case BFD_ENDIAN_LITTLE
:
301 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
305 internal_error (__FILE__
, __LINE__
, "bad switch");
308 fprintf_unfiltered (gdb_stderr
,
309 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
310 reg_num
, reg_offset
, buf_offset
, length
);
311 if (mips_debug
&& out
!= NULL
)
314 fprintf_unfiltered (gdb_stdlog
, "out ");
315 for (i
= 0; i
< length
; i
++)
316 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
319 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
, in
+ buf_offset
);
321 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
, out
+ buf_offset
);
322 if (mips_debug
&& in
!= NULL
)
325 fprintf_unfiltered (gdb_stdlog
, "in ");
326 for (i
= 0; i
< length
; i
++)
327 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
330 fprintf_unfiltered (gdb_stdlog
, "\n");
333 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
334 compatiblity mode. A return value of 1 means that we have
335 physical 64-bit registers, but should treat them as 32-bit registers. */
338 mips2_fp_compat (void)
340 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
342 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 4)
346 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
347 in all the places we deal with FP registers. PR gdb/413. */
348 /* Otherwise check the FR bit in the status register - it controls
349 the FP compatiblity mode. If it is clear we are in compatibility
351 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
358 /* Indicate that the ABI makes use of double-precision registers
359 provided by the FPU (rather than combining pairs of registers to
360 form double-precision values). See also MIPS_FPU_TYPE. */
361 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
363 /* The amount of space reserved on the stack for registers. This is
364 different to MIPS_SAVED_REGSIZE as it determines the alignment of
365 data allocated after the registers have run out. */
367 static const char *mips_stack_argsize_string
= size_auto
;
370 mips_stack_argsize (struct gdbarch_tdep
*tdep
)
372 if (mips_stack_argsize_string
== size_auto
)
373 return tdep
->mips_default_stack_argsize
;
374 else if (mips_stack_argsize_string
== size_64
)
376 else /* if (mips_stack_argsize_string == size_32) */
380 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
382 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
383 struct frame_info
*, int);
385 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
387 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
389 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
391 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
392 struct frame_info
*next_frame
,
395 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
396 mips_extra_func_info_t proc_desc
);
398 static struct type
*mips_float_register_type (void);
399 static struct type
*mips_double_register_type (void);
401 /* The list of available "set mips " and "show mips " commands */
403 static struct cmd_list_element
*setmipscmdlist
= NULL
;
404 static struct cmd_list_element
*showmipscmdlist
= NULL
;
406 /* Integer registers 0 thru 31 are handled explicitly by
407 mips_register_name(). Processor specific registers 32 and above
408 are listed in the followign tables. */
410 enum { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
414 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
415 "sr", "lo", "hi", "bad", "cause","pc",
416 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
417 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
418 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
419 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
420 "fsr", "fir", ""/*"fp"*/, "",
421 "", "", "", "", "", "", "", "",
422 "", "", "", "", "", "", "", "",
425 /* Names of IDT R3041 registers. */
427 static const char *mips_r3041_reg_names
[] = {
428 "sr", "lo", "hi", "bad", "cause","pc",
429 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
430 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
431 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
432 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
433 "fsr", "fir", "",/*"fp"*/ "",
434 "", "", "bus", "ccfg", "", "", "", "",
435 "", "", "port", "cmp", "", "", "epc", "prid",
438 /* Names of tx39 registers. */
440 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
441 "sr", "lo", "hi", "bad", "cause","pc",
442 "", "", "", "", "", "", "", "",
443 "", "", "", "", "", "", "", "",
444 "", "", "", "", "", "", "", "",
445 "", "", "", "", "", "", "", "",
447 "", "", "", "", "", "", "", "",
448 "", "", "config", "cache", "debug", "depc", "epc", ""
451 /* Names of IRIX registers. */
452 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
453 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
454 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
455 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
456 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
457 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
461 /* Return the name of the register corresponding to REGNO. */
463 mips_register_name (int regno
)
465 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
466 /* GPR names for all ABIs other than n32/n64. */
467 static char *mips_gpr_names
[] = {
468 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
469 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
470 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
471 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
474 /* GPR names for n32 and n64 ABIs. */
475 static char *mips_n32_n64_gpr_names
[] = {
476 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
477 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
478 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
479 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
482 enum mips_abi abi
= mips_abi (current_gdbarch
);
484 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
485 don't make the raw register names visible. */
486 int rawnum
= regno
% NUM_REGS
;
487 if (regno
< NUM_REGS
)
490 /* The MIPS integer registers are always mapped from 0 to 31. The
491 names of the registers (which reflects the conventions regarding
492 register use) vary depending on the ABI. */
493 if (0 <= rawnum
&& rawnum
< 32)
495 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
496 return mips_n32_n64_gpr_names
[rawnum
];
498 return mips_gpr_names
[rawnum
];
500 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
502 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
503 return tdep
->mips_processor_reg_names
[rawnum
- 32];
506 internal_error (__FILE__
, __LINE__
,
507 "mips_register_name: bad register number %d", rawnum
);
510 /* Return the groups that a MIPS register can be categorised into. */
513 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
514 struct reggroup
*reggroup
)
519 int rawnum
= regnum
% NUM_REGS
;
520 int pseudo
= regnum
/ NUM_REGS
;
521 if (reggroup
== all_reggroup
)
523 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
524 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
525 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
526 (gdbarch), as not all architectures are multi-arch. */
527 raw_p
= rawnum
< NUM_REGS
;
528 if (REGISTER_NAME (regnum
) == NULL
529 || REGISTER_NAME (regnum
)[0] == '\0')
531 if (reggroup
== float_reggroup
)
532 return float_p
&& pseudo
;
533 if (reggroup
== vector_reggroup
)
534 return vector_p
&& pseudo
;
535 if (reggroup
== general_reggroup
)
536 return (!vector_p
&& !float_p
) && pseudo
;
537 /* Save the pseudo registers. Need to make certain that any code
538 extracting register values from a saved register cache also uses
540 if (reggroup
== save_reggroup
)
541 return raw_p
&& pseudo
;
542 /* Restore the same pseudo register. */
543 if (reggroup
== restore_reggroup
)
544 return raw_p
&& pseudo
;
548 /* Map the symbol table registers which live in the range [1 *
549 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
550 registers. Take care of alignment and size problems. */
553 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
554 int cookednum
, void *buf
)
556 int rawnum
= cookednum
% NUM_REGS
;
557 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
558 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
559 return regcache_raw_read (regcache
, rawnum
, buf
);
560 else if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, cookednum
))
562 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
563 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
564 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
566 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
569 internal_error (__FILE__
, __LINE__
, "bad register size");
573 mips_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
574 int cookednum
, const void *buf
)
576 int rawnum
= cookednum
% NUM_REGS
;
577 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
578 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
579 return regcache_raw_write (regcache
, rawnum
, buf
);
580 else if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, cookednum
))
582 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
583 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
584 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
586 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
589 internal_error (__FILE__
, __LINE__
, "bad register size");
592 /* Table to translate MIPS16 register field to actual register number. */
593 static int mips16_to_32_reg
[8] =
594 {16, 17, 2, 3, 4, 5, 6, 7};
596 /* Heuristic_proc_start may hunt through the text section for a long
597 time across a 2400 baud serial line. Allows the user to limit this
600 static unsigned int heuristic_fence_post
= 0;
602 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
603 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
604 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
605 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
606 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
607 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
608 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
609 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
610 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
611 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
612 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
613 this will corrupt pdr.iline. Fortunately we don't use it. */
614 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
615 #define _PROC_MAGIC_ 0x0F0F0F0F
616 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
617 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
619 struct linked_proc_info
621 struct mips_extra_func_info info
;
622 struct linked_proc_info
*next
;
624 *linked_proc_desc_table
= NULL
;
626 /* Number of bytes of storage in the actual machine representation for
627 register N. NOTE: This defines the pseudo register type so need to
628 rebuild the architecture vector. */
630 static int mips64_transfers_32bit_regs_p
= 0;
633 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
634 struct cmd_list_element
*c
)
636 struct gdbarch_info info
;
637 gdbarch_info_init (&info
);
638 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
639 instead of relying on globals. Doing that would let generic code
640 handle the search for this specific architecture. */
641 if (!gdbarch_update_p (info
))
643 mips64_transfers_32bit_regs_p
= 0;
644 error ("32-bit compatibility mode not supported");
648 /* Convert to/from a register and the corresponding memory value. */
651 mips_convert_register_p (int regnum
, struct type
*type
)
653 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
654 && register_size (current_gdbarch
, regnum
) == 4
655 && (regnum
) >= mips_regnum (current_gdbarch
)->fp0
&& (regnum
) < mips_regnum (current_gdbarch
)->fp0
+ 32
656 && TYPE_CODE(type
) == TYPE_CODE_FLT
657 && TYPE_LENGTH(type
) == 8);
661 mips_register_to_value (struct frame_info
*frame
, int regnum
,
662 struct type
*type
, void *to
)
664 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
665 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
669 mips_value_to_register (struct frame_info
*frame
, int regnum
,
670 struct type
*type
, const void *from
)
672 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
673 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
676 /* Return the GDB type object for the "standard" data type of data in
680 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
682 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
683 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
684 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
686 /* The floating-point registers raw, or cooked, always match
687 mips_regsize(), and also map 1:1, byte for byte. */
688 switch (gdbarch_byte_order (gdbarch
))
691 if (mips_regsize (gdbarch
) == 4)
692 return builtin_type_ieee_single_big
;
694 return builtin_type_ieee_double_big
;
695 case BFD_ENDIAN_LITTLE
:
696 if (mips_regsize (gdbarch
) == 4)
697 return builtin_type_ieee_single_little
;
699 return builtin_type_ieee_double_little
;
700 case BFD_ENDIAN_UNKNOWN
:
702 internal_error (__FILE__
, __LINE__
, "bad switch");
705 else if (regnum
>= (NUM_REGS
+ mips_regnum (current_gdbarch
)->fp_control_status
)
706 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
707 /* The pseudo/cooked view of the embedded registers is always
708 32-bit. The raw view is handled below. */
709 return builtin_type_int32
;
710 else if (regnum
>= NUM_REGS
&& mips_regsize (gdbarch
)
711 && gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
712 /* The target, while using a 64-bit register buffer, is only
713 transfering 32-bits of each integer register. Reflect this in
714 the cooked/pseudo register value. */
715 return builtin_type_int32
;
716 else if (mips_regsize (gdbarch
) == 8)
718 return builtin_type_int64
;
721 return builtin_type_int32
;
724 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
729 return read_signed_register (SP_REGNUM
);
732 /* Should the upper word of 64-bit addresses be zeroed? */
733 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
736 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
738 switch (mask_address_var
)
740 case AUTO_BOOLEAN_TRUE
:
742 case AUTO_BOOLEAN_FALSE
:
745 case AUTO_BOOLEAN_AUTO
:
746 return tdep
->default_mask_address_p
;
748 internal_error (__FILE__
, __LINE__
,
749 "mips_mask_address_p: bad switch");
755 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
757 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
758 switch (mask_address_var
)
760 case AUTO_BOOLEAN_TRUE
:
761 printf_filtered ("The 32 bit mips address mask is enabled\n");
763 case AUTO_BOOLEAN_FALSE
:
764 printf_filtered ("The 32 bit mips address mask is disabled\n");
766 case AUTO_BOOLEAN_AUTO
:
767 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
768 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
771 internal_error (__FILE__
, __LINE__
,
772 "show_mask_address: bad switch");
777 /* Should call_function allocate stack space for a struct return? */
780 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
782 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
783 return (TYPE_LENGTH (type
) > 2 * mips_saved_regsize (tdep
));
786 /* Should call_function pass struct by reference?
787 For each architecture, structs are passed either by
788 value or by reference, depending on their size. */
791 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
793 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
794 int len
= TYPE_LENGTH (check_typedef (type
));
795 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
797 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
798 return (len
> mips_saved_regsize (tdep
));
804 mips_n32n64_reg_struct_has_addr (int gcc_p
, struct type
*type
)
806 return 0; /* Assumption: N32/N64 never passes struct by ref. */
810 mips_o32_reg_struct_has_addr (int gcc_p
, struct type
*type
)
812 return 0; /* Assumption: O32/O64 never passes struct by ref. */
815 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
818 pc_is_mips16 (bfd_vma memaddr
)
820 struct minimal_symbol
*sym
;
822 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
823 if (is_mips16_addr (memaddr
))
826 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
827 the high bit of the info field. Use this to decide if the function is
828 MIPS16 or normal MIPS. */
829 sym
= lookup_minimal_symbol_by_pc (memaddr
);
831 return msymbol_is_special (sym
);
836 /* MIPS believes that the PC has a sign extended value. Perhaphs the
837 all registers should be sign extended for simplicity? */
840 mips_read_pc (ptid_t ptid
)
842 return read_signed_register_pid (PC_REGNUM
, ptid
);
845 /* This returns the PC of the first inst after the prologue. If we can't
846 find the prologue, then return 0. */
849 after_prologue (CORE_ADDR pc
,
850 mips_extra_func_info_t proc_desc
)
852 struct symtab_and_line sal
;
853 CORE_ADDR func_addr
, func_end
;
855 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
856 to read the stack pointer from the current machine state, because
857 the current machine state has nothing to do with the information
858 we need from the proc_desc; and the process may or may not exist
861 proc_desc
= find_proc_desc (pc
, NULL
, 0);
865 /* If function is frameless, then we need to do it the hard way. I
866 strongly suspect that frameless always means prologueless... */
867 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
868 && PROC_FRAME_OFFSET (proc_desc
) == 0)
872 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
873 return 0; /* Unknown */
875 sal
= find_pc_line (func_addr
, 0);
877 if (sal
.end
< func_end
)
880 /* The line after the prologue is after the end of the function. In this
881 case, tell the caller to find the prologue the hard way. */
886 /* Decode a MIPS32 instruction that saves a register in the stack, and
887 set the appropriate bit in the general register mask or float register mask
888 to indicate which register is saved. This is a helper function
889 for mips_find_saved_regs. */
892 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
893 unsigned long *float_mask
)
897 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
898 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
899 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
901 /* It might be possible to use the instruction to
902 find the offset, rather than the code below which
903 is based on things being in a certain order in the
904 frame, but figuring out what the instruction's offset
905 is relative to might be a little tricky. */
906 reg
= (inst
& 0x001f0000) >> 16;
907 *gen_mask
|= (1 << reg
);
909 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
910 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
911 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
914 reg
= ((inst
& 0x001f0000) >> 16);
915 *float_mask
|= (1 << reg
);
919 /* Decode a MIPS16 instruction that saves a register in the stack, and
920 set the appropriate bit in the general register or float register mask
921 to indicate which register is saved. This is a helper function
922 for mips_find_saved_regs. */
925 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
927 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
929 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
930 *gen_mask
|= (1 << reg
);
932 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
934 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
935 *gen_mask
|= (1 << reg
);
937 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
938 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
939 *gen_mask
|= (1 << RA_REGNUM
);
943 /* Fetch and return instruction from the specified location. If the PC
944 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
947 mips_fetch_instruction (CORE_ADDR addr
)
949 char buf
[MIPS_INSTLEN
];
953 if (pc_is_mips16 (addr
))
955 instlen
= MIPS16_INSTLEN
;
956 addr
= unmake_mips16_addr (addr
);
959 instlen
= MIPS_INSTLEN
;
960 status
= read_memory_nobpt (addr
, buf
, instlen
);
962 memory_error (status
, addr
);
963 return extract_unsigned_integer (buf
, instlen
);
967 /* These the fields of 32 bit mips instructions */
968 #define mips32_op(x) (x >> 26)
969 #define itype_op(x) (x >> 26)
970 #define itype_rs(x) ((x >> 21) & 0x1f)
971 #define itype_rt(x) ((x >> 16) & 0x1f)
972 #define itype_immediate(x) (x & 0xffff)
974 #define jtype_op(x) (x >> 26)
975 #define jtype_target(x) (x & 0x03ffffff)
977 #define rtype_op(x) (x >> 26)
978 #define rtype_rs(x) ((x >> 21) & 0x1f)
979 #define rtype_rt(x) ((x >> 16) & 0x1f)
980 #define rtype_rd(x) ((x >> 11) & 0x1f)
981 #define rtype_shamt(x) ((x >> 6) & 0x1f)
982 #define rtype_funct(x) (x & 0x3f)
985 mips32_relative_offset (unsigned long inst
)
988 x
= itype_immediate (inst
);
989 if (x
& 0x8000) /* sign bit set */
991 x
|= 0xffff0000; /* sign extension */
997 /* Determine whate to set a single step breakpoint while considering
1000 mips32_next_pc (CORE_ADDR pc
)
1004 inst
= mips_fetch_instruction (pc
);
1005 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1007 if (itype_op (inst
) >> 2 == 5)
1008 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1010 op
= (itype_op (inst
) & 0x03);
1020 goto greater_branch
;
1025 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1026 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1028 int tf
= itype_rt (inst
) & 0x01;
1029 int cnum
= itype_rt (inst
) >> 2;
1030 int fcrcs
= read_signed_register (mips_regnum (current_gdbarch
)->fp_control_status
);
1031 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1033 if (((cond
>> cnum
) & 0x01) == tf
)
1034 pc
+= mips32_relative_offset (inst
) + 4;
1039 pc
+= 4; /* Not a branch, next instruction is easy */
1042 { /* This gets way messy */
1044 /* Further subdivide into SPECIAL, REGIMM and other */
1045 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1047 case 0: /* SPECIAL */
1048 op
= rtype_funct (inst
);
1053 /* Set PC to that address */
1054 pc
= read_signed_register (rtype_rs (inst
));
1060 break; /* end SPECIAL */
1061 case 1: /* REGIMM */
1063 op
= itype_rt (inst
); /* branch condition */
1068 case 16: /* BLTZAL */
1069 case 18: /* BLTZALL */
1071 if (read_signed_register (itype_rs (inst
)) < 0)
1072 pc
+= mips32_relative_offset (inst
) + 4;
1074 pc
+= 8; /* after the delay slot */
1078 case 17: /* BGEZAL */
1079 case 19: /* BGEZALL */
1080 if (read_signed_register (itype_rs (inst
)) >= 0)
1081 pc
+= mips32_relative_offset (inst
) + 4;
1083 pc
+= 8; /* after the delay slot */
1085 /* All of the other instructions in the REGIMM category */
1090 break; /* end REGIMM */
1095 reg
= jtype_target (inst
) << 2;
1096 /* Upper four bits get never changed... */
1097 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1100 /* FIXME case JALX : */
1103 reg
= jtype_target (inst
) << 2;
1104 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1105 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1107 break; /* The new PC will be alternate mode */
1108 case 4: /* BEQ, BEQL */
1110 if (read_signed_register (itype_rs (inst
)) ==
1111 read_signed_register (itype_rt (inst
)))
1112 pc
+= mips32_relative_offset (inst
) + 4;
1116 case 5: /* BNE, BNEL */
1118 if (read_signed_register (itype_rs (inst
)) !=
1119 read_signed_register (itype_rt (inst
)))
1120 pc
+= mips32_relative_offset (inst
) + 4;
1124 case 6: /* BLEZ, BLEZL */
1125 if (read_signed_register (itype_rs (inst
) <= 0))
1126 pc
+= mips32_relative_offset (inst
) + 4;
1132 greater_branch
: /* BGTZ, BGTZL */
1133 if (read_signed_register (itype_rs (inst
) > 0))
1134 pc
+= mips32_relative_offset (inst
) + 4;
1141 } /* mips32_next_pc */
1143 /* Decoding the next place to set a breakpoint is irregular for the
1144 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1145 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1146 We dont want to set a single step instruction on the extend instruction
1150 /* Lots of mips16 instruction formats */
1151 /* Predicting jumps requires itype,ritype,i8type
1152 and their extensions extItype,extritype,extI8type
1154 enum mips16_inst_fmts
1156 itype
, /* 0 immediate 5,10 */
1157 ritype
, /* 1 5,3,8 */
1158 rrtype
, /* 2 5,3,3,5 */
1159 rritype
, /* 3 5,3,3,5 */
1160 rrrtype
, /* 4 5,3,3,3,2 */
1161 rriatype
, /* 5 5,3,3,1,4 */
1162 shifttype
, /* 6 5,3,3,3,2 */
1163 i8type
, /* 7 5,3,8 */
1164 i8movtype
, /* 8 5,3,3,5 */
1165 i8mov32rtype
, /* 9 5,3,5,3 */
1166 i64type
, /* 10 5,3,8 */
1167 ri64type
, /* 11 5,3,3,5 */
1168 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1169 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1170 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1171 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1172 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1173 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1174 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1175 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1176 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1177 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1179 /* I am heaping all the fields of the formats into one structure and
1180 then, only the fields which are involved in instruction extension */
1184 unsigned int regx
; /* Function in i8 type */
1189 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1190 for the bits which make up the immediatate extension. */
1193 extended_offset (unsigned int extension
)
1196 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1198 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1200 value
|= extension
& 0x01f; /* extract 4:0 */
1204 /* Only call this function if you know that this is an extendable
1205 instruction, It wont malfunction, but why make excess remote memory references?
1206 If the immediate operands get sign extended or somthing, do it after
1207 the extension is performed.
1209 /* FIXME: Every one of these cases needs to worry about sign extension
1210 when the offset is to be used in relative addressing */
1214 fetch_mips_16 (CORE_ADDR pc
)
1217 pc
&= 0xfffffffe; /* clear the low order bit */
1218 target_read_memory (pc
, buf
, 2);
1219 return extract_unsigned_integer (buf
, 2);
1223 unpack_mips16 (CORE_ADDR pc
,
1224 unsigned int extension
,
1226 enum mips16_inst_fmts insn_format
,
1227 struct upk_mips16
*upk
)
1232 switch (insn_format
)
1239 value
= extended_offset (extension
);
1240 value
= value
<< 11; /* rom for the original value */
1241 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1245 value
= inst
& 0x7ff;
1246 /* FIXME : Consider sign extension */
1255 { /* A register identifier and an offset */
1256 /* Most of the fields are the same as I type but the
1257 immediate value is of a different length */
1261 value
= extended_offset (extension
);
1262 value
= value
<< 8; /* from the original instruction */
1263 value
|= inst
& 0xff; /* eleven bits from instruction */
1264 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1265 if (value
& 0x4000) /* test the sign bit , bit 26 */
1267 value
&= ~0x3fff; /* remove the sign bit */
1273 value
= inst
& 0xff; /* 8 bits */
1274 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1275 /* FIXME: Do sign extension , this format needs it */
1276 if (value
& 0x80) /* THIS CONFUSES ME */
1278 value
&= 0xef; /* remove the sign bit */
1288 unsigned long value
;
1289 unsigned int nexthalf
;
1290 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1291 value
= value
<< 16;
1292 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1300 internal_error (__FILE__
, __LINE__
,
1303 upk
->offset
= offset
;
1310 add_offset_16 (CORE_ADDR pc
, int offset
)
1312 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1316 extended_mips16_next_pc (CORE_ADDR pc
,
1317 unsigned int extension
,
1320 int op
= (insn
>> 11);
1323 case 2: /* Branch */
1326 struct upk_mips16 upk
;
1327 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1328 offset
= upk
.offset
;
1334 pc
+= (offset
<< 1) + 2;
1337 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1339 struct upk_mips16 upk
;
1340 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1341 pc
= add_offset_16 (pc
, upk
.offset
);
1342 if ((insn
>> 10) & 0x01) /* Exchange mode */
1343 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1350 struct upk_mips16 upk
;
1352 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1353 reg
= read_signed_register (upk
.regx
);
1355 pc
+= (upk
.offset
<< 1) + 2;
1362 struct upk_mips16 upk
;
1364 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1365 reg
= read_signed_register (upk
.regx
);
1367 pc
+= (upk
.offset
<< 1) + 2;
1372 case 12: /* I8 Formats btez btnez */
1374 struct upk_mips16 upk
;
1376 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1377 /* upk.regx contains the opcode */
1378 reg
= read_signed_register (24); /* Test register is 24 */
1379 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1380 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1381 /* pc = add_offset_16(pc,upk.offset) ; */
1382 pc
+= (upk
.offset
<< 1) + 2;
1387 case 29: /* RR Formats JR, JALR, JALR-RA */
1389 struct upk_mips16 upk
;
1390 /* upk.fmt = rrtype; */
1395 upk
.regx
= (insn
>> 8) & 0x07;
1396 upk
.regy
= (insn
>> 5) & 0x07;
1404 break; /* Function return instruction */
1410 break; /* BOGUS Guess */
1412 pc
= read_signed_register (reg
);
1419 /* This is an instruction extension. Fetch the real instruction
1420 (which follows the extension) and decode things based on
1424 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1437 mips16_next_pc (CORE_ADDR pc
)
1439 unsigned int insn
= fetch_mips_16 (pc
);
1440 return extended_mips16_next_pc (pc
, 0, insn
);
1443 /* The mips_next_pc function supports single_step when the remote
1444 target monitor or stub is not developed enough to do a single_step.
1445 It works by decoding the current instruction and predicting where a
1446 branch will go. This isnt hard because all the data is available.
1447 The MIPS32 and MIPS16 variants are quite different */
1449 mips_next_pc (CORE_ADDR pc
)
1452 return mips16_next_pc (pc
);
1454 return mips32_next_pc (pc
);
1457 /* Set up the 'saved_regs' array. This is a data structure containing
1458 the addresses on the stack where each register has been saved, for
1459 each stack frame. Registers that have not been saved will have
1460 zero here. The stack pointer register is special: rather than the
1461 address where the stack register has been saved,
1462 saved_regs[SP_REGNUM] will have the actual value of the previous
1463 frame's stack register. */
1466 mips_find_saved_regs (struct frame_info
*fci
)
1469 /* r0 bit means kernel trap */
1471 /* What registers have been saved? Bitmasks. */
1472 unsigned long gen_mask
, float_mask
;
1473 mips_extra_func_info_t proc_desc
;
1475 CORE_ADDR
*saved_regs
;
1476 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1478 if (deprecated_get_frame_saved_regs (fci
) != NULL
)
1480 saved_regs
= frame_saved_regs_zalloc (fci
);
1482 /* If it is the frame for sigtramp, the saved registers are located
1483 in a sigcontext structure somewhere on the stack. If the stack
1484 layout for sigtramp changes we might have to change these
1485 constants and the companion fixup_sigtramp in mdebugread.c */
1486 #ifndef SIGFRAME_BASE
1487 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1488 above the sigtramp frame. */
1489 #define SIGFRAME_BASE mips_regsize (current_gdbarch)
1490 /* FIXME! Are these correct?? */
1491 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch))
1492 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch))
1493 #define SIGFRAME_FPREGSAVE_OFF \
1494 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch))
1496 if ((get_frame_type (fci
) == SIGTRAMP_FRAME
))
1498 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1500 CORE_ADDR reg_position
= (get_frame_base (fci
) + SIGFRAME_REGSAVE_OFF
1501 + ireg
* mips_regsize (current_gdbarch
));
1502 set_reg_offset (saved_regs
, ireg
, reg_position
);
1504 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1506 CORE_ADDR reg_position
= (get_frame_base (fci
)
1507 + SIGFRAME_FPREGSAVE_OFF
1508 + ireg
* mips_regsize (current_gdbarch
));
1509 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
, reg_position
);
1512 set_reg_offset (saved_regs
, PC_REGNUM
, get_frame_base (fci
) + SIGFRAME_PC_OFF
);
1513 /* SP_REGNUM, contains the value and not the address. */
1514 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1518 proc_desc
= get_frame_extra_info (fci
)->proc_desc
;
1519 if (proc_desc
== NULL
)
1520 /* I'm not sure how/whether this can happen. Normally when we
1521 can't find a proc_desc, we "synthesize" one using
1522 heuristic_proc_desc and set the saved_regs right away. */
1525 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1526 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1527 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1529 if (/* In any frame other than the innermost or a frame interrupted
1530 by a signal, we assume that all registers have been saved.
1531 This assumes that all register saves in a function happen
1532 before the first function call. */
1533 (get_next_frame (fci
) == NULL
1534 || (get_frame_type (get_next_frame (fci
)) == SIGTRAMP_FRAME
))
1536 /* In a dummy frame we know exactly where things are saved. */
1537 && !PROC_DESC_IS_DUMMY (proc_desc
)
1539 /* Don't bother unless we are inside a function prologue.
1540 Outside the prologue, we know where everything is. */
1542 && in_prologue (get_frame_pc (fci
), PROC_LOW_ADDR (proc_desc
))
1544 /* Not sure exactly what kernel_trap means, but if it means the
1545 kernel saves the registers without a prologue doing it, we
1546 better not examine the prologue to see whether registers
1547 have been saved yet. */
1550 /* We need to figure out whether the registers that the
1551 proc_desc claims are saved have been saved yet. */
1555 /* Bitmasks; set if we have found a save for the register. */
1556 unsigned long gen_save_found
= 0;
1557 unsigned long float_save_found
= 0;
1560 /* If the address is odd, assume this is MIPS16 code. */
1561 addr
= PROC_LOW_ADDR (proc_desc
);
1562 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1564 /* Scan through this function's instructions preceding the
1565 current PC, and look for those that save registers. */
1566 while (addr
< get_frame_pc (fci
))
1568 inst
= mips_fetch_instruction (addr
);
1569 if (pc_is_mips16 (addr
))
1570 mips16_decode_reg_save (inst
, &gen_save_found
);
1572 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1575 gen_mask
= gen_save_found
;
1576 float_mask
= float_save_found
;
1579 /* Fill in the offsets for the registers which gen_mask says were
1582 CORE_ADDR reg_position
= (get_frame_base (fci
)
1583 + PROC_REG_OFFSET (proc_desc
));
1584 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1585 if (gen_mask
& 0x80000000)
1587 set_reg_offset (saved_regs
, ireg
, reg_position
);
1588 reg_position
-= mips_saved_regsize (tdep
);
1592 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1593 order of that normally used by gcc. Therefore, we have to fetch
1594 the first instruction of the function, and if it's an entry
1595 instruction that saves $s0 or $s1, correct their saved addresses. */
1596 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1598 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1599 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1603 int sreg_count
= (inst
>> 6) & 3;
1605 /* Check if the ra register was pushed on the stack. */
1606 CORE_ADDR reg_position
= (get_frame_base (fci
)
1607 + PROC_REG_OFFSET (proc_desc
));
1609 reg_position
-= mips_saved_regsize (tdep
);
1611 /* Check if the s0 and s1 registers were pushed on the
1613 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1615 set_reg_offset (saved_regs
, reg
, reg_position
);
1616 reg_position
-= mips_saved_regsize (tdep
);
1621 /* Fill in the offsets for the registers which float_mask says were
1624 CORE_ADDR reg_position
= (get_frame_base (fci
)
1625 + PROC_FREG_OFFSET (proc_desc
));
1627 /* Fill in the offsets for the float registers which float_mask
1629 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1630 if (float_mask
& 0x80000000)
1632 if (mips_saved_regsize (tdep
) == 4
1633 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1635 /* On a big endian 32 bit ABI, floating point registers
1636 are paired to form doubles such that the most
1637 significant part is in $f[N+1] and the least
1638 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1639 registers are also spilled as a pair and stored as a
1642 When little-endian the least significant part is
1643 stored first leading to the memory order $f[N] and
1646 Unfortunately, when big-endian the most significant
1647 part of the double is stored first, and the least
1648 significant is stored second. This leads to the
1649 registers being ordered in memory as firt $f[N+1] and
1652 For the big-endian case make certain that the
1653 addresses point at the correct (swapped) locations
1654 $f[N] and $f[N+1] pair (keep in mind that
1655 reg_position is decremented each time through the
1658 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1659 reg_position
- mips_saved_regsize (tdep
));
1661 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1662 reg_position
+ mips_saved_regsize (tdep
));
1665 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->fp0
+ ireg
, reg_position
);
1666 reg_position
-= mips_saved_regsize (tdep
);
1669 set_reg_offset (saved_regs
, PC_REGNUM
, saved_regs
[RA_REGNUM
]);
1672 /* SP_REGNUM, contains the value and not the address. */
1673 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1677 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1679 /* Always a pseudo. */
1680 gdb_assert (regno
>= NUM_REGS
);
1684 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1687 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1688 /* The SP_REGNUM is special, its value is stored in saved_regs.
1689 In fact, it is so special that it can even only be fetched
1690 using a raw register number! Once this code as been converted
1691 to frame-unwind the problem goes away. */
1692 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1694 return frame_unwind_register_signed (fi
, regno
);
1698 /* mips_addr_bits_remove - remove useless address bits */
1701 mips_addr_bits_remove (CORE_ADDR addr
)
1703 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1704 if (mips_mask_address_p (tdep
)
1705 && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
1706 /* This hack is a work-around for existing boards using PMON, the
1707 simulator, and any other 64-bit targets that doesn't have true
1708 64-bit addressing. On these targets, the upper 32 bits of
1709 addresses are ignored by the hardware. Thus, the PC or SP are
1710 likely to have been sign extended to all 1s by instruction
1711 sequences that load 32-bit addresses. For example, a typical
1712 piece of code that loads an address is this:
1714 lui $r2, <upper 16 bits>
1715 ori $r2, <lower 16 bits>
1717 But the lui sign-extends the value such that the upper 32 bits
1718 may be all 1s. The workaround is simply to mask off these
1719 bits. In the future, gcc may be changed to support true 64-bit
1720 addressing, and this masking will have to be disabled. */
1721 return addr
&= 0xffffffffUL
;
1726 /* mips_software_single_step() is called just before we want to resume
1727 the inferior, if we want to single-step it but there is no hardware
1728 or kernel single-step support (MIPS on GNU/Linux for example). We find
1729 the target of the coming instruction and breakpoint it.
1731 single_step is also called just after the inferior stops. If we had
1732 set up a simulated single-step, we undo our damage. */
1735 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1737 static CORE_ADDR next_pc
;
1738 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1739 static binsn_quantum break_mem
;
1742 if (insert_breakpoints_p
)
1744 pc
= read_register (PC_REGNUM
);
1745 next_pc
= mips_next_pc (pc
);
1747 target_insert_breakpoint (next_pc
, break_mem
);
1750 target_remove_breakpoint (next_pc
, break_mem
);
1754 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1759 ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev
))
1760 : get_next_frame (prev
)
1761 ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev
))
1763 tmp
= SKIP_TRAMPOLINE_CODE (pc
);
1764 return tmp
? tmp
: pc
;
1769 mips_frame_saved_pc (struct frame_info
*frame
)
1772 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1774 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
1776 /* Always unwind the cooked PC register value. */
1777 saved_pc
= frame_unwind_register_signed (frame
, NUM_REGS
+ PC_REGNUM
);
1781 mips_extra_func_info_t proc_desc
1782 = get_frame_extra_info (frame
)->proc_desc
;
1783 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1784 saved_pc
= read_memory_integer ((get_frame_base (frame
)
1785 - mips_saved_regsize (tdep
))
1786 , mips_saved_regsize (tdep
));
1789 /* We have to get the saved pc from the sigcontext if it is
1790 a signal handler frame. */
1791 int pcreg
= (get_frame_type (frame
) == SIGTRAMP_FRAME
? PC_REGNUM
1792 : proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1793 saved_pc
= read_next_frame_reg (frame
, NUM_REGS
+ pcreg
);
1796 return ADDR_BITS_REMOVE (saved_pc
);
1799 static struct mips_extra_func_info temp_proc_desc
;
1801 /* This hack will go away once the get_prev_frame() code has been
1802 modified to set the frame's type first. That is BEFORE init extra
1803 frame info et.al. is called. This is because it will become
1804 possible to skip the init extra info call for sigtramp and dummy
1806 static CORE_ADDR
*temp_saved_regs
;
1808 /* Set a register's saved stack address in temp_saved_regs. If an
1809 address has already been set for this register, do nothing; this
1810 way we will only recognize the first save of a given register in a
1813 For simplicity, save the address in both [0 .. NUM_REGS) and
1814 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1815 is used as it is only second range (the ABI instead of ISA
1816 registers) that comes into play when finding saved registers in a
1820 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
1822 if (saved_regs
[regno
] == 0)
1824 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
1825 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
1830 /* Test whether the PC points to the return instruction at the
1831 end of a function. */
1834 mips_about_to_return (CORE_ADDR pc
)
1836 if (pc_is_mips16 (pc
))
1837 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1838 generates a "jr $ra"; other times it generates code to load
1839 the return address from the stack to an accessible register (such
1840 as $a3), then a "jr" using that register. This second case
1841 is almost impossible to distinguish from an indirect jump
1842 used for switch statements, so we don't even try. */
1843 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1845 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1849 /* This fencepost looks highly suspicious to me. Removing it also
1850 seems suspicious as it could affect remote debugging across serial
1854 heuristic_proc_start (CORE_ADDR pc
)
1861 pc
= ADDR_BITS_REMOVE (pc
);
1863 fence
= start_pc
- heuristic_fence_post
;
1867 if (heuristic_fence_post
== UINT_MAX
1868 || fence
< VM_MIN_ADDRESS
)
1869 fence
= VM_MIN_ADDRESS
;
1871 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1873 /* search back for previous return */
1874 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1875 if (start_pc
< fence
)
1877 /* It's not clear to me why we reach this point when
1878 stop_soon, but with this test, at least we
1879 don't print out warnings for every child forked (eg, on
1880 decstation). 22apr93 rich@cygnus.com. */
1881 if (stop_soon
== NO_STOP_QUIETLY
)
1883 static int blurb_printed
= 0;
1885 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1890 /* This actually happens frequently in embedded
1891 development, when you first connect to a board
1892 and your stack pointer and pc are nowhere in
1893 particular. This message needs to give people
1894 in that situation enough information to
1895 determine that it's no big deal. */
1896 printf_filtered ("\n\
1897 GDB is unable to find the start of the function at 0x%s\n\
1898 and thus can't determine the size of that function's stack frame.\n\
1899 This means that GDB may be unable to access that stack frame, or\n\
1900 the frames below it.\n\
1901 This problem is most likely caused by an invalid program counter or\n\
1903 However, if you think GDB should simply search farther back\n\
1904 from 0x%s for code which looks like the beginning of a\n\
1905 function, you can increase the range of the search using the `set\n\
1906 heuristic-fence-post' command.\n",
1907 paddr_nz (pc
), paddr_nz (pc
));
1914 else if (pc_is_mips16 (start_pc
))
1916 unsigned short inst
;
1918 /* On MIPS16, any one of the following is likely to be the
1919 start of a function:
1923 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1924 inst
= mips_fetch_instruction (start_pc
);
1925 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1926 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1927 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1928 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1930 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1931 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1936 else if (mips_about_to_return (start_pc
))
1938 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1945 /* Fetch the immediate value from a MIPS16 instruction.
1946 If the previous instruction was an EXTEND, use it to extend
1947 the upper bits of the immediate value. This is a helper function
1948 for mips16_heuristic_proc_desc. */
1951 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1952 unsigned short inst
, /* current instruction */
1953 int nbits
, /* number of bits in imm field */
1954 int scale
, /* scale factor to be applied to imm */
1955 int is_signed
) /* is the imm field signed? */
1959 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1961 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1962 if (offset
& 0x8000) /* check for negative extend */
1963 offset
= 0 - (0x10000 - (offset
& 0xffff));
1964 return offset
| (inst
& 0x1f);
1968 int max_imm
= 1 << nbits
;
1969 int mask
= max_imm
- 1;
1970 int sign_bit
= max_imm
>> 1;
1972 offset
= inst
& mask
;
1973 if (is_signed
&& (offset
& sign_bit
))
1974 offset
= 0 - (max_imm
- offset
);
1975 return offset
* scale
;
1980 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1981 stream from start_pc to limit_pc. */
1984 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1985 struct frame_info
*next_frame
, CORE_ADDR sp
)
1988 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1989 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1990 unsigned inst
= 0; /* current instruction */
1991 unsigned entry_inst
= 0; /* the entry instruction */
1993 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1995 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1996 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1998 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2000 /* Save the previous instruction. If it's an EXTEND, we'll extract
2001 the immediate offset extension from it in mips16_get_imm. */
2004 /* Fetch and decode the instruction. */
2005 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2006 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2007 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2009 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2010 if (offset
< 0) /* negative stack adjustment? */
2011 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2013 /* Exit loop if a positive stack adjustment is found, which
2014 usually means that the stack cleanup code in the function
2015 epilogue is reached. */
2018 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2020 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2021 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2022 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2023 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2025 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2027 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2028 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2029 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2030 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2032 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2034 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2035 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2036 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2038 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2040 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2041 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2042 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2044 else if (inst
== 0x673d) /* move $s1, $sp */
2047 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2049 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2051 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2052 frame_addr
= sp
+ offset
;
2053 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2054 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2056 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2058 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2059 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2060 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2061 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2063 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2065 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2066 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2067 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2068 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2070 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2071 entry_inst
= inst
; /* save for later processing */
2072 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2073 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2076 /* The entry instruction is typically the first instruction in a function,
2077 and it stores registers at offsets relative to the value of the old SP
2078 (before the prologue). But the value of the sp parameter to this
2079 function is the new SP (after the prologue has been executed). So we
2080 can't calculate those offsets until we've seen the entire prologue,
2081 and can calculate what the old SP must have been. */
2082 if (entry_inst
!= 0)
2084 int areg_count
= (entry_inst
>> 8) & 7;
2085 int sreg_count
= (entry_inst
>> 6) & 3;
2087 /* The entry instruction always subtracts 32 from the SP. */
2088 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2090 /* Now we can calculate what the SP must have been at the
2091 start of the function prologue. */
2092 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2094 /* Check if a0-a3 were saved in the caller's argument save area. */
2095 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2097 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2098 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2099 offset
+= mips_saved_regsize (tdep
);
2102 /* Check if the ra register was pushed on the stack. */
2104 if (entry_inst
& 0x20)
2106 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2107 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2108 offset
-= mips_saved_regsize (tdep
);
2111 /* Check if the s0 and s1 registers were pushed on the stack. */
2112 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2114 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2115 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2116 offset
-= mips_saved_regsize (tdep
);
2122 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2123 struct frame_info
*next_frame
, CORE_ADDR sp
)
2126 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2128 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2129 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2130 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2131 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2132 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2134 unsigned long inst
, high_word
, low_word
;
2137 /* Fetch the instruction. */
2138 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2140 /* Save some code by pre-extracting some useful fields. */
2141 high_word
= (inst
>> 16) & 0xffff;
2142 low_word
= inst
& 0xffff;
2143 reg
= high_word
& 0x1f;
2145 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2146 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2147 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2149 if (low_word
& 0x8000) /* negative stack adjustment? */
2150 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2152 /* Exit loop if a positive stack adjustment is found, which
2153 usually means that the stack cleanup code in the function
2154 epilogue is reached. */
2157 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2159 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2160 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2162 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2164 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2165 but the register size used is only 32 bits. Make the address
2166 for the saved register point to the lower 32 bits. */
2167 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2168 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
+ 8 - mips_regsize (current_gdbarch
));
2170 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2172 /* Old gcc frame, r30 is virtual frame pointer. */
2173 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2174 frame_addr
= sp
+ low_word
;
2175 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2177 unsigned alloca_adjust
;
2178 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2179 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2180 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2181 if (alloca_adjust
> 0)
2183 /* FP > SP + frame_size. This may be because
2184 * of an alloca or somethings similar.
2185 * Fix sp to "pre-alloca" value, and try again.
2187 sp
+= alloca_adjust
;
2192 /* move $30,$sp. With different versions of gas this will be either
2193 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2194 Accept any one of these. */
2195 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2197 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2198 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2200 unsigned alloca_adjust
;
2201 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2202 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2203 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2204 if (alloca_adjust
> 0)
2206 /* FP > SP + frame_size. This may be because
2207 * of an alloca or somethings similar.
2208 * Fix sp to "pre-alloca" value, and try again.
2210 sp
+= alloca_adjust
;
2215 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2217 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2218 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2223 static mips_extra_func_info_t
2224 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2225 struct frame_info
*next_frame
, int cur_frame
)
2230 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2236 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2237 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2238 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2239 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2240 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2241 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2243 if (start_pc
+ 200 < limit_pc
)
2244 limit_pc
= start_pc
+ 200;
2245 if (pc_is_mips16 (start_pc
))
2246 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2248 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2249 return &temp_proc_desc
;
2252 struct mips_objfile_private
2258 /* Global used to communicate between non_heuristic_proc_desc and
2259 compare_pdr_entries within qsort (). */
2260 static bfd
*the_bfd
;
2263 compare_pdr_entries (const void *a
, const void *b
)
2265 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2266 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2270 else if (lhs
== rhs
)
2276 static mips_extra_func_info_t
2277 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2279 CORE_ADDR startaddr
;
2280 mips_extra_func_info_t proc_desc
;
2281 struct block
*b
= block_for_pc (pc
);
2283 struct obj_section
*sec
;
2284 struct mips_objfile_private
*priv
;
2286 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2289 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2291 *addrptr
= startaddr
;
2295 sec
= find_pc_section (pc
);
2298 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2300 /* Search the ".pdr" section generated by GAS. This includes most of
2301 the information normally found in ECOFF PDRs. */
2303 the_bfd
= sec
->objfile
->obfd
;
2305 && (the_bfd
->format
== bfd_object
2306 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2307 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2309 /* Right now GAS only outputs the address as a four-byte sequence.
2310 This means that we should not bother with this method on 64-bit
2311 targets (until that is fixed). */
2313 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2314 sizeof (struct mips_objfile_private
));
2316 sec
->objfile
->obj_private
= priv
;
2318 else if (priv
== NULL
)
2322 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2323 sizeof (struct mips_objfile_private
));
2325 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2328 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2329 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2331 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2332 priv
->contents
, 0, priv
->size
);
2334 /* In general, the .pdr section is sorted. However, in the
2335 presence of multiple code sections (and other corner cases)
2336 it can become unsorted. Sort it so that we can use a faster
2338 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
2343 sec
->objfile
->obj_private
= priv
;
2347 if (priv
->size
!= 0)
2353 high
= priv
->size
/ 32;
2359 mid
= (low
+ high
) / 2;
2361 ptr
= priv
->contents
+ mid
* 32;
2362 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2363 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2364 SECT_OFF_TEXT (sec
->objfile
));
2365 if (pdr_pc
== startaddr
)
2367 if (pdr_pc
> startaddr
)
2372 while (low
!= high
);
2376 struct symbol
*sym
= find_pc_function (pc
);
2378 /* Fill in what we need of the proc_desc. */
2379 proc_desc
= (mips_extra_func_info_t
)
2380 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2381 sizeof (struct mips_extra_func_info
));
2382 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2384 /* Only used for dummy frames. */
2385 PROC_HIGH_ADDR (proc_desc
) = 0;
2387 PROC_FRAME_OFFSET (proc_desc
)
2388 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2389 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2391 PROC_FRAME_ADJUST (proc_desc
) = 0;
2392 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2394 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2396 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2398 PROC_FREG_OFFSET (proc_desc
)
2399 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2400 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2402 proc_desc
->pdr
.isym
= (long) sym
;
2412 if (startaddr
> BLOCK_START (b
))
2414 /* This is the "pathological" case referred to in a comment in
2415 print_frame_info. It might be better to move this check into
2420 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2422 /* If we never found a PDR for this function in symbol reading, then
2423 examine prologues to find the information. */
2426 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2427 if (PROC_FRAME_REG (proc_desc
) == -1)
2437 static mips_extra_func_info_t
2438 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2440 mips_extra_func_info_t proc_desc
;
2441 CORE_ADDR startaddr
= 0;
2443 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2447 /* IF this is the topmost frame AND
2448 * (this proc does not have debugging information OR
2449 * the PC is in the procedure prologue)
2450 * THEN create a "heuristic" proc_desc (by analyzing
2451 * the actual code) to replace the "official" proc_desc.
2453 if (next_frame
== NULL
)
2455 struct symtab_and_line val
;
2456 struct symbol
*proc_symbol
=
2457 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2461 val
= find_pc_line (BLOCK_START
2462 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2464 val
.pc
= val
.end
? val
.end
: pc
;
2466 if (!proc_symbol
|| pc
< val
.pc
)
2468 mips_extra_func_info_t found_heuristic
=
2469 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2470 pc
, next_frame
, cur_frame
);
2471 if (found_heuristic
)
2472 proc_desc
= found_heuristic
;
2478 /* Is linked_proc_desc_table really necessary? It only seems to be used
2479 by procedure call dummys. However, the procedures being called ought
2480 to have their own proc_descs, and even if they don't,
2481 heuristic_proc_desc knows how to create them! */
2483 struct linked_proc_info
*link
;
2485 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2486 if (PROC_LOW_ADDR (&link
->info
) <= pc
2487 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2491 startaddr
= heuristic_proc_start (pc
);
2494 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2500 get_frame_pointer (struct frame_info
*frame
,
2501 mips_extra_func_info_t proc_desc
)
2503 return (read_next_frame_reg (frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2504 + PROC_FRAME_OFFSET (proc_desc
)
2505 - PROC_FRAME_ADJUST (proc_desc
));
2508 static mips_extra_func_info_t cached_proc_desc
;
2511 mips_frame_chain (struct frame_info
*frame
)
2513 mips_extra_func_info_t proc_desc
;
2515 CORE_ADDR saved_pc
= DEPRECATED_FRAME_SAVED_PC (frame
);
2517 /* Check if the PC is inside a call stub. If it is, fetch the
2518 PC of the caller of that stub. */
2519 if ((tmp
= SKIP_TRAMPOLINE_CODE (saved_pc
)) != 0)
2522 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc
, 0, 0))
2524 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2525 is well, frame->frame the bottom of the current frame will
2526 contain that value. */
2527 return get_frame_base (frame
);
2530 /* Look up the procedure descriptor for this PC. */
2531 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2535 cached_proc_desc
= proc_desc
;
2537 /* If no frame pointer and frame size is zero, we must be at end
2538 of stack (or otherwise hosed). If we don't check frame size,
2539 we loop forever if we see a zero size frame. */
2540 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2541 && PROC_FRAME_OFFSET (proc_desc
) == 0
2542 /* The previous frame from a sigtramp frame might be frameless
2543 and have frame size zero. */
2544 && !(get_frame_type (frame
) == SIGTRAMP_FRAME
)
2545 /* For a generic dummy frame, let get_frame_pointer() unwind a
2546 register value saved as part of the dummy frame call. */
2547 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0)))
2550 return get_frame_pointer (frame
, proc_desc
);
2554 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2557 mips_extra_func_info_t proc_desc
;
2559 if (get_frame_type (fci
) == DUMMY_FRAME
)
2562 /* Use proc_desc calculated in frame_chain. When there is no
2563 next frame, i.e, get_next_frame (fci) == NULL, we call
2564 find_proc_desc () to calculate it, passing an explicit
2565 NULL as the frame parameter. */
2567 get_next_frame (fci
)
2569 : find_proc_desc (get_frame_pc (fci
),
2570 NULL
/* i.e, get_next_frame (fci) */,
2573 frame_extra_info_zalloc (fci
, sizeof (struct frame_extra_info
));
2575 get_frame_extra_info (fci
)->proc_desc
=
2576 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2579 /* Fixup frame-pointer - only needed for top frame */
2580 /* This may not be quite right, if proc has a real frame register.
2581 Get the value of the frame relative sp, procedure might have been
2582 interrupted by a signal at it's very start. */
2583 if (get_frame_pc (fci
) == PROC_LOW_ADDR (proc_desc
)
2584 && !PROC_DESC_IS_DUMMY (proc_desc
))
2585 deprecated_update_frame_base_hack (fci
, read_next_frame_reg (get_next_frame (fci
), NUM_REGS
+ SP_REGNUM
));
2586 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci
), 0, 0))
2587 /* Do not ``fix'' fci->frame. It will have the value of the
2588 generic dummy frame's top-of-stack (since the draft
2589 fci->frame is obtained by returning the unwound stack
2590 pointer) and that is what we want. That way the fci->frame
2591 value will match the top-of-stack value that was saved as
2592 part of the dummy frames data. */
2595 deprecated_update_frame_base_hack (fci
, get_frame_pointer (get_next_frame (fci
), proc_desc
));
2597 if (proc_desc
== &temp_proc_desc
)
2601 /* Do not set the saved registers for a sigtramp frame,
2602 mips_find_saved_registers will do that for us. We can't
2603 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2605 /* FIXME: cagney/2002-11-18: This problem will go away once
2606 frame.c:get_prev_frame() is modified to set the frame's
2607 type before calling functions like this. */
2608 find_pc_partial_function (get_frame_pc (fci
), &name
,
2609 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2610 if (!PC_IN_SIGTRAMP (get_frame_pc (fci
), name
))
2612 frame_saved_regs_zalloc (fci
);
2613 /* Set value of previous frame's stack pointer.
2614 Remember that saved_regs[SP_REGNUM] is special in
2615 that it contains the value of the stack pointer
2616 register. The other saved_regs values are addresses
2617 (in the inferior) at which a given register's value
2619 set_reg_offset (temp_saved_regs
, SP_REGNUM
,
2620 get_frame_base (fci
));
2621 set_reg_offset (temp_saved_regs
, PC_REGNUM
,
2622 temp_saved_regs
[RA_REGNUM
]);
2623 memcpy (deprecated_get_frame_saved_regs (fci
), temp_saved_regs
,
2624 SIZEOF_FRAME_SAVED_REGS
);
2628 /* hack: if argument regs are saved, guess these contain args */
2629 /* assume we can't tell how many args for now */
2630 get_frame_extra_info (fci
)->num_args
= -1;
2631 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2633 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2635 get_frame_extra_info (fci
)->num_args
= regnum
- A0_REGNUM
+ 1;
2642 /* MIPS stack frames are almost impenetrable. When execution stops,
2643 we basically have to look at symbol information for the function
2644 that we stopped in, which tells us *which* register (if any) is
2645 the base of the frame pointer, and what offset from that register
2646 the frame itself is at.
2648 This presents a problem when trying to examine a stack in memory
2649 (that isn't executing at the moment), using the "frame" command. We
2650 don't have a PC, nor do we have any registers except SP.
2652 This routine takes two arguments, SP and PC, and tries to make the
2653 cached frames look as if these two arguments defined a frame on the
2654 cache. This allows the rest of info frame to extract the important
2655 arguments without difficulty. */
2658 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2661 error ("MIPS frame specifications require two arguments: sp and pc");
2663 return create_new_frame (argv
[0], argv
[1]);
2666 /* According to the current ABI, should the type be passed in a
2667 floating-point register (assuming that there is space)? When there
2668 is no FPU, FP are not even considered as possibile candidates for
2669 FP registers and, consequently this returns false - forces FP
2670 arguments into integer registers. */
2673 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2675 return ((typecode
== TYPE_CODE_FLT
2677 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2678 && TYPE_NFIELDS (arg_type
) == 1
2679 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2680 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2683 /* On o32, argument passing in GPRs depends on the alignment of the type being
2684 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2687 mips_type_needs_double_align (struct type
*type
)
2689 enum type_code typecode
= TYPE_CODE (type
);
2691 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2693 else if (typecode
== TYPE_CODE_STRUCT
)
2695 if (TYPE_NFIELDS (type
) < 1)
2697 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2699 else if (typecode
== TYPE_CODE_UNION
)
2703 n
= TYPE_NFIELDS (type
);
2704 for (i
= 0; i
< n
; i
++)
2705 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2712 /* Adjust the address downward (direction of stack growth) so that it
2713 is correctly aligned for a new stack frame. */
2715 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2717 return align_down (addr
, 16);
2721 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2722 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2723 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2724 CORE_ADDR struct_addr
)
2730 int stack_offset
= 0;
2731 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2733 /* For shared libraries, "t9" needs to point at the function
2735 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2737 /* Set the return address register to point to the entry point of
2738 the program, where a breakpoint lies in wait. */
2739 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2741 /* First ensure that the stack and structure return address (if any)
2742 are properly aligned. The stack has to be at least 64-bit
2743 aligned even on 32-bit machines, because doubles must be 64-bit
2744 aligned. For n32 and n64, stack frames need to be 128-bit
2745 aligned, so we round to this widest known alignment. */
2747 sp
= align_down (sp
, 16);
2748 struct_addr
= align_down (struct_addr
, 16);
2750 /* Now make space on the stack for the args. We allocate more
2751 than necessary for EABI, because the first few arguments are
2752 passed in registers, but that's OK. */
2753 for (argnum
= 0; argnum
< nargs
; argnum
++)
2754 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2755 mips_stack_argsize (tdep
));
2756 sp
-= align_up (len
, 16);
2759 fprintf_unfiltered (gdb_stdlog
,
2760 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2761 paddr_nz (sp
), (long) align_up (len
, 16));
2763 /* Initialize the integer and float register pointers. */
2765 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2767 /* The struct_return pointer occupies the first parameter-passing reg. */
2771 fprintf_unfiltered (gdb_stdlog
,
2772 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2773 argreg
, paddr_nz (struct_addr
));
2774 write_register (argreg
++, struct_addr
);
2777 /* Now load as many as possible of the first arguments into
2778 registers, and push the rest onto the stack. Loop thru args
2779 from first to last. */
2780 for (argnum
= 0; argnum
< nargs
; argnum
++)
2783 char valbuf
[MAX_REGISTER_SIZE
];
2784 struct value
*arg
= args
[argnum
];
2785 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2786 int len
= TYPE_LENGTH (arg_type
);
2787 enum type_code typecode
= TYPE_CODE (arg_type
);
2790 fprintf_unfiltered (gdb_stdlog
,
2791 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2792 argnum
+ 1, len
, (int) typecode
);
2794 /* The EABI passes structures that do not fit in a register by
2796 if (len
> mips_saved_regsize (tdep
)
2797 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2799 store_unsigned_integer (valbuf
, mips_saved_regsize (tdep
),
2800 VALUE_ADDRESS (arg
));
2801 typecode
= TYPE_CODE_PTR
;
2802 len
= mips_saved_regsize (tdep
);
2805 fprintf_unfiltered (gdb_stdlog
, " push");
2808 val
= (char *) VALUE_CONTENTS (arg
);
2810 /* 32-bit ABIs always start floating point arguments in an
2811 even-numbered floating point register. Round the FP register
2812 up before the check to see if there are any FP registers
2813 left. Non MIPS_EABI targets also pass the FP in the integer
2814 registers so also round up normal registers. */
2815 if (!FP_REGISTER_DOUBLE
2816 && fp_register_arg_p (typecode
, arg_type
))
2818 if ((float_argreg
& 1))
2822 /* Floating point arguments passed in registers have to be
2823 treated specially. On 32-bit architectures, doubles
2824 are passed in register pairs; the even register gets
2825 the low word, and the odd register gets the high word.
2826 On non-EABI processors, the first two floating point arguments are
2827 also copied to general registers, because MIPS16 functions
2828 don't use float registers for arguments. This duplication of
2829 arguments in general registers can't hurt non-MIPS16 functions
2830 because those registers are normally skipped. */
2831 /* MIPS_EABI squeezes a struct that contains a single floating
2832 point value into an FP register instead of pushing it onto the
2834 if (fp_register_arg_p (typecode
, arg_type
)
2835 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2837 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2839 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2840 unsigned long regval
;
2842 /* Write the low word of the double to the even register(s). */
2843 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2845 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2846 float_argreg
, phex (regval
, 4));
2847 write_register (float_argreg
++, regval
);
2849 /* Write the high word of the double to the odd register(s). */
2850 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2852 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2853 float_argreg
, phex (regval
, 4));
2854 write_register (float_argreg
++, regval
);
2858 /* This is a floating point value that fits entirely
2859 in a single register. */
2860 /* On 32 bit ABI's the float_argreg is further adjusted
2861 above to ensure that it is even register aligned. */
2862 LONGEST regval
= extract_unsigned_integer (val
, len
);
2864 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2865 float_argreg
, phex (regval
, len
));
2866 write_register (float_argreg
++, regval
);
2871 /* Copy the argument to general registers or the stack in
2872 register-sized pieces. Large arguments are split between
2873 registers and stack. */
2874 /* Note: structs whose size is not a multiple of
2875 mips_regsize() are treated specially: Irix cc passes them
2876 in registers where gcc sometimes puts them on the stack.
2877 For maximum compatibility, we will put them in both
2879 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
2880 && (len
% mips_saved_regsize (tdep
) != 0));
2882 /* Note: Floating-point values that didn't fit into an FP
2883 register are only written to memory. */
2886 /* Remember if the argument was written to the stack. */
2887 int stack_used_p
= 0;
2888 int partial_len
= (len
< mips_saved_regsize (tdep
)
2889 ? len
: mips_saved_regsize (tdep
));
2892 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2895 /* Write this portion of the argument to the stack. */
2896 if (argreg
> MIPS_LAST_ARG_REGNUM
2898 || fp_register_arg_p (typecode
, arg_type
))
2900 /* Should shorter than int integer values be
2901 promoted to int before being stored? */
2902 int longword_offset
= 0;
2905 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2907 if (mips_stack_argsize (tdep
) == 8
2908 && (typecode
== TYPE_CODE_INT
2909 || typecode
== TYPE_CODE_PTR
2910 || typecode
== TYPE_CODE_FLT
)
2912 longword_offset
= mips_stack_argsize (tdep
) - len
;
2913 else if ((typecode
== TYPE_CODE_STRUCT
2914 || typecode
== TYPE_CODE_UNION
)
2915 && (TYPE_LENGTH (arg_type
)
2916 < mips_stack_argsize (tdep
)))
2917 longword_offset
= mips_stack_argsize (tdep
) - len
;
2922 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2923 paddr_nz (stack_offset
));
2924 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2925 paddr_nz (longword_offset
));
2928 addr
= sp
+ stack_offset
+ longword_offset
;
2933 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2935 for (i
= 0; i
< partial_len
; i
++)
2937 fprintf_unfiltered (gdb_stdlog
, "%02x",
2941 write_memory (addr
, val
, partial_len
);
2944 /* Note!!! This is NOT an else clause. Odd sized
2945 structs may go thru BOTH paths. Floating point
2946 arguments will not. */
2947 /* Write this portion of the argument to a general
2948 purpose register. */
2949 if (argreg
<= MIPS_LAST_ARG_REGNUM
2950 && !fp_register_arg_p (typecode
, arg_type
))
2952 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2955 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2957 phex (regval
, mips_saved_regsize (tdep
)));
2958 write_register (argreg
, regval
);
2965 /* Compute the the offset into the stack at which we
2966 will copy the next parameter.
2968 In the new EABI (and the NABI32), the stack_offset
2969 only needs to be adjusted when it has been used. */
2972 stack_offset
+= align_up (partial_len
,
2973 mips_stack_argsize (tdep
));
2977 fprintf_unfiltered (gdb_stdlog
, "\n");
2980 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
2982 /* Return adjusted stack pointer. */
2986 /* N32/N64 version of push_dummy_call. */
2989 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2990 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2991 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2992 CORE_ADDR struct_addr
)
2998 int stack_offset
= 0;
2999 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3001 /* For shared libraries, "t9" needs to point at the function
3003 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3005 /* Set the return address register to point to the entry point of
3006 the program, where a breakpoint lies in wait. */
3007 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3009 /* First ensure that the stack and structure return address (if any)
3010 are properly aligned. The stack has to be at least 64-bit
3011 aligned even on 32-bit machines, because doubles must be 64-bit
3012 aligned. For n32 and n64, stack frames need to be 128-bit
3013 aligned, so we round to this widest known alignment. */
3015 sp
= align_down (sp
, 16);
3016 struct_addr
= align_down (struct_addr
, 16);
3018 /* Now make space on the stack for the args. */
3019 for (argnum
= 0; argnum
< nargs
; argnum
++)
3020 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3021 mips_stack_argsize (tdep
));
3022 sp
-= align_up (len
, 16);
3025 fprintf_unfiltered (gdb_stdlog
,
3026 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3027 paddr_nz (sp
), (long) align_up (len
, 16));
3029 /* Initialize the integer and float register pointers. */
3031 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3033 /* The struct_return pointer occupies the first parameter-passing reg. */
3037 fprintf_unfiltered (gdb_stdlog
,
3038 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3039 argreg
, paddr_nz (struct_addr
));
3040 write_register (argreg
++, struct_addr
);
3043 /* Now load as many as possible of the first arguments into
3044 registers, and push the rest onto the stack. Loop thru args
3045 from first to last. */
3046 for (argnum
= 0; argnum
< nargs
; argnum
++)
3049 char valbuf
[MAX_REGISTER_SIZE
];
3050 struct value
*arg
= args
[argnum
];
3051 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3052 int len
= TYPE_LENGTH (arg_type
);
3053 enum type_code typecode
= TYPE_CODE (arg_type
);
3056 fprintf_unfiltered (gdb_stdlog
,
3057 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3058 argnum
+ 1, len
, (int) typecode
);
3060 val
= (char *) VALUE_CONTENTS (arg
);
3062 if (fp_register_arg_p (typecode
, arg_type
)
3063 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3065 /* This is a floating point value that fits entirely
3066 in a single register. */
3067 /* On 32 bit ABI's the float_argreg is further adjusted
3068 above to ensure that it is even register aligned. */
3069 LONGEST regval
= extract_unsigned_integer (val
, len
);
3071 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3072 float_argreg
, phex (regval
, len
));
3073 write_register (float_argreg
++, regval
);
3076 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3077 argreg
, phex (regval
, len
));
3078 write_register (argreg
, regval
);
3083 /* Copy the argument to general registers or the stack in
3084 register-sized pieces. Large arguments are split between
3085 registers and stack. */
3086 /* Note: structs whose size is not a multiple of
3087 mips_regsize() are treated specially: Irix cc passes them
3088 in registers where gcc sometimes puts them on the stack.
3089 For maximum compatibility, we will put them in both
3091 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3092 && (len
% mips_saved_regsize (tdep
) != 0));
3093 /* Note: Floating-point values that didn't fit into an FP
3094 register are only written to memory. */
3097 /* Rememer if the argument was written to the stack. */
3098 int stack_used_p
= 0;
3099 int partial_len
= (len
< mips_saved_regsize (tdep
)
3100 ? len
: mips_saved_regsize (tdep
));
3103 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3106 /* Write this portion of the argument to the stack. */
3107 if (argreg
> MIPS_LAST_ARG_REGNUM
3109 || fp_register_arg_p (typecode
, arg_type
))
3111 /* Should shorter than int integer values be
3112 promoted to int before being stored? */
3113 int longword_offset
= 0;
3116 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3118 if (mips_stack_argsize (tdep
) == 8
3119 && (typecode
== TYPE_CODE_INT
3120 || typecode
== TYPE_CODE_PTR
3121 || typecode
== TYPE_CODE_FLT
)
3123 longword_offset
= mips_stack_argsize (tdep
) - len
;
3128 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3129 paddr_nz (stack_offset
));
3130 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3131 paddr_nz (longword_offset
));
3134 addr
= sp
+ stack_offset
+ longword_offset
;
3139 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3141 for (i
= 0; i
< partial_len
; i
++)
3143 fprintf_unfiltered (gdb_stdlog
, "%02x",
3147 write_memory (addr
, val
, partial_len
);
3150 /* Note!!! This is NOT an else clause. Odd sized
3151 structs may go thru BOTH paths. Floating point
3152 arguments will not. */
3153 /* Write this portion of the argument to a general
3154 purpose register. */
3155 if (argreg
<= MIPS_LAST_ARG_REGNUM
3156 && !fp_register_arg_p (typecode
, arg_type
))
3158 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
3160 /* A non-floating-point argument being passed in a
3161 general register. If a struct or union, and if
3162 the remaining length is smaller than the register
3163 size, we have to adjust the register value on
3166 It does not seem to be necessary to do the
3167 same for integral types.
3169 cagney/2001-07-23: gdb/179: Also, GCC, when
3170 outputting LE O32 with sizeof (struct) <
3171 mips_saved_regsize(), generates a left shift as
3172 part of storing the argument in a register a
3173 register (the left shift isn't generated when
3174 sizeof (struct) >= mips_saved_regsize()). Since
3175 it is quite possible that this is GCC
3176 contradicting the LE/O32 ABI, GDB has not been
3177 adjusted to accommodate this. Either someone
3178 needs to demonstrate that the LE/O32 ABI
3179 specifies such a left shift OR this new ABI gets
3180 identified as such and GDB gets tweaked
3183 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3184 && partial_len
< mips_saved_regsize (tdep
)
3185 && (typecode
== TYPE_CODE_STRUCT
||
3186 typecode
== TYPE_CODE_UNION
))
3187 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3191 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3193 phex (regval
, mips_saved_regsize (tdep
)));
3194 write_register (argreg
, regval
);
3201 /* Compute the the offset into the stack at which we
3202 will copy the next parameter.
3204 In N32 (N64?), the stack_offset only needs to be
3205 adjusted when it has been used. */
3208 stack_offset
+= align_up (partial_len
,
3209 mips_stack_argsize (tdep
));
3213 fprintf_unfiltered (gdb_stdlog
, "\n");
3216 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3218 /* Return adjusted stack pointer. */
3222 /* O32 version of push_dummy_call. */
3225 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3226 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3227 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3228 CORE_ADDR struct_addr
)
3234 int stack_offset
= 0;
3235 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3237 /* For shared libraries, "t9" needs to point at the function
3239 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3241 /* Set the return address register to point to the entry point of
3242 the program, where a breakpoint lies in wait. */
3243 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3245 /* First ensure that the stack and structure return address (if any)
3246 are properly aligned. The stack has to be at least 64-bit
3247 aligned even on 32-bit machines, because doubles must be 64-bit
3248 aligned. For n32 and n64, stack frames need to be 128-bit
3249 aligned, so we round to this widest known alignment. */
3251 sp
= align_down (sp
, 16);
3252 struct_addr
= align_down (struct_addr
, 16);
3254 /* Now make space on the stack for the args. */
3255 for (argnum
= 0; argnum
< nargs
; argnum
++)
3256 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3257 mips_stack_argsize (tdep
));
3258 sp
-= align_up (len
, 16);
3261 fprintf_unfiltered (gdb_stdlog
,
3262 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3263 paddr_nz (sp
), (long) align_up (len
, 16));
3265 /* Initialize the integer and float register pointers. */
3267 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3269 /* The struct_return pointer occupies the first parameter-passing reg. */
3273 fprintf_unfiltered (gdb_stdlog
,
3274 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3275 argreg
, paddr_nz (struct_addr
));
3276 write_register (argreg
++, struct_addr
);
3277 stack_offset
+= mips_stack_argsize (tdep
);
3280 /* Now load as many as possible of the first arguments into
3281 registers, and push the rest onto the stack. Loop thru args
3282 from first to last. */
3283 for (argnum
= 0; argnum
< nargs
; argnum
++)
3286 char valbuf
[MAX_REGISTER_SIZE
];
3287 struct value
*arg
= args
[argnum
];
3288 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3289 int len
= TYPE_LENGTH (arg_type
);
3290 enum type_code typecode
= TYPE_CODE (arg_type
);
3293 fprintf_unfiltered (gdb_stdlog
,
3294 "mips_o32_push_dummy_call: %d len=%d type=%d",
3295 argnum
+ 1, len
, (int) typecode
);
3297 val
= (char *) VALUE_CONTENTS (arg
);
3299 /* 32-bit ABIs always start floating point arguments in an
3300 even-numbered floating point register. Round the FP register
3301 up before the check to see if there are any FP registers
3302 left. O32/O64 targets also pass the FP in the integer
3303 registers so also round up normal registers. */
3304 if (!FP_REGISTER_DOUBLE
3305 && fp_register_arg_p (typecode
, arg_type
))
3307 if ((float_argreg
& 1))
3311 /* Floating point arguments passed in registers have to be
3312 treated specially. On 32-bit architectures, doubles
3313 are passed in register pairs; the even register gets
3314 the low word, and the odd register gets the high word.
3315 On O32/O64, the first two floating point arguments are
3316 also copied to general registers, because MIPS16 functions
3317 don't use float registers for arguments. This duplication of
3318 arguments in general registers can't hurt non-MIPS16 functions
3319 because those registers are normally skipped. */
3321 if (fp_register_arg_p (typecode
, arg_type
)
3322 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3324 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3326 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3327 unsigned long regval
;
3329 /* Write the low word of the double to the even register(s). */
3330 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3332 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3333 float_argreg
, phex (regval
, 4));
3334 write_register (float_argreg
++, regval
);
3336 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3337 argreg
, phex (regval
, 4));
3338 write_register (argreg
++, regval
);
3340 /* Write the high word of the double to the odd register(s). */
3341 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3343 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3344 float_argreg
, phex (regval
, 4));
3345 write_register (float_argreg
++, regval
);
3348 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3349 argreg
, phex (regval
, 4));
3350 write_register (argreg
++, regval
);
3354 /* This is a floating point value that fits entirely
3355 in a single register. */
3356 /* On 32 bit ABI's the float_argreg is further adjusted
3357 above to ensure that it is even register aligned. */
3358 LONGEST regval
= extract_unsigned_integer (val
, len
);
3360 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3361 float_argreg
, phex (regval
, len
));
3362 write_register (float_argreg
++, regval
);
3363 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3364 registers for each argument. The below is (my
3365 guess) to ensure that the corresponding integer
3366 register has reserved the same space. */
3368 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3369 argreg
, phex (regval
, len
));
3370 write_register (argreg
, regval
);
3371 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3373 /* Reserve space for the FP register. */
3374 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
3378 /* Copy the argument to general registers or the stack in
3379 register-sized pieces. Large arguments are split between
3380 registers and stack. */
3381 /* Note: structs whose size is not a multiple of
3382 mips_regsize() are treated specially: Irix cc passes them
3383 in registers where gcc sometimes puts them on the stack.
3384 For maximum compatibility, we will put them in both
3386 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3387 && (len
% mips_saved_regsize (tdep
) != 0));
3388 /* Structures should be aligned to eight bytes (even arg registers)
3389 on MIPS_ABI_O32, if their first member has double precision. */
3390 if (mips_saved_regsize (tdep
) < 8
3391 && mips_type_needs_double_align (arg_type
))
3396 /* Note: Floating-point values that didn't fit into an FP
3397 register are only written to memory. */
3400 /* Remember if the argument was written to the stack. */
3401 int stack_used_p
= 0;
3402 int partial_len
= (len
< mips_saved_regsize (tdep
)
3403 ? len
: mips_saved_regsize (tdep
));
3406 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3409 /* Write this portion of the argument to the stack. */
3410 if (argreg
> MIPS_LAST_ARG_REGNUM
3412 || fp_register_arg_p (typecode
, arg_type
))
3414 /* Should shorter than int integer values be
3415 promoted to int before being stored? */
3416 int longword_offset
= 0;
3419 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3421 if (mips_stack_argsize (tdep
) == 8
3422 && (typecode
== TYPE_CODE_INT
3423 || typecode
== TYPE_CODE_PTR
3424 || typecode
== TYPE_CODE_FLT
)
3426 longword_offset
= mips_stack_argsize (tdep
) - len
;
3431 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3432 paddr_nz (stack_offset
));
3433 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3434 paddr_nz (longword_offset
));
3437 addr
= sp
+ stack_offset
+ longword_offset
;
3442 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3444 for (i
= 0; i
< partial_len
; i
++)
3446 fprintf_unfiltered (gdb_stdlog
, "%02x",
3450 write_memory (addr
, val
, partial_len
);
3453 /* Note!!! This is NOT an else clause. Odd sized
3454 structs may go thru BOTH paths. Floating point
3455 arguments will not. */
3456 /* Write this portion of the argument to a general
3457 purpose register. */
3458 if (argreg
<= MIPS_LAST_ARG_REGNUM
3459 && !fp_register_arg_p (typecode
, arg_type
))
3461 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3462 /* Value may need to be sign extended, because
3463 mips_regsize() != mips_saved_regsize(). */
3465 /* A non-floating-point argument being passed in a
3466 general register. If a struct or union, and if
3467 the remaining length is smaller than the register
3468 size, we have to adjust the register value on
3471 It does not seem to be necessary to do the
3472 same for integral types.
3474 Also don't do this adjustment on O64 binaries.
3476 cagney/2001-07-23: gdb/179: Also, GCC, when
3477 outputting LE O32 with sizeof (struct) <
3478 mips_saved_regsize(), generates a left shift as
3479 part of storing the argument in a register a
3480 register (the left shift isn't generated when
3481 sizeof (struct) >= mips_saved_regsize()). Since
3482 it is quite possible that this is GCC
3483 contradicting the LE/O32 ABI, GDB has not been
3484 adjusted to accommodate this. Either someone
3485 needs to demonstrate that the LE/O32 ABI
3486 specifies such a left shift OR this new ABI gets
3487 identified as such and GDB gets tweaked
3490 if (mips_saved_regsize (tdep
) < 8
3491 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3492 && partial_len
< mips_saved_regsize (tdep
)
3493 && (typecode
== TYPE_CODE_STRUCT
||
3494 typecode
== TYPE_CODE_UNION
))
3495 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3499 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3501 phex (regval
, mips_saved_regsize (tdep
)));
3502 write_register (argreg
, regval
);
3505 /* Prevent subsequent floating point arguments from
3506 being passed in floating point registers. */
3507 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3513 /* Compute the the offset into the stack at which we
3514 will copy the next parameter.
3516 In older ABIs, the caller reserved space for
3517 registers that contained arguments. This was loosely
3518 refered to as their "home". Consequently, space is
3519 always allocated. */
3521 stack_offset
+= align_up (partial_len
,
3522 mips_stack_argsize (tdep
));
3526 fprintf_unfiltered (gdb_stdlog
, "\n");
3529 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3531 /* Return adjusted stack pointer. */
3535 /* O64 version of push_dummy_call. */
3538 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3539 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3540 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3541 CORE_ADDR struct_addr
)
3547 int stack_offset
= 0;
3548 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3550 /* For shared libraries, "t9" needs to point at the function
3552 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3554 /* Set the return address register to point to the entry point of
3555 the program, where a breakpoint lies in wait. */
3556 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3558 /* First ensure that the stack and structure return address (if any)
3559 are properly aligned. The stack has to be at least 64-bit
3560 aligned even on 32-bit machines, because doubles must be 64-bit
3561 aligned. For n32 and n64, stack frames need to be 128-bit
3562 aligned, so we round to this widest known alignment. */
3564 sp
= align_down (sp
, 16);
3565 struct_addr
= align_down (struct_addr
, 16);
3567 /* Now make space on the stack for the args. */
3568 for (argnum
= 0; argnum
< nargs
; argnum
++)
3569 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3570 mips_stack_argsize (tdep
));
3571 sp
-= align_up (len
, 16);
3574 fprintf_unfiltered (gdb_stdlog
,
3575 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3576 paddr_nz (sp
), (long) align_up (len
, 16));
3578 /* Initialize the integer and float register pointers. */
3580 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3582 /* The struct_return pointer occupies the first parameter-passing reg. */
3586 fprintf_unfiltered (gdb_stdlog
,
3587 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3588 argreg
, paddr_nz (struct_addr
));
3589 write_register (argreg
++, struct_addr
);
3590 stack_offset
+= mips_stack_argsize (tdep
);
3593 /* Now load as many as possible of the first arguments into
3594 registers, and push the rest onto the stack. Loop thru args
3595 from first to last. */
3596 for (argnum
= 0; argnum
< nargs
; argnum
++)
3599 char valbuf
[MAX_REGISTER_SIZE
];
3600 struct value
*arg
= args
[argnum
];
3601 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3602 int len
= TYPE_LENGTH (arg_type
);
3603 enum type_code typecode
= TYPE_CODE (arg_type
);
3606 fprintf_unfiltered (gdb_stdlog
,
3607 "mips_o64_push_dummy_call: %d len=%d type=%d",
3608 argnum
+ 1, len
, (int) typecode
);
3610 val
= (char *) VALUE_CONTENTS (arg
);
3612 /* 32-bit ABIs always start floating point arguments in an
3613 even-numbered floating point register. Round the FP register
3614 up before the check to see if there are any FP registers
3615 left. O32/O64 targets also pass the FP in the integer
3616 registers so also round up normal registers. */
3617 if (!FP_REGISTER_DOUBLE
3618 && fp_register_arg_p (typecode
, arg_type
))
3620 if ((float_argreg
& 1))
3624 /* Floating point arguments passed in registers have to be
3625 treated specially. On 32-bit architectures, doubles
3626 are passed in register pairs; the even register gets
3627 the low word, and the odd register gets the high word.
3628 On O32/O64, the first two floating point arguments are
3629 also copied to general registers, because MIPS16 functions
3630 don't use float registers for arguments. This duplication of
3631 arguments in general registers can't hurt non-MIPS16 functions
3632 because those registers are normally skipped. */
3634 if (fp_register_arg_p (typecode
, arg_type
)
3635 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3637 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3639 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3640 unsigned long regval
;
3642 /* Write the low word of the double to the even register(s). */
3643 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3645 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3646 float_argreg
, phex (regval
, 4));
3647 write_register (float_argreg
++, regval
);
3649 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3650 argreg
, phex (regval
, 4));
3651 write_register (argreg
++, regval
);
3653 /* Write the high word of the double to the odd register(s). */
3654 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3656 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3657 float_argreg
, phex (regval
, 4));
3658 write_register (float_argreg
++, regval
);
3661 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3662 argreg
, phex (regval
, 4));
3663 write_register (argreg
++, regval
);
3667 /* This is a floating point value that fits entirely
3668 in a single register. */
3669 /* On 32 bit ABI's the float_argreg is further adjusted
3670 above to ensure that it is even register aligned. */
3671 LONGEST regval
= extract_unsigned_integer (val
, len
);
3673 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3674 float_argreg
, phex (regval
, len
));
3675 write_register (float_argreg
++, regval
);
3676 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3677 registers for each argument. The below is (my
3678 guess) to ensure that the corresponding integer
3679 register has reserved the same space. */
3681 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3682 argreg
, phex (regval
, len
));
3683 write_register (argreg
, regval
);
3684 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3686 /* Reserve space for the FP register. */
3687 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
3691 /* Copy the argument to general registers or the stack in
3692 register-sized pieces. Large arguments are split between
3693 registers and stack. */
3694 /* Note: structs whose size is not a multiple of
3695 mips_regsize() are treated specially: Irix cc passes them
3696 in registers where gcc sometimes puts them on the stack.
3697 For maximum compatibility, we will put them in both
3699 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3700 && (len
% mips_saved_regsize (tdep
) != 0));
3701 /* Structures should be aligned to eight bytes (even arg registers)
3702 on MIPS_ABI_O32, if their first member has double precision. */
3703 if (mips_saved_regsize (tdep
) < 8
3704 && mips_type_needs_double_align (arg_type
))
3709 /* Note: Floating-point values that didn't fit into an FP
3710 register are only written to memory. */
3713 /* Remember if the argument was written to the stack. */
3714 int stack_used_p
= 0;
3715 int partial_len
= (len
< mips_saved_regsize (tdep
)
3716 ? len
: mips_saved_regsize (tdep
));
3719 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3722 /* Write this portion of the argument to the stack. */
3723 if (argreg
> MIPS_LAST_ARG_REGNUM
3725 || fp_register_arg_p (typecode
, arg_type
))
3727 /* Should shorter than int integer values be
3728 promoted to int before being stored? */
3729 int longword_offset
= 0;
3732 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3734 if (mips_stack_argsize (tdep
) == 8
3735 && (typecode
== TYPE_CODE_INT
3736 || typecode
== TYPE_CODE_PTR
3737 || typecode
== TYPE_CODE_FLT
)
3739 longword_offset
= mips_stack_argsize (tdep
) - len
;
3744 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3745 paddr_nz (stack_offset
));
3746 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3747 paddr_nz (longword_offset
));
3750 addr
= sp
+ stack_offset
+ longword_offset
;
3755 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3757 for (i
= 0; i
< partial_len
; i
++)
3759 fprintf_unfiltered (gdb_stdlog
, "%02x",
3763 write_memory (addr
, val
, partial_len
);
3766 /* Note!!! This is NOT an else clause. Odd sized
3767 structs may go thru BOTH paths. Floating point
3768 arguments will not. */
3769 /* Write this portion of the argument to a general
3770 purpose register. */
3771 if (argreg
<= MIPS_LAST_ARG_REGNUM
3772 && !fp_register_arg_p (typecode
, arg_type
))
3774 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3775 /* Value may need to be sign extended, because
3776 mips_regsize() != mips_saved_regsize(). */
3778 /* A non-floating-point argument being passed in a
3779 general register. If a struct or union, and if
3780 the remaining length is smaller than the register
3781 size, we have to adjust the register value on
3784 It does not seem to be necessary to do the
3785 same for integral types.
3787 Also don't do this adjustment on O64 binaries.
3789 cagney/2001-07-23: gdb/179: Also, GCC, when
3790 outputting LE O32 with sizeof (struct) <
3791 mips_saved_regsize(), generates a left shift as
3792 part of storing the argument in a register a
3793 register (the left shift isn't generated when
3794 sizeof (struct) >= mips_saved_regsize()). Since
3795 it is quite possible that this is GCC
3796 contradicting the LE/O32 ABI, GDB has not been
3797 adjusted to accommodate this. Either someone
3798 needs to demonstrate that the LE/O32 ABI
3799 specifies such a left shift OR this new ABI gets
3800 identified as such and GDB gets tweaked
3803 if (mips_saved_regsize (tdep
) < 8
3804 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3805 && partial_len
< mips_saved_regsize (tdep
)
3806 && (typecode
== TYPE_CODE_STRUCT
||
3807 typecode
== TYPE_CODE_UNION
))
3808 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3812 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3814 phex (regval
, mips_saved_regsize (tdep
)));
3815 write_register (argreg
, regval
);
3818 /* Prevent subsequent floating point arguments from
3819 being passed in floating point registers. */
3820 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3826 /* Compute the the offset into the stack at which we
3827 will copy the next parameter.
3829 In older ABIs, the caller reserved space for
3830 registers that contained arguments. This was loosely
3831 refered to as their "home". Consequently, space is
3832 always allocated. */
3834 stack_offset
+= align_up (partial_len
,
3835 mips_stack_argsize (tdep
));
3839 fprintf_unfiltered (gdb_stdlog
, "\n");
3842 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3844 /* Return adjusted stack pointer. */
3849 mips_pop_frame (void)
3852 struct frame_info
*frame
= get_current_frame ();
3853 CORE_ADDR new_sp
= get_frame_base (frame
);
3854 mips_extra_func_info_t proc_desc
;
3855 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3857 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
3859 generic_pop_dummy_frame ();
3860 flush_cached_frames ();
3864 proc_desc
= get_frame_extra_info (frame
)->proc_desc
;
3865 write_register (PC_REGNUM
, DEPRECATED_FRAME_SAVED_PC (frame
));
3866 mips_find_saved_regs (frame
);
3867 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
3868 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
3869 && deprecated_get_frame_saved_regs (frame
)[regnum
])
3871 /* Floating point registers must not be sign extended, in case
3872 mips_saved_regsize() = 4 but sizeof (FP0_REGNUM) == 8. */
3874 if (mips_regnum (current_gdbarch
)->fp0
<= regnum
&& regnum
< mips_regnum (current_gdbarch
)->fp0
+ 32)
3875 write_register (regnum
,
3876 read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3877 mips_saved_regsize (tdep
)));
3879 write_register (regnum
,
3880 read_memory_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3881 mips_saved_regsize (tdep
)));
3884 write_register (SP_REGNUM
, new_sp
);
3885 flush_cached_frames ();
3887 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
3889 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
3891 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
3893 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
3895 if (&pi_ptr
->info
== proc_desc
)
3900 error ("Can't locate dummy extra frame info\n");
3902 if (prev_ptr
!= NULL
)
3903 prev_ptr
->next
= pi_ptr
->next
;
3905 linked_proc_desc_table
= pi_ptr
->next
;
3909 write_register (mips_regnum (current_gdbarch
)->hi
,
3910 read_memory_integer ((new_sp
3911 - 2 * mips_saved_regsize (tdep
)),
3912 mips_saved_regsize (tdep
)));
3913 write_register (mips_regnum (current_gdbarch
)->lo
,
3914 read_memory_integer ((new_sp
3915 - 3 * mips_saved_regsize (tdep
)),
3916 mips_saved_regsize (tdep
)));
3917 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
3918 write_register (mips_regnum (current_gdbarch
)->fp_control_status
,
3919 read_memory_integer ((new_sp
3920 - 4 * mips_saved_regsize (tdep
)),
3921 mips_saved_regsize (tdep
)));
3925 /* Floating point register management.
3927 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3928 64bit operations, these early MIPS cpus treat fp register pairs
3929 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3930 registers and offer a compatibility mode that emulates the MIPS2 fp
3931 model. When operating in MIPS2 fp compat mode, later cpu's split
3932 double precision floats into two 32-bit chunks and store them in
3933 consecutive fp regs. To display 64-bit floats stored in this
3934 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3935 Throw in user-configurable endianness and you have a real mess.
3937 The way this works is:
3938 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3939 double-precision value will be split across two logical registers.
3940 The lower-numbered logical register will hold the low-order bits,
3941 regardless of the processor's endianness.
3942 - If we are on a 64-bit processor, and we are looking for a
3943 single-precision value, it will be in the low ordered bits
3944 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3945 save slot in memory.
3946 - If we are in 64-bit mode, everything is straightforward.
3948 Note that this code only deals with "live" registers at the top of the
3949 stack. We will attempt to deal with saved registers later, when
3950 the raw/cooked register interface is in place. (We need a general
3951 interface that can deal with dynamic saved register sizes -- fp
3952 regs could be 32 bits wide in one frame and 64 on the frame above
3955 static struct type
*
3956 mips_float_register_type (void)
3958 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3959 return builtin_type_ieee_single_big
;
3961 return builtin_type_ieee_single_little
;
3964 static struct type
*
3965 mips_double_register_type (void)
3967 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3968 return builtin_type_ieee_double_big
;
3970 return builtin_type_ieee_double_little
;
3973 /* Copy a 32-bit single-precision value from the current frame
3974 into rare_buffer. */
3977 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3980 int raw_size
= register_size (current_gdbarch
, regno
);
3981 char *raw_buffer
= alloca (raw_size
);
3983 if (!frame_register_read (frame
, regno
, raw_buffer
))
3984 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3987 /* We have a 64-bit value for this register. Find the low-order
3991 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3996 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4000 memcpy (rare_buffer
, raw_buffer
, 4);
4004 /* Copy a 64-bit double-precision value from the current frame into
4005 rare_buffer. This may include getting half of it from the next
4009 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4012 int raw_size
= register_size (current_gdbarch
, regno
);
4014 if (raw_size
== 8 && !mips2_fp_compat ())
4016 /* We have a 64-bit value for this register, and we should use
4018 if (!frame_register_read (frame
, regno
, rare_buffer
))
4019 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4023 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4024 internal_error (__FILE__
, __LINE__
,
4025 "mips_read_fp_register_double: bad access to "
4026 "odd-numbered FP register");
4028 /* mips_read_fp_register_single will find the correct 32 bits from
4030 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4032 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4033 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4037 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4038 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4044 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4046 { /* do values for FP (float) regs */
4048 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
4049 int inv1
, inv2
, namelen
;
4051 raw_buffer
= (char *) alloca (2 * register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
));
4053 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4054 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4057 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4059 /* 4-byte registers: Print hex and floating. Also print even
4060 numbered registers as doubles. */
4061 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4062 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4064 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w', file
);
4066 fprintf_filtered (file
, " flt: ");
4068 fprintf_filtered (file
, " <invalid float> ");
4070 fprintf_filtered (file
, "%-17.9g", flt1
);
4072 if (regnum
% 2 == 0)
4074 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4075 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4078 fprintf_filtered (file
, " dbl: ");
4080 fprintf_filtered (file
, "<invalid double>");
4082 fprintf_filtered (file
, "%-24.17g", doub
);
4087 /* Eight byte registers: print each one as hex, float and double. */
4088 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4089 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4091 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4092 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4095 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g', file
);
4097 fprintf_filtered (file
, " flt: ");
4099 fprintf_filtered (file
, "<invalid float>");
4101 fprintf_filtered (file
, "%-17.9g", flt1
);
4103 fprintf_filtered (file
, " dbl: ");
4105 fprintf_filtered (file
, "<invalid double>");
4107 fprintf_filtered (file
, "%-24.17g", doub
);
4112 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4113 int regnum
, int all
)
4115 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4116 char raw_buffer
[MAX_REGISTER_SIZE
];
4119 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4121 mips_print_fp_register (file
, frame
, regnum
);
4125 /* Get the data in raw format. */
4126 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4128 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4132 fputs_filtered (REGISTER_NAME (regnum
), file
);
4134 /* The problem with printing numeric register names (r26, etc.) is that
4135 the user can't use them on input. Probably the best solution is to
4136 fix it so that either the numeric or the funky (a2, etc.) names
4137 are accepted on input. */
4138 if (regnum
< MIPS_NUMREGS
)
4139 fprintf_filtered (file
, "(r%d): ", regnum
);
4141 fprintf_filtered (file
, ": ");
4143 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4144 offset
= register_size (current_gdbarch
, regnum
) - register_size (current_gdbarch
, regnum
);
4148 print_scalar_formatted (raw_buffer
+ offset
, gdbarch_register_type (gdbarch
, regnum
),
4152 /* Replacement for generic do_registers_info.
4153 Print regs in pretty columns. */
4156 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4159 fprintf_filtered (file
, " ");
4160 mips_print_fp_register (file
, frame
, regnum
);
4161 fprintf_filtered (file
, "\n");
4166 /* Print a row's worth of GP (int) registers, with name labels above */
4169 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4172 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4173 /* do values for GP (int) regs */
4174 char raw_buffer
[MAX_REGISTER_SIZE
];
4175 int ncols
= (mips_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4179 /* For GP registers, we print a separate row of names above the vals */
4180 fprintf_filtered (file
, " ");
4181 for (col
= 0, regnum
= start_regnum
;
4182 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4185 if (*REGISTER_NAME (regnum
) == '\0')
4186 continue; /* unused register */
4187 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4188 break; /* end the row: reached FP register */
4189 fprintf_filtered (file
, mips_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4190 REGISTER_NAME (regnum
));
4193 /* print the R0 to R31 names */
4194 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4195 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4197 fprintf_filtered (file
, "\n ");
4199 /* now print the values in hex, 4 or 8 to the row */
4200 for (col
= 0, regnum
= start_regnum
;
4201 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4204 if (*REGISTER_NAME (regnum
) == '\0')
4205 continue; /* unused register */
4206 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4207 break; /* end row: reached FP register */
4208 /* OK: get the data in raw format. */
4209 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4210 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4211 /* pad small registers */
4213 byte
< (mips_regsize (current_gdbarch
)
4214 - register_size (current_gdbarch
, regnum
));
4216 printf_filtered (" ");
4217 /* Now print the register value in hex, endian order. */
4218 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4219 for (byte
= register_size (current_gdbarch
, regnum
) - register_size (current_gdbarch
, regnum
);
4220 byte
< register_size (current_gdbarch
, regnum
);
4222 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4224 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4227 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4228 fprintf_filtered (file
, " ");
4231 if (col
> 0) /* ie. if we actually printed anything... */
4232 fprintf_filtered (file
, "\n");
4237 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4240 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4241 struct frame_info
*frame
, int regnum
, int all
)
4243 if (regnum
!= -1) /* do one specified register */
4245 gdb_assert (regnum
>= NUM_REGS
);
4246 if (*(REGISTER_NAME (regnum
)) == '\0')
4247 error ("Not a valid register for the current processor type");
4249 mips_print_register (file
, frame
, regnum
, 0);
4250 fprintf_filtered (file
, "\n");
4253 /* do all (or most) registers */
4256 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4258 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4260 if (all
) /* true for "INFO ALL-REGISTERS" command */
4261 regnum
= print_fp_register_row (file
, frame
, regnum
);
4263 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4266 regnum
= print_gp_register_row (file
, frame
, regnum
);
4271 /* Is this a branch with a delay slot? */
4273 static int is_delayed (unsigned long);
4276 is_delayed (unsigned long insn
)
4279 for (i
= 0; i
< NUMOPCODES
; ++i
)
4280 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4281 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4283 return (i
< NUMOPCODES
4284 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4285 | INSN_COND_BRANCH_DELAY
4286 | INSN_COND_BRANCH_LIKELY
)));
4290 mips_step_skips_delay (CORE_ADDR pc
)
4292 char buf
[MIPS_INSTLEN
];
4294 /* There is no branch delay slot on MIPS16. */
4295 if (pc_is_mips16 (pc
))
4298 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4299 /* If error reading memory, guess that it is not a delayed branch. */
4301 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4305 /* Given PC at the function's start address, attempt to find the
4306 prologue end using SAL information. Return zero if the skip fails.
4308 A non-optimized prologue traditionally has one SAL for the function
4309 and a second for the function body. A single line function has
4310 them both pointing at the same line.
4312 An optimized prologue is similar but the prologue may contain
4313 instructions (SALs) from the instruction body. Need to skip those
4314 while not getting into the function body.
4316 The functions end point and an increasing SAL line are used as
4317 indicators of the prologue's endpoint.
4319 This code is based on the function refine_prologue_limit (versions
4320 found in both ia64 and ppc). */
4323 skip_prologue_using_sal (CORE_ADDR func_addr
)
4325 struct symtab_and_line prologue_sal
;
4329 /* Get an initial range for the function. */
4330 find_pc_partial_function (func_addr
, NULL
, &start_pc
, &end_pc
);
4331 start_pc
+= FUNCTION_START_OFFSET
;
4333 prologue_sal
= find_pc_line (start_pc
, 0);
4334 if (prologue_sal
.line
!= 0)
4336 while (prologue_sal
.end
< end_pc
)
4338 struct symtab_and_line sal
;
4340 sal
= find_pc_line (prologue_sal
.end
, 0);
4343 /* Assume that a consecutive SAL for the same (or larger)
4344 line mark the prologue -> body transition. */
4345 if (sal
.line
>= prologue_sal
.line
)
4347 /* The case in which compiler's optimizer/scheduler has
4348 moved instructions into the prologue. We look ahead in
4349 the function looking for address ranges whose
4350 corresponding line number is less the first one that we
4351 found for the function. This is more conservative then
4352 refine_prologue_limit which scans a large number of SALs
4353 looking for any in the prologue */
4357 return prologue_sal
.end
;
4360 /* Skip the PC past function prologue instructions (32-bit version).
4361 This is a helper function for mips_skip_prologue. */
4364 mips32_skip_prologue (CORE_ADDR pc
)
4368 int seen_sp_adjust
= 0;
4369 int load_immediate_bytes
= 0;
4371 /* Find an upper bound on the prologue. */
4372 end_pc
= skip_prologue_using_sal (pc
);
4374 end_pc
= pc
+ 100; /* Magic. */
4376 /* Skip the typical prologue instructions. These are the stack adjustment
4377 instruction and the instructions that save registers on the stack
4378 or in the gcc frame. */
4379 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4381 unsigned long high_word
;
4383 inst
= mips_fetch_instruction (pc
);
4384 high_word
= (inst
>> 16) & 0xffff;
4386 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4387 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4389 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4390 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4392 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4393 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4394 && (inst
& 0x001F0000)) /* reg != $zero */
4397 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4399 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4401 continue; /* reg != $zero */
4403 /* move $s8,$sp. With different versions of gas this will be either
4404 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4405 Accept any one of these. */
4406 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4409 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4411 else if (high_word
== 0x3c1c) /* lui $gp,n */
4413 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4415 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4416 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4418 /* The following instructions load $at or $t0 with an immediate
4419 value in preparation for a stack adjustment via
4420 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4421 a local variable, so we accept them only before a stack adjustment
4422 instruction was seen. */
4423 else if (!seen_sp_adjust
)
4425 if (high_word
== 0x3c01 || /* lui $at,n */
4426 high_word
== 0x3c08) /* lui $t0,n */
4428 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4431 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4432 high_word
== 0x3508 || /* ori $t0,$t0,n */
4433 high_word
== 0x3401 || /* ori $at,$zero,n */
4434 high_word
== 0x3408) /* ori $t0,$zero,n */
4436 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4446 /* In a frameless function, we might have incorrectly
4447 skipped some load immediate instructions. Undo the skipping
4448 if the load immediate was not followed by a stack adjustment. */
4449 if (load_immediate_bytes
&& !seen_sp_adjust
)
4450 pc
-= load_immediate_bytes
;
4454 /* Skip the PC past function prologue instructions (16-bit version).
4455 This is a helper function for mips_skip_prologue. */
4458 mips16_skip_prologue (CORE_ADDR pc
)
4461 int extend_bytes
= 0;
4462 int prev_extend_bytes
;
4464 /* Table of instructions likely to be found in a function prologue. */
4467 unsigned short inst
;
4468 unsigned short mask
;
4475 , /* addiu $sp,offset */
4479 , /* daddiu $sp,offset */
4483 , /* sw reg,n($sp) */
4487 , /* sd reg,n($sp) */
4491 , /* sw $ra,n($sp) */
4495 , /* sd $ra,n($sp) */
4503 , /* sw $a0-$a3,n($s1) */
4507 , /* move reg,$a0-$a3 */
4511 , /* entry pseudo-op */
4515 , /* addiu $s1,$sp,n */
4518 } /* end of table marker */
4521 /* Find an upper bound on the prologue. */
4522 end_pc
= skip_prologue_using_sal (pc
);
4524 end_pc
= pc
+ 100; /* Magic. */
4526 /* Skip the typical prologue instructions. These are the stack adjustment
4527 instruction and the instructions that save registers on the stack
4528 or in the gcc frame. */
4529 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4531 unsigned short inst
;
4534 inst
= mips_fetch_instruction (pc
);
4536 /* Normally we ignore an extend instruction. However, if it is
4537 not followed by a valid prologue instruction, we must adjust
4538 the pc back over the extend so that it won't be considered
4539 part of the prologue. */
4540 if ((inst
& 0xf800) == 0xf000) /* extend */
4542 extend_bytes
= MIPS16_INSTLEN
;
4545 prev_extend_bytes
= extend_bytes
;
4548 /* Check for other valid prologue instructions besides extend. */
4549 for (i
= 0; table
[i
].mask
!= 0; i
++)
4550 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4552 if (table
[i
].mask
!= 0) /* it was in table? */
4553 continue; /* ignore it */
4557 /* Return the current pc, adjusted backwards by 2 if
4558 the previous instruction was an extend. */
4559 return pc
- prev_extend_bytes
;
4565 /* To skip prologues, I use this predicate. Returns either PC itself
4566 if the code at PC does not look like a function prologue; otherwise
4567 returns an address that (if we're lucky) follows the prologue. If
4568 LENIENT, then we must skip everything which is involved in setting
4569 up the frame (it's OK to skip more, just so long as we don't skip
4570 anything which might clobber the registers which are being saved.
4571 We must skip more in the case where part of the prologue is in the
4572 delay slot of a non-prologue instruction). */
4575 mips_skip_prologue (CORE_ADDR pc
)
4577 /* See if we can determine the end of the prologue via the symbol table.
4578 If so, then return either PC, or the PC after the prologue, whichever
4581 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4583 if (post_prologue_pc
!= 0)
4584 return max (pc
, post_prologue_pc
);
4586 /* Can't determine prologue from the symbol table, need to examine
4589 if (pc_is_mips16 (pc
))
4590 return mips16_skip_prologue (pc
);
4592 return mips32_skip_prologue (pc
);
4595 /* Determine how a return value is stored within the MIPS register
4596 file, given the return type `valtype'. */
4598 struct return_value_word
4607 return_value_location (struct type
*valtype
,
4608 struct return_value_word
*hi
,
4609 struct return_value_word
*lo
)
4611 int len
= TYPE_LENGTH (valtype
);
4612 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4614 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
4615 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
4616 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
4618 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4620 /* We need to break a 64bit float in two 32 bit halves and
4621 spread them across a floating-point register pair. */
4622 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4623 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
4624 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4625 && register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 8)
4627 hi
->reg_offset
= lo
->reg_offset
;
4628 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
4629 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
4635 /* The floating point value fits in a single floating-point
4637 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4638 && register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) == 8
4641 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
4652 /* Locate a result possibly spread across two registers. */
4654 lo
->reg
= regnum
+ 0;
4655 hi
->reg
= regnum
+ 1;
4656 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4657 && len
< mips_saved_regsize (tdep
))
4659 /* "un-left-justify" the value in the low register */
4660 lo
->reg_offset
= mips_saved_regsize (tdep
) - len
;
4665 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4666 && len
> mips_saved_regsize (tdep
) /* odd-size structs */
4667 && len
< mips_saved_regsize (tdep
) * 2
4668 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
4669 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
4671 /* "un-left-justify" the value spread across two registers. */
4672 lo
->reg_offset
= 2 * mips_saved_regsize (tdep
) - len
;
4673 lo
->len
= mips_saved_regsize (tdep
) - lo
->reg_offset
;
4675 hi
->len
= len
- lo
->len
;
4679 /* Only perform a partial copy of the second register. */
4682 if (len
> mips_saved_regsize (tdep
))
4684 lo
->len
= mips_saved_regsize (tdep
);
4685 hi
->len
= len
- mips_saved_regsize (tdep
);
4693 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4694 && register_size (current_gdbarch
, regnum
) == 8
4695 && mips_saved_regsize (tdep
) == 4)
4697 /* Account for the fact that only the least-signficant part
4698 of the register is being used */
4699 lo
->reg_offset
+= 4;
4700 hi
->reg_offset
+= 4;
4703 hi
->buf_offset
= lo
->len
;
4707 /* Given a return value in `regbuf' with a type `valtype', extract and
4708 copy its value into `valbuf'. */
4711 mips_eabi_extract_return_value (struct type
*valtype
,
4715 struct return_value_word lo
;
4716 struct return_value_word hi
;
4717 return_value_location (valtype
, &hi
, &lo
);
4719 memcpy (valbuf
+ lo
.buf_offset
,
4720 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) + lo
.reg_offset
,
4724 memcpy (valbuf
+ hi
.buf_offset
,
4725 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) + hi
.reg_offset
,
4730 mips_o64_extract_return_value (struct type
*valtype
,
4734 struct return_value_word lo
;
4735 struct return_value_word hi
;
4736 return_value_location (valtype
, &hi
, &lo
);
4738 memcpy (valbuf
+ lo
.buf_offset
,
4739 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) + lo
.reg_offset
,
4743 memcpy (valbuf
+ hi
.buf_offset
,
4744 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) + hi
.reg_offset
,
4748 /* Given a return value in `valbuf' with a type `valtype', write it's
4749 value into the appropriate register. */
4752 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
4754 char raw_buffer
[MAX_REGISTER_SIZE
];
4755 struct return_value_word lo
;
4756 struct return_value_word hi
;
4757 return_value_location (valtype
, &hi
, &lo
);
4759 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4760 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4761 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4762 register_size (current_gdbarch
, lo
.reg
));
4766 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4767 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4768 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4769 register_size (current_gdbarch
, hi
.reg
));
4774 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4776 char raw_buffer
[MAX_REGISTER_SIZE
];
4777 struct return_value_word lo
;
4778 struct return_value_word hi
;
4779 return_value_location (valtype
, &hi
, &lo
);
4781 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4782 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4783 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4784 register_size (current_gdbarch
, lo
.reg
));
4788 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4789 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4790 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4791 register_size (current_gdbarch
, hi
.reg
));
4795 /* O32 ABI stuff. */
4797 static enum return_value_convention
4798 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4799 struct regcache
*regcache
,
4800 void *readbuf
, const void *writebuf
)
4802 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4804 if (TYPE_CODE (type
)== TYPE_CODE_STRUCT
4805 || TYPE_CODE (type
)== TYPE_CODE_UNION
4806 || TYPE_CODE (type
)== TYPE_CODE_ARRAY
)
4807 return RETURN_VALUE_STRUCT_CONVENTION
;
4808 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4809 && TYPE_LENGTH (type
) == 4
4810 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4812 /* A single-precision floating-point value. It fits in the
4813 least significant part of FP0. */
4815 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4816 mips_xfer_register (regcache
,
4817 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4819 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4820 return RETURN_VALUE_REGISTER_CONVENTION
;
4822 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4823 && TYPE_LENGTH (type
) == 8
4824 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4826 /* A double-precision floating-point value. The most
4827 significant part goes in FP1, and the least significant in
4830 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4831 switch (TARGET_BYTE_ORDER
)
4833 case BFD_ENDIAN_LITTLE
:
4834 mips_xfer_register (regcache
,
4835 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 0,
4836 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4837 mips_xfer_register (regcache
,
4838 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 1,
4839 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4841 case BFD_ENDIAN_BIG
:
4842 mips_xfer_register (regcache
,
4843 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 1,
4844 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4845 mips_xfer_register (regcache
,
4846 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 0,
4847 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4850 internal_error (__FILE__
, __LINE__
, "bad switch");
4852 return RETURN_VALUE_REGISTER_CONVENTION
;
4855 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4856 && TYPE_NFIELDS (type
) <= 2
4857 && TYPE_NFIELDS (type
) >= 1
4858 && ((TYPE_NFIELDS (type
) == 1
4859 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4861 || (TYPE_NFIELDS (type
) == 2
4862 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4864 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4866 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4868 /* A struct that contains one or two floats. Each value is part
4869 in the least significant part of their floating point
4871 bfd_byte reg
[MAX_REGISTER_SIZE
];
4874 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4875 field
< TYPE_NFIELDS (type
);
4876 field
++, regnum
+= 2)
4878 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4881 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4882 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4883 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4884 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4886 return RETURN_VALUE_REGISTER_CONVENTION
;
4890 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4891 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4893 /* A structure or union. Extract the left justified value,
4894 regardless of the byte order. I.e. DO NOT USE
4898 for (offset
= 0, regnum
= V0_REGNUM
;
4899 offset
< TYPE_LENGTH (type
);
4900 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4902 int xfer
= register_size (current_gdbarch
, regnum
);
4903 if (offset
+ xfer
> TYPE_LENGTH (type
))
4904 xfer
= TYPE_LENGTH (type
) - offset
;
4906 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4907 offset
, xfer
, regnum
);
4908 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4909 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4911 return RETURN_VALUE_REGISTER_CONVENTION
;
4916 /* A scalar extract each part but least-significant-byte
4917 justified. o32 thinks registers are 4 byte, regardless of
4918 the ISA. mips_stack_argsize controls this. */
4921 for (offset
= 0, regnum
= V0_REGNUM
;
4922 offset
< TYPE_LENGTH (type
);
4923 offset
+= mips_stack_argsize (tdep
), regnum
++)
4925 int xfer
= mips_stack_argsize (tdep
);
4927 if (offset
+ xfer
> TYPE_LENGTH (type
))
4928 xfer
= TYPE_LENGTH (type
) - offset
;
4930 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4931 offset
, xfer
, regnum
);
4932 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4933 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4935 return RETURN_VALUE_REGISTER_CONVENTION
;
4939 /* N32/N44 ABI stuff. */
4941 static enum return_value_convention
4942 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
4943 struct type
*type
, struct regcache
*regcache
,
4944 void *readbuf
, const void *writebuf
)
4946 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4947 if (TYPE_CODE (type
)== TYPE_CODE_STRUCT
4948 || TYPE_CODE (type
)== TYPE_CODE_UNION
4949 || TYPE_CODE (type
)== TYPE_CODE_ARRAY
4950 || TYPE_LENGTH (type
) > 2 * mips_saved_regsize (tdep
))
4951 return RETURN_VALUE_STRUCT_CONVENTION
;
4952 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4953 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4955 /* A floating-point value belongs in the least significant part
4958 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4959 mips_xfer_register (regcache
,
4960 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4962 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4963 return RETURN_VALUE_REGISTER_CONVENTION
;
4965 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4966 && TYPE_NFIELDS (type
) <= 2
4967 && TYPE_NFIELDS (type
) >= 1
4968 && ((TYPE_NFIELDS (type
) == 1
4969 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4971 || (TYPE_NFIELDS (type
) == 2
4972 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4974 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4976 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4978 /* A struct that contains one or two floats. Each value is part
4979 in the least significant part of their floating point
4981 bfd_byte reg
[MAX_REGISTER_SIZE
];
4984 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4985 field
< TYPE_NFIELDS (type
);
4986 field
++, regnum
+= 2)
4988 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4991 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4992 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4993 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4994 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4996 return RETURN_VALUE_REGISTER_CONVENTION
;
4998 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4999 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5001 /* A structure or union. Extract the left justified value,
5002 regardless of the byte order. I.e. DO NOT USE
5006 for (offset
= 0, regnum
= V0_REGNUM
;
5007 offset
< TYPE_LENGTH (type
);
5008 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
5010 int xfer
= register_size (current_gdbarch
, regnum
);
5011 if (offset
+ xfer
> TYPE_LENGTH (type
))
5012 xfer
= TYPE_LENGTH (type
) - offset
;
5014 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5015 offset
, xfer
, regnum
);
5016 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
5017 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5019 return RETURN_VALUE_REGISTER_CONVENTION
;
5023 /* A scalar extract each part but least-significant-byte
5027 for (offset
= 0, regnum
= V0_REGNUM
;
5028 offset
< TYPE_LENGTH (type
);
5029 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
5031 int xfer
= register_size (current_gdbarch
, regnum
);
5033 if (offset
+ xfer
> TYPE_LENGTH (type
))
5034 xfer
= TYPE_LENGTH (type
) - offset
;
5036 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5037 offset
, xfer
, regnum
);
5038 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
5039 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
5041 return RETURN_VALUE_REGISTER_CONVENTION
;
5046 mips_extract_struct_value_address (struct regcache
*regcache
)
5048 /* FIXME: This will only work at random. The caller passes the
5049 struct_return address in V0, but it is not preserved. It may
5050 still be there, or this may be a random value. */
5053 regcache_cooked_read_signed (regcache
, V0_REGNUM
, &val
);
5057 /* Exported procedure: Is PC in the signal trampoline code */
5060 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
5062 if (sigtramp_address
== 0)
5064 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
5067 /* Root of all "set mips "/"show mips " commands. This will eventually be
5068 used for all MIPS-specific commands. */
5071 show_mips_command (char *args
, int from_tty
)
5073 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5077 set_mips_command (char *args
, int from_tty
)
5079 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
5080 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5083 /* Commands to show/set the MIPS FPU type. */
5086 show_mipsfpu_command (char *args
, int from_tty
)
5089 switch (MIPS_FPU_TYPE
)
5091 case MIPS_FPU_SINGLE
:
5092 fpu
= "single-precision";
5094 case MIPS_FPU_DOUBLE
:
5095 fpu
= "double-precision";
5098 fpu
= "absent (none)";
5101 internal_error (__FILE__
, __LINE__
, "bad switch");
5103 if (mips_fpu_type_auto
)
5104 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5107 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
5113 set_mipsfpu_command (char *args
, int from_tty
)
5115 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5116 show_mipsfpu_command (args
, from_tty
);
5120 set_mipsfpu_single_command (char *args
, int from_tty
)
5122 struct gdbarch_info info
;
5123 gdbarch_info_init (&info
);
5124 mips_fpu_type
= MIPS_FPU_SINGLE
;
5125 mips_fpu_type_auto
= 0;
5126 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5127 instead of relying on globals. Doing that would let generic code
5128 handle the search for this specific architecture. */
5129 if (!gdbarch_update_p (info
))
5130 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5134 set_mipsfpu_double_command (char *args
, int from_tty
)
5136 struct gdbarch_info info
;
5137 gdbarch_info_init (&info
);
5138 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5139 mips_fpu_type_auto
= 0;
5140 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5141 instead of relying on globals. Doing that would let generic code
5142 handle the search for this specific architecture. */
5143 if (!gdbarch_update_p (info
))
5144 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5148 set_mipsfpu_none_command (char *args
, int from_tty
)
5150 struct gdbarch_info info
;
5151 gdbarch_info_init (&info
);
5152 mips_fpu_type
= MIPS_FPU_NONE
;
5153 mips_fpu_type_auto
= 0;
5154 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5155 instead of relying on globals. Doing that would let generic code
5156 handle the search for this specific architecture. */
5157 if (!gdbarch_update_p (info
))
5158 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5162 set_mipsfpu_auto_command (char *args
, int from_tty
)
5164 mips_fpu_type_auto
= 1;
5167 /* Attempt to identify the particular processor model by reading the
5168 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5169 the relevant processor still exists (it dates back to '94) and
5170 secondly this is not the way to do this. The processor type should
5171 be set by forcing an architecture change. */
5174 deprecated_mips_set_processor_regs_hack (void)
5176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5179 prid
= read_register (PRID_REGNUM
);
5181 if ((prid
& ~0xf) == 0x700)
5182 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5185 /* Just like reinit_frame_cache, but with the right arguments to be
5186 callable as an sfunc. */
5189 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5190 struct cmd_list_element
*c
)
5192 reinit_frame_cache ();
5196 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5198 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5199 mips_extra_func_info_t proc_desc
;
5201 /* Search for the function containing this address. Set the low bit
5202 of the address when searching, in case we were given an even address
5203 that is the start of a 16-bit function. If we didn't do this,
5204 the search would fail because the symbol table says the function
5205 starts at an odd address, i.e. 1 byte past the given address. */
5206 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5207 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5209 /* Make an attempt to determine if this is a 16-bit function. If
5210 the procedure descriptor exists and the address therein is odd,
5211 it's definitely a 16-bit function. Otherwise, we have to just
5212 guess that if the address passed in is odd, it's 16-bits. */
5213 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5214 disassembler needs to be able to locally determine the ISA, and
5215 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5219 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5220 info
->mach
= bfd_mach_mips16
;
5224 if (pc_is_mips16 (memaddr
))
5225 info
->mach
= bfd_mach_mips16
;
5228 /* Round down the instruction address to the appropriate boundary. */
5229 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5231 /* Set the disassembler options. */
5232 if (tdep
->mips_abi
== MIPS_ABI_N32
5233 || tdep
->mips_abi
== MIPS_ABI_N64
)
5235 /* Set up the disassembler info, so that we get the right
5236 register names from libopcodes. */
5237 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5238 info
->disassembler_options
= "gpr-names=n32";
5240 info
->disassembler_options
= "gpr-names=64";
5241 info
->flavour
= bfd_target_elf_flavour
;
5244 /* This string is not recognized explicitly by the disassembler,
5245 but it tells the disassembler to not try to guess the ABI from
5246 the bfd elf headers, such that, if the user overrides the ABI
5247 of a program linked as NewABI, the disassembly will follow the
5248 register naming conventions specified by the user. */
5249 info
->disassembler_options
= "gpr-names=32";
5251 /* Call the appropriate disassembler based on the target endian-ness. */
5252 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5253 return print_insn_big_mips (memaddr
, info
);
5255 return print_insn_little_mips (memaddr
, info
);
5258 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5259 counter value to determine whether a 16- or 32-bit breakpoint should be
5260 used. It returns a pointer to a string of bytes that encode a breakpoint
5261 instruction, stores the length of the string to *lenptr, and adjusts pc
5262 (if necessary) to point to the actual memory location where the
5263 breakpoint should be inserted. */
5265 static const unsigned char *
5266 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
5268 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5270 if (pc_is_mips16 (*pcptr
))
5272 static unsigned char mips16_big_breakpoint
[] = {0xe8, 0xa5};
5273 *pcptr
= unmake_mips16_addr (*pcptr
);
5274 *lenptr
= sizeof (mips16_big_breakpoint
);
5275 return mips16_big_breakpoint
;
5279 /* The IDT board uses an unusual breakpoint value, and
5280 sometimes gets confused when it sees the usual MIPS
5281 breakpoint instruction. */
5282 static unsigned char big_breakpoint
[] = {0, 0x5, 0, 0xd};
5283 static unsigned char pmon_big_breakpoint
[] = {0, 0, 0, 0xd};
5284 static unsigned char idt_big_breakpoint
[] = {0, 0, 0x0a, 0xd};
5286 *lenptr
= sizeof (big_breakpoint
);
5288 if (strcmp (target_shortname
, "mips") == 0)
5289 return idt_big_breakpoint
;
5290 else if (strcmp (target_shortname
, "ddb") == 0
5291 || strcmp (target_shortname
, "pmon") == 0
5292 || strcmp (target_shortname
, "lsi") == 0)
5293 return pmon_big_breakpoint
;
5295 return big_breakpoint
;
5300 if (pc_is_mips16 (*pcptr
))
5302 static unsigned char mips16_little_breakpoint
[] = {0xa5, 0xe8};
5303 *pcptr
= unmake_mips16_addr (*pcptr
);
5304 *lenptr
= sizeof (mips16_little_breakpoint
);
5305 return mips16_little_breakpoint
;
5309 static unsigned char little_breakpoint
[] = {0xd, 0, 0x5, 0};
5310 static unsigned char pmon_little_breakpoint
[] = {0xd, 0, 0, 0};
5311 static unsigned char idt_little_breakpoint
[] = {0xd, 0x0a, 0, 0};
5313 *lenptr
= sizeof (little_breakpoint
);
5315 if (strcmp (target_shortname
, "mips") == 0)
5316 return idt_little_breakpoint
;
5317 else if (strcmp (target_shortname
, "ddb") == 0
5318 || strcmp (target_shortname
, "pmon") == 0
5319 || strcmp (target_shortname
, "lsi") == 0)
5320 return pmon_little_breakpoint
;
5322 return little_breakpoint
;
5327 /* If PC is in a mips16 call or return stub, return the address of the target
5328 PC, which is either the callee or the caller. There are several
5329 cases which must be handled:
5331 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5332 target PC is in $31 ($ra).
5333 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5334 and the target PC is in $2.
5335 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5336 before the jal instruction, this is effectively a call stub
5337 and the the target PC is in $2. Otherwise this is effectively
5338 a return stub and the target PC is in $18.
5340 See the source code for the stubs in gcc/config/mips/mips16.S for
5343 This function implements the SKIP_TRAMPOLINE_CODE macro.
5347 mips_skip_stub (CORE_ADDR pc
)
5350 CORE_ADDR start_addr
;
5352 /* Find the starting address and name of the function containing the PC. */
5353 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5356 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5357 target PC is in $31 ($ra). */
5358 if (strcmp (name
, "__mips16_ret_sf") == 0
5359 || strcmp (name
, "__mips16_ret_df") == 0)
5360 return read_signed_register (RA_REGNUM
);
5362 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5364 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5365 and the target PC is in $2. */
5366 if (name
[19] >= '0' && name
[19] <= '9')
5367 return read_signed_register (2);
5369 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5370 before the jal instruction, this is effectively a call stub
5371 and the the target PC is in $2. Otherwise this is effectively
5372 a return stub and the target PC is in $18. */
5373 else if (name
[19] == 's' || name
[19] == 'd')
5375 if (pc
== start_addr
)
5377 /* Check if the target of the stub is a compiler-generated
5378 stub. Such a stub for a function bar might have a name
5379 like __fn_stub_bar, and might look like this:
5384 la $1,bar (becomes a lui/addiu pair)
5386 So scan down to the lui/addi and extract the target
5387 address from those two instructions. */
5389 CORE_ADDR target_pc
= read_signed_register (2);
5393 /* See if the name of the target function is __fn_stub_*. */
5394 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
5396 if (strncmp (name
, "__fn_stub_", 10) != 0
5397 && strcmp (name
, "etext") != 0
5398 && strcmp (name
, "_etext") != 0)
5401 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5402 The limit on the search is arbitrarily set to 20
5403 instructions. FIXME. */
5404 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5406 inst
= mips_fetch_instruction (target_pc
);
5407 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5408 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5409 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5410 return pc
| (inst
& 0xffff); /* low word */
5413 /* Couldn't find the lui/addui pair, so return stub address. */
5417 /* This is the 'return' part of a call stub. The return
5418 address is in $r18. */
5419 return read_signed_register (18);
5422 return 0; /* not a stub */
5426 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5427 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5430 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5432 CORE_ADDR start_addr
;
5434 /* Find the starting address of the function containing the PC. If the
5435 caller didn't give us a name, look it up at the same time. */
5436 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
5439 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5441 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5442 if (name
[19] >= '0' && name
[19] <= '9')
5444 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5445 before the jal instruction, this is effectively a call stub. */
5446 else if (name
[19] == 's' || name
[19] == 'd')
5447 return pc
== start_addr
;
5450 return 0; /* not a stub */
5454 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5455 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5458 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5460 CORE_ADDR start_addr
;
5462 /* Find the starting address of the function containing the PC. */
5463 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5466 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5467 if (strcmp (name
, "__mips16_ret_sf") == 0
5468 || strcmp (name
, "__mips16_ret_df") == 0)
5471 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5472 i.e. after the jal instruction, this is effectively a return stub. */
5473 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5474 && (name
[19] == 's' || name
[19] == 'd')
5475 && pc
!= start_addr
)
5478 return 0; /* not a stub */
5482 /* Return non-zero if the PC is in a library helper function that should
5483 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5486 mips_ignore_helper (CORE_ADDR pc
)
5490 /* Find the starting address and name of the function containing the PC. */
5491 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5494 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5495 that we want to ignore. */
5496 return (strcmp (name
, "__mips16_ret_sf") == 0
5497 || strcmp (name
, "__mips16_ret_df") == 0);
5501 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5502 the register stored on the stack (32) is different to its real raw
5503 size (64). The below ensures that registers are fetched from the
5504 stack using their ABI size and then stored into the RAW_BUFFER
5505 using their raw size.
5507 The alternative to adding this function would be to add an ABI
5508 macro - REGISTER_STACK_SIZE(). */
5511 mips_get_saved_register (char *raw_buffer
,
5514 struct frame_info
*frame
,
5516 enum lval_type
*lvalp
)
5519 enum lval_type lvalx
;
5523 /* Always a pseudo. */
5524 gdb_assert (regnum
>= NUM_REGS
);
5526 /* Make certain that all needed parameters are present. */
5531 if (optimizedp
== NULL
)
5532 optimizedp
= &optimizedx
;
5534 if ((regnum
% NUM_REGS
) == SP_REGNUM
)
5535 /* The SP_REGNUM is special, its value is stored in saved_regs.
5536 In fact, it is so special that it can even only be fetched
5537 using a raw register number! Once this code as been converted
5538 to frame-unwind the problem goes away. */
5539 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5540 regnum
% NUM_REGS
, optimizedp
, lvalp
, addrp
,
5541 &realnumx
, raw_buffer
);
5543 /* Get it from the next frame. */
5544 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5545 regnum
, optimizedp
, lvalp
, addrp
,
5546 &realnumx
, raw_buffer
);
5549 /* Immediately after a function call, return the saved pc.
5550 Can't always go through the frames for this because on some machines
5551 the new frame is not set up until the new function executes
5552 some instructions. */
5555 mips_saved_pc_after_call (struct frame_info
*frame
)
5557 return read_signed_register (RA_REGNUM
);
5561 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5562 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5565 mips_stab_reg_to_regnum (int num
)
5568 if (num
>= 0 && num
< 32)
5570 else if (num
>= 38 && num
< 70)
5571 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5573 regnum
= mips_regnum (current_gdbarch
)->hi
;
5575 regnum
= mips_regnum (current_gdbarch
)->lo
;
5577 /* This will hopefully (eventually) provoke a warning. Should
5578 we be calling complaint() here? */
5579 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5580 return NUM_REGS
+ regnum
;
5584 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5585 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5588 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5591 if (num
>= 0 && num
< 32)
5593 else if (num
>= 32 && num
< 64)
5594 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5596 regnum
= mips_regnum (current_gdbarch
)->hi
;
5598 regnum
= mips_regnum (current_gdbarch
)->lo
;
5600 /* This will hopefully (eventually) provoke a warning. Should we
5601 be calling complaint() here? */
5602 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5603 return NUM_REGS
+ regnum
;
5607 mips_register_sim_regno (int regnum
)
5609 /* Only makes sense to supply raw registers. */
5610 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5611 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5612 decide if it is valid. Should instead define a standard sim/gdb
5613 register numbering scheme. */
5614 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5615 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5618 return LEGACY_SIM_REGNO_IGNORE
;
5622 /* Convert an integer into an address. By first converting the value
5623 into a pointer and then extracting it signed, the address is
5624 guarenteed to be correctly sign extended. */
5627 mips_integer_to_address (struct type
*type
, void *buf
)
5629 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5630 LONGEST val
= unpack_long (type
, buf
);
5631 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5632 return extract_signed_integer (tmp
,
5633 TYPE_LENGTH (builtin_type_void_data_ptr
));
5637 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5639 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5640 const char *name
= bfd_get_section_name (abfd
, sect
);
5642 if (*abip
!= MIPS_ABI_UNKNOWN
)
5645 if (strncmp (name
, ".mdebug.", 8) != 0)
5648 if (strcmp (name
, ".mdebug.abi32") == 0)
5649 *abip
= MIPS_ABI_O32
;
5650 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5651 *abip
= MIPS_ABI_N32
;
5652 else if (strcmp (name
, ".mdebug.abi64") == 0)
5653 *abip
= MIPS_ABI_N64
;
5654 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5655 *abip
= MIPS_ABI_O64
;
5656 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5657 *abip
= MIPS_ABI_EABI32
;
5658 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5659 *abip
= MIPS_ABI_EABI64
;
5661 warning ("unsupported ABI %s.", name
+ 8);
5664 static enum mips_abi
5665 global_mips_abi (void)
5669 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5670 if (mips_abi_strings
[i
] == mips_abi_string
)
5671 return (enum mips_abi
) i
;
5673 internal_error (__FILE__
, __LINE__
,
5674 "unknown ABI string");
5677 static struct gdbarch
*
5678 mips_gdbarch_init (struct gdbarch_info info
,
5679 struct gdbarch_list
*arches
)
5681 struct gdbarch
*gdbarch
;
5682 struct gdbarch_tdep
*tdep
;
5684 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5686 enum mips_fpu_type fpu_type
;
5688 /* First of all, extract the elf_flags, if available. */
5689 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5690 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5691 else if (arches
!= NULL
)
5692 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5696 fprintf_unfiltered (gdb_stdlog
,
5697 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5700 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5701 switch ((elf_flags
& EF_MIPS_ABI
))
5703 case E_MIPS_ABI_O32
:
5704 found_abi
= MIPS_ABI_O32
;
5706 case E_MIPS_ABI_O64
:
5707 found_abi
= MIPS_ABI_O64
;
5709 case E_MIPS_ABI_EABI32
:
5710 found_abi
= MIPS_ABI_EABI32
;
5712 case E_MIPS_ABI_EABI64
:
5713 found_abi
= MIPS_ABI_EABI64
;
5716 if ((elf_flags
& EF_MIPS_ABI2
))
5717 found_abi
= MIPS_ABI_N32
;
5719 found_abi
= MIPS_ABI_UNKNOWN
;
5723 /* GCC creates a pseudo-section whose name describes the ABI. */
5724 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5725 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5727 /* If we have no usefu BFD information, use the ABI from the last
5728 MIPS architecture (if there is one). */
5729 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5730 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5732 /* Try the architecture for any hint of the correct ABI. */
5733 if (found_abi
== MIPS_ABI_UNKNOWN
5734 && info
.bfd_arch_info
!= NULL
5735 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5737 switch (info
.bfd_arch_info
->mach
)
5739 case bfd_mach_mips3900
:
5740 found_abi
= MIPS_ABI_EABI32
;
5742 case bfd_mach_mips4100
:
5743 case bfd_mach_mips5000
:
5744 found_abi
= MIPS_ABI_EABI64
;
5746 case bfd_mach_mips8000
:
5747 case bfd_mach_mips10000
:
5748 /* On Irix, ELF64 executables use the N64 ABI. The
5749 pseudo-sections which describe the ABI aren't present
5750 on IRIX. (Even for executables created by gcc.) */
5751 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5752 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5753 found_abi
= MIPS_ABI_N64
;
5755 found_abi
= MIPS_ABI_N32
;
5761 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5764 /* What has the user specified from the command line? */
5765 wanted_abi
= global_mips_abi ();
5767 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5770 /* Now that we have found what the ABI for this binary would be,
5771 check whether the user is overriding it. */
5772 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5773 mips_abi
= wanted_abi
;
5774 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5775 mips_abi
= found_abi
;
5777 mips_abi
= MIPS_ABI_O32
;
5779 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5782 /* Also used when doing an architecture lookup. */
5784 fprintf_unfiltered (gdb_stdlog
,
5785 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5786 mips64_transfers_32bit_regs_p
);
5788 /* Determine the MIPS FPU type. */
5789 if (!mips_fpu_type_auto
)
5790 fpu_type
= mips_fpu_type
;
5791 else if (info
.bfd_arch_info
!= NULL
5792 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5793 switch (info
.bfd_arch_info
->mach
)
5795 case bfd_mach_mips3900
:
5796 case bfd_mach_mips4100
:
5797 case bfd_mach_mips4111
:
5798 fpu_type
= MIPS_FPU_NONE
;
5800 case bfd_mach_mips4650
:
5801 fpu_type
= MIPS_FPU_SINGLE
;
5804 fpu_type
= MIPS_FPU_DOUBLE
;
5807 else if (arches
!= NULL
)
5808 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5810 fpu_type
= MIPS_FPU_DOUBLE
;
5812 fprintf_unfiltered (gdb_stdlog
,
5813 "mips_gdbarch_init: fpu_type = %d\n",
5816 /* try to find a pre-existing architecture */
5817 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5819 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5821 /* MIPS needs to be pedantic about which ABI the object is
5823 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5825 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5827 /* Need to be pedantic about which register virtual size is
5829 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5830 != mips64_transfers_32bit_regs_p
)
5832 /* Be pedantic about which FPU is selected. */
5833 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5835 return arches
->gdbarch
;
5838 /* Need a new architecture. Fill in a target specific vector. */
5839 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5840 gdbarch
= gdbarch_alloc (&info
, tdep
);
5841 tdep
->elf_flags
= elf_flags
;
5842 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5843 tdep
->found_abi
= found_abi
;
5844 tdep
->mips_abi
= mips_abi
;
5845 tdep
->mips_fpu_type
= fpu_type
;
5847 /* Initially set everything according to the default ABI/ISA. */
5848 set_gdbarch_short_bit (gdbarch
, 16);
5849 set_gdbarch_int_bit (gdbarch
, 32);
5850 set_gdbarch_float_bit (gdbarch
, 32);
5851 set_gdbarch_double_bit (gdbarch
, 64);
5852 set_gdbarch_long_double_bit (gdbarch
, 64);
5853 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5854 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5855 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5857 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5858 mips_elf_make_msymbol_special
);
5860 /* Fill in the OS dependant register numbers and names. */
5862 const char **reg_names
;
5863 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5864 struct mips_regnum
);
5865 if (info
.osabi
== GDB_OSABI_IRIX
)
5870 regnum
->badvaddr
= 66;
5873 regnum
->fp_control_status
= 69;
5874 regnum
->fp_implementation_revision
= 70;
5876 reg_names
= mips_irix_reg_names
;
5880 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5881 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5882 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5883 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5884 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5885 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5886 regnum
->fp_control_status
= 70;
5887 regnum
->fp_implementation_revision
= 71;
5889 if (info
.bfd_arch_info
!= NULL
5890 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5891 reg_names
= mips_tx39_reg_names
;
5893 reg_names
= mips_generic_reg_names
;
5895 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5896 replaced by read_pc? */
5897 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
);
5898 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5899 set_gdbarch_num_regs (gdbarch
, num_regs
);
5900 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5901 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5902 tdep
->mips_processor_reg_names
= reg_names
;
5903 tdep
->regnum
= regnum
;
5909 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5910 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5911 tdep
->mips_default_saved_regsize
= 4;
5912 tdep
->mips_default_stack_argsize
= 4;
5913 tdep
->mips_fp_register_double
= 0;
5914 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5915 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5916 tdep
->default_mask_address_p
= 0;
5917 set_gdbarch_long_bit (gdbarch
, 32);
5918 set_gdbarch_ptr_bit (gdbarch
, 32);
5919 set_gdbarch_long_long_bit (gdbarch
, 64);
5920 set_gdbarch_deprecated_reg_struct_has_addr
5921 (gdbarch
, mips_o32_reg_struct_has_addr
);
5924 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5925 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_o64_store_return_value
);
5926 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_o64_extract_return_value
);
5927 tdep
->mips_default_saved_regsize
= 8;
5928 tdep
->mips_default_stack_argsize
= 8;
5929 tdep
->mips_fp_register_double
= 1;
5930 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5931 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5932 tdep
->default_mask_address_p
= 0;
5933 set_gdbarch_long_bit (gdbarch
, 32);
5934 set_gdbarch_ptr_bit (gdbarch
, 32);
5935 set_gdbarch_long_long_bit (gdbarch
, 64);
5936 set_gdbarch_deprecated_reg_struct_has_addr
5937 (gdbarch
, mips_o32_reg_struct_has_addr
);
5938 set_gdbarch_use_struct_convention (gdbarch
, always_use_struct_convention
);
5940 case MIPS_ABI_EABI32
:
5941 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5942 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5943 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5944 tdep
->mips_default_saved_regsize
= 4;
5945 tdep
->mips_default_stack_argsize
= 4;
5946 tdep
->mips_fp_register_double
= 0;
5947 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5948 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5949 tdep
->default_mask_address_p
= 0;
5950 set_gdbarch_long_bit (gdbarch
, 32);
5951 set_gdbarch_ptr_bit (gdbarch
, 32);
5952 set_gdbarch_long_long_bit (gdbarch
, 64);
5953 set_gdbarch_deprecated_reg_struct_has_addr
5954 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5955 set_gdbarch_use_struct_convention (gdbarch
,
5956 mips_eabi_use_struct_convention
);
5958 case MIPS_ABI_EABI64
:
5959 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5960 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5961 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5962 tdep
->mips_default_saved_regsize
= 8;
5963 tdep
->mips_default_stack_argsize
= 8;
5964 tdep
->mips_fp_register_double
= 1;
5965 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5966 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5967 tdep
->default_mask_address_p
= 0;
5968 set_gdbarch_long_bit (gdbarch
, 64);
5969 set_gdbarch_ptr_bit (gdbarch
, 64);
5970 set_gdbarch_long_long_bit (gdbarch
, 64);
5971 set_gdbarch_deprecated_reg_struct_has_addr
5972 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5973 set_gdbarch_use_struct_convention (gdbarch
,
5974 mips_eabi_use_struct_convention
);
5977 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5978 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5979 tdep
->mips_default_saved_regsize
= 8;
5980 tdep
->mips_default_stack_argsize
= 8;
5981 tdep
->mips_fp_register_double
= 1;
5982 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5983 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5984 tdep
->default_mask_address_p
= 0;
5985 set_gdbarch_long_bit (gdbarch
, 32);
5986 set_gdbarch_ptr_bit (gdbarch
, 32);
5987 set_gdbarch_long_long_bit (gdbarch
, 64);
5988 set_gdbarch_deprecated_reg_struct_has_addr
5989 (gdbarch
, mips_n32n64_reg_struct_has_addr
);
5992 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5993 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5994 tdep
->mips_default_saved_regsize
= 8;
5995 tdep
->mips_default_stack_argsize
= 8;
5996 tdep
->mips_fp_register_double
= 1;
5997 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5998 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5999 tdep
->default_mask_address_p
= 0;
6000 set_gdbarch_long_bit (gdbarch
, 64);
6001 set_gdbarch_ptr_bit (gdbarch
, 64);
6002 set_gdbarch_long_long_bit (gdbarch
, 64);
6003 set_gdbarch_deprecated_reg_struct_has_addr
6004 (gdbarch
, mips_n32n64_reg_struct_has_addr
);
6007 internal_error (__FILE__
, __LINE__
,
6008 "unknown ABI in switch");
6011 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6012 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6015 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6016 flag in object files because to do so would make it impossible to
6017 link with libraries compiled without "-gp32". This is
6018 unnecessarily restrictive.
6020 We could solve this problem by adding "-gp32" multilibs to gcc,
6021 but to set this flag before gcc is built with such multilibs will
6022 break too many systems.''
6024 But even more unhelpfully, the default linker output target for
6025 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6026 for 64-bit programs - you need to change the ABI to change this,
6027 and not all gcc targets support that currently. Therefore using
6028 this flag to detect 32-bit mode would do the wrong thing given
6029 the current gcc - it would make GDB treat these 64-bit programs
6030 as 32-bit programs by default. */
6032 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6033 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
6034 set_gdbarch_deprecated_target_read_fp (gdbarch
, mips_read_sp
); /* Draft FRAME base. */
6035 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6037 /* Add/remove bits from an address. The MIPS needs be careful to
6038 ensure that all 32 bit addresses are sign extended to 64 bits. */
6039 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6041 /* There's a mess in stack frame creation. See comments in
6042 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
6043 set_gdbarch_deprecated_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
6045 /* Map debug register numbers onto internal register numbers. */
6046 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6047 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6048 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6049 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6050 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6052 /* Initialize a frame */
6053 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch
, mips_find_saved_regs
);
6054 set_gdbarch_deprecated_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
6056 /* MIPS version of CALL_DUMMY */
6058 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6059 replaced by a command, and all targets will default to on stack
6060 (regardless of the stack's execute status). */
6061 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6062 set_gdbarch_deprecated_pop_frame (gdbarch
, mips_pop_frame
);
6063 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6064 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
6066 set_gdbarch_deprecated_frame_chain (gdbarch
, mips_frame_chain
);
6067 set_gdbarch_frameless_function_invocation (gdbarch
,
6068 generic_frameless_function_invocation_not
);
6069 set_gdbarch_deprecated_frame_saved_pc (gdbarch
, mips_frame_saved_pc
);
6070 set_gdbarch_frame_args_skip (gdbarch
, 0);
6072 set_gdbarch_deprecated_get_saved_register (gdbarch
, mips_get_saved_register
);
6074 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6075 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6076 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
6078 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6079 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
6081 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6082 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6083 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6085 set_gdbarch_function_start_offset (gdbarch
, 0);
6087 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6089 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6090 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
6092 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6094 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6095 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6096 need to all be folded into the target vector. Since they are
6097 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6098 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6100 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6102 /* Hook in OS ABI-specific overrides, if they have been registered. */
6103 gdbarch_init_osabi (info
, gdbarch
);
6105 set_gdbarch_extract_struct_value_address (gdbarch
,
6106 mips_extract_struct_value_address
);
6108 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6110 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6111 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6117 mips_abi_update (char *ignore_args
, int from_tty
,
6118 struct cmd_list_element
*c
)
6120 struct gdbarch_info info
;
6122 /* Force the architecture to update, and (if it's a MIPS architecture)
6123 mips_gdbarch_init will take care of the rest. */
6124 gdbarch_info_init (&info
);
6125 gdbarch_update_p (info
);
6128 /* Print out which MIPS ABI is in use. */
6131 show_mips_abi (char *ignore_args
, int from_tty
)
6133 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6135 "The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6138 enum mips_abi global_abi
= global_mips_abi ();
6139 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6140 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6142 if (global_abi
== MIPS_ABI_UNKNOWN
)
6143 printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n",
6145 else if (global_abi
== actual_abi
)
6147 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6151 /* Probably shouldn't happen... */
6153 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6155 mips_abi_strings
[global_abi
]);
6161 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6163 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6167 int ef_mips_32bitmode
;
6168 /* determine the ISA */
6169 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6187 /* determine the size of a pointer */
6188 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6189 fprintf_unfiltered (file
,
6190 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6192 fprintf_unfiltered (file
,
6193 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6195 fprintf_unfiltered (file
,
6196 "mips_dump_tdep: ef_mips_arch = %d\n",
6198 fprintf_unfiltered (file
,
6199 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6201 mips_abi_strings
[tdep
->mips_abi
]);
6202 fprintf_unfiltered (file
,
6203 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6204 mips_mask_address_p (tdep
),
6205 tdep
->default_mask_address_p
);
6207 fprintf_unfiltered (file
,
6208 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6209 FP_REGISTER_DOUBLE
);
6210 fprintf_unfiltered (file
,
6211 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6212 MIPS_DEFAULT_FPU_TYPE
,
6213 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6214 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6215 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6217 fprintf_unfiltered (file
,
6218 "mips_dump_tdep: MIPS_EABI = %d\n",
6220 fprintf_unfiltered (file
,
6221 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6223 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6224 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6225 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6227 fprintf_unfiltered (file
,
6228 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6229 FP_REGISTER_DOUBLE
);
6230 fprintf_unfiltered (file
,
6231 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6232 mips_stack_argsize (tdep
));
6233 fprintf_unfiltered (file
,
6234 "mips_dump_tdep: A0_REGNUM = %d\n",
6236 fprintf_unfiltered (file
,
6237 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6238 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
6239 fprintf_unfiltered (file
,
6240 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6241 XSTRING (ATTACH_DETACH
));
6242 fprintf_unfiltered (file
,
6243 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6244 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6245 fprintf_unfiltered (file
,
6246 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6247 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6248 fprintf_unfiltered (file
,
6249 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6250 FIRST_EMBED_REGNUM
);
6251 fprintf_unfiltered (file
,
6252 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6253 XSTRING (IGNORE_HELPER_CALL (PC
)));
6254 fprintf_unfiltered (file
,
6255 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6256 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6257 fprintf_unfiltered (file
,
6258 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6259 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6260 fprintf_unfiltered (file
,
6261 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6263 #ifdef MACHINE_CPROC_FP_OFFSET
6264 fprintf_unfiltered (file
,
6265 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6266 MACHINE_CPROC_FP_OFFSET
);
6268 #ifdef MACHINE_CPROC_PC_OFFSET
6269 fprintf_unfiltered (file
,
6270 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6271 MACHINE_CPROC_PC_OFFSET
);
6273 #ifdef MACHINE_CPROC_SP_OFFSET
6274 fprintf_unfiltered (file
,
6275 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6276 MACHINE_CPROC_SP_OFFSET
);
6278 fprintf_unfiltered (file
,
6279 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6281 fprintf_unfiltered (file
,
6282 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6283 fprintf_unfiltered (file
,
6284 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6285 fprintf_unfiltered (file
,
6286 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6288 fprintf_unfiltered (file
,
6289 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6290 MIPS_LAST_ARG_REGNUM
,
6291 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6292 fprintf_unfiltered (file
,
6293 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6295 fprintf_unfiltered (file
,
6296 "mips_dump_tdep: mips_saved_regsize() = %d\n",
6297 mips_saved_regsize (tdep
));
6298 fprintf_unfiltered (file
,
6299 "mips_dump_tdep: PRID_REGNUM = %d\n",
6301 fprintf_unfiltered (file
,
6302 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6303 fprintf_unfiltered (file
,
6304 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6305 fprintf_unfiltered (file
,
6306 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6307 fprintf_unfiltered (file
,
6308 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6309 fprintf_unfiltered (file
,
6310 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6311 fprintf_unfiltered (file
,
6312 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6313 fprintf_unfiltered (file
,
6314 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6315 fprintf_unfiltered (file
,
6316 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6317 fprintf_unfiltered (file
,
6318 "mips_dump_tdep: PROC_PC_REG = function?\n");
6319 fprintf_unfiltered (file
,
6320 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6321 fprintf_unfiltered (file
,
6322 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6323 fprintf_unfiltered (file
,
6324 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6325 fprintf_unfiltered (file
,
6326 "mips_dump_tdep: PS_REGNUM = %d\n",
6328 fprintf_unfiltered (file
,
6329 "mips_dump_tdep: RA_REGNUM = %d\n",
6332 fprintf_unfiltered (file
,
6333 "mips_dump_tdep: SAVED_BYTES = %d\n",
6337 fprintf_unfiltered (file
,
6338 "mips_dump_tdep: SAVED_FP = %d\n",
6342 fprintf_unfiltered (file
,
6343 "mips_dump_tdep: SAVED_PC = %d\n",
6346 fprintf_unfiltered (file
,
6347 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6348 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6349 fprintf_unfiltered (file
,
6350 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6351 fprintf_unfiltered (file
,
6352 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6354 fprintf_unfiltered (file
,
6355 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6356 SIGFRAME_FPREGSAVE_OFF
);
6357 fprintf_unfiltered (file
,
6358 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6360 fprintf_unfiltered (file
,
6361 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6362 SIGFRAME_REGSAVE_OFF
);
6363 fprintf_unfiltered (file
,
6364 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6365 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6366 fprintf_unfiltered (file
,
6367 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6368 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6369 fprintf_unfiltered (file
,
6370 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6371 SOFTWARE_SINGLE_STEP_P ());
6372 fprintf_unfiltered (file
,
6373 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6374 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6375 #ifdef STACK_END_ADDR
6376 fprintf_unfiltered (file
,
6377 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6380 fprintf_unfiltered (file
,
6381 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6382 XSTRING (STEP_SKIPS_DELAY (PC
)));
6383 fprintf_unfiltered (file
,
6384 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6385 STEP_SKIPS_DELAY_P
);
6386 fprintf_unfiltered (file
,
6387 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6388 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6389 fprintf_unfiltered (file
,
6390 "mips_dump_tdep: T9_REGNUM = %d\n",
6392 fprintf_unfiltered (file
,
6393 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6394 fprintf_unfiltered (file
,
6395 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6396 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
6397 fprintf_unfiltered (file
,
6398 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6399 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6401 fprintf_unfiltered (file
,
6402 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6403 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6406 fprintf_unfiltered (file
,
6407 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6410 #ifdef TRACE_FLAVOR_SIZE
6411 fprintf_unfiltered (file
,
6412 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6416 fprintf_unfiltered (file
,
6417 "mips_dump_tdep: TRACE_SET # %s\n",
6418 XSTRING (TRACE_SET (X
,STATE
)));
6420 #ifdef UNUSED_REGNUM
6421 fprintf_unfiltered (file
,
6422 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6425 fprintf_unfiltered (file
,
6426 "mips_dump_tdep: V0_REGNUM = %d\n",
6428 fprintf_unfiltered (file
,
6429 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6430 (long) VM_MIN_ADDRESS
);
6431 fprintf_unfiltered (file
,
6432 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6434 fprintf_unfiltered (file
,
6435 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6439 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6442 _initialize_mips_tdep (void)
6444 static struct cmd_list_element
*mipsfpulist
= NULL
;
6445 struct cmd_list_element
*c
;
6447 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6448 if (MIPS_ABI_LAST
+ 1
6449 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6450 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6452 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6454 /* Add root prefix command for all "set mips"/"show mips" commands */
6455 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6456 "Various MIPS specific commands.",
6457 &setmipscmdlist
, "set mips ", 0, &setlist
);
6459 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6460 "Various MIPS specific commands.",
6461 &showmipscmdlist
, "show mips ", 0, &showlist
);
6463 /* Allow the user to override the saved register size. */
6464 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6467 &mips_saved_regsize_string
, "\
6468 Set size of general purpose registers saved on the stack.\n\
6469 This option can be set to one of:\n\
6470 32 - Force GDB to treat saved GP registers as 32-bit\n\
6471 64 - Force GDB to treat saved GP registers as 64-bit\n\
6472 auto - Allow GDB to use the target's default setting or autodetect the\n\
6473 saved GP register size from information contained in the executable.\n\
6478 /* Allow the user to override the argument stack size. */
6479 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6482 &mips_stack_argsize_string
, "\
6483 Set the amount of stack space reserved for each argument.\n\
6484 This option can be set to one of:\n\
6485 32 - Force GDB to allocate 32-bit chunks per argument\n\
6486 64 - Force GDB to allocate 64-bit chunks per argument\n\
6487 auto - Allow GDB to determine the correct setting from the current\n\
6488 target and executable (default)",
6492 /* Allow the user to override the ABI. */
6493 c
= add_set_enum_cmd
6494 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6495 "Set the ABI used by this program.\n"
6496 "This option can be set to one of:\n"
6497 " auto - the default ABI associated with the current binary\n"
6505 set_cmd_sfunc (c
, mips_abi_update
);
6506 add_cmd ("abi", class_obscure
, show_mips_abi
,
6507 "Show ABI in use by MIPS target", &showmipscmdlist
);
6509 /* Let the user turn off floating point and set the fence post for
6510 heuristic_proc_start. */
6512 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6513 "Set use of MIPS floating-point coprocessor.",
6514 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6515 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6516 "Select single-precision MIPS floating-point coprocessor.",
6518 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6519 "Select double-precision MIPS floating-point coprocessor.",
6521 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6522 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6523 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6524 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6525 "Select no MIPS floating-point coprocessor.",
6527 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6528 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6529 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6530 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6531 "Select MIPS floating-point coprocessor automatically.",
6533 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6534 "Show current use of MIPS floating-point coprocessor target.",
6537 /* We really would like to have both "0" and "unlimited" work, but
6538 command.c doesn't deal with that. So make it a var_zinteger
6539 because the user can always use "999999" or some such for unlimited. */
6540 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6541 (char *) &heuristic_fence_post
,
6543 Set the distance searched for the start of a function.\n\
6544 If you are debugging a stripped executable, GDB needs to search through the\n\
6545 program for the start of a function. This command sets the distance of the\n\
6546 search. The only need to set it is when debugging a stripped executable.",
6548 /* We need to throw away the frame cache when we set this, since it
6549 might change our ability to get backtraces. */
6550 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6551 add_show_from_set (c
, &showlist
);
6553 /* Allow the user to control whether the upper bits of 64-bit
6554 addresses should be zeroed. */
6555 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6556 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6557 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6558 allow GDB to determine the correct value.\n", "\
6559 Show zeroing of upper 32 bits of 64-bit addresses.",
6560 NULL
, show_mask_address
,
6561 &setmipscmdlist
, &showmipscmdlist
);
6563 /* Allow the user to control the size of 32 bit registers within the
6564 raw remote packet. */
6565 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6566 var_boolean
, &mips64_transfers_32bit_regs_p
, "\
6567 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6568 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6569 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6570 64 bits for others. Use \"off\" to disable compatibility mode", "\
6571 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6572 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6573 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6574 64 bits for others. Use \"off\" to disable compatibility mode",
6575 set_mips64_transfers_32bit_regs
, NULL
,
6576 &setlist
, &showlist
);
6578 /* Debug this files internals. */
6579 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6580 &mips_debug
, "Set mips debugging.\n\
6581 When non-zero, mips specific debugging is enabled.", &setdebuglist
),