1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
62 static const struct objfile_data
*mips_pdr_data
;
64 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
66 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
67 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
68 #define ST0_FR (1 << 26)
70 /* The sizes of floating point registers. */
74 MIPS_FPU_SINGLE_REGSIZE
= 4,
75 MIPS_FPU_DOUBLE_REGSIZE
= 8
84 static const char *mips_abi_string
;
86 static const char *mips_abi_strings
[] = {
97 /* The standard register names, and all the valid aliases for them. */
104 /* Aliases for o32 and most other ABIs. */
105 const struct register_alias mips_o32_aliases
[] = {
112 /* Aliases for n32 and n64. */
113 const struct register_alias mips_n32_n64_aliases
[] = {
120 /* Aliases for ABI-independent registers. */
121 const struct register_alias mips_register_aliases
[] = {
122 /* The architecture manuals specify these ABI-independent names for
124 #define R(n) { "r" #n, n }
125 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
126 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
127 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
128 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
131 /* k0 and k1 are sometimes called these instead (for "kernel
136 /* This is the traditional GDB name for the CP0 status register. */
137 { "sr", MIPS_PS_REGNUM
},
139 /* This is the traditional GDB name for the CP0 BadVAddr register. */
140 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
142 /* This is the traditional GDB name for the FCSR. */
143 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
146 const struct register_alias mips_numeric_register_aliases
[] = {
147 #define R(n) { #n, n }
148 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
149 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
150 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
151 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto
= 1;
159 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
161 static int mips_debug
= 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc
*mips_tdesc_gp32
;
169 struct target_desc
*mips_tdesc_gp64
;
171 const struct mips_regnum
*
172 mips_regnum (struct gdbarch
*gdbarch
)
174 return gdbarch_tdep (gdbarch
)->regnum
;
178 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
180 return mips_regnum (gdbarch
)->fp0
+ 12;
183 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
185 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
187 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
189 #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
191 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
193 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
194 functions to test, set, or clear bit 0 of addresses. */
197 is_mips16_addr (CORE_ADDR addr
)
203 unmake_mips16_addr (CORE_ADDR addr
)
205 return ((addr
) & ~(CORE_ADDR
) 1);
208 /* Return the MIPS ABI associated with GDBARCH. */
210 mips_abi (struct gdbarch
*gdbarch
)
212 return gdbarch_tdep (gdbarch
)->mips_abi
;
216 mips_isa_regsize (struct gdbarch
*gdbarch
)
218 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
220 /* If we know how big the registers are, use that size. */
221 if (tdep
->register_size_valid_p
)
222 return tdep
->register_size
;
224 /* Fall back to the previous behavior. */
225 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
226 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
229 /* Return the currently configured (or set) saved register size. */
232 mips_abi_regsize (struct gdbarch
*gdbarch
)
234 switch (mips_abi (gdbarch
))
236 case MIPS_ABI_EABI32
:
242 case MIPS_ABI_EABI64
:
244 case MIPS_ABI_UNKNOWN
:
247 internal_error (__FILE__
, __LINE__
, _("bad switch"));
251 /* Functions for setting and testing a bit in a minimal symbol that
252 marks it as 16-bit function. The MSB of the minimal symbol's
253 "info" field is used for this purpose.
255 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
256 i.e. refers to a 16-bit function, and sets a "special" bit in a
257 minimal symbol to mark it as a 16-bit function
259 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
262 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
264 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
266 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
267 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
272 msymbol_is_special (struct minimal_symbol
*msym
)
274 return MSYMBOL_TARGET_FLAG_1 (msym
);
277 /* XFER a value from the big/little/left end of the register.
278 Depending on the size of the value it might occupy the entire
279 register or just part of it. Make an allowance for this, aligning
280 things accordingly. */
283 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
284 int reg_num
, int length
,
285 enum bfd_endian endian
, gdb_byte
*in
,
286 const gdb_byte
*out
, int buf_offset
)
290 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
291 /* Need to transfer the left or right part of the register, based on
292 the targets byte order. */
296 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
298 case BFD_ENDIAN_LITTLE
:
301 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
305 internal_error (__FILE__
, __LINE__
, _("bad switch"));
308 fprintf_unfiltered (gdb_stderr
,
309 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
310 reg_num
, reg_offset
, buf_offset
, length
);
311 if (mips_debug
&& out
!= NULL
)
314 fprintf_unfiltered (gdb_stdlog
, "out ");
315 for (i
= 0; i
< length
; i
++)
316 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
319 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
322 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
324 if (mips_debug
&& in
!= NULL
)
327 fprintf_unfiltered (gdb_stdlog
, "in ");
328 for (i
= 0; i
< length
; i
++)
329 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
332 fprintf_unfiltered (gdb_stdlog
, "\n");
335 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
336 compatiblity mode. A return value of 1 means that we have
337 physical 64-bit registers, but should treat them as 32-bit registers. */
340 mips2_fp_compat (struct frame_info
*frame
)
342 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
343 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
345 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
349 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
350 in all the places we deal with FP registers. PR gdb/413. */
351 /* Otherwise check the FR bit in the status register - it controls
352 the FP compatiblity mode. If it is clear we are in compatibility
354 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
361 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
363 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
365 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
367 /* The list of available "set mips " and "show mips " commands */
369 static struct cmd_list_element
*setmipscmdlist
= NULL
;
370 static struct cmd_list_element
*showmipscmdlist
= NULL
;
372 /* Integer registers 0 thru 31 are handled explicitly by
373 mips_register_name(). Processor specific registers 32 and above
374 are listed in the following tables. */
377 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
381 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
382 "sr", "lo", "hi", "bad", "cause", "pc",
383 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
384 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
385 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
386 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
387 "fsr", "fir", "" /*"fp" */ , "",
388 "", "", "", "", "", "", "", "",
389 "", "", "", "", "", "", "", "",
392 /* Names of IDT R3041 registers. */
394 static const char *mips_r3041_reg_names
[] = {
395 "sr", "lo", "hi", "bad", "cause", "pc",
396 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
397 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
398 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
399 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
400 "fsr", "fir", "", /*"fp" */ "",
401 "", "", "bus", "ccfg", "", "", "", "",
402 "", "", "port", "cmp", "", "", "epc", "prid",
405 /* Names of tx39 registers. */
407 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
408 "sr", "lo", "hi", "bad", "cause", "pc",
409 "", "", "", "", "", "", "", "",
410 "", "", "", "", "", "", "", "",
411 "", "", "", "", "", "", "", "",
412 "", "", "", "", "", "", "", "",
414 "", "", "", "", "", "", "", "",
415 "", "", "config", "cache", "debug", "depc", "epc", ""
418 /* Names of IRIX registers. */
419 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
420 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
421 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
422 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
423 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
424 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
428 /* Return the name of the register corresponding to REGNO. */
430 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
432 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
433 /* GPR names for all ABIs other than n32/n64. */
434 static char *mips_gpr_names
[] = {
435 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
436 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
437 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
438 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
441 /* GPR names for n32 and n64 ABIs. */
442 static char *mips_n32_n64_gpr_names
[] = {
443 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
444 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
445 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
446 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
449 enum mips_abi abi
= mips_abi (gdbarch
);
451 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
452 but then don't make the raw register names visible. */
453 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
454 if (regno
< gdbarch_num_regs (gdbarch
))
457 /* The MIPS integer registers are always mapped from 0 to 31. The
458 names of the registers (which reflects the conventions regarding
459 register use) vary depending on the ABI. */
460 if (0 <= rawnum
&& rawnum
< 32)
462 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
463 return mips_n32_n64_gpr_names
[rawnum
];
465 return mips_gpr_names
[rawnum
];
467 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
468 return tdesc_register_name (gdbarch
, rawnum
);
469 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
471 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
472 return tdep
->mips_processor_reg_names
[rawnum
- 32];
475 internal_error (__FILE__
, __LINE__
,
476 _("mips_register_name: bad register number %d"), rawnum
);
479 /* Return the groups that a MIPS register can be categorised into. */
482 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
483 struct reggroup
*reggroup
)
488 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
489 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
490 if (reggroup
== all_reggroup
)
492 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
493 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
494 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
495 (gdbarch), as not all architectures are multi-arch. */
496 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
497 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
498 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
500 if (reggroup
== float_reggroup
)
501 return float_p
&& pseudo
;
502 if (reggroup
== vector_reggroup
)
503 return vector_p
&& pseudo
;
504 if (reggroup
== general_reggroup
)
505 return (!vector_p
&& !float_p
) && pseudo
;
506 /* Save the pseudo registers. Need to make certain that any code
507 extracting register values from a saved register cache also uses
509 if (reggroup
== save_reggroup
)
510 return raw_p
&& pseudo
;
511 /* Restore the same pseudo register. */
512 if (reggroup
== restore_reggroup
)
513 return raw_p
&& pseudo
;
517 /* Return the groups that a MIPS register can be categorised into.
518 This version is only used if we have a target description which
519 describes real registers (and their groups). */
522 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
523 struct reggroup
*reggroup
)
525 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
526 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
529 /* Only save, restore, and display the pseudo registers. Need to
530 make certain that any code extracting register values from a
531 saved register cache also uses pseudo registers.
533 Note: saving and restoring the pseudo registers is slightly
534 strange; if we have 64 bits, we should save and restore all
535 64 bits. But this is hard and has little benefit. */
539 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
543 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
546 /* Map the symbol table registers which live in the range [1 *
547 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
548 registers. Take care of alignment and size problems. */
551 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
552 int cookednum
, gdb_byte
*buf
)
554 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
555 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
556 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
557 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
558 regcache_raw_read (regcache
, rawnum
, buf
);
559 else if (register_size (gdbarch
, rawnum
) >
560 register_size (gdbarch
, cookednum
))
562 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
563 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
564 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
566 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
569 internal_error (__FILE__
, __LINE__
, _("bad register size"));
573 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
574 struct regcache
*regcache
, int cookednum
,
577 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
578 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
579 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
580 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
581 regcache_raw_write (regcache
, rawnum
, buf
);
582 else if (register_size (gdbarch
, rawnum
) >
583 register_size (gdbarch
, cookednum
))
585 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
586 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
587 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
589 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
592 internal_error (__FILE__
, __LINE__
, _("bad register size"));
595 /* Table to translate MIPS16 register field to actual register number. */
596 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
598 /* Heuristic_proc_start may hunt through the text section for a long
599 time across a 2400 baud serial line. Allows the user to limit this
602 static unsigned int heuristic_fence_post
= 0;
604 /* Number of bytes of storage in the actual machine representation for
605 register N. NOTE: This defines the pseudo register type so need to
606 rebuild the architecture vector. */
608 static int mips64_transfers_32bit_regs_p
= 0;
611 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
612 struct cmd_list_element
*c
)
614 struct gdbarch_info info
;
615 gdbarch_info_init (&info
);
616 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
617 instead of relying on globals. Doing that would let generic code
618 handle the search for this specific architecture. */
619 if (!gdbarch_update_p (info
))
621 mips64_transfers_32bit_regs_p
= 0;
622 error (_("32-bit compatibility mode not supported"));
626 /* Convert to/from a register and the corresponding memory value. */
629 mips_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
631 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
632 && register_size (gdbarch
, regnum
) == 4
633 && (regnum
% gdbarch_num_regs (gdbarch
))
634 >= mips_regnum (gdbarch
)->fp0
635 && (regnum
% gdbarch_num_regs (gdbarch
))
636 < mips_regnum (gdbarch
)->fp0
+ 32
637 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
641 mips_register_to_value (struct frame_info
*frame
, int regnum
,
642 struct type
*type
, gdb_byte
*to
)
644 get_frame_register (frame
, regnum
+ 0, to
+ 4);
645 get_frame_register (frame
, regnum
+ 1, to
+ 0);
649 mips_value_to_register (struct frame_info
*frame
, int regnum
,
650 struct type
*type
, const gdb_byte
*from
)
652 put_frame_register (frame
, regnum
+ 0, from
+ 4);
653 put_frame_register (frame
, regnum
+ 1, from
+ 0);
656 /* Return the GDB type object for the "standard" data type of data in
660 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
662 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
663 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
664 && (regnum
% gdbarch_num_regs (gdbarch
))
665 < mips_regnum (gdbarch
)->fp0
+ 32)
667 /* The floating-point registers raw, or cooked, always match
668 mips_isa_regsize(), and also map 1:1, byte for byte. */
669 if (mips_isa_regsize (gdbarch
) == 4)
670 return builtin_type (gdbarch
)->builtin_float
;
672 return builtin_type (gdbarch
)->builtin_double
;
674 else if (regnum
< gdbarch_num_regs (gdbarch
))
676 /* The raw or ISA registers. These are all sized according to
678 if (mips_isa_regsize (gdbarch
) == 4)
679 return builtin_type (gdbarch
)->builtin_int32
;
681 return builtin_type (gdbarch
)->builtin_int64
;
685 /* The cooked or ABI registers. These are sized according to
686 the ABI (with a few complications). */
687 if (regnum
>= (gdbarch_num_regs (gdbarch
)
688 + mips_regnum (gdbarch
)->fp_control_status
)
689 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
690 /* The pseudo/cooked view of the embedded registers is always
691 32-bit. The raw view is handled below. */
692 return builtin_type (gdbarch
)->builtin_int32
;
693 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
694 /* The target, while possibly using a 64-bit register buffer,
695 is only transfering 32-bits of each integer register.
696 Reflect this in the cooked/pseudo (ABI) register value. */
697 return builtin_type (gdbarch
)->builtin_int32
;
698 else if (mips_abi_regsize (gdbarch
) == 4)
699 /* The ABI is restricted to 32-bit registers (the ISA could be
701 return builtin_type (gdbarch
)->builtin_int32
;
704 return builtin_type (gdbarch
)->builtin_int64
;
708 /* Return the GDB type for the pseudo register REGNUM, which is the
709 ABI-level view. This function is only called if there is a target
710 description which includes registers, so we know precisely the
711 types of hardware registers. */
714 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
716 const int num_regs
= gdbarch_num_regs (gdbarch
);
717 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
718 int rawnum
= regnum
% num_regs
;
719 struct type
*rawtype
;
721 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
723 /* Absent registers are still absent. */
724 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
725 if (TYPE_LENGTH (rawtype
) == 0)
728 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
729 /* Present the floating point registers however the hardware did;
730 do not try to convert between FPU layouts. */
733 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
735 /* The pseudo/cooked view of embedded registers is always
736 32-bit, even if the target transfers 64-bit values for them.
737 New targets relying on XML descriptions should only transfer
738 the necessary 32 bits, but older versions of GDB expected 64,
739 so allow the target to provide 64 bits without interfering
740 with the displayed type. */
741 return builtin_type (gdbarch
)->builtin_int32
;
744 /* Use pointer types for registers if we can. For n32 we can not,
745 since we do not have a 64-bit pointer type. */
746 if (mips_abi_regsize (gdbarch
)
747 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
749 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
750 return builtin_type (gdbarch
)->builtin_data_ptr
;
751 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
752 return builtin_type (gdbarch
)->builtin_func_ptr
;
755 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
756 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
757 return builtin_type (gdbarch
)->builtin_int32
;
759 /* For all other registers, pass through the hardware type. */
763 /* Should the upper word of 64-bit addresses be zeroed? */
764 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
767 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
769 switch (mask_address_var
)
771 case AUTO_BOOLEAN_TRUE
:
773 case AUTO_BOOLEAN_FALSE
:
776 case AUTO_BOOLEAN_AUTO
:
777 return tdep
->default_mask_address_p
;
779 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
785 show_mask_address (struct ui_file
*file
, int from_tty
,
786 struct cmd_list_element
*c
, const char *value
)
788 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
790 deprecated_show_value_hack (file
, from_tty
, c
, value
);
791 switch (mask_address_var
)
793 case AUTO_BOOLEAN_TRUE
:
794 printf_filtered ("The 32 bit mips address mask is enabled\n");
796 case AUTO_BOOLEAN_FALSE
:
797 printf_filtered ("The 32 bit mips address mask is disabled\n");
799 case AUTO_BOOLEAN_AUTO
:
801 ("The 32 bit address mask is set automatically. Currently %s\n",
802 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
805 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
810 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
813 mips_pc_is_mips16 (CORE_ADDR memaddr
)
815 struct minimal_symbol
*sym
;
817 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
818 if (is_mips16_addr (memaddr
))
821 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
822 the high bit of the info field. Use this to decide if the function is
823 MIPS16 or normal MIPS. */
824 sym
= lookup_minimal_symbol_by_pc (memaddr
);
826 return msymbol_is_special (sym
);
831 /* MIPS believes that the PC has a sign extended value. Perhaps the
832 all registers should be sign extended for simplicity? */
835 mips_read_pc (struct regcache
*regcache
)
838 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
839 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
844 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
846 return frame_unwind_register_signed
847 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
851 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
853 return frame_unwind_register_signed
854 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
857 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
858 dummy frame. The frame ID's base needs to match the TOS value
859 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
862 static struct frame_id
863 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
865 return frame_id_build
866 (get_frame_register_signed (this_frame
,
867 gdbarch_num_regs (gdbarch
)
869 get_frame_pc (this_frame
));
873 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
875 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
876 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
879 /* Fetch and return instruction from the specified location. If the PC
880 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
883 mips_fetch_instruction (CORE_ADDR addr
)
885 gdb_byte buf
[MIPS_INSN32_SIZE
];
889 if (mips_pc_is_mips16 (addr
))
891 instlen
= MIPS_INSN16_SIZE
;
892 addr
= unmake_mips16_addr (addr
);
895 instlen
= MIPS_INSN32_SIZE
;
896 status
= target_read_memory (addr
, buf
, instlen
);
898 memory_error (status
, addr
);
899 return extract_unsigned_integer (buf
, instlen
);
902 /* These the fields of 32 bit mips instructions */
903 #define mips32_op(x) (x >> 26)
904 #define itype_op(x) (x >> 26)
905 #define itype_rs(x) ((x >> 21) & 0x1f)
906 #define itype_rt(x) ((x >> 16) & 0x1f)
907 #define itype_immediate(x) (x & 0xffff)
909 #define jtype_op(x) (x >> 26)
910 #define jtype_target(x) (x & 0x03ffffff)
912 #define rtype_op(x) (x >> 26)
913 #define rtype_rs(x) ((x >> 21) & 0x1f)
914 #define rtype_rt(x) ((x >> 16) & 0x1f)
915 #define rtype_rd(x) ((x >> 11) & 0x1f)
916 #define rtype_shamt(x) ((x >> 6) & 0x1f)
917 #define rtype_funct(x) (x & 0x3f)
920 mips32_relative_offset (ULONGEST inst
)
922 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
925 /* Determine where to set a single step breakpoint while considering
926 branch prediction. */
928 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
932 inst
= mips_fetch_instruction (pc
);
933 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
935 if (itype_op (inst
) >> 2 == 5)
936 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
938 op
= (itype_op (inst
) & 0x03);
953 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
954 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
956 int tf
= itype_rt (inst
) & 0x01;
957 int cnum
= itype_rt (inst
) >> 2;
959 get_frame_register_signed (frame
,
960 mips_regnum (get_frame_arch (frame
))->
962 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
964 if (((cond
>> cnum
) & 0x01) == tf
)
965 pc
+= mips32_relative_offset (inst
) + 4;
970 pc
+= 4; /* Not a branch, next instruction is easy */
973 { /* This gets way messy */
975 /* Further subdivide into SPECIAL, REGIMM and other */
976 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
978 case 0: /* SPECIAL */
979 op
= rtype_funct (inst
);
984 /* Set PC to that address */
985 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
987 case 12: /* SYSCALL */
989 struct gdbarch_tdep
*tdep
;
991 tdep
= gdbarch_tdep (get_frame_arch (frame
));
992 if (tdep
->syscall_next_pc
!= NULL
)
993 pc
= tdep
->syscall_next_pc (frame
);
1002 break; /* end SPECIAL */
1003 case 1: /* REGIMM */
1005 op
= itype_rt (inst
); /* branch condition */
1010 case 16: /* BLTZAL */
1011 case 18: /* BLTZALL */
1013 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1014 pc
+= mips32_relative_offset (inst
) + 4;
1016 pc
+= 8; /* after the delay slot */
1020 case 17: /* BGEZAL */
1021 case 19: /* BGEZALL */
1022 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1023 pc
+= mips32_relative_offset (inst
) + 4;
1025 pc
+= 8; /* after the delay slot */
1027 /* All of the other instructions in the REGIMM category */
1032 break; /* end REGIMM */
1037 reg
= jtype_target (inst
) << 2;
1038 /* Upper four bits get never changed... */
1039 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1042 /* FIXME case JALX : */
1045 reg
= jtype_target (inst
) << 2;
1046 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1047 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1049 break; /* The new PC will be alternate mode */
1050 case 4: /* BEQ, BEQL */
1052 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1053 get_frame_register_signed (frame
, itype_rt (inst
)))
1054 pc
+= mips32_relative_offset (inst
) + 4;
1058 case 5: /* BNE, BNEL */
1060 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1061 get_frame_register_signed (frame
, itype_rt (inst
)))
1062 pc
+= mips32_relative_offset (inst
) + 4;
1066 case 6: /* BLEZ, BLEZL */
1067 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1068 pc
+= mips32_relative_offset (inst
) + 4;
1074 greater_branch
: /* BGTZ, BGTZL */
1075 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1076 pc
+= mips32_relative_offset (inst
) + 4;
1083 } /* mips32_next_pc */
1085 /* Decoding the next place to set a breakpoint is irregular for the
1086 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1087 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1088 We dont want to set a single step instruction on the extend instruction
1092 /* Lots of mips16 instruction formats */
1093 /* Predicting jumps requires itype,ritype,i8type
1094 and their extensions extItype,extritype,extI8type
1096 enum mips16_inst_fmts
1098 itype
, /* 0 immediate 5,10 */
1099 ritype
, /* 1 5,3,8 */
1100 rrtype
, /* 2 5,3,3,5 */
1101 rritype
, /* 3 5,3,3,5 */
1102 rrrtype
, /* 4 5,3,3,3,2 */
1103 rriatype
, /* 5 5,3,3,1,4 */
1104 shifttype
, /* 6 5,3,3,3,2 */
1105 i8type
, /* 7 5,3,8 */
1106 i8movtype
, /* 8 5,3,3,5 */
1107 i8mov32rtype
, /* 9 5,3,5,3 */
1108 i64type
, /* 10 5,3,8 */
1109 ri64type
, /* 11 5,3,3,5 */
1110 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1111 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1112 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1113 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1114 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1115 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1116 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1117 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1118 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1119 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1121 /* I am heaping all the fields of the formats into one structure and
1122 then, only the fields which are involved in instruction extension */
1126 unsigned int regx
; /* Function in i8 type */
1131 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1132 for the bits which make up the immediate extension. */
1135 extended_offset (unsigned int extension
)
1138 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1140 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1142 value
|= extension
& 0x01f; /* extract 4:0 */
1146 /* Only call this function if you know that this is an extendable
1147 instruction. It won't malfunction, but why make excess remote memory
1148 references? If the immediate operands get sign extended or something,
1149 do it after the extension is performed. */
1150 /* FIXME: Every one of these cases needs to worry about sign extension
1151 when the offset is to be used in relative addressing. */
1154 fetch_mips_16 (CORE_ADDR pc
)
1157 pc
&= 0xfffffffe; /* clear the low order bit */
1158 target_read_memory (pc
, buf
, 2);
1159 return extract_unsigned_integer (buf
, 2);
1163 unpack_mips16 (CORE_ADDR pc
,
1164 unsigned int extension
,
1166 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1171 switch (insn_format
)
1178 value
= extended_offset (extension
);
1179 value
= value
<< 11; /* rom for the original value */
1180 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1184 value
= inst
& 0x7ff;
1185 /* FIXME : Consider sign extension */
1194 { /* A register identifier and an offset */
1195 /* Most of the fields are the same as I type but the
1196 immediate value is of a different length */
1200 value
= extended_offset (extension
);
1201 value
= value
<< 8; /* from the original instruction */
1202 value
|= inst
& 0xff; /* eleven bits from instruction */
1203 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1204 if (value
& 0x4000) /* test the sign bit , bit 26 */
1206 value
&= ~0x3fff; /* remove the sign bit */
1212 value
= inst
& 0xff; /* 8 bits */
1213 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1214 /* FIXME: Do sign extension , this format needs it */
1215 if (value
& 0x80) /* THIS CONFUSES ME */
1217 value
&= 0xef; /* remove the sign bit */
1227 unsigned long value
;
1228 unsigned int nexthalf
;
1229 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1230 value
= value
<< 16;
1231 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1239 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1241 upk
->offset
= offset
;
1248 add_offset_16 (CORE_ADDR pc
, int offset
)
1250 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1254 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1255 unsigned int extension
, unsigned int insn
)
1257 int op
= (insn
>> 11);
1260 case 2: /* Branch */
1263 struct upk_mips16 upk
;
1264 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1265 offset
= upk
.offset
;
1271 pc
+= (offset
<< 1) + 2;
1274 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1276 struct upk_mips16 upk
;
1277 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1278 pc
= add_offset_16 (pc
, upk
.offset
);
1279 if ((insn
>> 10) & 0x01) /* Exchange mode */
1280 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1287 struct upk_mips16 upk
;
1289 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1290 reg
= get_frame_register_signed (frame
, upk
.regx
);
1292 pc
+= (upk
.offset
<< 1) + 2;
1299 struct upk_mips16 upk
;
1301 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1302 reg
= get_frame_register_signed (frame
, upk
.regx
);
1304 pc
+= (upk
.offset
<< 1) + 2;
1309 case 12: /* I8 Formats btez btnez */
1311 struct upk_mips16 upk
;
1313 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1314 /* upk.regx contains the opcode */
1315 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1316 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1317 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1318 /* pc = add_offset_16(pc,upk.offset) ; */
1319 pc
+= (upk
.offset
<< 1) + 2;
1324 case 29: /* RR Formats JR, JALR, JALR-RA */
1326 struct upk_mips16 upk
;
1327 /* upk.fmt = rrtype; */
1332 upk
.regx
= (insn
>> 8) & 0x07;
1333 upk
.regy
= (insn
>> 5) & 0x07;
1341 break; /* Function return instruction */
1347 break; /* BOGUS Guess */
1349 pc
= get_frame_register_signed (frame
, reg
);
1356 /* This is an instruction extension. Fetch the real instruction
1357 (which follows the extension) and decode things based on
1361 pc
= extended_mips16_next_pc (frame
, pc
, insn
, fetch_mips_16 (pc
));
1374 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1376 unsigned int insn
= fetch_mips_16 (pc
);
1377 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1380 /* The mips_next_pc function supports single_step when the remote
1381 target monitor or stub is not developed enough to do a single_step.
1382 It works by decoding the current instruction and predicting where a
1383 branch will go. This isnt hard because all the data is available.
1384 The MIPS32 and MIPS16 variants are quite different. */
1386 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1388 if (is_mips16_addr (pc
))
1389 return mips16_next_pc (frame
, pc
);
1391 return mips32_next_pc (frame
, pc
);
1394 struct mips_frame_cache
1397 struct trad_frame_saved_reg
*saved_regs
;
1400 /* Set a register's saved stack address in temp_saved_regs. If an
1401 address has already been set for this register, do nothing; this
1402 way we will only recognize the first save of a given register in a
1405 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1406 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1407 Strictly speaking, only the second range is used as it is only second
1408 range (the ABI instead of ISA registers) that comes into play when finding
1409 saved registers in a frame. */
1412 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1413 int regnum
, CORE_ADDR offset
)
1415 if (this_cache
!= NULL
1416 && this_cache
->saved_regs
[regnum
].addr
== -1)
1418 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1420 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1426 /* Fetch the immediate value from a MIPS16 instruction.
1427 If the previous instruction was an EXTEND, use it to extend
1428 the upper bits of the immediate value. This is a helper function
1429 for mips16_scan_prologue. */
1432 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1433 unsigned short inst
, /* current instruction */
1434 int nbits
, /* number of bits in imm field */
1435 int scale
, /* scale factor to be applied to imm */
1436 int is_signed
) /* is the imm field signed? */
1440 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1442 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1443 if (offset
& 0x8000) /* check for negative extend */
1444 offset
= 0 - (0x10000 - (offset
& 0xffff));
1445 return offset
| (inst
& 0x1f);
1449 int max_imm
= 1 << nbits
;
1450 int mask
= max_imm
- 1;
1451 int sign_bit
= max_imm
>> 1;
1453 offset
= inst
& mask
;
1454 if (is_signed
&& (offset
& sign_bit
))
1455 offset
= 0 - (max_imm
- offset
);
1456 return offset
* scale
;
1461 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1462 the associated FRAME_CACHE if not null.
1463 Return the address of the first instruction past the prologue. */
1466 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1467 struct frame_info
*this_frame
,
1468 struct mips_frame_cache
*this_cache
)
1471 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1473 long frame_offset
= 0; /* Size of stack frame. */
1474 long frame_adjust
= 0; /* Offset of FP from SP. */
1475 int frame_reg
= MIPS_SP_REGNUM
;
1476 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1477 unsigned inst
= 0; /* current instruction */
1478 unsigned entry_inst
= 0; /* the entry instruction */
1479 unsigned save_inst
= 0; /* the save instruction */
1482 int extend_bytes
= 0;
1483 int prev_extend_bytes
;
1484 CORE_ADDR end_prologue_addr
= 0;
1485 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1487 /* Can be called when there's no process, and hence when there's no
1489 if (this_frame
!= NULL
)
1490 sp
= get_frame_register_signed (this_frame
,
1491 gdbarch_num_regs (gdbarch
)
1496 if (limit_pc
> start_pc
+ 200)
1497 limit_pc
= start_pc
+ 200;
1499 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1501 /* Save the previous instruction. If it's an EXTEND, we'll extract
1502 the immediate offset extension from it in mips16_get_imm. */
1505 /* Fetch and decode the instruction. */
1506 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1508 /* Normally we ignore extend instructions. However, if it is
1509 not followed by a valid prologue instruction, then this
1510 instruction is not part of the prologue either. We must
1511 remember in this case to adjust the end_prologue_addr back
1513 if ((inst
& 0xf800) == 0xf000) /* extend */
1515 extend_bytes
= MIPS_INSN16_SIZE
;
1519 prev_extend_bytes
= extend_bytes
;
1522 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1523 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1525 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1526 if (offset
< 0) /* negative stack adjustment? */
1527 frame_offset
-= offset
;
1529 /* Exit loop if a positive stack adjustment is found, which
1530 usually means that the stack cleanup code in the function
1531 epilogue is reached. */
1534 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1536 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1537 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1538 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1540 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1542 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1543 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1544 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1546 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1548 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1549 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1551 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1553 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1554 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1556 else if (inst
== 0x673d) /* move $s1, $sp */
1561 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1563 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1564 frame_addr
= sp
+ offset
;
1566 frame_adjust
= offset
;
1568 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1570 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1571 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1572 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1574 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1576 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1577 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1578 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1580 else if ((inst
& 0xf81f) == 0xe809
1581 && (inst
& 0x700) != 0x700) /* entry */
1582 entry_inst
= inst
; /* save for later processing */
1583 else if ((inst
& 0xff80) == 0x6480) /* save */
1585 save_inst
= inst
; /* save for later processing */
1586 if (prev_extend_bytes
) /* extend */
1587 save_inst
|= prev_inst
<< 16;
1589 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1590 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1591 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1593 /* This instruction is part of the prologue, but we don't
1594 need to do anything special to handle it. */
1598 /* This instruction is not an instruction typically found
1599 in a prologue, so we must have reached the end of the
1601 if (end_prologue_addr
== 0)
1602 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1606 /* The entry instruction is typically the first instruction in a function,
1607 and it stores registers at offsets relative to the value of the old SP
1608 (before the prologue). But the value of the sp parameter to this
1609 function is the new SP (after the prologue has been executed). So we
1610 can't calculate those offsets until we've seen the entire prologue,
1611 and can calculate what the old SP must have been. */
1612 if (entry_inst
!= 0)
1614 int areg_count
= (entry_inst
>> 8) & 7;
1615 int sreg_count
= (entry_inst
>> 6) & 3;
1617 /* The entry instruction always subtracts 32 from the SP. */
1620 /* Now we can calculate what the SP must have been at the
1621 start of the function prologue. */
1624 /* Check if a0-a3 were saved in the caller's argument save area. */
1625 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1627 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1628 offset
+= mips_abi_regsize (gdbarch
);
1631 /* Check if the ra register was pushed on the stack. */
1633 if (entry_inst
& 0x20)
1635 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1636 offset
-= mips_abi_regsize (gdbarch
);
1639 /* Check if the s0 and s1 registers were pushed on the stack. */
1640 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1642 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1643 offset
-= mips_abi_regsize (gdbarch
);
1647 /* The SAVE instruction is similar to ENTRY, except that defined by the
1648 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1649 size of the frame is specified as an immediate field of instruction
1650 and an extended variation exists which lets additional registers and
1651 frame space to be specified. The instruction always treats registers
1652 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1653 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1655 static int args_table
[16] = {
1656 0, 0, 0, 0, 1, 1, 1, 1,
1657 2, 2, 2, 0, 3, 3, 4, -1,
1659 static int astatic_table
[16] = {
1660 0, 1, 2, 3, 0, 1, 2, 3,
1661 0, 1, 2, 4, 0, 1, 0, -1,
1663 int aregs
= (save_inst
>> 16) & 0xf;
1664 int xsregs
= (save_inst
>> 24) & 0x7;
1665 int args
= args_table
[aregs
];
1666 int astatic
= astatic_table
[aregs
];
1671 warning (_("Invalid number of argument registers encoded in SAVE."));
1676 warning (_("Invalid number of static registers encoded in SAVE."));
1680 /* For standard SAVE the frame size of 0 means 128. */
1681 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1682 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1685 frame_offset
+= frame_size
;
1687 /* Now we can calculate what the SP must have been at the
1688 start of the function prologue. */
1691 /* Check if A0-A3 were saved in the caller's argument save area. */
1692 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1694 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1695 offset
+= mips_abi_regsize (gdbarch
);
1700 /* Check if the RA register was pushed on the stack. */
1701 if (save_inst
& 0x40)
1703 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1704 offset
-= mips_abi_regsize (gdbarch
);
1707 /* Check if the S8 register was pushed on the stack. */
1710 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1711 offset
-= mips_abi_regsize (gdbarch
);
1714 /* Check if S2-S7 were pushed on the stack. */
1715 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1717 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1718 offset
-= mips_abi_regsize (gdbarch
);
1721 /* Check if the S1 register was pushed on the stack. */
1722 if (save_inst
& 0x10)
1724 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1725 offset
-= mips_abi_regsize (gdbarch
);
1727 /* Check if the S0 register was pushed on the stack. */
1728 if (save_inst
& 0x20)
1730 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1731 offset
-= mips_abi_regsize (gdbarch
);
1734 /* Check if A0-A3 were pushed on the stack. */
1735 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1737 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1738 offset
-= mips_abi_regsize (gdbarch
);
1742 if (this_cache
!= NULL
)
1745 (get_frame_register_signed (this_frame
,
1746 gdbarch_num_regs (gdbarch
) + frame_reg
)
1747 + frame_offset
- frame_adjust
);
1748 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1749 be able to get rid of the assignment below, evetually. But it's
1750 still needed for now. */
1751 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1752 + mips_regnum (gdbarch
)->pc
]
1753 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1756 /* If we didn't reach the end of the prologue when scanning the function
1757 instructions, then set end_prologue_addr to the address of the
1758 instruction immediately after the last one we scanned. */
1759 if (end_prologue_addr
== 0)
1760 end_prologue_addr
= cur_pc
;
1762 return end_prologue_addr
;
1765 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1766 Procedures that use the 32-bit instruction set are handled by the
1767 mips_insn32 unwinder. */
1769 static struct mips_frame_cache
*
1770 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1772 struct mips_frame_cache
*cache
;
1774 if ((*this_cache
) != NULL
)
1775 return (*this_cache
);
1776 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1777 (*this_cache
) = cache
;
1778 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1780 /* Analyze the function prologue. */
1782 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1783 CORE_ADDR start_addr
;
1785 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1786 if (start_addr
== 0)
1787 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
1788 /* We can't analyze the prologue if we couldn't find the begining
1790 if (start_addr
== 0)
1793 mips16_scan_prologue (start_addr
, pc
, this_frame
, *this_cache
);
1796 /* gdbarch_sp_regnum contains the value and not the address. */
1797 trad_frame_set_value (cache
->saved_regs
,
1798 gdbarch_num_regs (get_frame_arch (this_frame
))
1802 return (*this_cache
);
1806 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1807 struct frame_id
*this_id
)
1809 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1811 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
1814 static struct value
*
1815 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
1816 void **this_cache
, int regnum
)
1818 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1820 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1824 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
1825 struct frame_info
*this_frame
, void **this_cache
)
1827 CORE_ADDR pc
= get_frame_pc (this_frame
);
1828 if (mips_pc_is_mips16 (pc
))
1833 static const struct frame_unwind mips_insn16_frame_unwind
=
1836 mips_insn16_frame_this_id
,
1837 mips_insn16_frame_prev_register
,
1839 mips_insn16_frame_sniffer
1843 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
1846 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1851 static const struct frame_base mips_insn16_frame_base
=
1853 &mips_insn16_frame_unwind
,
1854 mips_insn16_frame_base_address
,
1855 mips_insn16_frame_base_address
,
1856 mips_insn16_frame_base_address
1859 static const struct frame_base
*
1860 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
1862 CORE_ADDR pc
= get_frame_pc (this_frame
);
1863 if (mips_pc_is_mips16 (pc
))
1864 return &mips_insn16_frame_base
;
1869 /* Mark all the registers as unset in the saved_regs array
1870 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1873 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
1875 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1879 const int num_regs
= gdbarch_num_regs (gdbarch
);
1882 for (i
= 0; i
< num_regs
; i
++)
1884 this_cache
->saved_regs
[i
].addr
= -1;
1889 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1890 the associated FRAME_CACHE if not null.
1891 Return the address of the first instruction past the prologue. */
1894 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1895 struct frame_info
*this_frame
,
1896 struct mips_frame_cache
*this_cache
)
1899 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1902 int frame_reg
= MIPS_SP_REGNUM
;
1904 CORE_ADDR end_prologue_addr
= 0;
1905 int seen_sp_adjust
= 0;
1906 int load_immediate_bytes
= 0;
1907 int in_delay_slot
= 0;
1908 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1909 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
1911 /* Can be called when there's no process, and hence when there's no
1913 if (this_frame
!= NULL
)
1914 sp
= get_frame_register_signed (this_frame
,
1915 gdbarch_num_regs (gdbarch
)
1920 if (limit_pc
> start_pc
+ 200)
1921 limit_pc
= start_pc
+ 200;
1926 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1928 unsigned long inst
, high_word
, low_word
;
1931 /* Fetch the instruction. */
1932 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1934 /* Save some code by pre-extracting some useful fields. */
1935 high_word
= (inst
>> 16) & 0xffff;
1936 low_word
= inst
& 0xffff;
1937 reg
= high_word
& 0x1f;
1939 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1940 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1941 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1943 if (low_word
& 0x8000) /* negative stack adjustment? */
1944 frame_offset
+= 0x10000 - low_word
;
1946 /* Exit loop if a positive stack adjustment is found, which
1947 usually means that the stack cleanup code in the function
1948 epilogue is reached. */
1952 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1953 && !regsize_is_64_bits
)
1955 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
1957 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1958 && regsize_is_64_bits
)
1960 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1961 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
1963 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1965 /* Old gcc frame, r30 is virtual frame pointer. */
1966 if ((long) low_word
!= frame_offset
)
1967 frame_addr
= sp
+ low_word
;
1968 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1970 unsigned alloca_adjust
;
1973 frame_addr
= get_frame_register_signed
1974 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
1976 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1977 if (alloca_adjust
> 0)
1979 /* FP > SP + frame_size. This may be because of
1980 an alloca or somethings similar. Fix sp to
1981 "pre-alloca" value, and try again. */
1982 sp
+= alloca_adjust
;
1983 /* Need to reset the status of all registers. Otherwise,
1984 we will hit a guard that prevents the new address
1985 for each register to be recomputed during the second
1987 reset_saved_regs (gdbarch
, this_cache
);
1992 /* move $30,$sp. With different versions of gas this will be either
1993 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1994 Accept any one of these. */
1995 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1997 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1998 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2000 unsigned alloca_adjust
;
2003 frame_addr
= get_frame_register_signed
2004 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2006 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2007 if (alloca_adjust
> 0)
2009 /* FP > SP + frame_size. This may be because of
2010 an alloca or somethings similar. Fix sp to
2011 "pre-alloca" value, and try again. */
2013 /* Need to reset the status of all registers. Otherwise,
2014 we will hit a guard that prevents the new address
2015 for each register to be recomputed during the second
2017 reset_saved_regs (gdbarch
, this_cache
);
2022 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2023 && !regsize_is_64_bits
)
2025 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2027 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2028 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2029 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2030 || high_word
== 0x3c1c /* lui $gp,n */
2031 || high_word
== 0x279c /* addiu $gp,$gp,n */
2032 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2033 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2036 /* These instructions are part of the prologue, but we don't
2037 need to do anything special to handle them. */
2039 /* The instructions below load $at or $t0 with an immediate
2040 value in preparation for a stack adjustment via
2041 subu $sp,$sp,[$at,$t0]. These instructions could also
2042 initialize a local variable, so we accept them only before
2043 a stack adjustment instruction was seen. */
2044 else if (!seen_sp_adjust
2045 && (high_word
== 0x3c01 /* lui $at,n */
2046 || high_word
== 0x3c08 /* lui $t0,n */
2047 || high_word
== 0x3421 /* ori $at,$at,n */
2048 || high_word
== 0x3508 /* ori $t0,$t0,n */
2049 || high_word
== 0x3401 /* ori $at,$zero,n */
2050 || high_word
== 0x3408 /* ori $t0,$zero,n */
2053 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2057 /* This instruction is not an instruction typically found
2058 in a prologue, so we must have reached the end of the
2060 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2061 loop now? Why would we need to continue scanning the function
2063 if (end_prologue_addr
== 0)
2064 end_prologue_addr
= cur_pc
;
2066 /* Check for branches and jumps. For now, only jump to
2067 register are caught (i.e. returns). */
2068 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2072 /* If the previous instruction was a jump, we must have reached
2073 the end of the prologue by now. Stop scanning so that we do
2074 not go past the function return. */
2079 if (this_cache
!= NULL
)
2082 (get_frame_register_signed (this_frame
,
2083 gdbarch_num_regs (gdbarch
) + frame_reg
)
2085 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2086 this assignment below, eventually. But it's still needed
2088 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2089 + mips_regnum (gdbarch
)->pc
]
2090 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2094 /* If we didn't reach the end of the prologue when scanning the function
2095 instructions, then set end_prologue_addr to the address of the
2096 instruction immediately after the last one we scanned. */
2097 /* brobecker/2004-10-10: I don't think this would ever happen, but
2098 we may as well be careful and do our best if we have a null
2099 end_prologue_addr. */
2100 if (end_prologue_addr
== 0)
2101 end_prologue_addr
= cur_pc
;
2103 /* In a frameless function, we might have incorrectly
2104 skipped some load immediate instructions. Undo the skipping
2105 if the load immediate was not followed by a stack adjustment. */
2106 if (load_immediate_bytes
&& !seen_sp_adjust
)
2107 end_prologue_addr
-= load_immediate_bytes
;
2109 return end_prologue_addr
;
2112 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2113 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2114 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2117 static struct mips_frame_cache
*
2118 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2120 struct mips_frame_cache
*cache
;
2122 if ((*this_cache
) != NULL
)
2123 return (*this_cache
);
2125 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2126 (*this_cache
) = cache
;
2127 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2129 /* Analyze the function prologue. */
2131 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2132 CORE_ADDR start_addr
;
2134 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2135 if (start_addr
== 0)
2136 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
2137 /* We can't analyze the prologue if we couldn't find the begining
2139 if (start_addr
== 0)
2142 mips32_scan_prologue (start_addr
, pc
, this_frame
, *this_cache
);
2145 /* gdbarch_sp_regnum contains the value and not the address. */
2146 trad_frame_set_value (cache
->saved_regs
,
2147 gdbarch_num_regs (get_frame_arch (this_frame
))
2151 return (*this_cache
);
2155 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2156 struct frame_id
*this_id
)
2158 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2160 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2163 static struct value
*
2164 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2165 void **this_cache
, int regnum
)
2167 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2169 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2173 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2174 struct frame_info
*this_frame
, void **this_cache
)
2176 CORE_ADDR pc
= get_frame_pc (this_frame
);
2177 if (! mips_pc_is_mips16 (pc
))
2182 static const struct frame_unwind mips_insn32_frame_unwind
=
2185 mips_insn32_frame_this_id
,
2186 mips_insn32_frame_prev_register
,
2188 mips_insn32_frame_sniffer
2192 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2195 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2200 static const struct frame_base mips_insn32_frame_base
=
2202 &mips_insn32_frame_unwind
,
2203 mips_insn32_frame_base_address
,
2204 mips_insn32_frame_base_address
,
2205 mips_insn32_frame_base_address
2208 static const struct frame_base
*
2209 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2211 CORE_ADDR pc
= get_frame_pc (this_frame
);
2212 if (! mips_pc_is_mips16 (pc
))
2213 return &mips_insn32_frame_base
;
2218 static struct trad_frame_cache
*
2219 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2222 CORE_ADDR start_addr
;
2223 CORE_ADDR stack_addr
;
2224 struct trad_frame_cache
*this_trad_cache
;
2225 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2226 int num_regs
= gdbarch_num_regs (gdbarch
);
2228 if ((*this_cache
) != NULL
)
2229 return (*this_cache
);
2230 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2231 (*this_cache
) = this_trad_cache
;
2233 /* The return address is in the link register. */
2234 trad_frame_set_reg_realreg (this_trad_cache
,
2235 gdbarch_pc_regnum (gdbarch
),
2236 num_regs
+ MIPS_RA_REGNUM
);
2238 /* Frame ID, since it's a frameless / stackless function, no stack
2239 space is allocated and SP on entry is the current SP. */
2240 pc
= get_frame_pc (this_frame
);
2241 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2242 stack_addr
= get_frame_register_signed (this_frame
,
2243 num_regs
+ MIPS_SP_REGNUM
);
2244 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2246 /* Assume that the frame's base is the same as the
2248 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2250 return this_trad_cache
;
2254 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2255 struct frame_id
*this_id
)
2257 struct trad_frame_cache
*this_trad_cache
2258 = mips_stub_frame_cache (this_frame
, this_cache
);
2259 trad_frame_get_id (this_trad_cache
, this_id
);
2262 static struct value
*
2263 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2264 void **this_cache
, int regnum
)
2266 struct trad_frame_cache
*this_trad_cache
2267 = mips_stub_frame_cache (this_frame
, this_cache
);
2268 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2272 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2273 struct frame_info
*this_frame
, void **this_cache
)
2276 struct obj_section
*s
;
2277 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2278 struct minimal_symbol
*msym
;
2280 /* Use the stub unwinder for unreadable code. */
2281 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2284 if (in_plt_section (pc
, NULL
))
2287 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2288 s
= find_pc_section (pc
);
2291 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2292 ".MIPS.stubs") == 0)
2295 /* Calling a PIC function from a non-PIC function passes through a
2296 stub. The stub for foo is named ".pic.foo". */
2297 msym
= lookup_minimal_symbol_by_pc (pc
);
2299 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2300 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2306 static const struct frame_unwind mips_stub_frame_unwind
=
2309 mips_stub_frame_this_id
,
2310 mips_stub_frame_prev_register
,
2312 mips_stub_frame_sniffer
2316 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2319 struct trad_frame_cache
*this_trad_cache
2320 = mips_stub_frame_cache (this_frame
, this_cache
);
2321 return trad_frame_get_this_base (this_trad_cache
);
2324 static const struct frame_base mips_stub_frame_base
=
2326 &mips_stub_frame_unwind
,
2327 mips_stub_frame_base_address
,
2328 mips_stub_frame_base_address
,
2329 mips_stub_frame_base_address
2332 static const struct frame_base
*
2333 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2335 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2336 return &mips_stub_frame_base
;
2341 /* mips_addr_bits_remove - remove useless address bits */
2344 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2346 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2347 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2348 /* This hack is a work-around for existing boards using PMON, the
2349 simulator, and any other 64-bit targets that doesn't have true
2350 64-bit addressing. On these targets, the upper 32 bits of
2351 addresses are ignored by the hardware. Thus, the PC or SP are
2352 likely to have been sign extended to all 1s by instruction
2353 sequences that load 32-bit addresses. For example, a typical
2354 piece of code that loads an address is this:
2356 lui $r2, <upper 16 bits>
2357 ori $r2, <lower 16 bits>
2359 But the lui sign-extends the value such that the upper 32 bits
2360 may be all 1s. The workaround is simply to mask off these
2361 bits. In the future, gcc may be changed to support true 64-bit
2362 addressing, and this masking will have to be disabled. */
2363 return addr
&= 0xffffffffUL
;
2368 /* Instructions used during single-stepping of atomic sequences. */
2369 #define LL_OPCODE 0x30
2370 #define LLD_OPCODE 0x34
2371 #define SC_OPCODE 0x38
2372 #define SCD_OPCODE 0x3c
2374 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2375 instruction and ending with a SC/SCD instruction. If such a sequence
2376 is found, attempt to step through it. A breakpoint is placed at the end of
2380 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2382 CORE_ADDR breaks
[2] = {-1, -1};
2384 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2388 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2389 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2394 insn
= mips_fetch_instruction (loc
);
2395 /* Assume all atomic sequences start with a ll/lld instruction. */
2396 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2399 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2401 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2404 loc
+= MIPS_INSN32_SIZE
;
2405 insn
= mips_fetch_instruction (loc
);
2407 /* Assume that there is at most one branch in the atomic
2408 sequence. If a branch is found, put a breakpoint in its
2409 destination address. */
2410 switch (itype_op (insn
))
2412 case 0: /* SPECIAL */
2413 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2414 return 0; /* fallback to the standard single-step code. */
2416 case 1: /* REGIMM */
2417 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2421 return 0; /* fallback to the standard single-step code. */
2428 case 22: /* BLEZL */
2429 case 23: /* BGTTL */
2435 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2440 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2441 if (last_breakpoint
>= 1)
2442 return 0; /* More than one branch found, fallback to the
2443 standard single-step code. */
2444 breaks
[1] = branch_bp
;
2448 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2452 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2453 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2456 loc
+= MIPS_INSN32_SIZE
;
2458 /* Insert a breakpoint right after the end of the atomic sequence. */
2461 /* Check for duplicated breakpoints. Check also for a breakpoint
2462 placed (branch instruction's destination) in the atomic sequence */
2463 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2464 last_breakpoint
= 0;
2466 /* Effectively inserts the breakpoints. */
2467 for (index
= 0; index
<= last_breakpoint
; index
++)
2468 insert_single_step_breakpoint (gdbarch
, breaks
[index
]);
2473 /* mips_software_single_step() is called just before we want to resume
2474 the inferior, if we want to single-step it but there is no hardware
2475 or kernel single-step support (MIPS on GNU/Linux for example). We find
2476 the target of the coming instruction and breakpoint it. */
2479 mips_software_single_step (struct frame_info
*frame
)
2481 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2482 CORE_ADDR pc
, next_pc
;
2484 pc
= get_frame_pc (frame
);
2485 if (deal_with_atomic_sequence (gdbarch
, pc
))
2488 next_pc
= mips_next_pc (frame
, pc
);
2490 insert_single_step_breakpoint (gdbarch
, next_pc
);
2494 /* Test whether the PC points to the return instruction at the
2495 end of a function. */
2498 mips_about_to_return (CORE_ADDR pc
)
2500 if (mips_pc_is_mips16 (pc
))
2501 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2502 generates a "jr $ra"; other times it generates code to load
2503 the return address from the stack to an accessible register (such
2504 as $a3), then a "jr" using that register. This second case
2505 is almost impossible to distinguish from an indirect jump
2506 used for switch statements, so we don't even try. */
2507 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2509 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2513 /* This fencepost looks highly suspicious to me. Removing it also
2514 seems suspicious as it could affect remote debugging across serial
2518 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2524 struct inferior
*inf
;
2526 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2528 fence
= start_pc
- heuristic_fence_post
;
2532 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2533 fence
= VM_MIN_ADDRESS
;
2535 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2537 inf
= current_inferior ();
2539 /* search back for previous return */
2540 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2541 if (start_pc
< fence
)
2543 /* It's not clear to me why we reach this point when
2544 stop_soon, but with this test, at least we
2545 don't print out warnings for every child forked (eg, on
2546 decstation). 22apr93 rich@cygnus.com. */
2547 if (inf
->stop_soon
== NO_STOP_QUIETLY
)
2549 static int blurb_printed
= 0;
2551 warning (_("GDB can't find the start of the function at %s."),
2552 paddress (gdbarch
, pc
));
2556 /* This actually happens frequently in embedded
2557 development, when you first connect to a board
2558 and your stack pointer and pc are nowhere in
2559 particular. This message needs to give people
2560 in that situation enough information to
2561 determine that it's no big deal. */
2562 printf_filtered ("\n\
2563 GDB is unable to find the start of the function at %s\n\
2564 and thus can't determine the size of that function's stack frame.\n\
2565 This means that GDB may be unable to access that stack frame, or\n\
2566 the frames below it.\n\
2567 This problem is most likely caused by an invalid program counter or\n\
2569 However, if you think GDB should simply search farther back\n\
2570 from %s for code which looks like the beginning of a\n\
2571 function, you can increase the range of the search using the `set\n\
2572 heuristic-fence-post' command.\n",
2573 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2580 else if (mips_pc_is_mips16 (start_pc
))
2582 unsigned short inst
;
2584 /* On MIPS16, any one of the following is likely to be the
2585 start of a function:
2591 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2592 inst
= mips_fetch_instruction (start_pc
);
2593 if ((inst
& 0xff80) == 0x6480) /* save */
2595 if (start_pc
- instlen
>= fence
)
2597 inst
= mips_fetch_instruction (start_pc
- instlen
);
2598 if ((inst
& 0xf800) == 0xf000) /* extend */
2599 start_pc
-= instlen
;
2603 else if (((inst
& 0xf81f) == 0xe809
2604 && (inst
& 0x700) != 0x700) /* entry */
2605 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2606 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2607 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2609 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2610 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2615 else if (mips_about_to_return (start_pc
))
2617 /* Skip return and its delay slot. */
2618 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2625 struct mips_objfile_private
2631 /* According to the current ABI, should the type be passed in a
2632 floating-point register (assuming that there is space)? When there
2633 is no FPU, FP are not even considered as possible candidates for
2634 FP registers and, consequently this returns false - forces FP
2635 arguments into integer registers. */
2638 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2639 struct type
*arg_type
)
2641 return ((typecode
== TYPE_CODE_FLT
2642 || (MIPS_EABI (gdbarch
)
2643 && (typecode
== TYPE_CODE_STRUCT
2644 || typecode
== TYPE_CODE_UNION
)
2645 && TYPE_NFIELDS (arg_type
) == 1
2646 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2648 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2651 /* On o32, argument passing in GPRs depends on the alignment of the type being
2652 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2655 mips_type_needs_double_align (struct type
*type
)
2657 enum type_code typecode
= TYPE_CODE (type
);
2659 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2661 else if (typecode
== TYPE_CODE_STRUCT
)
2663 if (TYPE_NFIELDS (type
) < 1)
2665 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2667 else if (typecode
== TYPE_CODE_UNION
)
2671 n
= TYPE_NFIELDS (type
);
2672 for (i
= 0; i
< n
; i
++)
2673 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2680 /* Adjust the address downward (direction of stack growth) so that it
2681 is correctly aligned for a new stack frame. */
2683 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2685 return align_down (addr
, 16);
2689 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2690 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2691 int nargs
, struct value
**args
, CORE_ADDR sp
,
2692 int struct_return
, CORE_ADDR struct_addr
)
2698 int stack_offset
= 0;
2699 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2700 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2701 int regsize
= mips_abi_regsize (gdbarch
);
2703 /* For shared libraries, "t9" needs to point at the function
2705 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2707 /* Set the return address register to point to the entry point of
2708 the program, where a breakpoint lies in wait. */
2709 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2711 /* First ensure that the stack and structure return address (if any)
2712 are properly aligned. The stack has to be at least 64-bit
2713 aligned even on 32-bit machines, because doubles must be 64-bit
2714 aligned. For n32 and n64, stack frames need to be 128-bit
2715 aligned, so we round to this widest known alignment. */
2717 sp
= align_down (sp
, 16);
2718 struct_addr
= align_down (struct_addr
, 16);
2720 /* Now make space on the stack for the args. We allocate more
2721 than necessary for EABI, because the first few arguments are
2722 passed in registers, but that's OK. */
2723 for (argnum
= 0; argnum
< nargs
; argnum
++)
2724 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2725 sp
-= align_up (len
, 16);
2728 fprintf_unfiltered (gdb_stdlog
,
2729 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2730 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2732 /* Initialize the integer and float register pointers. */
2733 argreg
= MIPS_A0_REGNUM
;
2734 float_argreg
= mips_fpa0_regnum (gdbarch
);
2736 /* The struct_return pointer occupies the first parameter-passing reg. */
2740 fprintf_unfiltered (gdb_stdlog
,
2741 "mips_eabi_push_dummy_call: struct_return reg=%d %s\n",
2742 argreg
, paddress (gdbarch
, struct_addr
));
2743 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2746 /* Now load as many as possible of the first arguments into
2747 registers, and push the rest onto the stack. Loop thru args
2748 from first to last. */
2749 for (argnum
= 0; argnum
< nargs
; argnum
++)
2751 const gdb_byte
*val
;
2752 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2753 struct value
*arg
= args
[argnum
];
2754 struct type
*arg_type
= check_typedef (value_type (arg
));
2755 int len
= TYPE_LENGTH (arg_type
);
2756 enum type_code typecode
= TYPE_CODE (arg_type
);
2759 fprintf_unfiltered (gdb_stdlog
,
2760 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2761 argnum
+ 1, len
, (int) typecode
);
2763 /* The EABI passes structures that do not fit in a register by
2766 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2768 store_unsigned_integer (valbuf
, regsize
, value_address (arg
));
2769 typecode
= TYPE_CODE_PTR
;
2773 fprintf_unfiltered (gdb_stdlog
, " push");
2776 val
= value_contents (arg
);
2778 /* 32-bit ABIs always start floating point arguments in an
2779 even-numbered floating point register. Round the FP register
2780 up before the check to see if there are any FP registers
2781 left. Non MIPS_EABI targets also pass the FP in the integer
2782 registers so also round up normal registers. */
2783 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2785 if ((float_argreg
& 1))
2789 /* Floating point arguments passed in registers have to be
2790 treated specially. On 32-bit architectures, doubles
2791 are passed in register pairs; the even register gets
2792 the low word, and the odd register gets the high word.
2793 On non-EABI processors, the first two floating point arguments are
2794 also copied to general registers, because MIPS16 functions
2795 don't use float registers for arguments. This duplication of
2796 arguments in general registers can't hurt non-MIPS16 functions
2797 because those registers are normally skipped. */
2798 /* MIPS_EABI squeezes a struct that contains a single floating
2799 point value into an FP register instead of pushing it onto the
2801 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
2802 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
2804 /* EABI32 will pass doubles in consecutive registers, even on
2805 64-bit cores. At one time, we used to check the size of
2806 `float_argreg' to determine whether or not to pass doubles
2807 in consecutive registers, but this is not sufficient for
2808 making the ABI determination. */
2809 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2811 int low_offset
= gdbarch_byte_order (gdbarch
)
2812 == BFD_ENDIAN_BIG
? 4 : 0;
2813 unsigned long regval
;
2815 /* Write the low word of the double to the even register(s). */
2816 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2818 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2819 float_argreg
, phex (regval
, 4));
2820 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2822 /* Write the high word of the double to the odd register(s). */
2823 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2825 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2826 float_argreg
, phex (regval
, 4));
2827 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2831 /* This is a floating point value that fits entirely
2832 in a single register. */
2833 /* On 32 bit ABI's the float_argreg is further adjusted
2834 above to ensure that it is even register aligned. */
2835 LONGEST regval
= extract_unsigned_integer (val
, len
);
2837 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2838 float_argreg
, phex (regval
, len
));
2839 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2844 /* Copy the argument to general registers or the stack in
2845 register-sized pieces. Large arguments are split between
2846 registers and stack. */
2847 /* Note: structs whose size is not a multiple of regsize
2848 are treated specially: Irix cc passes
2849 them in registers where gcc sometimes puts them on the
2850 stack. For maximum compatibility, we will put them in
2852 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2854 /* Note: Floating-point values that didn't fit into an FP
2855 register are only written to memory. */
2858 /* Remember if the argument was written to the stack. */
2859 int stack_used_p
= 0;
2860 int partial_len
= (len
< regsize
? len
: regsize
);
2863 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2866 /* Write this portion of the argument to the stack. */
2867 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
2869 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2871 /* Should shorter than int integer values be
2872 promoted to int before being stored? */
2873 int longword_offset
= 0;
2876 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2879 && (typecode
== TYPE_CODE_INT
2880 || typecode
== TYPE_CODE_PTR
2881 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2882 longword_offset
= regsize
- len
;
2883 else if ((typecode
== TYPE_CODE_STRUCT
2884 || typecode
== TYPE_CODE_UNION
)
2885 && TYPE_LENGTH (arg_type
) < regsize
)
2886 longword_offset
= regsize
- len
;
2891 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
2892 paddress (gdbarch
, stack_offset
));
2893 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
2894 paddress (gdbarch
, longword_offset
));
2897 addr
= sp
+ stack_offset
+ longword_offset
;
2902 fprintf_unfiltered (gdb_stdlog
, " @%s ",
2903 paddress (gdbarch
, addr
));
2904 for (i
= 0; i
< partial_len
; i
++)
2906 fprintf_unfiltered (gdb_stdlog
, "%02x",
2910 write_memory (addr
, val
, partial_len
);
2913 /* Note!!! This is NOT an else clause. Odd sized
2914 structs may go thru BOTH paths. Floating point
2915 arguments will not. */
2916 /* Write this portion of the argument to a general
2917 purpose register. */
2918 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
2919 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2922 extract_unsigned_integer (val
, partial_len
);
2925 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2927 phex (regval
, regsize
));
2928 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2935 /* Compute the the offset into the stack at which we
2936 will copy the next parameter.
2938 In the new EABI (and the NABI32), the stack_offset
2939 only needs to be adjusted when it has been used. */
2942 stack_offset
+= align_up (partial_len
, regsize
);
2946 fprintf_unfiltered (gdb_stdlog
, "\n");
2949 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2951 /* Return adjusted stack pointer. */
2955 /* Determine the return value convention being used. */
2957 static enum return_value_convention
2958 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2959 struct type
*type
, struct regcache
*regcache
,
2960 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2962 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2963 int fp_return_type
= 0;
2964 int offset
, regnum
, xfer
;
2966 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2967 return RETURN_VALUE_STRUCT_CONVENTION
;
2969 /* Floating point type? */
2970 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2972 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2974 /* Structs with a single field of float type
2975 are returned in a floating point register. */
2976 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
2977 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2978 && TYPE_NFIELDS (type
) == 1)
2980 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
2982 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
2989 /* A floating-point value belongs in the least significant part
2992 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
2993 regnum
= mips_regnum (gdbarch
)->fp0
;
2997 /* An integer value goes in V0/V1. */
2999 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3000 regnum
= MIPS_V0_REGNUM
;
3003 offset
< TYPE_LENGTH (type
);
3004 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3006 xfer
= mips_abi_regsize (gdbarch
);
3007 if (offset
+ xfer
> TYPE_LENGTH (type
))
3008 xfer
= TYPE_LENGTH (type
) - offset
;
3009 mips_xfer_register (gdbarch
, regcache
,
3010 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3011 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3015 return RETURN_VALUE_REGISTER_CONVENTION
;
3019 /* N32/N64 ABI stuff. */
3021 /* Search for a naturally aligned double at OFFSET inside a struct
3022 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3026 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3031 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3034 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3037 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3040 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3043 struct type
*field_type
;
3045 /* We're only looking at normal fields. */
3046 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3047 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3050 /* If we have gone past the offset, there is no double to pass. */
3051 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3055 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3057 /* If this field is entirely before the requested offset, go
3058 on to the next one. */
3059 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3062 /* If this is our special aligned double, we can stop. */
3063 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3064 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3067 /* This field starts at or before the requested offset, and
3068 overlaps it. If it is a structure, recurse inwards. */
3069 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3076 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3077 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3078 int nargs
, struct value
**args
, CORE_ADDR sp
,
3079 int struct_return
, CORE_ADDR struct_addr
)
3085 int stack_offset
= 0;
3086 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3087 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3089 /* For shared libraries, "t9" needs to point at the function
3091 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3093 /* Set the return address register to point to the entry point of
3094 the program, where a breakpoint lies in wait. */
3095 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3097 /* First ensure that the stack and structure return address (if any)
3098 are properly aligned. The stack has to be at least 64-bit
3099 aligned even on 32-bit machines, because doubles must be 64-bit
3100 aligned. For n32 and n64, stack frames need to be 128-bit
3101 aligned, so we round to this widest known alignment. */
3103 sp
= align_down (sp
, 16);
3104 struct_addr
= align_down (struct_addr
, 16);
3106 /* Now make space on the stack for the args. */
3107 for (argnum
= 0; argnum
< nargs
; argnum
++)
3108 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3109 sp
-= align_up (len
, 16);
3112 fprintf_unfiltered (gdb_stdlog
,
3113 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3114 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3116 /* Initialize the integer and float register pointers. */
3117 argreg
= MIPS_A0_REGNUM
;
3118 float_argreg
= mips_fpa0_regnum (gdbarch
);
3120 /* The struct_return pointer occupies the first parameter-passing reg. */
3124 fprintf_unfiltered (gdb_stdlog
,
3125 "mips_n32n64_push_dummy_call: struct_return reg=%d %s\n",
3126 argreg
, paddress (gdbarch
, struct_addr
));
3127 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3130 /* Now load as many as possible of the first arguments into
3131 registers, and push the rest onto the stack. Loop thru args
3132 from first to last. */
3133 for (argnum
= 0; argnum
< nargs
; argnum
++)
3135 const gdb_byte
*val
;
3136 struct value
*arg
= args
[argnum
];
3137 struct type
*arg_type
= check_typedef (value_type (arg
));
3138 int len
= TYPE_LENGTH (arg_type
);
3139 enum type_code typecode
= TYPE_CODE (arg_type
);
3142 fprintf_unfiltered (gdb_stdlog
,
3143 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3144 argnum
+ 1, len
, (int) typecode
);
3146 val
= value_contents (arg
);
3148 /* A 128-bit long double value requires an even-odd pair of
3149 floating-point registers. */
3151 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3152 && (float_argreg
& 1))
3158 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3159 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3161 /* This is a floating point value that fits entirely
3162 in a single register or a pair of registers. */
3163 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3164 LONGEST regval
= extract_unsigned_integer (val
, reglen
);
3166 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3167 float_argreg
, phex (regval
, reglen
));
3168 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3171 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3172 argreg
, phex (regval
, reglen
));
3173 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3178 regval
= extract_unsigned_integer (val
+ reglen
, reglen
);
3180 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3181 float_argreg
, phex (regval
, reglen
));
3182 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3185 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3186 argreg
, phex (regval
, reglen
));
3187 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3194 /* Copy the argument to general registers or the stack in
3195 register-sized pieces. Large arguments are split between
3196 registers and stack. */
3197 /* For N32/N64, structs, unions, or other composite types are
3198 treated as a sequence of doublewords, and are passed in integer
3199 or floating point registers as though they were simple scalar
3200 parameters to the extent that they fit, with any excess on the
3201 stack packed according to the normal memory layout of the
3203 The caller does not reserve space for the register arguments;
3204 the callee is responsible for reserving it if required. */
3205 /* Note: Floating-point values that didn't fit into an FP
3206 register are only written to memory. */
3209 /* Remember if the argument was written to the stack. */
3210 int stack_used_p
= 0;
3211 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3214 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3217 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3218 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3220 /* Write this portion of the argument to the stack. */
3221 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3223 /* Should shorter than int integer values be
3224 promoted to int before being stored? */
3225 int longword_offset
= 0;
3228 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3230 if ((typecode
== TYPE_CODE_INT
3231 || typecode
== TYPE_CODE_PTR
)
3233 longword_offset
= MIPS64_REGSIZE
- len
;
3238 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3239 paddress (gdbarch
, stack_offset
));
3240 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3241 paddress (gdbarch
, longword_offset
));
3244 addr
= sp
+ stack_offset
+ longword_offset
;
3249 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3250 paddress (gdbarch
, addr
));
3251 for (i
= 0; i
< partial_len
; i
++)
3253 fprintf_unfiltered (gdb_stdlog
, "%02x",
3257 write_memory (addr
, val
, partial_len
);
3260 /* Note!!! This is NOT an else clause. Odd sized
3261 structs may go thru BOTH paths. */
3262 /* Write this portion of the argument to a general
3263 purpose register. */
3264 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3268 /* Sign extend pointers, 32-bit integers and signed
3269 16-bit and 8-bit integers; everything else is taken
3272 if ((partial_len
== 4
3273 && (typecode
== TYPE_CODE_PTR
3274 || typecode
== TYPE_CODE_INT
))
3276 && typecode
== TYPE_CODE_INT
3277 && !TYPE_UNSIGNED (arg_type
)))
3278 regval
= extract_signed_integer (val
, partial_len
);
3280 regval
= extract_unsigned_integer (val
, partial_len
);
3282 /* A non-floating-point argument being passed in a
3283 general register. If a struct or union, and if
3284 the remaining length is smaller than the register
3285 size, we have to adjust the register value on
3288 It does not seem to be necessary to do the
3289 same for integral types. */
3291 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3292 && partial_len
< MIPS64_REGSIZE
3293 && (typecode
== TYPE_CODE_STRUCT
3294 || typecode
== TYPE_CODE_UNION
))
3295 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3299 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3301 phex (regval
, MIPS64_REGSIZE
));
3302 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3304 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3305 TYPE_LENGTH (arg_type
) - len
))
3308 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3310 phex (regval
, MIPS64_REGSIZE
));
3311 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3322 /* Compute the the offset into the stack at which we
3323 will copy the next parameter.
3325 In N32 (N64?), the stack_offset only needs to be
3326 adjusted when it has been used. */
3329 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3333 fprintf_unfiltered (gdb_stdlog
, "\n");
3336 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3338 /* Return adjusted stack pointer. */
3342 static enum return_value_convention
3343 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3344 struct type
*type
, struct regcache
*regcache
,
3345 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3347 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3349 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3351 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3352 if needed), as appropriate for the type. Composite results (struct,
3353 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3356 * A struct with only one or two floating point fields is returned in $f0
3357 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3360 * Any other struct or union results of at most 128 bits are returned in
3361 $2 (first 64 bits) and $3 (remainder, if necessary).
3363 * Larger composite results are handled by converting the function to a
3364 procedure with an implicit first parameter, which is a pointer to an area
3365 reserved by the caller to receive the result. [The o32-bit ABI requires
3366 that all composite results be handled by conversion to implicit first
3367 parameters. The MIPS/SGI Fortran implementation has always made a
3368 specific exception to return COMPLEX results in the floating point
3371 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
3372 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3373 return RETURN_VALUE_STRUCT_CONVENTION
;
3374 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3375 && TYPE_LENGTH (type
) == 16
3376 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3378 /* A 128-bit floating-point value fills both $f0 and $f2. The
3379 two registers are used in the same as memory order, so the
3380 eight bytes with the lower memory address are in $f0. */
3382 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3383 mips_xfer_register (gdbarch
, regcache
,
3384 gdbarch_num_regs (gdbarch
)
3385 + mips_regnum (gdbarch
)->fp0
,
3386 8, gdbarch_byte_order (gdbarch
),
3387 readbuf
, writebuf
, 0);
3388 mips_xfer_register (gdbarch
, regcache
,
3389 gdbarch_num_regs (gdbarch
)
3390 + mips_regnum (gdbarch
)->fp0
+ 2,
3391 8, gdbarch_byte_order (gdbarch
),
3392 readbuf
? readbuf
+ 8 : readbuf
,
3393 writebuf
? writebuf
+ 8 : writebuf
, 0);
3394 return RETURN_VALUE_REGISTER_CONVENTION
;
3396 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3397 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3399 /* A single or double floating-point value that fits in FP0. */
3401 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3402 mips_xfer_register (gdbarch
, regcache
,
3403 gdbarch_num_regs (gdbarch
)
3404 + mips_regnum (gdbarch
)->fp0
,
3406 gdbarch_byte_order (gdbarch
),
3407 readbuf
, writebuf
, 0);
3408 return RETURN_VALUE_REGISTER_CONVENTION
;
3410 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3411 && TYPE_NFIELDS (type
) <= 2
3412 && TYPE_NFIELDS (type
) >= 1
3413 && ((TYPE_NFIELDS (type
) == 1
3414 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3416 || (TYPE_NFIELDS (type
) == 2
3417 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3419 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3420 == TYPE_CODE_FLT
))))
3422 /* A struct that contains one or two floats. Each value is part
3423 in the least significant part of their floating point
3424 register (or GPR, for soft float). */
3427 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3428 ? mips_regnum (gdbarch
)->fp0
3430 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3432 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3435 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3437 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3439 /* A 16-byte long double field goes in two consecutive
3441 mips_xfer_register (gdbarch
, regcache
,
3442 gdbarch_num_regs (gdbarch
) + regnum
,
3444 gdbarch_byte_order (gdbarch
),
3445 readbuf
, writebuf
, offset
);
3446 mips_xfer_register (gdbarch
, regcache
,
3447 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3449 gdbarch_byte_order (gdbarch
),
3450 readbuf
, writebuf
, offset
+ 8);
3453 mips_xfer_register (gdbarch
, regcache
,
3454 gdbarch_num_regs (gdbarch
) + regnum
,
3455 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3456 gdbarch_byte_order (gdbarch
),
3457 readbuf
, writebuf
, offset
);
3459 return RETURN_VALUE_REGISTER_CONVENTION
;
3461 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3462 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3464 /* A structure or union. Extract the left justified value,
3465 regardless of the byte order. I.e. DO NOT USE
3469 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3470 offset
< TYPE_LENGTH (type
);
3471 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3473 int xfer
= register_size (gdbarch
, regnum
);
3474 if (offset
+ xfer
> TYPE_LENGTH (type
))
3475 xfer
= TYPE_LENGTH (type
) - offset
;
3477 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3478 offset
, xfer
, regnum
);
3479 mips_xfer_register (gdbarch
, regcache
,
3480 gdbarch_num_regs (gdbarch
) + regnum
,
3481 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3484 return RETURN_VALUE_REGISTER_CONVENTION
;
3488 /* A scalar extract each part but least-significant-byte
3492 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3493 offset
< TYPE_LENGTH (type
);
3494 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3496 int xfer
= register_size (gdbarch
, regnum
);
3497 if (offset
+ xfer
> TYPE_LENGTH (type
))
3498 xfer
= TYPE_LENGTH (type
) - offset
;
3500 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3501 offset
, xfer
, regnum
);
3502 mips_xfer_register (gdbarch
, regcache
,
3503 gdbarch_num_regs (gdbarch
) + regnum
,
3504 xfer
, gdbarch_byte_order (gdbarch
),
3505 readbuf
, writebuf
, offset
);
3507 return RETURN_VALUE_REGISTER_CONVENTION
;
3511 /* O32 ABI stuff. */
3514 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3515 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3516 int nargs
, struct value
**args
, CORE_ADDR sp
,
3517 int struct_return
, CORE_ADDR struct_addr
)
3523 int stack_offset
= 0;
3524 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3525 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3527 /* For shared libraries, "t9" needs to point at the function
3529 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3531 /* Set the return address register to point to the entry point of
3532 the program, where a breakpoint lies in wait. */
3533 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3535 /* First ensure that the stack and structure return address (if any)
3536 are properly aligned. The stack has to be at least 64-bit
3537 aligned even on 32-bit machines, because doubles must be 64-bit
3538 aligned. For n32 and n64, stack frames need to be 128-bit
3539 aligned, so we round to this widest known alignment. */
3541 sp
= align_down (sp
, 16);
3542 struct_addr
= align_down (struct_addr
, 16);
3544 /* Now make space on the stack for the args. */
3545 for (argnum
= 0; argnum
< nargs
; argnum
++)
3547 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3548 int arglen
= TYPE_LENGTH (arg_type
);
3550 /* Align to double-word if necessary. */
3551 if (mips_type_needs_double_align (arg_type
))
3552 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3553 /* Allocate space on the stack. */
3554 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3556 sp
-= align_up (len
, 16);
3559 fprintf_unfiltered (gdb_stdlog
,
3560 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3561 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3563 /* Initialize the integer and float register pointers. */
3564 argreg
= MIPS_A0_REGNUM
;
3565 float_argreg
= mips_fpa0_regnum (gdbarch
);
3567 /* The struct_return pointer occupies the first parameter-passing reg. */
3571 fprintf_unfiltered (gdb_stdlog
,
3572 "mips_o32_push_dummy_call: struct_return reg=%d %s\n",
3573 argreg
, paddress (gdbarch
, struct_addr
));
3574 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3575 stack_offset
+= MIPS32_REGSIZE
;
3578 /* Now load as many as possible of the first arguments into
3579 registers, and push the rest onto the stack. Loop thru args
3580 from first to last. */
3581 for (argnum
= 0; argnum
< nargs
; argnum
++)
3583 const gdb_byte
*val
;
3584 struct value
*arg
= args
[argnum
];
3585 struct type
*arg_type
= check_typedef (value_type (arg
));
3586 int len
= TYPE_LENGTH (arg_type
);
3587 enum type_code typecode
= TYPE_CODE (arg_type
);
3590 fprintf_unfiltered (gdb_stdlog
,
3591 "mips_o32_push_dummy_call: %d len=%d type=%d",
3592 argnum
+ 1, len
, (int) typecode
);
3594 val
= value_contents (arg
);
3596 /* 32-bit ABIs always start floating point arguments in an
3597 even-numbered floating point register. Round the FP register
3598 up before the check to see if there are any FP registers
3599 left. O32/O64 targets also pass the FP in the integer
3600 registers so also round up normal registers. */
3601 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3603 if ((float_argreg
& 1))
3607 /* Floating point arguments passed in registers have to be
3608 treated specially. On 32-bit architectures, doubles
3609 are passed in register pairs; the even register gets
3610 the low word, and the odd register gets the high word.
3611 On O32/O64, the first two floating point arguments are
3612 also copied to general registers, because MIPS16 functions
3613 don't use float registers for arguments. This duplication of
3614 arguments in general registers can't hurt non-MIPS16 functions
3615 because those registers are normally skipped. */
3617 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3618 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3620 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3622 int low_offset
= gdbarch_byte_order (gdbarch
)
3623 == BFD_ENDIAN_BIG
? 4 : 0;
3624 unsigned long regval
;
3626 /* Write the low word of the double to the even register(s). */
3627 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3629 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3630 float_argreg
, phex (regval
, 4));
3631 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3633 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3634 argreg
, phex (regval
, 4));
3635 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3637 /* Write the high word of the double to the odd register(s). */
3638 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3640 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3641 float_argreg
, phex (regval
, 4));
3642 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3645 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3646 argreg
, phex (regval
, 4));
3647 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3651 /* This is a floating point value that fits entirely
3652 in a single register. */
3653 /* On 32 bit ABI's the float_argreg is further adjusted
3654 above to ensure that it is even register aligned. */
3655 LONGEST regval
= extract_unsigned_integer (val
, len
);
3657 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3658 float_argreg
, phex (regval
, len
));
3659 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3660 /* Although two FP registers are reserved for each
3661 argument, only one corresponding integer register is
3664 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3665 argreg
, phex (regval
, len
));
3666 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3668 /* Reserve space for the FP register. */
3669 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3673 /* Copy the argument to general registers or the stack in
3674 register-sized pieces. Large arguments are split between
3675 registers and stack. */
3676 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3677 are treated specially: Irix cc passes
3678 them in registers where gcc sometimes puts them on the
3679 stack. For maximum compatibility, we will put them in
3681 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3682 && len
% MIPS32_REGSIZE
!= 0);
3683 /* Structures should be aligned to eight bytes (even arg registers)
3684 on MIPS_ABI_O32, if their first member has double precision. */
3685 if (mips_type_needs_double_align (arg_type
))
3690 stack_offset
+= MIPS32_REGSIZE
;
3695 /* Remember if the argument was written to the stack. */
3696 int stack_used_p
= 0;
3697 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3700 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3703 /* Write this portion of the argument to the stack. */
3704 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3705 || odd_sized_struct
)
3707 /* Should shorter than int integer values be
3708 promoted to int before being stored? */
3709 int longword_offset
= 0;
3715 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3716 paddress (gdbarch
, stack_offset
));
3717 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3718 paddress (gdbarch
, longword_offset
));
3721 addr
= sp
+ stack_offset
+ longword_offset
;
3726 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3727 paddress (gdbarch
, addr
));
3728 for (i
= 0; i
< partial_len
; i
++)
3730 fprintf_unfiltered (gdb_stdlog
, "%02x",
3734 write_memory (addr
, val
, partial_len
);
3737 /* Note!!! This is NOT an else clause. Odd sized
3738 structs may go thru BOTH paths. */
3739 /* Write this portion of the argument to a general
3740 purpose register. */
3741 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3743 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3744 /* Value may need to be sign extended, because
3745 mips_isa_regsize() != mips_abi_regsize(). */
3747 /* A non-floating-point argument being passed in a
3748 general register. If a struct or union, and if
3749 the remaining length is smaller than the register
3750 size, we have to adjust the register value on
3753 It does not seem to be necessary to do the
3754 same for integral types.
3756 Also don't do this adjustment on O64 binaries.
3758 cagney/2001-07-23: gdb/179: Also, GCC, when
3759 outputting LE O32 with sizeof (struct) <
3760 mips_abi_regsize(), generates a left shift
3761 as part of storing the argument in a register
3762 (the left shift isn't generated when
3763 sizeof (struct) >= mips_abi_regsize()). Since
3764 it is quite possible that this is GCC
3765 contradicting the LE/O32 ABI, GDB has not been
3766 adjusted to accommodate this. Either someone
3767 needs to demonstrate that the LE/O32 ABI
3768 specifies such a left shift OR this new ABI gets
3769 identified as such and GDB gets tweaked
3772 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3773 && partial_len
< MIPS32_REGSIZE
3774 && (typecode
== TYPE_CODE_STRUCT
3775 || typecode
== TYPE_CODE_UNION
))
3776 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3780 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3782 phex (regval
, MIPS32_REGSIZE
));
3783 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3786 /* Prevent subsequent floating point arguments from
3787 being passed in floating point registers. */
3788 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
3794 /* Compute the the offset into the stack at which we
3795 will copy the next parameter.
3797 In older ABIs, the caller reserved space for
3798 registers that contained arguments. This was loosely
3799 refered to as their "home". Consequently, space is
3800 always allocated. */
3802 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3806 fprintf_unfiltered (gdb_stdlog
, "\n");
3809 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3811 /* Return adjusted stack pointer. */
3815 static enum return_value_convention
3816 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3817 struct type
*type
, struct regcache
*regcache
,
3818 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3820 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3822 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3823 || TYPE_CODE (type
) == TYPE_CODE_UNION
3824 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3825 return RETURN_VALUE_STRUCT_CONVENTION
;
3826 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3827 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3829 /* A single-precision floating-point value. It fits in the
3830 least significant part of FP0. */
3832 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3833 mips_xfer_register (gdbarch
, regcache
,
3834 gdbarch_num_regs (gdbarch
)
3835 + mips_regnum (gdbarch
)->fp0
,
3837 gdbarch_byte_order (gdbarch
),
3838 readbuf
, writebuf
, 0);
3839 return RETURN_VALUE_REGISTER_CONVENTION
;
3841 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3842 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3844 /* A double-precision floating-point value. The most
3845 significant part goes in FP1, and the least significant in
3848 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3849 switch (gdbarch_byte_order (gdbarch
))
3851 case BFD_ENDIAN_LITTLE
:
3852 mips_xfer_register (gdbarch
, regcache
,
3853 gdbarch_num_regs (gdbarch
)
3854 + mips_regnum (gdbarch
)->fp0
+
3855 0, 4, gdbarch_byte_order (gdbarch
),
3856 readbuf
, writebuf
, 0);
3857 mips_xfer_register (gdbarch
, regcache
,
3858 gdbarch_num_regs (gdbarch
)
3859 + mips_regnum (gdbarch
)->fp0
+ 1,
3860 4, gdbarch_byte_order (gdbarch
),
3861 readbuf
, writebuf
, 4);
3863 case BFD_ENDIAN_BIG
:
3864 mips_xfer_register (gdbarch
, regcache
,
3865 gdbarch_num_regs (gdbarch
)
3866 + mips_regnum (gdbarch
)->fp0
+ 1,
3867 4, gdbarch_byte_order (gdbarch
),
3868 readbuf
, writebuf
, 0);
3869 mips_xfer_register (gdbarch
, regcache
,
3870 gdbarch_num_regs (gdbarch
)
3871 + mips_regnum (gdbarch
)->fp0
+ 0,
3872 4, gdbarch_byte_order (gdbarch
),
3873 readbuf
, writebuf
, 4);
3876 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3878 return RETURN_VALUE_REGISTER_CONVENTION
;
3881 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3882 && TYPE_NFIELDS (type
) <= 2
3883 && TYPE_NFIELDS (type
) >= 1
3884 && ((TYPE_NFIELDS (type
) == 1
3885 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3887 || (TYPE_NFIELDS (type
) == 2
3888 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3890 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3892 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3894 /* A struct that contains one or two floats. Each value is part
3895 in the least significant part of their floating point
3897 gdb_byte reg
[MAX_REGISTER_SIZE
];
3900 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3901 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3903 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3906 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3908 mips_xfer_register (gdbarch
, regcache
,
3909 gdbarch_num_regs (gdbarch
) + regnum
,
3910 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3911 gdbarch_byte_order (gdbarch
),
3912 readbuf
, writebuf
, offset
);
3914 return RETURN_VALUE_REGISTER_CONVENTION
;
3918 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3919 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3921 /* A structure or union. Extract the left justified value,
3922 regardless of the byte order. I.e. DO NOT USE
3926 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3927 offset
< TYPE_LENGTH (type
);
3928 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3930 int xfer
= register_size (gdbarch
, regnum
);
3931 if (offset
+ xfer
> TYPE_LENGTH (type
))
3932 xfer
= TYPE_LENGTH (type
) - offset
;
3934 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3935 offset
, xfer
, regnum
);
3936 mips_xfer_register (gdbarch
, regcache
,
3937 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3938 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3940 return RETURN_VALUE_REGISTER_CONVENTION
;
3945 /* A scalar extract each part but least-significant-byte
3946 justified. o32 thinks registers are 4 byte, regardless of
3950 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3951 offset
< TYPE_LENGTH (type
);
3952 offset
+= MIPS32_REGSIZE
, regnum
++)
3954 int xfer
= MIPS32_REGSIZE
;
3955 if (offset
+ xfer
> TYPE_LENGTH (type
))
3956 xfer
= TYPE_LENGTH (type
) - offset
;
3958 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3959 offset
, xfer
, regnum
);
3960 mips_xfer_register (gdbarch
, regcache
,
3961 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3962 gdbarch_byte_order (gdbarch
),
3963 readbuf
, writebuf
, offset
);
3965 return RETURN_VALUE_REGISTER_CONVENTION
;
3969 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3973 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3974 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3976 struct value
**args
, CORE_ADDR sp
,
3977 int struct_return
, CORE_ADDR struct_addr
)
3983 int stack_offset
= 0;
3984 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3985 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3987 /* For shared libraries, "t9" needs to point at the function
3989 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3991 /* Set the return address register to point to the entry point of
3992 the program, where a breakpoint lies in wait. */
3993 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3995 /* First ensure that the stack and structure return address (if any)
3996 are properly aligned. The stack has to be at least 64-bit
3997 aligned even on 32-bit machines, because doubles must be 64-bit
3998 aligned. For n32 and n64, stack frames need to be 128-bit
3999 aligned, so we round to this widest known alignment. */
4001 sp
= align_down (sp
, 16);
4002 struct_addr
= align_down (struct_addr
, 16);
4004 /* Now make space on the stack for the args. */
4005 for (argnum
= 0; argnum
< nargs
; argnum
++)
4007 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4008 int arglen
= TYPE_LENGTH (arg_type
);
4010 /* Allocate space on the stack. */
4011 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4013 sp
-= align_up (len
, 16);
4016 fprintf_unfiltered (gdb_stdlog
,
4017 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4018 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4020 /* Initialize the integer and float register pointers. */
4021 argreg
= MIPS_A0_REGNUM
;
4022 float_argreg
= mips_fpa0_regnum (gdbarch
);
4024 /* The struct_return pointer occupies the first parameter-passing reg. */
4028 fprintf_unfiltered (gdb_stdlog
,
4029 "mips_o64_push_dummy_call: struct_return reg=%d %s\n",
4030 argreg
, paddress (gdbarch
, struct_addr
));
4031 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4032 stack_offset
+= MIPS64_REGSIZE
;
4035 /* Now load as many as possible of the first arguments into
4036 registers, and push the rest onto the stack. Loop thru args
4037 from first to last. */
4038 for (argnum
= 0; argnum
< nargs
; argnum
++)
4040 const gdb_byte
*val
;
4041 struct value
*arg
= args
[argnum
];
4042 struct type
*arg_type
= check_typedef (value_type (arg
));
4043 int len
= TYPE_LENGTH (arg_type
);
4044 enum type_code typecode
= TYPE_CODE (arg_type
);
4047 fprintf_unfiltered (gdb_stdlog
,
4048 "mips_o64_push_dummy_call: %d len=%d type=%d",
4049 argnum
+ 1, len
, (int) typecode
);
4051 val
= value_contents (arg
);
4053 /* Floating point arguments passed in registers have to be
4054 treated specially. On 32-bit architectures, doubles
4055 are passed in register pairs; the even register gets
4056 the low word, and the odd register gets the high word.
4057 On O32/O64, the first two floating point arguments are
4058 also copied to general registers, because MIPS16 functions
4059 don't use float registers for arguments. This duplication of
4060 arguments in general registers can't hurt non-MIPS16 functions
4061 because those registers are normally skipped. */
4063 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4064 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4066 LONGEST regval
= extract_unsigned_integer (val
, len
);
4068 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4069 float_argreg
, phex (regval
, len
));
4070 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4072 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4073 argreg
, phex (regval
, len
));
4074 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4076 /* Reserve space for the FP register. */
4077 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4081 /* Copy the argument to general registers or the stack in
4082 register-sized pieces. Large arguments are split between
4083 registers and stack. */
4084 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4085 are treated specially: Irix cc passes them in registers
4086 where gcc sometimes puts them on the stack. For maximum
4087 compatibility, we will put them in both places. */
4088 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4089 && len
% MIPS64_REGSIZE
!= 0);
4092 /* Remember if the argument was written to the stack. */
4093 int stack_used_p
= 0;
4094 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4097 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4100 /* Write this portion of the argument to the stack. */
4101 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4102 || odd_sized_struct
)
4104 /* Should shorter than int integer values be
4105 promoted to int before being stored? */
4106 int longword_offset
= 0;
4109 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4111 if ((typecode
== TYPE_CODE_INT
4112 || typecode
== TYPE_CODE_PTR
4113 || typecode
== TYPE_CODE_FLT
)
4115 longword_offset
= MIPS64_REGSIZE
- len
;
4120 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4121 paddress (gdbarch
, stack_offset
));
4122 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4123 paddress (gdbarch
, longword_offset
));
4126 addr
= sp
+ stack_offset
+ longword_offset
;
4131 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4132 paddress (gdbarch
, addr
));
4133 for (i
= 0; i
< partial_len
; i
++)
4135 fprintf_unfiltered (gdb_stdlog
, "%02x",
4139 write_memory (addr
, val
, partial_len
);
4142 /* Note!!! This is NOT an else clause. Odd sized
4143 structs may go thru BOTH paths. */
4144 /* Write this portion of the argument to a general
4145 purpose register. */
4146 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4148 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4149 /* Value may need to be sign extended, because
4150 mips_isa_regsize() != mips_abi_regsize(). */
4152 /* A non-floating-point argument being passed in a
4153 general register. If a struct or union, and if
4154 the remaining length is smaller than the register
4155 size, we have to adjust the register value on
4158 It does not seem to be necessary to do the
4159 same for integral types. */
4161 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4162 && partial_len
< MIPS64_REGSIZE
4163 && (typecode
== TYPE_CODE_STRUCT
4164 || typecode
== TYPE_CODE_UNION
))
4165 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4169 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4171 phex (regval
, MIPS64_REGSIZE
));
4172 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4175 /* Prevent subsequent floating point arguments from
4176 being passed in floating point registers. */
4177 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4183 /* Compute the the offset into the stack at which we
4184 will copy the next parameter.
4186 In older ABIs, the caller reserved space for
4187 registers that contained arguments. This was loosely
4188 refered to as their "home". Consequently, space is
4189 always allocated. */
4191 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4195 fprintf_unfiltered (gdb_stdlog
, "\n");
4198 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4200 /* Return adjusted stack pointer. */
4204 static enum return_value_convention
4205 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4206 struct type
*type
, struct regcache
*regcache
,
4207 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4209 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4211 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4212 || TYPE_CODE (type
) == TYPE_CODE_UNION
4213 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4214 return RETURN_VALUE_STRUCT_CONVENTION
;
4215 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4217 /* A floating-point value. It fits in the least significant
4220 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4221 mips_xfer_register (gdbarch
, regcache
,
4222 gdbarch_num_regs (gdbarch
)
4223 + mips_regnum (gdbarch
)->fp0
,
4225 gdbarch_byte_order (gdbarch
),
4226 readbuf
, writebuf
, 0);
4227 return RETURN_VALUE_REGISTER_CONVENTION
;
4231 /* A scalar extract each part but least-significant-byte
4235 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4236 offset
< TYPE_LENGTH (type
);
4237 offset
+= MIPS64_REGSIZE
, regnum
++)
4239 int xfer
= MIPS64_REGSIZE
;
4240 if (offset
+ xfer
> TYPE_LENGTH (type
))
4241 xfer
= TYPE_LENGTH (type
) - offset
;
4243 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4244 offset
, xfer
, regnum
);
4245 mips_xfer_register (gdbarch
, regcache
,
4246 gdbarch_num_regs (gdbarch
) + regnum
,
4247 xfer
, gdbarch_byte_order (gdbarch
),
4248 readbuf
, writebuf
, offset
);
4250 return RETURN_VALUE_REGISTER_CONVENTION
;
4254 /* Floating point register management.
4256 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4257 64bit operations, these early MIPS cpus treat fp register pairs
4258 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4259 registers and offer a compatibility mode that emulates the MIPS2 fp
4260 model. When operating in MIPS2 fp compat mode, later cpu's split
4261 double precision floats into two 32-bit chunks and store them in
4262 consecutive fp regs. To display 64-bit floats stored in this
4263 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4264 Throw in user-configurable endianness and you have a real mess.
4266 The way this works is:
4267 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4268 double-precision value will be split across two logical registers.
4269 The lower-numbered logical register will hold the low-order bits,
4270 regardless of the processor's endianness.
4271 - If we are on a 64-bit processor, and we are looking for a
4272 single-precision value, it will be in the low ordered bits
4273 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4274 save slot in memory.
4275 - If we are in 64-bit mode, everything is straightforward.
4277 Note that this code only deals with "live" registers at the top of the
4278 stack. We will attempt to deal with saved registers later, when
4279 the raw/cooked register interface is in place. (We need a general
4280 interface that can deal with dynamic saved register sizes -- fp
4281 regs could be 32 bits wide in one frame and 64 on the frame above
4284 /* Copy a 32-bit single-precision value from the current frame
4285 into rare_buffer. */
4288 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4289 gdb_byte
*rare_buffer
)
4291 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4292 int raw_size
= register_size (gdbarch
, regno
);
4293 gdb_byte
*raw_buffer
= alloca (raw_size
);
4295 if (!frame_register_read (frame
, regno
, raw_buffer
))
4296 error (_("can't read register %d (%s)"),
4297 regno
, gdbarch_register_name (gdbarch
, regno
));
4300 /* We have a 64-bit value for this register. Find the low-order
4304 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4309 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4313 memcpy (rare_buffer
, raw_buffer
, 4);
4317 /* Copy a 64-bit double-precision value from the current frame into
4318 rare_buffer. This may include getting half of it from the next
4322 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4323 gdb_byte
*rare_buffer
)
4325 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4326 int raw_size
= register_size (gdbarch
, regno
);
4328 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4330 /* We have a 64-bit value for this register, and we should use
4332 if (!frame_register_read (frame
, regno
, rare_buffer
))
4333 error (_("can't read register %d (%s)"),
4334 regno
, gdbarch_register_name (gdbarch
, regno
));
4338 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4340 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4341 internal_error (__FILE__
, __LINE__
,
4342 _("mips_read_fp_register_double: bad access to "
4343 "odd-numbered FP register"));
4345 /* mips_read_fp_register_single will find the correct 32 bits from
4347 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4349 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4350 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4354 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4355 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4361 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4363 { /* do values for FP (float) regs */
4364 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4365 gdb_byte
*raw_buffer
;
4366 double doub
, flt1
; /* doubles extracted from raw hex data */
4369 raw_buffer
= alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
));
4371 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4372 fprintf_filtered (file
, "%*s",
4373 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4376 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4378 struct value_print_options opts
;
4380 /* 4-byte registers: Print hex and floating. Also print even
4381 numbered registers as doubles. */
4382 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4383 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
, raw_buffer
, &inv1
);
4385 get_formatted_print_options (&opts
, 'x');
4386 print_scalar_formatted (raw_buffer
,
4387 builtin_type (gdbarch
)->builtin_uint32
,
4390 fprintf_filtered (file
, " flt: ");
4392 fprintf_filtered (file
, " <invalid float> ");
4394 fprintf_filtered (file
, "%-17.9g", flt1
);
4396 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4398 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4399 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4402 fprintf_filtered (file
, " dbl: ");
4404 fprintf_filtered (file
, "<invalid double>");
4406 fprintf_filtered (file
, "%-24.17g", doub
);
4411 struct value_print_options opts
;
4413 /* Eight byte registers: print each one as hex, float and double. */
4414 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4415 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4418 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4419 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4422 get_formatted_print_options (&opts
, 'x');
4423 print_scalar_formatted (raw_buffer
,
4424 builtin_type (gdbarch
)->builtin_uint64
,
4427 fprintf_filtered (file
, " flt: ");
4429 fprintf_filtered (file
, "<invalid float>");
4431 fprintf_filtered (file
, "%-17.9g", flt1
);
4433 fprintf_filtered (file
, " dbl: ");
4435 fprintf_filtered (file
, "<invalid double>");
4437 fprintf_filtered (file
, "%-24.17g", doub
);
4442 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4445 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4446 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4448 struct value_print_options opts
;
4450 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4452 mips_print_fp_register (file
, frame
, regnum
);
4456 /* Get the data in raw format. */
4457 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4459 fprintf_filtered (file
, "%s: [Invalid]",
4460 gdbarch_register_name (gdbarch
, regnum
));
4464 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4466 /* The problem with printing numeric register names (r26, etc.) is that
4467 the user can't use them on input. Probably the best solution is to
4468 fix it so that either the numeric or the funky (a2, etc.) names
4469 are accepted on input. */
4470 if (regnum
< MIPS_NUMREGS
)
4471 fprintf_filtered (file
, "(r%d): ", regnum
);
4473 fprintf_filtered (file
, ": ");
4475 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4477 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4481 get_formatted_print_options (&opts
, 'x');
4482 print_scalar_formatted (raw_buffer
+ offset
,
4483 register_type (gdbarch
, regnum
), &opts
, 0,
4487 /* Replacement for generic do_registers_info.
4488 Print regs in pretty columns. */
4491 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4494 fprintf_filtered (file
, " ");
4495 mips_print_fp_register (file
, frame
, regnum
);
4496 fprintf_filtered (file
, "\n");
4501 /* Print a row's worth of GP (int) registers, with name labels above */
4504 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4507 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4508 /* do values for GP (int) regs */
4509 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4510 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4514 /* For GP registers, we print a separate row of names above the vals */
4515 for (col
= 0, regnum
= start_regnum
;
4516 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4517 + gdbarch_num_pseudo_regs (gdbarch
);
4520 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4521 continue; /* unused register */
4522 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4524 break; /* end the row: reached FP register */
4525 /* Large registers are handled separately. */
4526 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4529 break; /* End the row before this register. */
4531 /* Print this register on a row by itself. */
4532 mips_print_register (file
, frame
, regnum
);
4533 fprintf_filtered (file
, "\n");
4537 fprintf_filtered (file
, " ");
4538 fprintf_filtered (file
,
4539 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4540 gdbarch_register_name (gdbarch
, regnum
));
4547 /* print the R0 to R31 names */
4548 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4549 fprintf_filtered (file
, "\n R%-4d",
4550 start_regnum
% gdbarch_num_regs (gdbarch
));
4552 fprintf_filtered (file
, "\n ");
4554 /* now print the values in hex, 4 or 8 to the row */
4555 for (col
= 0, regnum
= start_regnum
;
4556 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4557 + gdbarch_num_pseudo_regs (gdbarch
);
4560 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4561 continue; /* unused register */
4562 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4564 break; /* end row: reached FP register */
4565 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4566 break; /* End row: large register. */
4568 /* OK: get the data in raw format. */
4569 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4570 error (_("can't read register %d (%s)"),
4571 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4572 /* pad small registers */
4574 byte
< (mips_abi_regsize (gdbarch
)
4575 - register_size (gdbarch
, regnum
)); byte
++)
4576 printf_filtered (" ");
4577 /* Now print the register value in hex, endian order. */
4578 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4580 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4581 byte
< register_size (gdbarch
, regnum
); byte
++)
4582 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4584 for (byte
= register_size (gdbarch
, regnum
) - 1;
4586 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4587 fprintf_filtered (file
, " ");
4590 if (col
> 0) /* ie. if we actually printed anything... */
4591 fprintf_filtered (file
, "\n");
4596 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4599 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4600 struct frame_info
*frame
, int regnum
, int all
)
4602 if (regnum
!= -1) /* do one specified register */
4604 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4605 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4606 error (_("Not a valid register for the current processor type"));
4608 mips_print_register (file
, frame
, regnum
);
4609 fprintf_filtered (file
, "\n");
4612 /* do all (or most) registers */
4614 regnum
= gdbarch_num_regs (gdbarch
);
4615 while (regnum
< gdbarch_num_regs (gdbarch
)
4616 + gdbarch_num_pseudo_regs (gdbarch
))
4618 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4621 if (all
) /* true for "INFO ALL-REGISTERS" command */
4622 regnum
= print_fp_register_row (file
, frame
, regnum
);
4624 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4627 regnum
= print_gp_register_row (file
, frame
, regnum
);
4632 /* Is this a branch with a delay slot? */
4635 is_delayed (unsigned long insn
)
4638 for (i
= 0; i
< NUMOPCODES
; ++i
)
4639 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4640 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4642 return (i
< NUMOPCODES
4643 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4644 | INSN_COND_BRANCH_DELAY
4645 | INSN_COND_BRANCH_LIKELY
)));
4649 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4650 struct frame_info
*frame
)
4652 CORE_ADDR pc
= get_frame_pc (frame
);
4653 gdb_byte buf
[MIPS_INSN32_SIZE
];
4655 /* There is no branch delay slot on MIPS16. */
4656 if (mips_pc_is_mips16 (pc
))
4659 if (!breakpoint_here_p (pc
+ 4))
4662 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4663 /* If error reading memory, guess that it is not a delayed
4666 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4669 /* To skip prologues, I use this predicate. Returns either PC itself
4670 if the code at PC does not look like a function prologue; otherwise
4671 returns an address that (if we're lucky) follows the prologue. If
4672 LENIENT, then we must skip everything which is involved in setting
4673 up the frame (it's OK to skip more, just so long as we don't skip
4674 anything which might clobber the registers which are being saved.
4675 We must skip more in the case where part of the prologue is in the
4676 delay slot of a non-prologue instruction). */
4679 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4682 CORE_ADDR func_addr
;
4684 /* See if we can determine the end of the prologue via the symbol table.
4685 If so, then return either PC, or the PC after the prologue, whichever
4687 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4689 CORE_ADDR post_prologue_pc
4690 = skip_prologue_using_sal (gdbarch
, func_addr
);
4691 if (post_prologue_pc
!= 0)
4692 return max (pc
, post_prologue_pc
);
4695 /* Can't determine prologue from the symbol table, need to examine
4698 /* Find an upper limit on the function prologue using the debug
4699 information. If the debug information could not be used to provide
4700 that bound, then use an arbitrary large number as the upper bound. */
4701 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
4703 limit_pc
= pc
+ 100; /* Magic. */
4705 if (mips_pc_is_mips16 (pc
))
4706 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4708 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4711 /* Check whether the PC is in a function epilogue (32-bit version).
4712 This is a helper function for mips_in_function_epilogue_p. */
4714 mips32_in_function_epilogue_p (CORE_ADDR pc
)
4716 CORE_ADDR func_addr
= 0, func_end
= 0;
4718 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4720 /* The MIPS epilogue is max. 12 bytes long. */
4721 CORE_ADDR addr
= func_end
- 12;
4723 if (addr
< func_addr
+ 4)
4724 addr
= func_addr
+ 4;
4728 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4730 unsigned long high_word
;
4733 inst
= mips_fetch_instruction (pc
);
4734 high_word
= (inst
>> 16) & 0xffff;
4736 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4737 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4738 && inst
!= 0x03e00008 /* jr $ra */
4739 && inst
!= 0x00000000) /* nop */
4749 /* Check whether the PC is in a function epilogue (16-bit version).
4750 This is a helper function for mips_in_function_epilogue_p. */
4752 mips16_in_function_epilogue_p (CORE_ADDR pc
)
4754 CORE_ADDR func_addr
= 0, func_end
= 0;
4756 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4758 /* The MIPS epilogue is max. 12 bytes long. */
4759 CORE_ADDR addr
= func_end
- 12;
4761 if (addr
< func_addr
+ 4)
4762 addr
= func_addr
+ 4;
4766 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4768 unsigned short inst
;
4770 inst
= mips_fetch_instruction (pc
);
4772 if ((inst
& 0xf800) == 0xf000) /* extend */
4775 if (inst
!= 0x6300 /* addiu $sp,offset */
4776 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
4777 && inst
!= 0xe820 /* jr $ra */
4778 && inst
!= 0xe8a0 /* jrc $ra */
4779 && inst
!= 0x6500) /* nop */
4789 /* The epilogue is defined here as the area at the end of a function,
4790 after an instruction which destroys the function's stack frame. */
4792 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4794 if (mips_pc_is_mips16 (pc
))
4795 return mips16_in_function_epilogue_p (pc
);
4797 return mips32_in_function_epilogue_p (pc
);
4800 /* Root of all "set mips "/"show mips " commands. This will eventually be
4801 used for all MIPS-specific commands. */
4804 show_mips_command (char *args
, int from_tty
)
4806 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4810 set_mips_command (char *args
, int from_tty
)
4813 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4814 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4817 /* Commands to show/set the MIPS FPU type. */
4820 show_mipsfpu_command (char *args
, int from_tty
)
4824 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
4827 ("The MIPS floating-point coprocessor is unknown "
4828 "because the current architecture is not MIPS.\n");
4832 switch (MIPS_FPU_TYPE (target_gdbarch
))
4834 case MIPS_FPU_SINGLE
:
4835 fpu
= "single-precision";
4837 case MIPS_FPU_DOUBLE
:
4838 fpu
= "double-precision";
4841 fpu
= "absent (none)";
4844 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4846 if (mips_fpu_type_auto
)
4848 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4852 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4857 set_mipsfpu_command (char *args
, int from_tty
)
4860 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4861 show_mipsfpu_command (args
, from_tty
);
4865 set_mipsfpu_single_command (char *args
, int from_tty
)
4867 struct gdbarch_info info
;
4868 gdbarch_info_init (&info
);
4869 mips_fpu_type
= MIPS_FPU_SINGLE
;
4870 mips_fpu_type_auto
= 0;
4871 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4872 instead of relying on globals. Doing that would let generic code
4873 handle the search for this specific architecture. */
4874 if (!gdbarch_update_p (info
))
4875 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4879 set_mipsfpu_double_command (char *args
, int from_tty
)
4881 struct gdbarch_info info
;
4882 gdbarch_info_init (&info
);
4883 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4884 mips_fpu_type_auto
= 0;
4885 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4886 instead of relying on globals. Doing that would let generic code
4887 handle the search for this specific architecture. */
4888 if (!gdbarch_update_p (info
))
4889 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4893 set_mipsfpu_none_command (char *args
, int from_tty
)
4895 struct gdbarch_info info
;
4896 gdbarch_info_init (&info
);
4897 mips_fpu_type
= MIPS_FPU_NONE
;
4898 mips_fpu_type_auto
= 0;
4899 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4900 instead of relying on globals. Doing that would let generic code
4901 handle the search for this specific architecture. */
4902 if (!gdbarch_update_p (info
))
4903 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4907 set_mipsfpu_auto_command (char *args
, int from_tty
)
4909 mips_fpu_type_auto
= 1;
4912 /* Attempt to identify the particular processor model by reading the
4913 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4914 the relevant processor still exists (it dates back to '94) and
4915 secondly this is not the way to do this. The processor type should
4916 be set by forcing an architecture change. */
4919 deprecated_mips_set_processor_regs_hack (void)
4921 struct regcache
*regcache
= get_current_regcache ();
4922 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
4923 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4926 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
4927 if ((prid
& ~0xf) == 0x700)
4928 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4931 /* Just like reinit_frame_cache, but with the right arguments to be
4932 callable as an sfunc. */
4935 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4936 struct cmd_list_element
*c
)
4938 reinit_frame_cache ();
4942 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4944 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4945 disassembler needs to be able to locally determine the ISA, and
4946 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4948 if (mips_pc_is_mips16 (memaddr
))
4949 info
->mach
= bfd_mach_mips16
;
4951 /* Round down the instruction address to the appropriate boundary. */
4952 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4954 /* Set the disassembler options. */
4955 if (!info
->disassembler_options
)
4956 /* This string is not recognized explicitly by the disassembler,
4957 but it tells the disassembler to not try to guess the ABI from
4958 the bfd elf headers, such that, if the user overrides the ABI
4959 of a program linked as NewABI, the disassembly will follow the
4960 register naming conventions specified by the user. */
4961 info
->disassembler_options
= "gpr-names=32";
4963 /* Call the appropriate disassembler based on the target endian-ness. */
4964 if (info
->endian
== BFD_ENDIAN_BIG
)
4965 return print_insn_big_mips (memaddr
, info
);
4967 return print_insn_little_mips (memaddr
, info
);
4971 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
4973 /* Set up the disassembler info, so that we get the right
4974 register names from libopcodes. */
4975 info
->disassembler_options
= "gpr-names=n32";
4976 info
->flavour
= bfd_target_elf_flavour
;
4978 return gdb_print_insn_mips (memaddr
, info
);
4982 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
4984 /* Set up the disassembler info, so that we get the right
4985 register names from libopcodes. */
4986 info
->disassembler_options
= "gpr-names=64";
4987 info
->flavour
= bfd_target_elf_flavour
;
4989 return gdb_print_insn_mips (memaddr
, info
);
4992 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4993 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4994 It returns a pointer to a string of bytes that encode a breakpoint
4995 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4996 necessary) to point to the actual memory location where the breakpoint
4997 should be inserted. */
4999 static const gdb_byte
*
5000 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
5002 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5004 if (mips_pc_is_mips16 (*pcptr
))
5006 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5007 *pcptr
= unmake_mips16_addr (*pcptr
);
5008 *lenptr
= sizeof (mips16_big_breakpoint
);
5009 return mips16_big_breakpoint
;
5013 /* The IDT board uses an unusual breakpoint value, and
5014 sometimes gets confused when it sees the usual MIPS
5015 breakpoint instruction. */
5016 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5017 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5018 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5020 *lenptr
= sizeof (big_breakpoint
);
5022 if (strcmp (target_shortname
, "mips") == 0)
5023 return idt_big_breakpoint
;
5024 else if (strcmp (target_shortname
, "ddb") == 0
5025 || strcmp (target_shortname
, "pmon") == 0
5026 || strcmp (target_shortname
, "lsi") == 0)
5027 return pmon_big_breakpoint
;
5029 return big_breakpoint
;
5034 if (mips_pc_is_mips16 (*pcptr
))
5036 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5037 *pcptr
= unmake_mips16_addr (*pcptr
);
5038 *lenptr
= sizeof (mips16_little_breakpoint
);
5039 return mips16_little_breakpoint
;
5043 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5044 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5045 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5047 *lenptr
= sizeof (little_breakpoint
);
5049 if (strcmp (target_shortname
, "mips") == 0)
5050 return idt_little_breakpoint
;
5051 else if (strcmp (target_shortname
, "ddb") == 0
5052 || strcmp (target_shortname
, "pmon") == 0
5053 || strcmp (target_shortname
, "lsi") == 0)
5054 return pmon_little_breakpoint
;
5056 return little_breakpoint
;
5061 /* If PC is in a mips16 call or return stub, return the address of the target
5062 PC, which is either the callee or the caller. There are several
5063 cases which must be handled:
5065 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5066 target PC is in $31 ($ra).
5067 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5068 and the target PC is in $2.
5069 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5070 before the jal instruction, this is effectively a call stub
5071 and the the target PC is in $2. Otherwise this is effectively
5072 a return stub and the target PC is in $18.
5074 See the source code for the stubs in gcc/config/mips/mips16.S for
5078 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5081 CORE_ADDR start_addr
;
5083 /* Find the starting address and name of the function containing the PC. */
5084 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5087 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5088 target PC is in $31 ($ra). */
5089 if (strcmp (name
, "__mips16_ret_sf") == 0
5090 || strcmp (name
, "__mips16_ret_df") == 0)
5091 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5093 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5095 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5096 and the target PC is in $2. */
5097 if (name
[19] >= '0' && name
[19] <= '9')
5098 return get_frame_register_signed (frame
, 2);
5100 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5101 before the jal instruction, this is effectively a call stub
5102 and the the target PC is in $2. Otherwise this is effectively
5103 a return stub and the target PC is in $18. */
5104 else if (name
[19] == 's' || name
[19] == 'd')
5106 if (pc
== start_addr
)
5108 /* Check if the target of the stub is a compiler-generated
5109 stub. Such a stub for a function bar might have a name
5110 like __fn_stub_bar, and might look like this:
5115 la $1,bar (becomes a lui/addiu pair)
5117 So scan down to the lui/addi and extract the target
5118 address from those two instructions. */
5120 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5124 /* See if the name of the target function is __fn_stub_*. */
5125 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5128 if (strncmp (name
, "__fn_stub_", 10) != 0
5129 && strcmp (name
, "etext") != 0
5130 && strcmp (name
, "_etext") != 0)
5133 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5134 The limit on the search is arbitrarily set to 20
5135 instructions. FIXME. */
5136 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5138 inst
= mips_fetch_instruction (target_pc
);
5139 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5140 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5141 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5142 return pc
| (inst
& 0xffff); /* low word */
5145 /* Couldn't find the lui/addui pair, so return stub address. */
5149 /* This is the 'return' part of a call stub. The return
5150 address is in $r18. */
5151 return get_frame_register_signed (frame
, 18);
5154 return 0; /* not a stub */
5157 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5158 PC of the stub target. The stub just loads $t9 and jumps to it,
5159 so that $t9 has the correct value at function entry. */
5162 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5164 struct minimal_symbol
*msym
;
5166 gdb_byte stub_code
[16];
5167 int32_t stub_words
[4];
5169 /* The stub for foo is named ".pic.foo", and is either two
5170 instructions inserted before foo or a three instruction sequence
5171 which jumps to foo. */
5172 msym
= lookup_minimal_symbol_by_pc (pc
);
5174 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5175 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5176 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5179 /* A two-instruction header. */
5180 if (MSYMBOL_SIZE (msym
) == 8)
5183 /* A three-instruction (plus delay slot) trampoline. */
5184 if (MSYMBOL_SIZE (msym
) == 16)
5186 if (target_read_memory (pc
, stub_code
, 16) != 0)
5188 for (i
= 0; i
< 4; i
++)
5189 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4, 4);
5191 /* A stub contains these instructions:
5194 addiu t9, t9, %lo(target)
5197 This works even for N64, since stubs are only generated with
5199 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5200 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5201 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5202 && stub_words
[3] == 0x00000000)
5203 return (((stub_words
[0] & 0x0000ffff) << 16)
5204 + (stub_words
[2] & 0x0000ffff));
5207 /* Not a recognized stub. */
5212 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5214 CORE_ADDR target_pc
;
5216 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5220 target_pc
= find_solib_trampoline_target (frame
, pc
);
5224 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5231 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5232 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5235 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5238 if (num
>= 0 && num
< 32)
5240 else if (num
>= 38 && num
< 70)
5241 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5243 regnum
= mips_regnum (gdbarch
)->hi
;
5245 regnum
= mips_regnum (gdbarch
)->lo
;
5247 /* This will hopefully (eventually) provoke a warning. Should
5248 we be calling complaint() here? */
5249 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5250 return gdbarch_num_regs (gdbarch
) + regnum
;
5254 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5255 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5258 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5261 if (num
>= 0 && num
< 32)
5263 else if (num
>= 32 && num
< 64)
5264 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5266 regnum
= mips_regnum (gdbarch
)->hi
;
5268 regnum
= mips_regnum (gdbarch
)->lo
;
5270 /* This will hopefully (eventually) provoke a warning. Should we
5271 be calling complaint() here? */
5272 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5273 return gdbarch_num_regs (gdbarch
) + regnum
;
5277 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5279 /* Only makes sense to supply raw registers. */
5280 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5281 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5282 decide if it is valid. Should instead define a standard sim/gdb
5283 register numbering scheme. */
5284 if (gdbarch_register_name (gdbarch
,
5285 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5286 && gdbarch_register_name (gdbarch
,
5287 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
5290 return LEGACY_SIM_REGNO_IGNORE
;
5294 /* Convert an integer into an address. Extracting the value signed
5295 guarantees a correctly sign extended address. */
5298 mips_integer_to_address (struct gdbarch
*gdbarch
,
5299 struct type
*type
, const gdb_byte
*buf
)
5301 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
5304 /* Dummy virtual frame pointer method. This is no more or less accurate
5305 than most other architectures; we just need to be explicit about it,
5306 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5307 an assertion failure. */
5310 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5311 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5313 *reg
= MIPS_SP_REGNUM
;
5318 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5320 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5321 const char *name
= bfd_get_section_name (abfd
, sect
);
5323 if (*abip
!= MIPS_ABI_UNKNOWN
)
5326 if (strncmp (name
, ".mdebug.", 8) != 0)
5329 if (strcmp (name
, ".mdebug.abi32") == 0)
5330 *abip
= MIPS_ABI_O32
;
5331 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5332 *abip
= MIPS_ABI_N32
;
5333 else if (strcmp (name
, ".mdebug.abi64") == 0)
5334 *abip
= MIPS_ABI_N64
;
5335 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5336 *abip
= MIPS_ABI_O64
;
5337 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5338 *abip
= MIPS_ABI_EABI32
;
5339 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5340 *abip
= MIPS_ABI_EABI64
;
5342 warning (_("unsupported ABI %s."), name
+ 8);
5346 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5348 int *lbp
= (int *) obj
;
5349 const char *name
= bfd_get_section_name (abfd
, sect
);
5351 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5353 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5355 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5356 warning (_("unrecognized .gcc_compiled_longXX"));
5359 static enum mips_abi
5360 global_mips_abi (void)
5364 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5365 if (mips_abi_strings
[i
] == mips_abi_string
)
5366 return (enum mips_abi
) i
;
5368 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5372 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5374 /* If the size matches the set of 32-bit or 64-bit integer registers,
5375 assume that's what we've got. */
5376 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5377 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5379 /* If the size matches the full set of registers GDB traditionally
5380 knows about, including floating point, for either 32-bit or
5381 64-bit, assume that's what we've got. */
5382 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5383 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5385 /* Otherwise we don't have a useful guess. */
5388 static struct value
*
5389 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5391 const int *reg_p
= baton
;
5392 return value_of_register (*reg_p
, frame
);
5395 static struct gdbarch
*
5396 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5398 struct gdbarch
*gdbarch
;
5399 struct gdbarch_tdep
*tdep
;
5401 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5403 enum mips_fpu_type fpu_type
;
5404 struct tdesc_arch_data
*tdesc_data
= NULL
;
5405 int elf_fpu_type
= 0;
5407 /* Check any target description for validity. */
5408 if (tdesc_has_registers (info
.target_desc
))
5410 static const char *const mips_gprs
[] = {
5411 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5412 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5413 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5414 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5416 static const char *const mips_fprs
[] = {
5417 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5418 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5419 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5420 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5423 const struct tdesc_feature
*feature
;
5426 feature
= tdesc_find_feature (info
.target_desc
,
5427 "org.gnu.gdb.mips.cpu");
5428 if (feature
== NULL
)
5431 tdesc_data
= tdesc_data_alloc ();
5434 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5435 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5439 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5440 MIPS_EMBED_LO_REGNUM
, "lo");
5441 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5442 MIPS_EMBED_HI_REGNUM
, "hi");
5443 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5444 MIPS_EMBED_PC_REGNUM
, "pc");
5448 tdesc_data_cleanup (tdesc_data
);
5452 feature
= tdesc_find_feature (info
.target_desc
,
5453 "org.gnu.gdb.mips.cp0");
5454 if (feature
== NULL
)
5456 tdesc_data_cleanup (tdesc_data
);
5461 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5462 MIPS_EMBED_BADVADDR_REGNUM
,
5464 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5465 MIPS_PS_REGNUM
, "status");
5466 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5467 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5471 tdesc_data_cleanup (tdesc_data
);
5475 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5476 backend is not prepared for that, though. */
5477 feature
= tdesc_find_feature (info
.target_desc
,
5478 "org.gnu.gdb.mips.fpu");
5479 if (feature
== NULL
)
5481 tdesc_data_cleanup (tdesc_data
);
5486 for (i
= 0; i
< 32; i
++)
5487 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5488 i
+ MIPS_EMBED_FP0_REGNUM
,
5491 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5492 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5493 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5494 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5498 tdesc_data_cleanup (tdesc_data
);
5502 /* It would be nice to detect an attempt to use a 64-bit ABI
5503 when only 32-bit registers are provided. */
5506 /* First of all, extract the elf_flags, if available. */
5507 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5508 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5509 else if (arches
!= NULL
)
5510 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5514 fprintf_unfiltered (gdb_stdlog
,
5515 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5517 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5518 switch ((elf_flags
& EF_MIPS_ABI
))
5520 case E_MIPS_ABI_O32
:
5521 found_abi
= MIPS_ABI_O32
;
5523 case E_MIPS_ABI_O64
:
5524 found_abi
= MIPS_ABI_O64
;
5526 case E_MIPS_ABI_EABI32
:
5527 found_abi
= MIPS_ABI_EABI32
;
5529 case E_MIPS_ABI_EABI64
:
5530 found_abi
= MIPS_ABI_EABI64
;
5533 if ((elf_flags
& EF_MIPS_ABI2
))
5534 found_abi
= MIPS_ABI_N32
;
5536 found_abi
= MIPS_ABI_UNKNOWN
;
5540 /* GCC creates a pseudo-section whose name describes the ABI. */
5541 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5542 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5544 /* If we have no useful BFD information, use the ABI from the last
5545 MIPS architecture (if there is one). */
5546 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5547 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5549 /* Try the architecture for any hint of the correct ABI. */
5550 if (found_abi
== MIPS_ABI_UNKNOWN
5551 && info
.bfd_arch_info
!= NULL
5552 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5554 switch (info
.bfd_arch_info
->mach
)
5556 case bfd_mach_mips3900
:
5557 found_abi
= MIPS_ABI_EABI32
;
5559 case bfd_mach_mips4100
:
5560 case bfd_mach_mips5000
:
5561 found_abi
= MIPS_ABI_EABI64
;
5563 case bfd_mach_mips8000
:
5564 case bfd_mach_mips10000
:
5565 /* On Irix, ELF64 executables use the N64 ABI. The
5566 pseudo-sections which describe the ABI aren't present
5567 on IRIX. (Even for executables created by gcc.) */
5568 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5569 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5570 found_abi
= MIPS_ABI_N64
;
5572 found_abi
= MIPS_ABI_N32
;
5577 /* Default 64-bit objects to N64 instead of O32. */
5578 if (found_abi
== MIPS_ABI_UNKNOWN
5579 && info
.abfd
!= NULL
5580 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5581 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5582 found_abi
= MIPS_ABI_N64
;
5585 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5588 /* What has the user specified from the command line? */
5589 wanted_abi
= global_mips_abi ();
5591 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5594 /* Now that we have found what the ABI for this binary would be,
5595 check whether the user is overriding it. */
5596 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5597 mips_abi
= wanted_abi
;
5598 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5599 mips_abi
= found_abi
;
5601 mips_abi
= MIPS_ABI_O32
;
5603 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5606 /* Also used when doing an architecture lookup. */
5608 fprintf_unfiltered (gdb_stdlog
,
5609 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5610 mips64_transfers_32bit_regs_p
);
5612 /* Determine the MIPS FPU type. */
5615 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5616 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5617 Tag_GNU_MIPS_ABI_FP
);
5618 #endif /* HAVE_ELF */
5620 if (!mips_fpu_type_auto
)
5621 fpu_type
= mips_fpu_type
;
5622 else if (elf_fpu_type
!= 0)
5624 switch (elf_fpu_type
)
5627 fpu_type
= MIPS_FPU_DOUBLE
;
5630 fpu_type
= MIPS_FPU_SINGLE
;
5634 /* Soft float or unknown. */
5635 fpu_type
= MIPS_FPU_NONE
;
5639 else if (info
.bfd_arch_info
!= NULL
5640 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5641 switch (info
.bfd_arch_info
->mach
)
5643 case bfd_mach_mips3900
:
5644 case bfd_mach_mips4100
:
5645 case bfd_mach_mips4111
:
5646 case bfd_mach_mips4120
:
5647 fpu_type
= MIPS_FPU_NONE
;
5649 case bfd_mach_mips4650
:
5650 fpu_type
= MIPS_FPU_SINGLE
;
5653 fpu_type
= MIPS_FPU_DOUBLE
;
5656 else if (arches
!= NULL
)
5657 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5659 fpu_type
= MIPS_FPU_DOUBLE
;
5661 fprintf_unfiltered (gdb_stdlog
,
5662 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5664 /* Check for blatant incompatibilities. */
5666 /* If we have only 32-bit registers, then we can't debug a 64-bit
5668 if (info
.target_desc
5669 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5670 && mips_abi
!= MIPS_ABI_EABI32
5671 && mips_abi
!= MIPS_ABI_O32
)
5673 if (tdesc_data
!= NULL
)
5674 tdesc_data_cleanup (tdesc_data
);
5678 /* try to find a pre-existing architecture */
5679 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5681 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5683 /* MIPS needs to be pedantic about which ABI the object is
5685 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5687 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5689 /* Need to be pedantic about which register virtual size is
5691 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5692 != mips64_transfers_32bit_regs_p
)
5694 /* Be pedantic about which FPU is selected. */
5695 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5698 if (tdesc_data
!= NULL
)
5699 tdesc_data_cleanup (tdesc_data
);
5700 return arches
->gdbarch
;
5703 /* Need a new architecture. Fill in a target specific vector. */
5704 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5705 gdbarch
= gdbarch_alloc (&info
, tdep
);
5706 tdep
->elf_flags
= elf_flags
;
5707 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5708 tdep
->found_abi
= found_abi
;
5709 tdep
->mips_abi
= mips_abi
;
5710 tdep
->mips_fpu_type
= fpu_type
;
5711 tdep
->register_size_valid_p
= 0;
5712 tdep
->register_size
= 0;
5714 if (info
.target_desc
)
5716 /* Some useful properties can be inferred from the target. */
5717 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5719 tdep
->register_size_valid_p
= 1;
5720 tdep
->register_size
= 4;
5722 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5724 tdep
->register_size_valid_p
= 1;
5725 tdep
->register_size
= 8;
5729 /* Initially set everything according to the default ABI/ISA. */
5730 set_gdbarch_short_bit (gdbarch
, 16);
5731 set_gdbarch_int_bit (gdbarch
, 32);
5732 set_gdbarch_float_bit (gdbarch
, 32);
5733 set_gdbarch_double_bit (gdbarch
, 64);
5734 set_gdbarch_long_double_bit (gdbarch
, 64);
5735 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5736 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5737 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5739 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5740 mips_elf_make_msymbol_special
);
5742 /* Fill in the OS dependant register numbers and names. */
5744 const char **reg_names
;
5745 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5746 struct mips_regnum
);
5747 if (tdesc_has_registers (info
.target_desc
))
5749 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5750 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5751 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5752 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5753 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5754 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5755 regnum
->fp_control_status
= 70;
5756 regnum
->fp_implementation_revision
= 71;
5757 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5760 else if (info
.osabi
== GDB_OSABI_IRIX
)
5765 regnum
->badvaddr
= 66;
5768 regnum
->fp_control_status
= 69;
5769 regnum
->fp_implementation_revision
= 70;
5771 reg_names
= mips_irix_reg_names
;
5775 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5776 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5777 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5778 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5779 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5780 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5781 regnum
->fp_control_status
= 70;
5782 regnum
->fp_implementation_revision
= 71;
5784 if (info
.bfd_arch_info
!= NULL
5785 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5786 reg_names
= mips_tx39_reg_names
;
5788 reg_names
= mips_generic_reg_names
;
5790 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5791 replaced by gdbarch_read_pc? */
5792 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5793 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5794 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5795 set_gdbarch_num_regs (gdbarch
, num_regs
);
5796 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5797 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5798 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
5799 tdep
->mips_processor_reg_names
= reg_names
;
5800 tdep
->regnum
= regnum
;
5806 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5807 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5808 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5809 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5810 tdep
->default_mask_address_p
= 0;
5811 set_gdbarch_long_bit (gdbarch
, 32);
5812 set_gdbarch_ptr_bit (gdbarch
, 32);
5813 set_gdbarch_long_long_bit (gdbarch
, 64);
5816 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5817 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5818 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5819 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5820 tdep
->default_mask_address_p
= 0;
5821 set_gdbarch_long_bit (gdbarch
, 32);
5822 set_gdbarch_ptr_bit (gdbarch
, 32);
5823 set_gdbarch_long_long_bit (gdbarch
, 64);
5825 case MIPS_ABI_EABI32
:
5826 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5827 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5828 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5829 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5830 tdep
->default_mask_address_p
= 0;
5831 set_gdbarch_long_bit (gdbarch
, 32);
5832 set_gdbarch_ptr_bit (gdbarch
, 32);
5833 set_gdbarch_long_long_bit (gdbarch
, 64);
5835 case MIPS_ABI_EABI64
:
5836 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5837 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5838 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5839 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5840 tdep
->default_mask_address_p
= 0;
5841 set_gdbarch_long_bit (gdbarch
, 64);
5842 set_gdbarch_ptr_bit (gdbarch
, 64);
5843 set_gdbarch_long_long_bit (gdbarch
, 64);
5846 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5847 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5848 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5849 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5850 tdep
->default_mask_address_p
= 0;
5851 set_gdbarch_long_bit (gdbarch
, 32);
5852 set_gdbarch_ptr_bit (gdbarch
, 32);
5853 set_gdbarch_long_long_bit (gdbarch
, 64);
5854 set_gdbarch_long_double_bit (gdbarch
, 128);
5855 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5858 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5859 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5860 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5861 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5862 tdep
->default_mask_address_p
= 0;
5863 set_gdbarch_long_bit (gdbarch
, 64);
5864 set_gdbarch_ptr_bit (gdbarch
, 64);
5865 set_gdbarch_long_long_bit (gdbarch
, 64);
5866 set_gdbarch_long_double_bit (gdbarch
, 128);
5867 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5870 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5873 /* GCC creates a pseudo-section whose name specifies the size of
5874 longs, since -mlong32 or -mlong64 may be used independent of
5875 other options. How those options affect pointer sizes is ABI and
5876 architecture dependent, so use them to override the default sizes
5877 set by the ABI. This table shows the relationship between ABI,
5878 -mlongXX, and size of pointers:
5880 ABI -mlongXX ptr bits
5881 --- -------- --------
5895 Note that for o32 and eabi32, pointers are always 32 bits
5896 regardless of any -mlongXX option. For all others, pointers and
5897 longs are the same, as set by -mlongXX or set by defaults.
5900 if (info
.abfd
!= NULL
)
5904 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5907 set_gdbarch_long_bit (gdbarch
, long_bit
);
5911 case MIPS_ABI_EABI32
:
5916 case MIPS_ABI_EABI64
:
5917 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5920 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5925 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5926 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5929 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5930 flag in object files because to do so would make it impossible to
5931 link with libraries compiled without "-gp32". This is
5932 unnecessarily restrictive.
5934 We could solve this problem by adding "-gp32" multilibs to gcc,
5935 but to set this flag before gcc is built with such multilibs will
5936 break too many systems.''
5938 But even more unhelpfully, the default linker output target for
5939 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5940 for 64-bit programs - you need to change the ABI to change this,
5941 and not all gcc targets support that currently. Therefore using
5942 this flag to detect 32-bit mode would do the wrong thing given
5943 the current gcc - it would make GDB treat these 64-bit programs
5944 as 32-bit programs by default. */
5946 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5947 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5949 /* Add/remove bits from an address. The MIPS needs be careful to
5950 ensure that all 32 bit addresses are sign extended to 64 bits. */
5951 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5953 /* Unwind the frame. */
5954 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5955 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5956 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
5958 /* Map debug register numbers onto internal register numbers. */
5959 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5960 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5961 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5962 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5963 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5964 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5966 /* MIPS version of CALL_DUMMY */
5968 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5969 replaced by a command, and all targets will default to on stack
5970 (regardless of the stack's execute status). */
5971 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5972 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5974 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5975 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5976 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5978 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5979 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5981 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5983 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
5985 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5986 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5987 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5989 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5991 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5993 if (mips_abi
== MIPS_ABI_N32
)
5994 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
5995 else if (mips_abi
== MIPS_ABI_N64
)
5996 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
5998 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6000 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6001 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6002 need to all be folded into the target vector. Since they are
6003 being used as guards for target_stopped_by_watchpoint, why not have
6004 target_stopped_by_watchpoint return the type of watchpoint that the code
6006 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6008 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6010 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
6012 /* Virtual tables. */
6013 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6015 mips_register_g_packet_guesses (gdbarch
);
6017 /* Hook in OS ABI-specific overrides, if they have been registered. */
6018 info
.tdep_info
= (void *) tdesc_data
;
6019 gdbarch_init_osabi (info
, gdbarch
);
6021 /* Unwind the frame. */
6022 dwarf2_append_unwinders (gdbarch
);
6023 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6024 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6025 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6026 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6027 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6028 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6029 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6033 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6034 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6036 /* Override the normal target description methods to handle our
6037 dual real and pseudo registers. */
6038 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6039 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
6041 num_regs
= gdbarch_num_regs (gdbarch
);
6042 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6043 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6044 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6047 /* Add ABI-specific aliases for the registers. */
6048 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6049 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6050 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6051 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6053 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6054 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6055 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6057 /* Add some other standard aliases. */
6058 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6059 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6060 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6062 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6063 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6064 value_of_mips_user_reg
,
6065 &mips_numeric_register_aliases
[i
].regnum
);
6071 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6073 struct gdbarch_info info
;
6075 /* Force the architecture to update, and (if it's a MIPS architecture)
6076 mips_gdbarch_init will take care of the rest. */
6077 gdbarch_info_init (&info
);
6078 gdbarch_update_p (info
);
6081 /* Print out which MIPS ABI is in use. */
6084 show_mips_abi (struct ui_file
*file
,
6086 struct cmd_list_element
*ignored_cmd
,
6087 const char *ignored_value
)
6089 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6092 "The MIPS ABI is unknown because the current architecture "
6096 enum mips_abi global_abi
= global_mips_abi ();
6097 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6098 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6100 if (global_abi
== MIPS_ABI_UNKNOWN
)
6103 "The MIPS ABI is set automatically (currently \"%s\").\n",
6105 else if (global_abi
== actual_abi
)
6108 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6112 /* Probably shouldn't happen... */
6115 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6116 actual_abi_str
, mips_abi_strings
[global_abi
]);
6122 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6124 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6128 int ef_mips_32bitmode
;
6129 /* Determine the ISA. */
6130 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6148 /* Determine the size of a pointer. */
6149 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6150 fprintf_unfiltered (file
,
6151 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6153 fprintf_unfiltered (file
,
6154 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6156 fprintf_unfiltered (file
,
6157 "mips_dump_tdep: ef_mips_arch = %d\n",
6159 fprintf_unfiltered (file
,
6160 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6161 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6162 fprintf_unfiltered (file
,
6163 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6164 mips_mask_address_p (tdep
),
6165 tdep
->default_mask_address_p
);
6167 fprintf_unfiltered (file
,
6168 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6169 MIPS_DEFAULT_FPU_TYPE
,
6170 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6171 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6172 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6174 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6175 MIPS_EABI (gdbarch
));
6176 fprintf_unfiltered (file
,
6177 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6178 MIPS_FPU_TYPE (gdbarch
),
6179 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6180 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6181 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6185 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6188 _initialize_mips_tdep (void)
6190 static struct cmd_list_element
*mipsfpulist
= NULL
;
6191 struct cmd_list_element
*c
;
6193 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6194 if (MIPS_ABI_LAST
+ 1
6195 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6196 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6198 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6200 mips_pdr_data
= register_objfile_data ();
6202 /* Create feature sets with the appropriate properties. The values
6203 are not important. */
6204 mips_tdesc_gp32
= allocate_target_description ();
6205 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6207 mips_tdesc_gp64
= allocate_target_description ();
6208 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6210 /* Add root prefix command for all "set mips"/"show mips" commands */
6211 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6212 _("Various MIPS specific commands."),
6213 &setmipscmdlist
, "set mips ", 0, &setlist
);
6215 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6216 _("Various MIPS specific commands."),
6217 &showmipscmdlist
, "show mips ", 0, &showlist
);
6219 /* Allow the user to override the ABI. */
6220 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6221 &mips_abi_string
, _("\
6222 Set the MIPS ABI used by this program."), _("\
6223 Show the MIPS ABI used by this program."), _("\
6224 This option can be set to one of:\n\
6225 auto - the default ABI associated with the current binary\n\
6234 &setmipscmdlist
, &showmipscmdlist
);
6236 /* Let the user turn off floating point and set the fence post for
6237 heuristic_proc_start. */
6239 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6240 _("Set use of MIPS floating-point coprocessor."),
6241 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6242 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6243 _("Select single-precision MIPS floating-point coprocessor."),
6245 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6246 _("Select double-precision MIPS floating-point coprocessor."),
6248 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6249 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6250 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6251 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6252 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6253 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6254 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6255 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6256 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6257 _("Select MIPS floating-point coprocessor automatically."),
6259 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6260 _("Show current use of MIPS floating-point coprocessor target."),
6263 /* We really would like to have both "0" and "unlimited" work, but
6264 command.c doesn't deal with that. So make it a var_zinteger
6265 because the user can always use "999999" or some such for unlimited. */
6266 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6267 &heuristic_fence_post
, _("\
6268 Set the distance searched for the start of a function."), _("\
6269 Show the distance searched for the start of a function."), _("\
6270 If you are debugging a stripped executable, GDB needs to search through the\n\
6271 program for the start of a function. This command sets the distance of the\n\
6272 search. The only need to set it is when debugging a stripped executable."),
6273 reinit_frame_cache_sfunc
,
6274 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
6275 &setlist
, &showlist
);
6277 /* Allow the user to control whether the upper bits of 64-bit
6278 addresses should be zeroed. */
6279 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6280 &mask_address_var
, _("\
6281 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6282 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6283 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6284 allow GDB to determine the correct value."),
6285 NULL
, show_mask_address
,
6286 &setmipscmdlist
, &showmipscmdlist
);
6288 /* Allow the user to control the size of 32 bit registers within the
6289 raw remote packet. */
6290 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6291 &mips64_transfers_32bit_regs_p
, _("\
6292 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6294 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6296 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6297 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6298 64 bits for others. Use \"off\" to disable compatibility mode"),
6299 set_mips64_transfers_32bit_regs
,
6300 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6301 &setlist
, &showlist
);
6303 /* Debug this files internals. */
6304 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6306 Set mips debugging."), _("\
6307 Show mips debugging."), _("\
6308 When non-zero, mips specific debugging is enabled."),
6310 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
6311 &setdebuglist
, &showdebuglist
);