1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
58 static const struct objfile_data
*mips_pdr_data
;
60 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 /* A useful bit in the CP0 status register (PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE
= 4,
72 MIPS_FPU_DOUBLE_REGSIZE
= 8
76 static const char *mips_abi_string
;
78 static const char *mips_abi_strings
[] = {
89 struct frame_extra_info
91 mips_extra_func_info_t proc_desc
;
95 /* Various MIPS ISA options (related to stack analysis) can be
96 overridden dynamically. Establish an enum/array for managing
99 static const char size_auto
[] = "auto";
100 static const char size_32
[] = "32";
101 static const char size_64
[] = "64";
103 static const char *size_enums
[] = {
110 /* Some MIPS boards don't support floating point while others only
111 support single-precision floating-point operations. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int default_mask_address_p
;
141 /* Is the target using 64-bit raw integer registers but only
142 storing a left-aligned 32-bit value in each? */
143 int mips64_transfers_32bit_regs_p
;
144 /* Indexes for various registers. IRIX and embedded have
145 different values. This contains the "public" fields. Don't
146 add any that do not need to be public. */
147 const struct mips_regnum
*regnum
;
148 /* Register names table for the current register set. */
149 const char **mips_processor_reg_names
;
152 const struct mips_regnum
*
153 mips_regnum (struct gdbarch
*gdbarch
)
155 return gdbarch_tdep (gdbarch
)->regnum
;
159 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
161 return mips_regnum (gdbarch
)->fp0
+ 12;
164 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
165 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
167 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
169 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
171 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
173 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
174 functions to test, set, or clear bit 0 of addresses. */
177 is_mips16_addr (CORE_ADDR addr
)
183 make_mips16_addr (CORE_ADDR addr
)
189 unmake_mips16_addr (CORE_ADDR addr
)
191 return ((addr
) & ~1);
194 /* Return the contents of register REGNUM as a signed integer. */
197 read_signed_register (int regnum
)
199 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
200 deprecated_read_register_gen (regnum
, buf
);
201 return (extract_signed_integer
202 (buf
, register_size (current_gdbarch
, regnum
)));
206 read_signed_register_pid (int regnum
, ptid_t ptid
)
211 if (ptid_equal (ptid
, inferior_ptid
))
212 return read_signed_register (regnum
);
214 save_ptid
= inferior_ptid
;
216 inferior_ptid
= ptid
;
218 retval
= read_signed_register (regnum
);
220 inferior_ptid
= save_ptid
;
225 /* Return the MIPS ABI associated with GDBARCH. */
227 mips_abi (struct gdbarch
*gdbarch
)
229 return gdbarch_tdep (gdbarch
)->mips_abi
;
233 mips_isa_regsize (struct gdbarch
*gdbarch
)
235 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
236 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
239 /* Return the currently configured (or set) saved register size. */
241 static const char *mips_abi_regsize_string
= size_auto
;
244 mips_abi_regsize (struct gdbarch
*gdbarch
)
246 if (mips_abi_regsize_string
== size_auto
)
247 switch (mips_abi (gdbarch
))
249 case MIPS_ABI_EABI32
:
255 case MIPS_ABI_EABI64
:
257 case MIPS_ABI_UNKNOWN
:
260 internal_error (__FILE__
, __LINE__
, "bad switch");
262 else if (mips_abi_regsize_string
== size_64
)
264 else /* if (mips_abi_regsize_string == size_32) */
268 /* Functions for setting and testing a bit in a minimal symbol that
269 marks it as 16-bit function. The MSB of the minimal symbol's
270 "info" field is used for this purpose.
272 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
273 i.e. refers to a 16-bit function, and sets a "special" bit in a
274 minimal symbol to mark it as a 16-bit function
276 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
279 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
281 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
283 MSYMBOL_INFO (msym
) = (char *)
284 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
285 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
290 msymbol_is_special (struct minimal_symbol
*msym
)
292 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
295 /* XFER a value from the big/little/left end of the register.
296 Depending on the size of the value it might occupy the entire
297 register or just part of it. Make an allowance for this, aligning
298 things accordingly. */
301 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
302 enum bfd_endian endian
, bfd_byte
* in
,
303 const bfd_byte
* out
, int buf_offset
)
306 gdb_assert (reg_num
>= NUM_REGS
);
307 /* Need to transfer the left or right part of the register, based on
308 the targets byte order. */
312 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
314 case BFD_ENDIAN_LITTLE
:
317 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
321 internal_error (__FILE__
, __LINE__
, "bad switch");
324 fprintf_unfiltered (gdb_stderr
,
325 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
326 reg_num
, reg_offset
, buf_offset
, length
);
327 if (mips_debug
&& out
!= NULL
)
330 fprintf_unfiltered (gdb_stdlog
, "out ");
331 for (i
= 0; i
< length
; i
++)
332 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
335 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
338 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
340 if (mips_debug
&& in
!= NULL
)
343 fprintf_unfiltered (gdb_stdlog
, "in ");
344 for (i
= 0; i
< length
; i
++)
345 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
348 fprintf_unfiltered (gdb_stdlog
, "\n");
351 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
352 compatiblity mode. A return value of 1 means that we have
353 physical 64-bit registers, but should treat them as 32-bit registers. */
356 mips2_fp_compat (void)
358 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
360 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
365 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
366 in all the places we deal with FP registers. PR gdb/413. */
367 /* Otherwise check the FR bit in the status register - it controls
368 the FP compatiblity mode. If it is clear we are in compatibility
370 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
377 /* The amount of space reserved on the stack for registers. This is
378 different to MIPS_ABI_REGSIZE as it determines the alignment of
379 data allocated after the registers have run out. */
381 static const char *mips_stack_argsize_string
= size_auto
;
384 mips_stack_argsize (struct gdbarch
*gdbarch
)
386 if (mips_stack_argsize_string
== size_auto
)
387 return mips_abi_regsize (gdbarch
);
388 else if (mips_stack_argsize_string
== size_64
)
390 else /* if (mips_stack_argsize_string == size_32) */
394 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
396 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
397 struct frame_info
*, int);
398 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
401 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
403 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
405 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
407 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
408 struct frame_info
*next_frame
,
411 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
412 mips_extra_func_info_t proc_desc
);
414 static struct type
*mips_float_register_type (void);
415 static struct type
*mips_double_register_type (void);
417 /* The list of available "set mips " and "show mips " commands */
419 static struct cmd_list_element
*setmipscmdlist
= NULL
;
420 static struct cmd_list_element
*showmipscmdlist
= NULL
;
422 /* Integer registers 0 thru 31 are handled explicitly by
423 mips_register_name(). Processor specific registers 32 and above
424 are listed in the followign tables. */
427 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
431 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
432 "sr", "lo", "hi", "bad", "cause", "pc",
433 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
434 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
435 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
436 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
437 "fsr", "fir", "" /*"fp" */ , "",
438 "", "", "", "", "", "", "", "",
439 "", "", "", "", "", "", "", "",
442 /* Names of IDT R3041 registers. */
444 static const char *mips_r3041_reg_names
[] = {
445 "sr", "lo", "hi", "bad", "cause", "pc",
446 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
447 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
448 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
449 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
450 "fsr", "fir", "", /*"fp" */ "",
451 "", "", "bus", "ccfg", "", "", "", "",
452 "", "", "port", "cmp", "", "", "epc", "prid",
455 /* Names of tx39 registers. */
457 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
458 "sr", "lo", "hi", "bad", "cause", "pc",
459 "", "", "", "", "", "", "", "",
460 "", "", "", "", "", "", "", "",
461 "", "", "", "", "", "", "", "",
462 "", "", "", "", "", "", "", "",
464 "", "", "", "", "", "", "", "",
465 "", "", "config", "cache", "debug", "depc", "epc", ""
468 /* Names of IRIX registers. */
469 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
470 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
471 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
472 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
473 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
474 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
478 /* Return the name of the register corresponding to REGNO. */
480 mips_register_name (int regno
)
482 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
483 /* GPR names for all ABIs other than n32/n64. */
484 static char *mips_gpr_names
[] = {
485 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
486 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
487 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
488 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
491 /* GPR names for n32 and n64 ABIs. */
492 static char *mips_n32_n64_gpr_names
[] = {
493 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
494 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
495 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
496 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
499 enum mips_abi abi
= mips_abi (current_gdbarch
);
501 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
502 don't make the raw register names visible. */
503 int rawnum
= regno
% NUM_REGS
;
504 if (regno
< NUM_REGS
)
507 /* The MIPS integer registers are always mapped from 0 to 31. The
508 names of the registers (which reflects the conventions regarding
509 register use) vary depending on the ABI. */
510 if (0 <= rawnum
&& rawnum
< 32)
512 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
513 return mips_n32_n64_gpr_names
[rawnum
];
515 return mips_gpr_names
[rawnum
];
517 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
519 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
520 return tdep
->mips_processor_reg_names
[rawnum
- 32];
523 internal_error (__FILE__
, __LINE__
,
524 "mips_register_name: bad register number %d", rawnum
);
527 /* Return the groups that a MIPS register can be categorised into. */
530 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
531 struct reggroup
*reggroup
)
536 int rawnum
= regnum
% NUM_REGS
;
537 int pseudo
= regnum
/ NUM_REGS
;
538 if (reggroup
== all_reggroup
)
540 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
541 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
542 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
543 (gdbarch), as not all architectures are multi-arch. */
544 raw_p
= rawnum
< NUM_REGS
;
545 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
547 if (reggroup
== float_reggroup
)
548 return float_p
&& pseudo
;
549 if (reggroup
== vector_reggroup
)
550 return vector_p
&& pseudo
;
551 if (reggroup
== general_reggroup
)
552 return (!vector_p
&& !float_p
) && pseudo
;
553 /* Save the pseudo registers. Need to make certain that any code
554 extracting register values from a saved register cache also uses
556 if (reggroup
== save_reggroup
)
557 return raw_p
&& pseudo
;
558 /* Restore the same pseudo register. */
559 if (reggroup
== restore_reggroup
)
560 return raw_p
&& pseudo
;
564 /* Map the symbol table registers which live in the range [1 *
565 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
566 registers. Take care of alignment and size problems. */
569 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
570 int cookednum
, void *buf
)
572 int rawnum
= cookednum
% NUM_REGS
;
573 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
574 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
575 regcache_raw_read (regcache
, rawnum
, buf
);
576 else if (register_size (gdbarch
, rawnum
) >
577 register_size (gdbarch
, cookednum
))
579 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
580 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
581 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
583 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
586 internal_error (__FILE__
, __LINE__
, "bad register size");
590 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
591 struct regcache
*regcache
, int cookednum
,
594 int rawnum
= cookednum
% NUM_REGS
;
595 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
596 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
597 regcache_raw_write (regcache
, rawnum
, buf
);
598 else if (register_size (gdbarch
, rawnum
) >
599 register_size (gdbarch
, cookednum
))
601 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
602 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
603 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
605 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
608 internal_error (__FILE__
, __LINE__
, "bad register size");
611 /* Table to translate MIPS16 register field to actual register number. */
612 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
614 /* Heuristic_proc_start may hunt through the text section for a long
615 time across a 2400 baud serial line. Allows the user to limit this
618 static unsigned int heuristic_fence_post
= 0;
620 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
621 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
622 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
623 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
624 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
625 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
626 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
627 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
628 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
629 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
630 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
631 this will corrupt pdr.iline. Fortunately we don't use it. */
632 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
633 #define _PROC_MAGIC_ 0x0F0F0F0F
634 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
635 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
637 struct linked_proc_info
639 struct mips_extra_func_info info
;
640 struct linked_proc_info
*next
;
642 *linked_proc_desc_table
= NULL
;
644 /* Number of bytes of storage in the actual machine representation for
645 register N. NOTE: This defines the pseudo register type so need to
646 rebuild the architecture vector. */
648 static int mips64_transfers_32bit_regs_p
= 0;
651 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
652 struct cmd_list_element
*c
)
654 struct gdbarch_info info
;
655 gdbarch_info_init (&info
);
656 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
657 instead of relying on globals. Doing that would let generic code
658 handle the search for this specific architecture. */
659 if (!gdbarch_update_p (info
))
661 mips64_transfers_32bit_regs_p
= 0;
662 error ("32-bit compatibility mode not supported");
666 /* Convert to/from a register and the corresponding memory value. */
669 mips_convert_register_p (int regnum
, struct type
*type
)
671 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
672 && register_size (current_gdbarch
, regnum
) == 4
673 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
674 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
675 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
679 mips_register_to_value (struct frame_info
*frame
, int regnum
,
680 struct type
*type
, void *to
)
682 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
683 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
687 mips_value_to_register (struct frame_info
*frame
, int regnum
,
688 struct type
*type
, const void *from
)
690 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
691 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
694 /* Return the GDB type object for the "standard" data type of data in
698 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
700 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
701 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
702 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
704 /* The floating-point registers raw, or cooked, always match
705 mips_isa_regsize(), and also map 1:1, byte for byte. */
706 switch (gdbarch_byte_order (gdbarch
))
709 if (mips_isa_regsize (gdbarch
) == 4)
710 return builtin_type_ieee_single_big
;
712 return builtin_type_ieee_double_big
;
713 case BFD_ENDIAN_LITTLE
:
714 if (mips_isa_regsize (gdbarch
) == 4)
715 return builtin_type_ieee_single_little
;
717 return builtin_type_ieee_double_little
;
718 case BFD_ENDIAN_UNKNOWN
:
720 internal_error (__FILE__
, __LINE__
, "bad switch");
723 else if (regnum
< NUM_REGS
)
725 /* The raw or ISA registers. These are all sized according to
727 if (mips_isa_regsize (gdbarch
) == 4)
728 return builtin_type_int32
;
730 return builtin_type_int64
;
734 /* The cooked or ABI registers. These are sized according to
735 the ABI (with a few complications). */
736 if (regnum
>= (NUM_REGS
737 + mips_regnum (current_gdbarch
)->fp_control_status
)
738 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
739 /* The pseudo/cooked view of the embedded registers is always
740 32-bit. The raw view is handled below. */
741 return builtin_type_int32
;
742 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
743 /* The target, while possibly using a 64-bit register buffer,
744 is only transfering 32-bits of each integer register.
745 Reflect this in the cooked/pseudo (ABI) register value. */
746 return builtin_type_int32
;
747 else if (mips_abi_regsize (gdbarch
) == 4)
748 /* The ABI is restricted to 32-bit registers (the ISA could be
750 return builtin_type_int32
;
753 return builtin_type_int64
;
757 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
762 return read_signed_register (MIPS_SP_REGNUM
);
765 /* Should the upper word of 64-bit addresses be zeroed? */
766 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
769 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
771 switch (mask_address_var
)
773 case AUTO_BOOLEAN_TRUE
:
775 case AUTO_BOOLEAN_FALSE
:
778 case AUTO_BOOLEAN_AUTO
:
779 return tdep
->default_mask_address_p
;
781 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
787 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
789 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
790 switch (mask_address_var
)
792 case AUTO_BOOLEAN_TRUE
:
793 printf_filtered ("The 32 bit mips address mask is enabled\n");
795 case AUTO_BOOLEAN_FALSE
:
796 printf_filtered ("The 32 bit mips address mask is disabled\n");
798 case AUTO_BOOLEAN_AUTO
:
800 ("The 32 bit address mask is set automatically. Currently %s\n",
801 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
804 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
809 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
812 pc_is_mips16 (bfd_vma memaddr
)
814 struct minimal_symbol
*sym
;
816 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
817 if (is_mips16_addr (memaddr
))
820 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
821 the high bit of the info field. Use this to decide if the function is
822 MIPS16 or normal MIPS. */
823 sym
= lookup_minimal_symbol_by_pc (memaddr
);
825 return msymbol_is_special (sym
);
830 /* MIPS believes that the PC has a sign extended value. Perhaps the
831 all registers should be sign extended for simplicity? */
834 mips_read_pc (ptid_t ptid
)
836 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
840 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
842 return frame_unwind_register_signed (next_frame
,
843 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
846 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
847 dummy frame. The frame ID's base needs to match the TOS value
848 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
851 static struct frame_id
852 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
854 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
855 frame_pc_unwind (next_frame
));
859 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
861 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
864 /* This returns the PC of the first inst after the prologue. If we can't
865 find the prologue, then return 0. */
868 after_prologue (CORE_ADDR pc
, mips_extra_func_info_t proc_desc
)
870 struct symtab_and_line sal
;
871 CORE_ADDR func_addr
, func_end
;
873 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
874 to read the stack pointer from the current machine state, because
875 the current machine state has nothing to do with the information
876 we need from the proc_desc; and the process may or may not exist
879 proc_desc
= find_proc_desc (pc
, NULL
, 0);
883 /* If function is frameless, then we need to do it the hard way. I
884 strongly suspect that frameless always means prologueless... */
885 if (PROC_FRAME_REG (proc_desc
) == MIPS_SP_REGNUM
886 && PROC_FRAME_OFFSET (proc_desc
) == 0)
890 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
891 return 0; /* Unknown */
893 sal
= find_pc_line (func_addr
, 0);
895 if (sal
.end
< func_end
)
898 /* The line after the prologue is after the end of the function. In this
899 case, tell the caller to find the prologue the hard way. */
904 /* Decode a MIPS32 instruction that saves a register in the stack, and
905 set the appropriate bit in the general register mask or float register mask
906 to indicate which register is saved. This is a helper function
907 for mips_find_saved_regs. */
910 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
911 unsigned long *float_mask
)
915 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
916 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
917 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
919 /* It might be possible to use the instruction to
920 find the offset, rather than the code below which
921 is based on things being in a certain order in the
922 frame, but figuring out what the instruction's offset
923 is relative to might be a little tricky. */
924 reg
= (inst
& 0x001f0000) >> 16;
925 *gen_mask
|= (1 << reg
);
927 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
928 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
929 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
932 reg
= ((inst
& 0x001f0000) >> 16);
933 *float_mask
|= (1 << reg
);
937 /* Decode a MIPS16 instruction that saves a register in the stack, and
938 set the appropriate bit in the general register or float register mask
939 to indicate which register is saved. This is a helper function
940 for mips_find_saved_regs. */
943 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
945 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
947 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
948 *gen_mask
|= (1 << reg
);
950 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
952 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
953 *gen_mask
|= (1 << reg
);
955 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
956 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
957 *gen_mask
|= (1 << RA_REGNUM
);
961 /* Fetch and return instruction from the specified location. If the PC
962 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
965 mips_fetch_instruction (CORE_ADDR addr
)
967 char buf
[MIPS_INSTLEN
];
971 if (pc_is_mips16 (addr
))
973 instlen
= MIPS16_INSTLEN
;
974 addr
= unmake_mips16_addr (addr
);
977 instlen
= MIPS_INSTLEN
;
978 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
980 memory_error (status
, addr
);
981 return extract_unsigned_integer (buf
, instlen
);
985 mips16_fetch_instruction (CORE_ADDR addr
)
987 char buf
[MIPS_INSTLEN
];
991 instlen
= MIPS16_INSTLEN
;
992 addr
= unmake_mips16_addr (addr
);
993 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
995 memory_error (status
, addr
);
996 return extract_unsigned_integer (buf
, instlen
);
1000 mips32_fetch_instruction (CORE_ADDR addr
)
1002 char buf
[MIPS_INSTLEN
];
1005 instlen
= MIPS_INSTLEN
;
1006 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1008 memory_error (status
, addr
);
1009 return extract_unsigned_integer (buf
, instlen
);
1013 /* These the fields of 32 bit mips instructions */
1014 #define mips32_op(x) (x >> 26)
1015 #define itype_op(x) (x >> 26)
1016 #define itype_rs(x) ((x >> 21) & 0x1f)
1017 #define itype_rt(x) ((x >> 16) & 0x1f)
1018 #define itype_immediate(x) (x & 0xffff)
1020 #define jtype_op(x) (x >> 26)
1021 #define jtype_target(x) (x & 0x03ffffff)
1023 #define rtype_op(x) (x >> 26)
1024 #define rtype_rs(x) ((x >> 21) & 0x1f)
1025 #define rtype_rt(x) ((x >> 16) & 0x1f)
1026 #define rtype_rd(x) ((x >> 11) & 0x1f)
1027 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1028 #define rtype_funct(x) (x & 0x3f)
1031 mips32_relative_offset (unsigned long inst
)
1034 x
= itype_immediate (inst
);
1035 if (x
& 0x8000) /* sign bit set */
1037 x
|= 0xffff0000; /* sign extension */
1043 /* Determine whate to set a single step breakpoint while considering
1044 branch prediction */
1046 mips32_next_pc (CORE_ADDR pc
)
1050 inst
= mips_fetch_instruction (pc
);
1051 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1053 if (itype_op (inst
) >> 2 == 5)
1054 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1056 op
= (itype_op (inst
) & 0x03);
1066 goto greater_branch
;
1071 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1072 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1074 int tf
= itype_rt (inst
) & 0x01;
1075 int cnum
= itype_rt (inst
) >> 2;
1077 read_signed_register (mips_regnum (current_gdbarch
)->
1079 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1081 if (((cond
>> cnum
) & 0x01) == tf
)
1082 pc
+= mips32_relative_offset (inst
) + 4;
1087 pc
+= 4; /* Not a branch, next instruction is easy */
1090 { /* This gets way messy */
1092 /* Further subdivide into SPECIAL, REGIMM and other */
1093 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1095 case 0: /* SPECIAL */
1096 op
= rtype_funct (inst
);
1101 /* Set PC to that address */
1102 pc
= read_signed_register (rtype_rs (inst
));
1108 break; /* end SPECIAL */
1109 case 1: /* REGIMM */
1111 op
= itype_rt (inst
); /* branch condition */
1116 case 16: /* BLTZAL */
1117 case 18: /* BLTZALL */
1119 if (read_signed_register (itype_rs (inst
)) < 0)
1120 pc
+= mips32_relative_offset (inst
) + 4;
1122 pc
+= 8; /* after the delay slot */
1126 case 17: /* BGEZAL */
1127 case 19: /* BGEZALL */
1128 if (read_signed_register (itype_rs (inst
)) >= 0)
1129 pc
+= mips32_relative_offset (inst
) + 4;
1131 pc
+= 8; /* after the delay slot */
1133 /* All of the other instructions in the REGIMM category */
1138 break; /* end REGIMM */
1143 reg
= jtype_target (inst
) << 2;
1144 /* Upper four bits get never changed... */
1145 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1148 /* FIXME case JALX : */
1151 reg
= jtype_target (inst
) << 2;
1152 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1153 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1155 break; /* The new PC will be alternate mode */
1156 case 4: /* BEQ, BEQL */
1158 if (read_signed_register (itype_rs (inst
)) ==
1159 read_signed_register (itype_rt (inst
)))
1160 pc
+= mips32_relative_offset (inst
) + 4;
1164 case 5: /* BNE, BNEL */
1166 if (read_signed_register (itype_rs (inst
)) !=
1167 read_signed_register (itype_rt (inst
)))
1168 pc
+= mips32_relative_offset (inst
) + 4;
1172 case 6: /* BLEZ, BLEZL */
1173 if (read_signed_register (itype_rs (inst
) <= 0))
1174 pc
+= mips32_relative_offset (inst
) + 4;
1180 greater_branch
: /* BGTZ, BGTZL */
1181 if (read_signed_register (itype_rs (inst
) > 0))
1182 pc
+= mips32_relative_offset (inst
) + 4;
1189 } /* mips32_next_pc */
1191 /* Decoding the next place to set a breakpoint is irregular for the
1192 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1193 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1194 We dont want to set a single step instruction on the extend instruction
1198 /* Lots of mips16 instruction formats */
1199 /* Predicting jumps requires itype,ritype,i8type
1200 and their extensions extItype,extritype,extI8type
1202 enum mips16_inst_fmts
1204 itype
, /* 0 immediate 5,10 */
1205 ritype
, /* 1 5,3,8 */
1206 rrtype
, /* 2 5,3,3,5 */
1207 rritype
, /* 3 5,3,3,5 */
1208 rrrtype
, /* 4 5,3,3,3,2 */
1209 rriatype
, /* 5 5,3,3,1,4 */
1210 shifttype
, /* 6 5,3,3,3,2 */
1211 i8type
, /* 7 5,3,8 */
1212 i8movtype
, /* 8 5,3,3,5 */
1213 i8mov32rtype
, /* 9 5,3,5,3 */
1214 i64type
, /* 10 5,3,8 */
1215 ri64type
, /* 11 5,3,3,5 */
1216 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1217 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1218 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1219 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1220 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1221 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1222 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1223 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1224 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1225 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1227 /* I am heaping all the fields of the formats into one structure and
1228 then, only the fields which are involved in instruction extension */
1232 unsigned int regx
; /* Function in i8 type */
1237 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1238 for the bits which make up the immediatate extension. */
1241 extended_offset (unsigned int extension
)
1244 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1246 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1248 value
|= extension
& 0x01f; /* extract 4:0 */
1252 /* Only call this function if you know that this is an extendable
1253 instruction, It wont malfunction, but why make excess remote memory references?
1254 If the immediate operands get sign extended or somthing, do it after
1255 the extension is performed.
1257 /* FIXME: Every one of these cases needs to worry about sign extension
1258 when the offset is to be used in relative addressing */
1262 fetch_mips_16 (CORE_ADDR pc
)
1265 pc
&= 0xfffffffe; /* clear the low order bit */
1266 target_read_memory (pc
, buf
, 2);
1267 return extract_unsigned_integer (buf
, 2);
1271 unpack_mips16 (CORE_ADDR pc
,
1272 unsigned int extension
,
1274 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1279 switch (insn_format
)
1286 value
= extended_offset (extension
);
1287 value
= value
<< 11; /* rom for the original value */
1288 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1292 value
= inst
& 0x7ff;
1293 /* FIXME : Consider sign extension */
1302 { /* A register identifier and an offset */
1303 /* Most of the fields are the same as I type but the
1304 immediate value is of a different length */
1308 value
= extended_offset (extension
);
1309 value
= value
<< 8; /* from the original instruction */
1310 value
|= inst
& 0xff; /* eleven bits from instruction */
1311 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1312 if (value
& 0x4000) /* test the sign bit , bit 26 */
1314 value
&= ~0x3fff; /* remove the sign bit */
1320 value
= inst
& 0xff; /* 8 bits */
1321 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1322 /* FIXME: Do sign extension , this format needs it */
1323 if (value
& 0x80) /* THIS CONFUSES ME */
1325 value
&= 0xef; /* remove the sign bit */
1335 unsigned long value
;
1336 unsigned int nexthalf
;
1337 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1338 value
= value
<< 16;
1339 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1347 internal_error (__FILE__
, __LINE__
, "bad switch");
1349 upk
->offset
= offset
;
1356 add_offset_16 (CORE_ADDR pc
, int offset
)
1358 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1362 extended_mips16_next_pc (CORE_ADDR pc
,
1363 unsigned int extension
, unsigned int insn
)
1365 int op
= (insn
>> 11);
1368 case 2: /* Branch */
1371 struct upk_mips16 upk
;
1372 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1373 offset
= upk
.offset
;
1379 pc
+= (offset
<< 1) + 2;
1382 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1384 struct upk_mips16 upk
;
1385 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1386 pc
= add_offset_16 (pc
, upk
.offset
);
1387 if ((insn
>> 10) & 0x01) /* Exchange mode */
1388 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1395 struct upk_mips16 upk
;
1397 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1398 reg
= read_signed_register (upk
.regx
);
1400 pc
+= (upk
.offset
<< 1) + 2;
1407 struct upk_mips16 upk
;
1409 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1410 reg
= read_signed_register (upk
.regx
);
1412 pc
+= (upk
.offset
<< 1) + 2;
1417 case 12: /* I8 Formats btez btnez */
1419 struct upk_mips16 upk
;
1421 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1422 /* upk.regx contains the opcode */
1423 reg
= read_signed_register (24); /* Test register is 24 */
1424 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1425 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1426 /* pc = add_offset_16(pc,upk.offset) ; */
1427 pc
+= (upk
.offset
<< 1) + 2;
1432 case 29: /* RR Formats JR, JALR, JALR-RA */
1434 struct upk_mips16 upk
;
1435 /* upk.fmt = rrtype; */
1440 upk
.regx
= (insn
>> 8) & 0x07;
1441 upk
.regy
= (insn
>> 5) & 0x07;
1449 break; /* Function return instruction */
1455 break; /* BOGUS Guess */
1457 pc
= read_signed_register (reg
);
1464 /* This is an instruction extension. Fetch the real instruction
1465 (which follows the extension) and decode things based on
1469 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1482 mips16_next_pc (CORE_ADDR pc
)
1484 unsigned int insn
= fetch_mips_16 (pc
);
1485 return extended_mips16_next_pc (pc
, 0, insn
);
1488 /* The mips_next_pc function supports single_step when the remote
1489 target monitor or stub is not developed enough to do a single_step.
1490 It works by decoding the current instruction and predicting where a
1491 branch will go. This isnt hard because all the data is available.
1492 The MIPS32 and MIPS16 variants are quite different */
1494 mips_next_pc (CORE_ADDR pc
)
1497 return mips16_next_pc (pc
);
1499 return mips32_next_pc (pc
);
1502 struct mips_frame_cache
1505 struct trad_frame_saved_reg
*saved_regs
;
1509 static struct mips_frame_cache
*
1510 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1512 mips_extra_func_info_t proc_desc
;
1513 struct mips_frame_cache
*cache
;
1514 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1515 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1516 /* r0 bit means kernel trap */
1518 /* What registers have been saved? Bitmasks. */
1519 unsigned long gen_mask
, float_mask
;
1521 if ((*this_cache
) != NULL
)
1522 return (*this_cache
);
1523 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1524 (*this_cache
) = cache
;
1525 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1527 /* Get the mdebug proc descriptor. */
1528 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
, 1);
1529 if (proc_desc
== NULL
)
1530 /* I'm not sure how/whether this can happen. Normally when we
1531 can't find a proc_desc, we "synthesize" one using
1532 heuristic_proc_desc and set the saved_regs right away. */
1535 /* Extract the frame's base. */
1536 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1537 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1539 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1540 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1541 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1543 /* In any frame other than the innermost or a frame interrupted by a
1544 signal, we assume that all registers have been saved. This
1545 assumes that all register saves in a function happen before the
1546 first function call. */
1547 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1548 /* Not sure exactly what kernel_trap means, but if it means the
1549 kernel saves the registers without a prologue doing it, we
1550 better not examine the prologue to see whether registers
1551 have been saved yet. */
1554 /* We need to figure out whether the registers that the
1555 proc_desc claims are saved have been saved yet. */
1559 /* Bitmasks; set if we have found a save for the register. */
1560 unsigned long gen_save_found
= 0;
1561 unsigned long float_save_found
= 0;
1564 /* If the address is odd, assume this is MIPS16 code. */
1565 addr
= PROC_LOW_ADDR (proc_desc
);
1566 mips16
= pc_is_mips16 (addr
);
1568 /* Scan through this function's instructions preceding the
1569 current PC, and look for those that save registers. */
1570 while (addr
< frame_pc_unwind (next_frame
))
1574 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1576 addr
+= MIPS16_INSTLEN
;
1580 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1581 &gen_save_found
, &float_save_found
);
1582 addr
+= MIPS_INSTLEN
;
1585 gen_mask
= gen_save_found
;
1586 float_mask
= float_save_found
;
1589 /* Fill in the offsets for the registers which gen_mask says were
1592 CORE_ADDR reg_position
= (cache
->base
1593 + PROC_REG_OFFSET (proc_desc
));
1595 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1596 if (gen_mask
& 0x80000000)
1598 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1599 reg_position
-= mips_abi_regsize (gdbarch
);
1603 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1604 order of that normally used by gcc. Therefore, we have to fetch
1605 the first instruction of the function, and if it's an entry
1606 instruction that saves $s0 or $s1, correct their saved addresses. */
1607 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1609 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1610 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1614 int sreg_count
= (inst
>> 6) & 3;
1616 /* Check if the ra register was pushed on the stack. */
1617 CORE_ADDR reg_position
= (cache
->base
1618 + PROC_REG_OFFSET (proc_desc
));
1620 reg_position
-= mips_abi_regsize (gdbarch
);
1622 /* Check if the s0 and s1 registers were pushed on the
1624 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1626 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1628 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1629 reg_position
-= mips_abi_regsize (gdbarch
);
1634 /* Fill in the offsets for the registers which float_mask says were
1637 CORE_ADDR reg_position
= (cache
->base
1638 + PROC_FREG_OFFSET (proc_desc
));
1640 /* Fill in the offsets for the float registers which float_mask
1642 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1643 if (float_mask
& 0x80000000)
1645 if (mips_abi_regsize (gdbarch
) == 4
1646 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1648 /* On a big endian 32 bit ABI, floating point registers
1649 are paired to form doubles such that the most
1650 significant part is in $f[N+1] and the least
1651 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1652 registers are also spilled as a pair and stored as a
1655 When little-endian the least significant part is
1656 stored first leading to the memory order $f[N] and
1659 Unfortunately, when big-endian the most significant
1660 part of the double is stored first, and the least
1661 significant is stored second. This leads to the
1662 registers being ordered in memory as firt $f[N+1] and
1665 For the big-endian case make certain that the
1666 addresses point at the correct (swapped) locations
1667 $f[N] and $f[N+1] pair (keep in mind that
1668 reg_position is decremented each time through the
1671 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1672 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1674 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1675 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1678 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1679 .addr
= reg_position
;
1680 reg_position
-= mips_abi_regsize (gdbarch
);
1683 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1684 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1687 /* SP_REGNUM, contains the value and not the address. */
1688 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1690 return (*this_cache
);
1694 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1695 struct frame_id
*this_id
)
1697 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1699 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1703 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1705 int regnum
, int *optimizedp
,
1706 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1707 int *realnump
, void *valuep
)
1709 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1711 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1712 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1715 static const struct frame_unwind mips_mdebug_frame_unwind
=
1718 mips_mdebug_frame_this_id
,
1719 mips_mdebug_frame_prev_register
1722 static const struct frame_unwind
*
1723 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1725 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1726 CORE_ADDR startaddr
= 0;
1727 mips_extra_func_info_t proc_desc
;
1730 /* Only use the mdebug frame unwinder on mdebug frames where all the
1731 registers have been saved. Leave hard cases such as no mdebug or
1732 in prologue for the heuristic unwinders. */
1734 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1735 if (proc_desc
== NULL
)
1738 /* Not sure exactly what kernel_trap means, but if it means the
1739 kernel saves the registers without a prologue doing it, we better
1740 not examine the prologue to see whether registers have been saved
1742 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1744 return &mips_mdebug_frame_unwind
;
1746 /* In any frame other than the innermost or a frame interrupted by a
1747 signal, we assume that all registers have been saved. This
1748 assumes that all register saves in a function happen before the
1749 first function call. */
1750 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1751 return &mips_mdebug_frame_unwind
;
1757 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1760 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1765 static const struct frame_base mips_mdebug_frame_base
= {
1766 &mips_mdebug_frame_unwind
,
1767 mips_mdebug_frame_base_address
,
1768 mips_mdebug_frame_base_address
,
1769 mips_mdebug_frame_base_address
1772 static const struct frame_base
*
1773 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1775 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1776 return &mips_mdebug_frame_base
;
1781 static struct mips_frame_cache
*
1782 mips16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1784 mips_extra_func_info_t proc_desc
;
1785 struct mips_frame_cache
*cache
;
1786 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1787 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1788 /* r0 bit means kernel trap */
1790 /* What registers have been saved? Bitmasks. */
1791 unsigned long gen_mask
, float_mask
;
1793 if ((*this_cache
) != NULL
)
1794 return (*this_cache
);
1795 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1796 (*this_cache
) = cache
;
1797 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1799 /* Get the mdebug proc descriptor. */
1800 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
, 1);
1801 if (proc_desc
== NULL
)
1802 /* I'm not sure how/whether this can happen. Normally when we
1803 can't find a proc_desc, we "synthesize" one using
1804 heuristic_proc_desc and set the saved_regs right away. */
1807 /* Extract the frame's base. */
1808 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1809 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1811 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1812 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1813 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1815 /* In any frame other than the innermost or a frame interrupted by a
1816 signal, we assume that all registers have been saved. This
1817 assumes that all register saves in a function happen before the
1818 first function call. */
1819 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1820 /* Not sure exactly what kernel_trap means, but if it means the
1821 kernel saves the registers without a prologue doing it, we
1822 better not examine the prologue to see whether registers
1823 have been saved yet. */
1826 /* We need to figure out whether the registers that the
1827 proc_desc claims are saved have been saved yet. */
1831 /* Bitmasks; set if we have found a save for the register. */
1832 unsigned long gen_save_found
= 0;
1833 unsigned long float_save_found
= 0;
1836 /* If the address is odd, assume this is MIPS16 code. */
1837 addr
= PROC_LOW_ADDR (proc_desc
);
1838 mips16
= pc_is_mips16 (addr
);
1840 /* Scan through this function's instructions preceding the
1841 current PC, and look for those that save registers. */
1842 while (addr
< frame_pc_unwind (next_frame
))
1846 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1848 addr
+= MIPS16_INSTLEN
;
1852 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1853 &gen_save_found
, &float_save_found
);
1854 addr
+= MIPS_INSTLEN
;
1857 gen_mask
= gen_save_found
;
1858 float_mask
= float_save_found
;
1861 /* Fill in the offsets for the registers which gen_mask says were
1864 CORE_ADDR reg_position
= (cache
->base
1865 + PROC_REG_OFFSET (proc_desc
));
1867 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1868 if (gen_mask
& 0x80000000)
1870 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1871 reg_position
-= mips_abi_regsize (gdbarch
);
1875 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1876 order of that normally used by gcc. Therefore, we have to fetch
1877 the first instruction of the function, and if it's an entry
1878 instruction that saves $s0 or $s1, correct their saved addresses. */
1879 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1881 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1882 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1886 int sreg_count
= (inst
>> 6) & 3;
1888 /* Check if the ra register was pushed on the stack. */
1889 CORE_ADDR reg_position
= (cache
->base
1890 + PROC_REG_OFFSET (proc_desc
));
1892 reg_position
-= mips_abi_regsize (gdbarch
);
1894 /* Check if the s0 and s1 registers were pushed on the
1896 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1898 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1900 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1901 reg_position
-= mips_abi_regsize (gdbarch
);
1906 /* Fill in the offsets for the registers which float_mask says were
1909 CORE_ADDR reg_position
= (cache
->base
1910 + PROC_FREG_OFFSET (proc_desc
));
1912 /* Fill in the offsets for the float registers which float_mask
1914 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1915 if (float_mask
& 0x80000000)
1917 if (mips_abi_regsize (gdbarch
) == 4
1918 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1920 /* On a big endian 32 bit ABI, floating point registers
1921 are paired to form doubles such that the most
1922 significant part is in $f[N+1] and the least
1923 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1924 registers are also spilled as a pair and stored as a
1927 When little-endian the least significant part is
1928 stored first leading to the memory order $f[N] and
1931 Unfortunately, when big-endian the most significant
1932 part of the double is stored first, and the least
1933 significant is stored second. This leads to the
1934 registers being ordered in memory as firt $f[N+1] and
1937 For the big-endian case make certain that the
1938 addresses point at the correct (swapped) locations
1939 $f[N] and $f[N+1] pair (keep in mind that
1940 reg_position is decremented each time through the
1943 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1944 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1946 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1947 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1950 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1951 .addr
= reg_position
;
1952 reg_position
-= mips_abi_regsize (gdbarch
);
1955 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1956 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1959 /* SP_REGNUM, contains the value and not the address. */
1960 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1962 return (*this_cache
);
1966 mips16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1967 struct frame_id
*this_id
)
1969 struct mips_frame_cache
*info
= mips16_frame_cache (next_frame
,
1971 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1975 mips16_frame_prev_register (struct frame_info
*next_frame
,
1977 int regnum
, int *optimizedp
,
1978 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1979 int *realnump
, void *valuep
)
1981 struct mips_frame_cache
*info
= mips16_frame_cache (next_frame
,
1983 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1984 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1987 static const struct frame_unwind mips16_frame_unwind
=
1990 mips16_frame_this_id
,
1991 mips16_frame_prev_register
1994 static const struct frame_unwind
*
1995 mips16_frame_sniffer (struct frame_info
*next_frame
)
1997 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1998 if (pc_is_mips16 (pc
))
1999 return &mips16_frame_unwind
;
2004 mips16_frame_base_address (struct frame_info
*next_frame
,
2007 struct mips_frame_cache
*info
= mips16_frame_cache (next_frame
,
2012 static const struct frame_base mips16_frame_base
=
2014 &mips16_frame_unwind
,
2015 mips16_frame_base_address
,
2016 mips16_frame_base_address
,
2017 mips16_frame_base_address
2020 static const struct frame_base
*
2021 mips16_frame_base_sniffer (struct frame_info
*next_frame
)
2023 if (mips16_frame_sniffer (next_frame
) != NULL
)
2024 return &mips16_frame_base
;
2029 static struct mips_frame_cache
*
2030 mips32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2032 mips_extra_func_info_t proc_desc
;
2033 struct mips_frame_cache
*cache
;
2034 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2035 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2036 /* r0 bit means kernel trap */
2038 /* What registers have been saved? Bitmasks. */
2039 unsigned long gen_mask
, float_mask
;
2041 if ((*this_cache
) != NULL
)
2042 return (*this_cache
);
2043 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2044 (*this_cache
) = cache
;
2045 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2047 /* Get the mdebug proc descriptor. */
2048 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
, 1);
2049 if (proc_desc
== NULL
)
2050 /* I'm not sure how/whether this can happen. Normally when we
2051 can't find a proc_desc, we "synthesize" one using
2052 heuristic_proc_desc and set the saved_regs right away. */
2055 /* Extract the frame's base. */
2056 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2057 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2059 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
2060 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
2061 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
2063 /* In any frame other than the innermost or a frame interrupted by a
2064 signal, we assume that all registers have been saved. This
2065 assumes that all register saves in a function happen before the
2066 first function call. */
2067 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
2068 /* Not sure exactly what kernel_trap means, but if it means the
2069 kernel saves the registers without a prologue doing it, we
2070 better not examine the prologue to see whether registers
2071 have been saved yet. */
2074 /* We need to figure out whether the registers that the
2075 proc_desc claims are saved have been saved yet. */
2079 /* Bitmasks; set if we have found a save for the register. */
2080 unsigned long gen_save_found
= 0;
2081 unsigned long float_save_found
= 0;
2084 /* If the address is odd, assume this is MIPS16 code. */
2085 addr
= PROC_LOW_ADDR (proc_desc
);
2086 mips16
= pc_is_mips16 (addr
);
2088 /* Scan through this function's instructions preceding the
2089 current PC, and look for those that save registers. */
2090 while (addr
< frame_pc_unwind (next_frame
))
2094 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
2096 addr
+= MIPS16_INSTLEN
;
2100 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
2101 &gen_save_found
, &float_save_found
);
2102 addr
+= MIPS_INSTLEN
;
2105 gen_mask
= gen_save_found
;
2106 float_mask
= float_save_found
;
2109 /* Fill in the offsets for the registers which gen_mask says were
2112 CORE_ADDR reg_position
= (cache
->base
2113 + PROC_REG_OFFSET (proc_desc
));
2115 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
2116 if (gen_mask
& 0x80000000)
2118 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
2119 reg_position
-= mips_abi_regsize (gdbarch
);
2123 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
2124 order of that normally used by gcc. Therefore, we have to fetch
2125 the first instruction of the function, and if it's an entry
2126 instruction that saves $s0 or $s1, correct their saved addresses. */
2127 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
2129 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
2130 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
2134 int sreg_count
= (inst
>> 6) & 3;
2136 /* Check if the ra register was pushed on the stack. */
2137 CORE_ADDR reg_position
= (cache
->base
2138 + PROC_REG_OFFSET (proc_desc
));
2140 reg_position
-= mips_abi_regsize (gdbarch
);
2142 /* Check if the s0 and s1 registers were pushed on the
2144 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
2146 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2148 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
2149 reg_position
-= mips_abi_regsize (gdbarch
);
2154 /* Fill in the offsets for the registers which float_mask says were
2157 CORE_ADDR reg_position
= (cache
->base
2158 + PROC_FREG_OFFSET (proc_desc
));
2160 /* Fill in the offsets for the float registers which float_mask
2162 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
2163 if (float_mask
& 0x80000000)
2165 if (mips_abi_regsize (gdbarch
) == 4
2166 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2168 /* On a big endian 32 bit ABI, floating point registers
2169 are paired to form doubles such that the most
2170 significant part is in $f[N+1] and the least
2171 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
2172 registers are also spilled as a pair and stored as a
2175 When little-endian the least significant part is
2176 stored first leading to the memory order $f[N] and
2179 Unfortunately, when big-endian the most significant
2180 part of the double is stored first, and the least
2181 significant is stored second. This leads to the
2182 registers being ordered in memory as firt $f[N+1] and
2185 For the big-endian case make certain that the
2186 addresses point at the correct (swapped) locations
2187 $f[N] and $f[N+1] pair (keep in mind that
2188 reg_position is decremented each time through the
2191 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
2192 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
2194 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
2195 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
2198 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
2199 .addr
= reg_position
;
2200 reg_position
-= mips_abi_regsize (gdbarch
);
2203 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2204 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2207 /* SP_REGNUM, contains the value and not the address. */
2208 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2210 return (*this_cache
);
2214 mips32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2215 struct frame_id
*this_id
)
2217 struct mips_frame_cache
*info
= mips32_frame_cache (next_frame
,
2219 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2223 mips32_frame_prev_register (struct frame_info
*next_frame
,
2225 int regnum
, int *optimizedp
,
2226 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2227 int *realnump
, void *valuep
)
2229 struct mips_frame_cache
*info
= mips32_frame_cache (next_frame
,
2231 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2232 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2235 static const struct frame_unwind mips32_frame_unwind
=
2238 mips32_frame_this_id
,
2239 mips32_frame_prev_register
2242 static const struct frame_unwind
*
2243 mips32_frame_sniffer (struct frame_info
*next_frame
)
2245 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2246 if (! pc_is_mips16 (pc
))
2247 return &mips32_frame_unwind
;
2252 mips32_frame_base_address (struct frame_info
*next_frame
,
2255 struct mips_frame_cache
*info
= mips32_frame_cache (next_frame
,
2260 static const struct frame_base mips32_frame_base
=
2262 &mips32_frame_unwind
,
2263 mips32_frame_base_address
,
2264 mips32_frame_base_address
,
2265 mips32_frame_base_address
2268 static const struct frame_base
*
2269 mips32_frame_base_sniffer (struct frame_info
*next_frame
)
2271 if (mips32_frame_sniffer (next_frame
) != NULL
)
2272 return &mips32_frame_base
;
2277 static struct trad_frame_cache
*
2278 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2281 CORE_ADDR start_addr
;
2282 CORE_ADDR stack_addr
;
2283 struct trad_frame_cache
*this_trad_cache
;
2285 if ((*this_cache
) != NULL
)
2286 return (*this_cache
);
2287 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2288 (*this_cache
) = this_trad_cache
;
2290 /* The return address is in the link register. */
2291 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, RA_REGNUM
);
2293 /* Frame ID, since it's a frameless / stackless function, no stack
2294 space is allocated and SP on entry is the current SP. */
2295 pc
= frame_pc_unwind (next_frame
);
2296 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2297 stack_addr
= frame_unwind_register_signed (next_frame
, SP_REGNUM
);
2298 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2300 /* Assume that the frame's base is the same as the
2302 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2304 return this_trad_cache
;
2308 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2309 struct frame_id
*this_id
)
2311 struct trad_frame_cache
*this_trad_cache
2312 = mips_stub_frame_cache (next_frame
, this_cache
);
2313 trad_frame_get_id (this_trad_cache
, this_id
);
2317 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2319 int regnum
, int *optimizedp
,
2320 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2321 int *realnump
, void *valuep
)
2323 struct trad_frame_cache
*this_trad_cache
2324 = mips_stub_frame_cache (next_frame
, this_cache
);
2325 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2326 lvalp
, addrp
, realnump
, valuep
);
2329 static const struct frame_unwind mips_stub_frame_unwind
=
2332 mips_stub_frame_this_id
,
2333 mips_stub_frame_prev_register
2336 static const struct frame_unwind
*
2337 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2339 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2340 if (in_plt_section (pc
, NULL
))
2341 return &mips_stub_frame_unwind
;
2347 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2350 struct trad_frame_cache
*this_trad_cache
2351 = mips_stub_frame_cache (next_frame
, this_cache
);
2352 return trad_frame_get_this_base (this_trad_cache
);
2355 static const struct frame_base mips_stub_frame_base
=
2357 &mips_stub_frame_unwind
,
2358 mips_stub_frame_base_address
,
2359 mips_stub_frame_base_address
,
2360 mips_stub_frame_base_address
2363 static const struct frame_base
*
2364 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2366 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2367 return &mips_stub_frame_base
;
2373 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2375 /* Always a pseudo. */
2376 gdb_assert (regno
>= NUM_REGS
);
2380 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2383 else if ((regno
% NUM_REGS
) == MIPS_SP_REGNUM
)
2384 /* MIPS_SP_REGNUM is special, its value is stored in saved_regs.
2385 In fact, it is so special that it can even only be fetched
2386 using a raw register number! Once this code as been converted
2387 to frame-unwind the problem goes away. */
2388 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
2390 return frame_unwind_register_signed (fi
, regno
);
2394 /* mips_addr_bits_remove - remove useless address bits */
2397 mips_addr_bits_remove (CORE_ADDR addr
)
2399 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2400 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2401 /* This hack is a work-around for existing boards using PMON, the
2402 simulator, and any other 64-bit targets that doesn't have true
2403 64-bit addressing. On these targets, the upper 32 bits of
2404 addresses are ignored by the hardware. Thus, the PC or SP are
2405 likely to have been sign extended to all 1s by instruction
2406 sequences that load 32-bit addresses. For example, a typical
2407 piece of code that loads an address is this:
2409 lui $r2, <upper 16 bits>
2410 ori $r2, <lower 16 bits>
2412 But the lui sign-extends the value such that the upper 32 bits
2413 may be all 1s. The workaround is simply to mask off these
2414 bits. In the future, gcc may be changed to support true 64-bit
2415 addressing, and this masking will have to be disabled. */
2416 return addr
&= 0xffffffffUL
;
2421 /* mips_software_single_step() is called just before we want to resume
2422 the inferior, if we want to single-step it but there is no hardware
2423 or kernel single-step support (MIPS on GNU/Linux for example). We find
2424 the target of the coming instruction and breakpoint it.
2426 single_step is also called just after the inferior stops. If we had
2427 set up a simulated single-step, we undo our damage. */
2430 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2432 static CORE_ADDR next_pc
;
2433 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2434 static binsn_quantum break_mem
;
2437 if (insert_breakpoints_p
)
2439 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2440 next_pc
= mips_next_pc (pc
);
2442 target_insert_breakpoint (next_pc
, break_mem
);
2445 target_remove_breakpoint (next_pc
, break_mem
);
2448 static struct mips_extra_func_info temp_proc_desc
;
2450 /* This hack will go away once the get_prev_frame() code has been
2451 modified to set the frame's type first. That is BEFORE init extra
2452 frame info et.al. is called. This is because it will become
2453 possible to skip the init extra info call for sigtramp and dummy
2455 static CORE_ADDR
*temp_saved_regs
;
2457 /* Set a register's saved stack address in temp_saved_regs. If an
2458 address has already been set for this register, do nothing; this
2459 way we will only recognize the first save of a given register in a
2462 For simplicity, save the address in both [0 .. NUM_REGS) and
2463 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
2464 is used as it is only second range (the ABI instead of ISA
2465 registers) that comes into play when finding saved registers in a
2469 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
2471 if (saved_regs
[regno
] == 0)
2473 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
2474 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
2479 /* Test whether the PC points to the return instruction at the
2480 end of a function. */
2483 mips_about_to_return (CORE_ADDR pc
)
2485 if (pc_is_mips16 (pc
))
2486 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2487 generates a "jr $ra"; other times it generates code to load
2488 the return address from the stack to an accessible register (such
2489 as $a3), then a "jr" using that register. This second case
2490 is almost impossible to distinguish from an indirect jump
2491 used for switch statements, so we don't even try. */
2492 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2494 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2498 /* This fencepost looks highly suspicious to me. Removing it also
2499 seems suspicious as it could affect remote debugging across serial
2503 heuristic_proc_start (CORE_ADDR pc
)
2510 pc
= ADDR_BITS_REMOVE (pc
);
2512 fence
= start_pc
- heuristic_fence_post
;
2516 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2517 fence
= VM_MIN_ADDRESS
;
2519 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
2521 /* search back for previous return */
2522 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2523 if (start_pc
< fence
)
2525 /* It's not clear to me why we reach this point when
2526 stop_soon, but with this test, at least we
2527 don't print out warnings for every child forked (eg, on
2528 decstation). 22apr93 rich@cygnus.com. */
2529 if (stop_soon
== NO_STOP_QUIETLY
)
2531 static int blurb_printed
= 0;
2533 warning ("GDB can't find the start of the function at 0x%s.",
2538 /* This actually happens frequently in embedded
2539 development, when you first connect to a board
2540 and your stack pointer and pc are nowhere in
2541 particular. This message needs to give people
2542 in that situation enough information to
2543 determine that it's no big deal. */
2544 printf_filtered ("\n\
2545 GDB is unable to find the start of the function at 0x%s\n\
2546 and thus can't determine the size of that function's stack frame.\n\
2547 This means that GDB may be unable to access that stack frame, or\n\
2548 the frames below it.\n\
2549 This problem is most likely caused by an invalid program counter or\n\
2551 However, if you think GDB should simply search farther back\n\
2552 from 0x%s for code which looks like the beginning of a\n\
2553 function, you can increase the range of the search using the `set\n\
2554 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2561 else if (pc_is_mips16 (start_pc
))
2563 unsigned short inst
;
2565 /* On MIPS16, any one of the following is likely to be the
2566 start of a function:
2570 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2571 inst
= mips_fetch_instruction (start_pc
);
2572 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2573 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2574 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2575 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2577 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2578 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2583 else if (mips_about_to_return (start_pc
))
2585 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2592 /* Fetch the immediate value from a MIPS16 instruction.
2593 If the previous instruction was an EXTEND, use it to extend
2594 the upper bits of the immediate value. This is a helper function
2595 for mips16_heuristic_proc_desc. */
2598 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2599 unsigned short inst
, /* current instruction */
2600 int nbits
, /* number of bits in imm field */
2601 int scale
, /* scale factor to be applied to imm */
2602 int is_signed
) /* is the imm field signed? */
2606 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2608 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2609 if (offset
& 0x8000) /* check for negative extend */
2610 offset
= 0 - (0x10000 - (offset
& 0xffff));
2611 return offset
| (inst
& 0x1f);
2615 int max_imm
= 1 << nbits
;
2616 int mask
= max_imm
- 1;
2617 int sign_bit
= max_imm
>> 1;
2619 offset
= inst
& mask
;
2620 if (is_signed
&& (offset
& sign_bit
))
2621 offset
= 0 - (max_imm
- offset
);
2622 return offset
* scale
;
2627 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2628 stream from start_pc to limit_pc. */
2631 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2632 struct frame_info
*next_frame
, CORE_ADDR sp
)
2635 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2636 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2637 unsigned inst
= 0; /* current instruction */
2638 unsigned entry_inst
= 0; /* the entry instruction */
2640 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2642 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2643 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2645 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2647 /* Save the previous instruction. If it's an EXTEND, we'll extract
2648 the immediate offset extension from it in mips16_get_imm. */
2651 /* Fetch and decode the instruction. */
2652 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2653 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2654 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2656 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2657 if (offset
< 0) /* negative stack adjustment? */
2658 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2660 /* Exit loop if a positive stack adjustment is found, which
2661 usually means that the stack cleanup code in the function
2662 epilogue is reached. */
2665 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2667 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2668 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2669 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2670 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2672 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2674 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2675 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2676 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2677 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2679 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2681 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2682 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2683 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2685 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2687 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2688 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2689 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2691 else if (inst
== 0x673d) /* move $s1, $sp */
2694 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2696 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2698 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2699 frame_addr
= sp
+ offset
;
2700 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2701 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2703 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2705 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2706 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2707 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2708 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2710 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2712 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2713 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2714 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2715 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2717 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2718 entry_inst
= inst
; /* save for later processing */
2719 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2720 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2723 /* The entry instruction is typically the first instruction in a function,
2724 and it stores registers at offsets relative to the value of the old SP
2725 (before the prologue). But the value of the sp parameter to this
2726 function is the new SP (after the prologue has been executed). So we
2727 can't calculate those offsets until we've seen the entire prologue,
2728 and can calculate what the old SP must have been. */
2729 if (entry_inst
!= 0)
2731 int areg_count
= (entry_inst
>> 8) & 7;
2732 int sreg_count
= (entry_inst
>> 6) & 3;
2734 /* The entry instruction always subtracts 32 from the SP. */
2735 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2737 /* Now we can calculate what the SP must have been at the
2738 start of the function prologue. */
2739 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2741 /* Check if a0-a3 were saved in the caller's argument save area. */
2742 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2744 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2745 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2746 offset
+= mips_abi_regsize (current_gdbarch
);
2749 /* Check if the ra register was pushed on the stack. */
2751 if (entry_inst
& 0x20)
2753 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2754 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2755 offset
-= mips_abi_regsize (current_gdbarch
);
2758 /* Check if the s0 and s1 registers were pushed on the stack. */
2759 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2761 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2762 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2763 offset
-= mips_abi_regsize (current_gdbarch
);
2769 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2770 struct frame_info
*next_frame
, CORE_ADDR sp
)
2773 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2775 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2776 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2777 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2778 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2779 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2781 unsigned long inst
, high_word
, low_word
;
2784 /* Fetch the instruction. */
2785 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2787 /* Save some code by pre-extracting some useful fields. */
2788 high_word
= (inst
>> 16) & 0xffff;
2789 low_word
= inst
& 0xffff;
2790 reg
= high_word
& 0x1f;
2792 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2793 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2794 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2796 if (low_word
& 0x8000) /* negative stack adjustment? */
2797 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2799 /* Exit loop if a positive stack adjustment is found, which
2800 usually means that the stack cleanup code in the function
2801 epilogue is reached. */
2804 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2806 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2807 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2809 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2811 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and
2813 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2814 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2816 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2818 /* Old gcc frame, r30 is virtual frame pointer. */
2819 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2820 frame_addr
= sp
+ low_word
;
2821 else if (PROC_FRAME_REG (&temp_proc_desc
) == MIPS_SP_REGNUM
)
2823 unsigned alloca_adjust
;
2824 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2825 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2826 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2827 if (alloca_adjust
> 0)
2829 /* FP > SP + frame_size. This may be because
2830 * of an alloca or somethings similar.
2831 * Fix sp to "pre-alloca" value, and try again.
2833 sp
+= alloca_adjust
;
2838 /* move $30,$sp. With different versions of gas this will be either
2839 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2840 Accept any one of these. */
2841 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2843 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2844 if (PROC_FRAME_REG (&temp_proc_desc
) == MIPS_SP_REGNUM
)
2846 unsigned alloca_adjust
;
2847 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2848 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2849 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2850 if (alloca_adjust
> 0)
2852 /* FP > SP + frame_size. This may be because
2853 * of an alloca or somethings similar.
2854 * Fix sp to "pre-alloca" value, and try again.
2856 sp
+= alloca_adjust
;
2861 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2863 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2864 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2869 static mips_extra_func_info_t
2870 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2871 struct frame_info
*next_frame
, int cur_frame
)
2876 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2882 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2883 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2884 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2885 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2886 PROC_FRAME_REG (&temp_proc_desc
) = MIPS_SP_REGNUM
;
2887 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2889 if (start_pc
+ 200 < limit_pc
)
2890 limit_pc
= start_pc
+ 200;
2891 if (pc_is_mips16 (start_pc
))
2892 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2894 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2895 return &temp_proc_desc
;
2898 struct mips_objfile_private
2904 /* Global used to communicate between non_heuristic_proc_desc and
2905 compare_pdr_entries within qsort (). */
2906 static bfd
*the_bfd
;
2909 compare_pdr_entries (const void *a
, const void *b
)
2911 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2912 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2916 else if (lhs
== rhs
)
2922 static mips_extra_func_info_t
2923 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2925 CORE_ADDR startaddr
;
2926 mips_extra_func_info_t proc_desc
;
2927 struct block
*b
= block_for_pc (pc
);
2929 struct obj_section
*sec
;
2930 struct mips_objfile_private
*priv
;
2932 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2934 *addrptr
= startaddr
;
2938 sec
= find_pc_section (pc
);
2941 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2943 /* Search the ".pdr" section generated by GAS. This includes most of
2944 the information normally found in ECOFF PDRs. */
2946 the_bfd
= sec
->objfile
->obfd
;
2948 && (the_bfd
->format
== bfd_object
2949 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2950 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2952 /* Right now GAS only outputs the address as a four-byte sequence.
2953 This means that we should not bother with this method on 64-bit
2954 targets (until that is fixed). */
2956 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2957 sizeof (struct mips_objfile_private
));
2959 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2961 else if (priv
== NULL
)
2965 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2966 sizeof (struct mips_objfile_private
));
2968 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2971 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2972 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2974 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2975 priv
->contents
, 0, priv
->size
);
2977 /* In general, the .pdr section is sorted. However, in the
2978 presence of multiple code sections (and other corner cases)
2979 it can become unsorted. Sort it so that we can use a faster
2981 qsort (priv
->contents
, priv
->size
/ 32, 32,
2982 compare_pdr_entries
);
2987 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2991 if (priv
->size
!= 0)
2998 high
= priv
->size
/ 32;
3000 /* We've found a .pdr section describing this objfile. We want to
3001 find the entry which describes this code address. The .pdr
3002 information is not very descriptive; we have only a function
3003 start address. We have to look for the closest entry, because
3004 the local symbol at the beginning of this function may have
3005 been stripped - so if we ask the symbol table for the start
3006 address we may get a preceding global function. */
3008 /* First, find the last .pdr entry starting at or before PC. */
3011 mid
= (low
+ high
) / 2;
3013 ptr
= priv
->contents
+ mid
* 32;
3014 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
3015 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
3016 SECT_OFF_TEXT (sec
->objfile
));
3023 while (low
!= high
);
3025 /* Both low and high point one past the PDR of interest. If
3026 both are zero, that means this PC is before any region
3027 covered by a PDR, i.e. pdr_pc for the first PDR entry is
3031 ptr
= priv
->contents
+ (low
- 1) * 32;
3032 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
3033 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
3034 SECT_OFF_TEXT (sec
->objfile
));
3037 /* We don't have a range, so we have no way to know for sure
3038 whether we're in the correct PDR or a PDR for a preceding
3039 function and the current function was a stripped local
3040 symbol. But if the PDR's PC is at least as great as the
3041 best guess from the symbol table, assume that it does cover
3042 the right area; if a .pdr section is present at all then
3043 nearly every function will have an entry. The biggest exception
3044 will be the dynamic linker stubs; conveniently these are
3045 placed before .text instead of after. */
3047 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
3049 struct symbol
*sym
= find_pc_function (pc
);
3054 /* Fill in what we need of the proc_desc. */
3055 proc_desc
= (mips_extra_func_info_t
)
3056 obstack_alloc (&sec
->objfile
->objfile_obstack
,
3057 sizeof (struct mips_extra_func_info
));
3058 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
3060 /* Only used for dummy frames. */
3061 PROC_HIGH_ADDR (proc_desc
) = 0;
3063 PROC_FRAME_OFFSET (proc_desc
)
3064 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
3065 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3067 PROC_FRAME_ADJUST (proc_desc
) = 0;
3068 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3070 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3072 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3074 PROC_FREG_OFFSET (proc_desc
)
3075 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
3076 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3078 proc_desc
->pdr
.isym
= (long) sym
;
3088 if (startaddr
> BLOCK_START (b
))
3090 /* This is the "pathological" case referred to in a comment in
3091 print_frame_info. It might be better to move this check into
3096 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
3098 /* If we never found a PDR for this function in symbol reading, then
3099 examine prologues to find the information. */
3102 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
3103 if (PROC_FRAME_REG (proc_desc
) == -1)
3113 static mips_extra_func_info_t
3114 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
3116 mips_extra_func_info_t proc_desc
;
3117 CORE_ADDR startaddr
= 0;
3119 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
3123 /* IF this is the topmost frame AND
3124 * (this proc does not have debugging information OR
3125 * the PC is in the procedure prologue)
3126 * THEN create a "heuristic" proc_desc (by analyzing
3127 * the actual code) to replace the "official" proc_desc.
3129 if (next_frame
== NULL
)
3131 struct symtab_and_line val
;
3132 struct symbol
*proc_symbol
=
3133 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
3137 val
= find_pc_line (BLOCK_START
3138 (SYMBOL_BLOCK_VALUE (proc_symbol
)), 0);
3139 val
.pc
= val
.end
? val
.end
: pc
;
3141 if (!proc_symbol
|| pc
< val
.pc
)
3143 mips_extra_func_info_t found_heuristic
=
3144 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
3145 pc
, next_frame
, cur_frame
);
3146 if (found_heuristic
)
3147 proc_desc
= found_heuristic
;
3153 /* Is linked_proc_desc_table really necessary? It only seems to be used
3154 by procedure call dummys. However, the procedures being called ought
3155 to have their own proc_descs, and even if they don't,
3156 heuristic_proc_desc knows how to create them! */
3158 struct linked_proc_info
*link
;
3160 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
3161 if (PROC_LOW_ADDR (&link
->info
) <= pc
3162 && PROC_HIGH_ADDR (&link
->info
) > pc
)
3166 startaddr
= heuristic_proc_start (pc
);
3168 proc_desc
= heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
3173 /* MIPS stack frames are almost impenetrable. When execution stops,
3174 we basically have to look at symbol information for the function
3175 that we stopped in, which tells us *which* register (if any) is
3176 the base of the frame pointer, and what offset from that register
3177 the frame itself is at.
3179 This presents a problem when trying to examine a stack in memory
3180 (that isn't executing at the moment), using the "frame" command. We
3181 don't have a PC, nor do we have any registers except SP.
3183 This routine takes two arguments, SP and PC, and tries to make the
3184 cached frames look as if these two arguments defined a frame on the
3185 cache. This allows the rest of info frame to extract the important
3186 arguments without difficulty. */
3189 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
3192 error ("MIPS frame specifications require two arguments: sp and pc");
3194 return create_new_frame (argv
[0], argv
[1]);
3197 /* According to the current ABI, should the type be passed in a
3198 floating-point register (assuming that there is space)? When there
3199 is no FPU, FP are not even considered as possibile candidates for
3200 FP registers and, consequently this returns false - forces FP
3201 arguments into integer registers. */
3204 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
3206 return ((typecode
== TYPE_CODE_FLT
3208 && (typecode
== TYPE_CODE_STRUCT
3209 || typecode
== TYPE_CODE_UNION
)
3210 && TYPE_NFIELDS (arg_type
) == 1
3211 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
3212 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
3215 /* On o32, argument passing in GPRs depends on the alignment of the type being
3216 passed. Return 1 if this type must be aligned to a doubleword boundary. */
3219 mips_type_needs_double_align (struct type
*type
)
3221 enum type_code typecode
= TYPE_CODE (type
);
3223 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
3225 else if (typecode
== TYPE_CODE_STRUCT
)
3227 if (TYPE_NFIELDS (type
) < 1)
3229 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
3231 else if (typecode
== TYPE_CODE_UNION
)
3235 n
= TYPE_NFIELDS (type
);
3236 for (i
= 0; i
< n
; i
++)
3237 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
3244 /* Adjust the address downward (direction of stack growth) so that it
3245 is correctly aligned for a new stack frame. */
3247 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3249 return align_down (addr
, 16);
3252 /* Determine how a return value is stored within the MIPS register
3253 file, given the return type `valtype'. */
3255 struct return_value_word
3264 return_value_location (struct type
*valtype
,
3265 struct return_value_word
*hi
,
3266 struct return_value_word
*lo
)
3268 int len
= TYPE_LENGTH (valtype
);
3269 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3271 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3272 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3273 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3275 if (mips_abi_regsize (current_gdbarch
) < 8 && len
== 8)
3277 /* We need to break a 64bit float in two 32 bit halves and
3278 spread them across a floating-point register pair. */
3279 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3280 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3281 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3282 && register_size (current_gdbarch
,
3283 mips_regnum (current_gdbarch
)->
3284 fp0
) == 8) ? 4 : 0);
3285 hi
->reg_offset
= lo
->reg_offset
;
3286 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
3287 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
3293 /* The floating point value fits in a single floating-point
3295 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3296 && register_size (current_gdbarch
,
3297 mips_regnum (current_gdbarch
)->
3299 && len
== 4) ? 4 : 0);
3300 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
3311 /* Locate a result possibly spread across two registers. */
3313 lo
->reg
= regnum
+ 0;
3314 hi
->reg
= regnum
+ 1;
3315 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3316 && len
< mips_abi_regsize (current_gdbarch
))
3318 /* "un-left-justify" the value in the low register */
3319 lo
->reg_offset
= mips_abi_regsize (current_gdbarch
) - len
;
3324 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (current_gdbarch
) /* odd-size structs */
3325 && len
< mips_abi_regsize (current_gdbarch
) * 2
3326 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3327 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3329 /* "un-left-justify" the value spread across two registers. */
3330 lo
->reg_offset
= 2 * mips_abi_regsize (current_gdbarch
) - len
;
3331 lo
->len
= mips_abi_regsize (current_gdbarch
) - lo
->reg_offset
;
3333 hi
->len
= len
- lo
->len
;
3337 /* Only perform a partial copy of the second register. */
3340 if (len
> mips_abi_regsize (current_gdbarch
))
3342 lo
->len
= mips_abi_regsize (current_gdbarch
);
3343 hi
->len
= len
- mips_abi_regsize (current_gdbarch
);
3351 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3352 && register_size (current_gdbarch
, regnum
) == 8
3353 && mips_abi_regsize (current_gdbarch
) == 4)
3355 /* Account for the fact that only the least-signficant part
3356 of the register is being used */
3357 lo
->reg_offset
+= 4;
3358 hi
->reg_offset
+= 4;
3361 hi
->buf_offset
= lo
->len
;
3365 /* Should call_function allocate stack space for a struct return? */
3368 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
3370 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3371 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (current_gdbarch
));
3374 /* Should call_function pass struct by reference?
3375 For each architecture, structs are passed either by
3376 value or by reference, depending on their size. */
3379 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
3381 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
3382 int len
= TYPE_LENGTH (check_typedef (type
));
3383 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3385 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
3386 return (len
> mips_abi_regsize (current_gdbarch
));
3392 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3393 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3394 int nargs
, struct value
**args
, CORE_ADDR sp
,
3395 int struct_return
, CORE_ADDR struct_addr
)
3401 int stack_offset
= 0;
3402 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3403 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3405 /* For shared libraries, "t9" needs to point at the function
3407 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3409 /* Set the return address register to point to the entry point of
3410 the program, where a breakpoint lies in wait. */
3411 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3413 /* First ensure that the stack and structure return address (if any)
3414 are properly aligned. The stack has to be at least 64-bit
3415 aligned even on 32-bit machines, because doubles must be 64-bit
3416 aligned. For n32 and n64, stack frames need to be 128-bit
3417 aligned, so we round to this widest known alignment. */
3419 sp
= align_down (sp
, 16);
3420 struct_addr
= align_down (struct_addr
, 16);
3422 /* Now make space on the stack for the args. We allocate more
3423 than necessary for EABI, because the first few arguments are
3424 passed in registers, but that's OK. */
3425 for (argnum
= 0; argnum
< nargs
; argnum
++)
3426 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3427 mips_stack_argsize (gdbarch
));
3428 sp
-= align_up (len
, 16);
3431 fprintf_unfiltered (gdb_stdlog
,
3432 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
3433 paddr_nz (sp
), (long) align_up (len
, 16));
3435 /* Initialize the integer and float register pointers. */
3437 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3439 /* The struct_return pointer occupies the first parameter-passing reg. */
3443 fprintf_unfiltered (gdb_stdlog
,
3444 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
3445 argreg
, paddr_nz (struct_addr
));
3446 write_register (argreg
++, struct_addr
);
3449 /* Now load as many as possible of the first arguments into
3450 registers, and push the rest onto the stack. Loop thru args
3451 from first to last. */
3452 for (argnum
= 0; argnum
< nargs
; argnum
++)
3455 char valbuf
[MAX_REGISTER_SIZE
];
3456 struct value
*arg
= args
[argnum
];
3457 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3458 int len
= TYPE_LENGTH (arg_type
);
3459 enum type_code typecode
= TYPE_CODE (arg_type
);
3462 fprintf_unfiltered (gdb_stdlog
,
3463 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3464 argnum
+ 1, len
, (int) typecode
);
3466 /* The EABI passes structures that do not fit in a register by
3468 if (len
> mips_abi_regsize (gdbarch
)
3469 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3471 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
3472 VALUE_ADDRESS (arg
));
3473 typecode
= TYPE_CODE_PTR
;
3474 len
= mips_abi_regsize (gdbarch
);
3477 fprintf_unfiltered (gdb_stdlog
, " push");
3480 val
= (char *) VALUE_CONTENTS (arg
);
3482 /* 32-bit ABIs always start floating point arguments in an
3483 even-numbered floating point register. Round the FP register
3484 up before the check to see if there are any FP registers
3485 left. Non MIPS_EABI targets also pass the FP in the integer
3486 registers so also round up normal registers. */
3487 if (mips_abi_regsize (gdbarch
) < 8
3488 && fp_register_arg_p (typecode
, arg_type
))
3490 if ((float_argreg
& 1))
3494 /* Floating point arguments passed in registers have to be
3495 treated specially. On 32-bit architectures, doubles
3496 are passed in register pairs; the even register gets
3497 the low word, and the odd register gets the high word.
3498 On non-EABI processors, the first two floating point arguments are
3499 also copied to general registers, because MIPS16 functions
3500 don't use float registers for arguments. This duplication of
3501 arguments in general registers can't hurt non-MIPS16 functions
3502 because those registers are normally skipped. */
3503 /* MIPS_EABI squeezes a struct that contains a single floating
3504 point value into an FP register instead of pushing it onto the
3506 if (fp_register_arg_p (typecode
, arg_type
)
3507 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3509 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3511 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3512 unsigned long regval
;
3514 /* Write the low word of the double to the even register(s). */
3515 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3517 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3518 float_argreg
, phex (regval
, 4));
3519 write_register (float_argreg
++, regval
);
3521 /* Write the high word of the double to the odd register(s). */
3522 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3524 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3525 float_argreg
, phex (regval
, 4));
3526 write_register (float_argreg
++, regval
);
3530 /* This is a floating point value that fits entirely
3531 in a single register. */
3532 /* On 32 bit ABI's the float_argreg is further adjusted
3533 above to ensure that it is even register aligned. */
3534 LONGEST regval
= extract_unsigned_integer (val
, len
);
3536 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3537 float_argreg
, phex (regval
, len
));
3538 write_register (float_argreg
++, regval
);
3543 /* Copy the argument to general registers or the stack in
3544 register-sized pieces. Large arguments are split between
3545 registers and stack. */
3546 /* Note: structs whose size is not a multiple of
3547 mips_abi_regsize() are treated specially: Irix cc passes
3548 them in registers where gcc sometimes puts them on the
3549 stack. For maximum compatibility, we will put them in
3551 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3552 && (len
% mips_abi_regsize (gdbarch
) != 0));
3554 /* Note: Floating-point values that didn't fit into an FP
3555 register are only written to memory. */
3558 /* Remember if the argument was written to the stack. */
3559 int stack_used_p
= 0;
3560 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3561 ? len
: mips_abi_regsize (gdbarch
));
3564 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3567 /* Write this portion of the argument to the stack. */
3568 if (argreg
> MIPS_LAST_ARG_REGNUM
3570 || fp_register_arg_p (typecode
, arg_type
))
3572 /* Should shorter than int integer values be
3573 promoted to int before being stored? */
3574 int longword_offset
= 0;
3577 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3579 if (mips_stack_argsize (gdbarch
) == 8
3580 && (typecode
== TYPE_CODE_INT
3581 || typecode
== TYPE_CODE_PTR
3582 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3583 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3584 else if ((typecode
== TYPE_CODE_STRUCT
3585 || typecode
== TYPE_CODE_UNION
)
3586 && (TYPE_LENGTH (arg_type
)
3587 < mips_stack_argsize (gdbarch
)))
3588 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3593 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3594 paddr_nz (stack_offset
));
3595 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3596 paddr_nz (longword_offset
));
3599 addr
= sp
+ stack_offset
+ longword_offset
;
3604 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3606 for (i
= 0; i
< partial_len
; i
++)
3608 fprintf_unfiltered (gdb_stdlog
, "%02x",
3612 write_memory (addr
, val
, partial_len
);
3615 /* Note!!! This is NOT an else clause. Odd sized
3616 structs may go thru BOTH paths. Floating point
3617 arguments will not. */
3618 /* Write this portion of the argument to a general
3619 purpose register. */
3620 if (argreg
<= MIPS_LAST_ARG_REGNUM
3621 && !fp_register_arg_p (typecode
, arg_type
))
3624 extract_unsigned_integer (val
, partial_len
);
3627 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3630 mips_abi_regsize (gdbarch
)));
3631 write_register (argreg
, regval
);
3638 /* Compute the the offset into the stack at which we
3639 will copy the next parameter.
3641 In the new EABI (and the NABI32), the stack_offset
3642 only needs to be adjusted when it has been used. */
3645 stack_offset
+= align_up (partial_len
,
3646 mips_stack_argsize (gdbarch
));
3650 fprintf_unfiltered (gdb_stdlog
, "\n");
3653 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3655 /* Return adjusted stack pointer. */
3659 /* Given a return value in `regbuf' with a type `valtype', extract and
3660 copy its value into `valbuf'. */
3663 mips_eabi_extract_return_value (struct type
*valtype
,
3664 char regbuf
[], char *valbuf
)
3666 struct return_value_word lo
;
3667 struct return_value_word hi
;
3668 return_value_location (valtype
, &hi
, &lo
);
3670 memcpy (valbuf
+ lo
.buf_offset
,
3671 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3672 lo
.reg_offset
, lo
.len
);
3675 memcpy (valbuf
+ hi
.buf_offset
,
3676 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3677 hi
.reg_offset
, hi
.len
);
3680 /* Given a return value in `valbuf' with a type `valtype', write it's
3681 value into the appropriate register. */
3684 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3686 char raw_buffer
[MAX_REGISTER_SIZE
];
3687 struct return_value_word lo
;
3688 struct return_value_word hi
;
3689 return_value_location (valtype
, &hi
, &lo
);
3691 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3692 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3693 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3694 raw_buffer
, register_size (current_gdbarch
,
3699 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3700 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3701 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3703 register_size (current_gdbarch
,
3708 /* N32/N64 ABI stuff. */
3711 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3712 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3713 int nargs
, struct value
**args
, CORE_ADDR sp
,
3714 int struct_return
, CORE_ADDR struct_addr
)
3720 int stack_offset
= 0;
3721 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3722 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3724 /* For shared libraries, "t9" needs to point at the function
3726 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3728 /* Set the return address register to point to the entry point of
3729 the program, where a breakpoint lies in wait. */
3730 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3732 /* First ensure that the stack and structure return address (if any)
3733 are properly aligned. The stack has to be at least 64-bit
3734 aligned even on 32-bit machines, because doubles must be 64-bit
3735 aligned. For n32 and n64, stack frames need to be 128-bit
3736 aligned, so we round to this widest known alignment. */
3738 sp
= align_down (sp
, 16);
3739 struct_addr
= align_down (struct_addr
, 16);
3741 /* Now make space on the stack for the args. */
3742 for (argnum
= 0; argnum
< nargs
; argnum
++)
3743 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3744 mips_stack_argsize (gdbarch
));
3745 sp
-= align_up (len
, 16);
3748 fprintf_unfiltered (gdb_stdlog
,
3749 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3750 paddr_nz (sp
), (long) align_up (len
, 16));
3752 /* Initialize the integer and float register pointers. */
3754 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3756 /* The struct_return pointer occupies the first parameter-passing reg. */
3760 fprintf_unfiltered (gdb_stdlog
,
3761 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3762 argreg
, paddr_nz (struct_addr
));
3763 write_register (argreg
++, struct_addr
);
3766 /* Now load as many as possible of the first arguments into
3767 registers, and push the rest onto the stack. Loop thru args
3768 from first to last. */
3769 for (argnum
= 0; argnum
< nargs
; argnum
++)
3772 struct value
*arg
= args
[argnum
];
3773 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3774 int len
= TYPE_LENGTH (arg_type
);
3775 enum type_code typecode
= TYPE_CODE (arg_type
);
3778 fprintf_unfiltered (gdb_stdlog
,
3779 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3780 argnum
+ 1, len
, (int) typecode
);
3782 val
= (char *) VALUE_CONTENTS (arg
);
3784 if (fp_register_arg_p (typecode
, arg_type
)
3785 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3787 /* This is a floating point value that fits entirely
3788 in a single register. */
3789 /* On 32 bit ABI's the float_argreg is further adjusted
3790 above to ensure that it is even register aligned. */
3791 LONGEST regval
= extract_unsigned_integer (val
, len
);
3793 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3794 float_argreg
, phex (regval
, len
));
3795 write_register (float_argreg
++, regval
);
3798 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3799 argreg
, phex (regval
, len
));
3800 write_register (argreg
, regval
);
3805 /* Copy the argument to general registers or the stack in
3806 register-sized pieces. Large arguments are split between
3807 registers and stack. */
3808 /* Note: structs whose size is not a multiple of
3809 mips_abi_regsize() are treated specially: Irix cc passes
3810 them in registers where gcc sometimes puts them on the
3811 stack. For maximum compatibility, we will put them in
3813 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3814 && (len
% mips_abi_regsize (gdbarch
) != 0));
3815 /* Note: Floating-point values that didn't fit into an FP
3816 register are only written to memory. */
3819 /* Rememer if the argument was written to the stack. */
3820 int stack_used_p
= 0;
3821 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3822 ? len
: mips_abi_regsize (gdbarch
));
3825 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3828 /* Write this portion of the argument to the stack. */
3829 if (argreg
> MIPS_LAST_ARG_REGNUM
3831 || fp_register_arg_p (typecode
, arg_type
))
3833 /* Should shorter than int integer values be
3834 promoted to int before being stored? */
3835 int longword_offset
= 0;
3838 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3840 if (mips_stack_argsize (gdbarch
) == 8
3841 && (typecode
== TYPE_CODE_INT
3842 || typecode
== TYPE_CODE_PTR
3843 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3844 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3849 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3850 paddr_nz (stack_offset
));
3851 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3852 paddr_nz (longword_offset
));
3855 addr
= sp
+ stack_offset
+ longword_offset
;
3860 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3862 for (i
= 0; i
< partial_len
; i
++)
3864 fprintf_unfiltered (gdb_stdlog
, "%02x",
3868 write_memory (addr
, val
, partial_len
);
3871 /* Note!!! This is NOT an else clause. Odd sized
3872 structs may go thru BOTH paths. Floating point
3873 arguments will not. */
3874 /* Write this portion of the argument to a general
3875 purpose register. */
3876 if (argreg
<= MIPS_LAST_ARG_REGNUM
3877 && !fp_register_arg_p (typecode
, arg_type
))
3880 extract_unsigned_integer (val
, partial_len
);
3882 /* A non-floating-point argument being passed in a
3883 general register. If a struct or union, and if
3884 the remaining length is smaller than the register
3885 size, we have to adjust the register value on
3888 It does not seem to be necessary to do the
3889 same for integral types.
3891 cagney/2001-07-23: gdb/179: Also, GCC, when
3892 outputting LE O32 with sizeof (struct) <
3893 mips_abi_regsize(), generates a left shift as
3894 part of storing the argument in a register a
3895 register (the left shift isn't generated when
3896 sizeof (struct) >= mips_abi_regsize()). Since
3897 it is quite possible that this is GCC
3898 contradicting the LE/O32 ABI, GDB has not been
3899 adjusted to accommodate this. Either someone
3900 needs to demonstrate that the LE/O32 ABI
3901 specifies such a left shift OR this new ABI gets
3902 identified as such and GDB gets tweaked
3905 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3906 && partial_len
< mips_abi_regsize (gdbarch
)
3907 && (typecode
== TYPE_CODE_STRUCT
||
3908 typecode
== TYPE_CODE_UNION
))
3909 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3913 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3916 mips_abi_regsize (gdbarch
)));
3917 write_register (argreg
, regval
);
3924 /* Compute the the offset into the stack at which we
3925 will copy the next parameter.
3927 In N32 (N64?), the stack_offset only needs to be
3928 adjusted when it has been used. */
3931 stack_offset
+= align_up (partial_len
,
3932 mips_stack_argsize (gdbarch
));
3936 fprintf_unfiltered (gdb_stdlog
, "\n");
3939 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3941 /* Return adjusted stack pointer. */
3945 static enum return_value_convention
3946 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3947 struct type
*type
, struct regcache
*regcache
,
3948 void *readbuf
, const void *writebuf
)
3950 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3951 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3952 || TYPE_CODE (type
) == TYPE_CODE_UNION
3953 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3954 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3955 return RETURN_VALUE_STRUCT_CONVENTION
;
3956 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3957 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3959 /* A floating-point value belongs in the least significant part
3962 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3963 mips_xfer_register (regcache
,
3964 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3966 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3967 return RETURN_VALUE_REGISTER_CONVENTION
;
3969 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3970 && TYPE_NFIELDS (type
) <= 2
3971 && TYPE_NFIELDS (type
) >= 1
3972 && ((TYPE_NFIELDS (type
) == 1
3973 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3975 || (TYPE_NFIELDS (type
) == 2
3976 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3978 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3980 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3982 /* A struct that contains one or two floats. Each value is part
3983 in the least significant part of their floating point
3987 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3988 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3990 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3993 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3995 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3996 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3997 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3999 return RETURN_VALUE_REGISTER_CONVENTION
;
4001 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4002 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4004 /* A structure or union. Extract the left justified value,
4005 regardless of the byte order. I.e. DO NOT USE
4009 for (offset
= 0, regnum
= V0_REGNUM
;
4010 offset
< TYPE_LENGTH (type
);
4011 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4013 int xfer
= register_size (current_gdbarch
, regnum
);
4014 if (offset
+ xfer
> TYPE_LENGTH (type
))
4015 xfer
= TYPE_LENGTH (type
) - offset
;
4017 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4018 offset
, xfer
, regnum
);
4019 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4020 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4022 return RETURN_VALUE_REGISTER_CONVENTION
;
4026 /* A scalar extract each part but least-significant-byte
4030 for (offset
= 0, regnum
= V0_REGNUM
;
4031 offset
< TYPE_LENGTH (type
);
4032 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4034 int xfer
= register_size (current_gdbarch
, regnum
);
4035 if (offset
+ xfer
> TYPE_LENGTH (type
))
4036 xfer
= TYPE_LENGTH (type
) - offset
;
4038 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4039 offset
, xfer
, regnum
);
4040 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4041 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4043 return RETURN_VALUE_REGISTER_CONVENTION
;
4047 /* O32 ABI stuff. */
4050 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4051 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4052 int nargs
, struct value
**args
, CORE_ADDR sp
,
4053 int struct_return
, CORE_ADDR struct_addr
)
4059 int stack_offset
= 0;
4060 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4061 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4063 /* For shared libraries, "t9" needs to point at the function
4065 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4067 /* Set the return address register to point to the entry point of
4068 the program, where a breakpoint lies in wait. */
4069 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4071 /* First ensure that the stack and structure return address (if any)
4072 are properly aligned. The stack has to be at least 64-bit
4073 aligned even on 32-bit machines, because doubles must be 64-bit
4074 aligned. For n32 and n64, stack frames need to be 128-bit
4075 aligned, so we round to this widest known alignment. */
4077 sp
= align_down (sp
, 16);
4078 struct_addr
= align_down (struct_addr
, 16);
4080 /* Now make space on the stack for the args. */
4081 for (argnum
= 0; argnum
< nargs
; argnum
++)
4082 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4083 mips_stack_argsize (gdbarch
));
4084 sp
-= align_up (len
, 16);
4087 fprintf_unfiltered (gdb_stdlog
,
4088 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
4089 paddr_nz (sp
), (long) align_up (len
, 16));
4091 /* Initialize the integer and float register pointers. */
4093 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4095 /* The struct_return pointer occupies the first parameter-passing reg. */
4099 fprintf_unfiltered (gdb_stdlog
,
4100 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
4101 argreg
, paddr_nz (struct_addr
));
4102 write_register (argreg
++, struct_addr
);
4103 stack_offset
+= mips_stack_argsize (gdbarch
);
4106 /* Now load as many as possible of the first arguments into
4107 registers, and push the rest onto the stack. Loop thru args
4108 from first to last. */
4109 for (argnum
= 0; argnum
< nargs
; argnum
++)
4112 struct value
*arg
= args
[argnum
];
4113 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4114 int len
= TYPE_LENGTH (arg_type
);
4115 enum type_code typecode
= TYPE_CODE (arg_type
);
4118 fprintf_unfiltered (gdb_stdlog
,
4119 "mips_o32_push_dummy_call: %d len=%d type=%d",
4120 argnum
+ 1, len
, (int) typecode
);
4122 val
= (char *) VALUE_CONTENTS (arg
);
4124 /* 32-bit ABIs always start floating point arguments in an
4125 even-numbered floating point register. Round the FP register
4126 up before the check to see if there are any FP registers
4127 left. O32/O64 targets also pass the FP in the integer
4128 registers so also round up normal registers. */
4129 if (mips_abi_regsize (gdbarch
) < 8
4130 && fp_register_arg_p (typecode
, arg_type
))
4132 if ((float_argreg
& 1))
4136 /* Floating point arguments passed in registers have to be
4137 treated specially. On 32-bit architectures, doubles
4138 are passed in register pairs; the even register gets
4139 the low word, and the odd register gets the high word.
4140 On O32/O64, the first two floating point arguments are
4141 also copied to general registers, because MIPS16 functions
4142 don't use float registers for arguments. This duplication of
4143 arguments in general registers can't hurt non-MIPS16 functions
4144 because those registers are normally skipped. */
4146 if (fp_register_arg_p (typecode
, arg_type
)
4147 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4149 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4151 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4152 unsigned long regval
;
4154 /* Write the low word of the double to the even register(s). */
4155 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4157 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4158 float_argreg
, phex (regval
, 4));
4159 write_register (float_argreg
++, regval
);
4161 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4162 argreg
, phex (regval
, 4));
4163 write_register (argreg
++, regval
);
4165 /* Write the high word of the double to the odd register(s). */
4166 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4168 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4169 float_argreg
, phex (regval
, 4));
4170 write_register (float_argreg
++, regval
);
4173 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4174 argreg
, phex (regval
, 4));
4175 write_register (argreg
++, regval
);
4179 /* This is a floating point value that fits entirely
4180 in a single register. */
4181 /* On 32 bit ABI's the float_argreg is further adjusted
4182 above to ensure that it is even register aligned. */
4183 LONGEST regval
= extract_unsigned_integer (val
, len
);
4185 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4186 float_argreg
, phex (regval
, len
));
4187 write_register (float_argreg
++, regval
);
4188 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4189 registers for each argument. The below is (my
4190 guess) to ensure that the corresponding integer
4191 register has reserved the same space. */
4193 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4194 argreg
, phex (regval
, len
));
4195 write_register (argreg
, regval
);
4196 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4198 /* Reserve space for the FP register. */
4199 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4203 /* Copy the argument to general registers or the stack in
4204 register-sized pieces. Large arguments are split between
4205 registers and stack. */
4206 /* Note: structs whose size is not a multiple of
4207 mips_abi_regsize() are treated specially: Irix cc passes
4208 them in registers where gcc sometimes puts them on the
4209 stack. For maximum compatibility, we will put them in
4211 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4212 && (len
% mips_abi_regsize (gdbarch
) != 0));
4213 /* Structures should be aligned to eight bytes (even arg registers)
4214 on MIPS_ABI_O32, if their first member has double precision. */
4215 if (mips_abi_regsize (gdbarch
) < 8
4216 && mips_type_needs_double_align (arg_type
))
4221 /* Note: Floating-point values that didn't fit into an FP
4222 register are only written to memory. */
4225 /* Remember if the argument was written to the stack. */
4226 int stack_used_p
= 0;
4227 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4228 ? len
: mips_abi_regsize (gdbarch
));
4231 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4234 /* Write this portion of the argument to the stack. */
4235 if (argreg
> MIPS_LAST_ARG_REGNUM
4237 || fp_register_arg_p (typecode
, arg_type
))
4239 /* Should shorter than int integer values be
4240 promoted to int before being stored? */
4241 int longword_offset
= 0;
4244 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4246 if (mips_stack_argsize (gdbarch
) == 8
4247 && (typecode
== TYPE_CODE_INT
4248 || typecode
== TYPE_CODE_PTR
4249 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4250 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4255 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4256 paddr_nz (stack_offset
));
4257 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4258 paddr_nz (longword_offset
));
4261 addr
= sp
+ stack_offset
+ longword_offset
;
4266 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4268 for (i
= 0; i
< partial_len
; i
++)
4270 fprintf_unfiltered (gdb_stdlog
, "%02x",
4274 write_memory (addr
, val
, partial_len
);
4277 /* Note!!! This is NOT an else clause. Odd sized
4278 structs may go thru BOTH paths. Floating point
4279 arguments will not. */
4280 /* Write this portion of the argument to a general
4281 purpose register. */
4282 if (argreg
<= MIPS_LAST_ARG_REGNUM
4283 && !fp_register_arg_p (typecode
, arg_type
))
4285 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4286 /* Value may need to be sign extended, because
4287 mips_isa_regsize() != mips_abi_regsize(). */
4289 /* A non-floating-point argument being passed in a
4290 general register. If a struct or union, and if
4291 the remaining length is smaller than the register
4292 size, we have to adjust the register value on
4295 It does not seem to be necessary to do the
4296 same for integral types.
4298 Also don't do this adjustment on O64 binaries.
4300 cagney/2001-07-23: gdb/179: Also, GCC, when
4301 outputting LE O32 with sizeof (struct) <
4302 mips_abi_regsize(), generates a left shift as
4303 part of storing the argument in a register a
4304 register (the left shift isn't generated when
4305 sizeof (struct) >= mips_abi_regsize()). Since
4306 it is quite possible that this is GCC
4307 contradicting the LE/O32 ABI, GDB has not been
4308 adjusted to accommodate this. Either someone
4309 needs to demonstrate that the LE/O32 ABI
4310 specifies such a left shift OR this new ABI gets
4311 identified as such and GDB gets tweaked
4314 if (mips_abi_regsize (gdbarch
) < 8
4315 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4316 && partial_len
< mips_abi_regsize (gdbarch
)
4317 && (typecode
== TYPE_CODE_STRUCT
||
4318 typecode
== TYPE_CODE_UNION
))
4319 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4323 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4326 mips_abi_regsize (gdbarch
)));
4327 write_register (argreg
, regval
);
4330 /* Prevent subsequent floating point arguments from
4331 being passed in floating point registers. */
4332 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4338 /* Compute the the offset into the stack at which we
4339 will copy the next parameter.
4341 In older ABIs, the caller reserved space for
4342 registers that contained arguments. This was loosely
4343 refered to as their "home". Consequently, space is
4344 always allocated. */
4346 stack_offset
+= align_up (partial_len
,
4347 mips_stack_argsize (gdbarch
));
4351 fprintf_unfiltered (gdb_stdlog
, "\n");
4354 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4356 /* Return adjusted stack pointer. */
4360 static enum return_value_convention
4361 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4362 struct regcache
*regcache
,
4363 void *readbuf
, const void *writebuf
)
4365 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4367 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4368 || TYPE_CODE (type
) == TYPE_CODE_UNION
4369 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4370 return RETURN_VALUE_STRUCT_CONVENTION
;
4371 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4372 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4374 /* A single-precision floating-point value. It fits in the
4375 least significant part of FP0. */
4377 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4378 mips_xfer_register (regcache
,
4379 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4381 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4382 return RETURN_VALUE_REGISTER_CONVENTION
;
4384 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4385 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4387 /* A double-precision floating-point value. The most
4388 significant part goes in FP1, and the least significant in
4391 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4392 switch (TARGET_BYTE_ORDER
)
4394 case BFD_ENDIAN_LITTLE
:
4395 mips_xfer_register (regcache
,
4396 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4397 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4398 mips_xfer_register (regcache
,
4399 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4400 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4402 case BFD_ENDIAN_BIG
:
4403 mips_xfer_register (regcache
,
4404 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4405 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4406 mips_xfer_register (regcache
,
4407 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4408 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4411 internal_error (__FILE__
, __LINE__
, "bad switch");
4413 return RETURN_VALUE_REGISTER_CONVENTION
;
4416 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4417 && TYPE_NFIELDS (type
) <= 2
4418 && TYPE_NFIELDS (type
) >= 1
4419 && ((TYPE_NFIELDS (type
) == 1
4420 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4422 || (TYPE_NFIELDS (type
) == 2
4423 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4425 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4427 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4429 /* A struct that contains one or two floats. Each value is part
4430 in the least significant part of their floating point
4432 bfd_byte reg
[MAX_REGISTER_SIZE
];
4435 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4436 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4438 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4441 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4443 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4444 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4445 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4447 return RETURN_VALUE_REGISTER_CONVENTION
;
4451 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4452 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4454 /* A structure or union. Extract the left justified value,
4455 regardless of the byte order. I.e. DO NOT USE
4459 for (offset
= 0, regnum
= V0_REGNUM
;
4460 offset
< TYPE_LENGTH (type
);
4461 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4463 int xfer
= register_size (current_gdbarch
, regnum
);
4464 if (offset
+ xfer
> TYPE_LENGTH (type
))
4465 xfer
= TYPE_LENGTH (type
) - offset
;
4467 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4468 offset
, xfer
, regnum
);
4469 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4470 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4472 return RETURN_VALUE_REGISTER_CONVENTION
;
4477 /* A scalar extract each part but least-significant-byte
4478 justified. o32 thinks registers are 4 byte, regardless of
4479 the ISA. mips_stack_argsize controls this. */
4482 for (offset
= 0, regnum
= V0_REGNUM
;
4483 offset
< TYPE_LENGTH (type
);
4484 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
4486 int xfer
= mips_stack_argsize (gdbarch
);
4487 if (offset
+ xfer
> TYPE_LENGTH (type
))
4488 xfer
= TYPE_LENGTH (type
) - offset
;
4490 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4491 offset
, xfer
, regnum
);
4492 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4493 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4495 return RETURN_VALUE_REGISTER_CONVENTION
;
4499 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4503 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4504 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4506 struct value
**args
, CORE_ADDR sp
,
4507 int struct_return
, CORE_ADDR struct_addr
)
4513 int stack_offset
= 0;
4514 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4515 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4517 /* For shared libraries, "t9" needs to point at the function
4519 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4521 /* Set the return address register to point to the entry point of
4522 the program, where a breakpoint lies in wait. */
4523 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4525 /* First ensure that the stack and structure return address (if any)
4526 are properly aligned. The stack has to be at least 64-bit
4527 aligned even on 32-bit machines, because doubles must be 64-bit
4528 aligned. For n32 and n64, stack frames need to be 128-bit
4529 aligned, so we round to this widest known alignment. */
4531 sp
= align_down (sp
, 16);
4532 struct_addr
= align_down (struct_addr
, 16);
4534 /* Now make space on the stack for the args. */
4535 for (argnum
= 0; argnum
< nargs
; argnum
++)
4536 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4537 mips_stack_argsize (gdbarch
));
4538 sp
-= align_up (len
, 16);
4541 fprintf_unfiltered (gdb_stdlog
,
4542 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4543 paddr_nz (sp
), (long) align_up (len
, 16));
4545 /* Initialize the integer and float register pointers. */
4547 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4549 /* The struct_return pointer occupies the first parameter-passing reg. */
4553 fprintf_unfiltered (gdb_stdlog
,
4554 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4555 argreg
, paddr_nz (struct_addr
));
4556 write_register (argreg
++, struct_addr
);
4557 stack_offset
+= mips_stack_argsize (gdbarch
);
4560 /* Now load as many as possible of the first arguments into
4561 registers, and push the rest onto the stack. Loop thru args
4562 from first to last. */
4563 for (argnum
= 0; argnum
< nargs
; argnum
++)
4566 struct value
*arg
= args
[argnum
];
4567 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4568 int len
= TYPE_LENGTH (arg_type
);
4569 enum type_code typecode
= TYPE_CODE (arg_type
);
4572 fprintf_unfiltered (gdb_stdlog
,
4573 "mips_o64_push_dummy_call: %d len=%d type=%d",
4574 argnum
+ 1, len
, (int) typecode
);
4576 val
= (char *) VALUE_CONTENTS (arg
);
4578 /* 32-bit ABIs always start floating point arguments in an
4579 even-numbered floating point register. Round the FP register
4580 up before the check to see if there are any FP registers
4581 left. O32/O64 targets also pass the FP in the integer
4582 registers so also round up normal registers. */
4583 if (mips_abi_regsize (gdbarch
) < 8
4584 && fp_register_arg_p (typecode
, arg_type
))
4586 if ((float_argreg
& 1))
4590 /* Floating point arguments passed in registers have to be
4591 treated specially. On 32-bit architectures, doubles
4592 are passed in register pairs; the even register gets
4593 the low word, and the odd register gets the high word.
4594 On O32/O64, the first two floating point arguments are
4595 also copied to general registers, because MIPS16 functions
4596 don't use float registers for arguments. This duplication of
4597 arguments in general registers can't hurt non-MIPS16 functions
4598 because those registers are normally skipped. */
4600 if (fp_register_arg_p (typecode
, arg_type
)
4601 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4603 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4605 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4606 unsigned long regval
;
4608 /* Write the low word of the double to the even register(s). */
4609 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4611 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4612 float_argreg
, phex (regval
, 4));
4613 write_register (float_argreg
++, regval
);
4615 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4616 argreg
, phex (regval
, 4));
4617 write_register (argreg
++, regval
);
4619 /* Write the high word of the double to the odd register(s). */
4620 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4622 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4623 float_argreg
, phex (regval
, 4));
4624 write_register (float_argreg
++, regval
);
4627 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4628 argreg
, phex (regval
, 4));
4629 write_register (argreg
++, regval
);
4633 /* This is a floating point value that fits entirely
4634 in a single register. */
4635 /* On 32 bit ABI's the float_argreg is further adjusted
4636 above to ensure that it is even register aligned. */
4637 LONGEST regval
= extract_unsigned_integer (val
, len
);
4639 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4640 float_argreg
, phex (regval
, len
));
4641 write_register (float_argreg
++, regval
);
4642 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4643 registers for each argument. The below is (my
4644 guess) to ensure that the corresponding integer
4645 register has reserved the same space. */
4647 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4648 argreg
, phex (regval
, len
));
4649 write_register (argreg
, regval
);
4650 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4652 /* Reserve space for the FP register. */
4653 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4657 /* Copy the argument to general registers or the stack in
4658 register-sized pieces. Large arguments are split between
4659 registers and stack. */
4660 /* Note: structs whose size is not a multiple of
4661 mips_abi_regsize() are treated specially: Irix cc passes
4662 them in registers where gcc sometimes puts them on the
4663 stack. For maximum compatibility, we will put them in
4665 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4666 && (len
% mips_abi_regsize (gdbarch
) != 0));
4667 /* Structures should be aligned to eight bytes (even arg registers)
4668 on MIPS_ABI_O32, if their first member has double precision. */
4669 if (mips_abi_regsize (gdbarch
) < 8
4670 && mips_type_needs_double_align (arg_type
))
4675 /* Note: Floating-point values that didn't fit into an FP
4676 register are only written to memory. */
4679 /* Remember if the argument was written to the stack. */
4680 int stack_used_p
= 0;
4681 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4682 ? len
: mips_abi_regsize (gdbarch
));
4685 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4688 /* Write this portion of the argument to the stack. */
4689 if (argreg
> MIPS_LAST_ARG_REGNUM
4691 || fp_register_arg_p (typecode
, arg_type
))
4693 /* Should shorter than int integer values be
4694 promoted to int before being stored? */
4695 int longword_offset
= 0;
4698 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4700 if (mips_stack_argsize (gdbarch
) == 8
4701 && (typecode
== TYPE_CODE_INT
4702 || typecode
== TYPE_CODE_PTR
4703 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4704 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4709 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4710 paddr_nz (stack_offset
));
4711 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4712 paddr_nz (longword_offset
));
4715 addr
= sp
+ stack_offset
+ longword_offset
;
4720 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4722 for (i
= 0; i
< partial_len
; i
++)
4724 fprintf_unfiltered (gdb_stdlog
, "%02x",
4728 write_memory (addr
, val
, partial_len
);
4731 /* Note!!! This is NOT an else clause. Odd sized
4732 structs may go thru BOTH paths. Floating point
4733 arguments will not. */
4734 /* Write this portion of the argument to a general
4735 purpose register. */
4736 if (argreg
<= MIPS_LAST_ARG_REGNUM
4737 && !fp_register_arg_p (typecode
, arg_type
))
4739 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4740 /* Value may need to be sign extended, because
4741 mips_isa_regsize() != mips_abi_regsize(). */
4743 /* A non-floating-point argument being passed in a
4744 general register. If a struct or union, and if
4745 the remaining length is smaller than the register
4746 size, we have to adjust the register value on
4749 It does not seem to be necessary to do the
4750 same for integral types.
4752 Also don't do this adjustment on O64 binaries.
4754 cagney/2001-07-23: gdb/179: Also, GCC, when
4755 outputting LE O32 with sizeof (struct) <
4756 mips_abi_regsize(), generates a left shift as
4757 part of storing the argument in a register a
4758 register (the left shift isn't generated when
4759 sizeof (struct) >= mips_abi_regsize()). Since
4760 it is quite possible that this is GCC
4761 contradicting the LE/O32 ABI, GDB has not been
4762 adjusted to accommodate this. Either someone
4763 needs to demonstrate that the LE/O32 ABI
4764 specifies such a left shift OR this new ABI gets
4765 identified as such and GDB gets tweaked
4768 if (mips_abi_regsize (gdbarch
) < 8
4769 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4770 && partial_len
< mips_abi_regsize (gdbarch
)
4771 && (typecode
== TYPE_CODE_STRUCT
||
4772 typecode
== TYPE_CODE_UNION
))
4773 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4777 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4780 mips_abi_regsize (gdbarch
)));
4781 write_register (argreg
, regval
);
4784 /* Prevent subsequent floating point arguments from
4785 being passed in floating point registers. */
4786 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4792 /* Compute the the offset into the stack at which we
4793 will copy the next parameter.
4795 In older ABIs, the caller reserved space for
4796 registers that contained arguments. This was loosely
4797 refered to as their "home". Consequently, space is
4798 always allocated. */
4800 stack_offset
+= align_up (partial_len
,
4801 mips_stack_argsize (gdbarch
));
4805 fprintf_unfiltered (gdb_stdlog
, "\n");
4808 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4810 /* Return adjusted stack pointer. */
4815 mips_o64_extract_return_value (struct type
*valtype
,
4816 char regbuf
[], char *valbuf
)
4818 struct return_value_word lo
;
4819 struct return_value_word hi
;
4820 return_value_location (valtype
, &hi
, &lo
);
4822 memcpy (valbuf
+ lo
.buf_offset
,
4823 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4824 lo
.reg_offset
, lo
.len
);
4827 memcpy (valbuf
+ hi
.buf_offset
,
4828 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4829 hi
.reg_offset
, hi
.len
);
4833 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4835 char raw_buffer
[MAX_REGISTER_SIZE
];
4836 struct return_value_word lo
;
4837 struct return_value_word hi
;
4838 return_value_location (valtype
, &hi
, &lo
);
4840 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4841 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4842 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4843 raw_buffer
, register_size (current_gdbarch
,
4848 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4849 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4850 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4852 register_size (current_gdbarch
,
4857 /* Floating point register management.
4859 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4860 64bit operations, these early MIPS cpus treat fp register pairs
4861 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4862 registers and offer a compatibility mode that emulates the MIPS2 fp
4863 model. When operating in MIPS2 fp compat mode, later cpu's split
4864 double precision floats into two 32-bit chunks and store them in
4865 consecutive fp regs. To display 64-bit floats stored in this
4866 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4867 Throw in user-configurable endianness and you have a real mess.
4869 The way this works is:
4870 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4871 double-precision value will be split across two logical registers.
4872 The lower-numbered logical register will hold the low-order bits,
4873 regardless of the processor's endianness.
4874 - If we are on a 64-bit processor, and we are looking for a
4875 single-precision value, it will be in the low ordered bits
4876 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4877 save slot in memory.
4878 - If we are in 64-bit mode, everything is straightforward.
4880 Note that this code only deals with "live" registers at the top of the
4881 stack. We will attempt to deal with saved registers later, when
4882 the raw/cooked register interface is in place. (We need a general
4883 interface that can deal with dynamic saved register sizes -- fp
4884 regs could be 32 bits wide in one frame and 64 on the frame above
4887 static struct type
*
4888 mips_float_register_type (void)
4890 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4891 return builtin_type_ieee_single_big
;
4893 return builtin_type_ieee_single_little
;
4896 static struct type
*
4897 mips_double_register_type (void)
4899 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4900 return builtin_type_ieee_double_big
;
4902 return builtin_type_ieee_double_little
;
4905 /* Copy a 32-bit single-precision value from the current frame
4906 into rare_buffer. */
4909 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4912 int raw_size
= register_size (current_gdbarch
, regno
);
4913 char *raw_buffer
= alloca (raw_size
);
4915 if (!frame_register_read (frame
, regno
, raw_buffer
))
4916 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4919 /* We have a 64-bit value for this register. Find the low-order
4923 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4928 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4932 memcpy (rare_buffer
, raw_buffer
, 4);
4936 /* Copy a 64-bit double-precision value from the current frame into
4937 rare_buffer. This may include getting half of it from the next
4941 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4944 int raw_size
= register_size (current_gdbarch
, regno
);
4946 if (raw_size
== 8 && !mips2_fp_compat ())
4948 /* We have a 64-bit value for this register, and we should use
4950 if (!frame_register_read (frame
, regno
, rare_buffer
))
4951 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4955 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4956 internal_error (__FILE__
, __LINE__
,
4957 "mips_read_fp_register_double: bad access to "
4958 "odd-numbered FP register");
4960 /* mips_read_fp_register_single will find the correct 32 bits from
4962 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4964 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4965 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4969 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4970 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4976 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4978 { /* do values for FP (float) regs */
4980 double doub
, flt1
; /* doubles extracted from raw hex data */
4984 (char *) alloca (2 *
4985 register_size (current_gdbarch
,
4986 mips_regnum (current_gdbarch
)->fp0
));
4988 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4989 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4992 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4994 /* 4-byte registers: Print hex and floating. Also print even
4995 numbered registers as doubles. */
4996 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4997 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4999 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
5002 fprintf_filtered (file
, " flt: ");
5004 fprintf_filtered (file
, " <invalid float> ");
5006 fprintf_filtered (file
, "%-17.9g", flt1
);
5008 if (regnum
% 2 == 0)
5010 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
5011 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
5014 fprintf_filtered (file
, " dbl: ");
5016 fprintf_filtered (file
, "<invalid double>");
5018 fprintf_filtered (file
, "%-24.17g", doub
);
5023 /* Eight byte registers: print each one as hex, float and double. */
5024 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
5025 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
5027 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
5028 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
5031 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
5034 fprintf_filtered (file
, " flt: ");
5036 fprintf_filtered (file
, "<invalid float>");
5038 fprintf_filtered (file
, "%-17.9g", flt1
);
5040 fprintf_filtered (file
, " dbl: ");
5042 fprintf_filtered (file
, "<invalid double>");
5044 fprintf_filtered (file
, "%-24.17g", doub
);
5049 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
5050 int regnum
, int all
)
5052 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5053 char raw_buffer
[MAX_REGISTER_SIZE
];
5056 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
5058 mips_print_fp_register (file
, frame
, regnum
);
5062 /* Get the data in raw format. */
5063 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5065 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
5069 fputs_filtered (REGISTER_NAME (regnum
), file
);
5071 /* The problem with printing numeric register names (r26, etc.) is that
5072 the user can't use them on input. Probably the best solution is to
5073 fix it so that either the numeric or the funky (a2, etc.) names
5074 are accepted on input. */
5075 if (regnum
< MIPS_NUMREGS
)
5076 fprintf_filtered (file
, "(r%d): ", regnum
);
5078 fprintf_filtered (file
, ": ");
5080 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5082 register_size (current_gdbarch
,
5083 regnum
) - register_size (current_gdbarch
, regnum
);
5087 print_scalar_formatted (raw_buffer
+ offset
,
5088 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
5092 /* Replacement for generic do_registers_info.
5093 Print regs in pretty columns. */
5096 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5099 fprintf_filtered (file
, " ");
5100 mips_print_fp_register (file
, frame
, regnum
);
5101 fprintf_filtered (file
, "\n");
5106 /* Print a row's worth of GP (int) registers, with name labels above */
5109 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5112 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5113 /* do values for GP (int) regs */
5114 char raw_buffer
[MAX_REGISTER_SIZE
];
5115 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
5119 /* For GP registers, we print a separate row of names above the vals */
5120 fprintf_filtered (file
, " ");
5121 for (col
= 0, regnum
= start_regnum
;
5122 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
5124 if (*REGISTER_NAME (regnum
) == '\0')
5125 continue; /* unused register */
5126 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5128 break; /* end the row: reached FP register */
5129 fprintf_filtered (file
,
5130 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
5131 REGISTER_NAME (regnum
));
5134 /* print the R0 to R31 names */
5135 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
5136 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
5138 fprintf_filtered (file
, "\n ");
5140 /* now print the values in hex, 4 or 8 to the row */
5141 for (col
= 0, regnum
= start_regnum
;
5142 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
5144 if (*REGISTER_NAME (regnum
) == '\0')
5145 continue; /* unused register */
5146 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5148 break; /* end row: reached FP register */
5149 /* OK: get the data in raw format. */
5150 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5151 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
5152 /* pad small registers */
5154 byte
< (mips_abi_regsize (current_gdbarch
)
5155 - register_size (current_gdbarch
, regnum
)); byte
++)
5156 printf_filtered (" ");
5157 /* Now print the register value in hex, endian order. */
5158 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5160 register_size (current_gdbarch
,
5161 regnum
) - register_size (current_gdbarch
, regnum
);
5162 byte
< register_size (current_gdbarch
, regnum
); byte
++)
5163 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5165 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
5167 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5168 fprintf_filtered (file
, " ");
5171 if (col
> 0) /* ie. if we actually printed anything... */
5172 fprintf_filtered (file
, "\n");
5177 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
5180 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
5181 struct frame_info
*frame
, int regnum
, int all
)
5183 if (regnum
!= -1) /* do one specified register */
5185 gdb_assert (regnum
>= NUM_REGS
);
5186 if (*(REGISTER_NAME (regnum
)) == '\0')
5187 error ("Not a valid register for the current processor type");
5189 mips_print_register (file
, frame
, regnum
, 0);
5190 fprintf_filtered (file
, "\n");
5193 /* do all (or most) registers */
5196 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
5198 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5201 if (all
) /* true for "INFO ALL-REGISTERS" command */
5202 regnum
= print_fp_register_row (file
, frame
, regnum
);
5204 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
5207 regnum
= print_gp_register_row (file
, frame
, regnum
);
5212 /* Is this a branch with a delay slot? */
5214 static int is_delayed (unsigned long);
5217 is_delayed (unsigned long insn
)
5220 for (i
= 0; i
< NUMOPCODES
; ++i
)
5221 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
5222 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
5224 return (i
< NUMOPCODES
5225 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
5226 | INSN_COND_BRANCH_DELAY
5227 | INSN_COND_BRANCH_LIKELY
)));
5231 mips_step_skips_delay (CORE_ADDR pc
)
5233 char buf
[MIPS_INSTLEN
];
5235 /* There is no branch delay slot on MIPS16. */
5236 if (pc_is_mips16 (pc
))
5239 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
5240 /* If error reading memory, guess that it is not a delayed branch. */
5242 return is_delayed ((unsigned long)
5243 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
5246 /* Skip the PC past function prologue instructions (32-bit version).
5247 This is a helper function for mips_skip_prologue. */
5250 mips32_skip_prologue (CORE_ADDR pc
)
5254 int seen_sp_adjust
= 0;
5255 int load_immediate_bytes
= 0;
5257 /* Find an upper bound on the prologue. */
5258 end_pc
= skip_prologue_using_sal (pc
);
5260 end_pc
= pc
+ 100; /* Magic. */
5262 /* Skip the typical prologue instructions. These are the stack adjustment
5263 instruction and the instructions that save registers on the stack
5264 or in the gcc frame. */
5265 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
5267 unsigned long high_word
;
5269 inst
= mips_fetch_instruction (pc
);
5270 high_word
= (inst
>> 16) & 0xffff;
5272 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
5273 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
5275 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
5276 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
5278 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
5279 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
5280 && (inst
& 0x001F0000)) /* reg != $zero */
5283 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
5285 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
5287 continue; /* reg != $zero */
5289 /* move $s8,$sp. With different versions of gas this will be either
5290 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
5291 Accept any one of these. */
5292 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
5295 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
5297 else if (high_word
== 0x3c1c) /* lui $gp,n */
5299 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
5301 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
5302 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
5304 /* The following instructions load $at or $t0 with an immediate
5305 value in preparation for a stack adjustment via
5306 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
5307 a local variable, so we accept them only before a stack adjustment
5308 instruction was seen. */
5309 else if (!seen_sp_adjust
)
5311 if (high_word
== 0x3c01 || /* lui $at,n */
5312 high_word
== 0x3c08) /* lui $t0,n */
5314 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5317 else if (high_word
== 0x3421 || /* ori $at,$at,n */
5318 high_word
== 0x3508 || /* ori $t0,$t0,n */
5319 high_word
== 0x3401 || /* ori $at,$zero,n */
5320 high_word
== 0x3408) /* ori $t0,$zero,n */
5322 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5332 /* In a frameless function, we might have incorrectly
5333 skipped some load immediate instructions. Undo the skipping
5334 if the load immediate was not followed by a stack adjustment. */
5335 if (load_immediate_bytes
&& !seen_sp_adjust
)
5336 pc
-= load_immediate_bytes
;
5340 /* Skip the PC past function prologue instructions (16-bit version).
5341 This is a helper function for mips_skip_prologue. */
5344 mips16_skip_prologue (CORE_ADDR pc
)
5347 int extend_bytes
= 0;
5348 int prev_extend_bytes
;
5350 /* Table of instructions likely to be found in a function prologue. */
5353 unsigned short inst
;
5354 unsigned short mask
;
5360 , /* addiu $sp,offset */
5363 , /* daddiu $sp,offset */
5366 , /* sw reg,n($sp) */
5369 , /* sd reg,n($sp) */
5372 , /* sw $ra,n($sp) */
5375 , /* sd $ra,n($sp) */
5381 , /* sw $a0-$a3,n($s1) */
5384 , /* move reg,$a0-$a3 */
5387 , /* entry pseudo-op */
5390 , /* addiu $s1,$sp,n */
5392 0, 0} /* end of table marker */
5395 /* Find an upper bound on the prologue. */
5396 end_pc
= skip_prologue_using_sal (pc
);
5398 end_pc
= pc
+ 100; /* Magic. */
5400 /* Skip the typical prologue instructions. These are the stack adjustment
5401 instruction and the instructions that save registers on the stack
5402 or in the gcc frame. */
5403 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
5405 unsigned short inst
;
5408 inst
= mips_fetch_instruction (pc
);
5410 /* Normally we ignore an extend instruction. However, if it is
5411 not followed by a valid prologue instruction, we must adjust
5412 the pc back over the extend so that it won't be considered
5413 part of the prologue. */
5414 if ((inst
& 0xf800) == 0xf000) /* extend */
5416 extend_bytes
= MIPS16_INSTLEN
;
5419 prev_extend_bytes
= extend_bytes
;
5422 /* Check for other valid prologue instructions besides extend. */
5423 for (i
= 0; table
[i
].mask
!= 0; i
++)
5424 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
5426 if (table
[i
].mask
!= 0) /* it was in table? */
5427 continue; /* ignore it */
5431 /* Return the current pc, adjusted backwards by 2 if
5432 the previous instruction was an extend. */
5433 return pc
- prev_extend_bytes
;
5439 /* To skip prologues, I use this predicate. Returns either PC itself
5440 if the code at PC does not look like a function prologue; otherwise
5441 returns an address that (if we're lucky) follows the prologue. If
5442 LENIENT, then we must skip everything which is involved in setting
5443 up the frame (it's OK to skip more, just so long as we don't skip
5444 anything which might clobber the registers which are being saved.
5445 We must skip more in the case where part of the prologue is in the
5446 delay slot of a non-prologue instruction). */
5449 mips_skip_prologue (CORE_ADDR pc
)
5451 /* See if we can determine the end of the prologue via the symbol table.
5452 If so, then return either PC, or the PC after the prologue, whichever
5455 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
5457 if (post_prologue_pc
!= 0)
5458 return max (pc
, post_prologue_pc
);
5460 /* Can't determine prologue from the symbol table, need to examine
5463 if (pc_is_mips16 (pc
))
5464 return mips16_skip_prologue (pc
);
5466 return mips32_skip_prologue (pc
);
5469 /* Root of all "set mips "/"show mips " commands. This will eventually be
5470 used for all MIPS-specific commands. */
5473 show_mips_command (char *args
, int from_tty
)
5475 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5479 set_mips_command (char *args
, int from_tty
)
5482 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5483 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5486 /* Commands to show/set the MIPS FPU type. */
5489 show_mipsfpu_command (char *args
, int from_tty
)
5492 switch (MIPS_FPU_TYPE
)
5494 case MIPS_FPU_SINGLE
:
5495 fpu
= "single-precision";
5497 case MIPS_FPU_DOUBLE
:
5498 fpu
= "double-precision";
5501 fpu
= "absent (none)";
5504 internal_error (__FILE__
, __LINE__
, "bad switch");
5506 if (mips_fpu_type_auto
)
5508 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5512 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5517 set_mipsfpu_command (char *args
, int from_tty
)
5520 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5521 show_mipsfpu_command (args
, from_tty
);
5525 set_mipsfpu_single_command (char *args
, int from_tty
)
5527 struct gdbarch_info info
;
5528 gdbarch_info_init (&info
);
5529 mips_fpu_type
= MIPS_FPU_SINGLE
;
5530 mips_fpu_type_auto
= 0;
5531 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5532 instead of relying on globals. Doing that would let generic code
5533 handle the search for this specific architecture. */
5534 if (!gdbarch_update_p (info
))
5535 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5539 set_mipsfpu_double_command (char *args
, int from_tty
)
5541 struct gdbarch_info info
;
5542 gdbarch_info_init (&info
);
5543 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5544 mips_fpu_type_auto
= 0;
5545 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5546 instead of relying on globals. Doing that would let generic code
5547 handle the search for this specific architecture. */
5548 if (!gdbarch_update_p (info
))
5549 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5553 set_mipsfpu_none_command (char *args
, int from_tty
)
5555 struct gdbarch_info info
;
5556 gdbarch_info_init (&info
);
5557 mips_fpu_type
= MIPS_FPU_NONE
;
5558 mips_fpu_type_auto
= 0;
5559 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5560 instead of relying on globals. Doing that would let generic code
5561 handle the search for this specific architecture. */
5562 if (!gdbarch_update_p (info
))
5563 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5567 set_mipsfpu_auto_command (char *args
, int from_tty
)
5569 mips_fpu_type_auto
= 1;
5572 /* Attempt to identify the particular processor model by reading the
5573 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5574 the relevant processor still exists (it dates back to '94) and
5575 secondly this is not the way to do this. The processor type should
5576 be set by forcing an architecture change. */
5579 deprecated_mips_set_processor_regs_hack (void)
5581 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5584 prid
= read_register (PRID_REGNUM
);
5586 if ((prid
& ~0xf) == 0x700)
5587 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5590 /* Just like reinit_frame_cache, but with the right arguments to be
5591 callable as an sfunc. */
5594 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5595 struct cmd_list_element
*c
)
5597 reinit_frame_cache ();
5601 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5603 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5604 mips_extra_func_info_t proc_desc
;
5606 /* Search for the function containing this address. Set the low bit
5607 of the address when searching, in case we were given an even address
5608 that is the start of a 16-bit function. If we didn't do this,
5609 the search would fail because the symbol table says the function
5610 starts at an odd address, i.e. 1 byte past the given address. */
5611 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5612 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5614 /* Make an attempt to determine if this is a 16-bit function. If
5615 the procedure descriptor exists and the address therein is odd,
5616 it's definitely a 16-bit function. Otherwise, we have to just
5617 guess that if the address passed in is odd, it's 16-bits. */
5618 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5619 disassembler needs to be able to locally determine the ISA, and
5620 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5624 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5625 info
->mach
= bfd_mach_mips16
;
5629 if (pc_is_mips16 (memaddr
))
5630 info
->mach
= bfd_mach_mips16
;
5633 /* Round down the instruction address to the appropriate boundary. */
5634 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5636 /* Set the disassembler options. */
5637 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5639 /* Set up the disassembler info, so that we get the right
5640 register names from libopcodes. */
5641 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5642 info
->disassembler_options
= "gpr-names=n32";
5644 info
->disassembler_options
= "gpr-names=64";
5645 info
->flavour
= bfd_target_elf_flavour
;
5648 /* This string is not recognized explicitly by the disassembler,
5649 but it tells the disassembler to not try to guess the ABI from
5650 the bfd elf headers, such that, if the user overrides the ABI
5651 of a program linked as NewABI, the disassembly will follow the
5652 register naming conventions specified by the user. */
5653 info
->disassembler_options
= "gpr-names=32";
5655 /* Call the appropriate disassembler based on the target endian-ness. */
5656 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5657 return print_insn_big_mips (memaddr
, info
);
5659 return print_insn_little_mips (memaddr
, info
);
5662 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5663 counter value to determine whether a 16- or 32-bit breakpoint should be
5664 used. It returns a pointer to a string of bytes that encode a breakpoint
5665 instruction, stores the length of the string to *lenptr, and adjusts pc
5666 (if necessary) to point to the actual memory location where the
5667 breakpoint should be inserted. */
5669 static const unsigned char *
5670 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5672 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5674 if (pc_is_mips16 (*pcptr
))
5676 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5677 *pcptr
= unmake_mips16_addr (*pcptr
);
5678 *lenptr
= sizeof (mips16_big_breakpoint
);
5679 return mips16_big_breakpoint
;
5683 /* The IDT board uses an unusual breakpoint value, and
5684 sometimes gets confused when it sees the usual MIPS
5685 breakpoint instruction. */
5686 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5687 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5688 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5690 *lenptr
= sizeof (big_breakpoint
);
5692 if (strcmp (target_shortname
, "mips") == 0)
5693 return idt_big_breakpoint
;
5694 else if (strcmp (target_shortname
, "ddb") == 0
5695 || strcmp (target_shortname
, "pmon") == 0
5696 || strcmp (target_shortname
, "lsi") == 0)
5697 return pmon_big_breakpoint
;
5699 return big_breakpoint
;
5704 if (pc_is_mips16 (*pcptr
))
5706 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5707 *pcptr
= unmake_mips16_addr (*pcptr
);
5708 *lenptr
= sizeof (mips16_little_breakpoint
);
5709 return mips16_little_breakpoint
;
5713 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5714 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5715 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5717 *lenptr
= sizeof (little_breakpoint
);
5719 if (strcmp (target_shortname
, "mips") == 0)
5720 return idt_little_breakpoint
;
5721 else if (strcmp (target_shortname
, "ddb") == 0
5722 || strcmp (target_shortname
, "pmon") == 0
5723 || strcmp (target_shortname
, "lsi") == 0)
5724 return pmon_little_breakpoint
;
5726 return little_breakpoint
;
5731 /* If PC is in a mips16 call or return stub, return the address of the target
5732 PC, which is either the callee or the caller. There are several
5733 cases which must be handled:
5735 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5736 target PC is in $31 ($ra).
5737 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5738 and the target PC is in $2.
5739 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5740 before the jal instruction, this is effectively a call stub
5741 and the the target PC is in $2. Otherwise this is effectively
5742 a return stub and the target PC is in $18.
5744 See the source code for the stubs in gcc/config/mips/mips16.S for
5747 This function implements the SKIP_TRAMPOLINE_CODE macro.
5751 mips_skip_stub (CORE_ADDR pc
)
5754 CORE_ADDR start_addr
;
5756 /* Find the starting address and name of the function containing the PC. */
5757 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5760 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5761 target PC is in $31 ($ra). */
5762 if (strcmp (name
, "__mips16_ret_sf") == 0
5763 || strcmp (name
, "__mips16_ret_df") == 0)
5764 return read_signed_register (RA_REGNUM
);
5766 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5768 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5769 and the target PC is in $2. */
5770 if (name
[19] >= '0' && name
[19] <= '9')
5771 return read_signed_register (2);
5773 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5774 before the jal instruction, this is effectively a call stub
5775 and the the target PC is in $2. Otherwise this is effectively
5776 a return stub and the target PC is in $18. */
5777 else if (name
[19] == 's' || name
[19] == 'd')
5779 if (pc
== start_addr
)
5781 /* Check if the target of the stub is a compiler-generated
5782 stub. Such a stub for a function bar might have a name
5783 like __fn_stub_bar, and might look like this:
5788 la $1,bar (becomes a lui/addiu pair)
5790 So scan down to the lui/addi and extract the target
5791 address from those two instructions. */
5793 CORE_ADDR target_pc
= read_signed_register (2);
5797 /* See if the name of the target function is __fn_stub_*. */
5798 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5801 if (strncmp (name
, "__fn_stub_", 10) != 0
5802 && strcmp (name
, "etext") != 0
5803 && strcmp (name
, "_etext") != 0)
5806 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5807 The limit on the search is arbitrarily set to 20
5808 instructions. FIXME. */
5809 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5811 inst
= mips_fetch_instruction (target_pc
);
5812 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5813 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5814 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5815 return pc
| (inst
& 0xffff); /* low word */
5818 /* Couldn't find the lui/addui pair, so return stub address. */
5822 /* This is the 'return' part of a call stub. The return
5823 address is in $r18. */
5824 return read_signed_register (18);
5827 return 0; /* not a stub */
5831 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5832 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5835 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5837 CORE_ADDR start_addr
;
5839 /* Find the starting address of the function containing the PC. If the
5840 caller didn't give us a name, look it up at the same time. */
5841 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5845 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5847 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5848 if (name
[19] >= '0' && name
[19] <= '9')
5850 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5851 before the jal instruction, this is effectively a call stub. */
5852 else if (name
[19] == 's' || name
[19] == 'd')
5853 return pc
== start_addr
;
5856 return 0; /* not a stub */
5860 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5861 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5864 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5866 CORE_ADDR start_addr
;
5868 /* Find the starting address of the function containing the PC. */
5869 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5872 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5873 if (strcmp (name
, "__mips16_ret_sf") == 0
5874 || strcmp (name
, "__mips16_ret_df") == 0)
5877 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5878 i.e. after the jal instruction, this is effectively a return stub. */
5879 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5880 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5883 return 0; /* not a stub */
5887 /* Return non-zero if the PC is in a library helper function that
5888 should be ignored. This implements the
5889 DEPRECATED_IGNORE_HELPER_CALL macro. */
5892 mips_ignore_helper (CORE_ADDR pc
)
5896 /* Find the starting address and name of the function containing the PC. */
5897 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5900 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5901 that we want to ignore. */
5902 return (strcmp (name
, "__mips16_ret_sf") == 0
5903 || strcmp (name
, "__mips16_ret_df") == 0);
5907 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5908 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5911 mips_stab_reg_to_regnum (int num
)
5914 if (num
>= 0 && num
< 32)
5916 else if (num
>= 38 && num
< 70)
5917 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5919 regnum
= mips_regnum (current_gdbarch
)->hi
;
5921 regnum
= mips_regnum (current_gdbarch
)->lo
;
5923 /* This will hopefully (eventually) provoke a warning. Should
5924 we be calling complaint() here? */
5925 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5926 return NUM_REGS
+ regnum
;
5930 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5931 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5934 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5937 if (num
>= 0 && num
< 32)
5939 else if (num
>= 32 && num
< 64)
5940 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5942 regnum
= mips_regnum (current_gdbarch
)->hi
;
5944 regnum
= mips_regnum (current_gdbarch
)->lo
;
5946 /* This will hopefully (eventually) provoke a warning. Should we
5947 be calling complaint() here? */
5948 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5949 return NUM_REGS
+ regnum
;
5953 mips_register_sim_regno (int regnum
)
5955 /* Only makes sense to supply raw registers. */
5956 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5957 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5958 decide if it is valid. Should instead define a standard sim/gdb
5959 register numbering scheme. */
5960 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5961 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5964 return LEGACY_SIM_REGNO_IGNORE
;
5968 /* Convert an integer into an address. By first converting the value
5969 into a pointer and then extracting it signed, the address is
5970 guarenteed to be correctly sign extended. */
5973 mips_integer_to_address (struct type
*type
, void *buf
)
5975 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5976 LONGEST val
= unpack_long (type
, buf
);
5977 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5978 return extract_signed_integer (tmp
,
5979 TYPE_LENGTH (builtin_type_void_data_ptr
));
5983 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5985 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5986 const char *name
= bfd_get_section_name (abfd
, sect
);
5988 if (*abip
!= MIPS_ABI_UNKNOWN
)
5991 if (strncmp (name
, ".mdebug.", 8) != 0)
5994 if (strcmp (name
, ".mdebug.abi32") == 0)
5995 *abip
= MIPS_ABI_O32
;
5996 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5997 *abip
= MIPS_ABI_N32
;
5998 else if (strcmp (name
, ".mdebug.abi64") == 0)
5999 *abip
= MIPS_ABI_N64
;
6000 else if (strcmp (name
, ".mdebug.abiO64") == 0)
6001 *abip
= MIPS_ABI_O64
;
6002 else if (strcmp (name
, ".mdebug.eabi32") == 0)
6003 *abip
= MIPS_ABI_EABI32
;
6004 else if (strcmp (name
, ".mdebug.eabi64") == 0)
6005 *abip
= MIPS_ABI_EABI64
;
6007 warning ("unsupported ABI %s.", name
+ 8);
6010 static enum mips_abi
6011 global_mips_abi (void)
6015 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
6016 if (mips_abi_strings
[i
] == mips_abi_string
)
6017 return (enum mips_abi
) i
;
6019 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
6022 static struct gdbarch
*
6023 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6025 struct gdbarch
*gdbarch
;
6026 struct gdbarch_tdep
*tdep
;
6028 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
6030 enum mips_fpu_type fpu_type
;
6032 /* First of all, extract the elf_flags, if available. */
6033 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6034 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6035 else if (arches
!= NULL
)
6036 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
6040 fprintf_unfiltered (gdb_stdlog
,
6041 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
6043 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
6044 switch ((elf_flags
& EF_MIPS_ABI
))
6046 case E_MIPS_ABI_O32
:
6047 found_abi
= MIPS_ABI_O32
;
6049 case E_MIPS_ABI_O64
:
6050 found_abi
= MIPS_ABI_O64
;
6052 case E_MIPS_ABI_EABI32
:
6053 found_abi
= MIPS_ABI_EABI32
;
6055 case E_MIPS_ABI_EABI64
:
6056 found_abi
= MIPS_ABI_EABI64
;
6059 if ((elf_flags
& EF_MIPS_ABI2
))
6060 found_abi
= MIPS_ABI_N32
;
6062 found_abi
= MIPS_ABI_UNKNOWN
;
6066 /* GCC creates a pseudo-section whose name describes the ABI. */
6067 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
6068 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6070 /* If we have no useful BFD information, use the ABI from the last
6071 MIPS architecture (if there is one). */
6072 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6073 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6075 /* Try the architecture for any hint of the correct ABI. */
6076 if (found_abi
== MIPS_ABI_UNKNOWN
6077 && info
.bfd_arch_info
!= NULL
6078 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6080 switch (info
.bfd_arch_info
->mach
)
6082 case bfd_mach_mips3900
:
6083 found_abi
= MIPS_ABI_EABI32
;
6085 case bfd_mach_mips4100
:
6086 case bfd_mach_mips5000
:
6087 found_abi
= MIPS_ABI_EABI64
;
6089 case bfd_mach_mips8000
:
6090 case bfd_mach_mips10000
:
6091 /* On Irix, ELF64 executables use the N64 ABI. The
6092 pseudo-sections which describe the ABI aren't present
6093 on IRIX. (Even for executables created by gcc.) */
6094 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6095 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6096 found_abi
= MIPS_ABI_N64
;
6098 found_abi
= MIPS_ABI_N32
;
6104 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6107 /* What has the user specified from the command line? */
6108 wanted_abi
= global_mips_abi ();
6110 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6113 /* Now that we have found what the ABI for this binary would be,
6114 check whether the user is overriding it. */
6115 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6116 mips_abi
= wanted_abi
;
6117 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6118 mips_abi
= found_abi
;
6120 mips_abi
= MIPS_ABI_O32
;
6122 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6125 /* Also used when doing an architecture lookup. */
6127 fprintf_unfiltered (gdb_stdlog
,
6128 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
6129 mips64_transfers_32bit_regs_p
);
6131 /* Determine the MIPS FPU type. */
6132 if (!mips_fpu_type_auto
)
6133 fpu_type
= mips_fpu_type
;
6134 else if (info
.bfd_arch_info
!= NULL
6135 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6136 switch (info
.bfd_arch_info
->mach
)
6138 case bfd_mach_mips3900
:
6139 case bfd_mach_mips4100
:
6140 case bfd_mach_mips4111
:
6141 case bfd_mach_mips4120
:
6142 fpu_type
= MIPS_FPU_NONE
;
6144 case bfd_mach_mips4650
:
6145 fpu_type
= MIPS_FPU_SINGLE
;
6148 fpu_type
= MIPS_FPU_DOUBLE
;
6151 else if (arches
!= NULL
)
6152 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6154 fpu_type
= MIPS_FPU_DOUBLE
;
6156 fprintf_unfiltered (gdb_stdlog
,
6157 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6159 /* try to find a pre-existing architecture */
6160 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6162 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6164 /* MIPS needs to be pedantic about which ABI the object is
6166 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6168 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6170 /* Need to be pedantic about which register virtual size is
6172 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6173 != mips64_transfers_32bit_regs_p
)
6175 /* Be pedantic about which FPU is selected. */
6176 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6178 return arches
->gdbarch
;
6181 /* Need a new architecture. Fill in a target specific vector. */
6182 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6183 gdbarch
= gdbarch_alloc (&info
, tdep
);
6184 tdep
->elf_flags
= elf_flags
;
6185 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6186 tdep
->found_abi
= found_abi
;
6187 tdep
->mips_abi
= mips_abi
;
6188 tdep
->mips_fpu_type
= fpu_type
;
6190 /* Initially set everything according to the default ABI/ISA. */
6191 set_gdbarch_short_bit (gdbarch
, 16);
6192 set_gdbarch_int_bit (gdbarch
, 32);
6193 set_gdbarch_float_bit (gdbarch
, 32);
6194 set_gdbarch_double_bit (gdbarch
, 64);
6195 set_gdbarch_long_double_bit (gdbarch
, 64);
6196 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6197 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6198 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6200 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6201 mips_elf_make_msymbol_special
);
6203 /* Fill in the OS dependant register numbers and names. */
6205 const char **reg_names
;
6206 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
6207 struct mips_regnum
);
6208 if (info
.osabi
== GDB_OSABI_IRIX
)
6213 regnum
->badvaddr
= 66;
6216 regnum
->fp_control_status
= 69;
6217 regnum
->fp_implementation_revision
= 70;
6219 reg_names
= mips_irix_reg_names
;
6223 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6224 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6225 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6226 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6227 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6228 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6229 regnum
->fp_control_status
= 70;
6230 regnum
->fp_implementation_revision
= 71;
6232 if (info
.bfd_arch_info
!= NULL
6233 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6234 reg_names
= mips_tx39_reg_names
;
6236 reg_names
= mips_generic_reg_names
;
6238 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
6239 replaced by read_pc? */
6240 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6241 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6242 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6243 set_gdbarch_num_regs (gdbarch
, num_regs
);
6244 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6245 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6246 tdep
->mips_processor_reg_names
= reg_names
;
6247 tdep
->regnum
= regnum
;
6253 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6254 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6255 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6256 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6257 tdep
->default_mask_address_p
= 0;
6258 set_gdbarch_long_bit (gdbarch
, 32);
6259 set_gdbarch_ptr_bit (gdbarch
, 32);
6260 set_gdbarch_long_long_bit (gdbarch
, 64);
6263 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6264 set_gdbarch_deprecated_store_return_value (gdbarch
,
6265 mips_o64_store_return_value
);
6266 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6267 mips_o64_extract_return_value
);
6268 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6269 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6270 tdep
->default_mask_address_p
= 0;
6271 set_gdbarch_long_bit (gdbarch
, 32);
6272 set_gdbarch_ptr_bit (gdbarch
, 32);
6273 set_gdbarch_long_long_bit (gdbarch
, 64);
6274 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
6276 case MIPS_ABI_EABI32
:
6277 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6278 set_gdbarch_deprecated_store_return_value (gdbarch
,
6279 mips_eabi_store_return_value
);
6280 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6281 mips_eabi_extract_return_value
);
6282 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6283 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6284 tdep
->default_mask_address_p
= 0;
6285 set_gdbarch_long_bit (gdbarch
, 32);
6286 set_gdbarch_ptr_bit (gdbarch
, 32);
6287 set_gdbarch_long_long_bit (gdbarch
, 64);
6288 set_gdbarch_deprecated_reg_struct_has_addr
6289 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6290 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6292 case MIPS_ABI_EABI64
:
6293 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6294 set_gdbarch_deprecated_store_return_value (gdbarch
,
6295 mips_eabi_store_return_value
);
6296 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6297 mips_eabi_extract_return_value
);
6298 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6299 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6300 tdep
->default_mask_address_p
= 0;
6301 set_gdbarch_long_bit (gdbarch
, 64);
6302 set_gdbarch_ptr_bit (gdbarch
, 64);
6303 set_gdbarch_long_long_bit (gdbarch
, 64);
6304 set_gdbarch_deprecated_reg_struct_has_addr
6305 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6306 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6309 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6310 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6311 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6312 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6313 tdep
->default_mask_address_p
= 0;
6314 set_gdbarch_long_bit (gdbarch
, 32);
6315 set_gdbarch_ptr_bit (gdbarch
, 32);
6316 set_gdbarch_long_long_bit (gdbarch
, 64);
6319 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6320 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6321 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6322 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6323 tdep
->default_mask_address_p
= 0;
6324 set_gdbarch_long_bit (gdbarch
, 64);
6325 set_gdbarch_ptr_bit (gdbarch
, 64);
6326 set_gdbarch_long_long_bit (gdbarch
, 64);
6329 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
6332 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6333 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6336 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6337 flag in object files because to do so would make it impossible to
6338 link with libraries compiled without "-gp32". This is
6339 unnecessarily restrictive.
6341 We could solve this problem by adding "-gp32" multilibs to gcc,
6342 but to set this flag before gcc is built with such multilibs will
6343 break too many systems.''
6345 But even more unhelpfully, the default linker output target for
6346 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6347 for 64-bit programs - you need to change the ABI to change this,
6348 and not all gcc targets support that currently. Therefore using
6349 this flag to detect 32-bit mode would do the wrong thing given
6350 the current gcc - it would make GDB treat these 64-bit programs
6351 as 32-bit programs by default. */
6353 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6354 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6355 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6357 /* Add/remove bits from an address. The MIPS needs be careful to
6358 ensure that all 32 bit addresses are sign extended to 64 bits. */
6359 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6361 /* Unwind the frame. */
6362 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6363 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
6365 /* Map debug register numbers onto internal register numbers. */
6366 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6367 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6368 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6369 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
6370 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6371 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6372 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6373 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6375 /* MIPS version of CALL_DUMMY */
6377 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6378 replaced by a command, and all targets will default to on stack
6379 (regardless of the stack's execute status). */
6380 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6381 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6383 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6384 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6385 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6387 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6388 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6390 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6392 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6393 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6394 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6396 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6398 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6400 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6402 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6403 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6404 need to all be folded into the target vector. Since they are
6405 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6406 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6408 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6410 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6412 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
6413 to support MIPS16. This is a bad thing. Make sure not to do it
6414 if we have an OS ABI that actually supports shared libraries, since
6415 shared library support is more important. If we have an OS someday
6416 that supports both shared libraries and MIPS16, we'll have to find
6417 a better place for these. */
6418 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
6420 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6421 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6424 /* Hook in OS ABI-specific overrides, if they have been registered. */
6425 gdbarch_init_osabi (info
, gdbarch
);
6427 /* Unwind the frame. */
6428 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
6429 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
6430 frame_unwind_append_sniffer (gdbarch
, mips16_frame_sniffer
);
6431 frame_unwind_append_sniffer (gdbarch
, mips32_frame_sniffer
);
6432 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6433 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
6434 frame_base_append_sniffer (gdbarch
, mips16_frame_base_sniffer
);
6435 frame_base_append_sniffer (gdbarch
, mips32_frame_base_sniffer
);
6441 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6443 struct gdbarch_info info
;
6445 /* Force the architecture to update, and (if it's a MIPS architecture)
6446 mips_gdbarch_init will take care of the rest. */
6447 gdbarch_info_init (&info
);
6448 gdbarch_update_p (info
);
6451 /* Print out which MIPS ABI is in use. */
6454 show_mips_abi (char *ignore_args
, int from_tty
)
6456 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6458 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6461 enum mips_abi global_abi
= global_mips_abi ();
6462 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6463 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6465 if (global_abi
== MIPS_ABI_UNKNOWN
)
6467 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6469 else if (global_abi
== actual_abi
)
6471 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6475 /* Probably shouldn't happen... */
6477 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6478 actual_abi_str
, mips_abi_strings
[global_abi
]);
6484 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6486 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6490 int ef_mips_32bitmode
;
6491 /* determine the ISA */
6492 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6510 /* determine the size of a pointer */
6511 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6512 fprintf_unfiltered (file
,
6513 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6515 fprintf_unfiltered (file
,
6516 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6518 fprintf_unfiltered (file
,
6519 "mips_dump_tdep: ef_mips_arch = %d\n",
6521 fprintf_unfiltered (file
,
6522 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6523 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6524 fprintf_unfiltered (file
,
6525 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6526 mips_mask_address_p (tdep
),
6527 tdep
->default_mask_address_p
);
6529 fprintf_unfiltered (file
,
6530 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6531 MIPS_DEFAULT_FPU_TYPE
,
6532 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6533 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6534 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6536 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6537 fprintf_unfiltered (file
,
6538 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6540 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6541 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6542 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6544 fprintf_unfiltered (file
,
6545 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6546 mips_stack_argsize (current_gdbarch
));
6547 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6548 fprintf_unfiltered (file
,
6549 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6550 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6551 fprintf_unfiltered (file
,
6552 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6553 XSTRING (ATTACH_DETACH
));
6554 fprintf_unfiltered (file
,
6555 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6556 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6557 fprintf_unfiltered (file
,
6558 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6559 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6560 fprintf_unfiltered (file
,
6561 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6562 FIRST_EMBED_REGNUM
);
6563 fprintf_unfiltered (file
,
6564 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
6565 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
6566 fprintf_unfiltered (file
,
6567 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6568 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6569 fprintf_unfiltered (file
,
6570 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6571 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6572 fprintf_unfiltered (file
,
6573 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6575 #ifdef MACHINE_CPROC_FP_OFFSET
6576 fprintf_unfiltered (file
,
6577 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6578 MACHINE_CPROC_FP_OFFSET
);
6580 #ifdef MACHINE_CPROC_PC_OFFSET
6581 fprintf_unfiltered (file
,
6582 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6583 MACHINE_CPROC_PC_OFFSET
);
6585 #ifdef MACHINE_CPROC_SP_OFFSET
6586 fprintf_unfiltered (file
,
6587 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6588 MACHINE_CPROC_SP_OFFSET
);
6590 fprintf_unfiltered (file
,
6591 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6593 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6594 fprintf_unfiltered (file
,
6595 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6596 fprintf_unfiltered (file
,
6597 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6598 fprintf_unfiltered (file
,
6599 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6600 MIPS_LAST_ARG_REGNUM
,
6601 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6602 fprintf_unfiltered (file
,
6603 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6604 fprintf_unfiltered (file
,
6605 "mips_dump_tdep: mips_abi_regsize() = %d\n",
6606 mips_abi_regsize (current_gdbarch
));
6607 fprintf_unfiltered (file
,
6608 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6609 fprintf_unfiltered (file
,
6610 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6611 fprintf_unfiltered (file
,
6612 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6613 fprintf_unfiltered (file
,
6614 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6615 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6616 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6617 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6618 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6619 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6620 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6621 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6622 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6623 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6624 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6625 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6627 fprintf_unfiltered (file
,
6628 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6631 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6634 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6636 fprintf_unfiltered (file
,
6637 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6638 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6639 fprintf_unfiltered (file
,
6640 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6641 fprintf_unfiltered (file
,
6642 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6643 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6644 fprintf_unfiltered (file
,
6645 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6646 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6647 fprintf_unfiltered (file
,
6648 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6649 SOFTWARE_SINGLE_STEP_P ());
6650 fprintf_unfiltered (file
,
6651 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6652 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6653 #ifdef STACK_END_ADDR
6654 fprintf_unfiltered (file
,
6655 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6658 fprintf_unfiltered (file
,
6659 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6660 XSTRING (STEP_SKIPS_DELAY (PC
)));
6661 fprintf_unfiltered (file
,
6662 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6663 STEP_SKIPS_DELAY_P
);
6664 fprintf_unfiltered (file
,
6665 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6666 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6667 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6668 fprintf_unfiltered (file
,
6669 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6670 fprintf_unfiltered (file
,
6671 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6672 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6673 (TYPE
, CNT
, OTHERTYPE
)));
6674 fprintf_unfiltered (file
,
6675 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6676 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6678 fprintf_unfiltered (file
,
6679 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6680 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6683 fprintf_unfiltered (file
,
6684 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6686 #ifdef TRACE_FLAVOR_SIZE
6687 fprintf_unfiltered (file
,
6688 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6692 fprintf_unfiltered (file
,
6693 "mips_dump_tdep: TRACE_SET # %s\n",
6694 XSTRING (TRACE_SET (X
, STATE
)));
6696 #ifdef UNUSED_REGNUM
6697 fprintf_unfiltered (file
,
6698 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6700 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6701 fprintf_unfiltered (file
,
6702 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6703 (long) VM_MIN_ADDRESS
);
6704 fprintf_unfiltered (file
,
6705 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6706 fprintf_unfiltered (file
,
6707 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_
);
6710 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6713 _initialize_mips_tdep (void)
6715 static struct cmd_list_element
*mipsfpulist
= NULL
;
6716 struct cmd_list_element
*c
;
6718 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6719 if (MIPS_ABI_LAST
+ 1
6720 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6721 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6723 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6725 mips_pdr_data
= register_objfile_data ();
6727 /* Add root prefix command for all "set mips"/"show mips" commands */
6728 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6729 "Various MIPS specific commands.",
6730 &setmipscmdlist
, "set mips ", 0, &setlist
);
6732 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6733 "Various MIPS specific commands.",
6734 &showmipscmdlist
, "show mips ", 0, &showlist
);
6736 /* Allow the user to override the saved register size. */
6737 deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6740 &mips_abi_regsize_string
, "\
6741 Set size of general purpose registers saved on the stack.\n\
6742 This option can be set to one of:\n\
6743 32 - Force GDB to treat saved GP registers as 32-bit\n\
6744 64 - Force GDB to treat saved GP registers as 64-bit\n\
6745 auto - Allow GDB to use the target's default setting or autodetect the\n\
6746 saved GP register size from information contained in the executable.\n\
6747 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6749 /* Allow the user to override the argument stack size. */
6750 deprecated_add_show_from_set
6751 (add_set_enum_cmd ("stack-arg-size",
6754 &mips_stack_argsize_string
, "\
6755 Set the amount of stack space reserved for each argument.\n\
6756 This option can be set to one of:\n\
6757 32 - Force GDB to allocate 32-bit chunks per argument\n\
6758 64 - Force GDB to allocate 64-bit chunks per argument\n\
6759 auto - Allow GDB to determine the correct setting from the current\n\
6760 target and executable (default)", &setmipscmdlist
),
6763 /* Allow the user to override the ABI. */
6764 c
= add_set_enum_cmd
6765 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6766 "Set the ABI used by this program.\n"
6767 "This option can be set to one of:\n"
6768 " auto - the default ABI associated with the current binary\n"
6770 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6771 set_cmd_sfunc (c
, mips_abi_update
);
6772 add_cmd ("abi", class_obscure
, show_mips_abi
,
6773 "Show ABI in use by MIPS target", &showmipscmdlist
);
6775 /* Let the user turn off floating point and set the fence post for
6776 heuristic_proc_start. */
6778 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6779 "Set use of MIPS floating-point coprocessor.",
6780 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6781 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6782 "Select single-precision MIPS floating-point coprocessor.",
6784 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6785 "Select double-precision MIPS floating-point coprocessor.",
6787 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6788 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6789 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6790 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6791 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6792 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6793 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6794 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6795 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6796 "Select MIPS floating-point coprocessor automatically.",
6798 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6799 "Show current use of MIPS floating-point coprocessor target.",
6802 /* We really would like to have both "0" and "unlimited" work, but
6803 command.c doesn't deal with that. So make it a var_zinteger
6804 because the user can always use "999999" or some such for unlimited. */
6805 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6806 (char *) &heuristic_fence_post
, "\
6807 Set the distance searched for the start of a function.\n\
6808 If you are debugging a stripped executable, GDB needs to search through the\n\
6809 program for the start of a function. This command sets the distance of the\n\
6810 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6811 /* We need to throw away the frame cache when we set this, since it
6812 might change our ability to get backtraces. */
6813 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6814 deprecated_add_show_from_set (c
, &showlist
);
6816 /* Allow the user to control whether the upper bits of 64-bit
6817 addresses should be zeroed. */
6818 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6819 Set zeroing of upper 32 bits of 64-bit addresses.", "\
6820 Show zeroing of upper 32 bits of 64-bit addresses.", "\
6821 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6822 allow GDB to determine the correct value.\n", "\
6823 Zerroing of upper 32 bits of 64-bit address is %s.",
6824 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6826 /* Allow the user to control the size of 32 bit registers within the
6827 raw remote packet. */
6828 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6829 &mips64_transfers_32bit_regs_p
, "\
6830 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6831 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6832 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6833 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6834 64 bits for others. Use \"off\" to disable compatibility mode", "\
6835 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6836 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6838 /* Debug this files internals. */
6839 deprecated_add_show_from_set
6840 (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6841 &mips_debug
, "Set mips debugging.\n\
6842 When non-zero, mips specific debugging is enabled.", &setdebuglist
),