1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 /* A useful bit in the CP0 status register (PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE
= 4,
72 MIPS_FPU_DOUBLE_REGSIZE
= 8
76 static const char *mips_abi_string
;
78 static const char *mips_abi_strings
[] = {
89 struct frame_extra_info
91 mips_extra_func_info_t proc_desc
;
95 /* Various MIPS ISA options (related to stack analysis) can be
96 overridden dynamically. Establish an enum/array for managing
99 static const char size_auto
[] = "auto";
100 static const char size_32
[] = "32";
101 static const char size_64
[] = "64";
103 static const char *size_enums
[] = {
110 /* Some MIPS boards don't support floating point while others only
111 support single-precision floating-point operations. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int default_mask_address_p
;
141 /* Is the target using 64-bit raw integer registers but only
142 storing a left-aligned 32-bit value in each? */
143 int mips64_transfers_32bit_regs_p
;
144 /* Indexes for various registers. IRIX and embedded have
145 different values. This contains the "public" fields. Don't
146 add any that do not need to be public. */
147 const struct mips_regnum
*regnum
;
148 /* Register names table for the current register set. */
149 const char **mips_processor_reg_names
;
153 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
159 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
160 They are implemented as a pair of 64bit doubles where the high
161 part holds the result of the operation rounded to double, and
162 the low double holds the difference between the exact result and
163 the rounded result. So "high" + "low" contains the result with
164 added precision. Unfortunately, the floatformat structure used
165 by GDB is not powerful enough to describe this format. As a temporary
166 measure, we define a 128bit floatformat that only uses the high part.
167 We lose a bit of precision but that's probably the best we can do
168 for now with the current infrastructure. */
170 static const struct floatformat floatformat_n32n64_long_double_big
=
172 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
173 floatformat_intbit_no
,
174 "floatformat_ieee_double_big",
175 n32n64_floatformat_always_valid
178 const struct mips_regnum
*
179 mips_regnum (struct gdbarch
*gdbarch
)
181 return gdbarch_tdep (gdbarch
)->regnum
;
185 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
187 return mips_regnum (gdbarch
)->fp0
+ 12;
190 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
191 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
193 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
195 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
197 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
199 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
200 functions to test, set, or clear bit 0 of addresses. */
203 is_mips16_addr (CORE_ADDR addr
)
209 make_mips16_addr (CORE_ADDR addr
)
215 unmake_mips16_addr (CORE_ADDR addr
)
217 return ((addr
) & ~1);
220 /* Return the contents of register REGNUM as a signed integer. */
223 read_signed_register (int regnum
)
225 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
226 deprecated_read_register_gen (regnum
, buf
);
227 return (extract_signed_integer
228 (buf
, register_size (current_gdbarch
, regnum
)));
232 read_signed_register_pid (int regnum
, ptid_t ptid
)
237 if (ptid_equal (ptid
, inferior_ptid
))
238 return read_signed_register (regnum
);
240 save_ptid
= inferior_ptid
;
242 inferior_ptid
= ptid
;
244 retval
= read_signed_register (regnum
);
246 inferior_ptid
= save_ptid
;
251 /* Return the MIPS ABI associated with GDBARCH. */
253 mips_abi (struct gdbarch
*gdbarch
)
255 return gdbarch_tdep (gdbarch
)->mips_abi
;
259 mips_isa_regsize (struct gdbarch
*gdbarch
)
261 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
262 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
265 /* Return the currently configured (or set) saved register size. */
267 static const char *mips_abi_regsize_string
= size_auto
;
270 mips_abi_regsize (struct gdbarch
*gdbarch
)
272 if (mips_abi_regsize_string
== size_auto
)
273 switch (mips_abi (gdbarch
))
275 case MIPS_ABI_EABI32
:
281 case MIPS_ABI_EABI64
:
283 case MIPS_ABI_UNKNOWN
:
286 internal_error (__FILE__
, __LINE__
, "bad switch");
288 else if (mips_abi_regsize_string
== size_64
)
290 else /* if (mips_abi_regsize_string == size_32) */
294 /* Functions for setting and testing a bit in a minimal symbol that
295 marks it as 16-bit function. The MSB of the minimal symbol's
296 "info" field is used for this purpose.
298 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
299 i.e. refers to a 16-bit function, and sets a "special" bit in a
300 minimal symbol to mark it as a 16-bit function
302 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
305 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
307 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
309 MSYMBOL_INFO (msym
) = (char *)
310 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
311 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
316 msymbol_is_special (struct minimal_symbol
*msym
)
318 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
321 /* XFER a value from the big/little/left end of the register.
322 Depending on the size of the value it might occupy the entire
323 register or just part of it. Make an allowance for this, aligning
324 things accordingly. */
327 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
328 enum bfd_endian endian
, bfd_byte
* in
,
329 const bfd_byte
* out
, int buf_offset
)
332 gdb_assert (reg_num
>= NUM_REGS
);
333 /* Need to transfer the left or right part of the register, based on
334 the targets byte order. */
338 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
340 case BFD_ENDIAN_LITTLE
:
343 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
347 internal_error (__FILE__
, __LINE__
, "bad switch");
350 fprintf_unfiltered (gdb_stderr
,
351 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
352 reg_num
, reg_offset
, buf_offset
, length
);
353 if (mips_debug
&& out
!= NULL
)
356 fprintf_unfiltered (gdb_stdlog
, "out ");
357 for (i
= 0; i
< length
; i
++)
358 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
361 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
364 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
366 if (mips_debug
&& in
!= NULL
)
369 fprintf_unfiltered (gdb_stdlog
, "in ");
370 for (i
= 0; i
< length
; i
++)
371 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
374 fprintf_unfiltered (gdb_stdlog
, "\n");
377 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
378 compatiblity mode. A return value of 1 means that we have
379 physical 64-bit registers, but should treat them as 32-bit registers. */
382 mips2_fp_compat (void)
384 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
386 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
391 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
392 in all the places we deal with FP registers. PR gdb/413. */
393 /* Otherwise check the FR bit in the status register - it controls
394 the FP compatiblity mode. If it is clear we are in compatibility
396 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
403 /* The amount of space reserved on the stack for registers. This is
404 different to MIPS_ABI_REGSIZE as it determines the alignment of
405 data allocated after the registers have run out. */
407 static const char *mips_stack_argsize_string
= size_auto
;
410 mips_stack_argsize (struct gdbarch
*gdbarch
)
412 if (mips_stack_argsize_string
== size_auto
)
413 return mips_abi_regsize (gdbarch
);
414 else if (mips_stack_argsize_string
== size_64
)
416 else /* if (mips_stack_argsize_string == size_32) */
420 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
422 struct mips_frame_cache
;
423 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
425 struct mips_frame_cache
*);
426 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
429 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
431 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
433 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
435 static CORE_ADDR
after_prologue (CORE_ADDR pc
);
437 static struct type
*mips_float_register_type (void);
438 static struct type
*mips_double_register_type (void);
440 /* The list of available "set mips " and "show mips " commands */
442 static struct cmd_list_element
*setmipscmdlist
= NULL
;
443 static struct cmd_list_element
*showmipscmdlist
= NULL
;
445 /* Integer registers 0 thru 31 are handled explicitly by
446 mips_register_name(). Processor specific registers 32 and above
447 are listed in the followign tables. */
450 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
454 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
455 "sr", "lo", "hi", "bad", "cause", "pc",
456 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
457 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
458 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
459 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
460 "fsr", "fir", "" /*"fp" */ , "",
461 "", "", "", "", "", "", "", "",
462 "", "", "", "", "", "", "", "",
465 /* Names of IDT R3041 registers. */
467 static const char *mips_r3041_reg_names
[] = {
468 "sr", "lo", "hi", "bad", "cause", "pc",
469 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
470 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
471 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
472 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
473 "fsr", "fir", "", /*"fp" */ "",
474 "", "", "bus", "ccfg", "", "", "", "",
475 "", "", "port", "cmp", "", "", "epc", "prid",
478 /* Names of tx39 registers. */
480 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
481 "sr", "lo", "hi", "bad", "cause", "pc",
482 "", "", "", "", "", "", "", "",
483 "", "", "", "", "", "", "", "",
484 "", "", "", "", "", "", "", "",
485 "", "", "", "", "", "", "", "",
487 "", "", "", "", "", "", "", "",
488 "", "", "config", "cache", "debug", "depc", "epc", ""
491 /* Names of IRIX registers. */
492 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
493 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
494 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
495 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
496 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
497 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
501 /* Return the name of the register corresponding to REGNO. */
503 mips_register_name (int regno
)
505 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
506 /* GPR names for all ABIs other than n32/n64. */
507 static char *mips_gpr_names
[] = {
508 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
509 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
510 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
511 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
514 /* GPR names for n32 and n64 ABIs. */
515 static char *mips_n32_n64_gpr_names
[] = {
516 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
517 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
518 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
519 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
522 enum mips_abi abi
= mips_abi (current_gdbarch
);
524 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
525 don't make the raw register names visible. */
526 int rawnum
= regno
% NUM_REGS
;
527 if (regno
< NUM_REGS
)
530 /* The MIPS integer registers are always mapped from 0 to 31. The
531 names of the registers (which reflects the conventions regarding
532 register use) vary depending on the ABI. */
533 if (0 <= rawnum
&& rawnum
< 32)
535 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
536 return mips_n32_n64_gpr_names
[rawnum
];
538 return mips_gpr_names
[rawnum
];
540 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
542 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
543 return tdep
->mips_processor_reg_names
[rawnum
- 32];
546 internal_error (__FILE__
, __LINE__
,
547 "mips_register_name: bad register number %d", rawnum
);
550 /* Return the groups that a MIPS register can be categorised into. */
553 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
554 struct reggroup
*reggroup
)
559 int rawnum
= regnum
% NUM_REGS
;
560 int pseudo
= regnum
/ NUM_REGS
;
561 if (reggroup
== all_reggroup
)
563 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
564 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
565 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
566 (gdbarch), as not all architectures are multi-arch. */
567 raw_p
= rawnum
< NUM_REGS
;
568 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
570 if (reggroup
== float_reggroup
)
571 return float_p
&& pseudo
;
572 if (reggroup
== vector_reggroup
)
573 return vector_p
&& pseudo
;
574 if (reggroup
== general_reggroup
)
575 return (!vector_p
&& !float_p
) && pseudo
;
576 /* Save the pseudo registers. Need to make certain that any code
577 extracting register values from a saved register cache also uses
579 if (reggroup
== save_reggroup
)
580 return raw_p
&& pseudo
;
581 /* Restore the same pseudo register. */
582 if (reggroup
== restore_reggroup
)
583 return raw_p
&& pseudo
;
587 /* Map the symbol table registers which live in the range [1 *
588 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
589 registers. Take care of alignment and size problems. */
592 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
593 int cookednum
, void *buf
)
595 int rawnum
= cookednum
% NUM_REGS
;
596 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
597 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
598 regcache_raw_read (regcache
, rawnum
, buf
);
599 else if (register_size (gdbarch
, rawnum
) >
600 register_size (gdbarch
, cookednum
))
602 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
603 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
604 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
606 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
609 internal_error (__FILE__
, __LINE__
, "bad register size");
613 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
614 struct regcache
*regcache
, int cookednum
,
617 int rawnum
= cookednum
% NUM_REGS
;
618 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
619 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
620 regcache_raw_write (regcache
, rawnum
, buf
);
621 else if (register_size (gdbarch
, rawnum
) >
622 register_size (gdbarch
, cookednum
))
624 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
625 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
626 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
628 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
631 internal_error (__FILE__
, __LINE__
, "bad register size");
634 /* Table to translate MIPS16 register field to actual register number. */
635 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
637 /* Heuristic_proc_start may hunt through the text section for a long
638 time across a 2400 baud serial line. Allows the user to limit this
641 static unsigned int heuristic_fence_post
= 0;
643 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
644 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
645 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
646 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
647 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
648 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
649 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
650 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
651 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
652 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
653 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
654 this will corrupt pdr.iline. Fortunately we don't use it. */
655 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
656 #define _PROC_MAGIC_ 0x0F0F0F0F
658 /* Number of bytes of storage in the actual machine representation for
659 register N. NOTE: This defines the pseudo register type so need to
660 rebuild the architecture vector. */
662 static int mips64_transfers_32bit_regs_p
= 0;
665 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
666 struct cmd_list_element
*c
)
668 struct gdbarch_info info
;
669 gdbarch_info_init (&info
);
670 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
671 instead of relying on globals. Doing that would let generic code
672 handle the search for this specific architecture. */
673 if (!gdbarch_update_p (info
))
675 mips64_transfers_32bit_regs_p
= 0;
676 error ("32-bit compatibility mode not supported");
680 /* Convert to/from a register and the corresponding memory value. */
683 mips_convert_register_p (int regnum
, struct type
*type
)
685 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
686 && register_size (current_gdbarch
, regnum
) == 4
687 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
688 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
689 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
693 mips_register_to_value (struct frame_info
*frame
, int regnum
,
694 struct type
*type
, void *to
)
696 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
697 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
701 mips_value_to_register (struct frame_info
*frame
, int regnum
,
702 struct type
*type
, const void *from
)
704 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
705 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
708 /* Return the GDB type object for the "standard" data type of data in
712 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
714 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
715 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
716 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
718 /* The floating-point registers raw, or cooked, always match
719 mips_isa_regsize(), and also map 1:1, byte for byte. */
720 switch (gdbarch_byte_order (gdbarch
))
723 if (mips_isa_regsize (gdbarch
) == 4)
724 return builtin_type_ieee_single_big
;
726 return builtin_type_ieee_double_big
;
727 case BFD_ENDIAN_LITTLE
:
728 if (mips_isa_regsize (gdbarch
) == 4)
729 return builtin_type_ieee_single_little
;
731 return builtin_type_ieee_double_little
;
732 case BFD_ENDIAN_UNKNOWN
:
734 internal_error (__FILE__
, __LINE__
, "bad switch");
737 else if (regnum
< NUM_REGS
)
739 /* The raw or ISA registers. These are all sized according to
741 if (mips_isa_regsize (gdbarch
) == 4)
742 return builtin_type_int32
;
744 return builtin_type_int64
;
748 /* The cooked or ABI registers. These are sized according to
749 the ABI (with a few complications). */
750 if (regnum
>= (NUM_REGS
751 + mips_regnum (current_gdbarch
)->fp_control_status
)
752 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
753 /* The pseudo/cooked view of the embedded registers is always
754 32-bit. The raw view is handled below. */
755 return builtin_type_int32
;
756 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
757 /* The target, while possibly using a 64-bit register buffer,
758 is only transfering 32-bits of each integer register.
759 Reflect this in the cooked/pseudo (ABI) register value. */
760 return builtin_type_int32
;
761 else if (mips_abi_regsize (gdbarch
) == 4)
762 /* The ABI is restricted to 32-bit registers (the ISA could be
764 return builtin_type_int32
;
767 return builtin_type_int64
;
771 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
776 return read_signed_register (MIPS_SP_REGNUM
);
779 /* Should the upper word of 64-bit addresses be zeroed? */
780 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
783 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
785 switch (mask_address_var
)
787 case AUTO_BOOLEAN_TRUE
:
789 case AUTO_BOOLEAN_FALSE
:
792 case AUTO_BOOLEAN_AUTO
:
793 return tdep
->default_mask_address_p
;
795 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
801 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
803 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
804 switch (mask_address_var
)
806 case AUTO_BOOLEAN_TRUE
:
807 printf_filtered ("The 32 bit mips address mask is enabled\n");
809 case AUTO_BOOLEAN_FALSE
:
810 printf_filtered ("The 32 bit mips address mask is disabled\n");
812 case AUTO_BOOLEAN_AUTO
:
814 ("The 32 bit address mask is set automatically. Currently %s\n",
815 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
818 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
823 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
826 pc_is_mips16 (bfd_vma memaddr
)
828 struct minimal_symbol
*sym
;
830 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
831 if (is_mips16_addr (memaddr
))
834 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
835 the high bit of the info field. Use this to decide if the function is
836 MIPS16 or normal MIPS. */
837 sym
= lookup_minimal_symbol_by_pc (memaddr
);
839 return msymbol_is_special (sym
);
844 /* MIPS believes that the PC has a sign extended value. Perhaps the
845 all registers should be sign extended for simplicity? */
848 mips_read_pc (ptid_t ptid
)
850 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
854 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
856 return frame_unwind_register_signed (next_frame
,
857 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
860 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
861 dummy frame. The frame ID's base needs to match the TOS value
862 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
865 static struct frame_id
866 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
868 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
869 frame_pc_unwind (next_frame
));
873 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
875 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
878 /* This returns the PC of the first inst after the prologue. If we can't
879 find the prologue, then return 0. */
882 after_prologue (CORE_ADDR pc
)
884 mips_extra_func_info_t proc_desc
;
885 struct symtab_and_line sal
;
886 CORE_ADDR func_addr
, func_end
;
887 CORE_ADDR startaddr
= 0;
889 /* Pass a NULL next_frame to heuristic_proc_desc. We should not
890 attempt to read the stack pointer from the current machine state,
891 because the current machine state has nothing to do with the
892 information we need from the proc_desc; and the process may or
893 may not exist right now. */
894 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
897 /* IF this is the topmost frame AND (this proc does not have
898 debugging information OR the PC is in the procedure prologue)
899 THEN create a "heuristic" proc_desc (by analyzing the actual
900 code) to replace the "official" proc_desc. */
901 struct symtab_and_line val
;
902 if (PROC_SYMBOL (proc_desc
))
904 val
= find_pc_line (BLOCK_START
905 (SYMBOL_BLOCK_VALUE (PROC_SYMBOL (proc_desc
))),
907 val
.pc
= val
.end
? val
.end
: pc
;
909 if (!PROC_SYMBOL (proc_desc
) || pc
< val
.pc
)
911 mips_extra_func_info_t found_heuristic
=
912 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
), pc
, NULL
, NULL
);
914 proc_desc
= found_heuristic
;
920 startaddr
= heuristic_proc_start (pc
);
922 proc_desc
= heuristic_proc_desc (startaddr
, pc
, NULL
, NULL
);
927 /* If function is frameless, then we need to do it the hard way. I
928 strongly suspect that frameless always means prologueless... */
929 if (PROC_FRAME_REG (proc_desc
) == MIPS_SP_REGNUM
930 && PROC_FRAME_OFFSET (proc_desc
) == 0)
934 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
935 return 0; /* Unknown */
937 sal
= find_pc_line (func_addr
, 0);
939 if (sal
.end
< func_end
)
942 /* The line after the prologue is after the end of the function. In this
943 case, tell the caller to find the prologue the hard way. */
948 /* Fetch and return instruction from the specified location. If the PC
949 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
952 mips_fetch_instruction (CORE_ADDR addr
)
954 char buf
[MIPS_INSTLEN
];
958 if (pc_is_mips16 (addr
))
960 instlen
= MIPS16_INSTLEN
;
961 addr
= unmake_mips16_addr (addr
);
964 instlen
= MIPS_INSTLEN
;
965 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
967 memory_error (status
, addr
);
968 return extract_unsigned_integer (buf
, instlen
);
972 mips16_fetch_instruction (CORE_ADDR addr
)
974 char buf
[MIPS_INSTLEN
];
978 instlen
= MIPS16_INSTLEN
;
979 addr
= unmake_mips16_addr (addr
);
980 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
982 memory_error (status
, addr
);
983 return extract_unsigned_integer (buf
, instlen
);
986 /* These the fields of 32 bit mips instructions */
987 #define mips32_op(x) (x >> 26)
988 #define itype_op(x) (x >> 26)
989 #define itype_rs(x) ((x >> 21) & 0x1f)
990 #define itype_rt(x) ((x >> 16) & 0x1f)
991 #define itype_immediate(x) (x & 0xffff)
993 #define jtype_op(x) (x >> 26)
994 #define jtype_target(x) (x & 0x03ffffff)
996 #define rtype_op(x) (x >> 26)
997 #define rtype_rs(x) ((x >> 21) & 0x1f)
998 #define rtype_rt(x) ((x >> 16) & 0x1f)
999 #define rtype_rd(x) ((x >> 11) & 0x1f)
1000 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1001 #define rtype_funct(x) (x & 0x3f)
1004 mips32_relative_offset (unsigned long inst
)
1007 x
= itype_immediate (inst
);
1008 if (x
& 0x8000) /* sign bit set */
1010 x
|= 0xffff0000; /* sign extension */
1016 /* Determine whate to set a single step breakpoint while considering
1017 branch prediction */
1019 mips32_next_pc (CORE_ADDR pc
)
1023 inst
= mips_fetch_instruction (pc
);
1024 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1026 if (itype_op (inst
) >> 2 == 5)
1027 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1029 op
= (itype_op (inst
) & 0x03);
1039 goto greater_branch
;
1044 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1045 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1047 int tf
= itype_rt (inst
) & 0x01;
1048 int cnum
= itype_rt (inst
) >> 2;
1050 read_signed_register (mips_regnum (current_gdbarch
)->
1052 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1054 if (((cond
>> cnum
) & 0x01) == tf
)
1055 pc
+= mips32_relative_offset (inst
) + 4;
1060 pc
+= 4; /* Not a branch, next instruction is easy */
1063 { /* This gets way messy */
1065 /* Further subdivide into SPECIAL, REGIMM and other */
1066 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1068 case 0: /* SPECIAL */
1069 op
= rtype_funct (inst
);
1074 /* Set PC to that address */
1075 pc
= read_signed_register (rtype_rs (inst
));
1081 break; /* end SPECIAL */
1082 case 1: /* REGIMM */
1084 op
= itype_rt (inst
); /* branch condition */
1089 case 16: /* BLTZAL */
1090 case 18: /* BLTZALL */
1092 if (read_signed_register (itype_rs (inst
)) < 0)
1093 pc
+= mips32_relative_offset (inst
) + 4;
1095 pc
+= 8; /* after the delay slot */
1099 case 17: /* BGEZAL */
1100 case 19: /* BGEZALL */
1101 if (read_signed_register (itype_rs (inst
)) >= 0)
1102 pc
+= mips32_relative_offset (inst
) + 4;
1104 pc
+= 8; /* after the delay slot */
1106 /* All of the other instructions in the REGIMM category */
1111 break; /* end REGIMM */
1116 reg
= jtype_target (inst
) << 2;
1117 /* Upper four bits get never changed... */
1118 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1121 /* FIXME case JALX : */
1124 reg
= jtype_target (inst
) << 2;
1125 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1126 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1128 break; /* The new PC will be alternate mode */
1129 case 4: /* BEQ, BEQL */
1131 if (read_signed_register (itype_rs (inst
)) ==
1132 read_signed_register (itype_rt (inst
)))
1133 pc
+= mips32_relative_offset (inst
) + 4;
1137 case 5: /* BNE, BNEL */
1139 if (read_signed_register (itype_rs (inst
)) !=
1140 read_signed_register (itype_rt (inst
)))
1141 pc
+= mips32_relative_offset (inst
) + 4;
1145 case 6: /* BLEZ, BLEZL */
1146 if (read_signed_register (itype_rs (inst
)) <= 0)
1147 pc
+= mips32_relative_offset (inst
) + 4;
1153 greater_branch
: /* BGTZ, BGTZL */
1154 if (read_signed_register (itype_rs (inst
)) > 0)
1155 pc
+= mips32_relative_offset (inst
) + 4;
1162 } /* mips32_next_pc */
1164 /* Decoding the next place to set a breakpoint is irregular for the
1165 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1166 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1167 We dont want to set a single step instruction on the extend instruction
1171 /* Lots of mips16 instruction formats */
1172 /* Predicting jumps requires itype,ritype,i8type
1173 and their extensions extItype,extritype,extI8type
1175 enum mips16_inst_fmts
1177 itype
, /* 0 immediate 5,10 */
1178 ritype
, /* 1 5,3,8 */
1179 rrtype
, /* 2 5,3,3,5 */
1180 rritype
, /* 3 5,3,3,5 */
1181 rrrtype
, /* 4 5,3,3,3,2 */
1182 rriatype
, /* 5 5,3,3,1,4 */
1183 shifttype
, /* 6 5,3,3,3,2 */
1184 i8type
, /* 7 5,3,8 */
1185 i8movtype
, /* 8 5,3,3,5 */
1186 i8mov32rtype
, /* 9 5,3,5,3 */
1187 i64type
, /* 10 5,3,8 */
1188 ri64type
, /* 11 5,3,3,5 */
1189 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1190 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1191 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1192 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1193 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1194 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1195 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1196 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1197 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1198 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1200 /* I am heaping all the fields of the formats into one structure and
1201 then, only the fields which are involved in instruction extension */
1205 unsigned int regx
; /* Function in i8 type */
1210 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1211 for the bits which make up the immediatate extension. */
1214 extended_offset (unsigned int extension
)
1217 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1219 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1221 value
|= extension
& 0x01f; /* extract 4:0 */
1225 /* Only call this function if you know that this is an extendable
1226 instruction, It wont malfunction, but why make excess remote memory references?
1227 If the immediate operands get sign extended or somthing, do it after
1228 the extension is performed.
1230 /* FIXME: Every one of these cases needs to worry about sign extension
1231 when the offset is to be used in relative addressing */
1235 fetch_mips_16 (CORE_ADDR pc
)
1238 pc
&= 0xfffffffe; /* clear the low order bit */
1239 target_read_memory (pc
, buf
, 2);
1240 return extract_unsigned_integer (buf
, 2);
1244 unpack_mips16 (CORE_ADDR pc
,
1245 unsigned int extension
,
1247 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1252 switch (insn_format
)
1259 value
= extended_offset (extension
);
1260 value
= value
<< 11; /* rom for the original value */
1261 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1265 value
= inst
& 0x7ff;
1266 /* FIXME : Consider sign extension */
1275 { /* A register identifier and an offset */
1276 /* Most of the fields are the same as I type but the
1277 immediate value is of a different length */
1281 value
= extended_offset (extension
);
1282 value
= value
<< 8; /* from the original instruction */
1283 value
|= inst
& 0xff; /* eleven bits from instruction */
1284 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1285 if (value
& 0x4000) /* test the sign bit , bit 26 */
1287 value
&= ~0x3fff; /* remove the sign bit */
1293 value
= inst
& 0xff; /* 8 bits */
1294 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1295 /* FIXME: Do sign extension , this format needs it */
1296 if (value
& 0x80) /* THIS CONFUSES ME */
1298 value
&= 0xef; /* remove the sign bit */
1308 unsigned long value
;
1309 unsigned int nexthalf
;
1310 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1311 value
= value
<< 16;
1312 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1320 internal_error (__FILE__
, __LINE__
, "bad switch");
1322 upk
->offset
= offset
;
1329 add_offset_16 (CORE_ADDR pc
, int offset
)
1331 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1335 extended_mips16_next_pc (CORE_ADDR pc
,
1336 unsigned int extension
, unsigned int insn
)
1338 int op
= (insn
>> 11);
1341 case 2: /* Branch */
1344 struct upk_mips16 upk
;
1345 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1346 offset
= upk
.offset
;
1352 pc
+= (offset
<< 1) + 2;
1355 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1357 struct upk_mips16 upk
;
1358 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1359 pc
= add_offset_16 (pc
, upk
.offset
);
1360 if ((insn
>> 10) & 0x01) /* Exchange mode */
1361 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1368 struct upk_mips16 upk
;
1370 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1371 reg
= read_signed_register (upk
.regx
);
1373 pc
+= (upk
.offset
<< 1) + 2;
1380 struct upk_mips16 upk
;
1382 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1383 reg
= read_signed_register (upk
.regx
);
1385 pc
+= (upk
.offset
<< 1) + 2;
1390 case 12: /* I8 Formats btez btnez */
1392 struct upk_mips16 upk
;
1394 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1395 /* upk.regx contains the opcode */
1396 reg
= read_signed_register (24); /* Test register is 24 */
1397 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1398 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1399 /* pc = add_offset_16(pc,upk.offset) ; */
1400 pc
+= (upk
.offset
<< 1) + 2;
1405 case 29: /* RR Formats JR, JALR, JALR-RA */
1407 struct upk_mips16 upk
;
1408 /* upk.fmt = rrtype; */
1413 upk
.regx
= (insn
>> 8) & 0x07;
1414 upk
.regy
= (insn
>> 5) & 0x07;
1422 break; /* Function return instruction */
1428 break; /* BOGUS Guess */
1430 pc
= read_signed_register (reg
);
1437 /* This is an instruction extension. Fetch the real instruction
1438 (which follows the extension) and decode things based on
1442 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1455 mips16_next_pc (CORE_ADDR pc
)
1457 unsigned int insn
= fetch_mips_16 (pc
);
1458 return extended_mips16_next_pc (pc
, 0, insn
);
1461 /* The mips_next_pc function supports single_step when the remote
1462 target monitor or stub is not developed enough to do a single_step.
1463 It works by decoding the current instruction and predicting where a
1464 branch will go. This isnt hard because all the data is available.
1465 The MIPS32 and MIPS16 variants are quite different */
1467 mips_next_pc (CORE_ADDR pc
)
1470 return mips16_next_pc (pc
);
1472 return mips32_next_pc (pc
);
1475 struct mips_frame_cache
1478 struct trad_frame_saved_reg
*saved_regs
;
1482 static struct mips_frame_cache
*
1483 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1485 CORE_ADDR startaddr
= 0;
1486 mips_extra_func_info_t proc_desc
;
1487 struct mips_frame_cache
*cache
;
1488 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1489 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1490 /* r0 bit means kernel trap */
1492 /* What registers have been saved? Bitmasks. */
1493 unsigned long gen_mask
, float_mask
;
1495 if ((*this_cache
) != NULL
)
1496 return (*this_cache
);
1497 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1498 (*this_cache
) = cache
;
1499 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1501 /* Get the mdebug proc descriptor. */
1502 proc_desc
= non_heuristic_proc_desc (frame_pc_unwind (next_frame
),
1504 /* Must be true. This is only called when the sniffer detected a
1506 gdb_assert (proc_desc
!= NULL
);
1508 /* Extract the frame's base. */
1509 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1510 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1512 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1513 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1514 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1516 /* Must be true. The in_prologue case is left for the heuristic
1517 unwinder. This is always used on kernel traps. */
1518 gdb_assert (!in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1521 /* Fill in the offsets for the registers which gen_mask says were
1524 CORE_ADDR reg_position
= (cache
->base
+ PROC_REG_OFFSET (proc_desc
));
1527 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1528 if (gen_mask
& 0x80000000)
1530 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1531 reg_position
-= mips_abi_regsize (gdbarch
);
1535 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1536 order of that normally used by gcc. Therefore, we have to fetch
1537 the first instruction of the function, and if it's an entry
1538 instruction that saves $s0 or $s1, correct their saved addresses. */
1539 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1541 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1542 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1546 int sreg_count
= (inst
>> 6) & 3;
1548 /* Check if the ra register was pushed on the stack. */
1549 CORE_ADDR reg_position
= (cache
->base
1550 + PROC_REG_OFFSET (proc_desc
));
1552 reg_position
-= mips_abi_regsize (gdbarch
);
1554 /* Check if the s0 and s1 registers were pushed on the
1556 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1558 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1560 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1561 reg_position
-= mips_abi_regsize (gdbarch
);
1566 /* Fill in the offsets for the registers which float_mask says were
1569 CORE_ADDR reg_position
= (cache
->base
1570 + PROC_FREG_OFFSET (proc_desc
));
1572 /* Fill in the offsets for the float registers which float_mask
1574 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1575 if (float_mask
& 0x80000000)
1577 if (mips_abi_regsize (gdbarch
) == 4
1578 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1580 /* On a big endian 32 bit ABI, floating point registers
1581 are paired to form doubles such that the most
1582 significant part is in $f[N+1] and the least
1583 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1584 registers are also spilled as a pair and stored as a
1587 When little-endian the least significant part is
1588 stored first leading to the memory order $f[N] and
1591 Unfortunately, when big-endian the most significant
1592 part of the double is stored first, and the least
1593 significant is stored second. This leads to the
1594 registers being ordered in memory as firt $f[N+1] and
1597 For the big-endian case make certain that the
1598 addresses point at the correct (swapped) locations
1599 $f[N] and $f[N+1] pair (keep in mind that
1600 reg_position is decremented each time through the
1603 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1604 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1606 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1607 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1610 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1611 .addr
= reg_position
;
1612 reg_position
-= mips_abi_regsize (gdbarch
);
1615 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1616 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1619 /* SP_REGNUM, contains the value and not the address. */
1620 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1622 return (*this_cache
);
1626 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1627 struct frame_id
*this_id
)
1629 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1631 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1635 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1637 int regnum
, int *optimizedp
,
1638 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1639 int *realnump
, void *valuep
)
1641 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1643 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1644 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1647 static const struct frame_unwind mips_mdebug_frame_unwind
=
1650 mips_mdebug_frame_this_id
,
1651 mips_mdebug_frame_prev_register
1654 static const struct frame_unwind
*
1655 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1657 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1658 CORE_ADDR startaddr
= 0;
1659 mips_extra_func_info_t proc_desc
;
1662 /* Only use the mdebug frame unwinder on mdebug frames where all the
1663 registers have been saved. Leave hard cases such as no mdebug or
1664 in prologue for the heuristic unwinders. */
1666 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1667 if (proc_desc
== NULL
)
1670 /* Not sure exactly what kernel_trap means, but if it means the
1671 kernel saves the registers without a prologue doing it, we better
1672 not examine the prologue to see whether registers have been saved
1674 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1676 return &mips_mdebug_frame_unwind
;
1678 /* In any frame other than the innermost or a frame interrupted by a
1679 signal, we assume that all registers have been saved. This
1680 assumes that all register saves in a function happen before the
1681 first function call. */
1682 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1683 return &mips_mdebug_frame_unwind
;
1689 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1692 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1697 static const struct frame_base mips_mdebug_frame_base
= {
1698 &mips_mdebug_frame_unwind
,
1699 mips_mdebug_frame_base_address
,
1700 mips_mdebug_frame_base_address
,
1701 mips_mdebug_frame_base_address
1704 static const struct frame_base
*
1705 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1707 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1708 return &mips_mdebug_frame_base
;
1713 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1714 Procedures that use the 32-bit instruction set are handled by the
1715 mips_insn32 unwinder. */
1717 static struct mips_frame_cache
*
1718 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1720 struct mips_frame_cache
*cache
;
1722 if ((*this_cache
) != NULL
)
1723 return (*this_cache
);
1724 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1725 (*this_cache
) = cache
;
1726 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1728 /* Analyze the function prologue. */
1730 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1731 CORE_ADDR start_addr
;
1733 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1734 if (start_addr
== 0)
1735 start_addr
= heuristic_proc_start (pc
);
1736 /* We can't analyze the prologue if we couldn't find the begining
1738 if (start_addr
== 0)
1741 heuristic_proc_desc (start_addr
, pc
, next_frame
, *this_cache
);
1744 /* SP_REGNUM, contains the value and not the address. */
1745 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1747 return (*this_cache
);
1751 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1752 struct frame_id
*this_id
)
1754 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1756 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1760 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1762 int regnum
, int *optimizedp
,
1763 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1764 int *realnump
, void *valuep
)
1766 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1768 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1769 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1772 static const struct frame_unwind mips_insn16_frame_unwind
=
1775 mips_insn16_frame_this_id
,
1776 mips_insn16_frame_prev_register
1779 static const struct frame_unwind
*
1780 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1782 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1783 if (pc_is_mips16 (pc
))
1784 return &mips_insn16_frame_unwind
;
1789 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1792 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1797 static const struct frame_base mips_insn16_frame_base
=
1799 &mips_insn16_frame_unwind
,
1800 mips_insn16_frame_base_address
,
1801 mips_insn16_frame_base_address
,
1802 mips_insn16_frame_base_address
1805 static const struct frame_base
*
1806 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1808 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1809 return &mips_insn16_frame_base
;
1814 /* Heuristic unwinder for procedures using 32-bit instructions (covers
1815 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
1816 instructions (a.k.a. MIPS16) are handled by the mips_insn16
1819 static struct mips_frame_cache
*
1820 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1822 struct mips_frame_cache
*cache
;
1824 if ((*this_cache
) != NULL
)
1825 return (*this_cache
);
1827 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1828 (*this_cache
) = cache
;
1829 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1831 /* Analyze the function prologue. */
1833 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1834 CORE_ADDR start_addr
;
1836 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1837 if (start_addr
== 0)
1838 start_addr
= heuristic_proc_start (pc
);
1839 /* We can't analyze the prologue if we couldn't find the begining
1841 if (start_addr
== 0)
1844 heuristic_proc_desc (start_addr
, pc
, next_frame
, *this_cache
);
1847 /* SP_REGNUM, contains the value and not the address. */
1848 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1850 return (*this_cache
);
1854 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1855 struct frame_id
*this_id
)
1857 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1859 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1863 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
1865 int regnum
, int *optimizedp
,
1866 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1867 int *realnump
, void *valuep
)
1869 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1871 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1872 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1875 static const struct frame_unwind mips_insn32_frame_unwind
=
1878 mips_insn32_frame_this_id
,
1879 mips_insn32_frame_prev_register
1882 static const struct frame_unwind
*
1883 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
1885 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1886 if (! pc_is_mips16 (pc
))
1887 return &mips_insn32_frame_unwind
;
1892 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
1895 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1900 static const struct frame_base mips_insn32_frame_base
=
1902 &mips_insn32_frame_unwind
,
1903 mips_insn32_frame_base_address
,
1904 mips_insn32_frame_base_address
,
1905 mips_insn32_frame_base_address
1908 static const struct frame_base
*
1909 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
1911 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
1912 return &mips_insn32_frame_base
;
1917 static struct trad_frame_cache
*
1918 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1921 CORE_ADDR start_addr
;
1922 CORE_ADDR stack_addr
;
1923 struct trad_frame_cache
*this_trad_cache
;
1925 if ((*this_cache
) != NULL
)
1926 return (*this_cache
);
1927 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
1928 (*this_cache
) = this_trad_cache
;
1930 /* The return address is in the link register. */
1931 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, RA_REGNUM
);
1933 /* Frame ID, since it's a frameless / stackless function, no stack
1934 space is allocated and SP on entry is the current SP. */
1935 pc
= frame_pc_unwind (next_frame
);
1936 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1937 stack_addr
= frame_unwind_register_signed (next_frame
, SP_REGNUM
);
1938 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
1940 /* Assume that the frame's base is the same as the
1942 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
1944 return this_trad_cache
;
1948 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1949 struct frame_id
*this_id
)
1951 struct trad_frame_cache
*this_trad_cache
1952 = mips_stub_frame_cache (next_frame
, this_cache
);
1953 trad_frame_get_id (this_trad_cache
, this_id
);
1957 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
1959 int regnum
, int *optimizedp
,
1960 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1961 int *realnump
, void *valuep
)
1963 struct trad_frame_cache
*this_trad_cache
1964 = mips_stub_frame_cache (next_frame
, this_cache
);
1965 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
1966 lvalp
, addrp
, realnump
, valuep
);
1969 static const struct frame_unwind mips_stub_frame_unwind
=
1972 mips_stub_frame_this_id
,
1973 mips_stub_frame_prev_register
1976 static const struct frame_unwind
*
1977 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
1979 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1980 if (in_plt_section (pc
, NULL
))
1981 return &mips_stub_frame_unwind
;
1987 mips_stub_frame_base_address (struct frame_info
*next_frame
,
1990 struct trad_frame_cache
*this_trad_cache
1991 = mips_stub_frame_cache (next_frame
, this_cache
);
1992 return trad_frame_get_this_base (this_trad_cache
);
1995 static const struct frame_base mips_stub_frame_base
=
1997 &mips_stub_frame_unwind
,
1998 mips_stub_frame_base_address
,
1999 mips_stub_frame_base_address
,
2000 mips_stub_frame_base_address
2003 static const struct frame_base
*
2004 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2006 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2007 return &mips_stub_frame_base
;
2013 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2015 /* Always a pseudo. */
2016 gdb_assert (regno
>= NUM_REGS
);
2020 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2024 return frame_unwind_register_signed (fi
, regno
);
2028 /* mips_addr_bits_remove - remove useless address bits */
2031 mips_addr_bits_remove (CORE_ADDR addr
)
2033 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2034 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2035 /* This hack is a work-around for existing boards using PMON, the
2036 simulator, and any other 64-bit targets that doesn't have true
2037 64-bit addressing. On these targets, the upper 32 bits of
2038 addresses are ignored by the hardware. Thus, the PC or SP are
2039 likely to have been sign extended to all 1s by instruction
2040 sequences that load 32-bit addresses. For example, a typical
2041 piece of code that loads an address is this:
2043 lui $r2, <upper 16 bits>
2044 ori $r2, <lower 16 bits>
2046 But the lui sign-extends the value such that the upper 32 bits
2047 may be all 1s. The workaround is simply to mask off these
2048 bits. In the future, gcc may be changed to support true 64-bit
2049 addressing, and this masking will have to be disabled. */
2050 return addr
&= 0xffffffffUL
;
2055 /* mips_software_single_step() is called just before we want to resume
2056 the inferior, if we want to single-step it but there is no hardware
2057 or kernel single-step support (MIPS on GNU/Linux for example). We find
2058 the target of the coming instruction and breakpoint it.
2060 single_step is also called just after the inferior stops. If we had
2061 set up a simulated single-step, we undo our damage. */
2064 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2066 static CORE_ADDR next_pc
;
2067 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2068 static binsn_quantum break_mem
;
2071 if (insert_breakpoints_p
)
2073 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2074 next_pc
= mips_next_pc (pc
);
2076 target_insert_breakpoint (next_pc
, break_mem
);
2079 target_remove_breakpoint (next_pc
, break_mem
);
2082 static struct mips_extra_func_info temp_proc_desc
;
2084 /* Set a register's saved stack address in temp_saved_regs. If an
2085 address has already been set for this register, do nothing; this
2086 way we will only recognize the first save of a given register in a
2089 For simplicity, save the address in both [0 .. NUM_REGS) and
2090 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
2091 is used as it is only second range (the ABI instead of ISA
2092 registers) that comes into play when finding saved registers in a
2096 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
2099 if (this_cache
!= NULL
2100 && this_cache
->saved_regs
[regnum
].addr
== -1)
2102 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
2103 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
2108 /* Test whether the PC points to the return instruction at the
2109 end of a function. */
2112 mips_about_to_return (CORE_ADDR pc
)
2114 if (pc_is_mips16 (pc
))
2115 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2116 generates a "jr $ra"; other times it generates code to load
2117 the return address from the stack to an accessible register (such
2118 as $a3), then a "jr" using that register. This second case
2119 is almost impossible to distinguish from an indirect jump
2120 used for switch statements, so we don't even try. */
2121 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2123 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2127 /* This fencepost looks highly suspicious to me. Removing it also
2128 seems suspicious as it could affect remote debugging across serial
2132 heuristic_proc_start (CORE_ADDR pc
)
2139 pc
= ADDR_BITS_REMOVE (pc
);
2141 fence
= start_pc
- heuristic_fence_post
;
2145 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2146 fence
= VM_MIN_ADDRESS
;
2148 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
2150 /* search back for previous return */
2151 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2152 if (start_pc
< fence
)
2154 /* It's not clear to me why we reach this point when
2155 stop_soon, but with this test, at least we
2156 don't print out warnings for every child forked (eg, on
2157 decstation). 22apr93 rich@cygnus.com. */
2158 if (stop_soon
== NO_STOP_QUIETLY
)
2160 static int blurb_printed
= 0;
2162 warning ("GDB can't find the start of the function at 0x%s.",
2167 /* This actually happens frequently in embedded
2168 development, when you first connect to a board
2169 and your stack pointer and pc are nowhere in
2170 particular. This message needs to give people
2171 in that situation enough information to
2172 determine that it's no big deal. */
2173 printf_filtered ("\n\
2174 GDB is unable to find the start of the function at 0x%s\n\
2175 and thus can't determine the size of that function's stack frame.\n\
2176 This means that GDB may be unable to access that stack frame, or\n\
2177 the frames below it.\n\
2178 This problem is most likely caused by an invalid program counter or\n\
2180 However, if you think GDB should simply search farther back\n\
2181 from 0x%s for code which looks like the beginning of a\n\
2182 function, you can increase the range of the search using the `set\n\
2183 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2190 else if (pc_is_mips16 (start_pc
))
2192 unsigned short inst
;
2194 /* On MIPS16, any one of the following is likely to be the
2195 start of a function:
2199 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2200 inst
= mips_fetch_instruction (start_pc
);
2201 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2202 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2203 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2204 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2206 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2207 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2212 else if (mips_about_to_return (start_pc
))
2214 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2221 /* Fetch the immediate value from a MIPS16 instruction.
2222 If the previous instruction was an EXTEND, use it to extend
2223 the upper bits of the immediate value. This is a helper function
2224 for mips16_scan_prologue. */
2227 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2228 unsigned short inst
, /* current instruction */
2229 int nbits
, /* number of bits in imm field */
2230 int scale
, /* scale factor to be applied to imm */
2231 int is_signed
) /* is the imm field signed? */
2235 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2237 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2238 if (offset
& 0x8000) /* check for negative extend */
2239 offset
= 0 - (0x10000 - (offset
& 0xffff));
2240 return offset
| (inst
& 0x1f);
2244 int max_imm
= 1 << nbits
;
2245 int mask
= max_imm
- 1;
2246 int sign_bit
= max_imm
>> 1;
2248 offset
= inst
& mask
;
2249 if (is_signed
&& (offset
& sign_bit
))
2250 offset
= 0 - (max_imm
- offset
);
2251 return offset
* scale
;
2256 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2257 the associated FRAME_CACHE if not null. */
2260 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
, CORE_ADDR sp
,
2261 struct frame_info
*next_frame
,
2262 struct mips_frame_cache
*this_cache
)
2265 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2266 long frame_offset
= 0; /* Size of stack frame. */
2267 long frame_adjust
= 0; /* Offset of FP from SP. */
2268 int frame_reg
= MIPS_SP_REGNUM
;
2269 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2270 unsigned inst
= 0; /* current instruction */
2271 unsigned entry_inst
= 0; /* the entry instruction */
2274 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2276 /* Save the previous instruction. If it's an EXTEND, we'll extract
2277 the immediate offset extension from it in mips16_get_imm. */
2280 /* Fetch and decode the instruction. */
2281 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2282 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2283 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2285 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2286 if (offset
< 0) /* negative stack adjustment? */
2287 frame_offset
-= offset
;
2289 /* Exit loop if a positive stack adjustment is found, which
2290 usually means that the stack cleanup code in the function
2291 epilogue is reached. */
2294 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2296 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2297 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2298 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2300 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2302 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2303 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2304 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2306 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2308 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2309 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2311 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2313 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2314 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2316 else if (inst
== 0x673d) /* move $s1, $sp */
2321 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2323 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2324 frame_addr
= sp
+ offset
;
2326 frame_adjust
= offset
;
2328 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2330 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2331 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2332 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
2334 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2336 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2337 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2338 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
2340 else if ((inst
& 0xf81f) == 0xe809
2341 && (inst
& 0x700) != 0x700) /* entry */
2342 entry_inst
= inst
; /* save for later processing */
2343 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2344 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2347 /* The entry instruction is typically the first instruction in a function,
2348 and it stores registers at offsets relative to the value of the old SP
2349 (before the prologue). But the value of the sp parameter to this
2350 function is the new SP (after the prologue has been executed). So we
2351 can't calculate those offsets until we've seen the entire prologue,
2352 and can calculate what the old SP must have been. */
2353 if (entry_inst
!= 0)
2355 int areg_count
= (entry_inst
>> 8) & 7;
2356 int sreg_count
= (entry_inst
>> 6) & 3;
2358 /* The entry instruction always subtracts 32 from the SP. */
2361 /* Now we can calculate what the SP must have been at the
2362 start of the function prologue. */
2365 /* Check if a0-a3 were saved in the caller's argument save area. */
2366 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2368 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2369 offset
+= mips_abi_regsize (current_gdbarch
);
2372 /* Check if the ra register was pushed on the stack. */
2374 if (entry_inst
& 0x20)
2376 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2377 offset
-= mips_abi_regsize (current_gdbarch
);
2380 /* Check if the s0 and s1 registers were pushed on the stack. */
2381 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2383 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2384 offset
-= mips_abi_regsize (current_gdbarch
);
2388 if (this_cache
!= NULL
)
2391 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
2392 + frame_offset
- frame_adjust
);
2393 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2394 be able to get rid of the assignment below, evetually. But it's
2395 still needed for now. */
2396 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2397 = this_cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2401 /* Mark all the registers as unset in the saved_regs array
2402 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2405 reset_saved_regs (struct mips_frame_cache
*this_cache
)
2407 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2411 const int num_regs
= NUM_REGS
;
2414 for (i
= 0; i
< num_regs
; i
++)
2416 this_cache
->saved_regs
[i
].addr
= -1;
2421 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2422 the associated FRAME_CACHE if not null. */
2425 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
, CORE_ADDR sp
,
2426 struct frame_info
*next_frame
,
2427 struct mips_frame_cache
*this_cache
)
2430 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2432 int frame_reg
= MIPS_SP_REGNUM
;
2437 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2439 unsigned long inst
, high_word
, low_word
;
2442 /* Fetch the instruction. */
2443 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2445 /* Save some code by pre-extracting some useful fields. */
2446 high_word
= (inst
>> 16) & 0xffff;
2447 low_word
= inst
& 0xffff;
2448 reg
= high_word
& 0x1f;
2450 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2451 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2452 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2454 if (low_word
& 0x8000) /* negative stack adjustment? */
2455 frame_offset
+= 0x10000 - low_word
;
2457 /* Exit loop if a positive stack adjustment is found, which
2458 usually means that the stack cleanup code in the function
2459 epilogue is reached. */
2462 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2464 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2466 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2468 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and
2470 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2472 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2474 /* Old gcc frame, r30 is virtual frame pointer. */
2475 if ((long) low_word
!= frame_offset
)
2476 frame_addr
= sp
+ low_word
;
2477 else if (frame_reg
== MIPS_SP_REGNUM
)
2479 unsigned alloca_adjust
;
2482 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2483 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2484 if (alloca_adjust
> 0)
2486 /* FP > SP + frame_size. This may be because of
2487 an alloca or somethings similar. Fix sp to
2488 "pre-alloca" value, and try again. */
2489 sp
+= alloca_adjust
;
2490 /* Need to reset the status of all registers. Otherwise,
2491 we will hit a guard that prevents the new address
2492 for each register to be recomputed during the second
2494 reset_saved_regs (this_cache
);
2499 /* move $30,$sp. With different versions of gas this will be either
2500 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2501 Accept any one of these. */
2502 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2504 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2505 if (frame_reg
== MIPS_SP_REGNUM
)
2507 unsigned alloca_adjust
;
2510 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2511 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2512 if (alloca_adjust
> 0)
2514 /* FP > SP + frame_size. This may be because of
2515 an alloca or somethings similar. Fix sp to
2516 "pre-alloca" value, and try again. */
2518 /* Need to reset the status of all registers. Otherwise,
2519 we will hit a guard that prevents the new address
2520 for each register to be recomputed during the second
2522 reset_saved_regs (this_cache
);
2527 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2529 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
2533 if (this_cache
!= NULL
)
2536 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
2538 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2539 this assignment below, eventually. But it's still needed
2541 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2542 = this_cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2546 static mips_extra_func_info_t
2547 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2548 struct frame_info
*next_frame
,
2549 struct mips_frame_cache
*this_cache
)
2553 /* Can be called when there's no process, and hence when there's no
2555 if (next_frame
!= NULL
)
2556 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2562 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2563 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2564 PROC_FRAME_REG (&temp_proc_desc
) = MIPS_SP_REGNUM
;
2565 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2567 if (start_pc
+ 200 < limit_pc
)
2568 limit_pc
= start_pc
+ 200;
2569 if (pc_is_mips16 (start_pc
))
2570 mips16_scan_prologue (start_pc
, limit_pc
, sp
, next_frame
, this_cache
);
2572 mips32_scan_prologue (start_pc
, limit_pc
, sp
, next_frame
, this_cache
);
2573 return &temp_proc_desc
;
2576 struct mips_objfile_private
2582 /* Global used to communicate between non_heuristic_proc_desc and
2583 compare_pdr_entries within qsort (). */
2584 static bfd
*the_bfd
;
2587 compare_pdr_entries (const void *a
, const void *b
)
2589 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2590 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2594 else if (lhs
== rhs
)
2600 static mips_extra_func_info_t
2601 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2603 CORE_ADDR startaddr
;
2604 mips_extra_func_info_t proc_desc
;
2605 struct block
*b
= block_for_pc (pc
);
2607 struct obj_section
*sec
;
2608 struct mips_objfile_private
*priv
;
2610 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2612 *addrptr
= startaddr
;
2616 sec
= find_pc_section (pc
);
2619 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2621 /* Search the ".pdr" section generated by GAS. This includes most of
2622 the information normally found in ECOFF PDRs. */
2624 the_bfd
= sec
->objfile
->obfd
;
2626 && (the_bfd
->format
== bfd_object
2627 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2628 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2630 /* Right now GAS only outputs the address as a four-byte sequence.
2631 This means that we should not bother with this method on 64-bit
2632 targets (until that is fixed). */
2634 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2635 sizeof (struct mips_objfile_private
));
2637 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2639 else if (priv
== NULL
)
2643 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2644 sizeof (struct mips_objfile_private
));
2646 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2649 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2650 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2652 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2653 priv
->contents
, 0, priv
->size
);
2655 /* In general, the .pdr section is sorted. However, in the
2656 presence of multiple code sections (and other corner cases)
2657 it can become unsorted. Sort it so that we can use a faster
2659 qsort (priv
->contents
, priv
->size
/ 32, 32,
2660 compare_pdr_entries
);
2665 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2669 if (priv
->size
!= 0)
2676 high
= priv
->size
/ 32;
2678 /* We've found a .pdr section describing this objfile. We want to
2679 find the entry which describes this code address. The .pdr
2680 information is not very descriptive; we have only a function
2681 start address. We have to look for the closest entry, because
2682 the local symbol at the beginning of this function may have
2683 been stripped - so if we ask the symbol table for the start
2684 address we may get a preceding global function. */
2686 /* First, find the last .pdr entry starting at or before PC. */
2689 mid
= (low
+ high
) / 2;
2691 ptr
= priv
->contents
+ mid
* 32;
2692 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2693 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2694 SECT_OFF_TEXT (sec
->objfile
));
2701 while (low
!= high
);
2703 /* Both low and high point one past the PDR of interest. If
2704 both are zero, that means this PC is before any region
2705 covered by a PDR, i.e. pdr_pc for the first PDR entry is
2709 ptr
= priv
->contents
+ (low
- 1) * 32;
2710 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2711 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2712 SECT_OFF_TEXT (sec
->objfile
));
2715 /* We don't have a range, so we have no way to know for sure
2716 whether we're in the correct PDR or a PDR for a preceding
2717 function and the current function was a stripped local
2718 symbol. But if the PDR's PC is at least as great as the
2719 best guess from the symbol table, assume that it does cover
2720 the right area; if a .pdr section is present at all then
2721 nearly every function will have an entry. The biggest exception
2722 will be the dynamic linker stubs; conveniently these are
2723 placed before .text instead of after. */
2725 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
2727 struct symbol
*sym
= find_pc_function (pc
);
2732 /* Fill in what we need of the proc_desc. */
2733 proc_desc
= (mips_extra_func_info_t
)
2734 obstack_alloc (&sec
->objfile
->objfile_obstack
,
2735 sizeof (struct mips_extra_func_info
));
2736 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
2738 /* Only used for dummy frames. */
2739 PROC_HIGH_ADDR (proc_desc
) = 0;
2741 PROC_FRAME_OFFSET (proc_desc
)
2742 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2743 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2745 PROC_FRAME_ADJUST (proc_desc
) = 0;
2746 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2748 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2750 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2752 PROC_FREG_OFFSET (proc_desc
)
2753 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2754 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2756 proc_desc
->pdr
.isym
= (long) sym
;
2766 if (startaddr
> BLOCK_START (b
))
2768 /* This is the "pathological" case referred to in a comment in
2769 print_frame_info. It might be better to move this check into
2774 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2776 /* If we never found a PDR for this function in symbol reading, then
2777 examine prologues to find the information. */
2780 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2781 if (PROC_FRAME_REG (proc_desc
) == -1)
2790 /* MIPS stack frames are almost impenetrable. When execution stops,
2791 we basically have to look at symbol information for the function
2792 that we stopped in, which tells us *which* register (if any) is
2793 the base of the frame pointer, and what offset from that register
2794 the frame itself is at.
2796 This presents a problem when trying to examine a stack in memory
2797 (that isn't executing at the moment), using the "frame" command. We
2798 don't have a PC, nor do we have any registers except SP.
2800 This routine takes two arguments, SP and PC, and tries to make the
2801 cached frames look as if these two arguments defined a frame on the
2802 cache. This allows the rest of info frame to extract the important
2803 arguments without difficulty. */
2806 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2809 error ("MIPS frame specifications require two arguments: sp and pc");
2811 return create_new_frame (argv
[0], argv
[1]);
2814 /* According to the current ABI, should the type be passed in a
2815 floating-point register (assuming that there is space)? When there
2816 is no FPU, FP are not even considered as possibile candidates for
2817 FP registers and, consequently this returns false - forces FP
2818 arguments into integer registers. */
2821 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2823 return ((typecode
== TYPE_CODE_FLT
2825 && (typecode
== TYPE_CODE_STRUCT
2826 || typecode
== TYPE_CODE_UNION
)
2827 && TYPE_NFIELDS (arg_type
) == 1
2828 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2829 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2832 /* On o32, argument passing in GPRs depends on the alignment of the type being
2833 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2836 mips_type_needs_double_align (struct type
*type
)
2838 enum type_code typecode
= TYPE_CODE (type
);
2840 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2842 else if (typecode
== TYPE_CODE_STRUCT
)
2844 if (TYPE_NFIELDS (type
) < 1)
2846 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2848 else if (typecode
== TYPE_CODE_UNION
)
2852 n
= TYPE_NFIELDS (type
);
2853 for (i
= 0; i
< n
; i
++)
2854 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2861 /* Adjust the address downward (direction of stack growth) so that it
2862 is correctly aligned for a new stack frame. */
2864 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2866 return align_down (addr
, 16);
2869 /* Determine how a return value is stored within the MIPS register
2870 file, given the return type `valtype'. */
2872 struct return_value_word
2881 return_value_location (struct type
*valtype
,
2882 struct return_value_word
*hi
,
2883 struct return_value_word
*lo
)
2885 int len
= TYPE_LENGTH (valtype
);
2886 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2888 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2889 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2890 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2892 if (mips_abi_regsize (current_gdbarch
) < 8 && len
== 8)
2894 /* We need to break a 64bit float in two 32 bit halves and
2895 spread them across a floating-point register pair. */
2896 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2897 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
2898 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2899 && register_size (current_gdbarch
,
2900 mips_regnum (current_gdbarch
)->
2901 fp0
) == 8) ? 4 : 0);
2902 hi
->reg_offset
= lo
->reg_offset
;
2903 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
2904 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
2910 /* The floating point value fits in a single floating-point
2912 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2913 && register_size (current_gdbarch
,
2914 mips_regnum (current_gdbarch
)->
2916 && len
== 4) ? 4 : 0);
2917 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
2928 /* Locate a result possibly spread across two registers. */
2930 lo
->reg
= regnum
+ 0;
2931 hi
->reg
= regnum
+ 1;
2932 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2933 && len
< mips_abi_regsize (current_gdbarch
))
2935 /* "un-left-justify" the value in the low register */
2936 lo
->reg_offset
= mips_abi_regsize (current_gdbarch
) - len
;
2941 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (current_gdbarch
) /* odd-size structs */
2942 && len
< mips_abi_regsize (current_gdbarch
) * 2
2943 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2944 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2946 /* "un-left-justify" the value spread across two registers. */
2947 lo
->reg_offset
= 2 * mips_abi_regsize (current_gdbarch
) - len
;
2948 lo
->len
= mips_abi_regsize (current_gdbarch
) - lo
->reg_offset
;
2950 hi
->len
= len
- lo
->len
;
2954 /* Only perform a partial copy of the second register. */
2957 if (len
> mips_abi_regsize (current_gdbarch
))
2959 lo
->len
= mips_abi_regsize (current_gdbarch
);
2960 hi
->len
= len
- mips_abi_regsize (current_gdbarch
);
2968 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2969 && register_size (current_gdbarch
, regnum
) == 8
2970 && mips_abi_regsize (current_gdbarch
) == 4)
2972 /* Account for the fact that only the least-signficant part
2973 of the register is being used */
2974 lo
->reg_offset
+= 4;
2975 hi
->reg_offset
+= 4;
2978 hi
->buf_offset
= lo
->len
;
2982 /* Should call_function allocate stack space for a struct return? */
2985 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
2987 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2988 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (current_gdbarch
));
2991 /* Should call_function pass struct by reference?
2992 For each architecture, structs are passed either by
2993 value or by reference, depending on their size. */
2996 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
2998 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
2999 int len
= TYPE_LENGTH (check_typedef (type
));
3000 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3002 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
3003 return (len
> mips_abi_regsize (current_gdbarch
));
3009 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3010 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3011 int nargs
, struct value
**args
, CORE_ADDR sp
,
3012 int struct_return
, CORE_ADDR struct_addr
)
3018 int stack_offset
= 0;
3019 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3020 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3022 /* For shared libraries, "t9" needs to point at the function
3024 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3026 /* Set the return address register to point to the entry point of
3027 the program, where a breakpoint lies in wait. */
3028 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3030 /* First ensure that the stack and structure return address (if any)
3031 are properly aligned. The stack has to be at least 64-bit
3032 aligned even on 32-bit machines, because doubles must be 64-bit
3033 aligned. For n32 and n64, stack frames need to be 128-bit
3034 aligned, so we round to this widest known alignment. */
3036 sp
= align_down (sp
, 16);
3037 struct_addr
= align_down (struct_addr
, 16);
3039 /* Now make space on the stack for the args. We allocate more
3040 than necessary for EABI, because the first few arguments are
3041 passed in registers, but that's OK. */
3042 for (argnum
= 0; argnum
< nargs
; argnum
++)
3043 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3044 mips_stack_argsize (gdbarch
));
3045 sp
-= align_up (len
, 16);
3048 fprintf_unfiltered (gdb_stdlog
,
3049 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
3050 paddr_nz (sp
), (long) align_up (len
, 16));
3052 /* Initialize the integer and float register pointers. */
3054 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3056 /* The struct_return pointer occupies the first parameter-passing reg. */
3060 fprintf_unfiltered (gdb_stdlog
,
3061 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
3062 argreg
, paddr_nz (struct_addr
));
3063 write_register (argreg
++, struct_addr
);
3066 /* Now load as many as possible of the first arguments into
3067 registers, and push the rest onto the stack. Loop thru args
3068 from first to last. */
3069 for (argnum
= 0; argnum
< nargs
; argnum
++)
3072 char valbuf
[MAX_REGISTER_SIZE
];
3073 struct value
*arg
= args
[argnum
];
3074 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3075 int len
= TYPE_LENGTH (arg_type
);
3076 enum type_code typecode
= TYPE_CODE (arg_type
);
3079 fprintf_unfiltered (gdb_stdlog
,
3080 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3081 argnum
+ 1, len
, (int) typecode
);
3083 /* The EABI passes structures that do not fit in a register by
3085 if (len
> mips_abi_regsize (gdbarch
)
3086 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3088 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
3089 VALUE_ADDRESS (arg
));
3090 typecode
= TYPE_CODE_PTR
;
3091 len
= mips_abi_regsize (gdbarch
);
3094 fprintf_unfiltered (gdb_stdlog
, " push");
3097 val
= (char *) VALUE_CONTENTS (arg
);
3099 /* 32-bit ABIs always start floating point arguments in an
3100 even-numbered floating point register. Round the FP register
3101 up before the check to see if there are any FP registers
3102 left. Non MIPS_EABI targets also pass the FP in the integer
3103 registers so also round up normal registers. */
3104 if (mips_abi_regsize (gdbarch
) < 8
3105 && fp_register_arg_p (typecode
, arg_type
))
3107 if ((float_argreg
& 1))
3111 /* Floating point arguments passed in registers have to be
3112 treated specially. On 32-bit architectures, doubles
3113 are passed in register pairs; the even register gets
3114 the low word, and the odd register gets the high word.
3115 On non-EABI processors, the first two floating point arguments are
3116 also copied to general registers, because MIPS16 functions
3117 don't use float registers for arguments. This duplication of
3118 arguments in general registers can't hurt non-MIPS16 functions
3119 because those registers are normally skipped. */
3120 /* MIPS_EABI squeezes a struct that contains a single floating
3121 point value into an FP register instead of pushing it onto the
3123 if (fp_register_arg_p (typecode
, arg_type
)
3124 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3126 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3128 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3129 unsigned long regval
;
3131 /* Write the low word of the double to the even register(s). */
3132 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3134 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3135 float_argreg
, phex (regval
, 4));
3136 write_register (float_argreg
++, regval
);
3138 /* Write the high word of the double to the odd register(s). */
3139 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3141 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3142 float_argreg
, phex (regval
, 4));
3143 write_register (float_argreg
++, regval
);
3147 /* This is a floating point value that fits entirely
3148 in a single register. */
3149 /* On 32 bit ABI's the float_argreg is further adjusted
3150 above to ensure that it is even register aligned. */
3151 LONGEST regval
= extract_unsigned_integer (val
, len
);
3153 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3154 float_argreg
, phex (regval
, len
));
3155 write_register (float_argreg
++, regval
);
3160 /* Copy the argument to general registers or the stack in
3161 register-sized pieces. Large arguments are split between
3162 registers and stack. */
3163 /* Note: structs whose size is not a multiple of
3164 mips_abi_regsize() are treated specially: Irix cc passes
3165 them in registers where gcc sometimes puts them on the
3166 stack. For maximum compatibility, we will put them in
3168 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3169 && (len
% mips_abi_regsize (gdbarch
) != 0));
3171 /* Note: Floating-point values that didn't fit into an FP
3172 register are only written to memory. */
3175 /* Remember if the argument was written to the stack. */
3176 int stack_used_p
= 0;
3177 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3178 ? len
: mips_abi_regsize (gdbarch
));
3181 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3184 /* Write this portion of the argument to the stack. */
3185 if (argreg
> MIPS_LAST_ARG_REGNUM
3187 || fp_register_arg_p (typecode
, arg_type
))
3189 /* Should shorter than int integer values be
3190 promoted to int before being stored? */
3191 int longword_offset
= 0;
3194 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3196 if (mips_stack_argsize (gdbarch
) == 8
3197 && (typecode
== TYPE_CODE_INT
3198 || typecode
== TYPE_CODE_PTR
3199 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3200 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3201 else if ((typecode
== TYPE_CODE_STRUCT
3202 || typecode
== TYPE_CODE_UNION
)
3203 && (TYPE_LENGTH (arg_type
)
3204 < mips_stack_argsize (gdbarch
)))
3205 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3210 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3211 paddr_nz (stack_offset
));
3212 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3213 paddr_nz (longword_offset
));
3216 addr
= sp
+ stack_offset
+ longword_offset
;
3221 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3223 for (i
= 0; i
< partial_len
; i
++)
3225 fprintf_unfiltered (gdb_stdlog
, "%02x",
3229 write_memory (addr
, val
, partial_len
);
3232 /* Note!!! This is NOT an else clause. Odd sized
3233 structs may go thru BOTH paths. Floating point
3234 arguments will not. */
3235 /* Write this portion of the argument to a general
3236 purpose register. */
3237 if (argreg
<= MIPS_LAST_ARG_REGNUM
3238 && !fp_register_arg_p (typecode
, arg_type
))
3241 extract_unsigned_integer (val
, partial_len
);
3244 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3247 mips_abi_regsize (gdbarch
)));
3248 write_register (argreg
, regval
);
3255 /* Compute the the offset into the stack at which we
3256 will copy the next parameter.
3258 In the new EABI (and the NABI32), the stack_offset
3259 only needs to be adjusted when it has been used. */
3262 stack_offset
+= align_up (partial_len
,
3263 mips_stack_argsize (gdbarch
));
3267 fprintf_unfiltered (gdb_stdlog
, "\n");
3270 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3272 /* Return adjusted stack pointer. */
3276 /* Given a return value in `regbuf' with a type `valtype', extract and
3277 copy its value into `valbuf'. */
3280 mips_eabi_extract_return_value (struct type
*valtype
,
3281 char regbuf
[], char *valbuf
)
3283 struct return_value_word lo
;
3284 struct return_value_word hi
;
3285 return_value_location (valtype
, &hi
, &lo
);
3287 memcpy (valbuf
+ lo
.buf_offset
,
3288 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3289 lo
.reg_offset
, lo
.len
);
3292 memcpy (valbuf
+ hi
.buf_offset
,
3293 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3294 hi
.reg_offset
, hi
.len
);
3297 /* Given a return value in `valbuf' with a type `valtype', write it's
3298 value into the appropriate register. */
3301 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3303 char raw_buffer
[MAX_REGISTER_SIZE
];
3304 struct return_value_word lo
;
3305 struct return_value_word hi
;
3306 return_value_location (valtype
, &hi
, &lo
);
3308 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3309 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3310 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3311 raw_buffer
, register_size (current_gdbarch
,
3316 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3317 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3318 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3320 register_size (current_gdbarch
,
3325 /* N32/N64 ABI stuff. */
3328 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3329 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3330 int nargs
, struct value
**args
, CORE_ADDR sp
,
3331 int struct_return
, CORE_ADDR struct_addr
)
3337 int stack_offset
= 0;
3338 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3339 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3341 /* For shared libraries, "t9" needs to point at the function
3343 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3345 /* Set the return address register to point to the entry point of
3346 the program, where a breakpoint lies in wait. */
3347 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3349 /* First ensure that the stack and structure return address (if any)
3350 are properly aligned. The stack has to be at least 64-bit
3351 aligned even on 32-bit machines, because doubles must be 64-bit
3352 aligned. For n32 and n64, stack frames need to be 128-bit
3353 aligned, so we round to this widest known alignment. */
3355 sp
= align_down (sp
, 16);
3356 struct_addr
= align_down (struct_addr
, 16);
3358 /* Now make space on the stack for the args. */
3359 for (argnum
= 0; argnum
< nargs
; argnum
++)
3360 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3361 mips_stack_argsize (gdbarch
));
3362 sp
-= align_up (len
, 16);
3365 fprintf_unfiltered (gdb_stdlog
,
3366 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3367 paddr_nz (sp
), (long) align_up (len
, 16));
3369 /* Initialize the integer and float register pointers. */
3371 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3373 /* The struct_return pointer occupies the first parameter-passing reg. */
3377 fprintf_unfiltered (gdb_stdlog
,
3378 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3379 argreg
, paddr_nz (struct_addr
));
3380 write_register (argreg
++, struct_addr
);
3383 /* Now load as many as possible of the first arguments into
3384 registers, and push the rest onto the stack. Loop thru args
3385 from first to last. */
3386 for (argnum
= 0; argnum
< nargs
; argnum
++)
3389 struct value
*arg
= args
[argnum
];
3390 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3391 int len
= TYPE_LENGTH (arg_type
);
3392 enum type_code typecode
= TYPE_CODE (arg_type
);
3395 fprintf_unfiltered (gdb_stdlog
,
3396 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3397 argnum
+ 1, len
, (int) typecode
);
3399 val
= (char *) VALUE_CONTENTS (arg
);
3401 if (fp_register_arg_p (typecode
, arg_type
)
3402 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3404 /* This is a floating point value that fits entirely
3405 in a single register. */
3406 /* On 32 bit ABI's the float_argreg is further adjusted
3407 above to ensure that it is even register aligned. */
3408 LONGEST regval
= extract_unsigned_integer (val
, len
);
3410 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3411 float_argreg
, phex (regval
, len
));
3412 write_register (float_argreg
++, regval
);
3415 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3416 argreg
, phex (regval
, len
));
3417 write_register (argreg
, regval
);
3422 /* Copy the argument to general registers or the stack in
3423 register-sized pieces. Large arguments are split between
3424 registers and stack. */
3425 /* Note: structs whose size is not a multiple of
3426 mips_abi_regsize() are treated specially: Irix cc passes
3427 them in registers where gcc sometimes puts them on the
3428 stack. For maximum compatibility, we will put them in
3430 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3431 && (len
% mips_abi_regsize (gdbarch
) != 0));
3432 /* Note: Floating-point values that didn't fit into an FP
3433 register are only written to memory. */
3436 /* Rememer if the argument was written to the stack. */
3437 int stack_used_p
= 0;
3438 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3439 ? len
: mips_abi_regsize (gdbarch
));
3442 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3445 /* Write this portion of the argument to the stack. */
3446 if (argreg
> MIPS_LAST_ARG_REGNUM
3448 || fp_register_arg_p (typecode
, arg_type
))
3450 /* Should shorter than int integer values be
3451 promoted to int before being stored? */
3452 int longword_offset
= 0;
3455 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3457 if (mips_stack_argsize (gdbarch
) == 8
3458 && (typecode
== TYPE_CODE_INT
3459 || typecode
== TYPE_CODE_PTR
3460 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3461 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3466 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3467 paddr_nz (stack_offset
));
3468 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3469 paddr_nz (longword_offset
));
3472 addr
= sp
+ stack_offset
+ longword_offset
;
3477 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3479 for (i
= 0; i
< partial_len
; i
++)
3481 fprintf_unfiltered (gdb_stdlog
, "%02x",
3485 write_memory (addr
, val
, partial_len
);
3488 /* Note!!! This is NOT an else clause. Odd sized
3489 structs may go thru BOTH paths. Floating point
3490 arguments will not. */
3491 /* Write this portion of the argument to a general
3492 purpose register. */
3493 if (argreg
<= MIPS_LAST_ARG_REGNUM
3494 && !fp_register_arg_p (typecode
, arg_type
))
3497 extract_unsigned_integer (val
, partial_len
);
3499 /* A non-floating-point argument being passed in a
3500 general register. If a struct or union, and if
3501 the remaining length is smaller than the register
3502 size, we have to adjust the register value on
3505 It does not seem to be necessary to do the
3506 same for integral types.
3508 cagney/2001-07-23: gdb/179: Also, GCC, when
3509 outputting LE O32 with sizeof (struct) <
3510 mips_abi_regsize(), generates a left shift as
3511 part of storing the argument in a register a
3512 register (the left shift isn't generated when
3513 sizeof (struct) >= mips_abi_regsize()). Since
3514 it is quite possible that this is GCC
3515 contradicting the LE/O32 ABI, GDB has not been
3516 adjusted to accommodate this. Either someone
3517 needs to demonstrate that the LE/O32 ABI
3518 specifies such a left shift OR this new ABI gets
3519 identified as such and GDB gets tweaked
3522 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3523 && partial_len
< mips_abi_regsize (gdbarch
)
3524 && (typecode
== TYPE_CODE_STRUCT
||
3525 typecode
== TYPE_CODE_UNION
))
3526 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3530 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3533 mips_abi_regsize (gdbarch
)));
3534 write_register (argreg
, regval
);
3541 /* Compute the the offset into the stack at which we
3542 will copy the next parameter.
3544 In N32 (N64?), the stack_offset only needs to be
3545 adjusted when it has been used. */
3548 stack_offset
+= align_up (partial_len
,
3549 mips_stack_argsize (gdbarch
));
3553 fprintf_unfiltered (gdb_stdlog
, "\n");
3556 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3558 /* Return adjusted stack pointer. */
3562 static enum return_value_convention
3563 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3564 struct type
*type
, struct regcache
*regcache
,
3565 void *readbuf
, const void *writebuf
)
3567 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3568 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3569 || TYPE_CODE (type
) == TYPE_CODE_UNION
3570 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3571 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3572 return RETURN_VALUE_STRUCT_CONVENTION
;
3573 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3574 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3576 /* A floating-point value belongs in the least significant part
3579 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3580 mips_xfer_register (regcache
,
3581 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3583 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3584 return RETURN_VALUE_REGISTER_CONVENTION
;
3586 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3587 && TYPE_NFIELDS (type
) <= 2
3588 && TYPE_NFIELDS (type
) >= 1
3589 && ((TYPE_NFIELDS (type
) == 1
3590 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3592 || (TYPE_NFIELDS (type
) == 2
3593 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3595 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3597 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3599 /* A struct that contains one or two floats. Each value is part
3600 in the least significant part of their floating point
3604 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3605 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3607 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3610 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3612 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3613 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3614 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3616 return RETURN_VALUE_REGISTER_CONVENTION
;
3618 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3619 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3621 /* A structure or union. Extract the left justified value,
3622 regardless of the byte order. I.e. DO NOT USE
3626 for (offset
= 0, regnum
= V0_REGNUM
;
3627 offset
< TYPE_LENGTH (type
);
3628 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3630 int xfer
= register_size (current_gdbarch
, regnum
);
3631 if (offset
+ xfer
> TYPE_LENGTH (type
))
3632 xfer
= TYPE_LENGTH (type
) - offset
;
3634 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3635 offset
, xfer
, regnum
);
3636 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3637 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3639 return RETURN_VALUE_REGISTER_CONVENTION
;
3643 /* A scalar extract each part but least-significant-byte
3647 for (offset
= 0, regnum
= V0_REGNUM
;
3648 offset
< TYPE_LENGTH (type
);
3649 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3651 int xfer
= register_size (current_gdbarch
, regnum
);
3652 if (offset
+ xfer
> TYPE_LENGTH (type
))
3653 xfer
= TYPE_LENGTH (type
) - offset
;
3655 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3656 offset
, xfer
, regnum
);
3657 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3658 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3660 return RETURN_VALUE_REGISTER_CONVENTION
;
3664 /* O32 ABI stuff. */
3667 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3668 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3669 int nargs
, struct value
**args
, CORE_ADDR sp
,
3670 int struct_return
, CORE_ADDR struct_addr
)
3676 int stack_offset
= 0;
3677 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3678 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3680 /* For shared libraries, "t9" needs to point at the function
3682 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3684 /* Set the return address register to point to the entry point of
3685 the program, where a breakpoint lies in wait. */
3686 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3688 /* First ensure that the stack and structure return address (if any)
3689 are properly aligned. The stack has to be at least 64-bit
3690 aligned even on 32-bit machines, because doubles must be 64-bit
3691 aligned. For n32 and n64, stack frames need to be 128-bit
3692 aligned, so we round to this widest known alignment. */
3694 sp
= align_down (sp
, 16);
3695 struct_addr
= align_down (struct_addr
, 16);
3697 /* Now make space on the stack for the args. */
3698 for (argnum
= 0; argnum
< nargs
; argnum
++)
3699 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3700 mips_stack_argsize (gdbarch
));
3701 sp
-= align_up (len
, 16);
3704 fprintf_unfiltered (gdb_stdlog
,
3705 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3706 paddr_nz (sp
), (long) align_up (len
, 16));
3708 /* Initialize the integer and float register pointers. */
3710 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3712 /* The struct_return pointer occupies the first parameter-passing reg. */
3716 fprintf_unfiltered (gdb_stdlog
,
3717 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3718 argreg
, paddr_nz (struct_addr
));
3719 write_register (argreg
++, struct_addr
);
3720 stack_offset
+= mips_stack_argsize (gdbarch
);
3723 /* Now load as many as possible of the first arguments into
3724 registers, and push the rest onto the stack. Loop thru args
3725 from first to last. */
3726 for (argnum
= 0; argnum
< nargs
; argnum
++)
3729 struct value
*arg
= args
[argnum
];
3730 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3731 int len
= TYPE_LENGTH (arg_type
);
3732 enum type_code typecode
= TYPE_CODE (arg_type
);
3735 fprintf_unfiltered (gdb_stdlog
,
3736 "mips_o32_push_dummy_call: %d len=%d type=%d",
3737 argnum
+ 1, len
, (int) typecode
);
3739 val
= (char *) VALUE_CONTENTS (arg
);
3741 /* 32-bit ABIs always start floating point arguments in an
3742 even-numbered floating point register. Round the FP register
3743 up before the check to see if there are any FP registers
3744 left. O32/O64 targets also pass the FP in the integer
3745 registers so also round up normal registers. */
3746 if (mips_abi_regsize (gdbarch
) < 8
3747 && fp_register_arg_p (typecode
, arg_type
))
3749 if ((float_argreg
& 1))
3753 /* Floating point arguments passed in registers have to be
3754 treated specially. On 32-bit architectures, doubles
3755 are passed in register pairs; the even register gets
3756 the low word, and the odd register gets the high word.
3757 On O32/O64, the first two floating point arguments are
3758 also copied to general registers, because MIPS16 functions
3759 don't use float registers for arguments. This duplication of
3760 arguments in general registers can't hurt non-MIPS16 functions
3761 because those registers are normally skipped. */
3763 if (fp_register_arg_p (typecode
, arg_type
)
3764 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3766 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3768 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3769 unsigned long regval
;
3771 /* Write the low word of the double to the even register(s). */
3772 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3774 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3775 float_argreg
, phex (regval
, 4));
3776 write_register (float_argreg
++, regval
);
3778 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3779 argreg
, phex (regval
, 4));
3780 write_register (argreg
++, regval
);
3782 /* Write the high word of the double to the odd register(s). */
3783 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3785 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3786 float_argreg
, phex (regval
, 4));
3787 write_register (float_argreg
++, regval
);
3790 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3791 argreg
, phex (regval
, 4));
3792 write_register (argreg
++, regval
);
3796 /* This is a floating point value that fits entirely
3797 in a single register. */
3798 /* On 32 bit ABI's the float_argreg is further adjusted
3799 above to ensure that it is even register aligned. */
3800 LONGEST regval
= extract_unsigned_integer (val
, len
);
3802 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3803 float_argreg
, phex (regval
, len
));
3804 write_register (float_argreg
++, regval
);
3805 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3806 registers for each argument. The below is (my
3807 guess) to ensure that the corresponding integer
3808 register has reserved the same space. */
3810 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3811 argreg
, phex (regval
, len
));
3812 write_register (argreg
, regval
);
3813 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3815 /* Reserve space for the FP register. */
3816 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3820 /* Copy the argument to general registers or the stack in
3821 register-sized pieces. Large arguments are split between
3822 registers and stack. */
3823 /* Note: structs whose size is not a multiple of
3824 mips_abi_regsize() are treated specially: Irix cc passes
3825 them in registers where gcc sometimes puts them on the
3826 stack. For maximum compatibility, we will put them in
3828 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3829 && (len
% mips_abi_regsize (gdbarch
) != 0));
3830 /* Structures should be aligned to eight bytes (even arg registers)
3831 on MIPS_ABI_O32, if their first member has double precision. */
3832 if (mips_abi_regsize (gdbarch
) < 8
3833 && mips_type_needs_double_align (arg_type
))
3838 /* Note: Floating-point values that didn't fit into an FP
3839 register are only written to memory. */
3842 /* Remember if the argument was written to the stack. */
3843 int stack_used_p
= 0;
3844 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3845 ? len
: mips_abi_regsize (gdbarch
));
3848 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3851 /* Write this portion of the argument to the stack. */
3852 if (argreg
> MIPS_LAST_ARG_REGNUM
3854 || fp_register_arg_p (typecode
, arg_type
))
3856 /* Should shorter than int integer values be
3857 promoted to int before being stored? */
3858 int longword_offset
= 0;
3861 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3863 if (mips_stack_argsize (gdbarch
) == 8
3864 && (typecode
== TYPE_CODE_INT
3865 || typecode
== TYPE_CODE_PTR
3866 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3867 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3872 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3873 paddr_nz (stack_offset
));
3874 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3875 paddr_nz (longword_offset
));
3878 addr
= sp
+ stack_offset
+ longword_offset
;
3883 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3885 for (i
= 0; i
< partial_len
; i
++)
3887 fprintf_unfiltered (gdb_stdlog
, "%02x",
3891 write_memory (addr
, val
, partial_len
);
3894 /* Note!!! This is NOT an else clause. Odd sized
3895 structs may go thru BOTH paths. Floating point
3896 arguments will not. */
3897 /* Write this portion of the argument to a general
3898 purpose register. */
3899 if (argreg
<= MIPS_LAST_ARG_REGNUM
3900 && !fp_register_arg_p (typecode
, arg_type
))
3902 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3903 /* Value may need to be sign extended, because
3904 mips_isa_regsize() != mips_abi_regsize(). */
3906 /* A non-floating-point argument being passed in a
3907 general register. If a struct or union, and if
3908 the remaining length is smaller than the register
3909 size, we have to adjust the register value on
3912 It does not seem to be necessary to do the
3913 same for integral types.
3915 Also don't do this adjustment on O64 binaries.
3917 cagney/2001-07-23: gdb/179: Also, GCC, when
3918 outputting LE O32 with sizeof (struct) <
3919 mips_abi_regsize(), generates a left shift as
3920 part of storing the argument in a register a
3921 register (the left shift isn't generated when
3922 sizeof (struct) >= mips_abi_regsize()). Since
3923 it is quite possible that this is GCC
3924 contradicting the LE/O32 ABI, GDB has not been
3925 adjusted to accommodate this. Either someone
3926 needs to demonstrate that the LE/O32 ABI
3927 specifies such a left shift OR this new ABI gets
3928 identified as such and GDB gets tweaked
3931 if (mips_abi_regsize (gdbarch
) < 8
3932 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3933 && partial_len
< mips_abi_regsize (gdbarch
)
3934 && (typecode
== TYPE_CODE_STRUCT
||
3935 typecode
== TYPE_CODE_UNION
))
3936 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3940 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3943 mips_abi_regsize (gdbarch
)));
3944 write_register (argreg
, regval
);
3947 /* Prevent subsequent floating point arguments from
3948 being passed in floating point registers. */
3949 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3955 /* Compute the the offset into the stack at which we
3956 will copy the next parameter.
3958 In older ABIs, the caller reserved space for
3959 registers that contained arguments. This was loosely
3960 refered to as their "home". Consequently, space is
3961 always allocated. */
3963 stack_offset
+= align_up (partial_len
,
3964 mips_stack_argsize (gdbarch
));
3968 fprintf_unfiltered (gdb_stdlog
, "\n");
3971 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3973 /* Return adjusted stack pointer. */
3977 static enum return_value_convention
3978 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3979 struct regcache
*regcache
,
3980 void *readbuf
, const void *writebuf
)
3982 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3984 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3985 || TYPE_CODE (type
) == TYPE_CODE_UNION
3986 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3987 return RETURN_VALUE_STRUCT_CONVENTION
;
3988 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3989 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3991 /* A single-precision floating-point value. It fits in the
3992 least significant part of FP0. */
3994 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3995 mips_xfer_register (regcache
,
3996 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3998 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3999 return RETURN_VALUE_REGISTER_CONVENTION
;
4001 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4002 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4004 /* A double-precision floating-point value. The most
4005 significant part goes in FP1, and the least significant in
4008 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4009 switch (TARGET_BYTE_ORDER
)
4011 case BFD_ENDIAN_LITTLE
:
4012 mips_xfer_register (regcache
,
4013 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4014 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4015 mips_xfer_register (regcache
,
4016 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4017 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4019 case BFD_ENDIAN_BIG
:
4020 mips_xfer_register (regcache
,
4021 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4022 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4023 mips_xfer_register (regcache
,
4024 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4025 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4028 internal_error (__FILE__
, __LINE__
, "bad switch");
4030 return RETURN_VALUE_REGISTER_CONVENTION
;
4033 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4034 && TYPE_NFIELDS (type
) <= 2
4035 && TYPE_NFIELDS (type
) >= 1
4036 && ((TYPE_NFIELDS (type
) == 1
4037 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4039 || (TYPE_NFIELDS (type
) == 2
4040 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4042 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4044 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4046 /* A struct that contains one or two floats. Each value is part
4047 in the least significant part of their floating point
4049 bfd_byte reg
[MAX_REGISTER_SIZE
];
4052 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4053 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4055 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4058 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4060 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4061 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4062 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4064 return RETURN_VALUE_REGISTER_CONVENTION
;
4068 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4069 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4071 /* A structure or union. Extract the left justified value,
4072 regardless of the byte order. I.e. DO NOT USE
4076 for (offset
= 0, regnum
= V0_REGNUM
;
4077 offset
< TYPE_LENGTH (type
);
4078 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4080 int xfer
= register_size (current_gdbarch
, regnum
);
4081 if (offset
+ xfer
> TYPE_LENGTH (type
))
4082 xfer
= TYPE_LENGTH (type
) - offset
;
4084 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4085 offset
, xfer
, regnum
);
4086 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4087 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4089 return RETURN_VALUE_REGISTER_CONVENTION
;
4094 /* A scalar extract each part but least-significant-byte
4095 justified. o32 thinks registers are 4 byte, regardless of
4096 the ISA. mips_stack_argsize controls this. */
4099 for (offset
= 0, regnum
= V0_REGNUM
;
4100 offset
< TYPE_LENGTH (type
);
4101 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
4103 int xfer
= mips_stack_argsize (gdbarch
);
4104 if (offset
+ xfer
> TYPE_LENGTH (type
))
4105 xfer
= TYPE_LENGTH (type
) - offset
;
4107 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4108 offset
, xfer
, regnum
);
4109 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4110 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4112 return RETURN_VALUE_REGISTER_CONVENTION
;
4116 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4120 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4121 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4123 struct value
**args
, CORE_ADDR sp
,
4124 int struct_return
, CORE_ADDR struct_addr
)
4130 int stack_offset
= 0;
4131 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4132 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4134 /* For shared libraries, "t9" needs to point at the function
4136 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4138 /* Set the return address register to point to the entry point of
4139 the program, where a breakpoint lies in wait. */
4140 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4142 /* First ensure that the stack and structure return address (if any)
4143 are properly aligned. The stack has to be at least 64-bit
4144 aligned even on 32-bit machines, because doubles must be 64-bit
4145 aligned. For n32 and n64, stack frames need to be 128-bit
4146 aligned, so we round to this widest known alignment. */
4148 sp
= align_down (sp
, 16);
4149 struct_addr
= align_down (struct_addr
, 16);
4151 /* Now make space on the stack for the args. */
4152 for (argnum
= 0; argnum
< nargs
; argnum
++)
4153 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4154 mips_stack_argsize (gdbarch
));
4155 sp
-= align_up (len
, 16);
4158 fprintf_unfiltered (gdb_stdlog
,
4159 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4160 paddr_nz (sp
), (long) align_up (len
, 16));
4162 /* Initialize the integer and float register pointers. */
4164 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4166 /* The struct_return pointer occupies the first parameter-passing reg. */
4170 fprintf_unfiltered (gdb_stdlog
,
4171 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4172 argreg
, paddr_nz (struct_addr
));
4173 write_register (argreg
++, struct_addr
);
4174 stack_offset
+= mips_stack_argsize (gdbarch
);
4177 /* Now load as many as possible of the first arguments into
4178 registers, and push the rest onto the stack. Loop thru args
4179 from first to last. */
4180 for (argnum
= 0; argnum
< nargs
; argnum
++)
4183 struct value
*arg
= args
[argnum
];
4184 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4185 int len
= TYPE_LENGTH (arg_type
);
4186 enum type_code typecode
= TYPE_CODE (arg_type
);
4189 fprintf_unfiltered (gdb_stdlog
,
4190 "mips_o64_push_dummy_call: %d len=%d type=%d",
4191 argnum
+ 1, len
, (int) typecode
);
4193 val
= (char *) VALUE_CONTENTS (arg
);
4195 /* 32-bit ABIs always start floating point arguments in an
4196 even-numbered floating point register. Round the FP register
4197 up before the check to see if there are any FP registers
4198 left. O32/O64 targets also pass the FP in the integer
4199 registers so also round up normal registers. */
4200 if (mips_abi_regsize (gdbarch
) < 8
4201 && fp_register_arg_p (typecode
, arg_type
))
4203 if ((float_argreg
& 1))
4207 /* Floating point arguments passed in registers have to be
4208 treated specially. On 32-bit architectures, doubles
4209 are passed in register pairs; the even register gets
4210 the low word, and the odd register gets the high word.
4211 On O32/O64, the first two floating point arguments are
4212 also copied to general registers, because MIPS16 functions
4213 don't use float registers for arguments. This duplication of
4214 arguments in general registers can't hurt non-MIPS16 functions
4215 because those registers are normally skipped. */
4217 if (fp_register_arg_p (typecode
, arg_type
)
4218 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4220 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4222 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4223 unsigned long regval
;
4225 /* Write the low word of the double to the even register(s). */
4226 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4228 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4229 float_argreg
, phex (regval
, 4));
4230 write_register (float_argreg
++, regval
);
4232 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4233 argreg
, phex (regval
, 4));
4234 write_register (argreg
++, regval
);
4236 /* Write the high word of the double to the odd register(s). */
4237 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4239 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4240 float_argreg
, phex (regval
, 4));
4241 write_register (float_argreg
++, regval
);
4244 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4245 argreg
, phex (regval
, 4));
4246 write_register (argreg
++, regval
);
4250 /* This is a floating point value that fits entirely
4251 in a single register. */
4252 /* On 32 bit ABI's the float_argreg is further adjusted
4253 above to ensure that it is even register aligned. */
4254 LONGEST regval
= extract_unsigned_integer (val
, len
);
4256 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4257 float_argreg
, phex (regval
, len
));
4258 write_register (float_argreg
++, regval
);
4259 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4260 registers for each argument. The below is (my
4261 guess) to ensure that the corresponding integer
4262 register has reserved the same space. */
4264 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4265 argreg
, phex (regval
, len
));
4266 write_register (argreg
, regval
);
4267 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4269 /* Reserve space for the FP register. */
4270 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4274 /* Copy the argument to general registers or the stack in
4275 register-sized pieces. Large arguments are split between
4276 registers and stack. */
4277 /* Note: structs whose size is not a multiple of
4278 mips_abi_regsize() are treated specially: Irix cc passes
4279 them in registers where gcc sometimes puts them on the
4280 stack. For maximum compatibility, we will put them in
4282 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4283 && (len
% mips_abi_regsize (gdbarch
) != 0));
4284 /* Structures should be aligned to eight bytes (even arg registers)
4285 on MIPS_ABI_O32, if their first member has double precision. */
4286 if (mips_abi_regsize (gdbarch
) < 8
4287 && mips_type_needs_double_align (arg_type
))
4292 /* Note: Floating-point values that didn't fit into an FP
4293 register are only written to memory. */
4296 /* Remember if the argument was written to the stack. */
4297 int stack_used_p
= 0;
4298 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4299 ? len
: mips_abi_regsize (gdbarch
));
4302 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4305 /* Write this portion of the argument to the stack. */
4306 if (argreg
> MIPS_LAST_ARG_REGNUM
4308 || fp_register_arg_p (typecode
, arg_type
))
4310 /* Should shorter than int integer values be
4311 promoted to int before being stored? */
4312 int longword_offset
= 0;
4315 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4317 if (mips_stack_argsize (gdbarch
) == 8
4318 && (typecode
== TYPE_CODE_INT
4319 || typecode
== TYPE_CODE_PTR
4320 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4321 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4326 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4327 paddr_nz (stack_offset
));
4328 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4329 paddr_nz (longword_offset
));
4332 addr
= sp
+ stack_offset
+ longword_offset
;
4337 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4339 for (i
= 0; i
< partial_len
; i
++)
4341 fprintf_unfiltered (gdb_stdlog
, "%02x",
4345 write_memory (addr
, val
, partial_len
);
4348 /* Note!!! This is NOT an else clause. Odd sized
4349 structs may go thru BOTH paths. Floating point
4350 arguments will not. */
4351 /* Write this portion of the argument to a general
4352 purpose register. */
4353 if (argreg
<= MIPS_LAST_ARG_REGNUM
4354 && !fp_register_arg_p (typecode
, arg_type
))
4356 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4357 /* Value may need to be sign extended, because
4358 mips_isa_regsize() != mips_abi_regsize(). */
4360 /* A non-floating-point argument being passed in a
4361 general register. If a struct or union, and if
4362 the remaining length is smaller than the register
4363 size, we have to adjust the register value on
4366 It does not seem to be necessary to do the
4367 same for integral types.
4369 Also don't do this adjustment on O64 binaries.
4371 cagney/2001-07-23: gdb/179: Also, GCC, when
4372 outputting LE O32 with sizeof (struct) <
4373 mips_abi_regsize(), generates a left shift as
4374 part of storing the argument in a register a
4375 register (the left shift isn't generated when
4376 sizeof (struct) >= mips_abi_regsize()). Since
4377 it is quite possible that this is GCC
4378 contradicting the LE/O32 ABI, GDB has not been
4379 adjusted to accommodate this. Either someone
4380 needs to demonstrate that the LE/O32 ABI
4381 specifies such a left shift OR this new ABI gets
4382 identified as such and GDB gets tweaked
4385 if (mips_abi_regsize (gdbarch
) < 8
4386 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4387 && partial_len
< mips_abi_regsize (gdbarch
)
4388 && (typecode
== TYPE_CODE_STRUCT
||
4389 typecode
== TYPE_CODE_UNION
))
4390 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4394 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4397 mips_abi_regsize (gdbarch
)));
4398 write_register (argreg
, regval
);
4401 /* Prevent subsequent floating point arguments from
4402 being passed in floating point registers. */
4403 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4409 /* Compute the the offset into the stack at which we
4410 will copy the next parameter.
4412 In older ABIs, the caller reserved space for
4413 registers that contained arguments. This was loosely
4414 refered to as their "home". Consequently, space is
4415 always allocated. */
4417 stack_offset
+= align_up (partial_len
,
4418 mips_stack_argsize (gdbarch
));
4422 fprintf_unfiltered (gdb_stdlog
, "\n");
4425 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4427 /* Return adjusted stack pointer. */
4432 mips_o64_extract_return_value (struct type
*valtype
,
4433 char regbuf
[], char *valbuf
)
4435 struct return_value_word lo
;
4436 struct return_value_word hi
;
4437 return_value_location (valtype
, &hi
, &lo
);
4439 memcpy (valbuf
+ lo
.buf_offset
,
4440 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4441 lo
.reg_offset
, lo
.len
);
4444 memcpy (valbuf
+ hi
.buf_offset
,
4445 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4446 hi
.reg_offset
, hi
.len
);
4450 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4452 char raw_buffer
[MAX_REGISTER_SIZE
];
4453 struct return_value_word lo
;
4454 struct return_value_word hi
;
4455 return_value_location (valtype
, &hi
, &lo
);
4457 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4458 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4459 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4460 raw_buffer
, register_size (current_gdbarch
,
4465 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4466 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4467 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4469 register_size (current_gdbarch
,
4474 /* Floating point register management.
4476 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4477 64bit operations, these early MIPS cpus treat fp register pairs
4478 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4479 registers and offer a compatibility mode that emulates the MIPS2 fp
4480 model. When operating in MIPS2 fp compat mode, later cpu's split
4481 double precision floats into two 32-bit chunks and store them in
4482 consecutive fp regs. To display 64-bit floats stored in this
4483 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4484 Throw in user-configurable endianness and you have a real mess.
4486 The way this works is:
4487 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4488 double-precision value will be split across two logical registers.
4489 The lower-numbered logical register will hold the low-order bits,
4490 regardless of the processor's endianness.
4491 - If we are on a 64-bit processor, and we are looking for a
4492 single-precision value, it will be in the low ordered bits
4493 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4494 save slot in memory.
4495 - If we are in 64-bit mode, everything is straightforward.
4497 Note that this code only deals with "live" registers at the top of the
4498 stack. We will attempt to deal with saved registers later, when
4499 the raw/cooked register interface is in place. (We need a general
4500 interface that can deal with dynamic saved register sizes -- fp
4501 regs could be 32 bits wide in one frame and 64 on the frame above
4504 static struct type
*
4505 mips_float_register_type (void)
4507 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4508 return builtin_type_ieee_single_big
;
4510 return builtin_type_ieee_single_little
;
4513 static struct type
*
4514 mips_double_register_type (void)
4516 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4517 return builtin_type_ieee_double_big
;
4519 return builtin_type_ieee_double_little
;
4522 /* Copy a 32-bit single-precision value from the current frame
4523 into rare_buffer. */
4526 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4529 int raw_size
= register_size (current_gdbarch
, regno
);
4530 char *raw_buffer
= alloca (raw_size
);
4532 if (!frame_register_read (frame
, regno
, raw_buffer
))
4533 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4536 /* We have a 64-bit value for this register. Find the low-order
4540 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4545 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4549 memcpy (rare_buffer
, raw_buffer
, 4);
4553 /* Copy a 64-bit double-precision value from the current frame into
4554 rare_buffer. This may include getting half of it from the next
4558 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4561 int raw_size
= register_size (current_gdbarch
, regno
);
4563 if (raw_size
== 8 && !mips2_fp_compat ())
4565 /* We have a 64-bit value for this register, and we should use
4567 if (!frame_register_read (frame
, regno
, rare_buffer
))
4568 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4572 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4573 internal_error (__FILE__
, __LINE__
,
4574 "mips_read_fp_register_double: bad access to "
4575 "odd-numbered FP register");
4577 /* mips_read_fp_register_single will find the correct 32 bits from
4579 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4581 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4582 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4586 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4587 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4593 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4595 { /* do values for FP (float) regs */
4597 double doub
, flt1
; /* doubles extracted from raw hex data */
4601 (char *) alloca (2 *
4602 register_size (current_gdbarch
,
4603 mips_regnum (current_gdbarch
)->fp0
));
4605 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4606 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4609 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4611 /* 4-byte registers: Print hex and floating. Also print even
4612 numbered registers as doubles. */
4613 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4614 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4616 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4619 fprintf_filtered (file
, " flt: ");
4621 fprintf_filtered (file
, " <invalid float> ");
4623 fprintf_filtered (file
, "%-17.9g", flt1
);
4625 if (regnum
% 2 == 0)
4627 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4628 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4631 fprintf_filtered (file
, " dbl: ");
4633 fprintf_filtered (file
, "<invalid double>");
4635 fprintf_filtered (file
, "%-24.17g", doub
);
4640 /* Eight byte registers: print each one as hex, float and double. */
4641 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4642 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4644 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4645 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4648 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4651 fprintf_filtered (file
, " flt: ");
4653 fprintf_filtered (file
, "<invalid float>");
4655 fprintf_filtered (file
, "%-17.9g", flt1
);
4657 fprintf_filtered (file
, " dbl: ");
4659 fprintf_filtered (file
, "<invalid double>");
4661 fprintf_filtered (file
, "%-24.17g", doub
);
4666 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4667 int regnum
, int all
)
4669 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4670 char raw_buffer
[MAX_REGISTER_SIZE
];
4673 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4675 mips_print_fp_register (file
, frame
, regnum
);
4679 /* Get the data in raw format. */
4680 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4682 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4686 fputs_filtered (REGISTER_NAME (regnum
), file
);
4688 /* The problem with printing numeric register names (r26, etc.) is that
4689 the user can't use them on input. Probably the best solution is to
4690 fix it so that either the numeric or the funky (a2, etc.) names
4691 are accepted on input. */
4692 if (regnum
< MIPS_NUMREGS
)
4693 fprintf_filtered (file
, "(r%d): ", regnum
);
4695 fprintf_filtered (file
, ": ");
4697 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4699 register_size (current_gdbarch
,
4700 regnum
) - register_size (current_gdbarch
, regnum
);
4704 print_scalar_formatted (raw_buffer
+ offset
,
4705 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4709 /* Replacement for generic do_registers_info.
4710 Print regs in pretty columns. */
4713 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4716 fprintf_filtered (file
, " ");
4717 mips_print_fp_register (file
, frame
, regnum
);
4718 fprintf_filtered (file
, "\n");
4723 /* Print a row's worth of GP (int) registers, with name labels above */
4726 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4729 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4730 /* do values for GP (int) regs */
4731 char raw_buffer
[MAX_REGISTER_SIZE
];
4732 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4736 /* For GP registers, we print a separate row of names above the vals */
4737 fprintf_filtered (file
, " ");
4738 for (col
= 0, regnum
= start_regnum
;
4739 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4741 if (*REGISTER_NAME (regnum
) == '\0')
4742 continue; /* unused register */
4743 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4745 break; /* end the row: reached FP register */
4746 fprintf_filtered (file
,
4747 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4748 REGISTER_NAME (regnum
));
4751 /* print the R0 to R31 names */
4752 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4753 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4755 fprintf_filtered (file
, "\n ");
4757 /* now print the values in hex, 4 or 8 to the row */
4758 for (col
= 0, regnum
= start_regnum
;
4759 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4761 if (*REGISTER_NAME (regnum
) == '\0')
4762 continue; /* unused register */
4763 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4765 break; /* end row: reached FP register */
4766 /* OK: get the data in raw format. */
4767 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4768 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4769 /* pad small registers */
4771 byte
< (mips_abi_regsize (current_gdbarch
)
4772 - register_size (current_gdbarch
, regnum
)); byte
++)
4773 printf_filtered (" ");
4774 /* Now print the register value in hex, endian order. */
4775 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4777 register_size (current_gdbarch
,
4778 regnum
) - register_size (current_gdbarch
, regnum
);
4779 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4780 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4782 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4784 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4785 fprintf_filtered (file
, " ");
4788 if (col
> 0) /* ie. if we actually printed anything... */
4789 fprintf_filtered (file
, "\n");
4794 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4797 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4798 struct frame_info
*frame
, int regnum
, int all
)
4800 if (regnum
!= -1) /* do one specified register */
4802 gdb_assert (regnum
>= NUM_REGS
);
4803 if (*(REGISTER_NAME (regnum
)) == '\0')
4804 error ("Not a valid register for the current processor type");
4806 mips_print_register (file
, frame
, regnum
, 0);
4807 fprintf_filtered (file
, "\n");
4810 /* do all (or most) registers */
4813 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4815 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4818 if (all
) /* true for "INFO ALL-REGISTERS" command */
4819 regnum
= print_fp_register_row (file
, frame
, regnum
);
4821 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4824 regnum
= print_gp_register_row (file
, frame
, regnum
);
4829 /* Is this a branch with a delay slot? */
4831 static int is_delayed (unsigned long);
4834 is_delayed (unsigned long insn
)
4837 for (i
= 0; i
< NUMOPCODES
; ++i
)
4838 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4839 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4841 return (i
< NUMOPCODES
4842 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4843 | INSN_COND_BRANCH_DELAY
4844 | INSN_COND_BRANCH_LIKELY
)));
4848 mips_step_skips_delay (CORE_ADDR pc
)
4850 char buf
[MIPS_INSTLEN
];
4852 /* There is no branch delay slot on MIPS16. */
4853 if (pc_is_mips16 (pc
))
4856 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4857 /* If error reading memory, guess that it is not a delayed branch. */
4859 return is_delayed ((unsigned long)
4860 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4863 /* Skip the PC past function prologue instructions (32-bit version).
4864 This is a helper function for mips_skip_prologue. */
4867 mips32_skip_prologue (CORE_ADDR pc
)
4871 int seen_sp_adjust
= 0;
4872 int load_immediate_bytes
= 0;
4874 /* Find an upper bound on the prologue. */
4875 end_pc
= skip_prologue_using_sal (pc
);
4877 end_pc
= pc
+ 100; /* Magic. */
4879 /* Skip the typical prologue instructions. These are the stack adjustment
4880 instruction and the instructions that save registers on the stack
4881 or in the gcc frame. */
4882 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4884 unsigned long high_word
;
4886 inst
= mips_fetch_instruction (pc
);
4887 high_word
= (inst
>> 16) & 0xffff;
4889 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4890 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4892 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4893 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4895 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4896 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4897 && (inst
& 0x001F0000)) /* reg != $zero */
4900 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4902 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4904 continue; /* reg != $zero */
4906 /* move $s8,$sp. With different versions of gas this will be either
4907 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4908 Accept any one of these. */
4909 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4912 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4914 else if (high_word
== 0x3c1c) /* lui $gp,n */
4916 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4918 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4919 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4921 /* The following instructions load $at or $t0 with an immediate
4922 value in preparation for a stack adjustment via
4923 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4924 a local variable, so we accept them only before a stack adjustment
4925 instruction was seen. */
4926 else if (!seen_sp_adjust
)
4928 if (high_word
== 0x3c01 || /* lui $at,n */
4929 high_word
== 0x3c08) /* lui $t0,n */
4931 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4934 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4935 high_word
== 0x3508 || /* ori $t0,$t0,n */
4936 high_word
== 0x3401 || /* ori $at,$zero,n */
4937 high_word
== 0x3408) /* ori $t0,$zero,n */
4939 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4949 /* In a frameless function, we might have incorrectly
4950 skipped some load immediate instructions. Undo the skipping
4951 if the load immediate was not followed by a stack adjustment. */
4952 if (load_immediate_bytes
&& !seen_sp_adjust
)
4953 pc
-= load_immediate_bytes
;
4957 /* Skip the PC past function prologue instructions (16-bit version).
4958 This is a helper function for mips_skip_prologue. */
4961 mips16_skip_prologue (CORE_ADDR pc
)
4964 int extend_bytes
= 0;
4965 int prev_extend_bytes
;
4967 /* Table of instructions likely to be found in a function prologue. */
4970 unsigned short inst
;
4971 unsigned short mask
;
4977 , /* addiu $sp,offset */
4980 , /* daddiu $sp,offset */
4983 , /* sw reg,n($sp) */
4986 , /* sd reg,n($sp) */
4989 , /* sw $ra,n($sp) */
4992 , /* sd $ra,n($sp) */
4998 , /* sw $a0-$a3,n($s1) */
5001 , /* move reg,$a0-$a3 */
5004 , /* entry pseudo-op */
5007 , /* addiu $s1,$sp,n */
5009 0, 0} /* end of table marker */
5012 /* Find an upper bound on the prologue. */
5013 end_pc
= skip_prologue_using_sal (pc
);
5015 end_pc
= pc
+ 100; /* Magic. */
5017 /* Skip the typical prologue instructions. These are the stack adjustment
5018 instruction and the instructions that save registers on the stack
5019 or in the gcc frame. */
5020 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
5022 unsigned short inst
;
5025 inst
= mips_fetch_instruction (pc
);
5027 /* Normally we ignore an extend instruction. However, if it is
5028 not followed by a valid prologue instruction, we must adjust
5029 the pc back over the extend so that it won't be considered
5030 part of the prologue. */
5031 if ((inst
& 0xf800) == 0xf000) /* extend */
5033 extend_bytes
= MIPS16_INSTLEN
;
5036 prev_extend_bytes
= extend_bytes
;
5039 /* Check for other valid prologue instructions besides extend. */
5040 for (i
= 0; table
[i
].mask
!= 0; i
++)
5041 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
5043 if (table
[i
].mask
!= 0) /* it was in table? */
5044 continue; /* ignore it */
5048 /* Return the current pc, adjusted backwards by 2 if
5049 the previous instruction was an extend. */
5050 return pc
- prev_extend_bytes
;
5056 /* To skip prologues, I use this predicate. Returns either PC itself
5057 if the code at PC does not look like a function prologue; otherwise
5058 returns an address that (if we're lucky) follows the prologue. If
5059 LENIENT, then we must skip everything which is involved in setting
5060 up the frame (it's OK to skip more, just so long as we don't skip
5061 anything which might clobber the registers which are being saved.
5062 We must skip more in the case where part of the prologue is in the
5063 delay slot of a non-prologue instruction). */
5066 mips_skip_prologue (CORE_ADDR pc
)
5068 /* See if we can determine the end of the prologue via the symbol table.
5069 If so, then return either PC, or the PC after the prologue, whichever
5072 CORE_ADDR post_prologue_pc
= after_prologue (pc
);
5074 if (post_prologue_pc
!= 0)
5075 return max (pc
, post_prologue_pc
);
5077 /* Can't determine prologue from the symbol table, need to examine
5080 if (pc_is_mips16 (pc
))
5081 return mips16_skip_prologue (pc
);
5083 return mips32_skip_prologue (pc
);
5086 /* Root of all "set mips "/"show mips " commands. This will eventually be
5087 used for all MIPS-specific commands. */
5090 show_mips_command (char *args
, int from_tty
)
5092 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5096 set_mips_command (char *args
, int from_tty
)
5099 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5100 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5103 /* Commands to show/set the MIPS FPU type. */
5106 show_mipsfpu_command (char *args
, int from_tty
)
5109 switch (MIPS_FPU_TYPE
)
5111 case MIPS_FPU_SINGLE
:
5112 fpu
= "single-precision";
5114 case MIPS_FPU_DOUBLE
:
5115 fpu
= "double-precision";
5118 fpu
= "absent (none)";
5121 internal_error (__FILE__
, __LINE__
, "bad switch");
5123 if (mips_fpu_type_auto
)
5125 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5129 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5134 set_mipsfpu_command (char *args
, int from_tty
)
5137 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5138 show_mipsfpu_command (args
, from_tty
);
5142 set_mipsfpu_single_command (char *args
, int from_tty
)
5144 struct gdbarch_info info
;
5145 gdbarch_info_init (&info
);
5146 mips_fpu_type
= MIPS_FPU_SINGLE
;
5147 mips_fpu_type_auto
= 0;
5148 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5149 instead of relying on globals. Doing that would let generic code
5150 handle the search for this specific architecture. */
5151 if (!gdbarch_update_p (info
))
5152 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5156 set_mipsfpu_double_command (char *args
, int from_tty
)
5158 struct gdbarch_info info
;
5159 gdbarch_info_init (&info
);
5160 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5161 mips_fpu_type_auto
= 0;
5162 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5163 instead of relying on globals. Doing that would let generic code
5164 handle the search for this specific architecture. */
5165 if (!gdbarch_update_p (info
))
5166 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5170 set_mipsfpu_none_command (char *args
, int from_tty
)
5172 struct gdbarch_info info
;
5173 gdbarch_info_init (&info
);
5174 mips_fpu_type
= MIPS_FPU_NONE
;
5175 mips_fpu_type_auto
= 0;
5176 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5177 instead of relying on globals. Doing that would let generic code
5178 handle the search for this specific architecture. */
5179 if (!gdbarch_update_p (info
))
5180 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5184 set_mipsfpu_auto_command (char *args
, int from_tty
)
5186 mips_fpu_type_auto
= 1;
5189 /* Attempt to identify the particular processor model by reading the
5190 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5191 the relevant processor still exists (it dates back to '94) and
5192 secondly this is not the way to do this. The processor type should
5193 be set by forcing an architecture change. */
5196 deprecated_mips_set_processor_regs_hack (void)
5198 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5201 prid
= read_register (PRID_REGNUM
);
5203 if ((prid
& ~0xf) == 0x700)
5204 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5207 /* Just like reinit_frame_cache, but with the right arguments to be
5208 callable as an sfunc. */
5211 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5212 struct cmd_list_element
*c
)
5214 reinit_frame_cache ();
5218 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5220 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5221 mips_extra_func_info_t proc_desc
;
5223 /* Search for the function containing this address. Set the low bit
5224 of the address when searching, in case we were given an even address
5225 that is the start of a 16-bit function. If we didn't do this,
5226 the search would fail because the symbol table says the function
5227 starts at an odd address, i.e. 1 byte past the given address. */
5228 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5229 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5231 /* Make an attempt to determine if this is a 16-bit function. If
5232 the procedure descriptor exists and the address therein is odd,
5233 it's definitely a 16-bit function. Otherwise, we have to just
5234 guess that if the address passed in is odd, it's 16-bits. */
5235 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5236 disassembler needs to be able to locally determine the ISA, and
5237 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5241 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5242 info
->mach
= bfd_mach_mips16
;
5246 if (pc_is_mips16 (memaddr
))
5247 info
->mach
= bfd_mach_mips16
;
5250 /* Round down the instruction address to the appropriate boundary. */
5251 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5253 /* Set the disassembler options. */
5254 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5256 /* Set up the disassembler info, so that we get the right
5257 register names from libopcodes. */
5258 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5259 info
->disassembler_options
= "gpr-names=n32";
5261 info
->disassembler_options
= "gpr-names=64";
5262 info
->flavour
= bfd_target_elf_flavour
;
5265 /* This string is not recognized explicitly by the disassembler,
5266 but it tells the disassembler to not try to guess the ABI from
5267 the bfd elf headers, such that, if the user overrides the ABI
5268 of a program linked as NewABI, the disassembly will follow the
5269 register naming conventions specified by the user. */
5270 info
->disassembler_options
= "gpr-names=32";
5272 /* Call the appropriate disassembler based on the target endian-ness. */
5273 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5274 return print_insn_big_mips (memaddr
, info
);
5276 return print_insn_little_mips (memaddr
, info
);
5279 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5280 counter value to determine whether a 16- or 32-bit breakpoint should be
5281 used. It returns a pointer to a string of bytes that encode a breakpoint
5282 instruction, stores the length of the string to *lenptr, and adjusts pc
5283 (if necessary) to point to the actual memory location where the
5284 breakpoint should be inserted. */
5286 static const unsigned char *
5287 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5289 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5291 if (pc_is_mips16 (*pcptr
))
5293 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5294 *pcptr
= unmake_mips16_addr (*pcptr
);
5295 *lenptr
= sizeof (mips16_big_breakpoint
);
5296 return mips16_big_breakpoint
;
5300 /* The IDT board uses an unusual breakpoint value, and
5301 sometimes gets confused when it sees the usual MIPS
5302 breakpoint instruction. */
5303 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5304 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5305 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5307 *lenptr
= sizeof (big_breakpoint
);
5309 if (strcmp (target_shortname
, "mips") == 0)
5310 return idt_big_breakpoint
;
5311 else if (strcmp (target_shortname
, "ddb") == 0
5312 || strcmp (target_shortname
, "pmon") == 0
5313 || strcmp (target_shortname
, "lsi") == 0)
5314 return pmon_big_breakpoint
;
5316 return big_breakpoint
;
5321 if (pc_is_mips16 (*pcptr
))
5323 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5324 *pcptr
= unmake_mips16_addr (*pcptr
);
5325 *lenptr
= sizeof (mips16_little_breakpoint
);
5326 return mips16_little_breakpoint
;
5330 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5331 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5332 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5334 *lenptr
= sizeof (little_breakpoint
);
5336 if (strcmp (target_shortname
, "mips") == 0)
5337 return idt_little_breakpoint
;
5338 else if (strcmp (target_shortname
, "ddb") == 0
5339 || strcmp (target_shortname
, "pmon") == 0
5340 || strcmp (target_shortname
, "lsi") == 0)
5341 return pmon_little_breakpoint
;
5343 return little_breakpoint
;
5348 /* If PC is in a mips16 call or return stub, return the address of the target
5349 PC, which is either the callee or the caller. There are several
5350 cases which must be handled:
5352 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5353 target PC is in $31 ($ra).
5354 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5355 and the target PC is in $2.
5356 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5357 before the jal instruction, this is effectively a call stub
5358 and the the target PC is in $2. Otherwise this is effectively
5359 a return stub and the target PC is in $18.
5361 See the source code for the stubs in gcc/config/mips/mips16.S for
5364 This function implements the SKIP_TRAMPOLINE_CODE macro.
5368 mips_skip_stub (CORE_ADDR pc
)
5371 CORE_ADDR start_addr
;
5373 /* Find the starting address and name of the function containing the PC. */
5374 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5377 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5378 target PC is in $31 ($ra). */
5379 if (strcmp (name
, "__mips16_ret_sf") == 0
5380 || strcmp (name
, "__mips16_ret_df") == 0)
5381 return read_signed_register (RA_REGNUM
);
5383 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5385 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5386 and the target PC is in $2. */
5387 if (name
[19] >= '0' && name
[19] <= '9')
5388 return read_signed_register (2);
5390 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5391 before the jal instruction, this is effectively a call stub
5392 and the the target PC is in $2. Otherwise this is effectively
5393 a return stub and the target PC is in $18. */
5394 else if (name
[19] == 's' || name
[19] == 'd')
5396 if (pc
== start_addr
)
5398 /* Check if the target of the stub is a compiler-generated
5399 stub. Such a stub for a function bar might have a name
5400 like __fn_stub_bar, and might look like this:
5405 la $1,bar (becomes a lui/addiu pair)
5407 So scan down to the lui/addi and extract the target
5408 address from those two instructions. */
5410 CORE_ADDR target_pc
= read_signed_register (2);
5414 /* See if the name of the target function is __fn_stub_*. */
5415 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5418 if (strncmp (name
, "__fn_stub_", 10) != 0
5419 && strcmp (name
, "etext") != 0
5420 && strcmp (name
, "_etext") != 0)
5423 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5424 The limit on the search is arbitrarily set to 20
5425 instructions. FIXME. */
5426 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5428 inst
= mips_fetch_instruction (target_pc
);
5429 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5430 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5431 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5432 return pc
| (inst
& 0xffff); /* low word */
5435 /* Couldn't find the lui/addui pair, so return stub address. */
5439 /* This is the 'return' part of a call stub. The return
5440 address is in $r18. */
5441 return read_signed_register (18);
5444 return 0; /* not a stub */
5448 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5449 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5452 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5454 CORE_ADDR start_addr
;
5456 /* Find the starting address of the function containing the PC. If the
5457 caller didn't give us a name, look it up at the same time. */
5458 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5462 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5464 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5465 if (name
[19] >= '0' && name
[19] <= '9')
5467 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5468 before the jal instruction, this is effectively a call stub. */
5469 else if (name
[19] == 's' || name
[19] == 'd')
5470 return pc
== start_addr
;
5473 return 0; /* not a stub */
5477 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5478 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5481 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5483 CORE_ADDR start_addr
;
5485 /* Find the starting address of the function containing the PC. */
5486 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5489 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5490 if (strcmp (name
, "__mips16_ret_sf") == 0
5491 || strcmp (name
, "__mips16_ret_df") == 0)
5494 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5495 i.e. after the jal instruction, this is effectively a return stub. */
5496 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5497 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5500 return 0; /* not a stub */
5504 /* Return non-zero if the PC is in a library helper function that
5505 should be ignored. This implements the
5506 DEPRECATED_IGNORE_HELPER_CALL macro. */
5509 mips_ignore_helper (CORE_ADDR pc
)
5513 /* Find the starting address and name of the function containing the PC. */
5514 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5517 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5518 that we want to ignore. */
5519 return (strcmp (name
, "__mips16_ret_sf") == 0
5520 || strcmp (name
, "__mips16_ret_df") == 0);
5524 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5525 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5528 mips_stab_reg_to_regnum (int num
)
5531 if (num
>= 0 && num
< 32)
5533 else if (num
>= 38 && num
< 70)
5534 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5536 regnum
= mips_regnum (current_gdbarch
)->hi
;
5538 regnum
= mips_regnum (current_gdbarch
)->lo
;
5540 /* This will hopefully (eventually) provoke a warning. Should
5541 we be calling complaint() here? */
5542 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5543 return NUM_REGS
+ regnum
;
5547 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5548 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5551 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5554 if (num
>= 0 && num
< 32)
5556 else if (num
>= 32 && num
< 64)
5557 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5559 regnum
= mips_regnum (current_gdbarch
)->hi
;
5561 regnum
= mips_regnum (current_gdbarch
)->lo
;
5563 /* This will hopefully (eventually) provoke a warning. Should we
5564 be calling complaint() here? */
5565 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5566 return NUM_REGS
+ regnum
;
5570 mips_register_sim_regno (int regnum
)
5572 /* Only makes sense to supply raw registers. */
5573 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5574 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5575 decide if it is valid. Should instead define a standard sim/gdb
5576 register numbering scheme. */
5577 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5578 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5581 return LEGACY_SIM_REGNO_IGNORE
;
5585 /* Convert an integer into an address. By first converting the value
5586 into a pointer and then extracting it signed, the address is
5587 guarenteed to be correctly sign extended. */
5590 mips_integer_to_address (struct type
*type
, void *buf
)
5592 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5593 LONGEST val
= unpack_long (type
, buf
);
5594 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5595 return extract_signed_integer (tmp
,
5596 TYPE_LENGTH (builtin_type_void_data_ptr
));
5600 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5602 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5603 const char *name
= bfd_get_section_name (abfd
, sect
);
5605 if (*abip
!= MIPS_ABI_UNKNOWN
)
5608 if (strncmp (name
, ".mdebug.", 8) != 0)
5611 if (strcmp (name
, ".mdebug.abi32") == 0)
5612 *abip
= MIPS_ABI_O32
;
5613 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5614 *abip
= MIPS_ABI_N32
;
5615 else if (strcmp (name
, ".mdebug.abi64") == 0)
5616 *abip
= MIPS_ABI_N64
;
5617 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5618 *abip
= MIPS_ABI_O64
;
5619 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5620 *abip
= MIPS_ABI_EABI32
;
5621 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5622 *abip
= MIPS_ABI_EABI64
;
5624 warning ("unsupported ABI %s.", name
+ 8);
5627 static enum mips_abi
5628 global_mips_abi (void)
5632 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5633 if (mips_abi_strings
[i
] == mips_abi_string
)
5634 return (enum mips_abi
) i
;
5636 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5639 static struct gdbarch
*
5640 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5642 struct gdbarch
*gdbarch
;
5643 struct gdbarch_tdep
*tdep
;
5645 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5647 enum mips_fpu_type fpu_type
;
5649 /* First of all, extract the elf_flags, if available. */
5650 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5651 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5652 else if (arches
!= NULL
)
5653 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5657 fprintf_unfiltered (gdb_stdlog
,
5658 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5660 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5661 switch ((elf_flags
& EF_MIPS_ABI
))
5663 case E_MIPS_ABI_O32
:
5664 found_abi
= MIPS_ABI_O32
;
5666 case E_MIPS_ABI_O64
:
5667 found_abi
= MIPS_ABI_O64
;
5669 case E_MIPS_ABI_EABI32
:
5670 found_abi
= MIPS_ABI_EABI32
;
5672 case E_MIPS_ABI_EABI64
:
5673 found_abi
= MIPS_ABI_EABI64
;
5676 if ((elf_flags
& EF_MIPS_ABI2
))
5677 found_abi
= MIPS_ABI_N32
;
5679 found_abi
= MIPS_ABI_UNKNOWN
;
5683 /* GCC creates a pseudo-section whose name describes the ABI. */
5684 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5685 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5687 /* If we have no useful BFD information, use the ABI from the last
5688 MIPS architecture (if there is one). */
5689 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5690 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5692 /* Try the architecture for any hint of the correct ABI. */
5693 if (found_abi
== MIPS_ABI_UNKNOWN
5694 && info
.bfd_arch_info
!= NULL
5695 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5697 switch (info
.bfd_arch_info
->mach
)
5699 case bfd_mach_mips3900
:
5700 found_abi
= MIPS_ABI_EABI32
;
5702 case bfd_mach_mips4100
:
5703 case bfd_mach_mips5000
:
5704 found_abi
= MIPS_ABI_EABI64
;
5706 case bfd_mach_mips8000
:
5707 case bfd_mach_mips10000
:
5708 /* On Irix, ELF64 executables use the N64 ABI. The
5709 pseudo-sections which describe the ABI aren't present
5710 on IRIX. (Even for executables created by gcc.) */
5711 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5712 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5713 found_abi
= MIPS_ABI_N64
;
5715 found_abi
= MIPS_ABI_N32
;
5721 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5724 /* What has the user specified from the command line? */
5725 wanted_abi
= global_mips_abi ();
5727 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5730 /* Now that we have found what the ABI for this binary would be,
5731 check whether the user is overriding it. */
5732 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5733 mips_abi
= wanted_abi
;
5734 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5735 mips_abi
= found_abi
;
5737 mips_abi
= MIPS_ABI_O32
;
5739 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5742 /* Also used when doing an architecture lookup. */
5744 fprintf_unfiltered (gdb_stdlog
,
5745 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5746 mips64_transfers_32bit_regs_p
);
5748 /* Determine the MIPS FPU type. */
5749 if (!mips_fpu_type_auto
)
5750 fpu_type
= mips_fpu_type
;
5751 else if (info
.bfd_arch_info
!= NULL
5752 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5753 switch (info
.bfd_arch_info
->mach
)
5755 case bfd_mach_mips3900
:
5756 case bfd_mach_mips4100
:
5757 case bfd_mach_mips4111
:
5758 case bfd_mach_mips4120
:
5759 fpu_type
= MIPS_FPU_NONE
;
5761 case bfd_mach_mips4650
:
5762 fpu_type
= MIPS_FPU_SINGLE
;
5765 fpu_type
= MIPS_FPU_DOUBLE
;
5768 else if (arches
!= NULL
)
5769 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5771 fpu_type
= MIPS_FPU_DOUBLE
;
5773 fprintf_unfiltered (gdb_stdlog
,
5774 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5776 /* try to find a pre-existing architecture */
5777 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5779 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5781 /* MIPS needs to be pedantic about which ABI the object is
5783 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5785 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5787 /* Need to be pedantic about which register virtual size is
5789 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5790 != mips64_transfers_32bit_regs_p
)
5792 /* Be pedantic about which FPU is selected. */
5793 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5795 return arches
->gdbarch
;
5798 /* Need a new architecture. Fill in a target specific vector. */
5799 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5800 gdbarch
= gdbarch_alloc (&info
, tdep
);
5801 tdep
->elf_flags
= elf_flags
;
5802 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5803 tdep
->found_abi
= found_abi
;
5804 tdep
->mips_abi
= mips_abi
;
5805 tdep
->mips_fpu_type
= fpu_type
;
5807 /* Initially set everything according to the default ABI/ISA. */
5808 set_gdbarch_short_bit (gdbarch
, 16);
5809 set_gdbarch_int_bit (gdbarch
, 32);
5810 set_gdbarch_float_bit (gdbarch
, 32);
5811 set_gdbarch_double_bit (gdbarch
, 64);
5812 set_gdbarch_long_double_bit (gdbarch
, 64);
5813 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5814 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5815 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5817 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5818 mips_elf_make_msymbol_special
);
5820 /* Fill in the OS dependant register numbers and names. */
5822 const char **reg_names
;
5823 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5824 struct mips_regnum
);
5825 if (info
.osabi
== GDB_OSABI_IRIX
)
5830 regnum
->badvaddr
= 66;
5833 regnum
->fp_control_status
= 69;
5834 regnum
->fp_implementation_revision
= 70;
5836 reg_names
= mips_irix_reg_names
;
5840 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5841 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5842 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5843 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5844 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5845 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5846 regnum
->fp_control_status
= 70;
5847 regnum
->fp_implementation_revision
= 71;
5849 if (info
.bfd_arch_info
!= NULL
5850 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5851 reg_names
= mips_tx39_reg_names
;
5853 reg_names
= mips_generic_reg_names
;
5855 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5856 replaced by read_pc? */
5857 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5858 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5859 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5860 set_gdbarch_num_regs (gdbarch
, num_regs
);
5861 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5862 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5863 tdep
->mips_processor_reg_names
= reg_names
;
5864 tdep
->regnum
= regnum
;
5870 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5871 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5872 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5873 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5874 tdep
->default_mask_address_p
= 0;
5875 set_gdbarch_long_bit (gdbarch
, 32);
5876 set_gdbarch_ptr_bit (gdbarch
, 32);
5877 set_gdbarch_long_long_bit (gdbarch
, 64);
5880 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5881 set_gdbarch_deprecated_store_return_value (gdbarch
,
5882 mips_o64_store_return_value
);
5883 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5884 mips_o64_extract_return_value
);
5885 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5886 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5887 tdep
->default_mask_address_p
= 0;
5888 set_gdbarch_long_bit (gdbarch
, 32);
5889 set_gdbarch_ptr_bit (gdbarch
, 32);
5890 set_gdbarch_long_long_bit (gdbarch
, 64);
5891 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
5893 case MIPS_ABI_EABI32
:
5894 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5895 set_gdbarch_deprecated_store_return_value (gdbarch
,
5896 mips_eabi_store_return_value
);
5897 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5898 mips_eabi_extract_return_value
);
5899 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5900 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5901 tdep
->default_mask_address_p
= 0;
5902 set_gdbarch_long_bit (gdbarch
, 32);
5903 set_gdbarch_ptr_bit (gdbarch
, 32);
5904 set_gdbarch_long_long_bit (gdbarch
, 64);
5905 set_gdbarch_deprecated_reg_struct_has_addr
5906 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5907 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
5909 case MIPS_ABI_EABI64
:
5910 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5911 set_gdbarch_deprecated_store_return_value (gdbarch
,
5912 mips_eabi_store_return_value
);
5913 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5914 mips_eabi_extract_return_value
);
5915 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5916 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5917 tdep
->default_mask_address_p
= 0;
5918 set_gdbarch_long_bit (gdbarch
, 64);
5919 set_gdbarch_ptr_bit (gdbarch
, 64);
5920 set_gdbarch_long_long_bit (gdbarch
, 64);
5921 set_gdbarch_deprecated_reg_struct_has_addr
5922 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5923 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
5926 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5927 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5928 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5929 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5930 tdep
->default_mask_address_p
= 0;
5931 set_gdbarch_long_bit (gdbarch
, 32);
5932 set_gdbarch_ptr_bit (gdbarch
, 32);
5933 set_gdbarch_long_long_bit (gdbarch
, 64);
5934 set_gdbarch_long_double_bit (gdbarch
, 128);
5935 set_gdbarch_long_double_format (gdbarch
,
5936 &floatformat_n32n64_long_double_big
);
5939 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5940 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5941 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5942 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5943 tdep
->default_mask_address_p
= 0;
5944 set_gdbarch_long_bit (gdbarch
, 64);
5945 set_gdbarch_ptr_bit (gdbarch
, 64);
5946 set_gdbarch_long_long_bit (gdbarch
, 64);
5947 set_gdbarch_long_double_bit (gdbarch
, 128);
5948 set_gdbarch_long_double_format (gdbarch
,
5949 &floatformat_n32n64_long_double_big
);
5952 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
5955 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5956 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5959 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5960 flag in object files because to do so would make it impossible to
5961 link with libraries compiled without "-gp32". This is
5962 unnecessarily restrictive.
5964 We could solve this problem by adding "-gp32" multilibs to gcc,
5965 but to set this flag before gcc is built with such multilibs will
5966 break too many systems.''
5968 But even more unhelpfully, the default linker output target for
5969 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5970 for 64-bit programs - you need to change the ABI to change this,
5971 and not all gcc targets support that currently. Therefore using
5972 this flag to detect 32-bit mode would do the wrong thing given
5973 the current gcc - it would make GDB treat these 64-bit programs
5974 as 32-bit programs by default. */
5976 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5977 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5978 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5980 /* Add/remove bits from an address. The MIPS needs be careful to
5981 ensure that all 32 bit addresses are sign extended to 64 bits. */
5982 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5984 /* Unwind the frame. */
5985 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5986 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5988 /* Map debug register numbers onto internal register numbers. */
5989 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5990 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5991 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5992 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5993 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5994 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5995 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5996 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5998 /* MIPS version of CALL_DUMMY */
6000 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6001 replaced by a command, and all targets will default to on stack
6002 (regardless of the stack's execute status). */
6003 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6004 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6006 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6007 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6008 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6010 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6011 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6013 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6015 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6016 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6017 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6019 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6021 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6023 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6025 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6026 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6027 need to all be folded into the target vector. Since they are
6028 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6029 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6031 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6033 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6035 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
6036 to support MIPS16. This is a bad thing. Make sure not to do it
6037 if we have an OS ABI that actually supports shared libraries, since
6038 shared library support is more important. If we have an OS someday
6039 that supports both shared libraries and MIPS16, we'll have to find
6040 a better place for these. */
6041 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
6043 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6044 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6047 /* Hook in OS ABI-specific overrides, if they have been registered. */
6048 gdbarch_init_osabi (info
, gdbarch
);
6050 /* Unwind the frame. */
6051 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
6052 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
6053 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
6054 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
6055 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6056 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
6057 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6058 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6064 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6066 struct gdbarch_info info
;
6068 /* Force the architecture to update, and (if it's a MIPS architecture)
6069 mips_gdbarch_init will take care of the rest. */
6070 gdbarch_info_init (&info
);
6071 gdbarch_update_p (info
);
6074 /* Print out which MIPS ABI is in use. */
6077 show_mips_abi (char *ignore_args
, int from_tty
)
6079 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6081 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6084 enum mips_abi global_abi
= global_mips_abi ();
6085 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6086 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6088 if (global_abi
== MIPS_ABI_UNKNOWN
)
6090 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6092 else if (global_abi
== actual_abi
)
6094 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6098 /* Probably shouldn't happen... */
6100 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6101 actual_abi_str
, mips_abi_strings
[global_abi
]);
6107 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6109 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6113 int ef_mips_32bitmode
;
6114 /* determine the ISA */
6115 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6133 /* determine the size of a pointer */
6134 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6135 fprintf_unfiltered (file
,
6136 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6138 fprintf_unfiltered (file
,
6139 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6141 fprintf_unfiltered (file
,
6142 "mips_dump_tdep: ef_mips_arch = %d\n",
6144 fprintf_unfiltered (file
,
6145 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6146 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6147 fprintf_unfiltered (file
,
6148 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6149 mips_mask_address_p (tdep
),
6150 tdep
->default_mask_address_p
);
6152 fprintf_unfiltered (file
,
6153 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6154 MIPS_DEFAULT_FPU_TYPE
,
6155 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6156 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6157 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6159 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6160 fprintf_unfiltered (file
,
6161 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6163 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6164 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6165 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6167 fprintf_unfiltered (file
,
6168 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6169 mips_stack_argsize (current_gdbarch
));
6170 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6171 fprintf_unfiltered (file
,
6172 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6173 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6174 fprintf_unfiltered (file
,
6175 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6176 XSTRING (ATTACH_DETACH
));
6177 fprintf_unfiltered (file
,
6178 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6179 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6180 fprintf_unfiltered (file
,
6181 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6182 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6183 fprintf_unfiltered (file
,
6184 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6185 FIRST_EMBED_REGNUM
);
6186 fprintf_unfiltered (file
,
6187 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
6188 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
6189 fprintf_unfiltered (file
,
6190 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6191 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6192 fprintf_unfiltered (file
,
6193 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6194 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6195 fprintf_unfiltered (file
,
6196 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6198 #ifdef MACHINE_CPROC_FP_OFFSET
6199 fprintf_unfiltered (file
,
6200 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6201 MACHINE_CPROC_FP_OFFSET
);
6203 #ifdef MACHINE_CPROC_PC_OFFSET
6204 fprintf_unfiltered (file
,
6205 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6206 MACHINE_CPROC_PC_OFFSET
);
6208 #ifdef MACHINE_CPROC_SP_OFFSET
6209 fprintf_unfiltered (file
,
6210 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6211 MACHINE_CPROC_SP_OFFSET
);
6213 fprintf_unfiltered (file
,
6214 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6216 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6217 fprintf_unfiltered (file
,
6218 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6219 fprintf_unfiltered (file
,
6220 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6221 fprintf_unfiltered (file
,
6222 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6223 MIPS_LAST_ARG_REGNUM
,
6224 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6225 fprintf_unfiltered (file
,
6226 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6227 fprintf_unfiltered (file
,
6228 "mips_dump_tdep: mips_abi_regsize() = %d\n",
6229 mips_abi_regsize (current_gdbarch
));
6230 fprintf_unfiltered (file
,
6231 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6232 fprintf_unfiltered (file
,
6233 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6234 fprintf_unfiltered (file
,
6235 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6236 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6237 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6238 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6239 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6240 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6241 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6242 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6243 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6244 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6245 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6246 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6248 fprintf_unfiltered (file
,
6249 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6252 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6255 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6257 fprintf_unfiltered (file
,
6258 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6259 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6260 fprintf_unfiltered (file
,
6261 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6262 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6263 fprintf_unfiltered (file
,
6264 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6265 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6266 fprintf_unfiltered (file
,
6267 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6268 SOFTWARE_SINGLE_STEP_P ());
6269 fprintf_unfiltered (file
,
6270 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6271 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6272 #ifdef STACK_END_ADDR
6273 fprintf_unfiltered (file
,
6274 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6277 fprintf_unfiltered (file
,
6278 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6279 XSTRING (STEP_SKIPS_DELAY (PC
)));
6280 fprintf_unfiltered (file
,
6281 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6282 STEP_SKIPS_DELAY_P
);
6283 fprintf_unfiltered (file
,
6284 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6285 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6286 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6287 fprintf_unfiltered (file
,
6288 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6289 fprintf_unfiltered (file
,
6290 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6291 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6292 (TYPE
, CNT
, OTHERTYPE
)));
6294 fprintf_unfiltered (file
,
6295 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6296 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6299 fprintf_unfiltered (file
,
6300 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6302 #ifdef TRACE_FLAVOR_SIZE
6303 fprintf_unfiltered (file
,
6304 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6308 fprintf_unfiltered (file
,
6309 "mips_dump_tdep: TRACE_SET # %s\n",
6310 XSTRING (TRACE_SET (X
, STATE
)));
6312 #ifdef UNUSED_REGNUM
6313 fprintf_unfiltered (file
,
6314 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6316 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6317 fprintf_unfiltered (file
,
6318 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6319 (long) VM_MIN_ADDRESS
);
6320 fprintf_unfiltered (file
,
6321 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6324 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6327 _initialize_mips_tdep (void)
6329 static struct cmd_list_element
*mipsfpulist
= NULL
;
6330 struct cmd_list_element
*c
;
6332 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6333 if (MIPS_ABI_LAST
+ 1
6334 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6335 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6337 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6339 mips_pdr_data
= register_objfile_data ();
6341 /* Add root prefix command for all "set mips"/"show mips" commands */
6342 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6343 "Various MIPS specific commands.",
6344 &setmipscmdlist
, "set mips ", 0, &setlist
);
6346 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6347 "Various MIPS specific commands.",
6348 &showmipscmdlist
, "show mips ", 0, &showlist
);
6350 /* Allow the user to override the saved register size. */
6351 deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6354 &mips_abi_regsize_string
, "\
6355 Set size of general purpose registers saved on the stack.\n\
6356 This option can be set to one of:\n\
6357 32 - Force GDB to treat saved GP registers as 32-bit\n\
6358 64 - Force GDB to treat saved GP registers as 64-bit\n\
6359 auto - Allow GDB to use the target's default setting or autodetect the\n\
6360 saved GP register size from information contained in the executable.\n\
6361 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6363 /* Allow the user to override the argument stack size. */
6364 deprecated_add_show_from_set
6365 (add_set_enum_cmd ("stack-arg-size",
6368 &mips_stack_argsize_string
, "\
6369 Set the amount of stack space reserved for each argument.\n\
6370 This option can be set to one of:\n\
6371 32 - Force GDB to allocate 32-bit chunks per argument\n\
6372 64 - Force GDB to allocate 64-bit chunks per argument\n\
6373 auto - Allow GDB to determine the correct setting from the current\n\
6374 target and executable (default)", &setmipscmdlist
),
6377 /* Allow the user to override the ABI. */
6378 c
= add_set_enum_cmd
6379 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6380 "Set the ABI used by this program.\n"
6381 "This option can be set to one of:\n"
6382 " auto - the default ABI associated with the current binary\n"
6384 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6385 set_cmd_sfunc (c
, mips_abi_update
);
6386 add_cmd ("abi", class_obscure
, show_mips_abi
,
6387 "Show ABI in use by MIPS target", &showmipscmdlist
);
6389 /* Let the user turn off floating point and set the fence post for
6390 heuristic_proc_start. */
6392 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6393 "Set use of MIPS floating-point coprocessor.",
6394 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6395 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6396 "Select single-precision MIPS floating-point coprocessor.",
6398 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6399 "Select double-precision MIPS floating-point coprocessor.",
6401 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6402 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6403 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6404 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6405 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6406 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6407 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6408 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6409 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6410 "Select MIPS floating-point coprocessor automatically.",
6412 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6413 "Show current use of MIPS floating-point coprocessor target.",
6416 /* We really would like to have both "0" and "unlimited" work, but
6417 command.c doesn't deal with that. So make it a var_zinteger
6418 because the user can always use "999999" or some such for unlimited. */
6419 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6420 (char *) &heuristic_fence_post
, "\
6421 Set the distance searched for the start of a function.\n\
6422 If you are debugging a stripped executable, GDB needs to search through the\n\
6423 program for the start of a function. This command sets the distance of the\n\
6424 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6425 /* We need to throw away the frame cache when we set this, since it
6426 might change our ability to get backtraces. */
6427 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6428 deprecated_add_show_from_set (c
, &showlist
);
6430 /* Allow the user to control whether the upper bits of 64-bit
6431 addresses should be zeroed. */
6432 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6433 Set zeroing of upper 32 bits of 64-bit addresses.", "\
6434 Show zeroing of upper 32 bits of 64-bit addresses.", "\
6435 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6436 allow GDB to determine the correct value.\n", "\
6437 Zerroing of upper 32 bits of 64-bit address is %s.",
6438 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6440 /* Allow the user to control the size of 32 bit registers within the
6441 raw remote packet. */
6442 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6443 &mips64_transfers_32bit_regs_p
, "\
6444 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6445 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6446 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6447 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6448 64 bits for others. Use \"off\" to disable compatibility mode", "\
6449 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6450 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6452 /* Debug this files internals. */
6453 deprecated_add_show_from_set
6454 (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6455 &mips_debug
, "Set mips debugging.\n\
6456 When non-zero, mips specific debugging is enabled.", &setdebuglist
),