1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
47 #include "frame-unwind.h"
48 #include "frame-base.h"
49 #include "trad-frame.h"
51 #include "floatformat.h"
53 #include "target-descriptions.h"
54 #include "dwarf2-frame.h"
55 #include "user-regs.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
65 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
66 static int mips16_instruction_has_delay_slot (unsigned short inst
,
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 CORE_ADDR addr
, int mustbe32
);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
76 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
77 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
78 #define ST0_FR (1 << 26)
80 /* The sizes of floating point registers. */
84 MIPS_FPU_SINGLE_REGSIZE
= 4,
85 MIPS_FPU_DOUBLE_REGSIZE
= 8
94 static const char *mips_abi_string
;
96 static const char *const mips_abi_strings
[] = {
107 /* For backwards compatibility we default to MIPS16. This flag is
108 overridden as soon as unambiguous ELF file flags tell us the
109 compressed ISA encoding used. */
110 static const char mips_compression_mips16
[] = "mips16";
111 static const char mips_compression_micromips
[] = "micromips";
112 static const char *const mips_compression_strings
[] =
114 mips_compression_mips16
,
115 mips_compression_micromips
,
119 static const char *mips_compression_string
= mips_compression_mips16
;
121 /* The standard register names, and all the valid aliases for them. */
122 struct register_alias
128 /* Aliases for o32 and most other ABIs. */
129 const struct register_alias mips_o32_aliases
[] = {
136 /* Aliases for n32 and n64. */
137 const struct register_alias mips_n32_n64_aliases
[] = {
144 /* Aliases for ABI-independent registers. */
145 const struct register_alias mips_register_aliases
[] = {
146 /* The architecture manuals specify these ABI-independent names for
148 #define R(n) { "r" #n, n }
149 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
150 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
151 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
152 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
155 /* k0 and k1 are sometimes called these instead (for "kernel
160 /* This is the traditional GDB name for the CP0 status register. */
161 { "sr", MIPS_PS_REGNUM
},
163 /* This is the traditional GDB name for the CP0 BadVAddr register. */
164 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
166 /* This is the traditional GDB name for the FCSR. */
167 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
170 const struct register_alias mips_numeric_register_aliases
[] = {
171 #define R(n) { #n, n }
172 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
173 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
174 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
175 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
179 #ifndef MIPS_DEFAULT_FPU_TYPE
180 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
182 static int mips_fpu_type_auto
= 1;
183 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
185 static unsigned int mips_debug
= 0;
187 /* Properties (for struct target_desc) describing the g/G packet
189 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
190 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
192 struct target_desc
*mips_tdesc_gp32
;
193 struct target_desc
*mips_tdesc_gp64
;
195 const struct mips_regnum
*
196 mips_regnum (struct gdbarch
*gdbarch
)
198 return gdbarch_tdep (gdbarch
)->regnum
;
202 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
204 return mips_regnum (gdbarch
)->fp0
+ 12;
207 /* Return 1 if REGNUM refers to a floating-point general register, raw
208 or cooked. Otherwise return 0. */
211 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
213 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
215 return (rawnum
>= mips_regnum (gdbarch
)->fp0
216 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
219 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
221 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
223 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
224 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
226 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
227 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
229 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
231 /* Return the MIPS ABI associated with GDBARCH. */
233 mips_abi (struct gdbarch
*gdbarch
)
235 return gdbarch_tdep (gdbarch
)->mips_abi
;
239 mips_isa_regsize (struct gdbarch
*gdbarch
)
241 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
243 /* If we know how big the registers are, use that size. */
244 if (tdep
->register_size_valid_p
)
245 return tdep
->register_size
;
247 /* Fall back to the previous behavior. */
248 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
249 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
252 /* Return the currently configured (or set) saved register size. */
255 mips_abi_regsize (struct gdbarch
*gdbarch
)
257 switch (mips_abi (gdbarch
))
259 case MIPS_ABI_EABI32
:
265 case MIPS_ABI_EABI64
:
267 case MIPS_ABI_UNKNOWN
:
270 internal_error (__FILE__
, __LINE__
, _("bad switch"));
274 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
275 are some functions to handle addresses associated with compressed
276 code including but not limited to testing, setting, or clearing
277 bit 0 of such addresses. */
279 /* Return one iff compressed code is the MIPS16 instruction set. */
282 is_mips16_isa (struct gdbarch
*gdbarch
)
284 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
287 /* Return one iff compressed code is the microMIPS instruction set. */
290 is_micromips_isa (struct gdbarch
*gdbarch
)
292 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
295 /* Return one iff ADDR denotes compressed code. */
298 is_compact_addr (CORE_ADDR addr
)
303 /* Return one iff ADDR denotes standard ISA code. */
306 is_mips_addr (CORE_ADDR addr
)
308 return !is_compact_addr (addr
);
311 /* Return one iff ADDR denotes MIPS16 code. */
314 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
316 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
319 /* Return one iff ADDR denotes microMIPS code. */
322 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
324 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
327 /* Strip the ISA (compression) bit off from ADDR. */
330 unmake_compact_addr (CORE_ADDR addr
)
332 return ((addr
) & ~(CORE_ADDR
) 1);
335 /* Add the ISA (compression) bit to ADDR. */
338 make_compact_addr (CORE_ADDR addr
)
340 return ((addr
) | (CORE_ADDR
) 1);
343 /* Functions for setting and testing a bit in a minimal symbol that
344 marks it as MIPS16 or microMIPS function. The MSB of the minimal
345 symbol's "info" field is used for this purpose.
347 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
348 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
349 one of the "special" bits in a minimal symbol to mark it accordingly.
350 The test checks an ELF-private flag that is valid for true function
351 symbols only; for synthetic symbols such as for PLT stubs that have
352 no ELF-private part at all the MIPS BFD backend arranges for this
353 information to be carried in the asymbol's udata field instead.
355 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
356 in a minimal symbol. */
359 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
361 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
362 unsigned char st_other
;
364 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
365 st_other
= elfsym
->internal_elf_sym
.st_other
;
366 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
367 st_other
= sym
->udata
.i
;
371 if (ELF_ST_IS_MICROMIPS (st_other
))
372 MSYMBOL_TARGET_FLAG_2 (msym
) = 1;
373 else if (ELF_ST_IS_MIPS16 (st_other
))
374 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
377 /* Return one iff MSYM refers to standard ISA code. */
380 msymbol_is_mips (struct minimal_symbol
*msym
)
382 return !(MSYMBOL_TARGET_FLAG_1 (msym
) | MSYMBOL_TARGET_FLAG_2 (msym
));
385 /* Return one iff MSYM refers to MIPS16 code. */
388 msymbol_is_mips16 (struct minimal_symbol
*msym
)
390 return MSYMBOL_TARGET_FLAG_1 (msym
);
393 /* Return one iff MSYM refers to microMIPS code. */
396 msymbol_is_micromips (struct minimal_symbol
*msym
)
398 return MSYMBOL_TARGET_FLAG_2 (msym
);
401 /* XFER a value from the big/little/left end of the register.
402 Depending on the size of the value it might occupy the entire
403 register or just part of it. Make an allowance for this, aligning
404 things accordingly. */
407 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
408 int reg_num
, int length
,
409 enum bfd_endian endian
, gdb_byte
*in
,
410 const gdb_byte
*out
, int buf_offset
)
414 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
415 /* Need to transfer the left or right part of the register, based on
416 the targets byte order. */
420 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
422 case BFD_ENDIAN_LITTLE
:
425 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
429 internal_error (__FILE__
, __LINE__
, _("bad switch"));
432 fprintf_unfiltered (gdb_stderr
,
433 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
434 reg_num
, reg_offset
, buf_offset
, length
);
435 if (mips_debug
&& out
!= NULL
)
438 fprintf_unfiltered (gdb_stdlog
, "out ");
439 for (i
= 0; i
< length
; i
++)
440 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
443 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
446 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
448 if (mips_debug
&& in
!= NULL
)
451 fprintf_unfiltered (gdb_stdlog
, "in ");
452 for (i
= 0; i
< length
; i
++)
453 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
456 fprintf_unfiltered (gdb_stdlog
, "\n");
459 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
460 compatiblity mode. A return value of 1 means that we have
461 physical 64-bit registers, but should treat them as 32-bit registers. */
464 mips2_fp_compat (struct frame_info
*frame
)
466 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
467 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
469 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
473 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
474 in all the places we deal with FP registers. PR gdb/413. */
475 /* Otherwise check the FR bit in the status register - it controls
476 the FP compatiblity mode. If it is clear we are in compatibility
478 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
485 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
487 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
489 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
491 /* The list of available "set mips " and "show mips " commands. */
493 static struct cmd_list_element
*setmipscmdlist
= NULL
;
494 static struct cmd_list_element
*showmipscmdlist
= NULL
;
496 /* Integer registers 0 thru 31 are handled explicitly by
497 mips_register_name(). Processor specific registers 32 and above
498 are listed in the following tables. */
501 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
505 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
506 "sr", "lo", "hi", "bad", "cause", "pc",
507 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
508 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
509 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
510 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
514 /* Names of IDT R3041 registers. */
516 static const char *mips_r3041_reg_names
[] = {
517 "sr", "lo", "hi", "bad", "cause", "pc",
518 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
519 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
520 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
521 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
522 "fsr", "fir", "", /*"fp" */ "",
523 "", "", "bus", "ccfg", "", "", "", "",
524 "", "", "port", "cmp", "", "", "epc", "prid",
527 /* Names of tx39 registers. */
529 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
530 "sr", "lo", "hi", "bad", "cause", "pc",
531 "", "", "", "", "", "", "", "",
532 "", "", "", "", "", "", "", "",
533 "", "", "", "", "", "", "", "",
534 "", "", "", "", "", "", "", "",
536 "", "", "", "", "", "", "", "",
537 "", "", "config", "cache", "debug", "depc", "epc",
540 /* Names of IRIX registers. */
541 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
542 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
543 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
544 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
545 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
546 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
549 /* Names of registers with Linux kernels. */
550 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
551 "sr", "lo", "hi", "bad", "cause", "pc",
552 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
553 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
554 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
555 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
560 /* Return the name of the register corresponding to REGNO. */
562 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
564 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
565 /* GPR names for all ABIs other than n32/n64. */
566 static char *mips_gpr_names
[] = {
567 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
568 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
569 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
570 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
573 /* GPR names for n32 and n64 ABIs. */
574 static char *mips_n32_n64_gpr_names
[] = {
575 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
576 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
577 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
578 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
581 enum mips_abi abi
= mips_abi (gdbarch
);
583 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
584 but then don't make the raw register names visible. This (upper)
585 range of user visible register numbers are the pseudo-registers.
587 This approach was adopted accommodate the following scenario:
588 It is possible to debug a 64-bit device using a 32-bit
589 programming model. In such instances, the raw registers are
590 configured to be 64-bits wide, while the pseudo registers are
591 configured to be 32-bits wide. The registers that the user
592 sees - the pseudo registers - match the users expectations
593 given the programming model being used. */
594 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
595 if (regno
< gdbarch_num_regs (gdbarch
))
598 /* The MIPS integer registers are always mapped from 0 to 31. The
599 names of the registers (which reflects the conventions regarding
600 register use) vary depending on the ABI. */
601 if (0 <= rawnum
&& rawnum
< 32)
603 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
604 return mips_n32_n64_gpr_names
[rawnum
];
606 return mips_gpr_names
[rawnum
];
608 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
609 return tdesc_register_name (gdbarch
, rawnum
);
610 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
612 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
613 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
614 return tdep
->mips_processor_reg_names
[rawnum
- 32];
618 internal_error (__FILE__
, __LINE__
,
619 _("mips_register_name: bad register number %d"), rawnum
);
622 /* Return the groups that a MIPS register can be categorised into. */
625 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
626 struct reggroup
*reggroup
)
631 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
632 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
633 if (reggroup
== all_reggroup
)
635 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
636 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
637 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
638 (gdbarch), as not all architectures are multi-arch. */
639 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
640 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
641 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
643 if (reggroup
== float_reggroup
)
644 return float_p
&& pseudo
;
645 if (reggroup
== vector_reggroup
)
646 return vector_p
&& pseudo
;
647 if (reggroup
== general_reggroup
)
648 return (!vector_p
&& !float_p
) && pseudo
;
649 /* Save the pseudo registers. Need to make certain that any code
650 extracting register values from a saved register cache also uses
652 if (reggroup
== save_reggroup
)
653 return raw_p
&& pseudo
;
654 /* Restore the same pseudo register. */
655 if (reggroup
== restore_reggroup
)
656 return raw_p
&& pseudo
;
660 /* Return the groups that a MIPS register can be categorised into.
661 This version is only used if we have a target description which
662 describes real registers (and their groups). */
665 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
666 struct reggroup
*reggroup
)
668 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
669 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
672 /* Only save, restore, and display the pseudo registers. Need to
673 make certain that any code extracting register values from a
674 saved register cache also uses pseudo registers.
676 Note: saving and restoring the pseudo registers is slightly
677 strange; if we have 64 bits, we should save and restore all
678 64 bits. But this is hard and has little benefit. */
682 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
686 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
689 /* Map the symbol table registers which live in the range [1 *
690 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
691 registers. Take care of alignment and size problems. */
693 static enum register_status
694 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
695 int cookednum
, gdb_byte
*buf
)
697 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
698 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
699 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
700 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
701 return regcache_raw_read (regcache
, rawnum
, buf
);
702 else if (register_size (gdbarch
, rawnum
) >
703 register_size (gdbarch
, cookednum
))
705 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
706 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
709 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
711 enum register_status status
;
713 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
714 if (status
== REG_VALID
)
715 store_signed_integer (buf
, 4, byte_order
, regval
);
720 internal_error (__FILE__
, __LINE__
, _("bad register size"));
724 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
725 struct regcache
*regcache
, int cookednum
,
728 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
729 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
730 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
731 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
732 regcache_raw_write (regcache
, rawnum
, buf
);
733 else if (register_size (gdbarch
, rawnum
) >
734 register_size (gdbarch
, cookednum
))
736 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
737 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
740 /* Sign extend the shortened version of the register prior
741 to placing it in the raw register. This is required for
742 some mips64 parts in order to avoid unpredictable behavior. */
743 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
744 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
745 regcache_raw_write_signed (regcache
, rawnum
, regval
);
749 internal_error (__FILE__
, __LINE__
, _("bad register size"));
753 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
754 struct agent_expr
*ax
, int reg
)
756 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
757 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
758 && reg
< 2 * gdbarch_num_regs (gdbarch
));
760 ax_reg_mask (ax
, rawnum
);
766 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
767 struct agent_expr
*ax
, int reg
)
769 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
770 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
771 && reg
< 2 * gdbarch_num_regs (gdbarch
));
772 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
776 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
778 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
779 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
782 ax_simple (ax
, aop_lsh
);
785 ax_simple (ax
, aop_rsh_signed
);
789 internal_error (__FILE__
, __LINE__
, _("bad register size"));
794 /* Table to translate 3-bit register field to actual register number. */
795 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
797 /* Heuristic_proc_start may hunt through the text section for a long
798 time across a 2400 baud serial line. Allows the user to limit this
801 static int heuristic_fence_post
= 0;
803 /* Number of bytes of storage in the actual machine representation for
804 register N. NOTE: This defines the pseudo register type so need to
805 rebuild the architecture vector. */
807 static int mips64_transfers_32bit_regs_p
= 0;
810 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
811 struct cmd_list_element
*c
)
813 struct gdbarch_info info
;
814 gdbarch_info_init (&info
);
815 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
816 instead of relying on globals. Doing that would let generic code
817 handle the search for this specific architecture. */
818 if (!gdbarch_update_p (info
))
820 mips64_transfers_32bit_regs_p
= 0;
821 error (_("32-bit compatibility mode not supported"));
825 /* Convert to/from a register and the corresponding memory value. */
827 /* This predicate tests for the case of an 8 byte floating point
828 value that is being transferred to or from a pair of floating point
829 registers each of which are (or are considered to be) only 4 bytes
832 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
835 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
836 && register_size (gdbarch
, regnum
) == 4
837 && mips_float_register_p (gdbarch
, regnum
)
838 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
841 /* This predicate tests for the case of a value of less than 8
842 bytes in width that is being transfered to or from an 8 byte
843 general purpose register. */
845 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
848 int num_regs
= gdbarch_num_regs (gdbarch
);
850 return (register_size (gdbarch
, regnum
) == 8
851 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
852 && TYPE_LENGTH (type
) < 8);
856 mips_convert_register_p (struct gdbarch
*gdbarch
,
857 int regnum
, struct type
*type
)
859 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
860 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
864 mips_register_to_value (struct frame_info
*frame
, int regnum
,
865 struct type
*type
, gdb_byte
*to
,
866 int *optimizedp
, int *unavailablep
)
868 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
870 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
872 get_frame_register (frame
, regnum
+ 0, to
+ 4);
873 get_frame_register (frame
, regnum
+ 1, to
+ 0);
875 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
876 optimizedp
, unavailablep
))
879 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
880 optimizedp
, unavailablep
))
882 *optimizedp
= *unavailablep
= 0;
885 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
887 int len
= TYPE_LENGTH (type
);
890 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
891 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
892 optimizedp
, unavailablep
))
895 *optimizedp
= *unavailablep
= 0;
900 internal_error (__FILE__
, __LINE__
,
901 _("mips_register_to_value: unrecognized case"));
906 mips_value_to_register (struct frame_info
*frame
, int regnum
,
907 struct type
*type
, const gdb_byte
*from
)
909 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
911 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
913 put_frame_register (frame
, regnum
+ 0, from
+ 4);
914 put_frame_register (frame
, regnum
+ 1, from
+ 0);
916 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
919 int len
= TYPE_LENGTH (type
);
921 /* Sign extend values, irrespective of type, that are stored to
922 a 64-bit general purpose register. (32-bit unsigned values
923 are stored as signed quantities within a 64-bit register.
924 When performing an operation, in compiled code, that combines
925 a 32-bit unsigned value with a signed 64-bit value, a type
926 conversion is first performed that zeroes out the high 32 bits.) */
927 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
930 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
932 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
933 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
934 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
938 if (from
[len
-1] & 0x80)
939 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
941 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
942 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
943 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
948 internal_error (__FILE__
, __LINE__
,
949 _("mips_value_to_register: unrecognized case"));
953 /* Return the GDB type object for the "standard" data type of data in
957 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
959 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
960 if (mips_float_register_p (gdbarch
, regnum
))
962 /* The floating-point registers raw, or cooked, always match
963 mips_isa_regsize(), and also map 1:1, byte for byte. */
964 if (mips_isa_regsize (gdbarch
) == 4)
965 return builtin_type (gdbarch
)->builtin_float
;
967 return builtin_type (gdbarch
)->builtin_double
;
969 else if (regnum
< gdbarch_num_regs (gdbarch
))
971 /* The raw or ISA registers. These are all sized according to
973 if (mips_isa_regsize (gdbarch
) == 4)
974 return builtin_type (gdbarch
)->builtin_int32
;
976 return builtin_type (gdbarch
)->builtin_int64
;
980 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
982 /* The cooked or ABI registers. These are sized according to
983 the ABI (with a few complications). */
984 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
985 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
986 return builtin_type (gdbarch
)->builtin_int32
;
987 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
988 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
989 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
990 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
991 /* The pseudo/cooked view of the embedded registers is always
992 32-bit. The raw view is handled below. */
993 return builtin_type (gdbarch
)->builtin_int32
;
994 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
995 /* The target, while possibly using a 64-bit register buffer,
996 is only transfering 32-bits of each integer register.
997 Reflect this in the cooked/pseudo (ABI) register value. */
998 return builtin_type (gdbarch
)->builtin_int32
;
999 else if (mips_abi_regsize (gdbarch
) == 4)
1000 /* The ABI is restricted to 32-bit registers (the ISA could be
1002 return builtin_type (gdbarch
)->builtin_int32
;
1005 return builtin_type (gdbarch
)->builtin_int64
;
1009 /* Return the GDB type for the pseudo register REGNUM, which is the
1010 ABI-level view. This function is only called if there is a target
1011 description which includes registers, so we know precisely the
1012 types of hardware registers. */
1014 static struct type
*
1015 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1017 const int num_regs
= gdbarch_num_regs (gdbarch
);
1018 int rawnum
= regnum
% num_regs
;
1019 struct type
*rawtype
;
1021 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1023 /* Absent registers are still absent. */
1024 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1025 if (TYPE_LENGTH (rawtype
) == 0)
1028 if (mips_float_register_p (gdbarch
, rawnum
))
1029 /* Present the floating point registers however the hardware did;
1030 do not try to convert between FPU layouts. */
1033 /* Use pointer types for registers if we can. For n32 we can not,
1034 since we do not have a 64-bit pointer type. */
1035 if (mips_abi_regsize (gdbarch
)
1036 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1038 if (rawnum
== MIPS_SP_REGNUM
1039 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1040 return builtin_type (gdbarch
)->builtin_data_ptr
;
1041 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1042 return builtin_type (gdbarch
)->builtin_func_ptr
;
1045 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1046 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1047 || rawnum
== mips_regnum (gdbarch
)->lo
1048 || rawnum
== mips_regnum (gdbarch
)->hi
1049 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1050 || rawnum
== mips_regnum (gdbarch
)->cause
1051 || rawnum
== mips_regnum (gdbarch
)->pc
1052 || (mips_regnum (gdbarch
)->dspacc
!= -1
1053 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1054 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1055 return builtin_type (gdbarch
)->builtin_int32
;
1057 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
1058 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1059 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
1060 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1062 /* The pseudo/cooked view of embedded registers is always
1063 32-bit, even if the target transfers 64-bit values for them.
1064 New targets relying on XML descriptions should only transfer
1065 the necessary 32 bits, but older versions of GDB expected 64,
1066 so allow the target to provide 64 bits without interfering
1067 with the displayed type. */
1068 return builtin_type (gdbarch
)->builtin_int32
;
1071 /* For all other registers, pass through the hardware type. */
1075 /* Should the upper word of 64-bit addresses be zeroed? */
1076 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1079 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1081 switch (mask_address_var
)
1083 case AUTO_BOOLEAN_TRUE
:
1085 case AUTO_BOOLEAN_FALSE
:
1088 case AUTO_BOOLEAN_AUTO
:
1089 return tdep
->default_mask_address_p
;
1091 internal_error (__FILE__
, __LINE__
,
1092 _("mips_mask_address_p: bad switch"));
1098 show_mask_address (struct ui_file
*file
, int from_tty
,
1099 struct cmd_list_element
*c
, const char *value
)
1101 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1103 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1104 switch (mask_address_var
)
1106 case AUTO_BOOLEAN_TRUE
:
1107 printf_filtered ("The 32 bit mips address mask is enabled\n");
1109 case AUTO_BOOLEAN_FALSE
:
1110 printf_filtered ("The 32 bit mips address mask is disabled\n");
1112 case AUTO_BOOLEAN_AUTO
:
1114 ("The 32 bit address mask is set automatically. Currently %s\n",
1115 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1118 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1123 /* Tell if the program counter value in MEMADDR is in a standard ISA
1127 mips_pc_is_mips (CORE_ADDR memaddr
)
1129 struct bound_minimal_symbol sym
;
1131 /* Flags indicating that this is a MIPS16 or microMIPS function is
1132 stored by elfread.c in the high bit of the info field. Use this
1133 to decide if the function is standard MIPS. Otherwise if bit 0
1134 of the address is clear, then this is a standard MIPS function. */
1135 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1137 return msymbol_is_mips (sym
.minsym
);
1139 return is_mips_addr (memaddr
);
1142 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1145 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1147 struct bound_minimal_symbol sym
;
1149 /* A flag indicating that this is a MIPS16 function is stored by
1150 elfread.c in the high bit of the info field. Use this to decide
1151 if the function is MIPS16. Otherwise if bit 0 of the address is
1152 set, then ELF file flags will tell if this is a MIPS16 function. */
1153 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1155 return msymbol_is_mips16 (sym
.minsym
);
1157 return is_mips16_addr (gdbarch
, memaddr
);
1160 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1163 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1165 struct bound_minimal_symbol sym
;
1167 /* A flag indicating that this is a microMIPS function is stored by
1168 elfread.c in the high bit of the info field. Use this to decide
1169 if the function is microMIPS. Otherwise if bit 0 of the address
1170 is set, then ELF file flags will tell if this is a microMIPS
1172 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1174 return msymbol_is_micromips (sym
.minsym
);
1176 return is_micromips_addr (gdbarch
, memaddr
);
1179 /* Tell the ISA type of the function the program counter value in MEMADDR
1182 static enum mips_isa
1183 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1185 struct bound_minimal_symbol sym
;
1187 /* A flag indicating that this is a MIPS16 or a microMIPS function
1188 is stored by elfread.c in the high bit of the info field. Use
1189 this to decide if the function is MIPS16 or microMIPS or normal
1190 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1191 flags will tell if this is a MIPS16 or a microMIPS function. */
1192 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1195 if (msymbol_is_micromips (sym
.minsym
))
1196 return ISA_MICROMIPS
;
1197 else if (msymbol_is_mips16 (sym
.minsym
))
1204 if (is_mips_addr (memaddr
))
1206 else if (is_micromips_addr (gdbarch
, memaddr
))
1207 return ISA_MICROMIPS
;
1213 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1215 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1216 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1217 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1218 static const char mips_str_call_stub
[] = "__call_stub_";
1219 static const char mips_str_fn_stub
[] = "__fn_stub_";
1221 /* This is used as a PIC thunk prefix. */
1223 static const char mips_str_pic
[] = ".pic.";
1225 /* Return non-zero if the PC is inside a call thunk (aka stub or
1226 trampoline) that should be treated as a temporary frame. */
1229 mips_in_frame_stub (CORE_ADDR pc
)
1231 CORE_ADDR start_addr
;
1234 /* Find the starting address of the function containing the PC. */
1235 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1238 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1239 if (strncmp (name
, mips_str_mips16_call_stub
,
1240 strlen (mips_str_mips16_call_stub
)) == 0)
1242 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1243 if (strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
1245 /* If the PC is in __fn_stub_*, this is a call stub. */
1246 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0)
1249 return 0; /* Not a stub. */
1252 /* MIPS believes that the PC has a sign extended value. Perhaps the
1253 all registers should be sign extended for simplicity? */
1256 mips_read_pc (struct regcache
*regcache
)
1258 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1261 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1262 if (is_compact_addr (pc
))
1263 pc
= unmake_compact_addr (pc
);
1268 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1272 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1273 if (is_compact_addr (pc
))
1274 pc
= unmake_compact_addr (pc
);
1275 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1276 intermediate frames. In this case we can get the caller's address
1277 from $ra, or if $ra contains an address within a thunk as well, then
1278 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1279 and thus the caller's address is in $s2. */
1280 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1282 pc
= frame_unwind_register_signed
1283 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1284 if (is_compact_addr (pc
))
1285 pc
= unmake_compact_addr (pc
);
1286 if (mips_in_frame_stub (pc
))
1288 pc
= frame_unwind_register_signed
1289 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1290 if (is_compact_addr (pc
))
1291 pc
= unmake_compact_addr (pc
);
1298 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1300 return frame_unwind_register_signed
1301 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1304 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1305 dummy frame. The frame ID's base needs to match the TOS value
1306 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1309 static struct frame_id
1310 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1312 return frame_id_build
1313 (get_frame_register_signed (this_frame
,
1314 gdbarch_num_regs (gdbarch
)
1316 get_frame_pc (this_frame
));
1319 /* Implement the "write_pc" gdbarch method. */
1322 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1324 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1326 if (mips_pc_is_mips (pc
))
1327 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1329 regcache_cooked_write_unsigned (regcache
, regnum
, make_compact_addr (pc
));
1332 /* Fetch and return instruction from the specified location. Handle
1333 MIPS16/microMIPS as appropriate. */
1336 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1337 enum mips_isa isa
, CORE_ADDR addr
, int *statusp
)
1339 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1340 gdb_byte buf
[MIPS_INSN32_SIZE
];
1348 instlen
= MIPS_INSN16_SIZE
;
1349 addr
= unmake_compact_addr (addr
);
1352 instlen
= MIPS_INSN32_SIZE
;
1355 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1358 status
= target_read_memory (addr
, buf
, instlen
);
1359 if (statusp
!= NULL
)
1363 if (statusp
== NULL
)
1364 memory_error (status
, addr
);
1367 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1370 /* These are the fields of 32 bit mips instructions. */
1371 #define mips32_op(x) (x >> 26)
1372 #define itype_op(x) (x >> 26)
1373 #define itype_rs(x) ((x >> 21) & 0x1f)
1374 #define itype_rt(x) ((x >> 16) & 0x1f)
1375 #define itype_immediate(x) (x & 0xffff)
1377 #define jtype_op(x) (x >> 26)
1378 #define jtype_target(x) (x & 0x03ffffff)
1380 #define rtype_op(x) (x >> 26)
1381 #define rtype_rs(x) ((x >> 21) & 0x1f)
1382 #define rtype_rt(x) ((x >> 16) & 0x1f)
1383 #define rtype_rd(x) ((x >> 11) & 0x1f)
1384 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1385 #define rtype_funct(x) (x & 0x3f)
1387 /* MicroMIPS instruction fields. */
1388 #define micromips_op(x) ((x) >> 10)
1390 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1391 bit and the size respectively of the field extracted. */
1392 #define b0s4_imm(x) ((x) & 0xf)
1393 #define b0s5_imm(x) ((x) & 0x1f)
1394 #define b0s5_reg(x) ((x) & 0x1f)
1395 #define b0s7_imm(x) ((x) & 0x7f)
1396 #define b0s10_imm(x) ((x) & 0x3ff)
1397 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1398 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1399 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1400 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1401 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1402 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1403 #define b6s4_op(x) (((x) >> 6) & 0xf)
1404 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1406 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1407 respectively of the field extracted. */
1408 #define b0s6_op(x) ((x) & 0x3f)
1409 #define b0s11_op(x) ((x) & 0x7ff)
1410 #define b0s12_imm(x) ((x) & 0xfff)
1411 #define b0s16_imm(x) ((x) & 0xffff)
1412 #define b0s26_imm(x) ((x) & 0x3ffffff)
1413 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1414 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1415 #define b12s4_op(x) (((x) >> 12) & 0xf)
1417 /* Return the size in bytes of the instruction INSN encoded in the ISA
1421 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1426 if (micromips_op (insn
) == 0x1f)
1427 return 3 * MIPS_INSN16_SIZE
;
1428 else if (((micromips_op (insn
) & 0x4) == 0x4)
1429 || ((micromips_op (insn
) & 0x7) == 0x0))
1430 return 2 * MIPS_INSN16_SIZE
;
1432 return MIPS_INSN16_SIZE
;
1434 if ((insn
& 0xf800) == 0xf000)
1435 return 2 * MIPS_INSN16_SIZE
;
1437 return MIPS_INSN16_SIZE
;
1439 return MIPS_INSN32_SIZE
;
1441 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1445 mips32_relative_offset (ULONGEST inst
)
1447 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1450 /* Determine the address of the next instruction executed after the INST
1451 floating condition branch instruction at PC. COUNT specifies the
1452 number of the floating condition bits tested by the branch. */
1455 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1456 ULONGEST inst
, CORE_ADDR pc
, int count
)
1458 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1459 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1460 int tf
= itype_rt (inst
) & 1;
1461 int mask
= (1 << count
) - 1;
1466 /* No way to handle; it'll most likely trap anyway. */
1469 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1470 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1472 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1473 pc
+= mips32_relative_offset (inst
);
1480 /* Return nonzero if the gdbarch is an Octeon series. */
1483 is_octeon (struct gdbarch
*gdbarch
)
1485 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1487 return (info
->mach
== bfd_mach_mips_octeon
1488 || info
->mach
== bfd_mach_mips_octeonp
1489 || info
->mach
== bfd_mach_mips_octeon2
);
1492 /* Return true if the OP represents the Octeon's BBIT instruction. */
1495 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1497 if (!is_octeon (gdbarch
))
1499 /* BBIT0 is encoded as LWC2: 110 010. */
1500 /* BBIT032 is encoded as LDC2: 110 110. */
1501 /* BBIT1 is encoded as SWC2: 111 010. */
1502 /* BBIT132 is encoded as SDC2: 111 110. */
1503 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1509 /* Determine where to set a single step breakpoint while considering
1510 branch prediction. */
1513 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1515 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1518 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1519 op
= itype_op (inst
);
1520 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1524 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1535 goto greater_branch
;
1540 else if (op
== 17 && itype_rs (inst
) == 8)
1541 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1542 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1543 else if (op
== 17 && itype_rs (inst
) == 9
1544 && (itype_rt (inst
) & 2) == 0)
1545 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1546 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1547 else if (op
== 17 && itype_rs (inst
) == 10
1548 && (itype_rt (inst
) & 2) == 0)
1549 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1550 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1553 /* The new PC will be alternate mode. */
1557 reg
= jtype_target (inst
) << 2;
1558 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1559 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1561 else if (is_octeon_bbit_op (op
, gdbarch
))
1565 branch_if
= op
== 58 || op
== 62;
1566 bit
= itype_rt (inst
);
1568 /* Take into account the *32 instructions. */
1569 if (op
== 54 || op
== 62)
1572 if (((get_frame_register_signed (frame
,
1573 itype_rs (inst
)) >> bit
) & 1)
1575 pc
+= mips32_relative_offset (inst
) + 4;
1577 pc
+= 8; /* After the delay slot. */
1581 pc
+= 4; /* Not a branch, next instruction is easy. */
1584 { /* This gets way messy. */
1586 /* Further subdivide into SPECIAL, REGIMM and other. */
1587 switch (op
& 0x07) /* Extract bits 28,27,26. */
1589 case 0: /* SPECIAL */
1590 op
= rtype_funct (inst
);
1595 /* Set PC to that address. */
1596 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1598 case 12: /* SYSCALL */
1600 struct gdbarch_tdep
*tdep
;
1602 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1603 if (tdep
->syscall_next_pc
!= NULL
)
1604 pc
= tdep
->syscall_next_pc (frame
);
1613 break; /* end SPECIAL */
1614 case 1: /* REGIMM */
1616 op
= itype_rt (inst
); /* branch condition */
1621 case 16: /* BLTZAL */
1622 case 18: /* BLTZALL */
1624 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1625 pc
+= mips32_relative_offset (inst
) + 4;
1627 pc
+= 8; /* after the delay slot */
1631 case 17: /* BGEZAL */
1632 case 19: /* BGEZALL */
1633 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1634 pc
+= mips32_relative_offset (inst
) + 4;
1636 pc
+= 8; /* after the delay slot */
1638 case 0x1c: /* BPOSGE32 */
1639 case 0x1e: /* BPOSGE64 */
1641 if (itype_rs (inst
) == 0)
1643 unsigned int pos
= (op
& 2) ? 64 : 32;
1644 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1647 /* No way to handle; it'll most likely trap anyway. */
1650 if ((get_frame_register_unsigned (frame
,
1651 dspctl
) & 0x7f) >= pos
)
1652 pc
+= mips32_relative_offset (inst
);
1657 /* All of the other instructions in the REGIMM category */
1662 break; /* end REGIMM */
1667 reg
= jtype_target (inst
) << 2;
1668 /* Upper four bits get never changed... */
1669 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1672 case 4: /* BEQ, BEQL */
1674 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1675 get_frame_register_signed (frame
, itype_rt (inst
)))
1676 pc
+= mips32_relative_offset (inst
) + 4;
1680 case 5: /* BNE, BNEL */
1682 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1683 get_frame_register_signed (frame
, itype_rt (inst
)))
1684 pc
+= mips32_relative_offset (inst
) + 4;
1688 case 6: /* BLEZ, BLEZL */
1689 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1690 pc
+= mips32_relative_offset (inst
) + 4;
1696 greater_branch
: /* BGTZ, BGTZL */
1697 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1698 pc
+= mips32_relative_offset (inst
) + 4;
1705 } /* mips32_next_pc */
1707 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1711 micromips_relative_offset7 (ULONGEST insn
)
1713 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1716 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1720 micromips_relative_offset10 (ULONGEST insn
)
1722 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1725 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1729 micromips_relative_offset16 (ULONGEST insn
)
1731 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1734 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1737 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1741 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1742 return mips_insn_size (ISA_MICROMIPS
, insn
);
1745 /* Calculate the address of the next microMIPS instruction to execute
1746 after the INSN coprocessor 1 conditional branch instruction at the
1747 address PC. COUNT denotes the number of coprocessor condition bits
1748 examined by the branch. */
1751 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1752 ULONGEST insn
, CORE_ADDR pc
, int count
)
1754 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1755 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1756 int tf
= b5s5_op (insn
>> 16) & 1;
1757 int mask
= (1 << count
) - 1;
1762 /* No way to handle; it'll most likely trap anyway. */
1765 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1766 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1768 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1769 pc
+= micromips_relative_offset16 (insn
);
1771 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1776 /* Calculate the address of the next microMIPS instruction to execute
1777 after the instruction at the address PC. */
1780 micromips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1782 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1785 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1786 pc
+= MIPS_INSN16_SIZE
;
1787 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1789 /* 48-bit instructions. */
1790 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
1791 /* No branch or jump instructions in this category. */
1792 pc
+= 2 * MIPS_INSN16_SIZE
;
1795 /* 32-bit instructions. */
1796 case 2 * MIPS_INSN16_SIZE
:
1798 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1799 pc
+= MIPS_INSN16_SIZE
;
1800 switch (micromips_op (insn
>> 16))
1802 case 0x00: /* POOL32A: bits 000000 */
1803 if (b0s6_op (insn
) == 0x3c
1804 /* POOL32Axf: bits 000000 ... 111100 */
1805 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1806 /* JALR, JALR.HB: 000000 000x111100 111100 */
1807 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1808 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
>> 16));
1811 case 0x10: /* POOL32I: bits 010000 */
1812 switch (b5s5_op (insn
>> 16))
1814 case 0x00: /* BLTZ: bits 010000 00000 */
1815 case 0x01: /* BLTZAL: bits 010000 00001 */
1816 case 0x11: /* BLTZALS: bits 010000 10001 */
1817 if (get_frame_register_signed (frame
,
1818 b0s5_reg (insn
>> 16)) < 0)
1819 pc
+= micromips_relative_offset16 (insn
);
1821 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1824 case 0x02: /* BGEZ: bits 010000 00010 */
1825 case 0x03: /* BGEZAL: bits 010000 00011 */
1826 case 0x13: /* BGEZALS: bits 010000 10011 */
1827 if (get_frame_register_signed (frame
,
1828 b0s5_reg (insn
>> 16)) >= 0)
1829 pc
+= micromips_relative_offset16 (insn
);
1831 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1834 case 0x04: /* BLEZ: bits 010000 00100 */
1835 if (get_frame_register_signed (frame
,
1836 b0s5_reg (insn
>> 16)) <= 0)
1837 pc
+= micromips_relative_offset16 (insn
);
1839 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1842 case 0x05: /* BNEZC: bits 010000 00101 */
1843 if (get_frame_register_signed (frame
,
1844 b0s5_reg (insn
>> 16)) != 0)
1845 pc
+= micromips_relative_offset16 (insn
);
1848 case 0x06: /* BGTZ: bits 010000 00110 */
1849 if (get_frame_register_signed (frame
,
1850 b0s5_reg (insn
>> 16)) > 0)
1851 pc
+= micromips_relative_offset16 (insn
);
1853 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1856 case 0x07: /* BEQZC: bits 010000 00111 */
1857 if (get_frame_register_signed (frame
,
1858 b0s5_reg (insn
>> 16)) == 0)
1859 pc
+= micromips_relative_offset16 (insn
);
1862 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1863 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1864 if (((insn
>> 16) & 0x3) == 0x0)
1865 /* BC2F, BC2T: don't know how to handle these. */
1869 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1870 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1872 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1873 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1876 /* No way to handle; it'll most likely trap anyway. */
1879 if ((get_frame_register_unsigned (frame
,
1880 dspctl
) & 0x7f) >= pos
)
1881 pc
+= micromips_relative_offset16 (insn
);
1883 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1887 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1888 /* BC1ANY2F: bits 010000 11100 xxx01 */
1889 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1890 /* BC1ANY2T: bits 010000 11101 xxx01 */
1891 if (((insn
>> 16) & 0x2) == 0x0)
1892 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
,
1893 ((insn
>> 16) & 0x1) + 1);
1896 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1897 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1898 if (((insn
>> 16) & 0x3) == 0x1)
1899 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
, 4);
1904 case 0x1d: /* JALS: bits 011101 */
1905 case 0x35: /* J: bits 110101 */
1906 case 0x3d: /* JAL: bits 111101 */
1907 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
1910 case 0x25: /* BEQ: bits 100101 */
1911 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1912 == get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1913 pc
+= micromips_relative_offset16 (insn
);
1915 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1918 case 0x2d: /* BNE: bits 101101 */
1919 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1920 != get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1921 pc
+= micromips_relative_offset16 (insn
);
1923 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1926 case 0x3c: /* JALX: bits 111100 */
1927 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
1932 /* 16-bit instructions. */
1933 case MIPS_INSN16_SIZE
:
1934 switch (micromips_op (insn
))
1936 case 0x11: /* POOL16C: bits 010001 */
1937 if ((b5s5_op (insn
) & 0x1c) == 0xc)
1938 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
1939 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
));
1940 else if (b5s5_op (insn
) == 0x18)
1941 /* JRADDIUSP: bits 010001 11000 */
1942 pc
= get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
1945 case 0x23: /* BEQZ16: bits 100011 */
1947 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
1949 if (get_frame_register_signed (frame
, rs
) == 0)
1950 pc
+= micromips_relative_offset7 (insn
);
1952 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1956 case 0x2b: /* BNEZ16: bits 101011 */
1958 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
1960 if (get_frame_register_signed (frame
, rs
) != 0)
1961 pc
+= micromips_relative_offset7 (insn
);
1963 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1967 case 0x33: /* B16: bits 110011 */
1968 pc
+= micromips_relative_offset10 (insn
);
1977 /* Decoding the next place to set a breakpoint is irregular for the
1978 mips 16 variant, but fortunately, there fewer instructions. We have
1979 to cope ith extensions for 16 bit instructions and a pair of actual
1980 32 bit instructions. We dont want to set a single step instruction
1981 on the extend instruction either. */
1983 /* Lots of mips16 instruction formats */
1984 /* Predicting jumps requires itype,ritype,i8type
1985 and their extensions extItype,extritype,extI8type. */
1986 enum mips16_inst_fmts
1988 itype
, /* 0 immediate 5,10 */
1989 ritype
, /* 1 5,3,8 */
1990 rrtype
, /* 2 5,3,3,5 */
1991 rritype
, /* 3 5,3,3,5 */
1992 rrrtype
, /* 4 5,3,3,3,2 */
1993 rriatype
, /* 5 5,3,3,1,4 */
1994 shifttype
, /* 6 5,3,3,3,2 */
1995 i8type
, /* 7 5,3,8 */
1996 i8movtype
, /* 8 5,3,3,5 */
1997 i8mov32rtype
, /* 9 5,3,5,3 */
1998 i64type
, /* 10 5,3,8 */
1999 ri64type
, /* 11 5,3,3,5 */
2000 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2001 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2002 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2003 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2004 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2005 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2006 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2007 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2008 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2009 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2011 /* I am heaping all the fields of the formats into one structure and
2012 then, only the fields which are involved in instruction extension. */
2016 unsigned int regx
; /* Function in i8 type. */
2021 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2022 for the bits which make up the immediate extension. */
2025 extended_offset (unsigned int extension
)
2029 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2031 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2033 value
|= extension
& 0x1f; /* Extract 4:0. */
2038 /* Only call this function if you know that this is an extendable
2039 instruction. It won't malfunction, but why make excess remote memory
2040 references? If the immediate operands get sign extended or something,
2041 do it after the extension is performed. */
2042 /* FIXME: Every one of these cases needs to worry about sign extension
2043 when the offset is to be used in relative addressing. */
2046 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2048 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2051 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2052 target_read_memory (pc
, buf
, 2);
2053 return extract_unsigned_integer (buf
, 2, byte_order
);
2057 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2058 unsigned int extension
,
2060 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2065 switch (insn_format
)
2072 value
= extended_offset ((extension
<< 16) | inst
);
2073 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2077 value
= inst
& 0x7ff;
2078 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2087 { /* A register identifier and an offset. */
2088 /* Most of the fields are the same as I type but the
2089 immediate value is of a different length. */
2093 value
= extended_offset ((extension
<< 16) | inst
);
2094 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2098 value
= inst
& 0xff; /* 8 bits */
2099 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2102 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2108 unsigned long value
;
2109 unsigned int nexthalf
;
2110 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2111 value
= value
<< 16;
2112 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2113 /* Low bit still set. */
2121 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2123 upk
->offset
= offset
;
2129 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2130 and having a signed 16-bit OFFSET. */
2133 add_offset_16 (CORE_ADDR pc
, int offset
)
2135 return pc
+ (offset
<< 1) + 2;
2139 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
2140 unsigned int extension
, unsigned int insn
)
2142 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2143 int op
= (insn
>> 11);
2146 case 2: /* Branch */
2148 struct upk_mips16 upk
;
2149 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2150 pc
= add_offset_16 (pc
, upk
.offset
);
2153 case 3: /* JAL , JALX - Watch out, these are 32 bit
2156 struct upk_mips16 upk
;
2157 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2158 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2159 if ((insn
>> 10) & 0x01) /* Exchange mode */
2160 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2167 struct upk_mips16 upk
;
2169 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2170 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2172 pc
= add_offset_16 (pc
, upk
.offset
);
2179 struct upk_mips16 upk
;
2181 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2182 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2184 pc
= add_offset_16 (pc
, upk
.offset
);
2189 case 12: /* I8 Formats btez btnez */
2191 struct upk_mips16 upk
;
2193 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2194 /* upk.regx contains the opcode */
2195 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
2196 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2197 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2198 pc
= add_offset_16 (pc
, upk
.offset
);
2203 case 29: /* RR Formats JR, JALR, JALR-RA */
2205 struct upk_mips16 upk
;
2206 /* upk.fmt = rrtype; */
2211 upk
.regx
= (insn
>> 8) & 0x07;
2212 upk
.regy
= (insn
>> 5) & 0x07;
2213 if ((upk
.regy
& 1) == 0)
2214 reg
= mips_reg3_to_reg
[upk
.regx
];
2216 reg
= 31; /* Function return instruction. */
2217 pc
= get_frame_register_signed (frame
, reg
);
2224 /* This is an instruction extension. Fetch the real instruction
2225 (which follows the extension) and decode things based on
2229 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
2230 fetch_mips_16 (gdbarch
, pc
));
2243 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2245 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2246 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2247 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
2250 /* The mips_next_pc function supports single_step when the remote
2251 target monitor or stub is not developed enough to do a single_step.
2252 It works by decoding the current instruction and predicting where a
2253 branch will go. This isn't hard because all the data is available.
2254 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2256 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2258 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2260 if (mips_pc_is_mips16 (gdbarch
, pc
))
2261 return mips16_next_pc (frame
, pc
);
2262 else if (mips_pc_is_micromips (gdbarch
, pc
))
2263 return micromips_next_pc (frame
, pc
);
2265 return mips32_next_pc (frame
, pc
);
2268 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2272 mips16_instruction_is_compact_branch (unsigned short insn
)
2274 switch (insn
& 0xf800)
2277 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2279 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2280 case 0x2800: /* BNEZ */
2281 case 0x2000: /* BEQZ */
2282 case 0x1000: /* B */
2289 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2293 micromips_instruction_is_compact_branch (unsigned short insn
)
2295 switch (micromips_op (insn
))
2297 case 0x11: /* POOL16C: bits 010001 */
2298 return (b5s5_op (insn
) == 0x18
2299 /* JRADDIUSP: bits 010001 11000 */
2300 || b5s5_op (insn
) == 0xd);
2301 /* JRC: bits 010011 01101 */
2302 case 0x10: /* POOL32I: bits 010000 */
2303 return (b5s5_op (insn
) & 0x1d) == 0x5;
2304 /* BEQZC/BNEZC: bits 010000 001x1 */
2310 struct mips_frame_cache
2313 struct trad_frame_saved_reg
*saved_regs
;
2316 /* Set a register's saved stack address in temp_saved_regs. If an
2317 address has already been set for this register, do nothing; this
2318 way we will only recognize the first save of a given register in a
2321 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2322 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2323 Strictly speaking, only the second range is used as it is only second
2324 range (the ABI instead of ISA registers) that comes into play when finding
2325 saved registers in a frame. */
2328 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2329 int regnum
, CORE_ADDR offset
)
2331 if (this_cache
!= NULL
2332 && this_cache
->saved_regs
[regnum
].addr
== -1)
2334 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2336 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2342 /* Fetch the immediate value from a MIPS16 instruction.
2343 If the previous instruction was an EXTEND, use it to extend
2344 the upper bits of the immediate value. This is a helper function
2345 for mips16_scan_prologue. */
2348 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2349 unsigned short inst
, /* current instruction */
2350 int nbits
, /* number of bits in imm field */
2351 int scale
, /* scale factor to be applied to imm */
2352 int is_signed
) /* is the imm field signed? */
2356 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2358 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2359 if (offset
& 0x8000) /* check for negative extend */
2360 offset
= 0 - (0x10000 - (offset
& 0xffff));
2361 return offset
| (inst
& 0x1f);
2365 int max_imm
= 1 << nbits
;
2366 int mask
= max_imm
- 1;
2367 int sign_bit
= max_imm
>> 1;
2369 offset
= inst
& mask
;
2370 if (is_signed
&& (offset
& sign_bit
))
2371 offset
= 0 - (max_imm
- offset
);
2372 return offset
* scale
;
2377 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2378 the associated FRAME_CACHE if not null.
2379 Return the address of the first instruction past the prologue. */
2382 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2383 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2384 struct frame_info
*this_frame
,
2385 struct mips_frame_cache
*this_cache
)
2387 int prev_non_prologue_insn
= 0;
2388 int this_non_prologue_insn
;
2389 int non_prologue_insns
= 0;
2392 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2394 long frame_offset
= 0; /* Size of stack frame. */
2395 long frame_adjust
= 0; /* Offset of FP from SP. */
2396 int frame_reg
= MIPS_SP_REGNUM
;
2397 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2398 unsigned inst
= 0; /* current instruction */
2399 unsigned entry_inst
= 0; /* the entry instruction */
2400 unsigned save_inst
= 0; /* the save instruction */
2401 int prev_delay_slot
= 0;
2405 int extend_bytes
= 0;
2406 int prev_extend_bytes
= 0;
2407 CORE_ADDR end_prologue_addr
;
2409 /* Can be called when there's no process, and hence when there's no
2411 if (this_frame
!= NULL
)
2412 sp
= get_frame_register_signed (this_frame
,
2413 gdbarch_num_regs (gdbarch
)
2418 if (limit_pc
> start_pc
+ 200)
2419 limit_pc
= start_pc
+ 200;
2422 /* Permit at most one non-prologue non-control-transfer instruction
2423 in the middle which may have been reordered by the compiler for
2425 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2427 this_non_prologue_insn
= 0;
2430 /* Save the previous instruction. If it's an EXTEND, we'll extract
2431 the immediate offset extension from it in mips16_get_imm. */
2434 /* Fetch and decode the instruction. */
2435 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2438 /* Normally we ignore extend instructions. However, if it is
2439 not followed by a valid prologue instruction, then this
2440 instruction is not part of the prologue either. We must
2441 remember in this case to adjust the end_prologue_addr back
2443 if ((inst
& 0xf800) == 0xf000) /* extend */
2445 extend_bytes
= MIPS_INSN16_SIZE
;
2449 prev_extend_bytes
= extend_bytes
;
2452 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2453 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2455 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2456 if (offset
< 0) /* Negative stack adjustment? */
2457 frame_offset
-= offset
;
2459 /* Exit loop if a positive stack adjustment is found, which
2460 usually means that the stack cleanup code in the function
2461 epilogue is reached. */
2464 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2466 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2467 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2468 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2470 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2472 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2473 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2474 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2476 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2478 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2479 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2481 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2483 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2484 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2486 else if (inst
== 0x673d) /* move $s1, $sp */
2491 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2493 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2494 frame_addr
= sp
+ offset
;
2496 frame_adjust
= offset
;
2498 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2500 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2501 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2502 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2504 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2506 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2507 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2508 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2510 else if ((inst
& 0xf81f) == 0xe809
2511 && (inst
& 0x700) != 0x700) /* entry */
2512 entry_inst
= inst
; /* Save for later processing. */
2513 else if ((inst
& 0xff80) == 0x6480) /* save */
2515 save_inst
= inst
; /* Save for later processing. */
2516 if (prev_extend_bytes
) /* extend */
2517 save_inst
|= prev_inst
<< 16;
2519 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2521 /* This instruction is part of the prologue, but we don't
2522 need to do anything special to handle it. */
2524 else if (mips16_instruction_has_delay_slot (inst
, 0))
2525 /* JAL/JALR/JALX/JR */
2527 /* The instruction in the delay slot can be a part
2528 of the prologue, so move forward once more. */
2530 if (mips16_instruction_has_delay_slot (inst
, 1))
2533 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2534 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2539 this_non_prologue_insn
= 1;
2542 non_prologue_insns
+= this_non_prologue_insn
;
2544 /* A jump or branch, or enough non-prologue insns seen? If so,
2545 then we must have reached the end of the prologue by now. */
2546 if (prev_delay_slot
|| non_prologue_insns
> 1
2547 || mips16_instruction_is_compact_branch (inst
))
2550 prev_non_prologue_insn
= this_non_prologue_insn
;
2551 prev_delay_slot
= in_delay_slot
;
2552 prev_pc
= cur_pc
- prev_extend_bytes
;
2555 /* The entry instruction is typically the first instruction in a function,
2556 and it stores registers at offsets relative to the value of the old SP
2557 (before the prologue). But the value of the sp parameter to this
2558 function is the new SP (after the prologue has been executed). So we
2559 can't calculate those offsets until we've seen the entire prologue,
2560 and can calculate what the old SP must have been. */
2561 if (entry_inst
!= 0)
2563 int areg_count
= (entry_inst
>> 8) & 7;
2564 int sreg_count
= (entry_inst
>> 6) & 3;
2566 /* The entry instruction always subtracts 32 from the SP. */
2569 /* Now we can calculate what the SP must have been at the
2570 start of the function prologue. */
2573 /* Check if a0-a3 were saved in the caller's argument save area. */
2574 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2576 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2577 offset
+= mips_abi_regsize (gdbarch
);
2580 /* Check if the ra register was pushed on the stack. */
2582 if (entry_inst
& 0x20)
2584 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2585 offset
-= mips_abi_regsize (gdbarch
);
2588 /* Check if the s0 and s1 registers were pushed on the stack. */
2589 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2591 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2592 offset
-= mips_abi_regsize (gdbarch
);
2596 /* The SAVE instruction is similar to ENTRY, except that defined by the
2597 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2598 size of the frame is specified as an immediate field of instruction
2599 and an extended variation exists which lets additional registers and
2600 frame space to be specified. The instruction always treats registers
2601 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2602 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2604 static int args_table
[16] = {
2605 0, 0, 0, 0, 1, 1, 1, 1,
2606 2, 2, 2, 0, 3, 3, 4, -1,
2608 static int astatic_table
[16] = {
2609 0, 1, 2, 3, 0, 1, 2, 3,
2610 0, 1, 2, 4, 0, 1, 0, -1,
2612 int aregs
= (save_inst
>> 16) & 0xf;
2613 int xsregs
= (save_inst
>> 24) & 0x7;
2614 int args
= args_table
[aregs
];
2615 int astatic
= astatic_table
[aregs
];
2620 warning (_("Invalid number of argument registers encoded in SAVE."));
2625 warning (_("Invalid number of static registers encoded in SAVE."));
2629 /* For standard SAVE the frame size of 0 means 128. */
2630 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2631 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2634 frame_offset
+= frame_size
;
2636 /* Now we can calculate what the SP must have been at the
2637 start of the function prologue. */
2640 /* Check if A0-A3 were saved in the caller's argument save area. */
2641 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2643 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2644 offset
+= mips_abi_regsize (gdbarch
);
2649 /* Check if the RA register was pushed on the stack. */
2650 if (save_inst
& 0x40)
2652 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2653 offset
-= mips_abi_regsize (gdbarch
);
2656 /* Check if the S8 register was pushed on the stack. */
2659 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2660 offset
-= mips_abi_regsize (gdbarch
);
2663 /* Check if S2-S7 were pushed on the stack. */
2664 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2666 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2667 offset
-= mips_abi_regsize (gdbarch
);
2670 /* Check if the S1 register was pushed on the stack. */
2671 if (save_inst
& 0x10)
2673 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2674 offset
-= mips_abi_regsize (gdbarch
);
2676 /* Check if the S0 register was pushed on the stack. */
2677 if (save_inst
& 0x20)
2679 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2680 offset
-= mips_abi_regsize (gdbarch
);
2683 /* Check if A0-A3 were pushed on the stack. */
2684 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2686 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2687 offset
-= mips_abi_regsize (gdbarch
);
2691 if (this_cache
!= NULL
)
2694 (get_frame_register_signed (this_frame
,
2695 gdbarch_num_regs (gdbarch
) + frame_reg
)
2696 + frame_offset
- frame_adjust
);
2697 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2698 be able to get rid of the assignment below, evetually. But it's
2699 still needed for now. */
2700 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2701 + mips_regnum (gdbarch
)->pc
]
2702 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2705 /* Set end_prologue_addr to the address of the instruction immediately
2706 after the last one we scanned. Unless the last one looked like a
2707 non-prologue instruction (and we looked ahead), in which case use
2708 its address instead. */
2709 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2710 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2712 return end_prologue_addr
;
2715 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2716 Procedures that use the 32-bit instruction set are handled by the
2717 mips_insn32 unwinder. */
2719 static struct mips_frame_cache
*
2720 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2722 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2723 struct mips_frame_cache
*cache
;
2725 if ((*this_cache
) != NULL
)
2726 return (*this_cache
);
2727 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2728 (*this_cache
) = cache
;
2729 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2731 /* Analyze the function prologue. */
2733 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2734 CORE_ADDR start_addr
;
2736 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2737 if (start_addr
== 0)
2738 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2739 /* We can't analyze the prologue if we couldn't find the begining
2741 if (start_addr
== 0)
2744 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2747 /* gdbarch_sp_regnum contains the value and not the address. */
2748 trad_frame_set_value (cache
->saved_regs
,
2749 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2752 return (*this_cache
);
2756 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2757 struct frame_id
*this_id
)
2759 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2761 /* This marks the outermost frame. */
2762 if (info
->base
== 0)
2764 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2767 static struct value
*
2768 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2769 void **this_cache
, int regnum
)
2771 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2773 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2777 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2778 struct frame_info
*this_frame
, void **this_cache
)
2780 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2781 CORE_ADDR pc
= get_frame_pc (this_frame
);
2782 if (mips_pc_is_mips16 (gdbarch
, pc
))
2787 static const struct frame_unwind mips_insn16_frame_unwind
=
2790 default_frame_unwind_stop_reason
,
2791 mips_insn16_frame_this_id
,
2792 mips_insn16_frame_prev_register
,
2794 mips_insn16_frame_sniffer
2798 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2801 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2806 static const struct frame_base mips_insn16_frame_base
=
2808 &mips_insn16_frame_unwind
,
2809 mips_insn16_frame_base_address
,
2810 mips_insn16_frame_base_address
,
2811 mips_insn16_frame_base_address
2814 static const struct frame_base
*
2815 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2817 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2818 CORE_ADDR pc
= get_frame_pc (this_frame
);
2819 if (mips_pc_is_mips16 (gdbarch
, pc
))
2820 return &mips_insn16_frame_base
;
2825 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2826 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2827 interpreted directly, and then multiplied by 4. */
2830 micromips_decode_imm9 (int imm
)
2832 imm
= (imm
^ 0x100) - 0x100;
2833 if (imm
> -3 && imm
< 2)
2838 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2839 the address of the first instruction past the prologue. */
2842 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2843 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2844 struct frame_info
*this_frame
,
2845 struct mips_frame_cache
*this_cache
)
2847 CORE_ADDR end_prologue_addr
;
2848 int prev_non_prologue_insn
= 0;
2849 int frame_reg
= MIPS_SP_REGNUM
;
2850 int this_non_prologue_insn
;
2851 int non_prologue_insns
= 0;
2852 long frame_offset
= 0; /* Size of stack frame. */
2853 long frame_adjust
= 0; /* Offset of FP from SP. */
2854 CORE_ADDR frame_addr
= 0; /* Value of $30, used as frame pointer. */
2855 int prev_delay_slot
= 0;
2859 ULONGEST insn
; /* current instruction */
2863 long v1_off
= 0; /* The assumption is LUI will replace it. */
2874 /* Can be called when there's no process, and hence when there's no
2876 if (this_frame
!= NULL
)
2877 sp
= get_frame_register_signed (this_frame
,
2878 gdbarch_num_regs (gdbarch
)
2883 if (limit_pc
> start_pc
+ 200)
2884 limit_pc
= start_pc
+ 200;
2887 /* Permit at most one non-prologue non-control-transfer instruction
2888 in the middle which may have been reordered by the compiler for
2890 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2892 this_non_prologue_insn
= 0;
2896 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2897 loc
+= MIPS_INSN16_SIZE
;
2898 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2900 /* 48-bit instructions. */
2901 case 3 * MIPS_INSN16_SIZE
:
2902 /* No prologue instructions in this category. */
2903 this_non_prologue_insn
= 1;
2904 loc
+= 2 * MIPS_INSN16_SIZE
;
2907 /* 32-bit instructions. */
2908 case 2 * MIPS_INSN16_SIZE
:
2910 insn
|= mips_fetch_instruction (gdbarch
,
2911 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
2912 loc
+= MIPS_INSN16_SIZE
;
2913 switch (micromips_op (insn
>> 16))
2915 /* Record $sp/$fp adjustment. */
2916 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2917 case 0x0: /* POOL32A: bits 000000 */
2918 case 0x16: /* POOL32S: bits 010110 */
2919 op
= b0s11_op (insn
);
2920 sreg
= b0s5_reg (insn
>> 16);
2921 treg
= b5s5_reg (insn
>> 16);
2922 dreg
= b11s5_reg (insn
);
2924 /* SUBU: bits 000000 00111010000 */
2925 /* DSUBU: bits 010110 00111010000 */
2926 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
2928 /* (D)SUBU $sp, $v1 */
2930 else if (op
!= 0x150
2931 /* ADDU: bits 000000 00101010000 */
2932 /* DADDU: bits 010110 00101010000 */
2933 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
2934 this_non_prologue_insn
= 1;
2937 case 0x8: /* POOL32B: bits 001000 */
2938 op
= b12s4_op (insn
);
2939 breg
= b0s5_reg (insn
>> 16);
2940 reglist
= sreg
= b5s5_reg (insn
>> 16);
2941 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
2942 if ((op
== 0x9 || op
== 0xc)
2943 /* SWP: bits 001000 1001 */
2944 /* SDP: bits 001000 1100 */
2945 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
2946 /* S[DW]P reg,offset($sp) */
2948 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
2949 set_reg_offset (gdbarch
, this_cache
,
2951 set_reg_offset (gdbarch
, this_cache
,
2952 sreg
+ 1, sp
+ offset
+ s
);
2954 else if ((op
== 0xd || op
== 0xf)
2955 /* SWM: bits 001000 1101 */
2956 /* SDM: bits 001000 1111 */
2957 && breg
== MIPS_SP_REGNUM
2958 /* SWM reglist,offset($sp) */
2959 && ((reglist
>= 1 && reglist
<= 9)
2960 || (reglist
>= 16 && reglist
<= 25)))
2962 int sreglist
= min(reglist
& 0xf, 8);
2964 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
2965 for (i
= 0; i
< sreglist
; i
++)
2966 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
2967 if ((reglist
& 0xf) > 8)
2968 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
2969 if ((reglist
& 0x10) == 0x10)
2970 set_reg_offset (gdbarch
, this_cache
,
2971 MIPS_RA_REGNUM
, sp
+ s
* i
++);
2974 this_non_prologue_insn
= 1;
2977 /* Record $sp/$fp adjustment. */
2978 /* Discard (D)ADDIU $gp used for PIC code. */
2979 case 0xc: /* ADDIU: bits 001100 */
2980 case 0x17: /* DADDIU: bits 010111 */
2981 sreg
= b0s5_reg (insn
>> 16);
2982 dreg
= b5s5_reg (insn
>> 16);
2983 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
2984 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
2985 /* (D)ADDIU $sp, imm */
2987 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
2988 /* (D)ADDIU $fp, $sp, imm */
2990 frame_addr
= sp
+ offset
;
2991 frame_adjust
= offset
;
2994 else if (sreg
!= 28 || dreg
!= 28)
2995 /* (D)ADDIU $gp, imm */
2996 this_non_prologue_insn
= 1;
2999 /* LUI $v1 is used for larger $sp adjustments. */
3000 /* Discard LUI $gp used for PIC code. */
3001 case 0x10: /* POOL32I: bits 010000 */
3002 if (b5s5_op (insn
>> 16) == 0xd
3003 /* LUI: bits 010000 001101 */
3004 && b0s5_reg (insn
>> 16) == 3)
3006 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3007 else if (b5s5_op (insn
>> 16) != 0xd
3008 /* LUI: bits 010000 001101 */
3009 || b0s5_reg (insn
>> 16) != 28)
3011 this_non_prologue_insn
= 1;
3014 /* ORI $v1 is used for larger $sp adjustments. */
3015 case 0x14: /* ORI: bits 010100 */
3016 sreg
= b0s5_reg (insn
>> 16);
3017 dreg
= b5s5_reg (insn
>> 16);
3018 if (sreg
== 3 && dreg
== 3)
3020 v1_off
|= b0s16_imm (insn
);
3022 this_non_prologue_insn
= 1;
3025 case 0x26: /* SWC1: bits 100110 */
3026 case 0x2e: /* SDC1: bits 101110 */
3027 breg
= b0s5_reg (insn
>> 16);
3028 if (breg
!= MIPS_SP_REGNUM
)
3029 /* S[DW]C1 reg,offset($sp) */
3030 this_non_prologue_insn
= 1;
3033 case 0x36: /* SD: bits 110110 */
3034 case 0x3e: /* SW: bits 111110 */
3035 breg
= b0s5_reg (insn
>> 16);
3036 sreg
= b5s5_reg (insn
>> 16);
3037 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3038 if (breg
== MIPS_SP_REGNUM
)
3039 /* S[DW] reg,offset($sp) */
3040 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3042 this_non_prologue_insn
= 1;
3046 /* The instruction in the delay slot can be a part
3047 of the prologue, so move forward once more. */
3048 if (micromips_instruction_has_delay_slot (insn
, 0))
3051 this_non_prologue_insn
= 1;
3057 /* 16-bit instructions. */
3058 case MIPS_INSN16_SIZE
:
3059 switch (micromips_op (insn
))
3061 case 0x3: /* MOVE: bits 000011 */
3062 sreg
= b0s5_reg (insn
);
3063 dreg
= b5s5_reg (insn
);
3064 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3070 else if ((sreg
& 0x1c) != 0x4)
3071 /* MOVE reg, $a0-$a3 */
3072 this_non_prologue_insn
= 1;
3075 case 0x11: /* POOL16C: bits 010001 */
3076 if (b6s4_op (insn
) == 0x5)
3077 /* SWM: bits 010001 0101 */
3079 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3080 reglist
= b4s2_regl (insn
);
3081 for (i
= 0; i
<= reglist
; i
++)
3082 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3083 set_reg_offset (gdbarch
, this_cache
,
3084 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3087 this_non_prologue_insn
= 1;
3090 case 0x13: /* POOL16D: bits 010011 */
3091 if ((insn
& 0x1) == 0x1)
3092 /* ADDIUSP: bits 010011 1 */
3093 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3094 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3095 /* ADDIUS5: bits 010011 0 */
3096 /* ADDIUS5 $sp, imm */
3097 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3099 this_non_prologue_insn
= 1;
3102 case 0x32: /* SWSP: bits 110010 */
3103 offset
= b0s5_imm (insn
) << 2;
3104 sreg
= b5s5_reg (insn
);
3105 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3109 /* The instruction in the delay slot can be a part
3110 of the prologue, so move forward once more. */
3111 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3114 this_non_prologue_insn
= 1;
3120 frame_offset
-= sp_adj
;
3122 non_prologue_insns
+= this_non_prologue_insn
;
3124 /* A jump or branch, enough non-prologue insns seen or positive
3125 stack adjustment? If so, then we must have reached the end
3126 of the prologue by now. */
3127 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3128 || micromips_instruction_is_compact_branch (insn
))
3131 prev_non_prologue_insn
= this_non_prologue_insn
;
3132 prev_delay_slot
= in_delay_slot
;
3136 if (this_cache
!= NULL
)
3139 (get_frame_register_signed (this_frame
,
3140 gdbarch_num_regs (gdbarch
) + frame_reg
)
3141 + frame_offset
- frame_adjust
);
3142 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3143 be able to get rid of the assignment below, evetually. But it's
3144 still needed for now. */
3145 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3146 + mips_regnum (gdbarch
)->pc
]
3147 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3150 /* Set end_prologue_addr to the address of the instruction immediately
3151 after the last one we scanned. Unless the last one looked like a
3152 non-prologue instruction (and we looked ahead), in which case use
3153 its address instead. */
3155 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3157 return end_prologue_addr
;
3160 /* Heuristic unwinder for procedures using microMIPS instructions.
3161 Procedures that use the 32-bit instruction set are handled by the
3162 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3164 static struct mips_frame_cache
*
3165 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3167 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3168 struct mips_frame_cache
*cache
;
3170 if ((*this_cache
) != NULL
)
3171 return (*this_cache
);
3173 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3174 (*this_cache
) = cache
;
3175 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3177 /* Analyze the function prologue. */
3179 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3180 CORE_ADDR start_addr
;
3182 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3183 if (start_addr
== 0)
3184 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3185 /* We can't analyze the prologue if we couldn't find the begining
3187 if (start_addr
== 0)
3190 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3193 /* gdbarch_sp_regnum contains the value and not the address. */
3194 trad_frame_set_value (cache
->saved_regs
,
3195 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3198 return (*this_cache
);
3202 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3203 struct frame_id
*this_id
)
3205 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3207 /* This marks the outermost frame. */
3208 if (info
->base
== 0)
3210 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3213 static struct value
*
3214 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3215 void **this_cache
, int regnum
)
3217 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3219 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3223 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3224 struct frame_info
*this_frame
, void **this_cache
)
3226 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3227 CORE_ADDR pc
= get_frame_pc (this_frame
);
3229 if (mips_pc_is_micromips (gdbarch
, pc
))
3234 static const struct frame_unwind mips_micro_frame_unwind
=
3237 default_frame_unwind_stop_reason
,
3238 mips_micro_frame_this_id
,
3239 mips_micro_frame_prev_register
,
3241 mips_micro_frame_sniffer
3245 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3248 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3253 static const struct frame_base mips_micro_frame_base
=
3255 &mips_micro_frame_unwind
,
3256 mips_micro_frame_base_address
,
3257 mips_micro_frame_base_address
,
3258 mips_micro_frame_base_address
3261 static const struct frame_base
*
3262 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3264 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3265 CORE_ADDR pc
= get_frame_pc (this_frame
);
3267 if (mips_pc_is_micromips (gdbarch
, pc
))
3268 return &mips_micro_frame_base
;
3273 /* Mark all the registers as unset in the saved_regs array
3274 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3277 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3279 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3283 const int num_regs
= gdbarch_num_regs (gdbarch
);
3286 for (i
= 0; i
< num_regs
; i
++)
3288 this_cache
->saved_regs
[i
].addr
= -1;
3293 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3294 the associated FRAME_CACHE if not null.
3295 Return the address of the first instruction past the prologue. */
3298 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3299 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3300 struct frame_info
*this_frame
,
3301 struct mips_frame_cache
*this_cache
)
3303 int prev_non_prologue_insn
;
3304 int this_non_prologue_insn
;
3305 int non_prologue_insns
;
3306 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3308 int prev_delay_slot
;
3313 int frame_reg
= MIPS_SP_REGNUM
;
3315 CORE_ADDR end_prologue_addr
;
3316 int seen_sp_adjust
= 0;
3317 int load_immediate_bytes
= 0;
3319 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3321 /* Can be called when there's no process, and hence when there's no
3323 if (this_frame
!= NULL
)
3324 sp
= get_frame_register_signed (this_frame
,
3325 gdbarch_num_regs (gdbarch
)
3330 if (limit_pc
> start_pc
+ 200)
3331 limit_pc
= start_pc
+ 200;
3334 prev_non_prologue_insn
= 0;
3335 non_prologue_insns
= 0;
3336 prev_delay_slot
= 0;
3339 /* Permit at most one non-prologue non-control-transfer instruction
3340 in the middle which may have been reordered by the compiler for
3343 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3345 unsigned long inst
, high_word
, low_word
;
3348 this_non_prologue_insn
= 0;
3351 /* Fetch the instruction. */
3352 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3355 /* Save some code by pre-extracting some useful fields. */
3356 high_word
= (inst
>> 16) & 0xffff;
3357 low_word
= inst
& 0xffff;
3358 reg
= high_word
& 0x1f;
3360 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3361 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3362 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3364 if (low_word
& 0x8000) /* Negative stack adjustment? */
3365 frame_offset
+= 0x10000 - low_word
;
3367 /* Exit loop if a positive stack adjustment is found, which
3368 usually means that the stack cleanup code in the function
3369 epilogue is reached. */
3373 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3374 && !regsize_is_64_bits
)
3376 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3378 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3379 && regsize_is_64_bits
)
3381 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3382 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3384 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3386 /* Old gcc frame, r30 is virtual frame pointer. */
3387 if ((long) low_word
!= frame_offset
)
3388 frame_addr
= sp
+ low_word
;
3389 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3391 unsigned alloca_adjust
;
3394 frame_addr
= get_frame_register_signed
3395 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3398 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
3399 if (alloca_adjust
> 0)
3401 /* FP > SP + frame_size. This may be because of
3402 an alloca or somethings similar. Fix sp to
3403 "pre-alloca" value, and try again. */
3404 sp
+= alloca_adjust
;
3405 /* Need to reset the status of all registers. Otherwise,
3406 we will hit a guard that prevents the new address
3407 for each register to be recomputed during the second
3409 reset_saved_regs (gdbarch
, this_cache
);
3414 /* move $30,$sp. With different versions of gas this will be either
3415 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3416 Accept any one of these. */
3417 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3419 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3420 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3422 unsigned alloca_adjust
;
3425 frame_addr
= get_frame_register_signed
3426 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3428 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3429 if (alloca_adjust
> 0)
3431 /* FP > SP + frame_size. This may be because of
3432 an alloca or somethings similar. Fix sp to
3433 "pre-alloca" value, and try again. */
3435 /* Need to reset the status of all registers. Otherwise,
3436 we will hit a guard that prevents the new address
3437 for each register to be recomputed during the second
3439 reset_saved_regs (gdbarch
, this_cache
);
3444 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3445 && !regsize_is_64_bits
)
3447 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
3449 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3450 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3451 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3452 || high_word
== 0x3c1c /* lui $gp,n */
3453 || high_word
== 0x279c /* addiu $gp,$gp,n */
3454 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3455 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3458 /* These instructions are part of the prologue, but we don't
3459 need to do anything special to handle them. */
3461 /* The instructions below load $at or $t0 with an immediate
3462 value in preparation for a stack adjustment via
3463 subu $sp,$sp,[$at,$t0]. These instructions could also
3464 initialize a local variable, so we accept them only before
3465 a stack adjustment instruction was seen. */
3466 else if (!seen_sp_adjust
3468 && (high_word
== 0x3c01 /* lui $at,n */
3469 || high_word
== 0x3c08 /* lui $t0,n */
3470 || high_word
== 0x3421 /* ori $at,$at,n */
3471 || high_word
== 0x3508 /* ori $t0,$t0,n */
3472 || high_word
== 0x3401 /* ori $at,$zero,n */
3473 || high_word
== 0x3408 /* ori $t0,$zero,n */
3476 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3478 /* Check for branches and jumps. The instruction in the delay
3479 slot can be a part of the prologue, so move forward once more. */
3480 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3484 /* This instruction is not an instruction typically found
3485 in a prologue, so we must have reached the end of the
3489 this_non_prologue_insn
= 1;
3492 non_prologue_insns
+= this_non_prologue_insn
;
3494 /* A jump or branch, or enough non-prologue insns seen? If so,
3495 then we must have reached the end of the prologue by now. */
3496 if (prev_delay_slot
|| non_prologue_insns
> 1)
3499 prev_non_prologue_insn
= this_non_prologue_insn
;
3500 prev_delay_slot
= in_delay_slot
;
3504 if (this_cache
!= NULL
)
3507 (get_frame_register_signed (this_frame
,
3508 gdbarch_num_regs (gdbarch
) + frame_reg
)
3510 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3511 this assignment below, eventually. But it's still needed
3513 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3514 + mips_regnum (gdbarch
)->pc
]
3515 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3519 /* Set end_prologue_addr to the address of the instruction immediately
3520 after the last one we scanned. Unless the last one looked like a
3521 non-prologue instruction (and we looked ahead), in which case use
3522 its address instead. */
3524 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3526 /* In a frameless function, we might have incorrectly
3527 skipped some load immediate instructions. Undo the skipping
3528 if the load immediate was not followed by a stack adjustment. */
3529 if (load_immediate_bytes
&& !seen_sp_adjust
)
3530 end_prologue_addr
-= load_immediate_bytes
;
3532 return end_prologue_addr
;
3535 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3536 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3537 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3538 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3540 static struct mips_frame_cache
*
3541 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3543 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3544 struct mips_frame_cache
*cache
;
3546 if ((*this_cache
) != NULL
)
3547 return (*this_cache
);
3549 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3550 (*this_cache
) = cache
;
3551 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3553 /* Analyze the function prologue. */
3555 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3556 CORE_ADDR start_addr
;
3558 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3559 if (start_addr
== 0)
3560 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3561 /* We can't analyze the prologue if we couldn't find the begining
3563 if (start_addr
== 0)
3566 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3569 /* gdbarch_sp_regnum contains the value and not the address. */
3570 trad_frame_set_value (cache
->saved_regs
,
3571 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3574 return (*this_cache
);
3578 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3579 struct frame_id
*this_id
)
3581 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3583 /* This marks the outermost frame. */
3584 if (info
->base
== 0)
3586 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3589 static struct value
*
3590 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3591 void **this_cache
, int regnum
)
3593 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3595 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3599 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3600 struct frame_info
*this_frame
, void **this_cache
)
3602 CORE_ADDR pc
= get_frame_pc (this_frame
);
3603 if (mips_pc_is_mips (pc
))
3608 static const struct frame_unwind mips_insn32_frame_unwind
=
3611 default_frame_unwind_stop_reason
,
3612 mips_insn32_frame_this_id
,
3613 mips_insn32_frame_prev_register
,
3615 mips_insn32_frame_sniffer
3619 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3622 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3627 static const struct frame_base mips_insn32_frame_base
=
3629 &mips_insn32_frame_unwind
,
3630 mips_insn32_frame_base_address
,
3631 mips_insn32_frame_base_address
,
3632 mips_insn32_frame_base_address
3635 static const struct frame_base
*
3636 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3638 CORE_ADDR pc
= get_frame_pc (this_frame
);
3639 if (mips_pc_is_mips (pc
))
3640 return &mips_insn32_frame_base
;
3645 static struct trad_frame_cache
*
3646 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3649 CORE_ADDR start_addr
;
3650 CORE_ADDR stack_addr
;
3651 struct trad_frame_cache
*this_trad_cache
;
3652 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3653 int num_regs
= gdbarch_num_regs (gdbarch
);
3655 if ((*this_cache
) != NULL
)
3656 return (*this_cache
);
3657 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3658 (*this_cache
) = this_trad_cache
;
3660 /* The return address is in the link register. */
3661 trad_frame_set_reg_realreg (this_trad_cache
,
3662 gdbarch_pc_regnum (gdbarch
),
3663 num_regs
+ MIPS_RA_REGNUM
);
3665 /* Frame ID, since it's a frameless / stackless function, no stack
3666 space is allocated and SP on entry is the current SP. */
3667 pc
= get_frame_pc (this_frame
);
3668 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3669 stack_addr
= get_frame_register_signed (this_frame
,
3670 num_regs
+ MIPS_SP_REGNUM
);
3671 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3673 /* Assume that the frame's base is the same as the
3675 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3677 return this_trad_cache
;
3681 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3682 struct frame_id
*this_id
)
3684 struct trad_frame_cache
*this_trad_cache
3685 = mips_stub_frame_cache (this_frame
, this_cache
);
3686 trad_frame_get_id (this_trad_cache
, this_id
);
3689 static struct value
*
3690 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3691 void **this_cache
, int regnum
)
3693 struct trad_frame_cache
*this_trad_cache
3694 = mips_stub_frame_cache (this_frame
, this_cache
);
3695 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3699 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3700 struct frame_info
*this_frame
, void **this_cache
)
3703 struct obj_section
*s
;
3704 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3705 struct bound_minimal_symbol msym
;
3707 /* Use the stub unwinder for unreadable code. */
3708 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3711 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3714 /* Calling a PIC function from a non-PIC function passes through a
3715 stub. The stub for foo is named ".pic.foo". */
3716 msym
= lookup_minimal_symbol_by_pc (pc
);
3717 if (msym
.minsym
!= NULL
3718 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
3719 && strncmp (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic.", 5) == 0)
3725 static const struct frame_unwind mips_stub_frame_unwind
=
3728 default_frame_unwind_stop_reason
,
3729 mips_stub_frame_this_id
,
3730 mips_stub_frame_prev_register
,
3732 mips_stub_frame_sniffer
3736 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3739 struct trad_frame_cache
*this_trad_cache
3740 = mips_stub_frame_cache (this_frame
, this_cache
);
3741 return trad_frame_get_this_base (this_trad_cache
);
3744 static const struct frame_base mips_stub_frame_base
=
3746 &mips_stub_frame_unwind
,
3747 mips_stub_frame_base_address
,
3748 mips_stub_frame_base_address
,
3749 mips_stub_frame_base_address
3752 static const struct frame_base
*
3753 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3755 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3756 return &mips_stub_frame_base
;
3761 /* mips_addr_bits_remove - remove useless address bits */
3764 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3766 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3768 if (is_compact_addr (addr
))
3769 addr
= unmake_compact_addr (addr
);
3771 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3772 /* This hack is a work-around for existing boards using PMON, the
3773 simulator, and any other 64-bit targets that doesn't have true
3774 64-bit addressing. On these targets, the upper 32 bits of
3775 addresses are ignored by the hardware. Thus, the PC or SP are
3776 likely to have been sign extended to all 1s by instruction
3777 sequences that load 32-bit addresses. For example, a typical
3778 piece of code that loads an address is this:
3780 lui $r2, <upper 16 bits>
3781 ori $r2, <lower 16 bits>
3783 But the lui sign-extends the value such that the upper 32 bits
3784 may be all 1s. The workaround is simply to mask off these
3785 bits. In the future, gcc may be changed to support true 64-bit
3786 addressing, and this masking will have to be disabled. */
3787 return addr
&= 0xffffffffUL
;
3793 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3794 instruction and ending with a SC/SCD instruction. If such a sequence
3795 is found, attempt to step through it. A breakpoint is placed at the end of
3798 /* Instructions used during single-stepping of atomic sequences, standard
3800 #define LL_OPCODE 0x30
3801 #define LLD_OPCODE 0x34
3802 #define SC_OPCODE 0x38
3803 #define SCD_OPCODE 0x3c
3806 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3807 struct address_space
*aspace
, CORE_ADDR pc
)
3809 CORE_ADDR breaks
[2] = {-1, -1};
3811 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3815 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3816 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3818 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3819 /* Assume all atomic sequences start with a ll/lld instruction. */
3820 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3823 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3825 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3828 loc
+= MIPS_INSN32_SIZE
;
3829 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3831 /* Assume that there is at most one branch in the atomic
3832 sequence. If a branch is found, put a breakpoint in its
3833 destination address. */
3834 switch (itype_op (insn
))
3836 case 0: /* SPECIAL */
3837 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3838 return 0; /* fallback to the standard single-step code. */
3840 case 1: /* REGIMM */
3841 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3842 || ((itype_rt (insn
) & 0x1e) == 0
3843 && itype_rs (insn
) == 0)); /* BPOSGE* */
3847 return 0; /* fallback to the standard single-step code. */
3854 case 22: /* BLEZL */
3855 case 23: /* BGTTL */
3859 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3860 && (itype_rt (insn
) & 0x2) == 0);
3861 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3866 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3871 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3872 if (last_breakpoint
>= 1)
3873 return 0; /* More than one branch found, fallback to the
3874 standard single-step code. */
3875 breaks
[1] = branch_bp
;
3879 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3883 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3884 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3887 loc
+= MIPS_INSN32_SIZE
;
3889 /* Insert a breakpoint right after the end of the atomic sequence. */
3892 /* Check for duplicated breakpoints. Check also for a breakpoint
3893 placed (branch instruction's destination) in the atomic sequence. */
3894 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3895 last_breakpoint
= 0;
3897 /* Effectively inserts the breakpoints. */
3898 for (index
= 0; index
<= last_breakpoint
; index
++)
3899 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3905 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3906 struct address_space
*aspace
,
3909 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3910 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3911 CORE_ADDR breaks
[2] = {-1, -1};
3912 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
3920 /* Assume all atomic sequences start with a ll/lld instruction. */
3921 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3922 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
3924 loc
+= MIPS_INSN16_SIZE
;
3926 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3927 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
3929 loc
+= MIPS_INSN16_SIZE
;
3931 /* Assume all atomic sequences end with an sc/scd instruction. Assume
3932 that no atomic sequence is longer than "atomic_sequence_length"
3934 for (insn_count
= 0;
3935 !sc_found
&& insn_count
< atomic_sequence_length
;
3940 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3941 loc
+= MIPS_INSN16_SIZE
;
3943 /* Assume that there is at most one conditional branch in the
3944 atomic sequence. If a branch is found, put a breakpoint in
3945 its destination address. */
3946 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3948 /* 48-bit instructions. */
3949 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
3950 loc
+= 2 * MIPS_INSN16_SIZE
;
3953 /* 32-bit instructions. */
3954 case 2 * MIPS_INSN16_SIZE
:
3955 switch (micromips_op (insn
))
3957 case 0x10: /* POOL32I: bits 010000 */
3958 if ((b5s5_op (insn
) & 0x18) != 0x0
3959 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
3960 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
3961 && (b5s5_op (insn
) & 0x1d) != 0x11
3962 /* BLTZALS, BGEZALS: bits 010000 100x1 */
3963 && ((b5s5_op (insn
) & 0x1e) != 0x14
3964 || (insn
& 0x3) != 0x0)
3965 /* BC2F, BC2T: bits 010000 1010x xxx00 */
3966 && (b5s5_op (insn
) & 0x1e) != 0x1a
3967 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
3968 && ((b5s5_op (insn
) & 0x1e) != 0x1c
3969 || (insn
& 0x3) != 0x0)
3970 /* BC1F, BC1T: bits 010000 1110x xxx00 */
3971 && ((b5s5_op (insn
) & 0x1c) != 0x1c
3972 || (insn
& 0x3) != 0x1))
3973 /* BC1ANY*: bits 010000 111xx xxx01 */
3977 case 0x25: /* BEQ: bits 100101 */
3978 case 0x2d: /* BNE: bits 101101 */
3980 insn
|= mips_fetch_instruction (gdbarch
,
3981 ISA_MICROMIPS
, loc
, NULL
);
3982 branch_bp
= (loc
+ MIPS_INSN16_SIZE
3983 + micromips_relative_offset16 (insn
));
3987 case 0x00: /* POOL32A: bits 000000 */
3989 insn
|= mips_fetch_instruction (gdbarch
,
3990 ISA_MICROMIPS
, loc
, NULL
);
3991 if (b0s6_op (insn
) != 0x3c
3992 /* POOL32Axf: bits 000000 ... 111100 */
3993 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
3994 /* JALR, JALR.HB: 000000 000x111100 111100 */
3995 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
3999 case 0x1d: /* JALS: bits 011101 */
4000 case 0x35: /* J: bits 110101 */
4001 case 0x3d: /* JAL: bits 111101 */
4002 case 0x3c: /* JALX: bits 111100 */
4003 return 0; /* Fall back to the standard single-step code. */
4005 case 0x18: /* POOL32C: bits 011000 */
4006 if ((b12s4_op (insn
) & 0xb) == 0xb)
4007 /* SC, SCD: bits 011000 1x11 */
4011 loc
+= MIPS_INSN16_SIZE
;
4014 /* 16-bit instructions. */
4015 case MIPS_INSN16_SIZE
:
4016 switch (micromips_op (insn
))
4018 case 0x23: /* BEQZ16: bits 100011 */
4019 case 0x2b: /* BNEZ16: bits 101011 */
4020 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4024 case 0x11: /* POOL16C: bits 010001 */
4025 if ((b5s5_op (insn
) & 0x1c) != 0xc
4026 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4027 && b5s5_op (insn
) != 0x18)
4028 /* JRADDIUSP: bits 010001 11000 */
4030 return 0; /* Fall back to the standard single-step code. */
4032 case 0x33: /* B16: bits 110011 */
4033 return 0; /* Fall back to the standard single-step code. */
4039 if (last_breakpoint
>= 1)
4040 return 0; /* More than one branch found, fallback to the
4041 standard single-step code. */
4042 breaks
[1] = branch_bp
;
4049 /* Insert a breakpoint right after the end of the atomic sequence. */
4052 /* Check for duplicated breakpoints. Check also for a breakpoint
4053 placed (branch instruction's destination) in the atomic sequence */
4054 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4055 last_breakpoint
= 0;
4057 /* Effectively inserts the breakpoints. */
4058 for (index
= 0; index
<= last_breakpoint
; index
++)
4059 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
4065 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4066 struct address_space
*aspace
, CORE_ADDR pc
)
4068 if (mips_pc_is_mips (pc
))
4069 return mips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4070 else if (mips_pc_is_micromips (gdbarch
, pc
))
4071 return micromips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4076 /* mips_software_single_step() is called just before we want to resume
4077 the inferior, if we want to single-step it but there is no hardware
4078 or kernel single-step support (MIPS on GNU/Linux for example). We find
4079 the target of the coming instruction and breakpoint it. */
4082 mips_software_single_step (struct frame_info
*frame
)
4084 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4085 struct address_space
*aspace
= get_frame_address_space (frame
);
4086 CORE_ADDR pc
, next_pc
;
4088 pc
= get_frame_pc (frame
);
4089 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
4092 next_pc
= mips_next_pc (frame
, pc
);
4094 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
4098 /* Test whether the PC points to the return instruction at the
4099 end of a function. */
4102 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4107 /* This used to check for MIPS16, but this piece of code is never
4108 called for MIPS16 functions. And likewise microMIPS ones. */
4109 gdb_assert (mips_pc_is_mips (pc
));
4111 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4113 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4117 /* This fencepost looks highly suspicious to me. Removing it also
4118 seems suspicious as it could affect remote debugging across serial
4122 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4128 struct inferior
*inf
;
4130 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4132 fence
= start_pc
- heuristic_fence_post
;
4136 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4137 fence
= VM_MIN_ADDRESS
;
4139 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4141 inf
= current_inferior ();
4143 /* Search back for previous return. */
4144 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4145 if (start_pc
< fence
)
4147 /* It's not clear to me why we reach this point when
4148 stop_soon, but with this test, at least we
4149 don't print out warnings for every child forked (eg, on
4150 decstation). 22apr93 rich@cygnus.com. */
4151 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4153 static int blurb_printed
= 0;
4155 warning (_("GDB can't find the start of the function at %s."),
4156 paddress (gdbarch
, pc
));
4160 /* This actually happens frequently in embedded
4161 development, when you first connect to a board
4162 and your stack pointer and pc are nowhere in
4163 particular. This message needs to give people
4164 in that situation enough information to
4165 determine that it's no big deal. */
4166 printf_filtered ("\n\
4167 GDB is unable to find the start of the function at %s\n\
4168 and thus can't determine the size of that function's stack frame.\n\
4169 This means that GDB may be unable to access that stack frame, or\n\
4170 the frames below it.\n\
4171 This problem is most likely caused by an invalid program counter or\n\
4173 However, if you think GDB should simply search farther back\n\
4174 from %s for code which looks like the beginning of a\n\
4175 function, you can increase the range of the search using the `set\n\
4176 heuristic-fence-post' command.\n",
4177 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4184 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4186 unsigned short inst
;
4188 /* On MIPS16, any one of the following is likely to be the
4189 start of a function:
4195 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4196 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4197 if ((inst
& 0xff80) == 0x6480) /* save */
4199 if (start_pc
- instlen
>= fence
)
4201 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4202 start_pc
- instlen
, NULL
);
4203 if ((inst
& 0xf800) == 0xf000) /* extend */
4204 start_pc
-= instlen
;
4208 else if (((inst
& 0xf81f) == 0xe809
4209 && (inst
& 0x700) != 0x700) /* entry */
4210 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4211 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4212 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4214 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4215 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4220 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4228 /* On microMIPS, any one of the following is likely to be the
4229 start of a function:
4233 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4234 switch (micromips_op (insn
))
4236 case 0xc: /* ADDIU: bits 001100 */
4237 case 0x17: /* DADDIU: bits 010111 */
4238 sreg
= b0s5_reg (insn
);
4239 dreg
= b5s5_reg (insn
);
4241 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4242 pc
+ MIPS_INSN16_SIZE
, NULL
);
4243 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4244 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4245 /* (D)ADDIU $sp, imm */
4250 case 0x10: /* POOL32I: bits 010000 */
4251 if (b5s5_op (insn
) == 0xd
4252 /* LUI: bits 010000 001101 */
4253 && b0s5_reg (insn
>> 16) == 28)
4258 case 0x13: /* POOL16D: bits 010011 */
4259 if ((insn
& 0x1) == 0x1)
4260 /* ADDIUSP: bits 010011 1 */
4262 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4268 /* ADDIUS5: bits 010011 0 */
4270 dreg
= b5s5_reg (insn
);
4271 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4272 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4273 /* ADDIUS5 $sp, -imm */
4281 else if (mips_about_to_return (gdbarch
, start_pc
))
4283 /* Skip return and its delay slot. */
4284 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4291 struct mips_objfile_private
4297 /* According to the current ABI, should the type be passed in a
4298 floating-point register (assuming that there is space)? When there
4299 is no FPU, FP are not even considered as possible candidates for
4300 FP registers and, consequently this returns false - forces FP
4301 arguments into integer registers. */
4304 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4305 struct type
*arg_type
)
4307 return ((typecode
== TYPE_CODE_FLT
4308 || (MIPS_EABI (gdbarch
)
4309 && (typecode
== TYPE_CODE_STRUCT
4310 || typecode
== TYPE_CODE_UNION
)
4311 && TYPE_NFIELDS (arg_type
) == 1
4312 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4314 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4317 /* On o32, argument passing in GPRs depends on the alignment of the type being
4318 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4321 mips_type_needs_double_align (struct type
*type
)
4323 enum type_code typecode
= TYPE_CODE (type
);
4325 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4327 else if (typecode
== TYPE_CODE_STRUCT
)
4329 if (TYPE_NFIELDS (type
) < 1)
4331 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4333 else if (typecode
== TYPE_CODE_UNION
)
4337 n
= TYPE_NFIELDS (type
);
4338 for (i
= 0; i
< n
; i
++)
4339 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4346 /* Adjust the address downward (direction of stack growth) so that it
4347 is correctly aligned for a new stack frame. */
4349 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4351 return align_down (addr
, 16);
4354 /* Implement the "push_dummy_code" gdbarch method. */
4357 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4358 CORE_ADDR funaddr
, struct value
**args
,
4359 int nargs
, struct type
*value_type
,
4360 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4361 struct regcache
*regcache
)
4363 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4367 /* Reserve enough room on the stack for our breakpoint instruction. */
4368 bp_slot
= sp
- sizeof (nop_insn
);
4370 /* Return to microMIPS mode if calling microMIPS code to avoid
4371 triggering an address error exception on processors that only
4372 support microMIPS execution. */
4373 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4374 ? make_compact_addr (bp_slot
) : bp_slot
);
4376 /* The breakpoint layer automatically adjusts the address of
4377 breakpoints inserted in a branch delay slot. With enough
4378 bad luck, the 4 bytes located just before our breakpoint
4379 instruction could look like a branch instruction, and thus
4380 trigger the adjustement, and break the function call entirely.
4381 So, we reserve those 4 bytes and write a nop instruction
4382 to prevent that from happening. */
4383 nop_addr
= bp_slot
- sizeof (nop_insn
);
4384 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4385 sp
= mips_frame_align (gdbarch
, nop_addr
);
4387 /* Inferior resumes at the function entry point. */
4394 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4395 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4396 int nargs
, struct value
**args
, CORE_ADDR sp
,
4397 int struct_return
, CORE_ADDR struct_addr
)
4403 int stack_offset
= 0;
4404 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4405 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4406 int regsize
= mips_abi_regsize (gdbarch
);
4408 /* For shared libraries, "t9" needs to point at the function
4410 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4412 /* Set the return address register to point to the entry point of
4413 the program, where a breakpoint lies in wait. */
4414 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4416 /* First ensure that the stack and structure return address (if any)
4417 are properly aligned. The stack has to be at least 64-bit
4418 aligned even on 32-bit machines, because doubles must be 64-bit
4419 aligned. For n32 and n64, stack frames need to be 128-bit
4420 aligned, so we round to this widest known alignment. */
4422 sp
= align_down (sp
, 16);
4423 struct_addr
= align_down (struct_addr
, 16);
4425 /* Now make space on the stack for the args. We allocate more
4426 than necessary for EABI, because the first few arguments are
4427 passed in registers, but that's OK. */
4428 for (argnum
= 0; argnum
< nargs
; argnum
++)
4429 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
4430 sp
-= align_up (len
, 16);
4433 fprintf_unfiltered (gdb_stdlog
,
4434 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4435 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4437 /* Initialize the integer and float register pointers. */
4438 argreg
= MIPS_A0_REGNUM
;
4439 float_argreg
= mips_fpa0_regnum (gdbarch
);
4441 /* The struct_return pointer occupies the first parameter-passing reg. */
4445 fprintf_unfiltered (gdb_stdlog
,
4446 "mips_eabi_push_dummy_call: "
4447 "struct_return reg=%d %s\n",
4448 argreg
, paddress (gdbarch
, struct_addr
));
4449 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4452 /* Now load as many as possible of the first arguments into
4453 registers, and push the rest onto the stack. Loop thru args
4454 from first to last. */
4455 for (argnum
= 0; argnum
< nargs
; argnum
++)
4457 const gdb_byte
*val
;
4458 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4459 struct value
*arg
= args
[argnum
];
4460 struct type
*arg_type
= check_typedef (value_type (arg
));
4461 int len
= TYPE_LENGTH (arg_type
);
4462 enum type_code typecode
= TYPE_CODE (arg_type
);
4465 fprintf_unfiltered (gdb_stdlog
,
4466 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4467 argnum
+ 1, len
, (int) typecode
);
4469 /* Function pointer arguments to mips16 code need to be made into
4471 if (typecode
== TYPE_CODE_PTR
4472 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4474 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4476 if (mips_pc_is_mips (addr
))
4477 val
= value_contents (arg
);
4480 store_signed_integer (valbuf
, len
, byte_order
,
4481 make_compact_addr (addr
));
4485 /* The EABI passes structures that do not fit in a register by
4487 else if (len
> regsize
4488 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4490 store_unsigned_integer (valbuf
, regsize
, byte_order
,
4491 value_address (arg
));
4492 typecode
= TYPE_CODE_PTR
;
4496 fprintf_unfiltered (gdb_stdlog
, " push");
4499 val
= value_contents (arg
);
4501 /* 32-bit ABIs always start floating point arguments in an
4502 even-numbered floating point register. Round the FP register
4503 up before the check to see if there are any FP registers
4504 left. Non MIPS_EABI targets also pass the FP in the integer
4505 registers so also round up normal registers. */
4506 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4508 if ((float_argreg
& 1))
4512 /* Floating point arguments passed in registers have to be
4513 treated specially. On 32-bit architectures, doubles
4514 are passed in register pairs; the even register gets
4515 the low word, and the odd register gets the high word.
4516 On non-EABI processors, the first two floating point arguments are
4517 also copied to general registers, because MIPS16 functions
4518 don't use float registers for arguments. This duplication of
4519 arguments in general registers can't hurt non-MIPS16 functions
4520 because those registers are normally skipped. */
4521 /* MIPS_EABI squeezes a struct that contains a single floating
4522 point value into an FP register instead of pushing it onto the
4524 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4525 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4527 /* EABI32 will pass doubles in consecutive registers, even on
4528 64-bit cores. At one time, we used to check the size of
4529 `float_argreg' to determine whether or not to pass doubles
4530 in consecutive registers, but this is not sufficient for
4531 making the ABI determination. */
4532 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4534 int low_offset
= gdbarch_byte_order (gdbarch
)
4535 == BFD_ENDIAN_BIG
? 4 : 0;
4538 /* Write the low word of the double to the even register(s). */
4539 regval
= extract_signed_integer (val
+ low_offset
,
4542 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4543 float_argreg
, phex (regval
, 4));
4544 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4546 /* Write the high word of the double to the odd register(s). */
4547 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4550 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4551 float_argreg
, phex (regval
, 4));
4552 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4556 /* This is a floating point value that fits entirely
4557 in a single register. */
4558 /* On 32 bit ABI's the float_argreg is further adjusted
4559 above to ensure that it is even register aligned. */
4560 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4562 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4563 float_argreg
, phex (regval
, len
));
4564 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4569 /* Copy the argument to general registers or the stack in
4570 register-sized pieces. Large arguments are split between
4571 registers and stack. */
4572 /* Note: structs whose size is not a multiple of regsize
4573 are treated specially: Irix cc passes
4574 them in registers where gcc sometimes puts them on the
4575 stack. For maximum compatibility, we will put them in
4577 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
4579 /* Note: Floating-point values that didn't fit into an FP
4580 register are only written to memory. */
4583 /* Remember if the argument was written to the stack. */
4584 int stack_used_p
= 0;
4585 int partial_len
= (len
< regsize
? len
: regsize
);
4588 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4591 /* Write this portion of the argument to the stack. */
4592 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4594 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4596 /* Should shorter than int integer values be
4597 promoted to int before being stored? */
4598 int longword_offset
= 0;
4601 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4604 && (typecode
== TYPE_CODE_INT
4605 || typecode
== TYPE_CODE_PTR
4606 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4607 longword_offset
= regsize
- len
;
4608 else if ((typecode
== TYPE_CODE_STRUCT
4609 || typecode
== TYPE_CODE_UNION
)
4610 && TYPE_LENGTH (arg_type
) < regsize
)
4611 longword_offset
= regsize
- len
;
4616 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4617 paddress (gdbarch
, stack_offset
));
4618 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4619 paddress (gdbarch
, longword_offset
));
4622 addr
= sp
+ stack_offset
+ longword_offset
;
4627 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4628 paddress (gdbarch
, addr
));
4629 for (i
= 0; i
< partial_len
; i
++)
4631 fprintf_unfiltered (gdb_stdlog
, "%02x",
4635 write_memory (addr
, val
, partial_len
);
4638 /* Note!!! This is NOT an else clause. Odd sized
4639 structs may go thru BOTH paths. Floating point
4640 arguments will not. */
4641 /* Write this portion of the argument to a general
4642 purpose register. */
4643 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4644 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4647 extract_signed_integer (val
, partial_len
, byte_order
);
4650 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4652 phex (regval
, regsize
));
4653 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4660 /* Compute the offset into the stack at which we will
4661 copy the next parameter.
4663 In the new EABI (and the NABI32), the stack_offset
4664 only needs to be adjusted when it has been used. */
4667 stack_offset
+= align_up (partial_len
, regsize
);
4671 fprintf_unfiltered (gdb_stdlog
, "\n");
4674 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4676 /* Return adjusted stack pointer. */
4680 /* Determine the return value convention being used. */
4682 static enum return_value_convention
4683 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4684 struct type
*type
, struct regcache
*regcache
,
4685 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4687 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4688 int fp_return_type
= 0;
4689 int offset
, regnum
, xfer
;
4691 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4692 return RETURN_VALUE_STRUCT_CONVENTION
;
4694 /* Floating point type? */
4695 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4697 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4699 /* Structs with a single field of float type
4700 are returned in a floating point register. */
4701 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4702 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4703 && TYPE_NFIELDS (type
) == 1)
4705 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4707 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4714 /* A floating-point value belongs in the least significant part
4717 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4718 regnum
= mips_regnum (gdbarch
)->fp0
;
4722 /* An integer value goes in V0/V1. */
4724 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4725 regnum
= MIPS_V0_REGNUM
;
4728 offset
< TYPE_LENGTH (type
);
4729 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4731 xfer
= mips_abi_regsize (gdbarch
);
4732 if (offset
+ xfer
> TYPE_LENGTH (type
))
4733 xfer
= TYPE_LENGTH (type
) - offset
;
4734 mips_xfer_register (gdbarch
, regcache
,
4735 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4736 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4740 return RETURN_VALUE_REGISTER_CONVENTION
;
4744 /* N32/N64 ABI stuff. */
4746 /* Search for a naturally aligned double at OFFSET inside a struct
4747 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4751 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4756 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4759 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4762 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4765 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4768 struct type
*field_type
;
4770 /* We're only looking at normal fields. */
4771 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4772 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4775 /* If we have gone past the offset, there is no double to pass. */
4776 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4780 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4782 /* If this field is entirely before the requested offset, go
4783 on to the next one. */
4784 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4787 /* If this is our special aligned double, we can stop. */
4788 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4789 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4792 /* This field starts at or before the requested offset, and
4793 overlaps it. If it is a structure, recurse inwards. */
4794 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4801 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4802 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4803 int nargs
, struct value
**args
, CORE_ADDR sp
,
4804 int struct_return
, CORE_ADDR struct_addr
)
4810 int stack_offset
= 0;
4811 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4812 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4814 /* For shared libraries, "t9" needs to point at the function
4816 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4818 /* Set the return address register to point to the entry point of
4819 the program, where a breakpoint lies in wait. */
4820 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4822 /* First ensure that the stack and structure return address (if any)
4823 are properly aligned. The stack has to be at least 64-bit
4824 aligned even on 32-bit machines, because doubles must be 64-bit
4825 aligned. For n32 and n64, stack frames need to be 128-bit
4826 aligned, so we round to this widest known alignment. */
4828 sp
= align_down (sp
, 16);
4829 struct_addr
= align_down (struct_addr
, 16);
4831 /* Now make space on the stack for the args. */
4832 for (argnum
= 0; argnum
< nargs
; argnum
++)
4833 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4834 sp
-= align_up (len
, 16);
4837 fprintf_unfiltered (gdb_stdlog
,
4838 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4839 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4841 /* Initialize the integer and float register pointers. */
4842 argreg
= MIPS_A0_REGNUM
;
4843 float_argreg
= mips_fpa0_regnum (gdbarch
);
4845 /* The struct_return pointer occupies the first parameter-passing reg. */
4849 fprintf_unfiltered (gdb_stdlog
,
4850 "mips_n32n64_push_dummy_call: "
4851 "struct_return reg=%d %s\n",
4852 argreg
, paddress (gdbarch
, struct_addr
));
4853 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4856 /* Now load as many as possible of the first arguments into
4857 registers, and push the rest onto the stack. Loop thru args
4858 from first to last. */
4859 for (argnum
= 0; argnum
< nargs
; argnum
++)
4861 const gdb_byte
*val
;
4862 struct value
*arg
= args
[argnum
];
4863 struct type
*arg_type
= check_typedef (value_type (arg
));
4864 int len
= TYPE_LENGTH (arg_type
);
4865 enum type_code typecode
= TYPE_CODE (arg_type
);
4868 fprintf_unfiltered (gdb_stdlog
,
4869 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4870 argnum
+ 1, len
, (int) typecode
);
4872 val
= value_contents (arg
);
4874 /* A 128-bit long double value requires an even-odd pair of
4875 floating-point registers. */
4877 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4878 && (float_argreg
& 1))
4884 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4885 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4887 /* This is a floating point value that fits entirely
4888 in a single register or a pair of registers. */
4889 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4890 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4892 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4893 float_argreg
, phex (regval
, reglen
));
4894 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4897 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4898 argreg
, phex (regval
, reglen
));
4899 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4904 regval
= extract_unsigned_integer (val
+ reglen
,
4905 reglen
, byte_order
);
4907 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4908 float_argreg
, phex (regval
, reglen
));
4909 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4912 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4913 argreg
, phex (regval
, reglen
));
4914 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4921 /* Copy the argument to general registers or the stack in
4922 register-sized pieces. Large arguments are split between
4923 registers and stack. */
4924 /* For N32/N64, structs, unions, or other composite types are
4925 treated as a sequence of doublewords, and are passed in integer
4926 or floating point registers as though they were simple scalar
4927 parameters to the extent that they fit, with any excess on the
4928 stack packed according to the normal memory layout of the
4930 The caller does not reserve space for the register arguments;
4931 the callee is responsible for reserving it if required. */
4932 /* Note: Floating-point values that didn't fit into an FP
4933 register are only written to memory. */
4936 /* Remember if the argument was written to the stack. */
4937 int stack_used_p
= 0;
4938 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4941 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4944 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4945 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
4947 /* Write this portion of the argument to the stack. */
4948 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
4950 /* Should shorter than int integer values be
4951 promoted to int before being stored? */
4952 int longword_offset
= 0;
4955 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4957 if ((typecode
== TYPE_CODE_INT
4958 || typecode
== TYPE_CODE_PTR
)
4960 longword_offset
= MIPS64_REGSIZE
- len
;
4965 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4966 paddress (gdbarch
, stack_offset
));
4967 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4968 paddress (gdbarch
, longword_offset
));
4971 addr
= sp
+ stack_offset
+ longword_offset
;
4976 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4977 paddress (gdbarch
, addr
));
4978 for (i
= 0; i
< partial_len
; i
++)
4980 fprintf_unfiltered (gdb_stdlog
, "%02x",
4984 write_memory (addr
, val
, partial_len
);
4987 /* Note!!! This is NOT an else clause. Odd sized
4988 structs may go thru BOTH paths. */
4989 /* Write this portion of the argument to a general
4990 purpose register. */
4991 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4995 /* Sign extend pointers, 32-bit integers and signed
4996 16-bit and 8-bit integers; everything else is taken
4999 if ((partial_len
== 4
5000 && (typecode
== TYPE_CODE_PTR
5001 || typecode
== TYPE_CODE_INT
))
5003 && typecode
== TYPE_CODE_INT
5004 && !TYPE_UNSIGNED (arg_type
)))
5005 regval
= extract_signed_integer (val
, partial_len
,
5008 regval
= extract_unsigned_integer (val
, partial_len
,
5011 /* A non-floating-point argument being passed in a
5012 general register. If a struct or union, and if
5013 the remaining length is smaller than the register
5014 size, we have to adjust the register value on
5017 It does not seem to be necessary to do the
5018 same for integral types. */
5020 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5021 && partial_len
< MIPS64_REGSIZE
5022 && (typecode
== TYPE_CODE_STRUCT
5023 || typecode
== TYPE_CODE_UNION
))
5024 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5028 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5030 phex (regval
, MIPS64_REGSIZE
));
5031 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5033 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5034 TYPE_LENGTH (arg_type
) - len
))
5037 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5039 phex (regval
, MIPS64_REGSIZE
));
5040 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5051 /* Compute the offset into the stack at which we will
5052 copy the next parameter.
5054 In N32 (N64?), the stack_offset only needs to be
5055 adjusted when it has been used. */
5058 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5062 fprintf_unfiltered (gdb_stdlog
, "\n");
5065 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5067 /* Return adjusted stack pointer. */
5071 static enum return_value_convention
5072 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5073 struct type
*type
, struct regcache
*regcache
,
5074 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5076 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5078 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5080 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5081 if needed), as appropriate for the type. Composite results (struct,
5082 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5085 * A struct with only one or two floating point fields is returned in $f0
5086 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5089 * Any other composite results of at most 128 bits are returned in
5090 $2 (first 64 bits) and $3 (remainder, if necessary).
5092 * Larger composite results are handled by converting the function to a
5093 procedure with an implicit first parameter, which is a pointer to an area
5094 reserved by the caller to receive the result. [The o32-bit ABI requires
5095 that all composite results be handled by conversion to implicit first
5096 parameters. The MIPS/SGI Fortran implementation has always made a
5097 specific exception to return COMPLEX results in the floating point
5100 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5101 return RETURN_VALUE_STRUCT_CONVENTION
;
5102 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5103 && TYPE_LENGTH (type
) == 16
5104 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5106 /* A 128-bit floating-point value fills both $f0 and $f2. The
5107 two registers are used in the same as memory order, so the
5108 eight bytes with the lower memory address are in $f0. */
5110 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5111 mips_xfer_register (gdbarch
, regcache
,
5112 (gdbarch_num_regs (gdbarch
)
5113 + mips_regnum (gdbarch
)->fp0
),
5114 8, gdbarch_byte_order (gdbarch
),
5115 readbuf
, writebuf
, 0);
5116 mips_xfer_register (gdbarch
, regcache
,
5117 (gdbarch_num_regs (gdbarch
)
5118 + mips_regnum (gdbarch
)->fp0
+ 2),
5119 8, gdbarch_byte_order (gdbarch
),
5120 readbuf
? readbuf
+ 8 : readbuf
,
5121 writebuf
? writebuf
+ 8 : writebuf
, 0);
5122 return RETURN_VALUE_REGISTER_CONVENTION
;
5124 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5125 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5127 /* A single or double floating-point value that fits in FP0. */
5129 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5130 mips_xfer_register (gdbarch
, regcache
,
5131 (gdbarch_num_regs (gdbarch
)
5132 + mips_regnum (gdbarch
)->fp0
),
5134 gdbarch_byte_order (gdbarch
),
5135 readbuf
, writebuf
, 0);
5136 return RETURN_VALUE_REGISTER_CONVENTION
;
5138 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5139 && TYPE_NFIELDS (type
) <= 2
5140 && TYPE_NFIELDS (type
) >= 1
5141 && ((TYPE_NFIELDS (type
) == 1
5142 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5144 || (TYPE_NFIELDS (type
) == 2
5145 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5147 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
5148 == TYPE_CODE_FLT
))))
5150 /* A struct that contains one or two floats. Each value is part
5151 in the least significant part of their floating point
5152 register (or GPR, for soft float). */
5155 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5156 ? mips_regnum (gdbarch
)->fp0
5158 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5160 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5163 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5165 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5167 /* A 16-byte long double field goes in two consecutive
5169 mips_xfer_register (gdbarch
, regcache
,
5170 gdbarch_num_regs (gdbarch
) + regnum
,
5172 gdbarch_byte_order (gdbarch
),
5173 readbuf
, writebuf
, offset
);
5174 mips_xfer_register (gdbarch
, regcache
,
5175 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5177 gdbarch_byte_order (gdbarch
),
5178 readbuf
, writebuf
, offset
+ 8);
5181 mips_xfer_register (gdbarch
, regcache
,
5182 gdbarch_num_regs (gdbarch
) + regnum
,
5183 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5184 gdbarch_byte_order (gdbarch
),
5185 readbuf
, writebuf
, offset
);
5187 return RETURN_VALUE_REGISTER_CONVENTION
;
5189 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5190 || TYPE_CODE (type
) == TYPE_CODE_UNION
5191 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5193 /* A composite type. Extract the left justified value,
5194 regardless of the byte order. I.e. DO NOT USE
5198 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5199 offset
< TYPE_LENGTH (type
);
5200 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5202 int xfer
= register_size (gdbarch
, regnum
);
5203 if (offset
+ xfer
> TYPE_LENGTH (type
))
5204 xfer
= TYPE_LENGTH (type
) - offset
;
5206 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5207 offset
, xfer
, regnum
);
5208 mips_xfer_register (gdbarch
, regcache
,
5209 gdbarch_num_regs (gdbarch
) + regnum
,
5210 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5213 return RETURN_VALUE_REGISTER_CONVENTION
;
5217 /* A scalar extract each part but least-significant-byte
5221 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5222 offset
< TYPE_LENGTH (type
);
5223 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5225 int xfer
= register_size (gdbarch
, regnum
);
5226 if (offset
+ xfer
> TYPE_LENGTH (type
))
5227 xfer
= TYPE_LENGTH (type
) - offset
;
5229 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5230 offset
, xfer
, regnum
);
5231 mips_xfer_register (gdbarch
, regcache
,
5232 gdbarch_num_regs (gdbarch
) + regnum
,
5233 xfer
, gdbarch_byte_order (gdbarch
),
5234 readbuf
, writebuf
, offset
);
5236 return RETURN_VALUE_REGISTER_CONVENTION
;
5240 /* Which registers to use for passing floating-point values between
5241 function calls, one of floating-point, general and both kinds of
5242 registers. O32 and O64 use different register kinds for standard
5243 MIPS and MIPS16 code; to make the handling of cases where we may
5244 not know what kind of code is being used (e.g. no debug information)
5245 easier we sometimes use both kinds. */
5254 /* O32 ABI stuff. */
5257 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5258 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5259 int nargs
, struct value
**args
, CORE_ADDR sp
,
5260 int struct_return
, CORE_ADDR struct_addr
)
5266 int stack_offset
= 0;
5267 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5268 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5270 /* For shared libraries, "t9" needs to point at the function
5272 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5274 /* Set the return address register to point to the entry point of
5275 the program, where a breakpoint lies in wait. */
5276 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5278 /* First ensure that the stack and structure return address (if any)
5279 are properly aligned. The stack has to be at least 64-bit
5280 aligned even on 32-bit machines, because doubles must be 64-bit
5281 aligned. For n32 and n64, stack frames need to be 128-bit
5282 aligned, so we round to this widest known alignment. */
5284 sp
= align_down (sp
, 16);
5285 struct_addr
= align_down (struct_addr
, 16);
5287 /* Now make space on the stack for the args. */
5288 for (argnum
= 0; argnum
< nargs
; argnum
++)
5290 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5292 /* Align to double-word if necessary. */
5293 if (mips_type_needs_double_align (arg_type
))
5294 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5295 /* Allocate space on the stack. */
5296 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5298 sp
-= align_up (len
, 16);
5301 fprintf_unfiltered (gdb_stdlog
,
5302 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5303 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5305 /* Initialize the integer and float register pointers. */
5306 argreg
= MIPS_A0_REGNUM
;
5307 float_argreg
= mips_fpa0_regnum (gdbarch
);
5309 /* The struct_return pointer occupies the first parameter-passing reg. */
5313 fprintf_unfiltered (gdb_stdlog
,
5314 "mips_o32_push_dummy_call: "
5315 "struct_return reg=%d %s\n",
5316 argreg
, paddress (gdbarch
, struct_addr
));
5317 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5318 stack_offset
+= MIPS32_REGSIZE
;
5321 /* Now load as many as possible of the first arguments into
5322 registers, and push the rest onto the stack. Loop thru args
5323 from first to last. */
5324 for (argnum
= 0; argnum
< nargs
; argnum
++)
5326 const gdb_byte
*val
;
5327 struct value
*arg
= args
[argnum
];
5328 struct type
*arg_type
= check_typedef (value_type (arg
));
5329 int len
= TYPE_LENGTH (arg_type
);
5330 enum type_code typecode
= TYPE_CODE (arg_type
);
5333 fprintf_unfiltered (gdb_stdlog
,
5334 "mips_o32_push_dummy_call: %d len=%d type=%d",
5335 argnum
+ 1, len
, (int) typecode
);
5337 val
= value_contents (arg
);
5339 /* 32-bit ABIs always start floating point arguments in an
5340 even-numbered floating point register. Round the FP register
5341 up before the check to see if there are any FP registers
5342 left. O32 targets also pass the FP in the integer registers
5343 so also round up normal registers. */
5344 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5346 if ((float_argreg
& 1))
5350 /* Floating point arguments passed in registers have to be
5351 treated specially. On 32-bit architectures, doubles are
5352 passed in register pairs; the even FP register gets the
5353 low word, and the odd FP register gets the high word.
5354 On O32, the first two floating point arguments are also
5355 copied to general registers, following their memory order,
5356 because MIPS16 functions don't use float registers for
5357 arguments. This duplication of arguments in general
5358 registers can't hurt non-MIPS16 functions, because those
5359 registers are normally skipped. */
5361 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5362 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5364 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5366 int freg_offset
= gdbarch_byte_order (gdbarch
)
5367 == BFD_ENDIAN_BIG
? 1 : 0;
5368 unsigned long regval
;
5371 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5373 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5374 float_argreg
+ freg_offset
,
5376 regcache_cooked_write_unsigned (regcache
,
5377 float_argreg
++ + freg_offset
,
5380 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5381 argreg
, phex (regval
, 4));
5382 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5385 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5387 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5388 float_argreg
- freg_offset
,
5390 regcache_cooked_write_unsigned (regcache
,
5391 float_argreg
++ - freg_offset
,
5394 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5395 argreg
, phex (regval
, 4));
5396 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5400 /* This is a floating point value that fits entirely
5401 in a single register. */
5402 /* On 32 bit ABI's the float_argreg is further adjusted
5403 above to ensure that it is even register aligned. */
5404 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5406 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5407 float_argreg
, phex (regval
, len
));
5408 regcache_cooked_write_unsigned (regcache
,
5409 float_argreg
++, regval
);
5410 /* Although two FP registers are reserved for each
5411 argument, only one corresponding integer register is
5414 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5415 argreg
, phex (regval
, len
));
5416 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5418 /* Reserve space for the FP register. */
5419 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5423 /* Copy the argument to general registers or the stack in
5424 register-sized pieces. Large arguments are split between
5425 registers and stack. */
5426 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5427 are treated specially: Irix cc passes
5428 them in registers where gcc sometimes puts them on the
5429 stack. For maximum compatibility, we will put them in
5431 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5432 && len
% MIPS32_REGSIZE
!= 0);
5433 /* Structures should be aligned to eight bytes (even arg registers)
5434 on MIPS_ABI_O32, if their first member has double precision. */
5435 if (mips_type_needs_double_align (arg_type
))
5440 stack_offset
+= MIPS32_REGSIZE
;
5445 /* Remember if the argument was written to the stack. */
5446 int stack_used_p
= 0;
5447 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5450 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5453 /* Write this portion of the argument to the stack. */
5454 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5455 || odd_sized_struct
)
5457 /* Should shorter than int integer values be
5458 promoted to int before being stored? */
5459 int longword_offset
= 0;
5465 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5466 paddress (gdbarch
, stack_offset
));
5467 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5468 paddress (gdbarch
, longword_offset
));
5471 addr
= sp
+ stack_offset
+ longword_offset
;
5476 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5477 paddress (gdbarch
, addr
));
5478 for (i
= 0; i
< partial_len
; i
++)
5480 fprintf_unfiltered (gdb_stdlog
, "%02x",
5484 write_memory (addr
, val
, partial_len
);
5487 /* Note!!! This is NOT an else clause. Odd sized
5488 structs may go thru BOTH paths. */
5489 /* Write this portion of the argument to a general
5490 purpose register. */
5491 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5493 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5495 /* Value may need to be sign extended, because
5496 mips_isa_regsize() != mips_abi_regsize(). */
5498 /* A non-floating-point argument being passed in a
5499 general register. If a struct or union, and if
5500 the remaining length is smaller than the register
5501 size, we have to adjust the register value on
5504 It does not seem to be necessary to do the
5505 same for integral types.
5507 Also don't do this adjustment on O64 binaries.
5509 cagney/2001-07-23: gdb/179: Also, GCC, when
5510 outputting LE O32 with sizeof (struct) <
5511 mips_abi_regsize(), generates a left shift
5512 as part of storing the argument in a register
5513 (the left shift isn't generated when
5514 sizeof (struct) >= mips_abi_regsize()). Since
5515 it is quite possible that this is GCC
5516 contradicting the LE/O32 ABI, GDB has not been
5517 adjusted to accommodate this. Either someone
5518 needs to demonstrate that the LE/O32 ABI
5519 specifies such a left shift OR this new ABI gets
5520 identified as such and GDB gets tweaked
5523 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5524 && partial_len
< MIPS32_REGSIZE
5525 && (typecode
== TYPE_CODE_STRUCT
5526 || typecode
== TYPE_CODE_UNION
))
5527 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5531 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5533 phex (regval
, MIPS32_REGSIZE
));
5534 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5537 /* Prevent subsequent floating point arguments from
5538 being passed in floating point registers. */
5539 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5545 /* Compute the offset into the stack at which we will
5546 copy the next parameter.
5548 In older ABIs, the caller reserved space for
5549 registers that contained arguments. This was loosely
5550 refered to as their "home". Consequently, space is
5551 always allocated. */
5553 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5557 fprintf_unfiltered (gdb_stdlog
, "\n");
5560 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5562 /* Return adjusted stack pointer. */
5566 static enum return_value_convention
5567 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5568 struct type
*type
, struct regcache
*regcache
,
5569 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5571 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5572 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5573 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5574 enum mips_fval_reg fval_reg
;
5576 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5577 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5578 || TYPE_CODE (type
) == TYPE_CODE_UNION
5579 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5580 return RETURN_VALUE_STRUCT_CONVENTION
;
5581 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5582 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5584 /* A single-precision floating-point value. If reading in or copying,
5585 then we get it from/put it to FP0 for standard MIPS code or GPR2
5586 for MIPS16 code. If writing out only, then we put it to both FP0
5587 and GPR2. We do not support reading in with no function known, if
5588 this safety check ever triggers, then we'll have to try harder. */
5589 gdb_assert (function
|| !readbuf
);
5594 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5597 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5599 case mips_fval_both
:
5600 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5603 if (fval_reg
!= mips_fval_gpr
)
5604 mips_xfer_register (gdbarch
, regcache
,
5605 (gdbarch_num_regs (gdbarch
)
5606 + mips_regnum (gdbarch
)->fp0
),
5608 gdbarch_byte_order (gdbarch
),
5609 readbuf
, writebuf
, 0);
5610 if (fval_reg
!= mips_fval_fpr
)
5611 mips_xfer_register (gdbarch
, regcache
,
5612 gdbarch_num_regs (gdbarch
) + 2,
5614 gdbarch_byte_order (gdbarch
),
5615 readbuf
, writebuf
, 0);
5616 return RETURN_VALUE_REGISTER_CONVENTION
;
5618 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5619 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5621 /* A double-precision floating-point value. If reading in or copying,
5622 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5623 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5624 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5625 no function known, if this safety check ever triggers, then we'll
5626 have to try harder. */
5627 gdb_assert (function
|| !readbuf
);
5632 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5635 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5637 case mips_fval_both
:
5638 fprintf_unfiltered (gdb_stderr
,
5639 "Return float in $fp1/$fp0 and $2/$3\n");
5642 if (fval_reg
!= mips_fval_gpr
)
5644 /* The most significant part goes in FP1, and the least significant
5646 switch (gdbarch_byte_order (gdbarch
))
5648 case BFD_ENDIAN_LITTLE
:
5649 mips_xfer_register (gdbarch
, regcache
,
5650 (gdbarch_num_regs (gdbarch
)
5651 + mips_regnum (gdbarch
)->fp0
+ 0),
5652 4, gdbarch_byte_order (gdbarch
),
5653 readbuf
, writebuf
, 0);
5654 mips_xfer_register (gdbarch
, regcache
,
5655 (gdbarch_num_regs (gdbarch
)
5656 + mips_regnum (gdbarch
)->fp0
+ 1),
5657 4, gdbarch_byte_order (gdbarch
),
5658 readbuf
, writebuf
, 4);
5660 case BFD_ENDIAN_BIG
:
5661 mips_xfer_register (gdbarch
, regcache
,
5662 (gdbarch_num_regs (gdbarch
)
5663 + mips_regnum (gdbarch
)->fp0
+ 1),
5664 4, gdbarch_byte_order (gdbarch
),
5665 readbuf
, writebuf
, 0);
5666 mips_xfer_register (gdbarch
, regcache
,
5667 (gdbarch_num_regs (gdbarch
)
5668 + mips_regnum (gdbarch
)->fp0
+ 0),
5669 4, gdbarch_byte_order (gdbarch
),
5670 readbuf
, writebuf
, 4);
5673 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5676 if (fval_reg
!= mips_fval_fpr
)
5678 /* The two 32-bit parts are always placed in GPR2 and GPR3
5679 following these registers' memory order. */
5680 mips_xfer_register (gdbarch
, regcache
,
5681 gdbarch_num_regs (gdbarch
) + 2,
5682 4, gdbarch_byte_order (gdbarch
),
5683 readbuf
, writebuf
, 0);
5684 mips_xfer_register (gdbarch
, regcache
,
5685 gdbarch_num_regs (gdbarch
) + 3,
5686 4, gdbarch_byte_order (gdbarch
),
5687 readbuf
, writebuf
, 4);
5689 return RETURN_VALUE_REGISTER_CONVENTION
;
5692 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5693 && TYPE_NFIELDS (type
) <= 2
5694 && TYPE_NFIELDS (type
) >= 1
5695 && ((TYPE_NFIELDS (type
) == 1
5696 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5698 || (TYPE_NFIELDS (type
) == 2
5699 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5701 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5703 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5705 /* A struct that contains one or two floats. Each value is part
5706 in the least significant part of their floating point
5708 gdb_byte reg
[MAX_REGISTER_SIZE
];
5711 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5712 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5714 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5717 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5719 mips_xfer_register (gdbarch
, regcache
,
5720 gdbarch_num_regs (gdbarch
) + regnum
,
5721 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5722 gdbarch_byte_order (gdbarch
),
5723 readbuf
, writebuf
, offset
);
5725 return RETURN_VALUE_REGISTER_CONVENTION
;
5729 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5730 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5732 /* A structure or union. Extract the left justified value,
5733 regardless of the byte order. I.e. DO NOT USE
5737 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5738 offset
< TYPE_LENGTH (type
);
5739 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5741 int xfer
= register_size (gdbarch
, regnum
);
5742 if (offset
+ xfer
> TYPE_LENGTH (type
))
5743 xfer
= TYPE_LENGTH (type
) - offset
;
5745 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5746 offset
, xfer
, regnum
);
5747 mips_xfer_register (gdbarch
, regcache
,
5748 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5749 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5751 return RETURN_VALUE_REGISTER_CONVENTION
;
5756 /* A scalar extract each part but least-significant-byte
5757 justified. o32 thinks registers are 4 byte, regardless of
5761 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5762 offset
< TYPE_LENGTH (type
);
5763 offset
+= MIPS32_REGSIZE
, regnum
++)
5765 int xfer
= MIPS32_REGSIZE
;
5766 if (offset
+ xfer
> TYPE_LENGTH (type
))
5767 xfer
= TYPE_LENGTH (type
) - offset
;
5769 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5770 offset
, xfer
, regnum
);
5771 mips_xfer_register (gdbarch
, regcache
,
5772 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5773 gdbarch_byte_order (gdbarch
),
5774 readbuf
, writebuf
, offset
);
5776 return RETURN_VALUE_REGISTER_CONVENTION
;
5780 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5784 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5785 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5787 struct value
**args
, CORE_ADDR sp
,
5788 int struct_return
, CORE_ADDR struct_addr
)
5794 int stack_offset
= 0;
5795 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5796 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5798 /* For shared libraries, "t9" needs to point at the function
5800 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5802 /* Set the return address register to point to the entry point of
5803 the program, where a breakpoint lies in wait. */
5804 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5806 /* First ensure that the stack and structure return address (if any)
5807 are properly aligned. The stack has to be at least 64-bit
5808 aligned even on 32-bit machines, because doubles must be 64-bit
5809 aligned. For n32 and n64, stack frames need to be 128-bit
5810 aligned, so we round to this widest known alignment. */
5812 sp
= align_down (sp
, 16);
5813 struct_addr
= align_down (struct_addr
, 16);
5815 /* Now make space on the stack for the args. */
5816 for (argnum
= 0; argnum
< nargs
; argnum
++)
5818 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5820 /* Allocate space on the stack. */
5821 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5823 sp
-= align_up (len
, 16);
5826 fprintf_unfiltered (gdb_stdlog
,
5827 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5828 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5830 /* Initialize the integer and float register pointers. */
5831 argreg
= MIPS_A0_REGNUM
;
5832 float_argreg
= mips_fpa0_regnum (gdbarch
);
5834 /* The struct_return pointer occupies the first parameter-passing reg. */
5838 fprintf_unfiltered (gdb_stdlog
,
5839 "mips_o64_push_dummy_call: "
5840 "struct_return reg=%d %s\n",
5841 argreg
, paddress (gdbarch
, struct_addr
));
5842 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5843 stack_offset
+= MIPS64_REGSIZE
;
5846 /* Now load as many as possible of the first arguments into
5847 registers, and push the rest onto the stack. Loop thru args
5848 from first to last. */
5849 for (argnum
= 0; argnum
< nargs
; argnum
++)
5851 const gdb_byte
*val
;
5852 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
5853 struct value
*arg
= args
[argnum
];
5854 struct type
*arg_type
= check_typedef (value_type (arg
));
5855 int len
= TYPE_LENGTH (arg_type
);
5856 enum type_code typecode
= TYPE_CODE (arg_type
);
5859 fprintf_unfiltered (gdb_stdlog
,
5860 "mips_o64_push_dummy_call: %d len=%d type=%d",
5861 argnum
+ 1, len
, (int) typecode
);
5863 val
= value_contents (arg
);
5865 /* Function pointer arguments to mips16 code need to be made into
5867 if (typecode
== TYPE_CODE_PTR
5868 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
5870 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
5872 if (!mips_pc_is_mips (addr
))
5874 store_signed_integer (valbuf
, len
, byte_order
,
5875 make_compact_addr (addr
));
5880 /* Floating point arguments passed in registers have to be
5881 treated specially. On 32-bit architectures, doubles are
5882 passed in register pairs; the even FP register gets the
5883 low word, and the odd FP register gets the high word.
5884 On O64, the first two floating point arguments are also
5885 copied to general registers, because MIPS16 functions
5886 don't use float registers for arguments. This duplication
5887 of arguments in general registers can't hurt non-MIPS16
5888 functions because those registers are normally skipped. */
5890 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5891 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5893 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5895 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5896 float_argreg
, phex (regval
, len
));
5897 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5899 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5900 argreg
, phex (regval
, len
));
5901 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5903 /* Reserve space for the FP register. */
5904 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5908 /* Copy the argument to general registers or the stack in
5909 register-sized pieces. Large arguments are split between
5910 registers and stack. */
5911 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5912 are treated specially: Irix cc passes them in registers
5913 where gcc sometimes puts them on the stack. For maximum
5914 compatibility, we will put them in both places. */
5915 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5916 && len
% MIPS64_REGSIZE
!= 0);
5919 /* Remember if the argument was written to the stack. */
5920 int stack_used_p
= 0;
5921 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5924 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5927 /* Write this portion of the argument to the stack. */
5928 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5929 || odd_sized_struct
)
5931 /* Should shorter than int integer values be
5932 promoted to int before being stored? */
5933 int longword_offset
= 0;
5936 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5938 if ((typecode
== TYPE_CODE_INT
5939 || typecode
== TYPE_CODE_PTR
5940 || typecode
== TYPE_CODE_FLT
)
5942 longword_offset
= MIPS64_REGSIZE
- len
;
5947 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5948 paddress (gdbarch
, stack_offset
));
5949 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5950 paddress (gdbarch
, longword_offset
));
5953 addr
= sp
+ stack_offset
+ longword_offset
;
5958 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5959 paddress (gdbarch
, addr
));
5960 for (i
= 0; i
< partial_len
; i
++)
5962 fprintf_unfiltered (gdb_stdlog
, "%02x",
5966 write_memory (addr
, val
, partial_len
);
5969 /* Note!!! This is NOT an else clause. Odd sized
5970 structs may go thru BOTH paths. */
5971 /* Write this portion of the argument to a general
5972 purpose register. */
5973 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5975 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5977 /* Value may need to be sign extended, because
5978 mips_isa_regsize() != mips_abi_regsize(). */
5980 /* A non-floating-point argument being passed in a
5981 general register. If a struct or union, and if
5982 the remaining length is smaller than the register
5983 size, we have to adjust the register value on
5986 It does not seem to be necessary to do the
5987 same for integral types. */
5989 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5990 && partial_len
< MIPS64_REGSIZE
5991 && (typecode
== TYPE_CODE_STRUCT
5992 || typecode
== TYPE_CODE_UNION
))
5993 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5997 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5999 phex (regval
, MIPS64_REGSIZE
));
6000 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6003 /* Prevent subsequent floating point arguments from
6004 being passed in floating point registers. */
6005 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
6011 /* Compute the offset into the stack at which we will
6012 copy the next parameter.
6014 In older ABIs, the caller reserved space for
6015 registers that contained arguments. This was loosely
6016 refered to as their "home". Consequently, space is
6017 always allocated. */
6019 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6023 fprintf_unfiltered (gdb_stdlog
, "\n");
6026 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6028 /* Return adjusted stack pointer. */
6032 static enum return_value_convention
6033 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6034 struct type
*type
, struct regcache
*regcache
,
6035 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6037 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6038 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6039 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6040 enum mips_fval_reg fval_reg
;
6042 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6043 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
6044 || TYPE_CODE (type
) == TYPE_CODE_UNION
6045 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
6046 return RETURN_VALUE_STRUCT_CONVENTION
;
6047 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
6049 /* A floating-point value. If reading in or copying, then we get it
6050 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6051 If writing out only, then we put it to both FP0 and GPR2. We do
6052 not support reading in with no function known, if this safety
6053 check ever triggers, then we'll have to try harder. */
6054 gdb_assert (function
|| !readbuf
);
6059 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6062 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6064 case mips_fval_both
:
6065 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6068 if (fval_reg
!= mips_fval_gpr
)
6069 mips_xfer_register (gdbarch
, regcache
,
6070 (gdbarch_num_regs (gdbarch
)
6071 + mips_regnum (gdbarch
)->fp0
),
6073 gdbarch_byte_order (gdbarch
),
6074 readbuf
, writebuf
, 0);
6075 if (fval_reg
!= mips_fval_fpr
)
6076 mips_xfer_register (gdbarch
, regcache
,
6077 gdbarch_num_regs (gdbarch
) + 2,
6079 gdbarch_byte_order (gdbarch
),
6080 readbuf
, writebuf
, 0);
6081 return RETURN_VALUE_REGISTER_CONVENTION
;
6085 /* A scalar extract each part but least-significant-byte
6089 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6090 offset
< TYPE_LENGTH (type
);
6091 offset
+= MIPS64_REGSIZE
, regnum
++)
6093 int xfer
= MIPS64_REGSIZE
;
6094 if (offset
+ xfer
> TYPE_LENGTH (type
))
6095 xfer
= TYPE_LENGTH (type
) - offset
;
6097 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6098 offset
, xfer
, regnum
);
6099 mips_xfer_register (gdbarch
, regcache
,
6100 gdbarch_num_regs (gdbarch
) + regnum
,
6101 xfer
, gdbarch_byte_order (gdbarch
),
6102 readbuf
, writebuf
, offset
);
6104 return RETURN_VALUE_REGISTER_CONVENTION
;
6108 /* Floating point register management.
6110 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6111 64bit operations, these early MIPS cpus treat fp register pairs
6112 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6113 registers and offer a compatibility mode that emulates the MIPS2 fp
6114 model. When operating in MIPS2 fp compat mode, later cpu's split
6115 double precision floats into two 32-bit chunks and store them in
6116 consecutive fp regs. To display 64-bit floats stored in this
6117 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6118 Throw in user-configurable endianness and you have a real mess.
6120 The way this works is:
6121 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6122 double-precision value will be split across two logical registers.
6123 The lower-numbered logical register will hold the low-order bits,
6124 regardless of the processor's endianness.
6125 - If we are on a 64-bit processor, and we are looking for a
6126 single-precision value, it will be in the low ordered bits
6127 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6128 save slot in memory.
6129 - If we are in 64-bit mode, everything is straightforward.
6131 Note that this code only deals with "live" registers at the top of the
6132 stack. We will attempt to deal with saved registers later, when
6133 the raw/cooked register interface is in place. (We need a general
6134 interface that can deal with dynamic saved register sizes -- fp
6135 regs could be 32 bits wide in one frame and 64 on the frame above
6138 /* Copy a 32-bit single-precision value from the current frame
6139 into rare_buffer. */
6142 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6143 gdb_byte
*rare_buffer
)
6145 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6146 int raw_size
= register_size (gdbarch
, regno
);
6147 gdb_byte
*raw_buffer
= alloca (raw_size
);
6149 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6150 error (_("can't read register %d (%s)"),
6151 regno
, gdbarch_register_name (gdbarch
, regno
));
6154 /* We have a 64-bit value for this register. Find the low-order
6158 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6163 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6167 memcpy (rare_buffer
, raw_buffer
, 4);
6171 /* Copy a 64-bit double-precision value from the current frame into
6172 rare_buffer. This may include getting half of it from the next
6176 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6177 gdb_byte
*rare_buffer
)
6179 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6180 int raw_size
= register_size (gdbarch
, regno
);
6182 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6184 /* We have a 64-bit value for this register, and we should use
6186 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6187 error (_("can't read register %d (%s)"),
6188 regno
, gdbarch_register_name (gdbarch
, regno
));
6192 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6194 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6195 internal_error (__FILE__
, __LINE__
,
6196 _("mips_read_fp_register_double: bad access to "
6197 "odd-numbered FP register"));
6199 /* mips_read_fp_register_single will find the correct 32 bits from
6201 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6203 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6204 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6208 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6209 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6215 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6217 { /* Do values for FP (float) regs. */
6218 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6219 gdb_byte
*raw_buffer
;
6220 double doub
, flt1
; /* Doubles extracted from raw hex data. */
6223 raw_buffer
= alloca (2 * register_size (gdbarch
,
6224 mips_regnum (gdbarch
)->fp0
));
6226 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6227 fprintf_filtered (file
, "%*s",
6228 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6231 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6233 struct value_print_options opts
;
6235 /* 4-byte registers: Print hex and floating. Also print even
6236 numbered registers as doubles. */
6237 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6238 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6241 get_formatted_print_options (&opts
, 'x');
6242 print_scalar_formatted (raw_buffer
,
6243 builtin_type (gdbarch
)->builtin_uint32
,
6246 fprintf_filtered (file
, " flt: ");
6248 fprintf_filtered (file
, " <invalid float> ");
6250 fprintf_filtered (file
, "%-17.9g", flt1
);
6252 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6254 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6255 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6258 fprintf_filtered (file
, " dbl: ");
6260 fprintf_filtered (file
, "<invalid double>");
6262 fprintf_filtered (file
, "%-24.17g", doub
);
6267 struct value_print_options opts
;
6269 /* Eight byte registers: print each one as hex, float and double. */
6270 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6271 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6274 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6275 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6278 get_formatted_print_options (&opts
, 'x');
6279 print_scalar_formatted (raw_buffer
,
6280 builtin_type (gdbarch
)->builtin_uint64
,
6283 fprintf_filtered (file
, " flt: ");
6285 fprintf_filtered (file
, "<invalid float>");
6287 fprintf_filtered (file
, "%-17.9g", flt1
);
6289 fprintf_filtered (file
, " dbl: ");
6291 fprintf_filtered (file
, "<invalid double>");
6293 fprintf_filtered (file
, "%-24.17g", doub
);
6298 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6301 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6302 struct value_print_options opts
;
6305 if (mips_float_register_p (gdbarch
, regnum
))
6307 mips_print_fp_register (file
, frame
, regnum
);
6311 val
= get_frame_register_value (frame
, regnum
);
6313 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6315 /* The problem with printing numeric register names (r26, etc.) is that
6316 the user can't use them on input. Probably the best solution is to
6317 fix it so that either the numeric or the funky (a2, etc.) names
6318 are accepted on input. */
6319 if (regnum
< MIPS_NUMREGS
)
6320 fprintf_filtered (file
, "(r%d): ", regnum
);
6322 fprintf_filtered (file
, ": ");
6324 get_formatted_print_options (&opts
, 'x');
6325 val_print_scalar_formatted (value_type (val
),
6326 value_contents_for_printing (val
),
6327 value_embedded_offset (val
),
6332 /* Replacement for generic do_registers_info.
6333 Print regs in pretty columns. */
6336 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6339 fprintf_filtered (file
, " ");
6340 mips_print_fp_register (file
, frame
, regnum
);
6341 fprintf_filtered (file
, "\n");
6346 /* Print a row's worth of GP (int) registers, with name labels above. */
6349 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6352 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6353 /* Do values for GP (int) regs. */
6354 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
6355 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6360 /* For GP registers, we print a separate row of names above the vals. */
6361 for (col
= 0, regnum
= start_regnum
;
6362 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6363 + gdbarch_num_pseudo_regs (gdbarch
);
6366 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6367 continue; /* unused register */
6368 if (mips_float_register_p (gdbarch
, regnum
))
6369 break; /* End the row: reached FP register. */
6370 /* Large registers are handled separately. */
6371 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6374 break; /* End the row before this register. */
6376 /* Print this register on a row by itself. */
6377 mips_print_register (file
, frame
, regnum
);
6378 fprintf_filtered (file
, "\n");
6382 fprintf_filtered (file
, " ");
6383 fprintf_filtered (file
,
6384 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6385 gdbarch_register_name (gdbarch
, regnum
));
6392 /* Print the R0 to R31 names. */
6393 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6394 fprintf_filtered (file
, "\n R%-4d",
6395 start_regnum
% gdbarch_num_regs (gdbarch
));
6397 fprintf_filtered (file
, "\n ");
6399 /* Now print the values in hex, 4 or 8 to the row. */
6400 for (col
= 0, regnum
= start_regnum
;
6401 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6402 + gdbarch_num_pseudo_regs (gdbarch
);
6405 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6406 continue; /* unused register */
6407 if (mips_float_register_p (gdbarch
, regnum
))
6408 break; /* End row: reached FP register. */
6409 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6410 break; /* End row: large register. */
6412 /* OK: get the data in raw format. */
6413 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
6414 error (_("can't read register %d (%s)"),
6415 regnum
, gdbarch_register_name (gdbarch
, regnum
));
6416 /* pad small registers */
6418 byte
< (mips_abi_regsize (gdbarch
)
6419 - register_size (gdbarch
, regnum
)); byte
++)
6420 printf_filtered (" ");
6421 /* Now print the register value in hex, endian order. */
6422 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6424 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6425 byte
< register_size (gdbarch
, regnum
); byte
++)
6426 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6428 for (byte
= register_size (gdbarch
, regnum
) - 1;
6430 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6431 fprintf_filtered (file
, " ");
6434 if (col
> 0) /* ie. if we actually printed anything... */
6435 fprintf_filtered (file
, "\n");
6440 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6443 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6444 struct frame_info
*frame
, int regnum
, int all
)
6446 if (regnum
!= -1) /* Do one specified register. */
6448 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6449 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6450 error (_("Not a valid register for the current processor type"));
6452 mips_print_register (file
, frame
, regnum
);
6453 fprintf_filtered (file
, "\n");
6456 /* Do all (or most) registers. */
6458 regnum
= gdbarch_num_regs (gdbarch
);
6459 while (regnum
< gdbarch_num_regs (gdbarch
)
6460 + gdbarch_num_pseudo_regs (gdbarch
))
6462 if (mips_float_register_p (gdbarch
, regnum
))
6464 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6465 regnum
= print_fp_register_row (file
, frame
, regnum
);
6467 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6470 regnum
= print_gp_register_row (file
, frame
, regnum
);
6476 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6477 struct frame_info
*frame
)
6479 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6480 CORE_ADDR pc
= get_frame_pc (frame
);
6481 struct address_space
*aspace
;
6487 if ((mips_pc_is_mips (pc
)
6488 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6489 || (mips_pc_is_micromips (gdbarch
, pc
)
6490 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6491 || (mips_pc_is_mips16 (gdbarch
, pc
)
6492 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6495 isa
= mips_pc_isa (gdbarch
, pc
);
6496 /* _has_delay_slot above will have validated the read. */
6497 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6498 size
= mips_insn_size (isa
, insn
);
6499 aspace
= get_frame_address_space (frame
);
6500 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6503 /* To skip prologues, I use this predicate. Returns either PC itself
6504 if the code at PC does not look like a function prologue; otherwise
6505 returns an address that (if we're lucky) follows the prologue. If
6506 LENIENT, then we must skip everything which is involved in setting
6507 up the frame (it's OK to skip more, just so long as we don't skip
6508 anything which might clobber the registers which are being saved.
6509 We must skip more in the case where part of the prologue is in the
6510 delay slot of a non-prologue instruction). */
6513 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6516 CORE_ADDR func_addr
;
6518 /* See if we can determine the end of the prologue via the symbol table.
6519 If so, then return either PC, or the PC after the prologue, whichever
6521 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6523 CORE_ADDR post_prologue_pc
6524 = skip_prologue_using_sal (gdbarch
, func_addr
);
6525 if (post_prologue_pc
!= 0)
6526 return max (pc
, post_prologue_pc
);
6529 /* Can't determine prologue from the symbol table, need to examine
6532 /* Find an upper limit on the function prologue using the debug
6533 information. If the debug information could not be used to provide
6534 that bound, then use an arbitrary large number as the upper bound. */
6535 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6537 limit_pc
= pc
+ 100; /* Magic. */
6539 if (mips_pc_is_mips16 (gdbarch
, pc
))
6540 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6541 else if (mips_pc_is_micromips (gdbarch
, pc
))
6542 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6544 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6547 /* Check whether the PC is in a function epilogue (32-bit version).
6548 This is a helper function for mips_in_function_epilogue_p. */
6550 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6552 CORE_ADDR func_addr
= 0, func_end
= 0;
6554 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6556 /* The MIPS epilogue is max. 12 bytes long. */
6557 CORE_ADDR addr
= func_end
- 12;
6559 if (addr
< func_addr
+ 4)
6560 addr
= func_addr
+ 4;
6564 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6566 unsigned long high_word
;
6569 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6570 high_word
= (inst
>> 16) & 0xffff;
6572 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6573 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6574 && inst
!= 0x03e00008 /* jr $ra */
6575 && inst
!= 0x00000000) /* nop */
6585 /* Check whether the PC is in a function epilogue (microMIPS version).
6586 This is a helper function for mips_in_function_epilogue_p. */
6589 micromips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6591 CORE_ADDR func_addr
= 0;
6592 CORE_ADDR func_end
= 0;
6600 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6603 /* The microMIPS epilogue is max. 12 bytes long. */
6604 addr
= func_end
- 12;
6606 if (addr
< func_addr
+ 2)
6607 addr
= func_addr
+ 2;
6611 for (; pc
< func_end
; pc
+= loc
)
6614 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6615 loc
+= MIPS_INSN16_SIZE
;
6616 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6618 /* 48-bit instructions. */
6619 case 3 * MIPS_INSN16_SIZE
:
6620 /* No epilogue instructions in this category. */
6623 /* 32-bit instructions. */
6624 case 2 * MIPS_INSN16_SIZE
:
6626 insn
|= mips_fetch_instruction (gdbarch
,
6627 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6628 loc
+= MIPS_INSN16_SIZE
;
6629 switch (micromips_op (insn
>> 16))
6631 case 0xc: /* ADDIU: bits 001100 */
6632 case 0x17: /* DADDIU: bits 010111 */
6633 sreg
= b0s5_reg (insn
>> 16);
6634 dreg
= b5s5_reg (insn
>> 16);
6635 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6636 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6637 /* (D)ADDIU $sp, imm */
6647 /* 16-bit instructions. */
6648 case MIPS_INSN16_SIZE
:
6649 switch (micromips_op (insn
))
6651 case 0x3: /* MOVE: bits 000011 */
6652 sreg
= b0s5_reg (insn
);
6653 dreg
= b5s5_reg (insn
);
6654 if (sreg
== 0 && dreg
== 0)
6655 /* MOVE $zero, $zero aka NOP */
6659 case 0x11: /* POOL16C: bits 010001 */
6660 if (b5s5_op (insn
) == 0x18
6661 /* JRADDIUSP: bits 010011 11000 */
6662 || (b5s5_op (insn
) == 0xd
6663 /* JRC: bits 010011 01101 */
6664 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6669 case 0x13: /* POOL16D: bits 010011 */
6670 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6671 if ((insn
& 0x1) == 0x1
6672 /* ADDIUSP: bits 010011 1 */
6686 /* Check whether the PC is in a function epilogue (16-bit version).
6687 This is a helper function for mips_in_function_epilogue_p. */
6689 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6691 CORE_ADDR func_addr
= 0, func_end
= 0;
6693 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6695 /* The MIPS epilogue is max. 12 bytes long. */
6696 CORE_ADDR addr
= func_end
- 12;
6698 if (addr
< func_addr
+ 4)
6699 addr
= func_addr
+ 4;
6703 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6705 unsigned short inst
;
6707 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6709 if ((inst
& 0xf800) == 0xf000) /* extend */
6712 if (inst
!= 0x6300 /* addiu $sp,offset */
6713 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6714 && inst
!= 0xe820 /* jr $ra */
6715 && inst
!= 0xe8a0 /* jrc $ra */
6716 && inst
!= 0x6500) /* nop */
6726 /* The epilogue is defined here as the area at the end of a function,
6727 after an instruction which destroys the function's stack frame. */
6729 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6731 if (mips_pc_is_mips16 (gdbarch
, pc
))
6732 return mips16_in_function_epilogue_p (gdbarch
, pc
);
6733 else if (mips_pc_is_micromips (gdbarch
, pc
))
6734 return micromips_in_function_epilogue_p (gdbarch
, pc
);
6736 return mips32_in_function_epilogue_p (gdbarch
, pc
);
6739 /* Root of all "set mips "/"show mips " commands. This will eventually be
6740 used for all MIPS-specific commands. */
6743 show_mips_command (char *args
, int from_tty
)
6745 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6749 set_mips_command (char *args
, int from_tty
)
6752 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6753 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6756 /* Commands to show/set the MIPS FPU type. */
6759 show_mipsfpu_command (char *args
, int from_tty
)
6763 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6766 ("The MIPS floating-point coprocessor is unknown "
6767 "because the current architecture is not MIPS.\n");
6771 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6773 case MIPS_FPU_SINGLE
:
6774 fpu
= "single-precision";
6776 case MIPS_FPU_DOUBLE
:
6777 fpu
= "double-precision";
6780 fpu
= "absent (none)";
6783 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6785 if (mips_fpu_type_auto
)
6786 printf_unfiltered ("The MIPS floating-point coprocessor "
6787 "is set automatically (currently %s)\n",
6791 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6796 set_mipsfpu_command (char *args
, int from_tty
)
6798 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6799 "\"single\",\"none\" or \"auto\".\n");
6800 show_mipsfpu_command (args
, from_tty
);
6804 set_mipsfpu_single_command (char *args
, int from_tty
)
6806 struct gdbarch_info info
;
6807 gdbarch_info_init (&info
);
6808 mips_fpu_type
= MIPS_FPU_SINGLE
;
6809 mips_fpu_type_auto
= 0;
6810 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6811 instead of relying on globals. Doing that would let generic code
6812 handle the search for this specific architecture. */
6813 if (!gdbarch_update_p (info
))
6814 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6818 set_mipsfpu_double_command (char *args
, int from_tty
)
6820 struct gdbarch_info info
;
6821 gdbarch_info_init (&info
);
6822 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6823 mips_fpu_type_auto
= 0;
6824 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6825 instead of relying on globals. Doing that would let generic code
6826 handle the search for this specific architecture. */
6827 if (!gdbarch_update_p (info
))
6828 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6832 set_mipsfpu_none_command (char *args
, int from_tty
)
6834 struct gdbarch_info info
;
6835 gdbarch_info_init (&info
);
6836 mips_fpu_type
= MIPS_FPU_NONE
;
6837 mips_fpu_type_auto
= 0;
6838 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6839 instead of relying on globals. Doing that would let generic code
6840 handle the search for this specific architecture. */
6841 if (!gdbarch_update_p (info
))
6842 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6846 set_mipsfpu_auto_command (char *args
, int from_tty
)
6848 mips_fpu_type_auto
= 1;
6851 /* Attempt to identify the particular processor model by reading the
6852 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
6853 the relevant processor still exists (it dates back to '94) and
6854 secondly this is not the way to do this. The processor type should
6855 be set by forcing an architecture change. */
6858 deprecated_mips_set_processor_regs_hack (void)
6860 struct regcache
*regcache
= get_current_regcache ();
6861 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6862 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6865 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
6866 if ((prid
& ~0xf) == 0x700)
6867 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
6870 /* Just like reinit_frame_cache, but with the right arguments to be
6871 callable as an sfunc. */
6874 reinit_frame_cache_sfunc (char *args
, int from_tty
,
6875 struct cmd_list_element
*c
)
6877 reinit_frame_cache ();
6881 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6883 struct gdbarch
*gdbarch
= info
->application_data
;
6885 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6886 disassembler needs to be able to locally determine the ISA, and
6887 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6889 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6890 info
->mach
= bfd_mach_mips16
;
6891 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6892 info
->mach
= bfd_mach_mips_micromips
;
6894 /* Round down the instruction address to the appropriate boundary. */
6895 memaddr
&= (info
->mach
== bfd_mach_mips16
6896 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
6898 /* Set the disassembler options. */
6899 if (!info
->disassembler_options
)
6900 /* This string is not recognized explicitly by the disassembler,
6901 but it tells the disassembler to not try to guess the ABI from
6902 the bfd elf headers, such that, if the user overrides the ABI
6903 of a program linked as NewABI, the disassembly will follow the
6904 register naming conventions specified by the user. */
6905 info
->disassembler_options
= "gpr-names=32";
6907 /* Call the appropriate disassembler based on the target endian-ness. */
6908 if (info
->endian
== BFD_ENDIAN_BIG
)
6909 return print_insn_big_mips (memaddr
, info
);
6911 return print_insn_little_mips (memaddr
, info
);
6915 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
6917 /* Set up the disassembler info, so that we get the right
6918 register names from libopcodes. */
6919 info
->disassembler_options
= "gpr-names=n32";
6920 info
->flavour
= bfd_target_elf_flavour
;
6922 return gdb_print_insn_mips (memaddr
, info
);
6926 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
6928 /* Set up the disassembler info, so that we get the right
6929 register names from libopcodes. */
6930 info
->disassembler_options
= "gpr-names=64";
6931 info
->flavour
= bfd_target_elf_flavour
;
6933 return gdb_print_insn_mips (memaddr
, info
);
6936 /* This function implements gdbarch_breakpoint_from_pc. It uses the
6937 program counter value to determine whether a 16- or 32-bit breakpoint
6938 should be used. It returns a pointer to a string of bytes that encode a
6939 breakpoint instruction, stores the length of the string to *lenptr, and
6940 adjusts pc (if necessary) to point to the actual memory location where
6941 the breakpoint should be inserted. */
6943 static const gdb_byte
*
6944 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
6945 CORE_ADDR
*pcptr
, int *lenptr
)
6947 CORE_ADDR pc
= *pcptr
;
6949 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6951 if (mips_pc_is_mips16 (gdbarch
, pc
))
6953 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
6954 *pcptr
= unmake_compact_addr (pc
);
6955 *lenptr
= sizeof (mips16_big_breakpoint
);
6956 return mips16_big_breakpoint
;
6958 else if (mips_pc_is_micromips (gdbarch
, pc
))
6960 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
6961 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
6966 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6968 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6969 *pcptr
= unmake_compact_addr (pc
);
6971 return (size
== 2) ? micromips16_big_breakpoint
6972 : micromips32_big_breakpoint
;
6976 /* The IDT board uses an unusual breakpoint value, and
6977 sometimes gets confused when it sees the usual MIPS
6978 breakpoint instruction. */
6979 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
6980 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
6981 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
6982 /* Likewise, IRIX appears to expect a different breakpoint,
6983 although this is not apparent until you try to use pthreads. */
6984 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
6986 *lenptr
= sizeof (big_breakpoint
);
6988 if (strcmp (target_shortname
, "mips") == 0)
6989 return idt_big_breakpoint
;
6990 else if (strcmp (target_shortname
, "ddb") == 0
6991 || strcmp (target_shortname
, "pmon") == 0
6992 || strcmp (target_shortname
, "lsi") == 0)
6993 return pmon_big_breakpoint
;
6994 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
6995 return irix_big_breakpoint
;
6997 return big_breakpoint
;
7002 if (mips_pc_is_mips16 (gdbarch
, pc
))
7004 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7005 *pcptr
= unmake_compact_addr (pc
);
7006 *lenptr
= sizeof (mips16_little_breakpoint
);
7007 return mips16_little_breakpoint
;
7009 else if (mips_pc_is_micromips (gdbarch
, pc
))
7011 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7012 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7017 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7019 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
7020 *pcptr
= unmake_compact_addr (pc
);
7022 return (size
== 2) ? micromips16_little_breakpoint
7023 : micromips32_little_breakpoint
;
7027 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7028 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
7029 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
7031 *lenptr
= sizeof (little_breakpoint
);
7033 if (strcmp (target_shortname
, "mips") == 0)
7034 return idt_little_breakpoint
;
7035 else if (strcmp (target_shortname
, "ddb") == 0
7036 || strcmp (target_shortname
, "pmon") == 0
7037 || strcmp (target_shortname
, "lsi") == 0)
7038 return pmon_little_breakpoint
;
7040 return little_breakpoint
;
7045 /* Determine the remote breakpoint kind suitable for the PC. The following
7048 * 2 -- 16-bit MIPS16 mode breakpoint,
7050 * 3 -- 16-bit microMIPS mode breakpoint,
7052 * 4 -- 32-bit standard MIPS mode breakpoint,
7054 * 5 -- 32-bit microMIPS mode breakpoint. */
7057 mips_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
7060 CORE_ADDR pc
= *pcptr
;
7062 if (mips_pc_is_mips16 (gdbarch
, pc
))
7064 *pcptr
= unmake_compact_addr (pc
);
7067 else if (mips_pc_is_micromips (gdbarch
, pc
))
7073 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7074 size
= status
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
7075 *pcptr
= unmake_compact_addr (pc
);
7076 *kindptr
= size
| 1;
7082 /* Return non-zero if the standard MIPS instruction INST has a branch
7083 delay slot (i.e. it is a jump or branch instruction). This function
7084 is based on mips32_next_pc. */
7087 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7093 op
= itype_op (inst
);
7094 if ((inst
& 0xe0000000) != 0)
7096 rs
= itype_rs (inst
);
7097 rt
= itype_rt (inst
);
7098 return (is_octeon_bbit_op (op
, gdbarch
)
7099 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7100 || op
== 29 /* JALX: bits 011101 */
7103 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7104 || (rs
== 9 && (rt
& 0x2) == 0)
7105 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7106 || (rs
== 10 && (rt
& 0x2) == 0))));
7107 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7110 switch (op
& 0x07) /* extract bits 28,27,26 */
7112 case 0: /* SPECIAL */
7113 op
= rtype_funct (inst
);
7114 return (op
== 8 /* JR */
7115 || op
== 9); /* JALR */
7116 break; /* end SPECIAL */
7117 case 1: /* REGIMM */
7118 rs
= itype_rs (inst
);
7119 rt
= itype_rt (inst
); /* branch condition */
7120 return ((rt
& 0xc) == 0
7121 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7122 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7123 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7124 /* BPOSGE32, BPOSGE64: bits 1110x */
7125 break; /* end REGIMM */
7126 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7132 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7133 delay slot (i.e. it is a jump or branch instruction). */
7136 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7141 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7145 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7148 /* Return non-zero if the microMIPS instruction INSN, comprising the
7149 16-bit major opcode word in the high 16 bits and any second word
7150 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7151 jump or branch instruction). The instruction must be 32-bit if
7152 MUSTBE32 is set or can be any instruction otherwise. */
7155 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7157 ULONGEST major
= insn
>> 16;
7159 switch (micromips_op (major
))
7161 /* 16-bit instructions. */
7162 case 0x33: /* B16: bits 110011 */
7163 case 0x2b: /* BNEZ16: bits 101011 */
7164 case 0x23: /* BEQZ16: bits 100011 */
7166 case 0x11: /* POOL16C: bits 010001 */
7168 && ((b5s5_op (major
) == 0xc
7169 /* JR16: bits 010001 01100 */
7170 || (b5s5_op (major
) & 0x1e) == 0xe)));
7171 /* JALR16, JALRS16: bits 010001 0111x */
7172 /* 32-bit instructions. */
7173 case 0x3d: /* JAL: bits 111101 */
7174 case 0x3c: /* JALX: bits 111100 */
7175 case 0x35: /* J: bits 110101 */
7176 case 0x2d: /* BNE: bits 101101 */
7177 case 0x25: /* BEQ: bits 100101 */
7178 case 0x1d: /* JALS: bits 011101 */
7180 case 0x10: /* POOL32I: bits 010000 */
7181 return ((b5s5_op (major
) & 0x1c) == 0x0
7182 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7183 || (b5s5_op (major
) & 0x1d) == 0x4
7184 /* BLEZ, BGTZ: bits 010000 001x0 */
7185 || (b5s5_op (major
) & 0x1d) == 0x11
7186 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7187 || ((b5s5_op (major
) & 0x1e) == 0x14
7188 && (major
& 0x3) == 0x0)
7189 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7190 || (b5s5_op (major
) & 0x1e) == 0x1a
7191 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7192 || ((b5s5_op (major
) & 0x1e) == 0x1c
7193 && (major
& 0x3) == 0x0)
7194 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7195 || ((b5s5_op (major
) & 0x1c) == 0x1c
7196 && (major
& 0x3) == 0x1));
7197 /* BC1ANY*: bits 010000 111xx xxx01 */
7198 case 0x0: /* POOL32A: bits 000000 */
7199 return (b0s6_op (insn
) == 0x3c
7200 /* POOL32Axf: bits 000000 ... 111100 */
7201 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7202 /* JALR, JALR.HB: 000000 000x111100 111100 */
7203 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7209 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7210 slot (i.e. it is a non-compact jump instruction). The instruction
7211 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7214 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7215 CORE_ADDR addr
, int mustbe32
)
7220 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7224 if (mips_insn_size (ISA_MICROMIPS
, insn
) == 2 * MIPS_INSN16_SIZE
)
7226 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7231 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7234 /* Return non-zero if the MIPS16 instruction INST, which must be
7235 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7236 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7237 instruction). This function is based on mips16_next_pc. */
7240 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7242 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7244 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7247 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7248 slot (i.e. it is a non-compact jump instruction). The instruction
7249 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7252 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7253 CORE_ADDR addr
, int mustbe32
)
7255 unsigned short insn
;
7258 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7262 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7265 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7266 This assumes KSSEG exists. */
7269 mips_segment_boundary (CORE_ADDR bpaddr
)
7271 CORE_ADDR mask
= CORE_ADDR_MAX
;
7274 if (sizeof (CORE_ADDR
) == 8)
7275 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7276 a compiler warning produced where CORE_ADDR is a 32-bit type even
7277 though in that case this is dead code). */
7278 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7281 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7282 segsize
= 29; /* 32-bit compatibility segment */
7284 segsize
= 62; /* xkseg */
7286 case 2: /* xkphys */
7289 default: /* xksseg (1), xkuseg/kuseg (0) */
7293 else if (bpaddr
& 0x80000000) /* kernel segment */
7296 segsize
= 31; /* user segment */
7298 return bpaddr
& mask
;
7301 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7302 it backwards if necessary. Return the address of the new location. */
7305 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7307 CORE_ADDR prev_addr
;
7309 CORE_ADDR func_addr
;
7311 /* If a breakpoint is set on the instruction in a branch delay slot,
7312 GDB gets confused. When the breakpoint is hit, the PC isn't on
7313 the instruction in the branch delay slot, the PC will point to
7314 the branch instruction. Since the PC doesn't match any known
7315 breakpoints, GDB reports a trap exception.
7317 There are two possible fixes for this problem.
7319 1) When the breakpoint gets hit, see if the BD bit is set in the
7320 Cause register (which indicates the last exception occurred in a
7321 branch delay slot). If the BD bit is set, fix the PC to point to
7322 the instruction in the branch delay slot.
7324 2) When the user sets the breakpoint, don't allow him to set the
7325 breakpoint on the instruction in the branch delay slot. Instead
7326 move the breakpoint to the branch instruction (which will have
7329 The problem with the first solution is that if the user then
7330 single-steps the processor, the branch instruction will get
7331 skipped (since GDB thinks the PC is on the instruction in the
7334 So, we'll use the second solution. To do this we need to know if
7335 the instruction we're trying to set the breakpoint on is in the
7336 branch delay slot. */
7338 boundary
= mips_segment_boundary (bpaddr
);
7340 /* Make sure we don't scan back before the beginning of the current
7341 function, since we may fetch constant data or insns that look like
7342 a jump. Of course we might do that anyway if the compiler has
7343 moved constants inline. :-( */
7344 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7345 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7346 boundary
= func_addr
;
7348 if (mips_pc_is_mips (bpaddr
))
7350 if (bpaddr
== boundary
)
7353 /* If the previous instruction has a branch delay slot, we have
7354 to move the breakpoint to the branch instruction. */
7355 prev_addr
= bpaddr
- 4;
7356 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7361 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7362 CORE_ADDR addr
, jmpaddr
;
7365 boundary
= unmake_compact_addr (boundary
);
7367 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7368 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7369 so try for that first, then try the 2 byte JALR/JR.
7370 The microMIPS ASE has a whole range of jumps and branches
7371 with delay slots, some of which take 4 bytes and some take
7372 2 bytes, so the idea is the same.
7373 FIXME: We have to assume that bpaddr is not the second half
7374 of an extended instruction. */
7375 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7376 ? micromips_insn_at_pc_has_delay_slot
7377 : mips16_insn_at_pc_has_delay_slot
);
7381 for (i
= 1; i
< 4; i
++)
7383 if (unmake_compact_addr (addr
) == boundary
)
7385 addr
-= MIPS_INSN16_SIZE
;
7386 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7387 /* Looks like a JR/JALR at [target-1], but it could be
7388 the second word of a previous JAL/JALX, so record it
7389 and check back one more. */
7391 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7394 /* Looks like a JAL/JALX at [target-2], but it could also
7395 be the second word of a previous JAL/JALX, record it,
7396 and check back one more. */
7399 /* Looks like a JAL/JALX at [target-3], so any previously
7400 recorded JAL/JALX or JR/JALR must be wrong, because:
7403 -2: JAL-ext (can't be JAL/JALX)
7404 -1: bdslot (can't be JR/JALR)
7407 Of course it could be another JAL-ext which looks
7408 like a JAL, but in that case we'd have broken out
7409 of this loop at [target-2]:
7413 -2: bdslot (can't be jmp)
7420 /* Not a jump instruction: if we're at [target-1] this
7421 could be the second word of a JAL/JALX, so continue;
7422 otherwise we're done. */
7435 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7436 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7439 mips_is_stub_suffix (const char *suffix
, int zero
)
7444 return zero
&& suffix
[1] == '\0';
7446 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7451 return suffix
[1] == '\0';
7457 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7458 call stubs, one of sf, df, sc, or dc. */
7461 mips_is_stub_mode (const char *mode
)
7463 return ((mode
[0] == 's' || mode
[0] == 'd')
7464 && (mode
[1] == 'f' || mode
[1] == 'c'));
7467 /* Code at PC is a compiler-generated stub. Such a stub for a function
7468 bar might have a name like __fn_stub_bar, and might look like this:
7475 followed by (or interspersed with):
7482 addiu $25, $25, %lo(bar)
7485 ($1 may be used in old code; for robustness we accept any register)
7488 lui $28, %hi(_gp_disp)
7489 addiu $28, $28, %lo(_gp_disp)
7492 addiu $25, $25, %lo(bar)
7495 In the case of a __call_stub_bar stub, the sequence to set up
7496 arguments might look like this:
7503 followed by (or interspersed with) one of the jump sequences above.
7505 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7506 of J or JR, respectively, followed by:
7512 We are at the beginning of the stub here, and scan down and extract
7513 the target address from the jump immediate instruction or, if a jump
7514 register instruction is used, from the register referred. Return
7515 the value of PC calculated or 0 if inconclusive.
7517 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7520 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7522 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7523 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7524 int addrreg
= MIPS_ZERO_REGNUM
;
7525 CORE_ADDR start_pc
= pc
;
7526 CORE_ADDR target_pc
= 0;
7533 status
== 0 && target_pc
== 0 && i
< 20;
7534 i
++, pc
+= MIPS_INSN32_SIZE
)
7536 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7542 switch (itype_op (inst
))
7544 case 0: /* SPECIAL */
7545 switch (rtype_funct (inst
))
7549 rs
= rtype_rs (inst
);
7550 if (rs
== MIPS_GP_REGNUM
)
7551 target_pc
= gp
; /* Hmm... */
7552 else if (rs
== addrreg
)
7556 case 0x21: /* ADDU */
7557 rt
= rtype_rt (inst
);
7558 rs
= rtype_rs (inst
);
7559 rd
= rtype_rd (inst
);
7560 if (rd
== MIPS_GP_REGNUM
7561 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7562 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7570 target_pc
= jtype_target (inst
) << 2;
7571 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7575 rt
= itype_rt (inst
);
7576 rs
= itype_rs (inst
);
7579 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7580 if (rt
== MIPS_GP_REGNUM
)
7582 else if (rt
== addrreg
)
7588 rt
= itype_rt (inst
);
7589 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7590 if (rt
== MIPS_GP_REGNUM
)
7592 else if (rt
!= MIPS_ZERO_REGNUM
)
7600 rt
= itype_rt (inst
);
7601 rs
= itype_rs (inst
);
7602 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7603 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7607 memset (buf
, 0, sizeof (buf
));
7608 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7610 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7619 /* If PC is in a MIPS16 call or return stub, return the address of the
7620 target PC, which is either the callee or the caller. There are several
7621 cases which must be handled:
7623 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7624 and the target PC is in $31 ($ra).
7625 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7626 and the target PC is in $2.
7627 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7628 i.e. before the JALR instruction, this is effectively a call stub
7629 and the target PC is in $2. Otherwise this is effectively
7630 a return stub and the target PC is in $18.
7631 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7632 JAL or JALR instruction, this is effectively a call stub and the
7633 target PC is buried in the instruction stream. Otherwise this
7634 is effectively a return stub and the target PC is in $18.
7635 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7636 stub and the target PC is buried in the instruction stream.
7638 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7639 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7643 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7645 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7646 CORE_ADDR start_addr
;
7650 /* Find the starting address and name of the function containing the PC. */
7651 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7654 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7655 and the target PC is in $31 ($ra). */
7656 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7657 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7658 && mips_is_stub_mode (name
+ prefixlen
)
7659 && name
[prefixlen
+ 2] == '\0')
7660 return get_frame_register_signed
7661 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7663 /* If the PC is in __mips16_call_stub_*, this is one of the call
7664 call/return stubs. */
7665 prefixlen
= strlen (mips_str_mips16_call_stub
);
7666 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7668 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7669 and the target PC is in $2. */
7670 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7671 return get_frame_register_signed
7672 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7674 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7675 i.e. before the JALR instruction, this is effectively a call stub
7676 and the target PC is in $2. Otherwise this is effectively
7677 a return stub and the target PC is in $18. */
7678 else if (mips_is_stub_mode (name
+ prefixlen
)
7679 && name
[prefixlen
+ 2] == '_'
7680 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7682 if (pc
== start_addr
)
7683 /* This is the 'call' part of a call stub. The return
7684 address is in $2. */
7685 return get_frame_register_signed
7686 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7688 /* This is the 'return' part of a call stub. The return
7689 address is in $18. */
7690 return get_frame_register_signed
7691 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7694 return 0; /* Not a stub. */
7697 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7698 compiler-generated call or call/return stubs. */
7699 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0
7700 || strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
7702 if (pc
== start_addr
)
7703 /* This is the 'call' part of a call stub. Call this helper
7704 to scan through this code for interesting instructions
7705 and determine the final PC. */
7706 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7708 /* This is the 'return' part of a call stub. The return address
7710 return get_frame_register_signed
7711 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7714 return 0; /* Not a stub. */
7717 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7718 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7721 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7723 CORE_ADDR start_addr
;
7726 /* Find the starting address of the function containing the PC. */
7727 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7730 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7731 the start, i.e. after the JALR instruction, this is effectively
7733 prefixlen
= strlen (mips_str_mips16_call_stub
);
7734 if (pc
!= start_addr
7735 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7736 && mips_is_stub_mode (name
+ prefixlen
)
7737 && name
[prefixlen
+ 2] == '_'
7738 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7741 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7742 the JAL or JALR instruction, this is effectively a return stub. */
7743 prefixlen
= strlen (mips_str_call_fp_stub
);
7744 if (pc
!= start_addr
7745 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7748 /* Consume the .pic. prefix of any PIC stub, this function must return
7749 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7750 or the call stub path will trigger in handle_inferior_event causing
7752 prefixlen
= strlen (mips_str_pic
);
7753 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7756 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7757 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7758 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7759 && mips_is_stub_mode (name
+ prefixlen
)
7760 && name
[prefixlen
+ 2] == '\0')
7763 return 0; /* Not a stub. */
7766 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7767 PC of the stub target. The stub just loads $t9 and jumps to it,
7768 so that $t9 has the correct value at function entry. */
7771 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7773 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7774 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7775 struct bound_minimal_symbol msym
;
7777 gdb_byte stub_code
[16];
7778 int32_t stub_words
[4];
7780 /* The stub for foo is named ".pic.foo", and is either two
7781 instructions inserted before foo or a three instruction sequence
7782 which jumps to foo. */
7783 msym
= lookup_minimal_symbol_by_pc (pc
);
7784 if (msym
.minsym
== NULL
7785 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7786 || MSYMBOL_LINKAGE_NAME (msym
.minsym
) == NULL
7787 || strncmp (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic.", 5) != 0)
7790 /* A two-instruction header. */
7791 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7794 /* A three-instruction (plus delay slot) trampoline. */
7795 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7797 if (target_read_memory (pc
, stub_code
, 16) != 0)
7799 for (i
= 0; i
< 4; i
++)
7800 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7803 /* A stub contains these instructions:
7806 addiu t9, t9, %lo(target)
7809 This works even for N64, since stubs are only generated with
7811 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7812 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7813 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7814 && stub_words
[3] == 0x00000000)
7815 return ((((stub_words
[0] & 0x0000ffff) << 16)
7816 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7819 /* Not a recognized stub. */
7824 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7826 CORE_ADDR requested_pc
= pc
;
7827 CORE_ADDR target_pc
;
7834 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7838 if (is_compact_addr (pc
))
7839 pc
= unmake_compact_addr (pc
);
7842 new_pc
= find_solib_trampoline_target (frame
, pc
);
7846 if (is_compact_addr (pc
))
7847 pc
= unmake_compact_addr (pc
);
7850 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7854 if (is_compact_addr (pc
))
7855 pc
= unmake_compact_addr (pc
);
7858 while (pc
!= target_pc
);
7860 return pc
!= requested_pc
? pc
: 0;
7863 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7864 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7867 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7870 if (num
>= 0 && num
< 32)
7872 else if (num
>= 38 && num
< 70)
7873 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7875 regnum
= mips_regnum (gdbarch
)->hi
;
7877 regnum
= mips_regnum (gdbarch
)->lo
;
7878 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7879 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7881 /* This will hopefully (eventually) provoke a warning. Should
7882 we be calling complaint() here? */
7883 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7884 return gdbarch_num_regs (gdbarch
) + regnum
;
7888 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7889 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7892 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7895 if (num
>= 0 && num
< 32)
7897 else if (num
>= 32 && num
< 64)
7898 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7900 regnum
= mips_regnum (gdbarch
)->hi
;
7902 regnum
= mips_regnum (gdbarch
)->lo
;
7903 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7904 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7906 /* This will hopefully (eventually) provoke a warning. Should we
7907 be calling complaint() here? */
7908 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7909 return gdbarch_num_regs (gdbarch
) + regnum
;
7913 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7915 /* Only makes sense to supply raw registers. */
7916 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7917 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7918 decide if it is valid. Should instead define a standard sim/gdb
7919 register numbering scheme. */
7920 if (gdbarch_register_name (gdbarch
,
7921 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7922 && gdbarch_register_name (gdbarch
,
7923 gdbarch_num_regs (gdbarch
)
7924 + regnum
)[0] != '\0')
7927 return LEGACY_SIM_REGNO_IGNORE
;
7931 /* Convert an integer into an address. Extracting the value signed
7932 guarantees a correctly sign extended address. */
7935 mips_integer_to_address (struct gdbarch
*gdbarch
,
7936 struct type
*type
, const gdb_byte
*buf
)
7938 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7939 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7942 /* Dummy virtual frame pointer method. This is no more or less accurate
7943 than most other architectures; we just need to be explicit about it,
7944 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7945 an assertion failure. */
7948 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7949 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7951 *reg
= MIPS_SP_REGNUM
;
7956 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7958 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7959 const char *name
= bfd_get_section_name (abfd
, sect
);
7961 if (*abip
!= MIPS_ABI_UNKNOWN
)
7964 if (strncmp (name
, ".mdebug.", 8) != 0)
7967 if (strcmp (name
, ".mdebug.abi32") == 0)
7968 *abip
= MIPS_ABI_O32
;
7969 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7970 *abip
= MIPS_ABI_N32
;
7971 else if (strcmp (name
, ".mdebug.abi64") == 0)
7972 *abip
= MIPS_ABI_N64
;
7973 else if (strcmp (name
, ".mdebug.abiO64") == 0)
7974 *abip
= MIPS_ABI_O64
;
7975 else if (strcmp (name
, ".mdebug.eabi32") == 0)
7976 *abip
= MIPS_ABI_EABI32
;
7977 else if (strcmp (name
, ".mdebug.eabi64") == 0)
7978 *abip
= MIPS_ABI_EABI64
;
7980 warning (_("unsupported ABI %s."), name
+ 8);
7984 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
7986 int *lbp
= (int *) obj
;
7987 const char *name
= bfd_get_section_name (abfd
, sect
);
7989 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
7991 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
7993 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
7994 warning (_("unrecognized .gcc_compiled_longXX"));
7997 static enum mips_abi
7998 global_mips_abi (void)
8002 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8003 if (mips_abi_strings
[i
] == mips_abi_string
)
8004 return (enum mips_abi
) i
;
8006 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8009 /* Return the default compressed instruction set, either of MIPS16
8010 or microMIPS, selected when none could have been determined from
8011 the ELF header of the binary being executed (or no binary has been
8014 static enum mips_isa
8015 global_mips_compression (void)
8019 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8020 if (mips_compression_strings
[i
] == mips_compression_string
)
8021 return (enum mips_isa
) i
;
8023 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8027 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8029 /* If the size matches the set of 32-bit or 64-bit integer registers,
8030 assume that's what we've got. */
8031 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8032 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8034 /* If the size matches the full set of registers GDB traditionally
8035 knows about, including floating point, for either 32-bit or
8036 64-bit, assume that's what we've got. */
8037 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8038 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8040 /* Otherwise we don't have a useful guess. */
8043 static struct value
*
8044 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8046 const int *reg_p
= baton
;
8047 return value_of_register (*reg_p
, frame
);
8050 static struct gdbarch
*
8051 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8053 struct gdbarch
*gdbarch
;
8054 struct gdbarch_tdep
*tdep
;
8056 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8058 enum mips_fpu_type fpu_type
;
8059 struct tdesc_arch_data
*tdesc_data
= NULL
;
8060 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8061 const char **reg_names
;
8062 struct mips_regnum mips_regnum
, *regnum
;
8063 enum mips_isa mips_isa
;
8067 /* Fill in the OS dependent register numbers and names. */
8068 if (info
.osabi
== GDB_OSABI_IRIX
)
8070 mips_regnum
.fp0
= 32;
8071 mips_regnum
.pc
= 64;
8072 mips_regnum
.cause
= 65;
8073 mips_regnum
.badvaddr
= 66;
8074 mips_regnum
.hi
= 67;
8075 mips_regnum
.lo
= 68;
8076 mips_regnum
.fp_control_status
= 69;
8077 mips_regnum
.fp_implementation_revision
= 70;
8078 mips_regnum
.dspacc
= dspacc
= -1;
8079 mips_regnum
.dspctl
= dspctl
= -1;
8081 reg_names
= mips_irix_reg_names
;
8083 else if (info
.osabi
== GDB_OSABI_LINUX
)
8085 mips_regnum
.fp0
= 38;
8086 mips_regnum
.pc
= 37;
8087 mips_regnum
.cause
= 36;
8088 mips_regnum
.badvaddr
= 35;
8089 mips_regnum
.hi
= 34;
8090 mips_regnum
.lo
= 33;
8091 mips_regnum
.fp_control_status
= 70;
8092 mips_regnum
.fp_implementation_revision
= 71;
8093 mips_regnum
.dspacc
= -1;
8094 mips_regnum
.dspctl
= -1;
8098 reg_names
= mips_linux_reg_names
;
8102 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8103 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8104 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8105 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8106 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8107 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8108 mips_regnum
.fp_control_status
= 70;
8109 mips_regnum
.fp_implementation_revision
= 71;
8110 mips_regnum
.dspacc
= dspacc
= -1;
8111 mips_regnum
.dspctl
= dspctl
= -1;
8112 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8113 if (info
.bfd_arch_info
!= NULL
8114 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8115 reg_names
= mips_tx39_reg_names
;
8117 reg_names
= mips_generic_reg_names
;
8120 /* Check any target description for validity. */
8121 if (tdesc_has_registers (info
.target_desc
))
8123 static const char *const mips_gprs
[] = {
8124 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8125 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8126 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8127 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8129 static const char *const mips_fprs
[] = {
8130 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8131 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8132 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8133 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8136 const struct tdesc_feature
*feature
;
8139 feature
= tdesc_find_feature (info
.target_desc
,
8140 "org.gnu.gdb.mips.cpu");
8141 if (feature
== NULL
)
8144 tdesc_data
= tdesc_data_alloc ();
8147 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8148 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
8152 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8153 mips_regnum
.lo
, "lo");
8154 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8155 mips_regnum
.hi
, "hi");
8156 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8157 mips_regnum
.pc
, "pc");
8161 tdesc_data_cleanup (tdesc_data
);
8165 feature
= tdesc_find_feature (info
.target_desc
,
8166 "org.gnu.gdb.mips.cp0");
8167 if (feature
== NULL
)
8169 tdesc_data_cleanup (tdesc_data
);
8174 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8175 mips_regnum
.badvaddr
, "badvaddr");
8176 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8177 MIPS_PS_REGNUM
, "status");
8178 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8179 mips_regnum
.cause
, "cause");
8183 tdesc_data_cleanup (tdesc_data
);
8187 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8188 backend is not prepared for that, though. */
8189 feature
= tdesc_find_feature (info
.target_desc
,
8190 "org.gnu.gdb.mips.fpu");
8191 if (feature
== NULL
)
8193 tdesc_data_cleanup (tdesc_data
);
8198 for (i
= 0; i
< 32; i
++)
8199 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8200 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8202 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8203 mips_regnum
.fp_control_status
,
8206 &= tdesc_numbered_register (feature
, tdesc_data
,
8207 mips_regnum
.fp_implementation_revision
,
8212 tdesc_data_cleanup (tdesc_data
);
8218 feature
= tdesc_find_feature (info
.target_desc
,
8219 "org.gnu.gdb.mips.dsp");
8220 /* The DSP registers are optional; it's OK if they are absent. */
8221 if (feature
!= NULL
)
8225 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8226 dspacc
+ i
++, "hi1");
8227 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8228 dspacc
+ i
++, "lo1");
8229 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8230 dspacc
+ i
++, "hi2");
8231 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8232 dspacc
+ i
++, "lo2");
8233 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8234 dspacc
+ i
++, "hi3");
8235 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8236 dspacc
+ i
++, "lo3");
8238 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8243 tdesc_data_cleanup (tdesc_data
);
8247 mips_regnum
.dspacc
= dspacc
;
8248 mips_regnum
.dspctl
= dspctl
;
8252 /* It would be nice to detect an attempt to use a 64-bit ABI
8253 when only 32-bit registers are provided. */
8257 /* First of all, extract the elf_flags, if available. */
8258 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8259 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8260 else if (arches
!= NULL
)
8261 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8265 fprintf_unfiltered (gdb_stdlog
,
8266 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8268 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8269 switch ((elf_flags
& EF_MIPS_ABI
))
8271 case E_MIPS_ABI_O32
:
8272 found_abi
= MIPS_ABI_O32
;
8274 case E_MIPS_ABI_O64
:
8275 found_abi
= MIPS_ABI_O64
;
8277 case E_MIPS_ABI_EABI32
:
8278 found_abi
= MIPS_ABI_EABI32
;
8280 case E_MIPS_ABI_EABI64
:
8281 found_abi
= MIPS_ABI_EABI64
;
8284 if ((elf_flags
& EF_MIPS_ABI2
))
8285 found_abi
= MIPS_ABI_N32
;
8287 found_abi
= MIPS_ABI_UNKNOWN
;
8291 /* GCC creates a pseudo-section whose name describes the ABI. */
8292 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8293 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8295 /* If we have no useful BFD information, use the ABI from the last
8296 MIPS architecture (if there is one). */
8297 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8298 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8300 /* Try the architecture for any hint of the correct ABI. */
8301 if (found_abi
== MIPS_ABI_UNKNOWN
8302 && info
.bfd_arch_info
!= NULL
8303 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8305 switch (info
.bfd_arch_info
->mach
)
8307 case bfd_mach_mips3900
:
8308 found_abi
= MIPS_ABI_EABI32
;
8310 case bfd_mach_mips4100
:
8311 case bfd_mach_mips5000
:
8312 found_abi
= MIPS_ABI_EABI64
;
8314 case bfd_mach_mips8000
:
8315 case bfd_mach_mips10000
:
8316 /* On Irix, ELF64 executables use the N64 ABI. The
8317 pseudo-sections which describe the ABI aren't present
8318 on IRIX. (Even for executables created by gcc.) */
8319 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8320 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8321 found_abi
= MIPS_ABI_N64
;
8323 found_abi
= MIPS_ABI_N32
;
8328 /* Default 64-bit objects to N64 instead of O32. */
8329 if (found_abi
== MIPS_ABI_UNKNOWN
8330 && info
.abfd
!= NULL
8331 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8332 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8333 found_abi
= MIPS_ABI_N64
;
8336 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8339 /* What has the user specified from the command line? */
8340 wanted_abi
= global_mips_abi ();
8342 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8345 /* Now that we have found what the ABI for this binary would be,
8346 check whether the user is overriding it. */
8347 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8348 mips_abi
= wanted_abi
;
8349 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8350 mips_abi
= found_abi
;
8352 mips_abi
= MIPS_ABI_O32
;
8354 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8357 /* Determine the default compressed ISA. */
8358 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8359 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8360 mips_isa
= ISA_MICROMIPS
;
8361 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8362 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8363 mips_isa
= ISA_MIPS16
;
8365 mips_isa
= global_mips_compression ();
8366 mips_compression_string
= mips_compression_strings
[mips_isa
];
8368 /* Also used when doing an architecture lookup. */
8370 fprintf_unfiltered (gdb_stdlog
,
8371 "mips_gdbarch_init: "
8372 "mips64_transfers_32bit_regs_p = %d\n",
8373 mips64_transfers_32bit_regs_p
);
8375 /* Determine the MIPS FPU type. */
8378 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8379 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8380 Tag_GNU_MIPS_ABI_FP
);
8381 #endif /* HAVE_ELF */
8383 if (!mips_fpu_type_auto
)
8384 fpu_type
= mips_fpu_type
;
8385 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8387 switch (elf_fpu_type
)
8389 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8390 fpu_type
= MIPS_FPU_DOUBLE
;
8392 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8393 fpu_type
= MIPS_FPU_SINGLE
;
8395 case Val_GNU_MIPS_ABI_FP_SOFT
:
8397 /* Soft float or unknown. */
8398 fpu_type
= MIPS_FPU_NONE
;
8402 else if (info
.bfd_arch_info
!= NULL
8403 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8404 switch (info
.bfd_arch_info
->mach
)
8406 case bfd_mach_mips3900
:
8407 case bfd_mach_mips4100
:
8408 case bfd_mach_mips4111
:
8409 case bfd_mach_mips4120
:
8410 fpu_type
= MIPS_FPU_NONE
;
8412 case bfd_mach_mips4650
:
8413 fpu_type
= MIPS_FPU_SINGLE
;
8416 fpu_type
= MIPS_FPU_DOUBLE
;
8419 else if (arches
!= NULL
)
8420 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
8422 fpu_type
= MIPS_FPU_DOUBLE
;
8424 fprintf_unfiltered (gdb_stdlog
,
8425 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8427 /* Check for blatant incompatibilities. */
8429 /* If we have only 32-bit registers, then we can't debug a 64-bit
8431 if (info
.target_desc
8432 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8433 && mips_abi
!= MIPS_ABI_EABI32
8434 && mips_abi
!= MIPS_ABI_O32
)
8436 if (tdesc_data
!= NULL
)
8437 tdesc_data_cleanup (tdesc_data
);
8441 /* Try to find a pre-existing architecture. */
8442 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8444 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8446 /* MIPS needs to be pedantic about which ABI and the compressed
8447 ISA variation the object is using. */
8448 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8450 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8452 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8454 /* Need to be pedantic about which register virtual size is
8456 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8457 != mips64_transfers_32bit_regs_p
)
8459 /* Be pedantic about which FPU is selected. */
8460 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
8463 if (tdesc_data
!= NULL
)
8464 tdesc_data_cleanup (tdesc_data
);
8465 return arches
->gdbarch
;
8468 /* Need a new architecture. Fill in a target specific vector. */
8469 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
8470 gdbarch
= gdbarch_alloc (&info
, tdep
);
8471 tdep
->elf_flags
= elf_flags
;
8472 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8473 tdep
->found_abi
= found_abi
;
8474 tdep
->mips_abi
= mips_abi
;
8475 tdep
->mips_isa
= mips_isa
;
8476 tdep
->mips_fpu_type
= fpu_type
;
8477 tdep
->register_size_valid_p
= 0;
8478 tdep
->register_size
= 0;
8480 if (info
.target_desc
)
8482 /* Some useful properties can be inferred from the target. */
8483 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8485 tdep
->register_size_valid_p
= 1;
8486 tdep
->register_size
= 4;
8488 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8490 tdep
->register_size_valid_p
= 1;
8491 tdep
->register_size
= 8;
8495 /* Initially set everything according to the default ABI/ISA. */
8496 set_gdbarch_short_bit (gdbarch
, 16);
8497 set_gdbarch_int_bit (gdbarch
, 32);
8498 set_gdbarch_float_bit (gdbarch
, 32);
8499 set_gdbarch_double_bit (gdbarch
, 64);
8500 set_gdbarch_long_double_bit (gdbarch
, 64);
8501 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8502 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8503 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8505 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8506 mips_ax_pseudo_register_collect
);
8507 set_gdbarch_ax_pseudo_register_push_stack
8508 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8510 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8511 mips_elf_make_msymbol_special
);
8513 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8514 *regnum
= mips_regnum
;
8515 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8516 set_gdbarch_num_regs (gdbarch
, num_regs
);
8517 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8518 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8519 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8520 tdep
->mips_processor_reg_names
= reg_names
;
8521 tdep
->regnum
= regnum
;
8526 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8527 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8528 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8529 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8530 tdep
->default_mask_address_p
= 0;
8531 set_gdbarch_long_bit (gdbarch
, 32);
8532 set_gdbarch_ptr_bit (gdbarch
, 32);
8533 set_gdbarch_long_long_bit (gdbarch
, 64);
8536 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8537 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8538 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8539 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8540 tdep
->default_mask_address_p
= 0;
8541 set_gdbarch_long_bit (gdbarch
, 32);
8542 set_gdbarch_ptr_bit (gdbarch
, 32);
8543 set_gdbarch_long_long_bit (gdbarch
, 64);
8545 case MIPS_ABI_EABI32
:
8546 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8547 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8548 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8549 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8550 tdep
->default_mask_address_p
= 0;
8551 set_gdbarch_long_bit (gdbarch
, 32);
8552 set_gdbarch_ptr_bit (gdbarch
, 32);
8553 set_gdbarch_long_long_bit (gdbarch
, 64);
8555 case MIPS_ABI_EABI64
:
8556 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8557 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8558 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8559 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8560 tdep
->default_mask_address_p
= 0;
8561 set_gdbarch_long_bit (gdbarch
, 64);
8562 set_gdbarch_ptr_bit (gdbarch
, 64);
8563 set_gdbarch_long_long_bit (gdbarch
, 64);
8566 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8567 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8568 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8569 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8570 tdep
->default_mask_address_p
= 0;
8571 set_gdbarch_long_bit (gdbarch
, 32);
8572 set_gdbarch_ptr_bit (gdbarch
, 32);
8573 set_gdbarch_long_long_bit (gdbarch
, 64);
8574 set_gdbarch_long_double_bit (gdbarch
, 128);
8575 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8578 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8579 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8580 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8581 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8582 tdep
->default_mask_address_p
= 0;
8583 set_gdbarch_long_bit (gdbarch
, 64);
8584 set_gdbarch_ptr_bit (gdbarch
, 64);
8585 set_gdbarch_long_long_bit (gdbarch
, 64);
8586 set_gdbarch_long_double_bit (gdbarch
, 128);
8587 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8590 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8593 /* GCC creates a pseudo-section whose name specifies the size of
8594 longs, since -mlong32 or -mlong64 may be used independent of
8595 other options. How those options affect pointer sizes is ABI and
8596 architecture dependent, so use them to override the default sizes
8597 set by the ABI. This table shows the relationship between ABI,
8598 -mlongXX, and size of pointers:
8600 ABI -mlongXX ptr bits
8601 --- -------- --------
8615 Note that for o32 and eabi32, pointers are always 32 bits
8616 regardless of any -mlongXX option. For all others, pointers and
8617 longs are the same, as set by -mlongXX or set by defaults. */
8619 if (info
.abfd
!= NULL
)
8623 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8626 set_gdbarch_long_bit (gdbarch
, long_bit
);
8630 case MIPS_ABI_EABI32
:
8635 case MIPS_ABI_EABI64
:
8636 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8639 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8644 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8645 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8648 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8649 flag in object files because to do so would make it impossible to
8650 link with libraries compiled without "-gp32". This is
8651 unnecessarily restrictive.
8653 We could solve this problem by adding "-gp32" multilibs to gcc,
8654 but to set this flag before gcc is built with such multilibs will
8655 break too many systems.''
8657 But even more unhelpfully, the default linker output target for
8658 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8659 for 64-bit programs - you need to change the ABI to change this,
8660 and not all gcc targets support that currently. Therefore using
8661 this flag to detect 32-bit mode would do the wrong thing given
8662 the current gcc - it would make GDB treat these 64-bit programs
8663 as 32-bit programs by default. */
8665 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8666 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8668 /* Add/remove bits from an address. The MIPS needs be careful to
8669 ensure that all 32 bit addresses are sign extended to 64 bits. */
8670 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8672 /* Unwind the frame. */
8673 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8674 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8675 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8677 /* Map debug register numbers onto internal register numbers. */
8678 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8679 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8680 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8681 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8682 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8683 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8685 /* MIPS version of CALL_DUMMY. */
8687 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8688 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8689 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8691 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8692 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8693 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8695 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8696 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
8697 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
8698 mips_remote_breakpoint_from_pc
);
8699 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8700 mips_adjust_breakpoint_address
);
8702 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8704 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
8706 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8707 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8708 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8710 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8712 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8714 if (mips_abi
== MIPS_ABI_N32
)
8715 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8716 else if (mips_abi
== MIPS_ABI_N64
)
8717 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8719 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8721 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8722 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8723 need to all be folded into the target vector. Since they are
8724 being used as guards for target_stopped_by_watchpoint, why not have
8725 target_stopped_by_watchpoint return the type of watchpoint that the code
8727 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8729 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8731 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8732 to support MIPS16. This is a bad thing. Make sure not to do it
8733 if we have an OS ABI that actually supports shared libraries, since
8734 shared library support is more important. If we have an OS someday
8735 that supports both shared libraries and MIPS16, we'll have to find
8736 a better place for these.
8737 macro/2012-04-25: But that applies to return trampolines only and
8738 currently no MIPS OS ABI uses shared libraries that have them. */
8739 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8741 set_gdbarch_single_step_through_delay (gdbarch
,
8742 mips_single_step_through_delay
);
8744 /* Virtual tables. */
8745 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8747 mips_register_g_packet_guesses (gdbarch
);
8749 /* Hook in OS ABI-specific overrides, if they have been registered. */
8750 info
.tdep_info
= (void *) tdesc_data
;
8751 gdbarch_init_osabi (info
, gdbarch
);
8753 /* The hook may have adjusted num_regs, fetch the final value and
8754 set pc_regnum and sp_regnum now that it has been fixed. */
8755 num_regs
= gdbarch_num_regs (gdbarch
);
8756 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8757 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8759 /* Unwind the frame. */
8760 dwarf2_append_unwinders (gdbarch
);
8761 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8762 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8763 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8764 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8765 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8766 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8767 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8768 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8769 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8773 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8774 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8776 /* Override the normal target description methods to handle our
8777 dual real and pseudo registers. */
8778 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8779 set_gdbarch_register_reggroup_p (gdbarch
,
8780 mips_tdesc_register_reggroup_p
);
8782 num_regs
= gdbarch_num_regs (gdbarch
);
8783 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8784 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8785 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8788 /* Add ABI-specific aliases for the registers. */
8789 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8790 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8791 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8792 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8794 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8795 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8796 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8798 /* Add some other standard aliases. */
8799 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8800 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8801 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8803 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8804 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8805 value_of_mips_user_reg
,
8806 &mips_numeric_register_aliases
[i
].regnum
);
8812 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
8814 struct gdbarch_info info
;
8816 /* Force the architecture to update, and (if it's a MIPS architecture)
8817 mips_gdbarch_init will take care of the rest. */
8818 gdbarch_info_init (&info
);
8819 gdbarch_update_p (info
);
8822 /* Print out which MIPS ABI is in use. */
8825 show_mips_abi (struct ui_file
*file
,
8827 struct cmd_list_element
*ignored_cmd
,
8828 const char *ignored_value
)
8830 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8833 "The MIPS ABI is unknown because the current architecture "
8837 enum mips_abi global_abi
= global_mips_abi ();
8838 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8839 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8841 if (global_abi
== MIPS_ABI_UNKNOWN
)
8844 "The MIPS ABI is set automatically (currently \"%s\").\n",
8846 else if (global_abi
== actual_abi
)
8849 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8853 /* Probably shouldn't happen... */
8854 fprintf_filtered (file
,
8855 "The (auto detected) MIPS ABI \"%s\" is in use "
8856 "even though the user setting was \"%s\".\n",
8857 actual_abi_str
, mips_abi_strings
[global_abi
]);
8862 /* Print out which MIPS compressed ISA encoding is used. */
8865 show_mips_compression (struct ui_file
*file
, int from_tty
,
8866 struct cmd_list_element
*c
, const char *value
)
8868 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8873 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8875 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8879 int ef_mips_32bitmode
;
8880 /* Determine the ISA. */
8881 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8899 /* Determine the size of a pointer. */
8900 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8901 fprintf_unfiltered (file
,
8902 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8904 fprintf_unfiltered (file
,
8905 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8907 fprintf_unfiltered (file
,
8908 "mips_dump_tdep: ef_mips_arch = %d\n",
8910 fprintf_unfiltered (file
,
8911 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8912 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8913 fprintf_unfiltered (file
,
8915 "mips_mask_address_p() %d (default %d)\n",
8916 mips_mask_address_p (tdep
),
8917 tdep
->default_mask_address_p
);
8919 fprintf_unfiltered (file
,
8920 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8921 MIPS_DEFAULT_FPU_TYPE
,
8922 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
8923 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
8924 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
8926 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8927 MIPS_EABI (gdbarch
));
8928 fprintf_unfiltered (file
,
8929 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8930 MIPS_FPU_TYPE (gdbarch
),
8931 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
8932 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
8933 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
8937 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
8940 _initialize_mips_tdep (void)
8942 static struct cmd_list_element
*mipsfpulist
= NULL
;
8943 struct cmd_list_element
*c
;
8945 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8946 if (MIPS_ABI_LAST
+ 1
8947 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8948 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8950 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8952 mips_pdr_data
= register_objfile_data ();
8954 /* Create feature sets with the appropriate properties. The values
8955 are not important. */
8956 mips_tdesc_gp32
= allocate_target_description ();
8957 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8959 mips_tdesc_gp64
= allocate_target_description ();
8960 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8962 /* Add root prefix command for all "set mips"/"show mips" commands. */
8963 add_prefix_cmd ("mips", no_class
, set_mips_command
,
8964 _("Various MIPS specific commands."),
8965 &setmipscmdlist
, "set mips ", 0, &setlist
);
8967 add_prefix_cmd ("mips", no_class
, show_mips_command
,
8968 _("Various MIPS specific commands."),
8969 &showmipscmdlist
, "show mips ", 0, &showlist
);
8971 /* Allow the user to override the ABI. */
8972 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
8973 &mips_abi_string
, _("\
8974 Set the MIPS ABI used by this program."), _("\
8975 Show the MIPS ABI used by this program."), _("\
8976 This option can be set to one of:\n\
8977 auto - the default ABI associated with the current binary\n\
8986 &setmipscmdlist
, &showmipscmdlist
);
8988 /* Allow the user to set the ISA to assume for compressed code if ELF
8989 file flags don't tell or there is no program file selected. This
8990 setting is updated whenever unambiguous ELF file flags are interpreted,
8991 and carried over to subsequent sessions. */
8992 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
8993 &mips_compression_string
, _("\
8994 Set the compressed ISA encoding used by MIPS code."), _("\
8995 Show the compressed ISA encoding used by MIPS code."), _("\
8996 Select the compressed ISA encoding used in functions that have no symbol\n\
8997 information available. The encoding can be set to either of:\n\
9000 and is updated automatically from ELF file flags if available."),
9002 show_mips_compression
,
9003 &setmipscmdlist
, &showmipscmdlist
);
9005 /* Let the user turn off floating point and set the fence post for
9006 heuristic_proc_start. */
9008 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
9009 _("Set use of MIPS floating-point coprocessor."),
9010 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
9011 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9012 _("Select single-precision MIPS floating-point coprocessor."),
9014 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9015 _("Select double-precision MIPS floating-point coprocessor."),
9017 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
9018 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
9019 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
9020 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9021 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9022 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
9023 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
9024 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
9025 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9026 _("Select MIPS floating-point coprocessor automatically."),
9028 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9029 _("Show current use of MIPS floating-point coprocessor target."),
9032 /* We really would like to have both "0" and "unlimited" work, but
9033 command.c doesn't deal with that. So make it a var_zinteger
9034 because the user can always use "999999" or some such for unlimited. */
9035 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9036 &heuristic_fence_post
, _("\
9037 Set the distance searched for the start of a function."), _("\
9038 Show the distance searched for the start of a function."), _("\
9039 If you are debugging a stripped executable, GDB needs to search through the\n\
9040 program for the start of a function. This command sets the distance of the\n\
9041 search. The only need to set it is when debugging a stripped executable."),
9042 reinit_frame_cache_sfunc
,
9043 NULL
, /* FIXME: i18n: The distance searched for
9044 the start of a function is %s. */
9045 &setlist
, &showlist
);
9047 /* Allow the user to control whether the upper bits of 64-bit
9048 addresses should be zeroed. */
9049 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9050 &mask_address_var
, _("\
9051 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9052 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9053 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9054 allow GDB to determine the correct value."),
9055 NULL
, show_mask_address
,
9056 &setmipscmdlist
, &showmipscmdlist
);
9058 /* Allow the user to control the size of 32 bit registers within the
9059 raw remote packet. */
9060 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9061 &mips64_transfers_32bit_regs_p
, _("\
9062 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9064 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9066 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9067 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9068 64 bits for others. Use \"off\" to disable compatibility mode"),
9069 set_mips64_transfers_32bit_regs
,
9070 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9071 MIPS target that transfers 32-bit
9072 quantities is %s. */
9073 &setlist
, &showlist
);
9075 /* Debug this files internals. */
9076 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9078 Set mips debugging."), _("\
9079 Show mips debugging."), _("\
9080 When non-zero, mips specific debugging is enabled."),
9082 NULL
, /* FIXME: i18n: Mips debugging is
9084 &setdebuglist
, &showdebuglist
);