1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
43 #include "opcode/mips.h"
48 /* A useful bit in the CP0 status register (PS_REGNUM). */
49 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
50 #define ST0_FR (1 << 26)
52 /* The sizes of floating point registers. */
56 MIPS_FPU_SINGLE_REGSIZE
= 4,
57 MIPS_FPU_DOUBLE_REGSIZE
= 8
60 /* All the possible MIPS ABIs. */
72 struct frame_extra_info
74 mips_extra_func_info_t proc_desc
;
78 /* Various MIPS ISA options (related to stack analysis) can be
79 overridden dynamically. Establish an enum/array for managing
82 static const char size_auto
[] = "auto";
83 static const char size_32
[] = "32";
84 static const char size_64
[] = "64";
86 static const char *size_enums
[] = {
93 /* Some MIPS boards don't support floating point while others only
94 support single-precision floating-point operations. See also
95 FP_REGISTER_DOUBLE. */
99 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
100 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
101 MIPS_FPU_NONE
/* No floating point. */
104 #ifndef MIPS_DEFAULT_FPU_TYPE
105 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
107 static int mips_fpu_type_auto
= 1;
108 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
109 #define MIPS_FPU_TYPE mips_fpu_type
111 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
112 #ifndef FP_REGISTER_DOUBLE
113 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
116 static int mips_debug
= 0;
118 /* MIPS specific per-architecture information */
121 /* from the elf header */
125 enum mips_abi mips_abi
;
126 const char *mips_abi_string
;
127 enum mips_fpu_type mips_fpu_type
;
128 int mips_last_arg_regnum
;
129 int mips_last_fp_arg_regnum
;
130 int mips_default_saved_regsize
;
131 int mips_fp_register_double
;
132 int mips_regs_have_home_p
;
133 int mips_default_stack_argsize
;
134 int gdb_target_is_mips64
;
135 int default_mask_address_p
;
137 enum gdb_osabi osabi
;
142 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
143 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
147 #undef MIPS_LAST_FP_ARG_REGNUM
148 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
152 #undef MIPS_LAST_ARG_REGNUM
153 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
158 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
161 /* Return the currently configured (or set) saved register size. */
164 #undef MIPS_DEFAULT_SAVED_REGSIZE
165 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
166 #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE)
167 #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
170 static const char *mips_saved_regsize_string
= size_auto
;
172 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
175 mips_saved_regsize (void)
177 if (mips_saved_regsize_string
== size_auto
)
178 return MIPS_DEFAULT_SAVED_REGSIZE
;
179 else if (mips_saved_regsize_string
== size_64
)
181 else /* if (mips_saved_regsize_string == size_32) */
185 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
186 compatiblity mode. A return value of 1 means that we have
187 physical 64-bit registers, but should treat them as 32-bit registers. */
190 mips2_fp_compat (void)
192 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
194 if (REGISTER_RAW_SIZE (FP0_REGNUM
) == 4)
198 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
199 in all the places we deal with FP registers. PR gdb/413. */
200 /* Otherwise check the FR bit in the status register - it controls
201 the FP compatiblity mode. If it is clear we are in compatibility
203 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
210 /* Indicate that the ABI makes use of double-precision registers
211 provided by the FPU (rather than combining pairs of registers to
212 form double-precision values). Do not use "TARGET_IS_MIPS64" to
213 determine if the ABI is using double-precision registers. See also
216 #undef FP_REGISTER_DOUBLE
217 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
220 /* Does the caller allocate a ``home'' for each register used in the
221 function call? The N32 ABI and MIPS_EABI do not, the others do. */
224 #undef MIPS_REGS_HAVE_HOME_P
225 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
226 #elif !defined (MIPS_REGS_HAVE_HOME_P)
227 #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI)
230 /* The amount of space reserved on the stack for registers. This is
231 different to MIPS_SAVED_REGSIZE as it determines the alignment of
232 data allocated after the registers have run out. */
235 #undef MIPS_DEFAULT_STACK_ARGSIZE
236 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
237 #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE)
238 #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE)
241 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
243 static const char *mips_stack_argsize_string
= size_auto
;
246 mips_stack_argsize (void)
248 if (mips_stack_argsize_string
== size_auto
)
249 return MIPS_DEFAULT_STACK_ARGSIZE
;
250 else if (mips_stack_argsize_string
== size_64
)
252 else /* if (mips_stack_argsize_string == size_32) */
257 #undef GDB_TARGET_IS_MIPS64
258 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
262 #undef MIPS_DEFAULT_MASK_ADDRESS_P
263 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
264 #elif !defined (MIPS_DEFAULT_MASK_ADDRESS_P)
265 #define MIPS_DEFAULT_MASK_ADDRESS_P (0)
268 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
270 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
272 static void mips_print_register (int, int);
274 static mips_extra_func_info_t
275 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*, int);
277 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
279 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
281 int mips_set_processor_type (char *);
283 static void mips_show_processor_type_command (char *, int);
285 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
287 static mips_extra_func_info_t
288 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
);
290 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
291 mips_extra_func_info_t proc_desc
);
293 static void mips_read_fp_register_single (int regno
, char *rare_buffer
);
294 static void mips_read_fp_register_double (int regno
, char *rare_buffer
);
296 static struct type
*mips_float_register_type (void);
297 static struct type
*mips_double_register_type (void);
299 /* This value is the model of MIPS in use. It is derived from the value
300 of the PrID register. */
302 char *mips_processor_type
;
304 char *tmp_mips_processor_type
;
306 /* The list of available "set mips " and "show mips " commands */
308 static struct cmd_list_element
*setmipscmdlist
= NULL
;
309 static struct cmd_list_element
*showmipscmdlist
= NULL
;
311 /* A set of original names, to be used when restoring back to generic
312 registers from a specific set. */
314 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
315 char **mips_processor_reg_names
= mips_generic_reg_names
;
318 mips_register_name (int i
)
320 return mips_processor_reg_names
[i
];
323 /* Names of IDT R3041 registers. */
325 char *mips_r3041_reg_names
[] = {
326 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
327 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
328 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
329 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
330 "sr", "lo", "hi", "bad", "cause","pc",
331 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
332 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
333 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
334 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
335 "fsr", "fir", "fp", "",
336 "", "", "bus", "ccfg", "", "", "", "",
337 "", "", "port", "cmp", "", "", "epc", "prid",
340 /* Names of IDT R3051 registers. */
342 char *mips_r3051_reg_names
[] = {
343 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
344 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
345 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
346 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
347 "sr", "lo", "hi", "bad", "cause","pc",
348 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
349 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
350 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
351 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
352 "fsr", "fir", "fp", "",
353 "inx", "rand", "elo", "", "ctxt", "", "", "",
354 "", "", "ehi", "", "", "", "epc", "prid",
357 /* Names of IDT R3081 registers. */
359 char *mips_r3081_reg_names
[] = {
360 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
361 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
362 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
363 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
364 "sr", "lo", "hi", "bad", "cause","pc",
365 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
366 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
367 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
368 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
369 "fsr", "fir", "fp", "",
370 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
371 "", "", "ehi", "", "", "", "epc", "prid",
374 /* Names of LSI 33k registers. */
376 char *mips_lsi33k_reg_names
[] = {
377 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
378 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
379 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
380 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
381 "epc", "hi", "lo", "sr", "cause","badvaddr",
382 "dcic", "bpc", "bda", "", "", "", "", "",
383 "", "", "", "", "", "", "", "",
384 "", "", "", "", "", "", "", "",
385 "", "", "", "", "", "", "", "",
387 "", "", "", "", "", "", "", "",
388 "", "", "", "", "", "", "", "",
394 } mips_processor_type_table
[] = {
395 { "generic", mips_generic_reg_names
},
396 { "r3041", mips_r3041_reg_names
},
397 { "r3051", mips_r3051_reg_names
},
398 { "r3071", mips_r3081_reg_names
},
399 { "r3081", mips_r3081_reg_names
},
400 { "lsi33k", mips_lsi33k_reg_names
},
408 /* Table to translate MIPS16 register field to actual register number. */
409 static int mips16_to_32_reg
[8] =
410 {16, 17, 2, 3, 4, 5, 6, 7};
412 /* Heuristic_proc_start may hunt through the text section for a long
413 time across a 2400 baud serial line. Allows the user to limit this
416 static unsigned int heuristic_fence_post
= 0;
418 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
419 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
420 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
421 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
422 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
423 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
424 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
425 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
426 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
427 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
428 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
429 #define _PROC_MAGIC_ 0x0F0F0F0F
430 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
431 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
433 struct linked_proc_info
435 struct mips_extra_func_info info
;
436 struct linked_proc_info
*next
;
438 *linked_proc_desc_table
= NULL
;
441 mips_print_extra_frame_info (struct frame_info
*fi
)
445 && fi
->extra_info
->proc_desc
446 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
447 printf_filtered (" frame pointer is at %s+%s\n",
448 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
449 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
452 /* Number of bytes of storage in the actual machine representation for
453 register N. NOTE: This indirectly defines the register size
454 transfered by the GDB protocol. */
456 static int mips64_transfers_32bit_regs_p
= 0;
459 mips_register_raw_size (int reg_nr
)
461 if (mips64_transfers_32bit_regs_p
)
462 return REGISTER_VIRTUAL_SIZE (reg_nr
);
463 else if (reg_nr
>= FP0_REGNUM
&& reg_nr
< FP0_REGNUM
+ 32
464 && FP_REGISTER_DOUBLE
)
465 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
472 /* Convert between RAW and VIRTUAL registers. The RAW register size
473 defines the remote-gdb packet. */
476 mips_register_convertible (int reg_nr
)
478 if (mips64_transfers_32bit_regs_p
)
481 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
485 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
486 char *raw_buf
, char *virt_buf
)
488 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
490 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
491 TYPE_LENGTH (virtual_type
));
495 TYPE_LENGTH (virtual_type
));
499 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
500 char *virt_buf
, char *raw_buf
)
502 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
503 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
504 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
506 TYPE_LENGTH (virtual_type
));
510 TYPE_LENGTH (virtual_type
));
513 /* Should the upper word of 64-bit addresses be zeroed? */
514 enum cmd_auto_boolean mask_address_var
= CMD_AUTO_BOOLEAN_AUTO
;
517 mips_mask_address_p (void)
519 switch (mask_address_var
)
521 case CMD_AUTO_BOOLEAN_TRUE
:
523 case CMD_AUTO_BOOLEAN_FALSE
:
526 case CMD_AUTO_BOOLEAN_AUTO
:
527 return MIPS_DEFAULT_MASK_ADDRESS_P
;
529 internal_error (__FILE__
, __LINE__
,
530 "mips_mask_address_p: bad switch");
536 show_mask_address (char *cmd
, int from_tty
)
538 switch (mask_address_var
)
540 case CMD_AUTO_BOOLEAN_TRUE
:
541 printf_filtered ("The 32 bit mips address mask is enabled\n");
543 case CMD_AUTO_BOOLEAN_FALSE
:
544 printf_filtered ("The 32 bit mips address mask is disabled\n");
546 case CMD_AUTO_BOOLEAN_AUTO
:
547 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
548 mips_mask_address_p () ? "enabled" : "disabled");
551 internal_error (__FILE__
, __LINE__
,
552 "show_mask_address: bad switch");
557 /* Should call_function allocate stack space for a struct return? */
559 mips_use_struct_convention (int gcc_p
, struct type
*type
)
562 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
564 return 1; /* Structures are returned by ref in extra arg0 */
567 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
570 pc_is_mips16 (bfd_vma memaddr
)
572 struct minimal_symbol
*sym
;
574 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
575 if (IS_MIPS16_ADDR (memaddr
))
578 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
579 the high bit of the info field. Use this to decide if the function is
580 MIPS16 or normal MIPS. */
581 sym
= lookup_minimal_symbol_by_pc (memaddr
);
583 return MSYMBOL_IS_SPECIAL (sym
);
588 /* MIPS believes that the PC has a sign extended value. Perhaphs the
589 all registers should be sign extended for simplicity? */
592 mips_read_pc (ptid_t ptid
)
594 return read_signed_register_pid (PC_REGNUM
, ptid
);
597 /* This returns the PC of the first inst after the prologue. If we can't
598 find the prologue, then return 0. */
601 after_prologue (CORE_ADDR pc
,
602 mips_extra_func_info_t proc_desc
)
604 struct symtab_and_line sal
;
605 CORE_ADDR func_addr
, func_end
;
607 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
608 to read the stack pointer from the current machine state, because
609 the current machine state has nothing to do with the information
610 we need from the proc_desc; and the process may or may not exist
613 proc_desc
= find_proc_desc (pc
, NULL
, 0);
617 /* If function is frameless, then we need to do it the hard way. I
618 strongly suspect that frameless always means prologueless... */
619 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
620 && PROC_FRAME_OFFSET (proc_desc
) == 0)
624 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
625 return 0; /* Unknown */
627 sal
= find_pc_line (func_addr
, 0);
629 if (sal
.end
< func_end
)
632 /* The line after the prologue is after the end of the function. In this
633 case, tell the caller to find the prologue the hard way. */
638 /* Decode a MIPS32 instruction that saves a register in the stack, and
639 set the appropriate bit in the general register mask or float register mask
640 to indicate which register is saved. This is a helper function
641 for mips_find_saved_regs. */
644 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
645 unsigned long *float_mask
)
649 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
650 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
651 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
653 /* It might be possible to use the instruction to
654 find the offset, rather than the code below which
655 is based on things being in a certain order in the
656 frame, but figuring out what the instruction's offset
657 is relative to might be a little tricky. */
658 reg
= (inst
& 0x001f0000) >> 16;
659 *gen_mask
|= (1 << reg
);
661 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
662 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
663 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
666 reg
= ((inst
& 0x001f0000) >> 16);
667 *float_mask
|= (1 << reg
);
671 /* Decode a MIPS16 instruction that saves a register in the stack, and
672 set the appropriate bit in the general register or float register mask
673 to indicate which register is saved. This is a helper function
674 for mips_find_saved_regs. */
677 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
679 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
681 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
682 *gen_mask
|= (1 << reg
);
684 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
686 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
687 *gen_mask
|= (1 << reg
);
689 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
690 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
691 *gen_mask
|= (1 << RA_REGNUM
);
695 /* Fetch and return instruction from the specified location. If the PC
696 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
699 mips_fetch_instruction (CORE_ADDR addr
)
701 char buf
[MIPS_INSTLEN
];
705 if (pc_is_mips16 (addr
))
707 instlen
= MIPS16_INSTLEN
;
708 addr
= UNMAKE_MIPS16_ADDR (addr
);
711 instlen
= MIPS_INSTLEN
;
712 status
= read_memory_nobpt (addr
, buf
, instlen
);
714 memory_error (status
, addr
);
715 return extract_unsigned_integer (buf
, instlen
);
719 /* These the fields of 32 bit mips instructions */
720 #define mips32_op(x) (x >> 26)
721 #define itype_op(x) (x >> 26)
722 #define itype_rs(x) ((x >> 21) & 0x1f)
723 #define itype_rt(x) ((x >> 16) & 0x1f)
724 #define itype_immediate(x) (x & 0xffff)
726 #define jtype_op(x) (x >> 26)
727 #define jtype_target(x) (x & 0x03ffffff)
729 #define rtype_op(x) (x >> 26)
730 #define rtype_rs(x) ((x >> 21) & 0x1f)
731 #define rtype_rt(x) ((x >> 16) & 0x1f)
732 #define rtype_rd(x) ((x >> 11) & 0x1f)
733 #define rtype_shamt(x) ((x >> 6) & 0x1f)
734 #define rtype_funct(x) (x & 0x3f)
737 mips32_relative_offset (unsigned long inst
)
740 x
= itype_immediate (inst
);
741 if (x
& 0x8000) /* sign bit set */
743 x
|= 0xffff0000; /* sign extension */
749 /* Determine whate to set a single step breakpoint while considering
752 mips32_next_pc (CORE_ADDR pc
)
756 inst
= mips_fetch_instruction (pc
);
757 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
759 if (itype_op (inst
) >> 2 == 5)
760 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
762 op
= (itype_op (inst
) & 0x03);
777 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
778 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
780 int tf
= itype_rt (inst
) & 0x01;
781 int cnum
= itype_rt (inst
) >> 2;
782 int fcrcs
= read_signed_register (FCRCS_REGNUM
);
783 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
785 if (((cond
>> cnum
) & 0x01) == tf
)
786 pc
+= mips32_relative_offset (inst
) + 4;
791 pc
+= 4; /* Not a branch, next instruction is easy */
794 { /* This gets way messy */
796 /* Further subdivide into SPECIAL, REGIMM and other */
797 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
799 case 0: /* SPECIAL */
800 op
= rtype_funct (inst
);
805 /* Set PC to that address */
806 pc
= read_signed_register (rtype_rs (inst
));
812 break; /* end SPECIAL */
815 op
= itype_rt (inst
); /* branch condition */
820 case 16: /* BLTZAL */
821 case 18: /* BLTZALL */
823 if (read_signed_register (itype_rs (inst
)) < 0)
824 pc
+= mips32_relative_offset (inst
) + 4;
826 pc
+= 8; /* after the delay slot */
830 case 17: /* BGEZAL */
831 case 19: /* BGEZALL */
832 greater_equal_branch
:
833 if (read_signed_register (itype_rs (inst
)) >= 0)
834 pc
+= mips32_relative_offset (inst
) + 4;
836 pc
+= 8; /* after the delay slot */
838 /* All of the other instructions in the REGIMM category */
843 break; /* end REGIMM */
848 reg
= jtype_target (inst
) << 2;
849 /* Upper four bits get never changed... */
850 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
853 /* FIXME case JALX : */
856 reg
= jtype_target (inst
) << 2;
857 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
858 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
860 break; /* The new PC will be alternate mode */
861 case 4: /* BEQ, BEQL */
863 if (read_signed_register (itype_rs (inst
)) ==
864 read_signed_register (itype_rt (inst
)))
865 pc
+= mips32_relative_offset (inst
) + 4;
869 case 5: /* BNE, BNEL */
871 if (read_signed_register (itype_rs (inst
)) !=
872 read_signed_register (itype_rt (inst
)))
873 pc
+= mips32_relative_offset (inst
) + 4;
877 case 6: /* BLEZ, BLEZL */
879 if (read_signed_register (itype_rs (inst
) <= 0))
880 pc
+= mips32_relative_offset (inst
) + 4;
886 greater_branch
: /* BGTZ, BGTZL */
887 if (read_signed_register (itype_rs (inst
) > 0))
888 pc
+= mips32_relative_offset (inst
) + 4;
895 } /* mips32_next_pc */
897 /* Decoding the next place to set a breakpoint is irregular for the
898 mips 16 variant, but fortunately, there fewer instructions. We have to cope
899 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
900 We dont want to set a single step instruction on the extend instruction
904 /* Lots of mips16 instruction formats */
905 /* Predicting jumps requires itype,ritype,i8type
906 and their extensions extItype,extritype,extI8type
908 enum mips16_inst_fmts
910 itype
, /* 0 immediate 5,10 */
911 ritype
, /* 1 5,3,8 */
912 rrtype
, /* 2 5,3,3,5 */
913 rritype
, /* 3 5,3,3,5 */
914 rrrtype
, /* 4 5,3,3,3,2 */
915 rriatype
, /* 5 5,3,3,1,4 */
916 shifttype
, /* 6 5,3,3,3,2 */
917 i8type
, /* 7 5,3,8 */
918 i8movtype
, /* 8 5,3,3,5 */
919 i8mov32rtype
, /* 9 5,3,5,3 */
920 i64type
, /* 10 5,3,8 */
921 ri64type
, /* 11 5,3,3,5 */
922 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
923 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
924 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
925 extRRItype
, /* 15 5,5,5,5,3,3,5 */
926 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
927 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
928 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
929 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
930 extRi64type
, /* 20 5,6,5,5,3,3,5 */
931 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
933 /* I am heaping all the fields of the formats into one structure and
934 then, only the fields which are involved in instruction extension */
938 unsigned int regx
; /* Function in i8 type */
943 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
944 for the bits which make up the immediatate extension. */
947 extended_offset (unsigned int extension
)
950 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
952 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
954 value
|= extension
& 0x01f; /* extract 4:0 */
958 /* Only call this function if you know that this is an extendable
959 instruction, It wont malfunction, but why make excess remote memory references?
960 If the immediate operands get sign extended or somthing, do it after
961 the extension is performed.
963 /* FIXME: Every one of these cases needs to worry about sign extension
964 when the offset is to be used in relative addressing */
968 fetch_mips_16 (CORE_ADDR pc
)
971 pc
&= 0xfffffffe; /* clear the low order bit */
972 target_read_memory (pc
, buf
, 2);
973 return extract_unsigned_integer (buf
, 2);
977 unpack_mips16 (CORE_ADDR pc
,
978 unsigned int extension
,
980 enum mips16_inst_fmts insn_format
,
981 struct upk_mips16
*upk
)
993 value
= extended_offset (extension
);
994 value
= value
<< 11; /* rom for the original value */
995 value
|= inst
& 0x7ff; /* eleven bits from instruction */
999 value
= inst
& 0x7ff;
1000 /* FIXME : Consider sign extension */
1009 { /* A register identifier and an offset */
1010 /* Most of the fields are the same as I type but the
1011 immediate value is of a different length */
1015 value
= extended_offset (extension
);
1016 value
= value
<< 8; /* from the original instruction */
1017 value
|= inst
& 0xff; /* eleven bits from instruction */
1018 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1019 if (value
& 0x4000) /* test the sign bit , bit 26 */
1021 value
&= ~0x3fff; /* remove the sign bit */
1027 value
= inst
& 0xff; /* 8 bits */
1028 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1029 /* FIXME: Do sign extension , this format needs it */
1030 if (value
& 0x80) /* THIS CONFUSES ME */
1032 value
&= 0xef; /* remove the sign bit */
1042 unsigned long value
;
1043 unsigned int nexthalf
;
1044 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1045 value
= value
<< 16;
1046 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1054 internal_error (__FILE__
, __LINE__
,
1057 upk
->offset
= offset
;
1064 add_offset_16 (CORE_ADDR pc
, int offset
)
1066 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1071 extended_mips16_next_pc (CORE_ADDR pc
,
1072 unsigned int extension
,
1075 int op
= (insn
>> 11);
1078 case 2: /* Branch */
1081 struct upk_mips16 upk
;
1082 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1083 offset
= upk
.offset
;
1089 pc
+= (offset
<< 1) + 2;
1092 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1094 struct upk_mips16 upk
;
1095 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1096 pc
= add_offset_16 (pc
, upk
.offset
);
1097 if ((insn
>> 10) & 0x01) /* Exchange mode */
1098 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1105 struct upk_mips16 upk
;
1107 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1108 reg
= read_signed_register (upk
.regx
);
1110 pc
+= (upk
.offset
<< 1) + 2;
1117 struct upk_mips16 upk
;
1119 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1120 reg
= read_signed_register (upk
.regx
);
1122 pc
+= (upk
.offset
<< 1) + 2;
1127 case 12: /* I8 Formats btez btnez */
1129 struct upk_mips16 upk
;
1131 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1132 /* upk.regx contains the opcode */
1133 reg
= read_signed_register (24); /* Test register is 24 */
1134 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1135 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1136 /* pc = add_offset_16(pc,upk.offset) ; */
1137 pc
+= (upk
.offset
<< 1) + 2;
1142 case 29: /* RR Formats JR, JALR, JALR-RA */
1144 struct upk_mips16 upk
;
1145 /* upk.fmt = rrtype; */
1150 upk
.regx
= (insn
>> 8) & 0x07;
1151 upk
.regy
= (insn
>> 5) & 0x07;
1159 break; /* Function return instruction */
1165 break; /* BOGUS Guess */
1167 pc
= read_signed_register (reg
);
1174 /* This is an instruction extension. Fetch the real instruction
1175 (which follows the extension) and decode things based on
1179 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1192 mips16_next_pc (CORE_ADDR pc
)
1194 unsigned int insn
= fetch_mips_16 (pc
);
1195 return extended_mips16_next_pc (pc
, 0, insn
);
1198 /* The mips_next_pc function supports single_step when the remote
1199 target monitor or stub is not developed enough to do a single_step.
1200 It works by decoding the current instruction and predicting where a
1201 branch will go. This isnt hard because all the data is available.
1202 The MIPS32 and MIPS16 variants are quite different */
1204 mips_next_pc (CORE_ADDR pc
)
1207 return mips16_next_pc (pc
);
1209 return mips32_next_pc (pc
);
1212 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1216 mips_find_saved_regs (struct frame_info
*fci
)
1219 CORE_ADDR reg_position
;
1220 /* r0 bit means kernel trap */
1222 /* What registers have been saved? Bitmasks. */
1223 unsigned long gen_mask
, float_mask
;
1224 mips_extra_func_info_t proc_desc
;
1227 frame_saved_regs_zalloc (fci
);
1229 /* If it is the frame for sigtramp, the saved registers are located
1230 in a sigcontext structure somewhere on the stack.
1231 If the stack layout for sigtramp changes we might have to change these
1232 constants and the companion fixup_sigtramp in mdebugread.c */
1233 #ifndef SIGFRAME_BASE
1234 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1235 above the sigtramp frame. */
1236 #define SIGFRAME_BASE MIPS_REGSIZE
1237 /* FIXME! Are these correct?? */
1238 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1239 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1240 #define SIGFRAME_FPREGSAVE_OFF \
1241 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1243 #ifndef SIGFRAME_REG_SIZE
1244 /* FIXME! Is this correct?? */
1245 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1247 if (fci
->signal_handler_caller
)
1249 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1251 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1252 + ireg
* SIGFRAME_REG_SIZE
;
1253 fci
->saved_regs
[ireg
] = reg_position
;
1255 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1257 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1258 + ireg
* SIGFRAME_REG_SIZE
;
1259 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1261 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1265 proc_desc
= fci
->extra_info
->proc_desc
;
1266 if (proc_desc
== NULL
)
1267 /* I'm not sure how/whether this can happen. Normally when we can't
1268 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1269 and set the saved_regs right away. */
1272 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1273 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1274 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1276 if ( /* In any frame other than the innermost or a frame interrupted by
1277 a signal, we assume that all registers have been saved.
1278 This assumes that all register saves in a function happen before
1279 the first function call. */
1280 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1282 /* In a dummy frame we know exactly where things are saved. */
1283 && !PROC_DESC_IS_DUMMY (proc_desc
)
1285 /* Don't bother unless we are inside a function prologue. Outside the
1286 prologue, we know where everything is. */
1288 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1290 /* Not sure exactly what kernel_trap means, but if it means
1291 the kernel saves the registers without a prologue doing it,
1292 we better not examine the prologue to see whether registers
1293 have been saved yet. */
1296 /* We need to figure out whether the registers that the proc_desc
1297 claims are saved have been saved yet. */
1301 /* Bitmasks; set if we have found a save for the register. */
1302 unsigned long gen_save_found
= 0;
1303 unsigned long float_save_found
= 0;
1306 /* If the address is odd, assume this is MIPS16 code. */
1307 addr
= PROC_LOW_ADDR (proc_desc
);
1308 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1310 /* Scan through this function's instructions preceding the current
1311 PC, and look for those that save registers. */
1312 while (addr
< fci
->pc
)
1314 inst
= mips_fetch_instruction (addr
);
1315 if (pc_is_mips16 (addr
))
1316 mips16_decode_reg_save (inst
, &gen_save_found
);
1318 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1321 gen_mask
= gen_save_found
;
1322 float_mask
= float_save_found
;
1325 /* Fill in the offsets for the registers which gen_mask says
1327 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1328 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1329 if (gen_mask
& 0x80000000)
1331 fci
->saved_regs
[ireg
] = reg_position
;
1332 reg_position
-= MIPS_SAVED_REGSIZE
;
1335 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1336 of that normally used by gcc. Therefore, we have to fetch the first
1337 instruction of the function, and if it's an entry instruction that
1338 saves $s0 or $s1, correct their saved addresses. */
1339 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1341 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1342 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1345 int sreg_count
= (inst
>> 6) & 3;
1347 /* Check if the ra register was pushed on the stack. */
1348 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1350 reg_position
-= MIPS_SAVED_REGSIZE
;
1352 /* Check if the s0 and s1 registers were pushed on the stack. */
1353 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1355 fci
->saved_regs
[reg
] = reg_position
;
1356 reg_position
-= MIPS_SAVED_REGSIZE
;
1361 /* Fill in the offsets for the registers which float_mask says
1363 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1365 /* The freg_offset points to where the first *double* register
1366 is saved. So skip to the high-order word. */
1367 if (!GDB_TARGET_IS_MIPS64
)
1368 reg_position
+= MIPS_SAVED_REGSIZE
;
1370 /* Fill in the offsets for the float registers which float_mask says
1372 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1373 if (float_mask
& 0x80000000)
1375 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1376 reg_position
-= MIPS_SAVED_REGSIZE
;
1379 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1383 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1385 for (; fi
; fi
= fi
->next
)
1387 /* We have to get the saved sp from the sigcontext
1388 if it is a signal handler frame. */
1389 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1393 if (fi
->saved_regs
== NULL
)
1394 mips_find_saved_regs (fi
);
1395 if (fi
->saved_regs
[regno
])
1396 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1399 return read_signed_register (regno
);
1402 /* mips_addr_bits_remove - remove useless address bits */
1405 mips_addr_bits_remove (CORE_ADDR addr
)
1407 if (GDB_TARGET_IS_MIPS64
)
1409 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1411 /* This hack is a work-around for existing boards using
1412 PMON, the simulator, and any other 64-bit targets that
1413 doesn't have true 64-bit addressing. On these targets,
1414 the upper 32 bits of addresses are ignored by the
1415 hardware. Thus, the PC or SP are likely to have been
1416 sign extended to all 1s by instruction sequences that
1417 load 32-bit addresses. For example, a typical piece of
1418 code that loads an address is this:
1419 lui $r2, <upper 16 bits>
1420 ori $r2, <lower 16 bits>
1421 But the lui sign-extends the value such that the upper 32
1422 bits may be all 1s. The workaround is simply to mask off
1423 these bits. In the future, gcc may be changed to support
1424 true 64-bit addressing, and this masking will have to be
1426 addr
&= (CORE_ADDR
) 0xffffffff;
1429 else if (mips_mask_address_p ())
1431 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1432 masking off bits, instead, the actual target should be asking
1433 for the address to be converted to a valid pointer. */
1434 /* Even when GDB is configured for some 32-bit targets
1435 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1436 so CORE_ADDR is 64 bits. So we still have to mask off
1437 useless bits from addresses. */
1438 addr
&= (CORE_ADDR
) 0xffffffff;
1443 /* mips_software_single_step() is called just before we want to resume
1444 the inferior, if we want to single-step it but there is no hardware
1445 or kernel single-step support (MIPS on GNU/Linux for example). We find
1446 the target of the coming instruction and breakpoint it.
1448 single_step is also called just after the inferior stops. If we had
1449 set up a simulated single-step, we undo our damage. */
1452 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1454 static CORE_ADDR next_pc
;
1455 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1456 static binsn_quantum break_mem
;
1459 if (insert_breakpoints_p
)
1461 pc
= read_register (PC_REGNUM
);
1462 next_pc
= mips_next_pc (pc
);
1464 target_insert_breakpoint (next_pc
, break_mem
);
1467 target_remove_breakpoint (next_pc
, break_mem
);
1471 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1475 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1476 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1477 tmp
= mips_skip_stub (pc
);
1478 prev
->pc
= tmp
? tmp
: pc
;
1483 mips_frame_saved_pc (struct frame_info
*frame
)
1486 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1487 /* We have to get the saved pc from the sigcontext
1488 if it is a signal handler frame. */
1489 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1490 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1492 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1493 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1495 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1497 return ADDR_BITS_REMOVE (saved_pc
);
1500 static struct mips_extra_func_info temp_proc_desc
;
1501 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1503 /* Set a register's saved stack address in temp_saved_regs. If an address
1504 has already been set for this register, do nothing; this way we will
1505 only recognize the first save of a given register in a function prologue.
1506 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1509 set_reg_offset (int regno
, CORE_ADDR offset
)
1511 if (temp_saved_regs
[regno
] == 0)
1512 temp_saved_regs
[regno
] = offset
;
1516 /* Test whether the PC points to the return instruction at the
1517 end of a function. */
1520 mips_about_to_return (CORE_ADDR pc
)
1522 if (pc_is_mips16 (pc
))
1523 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1524 generates a "jr $ra"; other times it generates code to load
1525 the return address from the stack to an accessible register (such
1526 as $a3), then a "jr" using that register. This second case
1527 is almost impossible to distinguish from an indirect jump
1528 used for switch statements, so we don't even try. */
1529 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1531 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1535 /* This fencepost looks highly suspicious to me. Removing it also
1536 seems suspicious as it could affect remote debugging across serial
1540 heuristic_proc_start (CORE_ADDR pc
)
1547 pc
= ADDR_BITS_REMOVE (pc
);
1549 fence
= start_pc
- heuristic_fence_post
;
1553 if (heuristic_fence_post
== UINT_MAX
1554 || fence
< VM_MIN_ADDRESS
)
1555 fence
= VM_MIN_ADDRESS
;
1557 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1559 /* search back for previous return */
1560 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1561 if (start_pc
< fence
)
1563 /* It's not clear to me why we reach this point when
1564 stop_soon_quietly, but with this test, at least we
1565 don't print out warnings for every child forked (eg, on
1566 decstation). 22apr93 rich@cygnus.com. */
1567 if (!stop_soon_quietly
)
1569 static int blurb_printed
= 0;
1571 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1576 /* This actually happens frequently in embedded
1577 development, when you first connect to a board
1578 and your stack pointer and pc are nowhere in
1579 particular. This message needs to give people
1580 in that situation enough information to
1581 determine that it's no big deal. */
1582 printf_filtered ("\n\
1583 GDB is unable to find the start of the function at 0x%s\n\
1584 and thus can't determine the size of that function's stack frame.\n\
1585 This means that GDB may be unable to access that stack frame, or\n\
1586 the frames below it.\n\
1587 This problem is most likely caused by an invalid program counter or\n\
1589 However, if you think GDB should simply search farther back\n\
1590 from 0x%s for code which looks like the beginning of a\n\
1591 function, you can increase the range of the search using the `set\n\
1592 heuristic-fence-post' command.\n",
1593 paddr_nz (pc
), paddr_nz (pc
));
1600 else if (pc_is_mips16 (start_pc
))
1602 unsigned short inst
;
1604 /* On MIPS16, any one of the following is likely to be the
1605 start of a function:
1609 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1610 inst
= mips_fetch_instruction (start_pc
);
1611 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1612 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1613 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1614 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1616 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1617 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1622 else if (mips_about_to_return (start_pc
))
1624 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1631 /* Fetch the immediate value from a MIPS16 instruction.
1632 If the previous instruction was an EXTEND, use it to extend
1633 the upper bits of the immediate value. This is a helper function
1634 for mips16_heuristic_proc_desc. */
1637 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1638 unsigned short inst
, /* current instruction */
1639 int nbits
, /* number of bits in imm field */
1640 int scale
, /* scale factor to be applied to imm */
1641 int is_signed
) /* is the imm field signed? */
1645 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1647 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1648 if (offset
& 0x8000) /* check for negative extend */
1649 offset
= 0 - (0x10000 - (offset
& 0xffff));
1650 return offset
| (inst
& 0x1f);
1654 int max_imm
= 1 << nbits
;
1655 int mask
= max_imm
- 1;
1656 int sign_bit
= max_imm
>> 1;
1658 offset
= inst
& mask
;
1659 if (is_signed
&& (offset
& sign_bit
))
1660 offset
= 0 - (max_imm
- offset
);
1661 return offset
* scale
;
1666 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1667 stream from start_pc to limit_pc. */
1670 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1671 struct frame_info
*next_frame
, CORE_ADDR sp
)
1674 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1675 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1676 unsigned inst
= 0; /* current instruction */
1677 unsigned entry_inst
= 0; /* the entry instruction */
1680 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1681 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1683 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1685 /* Save the previous instruction. If it's an EXTEND, we'll extract
1686 the immediate offset extension from it in mips16_get_imm. */
1689 /* Fetch and decode the instruction. */
1690 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1691 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1692 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1694 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1695 if (offset
< 0) /* negative stack adjustment? */
1696 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1698 /* Exit loop if a positive stack adjustment is found, which
1699 usually means that the stack cleanup code in the function
1700 epilogue is reached. */
1703 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1705 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1706 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1707 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1708 set_reg_offset (reg
, sp
+ offset
);
1710 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1712 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1713 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1714 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1715 set_reg_offset (reg
, sp
+ offset
);
1717 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1719 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1720 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1721 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1723 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1725 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1726 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1727 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1729 else if (inst
== 0x673d) /* move $s1, $sp */
1732 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1734 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1736 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1737 frame_addr
= sp
+ offset
;
1738 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1739 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1741 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1743 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1744 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1745 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1746 set_reg_offset (reg
, frame_addr
+ offset
);
1748 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1750 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1751 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1752 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1753 set_reg_offset (reg
, frame_addr
+ offset
);
1755 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1756 entry_inst
= inst
; /* save for later processing */
1757 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1758 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1761 /* The entry instruction is typically the first instruction in a function,
1762 and it stores registers at offsets relative to the value of the old SP
1763 (before the prologue). But the value of the sp parameter to this
1764 function is the new SP (after the prologue has been executed). So we
1765 can't calculate those offsets until we've seen the entire prologue,
1766 and can calculate what the old SP must have been. */
1767 if (entry_inst
!= 0)
1769 int areg_count
= (entry_inst
>> 8) & 7;
1770 int sreg_count
= (entry_inst
>> 6) & 3;
1772 /* The entry instruction always subtracts 32 from the SP. */
1773 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1775 /* Now we can calculate what the SP must have been at the
1776 start of the function prologue. */
1777 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1779 /* Check if a0-a3 were saved in the caller's argument save area. */
1780 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1782 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1783 set_reg_offset (reg
, sp
+ offset
);
1784 offset
+= MIPS_SAVED_REGSIZE
;
1787 /* Check if the ra register was pushed on the stack. */
1789 if (entry_inst
& 0x20)
1791 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1792 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1793 offset
-= MIPS_SAVED_REGSIZE
;
1796 /* Check if the s0 and s1 registers were pushed on the stack. */
1797 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1799 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1800 set_reg_offset (reg
, sp
+ offset
);
1801 offset
-= MIPS_SAVED_REGSIZE
;
1807 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1808 struct frame_info
*next_frame
, CORE_ADDR sp
)
1811 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1813 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1814 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1815 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1816 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1818 unsigned long inst
, high_word
, low_word
;
1821 /* Fetch the instruction. */
1822 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1824 /* Save some code by pre-extracting some useful fields. */
1825 high_word
= (inst
>> 16) & 0xffff;
1826 low_word
= inst
& 0xffff;
1827 reg
= high_word
& 0x1f;
1829 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1830 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1831 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1833 if (low_word
& 0x8000) /* negative stack adjustment? */
1834 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1836 /* Exit loop if a positive stack adjustment is found, which
1837 usually means that the stack cleanup code in the function
1838 epilogue is reached. */
1841 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1843 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1844 set_reg_offset (reg
, sp
+ low_word
);
1846 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1848 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1849 but the register size used is only 32 bits. Make the address
1850 for the saved register point to the lower 32 bits. */
1851 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1852 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1854 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1856 /* Old gcc frame, r30 is virtual frame pointer. */
1857 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1858 frame_addr
= sp
+ low_word
;
1859 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1861 unsigned alloca_adjust
;
1862 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1863 frame_addr
= read_next_frame_reg (next_frame
, 30);
1864 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1865 if (alloca_adjust
> 0)
1867 /* FP > SP + frame_size. This may be because
1868 * of an alloca or somethings similar.
1869 * Fix sp to "pre-alloca" value, and try again.
1871 sp
+= alloca_adjust
;
1876 /* move $30,$sp. With different versions of gas this will be either
1877 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1878 Accept any one of these. */
1879 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1881 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1882 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1884 unsigned alloca_adjust
;
1885 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1886 frame_addr
= read_next_frame_reg (next_frame
, 30);
1887 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1888 if (alloca_adjust
> 0)
1890 /* FP > SP + frame_size. This may be because
1891 * of an alloca or somethings similar.
1892 * Fix sp to "pre-alloca" value, and try again.
1894 sp
+= alloca_adjust
;
1899 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1901 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1902 set_reg_offset (reg
, frame_addr
+ low_word
);
1907 static mips_extra_func_info_t
1908 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1909 struct frame_info
*next_frame
, int cur_frame
)
1914 sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1920 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1921 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1922 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1923 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1924 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1926 if (start_pc
+ 200 < limit_pc
)
1927 limit_pc
= start_pc
+ 200;
1928 if (pc_is_mips16 (start_pc
))
1929 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1931 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1932 return &temp_proc_desc
;
1935 static mips_extra_func_info_t
1936 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
1938 CORE_ADDR startaddr
;
1939 mips_extra_func_info_t proc_desc
;
1940 struct block
*b
= block_for_pc (pc
);
1943 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1945 *addrptr
= startaddr
;
1946 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1950 if (startaddr
> BLOCK_START (b
))
1951 /* This is the "pathological" case referred to in a comment in
1952 print_frame_info. It might be better to move this check into
1956 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1959 /* If we never found a PDR for this function in symbol reading, then
1960 examine prologues to find the information. */
1963 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1964 if (PROC_FRAME_REG (proc_desc
) == -1)
1974 static mips_extra_func_info_t
1975 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
1977 mips_extra_func_info_t proc_desc
;
1978 CORE_ADDR startaddr
;
1980 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1984 /* IF this is the topmost frame AND
1985 * (this proc does not have debugging information OR
1986 * the PC is in the procedure prologue)
1987 * THEN create a "heuristic" proc_desc (by analyzing
1988 * the actual code) to replace the "official" proc_desc.
1990 if (next_frame
== NULL
)
1992 struct symtab_and_line val
;
1993 struct symbol
*proc_symbol
=
1994 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1998 val
= find_pc_line (BLOCK_START
1999 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2001 val
.pc
= val
.end
? val
.end
: pc
;
2003 if (!proc_symbol
|| pc
< val
.pc
)
2005 mips_extra_func_info_t found_heuristic
=
2006 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2007 pc
, next_frame
, cur_frame
);
2008 if (found_heuristic
)
2009 proc_desc
= found_heuristic
;
2015 /* Is linked_proc_desc_table really necessary? It only seems to be used
2016 by procedure call dummys. However, the procedures being called ought
2017 to have their own proc_descs, and even if they don't,
2018 heuristic_proc_desc knows how to create them! */
2020 register struct linked_proc_info
*link
;
2022 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2023 if (PROC_LOW_ADDR (&link
->info
) <= pc
2024 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2028 startaddr
= heuristic_proc_start (pc
);
2031 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2037 get_frame_pointer (struct frame_info
*frame
,
2038 mips_extra_func_info_t proc_desc
)
2040 return ADDR_BITS_REMOVE (
2041 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
2042 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2045 mips_extra_func_info_t cached_proc_desc
;
2048 mips_frame_chain (struct frame_info
*frame
)
2050 mips_extra_func_info_t proc_desc
;
2052 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
2054 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
2057 /* Check if the PC is inside a call stub. If it is, fetch the
2058 PC of the caller of that stub. */
2059 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
2062 /* Look up the procedure descriptor for this PC. */
2063 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2067 cached_proc_desc
= proc_desc
;
2069 /* If no frame pointer and frame size is zero, we must be at end
2070 of stack (or otherwise hosed). If we don't check frame size,
2071 we loop forever if we see a zero size frame. */
2072 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2073 && PROC_FRAME_OFFSET (proc_desc
) == 0
2074 /* The previous frame from a sigtramp frame might be frameless
2075 and have frame size zero. */
2076 && !frame
->signal_handler_caller
)
2079 return get_frame_pointer (frame
, proc_desc
);
2083 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2087 /* Use proc_desc calculated in frame_chain */
2088 mips_extra_func_info_t proc_desc
=
2089 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
, 1);
2091 fci
->extra_info
= (struct frame_extra_info
*)
2092 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2094 fci
->saved_regs
= NULL
;
2095 fci
->extra_info
->proc_desc
=
2096 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2099 /* Fixup frame-pointer - only needed for top frame */
2100 /* This may not be quite right, if proc has a real frame register.
2101 Get the value of the frame relative sp, procedure might have been
2102 interrupted by a signal at it's very start. */
2103 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2104 && !PROC_DESC_IS_DUMMY (proc_desc
))
2105 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2107 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2109 if (proc_desc
== &temp_proc_desc
)
2113 /* Do not set the saved registers for a sigtramp frame,
2114 mips_find_saved_registers will do that for us.
2115 We can't use fci->signal_handler_caller, it is not yet set. */
2116 find_pc_partial_function (fci
->pc
, &name
,
2117 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2118 if (!PC_IN_SIGTRAMP (fci
->pc
, name
))
2120 frame_saved_regs_zalloc (fci
);
2121 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2122 fci
->saved_regs
[PC_REGNUM
]
2123 = fci
->saved_regs
[RA_REGNUM
];
2127 /* hack: if argument regs are saved, guess these contain args */
2128 /* assume we can't tell how many args for now */
2129 fci
->extra_info
->num_args
= -1;
2130 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2132 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2134 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2141 /* MIPS stack frames are almost impenetrable. When execution stops,
2142 we basically have to look at symbol information for the function
2143 that we stopped in, which tells us *which* register (if any) is
2144 the base of the frame pointer, and what offset from that register
2145 the frame itself is at.
2147 This presents a problem when trying to examine a stack in memory
2148 (that isn't executing at the moment), using the "frame" command. We
2149 don't have a PC, nor do we have any registers except SP.
2151 This routine takes two arguments, SP and PC, and tries to make the
2152 cached frames look as if these two arguments defined a frame on the
2153 cache. This allows the rest of info frame to extract the important
2154 arguments without difficulty. */
2157 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2160 error ("MIPS frame specifications require two arguments: sp and pc");
2162 return create_new_frame (argv
[0], argv
[1]);
2165 /* According to the current ABI, should the type be passed in a
2166 floating-point register (assuming that there is space)? When there
2167 is no FPU, FP are not even considered as possibile candidates for
2168 FP registers and, consequently this returns false - forces FP
2169 arguments into integer registers. */
2172 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2174 return ((typecode
== TYPE_CODE_FLT
2176 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2177 && TYPE_NFIELDS (arg_type
) == 1
2178 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2179 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2182 /* On o32, argument passing in GPRs depends on the alignment of the type being
2183 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2186 mips_type_needs_double_align (struct type
*type
)
2188 enum type_code typecode
= TYPE_CODE (type
);
2190 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2192 else if (typecode
== TYPE_CODE_STRUCT
)
2194 if (TYPE_NFIELDS (type
) < 1)
2196 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2198 else if (typecode
== TYPE_CODE_UNION
)
2202 n
= TYPE_NFIELDS (type
);
2203 for (i
= 0; i
< n
; i
++)
2204 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2212 mips_push_arguments (int nargs
,
2213 struct value
**args
,
2216 CORE_ADDR struct_addr
)
2222 int stack_offset
= 0;
2224 /* Macros to round N up or down to the next A boundary; A must be
2226 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2227 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2229 /* First ensure that the stack and structure return address (if any)
2230 are properly aligned. The stack has to be at least 64-bit aligned
2231 even on 32-bit machines, because doubles must be 64-bit aligned.
2232 On at least one MIPS variant, stack frames need to be 128-bit
2233 aligned, so we round to this widest known alignment. */
2234 sp
= ROUND_DOWN (sp
, 16);
2235 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2237 /* Now make space on the stack for the args. We allocate more
2238 than necessary for EABI, because the first few arguments are
2239 passed in registers, but that's OK. */
2240 for (argnum
= 0; argnum
< nargs
; argnum
++)
2241 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_STACK_ARGSIZE
);
2242 sp
-= ROUND_UP (len
, 16);
2245 fprintf_unfiltered (gdb_stdlog
, "mips_push_arguments: sp=0x%lx allocated %d\n",
2246 (long) sp
, ROUND_UP (len
, 16));
2248 /* Initialize the integer and float register pointers. */
2250 float_argreg
= FPA0_REGNUM
;
2252 /* the struct_return pointer occupies the first parameter-passing reg */
2256 fprintf_unfiltered (gdb_stdlog
,
2257 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2258 argreg
, (long) struct_addr
);
2259 write_register (argreg
++, struct_addr
);
2260 if (MIPS_REGS_HAVE_HOME_P
)
2261 stack_offset
+= MIPS_STACK_ARGSIZE
;
2264 /* Now load as many as possible of the first arguments into
2265 registers, and push the rest onto the stack. Loop thru args
2266 from first to last. */
2267 for (argnum
= 0; argnum
< nargs
; argnum
++)
2270 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2271 struct value
*arg
= args
[argnum
];
2272 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2273 int len
= TYPE_LENGTH (arg_type
);
2274 enum type_code typecode
= TYPE_CODE (arg_type
);
2277 fprintf_unfiltered (gdb_stdlog
,
2278 "mips_push_arguments: %d len=%d type=%d",
2279 argnum
+ 1, len
, (int) typecode
);
2281 /* The EABI passes structures that do not fit in a register by
2282 reference. In all other cases, pass the structure by value. */
2284 && len
> MIPS_SAVED_REGSIZE
2285 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2287 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2288 typecode
= TYPE_CODE_PTR
;
2289 len
= MIPS_SAVED_REGSIZE
;
2292 fprintf_unfiltered (gdb_stdlog
, " push");
2295 val
= (char *) VALUE_CONTENTS (arg
);
2297 /* 32-bit ABIs always start floating point arguments in an
2298 even-numbered floating point register. Round the FP register
2299 up before the check to see if there are any FP registers
2300 left. Non MIPS_EABI targets also pass the FP in the integer
2301 registers so also round up normal registers. */
2302 if (!FP_REGISTER_DOUBLE
2303 && fp_register_arg_p (typecode
, arg_type
))
2305 if ((float_argreg
& 1))
2309 /* Floating point arguments passed in registers have to be
2310 treated specially. On 32-bit architectures, doubles
2311 are passed in register pairs; the even register gets
2312 the low word, and the odd register gets the high word.
2313 On non-EABI processors, the first two floating point arguments are
2314 also copied to general registers, because MIPS16 functions
2315 don't use float registers for arguments. This duplication of
2316 arguments in general registers can't hurt non-MIPS16 functions
2317 because those registers are normally skipped. */
2318 /* MIPS_EABI squeezes a struct that contains a single floating
2319 point value into an FP register instead of pushing it onto the
2321 if (fp_register_arg_p (typecode
, arg_type
)
2322 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2324 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2326 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2327 unsigned long regval
;
2329 /* Write the low word of the double to the even register(s). */
2330 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2332 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2333 float_argreg
, phex (regval
, 4));
2334 write_register (float_argreg
++, regval
);
2338 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2339 argreg
, phex (regval
, 4));
2340 write_register (argreg
++, regval
);
2343 /* Write the high word of the double to the odd register(s). */
2344 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2346 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2347 float_argreg
, phex (regval
, 4));
2348 write_register (float_argreg
++, regval
);
2352 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2353 argreg
, phex (regval
, 4));
2354 write_register (argreg
++, regval
);
2360 /* This is a floating point value that fits entirely
2361 in a single register. */
2362 /* On 32 bit ABI's the float_argreg is further adjusted
2363 above to ensure that it is even register aligned. */
2364 LONGEST regval
= extract_unsigned_integer (val
, len
);
2366 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2367 float_argreg
, phex (regval
, len
));
2368 write_register (float_argreg
++, regval
);
2371 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2372 registers for each argument. The below is (my
2373 guess) to ensure that the corresponding integer
2374 register has reserved the same space. */
2376 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2377 argreg
, phex (regval
, len
));
2378 write_register (argreg
, regval
);
2379 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2382 /* Reserve space for the FP register. */
2383 if (MIPS_REGS_HAVE_HOME_P
)
2384 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
2388 /* Copy the argument to general registers or the stack in
2389 register-sized pieces. Large arguments are split between
2390 registers and stack. */
2391 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2392 are treated specially: Irix cc passes them in registers
2393 where gcc sometimes puts them on the stack. For maximum
2394 compatibility, we will put them in both places. */
2395 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2396 (len
% MIPS_SAVED_REGSIZE
!= 0));
2397 /* Structures should be aligned to eight bytes (even arg registers)
2398 on MIPS_ABI_O32 if their first member has double precision. */
2399 if (gdbarch_tdep (current_gdbarch
)->mips_abi
== MIPS_ABI_O32
2400 && mips_type_needs_double_align (arg_type
))
2405 /* Note: Floating-point values that didn't fit into an FP
2406 register are only written to memory. */
2409 /* Rememer if the argument was written to the stack. */
2410 int stack_used_p
= 0;
2411 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2414 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2417 /* Write this portion of the argument to the stack. */
2418 if (argreg
> MIPS_LAST_ARG_REGNUM
2420 || fp_register_arg_p (typecode
, arg_type
))
2422 /* Should shorter than int integer values be
2423 promoted to int before being stored? */
2424 int longword_offset
= 0;
2427 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2429 if (MIPS_STACK_ARGSIZE
== 8 &&
2430 (typecode
== TYPE_CODE_INT
||
2431 typecode
== TYPE_CODE_PTR
||
2432 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2433 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2434 else if ((typecode
== TYPE_CODE_STRUCT
||
2435 typecode
== TYPE_CODE_UNION
) &&
2436 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2437 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2442 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%lx",
2443 (long) stack_offset
);
2444 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%lx",
2445 (long) longword_offset
);
2448 addr
= sp
+ stack_offset
+ longword_offset
;
2453 fprintf_unfiltered (gdb_stdlog
, " @0x%lx ", (long) addr
);
2454 for (i
= 0; i
< partial_len
; i
++)
2456 fprintf_unfiltered (gdb_stdlog
, "%02x", val
[i
] & 0xff);
2459 write_memory (addr
, val
, partial_len
);
2462 /* Note!!! This is NOT an else clause. Odd sized
2463 structs may go thru BOTH paths. Floating point
2464 arguments will not. */
2465 /* Write this portion of the argument to a general
2466 purpose register. */
2467 if (argreg
<= MIPS_LAST_ARG_REGNUM
2468 && !fp_register_arg_p (typecode
, arg_type
))
2470 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2472 /* A non-floating-point argument being passed in a
2473 general register. If a struct or union, and if
2474 the remaining length is smaller than the register
2475 size, we have to adjust the register value on
2478 It does not seem to be necessary to do the
2479 same for integral types.
2481 Also don't do this adjustment on EABI and O64
2484 cagney/2001-07-23: gdb/179: Also, GCC, when
2485 outputting LE O32 with sizeof (struct) <
2486 MIPS_SAVED_REGSIZE, generates a left shift as
2487 part of storing the argument in a register a
2488 register (the left shift isn't generated when
2489 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
2490 is quite possible that this is GCC contradicting
2491 the LE/O32 ABI, GDB has not been adjusted to
2492 accommodate this. Either someone needs to
2493 demonstrate that the LE/O32 ABI specifies such a
2494 left shift OR this new ABI gets identified as
2495 such and GDB gets tweaked accordingly. */
2498 && MIPS_SAVED_REGSIZE
< 8
2499 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2500 && partial_len
< MIPS_SAVED_REGSIZE
2501 && (typecode
== TYPE_CODE_STRUCT
||
2502 typecode
== TYPE_CODE_UNION
))
2503 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2507 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2509 phex (regval
, MIPS_SAVED_REGSIZE
));
2510 write_register (argreg
, regval
);
2513 /* If this is the old ABI, prevent subsequent floating
2514 point arguments from being passed in floating point
2517 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2523 /* Compute the the offset into the stack at which we
2524 will copy the next parameter.
2526 In older ABIs, the caller reserved space for
2527 registers that contained arguments. This was loosely
2528 refered to as their "home". Consequently, space is
2531 In the new EABI (and the NABI32), the stack_offset
2532 only needs to be adjusted when it has been used.. */
2534 if (MIPS_REGS_HAVE_HOME_P
|| stack_used_p
)
2535 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2539 fprintf_unfiltered (gdb_stdlog
, "\n");
2542 /* Return adjusted stack pointer. */
2547 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2549 /* Set the return address register to point to the entry
2550 point of the program, where a breakpoint lies in wait. */
2551 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2556 mips_push_register (CORE_ADDR
* sp
, int regno
)
2558 char buffer
[MAX_REGISTER_RAW_SIZE
];
2561 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2563 regsize
= MIPS_SAVED_REGSIZE
;
2564 offset
= (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2565 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2570 regsize
= REGISTER_RAW_SIZE (regno
);
2574 read_register_gen (regno
, buffer
);
2575 write_memory (*sp
, buffer
+ offset
, regsize
);
2578 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2579 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2582 mips_push_dummy_frame (void)
2585 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2586 xmalloc (sizeof (struct linked_proc_info
));
2587 mips_extra_func_info_t proc_desc
= &link
->info
;
2588 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
2589 CORE_ADDR old_sp
= sp
;
2590 link
->next
= linked_proc_desc_table
;
2591 linked_proc_desc_table
= link
;
2593 /* FIXME! are these correct ? */
2594 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2595 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2596 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2597 #define FLOAT_SINGLE_REG_SAVE_MASK \
2598 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2600 * The registers we must save are all those not preserved across
2601 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2602 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2603 * and FP Control/Status registers.
2606 * Dummy frame layout:
2609 * Saved MMHI, MMLO, FPC_CSR
2614 * Saved D18 (i.e. F19, F18)
2616 * Saved D0 (i.e. F1, F0)
2617 * Argument build area and stack arguments written via mips_push_arguments
2621 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2622 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2623 PROC_FRAME_OFFSET (proc_desc
) = 0;
2624 PROC_FRAME_ADJUST (proc_desc
) = 0;
2625 mips_push_register (&sp
, PC_REGNUM
);
2626 mips_push_register (&sp
, HI_REGNUM
);
2627 mips_push_register (&sp
, LO_REGNUM
);
2628 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2630 /* Save general CPU registers */
2631 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2632 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2633 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2634 for (ireg
= 32; --ireg
>= 0;)
2635 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2636 mips_push_register (&sp
, ireg
);
2638 /* Save floating point registers starting with high order word */
2639 PROC_FREG_MASK (proc_desc
) =
2640 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2641 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2642 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2644 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2645 for (ireg
= 32; --ireg
>= 0;)
2646 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2647 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2649 /* Update the frame pointer for the call dummy and the stack pointer.
2650 Set the procedure's starting and ending addresses to point to the
2651 call dummy address at the entry point. */
2652 write_register (PUSH_FP_REGNUM
, old_sp
);
2653 write_register (SP_REGNUM
, sp
);
2654 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2655 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2656 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2657 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2661 mips_pop_frame (void)
2663 register int regnum
;
2664 struct frame_info
*frame
= get_current_frame ();
2665 CORE_ADDR new_sp
= FRAME_FP (frame
);
2667 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2669 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2670 if (frame
->saved_regs
== NULL
)
2671 mips_find_saved_regs (frame
);
2672 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2674 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2675 && frame
->saved_regs
[regnum
])
2676 write_register (regnum
,
2677 read_memory_integer (frame
->saved_regs
[regnum
],
2678 MIPS_SAVED_REGSIZE
));
2680 write_register (SP_REGNUM
, new_sp
);
2681 flush_cached_frames ();
2683 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2685 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2687 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2689 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2691 if (&pi_ptr
->info
== proc_desc
)
2696 error ("Can't locate dummy extra frame info\n");
2698 if (prev_ptr
!= NULL
)
2699 prev_ptr
->next
= pi_ptr
->next
;
2701 linked_proc_desc_table
= pi_ptr
->next
;
2705 write_register (HI_REGNUM
,
2706 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2707 MIPS_SAVED_REGSIZE
));
2708 write_register (LO_REGNUM
,
2709 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2710 MIPS_SAVED_REGSIZE
));
2711 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2712 write_register (FCRCS_REGNUM
,
2713 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2714 MIPS_SAVED_REGSIZE
));
2718 /* Floating point register management.
2720 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
2721 64bit operations, these early MIPS cpus treat fp register pairs
2722 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
2723 registers and offer a compatibility mode that emulates the MIPS2 fp
2724 model. When operating in MIPS2 fp compat mode, later cpu's split
2725 double precision floats into two 32-bit chunks and store them in
2726 consecutive fp regs. To display 64-bit floats stored in this
2727 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
2728 Throw in user-configurable endianness and you have a real mess.
2730 The way this works is:
2731 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
2732 double-precision value will be split across two logical registers.
2733 The lower-numbered logical register will hold the low-order bits,
2734 regardless of the processor's endianness.
2735 - If we are on a 64-bit processor, and we are looking for a
2736 single-precision value, it will be in the low ordered bits
2737 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
2738 save slot in memory.
2739 - If we are in 64-bit mode, everything is straightforward.
2741 Note that this code only deals with "live" registers at the top of the
2742 stack. We will attempt to deal with saved registers later, when
2743 the raw/cooked register interface is in place. (We need a general
2744 interface that can deal with dynamic saved register sizes -- fp
2745 regs could be 32 bits wide in one frame and 64 on the frame above
2748 static struct type
*
2749 mips_float_register_type (void)
2751 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2752 return builtin_type_ieee_single_big
;
2754 return builtin_type_ieee_single_little
;
2757 static struct type
*
2758 mips_double_register_type (void)
2760 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2761 return builtin_type_ieee_double_big
;
2763 return builtin_type_ieee_double_little
;
2766 /* Copy a 32-bit single-precision value from the current frame
2767 into rare_buffer. */
2770 mips_read_fp_register_single (int regno
, char *rare_buffer
)
2772 int raw_size
= REGISTER_RAW_SIZE (regno
);
2773 char *raw_buffer
= alloca (raw_size
);
2775 if (!frame_register_read (selected_frame
, regno
, raw_buffer
))
2776 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
2779 /* We have a 64-bit value for this register. Find the low-order
2783 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2788 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
2792 memcpy (rare_buffer
, raw_buffer
, 4);
2796 /* Copy a 64-bit double-precision value from the current frame into
2797 rare_buffer. This may include getting half of it from the next
2801 mips_read_fp_register_double (int regno
, char *rare_buffer
)
2803 int raw_size
= REGISTER_RAW_SIZE (regno
);
2805 if (raw_size
== 8 && !mips2_fp_compat ())
2807 /* We have a 64-bit value for this register, and we should use
2809 if (!frame_register_read (selected_frame
, regno
, rare_buffer
))
2810 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
2814 if ((regno
- FP0_REGNUM
) & 1)
2815 internal_error (__FILE__
, __LINE__
,
2816 "mips_read_fp_register_double: bad access to "
2817 "odd-numbered FP register");
2819 /* mips_read_fp_register_single will find the correct 32 bits from
2821 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2823 mips_read_fp_register_single (regno
, rare_buffer
+ 4);
2824 mips_read_fp_register_single (regno
+ 1, rare_buffer
);
2828 mips_read_fp_register_single (regno
, rare_buffer
);
2829 mips_read_fp_register_single (regno
+ 1, rare_buffer
+ 4);
2835 mips_print_register (int regnum
, int all
)
2837 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2839 /* Get the data in raw format. */
2840 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
2842 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2846 /* If we have a actual 32-bit floating point register (or we are in
2847 32-bit compatibility mode), and the register is even-numbered,
2848 also print it as a double (spanning two registers). */
2849 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2850 && (REGISTER_RAW_SIZE (regnum
) == 4
2851 || mips2_fp_compat ())
2852 && !((regnum
- FP0_REGNUM
) & 1))
2854 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2856 mips_read_fp_register_double (regnum
, dbuffer
);
2858 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2859 val_print (mips_double_register_type (), dbuffer
, 0, 0,
2860 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2861 printf_filtered ("); ");
2863 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2865 /* The problem with printing numeric register names (r26, etc.) is that
2866 the user can't use them on input. Probably the best solution is to
2867 fix it so that either the numeric or the funky (a2, etc.) names
2868 are accepted on input. */
2869 if (regnum
< MIPS_NUMREGS
)
2870 printf_filtered ("(r%d): ", regnum
);
2872 printf_filtered (": ");
2874 /* If virtual format is floating, print it that way. */
2875 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2876 if (REGISTER_RAW_SIZE (regnum
) == 8 && !mips2_fp_compat ())
2878 /* We have a meaningful 64-bit value in this register. Show
2879 it as a 32-bit float and a 64-bit double. */
2880 int offset
= 4 * (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
);
2882 printf_filtered (" (float) ");
2883 val_print (mips_float_register_type (), raw_buffer
+ offset
, 0, 0,
2884 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2885 printf_filtered (", (double) ");
2886 val_print (mips_double_register_type (), raw_buffer
, 0, 0,
2887 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2890 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2891 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2892 /* Else print as integer in hex. */
2897 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2898 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2902 print_scalar_formatted (raw_buffer
+ offset
,
2903 REGISTER_VIRTUAL_TYPE (regnum
),
2904 'x', 0, gdb_stdout
);
2908 /* Replacement for generic do_registers_info.
2909 Print regs in pretty columns. */
2912 do_fp_register_row (int regnum
)
2913 { /* do values for FP (float) regs */
2915 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2916 int inv1
, inv2
, inv3
;
2918 raw_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2920 if (REGISTER_RAW_SIZE (regnum
) == 4 || mips2_fp_compat ())
2922 /* 4-byte registers: we can fit two registers per row. */
2923 /* Also print every pair of 4-byte regs as an 8-byte double. */
2924 mips_read_fp_register_single (regnum
, raw_buffer
);
2925 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
2927 mips_read_fp_register_single (regnum
+ 1, raw_buffer
);
2928 flt2
= unpack_double (mips_float_register_type (), raw_buffer
, &inv2
);
2930 mips_read_fp_register_double (regnum
, raw_buffer
);
2931 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
2933 printf_filtered (" %-5s", REGISTER_NAME (regnum
));
2935 printf_filtered (": <invalid float>");
2937 printf_filtered ("%-17.9g", flt1
);
2939 printf_filtered (" %-5s", REGISTER_NAME (regnum
+ 1));
2941 printf_filtered (": <invalid float>");
2943 printf_filtered ("%-17.9g", flt2
);
2945 printf_filtered (" dbl: ");
2947 printf_filtered ("<invalid double>");
2949 printf_filtered ("%-24.17g", doub
);
2950 printf_filtered ("\n");
2952 /* may want to do hex display here (future enhancement) */
2957 /* Eight byte registers: print each one as float AND as double. */
2958 mips_read_fp_register_single (regnum
, raw_buffer
);
2959 flt1
= unpack_double (mips_double_register_type (), raw_buffer
, &inv1
);
2961 mips_read_fp_register_double (regnum
, raw_buffer
);
2962 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
2964 printf_filtered (" %-5s: ", REGISTER_NAME (regnum
));
2966 printf_filtered ("<invalid float>");
2968 printf_filtered ("flt: %-17.9g", flt1
);
2970 printf_filtered (" dbl: ");
2972 printf_filtered ("<invalid double>");
2974 printf_filtered ("%-24.17g", doub
);
2976 printf_filtered ("\n");
2977 /* may want to do hex display here (future enhancement) */
2983 /* Print a row's worth of GP (int) registers, with name labels above */
2986 do_gp_register_row (int regnum
)
2988 /* do values for GP (int) regs */
2989 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2990 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2992 int start_regnum
= regnum
;
2993 int numregs
= NUM_REGS
;
2996 /* For GP registers, we print a separate row of names above the vals */
2997 printf_filtered (" ");
2998 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
3000 if (*REGISTER_NAME (regnum
) == '\0')
3001 continue; /* unused register */
3002 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3003 break; /* end the row: reached FP register */
3004 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
3005 REGISTER_NAME (regnum
));
3008 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
3009 start_regnum
); /* print the R0 to R31 names */
3011 regnum
= start_regnum
; /* go back to start of row */
3012 /* now print the values in hex, 4 or 8 to the row */
3013 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
3015 if (*REGISTER_NAME (regnum
) == '\0')
3016 continue; /* unused register */
3017 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3018 break; /* end row: reached FP register */
3019 /* OK: get the data in raw format. */
3020 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3021 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
3022 /* pad small registers */
3023 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
3024 printf_filtered (" ");
3025 /* Now print the register value in hex, endian order. */
3026 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3027 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3028 byte
< REGISTER_RAW_SIZE (regnum
);
3030 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3032 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
3035 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3036 printf_filtered (" ");
3039 if (col
> 0) /* ie. if we actually printed anything... */
3040 printf_filtered ("\n");
3045 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
3048 mips_do_registers_info (int regnum
, int fpregs
)
3050 if (regnum
!= -1) /* do one specified register */
3052 if (*(REGISTER_NAME (regnum
)) == '\0')
3053 error ("Not a valid register for the current processor type");
3055 mips_print_register (regnum
, 0);
3056 printf_filtered ("\n");
3059 /* do all (or most) registers */
3062 while (regnum
< NUM_REGS
)
3064 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3065 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
3066 regnum
= do_fp_register_row (regnum
); /* FP regs */
3068 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
3070 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
3075 /* Return number of args passed to a frame. described by FIP.
3076 Can return -1, meaning no way to tell. */
3079 mips_frame_num_args (struct frame_info
*frame
)
3084 /* Is this a branch with a delay slot? */
3086 static int is_delayed (unsigned long);
3089 is_delayed (unsigned long insn
)
3092 for (i
= 0; i
< NUMOPCODES
; ++i
)
3093 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
3094 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
3096 return (i
< NUMOPCODES
3097 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
3098 | INSN_COND_BRANCH_DELAY
3099 | INSN_COND_BRANCH_LIKELY
)));
3103 mips_step_skips_delay (CORE_ADDR pc
)
3105 char buf
[MIPS_INSTLEN
];
3107 /* There is no branch delay slot on MIPS16. */
3108 if (pc_is_mips16 (pc
))
3111 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
3112 /* If error reading memory, guess that it is not a delayed branch. */
3114 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
3118 /* Skip the PC past function prologue instructions (32-bit version).
3119 This is a helper function for mips_skip_prologue. */
3122 mips32_skip_prologue (CORE_ADDR pc
)
3126 int seen_sp_adjust
= 0;
3127 int load_immediate_bytes
= 0;
3129 /* Skip the typical prologue instructions. These are the stack adjustment
3130 instruction and the instructions that save registers on the stack
3131 or in the gcc frame. */
3132 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
3134 unsigned long high_word
;
3136 inst
= mips_fetch_instruction (pc
);
3137 high_word
= (inst
>> 16) & 0xffff;
3139 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
3140 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
3142 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
3143 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
3145 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
3146 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
3147 && (inst
& 0x001F0000)) /* reg != $zero */
3150 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
3152 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
3154 continue; /* reg != $zero */
3156 /* move $s8,$sp. With different versions of gas this will be either
3157 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
3158 Accept any one of these. */
3159 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3162 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
3164 else if (high_word
== 0x3c1c) /* lui $gp,n */
3166 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
3168 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3169 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
3171 /* The following instructions load $at or $t0 with an immediate
3172 value in preparation for a stack adjustment via
3173 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
3174 a local variable, so we accept them only before a stack adjustment
3175 instruction was seen. */
3176 else if (!seen_sp_adjust
)
3178 if (high_word
== 0x3c01 || /* lui $at,n */
3179 high_word
== 0x3c08) /* lui $t0,n */
3181 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3184 else if (high_word
== 0x3421 || /* ori $at,$at,n */
3185 high_word
== 0x3508 || /* ori $t0,$t0,n */
3186 high_word
== 0x3401 || /* ori $at,$zero,n */
3187 high_word
== 0x3408) /* ori $t0,$zero,n */
3189 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3199 /* In a frameless function, we might have incorrectly
3200 skipped some load immediate instructions. Undo the skipping
3201 if the load immediate was not followed by a stack adjustment. */
3202 if (load_immediate_bytes
&& !seen_sp_adjust
)
3203 pc
-= load_immediate_bytes
;
3207 /* Skip the PC past function prologue instructions (16-bit version).
3208 This is a helper function for mips_skip_prologue. */
3211 mips16_skip_prologue (CORE_ADDR pc
)
3214 int extend_bytes
= 0;
3215 int prev_extend_bytes
;
3217 /* Table of instructions likely to be found in a function prologue. */
3220 unsigned short inst
;
3221 unsigned short mask
;
3228 , /* addiu $sp,offset */
3232 , /* daddiu $sp,offset */
3236 , /* sw reg,n($sp) */
3240 , /* sd reg,n($sp) */
3244 , /* sw $ra,n($sp) */
3248 , /* sd $ra,n($sp) */
3256 , /* sw $a0-$a3,n($s1) */
3260 , /* move reg,$a0-$a3 */
3264 , /* entry pseudo-op */
3268 , /* addiu $s1,$sp,n */
3271 } /* end of table marker */
3274 /* Skip the typical prologue instructions. These are the stack adjustment
3275 instruction and the instructions that save registers on the stack
3276 or in the gcc frame. */
3277 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
3279 unsigned short inst
;
3282 inst
= mips_fetch_instruction (pc
);
3284 /* Normally we ignore an extend instruction. However, if it is
3285 not followed by a valid prologue instruction, we must adjust
3286 the pc back over the extend so that it won't be considered
3287 part of the prologue. */
3288 if ((inst
& 0xf800) == 0xf000) /* extend */
3290 extend_bytes
= MIPS16_INSTLEN
;
3293 prev_extend_bytes
= extend_bytes
;
3296 /* Check for other valid prologue instructions besides extend. */
3297 for (i
= 0; table
[i
].mask
!= 0; i
++)
3298 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
3300 if (table
[i
].mask
!= 0) /* it was in table? */
3301 continue; /* ignore it */
3305 /* Return the current pc, adjusted backwards by 2 if
3306 the previous instruction was an extend. */
3307 return pc
- prev_extend_bytes
;
3313 /* To skip prologues, I use this predicate. Returns either PC itself
3314 if the code at PC does not look like a function prologue; otherwise
3315 returns an address that (if we're lucky) follows the prologue. If
3316 LENIENT, then we must skip everything which is involved in setting
3317 up the frame (it's OK to skip more, just so long as we don't skip
3318 anything which might clobber the registers which are being saved.
3319 We must skip more in the case where part of the prologue is in the
3320 delay slot of a non-prologue instruction). */
3323 mips_skip_prologue (CORE_ADDR pc
)
3325 /* See if we can determine the end of the prologue via the symbol table.
3326 If so, then return either PC, or the PC after the prologue, whichever
3329 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
3331 if (post_prologue_pc
!= 0)
3332 return max (pc
, post_prologue_pc
);
3334 /* Can't determine prologue from the symbol table, need to examine
3337 if (pc_is_mips16 (pc
))
3338 return mips16_skip_prologue (pc
);
3340 return mips32_skip_prologue (pc
);
3343 /* Determine how a return value is stored within the MIPS register
3344 file, given the return type `valtype'. */
3346 struct return_value_word
3355 return_value_location (struct type
*valtype
,
3356 struct return_value_word
*hi
,
3357 struct return_value_word
*lo
)
3359 int len
= TYPE_LENGTH (valtype
);
3361 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3362 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3363 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3365 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3367 /* We need to break a 64bit float in two 32 bit halves and
3368 spread them across a floating-point register pair. */
3369 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3370 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3371 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3372 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3374 hi
->reg_offset
= lo
->reg_offset
;
3375 lo
->reg
= FP0_REGNUM
+ 0;
3376 hi
->reg
= FP0_REGNUM
+ 1;
3382 /* The floating point value fits in a single floating-point
3384 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3385 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3388 lo
->reg
= FP0_REGNUM
;
3399 /* Locate a result possibly spread across two registers. */
3401 lo
->reg
= regnum
+ 0;
3402 hi
->reg
= regnum
+ 1;
3403 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3404 && len
< MIPS_SAVED_REGSIZE
)
3406 /* "un-left-justify" the value in the low register */
3407 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3412 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3413 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3414 && len
< MIPS_SAVED_REGSIZE
* 2
3415 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3416 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3418 /* "un-left-justify" the value spread across two registers. */
3419 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3420 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3422 hi
->len
= len
- lo
->len
;
3426 /* Only perform a partial copy of the second register. */
3429 if (len
> MIPS_SAVED_REGSIZE
)
3431 lo
->len
= MIPS_SAVED_REGSIZE
;
3432 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3440 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3441 && REGISTER_RAW_SIZE (regnum
) == 8
3442 && MIPS_SAVED_REGSIZE
== 4)
3444 /* Account for the fact that only the least-signficant part
3445 of the register is being used */
3446 lo
->reg_offset
+= 4;
3447 hi
->reg_offset
+= 4;
3450 hi
->buf_offset
= lo
->len
;
3454 /* Given a return value in `regbuf' with a type `valtype', extract and
3455 copy its value into `valbuf'. */
3458 mips_extract_return_value (struct type
*valtype
,
3459 char regbuf
[REGISTER_BYTES
],
3462 struct return_value_word lo
;
3463 struct return_value_word hi
;
3464 return_value_location (valtype
, &hi
, &lo
);
3466 memcpy (valbuf
+ lo
.buf_offset
,
3467 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3471 memcpy (valbuf
+ hi
.buf_offset
,
3472 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3476 /* Given a return value in `valbuf' with a type `valtype', write it's
3477 value into the appropriate register. */
3480 mips_store_return_value (struct type
*valtype
, char *valbuf
)
3482 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3483 struct return_value_word lo
;
3484 struct return_value_word hi
;
3485 return_value_location (valtype
, &hi
, &lo
);
3487 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3488 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3489 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3491 REGISTER_RAW_SIZE (lo
.reg
));
3495 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3496 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3497 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3499 REGISTER_RAW_SIZE (hi
.reg
));
3503 /* Exported procedure: Is PC in the signal trampoline code */
3506 in_sigtramp (CORE_ADDR pc
, char *ignore
)
3508 if (sigtramp_address
== 0)
3510 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3513 /* Root of all "set mips "/"show mips " commands. This will eventually be
3514 used for all MIPS-specific commands. */
3517 show_mips_command (char *args
, int from_tty
)
3519 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3523 set_mips_command (char *args
, int from_tty
)
3525 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3526 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3529 /* Commands to show/set the MIPS FPU type. */
3532 show_mipsfpu_command (char *args
, int from_tty
)
3535 switch (MIPS_FPU_TYPE
)
3537 case MIPS_FPU_SINGLE
:
3538 fpu
= "single-precision";
3540 case MIPS_FPU_DOUBLE
:
3541 fpu
= "double-precision";
3544 fpu
= "absent (none)";
3547 internal_error (__FILE__
, __LINE__
, "bad switch");
3549 if (mips_fpu_type_auto
)
3550 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3553 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3559 set_mipsfpu_command (char *args
, int from_tty
)
3561 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3562 show_mipsfpu_command (args
, from_tty
);
3566 set_mipsfpu_single_command (char *args
, int from_tty
)
3568 mips_fpu_type
= MIPS_FPU_SINGLE
;
3569 mips_fpu_type_auto
= 0;
3572 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3577 set_mipsfpu_double_command (char *args
, int from_tty
)
3579 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3580 mips_fpu_type_auto
= 0;
3583 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3588 set_mipsfpu_none_command (char *args
, int from_tty
)
3590 mips_fpu_type
= MIPS_FPU_NONE
;
3591 mips_fpu_type_auto
= 0;
3594 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3599 set_mipsfpu_auto_command (char *args
, int from_tty
)
3601 mips_fpu_type_auto
= 1;
3604 /* Command to set the processor type. */
3607 mips_set_processor_type_command (char *args
, int from_tty
)
3611 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3613 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3614 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3615 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3617 /* Restore the value. */
3618 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3623 if (!mips_set_processor_type (tmp_mips_processor_type
))
3625 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3626 /* Restore its value. */
3627 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3632 mips_show_processor_type_command (char *args
, int from_tty
)
3636 /* Modify the actual processor type. */
3639 mips_set_processor_type (char *str
)
3646 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3648 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3650 mips_processor_type
= str
;
3651 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3653 /* FIXME tweak fpu flag too */
3660 /* Attempt to identify the particular processor model by reading the
3664 mips_read_processor_type (void)
3668 prid
= read_register (PRID_REGNUM
);
3670 if ((prid
& ~0xf) == 0x700)
3671 return savestring ("r3041", strlen ("r3041"));
3676 /* Just like reinit_frame_cache, but with the right arguments to be
3677 callable as an sfunc. */
3680 reinit_frame_cache_sfunc (char *args
, int from_tty
,
3681 struct cmd_list_element
*c
)
3683 reinit_frame_cache ();
3687 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
3689 mips_extra_func_info_t proc_desc
;
3691 /* Search for the function containing this address. Set the low bit
3692 of the address when searching, in case we were given an even address
3693 that is the start of a 16-bit function. If we didn't do this,
3694 the search would fail because the symbol table says the function
3695 starts at an odd address, i.e. 1 byte past the given address. */
3696 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3697 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3699 /* Make an attempt to determine if this is a 16-bit function. If
3700 the procedure descriptor exists and the address therein is odd,
3701 it's definitely a 16-bit function. Otherwise, we have to just
3702 guess that if the address passed in is odd, it's 16-bits. */
3704 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
3705 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3707 info
->mach
= pc_is_mips16 (memaddr
) ?
3708 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3710 /* Round down the instruction address to the appropriate boundary. */
3711 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
3713 /* Call the appropriate disassembler based on the target endian-ness. */
3714 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3715 return print_insn_big_mips (memaddr
, info
);
3717 return print_insn_little_mips (memaddr
, info
);
3720 /* Old-style breakpoint macros.
3721 The IDT board uses an unusual breakpoint value, and sometimes gets
3722 confused when it sees the usual MIPS breakpoint instruction. */
3724 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3725 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3726 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3727 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3728 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3729 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3730 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3731 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3733 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3734 counter value to determine whether a 16- or 32-bit breakpoint should be
3735 used. It returns a pointer to a string of bytes that encode a breakpoint
3736 instruction, stores the length of the string to *lenptr, and adjusts pc
3737 (if necessary) to point to the actual memory location where the
3738 breakpoint should be inserted. */
3740 const unsigned char *
3741 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
3743 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3745 if (pc_is_mips16 (*pcptr
))
3747 static unsigned char mips16_big_breakpoint
[] =
3748 MIPS16_BIG_BREAKPOINT
;
3749 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3750 *lenptr
= sizeof (mips16_big_breakpoint
);
3751 return mips16_big_breakpoint
;
3755 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
3756 static unsigned char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3757 static unsigned char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3759 *lenptr
= sizeof (big_breakpoint
);
3761 if (strcmp (target_shortname
, "mips") == 0)
3762 return idt_big_breakpoint
;
3763 else if (strcmp (target_shortname
, "ddb") == 0
3764 || strcmp (target_shortname
, "pmon") == 0
3765 || strcmp (target_shortname
, "lsi") == 0)
3766 return pmon_big_breakpoint
;
3768 return big_breakpoint
;
3773 if (pc_is_mips16 (*pcptr
))
3775 static unsigned char mips16_little_breakpoint
[] =
3776 MIPS16_LITTLE_BREAKPOINT
;
3777 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3778 *lenptr
= sizeof (mips16_little_breakpoint
);
3779 return mips16_little_breakpoint
;
3783 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3784 static unsigned char pmon_little_breakpoint
[] =
3785 PMON_LITTLE_BREAKPOINT
;
3786 static unsigned char idt_little_breakpoint
[] =
3787 IDT_LITTLE_BREAKPOINT
;
3789 *lenptr
= sizeof (little_breakpoint
);
3791 if (strcmp (target_shortname
, "mips") == 0)
3792 return idt_little_breakpoint
;
3793 else if (strcmp (target_shortname
, "ddb") == 0
3794 || strcmp (target_shortname
, "pmon") == 0
3795 || strcmp (target_shortname
, "lsi") == 0)
3796 return pmon_little_breakpoint
;
3798 return little_breakpoint
;
3803 /* If PC is in a mips16 call or return stub, return the address of the target
3804 PC, which is either the callee or the caller. There are several
3805 cases which must be handled:
3807 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3808 target PC is in $31 ($ra).
3809 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3810 and the target PC is in $2.
3811 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3812 before the jal instruction, this is effectively a call stub
3813 and the the target PC is in $2. Otherwise this is effectively
3814 a return stub and the target PC is in $18.
3816 See the source code for the stubs in gcc/config/mips/mips16.S for
3819 This function implements the SKIP_TRAMPOLINE_CODE macro.
3823 mips_skip_stub (CORE_ADDR pc
)
3826 CORE_ADDR start_addr
;
3828 /* Find the starting address and name of the function containing the PC. */
3829 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3832 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3833 target PC is in $31 ($ra). */
3834 if (strcmp (name
, "__mips16_ret_sf") == 0
3835 || strcmp (name
, "__mips16_ret_df") == 0)
3836 return read_signed_register (RA_REGNUM
);
3838 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3840 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3841 and the target PC is in $2. */
3842 if (name
[19] >= '0' && name
[19] <= '9')
3843 return read_signed_register (2);
3845 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3846 before the jal instruction, this is effectively a call stub
3847 and the the target PC is in $2. Otherwise this is effectively
3848 a return stub and the target PC is in $18. */
3849 else if (name
[19] == 's' || name
[19] == 'd')
3851 if (pc
== start_addr
)
3853 /* Check if the target of the stub is a compiler-generated
3854 stub. Such a stub for a function bar might have a name
3855 like __fn_stub_bar, and might look like this:
3860 la $1,bar (becomes a lui/addiu pair)
3862 So scan down to the lui/addi and extract the target
3863 address from those two instructions. */
3865 CORE_ADDR target_pc
= read_signed_register (2);
3869 /* See if the name of the target function is __fn_stub_*. */
3870 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3872 if (strncmp (name
, "__fn_stub_", 10) != 0
3873 && strcmp (name
, "etext") != 0
3874 && strcmp (name
, "_etext") != 0)
3877 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3878 The limit on the search is arbitrarily set to 20
3879 instructions. FIXME. */
3880 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3882 inst
= mips_fetch_instruction (target_pc
);
3883 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3884 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3885 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3886 return pc
| (inst
& 0xffff); /* low word */
3889 /* Couldn't find the lui/addui pair, so return stub address. */
3893 /* This is the 'return' part of a call stub. The return
3894 address is in $r18. */
3895 return read_signed_register (18);
3898 return 0; /* not a stub */
3902 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3903 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3906 mips_in_call_stub (CORE_ADDR pc
, char *name
)
3908 CORE_ADDR start_addr
;
3910 /* Find the starting address of the function containing the PC. If the
3911 caller didn't give us a name, look it up at the same time. */
3912 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3915 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3917 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3918 if (name
[19] >= '0' && name
[19] <= '9')
3920 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3921 before the jal instruction, this is effectively a call stub. */
3922 else if (name
[19] == 's' || name
[19] == 'd')
3923 return pc
== start_addr
;
3926 return 0; /* not a stub */
3930 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3931 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3934 mips_in_return_stub (CORE_ADDR pc
, char *name
)
3936 CORE_ADDR start_addr
;
3938 /* Find the starting address of the function containing the PC. */
3939 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3942 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3943 if (strcmp (name
, "__mips16_ret_sf") == 0
3944 || strcmp (name
, "__mips16_ret_df") == 0)
3947 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3948 i.e. after the jal instruction, this is effectively a return stub. */
3949 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3950 && (name
[19] == 's' || name
[19] == 'd')
3951 && pc
!= start_addr
)
3954 return 0; /* not a stub */
3958 /* Return non-zero if the PC is in a library helper function that should
3959 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3962 mips_ignore_helper (CORE_ADDR pc
)
3966 /* Find the starting address and name of the function containing the PC. */
3967 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3970 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3971 that we want to ignore. */
3972 return (strcmp (name
, "__mips16_ret_sf") == 0
3973 || strcmp (name
, "__mips16_ret_df") == 0);
3977 /* Return a location where we can set a breakpoint that will be hit
3978 when an inferior function call returns. This is normally the
3979 program's entry point. Executables that don't have an entry
3980 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3981 whose address is the location where the breakpoint should be placed. */
3984 mips_call_dummy_address (void)
3986 struct minimal_symbol
*sym
;
3988 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3990 return SYMBOL_VALUE_ADDRESS (sym
);
3992 return entry_point_address ();
3996 /* If the current gcc for this target does not produce correct debugging
3997 information for float parameters, both prototyped and unprototyped, then
3998 define this macro. This forces gdb to always assume that floats are
3999 passed as doubles and then converted in the callee.
4001 For the mips chip, it appears that the debug info marks the parameters as
4002 floats regardless of whether the function is prototyped, but the actual
4003 values are passed as doubles for the non-prototyped case and floats for
4004 the prototyped case. Thus we choose to make the non-prototyped case work
4005 for C and break the prototyped case, since the non-prototyped case is
4006 probably much more common. (FIXME). */
4009 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
4011 return current_language
->la_language
== language_c
;
4014 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
4015 the register stored on the stack (32) is different to its real raw
4016 size (64). The below ensures that registers are fetched from the
4017 stack using their ABI size and then stored into the RAW_BUFFER
4018 using their raw size.
4020 The alternative to adding this function would be to add an ABI
4021 macro - REGISTER_STACK_SIZE(). */
4024 mips_get_saved_register (char *raw_buffer
,
4027 struct frame_info
*frame
,
4029 enum lval_type
*lval
)
4033 if (!target_has_registers
)
4034 error ("No registers.");
4036 /* Normal systems don't optimize out things with register numbers. */
4037 if (optimized
!= NULL
)
4039 addr
= find_saved_register (frame
, regnum
);
4043 *lval
= lval_memory
;
4044 if (regnum
== SP_REGNUM
)
4046 if (raw_buffer
!= NULL
)
4048 /* Put it back in target format. */
4049 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
4056 if (raw_buffer
!= NULL
)
4060 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
4062 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
4064 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
4065 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
4071 *lval
= lval_register
;
4072 addr
= REGISTER_BYTE (regnum
);
4073 if (raw_buffer
!= NULL
)
4074 read_register_gen (regnum
, raw_buffer
);
4080 /* Immediately after a function call, return the saved pc.
4081 Can't always go through the frames for this because on some machines
4082 the new frame is not set up until the new function executes
4083 some instructions. */
4086 mips_saved_pc_after_call (struct frame_info
*frame
)
4088 return read_signed_register (RA_REGNUM
);
4092 /* Convert a dbx stab register number (from `r' declaration) to a gdb
4096 mips_stab_reg_to_regnum (int num
)
4101 return num
+ FP0_REGNUM
- 38;
4104 /* Convert a ecoff register number to a gdb REGNUM */
4107 mips_ecoff_reg_to_regnum (int num
)
4112 return num
+ FP0_REGNUM
- 32;
4115 /* Convert an integer into an address. By first converting the value
4116 into a pointer and then extracting it signed, the address is
4117 guarenteed to be correctly sign extended. */
4120 mips_integer_to_address (struct type
*type
, void *buf
)
4122 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
4123 LONGEST val
= unpack_long (type
, buf
);
4124 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
4125 return extract_signed_integer (tmp
,
4126 TYPE_LENGTH (builtin_type_void_data_ptr
));
4130 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4132 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4133 const char *name
= bfd_get_section_name (abfd
, sect
);
4135 if (*abip
!= MIPS_ABI_UNKNOWN
)
4138 if (strncmp (name
, ".mdebug.", 8) != 0)
4141 if (strcmp (name
, ".mdebug.abi32") == 0)
4142 *abip
= MIPS_ABI_O32
;
4143 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4144 *abip
= MIPS_ABI_N32
;
4145 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4146 *abip
= MIPS_ABI_O64
;
4147 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4148 *abip
= MIPS_ABI_EABI32
;
4149 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4150 *abip
= MIPS_ABI_EABI64
;
4152 warning ("unsupported ABI %s.", name
+ 8);
4155 static struct gdbarch
*
4156 mips_gdbarch_init (struct gdbarch_info info
,
4157 struct gdbarch_list
*arches
)
4159 static LONGEST mips_call_dummy_words
[] =
4161 struct gdbarch
*gdbarch
;
4162 struct gdbarch_tdep
*tdep
;
4164 enum mips_abi mips_abi
;
4165 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
4167 /* Reset the disassembly info, in case it was set to something
4169 tm_print_insn_info
.flavour
= bfd_target_unknown_flavour
;
4170 tm_print_insn_info
.arch
= bfd_arch_unknown
;
4171 tm_print_insn_info
.mach
= 0;
4177 /* First of all, extract the elf_flags, if available. */
4178 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4179 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4181 /* Try to determine the OS ABI of the object we are loading. If
4182 we end up with `unknown', just leave it that way. */
4183 osabi
= gdbarch_lookup_osabi (info
.abfd
);
4186 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4187 switch ((elf_flags
& EF_MIPS_ABI
))
4189 case E_MIPS_ABI_O32
:
4190 mips_abi
= MIPS_ABI_O32
;
4192 case E_MIPS_ABI_O64
:
4193 mips_abi
= MIPS_ABI_O64
;
4195 case E_MIPS_ABI_EABI32
:
4196 mips_abi
= MIPS_ABI_EABI32
;
4198 case E_MIPS_ABI_EABI64
:
4199 mips_abi
= MIPS_ABI_EABI64
;
4202 if ((elf_flags
& EF_MIPS_ABI2
))
4203 mips_abi
= MIPS_ABI_N32
;
4205 mips_abi
= MIPS_ABI_UNKNOWN
;
4209 /* GCC creates a pseudo-section whose name describes the ABI. */
4210 if (mips_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4211 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &mips_abi
);
4213 /* Try the architecture for any hint of the corect ABI */
4214 if (mips_abi
== MIPS_ABI_UNKNOWN
4215 && info
.bfd_arch_info
!= NULL
4216 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4218 switch (info
.bfd_arch_info
->mach
)
4220 case bfd_mach_mips3900
:
4221 mips_abi
= MIPS_ABI_EABI32
;
4223 case bfd_mach_mips4100
:
4224 case bfd_mach_mips5000
:
4225 mips_abi
= MIPS_ABI_EABI64
;
4227 case bfd_mach_mips8000
:
4228 case bfd_mach_mips10000
:
4229 mips_abi
= MIPS_ABI_N32
;
4233 #ifdef MIPS_DEFAULT_ABI
4234 if (mips_abi
== MIPS_ABI_UNKNOWN
)
4235 mips_abi
= MIPS_DEFAULT_ABI
;
4240 fprintf_unfiltered (gdb_stdlog
,
4241 "mips_gdbarch_init: elf_flags = 0x%08x\n",
4243 fprintf_unfiltered (gdb_stdlog
,
4244 "mips_gdbarch_init: mips_abi = %d\n",
4248 /* try to find a pre-existing architecture */
4249 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4251 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4253 /* MIPS needs to be pedantic about which ABI the object is
4255 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4257 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4259 if (gdbarch_tdep (arches
->gdbarch
)->osabi
== osabi
)
4260 return arches
->gdbarch
;
4263 /* Need a new architecture. Fill in a target specific vector. */
4264 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4265 gdbarch
= gdbarch_alloc (&info
, tdep
);
4266 tdep
->elf_flags
= elf_flags
;
4267 tdep
->osabi
= osabi
;
4269 /* Initially set everything according to the default ABI/ISA. */
4270 set_gdbarch_short_bit (gdbarch
, 16);
4271 set_gdbarch_int_bit (gdbarch
, 32);
4272 set_gdbarch_float_bit (gdbarch
, 32);
4273 set_gdbarch_double_bit (gdbarch
, 64);
4274 set_gdbarch_long_double_bit (gdbarch
, 64);
4275 set_gdbarch_register_raw_size (gdbarch
, mips_register_raw_size
);
4276 tdep
->mips_abi
= mips_abi
;
4281 tdep
->mips_abi_string
= "o32";
4282 tdep
->mips_default_saved_regsize
= 4;
4283 tdep
->mips_default_stack_argsize
= 4;
4284 tdep
->mips_fp_register_double
= 0;
4285 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4286 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4287 tdep
->mips_regs_have_home_p
= 1;
4288 tdep
->gdb_target_is_mips64
= 0;
4289 tdep
->default_mask_address_p
= 0;
4290 set_gdbarch_long_bit (gdbarch
, 32);
4291 set_gdbarch_ptr_bit (gdbarch
, 32);
4292 set_gdbarch_long_long_bit (gdbarch
, 64);
4295 tdep
->mips_abi_string
= "o64";
4296 tdep
->mips_default_saved_regsize
= 8;
4297 tdep
->mips_default_stack_argsize
= 8;
4298 tdep
->mips_fp_register_double
= 1;
4299 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4300 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4301 tdep
->mips_regs_have_home_p
= 1;
4302 tdep
->gdb_target_is_mips64
= 1;
4303 tdep
->default_mask_address_p
= 0;
4304 set_gdbarch_long_bit (gdbarch
, 32);
4305 set_gdbarch_ptr_bit (gdbarch
, 32);
4306 set_gdbarch_long_long_bit (gdbarch
, 64);
4308 case MIPS_ABI_EABI32
:
4309 tdep
->mips_abi_string
= "eabi32";
4310 tdep
->mips_default_saved_regsize
= 4;
4311 tdep
->mips_default_stack_argsize
= 4;
4312 tdep
->mips_fp_register_double
= 0;
4313 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4314 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4315 tdep
->mips_regs_have_home_p
= 0;
4316 tdep
->gdb_target_is_mips64
= 0;
4317 tdep
->default_mask_address_p
= 0;
4318 set_gdbarch_long_bit (gdbarch
, 32);
4319 set_gdbarch_ptr_bit (gdbarch
, 32);
4320 set_gdbarch_long_long_bit (gdbarch
, 64);
4322 case MIPS_ABI_EABI64
:
4323 tdep
->mips_abi_string
= "eabi64";
4324 tdep
->mips_default_saved_regsize
= 8;
4325 tdep
->mips_default_stack_argsize
= 8;
4326 tdep
->mips_fp_register_double
= 1;
4327 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4328 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4329 tdep
->mips_regs_have_home_p
= 0;
4330 tdep
->gdb_target_is_mips64
= 1;
4331 tdep
->default_mask_address_p
= 0;
4332 set_gdbarch_long_bit (gdbarch
, 64);
4333 set_gdbarch_ptr_bit (gdbarch
, 64);
4334 set_gdbarch_long_long_bit (gdbarch
, 64);
4337 tdep
->mips_abi_string
= "n32";
4338 tdep
->mips_default_saved_regsize
= 4;
4339 tdep
->mips_default_stack_argsize
= 8;
4340 tdep
->mips_fp_register_double
= 1;
4341 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4342 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4343 tdep
->mips_regs_have_home_p
= 0;
4344 tdep
->gdb_target_is_mips64
= 0;
4345 tdep
->default_mask_address_p
= 0;
4346 set_gdbarch_long_bit (gdbarch
, 32);
4347 set_gdbarch_ptr_bit (gdbarch
, 32);
4348 set_gdbarch_long_long_bit (gdbarch
, 64);
4350 /* Set up the disassembler info, so that we get the right
4351 register names from libopcodes. */
4352 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
4353 tm_print_insn_info
.arch
= bfd_arch_mips
;
4354 if (info
.bfd_arch_info
!= NULL
4355 && info
.bfd_arch_info
->arch
== bfd_arch_mips
4356 && info
.bfd_arch_info
->mach
)
4357 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
4359 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
4362 tdep
->mips_abi_string
= "default";
4363 tdep
->mips_default_saved_regsize
= MIPS_REGSIZE
;
4364 tdep
->mips_default_stack_argsize
= MIPS_REGSIZE
;
4365 tdep
->mips_fp_register_double
= (REGISTER_VIRTUAL_SIZE (FP0_REGNUM
) == 8);
4366 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4367 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4368 tdep
->mips_regs_have_home_p
= 1;
4369 tdep
->gdb_target_is_mips64
= 0;
4370 tdep
->default_mask_address_p
= 0;
4371 set_gdbarch_long_bit (gdbarch
, 32);
4372 set_gdbarch_ptr_bit (gdbarch
, 32);
4373 set_gdbarch_long_long_bit (gdbarch
, 64);
4377 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4378 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4381 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4382 flag in object files because to do so would make it impossible to
4383 link with libraries compiled without "-gp32". This is
4384 unnecessarily restrictive.
4386 We could solve this problem by adding "-gp32" multilibs to gcc,
4387 but to set this flag before gcc is built with such multilibs will
4388 break too many systems.''
4390 But even more unhelpfully, the default linker output target for
4391 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4392 for 64-bit programs - you need to change the ABI to change this,
4393 and not all gcc targets support that currently. Therefore using
4394 this flag to detect 32-bit mode would do the wrong thing given
4395 the current gcc - it would make GDB treat these 64-bit programs
4396 as 32-bit programs by default. */
4398 /* enable/disable the MIPS FPU */
4399 if (!mips_fpu_type_auto
)
4400 tdep
->mips_fpu_type
= mips_fpu_type
;
4401 else if (info
.bfd_arch_info
!= NULL
4402 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4403 switch (info
.bfd_arch_info
->mach
)
4405 case bfd_mach_mips3900
:
4406 case bfd_mach_mips4100
:
4407 case bfd_mach_mips4111
:
4408 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
4410 case bfd_mach_mips4650
:
4411 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
4414 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4418 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4420 /* MIPS version of register names. NOTE: At present the MIPS
4421 register name management is part way between the old -
4422 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4423 Further work on it is required. */
4424 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4425 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
4426 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4427 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4428 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4429 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4431 /* Add/remove bits from an address. The MIPS needs be careful to
4432 ensure that all 32 bit addresses are sign extended to 64 bits. */
4433 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
4435 /* There's a mess in stack frame creation. See comments in
4436 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
4437 set_gdbarch_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
4438 set_gdbarch_init_frame_pc (gdbarch
, init_frame_pc_noop
);
4440 /* Map debug register numbers onto internal register numbers. */
4441 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
4442 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_ecoff_reg_to_regnum
);
4444 /* Initialize a frame */
4445 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
4447 /* MIPS version of CALL_DUMMY */
4449 set_gdbarch_call_dummy_p (gdbarch
, 1);
4450 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4451 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
4452 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4453 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4454 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4455 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4456 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4457 set_gdbarch_call_dummy_length (gdbarch
, 0);
4458 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4459 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4460 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4461 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4462 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4463 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4464 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4466 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4467 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
4469 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4470 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
4471 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4473 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
4474 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
4476 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
4477 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
4478 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
4480 /* Hook in OS ABI-specific overrides, if they have been registered. */
4481 gdbarch_init_osabi (info
, gdbarch
, osabi
);
4487 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4489 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4493 int ef_mips_32bitmode
;
4494 /* determine the ISA */
4495 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
4513 /* determine the size of a pointer */
4514 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
4515 fprintf_unfiltered (file
,
4516 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4518 fprintf_unfiltered (file
,
4519 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4521 fprintf_unfiltered (file
,
4522 "mips_dump_tdep: ef_mips_arch = %d\n",
4524 fprintf_unfiltered (file
,
4525 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4527 tdep
->mips_abi_string
);
4528 fprintf_unfiltered (file
,
4529 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4530 mips_mask_address_p (),
4531 tdep
->default_mask_address_p
);
4533 fprintf_unfiltered (file
,
4534 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4535 FP_REGISTER_DOUBLE
);
4536 fprintf_unfiltered (file
,
4537 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4538 MIPS_DEFAULT_FPU_TYPE
,
4539 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4540 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4541 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4543 fprintf_unfiltered (file
,
4544 "mips_dump_tdep: MIPS_EABI = %d\n",
4546 fprintf_unfiltered (file
,
4547 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4548 MIPS_LAST_FP_ARG_REGNUM
,
4549 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
4550 fprintf_unfiltered (file
,
4551 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4553 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4554 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4555 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4557 fprintf_unfiltered (file
,
4558 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4559 MIPS_DEFAULT_SAVED_REGSIZE
);
4560 fprintf_unfiltered (file
,
4561 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4562 FP_REGISTER_DOUBLE
);
4563 fprintf_unfiltered (file
,
4564 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4565 MIPS_REGS_HAVE_HOME_P
);
4566 fprintf_unfiltered (file
,
4567 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4568 MIPS_DEFAULT_STACK_ARGSIZE
);
4569 fprintf_unfiltered (file
,
4570 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4571 MIPS_STACK_ARGSIZE
);
4572 fprintf_unfiltered (file
,
4573 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4575 fprintf_unfiltered (file
,
4576 "mips_dump_tdep: A0_REGNUM = %d\n",
4578 fprintf_unfiltered (file
,
4579 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4580 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
4581 fprintf_unfiltered (file
,
4582 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4583 XSTRING (ATTACH_DETACH
));
4584 fprintf_unfiltered (file
,
4585 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4587 fprintf_unfiltered (file
,
4588 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4589 fprintf_unfiltered (file
,
4590 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4592 fprintf_unfiltered (file
,
4593 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4595 fprintf_unfiltered (file
,
4596 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4598 fprintf_unfiltered (file
,
4599 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4600 XSTRING (DO_REGISTERS_INFO
));
4601 fprintf_unfiltered (file
,
4602 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4603 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
4604 fprintf_unfiltered (file
,
4605 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4606 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
4607 fprintf_unfiltered (file
,
4608 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4609 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
4610 fprintf_unfiltered (file
,
4611 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4613 fprintf_unfiltered (file
,
4614 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4616 fprintf_unfiltered (file
,
4617 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4618 FIRST_EMBED_REGNUM
);
4619 fprintf_unfiltered (file
,
4620 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4622 fprintf_unfiltered (file
,
4623 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4624 GDB_TARGET_IS_MIPS64
);
4625 fprintf_unfiltered (file
,
4626 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4627 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
4628 fprintf_unfiltered (file
,
4629 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4630 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
4631 fprintf_unfiltered (file
,
4632 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4634 fprintf_unfiltered (file
,
4635 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4636 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
4637 fprintf_unfiltered (file
,
4638 "mips_dump_tdep: HI_REGNUM = %d\n",
4640 fprintf_unfiltered (file
,
4641 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4642 fprintf_unfiltered (file
,
4643 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4644 fprintf_unfiltered (file
,
4645 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4646 XSTRING (IGNORE_HELPER_CALL (PC
)));
4647 fprintf_unfiltered (file
,
4648 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4649 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
4650 fprintf_unfiltered (file
,
4651 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4652 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
4653 fprintf_unfiltered (file
,
4654 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4655 fprintf_unfiltered (file
,
4656 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4658 fprintf_unfiltered (file
,
4659 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4660 fprintf_unfiltered (file
,
4661 "mips_dump_tdep: LO_REGNUM = %d\n",
4663 #ifdef MACHINE_CPROC_FP_OFFSET
4664 fprintf_unfiltered (file
,
4665 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4666 MACHINE_CPROC_FP_OFFSET
);
4668 #ifdef MACHINE_CPROC_PC_OFFSET
4669 fprintf_unfiltered (file
,
4670 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4671 MACHINE_CPROC_PC_OFFSET
);
4673 #ifdef MACHINE_CPROC_SP_OFFSET
4674 fprintf_unfiltered (file
,
4675 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4676 MACHINE_CPROC_SP_OFFSET
);
4678 fprintf_unfiltered (file
,
4679 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4680 fprintf_unfiltered (file
,
4681 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4682 fprintf_unfiltered (file
,
4683 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4685 fprintf_unfiltered (file
,
4686 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4687 fprintf_unfiltered (file
,
4688 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4689 fprintf_unfiltered (file
,
4690 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4691 fprintf_unfiltered (file
,
4692 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4694 fprintf_unfiltered (file
,
4695 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
4696 MIPS_LAST_ARG_REGNUM
,
4697 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
4698 fprintf_unfiltered (file
,
4699 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4701 fprintf_unfiltered (file
,
4702 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4703 fprintf_unfiltered (file
,
4704 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4705 MIPS_SAVED_REGSIZE
);
4706 fprintf_unfiltered (file
,
4707 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4708 fprintf_unfiltered (file
,
4709 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4710 XSTRING (MSYMBOL_SIZE (MSYM
)));
4711 fprintf_unfiltered (file
,
4712 "mips_dump_tdep: OP_LDFPR = used?\n");
4713 fprintf_unfiltered (file
,
4714 "mips_dump_tdep: OP_LDGPR = used?\n");
4715 fprintf_unfiltered (file
,
4716 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4717 fprintf_unfiltered (file
,
4718 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4719 fprintf_unfiltered (file
,
4720 "mips_dump_tdep: PRID_REGNUM = %d\n",
4722 fprintf_unfiltered (file
,
4723 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4724 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
4725 fprintf_unfiltered (file
,
4726 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4727 fprintf_unfiltered (file
,
4728 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4729 fprintf_unfiltered (file
,
4730 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4731 fprintf_unfiltered (file
,
4732 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4733 fprintf_unfiltered (file
,
4734 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4735 fprintf_unfiltered (file
,
4736 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4737 fprintf_unfiltered (file
,
4738 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4739 fprintf_unfiltered (file
,
4740 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4741 fprintf_unfiltered (file
,
4742 "mips_dump_tdep: PROC_PC_REG = function?\n");
4743 fprintf_unfiltered (file
,
4744 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4745 fprintf_unfiltered (file
,
4746 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4747 fprintf_unfiltered (file
,
4748 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4749 fprintf_unfiltered (file
,
4750 "mips_dump_tdep: PS_REGNUM = %d\n",
4752 fprintf_unfiltered (file
,
4753 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4755 fprintf_unfiltered (file
,
4756 "mips_dump_tdep: RA_REGNUM = %d\n",
4758 fprintf_unfiltered (file
,
4759 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4760 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4761 fprintf_unfiltered (file
,
4762 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4763 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4764 fprintf_unfiltered (file
,
4765 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4766 fprintf_unfiltered (file
,
4767 "mips_dump_tdep: ROUND_DOWN = function?\n");
4768 fprintf_unfiltered (file
,
4769 "mips_dump_tdep: ROUND_UP = function?\n");
4771 fprintf_unfiltered (file
,
4772 "mips_dump_tdep: SAVED_BYTES = %d\n",
4776 fprintf_unfiltered (file
,
4777 "mips_dump_tdep: SAVED_FP = %d\n",
4781 fprintf_unfiltered (file
,
4782 "mips_dump_tdep: SAVED_PC = %d\n",
4785 fprintf_unfiltered (file
,
4786 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
4787 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
4788 fprintf_unfiltered (file
,
4789 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
4790 fprintf_unfiltered (file
,
4791 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
4793 fprintf_unfiltered (file
,
4794 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
4795 SIGFRAME_FPREGSAVE_OFF
);
4796 fprintf_unfiltered (file
,
4797 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
4799 fprintf_unfiltered (file
,
4800 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
4801 SIGFRAME_REGSAVE_OFF
);
4802 fprintf_unfiltered (file
,
4803 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
4805 fprintf_unfiltered (file
,
4806 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
4807 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
4808 fprintf_unfiltered (file
,
4809 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
4810 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
4811 fprintf_unfiltered (file
,
4812 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
4813 SOFTWARE_SINGLE_STEP_P ());
4814 fprintf_unfiltered (file
,
4815 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
4816 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
4817 #ifdef STACK_END_ADDR
4818 fprintf_unfiltered (file
,
4819 "mips_dump_tdep: STACK_END_ADDR = %d\n",
4822 fprintf_unfiltered (file
,
4823 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
4824 XSTRING (STEP_SKIPS_DELAY (PC
)));
4825 fprintf_unfiltered (file
,
4826 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
4827 STEP_SKIPS_DELAY_P
);
4828 fprintf_unfiltered (file
,
4829 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
4830 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
4831 fprintf_unfiltered (file
,
4832 "mips_dump_tdep: T9_REGNUM = %d\n",
4834 fprintf_unfiltered (file
,
4835 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
4836 fprintf_unfiltered (file
,
4837 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
4838 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
4839 fprintf_unfiltered (file
,
4840 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
4841 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
4842 fprintf_unfiltered (file
,
4843 "mips_dump_tdep: TARGET_MIPS = used?\n");
4844 fprintf_unfiltered (file
,
4845 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
4846 XSTRING (TM_PRINT_INSN_MACH
));
4848 fprintf_unfiltered (file
,
4849 "mips_dump_tdep: TRACE_CLEAR # %s\n",
4850 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
4853 fprintf_unfiltered (file
,
4854 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
4857 #ifdef TRACE_FLAVOR_SIZE
4858 fprintf_unfiltered (file
,
4859 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
4863 fprintf_unfiltered (file
,
4864 "mips_dump_tdep: TRACE_SET # %s\n",
4865 XSTRING (TRACE_SET (X
,STATE
)));
4867 fprintf_unfiltered (file
,
4868 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
4869 #ifdef UNUSED_REGNUM
4870 fprintf_unfiltered (file
,
4871 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
4874 fprintf_unfiltered (file
,
4875 "mips_dump_tdep: V0_REGNUM = %d\n",
4877 fprintf_unfiltered (file
,
4878 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
4879 (long) VM_MIN_ADDRESS
);
4881 fprintf_unfiltered (file
,
4882 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
4885 fprintf_unfiltered (file
,
4886 "mips_dump_tdep: ZERO_REGNUM = %d\n",
4888 fprintf_unfiltered (file
,
4889 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
4892 fprintf_unfiltered (file
,
4893 "mips_dump_tdep: OS ABI = %s\n",
4894 gdbarch_osabi_name (tdep
->osabi
));
4898 _initialize_mips_tdep (void)
4900 static struct cmd_list_element
*mipsfpulist
= NULL
;
4901 struct cmd_list_element
*c
;
4903 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
4904 if (!tm_print_insn
) /* Someone may have already set it */
4905 tm_print_insn
= gdb_print_insn_mips
;
4907 /* Add root prefix command for all "set mips"/"show mips" commands */
4908 add_prefix_cmd ("mips", no_class
, set_mips_command
,
4909 "Various MIPS specific commands.",
4910 &setmipscmdlist
, "set mips ", 0, &setlist
);
4912 add_prefix_cmd ("mips", no_class
, show_mips_command
,
4913 "Various MIPS specific commands.",
4914 &showmipscmdlist
, "show mips ", 0, &showlist
);
4916 /* Allow the user to override the saved register size. */
4917 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
4920 &mips_saved_regsize_string
, "\
4921 Set size of general purpose registers saved on the stack.\n\
4922 This option can be set to one of:\n\
4923 32 - Force GDB to treat saved GP registers as 32-bit\n\
4924 64 - Force GDB to treat saved GP registers as 64-bit\n\
4925 auto - Allow GDB to use the target's default setting or autodetect the\n\
4926 saved GP register size from information contained in the executable.\n\
4931 /* Allow the user to override the argument stack size. */
4932 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
4935 &mips_stack_argsize_string
, "\
4936 Set the amount of stack space reserved for each argument.\n\
4937 This option can be set to one of:\n\
4938 32 - Force GDB to allocate 32-bit chunks per argument\n\
4939 64 - Force GDB to allocate 64-bit chunks per argument\n\
4940 auto - Allow GDB to determine the correct setting from the current\n\
4941 target and executable (default)",
4945 /* Let the user turn off floating point and set the fence post for
4946 heuristic_proc_start. */
4948 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
4949 "Set use of MIPS floating-point coprocessor.",
4950 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
4951 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
4952 "Select single-precision MIPS floating-point coprocessor.",
4954 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
4955 "Select double-precision MIPS floating-point coprocessor.",
4957 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
4958 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
4959 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
4960 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
4961 "Select no MIPS floating-point coprocessor.",
4963 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
4964 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
4965 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
4966 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
4967 "Select MIPS floating-point coprocessor automatically.",
4969 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
4970 "Show current use of MIPS floating-point coprocessor target.",
4974 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
4975 (char *) &tmp_mips_processor_type
,
4976 "Set the type of MIPS processor in use.\n\
4977 Set this to be able to access processor-type-specific registers.\n\
4980 set_cmd_cfunc (c
, mips_set_processor_type_command
);
4981 c
= add_show_from_set (c
, &showlist
);
4982 set_cmd_cfunc (c
, mips_show_processor_type_command
);
4984 tmp_mips_processor_type
= xstrdup (DEFAULT_MIPS_TYPE
);
4985 mips_set_processor_type_command (xstrdup (DEFAULT_MIPS_TYPE
), 0);
4988 /* We really would like to have both "0" and "unlimited" work, but
4989 command.c doesn't deal with that. So make it a var_zinteger
4990 because the user can always use "999999" or some such for unlimited. */
4991 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
4992 (char *) &heuristic_fence_post
,
4994 Set the distance searched for the start of a function.\n\
4995 If you are debugging a stripped executable, GDB needs to search through the\n\
4996 program for the start of a function. This command sets the distance of the\n\
4997 search. The only need to set it is when debugging a stripped executable.",
4999 /* We need to throw away the frame cache when we set this, since it
5000 might change our ability to get backtraces. */
5001 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
5002 add_show_from_set (c
, &showlist
);
5004 /* Allow the user to control whether the upper bits of 64-bit
5005 addresses should be zeroed. */
5006 c
= add_set_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
,
5007 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
5008 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\
5009 the correct value.\n",
5011 add_cmd ("mask-address", no_class
, show_mask_address
,
5012 "Show current mask-address value", &showmipscmdlist
);
5014 /* Allow the user to control the size of 32 bit registers within the
5015 raw remote packet. */
5016 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
5019 (char *)&mips64_transfers_32bit_regs_p
, "\
5020 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
5021 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5022 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5023 64 bits for others. Use \"off\" to disable compatibility mode",
5027 /* Debug this files internals. */
5028 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
5029 &mips_debug
, "Set mips debugging.\n\
5030 When non-zero, mips specific debugging is enabled.", &setdebuglist
),