1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
47 #include "frame-unwind.h"
48 #include "frame-base.h"
49 #include "trad-frame.h"
51 #include "floatformat.h"
53 #include "target-descriptions.h"
54 #include "dwarf2-frame.h"
55 #include "user-regs.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
65 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
66 static int mips16_instruction_has_delay_slot (unsigned short inst
,
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 CORE_ADDR addr
, int mustbe32
);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
76 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
77 struct frame_info
*, const char *);
79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
81 #define ST0_FR (1 << 26)
83 /* The sizes of floating point registers. */
87 MIPS_FPU_SINGLE_REGSIZE
= 4,
88 MIPS_FPU_DOUBLE_REGSIZE
= 8
97 static const char *mips_abi_string
;
99 static const char *const mips_abi_strings
[] = {
110 /* For backwards compatibility we default to MIPS16. This flag is
111 overridden as soon as unambiguous ELF file flags tell us the
112 compressed ISA encoding used. */
113 static const char mips_compression_mips16
[] = "mips16";
114 static const char mips_compression_micromips
[] = "micromips";
115 static const char *const mips_compression_strings
[] =
117 mips_compression_mips16
,
118 mips_compression_micromips
,
122 static const char *mips_compression_string
= mips_compression_mips16
;
124 /* The standard register names, and all the valid aliases for them. */
125 struct register_alias
131 /* Aliases for o32 and most other ABIs. */
132 const struct register_alias mips_o32_aliases
[] = {
139 /* Aliases for n32 and n64. */
140 const struct register_alias mips_n32_n64_aliases
[] = {
147 /* Aliases for ABI-independent registers. */
148 const struct register_alias mips_register_aliases
[] = {
149 /* The architecture manuals specify these ABI-independent names for
151 #define R(n) { "r" #n, n }
152 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
153 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
154 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
155 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
158 /* k0 and k1 are sometimes called these instead (for "kernel
163 /* This is the traditional GDB name for the CP0 status register. */
164 { "sr", MIPS_PS_REGNUM
},
166 /* This is the traditional GDB name for the CP0 BadVAddr register. */
167 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
169 /* This is the traditional GDB name for the FCSR. */
170 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
173 const struct register_alias mips_numeric_register_aliases
[] = {
174 #define R(n) { #n, n }
175 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
176 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
177 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
178 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
182 #ifndef MIPS_DEFAULT_FPU_TYPE
183 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
185 static int mips_fpu_type_auto
= 1;
186 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
188 static unsigned int mips_debug
= 0;
190 /* Properties (for struct target_desc) describing the g/G packet
192 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
193 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
195 struct target_desc
*mips_tdesc_gp32
;
196 struct target_desc
*mips_tdesc_gp64
;
198 const struct mips_regnum
*
199 mips_regnum (struct gdbarch
*gdbarch
)
201 return gdbarch_tdep (gdbarch
)->regnum
;
205 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
207 return mips_regnum (gdbarch
)->fp0
+ 12;
210 /* Return 1 if REGNUM refers to a floating-point general register, raw
211 or cooked. Otherwise return 0. */
214 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
216 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
218 return (rawnum
>= mips_regnum (gdbarch
)->fp0
219 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
222 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
224 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
226 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
227 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
229 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
230 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
232 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
234 /* Return the MIPS ABI associated with GDBARCH. */
236 mips_abi (struct gdbarch
*gdbarch
)
238 return gdbarch_tdep (gdbarch
)->mips_abi
;
242 mips_isa_regsize (struct gdbarch
*gdbarch
)
244 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
246 /* If we know how big the registers are, use that size. */
247 if (tdep
->register_size_valid_p
)
248 return tdep
->register_size
;
250 /* Fall back to the previous behavior. */
251 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
252 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
255 /* Return the currently configured (or set) saved register size. */
258 mips_abi_regsize (struct gdbarch
*gdbarch
)
260 switch (mips_abi (gdbarch
))
262 case MIPS_ABI_EABI32
:
268 case MIPS_ABI_EABI64
:
270 case MIPS_ABI_UNKNOWN
:
273 internal_error (__FILE__
, __LINE__
, _("bad switch"));
277 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
278 are some functions to handle addresses associated with compressed
279 code including but not limited to testing, setting, or clearing
280 bit 0 of such addresses. */
282 /* Return one iff compressed code is the MIPS16 instruction set. */
285 is_mips16_isa (struct gdbarch
*gdbarch
)
287 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
290 /* Return one iff compressed code is the microMIPS instruction set. */
293 is_micromips_isa (struct gdbarch
*gdbarch
)
295 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
298 /* Return one iff ADDR denotes compressed code. */
301 is_compact_addr (CORE_ADDR addr
)
306 /* Return one iff ADDR denotes standard ISA code. */
309 is_mips_addr (CORE_ADDR addr
)
311 return !is_compact_addr (addr
);
314 /* Return one iff ADDR denotes MIPS16 code. */
317 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
319 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
322 /* Return one iff ADDR denotes microMIPS code. */
325 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
327 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
330 /* Strip the ISA (compression) bit off from ADDR. */
333 unmake_compact_addr (CORE_ADDR addr
)
335 return ((addr
) & ~(CORE_ADDR
) 1);
338 /* Add the ISA (compression) bit to ADDR. */
341 make_compact_addr (CORE_ADDR addr
)
343 return ((addr
) | (CORE_ADDR
) 1);
346 /* Extern version of unmake_compact_addr; we use a separate function
347 so that unmake_compact_addr can be inlined throughout this file. */
350 mips_unmake_compact_addr (CORE_ADDR addr
)
352 return unmake_compact_addr (addr
);
355 /* Functions for setting and testing a bit in a minimal symbol that
356 marks it as MIPS16 or microMIPS function. The MSB of the minimal
357 symbol's "info" field is used for this purpose.
359 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
360 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
361 one of the "special" bits in a minimal symbol to mark it accordingly.
362 The test checks an ELF-private flag that is valid for true function
363 symbols only; for synthetic symbols such as for PLT stubs that have
364 no ELF-private part at all the MIPS BFD backend arranges for this
365 information to be carried in the asymbol's udata field instead.
367 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
368 in a minimal symbol. */
371 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
373 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
374 unsigned char st_other
;
376 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
377 st_other
= elfsym
->internal_elf_sym
.st_other
;
378 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
379 st_other
= sym
->udata
.i
;
383 if (ELF_ST_IS_MICROMIPS (st_other
))
385 MSYMBOL_TARGET_FLAG_MICROMIPS (msym
) = 1;
386 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
388 else if (ELF_ST_IS_MIPS16 (st_other
))
390 MSYMBOL_TARGET_FLAG_MIPS16 (msym
) = 1;
391 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
395 /* Return one iff MSYM refers to standard ISA code. */
398 msymbol_is_mips (struct minimal_symbol
*msym
)
400 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
401 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
404 /* Return one iff MSYM refers to MIPS16 code. */
407 msymbol_is_mips16 (struct minimal_symbol
*msym
)
409 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
412 /* Return one iff MSYM refers to microMIPS code. */
415 msymbol_is_micromips (struct minimal_symbol
*msym
)
417 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
420 /* Set the ISA bit in the main symbol too, complementing the corresponding
421 minimal symbol setting and reflecting the run-time value of the symbol.
422 The need for comes from the ISA bit having been cleared as code in
423 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
424 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
425 of symbols referring to compressed code different in GDB to the values
426 used by actual code. That in turn makes them evaluate incorrectly in
427 expressions, producing results different to what the same expressions
428 yield when compiled into the program being debugged. */
431 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
433 if (SYMBOL_CLASS (sym
) == LOC_BLOCK
)
435 /* We are in symbol reading so it is OK to cast away constness. */
436 struct block
*block
= (struct block
*) SYMBOL_BLOCK_VALUE (sym
);
437 CORE_ADDR compact_block_start
;
438 struct bound_minimal_symbol msym
;
440 compact_block_start
= BLOCK_START (block
) | 1;
441 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
442 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
444 BLOCK_START (block
) = compact_block_start
;
449 /* XFER a value from the big/little/left end of the register.
450 Depending on the size of the value it might occupy the entire
451 register or just part of it. Make an allowance for this, aligning
452 things accordingly. */
455 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
456 int reg_num
, int length
,
457 enum bfd_endian endian
, gdb_byte
*in
,
458 const gdb_byte
*out
, int buf_offset
)
462 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
463 /* Need to transfer the left or right part of the register, based on
464 the targets byte order. */
468 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
470 case BFD_ENDIAN_LITTLE
:
473 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
477 internal_error (__FILE__
, __LINE__
, _("bad switch"));
480 fprintf_unfiltered (gdb_stderr
,
481 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
482 reg_num
, reg_offset
, buf_offset
, length
);
483 if (mips_debug
&& out
!= NULL
)
486 fprintf_unfiltered (gdb_stdlog
, "out ");
487 for (i
= 0; i
< length
; i
++)
488 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
491 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
494 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
496 if (mips_debug
&& in
!= NULL
)
499 fprintf_unfiltered (gdb_stdlog
, "in ");
500 for (i
= 0; i
< length
; i
++)
501 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
504 fprintf_unfiltered (gdb_stdlog
, "\n");
507 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
508 compatiblity mode. A return value of 1 means that we have
509 physical 64-bit registers, but should treat them as 32-bit registers. */
512 mips2_fp_compat (struct frame_info
*frame
)
514 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
515 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
517 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
521 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
522 in all the places we deal with FP registers. PR gdb/413. */
523 /* Otherwise check the FR bit in the status register - it controls
524 the FP compatiblity mode. If it is clear we are in compatibility
526 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
533 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
535 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
537 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
539 /* The list of available "set mips " and "show mips " commands. */
541 static struct cmd_list_element
*setmipscmdlist
= NULL
;
542 static struct cmd_list_element
*showmipscmdlist
= NULL
;
544 /* Integer registers 0 thru 31 are handled explicitly by
545 mips_register_name(). Processor specific registers 32 and above
546 are listed in the following tables. */
549 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
553 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
554 "sr", "lo", "hi", "bad", "cause", "pc",
555 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
556 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
557 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
558 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
562 /* Names of IDT R3041 registers. */
564 static const char *mips_r3041_reg_names
[] = {
565 "sr", "lo", "hi", "bad", "cause", "pc",
566 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
567 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
568 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
569 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
570 "fsr", "fir", "", /*"fp" */ "",
571 "", "", "bus", "ccfg", "", "", "", "",
572 "", "", "port", "cmp", "", "", "epc", "prid",
575 /* Names of tx39 registers. */
577 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
578 "sr", "lo", "hi", "bad", "cause", "pc",
579 "", "", "", "", "", "", "", "",
580 "", "", "", "", "", "", "", "",
581 "", "", "", "", "", "", "", "",
582 "", "", "", "", "", "", "", "",
584 "", "", "", "", "", "", "", "",
585 "", "", "config", "cache", "debug", "depc", "epc",
588 /* Names of IRIX registers. */
589 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
590 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
591 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
592 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
593 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
594 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
597 /* Names of registers with Linux kernels. */
598 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
599 "sr", "lo", "hi", "bad", "cause", "pc",
600 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
601 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
602 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
603 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
608 /* Return the name of the register corresponding to REGNO. */
610 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
612 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
613 /* GPR names for all ABIs other than n32/n64. */
614 static char *mips_gpr_names
[] = {
615 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
616 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
617 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
618 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
621 /* GPR names for n32 and n64 ABIs. */
622 static char *mips_n32_n64_gpr_names
[] = {
623 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
624 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
625 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
626 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
629 enum mips_abi abi
= mips_abi (gdbarch
);
631 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
632 but then don't make the raw register names visible. This (upper)
633 range of user visible register numbers are the pseudo-registers.
635 This approach was adopted accommodate the following scenario:
636 It is possible to debug a 64-bit device using a 32-bit
637 programming model. In such instances, the raw registers are
638 configured to be 64-bits wide, while the pseudo registers are
639 configured to be 32-bits wide. The registers that the user
640 sees - the pseudo registers - match the users expectations
641 given the programming model being used. */
642 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
643 if (regno
< gdbarch_num_regs (gdbarch
))
646 /* The MIPS integer registers are always mapped from 0 to 31. The
647 names of the registers (which reflects the conventions regarding
648 register use) vary depending on the ABI. */
649 if (0 <= rawnum
&& rawnum
< 32)
651 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
652 return mips_n32_n64_gpr_names
[rawnum
];
654 return mips_gpr_names
[rawnum
];
656 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
657 return tdesc_register_name (gdbarch
, rawnum
);
658 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
660 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
661 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
662 return tdep
->mips_processor_reg_names
[rawnum
- 32];
666 internal_error (__FILE__
, __LINE__
,
667 _("mips_register_name: bad register number %d"), rawnum
);
670 /* Return the groups that a MIPS register can be categorised into. */
673 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
674 struct reggroup
*reggroup
)
679 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
680 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
681 if (reggroup
== all_reggroup
)
683 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
684 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
685 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
686 (gdbarch), as not all architectures are multi-arch. */
687 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
688 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
689 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
691 if (reggroup
== float_reggroup
)
692 return float_p
&& pseudo
;
693 if (reggroup
== vector_reggroup
)
694 return vector_p
&& pseudo
;
695 if (reggroup
== general_reggroup
)
696 return (!vector_p
&& !float_p
) && pseudo
;
697 /* Save the pseudo registers. Need to make certain that any code
698 extracting register values from a saved register cache also uses
700 if (reggroup
== save_reggroup
)
701 return raw_p
&& pseudo
;
702 /* Restore the same pseudo register. */
703 if (reggroup
== restore_reggroup
)
704 return raw_p
&& pseudo
;
708 /* Return the groups that a MIPS register can be categorised into.
709 This version is only used if we have a target description which
710 describes real registers (and their groups). */
713 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
714 struct reggroup
*reggroup
)
716 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
717 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
720 /* Only save, restore, and display the pseudo registers. Need to
721 make certain that any code extracting register values from a
722 saved register cache also uses pseudo registers.
724 Note: saving and restoring the pseudo registers is slightly
725 strange; if we have 64 bits, we should save and restore all
726 64 bits. But this is hard and has little benefit. */
730 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
734 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
737 /* Map the symbol table registers which live in the range [1 *
738 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
739 registers. Take care of alignment and size problems. */
741 static enum register_status
742 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
743 int cookednum
, gdb_byte
*buf
)
745 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
746 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
747 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
748 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
749 return regcache_raw_read (regcache
, rawnum
, buf
);
750 else if (register_size (gdbarch
, rawnum
) >
751 register_size (gdbarch
, cookednum
))
753 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
754 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
757 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
759 enum register_status status
;
761 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
762 if (status
== REG_VALID
)
763 store_signed_integer (buf
, 4, byte_order
, regval
);
768 internal_error (__FILE__
, __LINE__
, _("bad register size"));
772 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
773 struct regcache
*regcache
, int cookednum
,
776 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
777 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
778 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
779 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
780 regcache_raw_write (regcache
, rawnum
, buf
);
781 else if (register_size (gdbarch
, rawnum
) >
782 register_size (gdbarch
, cookednum
))
784 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
785 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
788 /* Sign extend the shortened version of the register prior
789 to placing it in the raw register. This is required for
790 some mips64 parts in order to avoid unpredictable behavior. */
791 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
792 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
793 regcache_raw_write_signed (regcache
, rawnum
, regval
);
797 internal_error (__FILE__
, __LINE__
, _("bad register size"));
801 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
802 struct agent_expr
*ax
, int reg
)
804 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
805 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
806 && reg
< 2 * gdbarch_num_regs (gdbarch
));
808 ax_reg_mask (ax
, rawnum
);
814 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
815 struct agent_expr
*ax
, int reg
)
817 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
818 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
819 && reg
< 2 * gdbarch_num_regs (gdbarch
));
820 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
824 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
826 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
827 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
830 ax_simple (ax
, aop_lsh
);
833 ax_simple (ax
, aop_rsh_signed
);
837 internal_error (__FILE__
, __LINE__
, _("bad register size"));
842 /* Table to translate 3-bit register field to actual register number. */
843 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
845 /* Heuristic_proc_start may hunt through the text section for a long
846 time across a 2400 baud serial line. Allows the user to limit this
849 static int heuristic_fence_post
= 0;
851 /* Number of bytes of storage in the actual machine representation for
852 register N. NOTE: This defines the pseudo register type so need to
853 rebuild the architecture vector. */
855 static int mips64_transfers_32bit_regs_p
= 0;
858 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
859 struct cmd_list_element
*c
)
861 struct gdbarch_info info
;
862 gdbarch_info_init (&info
);
863 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
864 instead of relying on globals. Doing that would let generic code
865 handle the search for this specific architecture. */
866 if (!gdbarch_update_p (info
))
868 mips64_transfers_32bit_regs_p
= 0;
869 error (_("32-bit compatibility mode not supported"));
873 /* Convert to/from a register and the corresponding memory value. */
875 /* This predicate tests for the case of an 8 byte floating point
876 value that is being transferred to or from a pair of floating point
877 registers each of which are (or are considered to be) only 4 bytes
880 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
883 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
884 && register_size (gdbarch
, regnum
) == 4
885 && mips_float_register_p (gdbarch
, regnum
)
886 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
889 /* This predicate tests for the case of a value of less than 8
890 bytes in width that is being transfered to or from an 8 byte
891 general purpose register. */
893 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
896 int num_regs
= gdbarch_num_regs (gdbarch
);
898 return (register_size (gdbarch
, regnum
) == 8
899 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
900 && TYPE_LENGTH (type
) < 8);
904 mips_convert_register_p (struct gdbarch
*gdbarch
,
905 int regnum
, struct type
*type
)
907 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
908 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
912 mips_register_to_value (struct frame_info
*frame
, int regnum
,
913 struct type
*type
, gdb_byte
*to
,
914 int *optimizedp
, int *unavailablep
)
916 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
918 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
920 get_frame_register (frame
, regnum
+ 0, to
+ 4);
921 get_frame_register (frame
, regnum
+ 1, to
+ 0);
923 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
924 optimizedp
, unavailablep
))
927 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
928 optimizedp
, unavailablep
))
930 *optimizedp
= *unavailablep
= 0;
933 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
935 int len
= TYPE_LENGTH (type
);
938 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
939 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
940 optimizedp
, unavailablep
))
943 *optimizedp
= *unavailablep
= 0;
948 internal_error (__FILE__
, __LINE__
,
949 _("mips_register_to_value: unrecognized case"));
954 mips_value_to_register (struct frame_info
*frame
, int regnum
,
955 struct type
*type
, const gdb_byte
*from
)
957 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
959 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
961 put_frame_register (frame
, regnum
+ 0, from
+ 4);
962 put_frame_register (frame
, regnum
+ 1, from
+ 0);
964 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
967 int len
= TYPE_LENGTH (type
);
969 /* Sign extend values, irrespective of type, that are stored to
970 a 64-bit general purpose register. (32-bit unsigned values
971 are stored as signed quantities within a 64-bit register.
972 When performing an operation, in compiled code, that combines
973 a 32-bit unsigned value with a signed 64-bit value, a type
974 conversion is first performed that zeroes out the high 32 bits.) */
975 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
978 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
980 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
981 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
982 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
986 if (from
[len
-1] & 0x80)
987 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
989 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
990 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
991 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
996 internal_error (__FILE__
, __LINE__
,
997 _("mips_value_to_register: unrecognized case"));
1001 /* Return the GDB type object for the "standard" data type of data in
1004 static struct type
*
1005 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1007 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1008 if (mips_float_register_p (gdbarch
, regnum
))
1010 /* The floating-point registers raw, or cooked, always match
1011 mips_isa_regsize(), and also map 1:1, byte for byte. */
1012 if (mips_isa_regsize (gdbarch
) == 4)
1013 return builtin_type (gdbarch
)->builtin_float
;
1015 return builtin_type (gdbarch
)->builtin_double
;
1017 else if (regnum
< gdbarch_num_regs (gdbarch
))
1019 /* The raw or ISA registers. These are all sized according to
1021 if (mips_isa_regsize (gdbarch
) == 4)
1022 return builtin_type (gdbarch
)->builtin_int32
;
1024 return builtin_type (gdbarch
)->builtin_int64
;
1028 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1030 /* The cooked or ABI registers. These are sized according to
1031 the ABI (with a few complications). */
1032 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1033 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1034 return builtin_type (gdbarch
)->builtin_int32
;
1035 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
1036 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1037 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1038 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1039 /* The pseudo/cooked view of the embedded registers is always
1040 32-bit. The raw view is handled below. */
1041 return builtin_type (gdbarch
)->builtin_int32
;
1042 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
1043 /* The target, while possibly using a 64-bit register buffer,
1044 is only transfering 32-bits of each integer register.
1045 Reflect this in the cooked/pseudo (ABI) register value. */
1046 return builtin_type (gdbarch
)->builtin_int32
;
1047 else if (mips_abi_regsize (gdbarch
) == 4)
1048 /* The ABI is restricted to 32-bit registers (the ISA could be
1050 return builtin_type (gdbarch
)->builtin_int32
;
1053 return builtin_type (gdbarch
)->builtin_int64
;
1057 /* Return the GDB type for the pseudo register REGNUM, which is the
1058 ABI-level view. This function is only called if there is a target
1059 description which includes registers, so we know precisely the
1060 types of hardware registers. */
1062 static struct type
*
1063 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1065 const int num_regs
= gdbarch_num_regs (gdbarch
);
1066 int rawnum
= regnum
% num_regs
;
1067 struct type
*rawtype
;
1069 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1071 /* Absent registers are still absent. */
1072 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1073 if (TYPE_LENGTH (rawtype
) == 0)
1076 if (mips_float_register_p (gdbarch
, rawnum
))
1077 /* Present the floating point registers however the hardware did;
1078 do not try to convert between FPU layouts. */
1081 /* Use pointer types for registers if we can. For n32 we can not,
1082 since we do not have a 64-bit pointer type. */
1083 if (mips_abi_regsize (gdbarch
)
1084 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1086 if (rawnum
== MIPS_SP_REGNUM
1087 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1088 return builtin_type (gdbarch
)->builtin_data_ptr
;
1089 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1090 return builtin_type (gdbarch
)->builtin_func_ptr
;
1093 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1094 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1095 || rawnum
== mips_regnum (gdbarch
)->lo
1096 || rawnum
== mips_regnum (gdbarch
)->hi
1097 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1098 || rawnum
== mips_regnum (gdbarch
)->cause
1099 || rawnum
== mips_regnum (gdbarch
)->pc
1100 || (mips_regnum (gdbarch
)->dspacc
!= -1
1101 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1102 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1103 return builtin_type (gdbarch
)->builtin_int32
;
1105 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
1106 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1107 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
1108 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1110 /* The pseudo/cooked view of embedded registers is always
1111 32-bit, even if the target transfers 64-bit values for them.
1112 New targets relying on XML descriptions should only transfer
1113 the necessary 32 bits, but older versions of GDB expected 64,
1114 so allow the target to provide 64 bits without interfering
1115 with the displayed type. */
1116 return builtin_type (gdbarch
)->builtin_int32
;
1119 /* For all other registers, pass through the hardware type. */
1123 /* Should the upper word of 64-bit addresses be zeroed? */
1124 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1127 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1129 switch (mask_address_var
)
1131 case AUTO_BOOLEAN_TRUE
:
1133 case AUTO_BOOLEAN_FALSE
:
1136 case AUTO_BOOLEAN_AUTO
:
1137 return tdep
->default_mask_address_p
;
1139 internal_error (__FILE__
, __LINE__
,
1140 _("mips_mask_address_p: bad switch"));
1146 show_mask_address (struct ui_file
*file
, int from_tty
,
1147 struct cmd_list_element
*c
, const char *value
)
1149 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1151 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1152 switch (mask_address_var
)
1154 case AUTO_BOOLEAN_TRUE
:
1155 printf_filtered ("The 32 bit mips address mask is enabled\n");
1157 case AUTO_BOOLEAN_FALSE
:
1158 printf_filtered ("The 32 bit mips address mask is disabled\n");
1160 case AUTO_BOOLEAN_AUTO
:
1162 ("The 32 bit address mask is set automatically. Currently %s\n",
1163 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1166 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1171 /* Tell if the program counter value in MEMADDR is in a standard ISA
1175 mips_pc_is_mips (CORE_ADDR memaddr
)
1177 struct bound_minimal_symbol sym
;
1179 /* Flags indicating that this is a MIPS16 or microMIPS function is
1180 stored by elfread.c in the high bit of the info field. Use this
1181 to decide if the function is standard MIPS. Otherwise if bit 0
1182 of the address is clear, then this is a standard MIPS function. */
1183 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1185 return msymbol_is_mips (sym
.minsym
);
1187 return is_mips_addr (memaddr
);
1190 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1193 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1195 struct bound_minimal_symbol sym
;
1197 /* A flag indicating that this is a MIPS16 function is stored by
1198 elfread.c in the high bit of the info field. Use this to decide
1199 if the function is MIPS16. Otherwise if bit 0 of the address is
1200 set, then ELF file flags will tell if this is a MIPS16 function. */
1201 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1203 return msymbol_is_mips16 (sym
.minsym
);
1205 return is_mips16_addr (gdbarch
, memaddr
);
1208 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1211 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1213 struct bound_minimal_symbol sym
;
1215 /* A flag indicating that this is a microMIPS function is stored by
1216 elfread.c in the high bit of the info field. Use this to decide
1217 if the function is microMIPS. Otherwise if bit 0 of the address
1218 is set, then ELF file flags will tell if this is a microMIPS
1220 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1222 return msymbol_is_micromips (sym
.minsym
);
1224 return is_micromips_addr (gdbarch
, memaddr
);
1227 /* Tell the ISA type of the function the program counter value in MEMADDR
1230 static enum mips_isa
1231 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1233 struct bound_minimal_symbol sym
;
1235 /* A flag indicating that this is a MIPS16 or a microMIPS function
1236 is stored by elfread.c in the high bit of the info field. Use
1237 this to decide if the function is MIPS16 or microMIPS or normal
1238 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1239 flags will tell if this is a MIPS16 or a microMIPS function. */
1240 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1243 if (msymbol_is_micromips (sym
.minsym
))
1244 return ISA_MICROMIPS
;
1245 else if (msymbol_is_mips16 (sym
.minsym
))
1252 if (is_mips_addr (memaddr
))
1254 else if (is_micromips_addr (gdbarch
, memaddr
))
1255 return ISA_MICROMIPS
;
1261 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1262 The need for comes from the ISA bit having been cleared, making
1263 addresses in FDE, range records, etc. referring to compressed code
1264 different to those in line information, the symbol table and finally
1265 the PC register. That in turn confuses many operations. */
1268 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1270 pc
= unmake_compact_addr (pc
);
1271 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1274 /* Recalculate the line record requested so that the resulting PC has
1275 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1276 this adjustment comes from some records associated with compressed
1277 code having the ISA bit cleared, most notably at function prologue
1278 ends. The ISA bit is in this context retrieved from the minimal
1279 symbol covering the address requested, which in turn has been
1280 constructed from the binary's symbol table rather than DWARF-2
1281 information. The correct setting of the ISA bit is required for
1282 breakpoint addresses to correctly match against the stop PC.
1284 As line entries can specify relative address adjustments we need to
1285 keep track of the absolute value of the last line address recorded
1286 in line information, so that we can calculate the actual address to
1287 apply the ISA bit adjustment to. We use PC for this tracking and
1288 keep the original address there.
1290 As such relative address adjustments can be odd within compressed
1291 code we need to keep track of the last line address with the ISA
1292 bit adjustment applied too, as the original address may or may not
1293 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1294 the adjusted address there.
1296 For relative address adjustments we then use these variables to
1297 calculate the address intended by line information, which will be
1298 PC-relative, and return an updated adjustment carrying ISA bit
1299 information, which will be ADJ_PC-relative. For absolute address
1300 adjustments we just return the same address that we store in ADJ_PC
1303 As the first line entry can be relative to an implied address value
1304 of 0 we need to have the initial address set up that we store in PC
1305 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1306 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1309 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1311 static CORE_ADDR adj_pc
;
1312 static CORE_ADDR pc
;
1315 pc
= rel
? pc
+ addr
: addr
;
1316 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1317 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1322 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1324 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1325 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1326 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1327 static const char mips_str_call_stub
[] = "__call_stub_";
1328 static const char mips_str_fn_stub
[] = "__fn_stub_";
1330 /* This is used as a PIC thunk prefix. */
1332 static const char mips_str_pic
[] = ".pic.";
1334 /* Return non-zero if the PC is inside a call thunk (aka stub or
1335 trampoline) that should be treated as a temporary frame. */
1338 mips_in_frame_stub (CORE_ADDR pc
)
1340 CORE_ADDR start_addr
;
1343 /* Find the starting address of the function containing the PC. */
1344 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1347 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1348 if (startswith (name
, mips_str_mips16_call_stub
))
1350 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1351 if (startswith (name
, mips_str_call_stub
))
1353 /* If the PC is in __fn_stub_*, this is a call stub. */
1354 if (startswith (name
, mips_str_fn_stub
))
1357 return 0; /* Not a stub. */
1360 /* MIPS believes that the PC has a sign extended value. Perhaps the
1361 all registers should be sign extended for simplicity? */
1364 mips_read_pc (struct regcache
*regcache
)
1366 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1369 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1374 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1378 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1379 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1380 intermediate frames. In this case we can get the caller's address
1381 from $ra, or if $ra contains an address within a thunk as well, then
1382 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1383 and thus the caller's address is in $s2. */
1384 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1386 pc
= frame_unwind_register_signed
1387 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1388 if (mips_in_frame_stub (pc
))
1389 pc
= frame_unwind_register_signed
1390 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1396 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1398 return frame_unwind_register_signed
1399 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1402 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1403 dummy frame. The frame ID's base needs to match the TOS value
1404 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1407 static struct frame_id
1408 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1410 return frame_id_build
1411 (get_frame_register_signed (this_frame
,
1412 gdbarch_num_regs (gdbarch
)
1414 get_frame_pc (this_frame
));
1417 /* Implement the "write_pc" gdbarch method. */
1420 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1422 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1424 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1427 /* Fetch and return instruction from the specified location. Handle
1428 MIPS16/microMIPS as appropriate. */
1431 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1432 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1434 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1435 gdb_byte buf
[MIPS_INSN32_SIZE
];
1443 instlen
= MIPS_INSN16_SIZE
;
1444 addr
= unmake_compact_addr (addr
);
1447 instlen
= MIPS_INSN32_SIZE
;
1450 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1453 err
= target_read_memory (addr
, buf
, instlen
);
1459 memory_error (TARGET_XFER_E_IO
, addr
);
1462 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1465 /* These are the fields of 32 bit mips instructions. */
1466 #define mips32_op(x) (x >> 26)
1467 #define itype_op(x) (x >> 26)
1468 #define itype_rs(x) ((x >> 21) & 0x1f)
1469 #define itype_rt(x) ((x >> 16) & 0x1f)
1470 #define itype_immediate(x) (x & 0xffff)
1472 #define jtype_op(x) (x >> 26)
1473 #define jtype_target(x) (x & 0x03ffffff)
1475 #define rtype_op(x) (x >> 26)
1476 #define rtype_rs(x) ((x >> 21) & 0x1f)
1477 #define rtype_rt(x) ((x >> 16) & 0x1f)
1478 #define rtype_rd(x) ((x >> 11) & 0x1f)
1479 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1480 #define rtype_funct(x) (x & 0x3f)
1482 /* MicroMIPS instruction fields. */
1483 #define micromips_op(x) ((x) >> 10)
1485 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1486 bit and the size respectively of the field extracted. */
1487 #define b0s4_imm(x) ((x) & 0xf)
1488 #define b0s5_imm(x) ((x) & 0x1f)
1489 #define b0s5_reg(x) ((x) & 0x1f)
1490 #define b0s7_imm(x) ((x) & 0x7f)
1491 #define b0s10_imm(x) ((x) & 0x3ff)
1492 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1493 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1494 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1495 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1496 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1497 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1498 #define b6s4_op(x) (((x) >> 6) & 0xf)
1499 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1501 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1502 respectively of the field extracted. */
1503 #define b0s6_op(x) ((x) & 0x3f)
1504 #define b0s11_op(x) ((x) & 0x7ff)
1505 #define b0s12_imm(x) ((x) & 0xfff)
1506 #define b0s16_imm(x) ((x) & 0xffff)
1507 #define b0s26_imm(x) ((x) & 0x3ffffff)
1508 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1509 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1510 #define b12s4_op(x) (((x) >> 12) & 0xf)
1512 /* Return the size in bytes of the instruction INSN encoded in the ISA
1516 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1521 if (micromips_op (insn
) == 0x1f)
1522 return 3 * MIPS_INSN16_SIZE
;
1523 else if (((micromips_op (insn
) & 0x4) == 0x4)
1524 || ((micromips_op (insn
) & 0x7) == 0x0))
1525 return 2 * MIPS_INSN16_SIZE
;
1527 return MIPS_INSN16_SIZE
;
1529 if ((insn
& 0xf800) == 0xf000)
1530 return 2 * MIPS_INSN16_SIZE
;
1532 return MIPS_INSN16_SIZE
;
1534 return MIPS_INSN32_SIZE
;
1536 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1540 mips32_relative_offset (ULONGEST inst
)
1542 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1545 /* Determine the address of the next instruction executed after the INST
1546 floating condition branch instruction at PC. COUNT specifies the
1547 number of the floating condition bits tested by the branch. */
1550 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1551 ULONGEST inst
, CORE_ADDR pc
, int count
)
1553 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1554 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1555 int tf
= itype_rt (inst
) & 1;
1556 int mask
= (1 << count
) - 1;
1561 /* No way to handle; it'll most likely trap anyway. */
1564 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1565 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1567 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1568 pc
+= mips32_relative_offset (inst
);
1575 /* Return nonzero if the gdbarch is an Octeon series. */
1578 is_octeon (struct gdbarch
*gdbarch
)
1580 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1582 return (info
->mach
== bfd_mach_mips_octeon
1583 || info
->mach
== bfd_mach_mips_octeonp
1584 || info
->mach
== bfd_mach_mips_octeon2
);
1587 /* Return true if the OP represents the Octeon's BBIT instruction. */
1590 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1592 if (!is_octeon (gdbarch
))
1594 /* BBIT0 is encoded as LWC2: 110 010. */
1595 /* BBIT032 is encoded as LDC2: 110 110. */
1596 /* BBIT1 is encoded as SWC2: 111 010. */
1597 /* BBIT132 is encoded as SDC2: 111 110. */
1598 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1604 /* Determine where to set a single step breakpoint while considering
1605 branch prediction. */
1608 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1610 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1613 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1614 op
= itype_op (inst
);
1615 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1619 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1630 goto greater_branch
;
1635 else if (op
== 17 && itype_rs (inst
) == 8)
1636 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1637 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1638 else if (op
== 17 && itype_rs (inst
) == 9
1639 && (itype_rt (inst
) & 2) == 0)
1640 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1641 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1642 else if (op
== 17 && itype_rs (inst
) == 10
1643 && (itype_rt (inst
) & 2) == 0)
1644 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1645 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1648 /* The new PC will be alternate mode. */
1652 reg
= jtype_target (inst
) << 2;
1653 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1654 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1656 else if (is_octeon_bbit_op (op
, gdbarch
))
1660 branch_if
= op
== 58 || op
== 62;
1661 bit
= itype_rt (inst
);
1663 /* Take into account the *32 instructions. */
1664 if (op
== 54 || op
== 62)
1667 if (((get_frame_register_signed (frame
,
1668 itype_rs (inst
)) >> bit
) & 1)
1670 pc
+= mips32_relative_offset (inst
) + 4;
1672 pc
+= 8; /* After the delay slot. */
1676 pc
+= 4; /* Not a branch, next instruction is easy. */
1679 { /* This gets way messy. */
1681 /* Further subdivide into SPECIAL, REGIMM and other. */
1682 switch (op
& 0x07) /* Extract bits 28,27,26. */
1684 case 0: /* SPECIAL */
1685 op
= rtype_funct (inst
);
1690 /* Set PC to that address. */
1691 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1693 case 12: /* SYSCALL */
1695 struct gdbarch_tdep
*tdep
;
1697 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1698 if (tdep
->syscall_next_pc
!= NULL
)
1699 pc
= tdep
->syscall_next_pc (frame
);
1708 break; /* end SPECIAL */
1709 case 1: /* REGIMM */
1711 op
= itype_rt (inst
); /* branch condition */
1716 case 16: /* BLTZAL */
1717 case 18: /* BLTZALL */
1719 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1720 pc
+= mips32_relative_offset (inst
) + 4;
1722 pc
+= 8; /* after the delay slot */
1726 case 17: /* BGEZAL */
1727 case 19: /* BGEZALL */
1728 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1729 pc
+= mips32_relative_offset (inst
) + 4;
1731 pc
+= 8; /* after the delay slot */
1733 case 0x1c: /* BPOSGE32 */
1734 case 0x1e: /* BPOSGE64 */
1736 if (itype_rs (inst
) == 0)
1738 unsigned int pos
= (op
& 2) ? 64 : 32;
1739 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1742 /* No way to handle; it'll most likely trap anyway. */
1745 if ((get_frame_register_unsigned (frame
,
1746 dspctl
) & 0x7f) >= pos
)
1747 pc
+= mips32_relative_offset (inst
);
1752 /* All of the other instructions in the REGIMM category */
1757 break; /* end REGIMM */
1762 reg
= jtype_target (inst
) << 2;
1763 /* Upper four bits get never changed... */
1764 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1767 case 4: /* BEQ, BEQL */
1769 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1770 get_frame_register_signed (frame
, itype_rt (inst
)))
1771 pc
+= mips32_relative_offset (inst
) + 4;
1775 case 5: /* BNE, BNEL */
1777 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1778 get_frame_register_signed (frame
, itype_rt (inst
)))
1779 pc
+= mips32_relative_offset (inst
) + 4;
1783 case 6: /* BLEZ, BLEZL */
1784 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1785 pc
+= mips32_relative_offset (inst
) + 4;
1791 greater_branch
: /* BGTZ, BGTZL */
1792 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1793 pc
+= mips32_relative_offset (inst
) + 4;
1800 } /* mips32_next_pc */
1802 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1806 micromips_relative_offset7 (ULONGEST insn
)
1808 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1811 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1815 micromips_relative_offset10 (ULONGEST insn
)
1817 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1820 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1824 micromips_relative_offset16 (ULONGEST insn
)
1826 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1829 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1832 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1836 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1837 return mips_insn_size (ISA_MICROMIPS
, insn
);
1840 /* Calculate the address of the next microMIPS instruction to execute
1841 after the INSN coprocessor 1 conditional branch instruction at the
1842 address PC. COUNT denotes the number of coprocessor condition bits
1843 examined by the branch. */
1846 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1847 ULONGEST insn
, CORE_ADDR pc
, int count
)
1849 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1850 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1851 int tf
= b5s5_op (insn
>> 16) & 1;
1852 int mask
= (1 << count
) - 1;
1857 /* No way to handle; it'll most likely trap anyway. */
1860 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1861 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1863 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1864 pc
+= micromips_relative_offset16 (insn
);
1866 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1871 /* Calculate the address of the next microMIPS instruction to execute
1872 after the instruction at the address PC. */
1875 micromips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1877 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1880 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1881 pc
+= MIPS_INSN16_SIZE
;
1882 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1884 /* 48-bit instructions. */
1885 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
1886 /* No branch or jump instructions in this category. */
1887 pc
+= 2 * MIPS_INSN16_SIZE
;
1890 /* 32-bit instructions. */
1891 case 2 * MIPS_INSN16_SIZE
:
1893 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1894 pc
+= MIPS_INSN16_SIZE
;
1895 switch (micromips_op (insn
>> 16))
1897 case 0x00: /* POOL32A: bits 000000 */
1898 if (b0s6_op (insn
) == 0x3c
1899 /* POOL32Axf: bits 000000 ... 111100 */
1900 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1901 /* JALR, JALR.HB: 000000 000x111100 111100 */
1902 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1903 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
>> 16));
1906 case 0x10: /* POOL32I: bits 010000 */
1907 switch (b5s5_op (insn
>> 16))
1909 case 0x00: /* BLTZ: bits 010000 00000 */
1910 case 0x01: /* BLTZAL: bits 010000 00001 */
1911 case 0x11: /* BLTZALS: bits 010000 10001 */
1912 if (get_frame_register_signed (frame
,
1913 b0s5_reg (insn
>> 16)) < 0)
1914 pc
+= micromips_relative_offset16 (insn
);
1916 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1919 case 0x02: /* BGEZ: bits 010000 00010 */
1920 case 0x03: /* BGEZAL: bits 010000 00011 */
1921 case 0x13: /* BGEZALS: bits 010000 10011 */
1922 if (get_frame_register_signed (frame
,
1923 b0s5_reg (insn
>> 16)) >= 0)
1924 pc
+= micromips_relative_offset16 (insn
);
1926 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1929 case 0x04: /* BLEZ: bits 010000 00100 */
1930 if (get_frame_register_signed (frame
,
1931 b0s5_reg (insn
>> 16)) <= 0)
1932 pc
+= micromips_relative_offset16 (insn
);
1934 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1937 case 0x05: /* BNEZC: bits 010000 00101 */
1938 if (get_frame_register_signed (frame
,
1939 b0s5_reg (insn
>> 16)) != 0)
1940 pc
+= micromips_relative_offset16 (insn
);
1943 case 0x06: /* BGTZ: bits 010000 00110 */
1944 if (get_frame_register_signed (frame
,
1945 b0s5_reg (insn
>> 16)) > 0)
1946 pc
+= micromips_relative_offset16 (insn
);
1948 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1951 case 0x07: /* BEQZC: bits 010000 00111 */
1952 if (get_frame_register_signed (frame
,
1953 b0s5_reg (insn
>> 16)) == 0)
1954 pc
+= micromips_relative_offset16 (insn
);
1957 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1958 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1959 if (((insn
>> 16) & 0x3) == 0x0)
1960 /* BC2F, BC2T: don't know how to handle these. */
1964 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1965 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1967 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1968 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1971 /* No way to handle; it'll most likely trap anyway. */
1974 if ((get_frame_register_unsigned (frame
,
1975 dspctl
) & 0x7f) >= pos
)
1976 pc
+= micromips_relative_offset16 (insn
);
1978 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1982 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1983 /* BC1ANY2F: bits 010000 11100 xxx01 */
1984 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1985 /* BC1ANY2T: bits 010000 11101 xxx01 */
1986 if (((insn
>> 16) & 0x2) == 0x0)
1987 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
,
1988 ((insn
>> 16) & 0x1) + 1);
1991 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1992 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1993 if (((insn
>> 16) & 0x3) == 0x1)
1994 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
, 4);
1999 case 0x1d: /* JALS: bits 011101 */
2000 case 0x35: /* J: bits 110101 */
2001 case 0x3d: /* JAL: bits 111101 */
2002 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2005 case 0x25: /* BEQ: bits 100101 */
2006 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
2007 == get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
2008 pc
+= micromips_relative_offset16 (insn
);
2010 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2013 case 0x2d: /* BNE: bits 101101 */
2014 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
2015 != get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
2016 pc
+= micromips_relative_offset16 (insn
);
2018 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2021 case 0x3c: /* JALX: bits 111100 */
2022 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2027 /* 16-bit instructions. */
2028 case MIPS_INSN16_SIZE
:
2029 switch (micromips_op (insn
))
2031 case 0x11: /* POOL16C: bits 010001 */
2032 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2033 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2034 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
));
2035 else if (b5s5_op (insn
) == 0x18)
2036 /* JRADDIUSP: bits 010001 11000 */
2037 pc
= get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
2040 case 0x23: /* BEQZ16: bits 100011 */
2042 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2044 if (get_frame_register_signed (frame
, rs
) == 0)
2045 pc
+= micromips_relative_offset7 (insn
);
2047 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2051 case 0x2b: /* BNEZ16: bits 101011 */
2053 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2055 if (get_frame_register_signed (frame
, rs
) != 0)
2056 pc
+= micromips_relative_offset7 (insn
);
2058 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2062 case 0x33: /* B16: bits 110011 */
2063 pc
+= micromips_relative_offset10 (insn
);
2072 /* Decoding the next place to set a breakpoint is irregular for the
2073 mips 16 variant, but fortunately, there fewer instructions. We have
2074 to cope ith extensions for 16 bit instructions and a pair of actual
2075 32 bit instructions. We dont want to set a single step instruction
2076 on the extend instruction either. */
2078 /* Lots of mips16 instruction formats */
2079 /* Predicting jumps requires itype,ritype,i8type
2080 and their extensions extItype,extritype,extI8type. */
2081 enum mips16_inst_fmts
2083 itype
, /* 0 immediate 5,10 */
2084 ritype
, /* 1 5,3,8 */
2085 rrtype
, /* 2 5,3,3,5 */
2086 rritype
, /* 3 5,3,3,5 */
2087 rrrtype
, /* 4 5,3,3,3,2 */
2088 rriatype
, /* 5 5,3,3,1,4 */
2089 shifttype
, /* 6 5,3,3,3,2 */
2090 i8type
, /* 7 5,3,8 */
2091 i8movtype
, /* 8 5,3,3,5 */
2092 i8mov32rtype
, /* 9 5,3,5,3 */
2093 i64type
, /* 10 5,3,8 */
2094 ri64type
, /* 11 5,3,3,5 */
2095 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2096 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2097 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2098 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2099 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2100 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2101 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2102 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2103 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2104 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2106 /* I am heaping all the fields of the formats into one structure and
2107 then, only the fields which are involved in instruction extension. */
2111 unsigned int regx
; /* Function in i8 type. */
2116 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2117 for the bits which make up the immediate extension. */
2120 extended_offset (unsigned int extension
)
2124 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2126 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2128 value
|= extension
& 0x1f; /* Extract 4:0. */
2133 /* Only call this function if you know that this is an extendable
2134 instruction. It won't malfunction, but why make excess remote memory
2135 references? If the immediate operands get sign extended or something,
2136 do it after the extension is performed. */
2137 /* FIXME: Every one of these cases needs to worry about sign extension
2138 when the offset is to be used in relative addressing. */
2141 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2143 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2146 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2147 target_read_memory (pc
, buf
, 2);
2148 return extract_unsigned_integer (buf
, 2, byte_order
);
2152 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2153 unsigned int extension
,
2155 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2160 switch (insn_format
)
2167 value
= extended_offset ((extension
<< 16) | inst
);
2168 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2172 value
= inst
& 0x7ff;
2173 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2182 { /* A register identifier and an offset. */
2183 /* Most of the fields are the same as I type but the
2184 immediate value is of a different length. */
2188 value
= extended_offset ((extension
<< 16) | inst
);
2189 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2193 value
= inst
& 0xff; /* 8 bits */
2194 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2197 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2203 unsigned long value
;
2204 unsigned int nexthalf
;
2205 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2206 value
= value
<< 16;
2207 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2208 /* Low bit still set. */
2216 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2218 upk
->offset
= offset
;
2224 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2225 and having a signed 16-bit OFFSET. */
2228 add_offset_16 (CORE_ADDR pc
, int offset
)
2230 return pc
+ (offset
<< 1) + 2;
2234 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
2235 unsigned int extension
, unsigned int insn
)
2237 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2238 int op
= (insn
>> 11);
2241 case 2: /* Branch */
2243 struct upk_mips16 upk
;
2244 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2245 pc
= add_offset_16 (pc
, upk
.offset
);
2248 case 3: /* JAL , JALX - Watch out, these are 32 bit
2251 struct upk_mips16 upk
;
2252 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2253 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2254 if ((insn
>> 10) & 0x01) /* Exchange mode */
2255 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2262 struct upk_mips16 upk
;
2264 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2265 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2267 pc
= add_offset_16 (pc
, upk
.offset
);
2274 struct upk_mips16 upk
;
2276 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2277 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2279 pc
= add_offset_16 (pc
, upk
.offset
);
2284 case 12: /* I8 Formats btez btnez */
2286 struct upk_mips16 upk
;
2288 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2289 /* upk.regx contains the opcode */
2290 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
2291 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2292 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2293 pc
= add_offset_16 (pc
, upk
.offset
);
2298 case 29: /* RR Formats JR, JALR, JALR-RA */
2300 struct upk_mips16 upk
;
2301 /* upk.fmt = rrtype; */
2306 upk
.regx
= (insn
>> 8) & 0x07;
2307 upk
.regy
= (insn
>> 5) & 0x07;
2308 if ((upk
.regy
& 1) == 0)
2309 reg
= mips_reg3_to_reg
[upk
.regx
];
2311 reg
= 31; /* Function return instruction. */
2312 pc
= get_frame_register_signed (frame
, reg
);
2319 /* This is an instruction extension. Fetch the real instruction
2320 (which follows the extension) and decode things based on
2324 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
2325 fetch_mips_16 (gdbarch
, pc
));
2338 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2340 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2341 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2342 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
2345 /* The mips_next_pc function supports single_step when the remote
2346 target monitor or stub is not developed enough to do a single_step.
2347 It works by decoding the current instruction and predicting where a
2348 branch will go. This isn't hard because all the data is available.
2349 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2351 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2353 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2355 if (mips_pc_is_mips16 (gdbarch
, pc
))
2356 return mips16_next_pc (frame
, pc
);
2357 else if (mips_pc_is_micromips (gdbarch
, pc
))
2358 return micromips_next_pc (frame
, pc
);
2360 return mips32_next_pc (frame
, pc
);
2363 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2367 mips16_instruction_is_compact_branch (unsigned short insn
)
2369 switch (insn
& 0xf800)
2372 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2374 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2375 case 0x2800: /* BNEZ */
2376 case 0x2000: /* BEQZ */
2377 case 0x1000: /* B */
2384 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2388 micromips_instruction_is_compact_branch (unsigned short insn
)
2390 switch (micromips_op (insn
))
2392 case 0x11: /* POOL16C: bits 010001 */
2393 return (b5s5_op (insn
) == 0x18
2394 /* JRADDIUSP: bits 010001 11000 */
2395 || b5s5_op (insn
) == 0xd);
2396 /* JRC: bits 010011 01101 */
2397 case 0x10: /* POOL32I: bits 010000 */
2398 return (b5s5_op (insn
) & 0x1d) == 0x5;
2399 /* BEQZC/BNEZC: bits 010000 001x1 */
2405 struct mips_frame_cache
2408 struct trad_frame_saved_reg
*saved_regs
;
2411 /* Set a register's saved stack address in temp_saved_regs. If an
2412 address has already been set for this register, do nothing; this
2413 way we will only recognize the first save of a given register in a
2416 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2417 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2418 Strictly speaking, only the second range is used as it is only second
2419 range (the ABI instead of ISA registers) that comes into play when finding
2420 saved registers in a frame. */
2423 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2424 int regnum
, CORE_ADDR offset
)
2426 if (this_cache
!= NULL
2427 && this_cache
->saved_regs
[regnum
].addr
== -1)
2429 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2431 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2437 /* Fetch the immediate value from a MIPS16 instruction.
2438 If the previous instruction was an EXTEND, use it to extend
2439 the upper bits of the immediate value. This is a helper function
2440 for mips16_scan_prologue. */
2443 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2444 unsigned short inst
, /* current instruction */
2445 int nbits
, /* number of bits in imm field */
2446 int scale
, /* scale factor to be applied to imm */
2447 int is_signed
) /* is the imm field signed? */
2451 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2453 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2454 if (offset
& 0x8000) /* check for negative extend */
2455 offset
= 0 - (0x10000 - (offset
& 0xffff));
2456 return offset
| (inst
& 0x1f);
2460 int max_imm
= 1 << nbits
;
2461 int mask
= max_imm
- 1;
2462 int sign_bit
= max_imm
>> 1;
2464 offset
= inst
& mask
;
2465 if (is_signed
&& (offset
& sign_bit
))
2466 offset
= 0 - (max_imm
- offset
);
2467 return offset
* scale
;
2472 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2473 the associated FRAME_CACHE if not null.
2474 Return the address of the first instruction past the prologue. */
2477 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2478 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2479 struct frame_info
*this_frame
,
2480 struct mips_frame_cache
*this_cache
)
2482 int prev_non_prologue_insn
= 0;
2483 int this_non_prologue_insn
;
2484 int non_prologue_insns
= 0;
2487 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2489 long frame_offset
= 0; /* Size of stack frame. */
2490 long frame_adjust
= 0; /* Offset of FP from SP. */
2491 int frame_reg
= MIPS_SP_REGNUM
;
2492 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2493 unsigned inst
= 0; /* current instruction */
2494 unsigned entry_inst
= 0; /* the entry instruction */
2495 unsigned save_inst
= 0; /* the save instruction */
2496 int prev_delay_slot
= 0;
2500 int extend_bytes
= 0;
2501 int prev_extend_bytes
= 0;
2502 CORE_ADDR end_prologue_addr
;
2504 /* Can be called when there's no process, and hence when there's no
2506 if (this_frame
!= NULL
)
2507 sp
= get_frame_register_signed (this_frame
,
2508 gdbarch_num_regs (gdbarch
)
2513 if (limit_pc
> start_pc
+ 200)
2514 limit_pc
= start_pc
+ 200;
2517 /* Permit at most one non-prologue non-control-transfer instruction
2518 in the middle which may have been reordered by the compiler for
2520 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2522 this_non_prologue_insn
= 0;
2525 /* Save the previous instruction. If it's an EXTEND, we'll extract
2526 the immediate offset extension from it in mips16_get_imm. */
2529 /* Fetch and decode the instruction. */
2530 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2533 /* Normally we ignore extend instructions. However, if it is
2534 not followed by a valid prologue instruction, then this
2535 instruction is not part of the prologue either. We must
2536 remember in this case to adjust the end_prologue_addr back
2538 if ((inst
& 0xf800) == 0xf000) /* extend */
2540 extend_bytes
= MIPS_INSN16_SIZE
;
2544 prev_extend_bytes
= extend_bytes
;
2547 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2548 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2550 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2551 if (offset
< 0) /* Negative stack adjustment? */
2552 frame_offset
-= offset
;
2554 /* Exit loop if a positive stack adjustment is found, which
2555 usually means that the stack cleanup code in the function
2556 epilogue is reached. */
2559 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2561 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2562 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2563 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2565 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2567 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2568 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2569 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2571 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2573 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2574 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2576 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2578 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2579 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2581 else if (inst
== 0x673d) /* move $s1, $sp */
2586 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2588 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2589 frame_addr
= sp
+ offset
;
2591 frame_adjust
= offset
;
2593 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2595 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2596 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2597 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2599 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2601 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2602 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2603 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2605 else if ((inst
& 0xf81f) == 0xe809
2606 && (inst
& 0x700) != 0x700) /* entry */
2607 entry_inst
= inst
; /* Save for later processing. */
2608 else if ((inst
& 0xff80) == 0x6480) /* save */
2610 save_inst
= inst
; /* Save for later processing. */
2611 if (prev_extend_bytes
) /* extend */
2612 save_inst
|= prev_inst
<< 16;
2614 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2616 /* This instruction is part of the prologue, but we don't
2617 need to do anything special to handle it. */
2619 else if (mips16_instruction_has_delay_slot (inst
, 0))
2620 /* JAL/JALR/JALX/JR */
2622 /* The instruction in the delay slot can be a part
2623 of the prologue, so move forward once more. */
2625 if (mips16_instruction_has_delay_slot (inst
, 1))
2628 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2629 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2634 this_non_prologue_insn
= 1;
2637 non_prologue_insns
+= this_non_prologue_insn
;
2639 /* A jump or branch, or enough non-prologue insns seen? If so,
2640 then we must have reached the end of the prologue by now. */
2641 if (prev_delay_slot
|| non_prologue_insns
> 1
2642 || mips16_instruction_is_compact_branch (inst
))
2645 prev_non_prologue_insn
= this_non_prologue_insn
;
2646 prev_delay_slot
= in_delay_slot
;
2647 prev_pc
= cur_pc
- prev_extend_bytes
;
2650 /* The entry instruction is typically the first instruction in a function,
2651 and it stores registers at offsets relative to the value of the old SP
2652 (before the prologue). But the value of the sp parameter to this
2653 function is the new SP (after the prologue has been executed). So we
2654 can't calculate those offsets until we've seen the entire prologue,
2655 and can calculate what the old SP must have been. */
2656 if (entry_inst
!= 0)
2658 int areg_count
= (entry_inst
>> 8) & 7;
2659 int sreg_count
= (entry_inst
>> 6) & 3;
2661 /* The entry instruction always subtracts 32 from the SP. */
2664 /* Now we can calculate what the SP must have been at the
2665 start of the function prologue. */
2668 /* Check if a0-a3 were saved in the caller's argument save area. */
2669 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2671 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2672 offset
+= mips_abi_regsize (gdbarch
);
2675 /* Check if the ra register was pushed on the stack. */
2677 if (entry_inst
& 0x20)
2679 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2680 offset
-= mips_abi_regsize (gdbarch
);
2683 /* Check if the s0 and s1 registers were pushed on the stack. */
2684 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2686 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2687 offset
-= mips_abi_regsize (gdbarch
);
2691 /* The SAVE instruction is similar to ENTRY, except that defined by the
2692 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2693 size of the frame is specified as an immediate field of instruction
2694 and an extended variation exists which lets additional registers and
2695 frame space to be specified. The instruction always treats registers
2696 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2697 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2699 static int args_table
[16] = {
2700 0, 0, 0, 0, 1, 1, 1, 1,
2701 2, 2, 2, 0, 3, 3, 4, -1,
2703 static int astatic_table
[16] = {
2704 0, 1, 2, 3, 0, 1, 2, 3,
2705 0, 1, 2, 4, 0, 1, 0, -1,
2707 int aregs
= (save_inst
>> 16) & 0xf;
2708 int xsregs
= (save_inst
>> 24) & 0x7;
2709 int args
= args_table
[aregs
];
2710 int astatic
= astatic_table
[aregs
];
2715 warning (_("Invalid number of argument registers encoded in SAVE."));
2720 warning (_("Invalid number of static registers encoded in SAVE."));
2724 /* For standard SAVE the frame size of 0 means 128. */
2725 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2726 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2729 frame_offset
+= frame_size
;
2731 /* Now we can calculate what the SP must have been at the
2732 start of the function prologue. */
2735 /* Check if A0-A3 were saved in the caller's argument save area. */
2736 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2738 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2739 offset
+= mips_abi_regsize (gdbarch
);
2744 /* Check if the RA register was pushed on the stack. */
2745 if (save_inst
& 0x40)
2747 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2748 offset
-= mips_abi_regsize (gdbarch
);
2751 /* Check if the S8 register was pushed on the stack. */
2754 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2755 offset
-= mips_abi_regsize (gdbarch
);
2758 /* Check if S2-S7 were pushed on the stack. */
2759 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2761 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2762 offset
-= mips_abi_regsize (gdbarch
);
2765 /* Check if the S1 register was pushed on the stack. */
2766 if (save_inst
& 0x10)
2768 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2769 offset
-= mips_abi_regsize (gdbarch
);
2771 /* Check if the S0 register was pushed on the stack. */
2772 if (save_inst
& 0x20)
2774 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2775 offset
-= mips_abi_regsize (gdbarch
);
2778 /* Check if A0-A3 were pushed on the stack. */
2779 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2781 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2782 offset
-= mips_abi_regsize (gdbarch
);
2786 if (this_cache
!= NULL
)
2789 (get_frame_register_signed (this_frame
,
2790 gdbarch_num_regs (gdbarch
) + frame_reg
)
2791 + frame_offset
- frame_adjust
);
2792 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2793 be able to get rid of the assignment below, evetually. But it's
2794 still needed for now. */
2795 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2796 + mips_regnum (gdbarch
)->pc
]
2797 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2800 /* Set end_prologue_addr to the address of the instruction immediately
2801 after the last one we scanned. Unless the last one looked like a
2802 non-prologue instruction (and we looked ahead), in which case use
2803 its address instead. */
2804 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2805 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2807 return end_prologue_addr
;
2810 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2811 Procedures that use the 32-bit instruction set are handled by the
2812 mips_insn32 unwinder. */
2814 static struct mips_frame_cache
*
2815 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2817 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2818 struct mips_frame_cache
*cache
;
2820 if ((*this_cache
) != NULL
)
2821 return (struct mips_frame_cache
*) (*this_cache
);
2822 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2823 (*this_cache
) = cache
;
2824 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2826 /* Analyze the function prologue. */
2828 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2829 CORE_ADDR start_addr
;
2831 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2832 if (start_addr
== 0)
2833 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2834 /* We can't analyze the prologue if we couldn't find the begining
2836 if (start_addr
== 0)
2839 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2840 (struct mips_frame_cache
*) *this_cache
);
2843 /* gdbarch_sp_regnum contains the value and not the address. */
2844 trad_frame_set_value (cache
->saved_regs
,
2845 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2848 return (struct mips_frame_cache
*) (*this_cache
);
2852 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2853 struct frame_id
*this_id
)
2855 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2857 /* This marks the outermost frame. */
2858 if (info
->base
== 0)
2860 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2863 static struct value
*
2864 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2865 void **this_cache
, int regnum
)
2867 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2869 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2873 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2874 struct frame_info
*this_frame
, void **this_cache
)
2876 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2877 CORE_ADDR pc
= get_frame_pc (this_frame
);
2878 if (mips_pc_is_mips16 (gdbarch
, pc
))
2883 static const struct frame_unwind mips_insn16_frame_unwind
=
2886 default_frame_unwind_stop_reason
,
2887 mips_insn16_frame_this_id
,
2888 mips_insn16_frame_prev_register
,
2890 mips_insn16_frame_sniffer
2894 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2897 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2902 static const struct frame_base mips_insn16_frame_base
=
2904 &mips_insn16_frame_unwind
,
2905 mips_insn16_frame_base_address
,
2906 mips_insn16_frame_base_address
,
2907 mips_insn16_frame_base_address
2910 static const struct frame_base
*
2911 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2913 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2914 CORE_ADDR pc
= get_frame_pc (this_frame
);
2915 if (mips_pc_is_mips16 (gdbarch
, pc
))
2916 return &mips_insn16_frame_base
;
2921 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2922 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2923 interpreted directly, and then multiplied by 4. */
2926 micromips_decode_imm9 (int imm
)
2928 imm
= (imm
^ 0x100) - 0x100;
2929 if (imm
> -3 && imm
< 2)
2934 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2935 the address of the first instruction past the prologue. */
2938 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2939 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2940 struct frame_info
*this_frame
,
2941 struct mips_frame_cache
*this_cache
)
2943 CORE_ADDR end_prologue_addr
;
2944 int prev_non_prologue_insn
= 0;
2945 int frame_reg
= MIPS_SP_REGNUM
;
2946 int this_non_prologue_insn
;
2947 int non_prologue_insns
= 0;
2948 long frame_offset
= 0; /* Size of stack frame. */
2949 long frame_adjust
= 0; /* Offset of FP from SP. */
2950 CORE_ADDR frame_addr
= 0; /* Value of $30, used as frame pointer. */
2951 int prev_delay_slot
= 0;
2955 ULONGEST insn
; /* current instruction */
2959 long v1_off
= 0; /* The assumption is LUI will replace it. */
2970 /* Can be called when there's no process, and hence when there's no
2972 if (this_frame
!= NULL
)
2973 sp
= get_frame_register_signed (this_frame
,
2974 gdbarch_num_regs (gdbarch
)
2979 if (limit_pc
> start_pc
+ 200)
2980 limit_pc
= start_pc
+ 200;
2983 /* Permit at most one non-prologue non-control-transfer instruction
2984 in the middle which may have been reordered by the compiler for
2986 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2988 this_non_prologue_insn
= 0;
2992 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2993 loc
+= MIPS_INSN16_SIZE
;
2994 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2996 /* 48-bit instructions. */
2997 case 3 * MIPS_INSN16_SIZE
:
2998 /* No prologue instructions in this category. */
2999 this_non_prologue_insn
= 1;
3000 loc
+= 2 * MIPS_INSN16_SIZE
;
3003 /* 32-bit instructions. */
3004 case 2 * MIPS_INSN16_SIZE
:
3006 insn
|= mips_fetch_instruction (gdbarch
,
3007 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
3008 loc
+= MIPS_INSN16_SIZE
;
3009 switch (micromips_op (insn
>> 16))
3011 /* Record $sp/$fp adjustment. */
3012 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3013 case 0x0: /* POOL32A: bits 000000 */
3014 case 0x16: /* POOL32S: bits 010110 */
3015 op
= b0s11_op (insn
);
3016 sreg
= b0s5_reg (insn
>> 16);
3017 treg
= b5s5_reg (insn
>> 16);
3018 dreg
= b11s5_reg (insn
);
3020 /* SUBU: bits 000000 00111010000 */
3021 /* DSUBU: bits 010110 00111010000 */
3022 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3024 /* (D)SUBU $sp, $v1 */
3026 else if (op
!= 0x150
3027 /* ADDU: bits 000000 00101010000 */
3028 /* DADDU: bits 010110 00101010000 */
3029 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3030 this_non_prologue_insn
= 1;
3033 case 0x8: /* POOL32B: bits 001000 */
3034 op
= b12s4_op (insn
);
3035 breg
= b0s5_reg (insn
>> 16);
3036 reglist
= sreg
= b5s5_reg (insn
>> 16);
3037 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3038 if ((op
== 0x9 || op
== 0xc)
3039 /* SWP: bits 001000 1001 */
3040 /* SDP: bits 001000 1100 */
3041 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3042 /* S[DW]P reg,offset($sp) */
3044 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3045 set_reg_offset (gdbarch
, this_cache
,
3047 set_reg_offset (gdbarch
, this_cache
,
3048 sreg
+ 1, sp
+ offset
+ s
);
3050 else if ((op
== 0xd || op
== 0xf)
3051 /* SWM: bits 001000 1101 */
3052 /* SDM: bits 001000 1111 */
3053 && breg
== MIPS_SP_REGNUM
3054 /* SWM reglist,offset($sp) */
3055 && ((reglist
>= 1 && reglist
<= 9)
3056 || (reglist
>= 16 && reglist
<= 25)))
3058 int sreglist
= min(reglist
& 0xf, 8);
3060 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3061 for (i
= 0; i
< sreglist
; i
++)
3062 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3063 if ((reglist
& 0xf) > 8)
3064 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3065 if ((reglist
& 0x10) == 0x10)
3066 set_reg_offset (gdbarch
, this_cache
,
3067 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3070 this_non_prologue_insn
= 1;
3073 /* Record $sp/$fp adjustment. */
3074 /* Discard (D)ADDIU $gp used for PIC code. */
3075 case 0xc: /* ADDIU: bits 001100 */
3076 case 0x17: /* DADDIU: bits 010111 */
3077 sreg
= b0s5_reg (insn
>> 16);
3078 dreg
= b5s5_reg (insn
>> 16);
3079 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3080 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3081 /* (D)ADDIU $sp, imm */
3083 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3084 /* (D)ADDIU $fp, $sp, imm */
3086 frame_addr
= sp
+ offset
;
3087 frame_adjust
= offset
;
3090 else if (sreg
!= 28 || dreg
!= 28)
3091 /* (D)ADDIU $gp, imm */
3092 this_non_prologue_insn
= 1;
3095 /* LUI $v1 is used for larger $sp adjustments. */
3096 /* Discard LUI $gp used for PIC code. */
3097 case 0x10: /* POOL32I: bits 010000 */
3098 if (b5s5_op (insn
>> 16) == 0xd
3099 /* LUI: bits 010000 001101 */
3100 && b0s5_reg (insn
>> 16) == 3)
3102 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3103 else if (b5s5_op (insn
>> 16) != 0xd
3104 /* LUI: bits 010000 001101 */
3105 || b0s5_reg (insn
>> 16) != 28)
3107 this_non_prologue_insn
= 1;
3110 /* ORI $v1 is used for larger $sp adjustments. */
3111 case 0x14: /* ORI: bits 010100 */
3112 sreg
= b0s5_reg (insn
>> 16);
3113 dreg
= b5s5_reg (insn
>> 16);
3114 if (sreg
== 3 && dreg
== 3)
3116 v1_off
|= b0s16_imm (insn
);
3118 this_non_prologue_insn
= 1;
3121 case 0x26: /* SWC1: bits 100110 */
3122 case 0x2e: /* SDC1: bits 101110 */
3123 breg
= b0s5_reg (insn
>> 16);
3124 if (breg
!= MIPS_SP_REGNUM
)
3125 /* S[DW]C1 reg,offset($sp) */
3126 this_non_prologue_insn
= 1;
3129 case 0x36: /* SD: bits 110110 */
3130 case 0x3e: /* SW: bits 111110 */
3131 breg
= b0s5_reg (insn
>> 16);
3132 sreg
= b5s5_reg (insn
>> 16);
3133 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3134 if (breg
== MIPS_SP_REGNUM
)
3135 /* S[DW] reg,offset($sp) */
3136 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3138 this_non_prologue_insn
= 1;
3142 /* The instruction in the delay slot can be a part
3143 of the prologue, so move forward once more. */
3144 if (micromips_instruction_has_delay_slot (insn
, 0))
3147 this_non_prologue_insn
= 1;
3153 /* 16-bit instructions. */
3154 case MIPS_INSN16_SIZE
:
3155 switch (micromips_op (insn
))
3157 case 0x3: /* MOVE: bits 000011 */
3158 sreg
= b0s5_reg (insn
);
3159 dreg
= b5s5_reg (insn
);
3160 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3166 else if ((sreg
& 0x1c) != 0x4)
3167 /* MOVE reg, $a0-$a3 */
3168 this_non_prologue_insn
= 1;
3171 case 0x11: /* POOL16C: bits 010001 */
3172 if (b6s4_op (insn
) == 0x5)
3173 /* SWM: bits 010001 0101 */
3175 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3176 reglist
= b4s2_regl (insn
);
3177 for (i
= 0; i
<= reglist
; i
++)
3178 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3179 set_reg_offset (gdbarch
, this_cache
,
3180 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3183 this_non_prologue_insn
= 1;
3186 case 0x13: /* POOL16D: bits 010011 */
3187 if ((insn
& 0x1) == 0x1)
3188 /* ADDIUSP: bits 010011 1 */
3189 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3190 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3191 /* ADDIUS5: bits 010011 0 */
3192 /* ADDIUS5 $sp, imm */
3193 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3195 this_non_prologue_insn
= 1;
3198 case 0x32: /* SWSP: bits 110010 */
3199 offset
= b0s5_imm (insn
) << 2;
3200 sreg
= b5s5_reg (insn
);
3201 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3205 /* The instruction in the delay slot can be a part
3206 of the prologue, so move forward once more. */
3207 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3210 this_non_prologue_insn
= 1;
3216 frame_offset
-= sp_adj
;
3218 non_prologue_insns
+= this_non_prologue_insn
;
3220 /* A jump or branch, enough non-prologue insns seen or positive
3221 stack adjustment? If so, then we must have reached the end
3222 of the prologue by now. */
3223 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3224 || micromips_instruction_is_compact_branch (insn
))
3227 prev_non_prologue_insn
= this_non_prologue_insn
;
3228 prev_delay_slot
= in_delay_slot
;
3232 if (this_cache
!= NULL
)
3235 (get_frame_register_signed (this_frame
,
3236 gdbarch_num_regs (gdbarch
) + frame_reg
)
3237 + frame_offset
- frame_adjust
);
3238 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3239 be able to get rid of the assignment below, evetually. But it's
3240 still needed for now. */
3241 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3242 + mips_regnum (gdbarch
)->pc
]
3243 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3246 /* Set end_prologue_addr to the address of the instruction immediately
3247 after the last one we scanned. Unless the last one looked like a
3248 non-prologue instruction (and we looked ahead), in which case use
3249 its address instead. */
3251 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3253 return end_prologue_addr
;
3256 /* Heuristic unwinder for procedures using microMIPS instructions.
3257 Procedures that use the 32-bit instruction set are handled by the
3258 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3260 static struct mips_frame_cache
*
3261 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3263 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3264 struct mips_frame_cache
*cache
;
3266 if ((*this_cache
) != NULL
)
3267 return (struct mips_frame_cache
*) (*this_cache
);
3269 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3270 (*this_cache
) = cache
;
3271 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3273 /* Analyze the function prologue. */
3275 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3276 CORE_ADDR start_addr
;
3278 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3279 if (start_addr
== 0)
3280 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3281 /* We can't analyze the prologue if we couldn't find the begining
3283 if (start_addr
== 0)
3286 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3287 (struct mips_frame_cache
*) *this_cache
);
3290 /* gdbarch_sp_regnum contains the value and not the address. */
3291 trad_frame_set_value (cache
->saved_regs
,
3292 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3295 return (struct mips_frame_cache
*) (*this_cache
);
3299 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3300 struct frame_id
*this_id
)
3302 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3304 /* This marks the outermost frame. */
3305 if (info
->base
== 0)
3307 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3310 static struct value
*
3311 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3312 void **this_cache
, int regnum
)
3314 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3316 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3320 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3321 struct frame_info
*this_frame
, void **this_cache
)
3323 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3324 CORE_ADDR pc
= get_frame_pc (this_frame
);
3326 if (mips_pc_is_micromips (gdbarch
, pc
))
3331 static const struct frame_unwind mips_micro_frame_unwind
=
3334 default_frame_unwind_stop_reason
,
3335 mips_micro_frame_this_id
,
3336 mips_micro_frame_prev_register
,
3338 mips_micro_frame_sniffer
3342 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3345 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3350 static const struct frame_base mips_micro_frame_base
=
3352 &mips_micro_frame_unwind
,
3353 mips_micro_frame_base_address
,
3354 mips_micro_frame_base_address
,
3355 mips_micro_frame_base_address
3358 static const struct frame_base
*
3359 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3361 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3362 CORE_ADDR pc
= get_frame_pc (this_frame
);
3364 if (mips_pc_is_micromips (gdbarch
, pc
))
3365 return &mips_micro_frame_base
;
3370 /* Mark all the registers as unset in the saved_regs array
3371 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3374 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3376 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3380 const int num_regs
= gdbarch_num_regs (gdbarch
);
3383 for (i
= 0; i
< num_regs
; i
++)
3385 this_cache
->saved_regs
[i
].addr
= -1;
3390 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3391 the associated FRAME_CACHE if not null.
3392 Return the address of the first instruction past the prologue. */
3395 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3396 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3397 struct frame_info
*this_frame
,
3398 struct mips_frame_cache
*this_cache
)
3400 int prev_non_prologue_insn
;
3401 int this_non_prologue_insn
;
3402 int non_prologue_insns
;
3403 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3405 int prev_delay_slot
;
3410 int frame_reg
= MIPS_SP_REGNUM
;
3412 CORE_ADDR end_prologue_addr
;
3413 int seen_sp_adjust
= 0;
3414 int load_immediate_bytes
= 0;
3416 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3418 /* Can be called when there's no process, and hence when there's no
3420 if (this_frame
!= NULL
)
3421 sp
= get_frame_register_signed (this_frame
,
3422 gdbarch_num_regs (gdbarch
)
3427 if (limit_pc
> start_pc
+ 200)
3428 limit_pc
= start_pc
+ 200;
3431 prev_non_prologue_insn
= 0;
3432 non_prologue_insns
= 0;
3433 prev_delay_slot
= 0;
3436 /* Permit at most one non-prologue non-control-transfer instruction
3437 in the middle which may have been reordered by the compiler for
3440 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3442 unsigned long inst
, high_word
;
3446 this_non_prologue_insn
= 0;
3449 /* Fetch the instruction. */
3450 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3453 /* Save some code by pre-extracting some useful fields. */
3454 high_word
= (inst
>> 16) & 0xffff;
3455 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3456 reg
= high_word
& 0x1f;
3458 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3459 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3460 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3462 if (offset
< 0) /* Negative stack adjustment? */
3463 frame_offset
-= offset
;
3465 /* Exit loop if a positive stack adjustment is found, which
3466 usually means that the stack cleanup code in the function
3467 epilogue is reached. */
3471 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3472 && !regsize_is_64_bits
)
3474 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3476 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3477 && regsize_is_64_bits
)
3479 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3480 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3482 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3484 /* Old gcc frame, r30 is virtual frame pointer. */
3485 if (offset
!= frame_offset
)
3486 frame_addr
= sp
+ offset
;
3487 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3489 unsigned alloca_adjust
;
3492 frame_addr
= get_frame_register_signed
3493 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3496 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3497 if (alloca_adjust
> 0)
3499 /* FP > SP + frame_size. This may be because of
3500 an alloca or somethings similar. Fix sp to
3501 "pre-alloca" value, and try again. */
3502 sp
+= alloca_adjust
;
3503 /* Need to reset the status of all registers. Otherwise,
3504 we will hit a guard that prevents the new address
3505 for each register to be recomputed during the second
3507 reset_saved_regs (gdbarch
, this_cache
);
3512 /* move $30,$sp. With different versions of gas this will be either
3513 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3514 Accept any one of these. */
3515 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3517 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3518 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3520 unsigned alloca_adjust
;
3523 frame_addr
= get_frame_register_signed
3524 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3526 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3527 if (alloca_adjust
> 0)
3529 /* FP > SP + frame_size. This may be because of
3530 an alloca or somethings similar. Fix sp to
3531 "pre-alloca" value, and try again. */
3533 /* Need to reset the status of all registers. Otherwise,
3534 we will hit a guard that prevents the new address
3535 for each register to be recomputed during the second
3537 reset_saved_regs (gdbarch
, this_cache
);
3542 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3543 && !regsize_is_64_bits
)
3545 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3547 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3548 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3549 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3550 || high_word
== 0x3c1c /* lui $gp,n */
3551 || high_word
== 0x279c /* addiu $gp,$gp,n */
3552 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3553 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3556 /* These instructions are part of the prologue, but we don't
3557 need to do anything special to handle them. */
3559 /* The instructions below load $at or $t0 with an immediate
3560 value in preparation for a stack adjustment via
3561 subu $sp,$sp,[$at,$t0]. These instructions could also
3562 initialize a local variable, so we accept them only before
3563 a stack adjustment instruction was seen. */
3564 else if (!seen_sp_adjust
3566 && (high_word
== 0x3c01 /* lui $at,n */
3567 || high_word
== 0x3c08 /* lui $t0,n */
3568 || high_word
== 0x3421 /* ori $at,$at,n */
3569 || high_word
== 0x3508 /* ori $t0,$t0,n */
3570 || high_word
== 0x3401 /* ori $at,$zero,n */
3571 || high_word
== 0x3408 /* ori $t0,$zero,n */
3574 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3576 /* Check for branches and jumps. The instruction in the delay
3577 slot can be a part of the prologue, so move forward once more. */
3578 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3582 /* This instruction is not an instruction typically found
3583 in a prologue, so we must have reached the end of the
3587 this_non_prologue_insn
= 1;
3590 non_prologue_insns
+= this_non_prologue_insn
;
3592 /* A jump or branch, or enough non-prologue insns seen? If so,
3593 then we must have reached the end of the prologue by now. */
3594 if (prev_delay_slot
|| non_prologue_insns
> 1)
3597 prev_non_prologue_insn
= this_non_prologue_insn
;
3598 prev_delay_slot
= in_delay_slot
;
3602 if (this_cache
!= NULL
)
3605 (get_frame_register_signed (this_frame
,
3606 gdbarch_num_regs (gdbarch
) + frame_reg
)
3608 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3609 this assignment below, eventually. But it's still needed
3611 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3612 + mips_regnum (gdbarch
)->pc
]
3613 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3617 /* Set end_prologue_addr to the address of the instruction immediately
3618 after the last one we scanned. Unless the last one looked like a
3619 non-prologue instruction (and we looked ahead), in which case use
3620 its address instead. */
3622 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3624 /* In a frameless function, we might have incorrectly
3625 skipped some load immediate instructions. Undo the skipping
3626 if the load immediate was not followed by a stack adjustment. */
3627 if (load_immediate_bytes
&& !seen_sp_adjust
)
3628 end_prologue_addr
-= load_immediate_bytes
;
3630 return end_prologue_addr
;
3633 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3634 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3635 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3636 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3638 static struct mips_frame_cache
*
3639 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3641 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3642 struct mips_frame_cache
*cache
;
3644 if ((*this_cache
) != NULL
)
3645 return (struct mips_frame_cache
*) (*this_cache
);
3647 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3648 (*this_cache
) = cache
;
3649 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3651 /* Analyze the function prologue. */
3653 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3654 CORE_ADDR start_addr
;
3656 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3657 if (start_addr
== 0)
3658 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3659 /* We can't analyze the prologue if we couldn't find the begining
3661 if (start_addr
== 0)
3664 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3665 (struct mips_frame_cache
*) *this_cache
);
3668 /* gdbarch_sp_regnum contains the value and not the address. */
3669 trad_frame_set_value (cache
->saved_regs
,
3670 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3673 return (struct mips_frame_cache
*) (*this_cache
);
3677 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3678 struct frame_id
*this_id
)
3680 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3682 /* This marks the outermost frame. */
3683 if (info
->base
== 0)
3685 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3688 static struct value
*
3689 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3690 void **this_cache
, int regnum
)
3692 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3694 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3698 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3699 struct frame_info
*this_frame
, void **this_cache
)
3701 CORE_ADDR pc
= get_frame_pc (this_frame
);
3702 if (mips_pc_is_mips (pc
))
3707 static const struct frame_unwind mips_insn32_frame_unwind
=
3710 default_frame_unwind_stop_reason
,
3711 mips_insn32_frame_this_id
,
3712 mips_insn32_frame_prev_register
,
3714 mips_insn32_frame_sniffer
3718 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3721 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3726 static const struct frame_base mips_insn32_frame_base
=
3728 &mips_insn32_frame_unwind
,
3729 mips_insn32_frame_base_address
,
3730 mips_insn32_frame_base_address
,
3731 mips_insn32_frame_base_address
3734 static const struct frame_base
*
3735 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3737 CORE_ADDR pc
= get_frame_pc (this_frame
);
3738 if (mips_pc_is_mips (pc
))
3739 return &mips_insn32_frame_base
;
3744 static struct trad_frame_cache
*
3745 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3748 CORE_ADDR start_addr
;
3749 CORE_ADDR stack_addr
;
3750 struct trad_frame_cache
*this_trad_cache
;
3751 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3752 int num_regs
= gdbarch_num_regs (gdbarch
);
3754 if ((*this_cache
) != NULL
)
3755 return (struct trad_frame_cache
*) (*this_cache
);
3756 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3757 (*this_cache
) = this_trad_cache
;
3759 /* The return address is in the link register. */
3760 trad_frame_set_reg_realreg (this_trad_cache
,
3761 gdbarch_pc_regnum (gdbarch
),
3762 num_regs
+ MIPS_RA_REGNUM
);
3764 /* Frame ID, since it's a frameless / stackless function, no stack
3765 space is allocated and SP on entry is the current SP. */
3766 pc
= get_frame_pc (this_frame
);
3767 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3768 stack_addr
= get_frame_register_signed (this_frame
,
3769 num_regs
+ MIPS_SP_REGNUM
);
3770 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3772 /* Assume that the frame's base is the same as the
3774 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3776 return this_trad_cache
;
3780 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3781 struct frame_id
*this_id
)
3783 struct trad_frame_cache
*this_trad_cache
3784 = mips_stub_frame_cache (this_frame
, this_cache
);
3785 trad_frame_get_id (this_trad_cache
, this_id
);
3788 static struct value
*
3789 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3790 void **this_cache
, int regnum
)
3792 struct trad_frame_cache
*this_trad_cache
3793 = mips_stub_frame_cache (this_frame
, this_cache
);
3794 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3798 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3799 struct frame_info
*this_frame
, void **this_cache
)
3802 struct obj_section
*s
;
3803 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3804 struct bound_minimal_symbol msym
;
3806 /* Use the stub unwinder for unreadable code. */
3807 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3810 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3813 /* Calling a PIC function from a non-PIC function passes through a
3814 stub. The stub for foo is named ".pic.foo". */
3815 msym
= lookup_minimal_symbol_by_pc (pc
);
3816 if (msym
.minsym
!= NULL
3817 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
3818 && startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
3824 static const struct frame_unwind mips_stub_frame_unwind
=
3827 default_frame_unwind_stop_reason
,
3828 mips_stub_frame_this_id
,
3829 mips_stub_frame_prev_register
,
3831 mips_stub_frame_sniffer
3835 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3838 struct trad_frame_cache
*this_trad_cache
3839 = mips_stub_frame_cache (this_frame
, this_cache
);
3840 return trad_frame_get_this_base (this_trad_cache
);
3843 static const struct frame_base mips_stub_frame_base
=
3845 &mips_stub_frame_unwind
,
3846 mips_stub_frame_base_address
,
3847 mips_stub_frame_base_address
,
3848 mips_stub_frame_base_address
3851 static const struct frame_base
*
3852 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3854 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3855 return &mips_stub_frame_base
;
3860 /* mips_addr_bits_remove - remove useless address bits */
3863 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3865 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3867 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3868 /* This hack is a work-around for existing boards using PMON, the
3869 simulator, and any other 64-bit targets that doesn't have true
3870 64-bit addressing. On these targets, the upper 32 bits of
3871 addresses are ignored by the hardware. Thus, the PC or SP are
3872 likely to have been sign extended to all 1s by instruction
3873 sequences that load 32-bit addresses. For example, a typical
3874 piece of code that loads an address is this:
3876 lui $r2, <upper 16 bits>
3877 ori $r2, <lower 16 bits>
3879 But the lui sign-extends the value such that the upper 32 bits
3880 may be all 1s. The workaround is simply to mask off these
3881 bits. In the future, gcc may be changed to support true 64-bit
3882 addressing, and this masking will have to be disabled. */
3883 return addr
&= 0xffffffffUL
;
3889 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3890 instruction and ending with a SC/SCD instruction. If such a sequence
3891 is found, attempt to step through it. A breakpoint is placed at the end of
3894 /* Instructions used during single-stepping of atomic sequences, standard
3896 #define LL_OPCODE 0x30
3897 #define LLD_OPCODE 0x34
3898 #define SC_OPCODE 0x38
3899 #define SCD_OPCODE 0x3c
3902 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3903 struct address_space
*aspace
, CORE_ADDR pc
)
3905 CORE_ADDR breaks
[2] = {-1, -1};
3907 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3911 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3912 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3914 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3915 /* Assume all atomic sequences start with a ll/lld instruction. */
3916 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3919 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3921 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3924 loc
+= MIPS_INSN32_SIZE
;
3925 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3927 /* Assume that there is at most one branch in the atomic
3928 sequence. If a branch is found, put a breakpoint in its
3929 destination address. */
3930 switch (itype_op (insn
))
3932 case 0: /* SPECIAL */
3933 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3934 return 0; /* fallback to the standard single-step code. */
3936 case 1: /* REGIMM */
3937 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3938 || ((itype_rt (insn
) & 0x1e) == 0
3939 && itype_rs (insn
) == 0)); /* BPOSGE* */
3943 return 0; /* fallback to the standard single-step code. */
3950 case 22: /* BLEZL */
3951 case 23: /* BGTTL */
3955 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3956 && (itype_rt (insn
) & 0x2) == 0);
3957 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3962 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3967 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3968 if (last_breakpoint
>= 1)
3969 return 0; /* More than one branch found, fallback to the
3970 standard single-step code. */
3971 breaks
[1] = branch_bp
;
3975 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3979 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3980 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3983 loc
+= MIPS_INSN32_SIZE
;
3985 /* Insert a breakpoint right after the end of the atomic sequence. */
3988 /* Check for duplicated breakpoints. Check also for a breakpoint
3989 placed (branch instruction's destination) in the atomic sequence. */
3990 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3991 last_breakpoint
= 0;
3993 /* Effectively inserts the breakpoints. */
3994 for (index
= 0; index
<= last_breakpoint
; index
++)
3995 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
4001 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4002 struct address_space
*aspace
,
4005 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4006 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4007 CORE_ADDR breaks
[2] = {-1, -1};
4008 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4016 /* Assume all atomic sequences start with a ll/lld instruction. */
4017 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4018 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4020 loc
+= MIPS_INSN16_SIZE
;
4022 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4023 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4025 loc
+= MIPS_INSN16_SIZE
;
4027 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4028 that no atomic sequence is longer than "atomic_sequence_length"
4030 for (insn_count
= 0;
4031 !sc_found
&& insn_count
< atomic_sequence_length
;
4036 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4037 loc
+= MIPS_INSN16_SIZE
;
4039 /* Assume that there is at most one conditional branch in the
4040 atomic sequence. If a branch is found, put a breakpoint in
4041 its destination address. */
4042 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4044 /* 48-bit instructions. */
4045 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
4046 loc
+= 2 * MIPS_INSN16_SIZE
;
4049 /* 32-bit instructions. */
4050 case 2 * MIPS_INSN16_SIZE
:
4051 switch (micromips_op (insn
))
4053 case 0x10: /* POOL32I: bits 010000 */
4054 if ((b5s5_op (insn
) & 0x18) != 0x0
4055 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4056 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4057 && (b5s5_op (insn
) & 0x1d) != 0x11
4058 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4059 && ((b5s5_op (insn
) & 0x1e) != 0x14
4060 || (insn
& 0x3) != 0x0)
4061 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4062 && (b5s5_op (insn
) & 0x1e) != 0x1a
4063 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4064 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4065 || (insn
& 0x3) != 0x0)
4066 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4067 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4068 || (insn
& 0x3) != 0x1))
4069 /* BC1ANY*: bits 010000 111xx xxx01 */
4073 case 0x25: /* BEQ: bits 100101 */
4074 case 0x2d: /* BNE: bits 101101 */
4076 insn
|= mips_fetch_instruction (gdbarch
,
4077 ISA_MICROMIPS
, loc
, NULL
);
4078 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4079 + micromips_relative_offset16 (insn
));
4083 case 0x00: /* POOL32A: bits 000000 */
4085 insn
|= mips_fetch_instruction (gdbarch
,
4086 ISA_MICROMIPS
, loc
, NULL
);
4087 if (b0s6_op (insn
) != 0x3c
4088 /* POOL32Axf: bits 000000 ... 111100 */
4089 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4090 /* JALR, JALR.HB: 000000 000x111100 111100 */
4091 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4095 case 0x1d: /* JALS: bits 011101 */
4096 case 0x35: /* J: bits 110101 */
4097 case 0x3d: /* JAL: bits 111101 */
4098 case 0x3c: /* JALX: bits 111100 */
4099 return 0; /* Fall back to the standard single-step code. */
4101 case 0x18: /* POOL32C: bits 011000 */
4102 if ((b12s4_op (insn
) & 0xb) == 0xb)
4103 /* SC, SCD: bits 011000 1x11 */
4107 loc
+= MIPS_INSN16_SIZE
;
4110 /* 16-bit instructions. */
4111 case MIPS_INSN16_SIZE
:
4112 switch (micromips_op (insn
))
4114 case 0x23: /* BEQZ16: bits 100011 */
4115 case 0x2b: /* BNEZ16: bits 101011 */
4116 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4120 case 0x11: /* POOL16C: bits 010001 */
4121 if ((b5s5_op (insn
) & 0x1c) != 0xc
4122 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4123 && b5s5_op (insn
) != 0x18)
4124 /* JRADDIUSP: bits 010001 11000 */
4126 return 0; /* Fall back to the standard single-step code. */
4128 case 0x33: /* B16: bits 110011 */
4129 return 0; /* Fall back to the standard single-step code. */
4135 if (last_breakpoint
>= 1)
4136 return 0; /* More than one branch found, fallback to the
4137 standard single-step code. */
4138 breaks
[1] = branch_bp
;
4145 /* Insert a breakpoint right after the end of the atomic sequence. */
4148 /* Check for duplicated breakpoints. Check also for a breakpoint
4149 placed (branch instruction's destination) in the atomic sequence */
4150 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4151 last_breakpoint
= 0;
4153 /* Effectively inserts the breakpoints. */
4154 for (index
= 0; index
<= last_breakpoint
; index
++)
4155 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
4161 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4162 struct address_space
*aspace
, CORE_ADDR pc
)
4164 if (mips_pc_is_mips (pc
))
4165 return mips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4166 else if (mips_pc_is_micromips (gdbarch
, pc
))
4167 return micromips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4172 /* mips_software_single_step() is called just before we want to resume
4173 the inferior, if we want to single-step it but there is no hardware
4174 or kernel single-step support (MIPS on GNU/Linux for example). We find
4175 the target of the coming instruction and breakpoint it. */
4178 mips_software_single_step (struct frame_info
*frame
)
4180 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4181 struct address_space
*aspace
= get_frame_address_space (frame
);
4182 CORE_ADDR pc
, next_pc
;
4184 pc
= get_frame_pc (frame
);
4185 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
4188 next_pc
= mips_next_pc (frame
, pc
);
4190 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
4194 /* Test whether the PC points to the return instruction at the
4195 end of a function. */
4198 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4203 /* This used to check for MIPS16, but this piece of code is never
4204 called for MIPS16 functions. And likewise microMIPS ones. */
4205 gdb_assert (mips_pc_is_mips (pc
));
4207 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4209 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4213 /* This fencepost looks highly suspicious to me. Removing it also
4214 seems suspicious as it could affect remote debugging across serial
4218 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4224 struct inferior
*inf
;
4226 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4228 fence
= start_pc
- heuristic_fence_post
;
4232 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4233 fence
= VM_MIN_ADDRESS
;
4235 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4237 inf
= current_inferior ();
4239 /* Search back for previous return. */
4240 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4241 if (start_pc
< fence
)
4243 /* It's not clear to me why we reach this point when
4244 stop_soon, but with this test, at least we
4245 don't print out warnings for every child forked (eg, on
4246 decstation). 22apr93 rich@cygnus.com. */
4247 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4249 static int blurb_printed
= 0;
4251 warning (_("GDB can't find the start of the function at %s."),
4252 paddress (gdbarch
, pc
));
4256 /* This actually happens frequently in embedded
4257 development, when you first connect to a board
4258 and your stack pointer and pc are nowhere in
4259 particular. This message needs to give people
4260 in that situation enough information to
4261 determine that it's no big deal. */
4262 printf_filtered ("\n\
4263 GDB is unable to find the start of the function at %s\n\
4264 and thus can't determine the size of that function's stack frame.\n\
4265 This means that GDB may be unable to access that stack frame, or\n\
4266 the frames below it.\n\
4267 This problem is most likely caused by an invalid program counter or\n\
4269 However, if you think GDB should simply search farther back\n\
4270 from %s for code which looks like the beginning of a\n\
4271 function, you can increase the range of the search using the `set\n\
4272 heuristic-fence-post' command.\n",
4273 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4280 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4282 unsigned short inst
;
4284 /* On MIPS16, any one of the following is likely to be the
4285 start of a function:
4291 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4292 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4293 if ((inst
& 0xff80) == 0x6480) /* save */
4295 if (start_pc
- instlen
>= fence
)
4297 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4298 start_pc
- instlen
, NULL
);
4299 if ((inst
& 0xf800) == 0xf000) /* extend */
4300 start_pc
-= instlen
;
4304 else if (((inst
& 0xf81f) == 0xe809
4305 && (inst
& 0x700) != 0x700) /* entry */
4306 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4307 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4308 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4310 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4311 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4316 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4324 /* On microMIPS, any one of the following is likely to be the
4325 start of a function:
4329 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4330 switch (micromips_op (insn
))
4332 case 0xc: /* ADDIU: bits 001100 */
4333 case 0x17: /* DADDIU: bits 010111 */
4334 sreg
= b0s5_reg (insn
);
4335 dreg
= b5s5_reg (insn
);
4337 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4338 pc
+ MIPS_INSN16_SIZE
, NULL
);
4339 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4340 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4341 /* (D)ADDIU $sp, imm */
4346 case 0x10: /* POOL32I: bits 010000 */
4347 if (b5s5_op (insn
) == 0xd
4348 /* LUI: bits 010000 001101 */
4349 && b0s5_reg (insn
>> 16) == 28)
4354 case 0x13: /* POOL16D: bits 010011 */
4355 if ((insn
& 0x1) == 0x1)
4356 /* ADDIUSP: bits 010011 1 */
4358 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4364 /* ADDIUS5: bits 010011 0 */
4366 dreg
= b5s5_reg (insn
);
4367 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4368 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4369 /* ADDIUS5 $sp, -imm */
4377 else if (mips_about_to_return (gdbarch
, start_pc
))
4379 /* Skip return and its delay slot. */
4380 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4387 struct mips_objfile_private
4393 /* According to the current ABI, should the type be passed in a
4394 floating-point register (assuming that there is space)? When there
4395 is no FPU, FP are not even considered as possible candidates for
4396 FP registers and, consequently this returns false - forces FP
4397 arguments into integer registers. */
4400 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4401 struct type
*arg_type
)
4403 return ((typecode
== TYPE_CODE_FLT
4404 || (MIPS_EABI (gdbarch
)
4405 && (typecode
== TYPE_CODE_STRUCT
4406 || typecode
== TYPE_CODE_UNION
)
4407 && TYPE_NFIELDS (arg_type
) == 1
4408 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4410 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4413 /* On o32, argument passing in GPRs depends on the alignment of the type being
4414 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4417 mips_type_needs_double_align (struct type
*type
)
4419 enum type_code typecode
= TYPE_CODE (type
);
4421 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4423 else if (typecode
== TYPE_CODE_STRUCT
)
4425 if (TYPE_NFIELDS (type
) < 1)
4427 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4429 else if (typecode
== TYPE_CODE_UNION
)
4433 n
= TYPE_NFIELDS (type
);
4434 for (i
= 0; i
< n
; i
++)
4435 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4442 /* Adjust the address downward (direction of stack growth) so that it
4443 is correctly aligned for a new stack frame. */
4445 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4447 return align_down (addr
, 16);
4450 /* Implement the "push_dummy_code" gdbarch method. */
4453 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4454 CORE_ADDR funaddr
, struct value
**args
,
4455 int nargs
, struct type
*value_type
,
4456 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4457 struct regcache
*regcache
)
4459 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4463 /* Reserve enough room on the stack for our breakpoint instruction. */
4464 bp_slot
= sp
- sizeof (nop_insn
);
4466 /* Return to microMIPS mode if calling microMIPS code to avoid
4467 triggering an address error exception on processors that only
4468 support microMIPS execution. */
4469 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4470 ? make_compact_addr (bp_slot
) : bp_slot
);
4472 /* The breakpoint layer automatically adjusts the address of
4473 breakpoints inserted in a branch delay slot. With enough
4474 bad luck, the 4 bytes located just before our breakpoint
4475 instruction could look like a branch instruction, and thus
4476 trigger the adjustement, and break the function call entirely.
4477 So, we reserve those 4 bytes and write a nop instruction
4478 to prevent that from happening. */
4479 nop_addr
= bp_slot
- sizeof (nop_insn
);
4480 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4481 sp
= mips_frame_align (gdbarch
, nop_addr
);
4483 /* Inferior resumes at the function entry point. */
4490 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4491 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4492 int nargs
, struct value
**args
, CORE_ADDR sp
,
4493 int struct_return
, CORE_ADDR struct_addr
)
4499 int stack_offset
= 0;
4500 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4501 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4502 int regsize
= mips_abi_regsize (gdbarch
);
4504 /* For shared libraries, "t9" needs to point at the function
4506 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4508 /* Set the return address register to point to the entry point of
4509 the program, where a breakpoint lies in wait. */
4510 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4512 /* First ensure that the stack and structure return address (if any)
4513 are properly aligned. The stack has to be at least 64-bit
4514 aligned even on 32-bit machines, because doubles must be 64-bit
4515 aligned. For n32 and n64, stack frames need to be 128-bit
4516 aligned, so we round to this widest known alignment. */
4518 sp
= align_down (sp
, 16);
4519 struct_addr
= align_down (struct_addr
, 16);
4521 /* Now make space on the stack for the args. We allocate more
4522 than necessary for EABI, because the first few arguments are
4523 passed in registers, but that's OK. */
4524 for (argnum
= 0; argnum
< nargs
; argnum
++)
4525 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
4526 sp
-= align_up (len
, 16);
4529 fprintf_unfiltered (gdb_stdlog
,
4530 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4531 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4533 /* Initialize the integer and float register pointers. */
4534 argreg
= MIPS_A0_REGNUM
;
4535 float_argreg
= mips_fpa0_regnum (gdbarch
);
4537 /* The struct_return pointer occupies the first parameter-passing reg. */
4541 fprintf_unfiltered (gdb_stdlog
,
4542 "mips_eabi_push_dummy_call: "
4543 "struct_return reg=%d %s\n",
4544 argreg
, paddress (gdbarch
, struct_addr
));
4545 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4548 /* Now load as many as possible of the first arguments into
4549 registers, and push the rest onto the stack. Loop thru args
4550 from first to last. */
4551 for (argnum
= 0; argnum
< nargs
; argnum
++)
4553 const gdb_byte
*val
;
4554 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4555 struct value
*arg
= args
[argnum
];
4556 struct type
*arg_type
= check_typedef (value_type (arg
));
4557 int len
= TYPE_LENGTH (arg_type
);
4558 enum type_code typecode
= TYPE_CODE (arg_type
);
4561 fprintf_unfiltered (gdb_stdlog
,
4562 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4563 argnum
+ 1, len
, (int) typecode
);
4565 /* The EABI passes structures that do not fit in a register by
4568 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4570 store_unsigned_integer (valbuf
, regsize
, byte_order
,
4571 value_address (arg
));
4572 typecode
= TYPE_CODE_PTR
;
4576 fprintf_unfiltered (gdb_stdlog
, " push");
4579 val
= value_contents (arg
);
4581 /* 32-bit ABIs always start floating point arguments in an
4582 even-numbered floating point register. Round the FP register
4583 up before the check to see if there are any FP registers
4584 left. Non MIPS_EABI targets also pass the FP in the integer
4585 registers so also round up normal registers. */
4586 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4588 if ((float_argreg
& 1))
4592 /* Floating point arguments passed in registers have to be
4593 treated specially. On 32-bit architectures, doubles
4594 are passed in register pairs; the even register gets
4595 the low word, and the odd register gets the high word.
4596 On non-EABI processors, the first two floating point arguments are
4597 also copied to general registers, because MIPS16 functions
4598 don't use float registers for arguments. This duplication of
4599 arguments in general registers can't hurt non-MIPS16 functions
4600 because those registers are normally skipped. */
4601 /* MIPS_EABI squeezes a struct that contains a single floating
4602 point value into an FP register instead of pushing it onto the
4604 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4605 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4607 /* EABI32 will pass doubles in consecutive registers, even on
4608 64-bit cores. At one time, we used to check the size of
4609 `float_argreg' to determine whether or not to pass doubles
4610 in consecutive registers, but this is not sufficient for
4611 making the ABI determination. */
4612 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4614 int low_offset
= gdbarch_byte_order (gdbarch
)
4615 == BFD_ENDIAN_BIG
? 4 : 0;
4618 /* Write the low word of the double to the even register(s). */
4619 regval
= extract_signed_integer (val
+ low_offset
,
4622 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4623 float_argreg
, phex (regval
, 4));
4624 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4626 /* Write the high word of the double to the odd register(s). */
4627 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4630 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4631 float_argreg
, phex (regval
, 4));
4632 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4636 /* This is a floating point value that fits entirely
4637 in a single register. */
4638 /* On 32 bit ABI's the float_argreg is further adjusted
4639 above to ensure that it is even register aligned. */
4640 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4642 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4643 float_argreg
, phex (regval
, len
));
4644 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4649 /* Copy the argument to general registers or the stack in
4650 register-sized pieces. Large arguments are split between
4651 registers and stack. */
4652 /* Note: structs whose size is not a multiple of regsize
4653 are treated specially: Irix cc passes
4654 them in registers where gcc sometimes puts them on the
4655 stack. For maximum compatibility, we will put them in
4657 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
4659 /* Note: Floating-point values that didn't fit into an FP
4660 register are only written to memory. */
4663 /* Remember if the argument was written to the stack. */
4664 int stack_used_p
= 0;
4665 int partial_len
= (len
< regsize
? len
: regsize
);
4668 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4671 /* Write this portion of the argument to the stack. */
4672 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4674 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4676 /* Should shorter than int integer values be
4677 promoted to int before being stored? */
4678 int longword_offset
= 0;
4681 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4684 && (typecode
== TYPE_CODE_INT
4685 || typecode
== TYPE_CODE_PTR
4686 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4687 longword_offset
= regsize
- len
;
4688 else if ((typecode
== TYPE_CODE_STRUCT
4689 || typecode
== TYPE_CODE_UNION
)
4690 && TYPE_LENGTH (arg_type
) < regsize
)
4691 longword_offset
= regsize
- len
;
4696 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4697 paddress (gdbarch
, stack_offset
));
4698 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4699 paddress (gdbarch
, longword_offset
));
4702 addr
= sp
+ stack_offset
+ longword_offset
;
4707 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4708 paddress (gdbarch
, addr
));
4709 for (i
= 0; i
< partial_len
; i
++)
4711 fprintf_unfiltered (gdb_stdlog
, "%02x",
4715 write_memory (addr
, val
, partial_len
);
4718 /* Note!!! This is NOT an else clause. Odd sized
4719 structs may go thru BOTH paths. Floating point
4720 arguments will not. */
4721 /* Write this portion of the argument to a general
4722 purpose register. */
4723 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4724 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4727 extract_signed_integer (val
, partial_len
, byte_order
);
4730 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4732 phex (regval
, regsize
));
4733 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4740 /* Compute the offset into the stack at which we will
4741 copy the next parameter.
4743 In the new EABI (and the NABI32), the stack_offset
4744 only needs to be adjusted when it has been used. */
4747 stack_offset
+= align_up (partial_len
, regsize
);
4751 fprintf_unfiltered (gdb_stdlog
, "\n");
4754 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4756 /* Return adjusted stack pointer. */
4760 /* Determine the return value convention being used. */
4762 static enum return_value_convention
4763 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4764 struct type
*type
, struct regcache
*regcache
,
4765 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4767 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4768 int fp_return_type
= 0;
4769 int offset
, regnum
, xfer
;
4771 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4772 return RETURN_VALUE_STRUCT_CONVENTION
;
4774 /* Floating point type? */
4775 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4777 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4779 /* Structs with a single field of float type
4780 are returned in a floating point register. */
4781 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4782 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4783 && TYPE_NFIELDS (type
) == 1)
4785 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4787 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4794 /* A floating-point value belongs in the least significant part
4797 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4798 regnum
= mips_regnum (gdbarch
)->fp0
;
4802 /* An integer value goes in V0/V1. */
4804 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4805 regnum
= MIPS_V0_REGNUM
;
4808 offset
< TYPE_LENGTH (type
);
4809 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4811 xfer
= mips_abi_regsize (gdbarch
);
4812 if (offset
+ xfer
> TYPE_LENGTH (type
))
4813 xfer
= TYPE_LENGTH (type
) - offset
;
4814 mips_xfer_register (gdbarch
, regcache
,
4815 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4816 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4820 return RETURN_VALUE_REGISTER_CONVENTION
;
4824 /* N32/N64 ABI stuff. */
4826 /* Search for a naturally aligned double at OFFSET inside a struct
4827 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4831 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4836 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4839 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4842 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4845 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4848 struct type
*field_type
;
4850 /* We're only looking at normal fields. */
4851 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4852 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4855 /* If we have gone past the offset, there is no double to pass. */
4856 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4860 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4862 /* If this field is entirely before the requested offset, go
4863 on to the next one. */
4864 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4867 /* If this is our special aligned double, we can stop. */
4868 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4869 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4872 /* This field starts at or before the requested offset, and
4873 overlaps it. If it is a structure, recurse inwards. */
4874 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4881 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4882 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4883 int nargs
, struct value
**args
, CORE_ADDR sp
,
4884 int struct_return
, CORE_ADDR struct_addr
)
4890 int stack_offset
= 0;
4891 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4892 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4894 /* For shared libraries, "t9" needs to point at the function
4896 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4898 /* Set the return address register to point to the entry point of
4899 the program, where a breakpoint lies in wait. */
4900 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4902 /* First ensure that the stack and structure return address (if any)
4903 are properly aligned. The stack has to be at least 64-bit
4904 aligned even on 32-bit machines, because doubles must be 64-bit
4905 aligned. For n32 and n64, stack frames need to be 128-bit
4906 aligned, so we round to this widest known alignment. */
4908 sp
= align_down (sp
, 16);
4909 struct_addr
= align_down (struct_addr
, 16);
4911 /* Now make space on the stack for the args. */
4912 for (argnum
= 0; argnum
< nargs
; argnum
++)
4913 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4914 sp
-= align_up (len
, 16);
4917 fprintf_unfiltered (gdb_stdlog
,
4918 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4919 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4921 /* Initialize the integer and float register pointers. */
4922 argreg
= MIPS_A0_REGNUM
;
4923 float_argreg
= mips_fpa0_regnum (gdbarch
);
4925 /* The struct_return pointer occupies the first parameter-passing reg. */
4929 fprintf_unfiltered (gdb_stdlog
,
4930 "mips_n32n64_push_dummy_call: "
4931 "struct_return reg=%d %s\n",
4932 argreg
, paddress (gdbarch
, struct_addr
));
4933 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4936 /* Now load as many as possible of the first arguments into
4937 registers, and push the rest onto the stack. Loop thru args
4938 from first to last. */
4939 for (argnum
= 0; argnum
< nargs
; argnum
++)
4941 const gdb_byte
*val
;
4942 struct value
*arg
= args
[argnum
];
4943 struct type
*arg_type
= check_typedef (value_type (arg
));
4944 int len
= TYPE_LENGTH (arg_type
);
4945 enum type_code typecode
= TYPE_CODE (arg_type
);
4948 fprintf_unfiltered (gdb_stdlog
,
4949 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4950 argnum
+ 1, len
, (int) typecode
);
4952 val
= value_contents (arg
);
4954 /* A 128-bit long double value requires an even-odd pair of
4955 floating-point registers. */
4957 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4958 && (float_argreg
& 1))
4964 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4965 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4967 /* This is a floating point value that fits entirely
4968 in a single register or a pair of registers. */
4969 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4970 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4972 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4973 float_argreg
, phex (regval
, reglen
));
4974 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4977 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4978 argreg
, phex (regval
, reglen
));
4979 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4984 regval
= extract_unsigned_integer (val
+ reglen
,
4985 reglen
, byte_order
);
4987 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4988 float_argreg
, phex (regval
, reglen
));
4989 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4992 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4993 argreg
, phex (regval
, reglen
));
4994 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5001 /* Copy the argument to general registers or the stack in
5002 register-sized pieces. Large arguments are split between
5003 registers and stack. */
5004 /* For N32/N64, structs, unions, or other composite types are
5005 treated as a sequence of doublewords, and are passed in integer
5006 or floating point registers as though they were simple scalar
5007 parameters to the extent that they fit, with any excess on the
5008 stack packed according to the normal memory layout of the
5010 The caller does not reserve space for the register arguments;
5011 the callee is responsible for reserving it if required. */
5012 /* Note: Floating-point values that didn't fit into an FP
5013 register are only written to memory. */
5016 /* Remember if the argument was written to the stack. */
5017 int stack_used_p
= 0;
5018 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5021 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5024 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5025 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
5027 /* Write this portion of the argument to the stack. */
5028 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
5030 /* Should shorter than int integer values be
5031 promoted to int before being stored? */
5032 int longword_offset
= 0;
5035 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5037 if ((typecode
== TYPE_CODE_INT
5038 || typecode
== TYPE_CODE_PTR
)
5040 longword_offset
= MIPS64_REGSIZE
- len
;
5045 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5046 paddress (gdbarch
, stack_offset
));
5047 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5048 paddress (gdbarch
, longword_offset
));
5051 addr
= sp
+ stack_offset
+ longword_offset
;
5056 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5057 paddress (gdbarch
, addr
));
5058 for (i
= 0; i
< partial_len
; i
++)
5060 fprintf_unfiltered (gdb_stdlog
, "%02x",
5064 write_memory (addr
, val
, partial_len
);
5067 /* Note!!! This is NOT an else clause. Odd sized
5068 structs may go thru BOTH paths. */
5069 /* Write this portion of the argument to a general
5070 purpose register. */
5071 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5075 /* Sign extend pointers, 32-bit integers and signed
5076 16-bit and 8-bit integers; everything else is taken
5079 if ((partial_len
== 4
5080 && (typecode
== TYPE_CODE_PTR
5081 || typecode
== TYPE_CODE_INT
))
5083 && typecode
== TYPE_CODE_INT
5084 && !TYPE_UNSIGNED (arg_type
)))
5085 regval
= extract_signed_integer (val
, partial_len
,
5088 regval
= extract_unsigned_integer (val
, partial_len
,
5091 /* A non-floating-point argument being passed in a
5092 general register. If a struct or union, and if
5093 the remaining length is smaller than the register
5094 size, we have to adjust the register value on
5097 It does not seem to be necessary to do the
5098 same for integral types. */
5100 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5101 && partial_len
< MIPS64_REGSIZE
5102 && (typecode
== TYPE_CODE_STRUCT
5103 || typecode
== TYPE_CODE_UNION
))
5104 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5108 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5110 phex (regval
, MIPS64_REGSIZE
));
5111 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5113 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5114 TYPE_LENGTH (arg_type
) - len
))
5117 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5119 phex (regval
, MIPS64_REGSIZE
));
5120 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5131 /* Compute the offset into the stack at which we will
5132 copy the next parameter.
5134 In N32 (N64?), the stack_offset only needs to be
5135 adjusted when it has been used. */
5138 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5142 fprintf_unfiltered (gdb_stdlog
, "\n");
5145 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5147 /* Return adjusted stack pointer. */
5151 static enum return_value_convention
5152 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5153 struct type
*type
, struct regcache
*regcache
,
5154 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5156 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5158 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5160 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5161 if needed), as appropriate for the type. Composite results (struct,
5162 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5165 * A struct with only one or two floating point fields is returned in $f0
5166 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5169 * Any other composite results of at most 128 bits are returned in
5170 $2 (first 64 bits) and $3 (remainder, if necessary).
5172 * Larger composite results are handled by converting the function to a
5173 procedure with an implicit first parameter, which is a pointer to an area
5174 reserved by the caller to receive the result. [The o32-bit ABI requires
5175 that all composite results be handled by conversion to implicit first
5176 parameters. The MIPS/SGI Fortran implementation has always made a
5177 specific exception to return COMPLEX results in the floating point
5180 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5181 return RETURN_VALUE_STRUCT_CONVENTION
;
5182 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5183 && TYPE_LENGTH (type
) == 16
5184 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5186 /* A 128-bit floating-point value fills both $f0 and $f2. The
5187 two registers are used in the same as memory order, so the
5188 eight bytes with the lower memory address are in $f0. */
5190 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5191 mips_xfer_register (gdbarch
, regcache
,
5192 (gdbarch_num_regs (gdbarch
)
5193 + mips_regnum (gdbarch
)->fp0
),
5194 8, gdbarch_byte_order (gdbarch
),
5195 readbuf
, writebuf
, 0);
5196 mips_xfer_register (gdbarch
, regcache
,
5197 (gdbarch_num_regs (gdbarch
)
5198 + mips_regnum (gdbarch
)->fp0
+ 2),
5199 8, gdbarch_byte_order (gdbarch
),
5200 readbuf
? readbuf
+ 8 : readbuf
,
5201 writebuf
? writebuf
+ 8 : writebuf
, 0);
5202 return RETURN_VALUE_REGISTER_CONVENTION
;
5204 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5205 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5207 /* A single or double floating-point value that fits in FP0. */
5209 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5210 mips_xfer_register (gdbarch
, regcache
,
5211 (gdbarch_num_regs (gdbarch
)
5212 + mips_regnum (gdbarch
)->fp0
),
5214 gdbarch_byte_order (gdbarch
),
5215 readbuf
, writebuf
, 0);
5216 return RETURN_VALUE_REGISTER_CONVENTION
;
5218 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5219 && TYPE_NFIELDS (type
) <= 2
5220 && TYPE_NFIELDS (type
) >= 1
5221 && ((TYPE_NFIELDS (type
) == 1
5222 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5224 || (TYPE_NFIELDS (type
) == 2
5225 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5227 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
5228 == TYPE_CODE_FLT
))))
5230 /* A struct that contains one or two floats. Each value is part
5231 in the least significant part of their floating point
5232 register (or GPR, for soft float). */
5235 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5236 ? mips_regnum (gdbarch
)->fp0
5238 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5240 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5243 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5245 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5247 /* A 16-byte long double field goes in two consecutive
5249 mips_xfer_register (gdbarch
, regcache
,
5250 gdbarch_num_regs (gdbarch
) + regnum
,
5252 gdbarch_byte_order (gdbarch
),
5253 readbuf
, writebuf
, offset
);
5254 mips_xfer_register (gdbarch
, regcache
,
5255 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5257 gdbarch_byte_order (gdbarch
),
5258 readbuf
, writebuf
, offset
+ 8);
5261 mips_xfer_register (gdbarch
, regcache
,
5262 gdbarch_num_regs (gdbarch
) + regnum
,
5263 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5264 gdbarch_byte_order (gdbarch
),
5265 readbuf
, writebuf
, offset
);
5267 return RETURN_VALUE_REGISTER_CONVENTION
;
5269 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5270 || TYPE_CODE (type
) == TYPE_CODE_UNION
5271 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5273 /* A composite type. Extract the left justified value,
5274 regardless of the byte order. I.e. DO NOT USE
5278 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5279 offset
< TYPE_LENGTH (type
);
5280 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5282 int xfer
= register_size (gdbarch
, regnum
);
5283 if (offset
+ xfer
> TYPE_LENGTH (type
))
5284 xfer
= TYPE_LENGTH (type
) - offset
;
5286 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5287 offset
, xfer
, regnum
);
5288 mips_xfer_register (gdbarch
, regcache
,
5289 gdbarch_num_regs (gdbarch
) + regnum
,
5290 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5293 return RETURN_VALUE_REGISTER_CONVENTION
;
5297 /* A scalar extract each part but least-significant-byte
5301 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5302 offset
< TYPE_LENGTH (type
);
5303 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5305 int xfer
= register_size (gdbarch
, regnum
);
5306 if (offset
+ xfer
> TYPE_LENGTH (type
))
5307 xfer
= TYPE_LENGTH (type
) - offset
;
5309 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5310 offset
, xfer
, regnum
);
5311 mips_xfer_register (gdbarch
, regcache
,
5312 gdbarch_num_regs (gdbarch
) + regnum
,
5313 xfer
, gdbarch_byte_order (gdbarch
),
5314 readbuf
, writebuf
, offset
);
5316 return RETURN_VALUE_REGISTER_CONVENTION
;
5320 /* Which registers to use for passing floating-point values between
5321 function calls, one of floating-point, general and both kinds of
5322 registers. O32 and O64 use different register kinds for standard
5323 MIPS and MIPS16 code; to make the handling of cases where we may
5324 not know what kind of code is being used (e.g. no debug information)
5325 easier we sometimes use both kinds. */
5334 /* O32 ABI stuff. */
5337 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5338 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5339 int nargs
, struct value
**args
, CORE_ADDR sp
,
5340 int struct_return
, CORE_ADDR struct_addr
)
5346 int stack_offset
= 0;
5347 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5348 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5350 /* For shared libraries, "t9" needs to point at the function
5352 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5354 /* Set the return address register to point to the entry point of
5355 the program, where a breakpoint lies in wait. */
5356 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5358 /* First ensure that the stack and structure return address (if any)
5359 are properly aligned. The stack has to be at least 64-bit
5360 aligned even on 32-bit machines, because doubles must be 64-bit
5361 aligned. For n32 and n64, stack frames need to be 128-bit
5362 aligned, so we round to this widest known alignment. */
5364 sp
= align_down (sp
, 16);
5365 struct_addr
= align_down (struct_addr
, 16);
5367 /* Now make space on the stack for the args. */
5368 for (argnum
= 0; argnum
< nargs
; argnum
++)
5370 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5372 /* Align to double-word if necessary. */
5373 if (mips_type_needs_double_align (arg_type
))
5374 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5375 /* Allocate space on the stack. */
5376 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5378 sp
-= align_up (len
, 16);
5381 fprintf_unfiltered (gdb_stdlog
,
5382 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5383 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5385 /* Initialize the integer and float register pointers. */
5386 argreg
= MIPS_A0_REGNUM
;
5387 float_argreg
= mips_fpa0_regnum (gdbarch
);
5389 /* The struct_return pointer occupies the first parameter-passing reg. */
5393 fprintf_unfiltered (gdb_stdlog
,
5394 "mips_o32_push_dummy_call: "
5395 "struct_return reg=%d %s\n",
5396 argreg
, paddress (gdbarch
, struct_addr
));
5397 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5398 stack_offset
+= MIPS32_REGSIZE
;
5401 /* Now load as many as possible of the first arguments into
5402 registers, and push the rest onto the stack. Loop thru args
5403 from first to last. */
5404 for (argnum
= 0; argnum
< nargs
; argnum
++)
5406 const gdb_byte
*val
;
5407 struct value
*arg
= args
[argnum
];
5408 struct type
*arg_type
= check_typedef (value_type (arg
));
5409 int len
= TYPE_LENGTH (arg_type
);
5410 enum type_code typecode
= TYPE_CODE (arg_type
);
5413 fprintf_unfiltered (gdb_stdlog
,
5414 "mips_o32_push_dummy_call: %d len=%d type=%d",
5415 argnum
+ 1, len
, (int) typecode
);
5417 val
= value_contents (arg
);
5419 /* 32-bit ABIs always start floating point arguments in an
5420 even-numbered floating point register. Round the FP register
5421 up before the check to see if there are any FP registers
5422 left. O32 targets also pass the FP in the integer registers
5423 so also round up normal registers. */
5424 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5426 if ((float_argreg
& 1))
5430 /* Floating point arguments passed in registers have to be
5431 treated specially. On 32-bit architectures, doubles are
5432 passed in register pairs; the even FP register gets the
5433 low word, and the odd FP register gets the high word.
5434 On O32, the first two floating point arguments are also
5435 copied to general registers, following their memory order,
5436 because MIPS16 functions don't use float registers for
5437 arguments. This duplication of arguments in general
5438 registers can't hurt non-MIPS16 functions, because those
5439 registers are normally skipped. */
5441 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5442 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5444 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5446 int freg_offset
= gdbarch_byte_order (gdbarch
)
5447 == BFD_ENDIAN_BIG
? 1 : 0;
5448 unsigned long regval
;
5451 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5453 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5454 float_argreg
+ freg_offset
,
5456 regcache_cooked_write_unsigned (regcache
,
5457 float_argreg
++ + freg_offset
,
5460 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5461 argreg
, phex (regval
, 4));
5462 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5465 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5467 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5468 float_argreg
- freg_offset
,
5470 regcache_cooked_write_unsigned (regcache
,
5471 float_argreg
++ - freg_offset
,
5474 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5475 argreg
, phex (regval
, 4));
5476 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5480 /* This is a floating point value that fits entirely
5481 in a single register. */
5482 /* On 32 bit ABI's the float_argreg is further adjusted
5483 above to ensure that it is even register aligned. */
5484 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5486 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5487 float_argreg
, phex (regval
, len
));
5488 regcache_cooked_write_unsigned (regcache
,
5489 float_argreg
++, regval
);
5490 /* Although two FP registers are reserved for each
5491 argument, only one corresponding integer register is
5494 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5495 argreg
, phex (regval
, len
));
5496 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5498 /* Reserve space for the FP register. */
5499 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5503 /* Copy the argument to general registers or the stack in
5504 register-sized pieces. Large arguments are split between
5505 registers and stack. */
5506 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5507 are treated specially: Irix cc passes
5508 them in registers where gcc sometimes puts them on the
5509 stack. For maximum compatibility, we will put them in
5511 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5512 && len
% MIPS32_REGSIZE
!= 0);
5513 /* Structures should be aligned to eight bytes (even arg registers)
5514 on MIPS_ABI_O32, if their first member has double precision. */
5515 if (mips_type_needs_double_align (arg_type
))
5520 stack_offset
+= MIPS32_REGSIZE
;
5525 /* Remember if the argument was written to the stack. */
5526 int stack_used_p
= 0;
5527 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5530 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5533 /* Write this portion of the argument to the stack. */
5534 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5535 || odd_sized_struct
)
5537 /* Should shorter than int integer values be
5538 promoted to int before being stored? */
5539 int longword_offset
= 0;
5545 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5546 paddress (gdbarch
, stack_offset
));
5547 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5548 paddress (gdbarch
, longword_offset
));
5551 addr
= sp
+ stack_offset
+ longword_offset
;
5556 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5557 paddress (gdbarch
, addr
));
5558 for (i
= 0; i
< partial_len
; i
++)
5560 fprintf_unfiltered (gdb_stdlog
, "%02x",
5564 write_memory (addr
, val
, partial_len
);
5567 /* Note!!! This is NOT an else clause. Odd sized
5568 structs may go thru BOTH paths. */
5569 /* Write this portion of the argument to a general
5570 purpose register. */
5571 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5573 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5575 /* Value may need to be sign extended, because
5576 mips_isa_regsize() != mips_abi_regsize(). */
5578 /* A non-floating-point argument being passed in a
5579 general register. If a struct or union, and if
5580 the remaining length is smaller than the register
5581 size, we have to adjust the register value on
5584 It does not seem to be necessary to do the
5585 same for integral types.
5587 Also don't do this adjustment on O64 binaries.
5589 cagney/2001-07-23: gdb/179: Also, GCC, when
5590 outputting LE O32 with sizeof (struct) <
5591 mips_abi_regsize(), generates a left shift
5592 as part of storing the argument in a register
5593 (the left shift isn't generated when
5594 sizeof (struct) >= mips_abi_regsize()). Since
5595 it is quite possible that this is GCC
5596 contradicting the LE/O32 ABI, GDB has not been
5597 adjusted to accommodate this. Either someone
5598 needs to demonstrate that the LE/O32 ABI
5599 specifies such a left shift OR this new ABI gets
5600 identified as such and GDB gets tweaked
5603 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5604 && partial_len
< MIPS32_REGSIZE
5605 && (typecode
== TYPE_CODE_STRUCT
5606 || typecode
== TYPE_CODE_UNION
))
5607 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5611 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5613 phex (regval
, MIPS32_REGSIZE
));
5614 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5617 /* Prevent subsequent floating point arguments from
5618 being passed in floating point registers. */
5619 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5625 /* Compute the offset into the stack at which we will
5626 copy the next parameter.
5628 In older ABIs, the caller reserved space for
5629 registers that contained arguments. This was loosely
5630 refered to as their "home". Consequently, space is
5631 always allocated. */
5633 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5637 fprintf_unfiltered (gdb_stdlog
, "\n");
5640 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5642 /* Return adjusted stack pointer. */
5646 static enum return_value_convention
5647 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5648 struct type
*type
, struct regcache
*regcache
,
5649 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5651 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5652 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5653 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5654 enum mips_fval_reg fval_reg
;
5656 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5657 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5658 || TYPE_CODE (type
) == TYPE_CODE_UNION
5659 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5660 return RETURN_VALUE_STRUCT_CONVENTION
;
5661 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5662 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5664 /* A single-precision floating-point value. If reading in or copying,
5665 then we get it from/put it to FP0 for standard MIPS code or GPR2
5666 for MIPS16 code. If writing out only, then we put it to both FP0
5667 and GPR2. We do not support reading in with no function known, if
5668 this safety check ever triggers, then we'll have to try harder. */
5669 gdb_assert (function
|| !readbuf
);
5674 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5677 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5679 case mips_fval_both
:
5680 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5683 if (fval_reg
!= mips_fval_gpr
)
5684 mips_xfer_register (gdbarch
, regcache
,
5685 (gdbarch_num_regs (gdbarch
)
5686 + mips_regnum (gdbarch
)->fp0
),
5688 gdbarch_byte_order (gdbarch
),
5689 readbuf
, writebuf
, 0);
5690 if (fval_reg
!= mips_fval_fpr
)
5691 mips_xfer_register (gdbarch
, regcache
,
5692 gdbarch_num_regs (gdbarch
) + 2,
5694 gdbarch_byte_order (gdbarch
),
5695 readbuf
, writebuf
, 0);
5696 return RETURN_VALUE_REGISTER_CONVENTION
;
5698 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5699 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5701 /* A double-precision floating-point value. If reading in or copying,
5702 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5703 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5704 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5705 no function known, if this safety check ever triggers, then we'll
5706 have to try harder. */
5707 gdb_assert (function
|| !readbuf
);
5712 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5715 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5717 case mips_fval_both
:
5718 fprintf_unfiltered (gdb_stderr
,
5719 "Return float in $fp1/$fp0 and $2/$3\n");
5722 if (fval_reg
!= mips_fval_gpr
)
5724 /* The most significant part goes in FP1, and the least significant
5726 switch (gdbarch_byte_order (gdbarch
))
5728 case BFD_ENDIAN_LITTLE
:
5729 mips_xfer_register (gdbarch
, regcache
,
5730 (gdbarch_num_regs (gdbarch
)
5731 + mips_regnum (gdbarch
)->fp0
+ 0),
5732 4, gdbarch_byte_order (gdbarch
),
5733 readbuf
, writebuf
, 0);
5734 mips_xfer_register (gdbarch
, regcache
,
5735 (gdbarch_num_regs (gdbarch
)
5736 + mips_regnum (gdbarch
)->fp0
+ 1),
5737 4, gdbarch_byte_order (gdbarch
),
5738 readbuf
, writebuf
, 4);
5740 case BFD_ENDIAN_BIG
:
5741 mips_xfer_register (gdbarch
, regcache
,
5742 (gdbarch_num_regs (gdbarch
)
5743 + mips_regnum (gdbarch
)->fp0
+ 1),
5744 4, gdbarch_byte_order (gdbarch
),
5745 readbuf
, writebuf
, 0);
5746 mips_xfer_register (gdbarch
, regcache
,
5747 (gdbarch_num_regs (gdbarch
)
5748 + mips_regnum (gdbarch
)->fp0
+ 0),
5749 4, gdbarch_byte_order (gdbarch
),
5750 readbuf
, writebuf
, 4);
5753 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5756 if (fval_reg
!= mips_fval_fpr
)
5758 /* The two 32-bit parts are always placed in GPR2 and GPR3
5759 following these registers' memory order. */
5760 mips_xfer_register (gdbarch
, regcache
,
5761 gdbarch_num_regs (gdbarch
) + 2,
5762 4, gdbarch_byte_order (gdbarch
),
5763 readbuf
, writebuf
, 0);
5764 mips_xfer_register (gdbarch
, regcache
,
5765 gdbarch_num_regs (gdbarch
) + 3,
5766 4, gdbarch_byte_order (gdbarch
),
5767 readbuf
, writebuf
, 4);
5769 return RETURN_VALUE_REGISTER_CONVENTION
;
5772 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5773 && TYPE_NFIELDS (type
) <= 2
5774 && TYPE_NFIELDS (type
) >= 1
5775 && ((TYPE_NFIELDS (type
) == 1
5776 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5778 || (TYPE_NFIELDS (type
) == 2
5779 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5781 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5783 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5785 /* A struct that contains one or two floats. Each value is part
5786 in the least significant part of their floating point
5788 gdb_byte reg
[MAX_REGISTER_SIZE
];
5791 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5792 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5794 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5797 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5799 mips_xfer_register (gdbarch
, regcache
,
5800 gdbarch_num_regs (gdbarch
) + regnum
,
5801 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5802 gdbarch_byte_order (gdbarch
),
5803 readbuf
, writebuf
, offset
);
5805 return RETURN_VALUE_REGISTER_CONVENTION
;
5809 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5810 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5812 /* A structure or union. Extract the left justified value,
5813 regardless of the byte order. I.e. DO NOT USE
5817 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5818 offset
< TYPE_LENGTH (type
);
5819 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5821 int xfer
= register_size (gdbarch
, regnum
);
5822 if (offset
+ xfer
> TYPE_LENGTH (type
))
5823 xfer
= TYPE_LENGTH (type
) - offset
;
5825 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5826 offset
, xfer
, regnum
);
5827 mips_xfer_register (gdbarch
, regcache
,
5828 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5829 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5831 return RETURN_VALUE_REGISTER_CONVENTION
;
5836 /* A scalar extract each part but least-significant-byte
5837 justified. o32 thinks registers are 4 byte, regardless of
5841 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5842 offset
< TYPE_LENGTH (type
);
5843 offset
+= MIPS32_REGSIZE
, regnum
++)
5845 int xfer
= MIPS32_REGSIZE
;
5846 if (offset
+ xfer
> TYPE_LENGTH (type
))
5847 xfer
= TYPE_LENGTH (type
) - offset
;
5849 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5850 offset
, xfer
, regnum
);
5851 mips_xfer_register (gdbarch
, regcache
,
5852 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5853 gdbarch_byte_order (gdbarch
),
5854 readbuf
, writebuf
, offset
);
5856 return RETURN_VALUE_REGISTER_CONVENTION
;
5860 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5864 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5865 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5867 struct value
**args
, CORE_ADDR sp
,
5868 int struct_return
, CORE_ADDR struct_addr
)
5874 int stack_offset
= 0;
5875 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5876 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5878 /* For shared libraries, "t9" needs to point at the function
5880 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5882 /* Set the return address register to point to the entry point of
5883 the program, where a breakpoint lies in wait. */
5884 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5886 /* First ensure that the stack and structure return address (if any)
5887 are properly aligned. The stack has to be at least 64-bit
5888 aligned even on 32-bit machines, because doubles must be 64-bit
5889 aligned. For n32 and n64, stack frames need to be 128-bit
5890 aligned, so we round to this widest known alignment. */
5892 sp
= align_down (sp
, 16);
5893 struct_addr
= align_down (struct_addr
, 16);
5895 /* Now make space on the stack for the args. */
5896 for (argnum
= 0; argnum
< nargs
; argnum
++)
5898 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5900 /* Allocate space on the stack. */
5901 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5903 sp
-= align_up (len
, 16);
5906 fprintf_unfiltered (gdb_stdlog
,
5907 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5908 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5910 /* Initialize the integer and float register pointers. */
5911 argreg
= MIPS_A0_REGNUM
;
5912 float_argreg
= mips_fpa0_regnum (gdbarch
);
5914 /* The struct_return pointer occupies the first parameter-passing reg. */
5918 fprintf_unfiltered (gdb_stdlog
,
5919 "mips_o64_push_dummy_call: "
5920 "struct_return reg=%d %s\n",
5921 argreg
, paddress (gdbarch
, struct_addr
));
5922 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5923 stack_offset
+= MIPS64_REGSIZE
;
5926 /* Now load as many as possible of the first arguments into
5927 registers, and push the rest onto the stack. Loop thru args
5928 from first to last. */
5929 for (argnum
= 0; argnum
< nargs
; argnum
++)
5931 const gdb_byte
*val
;
5932 struct value
*arg
= args
[argnum
];
5933 struct type
*arg_type
= check_typedef (value_type (arg
));
5934 int len
= TYPE_LENGTH (arg_type
);
5935 enum type_code typecode
= TYPE_CODE (arg_type
);
5938 fprintf_unfiltered (gdb_stdlog
,
5939 "mips_o64_push_dummy_call: %d len=%d type=%d",
5940 argnum
+ 1, len
, (int) typecode
);
5942 val
= value_contents (arg
);
5944 /* Floating point arguments passed in registers have to be
5945 treated specially. On 32-bit architectures, doubles are
5946 passed in register pairs; the even FP register gets the
5947 low word, and the odd FP register gets the high word.
5948 On O64, the first two floating point arguments are also
5949 copied to general registers, because MIPS16 functions
5950 don't use float registers for arguments. This duplication
5951 of arguments in general registers can't hurt non-MIPS16
5952 functions because those registers are normally skipped. */
5954 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5955 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5957 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5959 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5960 float_argreg
, phex (regval
, len
));
5961 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5963 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5964 argreg
, phex (regval
, len
));
5965 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5967 /* Reserve space for the FP register. */
5968 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5972 /* Copy the argument to general registers or the stack in
5973 register-sized pieces. Large arguments are split between
5974 registers and stack. */
5975 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5976 are treated specially: Irix cc passes them in registers
5977 where gcc sometimes puts them on the stack. For maximum
5978 compatibility, we will put them in both places. */
5979 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5980 && len
% MIPS64_REGSIZE
!= 0);
5983 /* Remember if the argument was written to the stack. */
5984 int stack_used_p
= 0;
5985 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5988 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5991 /* Write this portion of the argument to the stack. */
5992 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5993 || odd_sized_struct
)
5995 /* Should shorter than int integer values be
5996 promoted to int before being stored? */
5997 int longword_offset
= 0;
6000 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6002 if ((typecode
== TYPE_CODE_INT
6003 || typecode
== TYPE_CODE_PTR
6004 || typecode
== TYPE_CODE_FLT
)
6006 longword_offset
= MIPS64_REGSIZE
- len
;
6011 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
6012 paddress (gdbarch
, stack_offset
));
6013 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
6014 paddress (gdbarch
, longword_offset
));
6017 addr
= sp
+ stack_offset
+ longword_offset
;
6022 fprintf_unfiltered (gdb_stdlog
, " @%s ",
6023 paddress (gdbarch
, addr
));
6024 for (i
= 0; i
< partial_len
; i
++)
6026 fprintf_unfiltered (gdb_stdlog
, "%02x",
6030 write_memory (addr
, val
, partial_len
);
6033 /* Note!!! This is NOT an else clause. Odd sized
6034 structs may go thru BOTH paths. */
6035 /* Write this portion of the argument to a general
6036 purpose register. */
6037 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
6039 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6041 /* Value may need to be sign extended, because
6042 mips_isa_regsize() != mips_abi_regsize(). */
6044 /* A non-floating-point argument being passed in a
6045 general register. If a struct or union, and if
6046 the remaining length is smaller than the register
6047 size, we have to adjust the register value on
6050 It does not seem to be necessary to do the
6051 same for integral types. */
6053 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6054 && partial_len
< MIPS64_REGSIZE
6055 && (typecode
== TYPE_CODE_STRUCT
6056 || typecode
== TYPE_CODE_UNION
))
6057 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6061 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
6063 phex (regval
, MIPS64_REGSIZE
));
6064 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6067 /* Prevent subsequent floating point arguments from
6068 being passed in floating point registers. */
6069 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
6075 /* Compute the offset into the stack at which we will
6076 copy the next parameter.
6078 In older ABIs, the caller reserved space for
6079 registers that contained arguments. This was loosely
6080 refered to as their "home". Consequently, space is
6081 always allocated. */
6083 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6087 fprintf_unfiltered (gdb_stdlog
, "\n");
6090 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6092 /* Return adjusted stack pointer. */
6096 static enum return_value_convention
6097 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6098 struct type
*type
, struct regcache
*regcache
,
6099 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6101 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6102 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6103 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6104 enum mips_fval_reg fval_reg
;
6106 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6107 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
6108 || TYPE_CODE (type
) == TYPE_CODE_UNION
6109 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
6110 return RETURN_VALUE_STRUCT_CONVENTION
;
6111 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
6113 /* A floating-point value. If reading in or copying, then we get it
6114 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6115 If writing out only, then we put it to both FP0 and GPR2. We do
6116 not support reading in with no function known, if this safety
6117 check ever triggers, then we'll have to try harder. */
6118 gdb_assert (function
|| !readbuf
);
6123 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6126 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6128 case mips_fval_both
:
6129 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6132 if (fval_reg
!= mips_fval_gpr
)
6133 mips_xfer_register (gdbarch
, regcache
,
6134 (gdbarch_num_regs (gdbarch
)
6135 + mips_regnum (gdbarch
)->fp0
),
6137 gdbarch_byte_order (gdbarch
),
6138 readbuf
, writebuf
, 0);
6139 if (fval_reg
!= mips_fval_fpr
)
6140 mips_xfer_register (gdbarch
, regcache
,
6141 gdbarch_num_regs (gdbarch
) + 2,
6143 gdbarch_byte_order (gdbarch
),
6144 readbuf
, writebuf
, 0);
6145 return RETURN_VALUE_REGISTER_CONVENTION
;
6149 /* A scalar extract each part but least-significant-byte
6153 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6154 offset
< TYPE_LENGTH (type
);
6155 offset
+= MIPS64_REGSIZE
, regnum
++)
6157 int xfer
= MIPS64_REGSIZE
;
6158 if (offset
+ xfer
> TYPE_LENGTH (type
))
6159 xfer
= TYPE_LENGTH (type
) - offset
;
6161 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6162 offset
, xfer
, regnum
);
6163 mips_xfer_register (gdbarch
, regcache
,
6164 gdbarch_num_regs (gdbarch
) + regnum
,
6165 xfer
, gdbarch_byte_order (gdbarch
),
6166 readbuf
, writebuf
, offset
);
6168 return RETURN_VALUE_REGISTER_CONVENTION
;
6172 /* Floating point register management.
6174 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6175 64bit operations, these early MIPS cpus treat fp register pairs
6176 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6177 registers and offer a compatibility mode that emulates the MIPS2 fp
6178 model. When operating in MIPS2 fp compat mode, later cpu's split
6179 double precision floats into two 32-bit chunks and store them in
6180 consecutive fp regs. To display 64-bit floats stored in this
6181 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6182 Throw in user-configurable endianness and you have a real mess.
6184 The way this works is:
6185 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6186 double-precision value will be split across two logical registers.
6187 The lower-numbered logical register will hold the low-order bits,
6188 regardless of the processor's endianness.
6189 - If we are on a 64-bit processor, and we are looking for a
6190 single-precision value, it will be in the low ordered bits
6191 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6192 save slot in memory.
6193 - If we are in 64-bit mode, everything is straightforward.
6195 Note that this code only deals with "live" registers at the top of the
6196 stack. We will attempt to deal with saved registers later, when
6197 the raw/cooked register interface is in place. (We need a general
6198 interface that can deal with dynamic saved register sizes -- fp
6199 regs could be 32 bits wide in one frame and 64 on the frame above
6202 /* Copy a 32-bit single-precision value from the current frame
6203 into rare_buffer. */
6206 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6207 gdb_byte
*rare_buffer
)
6209 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6210 int raw_size
= register_size (gdbarch
, regno
);
6211 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6213 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6214 error (_("can't read register %d (%s)"),
6215 regno
, gdbarch_register_name (gdbarch
, regno
));
6218 /* We have a 64-bit value for this register. Find the low-order
6222 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6227 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6231 memcpy (rare_buffer
, raw_buffer
, 4);
6235 /* Copy a 64-bit double-precision value from the current frame into
6236 rare_buffer. This may include getting half of it from the next
6240 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6241 gdb_byte
*rare_buffer
)
6243 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6244 int raw_size
= register_size (gdbarch
, regno
);
6246 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6248 /* We have a 64-bit value for this register, and we should use
6250 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6251 error (_("can't read register %d (%s)"),
6252 regno
, gdbarch_register_name (gdbarch
, regno
));
6256 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6258 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6259 internal_error (__FILE__
, __LINE__
,
6260 _("mips_read_fp_register_double: bad access to "
6261 "odd-numbered FP register"));
6263 /* mips_read_fp_register_single will find the correct 32 bits from
6265 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6267 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6268 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6272 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6273 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6279 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6281 { /* Do values for FP (float) regs. */
6282 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6283 gdb_byte
*raw_buffer
;
6284 double doub
, flt1
; /* Doubles extracted from raw hex data. */
6289 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6291 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6292 fprintf_filtered (file
, "%*s",
6293 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6296 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6298 struct value_print_options opts
;
6300 /* 4-byte registers: Print hex and floating. Also print even
6301 numbered registers as doubles. */
6302 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6303 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6306 get_formatted_print_options (&opts
, 'x');
6307 print_scalar_formatted (raw_buffer
,
6308 builtin_type (gdbarch
)->builtin_uint32
,
6311 fprintf_filtered (file
, " flt: ");
6313 fprintf_filtered (file
, " <invalid float> ");
6315 fprintf_filtered (file
, "%-17.9g", flt1
);
6317 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6319 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6320 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6323 fprintf_filtered (file
, " dbl: ");
6325 fprintf_filtered (file
, "<invalid double>");
6327 fprintf_filtered (file
, "%-24.17g", doub
);
6332 struct value_print_options opts
;
6334 /* Eight byte registers: print each one as hex, float and double. */
6335 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6336 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6339 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6340 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6343 get_formatted_print_options (&opts
, 'x');
6344 print_scalar_formatted (raw_buffer
,
6345 builtin_type (gdbarch
)->builtin_uint64
,
6348 fprintf_filtered (file
, " flt: ");
6350 fprintf_filtered (file
, "<invalid float>");
6352 fprintf_filtered (file
, "%-17.9g", flt1
);
6354 fprintf_filtered (file
, " dbl: ");
6356 fprintf_filtered (file
, "<invalid double>");
6358 fprintf_filtered (file
, "%-24.17g", doub
);
6363 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6366 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6367 struct value_print_options opts
;
6370 if (mips_float_register_p (gdbarch
, regnum
))
6372 mips_print_fp_register (file
, frame
, regnum
);
6376 val
= get_frame_register_value (frame
, regnum
);
6378 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6380 /* The problem with printing numeric register names (r26, etc.) is that
6381 the user can't use them on input. Probably the best solution is to
6382 fix it so that either the numeric or the funky (a2, etc.) names
6383 are accepted on input. */
6384 if (regnum
< MIPS_NUMREGS
)
6385 fprintf_filtered (file
, "(r%d): ", regnum
);
6387 fprintf_filtered (file
, ": ");
6389 get_formatted_print_options (&opts
, 'x');
6390 val_print_scalar_formatted (value_type (val
),
6391 value_contents_for_printing (val
),
6392 value_embedded_offset (val
),
6397 /* Print IEEE exception condition bits in FLAGS. */
6400 print_fpu_flags (struct ui_file
*file
, int flags
)
6402 if (flags
& (1 << 0))
6403 fputs_filtered (" inexact", file
);
6404 if (flags
& (1 << 1))
6405 fputs_filtered (" uflow", file
);
6406 if (flags
& (1 << 2))
6407 fputs_filtered (" oflow", file
);
6408 if (flags
& (1 << 3))
6409 fputs_filtered (" div0", file
);
6410 if (flags
& (1 << 4))
6411 fputs_filtered (" inval", file
);
6412 if (flags
& (1 << 5))
6413 fputs_filtered (" unimp", file
);
6414 fputc_filtered ('\n', file
);
6417 /* Print interesting information about the floating point processor
6418 (if present) or emulator. */
6421 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6422 struct frame_info
*frame
, const char *args
)
6424 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6425 enum mips_fpu_type type
= MIPS_FPU_TYPE (gdbarch
);
6429 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6430 type
= MIPS_FPU_NONE
;
6432 fprintf_filtered (file
, "fpu type: %s\n",
6433 type
== MIPS_FPU_DOUBLE
? "double-precision"
6434 : type
== MIPS_FPU_SINGLE
? "single-precision"
6437 if (type
== MIPS_FPU_NONE
)
6440 fprintf_filtered (file
, "reg size: %d bits\n",
6441 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6443 fputs_filtered ("cond :", file
);
6444 if (fcs
& (1 << 23))
6445 fputs_filtered (" 0", file
);
6446 for (i
= 1; i
<= 7; i
++)
6447 if (fcs
& (1 << (24 + i
)))
6448 fprintf_filtered (file
, " %d", i
);
6449 fputc_filtered ('\n', file
);
6451 fputs_filtered ("cause :", file
);
6452 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6453 fputs ("mask :", stdout
);
6454 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6455 fputs ("flags :", stdout
);
6456 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6458 fputs_filtered ("rounding: ", file
);
6461 case 0: fputs_filtered ("nearest\n", file
); break;
6462 case 1: fputs_filtered ("zero\n", file
); break;
6463 case 2: fputs_filtered ("+inf\n", file
); break;
6464 case 3: fputs_filtered ("-inf\n", file
); break;
6467 fputs_filtered ("flush :", file
);
6468 if (fcs
& (1 << 21))
6469 fputs_filtered (" nearest", file
);
6470 if (fcs
& (1 << 22))
6471 fputs_filtered (" override", file
);
6472 if (fcs
& (1 << 24))
6473 fputs_filtered (" zero", file
);
6474 if ((fcs
& (0xb << 21)) == 0)
6475 fputs_filtered (" no", file
);
6476 fputc_filtered ('\n', file
);
6478 fprintf_filtered (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6479 fprintf_filtered (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6480 fputc_filtered ('\n', file
);
6482 default_print_float_info (gdbarch
, file
, frame
, args
);
6485 /* Replacement for generic do_registers_info.
6486 Print regs in pretty columns. */
6489 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6492 fprintf_filtered (file
, " ");
6493 mips_print_fp_register (file
, frame
, regnum
);
6494 fprintf_filtered (file
, "\n");
6499 /* Print a row's worth of GP (int) registers, with name labels above. */
6502 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6505 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6506 /* Do values for GP (int) regs. */
6507 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
6508 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6513 /* For GP registers, we print a separate row of names above the vals. */
6514 for (col
= 0, regnum
= start_regnum
;
6515 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6516 + gdbarch_num_pseudo_regs (gdbarch
);
6519 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6520 continue; /* unused register */
6521 if (mips_float_register_p (gdbarch
, regnum
))
6522 break; /* End the row: reached FP register. */
6523 /* Large registers are handled separately. */
6524 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6527 break; /* End the row before this register. */
6529 /* Print this register on a row by itself. */
6530 mips_print_register (file
, frame
, regnum
);
6531 fprintf_filtered (file
, "\n");
6535 fprintf_filtered (file
, " ");
6536 fprintf_filtered (file
,
6537 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6538 gdbarch_register_name (gdbarch
, regnum
));
6545 /* Print the R0 to R31 names. */
6546 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6547 fprintf_filtered (file
, "\n R%-4d",
6548 start_regnum
% gdbarch_num_regs (gdbarch
));
6550 fprintf_filtered (file
, "\n ");
6552 /* Now print the values in hex, 4 or 8 to the row. */
6553 for (col
= 0, regnum
= start_regnum
;
6554 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6555 + gdbarch_num_pseudo_regs (gdbarch
);
6558 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6559 continue; /* unused register */
6560 if (mips_float_register_p (gdbarch
, regnum
))
6561 break; /* End row: reached FP register. */
6562 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6563 break; /* End row: large register. */
6565 /* OK: get the data in raw format. */
6566 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
6567 error (_("can't read register %d (%s)"),
6568 regnum
, gdbarch_register_name (gdbarch
, regnum
));
6569 /* pad small registers */
6571 byte
< (mips_abi_regsize (gdbarch
)
6572 - register_size (gdbarch
, regnum
)); byte
++)
6573 printf_filtered (" ");
6574 /* Now print the register value in hex, endian order. */
6575 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6577 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6578 byte
< register_size (gdbarch
, regnum
); byte
++)
6579 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6581 for (byte
= register_size (gdbarch
, regnum
) - 1;
6583 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6584 fprintf_filtered (file
, " ");
6587 if (col
> 0) /* ie. if we actually printed anything... */
6588 fprintf_filtered (file
, "\n");
6593 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6596 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6597 struct frame_info
*frame
, int regnum
, int all
)
6599 if (regnum
!= -1) /* Do one specified register. */
6601 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6602 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6603 error (_("Not a valid register for the current processor type"));
6605 mips_print_register (file
, frame
, regnum
);
6606 fprintf_filtered (file
, "\n");
6609 /* Do all (or most) registers. */
6611 regnum
= gdbarch_num_regs (gdbarch
);
6612 while (regnum
< gdbarch_num_regs (gdbarch
)
6613 + gdbarch_num_pseudo_regs (gdbarch
))
6615 if (mips_float_register_p (gdbarch
, regnum
))
6617 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6618 regnum
= print_fp_register_row (file
, frame
, regnum
);
6620 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6623 regnum
= print_gp_register_row (file
, frame
, regnum
);
6629 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6630 struct frame_info
*frame
)
6632 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6633 CORE_ADDR pc
= get_frame_pc (frame
);
6634 struct address_space
*aspace
;
6640 if ((mips_pc_is_mips (pc
)
6641 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6642 || (mips_pc_is_micromips (gdbarch
, pc
)
6643 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6644 || (mips_pc_is_mips16 (gdbarch
, pc
)
6645 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6648 isa
= mips_pc_isa (gdbarch
, pc
);
6649 /* _has_delay_slot above will have validated the read. */
6650 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6651 size
= mips_insn_size (isa
, insn
);
6652 aspace
= get_frame_address_space (frame
);
6653 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6656 /* To skip prologues, I use this predicate. Returns either PC itself
6657 if the code at PC does not look like a function prologue; otherwise
6658 returns an address that (if we're lucky) follows the prologue. If
6659 LENIENT, then we must skip everything which is involved in setting
6660 up the frame (it's OK to skip more, just so long as we don't skip
6661 anything which might clobber the registers which are being saved.
6662 We must skip more in the case where part of the prologue is in the
6663 delay slot of a non-prologue instruction). */
6666 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6669 CORE_ADDR func_addr
;
6671 /* See if we can determine the end of the prologue via the symbol table.
6672 If so, then return either PC, or the PC after the prologue, whichever
6674 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6676 CORE_ADDR post_prologue_pc
6677 = skip_prologue_using_sal (gdbarch
, func_addr
);
6678 if (post_prologue_pc
!= 0)
6679 return max (pc
, post_prologue_pc
);
6682 /* Can't determine prologue from the symbol table, need to examine
6685 /* Find an upper limit on the function prologue using the debug
6686 information. If the debug information could not be used to provide
6687 that bound, then use an arbitrary large number as the upper bound. */
6688 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6690 limit_pc
= pc
+ 100; /* Magic. */
6692 if (mips_pc_is_mips16 (gdbarch
, pc
))
6693 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6694 else if (mips_pc_is_micromips (gdbarch
, pc
))
6695 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6697 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6700 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6701 This is a helper function for mips_stack_frame_destroyed_p. */
6704 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6706 CORE_ADDR func_addr
= 0, func_end
= 0;
6708 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6710 /* The MIPS epilogue is max. 12 bytes long. */
6711 CORE_ADDR addr
= func_end
- 12;
6713 if (addr
< func_addr
+ 4)
6714 addr
= func_addr
+ 4;
6718 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6720 unsigned long high_word
;
6723 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6724 high_word
= (inst
>> 16) & 0xffff;
6726 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6727 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6728 && inst
!= 0x03e00008 /* jr $ra */
6729 && inst
!= 0x00000000) /* nop */
6739 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6740 This is a helper function for mips_stack_frame_destroyed_p. */
6743 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6745 CORE_ADDR func_addr
= 0;
6746 CORE_ADDR func_end
= 0;
6754 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6757 /* The microMIPS epilogue is max. 12 bytes long. */
6758 addr
= func_end
- 12;
6760 if (addr
< func_addr
+ 2)
6761 addr
= func_addr
+ 2;
6765 for (; pc
< func_end
; pc
+= loc
)
6768 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6769 loc
+= MIPS_INSN16_SIZE
;
6770 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6772 /* 48-bit instructions. */
6773 case 3 * MIPS_INSN16_SIZE
:
6774 /* No epilogue instructions in this category. */
6777 /* 32-bit instructions. */
6778 case 2 * MIPS_INSN16_SIZE
:
6780 insn
|= mips_fetch_instruction (gdbarch
,
6781 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6782 loc
+= MIPS_INSN16_SIZE
;
6783 switch (micromips_op (insn
>> 16))
6785 case 0xc: /* ADDIU: bits 001100 */
6786 case 0x17: /* DADDIU: bits 010111 */
6787 sreg
= b0s5_reg (insn
>> 16);
6788 dreg
= b5s5_reg (insn
>> 16);
6789 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6790 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6791 /* (D)ADDIU $sp, imm */
6801 /* 16-bit instructions. */
6802 case MIPS_INSN16_SIZE
:
6803 switch (micromips_op (insn
))
6805 case 0x3: /* MOVE: bits 000011 */
6806 sreg
= b0s5_reg (insn
);
6807 dreg
= b5s5_reg (insn
);
6808 if (sreg
== 0 && dreg
== 0)
6809 /* MOVE $zero, $zero aka NOP */
6813 case 0x11: /* POOL16C: bits 010001 */
6814 if (b5s5_op (insn
) == 0x18
6815 /* JRADDIUSP: bits 010011 11000 */
6816 || (b5s5_op (insn
) == 0xd
6817 /* JRC: bits 010011 01101 */
6818 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6823 case 0x13: /* POOL16D: bits 010011 */
6824 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6825 if ((insn
& 0x1) == 0x1
6826 /* ADDIUSP: bits 010011 1 */
6840 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6841 This is a helper function for mips_stack_frame_destroyed_p. */
6844 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6846 CORE_ADDR func_addr
= 0, func_end
= 0;
6848 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6850 /* The MIPS epilogue is max. 12 bytes long. */
6851 CORE_ADDR addr
= func_end
- 12;
6853 if (addr
< func_addr
+ 4)
6854 addr
= func_addr
+ 4;
6858 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6860 unsigned short inst
;
6862 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6864 if ((inst
& 0xf800) == 0xf000) /* extend */
6867 if (inst
!= 0x6300 /* addiu $sp,offset */
6868 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6869 && inst
!= 0xe820 /* jr $ra */
6870 && inst
!= 0xe8a0 /* jrc $ra */
6871 && inst
!= 0x6500) /* nop */
6881 /* Implement the stack_frame_destroyed_p gdbarch method.
6883 The epilogue is defined here as the area at the end of a function,
6884 after an instruction which destroys the function's stack frame. */
6887 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6889 if (mips_pc_is_mips16 (gdbarch
, pc
))
6890 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6891 else if (mips_pc_is_micromips (gdbarch
, pc
))
6892 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6894 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6897 /* Root of all "set mips "/"show mips " commands. This will eventually be
6898 used for all MIPS-specific commands. */
6901 show_mips_command (char *args
, int from_tty
)
6903 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6907 set_mips_command (char *args
, int from_tty
)
6910 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6911 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6914 /* Commands to show/set the MIPS FPU type. */
6917 show_mipsfpu_command (char *args
, int from_tty
)
6921 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6924 ("The MIPS floating-point coprocessor is unknown "
6925 "because the current architecture is not MIPS.\n");
6929 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6931 case MIPS_FPU_SINGLE
:
6932 fpu
= "single-precision";
6934 case MIPS_FPU_DOUBLE
:
6935 fpu
= "double-precision";
6938 fpu
= "absent (none)";
6941 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6943 if (mips_fpu_type_auto
)
6944 printf_unfiltered ("The MIPS floating-point coprocessor "
6945 "is set automatically (currently %s)\n",
6949 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6954 set_mipsfpu_command (char *args
, int from_tty
)
6956 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6957 "\"single\",\"none\" or \"auto\".\n");
6958 show_mipsfpu_command (args
, from_tty
);
6962 set_mipsfpu_single_command (char *args
, int from_tty
)
6964 struct gdbarch_info info
;
6965 gdbarch_info_init (&info
);
6966 mips_fpu_type
= MIPS_FPU_SINGLE
;
6967 mips_fpu_type_auto
= 0;
6968 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6969 instead of relying on globals. Doing that would let generic code
6970 handle the search for this specific architecture. */
6971 if (!gdbarch_update_p (info
))
6972 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6976 set_mipsfpu_double_command (char *args
, int from_tty
)
6978 struct gdbarch_info info
;
6979 gdbarch_info_init (&info
);
6980 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6981 mips_fpu_type_auto
= 0;
6982 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6983 instead of relying on globals. Doing that would let generic code
6984 handle the search for this specific architecture. */
6985 if (!gdbarch_update_p (info
))
6986 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6990 set_mipsfpu_none_command (char *args
, int from_tty
)
6992 struct gdbarch_info info
;
6993 gdbarch_info_init (&info
);
6994 mips_fpu_type
= MIPS_FPU_NONE
;
6995 mips_fpu_type_auto
= 0;
6996 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6997 instead of relying on globals. Doing that would let generic code
6998 handle the search for this specific architecture. */
6999 if (!gdbarch_update_p (info
))
7000 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
7004 set_mipsfpu_auto_command (char *args
, int from_tty
)
7006 mips_fpu_type_auto
= 1;
7009 /* Attempt to identify the particular processor model by reading the
7010 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
7011 the relevant processor still exists (it dates back to '94) and
7012 secondly this is not the way to do this. The processor type should
7013 be set by forcing an architecture change. */
7016 deprecated_mips_set_processor_regs_hack (void)
7018 struct regcache
*regcache
= get_current_regcache ();
7019 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
7020 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7023 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
7024 if ((prid
& ~0xf) == 0x700)
7025 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
7028 /* Just like reinit_frame_cache, but with the right arguments to be
7029 callable as an sfunc. */
7032 reinit_frame_cache_sfunc (char *args
, int from_tty
,
7033 struct cmd_list_element
*c
)
7035 reinit_frame_cache ();
7039 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
7041 struct gdbarch
*gdbarch
= (struct gdbarch
*) info
->application_data
;
7043 /* FIXME: cagney/2003-06-26: Is this even necessary? The
7044 disassembler needs to be able to locally determine the ISA, and
7045 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
7047 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
7048 info
->mach
= bfd_mach_mips16
;
7049 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
7050 info
->mach
= bfd_mach_mips_micromips
;
7052 /* Round down the instruction address to the appropriate boundary. */
7053 memaddr
&= (info
->mach
== bfd_mach_mips16
7054 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7056 /* Set the disassembler options. */
7057 if (!info
->disassembler_options
)
7058 /* This string is not recognized explicitly by the disassembler,
7059 but it tells the disassembler to not try to guess the ABI from
7060 the bfd elf headers, such that, if the user overrides the ABI
7061 of a program linked as NewABI, the disassembly will follow the
7062 register naming conventions specified by the user. */
7063 info
->disassembler_options
= "gpr-names=32";
7065 /* Call the appropriate disassembler based on the target endian-ness. */
7066 if (info
->endian
== BFD_ENDIAN_BIG
)
7067 return print_insn_big_mips (memaddr
, info
);
7069 return print_insn_little_mips (memaddr
, info
);
7073 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
7075 /* Set up the disassembler info, so that we get the right
7076 register names from libopcodes. */
7077 info
->disassembler_options
= "gpr-names=n32";
7078 info
->flavour
= bfd_target_elf_flavour
;
7080 return gdb_print_insn_mips (memaddr
, info
);
7084 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
7086 /* Set up the disassembler info, so that we get the right
7087 register names from libopcodes. */
7088 info
->disassembler_options
= "gpr-names=64";
7089 info
->flavour
= bfd_target_elf_flavour
;
7091 return gdb_print_insn_mips (memaddr
, info
);
7094 /* This function implements gdbarch_breakpoint_from_pc. It uses the
7095 program counter value to determine whether a 16- or 32-bit breakpoint
7096 should be used. It returns a pointer to a string of bytes that encode a
7097 breakpoint instruction, stores the length of the string to *lenptr, and
7098 adjusts pc (if necessary) to point to the actual memory location where
7099 the breakpoint should be inserted. */
7101 static const gdb_byte
*
7102 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
7103 CORE_ADDR
*pcptr
, int *lenptr
)
7105 CORE_ADDR pc
= *pcptr
;
7107 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
7109 if (mips_pc_is_mips16 (gdbarch
, pc
))
7111 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7112 *pcptr
= unmake_compact_addr (pc
);
7113 *lenptr
= sizeof (mips16_big_breakpoint
);
7114 return mips16_big_breakpoint
;
7116 else if (mips_pc_is_micromips (gdbarch
, pc
))
7118 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7119 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7124 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &err
);
7126 ? 2 : (mips_insn_size (ISA_MICROMIPS
, insn
) == 2
7128 *pcptr
= unmake_compact_addr (pc
);
7130 return (size
== 2) ? micromips16_big_breakpoint
7131 : micromips32_big_breakpoint
;
7135 /* The IDT board uses an unusual breakpoint value, and
7136 sometimes gets confused when it sees the usual MIPS
7137 breakpoint instruction. */
7138 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7139 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
7140 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
7141 /* Likewise, IRIX appears to expect a different breakpoint,
7142 although this is not apparent until you try to use pthreads. */
7143 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
7145 *lenptr
= sizeof (big_breakpoint
);
7147 if (strcmp (target_shortname
, "mips") == 0)
7148 return idt_big_breakpoint
;
7149 else if (strcmp (target_shortname
, "ddb") == 0
7150 || strcmp (target_shortname
, "pmon") == 0
7151 || strcmp (target_shortname
, "lsi") == 0)
7152 return pmon_big_breakpoint
;
7153 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
7154 return irix_big_breakpoint
;
7156 return big_breakpoint
;
7161 if (mips_pc_is_mips16 (gdbarch
, pc
))
7163 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7164 *pcptr
= unmake_compact_addr (pc
);
7165 *lenptr
= sizeof (mips16_little_breakpoint
);
7166 return mips16_little_breakpoint
;
7168 else if (mips_pc_is_micromips (gdbarch
, pc
))
7170 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7171 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7176 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &err
);
7178 ? 2 : (mips_insn_size (ISA_MICROMIPS
, insn
) == 2
7180 *pcptr
= unmake_compact_addr (pc
);
7182 return (size
== 2) ? micromips16_little_breakpoint
7183 : micromips32_little_breakpoint
;
7187 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7188 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
7189 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
7191 *lenptr
= sizeof (little_breakpoint
);
7193 if (strcmp (target_shortname
, "mips") == 0)
7194 return idt_little_breakpoint
;
7195 else if (strcmp (target_shortname
, "ddb") == 0
7196 || strcmp (target_shortname
, "pmon") == 0
7197 || strcmp (target_shortname
, "lsi") == 0)
7198 return pmon_little_breakpoint
;
7200 return little_breakpoint
;
7205 /* Determine the remote breakpoint kind suitable for the PC. The following
7208 * 2 -- 16-bit MIPS16 mode breakpoint,
7210 * 3 -- 16-bit microMIPS mode breakpoint,
7212 * 4 -- 32-bit standard MIPS mode breakpoint,
7214 * 5 -- 32-bit microMIPS mode breakpoint. */
7217 mips_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
7220 CORE_ADDR pc
= *pcptr
;
7222 if (mips_pc_is_mips16 (gdbarch
, pc
))
7224 *pcptr
= unmake_compact_addr (pc
);
7227 else if (mips_pc_is_micromips (gdbarch
, pc
))
7233 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7234 size
= status
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
7235 *pcptr
= unmake_compact_addr (pc
);
7236 *kindptr
= size
| 1;
7242 /* Return non-zero if the standard MIPS instruction INST has a branch
7243 delay slot (i.e. it is a jump or branch instruction). This function
7244 is based on mips32_next_pc. */
7247 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7253 op
= itype_op (inst
);
7254 if ((inst
& 0xe0000000) != 0)
7256 rs
= itype_rs (inst
);
7257 rt
= itype_rt (inst
);
7258 return (is_octeon_bbit_op (op
, gdbarch
)
7259 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7260 || op
== 29 /* JALX: bits 011101 */
7263 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7264 || (rs
== 9 && (rt
& 0x2) == 0)
7265 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7266 || (rs
== 10 && (rt
& 0x2) == 0))));
7267 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7270 switch (op
& 0x07) /* extract bits 28,27,26 */
7272 case 0: /* SPECIAL */
7273 op
= rtype_funct (inst
);
7274 return (op
== 8 /* JR */
7275 || op
== 9); /* JALR */
7276 break; /* end SPECIAL */
7277 case 1: /* REGIMM */
7278 rs
= itype_rs (inst
);
7279 rt
= itype_rt (inst
); /* branch condition */
7280 return ((rt
& 0xc) == 0
7281 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7282 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7283 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7284 /* BPOSGE32, BPOSGE64: bits 1110x */
7285 break; /* end REGIMM */
7286 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7292 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7293 delay slot (i.e. it is a jump or branch instruction). */
7296 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7301 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7305 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7308 /* Return non-zero if the microMIPS instruction INSN, comprising the
7309 16-bit major opcode word in the high 16 bits and any second word
7310 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7311 jump or branch instruction). The instruction must be 32-bit if
7312 MUSTBE32 is set or can be any instruction otherwise. */
7315 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7317 ULONGEST major
= insn
>> 16;
7319 switch (micromips_op (major
))
7321 /* 16-bit instructions. */
7322 case 0x33: /* B16: bits 110011 */
7323 case 0x2b: /* BNEZ16: bits 101011 */
7324 case 0x23: /* BEQZ16: bits 100011 */
7326 case 0x11: /* POOL16C: bits 010001 */
7328 && ((b5s5_op (major
) == 0xc
7329 /* JR16: bits 010001 01100 */
7330 || (b5s5_op (major
) & 0x1e) == 0xe)));
7331 /* JALR16, JALRS16: bits 010001 0111x */
7332 /* 32-bit instructions. */
7333 case 0x3d: /* JAL: bits 111101 */
7334 case 0x3c: /* JALX: bits 111100 */
7335 case 0x35: /* J: bits 110101 */
7336 case 0x2d: /* BNE: bits 101101 */
7337 case 0x25: /* BEQ: bits 100101 */
7338 case 0x1d: /* JALS: bits 011101 */
7340 case 0x10: /* POOL32I: bits 010000 */
7341 return ((b5s5_op (major
) & 0x1c) == 0x0
7342 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7343 || (b5s5_op (major
) & 0x1d) == 0x4
7344 /* BLEZ, BGTZ: bits 010000 001x0 */
7345 || (b5s5_op (major
) & 0x1d) == 0x11
7346 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7347 || ((b5s5_op (major
) & 0x1e) == 0x14
7348 && (major
& 0x3) == 0x0)
7349 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7350 || (b5s5_op (major
) & 0x1e) == 0x1a
7351 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7352 || ((b5s5_op (major
) & 0x1e) == 0x1c
7353 && (major
& 0x3) == 0x0)
7354 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7355 || ((b5s5_op (major
) & 0x1c) == 0x1c
7356 && (major
& 0x3) == 0x1));
7357 /* BC1ANY*: bits 010000 111xx xxx01 */
7358 case 0x0: /* POOL32A: bits 000000 */
7359 return (b0s6_op (insn
) == 0x3c
7360 /* POOL32Axf: bits 000000 ... 111100 */
7361 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7362 /* JALR, JALR.HB: 000000 000x111100 111100 */
7363 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7369 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7370 slot (i.e. it is a non-compact jump instruction). The instruction
7371 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7374 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7375 CORE_ADDR addr
, int mustbe32
)
7380 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7384 if (mips_insn_size (ISA_MICROMIPS
, insn
) == 2 * MIPS_INSN16_SIZE
)
7386 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7391 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7394 /* Return non-zero if the MIPS16 instruction INST, which must be
7395 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7396 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7397 instruction). This function is based on mips16_next_pc. */
7400 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7402 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7404 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7407 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7408 slot (i.e. it is a non-compact jump instruction). The instruction
7409 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7412 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7413 CORE_ADDR addr
, int mustbe32
)
7415 unsigned short insn
;
7418 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7422 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7425 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7426 This assumes KSSEG exists. */
7429 mips_segment_boundary (CORE_ADDR bpaddr
)
7431 CORE_ADDR mask
= CORE_ADDR_MAX
;
7434 if (sizeof (CORE_ADDR
) == 8)
7435 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7436 a compiler warning produced where CORE_ADDR is a 32-bit type even
7437 though in that case this is dead code). */
7438 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7441 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7442 segsize
= 29; /* 32-bit compatibility segment */
7444 segsize
= 62; /* xkseg */
7446 case 2: /* xkphys */
7449 default: /* xksseg (1), xkuseg/kuseg (0) */
7453 else if (bpaddr
& 0x80000000) /* kernel segment */
7456 segsize
= 31; /* user segment */
7458 return bpaddr
& mask
;
7461 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7462 it backwards if necessary. Return the address of the new location. */
7465 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7467 CORE_ADDR prev_addr
;
7469 CORE_ADDR func_addr
;
7471 /* If a breakpoint is set on the instruction in a branch delay slot,
7472 GDB gets confused. When the breakpoint is hit, the PC isn't on
7473 the instruction in the branch delay slot, the PC will point to
7474 the branch instruction. Since the PC doesn't match any known
7475 breakpoints, GDB reports a trap exception.
7477 There are two possible fixes for this problem.
7479 1) When the breakpoint gets hit, see if the BD bit is set in the
7480 Cause register (which indicates the last exception occurred in a
7481 branch delay slot). If the BD bit is set, fix the PC to point to
7482 the instruction in the branch delay slot.
7484 2) When the user sets the breakpoint, don't allow him to set the
7485 breakpoint on the instruction in the branch delay slot. Instead
7486 move the breakpoint to the branch instruction (which will have
7489 The problem with the first solution is that if the user then
7490 single-steps the processor, the branch instruction will get
7491 skipped (since GDB thinks the PC is on the instruction in the
7494 So, we'll use the second solution. To do this we need to know if
7495 the instruction we're trying to set the breakpoint on is in the
7496 branch delay slot. */
7498 boundary
= mips_segment_boundary (bpaddr
);
7500 /* Make sure we don't scan back before the beginning of the current
7501 function, since we may fetch constant data or insns that look like
7502 a jump. Of course we might do that anyway if the compiler has
7503 moved constants inline. :-( */
7504 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7505 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7506 boundary
= func_addr
;
7508 if (mips_pc_is_mips (bpaddr
))
7510 if (bpaddr
== boundary
)
7513 /* If the previous instruction has a branch delay slot, we have
7514 to move the breakpoint to the branch instruction. */
7515 prev_addr
= bpaddr
- 4;
7516 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7521 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7522 CORE_ADDR addr
, jmpaddr
;
7525 boundary
= unmake_compact_addr (boundary
);
7527 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7528 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7529 so try for that first, then try the 2 byte JALR/JR.
7530 The microMIPS ASE has a whole range of jumps and branches
7531 with delay slots, some of which take 4 bytes and some take
7532 2 bytes, so the idea is the same.
7533 FIXME: We have to assume that bpaddr is not the second half
7534 of an extended instruction. */
7535 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7536 ? micromips_insn_at_pc_has_delay_slot
7537 : mips16_insn_at_pc_has_delay_slot
);
7541 for (i
= 1; i
< 4; i
++)
7543 if (unmake_compact_addr (addr
) == boundary
)
7545 addr
-= MIPS_INSN16_SIZE
;
7546 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7547 /* Looks like a JR/JALR at [target-1], but it could be
7548 the second word of a previous JAL/JALX, so record it
7549 and check back one more. */
7551 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7554 /* Looks like a JAL/JALX at [target-2], but it could also
7555 be the second word of a previous JAL/JALX, record it,
7556 and check back one more. */
7559 /* Looks like a JAL/JALX at [target-3], so any previously
7560 recorded JAL/JALX or JR/JALR must be wrong, because:
7563 -2: JAL-ext (can't be JAL/JALX)
7564 -1: bdslot (can't be JR/JALR)
7567 Of course it could be another JAL-ext which looks
7568 like a JAL, but in that case we'd have broken out
7569 of this loop at [target-2]:
7573 -2: bdslot (can't be jmp)
7580 /* Not a jump instruction: if we're at [target-1] this
7581 could be the second word of a JAL/JALX, so continue;
7582 otherwise we're done. */
7595 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7596 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7599 mips_is_stub_suffix (const char *suffix
, int zero
)
7604 return zero
&& suffix
[1] == '\0';
7606 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7611 return suffix
[1] == '\0';
7617 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7618 call stubs, one of sf, df, sc, or dc. */
7621 mips_is_stub_mode (const char *mode
)
7623 return ((mode
[0] == 's' || mode
[0] == 'd')
7624 && (mode
[1] == 'f' || mode
[1] == 'c'));
7627 /* Code at PC is a compiler-generated stub. Such a stub for a function
7628 bar might have a name like __fn_stub_bar, and might look like this:
7635 followed by (or interspersed with):
7642 addiu $25, $25, %lo(bar)
7645 ($1 may be used in old code; for robustness we accept any register)
7648 lui $28, %hi(_gp_disp)
7649 addiu $28, $28, %lo(_gp_disp)
7652 addiu $25, $25, %lo(bar)
7655 In the case of a __call_stub_bar stub, the sequence to set up
7656 arguments might look like this:
7663 followed by (or interspersed with) one of the jump sequences above.
7665 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7666 of J or JR, respectively, followed by:
7672 We are at the beginning of the stub here, and scan down and extract
7673 the target address from the jump immediate instruction or, if a jump
7674 register instruction is used, from the register referred. Return
7675 the value of PC calculated or 0 if inconclusive.
7677 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7680 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7682 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7683 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7684 int addrreg
= MIPS_ZERO_REGNUM
;
7685 CORE_ADDR start_pc
= pc
;
7686 CORE_ADDR target_pc
= 0;
7693 status
== 0 && target_pc
== 0 && i
< 20;
7694 i
++, pc
+= MIPS_INSN32_SIZE
)
7696 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7702 switch (itype_op (inst
))
7704 case 0: /* SPECIAL */
7705 switch (rtype_funct (inst
))
7709 rs
= rtype_rs (inst
);
7710 if (rs
== MIPS_GP_REGNUM
)
7711 target_pc
= gp
; /* Hmm... */
7712 else if (rs
== addrreg
)
7716 case 0x21: /* ADDU */
7717 rt
= rtype_rt (inst
);
7718 rs
= rtype_rs (inst
);
7719 rd
= rtype_rd (inst
);
7720 if (rd
== MIPS_GP_REGNUM
7721 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7722 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7730 target_pc
= jtype_target (inst
) << 2;
7731 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7735 rt
= itype_rt (inst
);
7736 rs
= itype_rs (inst
);
7739 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7740 if (rt
== MIPS_GP_REGNUM
)
7742 else if (rt
== addrreg
)
7748 rt
= itype_rt (inst
);
7749 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7750 if (rt
== MIPS_GP_REGNUM
)
7752 else if (rt
!= MIPS_ZERO_REGNUM
)
7760 rt
= itype_rt (inst
);
7761 rs
= itype_rs (inst
);
7762 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7763 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7767 memset (buf
, 0, sizeof (buf
));
7768 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7770 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7779 /* If PC is in a MIPS16 call or return stub, return the address of the
7780 target PC, which is either the callee or the caller. There are several
7781 cases which must be handled:
7783 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7784 and the target PC is in $31 ($ra).
7785 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7786 and the target PC is in $2.
7787 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7788 i.e. before the JALR instruction, this is effectively a call stub
7789 and the target PC is in $2. Otherwise this is effectively
7790 a return stub and the target PC is in $18.
7791 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7792 JAL or JALR instruction, this is effectively a call stub and the
7793 target PC is buried in the instruction stream. Otherwise this
7794 is effectively a return stub and the target PC is in $18.
7795 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7796 stub and the target PC is buried in the instruction stream.
7798 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7799 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7803 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7805 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7806 CORE_ADDR start_addr
;
7810 /* Find the starting address and name of the function containing the PC. */
7811 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7814 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7815 and the target PC is in $31 ($ra). */
7816 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7817 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7818 && mips_is_stub_mode (name
+ prefixlen
)
7819 && name
[prefixlen
+ 2] == '\0')
7820 return get_frame_register_signed
7821 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7823 /* If the PC is in __mips16_call_stub_*, this is one of the call
7824 call/return stubs. */
7825 prefixlen
= strlen (mips_str_mips16_call_stub
);
7826 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7828 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7829 and the target PC is in $2. */
7830 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7831 return get_frame_register_signed
7832 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7834 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7835 i.e. before the JALR instruction, this is effectively a call stub
7836 and the target PC is in $2. Otherwise this is effectively
7837 a return stub and the target PC is in $18. */
7838 else if (mips_is_stub_mode (name
+ prefixlen
)
7839 && name
[prefixlen
+ 2] == '_'
7840 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7842 if (pc
== start_addr
)
7843 /* This is the 'call' part of a call stub. The return
7844 address is in $2. */
7845 return get_frame_register_signed
7846 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7848 /* This is the 'return' part of a call stub. The return
7849 address is in $18. */
7850 return get_frame_register_signed
7851 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7854 return 0; /* Not a stub. */
7857 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7858 compiler-generated call or call/return stubs. */
7859 if (startswith (name
, mips_str_fn_stub
)
7860 || startswith (name
, mips_str_call_stub
))
7862 if (pc
== start_addr
)
7863 /* This is the 'call' part of a call stub. Call this helper
7864 to scan through this code for interesting instructions
7865 and determine the final PC. */
7866 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7868 /* This is the 'return' part of a call stub. The return address
7870 return get_frame_register_signed
7871 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7874 return 0; /* Not a stub. */
7877 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7878 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7881 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7883 CORE_ADDR start_addr
;
7886 /* Find the starting address of the function containing the PC. */
7887 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7890 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7891 the start, i.e. after the JALR instruction, this is effectively
7893 prefixlen
= strlen (mips_str_mips16_call_stub
);
7894 if (pc
!= start_addr
7895 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7896 && mips_is_stub_mode (name
+ prefixlen
)
7897 && name
[prefixlen
+ 2] == '_'
7898 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7901 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7902 the JAL or JALR instruction, this is effectively a return stub. */
7903 prefixlen
= strlen (mips_str_call_fp_stub
);
7904 if (pc
!= start_addr
7905 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7908 /* Consume the .pic. prefix of any PIC stub, this function must return
7909 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7910 or the call stub path will trigger in handle_inferior_event causing
7912 prefixlen
= strlen (mips_str_pic
);
7913 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7916 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7917 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7918 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7919 && mips_is_stub_mode (name
+ prefixlen
)
7920 && name
[prefixlen
+ 2] == '\0')
7923 return 0; /* Not a stub. */
7926 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7927 PC of the stub target. The stub just loads $t9 and jumps to it,
7928 so that $t9 has the correct value at function entry. */
7931 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7933 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7934 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7935 struct bound_minimal_symbol msym
;
7937 gdb_byte stub_code
[16];
7938 int32_t stub_words
[4];
7940 /* The stub for foo is named ".pic.foo", and is either two
7941 instructions inserted before foo or a three instruction sequence
7942 which jumps to foo. */
7943 msym
= lookup_minimal_symbol_by_pc (pc
);
7944 if (msym
.minsym
== NULL
7945 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7946 || MSYMBOL_LINKAGE_NAME (msym
.minsym
) == NULL
7947 || !startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
7950 /* A two-instruction header. */
7951 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7954 /* A three-instruction (plus delay slot) trampoline. */
7955 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7957 if (target_read_memory (pc
, stub_code
, 16) != 0)
7959 for (i
= 0; i
< 4; i
++)
7960 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7963 /* A stub contains these instructions:
7966 addiu t9, t9, %lo(target)
7969 This works even for N64, since stubs are only generated with
7971 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7972 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7973 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7974 && stub_words
[3] == 0x00000000)
7975 return ((((stub_words
[0] & 0x0000ffff) << 16)
7976 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7979 /* Not a recognized stub. */
7984 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7986 CORE_ADDR requested_pc
= pc
;
7987 CORE_ADDR target_pc
;
7994 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7998 new_pc
= find_solib_trampoline_target (frame
, pc
);
8002 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
8006 while (pc
!= target_pc
);
8008 return pc
!= requested_pc
? pc
: 0;
8011 /* Convert a dbx stab register number (from `r' declaration) to a GDB
8012 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
8015 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
8018 if (num
>= 0 && num
< 32)
8020 else if (num
>= 38 && num
< 70)
8021 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
8023 regnum
= mips_regnum (gdbarch
)->hi
;
8025 regnum
= mips_regnum (gdbarch
)->lo
;
8026 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
8027 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
8030 return gdbarch_num_regs (gdbarch
) + regnum
;
8034 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
8035 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
8038 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
8041 if (num
>= 0 && num
< 32)
8043 else if (num
>= 32 && num
< 64)
8044 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
8046 regnum
= mips_regnum (gdbarch
)->hi
;
8048 regnum
= mips_regnum (gdbarch
)->lo
;
8049 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
8050 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
8053 return gdbarch_num_regs (gdbarch
) + regnum
;
8057 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
8059 /* Only makes sense to supply raw registers. */
8060 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
8061 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
8062 decide if it is valid. Should instead define a standard sim/gdb
8063 register numbering scheme. */
8064 if (gdbarch_register_name (gdbarch
,
8065 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
8066 && gdbarch_register_name (gdbarch
,
8067 gdbarch_num_regs (gdbarch
)
8068 + regnum
)[0] != '\0')
8071 return LEGACY_SIM_REGNO_IGNORE
;
8075 /* Convert an integer into an address. Extracting the value signed
8076 guarantees a correctly sign extended address. */
8079 mips_integer_to_address (struct gdbarch
*gdbarch
,
8080 struct type
*type
, const gdb_byte
*buf
)
8082 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8083 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
8086 /* Dummy virtual frame pointer method. This is no more or less accurate
8087 than most other architectures; we just need to be explicit about it,
8088 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
8089 an assertion failure. */
8092 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
8093 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
8095 *reg
= MIPS_SP_REGNUM
;
8100 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
8102 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
8103 const char *name
= bfd_get_section_name (abfd
, sect
);
8105 if (*abip
!= MIPS_ABI_UNKNOWN
)
8108 if (!startswith (name
, ".mdebug."))
8111 if (strcmp (name
, ".mdebug.abi32") == 0)
8112 *abip
= MIPS_ABI_O32
;
8113 else if (strcmp (name
, ".mdebug.abiN32") == 0)
8114 *abip
= MIPS_ABI_N32
;
8115 else if (strcmp (name
, ".mdebug.abi64") == 0)
8116 *abip
= MIPS_ABI_N64
;
8117 else if (strcmp (name
, ".mdebug.abiO64") == 0)
8118 *abip
= MIPS_ABI_O64
;
8119 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8120 *abip
= MIPS_ABI_EABI32
;
8121 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8122 *abip
= MIPS_ABI_EABI64
;
8124 warning (_("unsupported ABI %s."), name
+ 8);
8128 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8130 int *lbp
= (int *) obj
;
8131 const char *name
= bfd_get_section_name (abfd
, sect
);
8133 if (startswith (name
, ".gcc_compiled_long32"))
8135 else if (startswith (name
, ".gcc_compiled_long64"))
8137 else if (startswith (name
, ".gcc_compiled_long"))
8138 warning (_("unrecognized .gcc_compiled_longXX"));
8141 static enum mips_abi
8142 global_mips_abi (void)
8146 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8147 if (mips_abi_strings
[i
] == mips_abi_string
)
8148 return (enum mips_abi
) i
;
8150 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8153 /* Return the default compressed instruction set, either of MIPS16
8154 or microMIPS, selected when none could have been determined from
8155 the ELF header of the binary being executed (or no binary has been
8158 static enum mips_isa
8159 global_mips_compression (void)
8163 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8164 if (mips_compression_strings
[i
] == mips_compression_string
)
8165 return (enum mips_isa
) i
;
8167 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8171 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8173 /* If the size matches the set of 32-bit or 64-bit integer registers,
8174 assume that's what we've got. */
8175 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8176 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8178 /* If the size matches the full set of registers GDB traditionally
8179 knows about, including floating point, for either 32-bit or
8180 64-bit, assume that's what we've got. */
8181 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8182 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8184 /* Otherwise we don't have a useful guess. */
8187 static struct value
*
8188 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8190 const int *reg_p
= (const int *) baton
;
8191 return value_of_register (*reg_p
, frame
);
8194 static struct gdbarch
*
8195 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8197 struct gdbarch
*gdbarch
;
8198 struct gdbarch_tdep
*tdep
;
8200 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8202 enum mips_fpu_type fpu_type
;
8203 struct tdesc_arch_data
*tdesc_data
= NULL
;
8204 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8205 const char **reg_names
;
8206 struct mips_regnum mips_regnum
, *regnum
;
8207 enum mips_isa mips_isa
;
8211 /* Fill in the OS dependent register numbers and names. */
8212 if (info
.osabi
== GDB_OSABI_IRIX
)
8214 mips_regnum
.fp0
= 32;
8215 mips_regnum
.pc
= 64;
8216 mips_regnum
.cause
= 65;
8217 mips_regnum
.badvaddr
= 66;
8218 mips_regnum
.hi
= 67;
8219 mips_regnum
.lo
= 68;
8220 mips_regnum
.fp_control_status
= 69;
8221 mips_regnum
.fp_implementation_revision
= 70;
8222 mips_regnum
.dspacc
= dspacc
= -1;
8223 mips_regnum
.dspctl
= dspctl
= -1;
8225 reg_names
= mips_irix_reg_names
;
8227 else if (info
.osabi
== GDB_OSABI_LINUX
)
8229 mips_regnum
.fp0
= 38;
8230 mips_regnum
.pc
= 37;
8231 mips_regnum
.cause
= 36;
8232 mips_regnum
.badvaddr
= 35;
8233 mips_regnum
.hi
= 34;
8234 mips_regnum
.lo
= 33;
8235 mips_regnum
.fp_control_status
= 70;
8236 mips_regnum
.fp_implementation_revision
= 71;
8237 mips_regnum
.dspacc
= -1;
8238 mips_regnum
.dspctl
= -1;
8242 reg_names
= mips_linux_reg_names
;
8246 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8247 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8248 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8249 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8250 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8251 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8252 mips_regnum
.fp_control_status
= 70;
8253 mips_regnum
.fp_implementation_revision
= 71;
8254 mips_regnum
.dspacc
= dspacc
= -1;
8255 mips_regnum
.dspctl
= dspctl
= -1;
8256 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8257 if (info
.bfd_arch_info
!= NULL
8258 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8259 reg_names
= mips_tx39_reg_names
;
8261 reg_names
= mips_generic_reg_names
;
8264 /* Check any target description for validity. */
8265 if (tdesc_has_registers (info
.target_desc
))
8267 static const char *const mips_gprs
[] = {
8268 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8269 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8270 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8271 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8273 static const char *const mips_fprs
[] = {
8274 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8275 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8276 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8277 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8280 const struct tdesc_feature
*feature
;
8283 feature
= tdesc_find_feature (info
.target_desc
,
8284 "org.gnu.gdb.mips.cpu");
8285 if (feature
== NULL
)
8288 tdesc_data
= tdesc_data_alloc ();
8291 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8292 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
8296 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8297 mips_regnum
.lo
, "lo");
8298 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8299 mips_regnum
.hi
, "hi");
8300 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8301 mips_regnum
.pc
, "pc");
8305 tdesc_data_cleanup (tdesc_data
);
8309 feature
= tdesc_find_feature (info
.target_desc
,
8310 "org.gnu.gdb.mips.cp0");
8311 if (feature
== NULL
)
8313 tdesc_data_cleanup (tdesc_data
);
8318 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8319 mips_regnum
.badvaddr
, "badvaddr");
8320 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8321 MIPS_PS_REGNUM
, "status");
8322 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8323 mips_regnum
.cause
, "cause");
8327 tdesc_data_cleanup (tdesc_data
);
8331 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8332 backend is not prepared for that, though. */
8333 feature
= tdesc_find_feature (info
.target_desc
,
8334 "org.gnu.gdb.mips.fpu");
8335 if (feature
== NULL
)
8337 tdesc_data_cleanup (tdesc_data
);
8342 for (i
= 0; i
< 32; i
++)
8343 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8344 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8346 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8347 mips_regnum
.fp_control_status
,
8350 &= tdesc_numbered_register (feature
, tdesc_data
,
8351 mips_regnum
.fp_implementation_revision
,
8356 tdesc_data_cleanup (tdesc_data
);
8362 feature
= tdesc_find_feature (info
.target_desc
,
8363 "org.gnu.gdb.mips.dsp");
8364 /* The DSP registers are optional; it's OK if they are absent. */
8365 if (feature
!= NULL
)
8369 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8370 dspacc
+ i
++, "hi1");
8371 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8372 dspacc
+ i
++, "lo1");
8373 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8374 dspacc
+ i
++, "hi2");
8375 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8376 dspacc
+ i
++, "lo2");
8377 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8378 dspacc
+ i
++, "hi3");
8379 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8380 dspacc
+ i
++, "lo3");
8382 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8387 tdesc_data_cleanup (tdesc_data
);
8391 mips_regnum
.dspacc
= dspacc
;
8392 mips_regnum
.dspctl
= dspctl
;
8396 /* It would be nice to detect an attempt to use a 64-bit ABI
8397 when only 32-bit registers are provided. */
8401 /* First of all, extract the elf_flags, if available. */
8402 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8403 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8404 else if (arches
!= NULL
)
8405 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8409 fprintf_unfiltered (gdb_stdlog
,
8410 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8412 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8413 switch ((elf_flags
& EF_MIPS_ABI
))
8415 case E_MIPS_ABI_O32
:
8416 found_abi
= MIPS_ABI_O32
;
8418 case E_MIPS_ABI_O64
:
8419 found_abi
= MIPS_ABI_O64
;
8421 case E_MIPS_ABI_EABI32
:
8422 found_abi
= MIPS_ABI_EABI32
;
8424 case E_MIPS_ABI_EABI64
:
8425 found_abi
= MIPS_ABI_EABI64
;
8428 if ((elf_flags
& EF_MIPS_ABI2
))
8429 found_abi
= MIPS_ABI_N32
;
8431 found_abi
= MIPS_ABI_UNKNOWN
;
8435 /* GCC creates a pseudo-section whose name describes the ABI. */
8436 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8437 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8439 /* If we have no useful BFD information, use the ABI from the last
8440 MIPS architecture (if there is one). */
8441 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8442 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8444 /* Try the architecture for any hint of the correct ABI. */
8445 if (found_abi
== MIPS_ABI_UNKNOWN
8446 && info
.bfd_arch_info
!= NULL
8447 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8449 switch (info
.bfd_arch_info
->mach
)
8451 case bfd_mach_mips3900
:
8452 found_abi
= MIPS_ABI_EABI32
;
8454 case bfd_mach_mips4100
:
8455 case bfd_mach_mips5000
:
8456 found_abi
= MIPS_ABI_EABI64
;
8458 case bfd_mach_mips8000
:
8459 case bfd_mach_mips10000
:
8460 /* On Irix, ELF64 executables use the N64 ABI. The
8461 pseudo-sections which describe the ABI aren't present
8462 on IRIX. (Even for executables created by gcc.) */
8463 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8464 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8465 found_abi
= MIPS_ABI_N64
;
8467 found_abi
= MIPS_ABI_N32
;
8472 /* Default 64-bit objects to N64 instead of O32. */
8473 if (found_abi
== MIPS_ABI_UNKNOWN
8474 && info
.abfd
!= NULL
8475 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8476 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8477 found_abi
= MIPS_ABI_N64
;
8480 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8483 /* What has the user specified from the command line? */
8484 wanted_abi
= global_mips_abi ();
8486 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8489 /* Now that we have found what the ABI for this binary would be,
8490 check whether the user is overriding it. */
8491 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8492 mips_abi
= wanted_abi
;
8493 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8494 mips_abi
= found_abi
;
8496 mips_abi
= MIPS_ABI_O32
;
8498 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8501 /* Determine the default compressed ISA. */
8502 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8503 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8504 mips_isa
= ISA_MICROMIPS
;
8505 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8506 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8507 mips_isa
= ISA_MIPS16
;
8509 mips_isa
= global_mips_compression ();
8510 mips_compression_string
= mips_compression_strings
[mips_isa
];
8512 /* Also used when doing an architecture lookup. */
8514 fprintf_unfiltered (gdb_stdlog
,
8515 "mips_gdbarch_init: "
8516 "mips64_transfers_32bit_regs_p = %d\n",
8517 mips64_transfers_32bit_regs_p
);
8519 /* Determine the MIPS FPU type. */
8522 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8523 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8524 Tag_GNU_MIPS_ABI_FP
);
8525 #endif /* HAVE_ELF */
8527 if (!mips_fpu_type_auto
)
8528 fpu_type
= mips_fpu_type
;
8529 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8531 switch (elf_fpu_type
)
8533 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8534 fpu_type
= MIPS_FPU_DOUBLE
;
8536 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8537 fpu_type
= MIPS_FPU_SINGLE
;
8539 case Val_GNU_MIPS_ABI_FP_SOFT
:
8541 /* Soft float or unknown. */
8542 fpu_type
= MIPS_FPU_NONE
;
8546 else if (info
.bfd_arch_info
!= NULL
8547 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8548 switch (info
.bfd_arch_info
->mach
)
8550 case bfd_mach_mips3900
:
8551 case bfd_mach_mips4100
:
8552 case bfd_mach_mips4111
:
8553 case bfd_mach_mips4120
:
8554 fpu_type
= MIPS_FPU_NONE
;
8556 case bfd_mach_mips4650
:
8557 fpu_type
= MIPS_FPU_SINGLE
;
8560 fpu_type
= MIPS_FPU_DOUBLE
;
8563 else if (arches
!= NULL
)
8564 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
8566 fpu_type
= MIPS_FPU_DOUBLE
;
8568 fprintf_unfiltered (gdb_stdlog
,
8569 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8571 /* Check for blatant incompatibilities. */
8573 /* If we have only 32-bit registers, then we can't debug a 64-bit
8575 if (info
.target_desc
8576 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8577 && mips_abi
!= MIPS_ABI_EABI32
8578 && mips_abi
!= MIPS_ABI_O32
)
8580 if (tdesc_data
!= NULL
)
8581 tdesc_data_cleanup (tdesc_data
);
8585 /* Try to find a pre-existing architecture. */
8586 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8588 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8590 /* MIPS needs to be pedantic about which ABI and the compressed
8591 ISA variation the object is using. */
8592 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8594 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8596 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8598 /* Need to be pedantic about which register virtual size is
8600 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8601 != mips64_transfers_32bit_regs_p
)
8603 /* Be pedantic about which FPU is selected. */
8604 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
8607 if (tdesc_data
!= NULL
)
8608 tdesc_data_cleanup (tdesc_data
);
8609 return arches
->gdbarch
;
8612 /* Need a new architecture. Fill in a target specific vector. */
8613 tdep
= XNEW (struct gdbarch_tdep
);
8614 gdbarch
= gdbarch_alloc (&info
, tdep
);
8615 tdep
->elf_flags
= elf_flags
;
8616 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8617 tdep
->found_abi
= found_abi
;
8618 tdep
->mips_abi
= mips_abi
;
8619 tdep
->mips_isa
= mips_isa
;
8620 tdep
->mips_fpu_type
= fpu_type
;
8621 tdep
->register_size_valid_p
= 0;
8622 tdep
->register_size
= 0;
8624 if (info
.target_desc
)
8626 /* Some useful properties can be inferred from the target. */
8627 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8629 tdep
->register_size_valid_p
= 1;
8630 tdep
->register_size
= 4;
8632 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8634 tdep
->register_size_valid_p
= 1;
8635 tdep
->register_size
= 8;
8639 /* Initially set everything according to the default ABI/ISA. */
8640 set_gdbarch_short_bit (gdbarch
, 16);
8641 set_gdbarch_int_bit (gdbarch
, 32);
8642 set_gdbarch_float_bit (gdbarch
, 32);
8643 set_gdbarch_double_bit (gdbarch
, 64);
8644 set_gdbarch_long_double_bit (gdbarch
, 64);
8645 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8646 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8647 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8649 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8650 mips_ax_pseudo_register_collect
);
8651 set_gdbarch_ax_pseudo_register_push_stack
8652 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8654 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8655 mips_elf_make_msymbol_special
);
8656 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8657 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8658 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8660 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8661 *regnum
= mips_regnum
;
8662 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8663 set_gdbarch_num_regs (gdbarch
, num_regs
);
8664 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8665 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8666 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8667 tdep
->mips_processor_reg_names
= reg_names
;
8668 tdep
->regnum
= regnum
;
8673 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8674 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8675 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8676 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8677 tdep
->default_mask_address_p
= 0;
8678 set_gdbarch_long_bit (gdbarch
, 32);
8679 set_gdbarch_ptr_bit (gdbarch
, 32);
8680 set_gdbarch_long_long_bit (gdbarch
, 64);
8683 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8684 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8685 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8686 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8687 tdep
->default_mask_address_p
= 0;
8688 set_gdbarch_long_bit (gdbarch
, 32);
8689 set_gdbarch_ptr_bit (gdbarch
, 32);
8690 set_gdbarch_long_long_bit (gdbarch
, 64);
8692 case MIPS_ABI_EABI32
:
8693 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8694 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8695 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8696 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8697 tdep
->default_mask_address_p
= 0;
8698 set_gdbarch_long_bit (gdbarch
, 32);
8699 set_gdbarch_ptr_bit (gdbarch
, 32);
8700 set_gdbarch_long_long_bit (gdbarch
, 64);
8702 case MIPS_ABI_EABI64
:
8703 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8704 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8705 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8706 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8707 tdep
->default_mask_address_p
= 0;
8708 set_gdbarch_long_bit (gdbarch
, 64);
8709 set_gdbarch_ptr_bit (gdbarch
, 64);
8710 set_gdbarch_long_long_bit (gdbarch
, 64);
8713 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8714 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8715 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8716 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8717 tdep
->default_mask_address_p
= 0;
8718 set_gdbarch_long_bit (gdbarch
, 32);
8719 set_gdbarch_ptr_bit (gdbarch
, 32);
8720 set_gdbarch_long_long_bit (gdbarch
, 64);
8721 set_gdbarch_long_double_bit (gdbarch
, 128);
8722 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8725 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8726 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8727 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8728 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8729 tdep
->default_mask_address_p
= 0;
8730 set_gdbarch_long_bit (gdbarch
, 64);
8731 set_gdbarch_ptr_bit (gdbarch
, 64);
8732 set_gdbarch_long_long_bit (gdbarch
, 64);
8733 set_gdbarch_long_double_bit (gdbarch
, 128);
8734 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8737 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8740 /* GCC creates a pseudo-section whose name specifies the size of
8741 longs, since -mlong32 or -mlong64 may be used independent of
8742 other options. How those options affect pointer sizes is ABI and
8743 architecture dependent, so use them to override the default sizes
8744 set by the ABI. This table shows the relationship between ABI,
8745 -mlongXX, and size of pointers:
8747 ABI -mlongXX ptr bits
8748 --- -------- --------
8762 Note that for o32 and eabi32, pointers are always 32 bits
8763 regardless of any -mlongXX option. For all others, pointers and
8764 longs are the same, as set by -mlongXX or set by defaults. */
8766 if (info
.abfd
!= NULL
)
8770 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8773 set_gdbarch_long_bit (gdbarch
, long_bit
);
8777 case MIPS_ABI_EABI32
:
8782 case MIPS_ABI_EABI64
:
8783 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8786 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8791 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8792 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8795 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8796 flag in object files because to do so would make it impossible to
8797 link with libraries compiled without "-gp32". This is
8798 unnecessarily restrictive.
8800 We could solve this problem by adding "-gp32" multilibs to gcc,
8801 but to set this flag before gcc is built with such multilibs will
8802 break too many systems.''
8804 But even more unhelpfully, the default linker output target for
8805 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8806 for 64-bit programs - you need to change the ABI to change this,
8807 and not all gcc targets support that currently. Therefore using
8808 this flag to detect 32-bit mode would do the wrong thing given
8809 the current gcc - it would make GDB treat these 64-bit programs
8810 as 32-bit programs by default. */
8812 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8813 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8815 /* Add/remove bits from an address. The MIPS needs be careful to
8816 ensure that all 32 bit addresses are sign extended to 64 bits. */
8817 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8819 /* Unwind the frame. */
8820 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8821 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8822 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8824 /* Map debug register numbers onto internal register numbers. */
8825 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8826 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8827 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8828 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8829 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8830 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8832 /* MIPS version of CALL_DUMMY. */
8834 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8835 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8836 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8838 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8840 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8841 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8842 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8844 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8845 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
8846 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
8847 mips_remote_breakpoint_from_pc
);
8848 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8849 mips_adjust_breakpoint_address
);
8851 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8853 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8855 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8856 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8857 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8859 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8861 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8863 if (mips_abi
== MIPS_ABI_N32
)
8864 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8865 else if (mips_abi
== MIPS_ABI_N64
)
8866 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8868 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8870 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8871 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8872 need to all be folded into the target vector. Since they are
8873 being used as guards for target_stopped_by_watchpoint, why not have
8874 target_stopped_by_watchpoint return the type of watchpoint that the code
8876 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8878 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8880 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8881 to support MIPS16. This is a bad thing. Make sure not to do it
8882 if we have an OS ABI that actually supports shared libraries, since
8883 shared library support is more important. If we have an OS someday
8884 that supports both shared libraries and MIPS16, we'll have to find
8885 a better place for these.
8886 macro/2012-04-25: But that applies to return trampolines only and
8887 currently no MIPS OS ABI uses shared libraries that have them. */
8888 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8890 set_gdbarch_single_step_through_delay (gdbarch
,
8891 mips_single_step_through_delay
);
8893 /* Virtual tables. */
8894 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8896 mips_register_g_packet_guesses (gdbarch
);
8898 /* Hook in OS ABI-specific overrides, if they have been registered. */
8899 info
.tdep_info
= tdesc_data
;
8900 gdbarch_init_osabi (info
, gdbarch
);
8902 /* The hook may have adjusted num_regs, fetch the final value and
8903 set pc_regnum and sp_regnum now that it has been fixed. */
8904 num_regs
= gdbarch_num_regs (gdbarch
);
8905 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8906 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8908 /* Unwind the frame. */
8909 dwarf2_append_unwinders (gdbarch
);
8910 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8911 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8912 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8913 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8914 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8915 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8916 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8917 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8918 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8922 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8923 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8925 /* Override the normal target description methods to handle our
8926 dual real and pseudo registers. */
8927 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8928 set_gdbarch_register_reggroup_p (gdbarch
,
8929 mips_tdesc_register_reggroup_p
);
8931 num_regs
= gdbarch_num_regs (gdbarch
);
8932 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8933 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8934 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8937 /* Add ABI-specific aliases for the registers. */
8938 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8939 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8940 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8941 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8943 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8944 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8945 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8947 /* Add some other standard aliases. */
8948 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8949 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8950 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8952 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8953 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8954 value_of_mips_user_reg
,
8955 &mips_numeric_register_aliases
[i
].regnum
);
8961 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
8963 struct gdbarch_info info
;
8965 /* Force the architecture to update, and (if it's a MIPS architecture)
8966 mips_gdbarch_init will take care of the rest. */
8967 gdbarch_info_init (&info
);
8968 gdbarch_update_p (info
);
8971 /* Print out which MIPS ABI is in use. */
8974 show_mips_abi (struct ui_file
*file
,
8976 struct cmd_list_element
*ignored_cmd
,
8977 const char *ignored_value
)
8979 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8982 "The MIPS ABI is unknown because the current architecture "
8986 enum mips_abi global_abi
= global_mips_abi ();
8987 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8988 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8990 if (global_abi
== MIPS_ABI_UNKNOWN
)
8993 "The MIPS ABI is set automatically (currently \"%s\").\n",
8995 else if (global_abi
== actual_abi
)
8998 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
9002 /* Probably shouldn't happen... */
9003 fprintf_filtered (file
,
9004 "The (auto detected) MIPS ABI \"%s\" is in use "
9005 "even though the user setting was \"%s\".\n",
9006 actual_abi_str
, mips_abi_strings
[global_abi
]);
9011 /* Print out which MIPS compressed ISA encoding is used. */
9014 show_mips_compression (struct ui_file
*file
, int from_tty
,
9015 struct cmd_list_element
*c
, const char *value
)
9017 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
9022 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
9024 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9028 int ef_mips_32bitmode
;
9029 /* Determine the ISA. */
9030 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
9048 /* Determine the size of a pointer. */
9049 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
9050 fprintf_unfiltered (file
,
9051 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
9053 fprintf_unfiltered (file
,
9054 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
9056 fprintf_unfiltered (file
,
9057 "mips_dump_tdep: ef_mips_arch = %d\n",
9059 fprintf_unfiltered (file
,
9060 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
9061 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
9062 fprintf_unfiltered (file
,
9064 "mips_mask_address_p() %d (default %d)\n",
9065 mips_mask_address_p (tdep
),
9066 tdep
->default_mask_address_p
);
9068 fprintf_unfiltered (file
,
9069 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
9070 MIPS_DEFAULT_FPU_TYPE
,
9071 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
9072 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
9073 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
9075 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
9076 MIPS_EABI (gdbarch
));
9077 fprintf_unfiltered (file
,
9078 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
9079 MIPS_FPU_TYPE (gdbarch
),
9080 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
9081 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
9082 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
9086 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
9089 _initialize_mips_tdep (void)
9091 static struct cmd_list_element
*mipsfpulist
= NULL
;
9092 struct cmd_list_element
*c
;
9094 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
9095 if (MIPS_ABI_LAST
+ 1
9096 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
9097 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
9099 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
9101 mips_pdr_data
= register_objfile_data ();
9103 /* Create feature sets with the appropriate properties. The values
9104 are not important. */
9105 mips_tdesc_gp32
= allocate_target_description ();
9106 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
9108 mips_tdesc_gp64
= allocate_target_description ();
9109 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
9111 /* Add root prefix command for all "set mips"/"show mips" commands. */
9112 add_prefix_cmd ("mips", no_class
, set_mips_command
,
9113 _("Various MIPS specific commands."),
9114 &setmipscmdlist
, "set mips ", 0, &setlist
);
9116 add_prefix_cmd ("mips", no_class
, show_mips_command
,
9117 _("Various MIPS specific commands."),
9118 &showmipscmdlist
, "show mips ", 0, &showlist
);
9120 /* Allow the user to override the ABI. */
9121 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9122 &mips_abi_string
, _("\
9123 Set the MIPS ABI used by this program."), _("\
9124 Show the MIPS ABI used by this program."), _("\
9125 This option can be set to one of:\n\
9126 auto - the default ABI associated with the current binary\n\
9135 &setmipscmdlist
, &showmipscmdlist
);
9137 /* Allow the user to set the ISA to assume for compressed code if ELF
9138 file flags don't tell or there is no program file selected. This
9139 setting is updated whenever unambiguous ELF file flags are interpreted,
9140 and carried over to subsequent sessions. */
9141 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9142 &mips_compression_string
, _("\
9143 Set the compressed ISA encoding used by MIPS code."), _("\
9144 Show the compressed ISA encoding used by MIPS code."), _("\
9145 Select the compressed ISA encoding used in functions that have no symbol\n\
9146 information available. The encoding can be set to either of:\n\
9149 and is updated automatically from ELF file flags if available."),
9151 show_mips_compression
,
9152 &setmipscmdlist
, &showmipscmdlist
);
9154 /* Let the user turn off floating point and set the fence post for
9155 heuristic_proc_start. */
9157 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
9158 _("Set use of MIPS floating-point coprocessor."),
9159 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
9160 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9161 _("Select single-precision MIPS floating-point coprocessor."),
9163 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9164 _("Select double-precision MIPS floating-point coprocessor."),
9166 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
9167 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
9168 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
9169 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9170 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9171 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
9172 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
9173 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
9174 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9175 _("Select MIPS floating-point coprocessor automatically."),
9177 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9178 _("Show current use of MIPS floating-point coprocessor target."),
9181 /* We really would like to have both "0" and "unlimited" work, but
9182 command.c doesn't deal with that. So make it a var_zinteger
9183 because the user can always use "999999" or some such for unlimited. */
9184 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9185 &heuristic_fence_post
, _("\
9186 Set the distance searched for the start of a function."), _("\
9187 Show the distance searched for the start of a function."), _("\
9188 If you are debugging a stripped executable, GDB needs to search through the\n\
9189 program for the start of a function. This command sets the distance of the\n\
9190 search. The only need to set it is when debugging a stripped executable."),
9191 reinit_frame_cache_sfunc
,
9192 NULL
, /* FIXME: i18n: The distance searched for
9193 the start of a function is %s. */
9194 &setlist
, &showlist
);
9196 /* Allow the user to control whether the upper bits of 64-bit
9197 addresses should be zeroed. */
9198 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9199 &mask_address_var
, _("\
9200 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9201 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9202 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9203 allow GDB to determine the correct value."),
9204 NULL
, show_mask_address
,
9205 &setmipscmdlist
, &showmipscmdlist
);
9207 /* Allow the user to control the size of 32 bit registers within the
9208 raw remote packet. */
9209 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9210 &mips64_transfers_32bit_regs_p
, _("\
9211 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9213 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9215 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9216 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9217 64 bits for others. Use \"off\" to disable compatibility mode"),
9218 set_mips64_transfers_32bit_regs
,
9219 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9220 MIPS target that transfers 32-bit
9221 quantities is %s. */
9222 &setlist
, &showlist
);
9224 /* Debug this files internals. */
9225 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9227 Set mips debugging."), _("\
9228 Show mips debugging."), _("\
9229 When non-zero, mips specific debugging is enabled."),
9231 NULL
, /* FIXME: i18n: Mips debugging is
9233 &setdebuglist
, &showdebuglist
);