1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
28 #include "gdb_assert.h"
40 #include "arch-utils.h"
43 #include "mips-tdep.h"
45 #include "reggroups.h"
46 #include "opcode/mips.h"
50 #include "sim-regno.h"
53 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
54 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
56 /* A useful bit in the CP0 status register (PS_REGNUM). */
57 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
58 #define ST0_FR (1 << 26)
60 /* The sizes of floating point registers. */
64 MIPS_FPU_SINGLE_REGSIZE
= 4,
65 MIPS_FPU_DOUBLE_REGSIZE
= 8
69 static const char *mips_abi_string
;
71 static const char *mips_abi_strings
[] = {
82 struct frame_extra_info
84 mips_extra_func_info_t proc_desc
;
88 /* Various MIPS ISA options (related to stack analysis) can be
89 overridden dynamically. Establish an enum/array for managing
92 static const char size_auto
[] = "auto";
93 static const char size_32
[] = "32";
94 static const char size_64
[] = "64";
96 static const char *size_enums
[] = {
103 /* Some MIPS boards don't support floating point while others only
104 support single-precision floating-point operations. See also
105 FP_REGISTER_DOUBLE. */
109 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
110 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
111 MIPS_FPU_NONE
/* No floating point. */
114 #ifndef MIPS_DEFAULT_FPU_TYPE
115 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
117 static int mips_fpu_type_auto
= 1;
118 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
120 static int mips_debug
= 0;
122 /* MIPS specific per-architecture information */
125 /* from the elf header */
129 enum mips_abi mips_abi
;
130 enum mips_abi found_abi
;
131 enum mips_fpu_type mips_fpu_type
;
132 int mips_last_arg_regnum
;
133 int mips_last_fp_arg_regnum
;
134 int mips_default_saved_regsize
;
135 int mips_fp_register_double
;
136 int mips_default_stack_argsize
;
137 int gdb_target_is_mips64
;
138 int default_mask_address_p
;
141 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
142 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
144 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
146 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
148 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
150 /* Return the currently configured (or set) saved register size. */
152 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
154 static const char *mips_saved_regsize_string
= size_auto
;
156 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
158 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
159 functions to test, set, or clear bit 0 of addresses. */
162 is_mips16_addr (CORE_ADDR addr
)
168 make_mips16_addr (CORE_ADDR addr
)
174 unmake_mips16_addr (CORE_ADDR addr
)
176 return ((addr
) & ~1);
179 /* Return the contents of register REGNUM as a signed integer. */
182 read_signed_register (int regnum
)
184 void *buf
= alloca (DEPRECATED_REGISTER_RAW_SIZE (regnum
));
185 deprecated_read_register_gen (regnum
, buf
);
186 return (extract_signed_integer (buf
, DEPRECATED_REGISTER_RAW_SIZE (regnum
)));
190 read_signed_register_pid (int regnum
, ptid_t ptid
)
195 if (ptid_equal (ptid
, inferior_ptid
))
196 return read_signed_register (regnum
);
198 save_ptid
= inferior_ptid
;
200 inferior_ptid
= ptid
;
202 retval
= read_signed_register (regnum
);
204 inferior_ptid
= save_ptid
;
209 /* Return the MIPS ABI associated with GDBARCH. */
211 mips_abi (struct gdbarch
*gdbarch
)
213 return gdbarch_tdep (gdbarch
)->mips_abi
;
217 mips_saved_regsize (void)
219 if (mips_saved_regsize_string
== size_auto
)
220 return MIPS_DEFAULT_SAVED_REGSIZE
;
221 else if (mips_saved_regsize_string
== size_64
)
223 else /* if (mips_saved_regsize_string == size_32) */
227 /* Functions for setting and testing a bit in a minimal symbol that
228 marks it as 16-bit function. The MSB of the minimal symbol's
229 "info" field is used for this purpose.
231 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
232 i.e. refers to a 16-bit function, and sets a "special" bit in a
233 minimal symbol to mark it as a 16-bit function
235 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
238 mips_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
240 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
242 MSYMBOL_INFO (msym
) = (char *)
243 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
244 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
249 msymbol_is_special (struct minimal_symbol
*msym
)
251 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
254 /* XFER a value from the big/little/left end of the register.
255 Depending on the size of the value it might occupy the entire
256 register or just part of it. Make an allowance for this, aligning
257 things accordingly. */
260 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
261 enum bfd_endian endian
, bfd_byte
*in
, const bfd_byte
*out
,
264 bfd_byte reg
[MAX_REGISTER_SIZE
];
266 gdb_assert (reg_num
>= NUM_REGS
);
267 /* Need to transfer the left or right part of the register, based on
268 the targets byte order. */
272 reg_offset
= DEPRECATED_REGISTER_RAW_SIZE (reg_num
) - length
;
274 case BFD_ENDIAN_LITTLE
:
277 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
281 internal_error (__FILE__
, __LINE__
, "bad switch");
284 fprintf_unfiltered (gdb_stderr
,
285 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
286 reg_num
, reg_offset
, buf_offset
, length
);
287 if (mips_debug
&& out
!= NULL
)
290 fprintf_unfiltered (gdb_stdlog
, "out ");
291 for (i
= 0; i
< length
; i
++)
292 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
295 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
, in
+ buf_offset
);
297 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
, out
+ buf_offset
);
298 if (mips_debug
&& in
!= NULL
)
301 fprintf_unfiltered (gdb_stdlog
, "in ");
302 for (i
= 0; i
< length
; i
++)
303 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
306 fprintf_unfiltered (gdb_stdlog
, "\n");
309 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
310 compatiblity mode. A return value of 1 means that we have
311 physical 64-bit registers, but should treat them as 32-bit registers. */
314 mips2_fp_compat (void)
316 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
318 if (DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM
) == 4)
322 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
323 in all the places we deal with FP registers. PR gdb/413. */
324 /* Otherwise check the FR bit in the status register - it controls
325 the FP compatiblity mode. If it is clear we are in compatibility
327 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
334 /* Indicate that the ABI makes use of double-precision registers
335 provided by the FPU (rather than combining pairs of registers to
336 form double-precision values). Do not use "TARGET_IS_MIPS64" to
337 determine if the ABI is using double-precision registers. See also
339 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
341 /* The amount of space reserved on the stack for registers. This is
342 different to MIPS_SAVED_REGSIZE as it determines the alignment of
343 data allocated after the registers have run out. */
345 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
347 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
349 static const char *mips_stack_argsize_string
= size_auto
;
352 mips_stack_argsize (void)
354 if (mips_stack_argsize_string
== size_auto
)
355 return MIPS_DEFAULT_STACK_ARGSIZE
;
356 else if (mips_stack_argsize_string
== size_64
)
358 else /* if (mips_stack_argsize_string == size_32) */
362 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
364 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
366 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
368 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
369 struct frame_info
*, int);
371 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
373 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
375 static int mips_set_processor_type (char *);
377 static void mips_show_processor_type_command (char *, int);
379 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
381 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
382 struct frame_info
*next_frame
,
385 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
386 mips_extra_func_info_t proc_desc
);
388 static struct type
*mips_float_register_type (void);
389 static struct type
*mips_double_register_type (void);
391 /* This value is the model of MIPS in use. It is derived from the value
392 of the PrID register. */
394 char *mips_processor_type
;
396 char *tmp_mips_processor_type
;
398 /* The list of available "set mips " and "show mips " commands */
400 static struct cmd_list_element
*setmipscmdlist
= NULL
;
401 static struct cmd_list_element
*showmipscmdlist
= NULL
;
403 /* A set of original names, to be used when restoring back to generic
404 registers from a specific set. */
405 static char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
407 /* Integer registers 0 thru 31 are handled explicitly by
408 mips_register_name(). Processor specific registers 32 and above
409 are listed in the sets of register names assigned to
410 mips_processor_reg_names. */
411 static char **mips_processor_reg_names
= mips_generic_reg_names
;
413 /* Return the name of the register corresponding to REGNO. */
415 mips_register_name (int regno
)
417 /* GPR names for all ABIs other than n32/n64. */
418 static char *mips_gpr_names
[] = {
419 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
420 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
421 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
422 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
425 /* GPR names for n32 and n64 ABIs. */
426 static char *mips_n32_n64_gpr_names
[] = {
427 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
428 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
429 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
430 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
433 enum mips_abi abi
= mips_abi (current_gdbarch
);
435 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
436 don't make the raw register names visible. */
437 int rawnum
= regno
% NUM_REGS
;
438 if (regno
< NUM_REGS
)
441 /* The MIPS integer registers are always mapped from 0 to 31. The
442 names of the registers (which reflects the conventions regarding
443 register use) vary depending on the ABI. */
444 if (0 <= rawnum
&& rawnum
< 32)
446 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
447 return mips_n32_n64_gpr_names
[rawnum
];
449 return mips_gpr_names
[rawnum
];
451 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
452 return mips_processor_reg_names
[rawnum
- 32];
454 internal_error (__FILE__
, __LINE__
,
455 "mips_register_name: bad register number %d", rawnum
);
459 /* Names of IDT R3041 registers. */
461 char *mips_r3041_reg_names
[] = {
462 "sr", "lo", "hi", "bad", "cause","pc",
463 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
464 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
465 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
466 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
467 "fsr", "fir", "",/*"fp"*/ "",
468 "", "", "bus", "ccfg", "", "", "", "",
469 "", "", "port", "cmp", "", "", "epc", "prid",
472 /* Names of IDT R3051 registers. */
474 char *mips_r3051_reg_names
[] = {
475 "sr", "lo", "hi", "bad", "cause","pc",
476 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
477 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
478 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
479 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
480 "fsr", "fir", ""/*"fp"*/, "",
481 "inx", "rand", "elo", "", "ctxt", "", "", "",
482 "", "", "ehi", "", "", "", "epc", "prid",
485 /* Names of IDT R3081 registers. */
487 char *mips_r3081_reg_names
[] = {
488 "sr", "lo", "hi", "bad", "cause","pc",
489 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
490 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
491 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
492 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
493 "fsr", "fir", ""/*"fp"*/, "",
494 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
495 "", "", "ehi", "", "", "", "epc", "prid",
498 /* Names of LSI 33k registers. */
500 char *mips_lsi33k_reg_names
[] = {
501 "epc", "hi", "lo", "sr", "cause","badvaddr",
502 "dcic", "bpc", "bda", "", "", "", "", "",
503 "", "", "", "", "", "", "", "",
504 "", "", "", "", "", "", "", "",
505 "", "", "", "", "", "", "", "",
507 "", "", "", "", "", "", "", "",
508 "", "", "", "", "", "", "", "",
514 } mips_processor_type_table
[] = {
515 { "generic", mips_generic_reg_names
},
516 { "r3041", mips_r3041_reg_names
},
517 { "r3051", mips_r3051_reg_names
},
518 { "r3071", mips_r3081_reg_names
},
519 { "r3081", mips_r3081_reg_names
},
520 { "lsi33k", mips_lsi33k_reg_names
},
525 /* Return the groups that a MIPS register can be categorised into. */
528 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
529 struct reggroup
*reggroup
)
534 int rawnum
= regnum
% NUM_REGS
;
535 int pseudo
= regnum
/ NUM_REGS
;
536 if (reggroup
== all_reggroup
)
538 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
539 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
540 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
541 (gdbarch), as not all architectures are multi-arch. */
542 raw_p
= rawnum
< NUM_REGS
;
543 if (REGISTER_NAME (regnum
) == NULL
544 || REGISTER_NAME (regnum
)[0] == '\0')
546 if (reggroup
== float_reggroup
)
547 return float_p
&& pseudo
;
548 if (reggroup
== vector_reggroup
)
549 return vector_p
&& pseudo
;
550 if (reggroup
== general_reggroup
)
551 return (!vector_p
&& !float_p
) && pseudo
;
552 /* Save the pseudo registers. Need to make certain that any code
553 extracting register values from a saved register cache also uses
555 if (reggroup
== save_reggroup
)
556 return raw_p
&& pseudo
;
557 /* Restore the same pseudo register. */
558 if (reggroup
== restore_reggroup
)
559 return raw_p
&& pseudo
;
563 /* Map the symbol table registers which live in the range [1 *
564 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
568 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
569 int cookednum
, void *buf
)
571 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
572 return regcache_raw_read (regcache
, cookednum
% NUM_REGS
, buf
);
576 mips_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
577 int cookednum
, const void *buf
)
579 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
580 return regcache_raw_write (regcache
, cookednum
% NUM_REGS
, buf
);
583 /* Table to translate MIPS16 register field to actual register number. */
584 static int mips16_to_32_reg
[8] =
585 {16, 17, 2, 3, 4, 5, 6, 7};
587 /* Heuristic_proc_start may hunt through the text section for a long
588 time across a 2400 baud serial line. Allows the user to limit this
591 static unsigned int heuristic_fence_post
= 0;
593 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
594 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
595 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
596 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
597 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
598 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
599 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
600 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
601 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
602 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
603 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
604 this will corrupt pdr.iline. Fortunately we don't use it. */
605 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
606 #define _PROC_MAGIC_ 0x0F0F0F0F
607 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
608 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
610 struct linked_proc_info
612 struct mips_extra_func_info info
;
613 struct linked_proc_info
*next
;
615 *linked_proc_desc_table
= NULL
;
617 /* Number of bytes of storage in the actual machine representation for
618 register N. NOTE: This indirectly defines the register size
619 transfered by the GDB protocol. */
621 static int mips64_transfers_32bit_regs_p
= 0;
624 mips_register_raw_size (int regnum
)
626 gdb_assert (regnum
>= 0);
627 if (regnum
< NUM_REGS
)
629 /* For compatibility with old code, implemnt the broken register raw
630 size map for the raw registers.
632 NOTE: cagney/2003-06-15: This is so bogus. The register's
633 raw size is changing according to the ABI
634 (FP_REGISTER_DOUBLE). Also, GDB's protocol is defined by a
635 combination of DEPRECATED_REGISTER_RAW_SIZE and DEPRECATED_REGISTER_BYTE. */
636 if (mips64_transfers_32bit_regs_p
)
637 return DEPRECATED_REGISTER_VIRTUAL_SIZE (regnum
);
638 else if (regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+ 32
639 && FP_REGISTER_DOUBLE
)
640 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
646 else if (regnum
< 2 * NUM_REGS
)
648 /* For the moment map [NUM_REGS .. 2*NUM_REGS) onto the same raw
649 registers, but always return the virtual size. */
650 int rawnum
= regnum
% NUM_REGS
;
651 return TYPE_LENGTH (gdbarch_register_type (current_gdbarch
, rawnum
));
654 internal_error (__FILE__
, __LINE__
, "Register %d out of range", regnum
);
657 /* Register offset in a buffer for each register.
659 FIXME: cagney/2003-06-15: This is so bogus. Instead REGISTER_TYPE
660 should strictly return the layout of the buffer. Unfortunately
661 remote.c and the MIPS have come to rely on a custom layout that
662 doesn't 1:1 map onto the register type. */
665 mips_register_byte (int regnum
)
667 gdb_assert (regnum
>= 0);
668 if (regnum
< NUM_REGS
)
669 /* Pick up the relevant per-tm file register byte method. */
670 return MIPS_REGISTER_BYTE (regnum
);
671 else if (regnum
< 2 * NUM_REGS
)
675 /* Start with the end of the raw register buffer - assum that
676 MIPS_REGISTER_BYTE (NUM_REGS) returns that end. */
677 byte
= MIPS_REGISTER_BYTE (NUM_REGS
);
678 /* Add space for all the proceeding registers based on their
680 for (reg
= NUM_REGS
; reg
< regnum
; reg
++)
681 byte
+= TYPE_LENGTH (gdbarch_register_type (current_gdbarch
,
686 internal_error (__FILE__
, __LINE__
, "Register %d out of range", regnum
);
689 /* Convert between RAW and VIRTUAL registers. The RAW register size
690 defines the remote-gdb packet. */
693 mips_register_convertible (int reg_nr
)
695 if (mips64_transfers_32bit_regs_p
)
698 return (DEPRECATED_REGISTER_RAW_SIZE (reg_nr
) > DEPRECATED_REGISTER_VIRTUAL_SIZE (reg_nr
));
702 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
703 char *raw_buf
, char *virt_buf
)
705 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
707 raw_buf
+ (DEPRECATED_REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
708 TYPE_LENGTH (virtual_type
));
712 TYPE_LENGTH (virtual_type
));
716 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
717 const char *virt_buf
, char *raw_buf
)
719 memset (raw_buf
, 0, DEPRECATED_REGISTER_RAW_SIZE (n
));
720 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
721 memcpy (raw_buf
+ (DEPRECATED_REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
723 TYPE_LENGTH (virtual_type
));
727 TYPE_LENGTH (virtual_type
));
731 mips_convert_register_p (int regnum
, struct type
*type
)
733 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
734 && DEPRECATED_REGISTER_RAW_SIZE (regnum
) == 4
735 && (regnum
) >= FP0_REGNUM
&& (regnum
) < FP0_REGNUM
+ 32
736 && TYPE_CODE(type
) == TYPE_CODE_FLT
737 && TYPE_LENGTH(type
) == 8);
741 mips_register_to_value (struct frame_info
*frame
, int regnum
,
742 struct type
*type
, void *to
)
744 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
745 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
749 mips_value_to_register (struct frame_info
*frame
, int regnum
,
750 struct type
*type
, const void *from
)
752 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
753 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
756 /* Return the GDB type object for the "standard" data type of data in
760 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
762 /* For moment, map [NUM_REGS .. 2*NUM_REGS) onto the same raw
763 registers. Even return the same type. */
764 int rawnum
= regnum
% NUM_REGS
;
765 gdb_assert (rawnum
>= 0 && rawnum
< NUM_REGS
);
766 #ifdef MIPS_REGISTER_TYPE
767 return MIPS_REGISTER_TYPE (rawnum
);
769 if (FP0_REGNUM
<= rawnum
&& rawnum
< FP0_REGNUM
+ 32)
771 /* Floating point registers... */
772 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
773 return builtin_type_ieee_double_big
;
775 return builtin_type_ieee_double_little
;
777 else if (rawnum
== PS_REGNUM
/* CR */)
778 return builtin_type_uint32
;
779 else if (FCRCS_REGNUM
<= rawnum
&& rawnum
<= LAST_EMBED_REGNUM
)
780 return builtin_type_uint32
;
783 /* Everything else...
784 Return type appropriate for width of register. */
785 if (MIPS_REGSIZE
== TYPE_LENGTH (builtin_type_uint64
))
786 return builtin_type_uint64
;
788 return builtin_type_uint32
;
793 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
798 return read_signed_register (SP_REGNUM
);
801 /* Should the upper word of 64-bit addresses be zeroed? */
802 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
805 mips_mask_address_p (void)
807 switch (mask_address_var
)
809 case AUTO_BOOLEAN_TRUE
:
811 case AUTO_BOOLEAN_FALSE
:
814 case AUTO_BOOLEAN_AUTO
:
815 return MIPS_DEFAULT_MASK_ADDRESS_P
;
817 internal_error (__FILE__
, __LINE__
,
818 "mips_mask_address_p: bad switch");
824 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
826 switch (mask_address_var
)
828 case AUTO_BOOLEAN_TRUE
:
829 printf_filtered ("The 32 bit mips address mask is enabled\n");
831 case AUTO_BOOLEAN_FALSE
:
832 printf_filtered ("The 32 bit mips address mask is disabled\n");
834 case AUTO_BOOLEAN_AUTO
:
835 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
836 mips_mask_address_p () ? "enabled" : "disabled");
839 internal_error (__FILE__
, __LINE__
,
840 "show_mask_address: bad switch");
845 /* Should call_function allocate stack space for a struct return? */
848 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
850 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
854 mips_n32n64_use_struct_convention (int gcc_p
, struct type
*type
)
856 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
859 /* Should call_function pass struct by reference?
860 For each architecture, structs are passed either by
861 value or by reference, depending on their size. */
864 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
866 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
867 int len
= TYPE_LENGTH (check_typedef (type
));
869 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
870 return (len
> MIPS_SAVED_REGSIZE
);
876 mips_n32n64_reg_struct_has_addr (int gcc_p
, struct type
*type
)
878 return 0; /* Assumption: N32/N64 never passes struct by ref. */
882 mips_o32_reg_struct_has_addr (int gcc_p
, struct type
*type
)
884 return 0; /* Assumption: O32/O64 never passes struct by ref. */
887 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
890 pc_is_mips16 (bfd_vma memaddr
)
892 struct minimal_symbol
*sym
;
894 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
895 if (is_mips16_addr (memaddr
))
898 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
899 the high bit of the info field. Use this to decide if the function is
900 MIPS16 or normal MIPS. */
901 sym
= lookup_minimal_symbol_by_pc (memaddr
);
903 return msymbol_is_special (sym
);
908 /* MIPS believes that the PC has a sign extended value. Perhaphs the
909 all registers should be sign extended for simplicity? */
912 mips_read_pc (ptid_t ptid
)
914 return read_signed_register_pid (PC_REGNUM
, ptid
);
917 /* This returns the PC of the first inst after the prologue. If we can't
918 find the prologue, then return 0. */
921 after_prologue (CORE_ADDR pc
,
922 mips_extra_func_info_t proc_desc
)
924 struct symtab_and_line sal
;
925 CORE_ADDR func_addr
, func_end
;
927 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
928 to read the stack pointer from the current machine state, because
929 the current machine state has nothing to do with the information
930 we need from the proc_desc; and the process may or may not exist
933 proc_desc
= find_proc_desc (pc
, NULL
, 0);
937 /* If function is frameless, then we need to do it the hard way. I
938 strongly suspect that frameless always means prologueless... */
939 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
940 && PROC_FRAME_OFFSET (proc_desc
) == 0)
944 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
945 return 0; /* Unknown */
947 sal
= find_pc_line (func_addr
, 0);
949 if (sal
.end
< func_end
)
952 /* The line after the prologue is after the end of the function. In this
953 case, tell the caller to find the prologue the hard way. */
958 /* Decode a MIPS32 instruction that saves a register in the stack, and
959 set the appropriate bit in the general register mask or float register mask
960 to indicate which register is saved. This is a helper function
961 for mips_find_saved_regs. */
964 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
965 unsigned long *float_mask
)
969 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
970 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
971 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
973 /* It might be possible to use the instruction to
974 find the offset, rather than the code below which
975 is based on things being in a certain order in the
976 frame, but figuring out what the instruction's offset
977 is relative to might be a little tricky. */
978 reg
= (inst
& 0x001f0000) >> 16;
979 *gen_mask
|= (1 << reg
);
981 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
982 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
983 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
986 reg
= ((inst
& 0x001f0000) >> 16);
987 *float_mask
|= (1 << reg
);
991 /* Decode a MIPS16 instruction that saves a register in the stack, and
992 set the appropriate bit in the general register or float register mask
993 to indicate which register is saved. This is a helper function
994 for mips_find_saved_regs. */
997 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
999 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1001 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1002 *gen_mask
|= (1 << reg
);
1004 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1006 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1007 *gen_mask
|= (1 << reg
);
1009 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
1010 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1011 *gen_mask
|= (1 << RA_REGNUM
);
1015 /* Fetch and return instruction from the specified location. If the PC
1016 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1019 mips_fetch_instruction (CORE_ADDR addr
)
1021 char buf
[MIPS_INSTLEN
];
1025 if (pc_is_mips16 (addr
))
1027 instlen
= MIPS16_INSTLEN
;
1028 addr
= unmake_mips16_addr (addr
);
1031 instlen
= MIPS_INSTLEN
;
1032 status
= read_memory_nobpt (addr
, buf
, instlen
);
1034 memory_error (status
, addr
);
1035 return extract_unsigned_integer (buf
, instlen
);
1039 /* These the fields of 32 bit mips instructions */
1040 #define mips32_op(x) (x >> 26)
1041 #define itype_op(x) (x >> 26)
1042 #define itype_rs(x) ((x >> 21) & 0x1f)
1043 #define itype_rt(x) ((x >> 16) & 0x1f)
1044 #define itype_immediate(x) (x & 0xffff)
1046 #define jtype_op(x) (x >> 26)
1047 #define jtype_target(x) (x & 0x03ffffff)
1049 #define rtype_op(x) (x >> 26)
1050 #define rtype_rs(x) ((x >> 21) & 0x1f)
1051 #define rtype_rt(x) ((x >> 16) & 0x1f)
1052 #define rtype_rd(x) ((x >> 11) & 0x1f)
1053 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1054 #define rtype_funct(x) (x & 0x3f)
1057 mips32_relative_offset (unsigned long inst
)
1060 x
= itype_immediate (inst
);
1061 if (x
& 0x8000) /* sign bit set */
1063 x
|= 0xffff0000; /* sign extension */
1069 /* Determine whate to set a single step breakpoint while considering
1070 branch prediction */
1072 mips32_next_pc (CORE_ADDR pc
)
1076 inst
= mips_fetch_instruction (pc
);
1077 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1079 if (itype_op (inst
) >> 2 == 5)
1080 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1082 op
= (itype_op (inst
) & 0x03);
1092 goto greater_branch
;
1097 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1098 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1100 int tf
= itype_rt (inst
) & 0x01;
1101 int cnum
= itype_rt (inst
) >> 2;
1102 int fcrcs
= read_signed_register (FCRCS_REGNUM
);
1103 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1105 if (((cond
>> cnum
) & 0x01) == tf
)
1106 pc
+= mips32_relative_offset (inst
) + 4;
1111 pc
+= 4; /* Not a branch, next instruction is easy */
1114 { /* This gets way messy */
1116 /* Further subdivide into SPECIAL, REGIMM and other */
1117 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1119 case 0: /* SPECIAL */
1120 op
= rtype_funct (inst
);
1125 /* Set PC to that address */
1126 pc
= read_signed_register (rtype_rs (inst
));
1132 break; /* end SPECIAL */
1133 case 1: /* REGIMM */
1135 op
= itype_rt (inst
); /* branch condition */
1140 case 16: /* BLTZAL */
1141 case 18: /* BLTZALL */
1143 if (read_signed_register (itype_rs (inst
)) < 0)
1144 pc
+= mips32_relative_offset (inst
) + 4;
1146 pc
+= 8; /* after the delay slot */
1150 case 17: /* BGEZAL */
1151 case 19: /* BGEZALL */
1152 greater_equal_branch
:
1153 if (read_signed_register (itype_rs (inst
)) >= 0)
1154 pc
+= mips32_relative_offset (inst
) + 4;
1156 pc
+= 8; /* after the delay slot */
1158 /* All of the other instructions in the REGIMM category */
1163 break; /* end REGIMM */
1168 reg
= jtype_target (inst
) << 2;
1169 /* Upper four bits get never changed... */
1170 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1173 /* FIXME case JALX : */
1176 reg
= jtype_target (inst
) << 2;
1177 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1178 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1180 break; /* The new PC will be alternate mode */
1181 case 4: /* BEQ, BEQL */
1183 if (read_signed_register (itype_rs (inst
)) ==
1184 read_signed_register (itype_rt (inst
)))
1185 pc
+= mips32_relative_offset (inst
) + 4;
1189 case 5: /* BNE, BNEL */
1191 if (read_signed_register (itype_rs (inst
)) !=
1192 read_signed_register (itype_rt (inst
)))
1193 pc
+= mips32_relative_offset (inst
) + 4;
1197 case 6: /* BLEZ, BLEZL */
1199 if (read_signed_register (itype_rs (inst
) <= 0))
1200 pc
+= mips32_relative_offset (inst
) + 4;
1206 greater_branch
: /* BGTZ, BGTZL */
1207 if (read_signed_register (itype_rs (inst
) > 0))
1208 pc
+= mips32_relative_offset (inst
) + 4;
1215 } /* mips32_next_pc */
1217 /* Decoding the next place to set a breakpoint is irregular for the
1218 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1219 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1220 We dont want to set a single step instruction on the extend instruction
1224 /* Lots of mips16 instruction formats */
1225 /* Predicting jumps requires itype,ritype,i8type
1226 and their extensions extItype,extritype,extI8type
1228 enum mips16_inst_fmts
1230 itype
, /* 0 immediate 5,10 */
1231 ritype
, /* 1 5,3,8 */
1232 rrtype
, /* 2 5,3,3,5 */
1233 rritype
, /* 3 5,3,3,5 */
1234 rrrtype
, /* 4 5,3,3,3,2 */
1235 rriatype
, /* 5 5,3,3,1,4 */
1236 shifttype
, /* 6 5,3,3,3,2 */
1237 i8type
, /* 7 5,3,8 */
1238 i8movtype
, /* 8 5,3,3,5 */
1239 i8mov32rtype
, /* 9 5,3,5,3 */
1240 i64type
, /* 10 5,3,8 */
1241 ri64type
, /* 11 5,3,3,5 */
1242 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1243 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1244 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1245 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1246 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1247 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1248 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1249 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1250 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1251 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1253 /* I am heaping all the fields of the formats into one structure and
1254 then, only the fields which are involved in instruction extension */
1258 unsigned int regx
; /* Function in i8 type */
1263 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1264 for the bits which make up the immediatate extension. */
1267 extended_offset (unsigned int extension
)
1270 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1272 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1274 value
|= extension
& 0x01f; /* extract 4:0 */
1278 /* Only call this function if you know that this is an extendable
1279 instruction, It wont malfunction, but why make excess remote memory references?
1280 If the immediate operands get sign extended or somthing, do it after
1281 the extension is performed.
1283 /* FIXME: Every one of these cases needs to worry about sign extension
1284 when the offset is to be used in relative addressing */
1288 fetch_mips_16 (CORE_ADDR pc
)
1291 pc
&= 0xfffffffe; /* clear the low order bit */
1292 target_read_memory (pc
, buf
, 2);
1293 return extract_unsigned_integer (buf
, 2);
1297 unpack_mips16 (CORE_ADDR pc
,
1298 unsigned int extension
,
1300 enum mips16_inst_fmts insn_format
,
1301 struct upk_mips16
*upk
)
1306 switch (insn_format
)
1313 value
= extended_offset (extension
);
1314 value
= value
<< 11; /* rom for the original value */
1315 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1319 value
= inst
& 0x7ff;
1320 /* FIXME : Consider sign extension */
1329 { /* A register identifier and an offset */
1330 /* Most of the fields are the same as I type but the
1331 immediate value is of a different length */
1335 value
= extended_offset (extension
);
1336 value
= value
<< 8; /* from the original instruction */
1337 value
|= inst
& 0xff; /* eleven bits from instruction */
1338 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1339 if (value
& 0x4000) /* test the sign bit , bit 26 */
1341 value
&= ~0x3fff; /* remove the sign bit */
1347 value
= inst
& 0xff; /* 8 bits */
1348 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1349 /* FIXME: Do sign extension , this format needs it */
1350 if (value
& 0x80) /* THIS CONFUSES ME */
1352 value
&= 0xef; /* remove the sign bit */
1362 unsigned long value
;
1363 unsigned int nexthalf
;
1364 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1365 value
= value
<< 16;
1366 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1374 internal_error (__FILE__
, __LINE__
,
1377 upk
->offset
= offset
;
1384 add_offset_16 (CORE_ADDR pc
, int offset
)
1386 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1390 extended_mips16_next_pc (CORE_ADDR pc
,
1391 unsigned int extension
,
1394 int op
= (insn
>> 11);
1397 case 2: /* Branch */
1400 struct upk_mips16 upk
;
1401 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1402 offset
= upk
.offset
;
1408 pc
+= (offset
<< 1) + 2;
1411 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1413 struct upk_mips16 upk
;
1414 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1415 pc
= add_offset_16 (pc
, upk
.offset
);
1416 if ((insn
>> 10) & 0x01) /* Exchange mode */
1417 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1424 struct upk_mips16 upk
;
1426 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1427 reg
= read_signed_register (upk
.regx
);
1429 pc
+= (upk
.offset
<< 1) + 2;
1436 struct upk_mips16 upk
;
1438 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1439 reg
= read_signed_register (upk
.regx
);
1441 pc
+= (upk
.offset
<< 1) + 2;
1446 case 12: /* I8 Formats btez btnez */
1448 struct upk_mips16 upk
;
1450 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1451 /* upk.regx contains the opcode */
1452 reg
= read_signed_register (24); /* Test register is 24 */
1453 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1454 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1455 /* pc = add_offset_16(pc,upk.offset) ; */
1456 pc
+= (upk
.offset
<< 1) + 2;
1461 case 29: /* RR Formats JR, JALR, JALR-RA */
1463 struct upk_mips16 upk
;
1464 /* upk.fmt = rrtype; */
1469 upk
.regx
= (insn
>> 8) & 0x07;
1470 upk
.regy
= (insn
>> 5) & 0x07;
1478 break; /* Function return instruction */
1484 break; /* BOGUS Guess */
1486 pc
= read_signed_register (reg
);
1493 /* This is an instruction extension. Fetch the real instruction
1494 (which follows the extension) and decode things based on
1498 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1511 mips16_next_pc (CORE_ADDR pc
)
1513 unsigned int insn
= fetch_mips_16 (pc
);
1514 return extended_mips16_next_pc (pc
, 0, insn
);
1517 /* The mips_next_pc function supports single_step when the remote
1518 target monitor or stub is not developed enough to do a single_step.
1519 It works by decoding the current instruction and predicting where a
1520 branch will go. This isnt hard because all the data is available.
1521 The MIPS32 and MIPS16 variants are quite different */
1523 mips_next_pc (CORE_ADDR pc
)
1526 return mips16_next_pc (pc
);
1528 return mips32_next_pc (pc
);
1531 /* Set up the 'saved_regs' array. This is a data structure containing
1532 the addresses on the stack where each register has been saved, for
1533 each stack frame. Registers that have not been saved will have
1534 zero here. The stack pointer register is special: rather than the
1535 address where the stack register has been saved,
1536 saved_regs[SP_REGNUM] will have the actual value of the previous
1537 frame's stack register. */
1540 mips_find_saved_regs (struct frame_info
*fci
)
1543 /* r0 bit means kernel trap */
1545 /* What registers have been saved? Bitmasks. */
1546 unsigned long gen_mask
, float_mask
;
1547 mips_extra_func_info_t proc_desc
;
1549 CORE_ADDR
*saved_regs
;
1551 if (deprecated_get_frame_saved_regs (fci
) != NULL
)
1553 saved_regs
= frame_saved_regs_zalloc (fci
);
1555 /* If it is the frame for sigtramp, the saved registers are located
1556 in a sigcontext structure somewhere on the stack. If the stack
1557 layout for sigtramp changes we might have to change these
1558 constants and the companion fixup_sigtramp in mdebugread.c */
1559 #ifndef SIGFRAME_BASE
1560 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1561 above the sigtramp frame. */
1562 #define SIGFRAME_BASE MIPS_REGSIZE
1563 /* FIXME! Are these correct?? */
1564 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1565 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1566 #define SIGFRAME_FPREGSAVE_OFF \
1567 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1569 #ifndef SIGFRAME_REG_SIZE
1570 /* FIXME! Is this correct?? */
1571 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1573 if ((get_frame_type (fci
) == SIGTRAMP_FRAME
))
1575 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1577 CORE_ADDR reg_position
= (get_frame_base (fci
) + SIGFRAME_REGSAVE_OFF
1578 + ireg
* SIGFRAME_REG_SIZE
);
1579 set_reg_offset (saved_regs
, ireg
, reg_position
);
1581 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1583 CORE_ADDR reg_position
= (get_frame_base (fci
)
1584 + SIGFRAME_FPREGSAVE_OFF
1585 + ireg
* SIGFRAME_REG_SIZE
);
1586 set_reg_offset (saved_regs
, FP0_REGNUM
+ ireg
, reg_position
);
1589 set_reg_offset (saved_regs
, PC_REGNUM
, get_frame_base (fci
) + SIGFRAME_PC_OFF
);
1590 /* SP_REGNUM, contains the value and not the address. */
1591 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1595 proc_desc
= get_frame_extra_info (fci
)->proc_desc
;
1596 if (proc_desc
== NULL
)
1597 /* I'm not sure how/whether this can happen. Normally when we
1598 can't find a proc_desc, we "synthesize" one using
1599 heuristic_proc_desc and set the saved_regs right away. */
1602 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1603 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1604 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1606 if (/* In any frame other than the innermost or a frame interrupted
1607 by a signal, we assume that all registers have been saved.
1608 This assumes that all register saves in a function happen
1609 before the first function call. */
1610 (get_next_frame (fci
) == NULL
1611 || (get_frame_type (get_next_frame (fci
)) == SIGTRAMP_FRAME
))
1613 /* In a dummy frame we know exactly where things are saved. */
1614 && !PROC_DESC_IS_DUMMY (proc_desc
)
1616 /* Don't bother unless we are inside a function prologue.
1617 Outside the prologue, we know where everything is. */
1619 && in_prologue (get_frame_pc (fci
), PROC_LOW_ADDR (proc_desc
))
1621 /* Not sure exactly what kernel_trap means, but if it means the
1622 kernel saves the registers without a prologue doing it, we
1623 better not examine the prologue to see whether registers
1624 have been saved yet. */
1627 /* We need to figure out whether the registers that the
1628 proc_desc claims are saved have been saved yet. */
1632 /* Bitmasks; set if we have found a save for the register. */
1633 unsigned long gen_save_found
= 0;
1634 unsigned long float_save_found
= 0;
1637 /* If the address is odd, assume this is MIPS16 code. */
1638 addr
= PROC_LOW_ADDR (proc_desc
);
1639 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1641 /* Scan through this function's instructions preceding the
1642 current PC, and look for those that save registers. */
1643 while (addr
< get_frame_pc (fci
))
1645 inst
= mips_fetch_instruction (addr
);
1646 if (pc_is_mips16 (addr
))
1647 mips16_decode_reg_save (inst
, &gen_save_found
);
1649 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1652 gen_mask
= gen_save_found
;
1653 float_mask
= float_save_found
;
1656 /* Fill in the offsets for the registers which gen_mask says were
1659 CORE_ADDR reg_position
= (get_frame_base (fci
)
1660 + PROC_REG_OFFSET (proc_desc
));
1661 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1662 if (gen_mask
& 0x80000000)
1664 set_reg_offset (saved_regs
, ireg
, reg_position
);
1665 reg_position
-= MIPS_SAVED_REGSIZE
;
1669 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1670 order of that normally used by gcc. Therefore, we have to fetch
1671 the first instruction of the function, and if it's an entry
1672 instruction that saves $s0 or $s1, correct their saved addresses. */
1673 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1675 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1676 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1680 int sreg_count
= (inst
>> 6) & 3;
1682 /* Check if the ra register was pushed on the stack. */
1683 CORE_ADDR reg_position
= (get_frame_base (fci
)
1684 + PROC_REG_OFFSET (proc_desc
));
1686 reg_position
-= MIPS_SAVED_REGSIZE
;
1688 /* Check if the s0 and s1 registers were pushed on the
1690 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1692 set_reg_offset (saved_regs
, reg
, reg_position
);
1693 reg_position
-= MIPS_SAVED_REGSIZE
;
1698 /* Fill in the offsets for the registers which float_mask says were
1701 CORE_ADDR reg_position
= (get_frame_base (fci
)
1702 + PROC_FREG_OFFSET (proc_desc
));
1704 /* Fill in the offsets for the float registers which float_mask
1706 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1707 if (float_mask
& 0x80000000)
1709 if (MIPS_SAVED_REGSIZE
== 4 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1711 /* On a big endian 32 bit ABI, floating point registers
1712 are paired to form doubles such that the most
1713 significant part is in $f[N+1] and the least
1714 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1715 registers are also spilled as a pair and stored as a
1718 When little-endian the least significant part is
1719 stored first leading to the memory order $f[N] and
1722 Unfortunately, when big-endian the most significant
1723 part of the double is stored first, and the least
1724 significant is stored second. This leads to the
1725 registers being ordered in memory as firt $f[N+1] and
1728 For the big-endian case make certain that the
1729 addresses point at the correct (swapped) locations
1730 $f[N] and $f[N+1] pair (keep in mind that
1731 reg_position is decremented each time through the
1734 set_reg_offset (saved_regs
, FP0_REGNUM
+ ireg
,
1735 reg_position
- MIPS_SAVED_REGSIZE
);
1737 set_reg_offset (saved_regs
, FP0_REGNUM
+ ireg
,
1738 reg_position
+ MIPS_SAVED_REGSIZE
);
1741 set_reg_offset (saved_regs
, FP0_REGNUM
+ ireg
, reg_position
);
1742 reg_position
-= MIPS_SAVED_REGSIZE
;
1745 set_reg_offset (saved_regs
, PC_REGNUM
, saved_regs
[RA_REGNUM
]);
1748 /* SP_REGNUM, contains the value and not the address. */
1749 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1753 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1755 /* Always a pseudo. */
1756 gdb_assert (regno
>= NUM_REGS
);
1760 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1763 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1764 /* The SP_REGNUM is special, its value is stored in saved_regs.
1765 In fact, it is so special that it can even only be fetched
1766 using a raw register number! Once this code as been converted
1767 to frame-unwind the problem goes away. */
1768 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1770 return frame_unwind_register_signed (fi
, regno
);
1774 /* mips_addr_bits_remove - remove useless address bits */
1777 mips_addr_bits_remove (CORE_ADDR addr
)
1779 if (GDB_TARGET_IS_MIPS64
)
1781 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1783 /* This hack is a work-around for existing boards using
1784 PMON, the simulator, and any other 64-bit targets that
1785 doesn't have true 64-bit addressing. On these targets,
1786 the upper 32 bits of addresses are ignored by the
1787 hardware. Thus, the PC or SP are likely to have been
1788 sign extended to all 1s by instruction sequences that
1789 load 32-bit addresses. For example, a typical piece of
1790 code that loads an address is this:
1791 lui $r2, <upper 16 bits>
1792 ori $r2, <lower 16 bits>
1793 But the lui sign-extends the value such that the upper 32
1794 bits may be all 1s. The workaround is simply to mask off
1795 these bits. In the future, gcc may be changed to support
1796 true 64-bit addressing, and this masking will have to be
1798 addr
&= (CORE_ADDR
) 0xffffffff;
1801 else if (mips_mask_address_p ())
1803 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1804 masking off bits, instead, the actual target should be asking
1805 for the address to be converted to a valid pointer. */
1806 /* Even when GDB is configured for some 32-bit targets
1807 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1808 so CORE_ADDR is 64 bits. So we still have to mask off
1809 useless bits from addresses. */
1810 addr
&= (CORE_ADDR
) 0xffffffff;
1815 /* mips_software_single_step() is called just before we want to resume
1816 the inferior, if we want to single-step it but there is no hardware
1817 or kernel single-step support (MIPS on GNU/Linux for example). We find
1818 the target of the coming instruction and breakpoint it.
1820 single_step is also called just after the inferior stops. If we had
1821 set up a simulated single-step, we undo our damage. */
1824 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1826 static CORE_ADDR next_pc
;
1827 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1828 static binsn_quantum break_mem
;
1831 if (insert_breakpoints_p
)
1833 pc
= read_register (PC_REGNUM
);
1834 next_pc
= mips_next_pc (pc
);
1836 target_insert_breakpoint (next_pc
, break_mem
);
1839 target_remove_breakpoint (next_pc
, break_mem
);
1843 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1848 ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev
))
1849 : get_next_frame (prev
)
1850 ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev
))
1852 tmp
= SKIP_TRAMPOLINE_CODE (pc
);
1853 return tmp
? tmp
: pc
;
1858 mips_frame_saved_pc (struct frame_info
*frame
)
1862 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
1865 /* Always unwind the cooked PC register value. */
1866 frame_unwind_signed_register (frame
, NUM_REGS
+ PC_REGNUM
, &tmp
);
1871 mips_extra_func_info_t proc_desc
1872 = get_frame_extra_info (frame
)->proc_desc
;
1873 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1874 saved_pc
= read_memory_integer (get_frame_base (frame
) - MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1877 /* We have to get the saved pc from the sigcontext if it is
1878 a signal handler frame. */
1879 int pcreg
= (get_frame_type (frame
) == SIGTRAMP_FRAME
? PC_REGNUM
1880 : proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1881 saved_pc
= read_next_frame_reg (frame
, NUM_REGS
+ pcreg
);
1884 return ADDR_BITS_REMOVE (saved_pc
);
1887 static struct mips_extra_func_info temp_proc_desc
;
1889 /* This hack will go away once the get_prev_frame() code has been
1890 modified to set the frame's type first. That is BEFORE init extra
1891 frame info et.al. is called. This is because it will become
1892 possible to skip the init extra info call for sigtramp and dummy
1894 static CORE_ADDR
*temp_saved_regs
;
1896 /* Set a register's saved stack address in temp_saved_regs. If an
1897 address has already been set for this register, do nothing; this
1898 way we will only recognize the first save of a given register in a
1901 For simplicity, save the address in both [0 .. NUM_REGS) and
1902 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1903 is used as it is only second range (the ABI instead of ISA
1904 registers) that comes into play when finding saved registers in a
1908 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
1910 if (saved_regs
[regno
] == 0)
1912 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
1913 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
1918 /* Test whether the PC points to the return instruction at the
1919 end of a function. */
1922 mips_about_to_return (CORE_ADDR pc
)
1924 if (pc_is_mips16 (pc
))
1925 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1926 generates a "jr $ra"; other times it generates code to load
1927 the return address from the stack to an accessible register (such
1928 as $a3), then a "jr" using that register. This second case
1929 is almost impossible to distinguish from an indirect jump
1930 used for switch statements, so we don't even try. */
1931 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1933 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1937 /* This fencepost looks highly suspicious to me. Removing it also
1938 seems suspicious as it could affect remote debugging across serial
1942 heuristic_proc_start (CORE_ADDR pc
)
1949 pc
= ADDR_BITS_REMOVE (pc
);
1951 fence
= start_pc
- heuristic_fence_post
;
1955 if (heuristic_fence_post
== UINT_MAX
1956 || fence
< VM_MIN_ADDRESS
)
1957 fence
= VM_MIN_ADDRESS
;
1959 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1961 /* search back for previous return */
1962 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1963 if (start_pc
< fence
)
1965 /* It's not clear to me why we reach this point when
1966 stop_soon, but with this test, at least we
1967 don't print out warnings for every child forked (eg, on
1968 decstation). 22apr93 rich@cygnus.com. */
1969 if (stop_soon
== NO_STOP_QUIETLY
)
1971 static int blurb_printed
= 0;
1973 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1978 /* This actually happens frequently in embedded
1979 development, when you first connect to a board
1980 and your stack pointer and pc are nowhere in
1981 particular. This message needs to give people
1982 in that situation enough information to
1983 determine that it's no big deal. */
1984 printf_filtered ("\n\
1985 GDB is unable to find the start of the function at 0x%s\n\
1986 and thus can't determine the size of that function's stack frame.\n\
1987 This means that GDB may be unable to access that stack frame, or\n\
1988 the frames below it.\n\
1989 This problem is most likely caused by an invalid program counter or\n\
1991 However, if you think GDB should simply search farther back\n\
1992 from 0x%s for code which looks like the beginning of a\n\
1993 function, you can increase the range of the search using the `set\n\
1994 heuristic-fence-post' command.\n",
1995 paddr_nz (pc
), paddr_nz (pc
));
2002 else if (pc_is_mips16 (start_pc
))
2004 unsigned short inst
;
2006 /* On MIPS16, any one of the following is likely to be the
2007 start of a function:
2011 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2012 inst
= mips_fetch_instruction (start_pc
);
2013 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2014 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2015 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2016 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2018 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2019 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2024 else if (mips_about_to_return (start_pc
))
2026 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2033 /* Fetch the immediate value from a MIPS16 instruction.
2034 If the previous instruction was an EXTEND, use it to extend
2035 the upper bits of the immediate value. This is a helper function
2036 for mips16_heuristic_proc_desc. */
2039 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2040 unsigned short inst
, /* current instruction */
2041 int nbits
, /* number of bits in imm field */
2042 int scale
, /* scale factor to be applied to imm */
2043 int is_signed
) /* is the imm field signed? */
2047 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2049 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2050 if (offset
& 0x8000) /* check for negative extend */
2051 offset
= 0 - (0x10000 - (offset
& 0xffff));
2052 return offset
| (inst
& 0x1f);
2056 int max_imm
= 1 << nbits
;
2057 int mask
= max_imm
- 1;
2058 int sign_bit
= max_imm
>> 1;
2060 offset
= inst
& mask
;
2061 if (is_signed
&& (offset
& sign_bit
))
2062 offset
= 0 - (max_imm
- offset
);
2063 return offset
* scale
;
2068 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2069 stream from start_pc to limit_pc. */
2072 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2073 struct frame_info
*next_frame
, CORE_ADDR sp
)
2076 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2077 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2078 unsigned inst
= 0; /* current instruction */
2079 unsigned entry_inst
= 0; /* the entry instruction */
2082 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2083 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2085 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2087 /* Save the previous instruction. If it's an EXTEND, we'll extract
2088 the immediate offset extension from it in mips16_get_imm. */
2091 /* Fetch and decode the instruction. */
2092 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2093 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2094 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2096 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2097 if (offset
< 0) /* negative stack adjustment? */
2098 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2100 /* Exit loop if a positive stack adjustment is found, which
2101 usually means that the stack cleanup code in the function
2102 epilogue is reached. */
2105 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2107 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2108 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2109 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2110 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2112 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2114 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2115 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2116 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2117 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2119 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2121 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2122 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2123 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2125 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2127 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2128 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2129 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2131 else if (inst
== 0x673d) /* move $s1, $sp */
2134 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2136 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2138 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2139 frame_addr
= sp
+ offset
;
2140 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2141 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2143 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2145 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2146 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2147 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2148 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2150 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2152 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2153 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2154 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2155 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2157 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2158 entry_inst
= inst
; /* save for later processing */
2159 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2160 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2163 /* The entry instruction is typically the first instruction in a function,
2164 and it stores registers at offsets relative to the value of the old SP
2165 (before the prologue). But the value of the sp parameter to this
2166 function is the new SP (after the prologue has been executed). So we
2167 can't calculate those offsets until we've seen the entire prologue,
2168 and can calculate what the old SP must have been. */
2169 if (entry_inst
!= 0)
2171 int areg_count
= (entry_inst
>> 8) & 7;
2172 int sreg_count
= (entry_inst
>> 6) & 3;
2174 /* The entry instruction always subtracts 32 from the SP. */
2175 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2177 /* Now we can calculate what the SP must have been at the
2178 start of the function prologue. */
2179 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2181 /* Check if a0-a3 were saved in the caller's argument save area. */
2182 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2184 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2185 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2186 offset
+= MIPS_SAVED_REGSIZE
;
2189 /* Check if the ra register was pushed on the stack. */
2191 if (entry_inst
& 0x20)
2193 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2194 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2195 offset
-= MIPS_SAVED_REGSIZE
;
2198 /* Check if the s0 and s1 registers were pushed on the stack. */
2199 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2201 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2202 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2203 offset
-= MIPS_SAVED_REGSIZE
;
2209 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2210 struct frame_info
*next_frame
, CORE_ADDR sp
)
2213 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2215 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2216 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2217 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2218 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2219 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2221 unsigned long inst
, high_word
, low_word
;
2224 /* Fetch the instruction. */
2225 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2227 /* Save some code by pre-extracting some useful fields. */
2228 high_word
= (inst
>> 16) & 0xffff;
2229 low_word
= inst
& 0xffff;
2230 reg
= high_word
& 0x1f;
2232 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2233 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2234 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2236 if (low_word
& 0x8000) /* negative stack adjustment? */
2237 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2239 /* Exit loop if a positive stack adjustment is found, which
2240 usually means that the stack cleanup code in the function
2241 epilogue is reached. */
2244 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2246 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2247 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2249 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2251 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2252 but the register size used is only 32 bits. Make the address
2253 for the saved register point to the lower 32 bits. */
2254 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2255 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
2257 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2259 /* Old gcc frame, r30 is virtual frame pointer. */
2260 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2261 frame_addr
= sp
+ low_word
;
2262 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2264 unsigned alloca_adjust
;
2265 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2266 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2267 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2268 if (alloca_adjust
> 0)
2270 /* FP > SP + frame_size. This may be because
2271 * of an alloca or somethings similar.
2272 * Fix sp to "pre-alloca" value, and try again.
2274 sp
+= alloca_adjust
;
2279 /* move $30,$sp. With different versions of gas this will be either
2280 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2281 Accept any one of these. */
2282 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2284 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2285 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2287 unsigned alloca_adjust
;
2288 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2289 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2290 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2291 if (alloca_adjust
> 0)
2293 /* FP > SP + frame_size. This may be because
2294 * of an alloca or somethings similar.
2295 * Fix sp to "pre-alloca" value, and try again.
2297 sp
+= alloca_adjust
;
2302 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2304 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2305 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2310 static mips_extra_func_info_t
2311 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2312 struct frame_info
*next_frame
, int cur_frame
)
2317 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2323 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2324 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2325 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2326 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2327 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2328 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2330 if (start_pc
+ 200 < limit_pc
)
2331 limit_pc
= start_pc
+ 200;
2332 if (pc_is_mips16 (start_pc
))
2333 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2335 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2336 return &temp_proc_desc
;
2339 struct mips_objfile_private
2345 /* Global used to communicate between non_heuristic_proc_desc and
2346 compare_pdr_entries within qsort (). */
2347 static bfd
*the_bfd
;
2350 compare_pdr_entries (const void *a
, const void *b
)
2352 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2353 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2357 else if (lhs
== rhs
)
2363 static mips_extra_func_info_t
2364 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2366 CORE_ADDR startaddr
;
2367 mips_extra_func_info_t proc_desc
;
2368 struct block
*b
= block_for_pc (pc
);
2370 struct obj_section
*sec
;
2371 struct mips_objfile_private
*priv
;
2373 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2376 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2378 *addrptr
= startaddr
;
2382 sec
= find_pc_section (pc
);
2385 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2387 /* Search the ".pdr" section generated by GAS. This includes most of
2388 the information normally found in ECOFF PDRs. */
2390 the_bfd
= sec
->objfile
->obfd
;
2392 && (the_bfd
->format
== bfd_object
2393 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2394 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2396 /* Right now GAS only outputs the address as a four-byte sequence.
2397 This means that we should not bother with this method on 64-bit
2398 targets (until that is fixed). */
2400 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2401 sizeof (struct mips_objfile_private
));
2403 sec
->objfile
->obj_private
= priv
;
2405 else if (priv
== NULL
)
2409 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2410 sizeof (struct mips_objfile_private
));
2412 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2415 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2416 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2418 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2419 priv
->contents
, 0, priv
->size
);
2421 /* In general, the .pdr section is sorted. However, in the
2422 presence of multiple code sections (and other corner cases)
2423 it can become unsorted. Sort it so that we can use a faster
2425 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
2430 sec
->objfile
->obj_private
= priv
;
2434 if (priv
->size
!= 0)
2440 high
= priv
->size
/ 32;
2446 mid
= (low
+ high
) / 2;
2448 ptr
= priv
->contents
+ mid
* 32;
2449 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2450 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2451 SECT_OFF_TEXT (sec
->objfile
));
2452 if (pdr_pc
== startaddr
)
2454 if (pdr_pc
> startaddr
)
2459 while (low
!= high
);
2463 struct symbol
*sym
= find_pc_function (pc
);
2465 /* Fill in what we need of the proc_desc. */
2466 proc_desc
= (mips_extra_func_info_t
)
2467 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2468 sizeof (struct mips_extra_func_info
));
2469 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2471 /* Only used for dummy frames. */
2472 PROC_HIGH_ADDR (proc_desc
) = 0;
2474 PROC_FRAME_OFFSET (proc_desc
)
2475 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2476 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2478 PROC_FRAME_ADJUST (proc_desc
) = 0;
2479 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2481 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2483 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2485 PROC_FREG_OFFSET (proc_desc
)
2486 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2487 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2489 proc_desc
->pdr
.isym
= (long) sym
;
2499 if (startaddr
> BLOCK_START (b
))
2501 /* This is the "pathological" case referred to in a comment in
2502 print_frame_info. It might be better to move this check into
2507 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2509 /* If we never found a PDR for this function in symbol reading, then
2510 examine prologues to find the information. */
2513 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2514 if (PROC_FRAME_REG (proc_desc
) == -1)
2524 static mips_extra_func_info_t
2525 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2527 mips_extra_func_info_t proc_desc
;
2528 CORE_ADDR startaddr
= 0;
2530 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2534 /* IF this is the topmost frame AND
2535 * (this proc does not have debugging information OR
2536 * the PC is in the procedure prologue)
2537 * THEN create a "heuristic" proc_desc (by analyzing
2538 * the actual code) to replace the "official" proc_desc.
2540 if (next_frame
== NULL
)
2542 struct symtab_and_line val
;
2543 struct symbol
*proc_symbol
=
2544 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2548 val
= find_pc_line (BLOCK_START
2549 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2551 val
.pc
= val
.end
? val
.end
: pc
;
2553 if (!proc_symbol
|| pc
< val
.pc
)
2555 mips_extra_func_info_t found_heuristic
=
2556 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2557 pc
, next_frame
, cur_frame
);
2558 if (found_heuristic
)
2559 proc_desc
= found_heuristic
;
2565 /* Is linked_proc_desc_table really necessary? It only seems to be used
2566 by procedure call dummys. However, the procedures being called ought
2567 to have their own proc_descs, and even if they don't,
2568 heuristic_proc_desc knows how to create them! */
2570 struct linked_proc_info
*link
;
2572 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2573 if (PROC_LOW_ADDR (&link
->info
) <= pc
2574 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2578 startaddr
= heuristic_proc_start (pc
);
2581 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2587 get_frame_pointer (struct frame_info
*frame
,
2588 mips_extra_func_info_t proc_desc
)
2590 return (read_next_frame_reg (frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2591 + PROC_FRAME_OFFSET (proc_desc
)
2592 - PROC_FRAME_ADJUST (proc_desc
));
2595 static mips_extra_func_info_t cached_proc_desc
;
2598 mips_frame_chain (struct frame_info
*frame
)
2600 mips_extra_func_info_t proc_desc
;
2602 CORE_ADDR saved_pc
= DEPRECATED_FRAME_SAVED_PC (frame
);
2604 if (saved_pc
== 0 || deprecated_inside_entry_file (saved_pc
))
2607 /* Check if the PC is inside a call stub. If it is, fetch the
2608 PC of the caller of that stub. */
2609 if ((tmp
= SKIP_TRAMPOLINE_CODE (saved_pc
)) != 0)
2612 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc
, 0, 0))
2614 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2615 is well, frame->frame the bottom of the current frame will
2616 contain that value. */
2617 return get_frame_base (frame
);
2620 /* Look up the procedure descriptor for this PC. */
2621 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2625 cached_proc_desc
= proc_desc
;
2627 /* If no frame pointer and frame size is zero, we must be at end
2628 of stack (or otherwise hosed). If we don't check frame size,
2629 we loop forever if we see a zero size frame. */
2630 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2631 && PROC_FRAME_OFFSET (proc_desc
) == 0
2632 /* The previous frame from a sigtramp frame might be frameless
2633 and have frame size zero. */
2634 && !(get_frame_type (frame
) == SIGTRAMP_FRAME
)
2635 /* For a generic dummy frame, let get_frame_pointer() unwind a
2636 register value saved as part of the dummy frame call. */
2637 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0)))
2640 return get_frame_pointer (frame
, proc_desc
);
2644 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2647 mips_extra_func_info_t proc_desc
;
2649 if (get_frame_type (fci
) == DUMMY_FRAME
)
2652 /* Use proc_desc calculated in frame_chain. When there is no
2653 next frame, i.e, get_next_frame (fci) == NULL, we call
2654 find_proc_desc () to calculate it, passing an explicit
2655 NULL as the frame parameter. */
2657 get_next_frame (fci
)
2659 : find_proc_desc (get_frame_pc (fci
),
2660 NULL
/* i.e, get_next_frame (fci) */,
2663 frame_extra_info_zalloc (fci
, sizeof (struct frame_extra_info
));
2665 deprecated_set_frame_saved_regs_hack (fci
, NULL
);
2666 get_frame_extra_info (fci
)->proc_desc
=
2667 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2670 /* Fixup frame-pointer - only needed for top frame */
2671 /* This may not be quite right, if proc has a real frame register.
2672 Get the value of the frame relative sp, procedure might have been
2673 interrupted by a signal at it's very start. */
2674 if (get_frame_pc (fci
) == PROC_LOW_ADDR (proc_desc
)
2675 && !PROC_DESC_IS_DUMMY (proc_desc
))
2676 deprecated_update_frame_base_hack (fci
, read_next_frame_reg (get_next_frame (fci
), NUM_REGS
+ SP_REGNUM
));
2677 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci
), 0, 0))
2678 /* Do not ``fix'' fci->frame. It will have the value of the
2679 generic dummy frame's top-of-stack (since the draft
2680 fci->frame is obtained by returning the unwound stack
2681 pointer) and that is what we want. That way the fci->frame
2682 value will match the top-of-stack value that was saved as
2683 part of the dummy frames data. */
2686 deprecated_update_frame_base_hack (fci
, get_frame_pointer (get_next_frame (fci
), proc_desc
));
2688 if (proc_desc
== &temp_proc_desc
)
2692 /* Do not set the saved registers for a sigtramp frame,
2693 mips_find_saved_registers will do that for us. We can't
2694 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2696 /* FIXME: cagney/2002-11-18: This problem will go away once
2697 frame.c:get_prev_frame() is modified to set the frame's
2698 type before calling functions like this. */
2699 find_pc_partial_function (get_frame_pc (fci
), &name
,
2700 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2701 if (!PC_IN_SIGTRAMP (get_frame_pc (fci
), name
))
2703 frame_saved_regs_zalloc (fci
);
2704 /* Set value of previous frame's stack pointer.
2705 Remember that saved_regs[SP_REGNUM] is special in
2706 that it contains the value of the stack pointer
2707 register. The other saved_regs values are addresses
2708 (in the inferior) at which a given register's value
2710 set_reg_offset (temp_saved_regs
, SP_REGNUM
,
2711 get_frame_base (fci
));
2712 set_reg_offset (temp_saved_regs
, PC_REGNUM
,
2713 temp_saved_regs
[RA_REGNUM
]);
2714 memcpy (deprecated_get_frame_saved_regs (fci
), temp_saved_regs
,
2715 SIZEOF_FRAME_SAVED_REGS
);
2719 /* hack: if argument regs are saved, guess these contain args */
2720 /* assume we can't tell how many args for now */
2721 get_frame_extra_info (fci
)->num_args
= -1;
2722 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2724 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2726 get_frame_extra_info (fci
)->num_args
= regnum
- A0_REGNUM
+ 1;
2733 /* MIPS stack frames are almost impenetrable. When execution stops,
2734 we basically have to look at symbol information for the function
2735 that we stopped in, which tells us *which* register (if any) is
2736 the base of the frame pointer, and what offset from that register
2737 the frame itself is at.
2739 This presents a problem when trying to examine a stack in memory
2740 (that isn't executing at the moment), using the "frame" command. We
2741 don't have a PC, nor do we have any registers except SP.
2743 This routine takes two arguments, SP and PC, and tries to make the
2744 cached frames look as if these two arguments defined a frame on the
2745 cache. This allows the rest of info frame to extract the important
2746 arguments without difficulty. */
2749 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2752 error ("MIPS frame specifications require two arguments: sp and pc");
2754 return create_new_frame (argv
[0], argv
[1]);
2757 /* According to the current ABI, should the type be passed in a
2758 floating-point register (assuming that there is space)? When there
2759 is no FPU, FP are not even considered as possibile candidates for
2760 FP registers and, consequently this returns false - forces FP
2761 arguments into integer registers. */
2764 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2766 return ((typecode
== TYPE_CODE_FLT
2768 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2769 && TYPE_NFIELDS (arg_type
) == 1
2770 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2771 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2774 /* On o32, argument passing in GPRs depends on the alignment of the type being
2775 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2778 mips_type_needs_double_align (struct type
*type
)
2780 enum type_code typecode
= TYPE_CODE (type
);
2782 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2784 else if (typecode
== TYPE_CODE_STRUCT
)
2786 if (TYPE_NFIELDS (type
) < 1)
2788 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2790 else if (typecode
== TYPE_CODE_UNION
)
2794 n
= TYPE_NFIELDS (type
);
2795 for (i
= 0; i
< n
; i
++)
2796 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2803 /* Adjust the address downward (direction of stack growth) so that it
2804 is correctly aligned for a new stack frame. */
2806 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2808 return align_down (addr
, 16);
2812 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2813 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2814 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2815 CORE_ADDR struct_addr
)
2821 int stack_offset
= 0;
2823 /* For shared libraries, "t9" needs to point at the function
2825 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2827 /* Set the return address register to point to the entry point of
2828 the program, where a breakpoint lies in wait. */
2829 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2831 /* First ensure that the stack and structure return address (if any)
2832 are properly aligned. The stack has to be at least 64-bit
2833 aligned even on 32-bit machines, because doubles must be 64-bit
2834 aligned. For n32 and n64, stack frames need to be 128-bit
2835 aligned, so we round to this widest known alignment. */
2837 sp
= align_down (sp
, 16);
2838 struct_addr
= align_down (struct_addr
, 16);
2840 /* Now make space on the stack for the args. We allocate more
2841 than necessary for EABI, because the first few arguments are
2842 passed in registers, but that's OK. */
2843 for (argnum
= 0; argnum
< nargs
; argnum
++)
2844 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2845 MIPS_STACK_ARGSIZE
);
2846 sp
-= align_up (len
, 16);
2849 fprintf_unfiltered (gdb_stdlog
,
2850 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2851 paddr_nz (sp
), (long) align_up (len
, 16));
2853 /* Initialize the integer and float register pointers. */
2855 float_argreg
= FPA0_REGNUM
;
2857 /* The struct_return pointer occupies the first parameter-passing reg. */
2861 fprintf_unfiltered (gdb_stdlog
,
2862 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2863 argreg
, paddr_nz (struct_addr
));
2864 write_register (argreg
++, struct_addr
);
2867 /* Now load as many as possible of the first arguments into
2868 registers, and push the rest onto the stack. Loop thru args
2869 from first to last. */
2870 for (argnum
= 0; argnum
< nargs
; argnum
++)
2873 char valbuf
[MAX_REGISTER_SIZE
];
2874 struct value
*arg
= args
[argnum
];
2875 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2876 int len
= TYPE_LENGTH (arg_type
);
2877 enum type_code typecode
= TYPE_CODE (arg_type
);
2880 fprintf_unfiltered (gdb_stdlog
,
2881 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2882 argnum
+ 1, len
, (int) typecode
);
2884 /* The EABI passes structures that do not fit in a register by
2886 if (len
> MIPS_SAVED_REGSIZE
2887 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2889 store_unsigned_integer (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2890 typecode
= TYPE_CODE_PTR
;
2891 len
= MIPS_SAVED_REGSIZE
;
2894 fprintf_unfiltered (gdb_stdlog
, " push");
2897 val
= (char *) VALUE_CONTENTS (arg
);
2899 /* 32-bit ABIs always start floating point arguments in an
2900 even-numbered floating point register. Round the FP register
2901 up before the check to see if there are any FP registers
2902 left. Non MIPS_EABI targets also pass the FP in the integer
2903 registers so also round up normal registers. */
2904 if (!FP_REGISTER_DOUBLE
2905 && fp_register_arg_p (typecode
, arg_type
))
2907 if ((float_argreg
& 1))
2911 /* Floating point arguments passed in registers have to be
2912 treated specially. On 32-bit architectures, doubles
2913 are passed in register pairs; the even register gets
2914 the low word, and the odd register gets the high word.
2915 On non-EABI processors, the first two floating point arguments are
2916 also copied to general registers, because MIPS16 functions
2917 don't use float registers for arguments. This duplication of
2918 arguments in general registers can't hurt non-MIPS16 functions
2919 because those registers are normally skipped. */
2920 /* MIPS_EABI squeezes a struct that contains a single floating
2921 point value into an FP register instead of pushing it onto the
2923 if (fp_register_arg_p (typecode
, arg_type
)
2924 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2926 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2928 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2929 unsigned long regval
;
2931 /* Write the low word of the double to the even register(s). */
2932 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2934 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2935 float_argreg
, phex (regval
, 4));
2936 write_register (float_argreg
++, regval
);
2938 /* Write the high word of the double to the odd register(s). */
2939 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2941 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2942 float_argreg
, phex (regval
, 4));
2943 write_register (float_argreg
++, regval
);
2947 /* This is a floating point value that fits entirely
2948 in a single register. */
2949 /* On 32 bit ABI's the float_argreg is further adjusted
2950 above to ensure that it is even register aligned. */
2951 LONGEST regval
= extract_unsigned_integer (val
, len
);
2953 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2954 float_argreg
, phex (regval
, len
));
2955 write_register (float_argreg
++, regval
);
2960 /* Copy the argument to general registers or the stack in
2961 register-sized pieces. Large arguments are split between
2962 registers and stack. */
2963 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2964 are treated specially: Irix cc passes them in registers
2965 where gcc sometimes puts them on the stack. For maximum
2966 compatibility, we will put them in both places. */
2967 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2968 (len
% MIPS_SAVED_REGSIZE
!= 0));
2970 /* Note: Floating-point values that didn't fit into an FP
2971 register are only written to memory. */
2974 /* Remember if the argument was written to the stack. */
2975 int stack_used_p
= 0;
2977 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2980 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2983 /* Write this portion of the argument to the stack. */
2984 if (argreg
> MIPS_LAST_ARG_REGNUM
2986 || fp_register_arg_p (typecode
, arg_type
))
2988 /* Should shorter than int integer values be
2989 promoted to int before being stored? */
2990 int longword_offset
= 0;
2993 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2995 if (MIPS_STACK_ARGSIZE
== 8 &&
2996 (typecode
== TYPE_CODE_INT
||
2997 typecode
== TYPE_CODE_PTR
||
2998 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2999 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3000 else if ((typecode
== TYPE_CODE_STRUCT
||
3001 typecode
== TYPE_CODE_UNION
) &&
3002 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
3003 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3008 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3009 paddr_nz (stack_offset
));
3010 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3011 paddr_nz (longword_offset
));
3014 addr
= sp
+ stack_offset
+ longword_offset
;
3019 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3021 for (i
= 0; i
< partial_len
; i
++)
3023 fprintf_unfiltered (gdb_stdlog
, "%02x",
3027 write_memory (addr
, val
, partial_len
);
3030 /* Note!!! This is NOT an else clause. Odd sized
3031 structs may go thru BOTH paths. Floating point
3032 arguments will not. */
3033 /* Write this portion of the argument to a general
3034 purpose register. */
3035 if (argreg
<= MIPS_LAST_ARG_REGNUM
3036 && !fp_register_arg_p (typecode
, arg_type
))
3038 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
3041 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3043 phex (regval
, MIPS_SAVED_REGSIZE
));
3044 write_register (argreg
, regval
);
3051 /* Compute the the offset into the stack at which we
3052 will copy the next parameter.
3054 In the new EABI (and the NABI32), the stack_offset
3055 only needs to be adjusted when it has been used. */
3058 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3062 fprintf_unfiltered (gdb_stdlog
, "\n");
3065 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3067 /* Return adjusted stack pointer. */
3071 /* N32/N64 version of push_dummy_call. */
3074 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3075 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3076 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3077 CORE_ADDR struct_addr
)
3083 int stack_offset
= 0;
3085 /* For shared libraries, "t9" needs to point at the function
3087 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3089 /* Set the return address register to point to the entry point of
3090 the program, where a breakpoint lies in wait. */
3091 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3093 /* First ensure that the stack and structure return address (if any)
3094 are properly aligned. The stack has to be at least 64-bit
3095 aligned even on 32-bit machines, because doubles must be 64-bit
3096 aligned. For n32 and n64, stack frames need to be 128-bit
3097 aligned, so we round to this widest known alignment. */
3099 sp
= align_down (sp
, 16);
3100 struct_addr
= align_down (struct_addr
, 16);
3102 /* Now make space on the stack for the args. */
3103 for (argnum
= 0; argnum
< nargs
; argnum
++)
3104 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3105 MIPS_STACK_ARGSIZE
);
3106 sp
-= align_up (len
, 16);
3109 fprintf_unfiltered (gdb_stdlog
,
3110 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3111 paddr_nz (sp
), (long) align_up (len
, 16));
3113 /* Initialize the integer and float register pointers. */
3115 float_argreg
= FPA0_REGNUM
;
3117 /* The struct_return pointer occupies the first parameter-passing reg. */
3121 fprintf_unfiltered (gdb_stdlog
,
3122 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3123 argreg
, paddr_nz (struct_addr
));
3124 write_register (argreg
++, struct_addr
);
3127 /* Now load as many as possible of the first arguments into
3128 registers, and push the rest onto the stack. Loop thru args
3129 from first to last. */
3130 for (argnum
= 0; argnum
< nargs
; argnum
++)
3133 char valbuf
[MAX_REGISTER_SIZE
];
3134 struct value
*arg
= args
[argnum
];
3135 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3136 int len
= TYPE_LENGTH (arg_type
);
3137 enum type_code typecode
= TYPE_CODE (arg_type
);
3140 fprintf_unfiltered (gdb_stdlog
,
3141 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3142 argnum
+ 1, len
, (int) typecode
);
3144 val
= (char *) VALUE_CONTENTS (arg
);
3146 if (fp_register_arg_p (typecode
, arg_type
)
3147 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3149 /* This is a floating point value that fits entirely
3150 in a single register. */
3151 /* On 32 bit ABI's the float_argreg is further adjusted
3152 above to ensure that it is even register aligned. */
3153 LONGEST regval
= extract_unsigned_integer (val
, len
);
3155 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3156 float_argreg
, phex (regval
, len
));
3157 write_register (float_argreg
++, regval
);
3160 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3161 argreg
, phex (regval
, len
));
3162 write_register (argreg
, regval
);
3167 /* Copy the argument to general registers or the stack in
3168 register-sized pieces. Large arguments are split between
3169 registers and stack. */
3170 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3171 are treated specially: Irix cc passes them in registers
3172 where gcc sometimes puts them on the stack. For maximum
3173 compatibility, we will put them in both places. */
3174 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3175 (len
% MIPS_SAVED_REGSIZE
!= 0));
3176 /* Note: Floating-point values that didn't fit into an FP
3177 register are only written to memory. */
3180 /* Rememer if the argument was written to the stack. */
3181 int stack_used_p
= 0;
3182 int partial_len
= len
< MIPS_SAVED_REGSIZE
?
3183 len
: MIPS_SAVED_REGSIZE
;
3186 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3189 /* Write this portion of the argument to the stack. */
3190 if (argreg
> MIPS_LAST_ARG_REGNUM
3192 || fp_register_arg_p (typecode
, arg_type
))
3194 /* Should shorter than int integer values be
3195 promoted to int before being stored? */
3196 int longword_offset
= 0;
3199 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3201 if (MIPS_STACK_ARGSIZE
== 8 &&
3202 (typecode
== TYPE_CODE_INT
||
3203 typecode
== TYPE_CODE_PTR
||
3204 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3205 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3210 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3211 paddr_nz (stack_offset
));
3212 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3213 paddr_nz (longword_offset
));
3216 addr
= sp
+ stack_offset
+ longword_offset
;
3221 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3223 for (i
= 0; i
< partial_len
; i
++)
3225 fprintf_unfiltered (gdb_stdlog
, "%02x",
3229 write_memory (addr
, val
, partial_len
);
3232 /* Note!!! This is NOT an else clause. Odd sized
3233 structs may go thru BOTH paths. Floating point
3234 arguments will not. */
3235 /* Write this portion of the argument to a general
3236 purpose register. */
3237 if (argreg
<= MIPS_LAST_ARG_REGNUM
3238 && !fp_register_arg_p (typecode
, arg_type
))
3240 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
3242 /* A non-floating-point argument being passed in a
3243 general register. If a struct or union, and if
3244 the remaining length is smaller than the register
3245 size, we have to adjust the register value on
3248 It does not seem to be necessary to do the
3249 same for integral types.
3251 cagney/2001-07-23: gdb/179: Also, GCC, when
3252 outputting LE O32 with sizeof (struct) <
3253 MIPS_SAVED_REGSIZE, generates a left shift as
3254 part of storing the argument in a register a
3255 register (the left shift isn't generated when
3256 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3257 is quite possible that this is GCC contradicting
3258 the LE/O32 ABI, GDB has not been adjusted to
3259 accommodate this. Either someone needs to
3260 demonstrate that the LE/O32 ABI specifies such a
3261 left shift OR this new ABI gets identified as
3262 such and GDB gets tweaked accordingly. */
3264 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3265 && partial_len
< MIPS_SAVED_REGSIZE
3266 && (typecode
== TYPE_CODE_STRUCT
||
3267 typecode
== TYPE_CODE_UNION
))
3268 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3272 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3274 phex (regval
, MIPS_SAVED_REGSIZE
));
3275 write_register (argreg
, regval
);
3282 /* Compute the the offset into the stack at which we
3283 will copy the next parameter.
3285 In N32 (N64?), the stack_offset only needs to be
3286 adjusted when it has been used. */
3289 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3293 fprintf_unfiltered (gdb_stdlog
, "\n");
3296 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3298 /* Return adjusted stack pointer. */
3302 /* O32 version of push_dummy_call. */
3305 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3306 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3307 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3308 CORE_ADDR struct_addr
)
3314 int stack_offset
= 0;
3316 /* For shared libraries, "t9" needs to point at the function
3318 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3320 /* Set the return address register to point to the entry point of
3321 the program, where a breakpoint lies in wait. */
3322 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3324 /* First ensure that the stack and structure return address (if any)
3325 are properly aligned. The stack has to be at least 64-bit
3326 aligned even on 32-bit machines, because doubles must be 64-bit
3327 aligned. For n32 and n64, stack frames need to be 128-bit
3328 aligned, so we round to this widest known alignment. */
3330 sp
= align_down (sp
, 16);
3331 struct_addr
= align_down (struct_addr
, 16);
3333 /* Now make space on the stack for the args. */
3334 for (argnum
= 0; argnum
< nargs
; argnum
++)
3335 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3336 MIPS_STACK_ARGSIZE
);
3337 sp
-= align_up (len
, 16);
3340 fprintf_unfiltered (gdb_stdlog
,
3341 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3342 paddr_nz (sp
), (long) align_up (len
, 16));
3344 /* Initialize the integer and float register pointers. */
3346 float_argreg
= FPA0_REGNUM
;
3348 /* The struct_return pointer occupies the first parameter-passing reg. */
3352 fprintf_unfiltered (gdb_stdlog
,
3353 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3354 argreg
, paddr_nz (struct_addr
));
3355 write_register (argreg
++, struct_addr
);
3356 stack_offset
+= MIPS_STACK_ARGSIZE
;
3359 /* Now load as many as possible of the first arguments into
3360 registers, and push the rest onto the stack. Loop thru args
3361 from first to last. */
3362 for (argnum
= 0; argnum
< nargs
; argnum
++)
3365 char valbuf
[MAX_REGISTER_SIZE
];
3366 struct value
*arg
= args
[argnum
];
3367 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3368 int len
= TYPE_LENGTH (arg_type
);
3369 enum type_code typecode
= TYPE_CODE (arg_type
);
3372 fprintf_unfiltered (gdb_stdlog
,
3373 "mips_o32_push_dummy_call: %d len=%d type=%d",
3374 argnum
+ 1, len
, (int) typecode
);
3376 val
= (char *) VALUE_CONTENTS (arg
);
3378 /* 32-bit ABIs always start floating point arguments in an
3379 even-numbered floating point register. Round the FP register
3380 up before the check to see if there are any FP registers
3381 left. O32/O64 targets also pass the FP in the integer
3382 registers so also round up normal registers. */
3383 if (!FP_REGISTER_DOUBLE
3384 && fp_register_arg_p (typecode
, arg_type
))
3386 if ((float_argreg
& 1))
3390 /* Floating point arguments passed in registers have to be
3391 treated specially. On 32-bit architectures, doubles
3392 are passed in register pairs; the even register gets
3393 the low word, and the odd register gets the high word.
3394 On O32/O64, the first two floating point arguments are
3395 also copied to general registers, because MIPS16 functions
3396 don't use float registers for arguments. This duplication of
3397 arguments in general registers can't hurt non-MIPS16 functions
3398 because those registers are normally skipped. */
3400 if (fp_register_arg_p (typecode
, arg_type
)
3401 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3403 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3405 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3406 unsigned long regval
;
3408 /* Write the low word of the double to the even register(s). */
3409 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3411 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3412 float_argreg
, phex (regval
, 4));
3413 write_register (float_argreg
++, regval
);
3415 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3416 argreg
, phex (regval
, 4));
3417 write_register (argreg
++, regval
);
3419 /* Write the high word of the double to the odd register(s). */
3420 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3422 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3423 float_argreg
, phex (regval
, 4));
3424 write_register (float_argreg
++, regval
);
3427 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3428 argreg
, phex (regval
, 4));
3429 write_register (argreg
++, regval
);
3433 /* This is a floating point value that fits entirely
3434 in a single register. */
3435 /* On 32 bit ABI's the float_argreg is further adjusted
3436 above to ensure that it is even register aligned. */
3437 LONGEST regval
= extract_unsigned_integer (val
, len
);
3439 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3440 float_argreg
, phex (regval
, len
));
3441 write_register (float_argreg
++, regval
);
3442 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3443 registers for each argument. The below is (my
3444 guess) to ensure that the corresponding integer
3445 register has reserved the same space. */
3447 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3448 argreg
, phex (regval
, len
));
3449 write_register (argreg
, regval
);
3450 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3452 /* Reserve space for the FP register. */
3453 stack_offset
+= align_up (len
, MIPS_STACK_ARGSIZE
);
3457 /* Copy the argument to general registers or the stack in
3458 register-sized pieces. Large arguments are split between
3459 registers and stack. */
3460 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3461 are treated specially: Irix cc passes them in registers
3462 where gcc sometimes puts them on the stack. For maximum
3463 compatibility, we will put them in both places. */
3464 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3465 (len
% MIPS_SAVED_REGSIZE
!= 0));
3466 /* Structures should be aligned to eight bytes (even arg registers)
3467 on MIPS_ABI_O32, if their first member has double precision. */
3468 if (MIPS_SAVED_REGSIZE
< 8
3469 && mips_type_needs_double_align (arg_type
))
3474 /* Note: Floating-point values that didn't fit into an FP
3475 register are only written to memory. */
3478 /* Remember if the argument was written to the stack. */
3479 int stack_used_p
= 0;
3481 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3484 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3487 /* Write this portion of the argument to the stack. */
3488 if (argreg
> MIPS_LAST_ARG_REGNUM
3490 || fp_register_arg_p (typecode
, arg_type
))
3492 /* Should shorter than int integer values be
3493 promoted to int before being stored? */
3494 int longword_offset
= 0;
3497 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3499 if (MIPS_STACK_ARGSIZE
== 8 &&
3500 (typecode
== TYPE_CODE_INT
||
3501 typecode
== TYPE_CODE_PTR
||
3502 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3503 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3508 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3509 paddr_nz (stack_offset
));
3510 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3511 paddr_nz (longword_offset
));
3514 addr
= sp
+ stack_offset
+ longword_offset
;
3519 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3521 for (i
= 0; i
< partial_len
; i
++)
3523 fprintf_unfiltered (gdb_stdlog
, "%02x",
3527 write_memory (addr
, val
, partial_len
);
3530 /* Note!!! This is NOT an else clause. Odd sized
3531 structs may go thru BOTH paths. Floating point
3532 arguments will not. */
3533 /* Write this portion of the argument to a general
3534 purpose register. */
3535 if (argreg
<= MIPS_LAST_ARG_REGNUM
3536 && !fp_register_arg_p (typecode
, arg_type
))
3538 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3539 /* Value may need to be sign extended, because
3540 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3542 /* A non-floating-point argument being passed in a
3543 general register. If a struct or union, and if
3544 the remaining length is smaller than the register
3545 size, we have to adjust the register value on
3548 It does not seem to be necessary to do the
3549 same for integral types.
3551 Also don't do this adjustment on O64 binaries.
3553 cagney/2001-07-23: gdb/179: Also, GCC, when
3554 outputting LE O32 with sizeof (struct) <
3555 MIPS_SAVED_REGSIZE, generates a left shift as
3556 part of storing the argument in a register a
3557 register (the left shift isn't generated when
3558 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3559 is quite possible that this is GCC contradicting
3560 the LE/O32 ABI, GDB has not been adjusted to
3561 accommodate this. Either someone needs to
3562 demonstrate that the LE/O32 ABI specifies such a
3563 left shift OR this new ABI gets identified as
3564 such and GDB gets tweaked accordingly. */
3566 if (MIPS_SAVED_REGSIZE
< 8
3567 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3568 && partial_len
< MIPS_SAVED_REGSIZE
3569 && (typecode
== TYPE_CODE_STRUCT
||
3570 typecode
== TYPE_CODE_UNION
))
3571 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3575 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3577 phex (regval
, MIPS_SAVED_REGSIZE
));
3578 write_register (argreg
, regval
);
3581 /* Prevent subsequent floating point arguments from
3582 being passed in floating point registers. */
3583 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3589 /* Compute the the offset into the stack at which we
3590 will copy the next parameter.
3592 In older ABIs, the caller reserved space for
3593 registers that contained arguments. This was loosely
3594 refered to as their "home". Consequently, space is
3595 always allocated. */
3597 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3601 fprintf_unfiltered (gdb_stdlog
, "\n");
3604 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3606 /* Return adjusted stack pointer. */
3610 /* O64 version of push_dummy_call. */
3613 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3614 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3615 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3616 CORE_ADDR struct_addr
)
3622 int stack_offset
= 0;
3624 /* For shared libraries, "t9" needs to point at the function
3626 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3628 /* Set the return address register to point to the entry point of
3629 the program, where a breakpoint lies in wait. */
3630 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3632 /* First ensure that the stack and structure return address (if any)
3633 are properly aligned. The stack has to be at least 64-bit
3634 aligned even on 32-bit machines, because doubles must be 64-bit
3635 aligned. For n32 and n64, stack frames need to be 128-bit
3636 aligned, so we round to this widest known alignment. */
3638 sp
= align_down (sp
, 16);
3639 struct_addr
= align_down (struct_addr
, 16);
3641 /* Now make space on the stack for the args. */
3642 for (argnum
= 0; argnum
< nargs
; argnum
++)
3643 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3644 MIPS_STACK_ARGSIZE
);
3645 sp
-= align_up (len
, 16);
3648 fprintf_unfiltered (gdb_stdlog
,
3649 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3650 paddr_nz (sp
), (long) align_up (len
, 16));
3652 /* Initialize the integer and float register pointers. */
3654 float_argreg
= FPA0_REGNUM
;
3656 /* The struct_return pointer occupies the first parameter-passing reg. */
3660 fprintf_unfiltered (gdb_stdlog
,
3661 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3662 argreg
, paddr_nz (struct_addr
));
3663 write_register (argreg
++, struct_addr
);
3664 stack_offset
+= MIPS_STACK_ARGSIZE
;
3667 /* Now load as many as possible of the first arguments into
3668 registers, and push the rest onto the stack. Loop thru args
3669 from first to last. */
3670 for (argnum
= 0; argnum
< nargs
; argnum
++)
3673 char valbuf
[MAX_REGISTER_SIZE
];
3674 struct value
*arg
= args
[argnum
];
3675 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3676 int len
= TYPE_LENGTH (arg_type
);
3677 enum type_code typecode
= TYPE_CODE (arg_type
);
3680 fprintf_unfiltered (gdb_stdlog
,
3681 "mips_o64_push_dummy_call: %d len=%d type=%d",
3682 argnum
+ 1, len
, (int) typecode
);
3684 val
= (char *) VALUE_CONTENTS (arg
);
3686 /* 32-bit ABIs always start floating point arguments in an
3687 even-numbered floating point register. Round the FP register
3688 up before the check to see if there are any FP registers
3689 left. O32/O64 targets also pass the FP in the integer
3690 registers so also round up normal registers. */
3691 if (!FP_REGISTER_DOUBLE
3692 && fp_register_arg_p (typecode
, arg_type
))
3694 if ((float_argreg
& 1))
3698 /* Floating point arguments passed in registers have to be
3699 treated specially. On 32-bit architectures, doubles
3700 are passed in register pairs; the even register gets
3701 the low word, and the odd register gets the high word.
3702 On O32/O64, the first two floating point arguments are
3703 also copied to general registers, because MIPS16 functions
3704 don't use float registers for arguments. This duplication of
3705 arguments in general registers can't hurt non-MIPS16 functions
3706 because those registers are normally skipped. */
3708 if (fp_register_arg_p (typecode
, arg_type
)
3709 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3711 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3713 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3714 unsigned long regval
;
3716 /* Write the low word of the double to the even register(s). */
3717 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3719 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3720 float_argreg
, phex (regval
, 4));
3721 write_register (float_argreg
++, regval
);
3723 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3724 argreg
, phex (regval
, 4));
3725 write_register (argreg
++, regval
);
3727 /* Write the high word of the double to the odd register(s). */
3728 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3730 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3731 float_argreg
, phex (regval
, 4));
3732 write_register (float_argreg
++, regval
);
3735 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3736 argreg
, phex (regval
, 4));
3737 write_register (argreg
++, regval
);
3741 /* This is a floating point value that fits entirely
3742 in a single register. */
3743 /* On 32 bit ABI's the float_argreg is further adjusted
3744 above to ensure that it is even register aligned. */
3745 LONGEST regval
= extract_unsigned_integer (val
, len
);
3747 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3748 float_argreg
, phex (regval
, len
));
3749 write_register (float_argreg
++, regval
);
3750 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3751 registers for each argument. The below is (my
3752 guess) to ensure that the corresponding integer
3753 register has reserved the same space. */
3755 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3756 argreg
, phex (regval
, len
));
3757 write_register (argreg
, regval
);
3758 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3760 /* Reserve space for the FP register. */
3761 stack_offset
+= align_up (len
, MIPS_STACK_ARGSIZE
);
3765 /* Copy the argument to general registers or the stack in
3766 register-sized pieces. Large arguments are split between
3767 registers and stack. */
3768 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3769 are treated specially: Irix cc passes them in registers
3770 where gcc sometimes puts them on the stack. For maximum
3771 compatibility, we will put them in both places. */
3772 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3773 (len
% MIPS_SAVED_REGSIZE
!= 0));
3774 /* Structures should be aligned to eight bytes (even arg registers)
3775 on MIPS_ABI_O32, if their first member has double precision. */
3776 if (MIPS_SAVED_REGSIZE
< 8
3777 && mips_type_needs_double_align (arg_type
))
3782 /* Note: Floating-point values that didn't fit into an FP
3783 register are only written to memory. */
3786 /* Remember if the argument was written to the stack. */
3787 int stack_used_p
= 0;
3789 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3792 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3795 /* Write this portion of the argument to the stack. */
3796 if (argreg
> MIPS_LAST_ARG_REGNUM
3798 || fp_register_arg_p (typecode
, arg_type
))
3800 /* Should shorter than int integer values be
3801 promoted to int before being stored? */
3802 int longword_offset
= 0;
3805 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3807 if (MIPS_STACK_ARGSIZE
== 8 &&
3808 (typecode
== TYPE_CODE_INT
||
3809 typecode
== TYPE_CODE_PTR
||
3810 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3811 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3816 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3817 paddr_nz (stack_offset
));
3818 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3819 paddr_nz (longword_offset
));
3822 addr
= sp
+ stack_offset
+ longword_offset
;
3827 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3829 for (i
= 0; i
< partial_len
; i
++)
3831 fprintf_unfiltered (gdb_stdlog
, "%02x",
3835 write_memory (addr
, val
, partial_len
);
3838 /* Note!!! This is NOT an else clause. Odd sized
3839 structs may go thru BOTH paths. Floating point
3840 arguments will not. */
3841 /* Write this portion of the argument to a general
3842 purpose register. */
3843 if (argreg
<= MIPS_LAST_ARG_REGNUM
3844 && !fp_register_arg_p (typecode
, arg_type
))
3846 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3847 /* Value may need to be sign extended, because
3848 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3850 /* A non-floating-point argument being passed in a
3851 general register. If a struct or union, and if
3852 the remaining length is smaller than the register
3853 size, we have to adjust the register value on
3856 It does not seem to be necessary to do the
3857 same for integral types.
3859 Also don't do this adjustment on O64 binaries.
3861 cagney/2001-07-23: gdb/179: Also, GCC, when
3862 outputting LE O32 with sizeof (struct) <
3863 MIPS_SAVED_REGSIZE, generates a left shift as
3864 part of storing the argument in a register a
3865 register (the left shift isn't generated when
3866 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3867 is quite possible that this is GCC contradicting
3868 the LE/O32 ABI, GDB has not been adjusted to
3869 accommodate this. Either someone needs to
3870 demonstrate that the LE/O32 ABI specifies such a
3871 left shift OR this new ABI gets identified as
3872 such and GDB gets tweaked accordingly. */
3874 if (MIPS_SAVED_REGSIZE
< 8
3875 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3876 && partial_len
< MIPS_SAVED_REGSIZE
3877 && (typecode
== TYPE_CODE_STRUCT
||
3878 typecode
== TYPE_CODE_UNION
))
3879 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3883 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3885 phex (regval
, MIPS_SAVED_REGSIZE
));
3886 write_register (argreg
, regval
);
3889 /* Prevent subsequent floating point arguments from
3890 being passed in floating point registers. */
3891 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3897 /* Compute the the offset into the stack at which we
3898 will copy the next parameter.
3900 In older ABIs, the caller reserved space for
3901 registers that contained arguments. This was loosely
3902 refered to as their "home". Consequently, space is
3903 always allocated. */
3905 stack_offset
+= align_up (partial_len
, MIPS_STACK_ARGSIZE
);
3909 fprintf_unfiltered (gdb_stdlog
, "\n");
3912 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3914 /* Return adjusted stack pointer. */
3919 mips_pop_frame (void)
3922 struct frame_info
*frame
= get_current_frame ();
3923 CORE_ADDR new_sp
= get_frame_base (frame
);
3924 mips_extra_func_info_t proc_desc
;
3926 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
3928 generic_pop_dummy_frame ();
3929 flush_cached_frames ();
3933 proc_desc
= get_frame_extra_info (frame
)->proc_desc
;
3934 write_register (PC_REGNUM
, DEPRECATED_FRAME_SAVED_PC (frame
));
3935 mips_find_saved_regs (frame
);
3936 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
3937 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
3938 && deprecated_get_frame_saved_regs (frame
)[regnum
])
3940 /* Floating point registers must not be sign extended,
3941 in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */
3943 if (FP0_REGNUM
<= regnum
&& regnum
< FP0_REGNUM
+ 32)
3944 write_register (regnum
,
3945 read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3946 MIPS_SAVED_REGSIZE
));
3948 write_register (regnum
,
3949 read_memory_integer (deprecated_get_frame_saved_regs (frame
)[regnum
],
3950 MIPS_SAVED_REGSIZE
));
3953 write_register (SP_REGNUM
, new_sp
);
3954 flush_cached_frames ();
3956 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
3958 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
3960 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
3962 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
3964 if (&pi_ptr
->info
== proc_desc
)
3969 error ("Can't locate dummy extra frame info\n");
3971 if (prev_ptr
!= NULL
)
3972 prev_ptr
->next
= pi_ptr
->next
;
3974 linked_proc_desc_table
= pi_ptr
->next
;
3978 write_register (HI_REGNUM
,
3979 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
3980 MIPS_SAVED_REGSIZE
));
3981 write_register (LO_REGNUM
,
3982 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
3983 MIPS_SAVED_REGSIZE
));
3984 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
3985 write_register (FCRCS_REGNUM
,
3986 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
3987 MIPS_SAVED_REGSIZE
));
3991 /* Floating point register management.
3993 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3994 64bit operations, these early MIPS cpus treat fp register pairs
3995 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3996 registers and offer a compatibility mode that emulates the MIPS2 fp
3997 model. When operating in MIPS2 fp compat mode, later cpu's split
3998 double precision floats into two 32-bit chunks and store them in
3999 consecutive fp regs. To display 64-bit floats stored in this
4000 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4001 Throw in user-configurable endianness and you have a real mess.
4003 The way this works is:
4004 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4005 double-precision value will be split across two logical registers.
4006 The lower-numbered logical register will hold the low-order bits,
4007 regardless of the processor's endianness.
4008 - If we are on a 64-bit processor, and we are looking for a
4009 single-precision value, it will be in the low ordered bits
4010 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4011 save slot in memory.
4012 - If we are in 64-bit mode, everything is straightforward.
4014 Note that this code only deals with "live" registers at the top of the
4015 stack. We will attempt to deal with saved registers later, when
4016 the raw/cooked register interface is in place. (We need a general
4017 interface that can deal with dynamic saved register sizes -- fp
4018 regs could be 32 bits wide in one frame and 64 on the frame above
4021 static struct type
*
4022 mips_float_register_type (void)
4024 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4025 return builtin_type_ieee_single_big
;
4027 return builtin_type_ieee_single_little
;
4030 static struct type
*
4031 mips_double_register_type (void)
4033 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4034 return builtin_type_ieee_double_big
;
4036 return builtin_type_ieee_double_little
;
4039 /* Copy a 32-bit single-precision value from the current frame
4040 into rare_buffer. */
4043 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4046 int raw_size
= DEPRECATED_REGISTER_RAW_SIZE (regno
);
4047 char *raw_buffer
= alloca (raw_size
);
4049 if (!frame_register_read (frame
, regno
, raw_buffer
))
4050 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4053 /* We have a 64-bit value for this register. Find the low-order
4057 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4062 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4066 memcpy (rare_buffer
, raw_buffer
, 4);
4070 /* Copy a 64-bit double-precision value from the current frame into
4071 rare_buffer. This may include getting half of it from the next
4075 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4078 int raw_size
= DEPRECATED_REGISTER_RAW_SIZE (regno
);
4080 if (raw_size
== 8 && !mips2_fp_compat ())
4082 /* We have a 64-bit value for this register, and we should use
4084 if (!frame_register_read (frame
, regno
, rare_buffer
))
4085 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4089 if ((regno
- FP0_REGNUM
) & 1)
4090 internal_error (__FILE__
, __LINE__
,
4091 "mips_read_fp_register_double: bad access to "
4092 "odd-numbered FP register");
4094 /* mips_read_fp_register_single will find the correct 32 bits from
4096 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4098 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4099 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4103 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4104 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4110 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4112 { /* do values for FP (float) regs */
4114 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
4115 int inv1
, inv2
, namelen
;
4117 raw_buffer
= (char *) alloca (2 * DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM
));
4119 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4120 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4123 if (DEPRECATED_REGISTER_RAW_SIZE (regnum
) == 4 || mips2_fp_compat ())
4125 /* 4-byte registers: Print hex and floating. Also print even
4126 numbered registers as doubles. */
4127 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4128 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4130 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w', file
);
4132 fprintf_filtered (file
, " flt: ");
4134 fprintf_filtered (file
, " <invalid float> ");
4136 fprintf_filtered (file
, "%-17.9g", flt1
);
4138 if (regnum
% 2 == 0)
4140 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4141 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4144 fprintf_filtered (file
, " dbl: ");
4146 fprintf_filtered (file
, "<invalid double>");
4148 fprintf_filtered (file
, "%-24.17g", doub
);
4153 /* Eight byte registers: print each one as hex, float and double. */
4154 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4155 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4157 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4158 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4161 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g', file
);
4163 fprintf_filtered (file
, " flt: ");
4165 fprintf_filtered (file
, "<invalid float>");
4167 fprintf_filtered (file
, "%-17.9g", flt1
);
4169 fprintf_filtered (file
, " dbl: ");
4171 fprintf_filtered (file
, "<invalid double>");
4173 fprintf_filtered (file
, "%-24.17g", doub
);
4178 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4179 int regnum
, int all
)
4181 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4182 char raw_buffer
[MAX_REGISTER_SIZE
];
4185 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4187 mips_print_fp_register (file
, frame
, regnum
);
4191 /* Get the data in raw format. */
4192 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4194 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4198 fputs_filtered (REGISTER_NAME (regnum
), file
);
4200 /* The problem with printing numeric register names (r26, etc.) is that
4201 the user can't use them on input. Probably the best solution is to
4202 fix it so that either the numeric or the funky (a2, etc.) names
4203 are accepted on input. */
4204 if (regnum
< MIPS_NUMREGS
)
4205 fprintf_filtered (file
, "(r%d): ", regnum
);
4207 fprintf_filtered (file
, ": ");
4209 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4210 offset
= DEPRECATED_REGISTER_RAW_SIZE (regnum
) - DEPRECATED_REGISTER_VIRTUAL_SIZE (regnum
);
4214 print_scalar_formatted (raw_buffer
+ offset
, gdbarch_register_type (gdbarch
, regnum
),
4218 /* Replacement for generic do_registers_info.
4219 Print regs in pretty columns. */
4222 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4225 fprintf_filtered (file
, " ");
4226 mips_print_fp_register (file
, frame
, regnum
);
4227 fprintf_filtered (file
, "\n");
4232 /* Print a row's worth of GP (int) registers, with name labels above */
4235 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4238 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4239 /* do values for GP (int) regs */
4240 char raw_buffer
[MAX_REGISTER_SIZE
];
4241 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
4245 /* For GP registers, we print a separate row of names above the vals */
4246 fprintf_filtered (file
, " ");
4247 for (col
= 0, regnum
= start_regnum
;
4248 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4251 if (*REGISTER_NAME (regnum
) == '\0')
4252 continue; /* unused register */
4253 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4254 break; /* end the row: reached FP register */
4255 fprintf_filtered (file
, MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
4256 REGISTER_NAME (regnum
));
4259 /* print the R0 to R31 names */
4260 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4261 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4263 fprintf_filtered (file
, "\n ");
4265 /* now print the values in hex, 4 or 8 to the row */
4266 for (col
= 0, regnum
= start_regnum
;
4267 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
;
4270 if (*REGISTER_NAME (regnum
) == '\0')
4271 continue; /* unused register */
4272 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4273 break; /* end row: reached FP register */
4274 /* OK: get the data in raw format. */
4275 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4276 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4277 /* pad small registers */
4278 for (byte
= 0; byte
< (MIPS_REGSIZE
- DEPRECATED_REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
4279 printf_filtered (" ");
4280 /* Now print the register value in hex, endian order. */
4281 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4282 for (byte
= DEPRECATED_REGISTER_RAW_SIZE (regnum
) - DEPRECATED_REGISTER_VIRTUAL_SIZE (regnum
);
4283 byte
< DEPRECATED_REGISTER_RAW_SIZE (regnum
);
4285 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4287 for (byte
= DEPRECATED_REGISTER_VIRTUAL_SIZE (regnum
) - 1;
4290 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4291 fprintf_filtered (file
, " ");
4294 if (col
> 0) /* ie. if we actually printed anything... */
4295 fprintf_filtered (file
, "\n");
4300 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4303 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4304 struct frame_info
*frame
, int regnum
, int all
)
4306 if (regnum
!= -1) /* do one specified register */
4308 gdb_assert (regnum
>= NUM_REGS
);
4309 if (*(REGISTER_NAME (regnum
)) == '\0')
4310 error ("Not a valid register for the current processor type");
4312 mips_print_register (file
, frame
, regnum
, 0);
4313 fprintf_filtered (file
, "\n");
4316 /* do all (or most) registers */
4319 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4321 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4323 if (all
) /* true for "INFO ALL-REGISTERS" command */
4324 regnum
= print_fp_register_row (file
, frame
, regnum
);
4326 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4329 regnum
= print_gp_register_row (file
, frame
, regnum
);
4334 /* Is this a branch with a delay slot? */
4336 static int is_delayed (unsigned long);
4339 is_delayed (unsigned long insn
)
4342 for (i
= 0; i
< NUMOPCODES
; ++i
)
4343 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4344 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4346 return (i
< NUMOPCODES
4347 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4348 | INSN_COND_BRANCH_DELAY
4349 | INSN_COND_BRANCH_LIKELY
)));
4353 mips_step_skips_delay (CORE_ADDR pc
)
4355 char buf
[MIPS_INSTLEN
];
4357 /* There is no branch delay slot on MIPS16. */
4358 if (pc_is_mips16 (pc
))
4361 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4362 /* If error reading memory, guess that it is not a delayed branch. */
4364 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4368 /* Skip the PC past function prologue instructions (32-bit version).
4369 This is a helper function for mips_skip_prologue. */
4372 mips32_skip_prologue (CORE_ADDR pc
)
4376 int seen_sp_adjust
= 0;
4377 int load_immediate_bytes
= 0;
4379 /* Skip the typical prologue instructions. These are the stack adjustment
4380 instruction and the instructions that save registers on the stack
4381 or in the gcc frame. */
4382 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4384 unsigned long high_word
;
4386 inst
= mips_fetch_instruction (pc
);
4387 high_word
= (inst
>> 16) & 0xffff;
4389 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4390 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4392 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4393 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4395 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4396 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4397 && (inst
& 0x001F0000)) /* reg != $zero */
4400 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4402 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4404 continue; /* reg != $zero */
4406 /* move $s8,$sp. With different versions of gas this will be either
4407 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4408 Accept any one of these. */
4409 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4412 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4414 else if (high_word
== 0x3c1c) /* lui $gp,n */
4416 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4418 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4419 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4421 /* The following instructions load $at or $t0 with an immediate
4422 value in preparation for a stack adjustment via
4423 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4424 a local variable, so we accept them only before a stack adjustment
4425 instruction was seen. */
4426 else if (!seen_sp_adjust
)
4428 if (high_word
== 0x3c01 || /* lui $at,n */
4429 high_word
== 0x3c08) /* lui $t0,n */
4431 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4434 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4435 high_word
== 0x3508 || /* ori $t0,$t0,n */
4436 high_word
== 0x3401 || /* ori $at,$zero,n */
4437 high_word
== 0x3408) /* ori $t0,$zero,n */
4439 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4449 /* In a frameless function, we might have incorrectly
4450 skipped some load immediate instructions. Undo the skipping
4451 if the load immediate was not followed by a stack adjustment. */
4452 if (load_immediate_bytes
&& !seen_sp_adjust
)
4453 pc
-= load_immediate_bytes
;
4457 /* Skip the PC past function prologue instructions (16-bit version).
4458 This is a helper function for mips_skip_prologue. */
4461 mips16_skip_prologue (CORE_ADDR pc
)
4464 int extend_bytes
= 0;
4465 int prev_extend_bytes
;
4467 /* Table of instructions likely to be found in a function prologue. */
4470 unsigned short inst
;
4471 unsigned short mask
;
4478 , /* addiu $sp,offset */
4482 , /* daddiu $sp,offset */
4486 , /* sw reg,n($sp) */
4490 , /* sd reg,n($sp) */
4494 , /* sw $ra,n($sp) */
4498 , /* sd $ra,n($sp) */
4506 , /* sw $a0-$a3,n($s1) */
4510 , /* move reg,$a0-$a3 */
4514 , /* entry pseudo-op */
4518 , /* addiu $s1,$sp,n */
4521 } /* end of table marker */
4524 /* Skip the typical prologue instructions. These are the stack adjustment
4525 instruction and the instructions that save registers on the stack
4526 or in the gcc frame. */
4527 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4529 unsigned short inst
;
4532 inst
= mips_fetch_instruction (pc
);
4534 /* Normally we ignore an extend instruction. However, if it is
4535 not followed by a valid prologue instruction, we must adjust
4536 the pc back over the extend so that it won't be considered
4537 part of the prologue. */
4538 if ((inst
& 0xf800) == 0xf000) /* extend */
4540 extend_bytes
= MIPS16_INSTLEN
;
4543 prev_extend_bytes
= extend_bytes
;
4546 /* Check for other valid prologue instructions besides extend. */
4547 for (i
= 0; table
[i
].mask
!= 0; i
++)
4548 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4550 if (table
[i
].mask
!= 0) /* it was in table? */
4551 continue; /* ignore it */
4555 /* Return the current pc, adjusted backwards by 2 if
4556 the previous instruction was an extend. */
4557 return pc
- prev_extend_bytes
;
4563 /* To skip prologues, I use this predicate. Returns either PC itself
4564 if the code at PC does not look like a function prologue; otherwise
4565 returns an address that (if we're lucky) follows the prologue. If
4566 LENIENT, then we must skip everything which is involved in setting
4567 up the frame (it's OK to skip more, just so long as we don't skip
4568 anything which might clobber the registers which are being saved.
4569 We must skip more in the case where part of the prologue is in the
4570 delay slot of a non-prologue instruction). */
4573 mips_skip_prologue (CORE_ADDR pc
)
4575 /* See if we can determine the end of the prologue via the symbol table.
4576 If so, then return either PC, or the PC after the prologue, whichever
4579 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4581 if (post_prologue_pc
!= 0)
4582 return max (pc
, post_prologue_pc
);
4584 /* Can't determine prologue from the symbol table, need to examine
4587 if (pc_is_mips16 (pc
))
4588 return mips16_skip_prologue (pc
);
4590 return mips32_skip_prologue (pc
);
4593 /* Determine how a return value is stored within the MIPS register
4594 file, given the return type `valtype'. */
4596 struct return_value_word
4605 return_value_location (struct type
*valtype
,
4606 struct return_value_word
*hi
,
4607 struct return_value_word
*lo
)
4609 int len
= TYPE_LENGTH (valtype
);
4611 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
4612 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
4613 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
4615 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4617 /* We need to break a 64bit float in two 32 bit halves and
4618 spread them across a floating-point register pair. */
4619 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4620 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
4621 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4622 && DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
4624 hi
->reg_offset
= lo
->reg_offset
;
4625 lo
->reg
= FP0_REGNUM
+ 0;
4626 hi
->reg
= FP0_REGNUM
+ 1;
4632 /* The floating point value fits in a single floating-point
4634 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4635 && DEPRECATED_REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
4638 lo
->reg
= FP0_REGNUM
;
4649 /* Locate a result possibly spread across two registers. */
4651 lo
->reg
= regnum
+ 0;
4652 hi
->reg
= regnum
+ 1;
4653 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4654 && len
< MIPS_SAVED_REGSIZE
)
4656 /* "un-left-justify" the value in the low register */
4657 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
4662 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4663 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
4664 && len
< MIPS_SAVED_REGSIZE
* 2
4665 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
4666 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
4668 /* "un-left-justify" the value spread across two registers. */
4669 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
4670 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
4672 hi
->len
= len
- lo
->len
;
4676 /* Only perform a partial copy of the second register. */
4679 if (len
> MIPS_SAVED_REGSIZE
)
4681 lo
->len
= MIPS_SAVED_REGSIZE
;
4682 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
4690 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4691 && DEPRECATED_REGISTER_RAW_SIZE (regnum
) == 8
4692 && MIPS_SAVED_REGSIZE
== 4)
4694 /* Account for the fact that only the least-signficant part
4695 of the register is being used */
4696 lo
->reg_offset
+= 4;
4697 hi
->reg_offset
+= 4;
4700 hi
->buf_offset
= lo
->len
;
4704 /* Given a return value in `regbuf' with a type `valtype', extract and
4705 copy its value into `valbuf'. */
4708 mips_eabi_extract_return_value (struct type
*valtype
,
4712 struct return_value_word lo
;
4713 struct return_value_word hi
;
4714 return_value_location (valtype
, &hi
, &lo
);
4716 memcpy (valbuf
+ lo
.buf_offset
,
4717 regbuf
+ DEPRECATED_REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4721 memcpy (valbuf
+ hi
.buf_offset
,
4722 regbuf
+ DEPRECATED_REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4727 mips_o64_extract_return_value (struct type
*valtype
,
4731 struct return_value_word lo
;
4732 struct return_value_word hi
;
4733 return_value_location (valtype
, &hi
, &lo
);
4735 memcpy (valbuf
+ lo
.buf_offset
,
4736 regbuf
+ DEPRECATED_REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4740 memcpy (valbuf
+ hi
.buf_offset
,
4741 regbuf
+ DEPRECATED_REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4745 /* Given a return value in `valbuf' with a type `valtype', write it's
4746 value into the appropriate register. */
4749 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
4751 char raw_buffer
[MAX_REGISTER_SIZE
];
4752 struct return_value_word lo
;
4753 struct return_value_word hi
;
4754 return_value_location (valtype
, &hi
, &lo
);
4756 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4757 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4758 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4759 DEPRECATED_REGISTER_RAW_SIZE (lo
.reg
));
4763 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4764 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4765 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4766 DEPRECATED_REGISTER_RAW_SIZE (hi
.reg
));
4771 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4773 char raw_buffer
[MAX_REGISTER_SIZE
];
4774 struct return_value_word lo
;
4775 struct return_value_word hi
;
4776 return_value_location (valtype
, &hi
, &lo
);
4778 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4779 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4780 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
), raw_buffer
,
4781 DEPRECATED_REGISTER_RAW_SIZE (lo
.reg
));
4785 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4786 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4787 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
), raw_buffer
,
4788 DEPRECATED_REGISTER_RAW_SIZE (hi
.reg
));
4792 /* O32 ABI stuff. */
4795 mips_o32_xfer_return_value (struct type
*type
,
4796 struct regcache
*regcache
,
4797 bfd_byte
*in
, const bfd_byte
*out
)
4799 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4800 if (TYPE_CODE (type
) == TYPE_CODE_FLT
4801 && TYPE_LENGTH (type
) == 4
4802 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4804 /* A single-precision floating-point value. It fits in the
4805 least significant part of FP0. */
4807 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4808 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
, TYPE_LENGTH (type
),
4809 TARGET_BYTE_ORDER
, in
, out
, 0);
4811 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4812 && TYPE_LENGTH (type
) == 8
4813 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4815 /* A double-precision floating-point value. The most
4816 significant part goes in FP1, and the least significant in
4819 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4820 switch (TARGET_BYTE_ORDER
)
4822 case BFD_ENDIAN_LITTLE
:
4823 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
+ 0, 4,
4824 TARGET_BYTE_ORDER
, in
, out
, 0);
4825 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
+ 1, 4,
4826 TARGET_BYTE_ORDER
, in
, out
, 4);
4828 case BFD_ENDIAN_BIG
:
4829 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
+ 1, 4,
4830 TARGET_BYTE_ORDER
, in
, out
, 0);
4831 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
+ 0, 4,
4832 TARGET_BYTE_ORDER
, in
, out
, 4);
4835 internal_error (__FILE__
, __LINE__
, "bad switch");
4839 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4840 && TYPE_NFIELDS (type
) <= 2
4841 && TYPE_NFIELDS (type
) >= 1
4842 && ((TYPE_NFIELDS (type
) == 1
4843 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4845 || (TYPE_NFIELDS (type
) == 2
4846 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4848 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4850 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4852 /* A struct that contains one or two floats. Each value is part
4853 in the least significant part of their floating point
4855 bfd_byte reg
[MAX_REGISTER_SIZE
];
4858 for (field
= 0, regnum
= FP0_REGNUM
;
4859 field
< TYPE_NFIELDS (type
);
4860 field
++, regnum
+= 2)
4862 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4865 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4866 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4867 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4868 TARGET_BYTE_ORDER
, in
, out
, offset
);
4873 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4874 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4876 /* A structure or union. Extract the left justified value,
4877 regardless of the byte order. I.e. DO NOT USE
4881 for (offset
= 0, regnum
= V0_REGNUM
;
4882 offset
< TYPE_LENGTH (type
);
4883 offset
+= DEPRECATED_REGISTER_RAW_SIZE (regnum
), regnum
++)
4885 int xfer
= DEPRECATED_REGISTER_RAW_SIZE (regnum
);
4886 if (offset
+ xfer
> TYPE_LENGTH (type
))
4887 xfer
= TYPE_LENGTH (type
) - offset
;
4889 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4890 offset
, xfer
, regnum
);
4891 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4892 BFD_ENDIAN_UNKNOWN
, in
, out
, offset
);
4898 /* A scalar extract each part but least-significant-byte
4899 justified. o32 thinks registers are 4 byte, regardless of
4900 the ISA. mips_stack_argsize controls this. */
4903 for (offset
= 0, regnum
= V0_REGNUM
;
4904 offset
< TYPE_LENGTH (type
);
4905 offset
+= mips_stack_argsize (), regnum
++)
4907 int xfer
= mips_stack_argsize ();
4909 if (offset
+ xfer
> TYPE_LENGTH (type
))
4910 xfer
= TYPE_LENGTH (type
) - offset
;
4912 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4913 offset
, xfer
, regnum
);
4914 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4915 TARGET_BYTE_ORDER
, in
, out
, offset
);
4921 mips_o32_extract_return_value (struct type
*type
,
4922 struct regcache
*regcache
,
4925 mips_o32_xfer_return_value (type
, regcache
, valbuf
, NULL
);
4929 mips_o32_store_return_value (struct type
*type
, char *valbuf
)
4931 mips_o32_xfer_return_value (type
, current_regcache
, NULL
, valbuf
);
4934 /* N32/N44 ABI stuff. */
4937 mips_n32n64_xfer_return_value (struct type
*type
,
4938 struct regcache
*regcache
,
4939 bfd_byte
*in
, const bfd_byte
*out
)
4941 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4942 if (TYPE_CODE (type
) == TYPE_CODE_FLT
4943 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4945 /* A floating-point value belongs in the least significant part
4948 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4949 mips_xfer_register (regcache
, NUM_REGS
+ FP0_REGNUM
, TYPE_LENGTH (type
),
4950 TARGET_BYTE_ORDER
, in
, out
, 0);
4952 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4953 && TYPE_NFIELDS (type
) <= 2
4954 && TYPE_NFIELDS (type
) >= 1
4955 && ((TYPE_NFIELDS (type
) == 1
4956 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4958 || (TYPE_NFIELDS (type
) == 2
4959 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4961 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4963 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4965 /* A struct that contains one or two floats. Each value is part
4966 in the least significant part of their floating point
4968 bfd_byte reg
[MAX_REGISTER_SIZE
];
4971 for (field
= 0, regnum
= FP0_REGNUM
;
4972 field
< TYPE_NFIELDS (type
);
4973 field
++, regnum
+= 2)
4975 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4978 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4979 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4980 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4981 TARGET_BYTE_ORDER
, in
, out
, offset
);
4984 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4985 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4987 /* A structure or union. Extract the left justified value,
4988 regardless of the byte order. I.e. DO NOT USE
4992 for (offset
= 0, regnum
= V0_REGNUM
;
4993 offset
< TYPE_LENGTH (type
);
4994 offset
+= DEPRECATED_REGISTER_RAW_SIZE (regnum
), regnum
++)
4996 int xfer
= DEPRECATED_REGISTER_RAW_SIZE (regnum
);
4997 if (offset
+ xfer
> TYPE_LENGTH (type
))
4998 xfer
= TYPE_LENGTH (type
) - offset
;
5000 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5001 offset
, xfer
, regnum
);
5002 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
5003 BFD_ENDIAN_UNKNOWN
, in
, out
, offset
);
5008 /* A scalar extract each part but least-significant-byte
5012 for (offset
= 0, regnum
= V0_REGNUM
;
5013 offset
< TYPE_LENGTH (type
);
5014 offset
+= DEPRECATED_REGISTER_RAW_SIZE (regnum
), regnum
++)
5016 int xfer
= DEPRECATED_REGISTER_RAW_SIZE (regnum
);
5018 if (offset
+ xfer
> TYPE_LENGTH (type
))
5019 xfer
= TYPE_LENGTH (type
) - offset
;
5021 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5022 offset
, xfer
, regnum
);
5023 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
5024 TARGET_BYTE_ORDER
, in
, out
, offset
);
5030 mips_n32n64_extract_return_value (struct type
*type
,
5031 struct regcache
*regcache
,
5034 mips_n32n64_xfer_return_value (type
, regcache
, valbuf
, NULL
);
5038 mips_n32n64_store_return_value (struct type
*type
, char *valbuf
)
5040 mips_n32n64_xfer_return_value (type
, current_regcache
, NULL
, valbuf
);
5044 mips_extract_struct_value_address (struct regcache
*regcache
)
5046 /* FIXME: This will only work at random. The caller passes the
5047 struct_return address in V0, but it is not preserved. It may
5048 still be there, or this may be a random value. */
5051 regcache_cooked_read_signed (regcache
, V0_REGNUM
, &val
);
5055 /* Exported procedure: Is PC in the signal trampoline code */
5058 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
5060 if (sigtramp_address
== 0)
5062 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
5065 /* Root of all "set mips "/"show mips " commands. This will eventually be
5066 used for all MIPS-specific commands. */
5069 show_mips_command (char *args
, int from_tty
)
5071 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5075 set_mips_command (char *args
, int from_tty
)
5077 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
5078 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5081 /* Commands to show/set the MIPS FPU type. */
5084 show_mipsfpu_command (char *args
, int from_tty
)
5087 switch (MIPS_FPU_TYPE
)
5089 case MIPS_FPU_SINGLE
:
5090 fpu
= "single-precision";
5092 case MIPS_FPU_DOUBLE
:
5093 fpu
= "double-precision";
5096 fpu
= "absent (none)";
5099 internal_error (__FILE__
, __LINE__
, "bad switch");
5101 if (mips_fpu_type_auto
)
5102 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5105 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
5111 set_mipsfpu_command (char *args
, int from_tty
)
5113 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5114 show_mipsfpu_command (args
, from_tty
);
5118 set_mipsfpu_single_command (char *args
, int from_tty
)
5120 mips_fpu_type
= MIPS_FPU_SINGLE
;
5121 mips_fpu_type_auto
= 0;
5122 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
5126 set_mipsfpu_double_command (char *args
, int from_tty
)
5128 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5129 mips_fpu_type_auto
= 0;
5130 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5134 set_mipsfpu_none_command (char *args
, int from_tty
)
5136 mips_fpu_type
= MIPS_FPU_NONE
;
5137 mips_fpu_type_auto
= 0;
5138 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
5142 set_mipsfpu_auto_command (char *args
, int from_tty
)
5144 mips_fpu_type_auto
= 1;
5147 /* Command to set the processor type. */
5150 mips_set_processor_type_command (char *args
, int from_tty
)
5154 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
5156 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
5157 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
5158 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
5160 /* Restore the value. */
5161 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
5166 if (!mips_set_processor_type (tmp_mips_processor_type
))
5168 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
5169 /* Restore its value. */
5170 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
5175 mips_show_processor_type_command (char *args
, int from_tty
)
5179 /* Modify the actual processor type. */
5182 mips_set_processor_type (char *str
)
5189 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
5191 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
5193 mips_processor_type
= str
;
5194 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
5196 /* FIXME tweak fpu flag too */
5203 /* Attempt to identify the particular processor model by reading the
5207 mips_read_processor_type (void)
5211 prid
= read_register (PRID_REGNUM
);
5213 if ((prid
& ~0xf) == 0x700)
5214 return savestring ("r3041", strlen ("r3041"));
5219 /* Just like reinit_frame_cache, but with the right arguments to be
5220 callable as an sfunc. */
5223 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5224 struct cmd_list_element
*c
)
5226 reinit_frame_cache ();
5230 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5232 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5233 mips_extra_func_info_t proc_desc
;
5235 /* Search for the function containing this address. Set the low bit
5236 of the address when searching, in case we were given an even address
5237 that is the start of a 16-bit function. If we didn't do this,
5238 the search would fail because the symbol table says the function
5239 starts at an odd address, i.e. 1 byte past the given address. */
5240 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5241 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5243 /* Make an attempt to determine if this is a 16-bit function. If
5244 the procedure descriptor exists and the address therein is odd,
5245 it's definitely a 16-bit function. Otherwise, we have to just
5246 guess that if the address passed in is odd, it's 16-bits. */
5247 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5248 disassembler needs to be able to locally determine the ISA, and
5249 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5253 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5254 info
->mach
= bfd_mach_mips16
;
5258 if (pc_is_mips16 (memaddr
))
5259 info
->mach
= bfd_mach_mips16
;
5262 /* Round down the instruction address to the appropriate boundary. */
5263 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5265 /* Set the disassembler options. */
5266 if (tdep
->mips_abi
== MIPS_ABI_N32
5267 || tdep
->mips_abi
== MIPS_ABI_N64
)
5269 /* Set up the disassembler info, so that we get the right
5270 register names from libopcodes. */
5271 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5272 info
->disassembler_options
= "gpr-names=n32";
5274 info
->disassembler_options
= "gpr-names=64";
5275 info
->flavour
= bfd_target_elf_flavour
;
5278 /* This string is not recognized explicitly by the disassembler,
5279 but it tells the disassembler to not try to guess the ABI from
5280 the bfd elf headers, such that, if the user overrides the ABI
5281 of a program linked as NewABI, the disassembly will follow the
5282 register naming conventions specified by the user. */
5283 info
->disassembler_options
= "gpr-names=32";
5285 /* Call the appropriate disassembler based on the target endian-ness. */
5286 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5287 return print_insn_big_mips (memaddr
, info
);
5289 return print_insn_little_mips (memaddr
, info
);
5292 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5293 counter value to determine whether a 16- or 32-bit breakpoint should be
5294 used. It returns a pointer to a string of bytes that encode a breakpoint
5295 instruction, stores the length of the string to *lenptr, and adjusts pc
5296 (if necessary) to point to the actual memory location where the
5297 breakpoint should be inserted. */
5299 static const unsigned char *
5300 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
5302 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5304 if (pc_is_mips16 (*pcptr
))
5306 static unsigned char mips16_big_breakpoint
[] = {0xe8, 0xa5};
5307 *pcptr
= unmake_mips16_addr (*pcptr
);
5308 *lenptr
= sizeof (mips16_big_breakpoint
);
5309 return mips16_big_breakpoint
;
5313 /* The IDT board uses an unusual breakpoint value, and
5314 sometimes gets confused when it sees the usual MIPS
5315 breakpoint instruction. */
5316 static unsigned char big_breakpoint
[] = {0, 0x5, 0, 0xd};
5317 static unsigned char pmon_big_breakpoint
[] = {0, 0, 0, 0xd};
5318 static unsigned char idt_big_breakpoint
[] = {0, 0, 0x0a, 0xd};
5320 *lenptr
= sizeof (big_breakpoint
);
5322 if (strcmp (target_shortname
, "mips") == 0)
5323 return idt_big_breakpoint
;
5324 else if (strcmp (target_shortname
, "ddb") == 0
5325 || strcmp (target_shortname
, "pmon") == 0
5326 || strcmp (target_shortname
, "lsi") == 0)
5327 return pmon_big_breakpoint
;
5329 return big_breakpoint
;
5334 if (pc_is_mips16 (*pcptr
))
5336 static unsigned char mips16_little_breakpoint
[] = {0xa5, 0xe8};
5337 *pcptr
= unmake_mips16_addr (*pcptr
);
5338 *lenptr
= sizeof (mips16_little_breakpoint
);
5339 return mips16_little_breakpoint
;
5343 static unsigned char little_breakpoint
[] = {0xd, 0, 0x5, 0};
5344 static unsigned char pmon_little_breakpoint
[] = {0xd, 0, 0, 0};
5345 static unsigned char idt_little_breakpoint
[] = {0xd, 0x0a, 0, 0};
5347 *lenptr
= sizeof (little_breakpoint
);
5349 if (strcmp (target_shortname
, "mips") == 0)
5350 return idt_little_breakpoint
;
5351 else if (strcmp (target_shortname
, "ddb") == 0
5352 || strcmp (target_shortname
, "pmon") == 0
5353 || strcmp (target_shortname
, "lsi") == 0)
5354 return pmon_little_breakpoint
;
5356 return little_breakpoint
;
5361 /* If PC is in a mips16 call or return stub, return the address of the target
5362 PC, which is either the callee or the caller. There are several
5363 cases which must be handled:
5365 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5366 target PC is in $31 ($ra).
5367 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5368 and the target PC is in $2.
5369 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5370 before the jal instruction, this is effectively a call stub
5371 and the the target PC is in $2. Otherwise this is effectively
5372 a return stub and the target PC is in $18.
5374 See the source code for the stubs in gcc/config/mips/mips16.S for
5377 This function implements the SKIP_TRAMPOLINE_CODE macro.
5381 mips_skip_stub (CORE_ADDR pc
)
5384 CORE_ADDR start_addr
;
5386 /* Find the starting address and name of the function containing the PC. */
5387 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5390 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5391 target PC is in $31 ($ra). */
5392 if (strcmp (name
, "__mips16_ret_sf") == 0
5393 || strcmp (name
, "__mips16_ret_df") == 0)
5394 return read_signed_register (RA_REGNUM
);
5396 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5398 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5399 and the target PC is in $2. */
5400 if (name
[19] >= '0' && name
[19] <= '9')
5401 return read_signed_register (2);
5403 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5404 before the jal instruction, this is effectively a call stub
5405 and the the target PC is in $2. Otherwise this is effectively
5406 a return stub and the target PC is in $18. */
5407 else if (name
[19] == 's' || name
[19] == 'd')
5409 if (pc
== start_addr
)
5411 /* Check if the target of the stub is a compiler-generated
5412 stub. Such a stub for a function bar might have a name
5413 like __fn_stub_bar, and might look like this:
5418 la $1,bar (becomes a lui/addiu pair)
5420 So scan down to the lui/addi and extract the target
5421 address from those two instructions. */
5423 CORE_ADDR target_pc
= read_signed_register (2);
5427 /* See if the name of the target function is __fn_stub_*. */
5428 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
5430 if (strncmp (name
, "__fn_stub_", 10) != 0
5431 && strcmp (name
, "etext") != 0
5432 && strcmp (name
, "_etext") != 0)
5435 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5436 The limit on the search is arbitrarily set to 20
5437 instructions. FIXME. */
5438 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5440 inst
= mips_fetch_instruction (target_pc
);
5441 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5442 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5443 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5444 return pc
| (inst
& 0xffff); /* low word */
5447 /* Couldn't find the lui/addui pair, so return stub address. */
5451 /* This is the 'return' part of a call stub. The return
5452 address is in $r18. */
5453 return read_signed_register (18);
5456 return 0; /* not a stub */
5460 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5461 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5464 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5466 CORE_ADDR start_addr
;
5468 /* Find the starting address of the function containing the PC. If the
5469 caller didn't give us a name, look it up at the same time. */
5470 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
5473 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5475 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5476 if (name
[19] >= '0' && name
[19] <= '9')
5478 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5479 before the jal instruction, this is effectively a call stub. */
5480 else if (name
[19] == 's' || name
[19] == 'd')
5481 return pc
== start_addr
;
5484 return 0; /* not a stub */
5488 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5489 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5492 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5494 CORE_ADDR start_addr
;
5496 /* Find the starting address of the function containing the PC. */
5497 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5500 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5501 if (strcmp (name
, "__mips16_ret_sf") == 0
5502 || strcmp (name
, "__mips16_ret_df") == 0)
5505 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5506 i.e. after the jal instruction, this is effectively a return stub. */
5507 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5508 && (name
[19] == 's' || name
[19] == 'd')
5509 && pc
!= start_addr
)
5512 return 0; /* not a stub */
5516 /* Return non-zero if the PC is in a library helper function that should
5517 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5520 mips_ignore_helper (CORE_ADDR pc
)
5524 /* Find the starting address and name of the function containing the PC. */
5525 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5528 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5529 that we want to ignore. */
5530 return (strcmp (name
, "__mips16_ret_sf") == 0
5531 || strcmp (name
, "__mips16_ret_df") == 0);
5535 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5536 the register stored on the stack (32) is different to its real raw
5537 size (64). The below ensures that registers are fetched from the
5538 stack using their ABI size and then stored into the RAW_BUFFER
5539 using their raw size.
5541 The alternative to adding this function would be to add an ABI
5542 macro - REGISTER_STACK_SIZE(). */
5545 mips_get_saved_register (char *raw_buffer
,
5548 struct frame_info
*frame
,
5550 enum lval_type
*lvalp
)
5553 enum lval_type lvalx
;
5557 /* Always a pseudo. */
5558 gdb_assert (regnum
>= NUM_REGS
);
5560 /* Make certain that all needed parameters are present. */
5565 if (optimizedp
== NULL
)
5566 optimizedp
= &optimizedx
;
5568 if ((regnum
% NUM_REGS
) == SP_REGNUM
)
5569 /* The SP_REGNUM is special, its value is stored in saved_regs.
5570 In fact, it is so special that it can even only be fetched
5571 using a raw register number! Once this code as been converted
5572 to frame-unwind the problem goes away. */
5573 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5574 regnum
% NUM_REGS
, optimizedp
, lvalp
, addrp
,
5575 &realnumx
, raw_buffer
);
5577 /* Get it from the next frame. */
5578 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5579 regnum
, optimizedp
, lvalp
, addrp
,
5580 &realnumx
, raw_buffer
);
5583 /* Immediately after a function call, return the saved pc.
5584 Can't always go through the frames for this because on some machines
5585 the new frame is not set up until the new function executes
5586 some instructions. */
5589 mips_saved_pc_after_call (struct frame_info
*frame
)
5591 return read_signed_register (RA_REGNUM
);
5595 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5596 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5599 mips_stab_reg_to_regnum (int num
)
5602 if (num
>= 0 && num
< 32)
5604 else if (num
>= 38 && num
< 70)
5605 regnum
= num
+ FP0_REGNUM
- 38;
5611 /* This will hopefully (eventually) provoke a warning. Should
5612 we be calling complaint() here? */
5613 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5614 return NUM_REGS
+ regnum
;
5618 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5619 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5622 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5625 if (num
>= 0 && num
< 32)
5627 else if (num
>= 32 && num
< 64)
5628 regnum
= num
+ FP0_REGNUM
- 32;
5634 /* This will hopefully (eventually) provoke a warning. Should we
5635 be calling complaint() here? */
5636 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5637 return NUM_REGS
+ regnum
;
5641 mips_register_sim_regno (int regnum
)
5643 /* Only makes sense to supply raw registers. */
5644 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5645 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5646 decide if it is valid. Should instead define a standard sim/gdb
5647 register numbering scheme. */
5648 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5649 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5652 return LEGACY_SIM_REGNO_IGNORE
;
5656 /* Convert an integer into an address. By first converting the value
5657 into a pointer and then extracting it signed, the address is
5658 guarenteed to be correctly sign extended. */
5661 mips_integer_to_address (struct type
*type
, void *buf
)
5663 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5664 LONGEST val
= unpack_long (type
, buf
);
5665 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5666 return extract_signed_integer (tmp
,
5667 TYPE_LENGTH (builtin_type_void_data_ptr
));
5671 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5673 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5674 const char *name
= bfd_get_section_name (abfd
, sect
);
5676 if (*abip
!= MIPS_ABI_UNKNOWN
)
5679 if (strncmp (name
, ".mdebug.", 8) != 0)
5682 if (strcmp (name
, ".mdebug.abi32") == 0)
5683 *abip
= MIPS_ABI_O32
;
5684 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5685 *abip
= MIPS_ABI_N32
;
5686 else if (strcmp (name
, ".mdebug.abi64") == 0)
5687 *abip
= MIPS_ABI_N64
;
5688 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5689 *abip
= MIPS_ABI_O64
;
5690 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5691 *abip
= MIPS_ABI_EABI32
;
5692 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5693 *abip
= MIPS_ABI_EABI64
;
5695 warning ("unsupported ABI %s.", name
+ 8);
5698 static enum mips_abi
5699 global_mips_abi (void)
5703 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5704 if (mips_abi_strings
[i
] == mips_abi_string
)
5705 return (enum mips_abi
) i
;
5707 internal_error (__FILE__
, __LINE__
,
5708 "unknown ABI string");
5711 static struct gdbarch
*
5712 mips_gdbarch_init (struct gdbarch_info info
,
5713 struct gdbarch_list
*arches
)
5715 struct gdbarch
*gdbarch
;
5716 struct gdbarch_tdep
*tdep
;
5718 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5725 /* First of all, extract the elf_flags, if available. */
5726 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5727 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5730 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5731 switch ((elf_flags
& EF_MIPS_ABI
))
5733 case E_MIPS_ABI_O32
:
5734 mips_abi
= MIPS_ABI_O32
;
5736 case E_MIPS_ABI_O64
:
5737 mips_abi
= MIPS_ABI_O64
;
5739 case E_MIPS_ABI_EABI32
:
5740 mips_abi
= MIPS_ABI_EABI32
;
5742 case E_MIPS_ABI_EABI64
:
5743 mips_abi
= MIPS_ABI_EABI64
;
5746 if ((elf_flags
& EF_MIPS_ABI2
))
5747 mips_abi
= MIPS_ABI_N32
;
5749 mips_abi
= MIPS_ABI_UNKNOWN
;
5753 /* GCC creates a pseudo-section whose name describes the ABI. */
5754 if (mips_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5755 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &mips_abi
);
5757 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
5758 Use the ABI from the last architecture if there is one. */
5759 if (info
.abfd
== NULL
&& arches
!= NULL
)
5760 mips_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5762 /* Try the architecture for any hint of the correct ABI. */
5763 if (mips_abi
== MIPS_ABI_UNKNOWN
5764 && info
.bfd_arch_info
!= NULL
5765 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5767 switch (info
.bfd_arch_info
->mach
)
5769 case bfd_mach_mips3900
:
5770 mips_abi
= MIPS_ABI_EABI32
;
5772 case bfd_mach_mips4100
:
5773 case bfd_mach_mips5000
:
5774 mips_abi
= MIPS_ABI_EABI64
;
5776 case bfd_mach_mips8000
:
5777 case bfd_mach_mips10000
:
5778 /* On Irix, ELF64 executables use the N64 ABI. The
5779 pseudo-sections which describe the ABI aren't present
5780 on IRIX. (Even for executables created by gcc.) */
5781 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5782 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5783 mips_abi
= MIPS_ABI_N64
;
5785 mips_abi
= MIPS_ABI_N32
;
5790 if (mips_abi
== MIPS_ABI_UNKNOWN
)
5791 mips_abi
= MIPS_ABI_O32
;
5793 /* Now that we have found what the ABI for this binary would be,
5794 check whether the user is overriding it. */
5795 found_abi
= mips_abi
;
5796 wanted_abi
= global_mips_abi ();
5797 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5798 mips_abi
= wanted_abi
;
5802 fprintf_unfiltered (gdb_stdlog
,
5803 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5805 fprintf_unfiltered (gdb_stdlog
,
5806 "mips_gdbarch_init: mips_abi = %d\n",
5808 fprintf_unfiltered (gdb_stdlog
,
5809 "mips_gdbarch_init: found_mips_abi = %d\n",
5813 /* try to find a pre-existing architecture */
5814 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5816 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5818 /* MIPS needs to be pedantic about which ABI the object is
5820 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5822 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5824 return arches
->gdbarch
;
5827 /* Need a new architecture. Fill in a target specific vector. */
5828 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5829 gdbarch
= gdbarch_alloc (&info
, tdep
);
5830 tdep
->elf_flags
= elf_flags
;
5832 /* Initially set everything according to the default ABI/ISA. */
5833 set_gdbarch_short_bit (gdbarch
, 16);
5834 set_gdbarch_int_bit (gdbarch
, 32);
5835 set_gdbarch_float_bit (gdbarch
, 32);
5836 set_gdbarch_double_bit (gdbarch
, 64);
5837 set_gdbarch_long_double_bit (gdbarch
, 64);
5838 set_gdbarch_deprecated_register_raw_size (gdbarch
, mips_register_raw_size
);
5839 set_gdbarch_deprecated_register_byte (gdbarch
, mips_register_byte
);
5840 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5841 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5842 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5843 tdep
->found_abi
= found_abi
;
5844 tdep
->mips_abi
= mips_abi
;
5846 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5847 mips_elf_make_msymbol_special
);
5850 if (info
.osabi
== GDB_OSABI_IRIX
)
5854 set_gdbarch_num_regs (gdbarch
, num_regs
);
5855 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5860 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5861 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_o32_store_return_value
);
5862 set_gdbarch_extract_return_value (gdbarch
, mips_o32_extract_return_value
);
5863 tdep
->mips_default_saved_regsize
= 4;
5864 tdep
->mips_default_stack_argsize
= 4;
5865 tdep
->mips_fp_register_double
= 0;
5866 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5867 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
5868 tdep
->gdb_target_is_mips64
= 0;
5869 tdep
->default_mask_address_p
= 0;
5870 set_gdbarch_long_bit (gdbarch
, 32);
5871 set_gdbarch_ptr_bit (gdbarch
, 32);
5872 set_gdbarch_long_long_bit (gdbarch
, 64);
5873 set_gdbarch_deprecated_reg_struct_has_addr
5874 (gdbarch
, mips_o32_reg_struct_has_addr
);
5875 set_gdbarch_use_struct_convention (gdbarch
,
5876 always_use_struct_convention
);
5879 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5880 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_o64_store_return_value
);
5881 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_o64_extract_return_value
);
5882 tdep
->mips_default_saved_regsize
= 8;
5883 tdep
->mips_default_stack_argsize
= 8;
5884 tdep
->mips_fp_register_double
= 1;
5885 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5886 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
5887 tdep
->gdb_target_is_mips64
= 1;
5888 tdep
->default_mask_address_p
= 0;
5889 set_gdbarch_long_bit (gdbarch
, 32);
5890 set_gdbarch_ptr_bit (gdbarch
, 32);
5891 set_gdbarch_long_long_bit (gdbarch
, 64);
5892 set_gdbarch_deprecated_reg_struct_has_addr
5893 (gdbarch
, mips_o32_reg_struct_has_addr
);
5894 set_gdbarch_use_struct_convention (gdbarch
, always_use_struct_convention
);
5896 case MIPS_ABI_EABI32
:
5897 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5898 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5899 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5900 tdep
->mips_default_saved_regsize
= 4;
5901 tdep
->mips_default_stack_argsize
= 4;
5902 tdep
->mips_fp_register_double
= 0;
5903 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5904 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5905 tdep
->gdb_target_is_mips64
= 0;
5906 tdep
->default_mask_address_p
= 0;
5907 set_gdbarch_long_bit (gdbarch
, 32);
5908 set_gdbarch_ptr_bit (gdbarch
, 32);
5909 set_gdbarch_long_long_bit (gdbarch
, 64);
5910 set_gdbarch_deprecated_reg_struct_has_addr
5911 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5912 set_gdbarch_use_struct_convention (gdbarch
,
5913 mips_eabi_use_struct_convention
);
5915 case MIPS_ABI_EABI64
:
5916 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5917 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5918 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5919 tdep
->mips_default_saved_regsize
= 8;
5920 tdep
->mips_default_stack_argsize
= 8;
5921 tdep
->mips_fp_register_double
= 1;
5922 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5923 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5924 tdep
->gdb_target_is_mips64
= 1;
5925 tdep
->default_mask_address_p
= 0;
5926 set_gdbarch_long_bit (gdbarch
, 64);
5927 set_gdbarch_ptr_bit (gdbarch
, 64);
5928 set_gdbarch_long_long_bit (gdbarch
, 64);
5929 set_gdbarch_deprecated_reg_struct_has_addr
5930 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5931 set_gdbarch_use_struct_convention (gdbarch
,
5932 mips_eabi_use_struct_convention
);
5935 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5936 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_n32n64_store_return_value
);
5937 set_gdbarch_extract_return_value (gdbarch
, mips_n32n64_extract_return_value
);
5938 tdep
->mips_default_saved_regsize
= 8;
5939 tdep
->mips_default_stack_argsize
= 8;
5940 tdep
->mips_fp_register_double
= 1;
5941 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5942 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5943 tdep
->gdb_target_is_mips64
= 1;
5944 tdep
->default_mask_address_p
= 0;
5945 set_gdbarch_long_bit (gdbarch
, 32);
5946 set_gdbarch_ptr_bit (gdbarch
, 32);
5947 set_gdbarch_long_long_bit (gdbarch
, 64);
5948 set_gdbarch_use_struct_convention (gdbarch
,
5949 mips_n32n64_use_struct_convention
);
5950 set_gdbarch_deprecated_reg_struct_has_addr
5951 (gdbarch
, mips_n32n64_reg_struct_has_addr
);
5954 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5955 set_gdbarch_deprecated_store_return_value (gdbarch
, mips_n32n64_store_return_value
);
5956 set_gdbarch_extract_return_value (gdbarch
, mips_n32n64_extract_return_value
);
5957 tdep
->mips_default_saved_regsize
= 8;
5958 tdep
->mips_default_stack_argsize
= 8;
5959 tdep
->mips_fp_register_double
= 1;
5960 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5961 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5962 tdep
->gdb_target_is_mips64
= 1;
5963 tdep
->default_mask_address_p
= 0;
5964 set_gdbarch_long_bit (gdbarch
, 64);
5965 set_gdbarch_ptr_bit (gdbarch
, 64);
5966 set_gdbarch_long_long_bit (gdbarch
, 64);
5967 set_gdbarch_use_struct_convention (gdbarch
,
5968 mips_n32n64_use_struct_convention
);
5969 set_gdbarch_deprecated_reg_struct_has_addr
5970 (gdbarch
, mips_n32n64_reg_struct_has_addr
);
5973 internal_error (__FILE__
, __LINE__
,
5974 "unknown ABI in switch");
5977 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5978 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5981 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5982 flag in object files because to do so would make it impossible to
5983 link with libraries compiled without "-gp32". This is
5984 unnecessarily restrictive.
5986 We could solve this problem by adding "-gp32" multilibs to gcc,
5987 but to set this flag before gcc is built with such multilibs will
5988 break too many systems.''
5990 But even more unhelpfully, the default linker output target for
5991 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5992 for 64-bit programs - you need to change the ABI to change this,
5993 and not all gcc targets support that currently. Therefore using
5994 this flag to detect 32-bit mode would do the wrong thing given
5995 the current gcc - it would make GDB treat these 64-bit programs
5996 as 32-bit programs by default. */
5998 /* enable/disable the MIPS FPU */
5999 if (!mips_fpu_type_auto
)
6000 tdep
->mips_fpu_type
= mips_fpu_type
;
6001 else if (info
.bfd_arch_info
!= NULL
6002 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6003 switch (info
.bfd_arch_info
->mach
)
6005 case bfd_mach_mips3900
:
6006 case bfd_mach_mips4100
:
6007 case bfd_mach_mips4111
:
6008 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
6010 case bfd_mach_mips4650
:
6011 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
6014 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
6018 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
6020 /* MIPS version of register names. NOTE: At present the MIPS
6021 register name management is part way between the old -
6022 #undef/#define MIPS_REGISTER_NAMES and the new REGISTER_NAME(nr).
6023 Further work on it is required. */
6024 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6025 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6026 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
6027 set_gdbarch_deprecated_target_read_fp (gdbarch
, mips_read_sp
); /* Draft FRAME base. */
6028 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6030 /* Add/remove bits from an address. The MIPS needs be careful to
6031 ensure that all 32 bit addresses are sign extended to 64 bits. */
6032 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6034 /* There's a mess in stack frame creation. See comments in
6035 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
6036 set_gdbarch_deprecated_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
6038 /* Map debug register numbers onto internal register numbers. */
6039 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6040 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6041 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6042 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6043 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6045 /* Initialize a frame */
6046 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch
, mips_find_saved_regs
);
6047 set_gdbarch_deprecated_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
6049 /* MIPS version of CALL_DUMMY */
6051 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6052 replaced by a command, and all targets will default to on stack
6053 (regardless of the stack's execute status). */
6054 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6055 set_gdbarch_deprecated_pop_frame (gdbarch
, mips_pop_frame
);
6056 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6057 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
6058 set_gdbarch_deprecated_register_convertible (gdbarch
, mips_register_convertible
);
6059 set_gdbarch_deprecated_register_convert_to_virtual (gdbarch
, mips_register_convert_to_virtual
);
6060 set_gdbarch_deprecated_register_convert_to_raw (gdbarch
, mips_register_convert_to_raw
);
6062 set_gdbarch_deprecated_frame_chain (gdbarch
, mips_frame_chain
);
6063 set_gdbarch_frameless_function_invocation (gdbarch
,
6064 generic_frameless_function_invocation_not
);
6065 set_gdbarch_deprecated_frame_saved_pc (gdbarch
, mips_frame_saved_pc
);
6066 set_gdbarch_frame_args_skip (gdbarch
, 0);
6068 set_gdbarch_deprecated_get_saved_register (gdbarch
, mips_get_saved_register
);
6070 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6071 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6072 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
6074 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6075 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
6077 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6078 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6079 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6081 set_gdbarch_function_start_offset (gdbarch
, 0);
6083 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6085 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6086 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
6088 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6090 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6091 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6092 need to all be folded into the target vector. Since they are
6093 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6094 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6096 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6098 /* Hook in OS ABI-specific overrides, if they have been registered. */
6099 gdbarch_init_osabi (info
, gdbarch
);
6101 set_gdbarch_extract_struct_value_address (gdbarch
,
6102 mips_extract_struct_value_address
);
6104 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6106 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6107 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6113 mips_abi_update (char *ignore_args
, int from_tty
,
6114 struct cmd_list_element
*c
)
6116 struct gdbarch_info info
;
6118 /* Force the architecture to update, and (if it's a MIPS architecture)
6119 mips_gdbarch_init will take care of the rest. */
6120 gdbarch_info_init (&info
);
6121 gdbarch_update_p (info
);
6124 /* Print out which MIPS ABI is in use. */
6127 show_mips_abi (char *ignore_args
, int from_tty
)
6129 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6131 "The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6134 enum mips_abi global_abi
= global_mips_abi ();
6135 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6136 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6138 if (global_abi
== MIPS_ABI_UNKNOWN
)
6139 printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n",
6141 else if (global_abi
== actual_abi
)
6143 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6147 /* Probably shouldn't happen... */
6149 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6151 mips_abi_strings
[global_abi
]);
6157 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6159 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6163 int ef_mips_32bitmode
;
6164 /* determine the ISA */
6165 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6183 /* determine the size of a pointer */
6184 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6185 fprintf_unfiltered (file
,
6186 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6188 fprintf_unfiltered (file
,
6189 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6191 fprintf_unfiltered (file
,
6192 "mips_dump_tdep: ef_mips_arch = %d\n",
6194 fprintf_unfiltered (file
,
6195 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6197 mips_abi_strings
[tdep
->mips_abi
]);
6198 fprintf_unfiltered (file
,
6199 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6200 mips_mask_address_p (),
6201 tdep
->default_mask_address_p
);
6203 fprintf_unfiltered (file
,
6204 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6205 FP_REGISTER_DOUBLE
);
6206 fprintf_unfiltered (file
,
6207 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6208 MIPS_DEFAULT_FPU_TYPE
,
6209 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6210 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6211 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6213 fprintf_unfiltered (file
,
6214 "mips_dump_tdep: MIPS_EABI = %d\n",
6216 fprintf_unfiltered (file
,
6217 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
6218 MIPS_LAST_FP_ARG_REGNUM
,
6219 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
6220 fprintf_unfiltered (file
,
6221 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6223 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6224 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6225 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6227 fprintf_unfiltered (file
,
6228 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
6229 MIPS_DEFAULT_SAVED_REGSIZE
);
6230 fprintf_unfiltered (file
,
6231 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6232 FP_REGISTER_DOUBLE
);
6233 fprintf_unfiltered (file
,
6234 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
6235 MIPS_DEFAULT_STACK_ARGSIZE
);
6236 fprintf_unfiltered (file
,
6237 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
6238 MIPS_STACK_ARGSIZE
);
6239 fprintf_unfiltered (file
,
6240 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
6242 fprintf_unfiltered (file
,
6243 "mips_dump_tdep: A0_REGNUM = %d\n",
6245 fprintf_unfiltered (file
,
6246 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6247 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
6248 fprintf_unfiltered (file
,
6249 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6250 XSTRING (ATTACH_DETACH
));
6251 fprintf_unfiltered (file
,
6252 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
6254 fprintf_unfiltered (file
,
6255 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
6257 fprintf_unfiltered (file
,
6258 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6259 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6260 fprintf_unfiltered (file
,
6261 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6262 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6263 fprintf_unfiltered (file
,
6264 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
6266 fprintf_unfiltered (file
,
6267 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
6269 fprintf_unfiltered (file
,
6270 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6271 FIRST_EMBED_REGNUM
);
6272 fprintf_unfiltered (file
,
6273 "mips_dump_tdep: FPA0_REGNUM = %d\n",
6275 fprintf_unfiltered (file
,
6276 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
6277 GDB_TARGET_IS_MIPS64
);
6278 fprintf_unfiltered (file
,
6279 "mips_dump_tdep: HI_REGNUM = %d\n",
6281 fprintf_unfiltered (file
,
6282 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6283 XSTRING (IGNORE_HELPER_CALL (PC
)));
6284 fprintf_unfiltered (file
,
6285 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6286 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6287 fprintf_unfiltered (file
,
6288 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6289 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6290 fprintf_unfiltered (file
,
6291 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6293 fprintf_unfiltered (file
,
6294 "mips_dump_tdep: LO_REGNUM = %d\n",
6296 #ifdef MACHINE_CPROC_FP_OFFSET
6297 fprintf_unfiltered (file
,
6298 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6299 MACHINE_CPROC_FP_OFFSET
);
6301 #ifdef MACHINE_CPROC_PC_OFFSET
6302 fprintf_unfiltered (file
,
6303 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6304 MACHINE_CPROC_PC_OFFSET
);
6306 #ifdef MACHINE_CPROC_SP_OFFSET
6307 fprintf_unfiltered (file
,
6308 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6309 MACHINE_CPROC_SP_OFFSET
);
6311 fprintf_unfiltered (file
,
6312 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6314 fprintf_unfiltered (file
,
6315 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6316 fprintf_unfiltered (file
,
6317 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6318 fprintf_unfiltered (file
,
6319 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6321 fprintf_unfiltered (file
,
6322 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6323 MIPS_LAST_ARG_REGNUM
,
6324 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6325 fprintf_unfiltered (file
,
6326 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6328 fprintf_unfiltered (file
,
6329 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
6330 fprintf_unfiltered (file
,
6331 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
6332 MIPS_SAVED_REGSIZE
);
6333 fprintf_unfiltered (file
,
6334 "mips_dump_tdep: OP_LDFPR = used?\n");
6335 fprintf_unfiltered (file
,
6336 "mips_dump_tdep: OP_LDGPR = used?\n");
6337 fprintf_unfiltered (file
,
6338 "mips_dump_tdep: PRID_REGNUM = %d\n",
6340 fprintf_unfiltered (file
,
6341 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6342 fprintf_unfiltered (file
,
6343 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6344 fprintf_unfiltered (file
,
6345 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6346 fprintf_unfiltered (file
,
6347 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6348 fprintf_unfiltered (file
,
6349 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6350 fprintf_unfiltered (file
,
6351 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6352 fprintf_unfiltered (file
,
6353 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6354 fprintf_unfiltered (file
,
6355 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6356 fprintf_unfiltered (file
,
6357 "mips_dump_tdep: PROC_PC_REG = function?\n");
6358 fprintf_unfiltered (file
,
6359 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6360 fprintf_unfiltered (file
,
6361 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6362 fprintf_unfiltered (file
,
6363 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6364 fprintf_unfiltered (file
,
6365 "mips_dump_tdep: PS_REGNUM = %d\n",
6367 fprintf_unfiltered (file
,
6368 "mips_dump_tdep: RA_REGNUM = %d\n",
6371 fprintf_unfiltered (file
,
6372 "mips_dump_tdep: SAVED_BYTES = %d\n",
6376 fprintf_unfiltered (file
,
6377 "mips_dump_tdep: SAVED_FP = %d\n",
6381 fprintf_unfiltered (file
,
6382 "mips_dump_tdep: SAVED_PC = %d\n",
6385 fprintf_unfiltered (file
,
6386 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6387 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6388 fprintf_unfiltered (file
,
6389 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6390 fprintf_unfiltered (file
,
6391 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6393 fprintf_unfiltered (file
,
6394 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6395 SIGFRAME_FPREGSAVE_OFF
);
6396 fprintf_unfiltered (file
,
6397 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6399 fprintf_unfiltered (file
,
6400 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6401 SIGFRAME_REGSAVE_OFF
);
6402 fprintf_unfiltered (file
,
6403 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
6405 fprintf_unfiltered (file
,
6406 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6407 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6408 fprintf_unfiltered (file
,
6409 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6410 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6411 fprintf_unfiltered (file
,
6412 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6413 SOFTWARE_SINGLE_STEP_P ());
6414 fprintf_unfiltered (file
,
6415 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6416 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6417 #ifdef STACK_END_ADDR
6418 fprintf_unfiltered (file
,
6419 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6422 fprintf_unfiltered (file
,
6423 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6424 XSTRING (STEP_SKIPS_DELAY (PC
)));
6425 fprintf_unfiltered (file
,
6426 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6427 STEP_SKIPS_DELAY_P
);
6428 fprintf_unfiltered (file
,
6429 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6430 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6431 fprintf_unfiltered (file
,
6432 "mips_dump_tdep: T9_REGNUM = %d\n",
6434 fprintf_unfiltered (file
,
6435 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6436 fprintf_unfiltered (file
,
6437 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6438 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
6439 fprintf_unfiltered (file
,
6440 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6441 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6443 fprintf_unfiltered (file
,
6444 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6445 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6448 fprintf_unfiltered (file
,
6449 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6452 #ifdef TRACE_FLAVOR_SIZE
6453 fprintf_unfiltered (file
,
6454 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6458 fprintf_unfiltered (file
,
6459 "mips_dump_tdep: TRACE_SET # %s\n",
6460 XSTRING (TRACE_SET (X
,STATE
)));
6462 #ifdef UNUSED_REGNUM
6463 fprintf_unfiltered (file
,
6464 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6467 fprintf_unfiltered (file
,
6468 "mips_dump_tdep: V0_REGNUM = %d\n",
6470 fprintf_unfiltered (file
,
6471 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6472 (long) VM_MIN_ADDRESS
);
6473 fprintf_unfiltered (file
,
6474 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6476 fprintf_unfiltered (file
,
6477 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6481 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6484 _initialize_mips_tdep (void)
6486 static struct cmd_list_element
*mipsfpulist
= NULL
;
6487 struct cmd_list_element
*c
;
6489 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6490 if (MIPS_ABI_LAST
+ 1
6491 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6492 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6494 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6496 /* Add root prefix command for all "set mips"/"show mips" commands */
6497 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6498 "Various MIPS specific commands.",
6499 &setmipscmdlist
, "set mips ", 0, &setlist
);
6501 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6502 "Various MIPS specific commands.",
6503 &showmipscmdlist
, "show mips ", 0, &showlist
);
6505 /* Allow the user to override the saved register size. */
6506 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6509 &mips_saved_regsize_string
, "\
6510 Set size of general purpose registers saved on the stack.\n\
6511 This option can be set to one of:\n\
6512 32 - Force GDB to treat saved GP registers as 32-bit\n\
6513 64 - Force GDB to treat saved GP registers as 64-bit\n\
6514 auto - Allow GDB to use the target's default setting or autodetect the\n\
6515 saved GP register size from information contained in the executable.\n\
6520 /* Allow the user to override the argument stack size. */
6521 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6524 &mips_stack_argsize_string
, "\
6525 Set the amount of stack space reserved for each argument.\n\
6526 This option can be set to one of:\n\
6527 32 - Force GDB to allocate 32-bit chunks per argument\n\
6528 64 - Force GDB to allocate 64-bit chunks per argument\n\
6529 auto - Allow GDB to determine the correct setting from the current\n\
6530 target and executable (default)",
6534 /* Allow the user to override the ABI. */
6535 c
= add_set_enum_cmd
6536 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6537 "Set the ABI used by this program.\n"
6538 "This option can be set to one of:\n"
6539 " auto - the default ABI associated with the current binary\n"
6547 set_cmd_sfunc (c
, mips_abi_update
);
6548 add_cmd ("abi", class_obscure
, show_mips_abi
,
6549 "Show ABI in use by MIPS target", &showmipscmdlist
);
6551 /* Let the user turn off floating point and set the fence post for
6552 heuristic_proc_start. */
6554 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6555 "Set use of MIPS floating-point coprocessor.",
6556 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6557 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6558 "Select single-precision MIPS floating-point coprocessor.",
6560 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6561 "Select double-precision MIPS floating-point coprocessor.",
6563 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6564 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6565 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6566 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6567 "Select no MIPS floating-point coprocessor.",
6569 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6570 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6571 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6572 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6573 "Select MIPS floating-point coprocessor automatically.",
6575 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6576 "Show current use of MIPS floating-point coprocessor target.",
6579 /* We really would like to have both "0" and "unlimited" work, but
6580 command.c doesn't deal with that. So make it a var_zinteger
6581 because the user can always use "999999" or some such for unlimited. */
6582 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6583 (char *) &heuristic_fence_post
,
6585 Set the distance searched for the start of a function.\n\
6586 If you are debugging a stripped executable, GDB needs to search through the\n\
6587 program for the start of a function. This command sets the distance of the\n\
6588 search. The only need to set it is when debugging a stripped executable.",
6590 /* We need to throw away the frame cache when we set this, since it
6591 might change our ability to get backtraces. */
6592 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6593 add_show_from_set (c
, &showlist
);
6595 /* Allow the user to control whether the upper bits of 64-bit
6596 addresses should be zeroed. */
6597 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6598 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6599 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6600 allow GDB to determine the correct value.\n", "\
6601 Show zeroing of upper 32 bits of 64-bit addresses.",
6602 NULL
, show_mask_address
,
6603 &setmipscmdlist
, &showmipscmdlist
);
6605 /* Allow the user to control the size of 32 bit registers within the
6606 raw remote packet. */
6607 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
6610 (char *)&mips64_transfers_32bit_regs_p
, "\
6611 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
6612 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6613 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6614 64 bits for others. Use \"off\" to disable compatibility mode",
6618 /* Debug this files internals. */
6619 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6620 &mips_debug
, "Set mips debugging.\n\
6621 When non-zero, mips specific debugging is enabled.", &setdebuglist
),