1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
58 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
60 /* A useful bit in the CP0 status register (PS_REGNUM). */
61 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
62 #define ST0_FR (1 << 26)
64 /* The sizes of floating point registers. */
68 MIPS_FPU_SINGLE_REGSIZE
= 4,
69 MIPS_FPU_DOUBLE_REGSIZE
= 8
73 static const char *mips_abi_string
;
75 static const char *mips_abi_strings
[] = {
86 struct frame_extra_info
88 mips_extra_func_info_t proc_desc
;
92 /* Various MIPS ISA options (related to stack analysis) can be
93 overridden dynamically. Establish an enum/array for managing
96 static const char size_auto
[] = "auto";
97 static const char size_32
[] = "32";
98 static const char size_64
[] = "64";
100 static const char *size_enums
[] = {
107 /* Some MIPS boards don't support floating point while others only
108 support single-precision floating-point operations. See also
109 FP_REGISTER_DOUBLE. */
113 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
114 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
115 MIPS_FPU_NONE
/* No floating point. */
118 #ifndef MIPS_DEFAULT_FPU_TYPE
119 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
121 static int mips_fpu_type_auto
= 1;
122 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
124 static int mips_debug
= 0;
126 /* MIPS specific per-architecture information */
129 /* from the elf header */
133 enum mips_abi mips_abi
;
134 enum mips_abi found_abi
;
135 enum mips_fpu_type mips_fpu_type
;
136 int mips_last_arg_regnum
;
137 int mips_last_fp_arg_regnum
;
138 int mips_default_saved_regsize
;
139 int mips_fp_register_double
;
140 int mips_default_stack_argsize
;
141 int default_mask_address_p
;
142 /* Is the target using 64-bit raw integer registers but only
143 storing a left-aligned 32-bit value in each? */
144 int mips64_transfers_32bit_regs_p
;
145 /* Indexes for various registers. IRIX and embedded have
146 different values. This contains the "public" fields. Don't
147 add any that do not need to be public. */
148 const struct mips_regnum
*regnum
;
149 /* Register names table for the current register set. */
150 const char **mips_processor_reg_names
;
153 const struct mips_regnum
*
154 mips_regnum (struct gdbarch
*gdbarch
)
156 return gdbarch_tdep (gdbarch
)->regnum
;
160 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
162 return mips_regnum (gdbarch
)->fp0
+ 12;
165 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
166 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
168 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
170 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
172 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
174 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
175 functions to test, set, or clear bit 0 of addresses. */
178 is_mips16_addr (CORE_ADDR addr
)
184 make_mips16_addr (CORE_ADDR addr
)
190 unmake_mips16_addr (CORE_ADDR addr
)
192 return ((addr
) & ~1);
195 /* Return the contents of register REGNUM as a signed integer. */
198 read_signed_register (int regnum
)
200 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
201 deprecated_read_register_gen (regnum
, buf
);
202 return (extract_signed_integer
203 (buf
, register_size (current_gdbarch
, regnum
)));
207 read_signed_register_pid (int regnum
, ptid_t ptid
)
212 if (ptid_equal (ptid
, inferior_ptid
))
213 return read_signed_register (regnum
);
215 save_ptid
= inferior_ptid
;
217 inferior_ptid
= ptid
;
219 retval
= read_signed_register (regnum
);
221 inferior_ptid
= save_ptid
;
226 /* Return the MIPS ABI associated with GDBARCH. */
228 mips_abi (struct gdbarch
*gdbarch
)
230 return gdbarch_tdep (gdbarch
)->mips_abi
;
234 mips_regsize (struct gdbarch
*gdbarch
)
236 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
237 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
240 /* Return the currently configured (or set) saved register size. */
242 static const char *mips_saved_regsize_string
= size_auto
;
245 mips_saved_regsize (struct gdbarch_tdep
*tdep
)
247 if (mips_saved_regsize_string
== size_auto
)
248 return tdep
->mips_default_saved_regsize
;
249 else if (mips_saved_regsize_string
== size_64
)
251 else /* if (mips_saved_regsize_string == size_32) */
255 /* Functions for setting and testing a bit in a minimal symbol that
256 marks it as 16-bit function. The MSB of the minimal symbol's
257 "info" field is used for this purpose.
259 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
260 i.e. refers to a 16-bit function, and sets a "special" bit in a
261 minimal symbol to mark it as a 16-bit function
263 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
266 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
268 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
270 MSYMBOL_INFO (msym
) = (char *)
271 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
272 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
277 msymbol_is_special (struct minimal_symbol
*msym
)
279 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
282 /* XFER a value from the big/little/left end of the register.
283 Depending on the size of the value it might occupy the entire
284 register or just part of it. Make an allowance for this, aligning
285 things accordingly. */
288 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
289 enum bfd_endian endian
, bfd_byte
* in
,
290 const bfd_byte
* out
, int buf_offset
)
292 bfd_byte reg
[MAX_REGISTER_SIZE
];
294 gdb_assert (reg_num
>= NUM_REGS
);
295 /* Need to transfer the left or right part of the register, based on
296 the targets byte order. */
300 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
302 case BFD_ENDIAN_LITTLE
:
305 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
309 internal_error (__FILE__
, __LINE__
, "bad switch");
312 fprintf_unfiltered (gdb_stderr
,
313 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
314 reg_num
, reg_offset
, buf_offset
, length
);
315 if (mips_debug
&& out
!= NULL
)
318 fprintf_unfiltered (gdb_stdlog
, "out ");
319 for (i
= 0; i
< length
; i
++)
320 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
323 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
326 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
328 if (mips_debug
&& in
!= NULL
)
331 fprintf_unfiltered (gdb_stdlog
, "in ");
332 for (i
= 0; i
< length
; i
++)
333 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
336 fprintf_unfiltered (gdb_stdlog
, "\n");
339 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
340 compatiblity mode. A return value of 1 means that we have
341 physical 64-bit registers, but should treat them as 32-bit registers. */
344 mips2_fp_compat (void)
346 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
348 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
353 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
354 in all the places we deal with FP registers. PR gdb/413. */
355 /* Otherwise check the FR bit in the status register - it controls
356 the FP compatiblity mode. If it is clear we are in compatibility
358 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
365 /* Indicate that the ABI makes use of double-precision registers
366 provided by the FPU (rather than combining pairs of registers to
367 form double-precision values). See also MIPS_FPU_TYPE. */
368 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
370 /* The amount of space reserved on the stack for registers. This is
371 different to MIPS_SAVED_REGSIZE as it determines the alignment of
372 data allocated after the registers have run out. */
374 static const char *mips_stack_argsize_string
= size_auto
;
377 mips_stack_argsize (struct gdbarch_tdep
*tdep
)
379 if (mips_stack_argsize_string
== size_auto
)
380 return tdep
->mips_default_stack_argsize
;
381 else if (mips_stack_argsize_string
== size_64
)
383 else /* if (mips_stack_argsize_string == size_32) */
387 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
389 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
390 struct frame_info
*, int);
392 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
394 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
396 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
398 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
399 struct frame_info
*next_frame
,
402 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
403 mips_extra_func_info_t proc_desc
);
405 static struct type
*mips_float_register_type (void);
406 static struct type
*mips_double_register_type (void);
408 /* The list of available "set mips " and "show mips " commands */
410 static struct cmd_list_element
*setmipscmdlist
= NULL
;
411 static struct cmd_list_element
*showmipscmdlist
= NULL
;
413 /* Integer registers 0 thru 31 are handled explicitly by
414 mips_register_name(). Processor specific registers 32 and above
415 are listed in the followign tables. */
418 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
422 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
423 "sr", "lo", "hi", "bad", "cause", "pc",
424 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
425 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
426 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
427 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
428 "fsr", "fir", "" /*"fp" */ , "",
429 "", "", "", "", "", "", "", "",
430 "", "", "", "", "", "", "", "",
433 /* Names of IDT R3041 registers. */
435 static const char *mips_r3041_reg_names
[] = {
436 "sr", "lo", "hi", "bad", "cause", "pc",
437 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
438 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
439 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
440 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
441 "fsr", "fir", "", /*"fp" */ "",
442 "", "", "bus", "ccfg", "", "", "", "",
443 "", "", "port", "cmp", "", "", "epc", "prid",
446 /* Names of tx39 registers. */
448 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
449 "sr", "lo", "hi", "bad", "cause", "pc",
450 "", "", "", "", "", "", "", "",
451 "", "", "", "", "", "", "", "",
452 "", "", "", "", "", "", "", "",
453 "", "", "", "", "", "", "", "",
455 "", "", "", "", "", "", "", "",
456 "", "", "config", "cache", "debug", "depc", "epc", ""
459 /* Names of IRIX registers. */
460 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
461 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
462 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
463 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
464 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
465 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
469 /* Return the name of the register corresponding to REGNO. */
471 mips_register_name (int regno
)
473 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
474 /* GPR names for all ABIs other than n32/n64. */
475 static char *mips_gpr_names
[] = {
476 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
477 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
478 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
479 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
482 /* GPR names for n32 and n64 ABIs. */
483 static char *mips_n32_n64_gpr_names
[] = {
484 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
485 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
486 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
487 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
490 enum mips_abi abi
= mips_abi (current_gdbarch
);
492 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
493 don't make the raw register names visible. */
494 int rawnum
= regno
% NUM_REGS
;
495 if (regno
< NUM_REGS
)
498 /* The MIPS integer registers are always mapped from 0 to 31. The
499 names of the registers (which reflects the conventions regarding
500 register use) vary depending on the ABI. */
501 if (0 <= rawnum
&& rawnum
< 32)
503 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
504 return mips_n32_n64_gpr_names
[rawnum
];
506 return mips_gpr_names
[rawnum
];
508 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
510 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
511 return tdep
->mips_processor_reg_names
[rawnum
- 32];
514 internal_error (__FILE__
, __LINE__
,
515 "mips_register_name: bad register number %d", rawnum
);
518 /* Return the groups that a MIPS register can be categorised into. */
521 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
522 struct reggroup
*reggroup
)
527 int rawnum
= regnum
% NUM_REGS
;
528 int pseudo
= regnum
/ NUM_REGS
;
529 if (reggroup
== all_reggroup
)
531 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
532 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
533 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
534 (gdbarch), as not all architectures are multi-arch. */
535 raw_p
= rawnum
< NUM_REGS
;
536 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
538 if (reggroup
== float_reggroup
)
539 return float_p
&& pseudo
;
540 if (reggroup
== vector_reggroup
)
541 return vector_p
&& pseudo
;
542 if (reggroup
== general_reggroup
)
543 return (!vector_p
&& !float_p
) && pseudo
;
544 /* Save the pseudo registers. Need to make certain that any code
545 extracting register values from a saved register cache also uses
547 if (reggroup
== save_reggroup
)
548 return raw_p
&& pseudo
;
549 /* Restore the same pseudo register. */
550 if (reggroup
== restore_reggroup
)
551 return raw_p
&& pseudo
;
555 /* Map the symbol table registers which live in the range [1 *
556 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
557 registers. Take care of alignment and size problems. */
560 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
561 int cookednum
, void *buf
)
563 int rawnum
= cookednum
% NUM_REGS
;
564 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
565 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
566 regcache_raw_read (regcache
, rawnum
, buf
);
567 else if (register_size (gdbarch
, rawnum
) >
568 register_size (gdbarch
, cookednum
))
570 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
571 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
572 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
574 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
577 internal_error (__FILE__
, __LINE__
, "bad register size");
581 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
582 struct regcache
*regcache
, int cookednum
,
585 int rawnum
= cookednum
% NUM_REGS
;
586 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
587 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
588 regcache_raw_write (regcache
, rawnum
, buf
);
589 else if (register_size (gdbarch
, rawnum
) >
590 register_size (gdbarch
, cookednum
))
592 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
593 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
594 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
596 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
599 internal_error (__FILE__
, __LINE__
, "bad register size");
602 /* Table to translate MIPS16 register field to actual register number. */
603 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
605 /* Heuristic_proc_start may hunt through the text section for a long
606 time across a 2400 baud serial line. Allows the user to limit this
609 static unsigned int heuristic_fence_post
= 0;
611 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
612 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
613 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
614 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
615 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
616 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
617 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
618 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
619 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
620 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
621 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
622 this will corrupt pdr.iline. Fortunately we don't use it. */
623 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
624 #define _PROC_MAGIC_ 0x0F0F0F0F
625 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
626 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
628 struct linked_proc_info
630 struct mips_extra_func_info info
;
631 struct linked_proc_info
*next
;
633 *linked_proc_desc_table
= NULL
;
635 /* Number of bytes of storage in the actual machine representation for
636 register N. NOTE: This defines the pseudo register type so need to
637 rebuild the architecture vector. */
639 static int mips64_transfers_32bit_regs_p
= 0;
642 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
643 struct cmd_list_element
*c
)
645 struct gdbarch_info info
;
646 gdbarch_info_init (&info
);
647 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
648 instead of relying on globals. Doing that would let generic code
649 handle the search for this specific architecture. */
650 if (!gdbarch_update_p (info
))
652 mips64_transfers_32bit_regs_p
= 0;
653 error ("32-bit compatibility mode not supported");
657 /* Convert to/from a register and the corresponding memory value. */
660 mips_convert_register_p (int regnum
, struct type
*type
)
662 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
663 && register_size (current_gdbarch
, regnum
) == 4
664 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
665 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
666 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
670 mips_register_to_value (struct frame_info
*frame
, int regnum
,
671 struct type
*type
, void *to
)
673 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
674 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
678 mips_value_to_register (struct frame_info
*frame
, int regnum
,
679 struct type
*type
, const void *from
)
681 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
682 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
685 /* Return the GDB type object for the "standard" data type of data in
689 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
691 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
692 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
693 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
695 /* The floating-point registers raw, or cooked, always match
696 mips_regsize(), and also map 1:1, byte for byte. */
697 switch (gdbarch_byte_order (gdbarch
))
700 if (mips_regsize (gdbarch
) == 4)
701 return builtin_type_ieee_single_big
;
703 return builtin_type_ieee_double_big
;
704 case BFD_ENDIAN_LITTLE
:
705 if (mips_regsize (gdbarch
) == 4)
706 return builtin_type_ieee_single_little
;
708 return builtin_type_ieee_double_little
;
709 case BFD_ENDIAN_UNKNOWN
:
711 internal_error (__FILE__
, __LINE__
, "bad switch");
715 (NUM_REGS
+ mips_regnum (current_gdbarch
)->fp_control_status
)
716 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
717 /* The pseudo/cooked view of the embedded registers is always
718 32-bit. The raw view is handled below. */
719 return builtin_type_int32
;
720 else if (regnum
>= NUM_REGS
&& mips_regsize (gdbarch
)
721 && gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
722 /* The target, while using a 64-bit register buffer, is only
723 transfering 32-bits of each integer register. Reflect this in
724 the cooked/pseudo register value. */
725 return builtin_type_int32
;
726 else if (mips_regsize (gdbarch
) == 8)
728 return builtin_type_int64
;
731 return builtin_type_int32
;
734 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
739 return read_signed_register (SP_REGNUM
);
742 /* Should the upper word of 64-bit addresses be zeroed? */
743 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
746 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
748 switch (mask_address_var
)
750 case AUTO_BOOLEAN_TRUE
:
752 case AUTO_BOOLEAN_FALSE
:
755 case AUTO_BOOLEAN_AUTO
:
756 return tdep
->default_mask_address_p
;
758 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
764 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
766 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
767 switch (mask_address_var
)
769 case AUTO_BOOLEAN_TRUE
:
770 printf_filtered ("The 32 bit mips address mask is enabled\n");
772 case AUTO_BOOLEAN_FALSE
:
773 printf_filtered ("The 32 bit mips address mask is disabled\n");
775 case AUTO_BOOLEAN_AUTO
:
777 ("The 32 bit address mask is set automatically. Currently %s\n",
778 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
781 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
786 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
789 pc_is_mips16 (bfd_vma memaddr
)
791 struct minimal_symbol
*sym
;
793 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
794 if (is_mips16_addr (memaddr
))
797 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
798 the high bit of the info field. Use this to decide if the function is
799 MIPS16 or normal MIPS. */
800 sym
= lookup_minimal_symbol_by_pc (memaddr
);
802 return msymbol_is_special (sym
);
807 /* MIPS believes that the PC has a sign extended value. Perhaphs the
808 all registers should be sign extended for simplicity? */
811 mips_read_pc (ptid_t ptid
)
813 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
817 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
819 return frame_unwind_register_signed (next_frame
,
820 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
823 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
824 dummy frame. The frame ID's base needs to match the TOS value
825 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
828 static struct frame_id
829 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
831 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ SP_REGNUM
),
832 frame_pc_unwind (next_frame
));
836 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
838 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
841 /* This returns the PC of the first inst after the prologue. If we can't
842 find the prologue, then return 0. */
845 after_prologue (CORE_ADDR pc
, mips_extra_func_info_t proc_desc
)
847 struct symtab_and_line sal
;
848 CORE_ADDR func_addr
, func_end
;
850 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
851 to read the stack pointer from the current machine state, because
852 the current machine state has nothing to do with the information
853 we need from the proc_desc; and the process may or may not exist
856 proc_desc
= find_proc_desc (pc
, NULL
, 0);
860 /* If function is frameless, then we need to do it the hard way. I
861 strongly suspect that frameless always means prologueless... */
862 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
863 && PROC_FRAME_OFFSET (proc_desc
) == 0)
867 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
868 return 0; /* Unknown */
870 sal
= find_pc_line (func_addr
, 0);
872 if (sal
.end
< func_end
)
875 /* The line after the prologue is after the end of the function. In this
876 case, tell the caller to find the prologue the hard way. */
881 /* Decode a MIPS32 instruction that saves a register in the stack, and
882 set the appropriate bit in the general register mask or float register mask
883 to indicate which register is saved. This is a helper function
884 for mips_find_saved_regs. */
887 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
888 unsigned long *float_mask
)
892 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
893 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
894 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
896 /* It might be possible to use the instruction to
897 find the offset, rather than the code below which
898 is based on things being in a certain order in the
899 frame, but figuring out what the instruction's offset
900 is relative to might be a little tricky. */
901 reg
= (inst
& 0x001f0000) >> 16;
902 *gen_mask
|= (1 << reg
);
904 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
905 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
906 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
909 reg
= ((inst
& 0x001f0000) >> 16);
910 *float_mask
|= (1 << reg
);
914 /* Decode a MIPS16 instruction that saves a register in the stack, and
915 set the appropriate bit in the general register or float register mask
916 to indicate which register is saved. This is a helper function
917 for mips_find_saved_regs. */
920 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
922 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
924 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
925 *gen_mask
|= (1 << reg
);
927 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
929 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
930 *gen_mask
|= (1 << reg
);
932 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
933 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
934 *gen_mask
|= (1 << RA_REGNUM
);
938 /* Fetch and return instruction from the specified location. If the PC
939 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
942 mips_fetch_instruction (CORE_ADDR addr
)
944 char buf
[MIPS_INSTLEN
];
948 if (pc_is_mips16 (addr
))
950 instlen
= MIPS16_INSTLEN
;
951 addr
= unmake_mips16_addr (addr
);
954 instlen
= MIPS_INSTLEN
;
955 status
= read_memory_nobpt (addr
, buf
, instlen
);
957 memory_error (status
, addr
);
958 return extract_unsigned_integer (buf
, instlen
);
962 mips16_fetch_instruction (CORE_ADDR addr
)
964 char buf
[MIPS_INSTLEN
];
968 instlen
= MIPS16_INSTLEN
;
969 addr
= unmake_mips16_addr (addr
);
970 status
= read_memory_nobpt (addr
, buf
, instlen
);
972 memory_error (status
, addr
);
973 return extract_unsigned_integer (buf
, instlen
);
977 mips32_fetch_instruction (CORE_ADDR addr
)
979 char buf
[MIPS_INSTLEN
];
982 instlen
= MIPS_INSTLEN
;
983 status
= read_memory_nobpt (addr
, buf
, instlen
);
985 memory_error (status
, addr
);
986 return extract_unsigned_integer (buf
, instlen
);
990 /* These the fields of 32 bit mips instructions */
991 #define mips32_op(x) (x >> 26)
992 #define itype_op(x) (x >> 26)
993 #define itype_rs(x) ((x >> 21) & 0x1f)
994 #define itype_rt(x) ((x >> 16) & 0x1f)
995 #define itype_immediate(x) (x & 0xffff)
997 #define jtype_op(x) (x >> 26)
998 #define jtype_target(x) (x & 0x03ffffff)
1000 #define rtype_op(x) (x >> 26)
1001 #define rtype_rs(x) ((x >> 21) & 0x1f)
1002 #define rtype_rt(x) ((x >> 16) & 0x1f)
1003 #define rtype_rd(x) ((x >> 11) & 0x1f)
1004 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1005 #define rtype_funct(x) (x & 0x3f)
1008 mips32_relative_offset (unsigned long inst
)
1011 x
= itype_immediate (inst
);
1012 if (x
& 0x8000) /* sign bit set */
1014 x
|= 0xffff0000; /* sign extension */
1020 /* Determine whate to set a single step breakpoint while considering
1021 branch prediction */
1023 mips32_next_pc (CORE_ADDR pc
)
1027 inst
= mips_fetch_instruction (pc
);
1028 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1030 if (itype_op (inst
) >> 2 == 5)
1031 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1033 op
= (itype_op (inst
) & 0x03);
1043 goto greater_branch
;
1048 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1049 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1051 int tf
= itype_rt (inst
) & 0x01;
1052 int cnum
= itype_rt (inst
) >> 2;
1054 read_signed_register (mips_regnum (current_gdbarch
)->
1056 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1058 if (((cond
>> cnum
) & 0x01) == tf
)
1059 pc
+= mips32_relative_offset (inst
) + 4;
1064 pc
+= 4; /* Not a branch, next instruction is easy */
1067 { /* This gets way messy */
1069 /* Further subdivide into SPECIAL, REGIMM and other */
1070 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1072 case 0: /* SPECIAL */
1073 op
= rtype_funct (inst
);
1078 /* Set PC to that address */
1079 pc
= read_signed_register (rtype_rs (inst
));
1085 break; /* end SPECIAL */
1086 case 1: /* REGIMM */
1088 op
= itype_rt (inst
); /* branch condition */
1093 case 16: /* BLTZAL */
1094 case 18: /* BLTZALL */
1096 if (read_signed_register (itype_rs (inst
)) < 0)
1097 pc
+= mips32_relative_offset (inst
) + 4;
1099 pc
+= 8; /* after the delay slot */
1103 case 17: /* BGEZAL */
1104 case 19: /* BGEZALL */
1105 if (read_signed_register (itype_rs (inst
)) >= 0)
1106 pc
+= mips32_relative_offset (inst
) + 4;
1108 pc
+= 8; /* after the delay slot */
1110 /* All of the other instructions in the REGIMM category */
1115 break; /* end REGIMM */
1120 reg
= jtype_target (inst
) << 2;
1121 /* Upper four bits get never changed... */
1122 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1125 /* FIXME case JALX : */
1128 reg
= jtype_target (inst
) << 2;
1129 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1130 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1132 break; /* The new PC will be alternate mode */
1133 case 4: /* BEQ, BEQL */
1135 if (read_signed_register (itype_rs (inst
)) ==
1136 read_signed_register (itype_rt (inst
)))
1137 pc
+= mips32_relative_offset (inst
) + 4;
1141 case 5: /* BNE, BNEL */
1143 if (read_signed_register (itype_rs (inst
)) !=
1144 read_signed_register (itype_rt (inst
)))
1145 pc
+= mips32_relative_offset (inst
) + 4;
1149 case 6: /* BLEZ, BLEZL */
1150 if (read_signed_register (itype_rs (inst
) <= 0))
1151 pc
+= mips32_relative_offset (inst
) + 4;
1157 greater_branch
: /* BGTZ, BGTZL */
1158 if (read_signed_register (itype_rs (inst
) > 0))
1159 pc
+= mips32_relative_offset (inst
) + 4;
1166 } /* mips32_next_pc */
1168 /* Decoding the next place to set a breakpoint is irregular for the
1169 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1170 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1171 We dont want to set a single step instruction on the extend instruction
1175 /* Lots of mips16 instruction formats */
1176 /* Predicting jumps requires itype,ritype,i8type
1177 and their extensions extItype,extritype,extI8type
1179 enum mips16_inst_fmts
1181 itype
, /* 0 immediate 5,10 */
1182 ritype
, /* 1 5,3,8 */
1183 rrtype
, /* 2 5,3,3,5 */
1184 rritype
, /* 3 5,3,3,5 */
1185 rrrtype
, /* 4 5,3,3,3,2 */
1186 rriatype
, /* 5 5,3,3,1,4 */
1187 shifttype
, /* 6 5,3,3,3,2 */
1188 i8type
, /* 7 5,3,8 */
1189 i8movtype
, /* 8 5,3,3,5 */
1190 i8mov32rtype
, /* 9 5,3,5,3 */
1191 i64type
, /* 10 5,3,8 */
1192 ri64type
, /* 11 5,3,3,5 */
1193 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1194 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1195 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1196 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1197 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1198 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1199 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1200 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1201 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1202 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1204 /* I am heaping all the fields of the formats into one structure and
1205 then, only the fields which are involved in instruction extension */
1209 unsigned int regx
; /* Function in i8 type */
1214 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1215 for the bits which make up the immediatate extension. */
1218 extended_offset (unsigned int extension
)
1221 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1223 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1225 value
|= extension
& 0x01f; /* extract 4:0 */
1229 /* Only call this function if you know that this is an extendable
1230 instruction, It wont malfunction, but why make excess remote memory references?
1231 If the immediate operands get sign extended or somthing, do it after
1232 the extension is performed.
1234 /* FIXME: Every one of these cases needs to worry about sign extension
1235 when the offset is to be used in relative addressing */
1239 fetch_mips_16 (CORE_ADDR pc
)
1242 pc
&= 0xfffffffe; /* clear the low order bit */
1243 target_read_memory (pc
, buf
, 2);
1244 return extract_unsigned_integer (buf
, 2);
1248 unpack_mips16 (CORE_ADDR pc
,
1249 unsigned int extension
,
1251 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1256 switch (insn_format
)
1263 value
= extended_offset (extension
);
1264 value
= value
<< 11; /* rom for the original value */
1265 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1269 value
= inst
& 0x7ff;
1270 /* FIXME : Consider sign extension */
1279 { /* A register identifier and an offset */
1280 /* Most of the fields are the same as I type but the
1281 immediate value is of a different length */
1285 value
= extended_offset (extension
);
1286 value
= value
<< 8; /* from the original instruction */
1287 value
|= inst
& 0xff; /* eleven bits from instruction */
1288 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1289 if (value
& 0x4000) /* test the sign bit , bit 26 */
1291 value
&= ~0x3fff; /* remove the sign bit */
1297 value
= inst
& 0xff; /* 8 bits */
1298 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1299 /* FIXME: Do sign extension , this format needs it */
1300 if (value
& 0x80) /* THIS CONFUSES ME */
1302 value
&= 0xef; /* remove the sign bit */
1312 unsigned long value
;
1313 unsigned int nexthalf
;
1314 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1315 value
= value
<< 16;
1316 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1324 internal_error (__FILE__
, __LINE__
, "bad switch");
1326 upk
->offset
= offset
;
1333 add_offset_16 (CORE_ADDR pc
, int offset
)
1335 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1339 extended_mips16_next_pc (CORE_ADDR pc
,
1340 unsigned int extension
, unsigned int insn
)
1342 int op
= (insn
>> 11);
1345 case 2: /* Branch */
1348 struct upk_mips16 upk
;
1349 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1350 offset
= upk
.offset
;
1356 pc
+= (offset
<< 1) + 2;
1359 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1361 struct upk_mips16 upk
;
1362 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1363 pc
= add_offset_16 (pc
, upk
.offset
);
1364 if ((insn
>> 10) & 0x01) /* Exchange mode */
1365 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1372 struct upk_mips16 upk
;
1374 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1375 reg
= read_signed_register (upk
.regx
);
1377 pc
+= (upk
.offset
<< 1) + 2;
1384 struct upk_mips16 upk
;
1386 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1387 reg
= read_signed_register (upk
.regx
);
1389 pc
+= (upk
.offset
<< 1) + 2;
1394 case 12: /* I8 Formats btez btnez */
1396 struct upk_mips16 upk
;
1398 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1399 /* upk.regx contains the opcode */
1400 reg
= read_signed_register (24); /* Test register is 24 */
1401 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1402 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1403 /* pc = add_offset_16(pc,upk.offset) ; */
1404 pc
+= (upk
.offset
<< 1) + 2;
1409 case 29: /* RR Formats JR, JALR, JALR-RA */
1411 struct upk_mips16 upk
;
1412 /* upk.fmt = rrtype; */
1417 upk
.regx
= (insn
>> 8) & 0x07;
1418 upk
.regy
= (insn
>> 5) & 0x07;
1426 break; /* Function return instruction */
1432 break; /* BOGUS Guess */
1434 pc
= read_signed_register (reg
);
1441 /* This is an instruction extension. Fetch the real instruction
1442 (which follows the extension) and decode things based on
1446 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1459 mips16_next_pc (CORE_ADDR pc
)
1461 unsigned int insn
= fetch_mips_16 (pc
);
1462 return extended_mips16_next_pc (pc
, 0, insn
);
1465 /* The mips_next_pc function supports single_step when the remote
1466 target monitor or stub is not developed enough to do a single_step.
1467 It works by decoding the current instruction and predicting where a
1468 branch will go. This isnt hard because all the data is available.
1469 The MIPS32 and MIPS16 variants are quite different */
1471 mips_next_pc (CORE_ADDR pc
)
1474 return mips16_next_pc (pc
);
1476 return mips32_next_pc (pc
);
1479 /* Set up the 'saved_regs' array. This is a data structure containing
1480 the addresses on the stack where each register has been saved, for
1481 each stack frame. Registers that have not been saved will have
1482 zero here. The stack pointer register is special: rather than the
1483 address where the stack register has been saved,
1484 saved_regs[SP_REGNUM] will have the actual value of the previous
1485 frame's stack register. */
1488 mips_find_saved_regs (struct frame_info
*fci
)
1491 /* r0 bit means kernel trap */
1493 /* What registers have been saved? Bitmasks. */
1494 unsigned long gen_mask
, float_mask
;
1495 mips_extra_func_info_t proc_desc
;
1497 CORE_ADDR
*saved_regs
;
1498 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1500 if (deprecated_get_frame_saved_regs (fci
) != NULL
)
1502 saved_regs
= frame_saved_regs_zalloc (fci
);
1504 /* If it is the frame for sigtramp, the saved registers are located
1505 in a sigcontext structure somewhere on the stack. If the stack
1506 layout for sigtramp changes we might have to change these
1507 constants and the companion fixup_sigtramp in mdebugread.c */
1508 #ifndef SIGFRAME_BASE
1509 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1510 above the sigtramp frame. */
1511 #define SIGFRAME_BASE mips_regsize (current_gdbarch)
1512 /* FIXME! Are these correct?? */
1513 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch))
1514 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch))
1515 #define SIGFRAME_FPREGSAVE_OFF \
1516 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch))
1518 if ((get_frame_type (fci
) == SIGTRAMP_FRAME
))
1520 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1522 CORE_ADDR reg_position
=
1523 (get_frame_base (fci
) + SIGFRAME_REGSAVE_OFF
+
1524 ireg
* mips_regsize (current_gdbarch
));
1525 set_reg_offset (saved_regs
, ireg
, reg_position
);
1527 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1529 CORE_ADDR reg_position
= (get_frame_base (fci
)
1530 + SIGFRAME_FPREGSAVE_OFF
1531 + ireg
* mips_regsize (current_gdbarch
));
1532 set_reg_offset (saved_regs
,
1533 mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1537 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->pc
,
1538 get_frame_base (fci
) + SIGFRAME_PC_OFF
);
1539 /* SP_REGNUM, contains the value and not the address. */
1540 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1544 proc_desc
= get_frame_extra_info (fci
)->proc_desc
;
1545 if (proc_desc
== NULL
)
1546 /* I'm not sure how/whether this can happen. Normally when we
1547 can't find a proc_desc, we "synthesize" one using
1548 heuristic_proc_desc and set the saved_regs right away. */
1551 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1552 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1553 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1555 if ( /* In any frame other than the innermost or a frame interrupted
1556 by a signal, we assume that all registers have been saved.
1557 This assumes that all register saves in a function happen
1558 before the first function call. */
1559 (get_next_frame (fci
) == NULL
1560 || (get_frame_type (get_next_frame (fci
)) == SIGTRAMP_FRAME
))
1561 /* In a dummy frame we know exactly where things are saved. */
1562 && !PROC_DESC_IS_DUMMY (proc_desc
)
1563 /* Don't bother unless we are inside a function prologue.
1564 Outside the prologue, we know where everything is. */
1565 && in_prologue (get_frame_pc (fci
), PROC_LOW_ADDR (proc_desc
))
1566 /* Not sure exactly what kernel_trap means, but if it means the
1567 kernel saves the registers without a prologue doing it, we
1568 better not examine the prologue to see whether registers
1569 have been saved yet. */
1572 /* We need to figure out whether the registers that the
1573 proc_desc claims are saved have been saved yet. */
1577 /* Bitmasks; set if we have found a save for the register. */
1578 unsigned long gen_save_found
= 0;
1579 unsigned long float_save_found
= 0;
1582 /* If the address is odd, assume this is MIPS16 code. */
1583 addr
= PROC_LOW_ADDR (proc_desc
);
1584 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1586 /* Scan through this function's instructions preceding the
1587 current PC, and look for those that save registers. */
1588 while (addr
< get_frame_pc (fci
))
1590 inst
= mips_fetch_instruction (addr
);
1591 if (pc_is_mips16 (addr
))
1592 mips16_decode_reg_save (inst
, &gen_save_found
);
1594 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1597 gen_mask
= gen_save_found
;
1598 float_mask
= float_save_found
;
1601 /* Fill in the offsets for the registers which gen_mask says were
1604 CORE_ADDR reg_position
= (get_frame_base (fci
)
1605 + PROC_REG_OFFSET (proc_desc
));
1606 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1607 if (gen_mask
& 0x80000000)
1609 set_reg_offset (saved_regs
, ireg
, reg_position
);
1610 reg_position
-= mips_saved_regsize (tdep
);
1614 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1615 order of that normally used by gcc. Therefore, we have to fetch
1616 the first instruction of the function, and if it's an entry
1617 instruction that saves $s0 or $s1, correct their saved addresses. */
1618 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1620 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1621 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1625 int sreg_count
= (inst
>> 6) & 3;
1627 /* Check if the ra register was pushed on the stack. */
1628 CORE_ADDR reg_position
= (get_frame_base (fci
)
1629 + PROC_REG_OFFSET (proc_desc
));
1631 reg_position
-= mips_saved_regsize (tdep
);
1633 /* Check if the s0 and s1 registers were pushed on the
1635 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1637 set_reg_offset (saved_regs
, reg
, reg_position
);
1638 reg_position
-= mips_saved_regsize (tdep
);
1643 /* Fill in the offsets for the registers which float_mask says were
1646 CORE_ADDR reg_position
= (get_frame_base (fci
)
1647 + PROC_FREG_OFFSET (proc_desc
));
1649 /* Fill in the offsets for the float registers which float_mask
1651 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1652 if (float_mask
& 0x80000000)
1654 if (mips_saved_regsize (tdep
) == 4
1655 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1657 /* On a big endian 32 bit ABI, floating point registers
1658 are paired to form doubles such that the most
1659 significant part is in $f[N+1] and the least
1660 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1661 registers are also spilled as a pair and stored as a
1664 When little-endian the least significant part is
1665 stored first leading to the memory order $f[N] and
1668 Unfortunately, when big-endian the most significant
1669 part of the double is stored first, and the least
1670 significant is stored second. This leads to the
1671 registers being ordered in memory as firt $f[N+1] and
1674 For the big-endian case make certain that the
1675 addresses point at the correct (swapped) locations
1676 $f[N] and $f[N+1] pair (keep in mind that
1677 reg_position is decremented each time through the
1680 set_reg_offset (saved_regs
,
1681 mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1682 reg_position
- mips_saved_regsize (tdep
));
1684 set_reg_offset (saved_regs
,
1685 mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1686 reg_position
+ mips_saved_regsize (tdep
));
1689 set_reg_offset (saved_regs
,
1690 mips_regnum (current_gdbarch
)->fp0
+ ireg
,
1692 reg_position
-= mips_saved_regsize (tdep
);
1695 set_reg_offset (saved_regs
, mips_regnum (current_gdbarch
)->pc
,
1696 saved_regs
[RA_REGNUM
]);
1699 /* SP_REGNUM, contains the value and not the address. */
1700 set_reg_offset (saved_regs
, SP_REGNUM
, get_frame_base (fci
));
1703 struct mips_frame_cache
1706 struct trad_frame_saved_reg
*saved_regs
;
1710 static struct mips_frame_cache
*
1711 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1713 mips_extra_func_info_t proc_desc
;
1714 struct mips_frame_cache
*cache
;
1715 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1716 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1717 /* r0 bit means kernel trap */
1719 /* What registers have been saved? Bitmasks. */
1720 unsigned long gen_mask
, float_mask
;
1722 if ((*this_cache
) != NULL
)
1723 return (*this_cache
);
1724 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1725 (*this_cache
) = cache
;
1726 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1728 /* Get the mdebug proc descriptor. */
1729 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
, 1);
1730 if (proc_desc
== NULL
)
1731 /* I'm not sure how/whether this can happen. Normally when we
1732 can't find a proc_desc, we "synthesize" one using
1733 heuristic_proc_desc and set the saved_regs right away. */
1736 /* Extract the frame's base. */
1737 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1738 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1740 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1741 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1742 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1744 /* In any frame other than the innermost or a frame interrupted by a
1745 signal, we assume that all registers have been saved. This
1746 assumes that all register saves in a function happen before the
1747 first function call. */
1748 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1749 /* Not sure exactly what kernel_trap means, but if it means the
1750 kernel saves the registers without a prologue doing it, we
1751 better not examine the prologue to see whether registers
1752 have been saved yet. */
1755 /* We need to figure out whether the registers that the
1756 proc_desc claims are saved have been saved yet. */
1760 /* Bitmasks; set if we have found a save for the register. */
1761 unsigned long gen_save_found
= 0;
1762 unsigned long float_save_found
= 0;
1765 /* If the address is odd, assume this is MIPS16 code. */
1766 addr
= PROC_LOW_ADDR (proc_desc
);
1767 mips16
= pc_is_mips16 (addr
);
1769 /* Scan through this function's instructions preceding the
1770 current PC, and look for those that save registers. */
1771 while (addr
< frame_pc_unwind (next_frame
))
1775 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1777 addr
+= MIPS16_INSTLEN
;
1781 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1782 &gen_save_found
, &float_save_found
);
1783 addr
+= MIPS_INSTLEN
;
1786 gen_mask
= gen_save_found
;
1787 float_mask
= float_save_found
;
1790 /* Fill in the offsets for the registers which gen_mask says were
1793 CORE_ADDR reg_position
= (cache
->base
1794 + PROC_REG_OFFSET (proc_desc
));
1796 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1797 if (gen_mask
& 0x80000000)
1799 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1800 reg_position
-= mips_saved_regsize (tdep
);
1804 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1805 order of that normally used by gcc. Therefore, we have to fetch
1806 the first instruction of the function, and if it's an entry
1807 instruction that saves $s0 or $s1, correct their saved addresses. */
1808 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1810 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1811 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1815 int sreg_count
= (inst
>> 6) & 3;
1817 /* Check if the ra register was pushed on the stack. */
1818 CORE_ADDR reg_position
= (cache
->base
1819 + PROC_REG_OFFSET (proc_desc
));
1821 reg_position
-= mips_saved_regsize (tdep
);
1823 /* Check if the s0 and s1 registers were pushed on the
1825 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1827 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1829 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1830 reg_position
-= mips_saved_regsize (tdep
);
1835 /* Fill in the offsets for the registers which float_mask says were
1838 CORE_ADDR reg_position
= (cache
->base
1839 + PROC_FREG_OFFSET (proc_desc
));
1841 /* Fill in the offsets for the float registers which float_mask
1843 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1844 if (float_mask
& 0x80000000)
1846 if (mips_saved_regsize (tdep
) == 4
1847 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1849 /* On a big endian 32 bit ABI, floating point registers
1850 are paired to form doubles such that the most
1851 significant part is in $f[N+1] and the least
1852 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1853 registers are also spilled as a pair and stored as a
1856 When little-endian the least significant part is
1857 stored first leading to the memory order $f[N] and
1860 Unfortunately, when big-endian the most significant
1861 part of the double is stored first, and the least
1862 significant is stored second. This leads to the
1863 registers being ordered in memory as firt $f[N+1] and
1866 For the big-endian case make certain that the
1867 addresses point at the correct (swapped) locations
1868 $f[N] and $f[N+1] pair (keep in mind that
1869 reg_position is decremented each time through the
1872 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1873 .addr
= reg_position
- mips_saved_regsize (tdep
);
1875 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1876 .addr
= reg_position
+ mips_saved_regsize (tdep
);
1879 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1880 .addr
= reg_position
;
1881 reg_position
-= mips_saved_regsize (tdep
);
1884 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1885 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1888 /* SP_REGNUM, contains the value and not the address. */
1889 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ SP_REGNUM
, cache
->base
);
1891 return (*this_cache
);
1895 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1896 struct frame_id
*this_id
)
1898 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1900 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1904 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1906 int regnum
, int *optimizedp
,
1907 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1908 int *realnump
, void *valuep
)
1910 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1912 trad_frame_prev_register (next_frame
, info
->saved_regs
, regnum
,
1913 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1916 static const struct frame_unwind mips_mdebug_frame_unwind
=
1919 mips_mdebug_frame_this_id
,
1920 mips_mdebug_frame_prev_register
1923 static const struct frame_unwind
*
1924 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1926 return &mips_mdebug_frame_unwind
;
1930 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1933 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1938 static const struct frame_base mips_mdebug_frame_base
= {
1939 &mips_mdebug_frame_unwind
,
1940 mips_mdebug_frame_base_address
,
1941 mips_mdebug_frame_base_address
,
1942 mips_mdebug_frame_base_address
1945 static const struct frame_base
*
1946 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1948 return &mips_mdebug_frame_base
;
1952 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1954 /* Always a pseudo. */
1955 gdb_assert (regno
>= NUM_REGS
);
1959 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1962 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1963 /* The SP_REGNUM is special, its value is stored in saved_regs.
1964 In fact, it is so special that it can even only be fetched
1965 using a raw register number! Once this code as been converted
1966 to frame-unwind the problem goes away. */
1967 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1969 return frame_unwind_register_signed (fi
, regno
);
1973 /* mips_addr_bits_remove - remove useless address bits */
1976 mips_addr_bits_remove (CORE_ADDR addr
)
1978 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1979 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
1980 /* This hack is a work-around for existing boards using PMON, the
1981 simulator, and any other 64-bit targets that doesn't have true
1982 64-bit addressing. On these targets, the upper 32 bits of
1983 addresses are ignored by the hardware. Thus, the PC or SP are
1984 likely to have been sign extended to all 1s by instruction
1985 sequences that load 32-bit addresses. For example, a typical
1986 piece of code that loads an address is this:
1988 lui $r2, <upper 16 bits>
1989 ori $r2, <lower 16 bits>
1991 But the lui sign-extends the value such that the upper 32 bits
1992 may be all 1s. The workaround is simply to mask off these
1993 bits. In the future, gcc may be changed to support true 64-bit
1994 addressing, and this masking will have to be disabled. */
1995 return addr
&= 0xffffffffUL
;
2000 /* mips_software_single_step() is called just before we want to resume
2001 the inferior, if we want to single-step it but there is no hardware
2002 or kernel single-step support (MIPS on GNU/Linux for example). We find
2003 the target of the coming instruction and breakpoint it.
2005 single_step is also called just after the inferior stops. If we had
2006 set up a simulated single-step, we undo our damage. */
2009 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2011 static CORE_ADDR next_pc
;
2012 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2013 static binsn_quantum break_mem
;
2016 if (insert_breakpoints_p
)
2018 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2019 next_pc
= mips_next_pc (pc
);
2021 target_insert_breakpoint (next_pc
, break_mem
);
2024 target_remove_breakpoint (next_pc
, break_mem
);
2028 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
2033 ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev
))
2034 : get_next_frame (prev
)
2035 ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev
)) : read_pc ());
2036 tmp
= SKIP_TRAMPOLINE_CODE (pc
);
2037 return tmp
? tmp
: pc
;
2042 mips_frame_saved_pc (struct frame_info
*frame
)
2045 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2047 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
2049 /* Always unwind the cooked PC register value. */
2050 saved_pc
= frame_unwind_register_signed (frame
, NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
);
2054 mips_extra_func_info_t proc_desc
2055 = get_frame_extra_info (frame
)->proc_desc
;
2056 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2057 saved_pc
= read_memory_integer ((get_frame_base (frame
)
2058 - mips_saved_regsize (tdep
)),
2059 mips_saved_regsize (tdep
));
2062 /* We have to get the saved pc from the sigcontext if it is
2063 a signal handler frame. */
2064 int pcreg
= (get_frame_type (frame
) == SIGTRAMP_FRAME
2065 ? mips_regnum (current_gdbarch
)->pc
2066 : proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
2067 saved_pc
= read_next_frame_reg (frame
, NUM_REGS
+ pcreg
);
2070 return ADDR_BITS_REMOVE (saved_pc
);
2073 static struct mips_extra_func_info temp_proc_desc
;
2075 /* This hack will go away once the get_prev_frame() code has been
2076 modified to set the frame's type first. That is BEFORE init extra
2077 frame info et.al. is called. This is because it will become
2078 possible to skip the init extra info call for sigtramp and dummy
2080 static CORE_ADDR
*temp_saved_regs
;
2082 /* Set a register's saved stack address in temp_saved_regs. If an
2083 address has already been set for this register, do nothing; this
2084 way we will only recognize the first save of a given register in a
2087 For simplicity, save the address in both [0 .. NUM_REGS) and
2088 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
2089 is used as it is only second range (the ABI instead of ISA
2090 registers) that comes into play when finding saved registers in a
2094 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
2096 if (saved_regs
[regno
] == 0)
2098 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
2099 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
2104 /* Test whether the PC points to the return instruction at the
2105 end of a function. */
2108 mips_about_to_return (CORE_ADDR pc
)
2110 if (pc_is_mips16 (pc
))
2111 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2112 generates a "jr $ra"; other times it generates code to load
2113 the return address from the stack to an accessible register (such
2114 as $a3), then a "jr" using that register. This second case
2115 is almost impossible to distinguish from an indirect jump
2116 used for switch statements, so we don't even try. */
2117 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2119 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2123 /* This fencepost looks highly suspicious to me. Removing it also
2124 seems suspicious as it could affect remote debugging across serial
2128 heuristic_proc_start (CORE_ADDR pc
)
2135 pc
= ADDR_BITS_REMOVE (pc
);
2137 fence
= start_pc
- heuristic_fence_post
;
2141 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2142 fence
= VM_MIN_ADDRESS
;
2144 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
2146 /* search back for previous return */
2147 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2148 if (start_pc
< fence
)
2150 /* It's not clear to me why we reach this point when
2151 stop_soon, but with this test, at least we
2152 don't print out warnings for every child forked (eg, on
2153 decstation). 22apr93 rich@cygnus.com. */
2154 if (stop_soon
== NO_STOP_QUIETLY
)
2156 static int blurb_printed
= 0;
2159 ("Warning: GDB can't find the start of the function at 0x%s.",
2164 /* This actually happens frequently in embedded
2165 development, when you first connect to a board
2166 and your stack pointer and pc are nowhere in
2167 particular. This message needs to give people
2168 in that situation enough information to
2169 determine that it's no big deal. */
2170 printf_filtered ("\n\
2171 GDB is unable to find the start of the function at 0x%s\n\
2172 and thus can't determine the size of that function's stack frame.\n\
2173 This means that GDB may be unable to access that stack frame, or\n\
2174 the frames below it.\n\
2175 This problem is most likely caused by an invalid program counter or\n\
2177 However, if you think GDB should simply search farther back\n\
2178 from 0x%s for code which looks like the beginning of a\n\
2179 function, you can increase the range of the search using the `set\n\
2180 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2187 else if (pc_is_mips16 (start_pc
))
2189 unsigned short inst
;
2191 /* On MIPS16, any one of the following is likely to be the
2192 start of a function:
2196 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2197 inst
= mips_fetch_instruction (start_pc
);
2198 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2199 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2200 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2201 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2203 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2204 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2209 else if (mips_about_to_return (start_pc
))
2211 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2218 /* Fetch the immediate value from a MIPS16 instruction.
2219 If the previous instruction was an EXTEND, use it to extend
2220 the upper bits of the immediate value. This is a helper function
2221 for mips16_heuristic_proc_desc. */
2224 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2225 unsigned short inst
, /* current instruction */
2226 int nbits
, /* number of bits in imm field */
2227 int scale
, /* scale factor to be applied to imm */
2228 int is_signed
) /* is the imm field signed? */
2232 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2234 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2235 if (offset
& 0x8000) /* check for negative extend */
2236 offset
= 0 - (0x10000 - (offset
& 0xffff));
2237 return offset
| (inst
& 0x1f);
2241 int max_imm
= 1 << nbits
;
2242 int mask
= max_imm
- 1;
2243 int sign_bit
= max_imm
>> 1;
2245 offset
= inst
& mask
;
2246 if (is_signed
&& (offset
& sign_bit
))
2247 offset
= 0 - (max_imm
- offset
);
2248 return offset
* scale
;
2253 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2254 stream from start_pc to limit_pc. */
2257 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2258 struct frame_info
*next_frame
, CORE_ADDR sp
)
2261 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2262 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2263 unsigned inst
= 0; /* current instruction */
2264 unsigned entry_inst
= 0; /* the entry instruction */
2266 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2268 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2269 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2271 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2273 /* Save the previous instruction. If it's an EXTEND, we'll extract
2274 the immediate offset extension from it in mips16_get_imm. */
2277 /* Fetch and decode the instruction. */
2278 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2279 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2280 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2282 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2283 if (offset
< 0) /* negative stack adjustment? */
2284 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2286 /* Exit loop if a positive stack adjustment is found, which
2287 usually means that the stack cleanup code in the function
2288 epilogue is reached. */
2291 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2293 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2294 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2295 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2296 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2298 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2300 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2301 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2302 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2303 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2305 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2307 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2308 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2309 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2311 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2313 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2314 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2315 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2317 else if (inst
== 0x673d) /* move $s1, $sp */
2320 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2322 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2324 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2325 frame_addr
= sp
+ offset
;
2326 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2327 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2329 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2331 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2332 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2333 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2334 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2336 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2338 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2339 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2340 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2341 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2343 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2344 entry_inst
= inst
; /* save for later processing */
2345 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2346 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2349 /* The entry instruction is typically the first instruction in a function,
2350 and it stores registers at offsets relative to the value of the old SP
2351 (before the prologue). But the value of the sp parameter to this
2352 function is the new SP (after the prologue has been executed). So we
2353 can't calculate those offsets until we've seen the entire prologue,
2354 and can calculate what the old SP must have been. */
2355 if (entry_inst
!= 0)
2357 int areg_count
= (entry_inst
>> 8) & 7;
2358 int sreg_count
= (entry_inst
>> 6) & 3;
2360 /* The entry instruction always subtracts 32 from the SP. */
2361 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2363 /* Now we can calculate what the SP must have been at the
2364 start of the function prologue. */
2365 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2367 /* Check if a0-a3 were saved in the caller's argument save area. */
2368 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2370 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2371 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2372 offset
+= mips_saved_regsize (tdep
);
2375 /* Check if the ra register was pushed on the stack. */
2377 if (entry_inst
& 0x20)
2379 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2380 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2381 offset
-= mips_saved_regsize (tdep
);
2384 /* Check if the s0 and s1 registers were pushed on the stack. */
2385 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2387 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2388 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2389 offset
-= mips_saved_regsize (tdep
);
2395 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2396 struct frame_info
*next_frame
, CORE_ADDR sp
)
2399 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2401 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2402 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2403 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2404 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2405 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2407 unsigned long inst
, high_word
, low_word
;
2410 /* Fetch the instruction. */
2411 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2413 /* Save some code by pre-extracting some useful fields. */
2414 high_word
= (inst
>> 16) & 0xffff;
2415 low_word
= inst
& 0xffff;
2416 reg
= high_word
& 0x1f;
2418 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2419 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2420 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2422 if (low_word
& 0x8000) /* negative stack adjustment? */
2423 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2425 /* Exit loop if a positive stack adjustment is found, which
2426 usually means that the stack cleanup code in the function
2427 epilogue is reached. */
2430 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2432 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2433 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2435 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2437 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2438 but the register size used is only 32 bits. Make the address
2439 for the saved register point to the lower 32 bits. */
2440 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2441 set_reg_offset (temp_saved_regs
, reg
,
2442 sp
+ low_word
+ 8 - mips_regsize (current_gdbarch
));
2444 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2446 /* Old gcc frame, r30 is virtual frame pointer. */
2447 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2448 frame_addr
= sp
+ low_word
;
2449 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2451 unsigned alloca_adjust
;
2452 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2453 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2454 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2455 if (alloca_adjust
> 0)
2457 /* FP > SP + frame_size. This may be because
2458 * of an alloca or somethings similar.
2459 * Fix sp to "pre-alloca" value, and try again.
2461 sp
+= alloca_adjust
;
2466 /* move $30,$sp. With different versions of gas this will be either
2467 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2468 Accept any one of these. */
2469 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2471 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2472 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2474 unsigned alloca_adjust
;
2475 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2476 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2477 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2478 if (alloca_adjust
> 0)
2480 /* FP > SP + frame_size. This may be because
2481 * of an alloca or somethings similar.
2482 * Fix sp to "pre-alloca" value, and try again.
2484 sp
+= alloca_adjust
;
2489 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2491 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2492 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2497 static mips_extra_func_info_t
2498 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2499 struct frame_info
*next_frame
, int cur_frame
)
2504 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2510 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2511 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2512 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2513 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2514 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2515 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2517 if (start_pc
+ 200 < limit_pc
)
2518 limit_pc
= start_pc
+ 200;
2519 if (pc_is_mips16 (start_pc
))
2520 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2522 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2523 return &temp_proc_desc
;
2526 struct mips_objfile_private
2532 /* Global used to communicate between non_heuristic_proc_desc and
2533 compare_pdr_entries within qsort (). */
2534 static bfd
*the_bfd
;
2537 compare_pdr_entries (const void *a
, const void *b
)
2539 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2540 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2544 else if (lhs
== rhs
)
2550 static mips_extra_func_info_t
2551 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2553 CORE_ADDR startaddr
;
2554 mips_extra_func_info_t proc_desc
;
2555 struct block
*b
= block_for_pc (pc
);
2557 struct obj_section
*sec
;
2558 struct mips_objfile_private
*priv
;
2560 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2563 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2565 *addrptr
= startaddr
;
2569 sec
= find_pc_section (pc
);
2572 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2574 /* Search the ".pdr" section generated by GAS. This includes most of
2575 the information normally found in ECOFF PDRs. */
2577 the_bfd
= sec
->objfile
->obfd
;
2579 && (the_bfd
->format
== bfd_object
2580 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2581 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2583 /* Right now GAS only outputs the address as a four-byte sequence.
2584 This means that we should not bother with this method on 64-bit
2585 targets (until that is fixed). */
2587 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2588 sizeof (struct mips_objfile_private
));
2590 sec
->objfile
->obj_private
= priv
;
2592 else if (priv
== NULL
)
2596 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2597 sizeof (struct mips_objfile_private
));
2599 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2602 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2603 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2605 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2606 priv
->contents
, 0, priv
->size
);
2608 /* In general, the .pdr section is sorted. However, in the
2609 presence of multiple code sections (and other corner cases)
2610 it can become unsorted. Sort it so that we can use a faster
2612 qsort (priv
->contents
, priv
->size
/ 32, 32,
2613 compare_pdr_entries
);
2618 sec
->objfile
->obj_private
= priv
;
2622 if (priv
->size
!= 0)
2628 high
= priv
->size
/ 32;
2634 mid
= (low
+ high
) / 2;
2636 ptr
= priv
->contents
+ mid
* 32;
2637 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2638 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2639 SECT_OFF_TEXT (sec
->objfile
));
2640 if (pdr_pc
== startaddr
)
2642 if (pdr_pc
> startaddr
)
2647 while (low
!= high
);
2651 struct symbol
*sym
= find_pc_function (pc
);
2653 /* Fill in what we need of the proc_desc. */
2654 proc_desc
= (mips_extra_func_info_t
)
2655 obstack_alloc (&sec
->objfile
->objfile_obstack
,
2656 sizeof (struct mips_extra_func_info
));
2657 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2659 /* Only used for dummy frames. */
2660 PROC_HIGH_ADDR (proc_desc
) = 0;
2662 PROC_FRAME_OFFSET (proc_desc
)
2663 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2664 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2666 PROC_FRAME_ADJUST (proc_desc
) = 0;
2667 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2669 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2671 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2673 PROC_FREG_OFFSET (proc_desc
)
2674 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2675 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2677 proc_desc
->pdr
.isym
= (long) sym
;
2687 if (startaddr
> BLOCK_START (b
))
2689 /* This is the "pathological" case referred to in a comment in
2690 print_frame_info. It might be better to move this check into
2695 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2697 /* If we never found a PDR for this function in symbol reading, then
2698 examine prologues to find the information. */
2701 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2702 if (PROC_FRAME_REG (proc_desc
) == -1)
2712 static mips_extra_func_info_t
2713 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2715 mips_extra_func_info_t proc_desc
;
2716 CORE_ADDR startaddr
= 0;
2718 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2722 /* IF this is the topmost frame AND
2723 * (this proc does not have debugging information OR
2724 * the PC is in the procedure prologue)
2725 * THEN create a "heuristic" proc_desc (by analyzing
2726 * the actual code) to replace the "official" proc_desc.
2728 if (next_frame
== NULL
)
2730 struct symtab_and_line val
;
2731 struct symbol
*proc_symbol
=
2732 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2736 val
= find_pc_line (BLOCK_START
2737 (SYMBOL_BLOCK_VALUE (proc_symbol
)), 0);
2738 val
.pc
= val
.end
? val
.end
: pc
;
2740 if (!proc_symbol
|| pc
< val
.pc
)
2742 mips_extra_func_info_t found_heuristic
=
2743 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2744 pc
, next_frame
, cur_frame
);
2745 if (found_heuristic
)
2746 proc_desc
= found_heuristic
;
2752 /* Is linked_proc_desc_table really necessary? It only seems to be used
2753 by procedure call dummys. However, the procedures being called ought
2754 to have their own proc_descs, and even if they don't,
2755 heuristic_proc_desc knows how to create them! */
2757 struct linked_proc_info
*link
;
2759 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2760 if (PROC_LOW_ADDR (&link
->info
) <= pc
2761 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2765 startaddr
= heuristic_proc_start (pc
);
2767 proc_desc
= heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2773 get_frame_pointer (struct frame_info
*frame
, mips_extra_func_info_t proc_desc
)
2775 return (read_next_frame_reg (frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2776 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2779 static mips_extra_func_info_t cached_proc_desc
;
2782 mips_frame_chain (struct frame_info
*frame
)
2784 mips_extra_func_info_t proc_desc
;
2786 CORE_ADDR saved_pc
= DEPRECATED_FRAME_SAVED_PC (frame
);
2788 /* Check if the PC is inside a call stub. If it is, fetch the
2789 PC of the caller of that stub. */
2790 if ((tmp
= SKIP_TRAMPOLINE_CODE (saved_pc
)) != 0)
2793 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc
, 0, 0))
2795 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2796 is well, frame->frame the bottom of the current frame will
2797 contain that value. */
2798 return get_frame_base (frame
);
2801 /* Look up the procedure descriptor for this PC. */
2802 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2806 cached_proc_desc
= proc_desc
;
2808 /* If no frame pointer and frame size is zero, we must be at end
2809 of stack (or otherwise hosed). If we don't check frame size,
2810 we loop forever if we see a zero size frame. */
2811 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2812 && PROC_FRAME_OFFSET (proc_desc
) == 0
2813 /* The previous frame from a sigtramp frame might be frameless
2814 and have frame size zero. */
2815 && !(get_frame_type (frame
) == SIGTRAMP_FRAME
)
2816 /* For a generic dummy frame, let get_frame_pointer() unwind a
2817 register value saved as part of the dummy frame call. */
2818 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0)))
2821 return get_frame_pointer (frame
, proc_desc
);
2825 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2828 mips_extra_func_info_t proc_desc
;
2830 if (get_frame_type (fci
) == DUMMY_FRAME
)
2833 /* Use proc_desc calculated in frame_chain. When there is no
2834 next frame, i.e, get_next_frame (fci) == NULL, we call
2835 find_proc_desc () to calculate it, passing an explicit
2836 NULL as the frame parameter. */
2838 get_next_frame (fci
)
2840 : find_proc_desc (get_frame_pc (fci
),
2841 NULL
/* i.e, get_next_frame (fci) */ ,
2844 frame_extra_info_zalloc (fci
, sizeof (struct frame_extra_info
));
2846 get_frame_extra_info (fci
)->proc_desc
=
2847 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2850 /* Fixup frame-pointer - only needed for top frame */
2851 /* This may not be quite right, if proc has a real frame register.
2852 Get the value of the frame relative sp, procedure might have been
2853 interrupted by a signal at it's very start. */
2854 if (get_frame_pc (fci
) == PROC_LOW_ADDR (proc_desc
)
2855 && !PROC_DESC_IS_DUMMY (proc_desc
))
2856 deprecated_update_frame_base_hack (fci
,
2857 read_next_frame_reg (get_next_frame
2861 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci
), 0, 0))
2862 /* Do not ``fix'' fci->frame. It will have the value of the
2863 generic dummy frame's top-of-stack (since the draft
2864 fci->frame is obtained by returning the unwound stack
2865 pointer) and that is what we want. That way the fci->frame
2866 value will match the top-of-stack value that was saved as
2867 part of the dummy frames data. */
2870 deprecated_update_frame_base_hack (fci
,
2871 get_frame_pointer (get_next_frame
2875 if (proc_desc
== &temp_proc_desc
)
2879 /* Do not set the saved registers for a sigtramp frame,
2880 mips_find_saved_registers will do that for us. We can't
2881 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2883 /* FIXME: cagney/2002-11-18: This problem will go away once
2884 frame.c:get_prev_frame() is modified to set the frame's
2885 type before calling functions like this. */
2886 find_pc_partial_function (get_frame_pc (fci
), &name
,
2887 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2888 if (!PC_IN_SIGTRAMP (get_frame_pc (fci
), name
))
2890 frame_saved_regs_zalloc (fci
);
2891 /* Set value of previous frame's stack pointer.
2892 Remember that saved_regs[SP_REGNUM] is special in
2893 that it contains the value of the stack pointer
2894 register. The other saved_regs values are addresses
2895 (in the inferior) at which a given register's value
2897 set_reg_offset (temp_saved_regs
, SP_REGNUM
,
2898 get_frame_base (fci
));
2899 set_reg_offset (temp_saved_regs
, mips_regnum (current_gdbarch
)->pc
,
2900 temp_saved_regs
[RA_REGNUM
]);
2901 memcpy (deprecated_get_frame_saved_regs (fci
), temp_saved_regs
,
2902 SIZEOF_FRAME_SAVED_REGS
);
2906 /* hack: if argument regs are saved, guess these contain args */
2907 /* assume we can't tell how many args for now */
2908 get_frame_extra_info (fci
)->num_args
= -1;
2909 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2911 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2913 get_frame_extra_info (fci
)->num_args
= regnum
- A0_REGNUM
+ 1;
2920 /* MIPS stack frames are almost impenetrable. When execution stops,
2921 we basically have to look at symbol information for the function
2922 that we stopped in, which tells us *which* register (if any) is
2923 the base of the frame pointer, and what offset from that register
2924 the frame itself is at.
2926 This presents a problem when trying to examine a stack in memory
2927 (that isn't executing at the moment), using the "frame" command. We
2928 don't have a PC, nor do we have any registers except SP.
2930 This routine takes two arguments, SP and PC, and tries to make the
2931 cached frames look as if these two arguments defined a frame on the
2932 cache. This allows the rest of info frame to extract the important
2933 arguments without difficulty. */
2936 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2939 error ("MIPS frame specifications require two arguments: sp and pc");
2941 return create_new_frame (argv
[0], argv
[1]);
2944 /* According to the current ABI, should the type be passed in a
2945 floating-point register (assuming that there is space)? When there
2946 is no FPU, FP are not even considered as possibile candidates for
2947 FP registers and, consequently this returns false - forces FP
2948 arguments into integer registers. */
2951 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2953 return ((typecode
== TYPE_CODE_FLT
2955 && (typecode
== TYPE_CODE_STRUCT
2956 || typecode
== TYPE_CODE_UNION
)
2957 && TYPE_NFIELDS (arg_type
) == 1
2958 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2959 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2962 /* On o32, argument passing in GPRs depends on the alignment of the type being
2963 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2966 mips_type_needs_double_align (struct type
*type
)
2968 enum type_code typecode
= TYPE_CODE (type
);
2970 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2972 else if (typecode
== TYPE_CODE_STRUCT
)
2974 if (TYPE_NFIELDS (type
) < 1)
2976 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2978 else if (typecode
== TYPE_CODE_UNION
)
2982 n
= TYPE_NFIELDS (type
);
2983 for (i
= 0; i
< n
; i
++)
2984 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2991 /* Adjust the address downward (direction of stack growth) so that it
2992 is correctly aligned for a new stack frame. */
2994 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2996 return align_down (addr
, 16);
2999 /* Determine how a return value is stored within the MIPS register
3000 file, given the return type `valtype'. */
3002 struct return_value_word
3011 return_value_location (struct type
*valtype
,
3012 struct return_value_word
*hi
,
3013 struct return_value_word
*lo
)
3015 int len
= TYPE_LENGTH (valtype
);
3016 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3018 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3019 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3020 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3022 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3024 /* We need to break a 64bit float in two 32 bit halves and
3025 spread them across a floating-point register pair. */
3026 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3027 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3028 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3029 && register_size (current_gdbarch
,
3030 mips_regnum (current_gdbarch
)->
3031 fp0
) == 8) ? 4 : 0);
3032 hi
->reg_offset
= lo
->reg_offset
;
3033 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
3034 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
3040 /* The floating point value fits in a single floating-point
3042 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3043 && register_size (current_gdbarch
,
3044 mips_regnum (current_gdbarch
)->
3046 && len
== 4) ? 4 : 0);
3047 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
3058 /* Locate a result possibly spread across two registers. */
3060 lo
->reg
= regnum
+ 0;
3061 hi
->reg
= regnum
+ 1;
3062 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3063 && len
< mips_saved_regsize (tdep
))
3065 /* "un-left-justify" the value in the low register */
3066 lo
->reg_offset
= mips_saved_regsize (tdep
) - len
;
3071 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_saved_regsize (tdep
) /* odd-size structs */
3072 && len
< mips_saved_regsize (tdep
) * 2
3073 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3074 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3076 /* "un-left-justify" the value spread across two registers. */
3077 lo
->reg_offset
= 2 * mips_saved_regsize (tdep
) - len
;
3078 lo
->len
= mips_saved_regsize (tdep
) - lo
->reg_offset
;
3080 hi
->len
= len
- lo
->len
;
3084 /* Only perform a partial copy of the second register. */
3087 if (len
> mips_saved_regsize (tdep
))
3089 lo
->len
= mips_saved_regsize (tdep
);
3090 hi
->len
= len
- mips_saved_regsize (tdep
);
3098 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3099 && register_size (current_gdbarch
, regnum
) == 8
3100 && mips_saved_regsize (tdep
) == 4)
3102 /* Account for the fact that only the least-signficant part
3103 of the register is being used */
3104 lo
->reg_offset
+= 4;
3105 hi
->reg_offset
+= 4;
3108 hi
->buf_offset
= lo
->len
;
3112 /* Should call_function allocate stack space for a struct return? */
3115 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
3117 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3118 return (TYPE_LENGTH (type
) > 2 * mips_saved_regsize (tdep
));
3121 /* Should call_function pass struct by reference?
3122 For each architecture, structs are passed either by
3123 value or by reference, depending on their size. */
3126 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
3128 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
3129 int len
= TYPE_LENGTH (check_typedef (type
));
3130 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3132 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
3133 return (len
> mips_saved_regsize (tdep
));
3139 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3140 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3141 int nargs
, struct value
**args
, CORE_ADDR sp
,
3142 int struct_return
, CORE_ADDR struct_addr
)
3148 int stack_offset
= 0;
3149 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3151 /* For shared libraries, "t9" needs to point at the function
3153 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3155 /* Set the return address register to point to the entry point of
3156 the program, where a breakpoint lies in wait. */
3157 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3159 /* First ensure that the stack and structure return address (if any)
3160 are properly aligned. The stack has to be at least 64-bit
3161 aligned even on 32-bit machines, because doubles must be 64-bit
3162 aligned. For n32 and n64, stack frames need to be 128-bit
3163 aligned, so we round to this widest known alignment. */
3165 sp
= align_down (sp
, 16);
3166 struct_addr
= align_down (struct_addr
, 16);
3168 /* Now make space on the stack for the args. We allocate more
3169 than necessary for EABI, because the first few arguments are
3170 passed in registers, but that's OK. */
3171 for (argnum
= 0; argnum
< nargs
; argnum
++)
3172 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3173 mips_stack_argsize (tdep
));
3174 sp
-= align_up (len
, 16);
3177 fprintf_unfiltered (gdb_stdlog
,
3178 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
3179 paddr_nz (sp
), (long) align_up (len
, 16));
3181 /* Initialize the integer and float register pointers. */
3183 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3185 /* The struct_return pointer occupies the first parameter-passing reg. */
3189 fprintf_unfiltered (gdb_stdlog
,
3190 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
3191 argreg
, paddr_nz (struct_addr
));
3192 write_register (argreg
++, struct_addr
);
3195 /* Now load as many as possible of the first arguments into
3196 registers, and push the rest onto the stack. Loop thru args
3197 from first to last. */
3198 for (argnum
= 0; argnum
< nargs
; argnum
++)
3201 char valbuf
[MAX_REGISTER_SIZE
];
3202 struct value
*arg
= args
[argnum
];
3203 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3204 int len
= TYPE_LENGTH (arg_type
);
3205 enum type_code typecode
= TYPE_CODE (arg_type
);
3208 fprintf_unfiltered (gdb_stdlog
,
3209 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3210 argnum
+ 1, len
, (int) typecode
);
3212 /* The EABI passes structures that do not fit in a register by
3214 if (len
> mips_saved_regsize (tdep
)
3215 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3217 store_unsigned_integer (valbuf
, mips_saved_regsize (tdep
),
3218 VALUE_ADDRESS (arg
));
3219 typecode
= TYPE_CODE_PTR
;
3220 len
= mips_saved_regsize (tdep
);
3223 fprintf_unfiltered (gdb_stdlog
, " push");
3226 val
= (char *) VALUE_CONTENTS (arg
);
3228 /* 32-bit ABIs always start floating point arguments in an
3229 even-numbered floating point register. Round the FP register
3230 up before the check to see if there are any FP registers
3231 left. Non MIPS_EABI targets also pass the FP in the integer
3232 registers so also round up normal registers. */
3233 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
3235 if ((float_argreg
& 1))
3239 /* Floating point arguments passed in registers have to be
3240 treated specially. On 32-bit architectures, doubles
3241 are passed in register pairs; the even register gets
3242 the low word, and the odd register gets the high word.
3243 On non-EABI processors, the first two floating point arguments are
3244 also copied to general registers, because MIPS16 functions
3245 don't use float registers for arguments. This duplication of
3246 arguments in general registers can't hurt non-MIPS16 functions
3247 because those registers are normally skipped. */
3248 /* MIPS_EABI squeezes a struct that contains a single floating
3249 point value into an FP register instead of pushing it onto the
3251 if (fp_register_arg_p (typecode
, arg_type
)
3252 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3254 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3256 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3257 unsigned long regval
;
3259 /* Write the low word of the double to the even register(s). */
3260 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3262 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3263 float_argreg
, phex (regval
, 4));
3264 write_register (float_argreg
++, regval
);
3266 /* Write the high word of the double to the odd register(s). */
3267 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3269 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3270 float_argreg
, phex (regval
, 4));
3271 write_register (float_argreg
++, regval
);
3275 /* This is a floating point value that fits entirely
3276 in a single register. */
3277 /* On 32 bit ABI's the float_argreg is further adjusted
3278 above to ensure that it is even register aligned. */
3279 LONGEST regval
= extract_unsigned_integer (val
, len
);
3281 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3282 float_argreg
, phex (regval
, len
));
3283 write_register (float_argreg
++, regval
);
3288 /* Copy the argument to general registers or the stack in
3289 register-sized pieces. Large arguments are split between
3290 registers and stack. */
3291 /* Note: structs whose size is not a multiple of
3292 mips_regsize() are treated specially: Irix cc passes them
3293 in registers where gcc sometimes puts them on the stack.
3294 For maximum compatibility, we will put them in both
3296 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3297 && (len
% mips_saved_regsize (tdep
) != 0));
3299 /* Note: Floating-point values that didn't fit into an FP
3300 register are only written to memory. */
3303 /* Remember if the argument was written to the stack. */
3304 int stack_used_p
= 0;
3305 int partial_len
= (len
< mips_saved_regsize (tdep
)
3306 ? len
: mips_saved_regsize (tdep
));
3309 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3312 /* Write this portion of the argument to the stack. */
3313 if (argreg
> MIPS_LAST_ARG_REGNUM
3315 || fp_register_arg_p (typecode
, arg_type
))
3317 /* Should shorter than int integer values be
3318 promoted to int before being stored? */
3319 int longword_offset
= 0;
3322 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3324 if (mips_stack_argsize (tdep
) == 8
3325 && (typecode
== TYPE_CODE_INT
3326 || typecode
== TYPE_CODE_PTR
3327 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3328 longword_offset
= mips_stack_argsize (tdep
) - len
;
3329 else if ((typecode
== TYPE_CODE_STRUCT
3330 || typecode
== TYPE_CODE_UNION
)
3331 && (TYPE_LENGTH (arg_type
)
3332 < mips_stack_argsize (tdep
)))
3333 longword_offset
= mips_stack_argsize (tdep
) - len
;
3338 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3339 paddr_nz (stack_offset
));
3340 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3341 paddr_nz (longword_offset
));
3344 addr
= sp
+ stack_offset
+ longword_offset
;
3349 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3351 for (i
= 0; i
< partial_len
; i
++)
3353 fprintf_unfiltered (gdb_stdlog
, "%02x",
3357 write_memory (addr
, val
, partial_len
);
3360 /* Note!!! This is NOT an else clause. Odd sized
3361 structs may go thru BOTH paths. Floating point
3362 arguments will not. */
3363 /* Write this portion of the argument to a general
3364 purpose register. */
3365 if (argreg
<= MIPS_LAST_ARG_REGNUM
3366 && !fp_register_arg_p (typecode
, arg_type
))
3369 extract_unsigned_integer (val
, partial_len
);
3372 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3375 mips_saved_regsize (tdep
)));
3376 write_register (argreg
, regval
);
3383 /* Compute the the offset into the stack at which we
3384 will copy the next parameter.
3386 In the new EABI (and the NABI32), the stack_offset
3387 only needs to be adjusted when it has been used. */
3390 stack_offset
+= align_up (partial_len
,
3391 mips_stack_argsize (tdep
));
3395 fprintf_unfiltered (gdb_stdlog
, "\n");
3398 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3400 /* Return adjusted stack pointer. */
3404 /* Given a return value in `regbuf' with a type `valtype', extract and
3405 copy its value into `valbuf'. */
3408 mips_eabi_extract_return_value (struct type
*valtype
,
3409 char regbuf
[], char *valbuf
)
3411 struct return_value_word lo
;
3412 struct return_value_word hi
;
3413 return_value_location (valtype
, &hi
, &lo
);
3415 memcpy (valbuf
+ lo
.buf_offset
,
3416 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3417 lo
.reg_offset
, lo
.len
);
3420 memcpy (valbuf
+ hi
.buf_offset
,
3421 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3422 hi
.reg_offset
, hi
.len
);
3425 /* Given a return value in `valbuf' with a type `valtype', write it's
3426 value into the appropriate register. */
3429 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3431 char raw_buffer
[MAX_REGISTER_SIZE
];
3432 struct return_value_word lo
;
3433 struct return_value_word hi
;
3434 return_value_location (valtype
, &hi
, &lo
);
3436 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3437 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3438 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3439 raw_buffer
, register_size (current_gdbarch
,
3444 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3445 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3446 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3448 register_size (current_gdbarch
,
3453 /* N32/N64 ABI stuff. */
3456 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3457 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3458 int nargs
, struct value
**args
, CORE_ADDR sp
,
3459 int struct_return
, CORE_ADDR struct_addr
)
3465 int stack_offset
= 0;
3466 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3468 /* For shared libraries, "t9" needs to point at the function
3470 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3472 /* Set the return address register to point to the entry point of
3473 the program, where a breakpoint lies in wait. */
3474 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3476 /* First ensure that the stack and structure return address (if any)
3477 are properly aligned. The stack has to be at least 64-bit
3478 aligned even on 32-bit machines, because doubles must be 64-bit
3479 aligned. For n32 and n64, stack frames need to be 128-bit
3480 aligned, so we round to this widest known alignment. */
3482 sp
= align_down (sp
, 16);
3483 struct_addr
= align_down (struct_addr
, 16);
3485 /* Now make space on the stack for the args. */
3486 for (argnum
= 0; argnum
< nargs
; argnum
++)
3487 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3488 mips_stack_argsize (tdep
));
3489 sp
-= align_up (len
, 16);
3492 fprintf_unfiltered (gdb_stdlog
,
3493 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3494 paddr_nz (sp
), (long) align_up (len
, 16));
3496 /* Initialize the integer and float register pointers. */
3498 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3500 /* The struct_return pointer occupies the first parameter-passing reg. */
3504 fprintf_unfiltered (gdb_stdlog
,
3505 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3506 argreg
, paddr_nz (struct_addr
));
3507 write_register (argreg
++, struct_addr
);
3510 /* Now load as many as possible of the first arguments into
3511 registers, and push the rest onto the stack. Loop thru args
3512 from first to last. */
3513 for (argnum
= 0; argnum
< nargs
; argnum
++)
3516 char valbuf
[MAX_REGISTER_SIZE
];
3517 struct value
*arg
= args
[argnum
];
3518 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3519 int len
= TYPE_LENGTH (arg_type
);
3520 enum type_code typecode
= TYPE_CODE (arg_type
);
3523 fprintf_unfiltered (gdb_stdlog
,
3524 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3525 argnum
+ 1, len
, (int) typecode
);
3527 val
= (char *) VALUE_CONTENTS (arg
);
3529 if (fp_register_arg_p (typecode
, arg_type
)
3530 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3532 /* This is a floating point value that fits entirely
3533 in a single register. */
3534 /* On 32 bit ABI's the float_argreg is further adjusted
3535 above to ensure that it is even register aligned. */
3536 LONGEST regval
= extract_unsigned_integer (val
, len
);
3538 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3539 float_argreg
, phex (regval
, len
));
3540 write_register (float_argreg
++, regval
);
3543 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3544 argreg
, phex (regval
, len
));
3545 write_register (argreg
, regval
);
3550 /* Copy the argument to general registers or the stack in
3551 register-sized pieces. Large arguments are split between
3552 registers and stack. */
3553 /* Note: structs whose size is not a multiple of
3554 mips_regsize() are treated specially: Irix cc passes them
3555 in registers where gcc sometimes puts them on the stack.
3556 For maximum compatibility, we will put them in both
3558 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3559 && (len
% mips_saved_regsize (tdep
) != 0));
3560 /* Note: Floating-point values that didn't fit into an FP
3561 register are only written to memory. */
3564 /* Rememer if the argument was written to the stack. */
3565 int stack_used_p
= 0;
3566 int partial_len
= (len
< mips_saved_regsize (tdep
)
3567 ? len
: mips_saved_regsize (tdep
));
3570 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3573 /* Write this portion of the argument to the stack. */
3574 if (argreg
> MIPS_LAST_ARG_REGNUM
3576 || fp_register_arg_p (typecode
, arg_type
))
3578 /* Should shorter than int integer values be
3579 promoted to int before being stored? */
3580 int longword_offset
= 0;
3583 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3585 if (mips_stack_argsize (tdep
) == 8
3586 && (typecode
== TYPE_CODE_INT
3587 || typecode
== TYPE_CODE_PTR
3588 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3589 longword_offset
= mips_stack_argsize (tdep
) - len
;
3594 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3595 paddr_nz (stack_offset
));
3596 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3597 paddr_nz (longword_offset
));
3600 addr
= sp
+ stack_offset
+ longword_offset
;
3605 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3607 for (i
= 0; i
< partial_len
; i
++)
3609 fprintf_unfiltered (gdb_stdlog
, "%02x",
3613 write_memory (addr
, val
, partial_len
);
3616 /* Note!!! This is NOT an else clause. Odd sized
3617 structs may go thru BOTH paths. Floating point
3618 arguments will not. */
3619 /* Write this portion of the argument to a general
3620 purpose register. */
3621 if (argreg
<= MIPS_LAST_ARG_REGNUM
3622 && !fp_register_arg_p (typecode
, arg_type
))
3625 extract_unsigned_integer (val
, partial_len
);
3627 /* A non-floating-point argument being passed in a
3628 general register. If a struct or union, and if
3629 the remaining length is smaller than the register
3630 size, we have to adjust the register value on
3633 It does not seem to be necessary to do the
3634 same for integral types.
3636 cagney/2001-07-23: gdb/179: Also, GCC, when
3637 outputting LE O32 with sizeof (struct) <
3638 mips_saved_regsize(), generates a left shift as
3639 part of storing the argument in a register a
3640 register (the left shift isn't generated when
3641 sizeof (struct) >= mips_saved_regsize()). Since
3642 it is quite possible that this is GCC
3643 contradicting the LE/O32 ABI, GDB has not been
3644 adjusted to accommodate this. Either someone
3645 needs to demonstrate that the LE/O32 ABI
3646 specifies such a left shift OR this new ABI gets
3647 identified as such and GDB gets tweaked
3650 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3651 && partial_len
< mips_saved_regsize (tdep
)
3652 && (typecode
== TYPE_CODE_STRUCT
||
3653 typecode
== TYPE_CODE_UNION
))
3654 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
3658 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3661 mips_saved_regsize (tdep
)));
3662 write_register (argreg
, regval
);
3669 /* Compute the the offset into the stack at which we
3670 will copy the next parameter.
3672 In N32 (N64?), the stack_offset only needs to be
3673 adjusted when it has been used. */
3676 stack_offset
+= align_up (partial_len
,
3677 mips_stack_argsize (tdep
));
3681 fprintf_unfiltered (gdb_stdlog
, "\n");
3684 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3686 /* Return adjusted stack pointer. */
3690 static enum return_value_convention
3691 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3692 struct type
*type
, struct regcache
*regcache
,
3693 void *readbuf
, const void *writebuf
)
3695 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3696 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3697 || TYPE_CODE (type
) == TYPE_CODE_UNION
3698 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3699 || TYPE_LENGTH (type
) > 2 * mips_saved_regsize (tdep
))
3700 return RETURN_VALUE_STRUCT_CONVENTION
;
3701 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3702 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3704 /* A floating-point value belongs in the least significant part
3707 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3708 mips_xfer_register (regcache
,
3709 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3711 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3712 return RETURN_VALUE_REGISTER_CONVENTION
;
3714 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3715 && TYPE_NFIELDS (type
) <= 2
3716 && TYPE_NFIELDS (type
) >= 1
3717 && ((TYPE_NFIELDS (type
) == 1
3718 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3720 || (TYPE_NFIELDS (type
) == 2
3721 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3723 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3725 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3727 /* A struct that contains one or two floats. Each value is part
3728 in the least significant part of their floating point
3730 bfd_byte reg
[MAX_REGISTER_SIZE
];
3733 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3734 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3736 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3739 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3741 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3742 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3743 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3745 return RETURN_VALUE_REGISTER_CONVENTION
;
3747 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3748 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3750 /* A structure or union. Extract the left justified value,
3751 regardless of the byte order. I.e. DO NOT USE
3755 for (offset
= 0, regnum
= V0_REGNUM
;
3756 offset
< TYPE_LENGTH (type
);
3757 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3759 int xfer
= register_size (current_gdbarch
, regnum
);
3760 if (offset
+ xfer
> TYPE_LENGTH (type
))
3761 xfer
= TYPE_LENGTH (type
) - offset
;
3763 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3764 offset
, xfer
, regnum
);
3765 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3766 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3768 return RETURN_VALUE_REGISTER_CONVENTION
;
3772 /* A scalar extract each part but least-significant-byte
3776 for (offset
= 0, regnum
= V0_REGNUM
;
3777 offset
< TYPE_LENGTH (type
);
3778 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3780 int xfer
= register_size (current_gdbarch
, regnum
);
3782 if (offset
+ xfer
> TYPE_LENGTH (type
))
3783 xfer
= TYPE_LENGTH (type
) - offset
;
3785 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3786 offset
, xfer
, regnum
);
3787 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3788 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3790 return RETURN_VALUE_REGISTER_CONVENTION
;
3794 /* O32 ABI stuff. */
3797 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3798 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3799 int nargs
, struct value
**args
, CORE_ADDR sp
,
3800 int struct_return
, CORE_ADDR struct_addr
)
3806 int stack_offset
= 0;
3807 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3809 /* For shared libraries, "t9" needs to point at the function
3811 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3813 /* Set the return address register to point to the entry point of
3814 the program, where a breakpoint lies in wait. */
3815 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3817 /* First ensure that the stack and structure return address (if any)
3818 are properly aligned. The stack has to be at least 64-bit
3819 aligned even on 32-bit machines, because doubles must be 64-bit
3820 aligned. For n32 and n64, stack frames need to be 128-bit
3821 aligned, so we round to this widest known alignment. */
3823 sp
= align_down (sp
, 16);
3824 struct_addr
= align_down (struct_addr
, 16);
3826 /* Now make space on the stack for the args. */
3827 for (argnum
= 0; argnum
< nargs
; argnum
++)
3828 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3829 mips_stack_argsize (tdep
));
3830 sp
-= align_up (len
, 16);
3833 fprintf_unfiltered (gdb_stdlog
,
3834 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3835 paddr_nz (sp
), (long) align_up (len
, 16));
3837 /* Initialize the integer and float register pointers. */
3839 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3841 /* The struct_return pointer occupies the first parameter-passing reg. */
3845 fprintf_unfiltered (gdb_stdlog
,
3846 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3847 argreg
, paddr_nz (struct_addr
));
3848 write_register (argreg
++, struct_addr
);
3849 stack_offset
+= mips_stack_argsize (tdep
);
3852 /* Now load as many as possible of the first arguments into
3853 registers, and push the rest onto the stack. Loop thru args
3854 from first to last. */
3855 for (argnum
= 0; argnum
< nargs
; argnum
++)
3858 char valbuf
[MAX_REGISTER_SIZE
];
3859 struct value
*arg
= args
[argnum
];
3860 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3861 int len
= TYPE_LENGTH (arg_type
);
3862 enum type_code typecode
= TYPE_CODE (arg_type
);
3865 fprintf_unfiltered (gdb_stdlog
,
3866 "mips_o32_push_dummy_call: %d len=%d type=%d",
3867 argnum
+ 1, len
, (int) typecode
);
3869 val
= (char *) VALUE_CONTENTS (arg
);
3871 /* 32-bit ABIs always start floating point arguments in an
3872 even-numbered floating point register. Round the FP register
3873 up before the check to see if there are any FP registers
3874 left. O32/O64 targets also pass the FP in the integer
3875 registers so also round up normal registers. */
3876 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
3878 if ((float_argreg
& 1))
3882 /* Floating point arguments passed in registers have to be
3883 treated specially. On 32-bit architectures, doubles
3884 are passed in register pairs; the even register gets
3885 the low word, and the odd register gets the high word.
3886 On O32/O64, the first two floating point arguments are
3887 also copied to general registers, because MIPS16 functions
3888 don't use float registers for arguments. This duplication of
3889 arguments in general registers can't hurt non-MIPS16 functions
3890 because those registers are normally skipped. */
3892 if (fp_register_arg_p (typecode
, arg_type
)
3893 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3895 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3897 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3898 unsigned long regval
;
3900 /* Write the low word of the double to the even register(s). */
3901 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3903 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3904 float_argreg
, phex (regval
, 4));
3905 write_register (float_argreg
++, regval
);
3907 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3908 argreg
, phex (regval
, 4));
3909 write_register (argreg
++, regval
);
3911 /* Write the high word of the double to the odd register(s). */
3912 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3914 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3915 float_argreg
, phex (regval
, 4));
3916 write_register (float_argreg
++, regval
);
3919 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3920 argreg
, phex (regval
, 4));
3921 write_register (argreg
++, regval
);
3925 /* This is a floating point value that fits entirely
3926 in a single register. */
3927 /* On 32 bit ABI's the float_argreg is further adjusted
3928 above to ensure that it is even register aligned. */
3929 LONGEST regval
= extract_unsigned_integer (val
, len
);
3931 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3932 float_argreg
, phex (regval
, len
));
3933 write_register (float_argreg
++, regval
);
3934 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3935 registers for each argument. The below is (my
3936 guess) to ensure that the corresponding integer
3937 register has reserved the same space. */
3939 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3940 argreg
, phex (regval
, len
));
3941 write_register (argreg
, regval
);
3942 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3944 /* Reserve space for the FP register. */
3945 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
3949 /* Copy the argument to general registers or the stack in
3950 register-sized pieces. Large arguments are split between
3951 registers and stack. */
3952 /* Note: structs whose size is not a multiple of
3953 mips_regsize() are treated specially: Irix cc passes them
3954 in registers where gcc sometimes puts them on the stack.
3955 For maximum compatibility, we will put them in both
3957 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
3958 && (len
% mips_saved_regsize (tdep
) != 0));
3959 /* Structures should be aligned to eight bytes (even arg registers)
3960 on MIPS_ABI_O32, if their first member has double precision. */
3961 if (mips_saved_regsize (tdep
) < 8
3962 && mips_type_needs_double_align (arg_type
))
3967 /* Note: Floating-point values that didn't fit into an FP
3968 register are only written to memory. */
3971 /* Remember if the argument was written to the stack. */
3972 int stack_used_p
= 0;
3973 int partial_len
= (len
< mips_saved_regsize (tdep
)
3974 ? len
: mips_saved_regsize (tdep
));
3977 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3980 /* Write this portion of the argument to the stack. */
3981 if (argreg
> MIPS_LAST_ARG_REGNUM
3983 || fp_register_arg_p (typecode
, arg_type
))
3985 /* Should shorter than int integer values be
3986 promoted to int before being stored? */
3987 int longword_offset
= 0;
3990 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3992 if (mips_stack_argsize (tdep
) == 8
3993 && (typecode
== TYPE_CODE_INT
3994 || typecode
== TYPE_CODE_PTR
3995 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3996 longword_offset
= mips_stack_argsize (tdep
) - len
;
4001 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4002 paddr_nz (stack_offset
));
4003 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4004 paddr_nz (longword_offset
));
4007 addr
= sp
+ stack_offset
+ longword_offset
;
4012 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4014 for (i
= 0; i
< partial_len
; i
++)
4016 fprintf_unfiltered (gdb_stdlog
, "%02x",
4020 write_memory (addr
, val
, partial_len
);
4023 /* Note!!! This is NOT an else clause. Odd sized
4024 structs may go thru BOTH paths. Floating point
4025 arguments will not. */
4026 /* Write this portion of the argument to a general
4027 purpose register. */
4028 if (argreg
<= MIPS_LAST_ARG_REGNUM
4029 && !fp_register_arg_p (typecode
, arg_type
))
4031 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4032 /* Value may need to be sign extended, because
4033 mips_regsize() != mips_saved_regsize(). */
4035 /* A non-floating-point argument being passed in a
4036 general register. If a struct or union, and if
4037 the remaining length is smaller than the register
4038 size, we have to adjust the register value on
4041 It does not seem to be necessary to do the
4042 same for integral types.
4044 Also don't do this adjustment on O64 binaries.
4046 cagney/2001-07-23: gdb/179: Also, GCC, when
4047 outputting LE O32 with sizeof (struct) <
4048 mips_saved_regsize(), generates a left shift as
4049 part of storing the argument in a register a
4050 register (the left shift isn't generated when
4051 sizeof (struct) >= mips_saved_regsize()). Since
4052 it is quite possible that this is GCC
4053 contradicting the LE/O32 ABI, GDB has not been
4054 adjusted to accommodate this. Either someone
4055 needs to demonstrate that the LE/O32 ABI
4056 specifies such a left shift OR this new ABI gets
4057 identified as such and GDB gets tweaked
4060 if (mips_saved_regsize (tdep
) < 8
4061 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4062 && partial_len
< mips_saved_regsize (tdep
)
4063 && (typecode
== TYPE_CODE_STRUCT
||
4064 typecode
== TYPE_CODE_UNION
))
4065 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
4069 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4072 mips_saved_regsize (tdep
)));
4073 write_register (argreg
, regval
);
4076 /* Prevent subsequent floating point arguments from
4077 being passed in floating point registers. */
4078 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4084 /* Compute the the offset into the stack at which we
4085 will copy the next parameter.
4087 In older ABIs, the caller reserved space for
4088 registers that contained arguments. This was loosely
4089 refered to as their "home". Consequently, space is
4090 always allocated. */
4092 stack_offset
+= align_up (partial_len
,
4093 mips_stack_argsize (tdep
));
4097 fprintf_unfiltered (gdb_stdlog
, "\n");
4100 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
4102 /* Return adjusted stack pointer. */
4106 static enum return_value_convention
4107 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4108 struct regcache
*regcache
,
4109 void *readbuf
, const void *writebuf
)
4111 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4113 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4114 || TYPE_CODE (type
) == TYPE_CODE_UNION
4115 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4116 return RETURN_VALUE_STRUCT_CONVENTION
;
4117 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4118 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4120 /* A single-precision floating-point value. It fits in the
4121 least significant part of FP0. */
4123 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4124 mips_xfer_register (regcache
,
4125 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4127 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4128 return RETURN_VALUE_REGISTER_CONVENTION
;
4130 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4131 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4133 /* A double-precision floating-point value. The most
4134 significant part goes in FP1, and the least significant in
4137 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4138 switch (TARGET_BYTE_ORDER
)
4140 case BFD_ENDIAN_LITTLE
:
4141 mips_xfer_register (regcache
,
4142 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4143 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4144 mips_xfer_register (regcache
,
4145 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4146 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4148 case BFD_ENDIAN_BIG
:
4149 mips_xfer_register (regcache
,
4150 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4151 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4152 mips_xfer_register (regcache
,
4153 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4154 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4157 internal_error (__FILE__
, __LINE__
, "bad switch");
4159 return RETURN_VALUE_REGISTER_CONVENTION
;
4162 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4163 && TYPE_NFIELDS (type
) <= 2
4164 && TYPE_NFIELDS (type
) >= 1
4165 && ((TYPE_NFIELDS (type
) == 1
4166 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4168 || (TYPE_NFIELDS (type
) == 2
4169 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4171 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4173 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4175 /* A struct that contains one or two floats. Each value is part
4176 in the least significant part of their floating point
4178 bfd_byte reg
[MAX_REGISTER_SIZE
];
4181 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4182 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4184 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4187 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4189 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4190 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4191 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4193 return RETURN_VALUE_REGISTER_CONVENTION
;
4197 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4198 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4200 /* A structure or union. Extract the left justified value,
4201 regardless of the byte order. I.e. DO NOT USE
4205 for (offset
= 0, regnum
= V0_REGNUM
;
4206 offset
< TYPE_LENGTH (type
);
4207 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4209 int xfer
= register_size (current_gdbarch
, regnum
);
4210 if (offset
+ xfer
> TYPE_LENGTH (type
))
4211 xfer
= TYPE_LENGTH (type
) - offset
;
4213 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4214 offset
, xfer
, regnum
);
4215 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4216 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4218 return RETURN_VALUE_REGISTER_CONVENTION
;
4223 /* A scalar extract each part but least-significant-byte
4224 justified. o32 thinks registers are 4 byte, regardless of
4225 the ISA. mips_stack_argsize controls this. */
4228 for (offset
= 0, regnum
= V0_REGNUM
;
4229 offset
< TYPE_LENGTH (type
);
4230 offset
+= mips_stack_argsize (tdep
), regnum
++)
4232 int xfer
= mips_stack_argsize (tdep
);
4234 if (offset
+ xfer
> TYPE_LENGTH (type
))
4235 xfer
= TYPE_LENGTH (type
) - offset
;
4237 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4238 offset
, xfer
, regnum
);
4239 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4240 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4242 return RETURN_VALUE_REGISTER_CONVENTION
;
4246 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4250 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
4251 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4253 struct value
**args
, CORE_ADDR sp
,
4254 int struct_return
, CORE_ADDR struct_addr
)
4260 int stack_offset
= 0;
4261 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4263 /* For shared libraries, "t9" needs to point at the function
4265 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4267 /* Set the return address register to point to the entry point of
4268 the program, where a breakpoint lies in wait. */
4269 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4271 /* First ensure that the stack and structure return address (if any)
4272 are properly aligned. The stack has to be at least 64-bit
4273 aligned even on 32-bit machines, because doubles must be 64-bit
4274 aligned. For n32 and n64, stack frames need to be 128-bit
4275 aligned, so we round to this widest known alignment. */
4277 sp
= align_down (sp
, 16);
4278 struct_addr
= align_down (struct_addr
, 16);
4280 /* Now make space on the stack for the args. */
4281 for (argnum
= 0; argnum
< nargs
; argnum
++)
4282 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4283 mips_stack_argsize (tdep
));
4284 sp
-= align_up (len
, 16);
4287 fprintf_unfiltered (gdb_stdlog
,
4288 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4289 paddr_nz (sp
), (long) align_up (len
, 16));
4291 /* Initialize the integer and float register pointers. */
4293 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4295 /* The struct_return pointer occupies the first parameter-passing reg. */
4299 fprintf_unfiltered (gdb_stdlog
,
4300 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4301 argreg
, paddr_nz (struct_addr
));
4302 write_register (argreg
++, struct_addr
);
4303 stack_offset
+= mips_stack_argsize (tdep
);
4306 /* Now load as many as possible of the first arguments into
4307 registers, and push the rest onto the stack. Loop thru args
4308 from first to last. */
4309 for (argnum
= 0; argnum
< nargs
; argnum
++)
4312 char valbuf
[MAX_REGISTER_SIZE
];
4313 struct value
*arg
= args
[argnum
];
4314 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4315 int len
= TYPE_LENGTH (arg_type
);
4316 enum type_code typecode
= TYPE_CODE (arg_type
);
4319 fprintf_unfiltered (gdb_stdlog
,
4320 "mips_o64_push_dummy_call: %d len=%d type=%d",
4321 argnum
+ 1, len
, (int) typecode
);
4323 val
= (char *) VALUE_CONTENTS (arg
);
4325 /* 32-bit ABIs always start floating point arguments in an
4326 even-numbered floating point register. Round the FP register
4327 up before the check to see if there are any FP registers
4328 left. O32/O64 targets also pass the FP in the integer
4329 registers so also round up normal registers. */
4330 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
4332 if ((float_argreg
& 1))
4336 /* Floating point arguments passed in registers have to be
4337 treated specially. On 32-bit architectures, doubles
4338 are passed in register pairs; the even register gets
4339 the low word, and the odd register gets the high word.
4340 On O32/O64, the first two floating point arguments are
4341 also copied to general registers, because MIPS16 functions
4342 don't use float registers for arguments. This duplication of
4343 arguments in general registers can't hurt non-MIPS16 functions
4344 because those registers are normally skipped. */
4346 if (fp_register_arg_p (typecode
, arg_type
)
4347 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4349 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4351 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4352 unsigned long regval
;
4354 /* Write the low word of the double to the even register(s). */
4355 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4357 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4358 float_argreg
, phex (regval
, 4));
4359 write_register (float_argreg
++, regval
);
4361 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4362 argreg
, phex (regval
, 4));
4363 write_register (argreg
++, regval
);
4365 /* Write the high word of the double to the odd register(s). */
4366 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4368 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4369 float_argreg
, phex (regval
, 4));
4370 write_register (float_argreg
++, regval
);
4373 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4374 argreg
, phex (regval
, 4));
4375 write_register (argreg
++, regval
);
4379 /* This is a floating point value that fits entirely
4380 in a single register. */
4381 /* On 32 bit ABI's the float_argreg is further adjusted
4382 above to ensure that it is even register aligned. */
4383 LONGEST regval
= extract_unsigned_integer (val
, len
);
4385 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4386 float_argreg
, phex (regval
, len
));
4387 write_register (float_argreg
++, regval
);
4388 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4389 registers for each argument. The below is (my
4390 guess) to ensure that the corresponding integer
4391 register has reserved the same space. */
4393 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4394 argreg
, phex (regval
, len
));
4395 write_register (argreg
, regval
);
4396 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
4398 /* Reserve space for the FP register. */
4399 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
4403 /* Copy the argument to general registers or the stack in
4404 register-sized pieces. Large arguments are split between
4405 registers and stack. */
4406 /* Note: structs whose size is not a multiple of
4407 mips_regsize() are treated specially: Irix cc passes them
4408 in registers where gcc sometimes puts them on the stack.
4409 For maximum compatibility, we will put them in both
4411 int odd_sized_struct
= ((len
> mips_saved_regsize (tdep
))
4412 && (len
% mips_saved_regsize (tdep
) != 0));
4413 /* Structures should be aligned to eight bytes (even arg registers)
4414 on MIPS_ABI_O32, if their first member has double precision. */
4415 if (mips_saved_regsize (tdep
) < 8
4416 && mips_type_needs_double_align (arg_type
))
4421 /* Note: Floating-point values that didn't fit into an FP
4422 register are only written to memory. */
4425 /* Remember if the argument was written to the stack. */
4426 int stack_used_p
= 0;
4427 int partial_len
= (len
< mips_saved_regsize (tdep
)
4428 ? len
: mips_saved_regsize (tdep
));
4431 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4434 /* Write this portion of the argument to the stack. */
4435 if (argreg
> MIPS_LAST_ARG_REGNUM
4437 || fp_register_arg_p (typecode
, arg_type
))
4439 /* Should shorter than int integer values be
4440 promoted to int before being stored? */
4441 int longword_offset
= 0;
4444 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4446 if (mips_stack_argsize (tdep
) == 8
4447 && (typecode
== TYPE_CODE_INT
4448 || typecode
== TYPE_CODE_PTR
4449 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4450 longword_offset
= mips_stack_argsize (tdep
) - len
;
4455 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4456 paddr_nz (stack_offset
));
4457 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4458 paddr_nz (longword_offset
));
4461 addr
= sp
+ stack_offset
+ longword_offset
;
4466 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4468 for (i
= 0; i
< partial_len
; i
++)
4470 fprintf_unfiltered (gdb_stdlog
, "%02x",
4474 write_memory (addr
, val
, partial_len
);
4477 /* Note!!! This is NOT an else clause. Odd sized
4478 structs may go thru BOTH paths. Floating point
4479 arguments will not. */
4480 /* Write this portion of the argument to a general
4481 purpose register. */
4482 if (argreg
<= MIPS_LAST_ARG_REGNUM
4483 && !fp_register_arg_p (typecode
, arg_type
))
4485 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4486 /* Value may need to be sign extended, because
4487 mips_regsize() != mips_saved_regsize(). */
4489 /* A non-floating-point argument being passed in a
4490 general register. If a struct or union, and if
4491 the remaining length is smaller than the register
4492 size, we have to adjust the register value on
4495 It does not seem to be necessary to do the
4496 same for integral types.
4498 Also don't do this adjustment on O64 binaries.
4500 cagney/2001-07-23: gdb/179: Also, GCC, when
4501 outputting LE O32 with sizeof (struct) <
4502 mips_saved_regsize(), generates a left shift as
4503 part of storing the argument in a register a
4504 register (the left shift isn't generated when
4505 sizeof (struct) >= mips_saved_regsize()). Since
4506 it is quite possible that this is GCC
4507 contradicting the LE/O32 ABI, GDB has not been
4508 adjusted to accommodate this. Either someone
4509 needs to demonstrate that the LE/O32 ABI
4510 specifies such a left shift OR this new ABI gets
4511 identified as such and GDB gets tweaked
4514 if (mips_saved_regsize (tdep
) < 8
4515 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4516 && partial_len
< mips_saved_regsize (tdep
)
4517 && (typecode
== TYPE_CODE_STRUCT
||
4518 typecode
== TYPE_CODE_UNION
))
4519 regval
<<= ((mips_saved_regsize (tdep
) - partial_len
) *
4523 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4526 mips_saved_regsize (tdep
)));
4527 write_register (argreg
, regval
);
4530 /* Prevent subsequent floating point arguments from
4531 being passed in floating point registers. */
4532 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4538 /* Compute the the offset into the stack at which we
4539 will copy the next parameter.
4541 In older ABIs, the caller reserved space for
4542 registers that contained arguments. This was loosely
4543 refered to as their "home". Consequently, space is
4544 always allocated. */
4546 stack_offset
+= align_up (partial_len
,
4547 mips_stack_argsize (tdep
));
4551 fprintf_unfiltered (gdb_stdlog
, "\n");
4554 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
4556 /* Return adjusted stack pointer. */
4561 mips_o64_extract_return_value (struct type
*valtype
,
4562 char regbuf
[], char *valbuf
)
4564 struct return_value_word lo
;
4565 struct return_value_word hi
;
4566 return_value_location (valtype
, &hi
, &lo
);
4568 memcpy (valbuf
+ lo
.buf_offset
,
4569 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4570 lo
.reg_offset
, lo
.len
);
4573 memcpy (valbuf
+ hi
.buf_offset
,
4574 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4575 hi
.reg_offset
, hi
.len
);
4579 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4581 char raw_buffer
[MAX_REGISTER_SIZE
];
4582 struct return_value_word lo
;
4583 struct return_value_word hi
;
4584 return_value_location (valtype
, &hi
, &lo
);
4586 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4587 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4588 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4589 raw_buffer
, register_size (current_gdbarch
,
4594 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4595 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4596 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4598 register_size (current_gdbarch
,
4604 mips_pop_frame (void)
4607 struct frame_info
*frame
= get_current_frame ();
4608 CORE_ADDR new_sp
= get_frame_base (frame
);
4609 mips_extra_func_info_t proc_desc
;
4610 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4612 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
), 0, 0))
4614 generic_pop_dummy_frame ();
4615 flush_cached_frames ();
4619 proc_desc
= get_frame_extra_info (frame
)->proc_desc
;
4620 write_register (mips_regnum (current_gdbarch
)->pc
,
4621 DEPRECATED_FRAME_SAVED_PC (frame
));
4622 mips_find_saved_regs (frame
);
4623 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
4624 if (regnum
!= SP_REGNUM
&& regnum
!= mips_regnum (current_gdbarch
)->pc
4625 && deprecated_get_frame_saved_regs (frame
)[regnum
])
4627 /* Floating point registers must not be sign extended, in case
4628 mips_saved_regsize() = 4 but sizeof (FP0_REGNUM) == 8. */
4630 if (mips_regnum (current_gdbarch
)->fp0
<= regnum
4631 && regnum
< mips_regnum (current_gdbarch
)->fp0
+ 32)
4632 write_register (regnum
,
4633 read_memory_unsigned_integer
4634 (deprecated_get_frame_saved_regs (frame
)[regnum
],
4635 mips_saved_regsize (tdep
)));
4637 write_register (regnum
,
4638 read_memory_integer (deprecated_get_frame_saved_regs
4640 mips_saved_regsize (tdep
)));
4643 write_register (SP_REGNUM
, new_sp
);
4644 flush_cached_frames ();
4646 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
4648 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
4650 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
4651 pi_ptr
!= NULL
; prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
4653 if (&pi_ptr
->info
== proc_desc
)
4658 error ("Can't locate dummy extra frame info\n");
4660 if (prev_ptr
!= NULL
)
4661 prev_ptr
->next
= pi_ptr
->next
;
4663 linked_proc_desc_table
= pi_ptr
->next
;
4667 write_register (mips_regnum (current_gdbarch
)->hi
,
4668 read_memory_integer ((new_sp
4669 - 2 * mips_saved_regsize (tdep
)),
4670 mips_saved_regsize (tdep
)));
4671 write_register (mips_regnum (current_gdbarch
)->lo
,
4672 read_memory_integer ((new_sp
4673 - 3 * mips_saved_regsize (tdep
)),
4674 mips_saved_regsize (tdep
)));
4675 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
4676 write_register (mips_regnum (current_gdbarch
)->fp_control_status
,
4677 read_memory_integer ((new_sp
4679 4 * mips_saved_regsize (tdep
)),
4680 mips_saved_regsize (tdep
)));
4684 /* Floating point register management.
4686 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4687 64bit operations, these early MIPS cpus treat fp register pairs
4688 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4689 registers and offer a compatibility mode that emulates the MIPS2 fp
4690 model. When operating in MIPS2 fp compat mode, later cpu's split
4691 double precision floats into two 32-bit chunks and store them in
4692 consecutive fp regs. To display 64-bit floats stored in this
4693 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4694 Throw in user-configurable endianness and you have a real mess.
4696 The way this works is:
4697 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4698 double-precision value will be split across two logical registers.
4699 The lower-numbered logical register will hold the low-order bits,
4700 regardless of the processor's endianness.
4701 - If we are on a 64-bit processor, and we are looking for a
4702 single-precision value, it will be in the low ordered bits
4703 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4704 save slot in memory.
4705 - If we are in 64-bit mode, everything is straightforward.
4707 Note that this code only deals with "live" registers at the top of the
4708 stack. We will attempt to deal with saved registers later, when
4709 the raw/cooked register interface is in place. (We need a general
4710 interface that can deal with dynamic saved register sizes -- fp
4711 regs could be 32 bits wide in one frame and 64 on the frame above
4714 static struct type
*
4715 mips_float_register_type (void)
4717 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4718 return builtin_type_ieee_single_big
;
4720 return builtin_type_ieee_single_little
;
4723 static struct type
*
4724 mips_double_register_type (void)
4726 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4727 return builtin_type_ieee_double_big
;
4729 return builtin_type_ieee_double_little
;
4732 /* Copy a 32-bit single-precision value from the current frame
4733 into rare_buffer. */
4736 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4739 int raw_size
= register_size (current_gdbarch
, regno
);
4740 char *raw_buffer
= alloca (raw_size
);
4742 if (!frame_register_read (frame
, regno
, raw_buffer
))
4743 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4746 /* We have a 64-bit value for this register. Find the low-order
4750 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4755 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4759 memcpy (rare_buffer
, raw_buffer
, 4);
4763 /* Copy a 64-bit double-precision value from the current frame into
4764 rare_buffer. This may include getting half of it from the next
4768 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4771 int raw_size
= register_size (current_gdbarch
, regno
);
4773 if (raw_size
== 8 && !mips2_fp_compat ())
4775 /* We have a 64-bit value for this register, and we should use
4777 if (!frame_register_read (frame
, regno
, rare_buffer
))
4778 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4782 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4783 internal_error (__FILE__
, __LINE__
,
4784 "mips_read_fp_register_double: bad access to "
4785 "odd-numbered FP register");
4787 /* mips_read_fp_register_single will find the correct 32 bits from
4789 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4791 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4792 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4796 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4797 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4803 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4805 { /* do values for FP (float) regs */
4807 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
4808 int inv1
, inv2
, namelen
;
4811 (char *) alloca (2 *
4812 register_size (current_gdbarch
,
4813 mips_regnum (current_gdbarch
)->fp0
));
4815 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4816 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4819 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4821 /* 4-byte registers: Print hex and floating. Also print even
4822 numbered registers as doubles. */
4823 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4824 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4826 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4829 fprintf_filtered (file
, " flt: ");
4831 fprintf_filtered (file
, " <invalid float> ");
4833 fprintf_filtered (file
, "%-17.9g", flt1
);
4835 if (regnum
% 2 == 0)
4837 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4838 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4841 fprintf_filtered (file
, " dbl: ");
4843 fprintf_filtered (file
, "<invalid double>");
4845 fprintf_filtered (file
, "%-24.17g", doub
);
4850 /* Eight byte registers: print each one as hex, float and double. */
4851 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4852 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4854 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4855 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4858 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4861 fprintf_filtered (file
, " flt: ");
4863 fprintf_filtered (file
, "<invalid float>");
4865 fprintf_filtered (file
, "%-17.9g", flt1
);
4867 fprintf_filtered (file
, " dbl: ");
4869 fprintf_filtered (file
, "<invalid double>");
4871 fprintf_filtered (file
, "%-24.17g", doub
);
4876 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4877 int regnum
, int all
)
4879 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4880 char raw_buffer
[MAX_REGISTER_SIZE
];
4883 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4885 mips_print_fp_register (file
, frame
, regnum
);
4889 /* Get the data in raw format. */
4890 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4892 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4896 fputs_filtered (REGISTER_NAME (regnum
), file
);
4898 /* The problem with printing numeric register names (r26, etc.) is that
4899 the user can't use them on input. Probably the best solution is to
4900 fix it so that either the numeric or the funky (a2, etc.) names
4901 are accepted on input. */
4902 if (regnum
< MIPS_NUMREGS
)
4903 fprintf_filtered (file
, "(r%d): ", regnum
);
4905 fprintf_filtered (file
, ": ");
4907 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4909 register_size (current_gdbarch
,
4910 regnum
) - register_size (current_gdbarch
, regnum
);
4914 print_scalar_formatted (raw_buffer
+ offset
,
4915 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4919 /* Replacement for generic do_registers_info.
4920 Print regs in pretty columns. */
4923 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4926 fprintf_filtered (file
, " ");
4927 mips_print_fp_register (file
, frame
, regnum
);
4928 fprintf_filtered (file
, "\n");
4933 /* Print a row's worth of GP (int) registers, with name labels above */
4936 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4939 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4940 /* do values for GP (int) regs */
4941 char raw_buffer
[MAX_REGISTER_SIZE
];
4942 int ncols
= (mips_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4946 /* For GP registers, we print a separate row of names above the vals */
4947 fprintf_filtered (file
, " ");
4948 for (col
= 0, regnum
= start_regnum
;
4949 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4951 if (*REGISTER_NAME (regnum
) == '\0')
4952 continue; /* unused register */
4953 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4955 break; /* end the row: reached FP register */
4956 fprintf_filtered (file
,
4957 mips_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4958 REGISTER_NAME (regnum
));
4961 /* print the R0 to R31 names */
4962 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4963 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4965 fprintf_filtered (file
, "\n ");
4967 /* now print the values in hex, 4 or 8 to the row */
4968 for (col
= 0, regnum
= start_regnum
;
4969 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4971 if (*REGISTER_NAME (regnum
) == '\0')
4972 continue; /* unused register */
4973 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4975 break; /* end row: reached FP register */
4976 /* OK: get the data in raw format. */
4977 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4978 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4979 /* pad small registers */
4981 byte
< (mips_regsize (current_gdbarch
)
4982 - register_size (current_gdbarch
, regnum
)); byte
++)
4983 printf_filtered (" ");
4984 /* Now print the register value in hex, endian order. */
4985 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4987 register_size (current_gdbarch
,
4988 regnum
) - register_size (current_gdbarch
, regnum
);
4989 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4990 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4992 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4994 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4995 fprintf_filtered (file
, " ");
4998 if (col
> 0) /* ie. if we actually printed anything... */
4999 fprintf_filtered (file
, "\n");
5004 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
5007 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
5008 struct frame_info
*frame
, int regnum
, int all
)
5010 if (regnum
!= -1) /* do one specified register */
5012 gdb_assert (regnum
>= NUM_REGS
);
5013 if (*(REGISTER_NAME (regnum
)) == '\0')
5014 error ("Not a valid register for the current processor type");
5016 mips_print_register (file
, frame
, regnum
, 0);
5017 fprintf_filtered (file
, "\n");
5020 /* do all (or most) registers */
5023 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
5025 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5028 if (all
) /* true for "INFO ALL-REGISTERS" command */
5029 regnum
= print_fp_register_row (file
, frame
, regnum
);
5031 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
5034 regnum
= print_gp_register_row (file
, frame
, regnum
);
5039 /* Is this a branch with a delay slot? */
5041 static int is_delayed (unsigned long);
5044 is_delayed (unsigned long insn
)
5047 for (i
= 0; i
< NUMOPCODES
; ++i
)
5048 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
5049 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
5051 return (i
< NUMOPCODES
5052 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
5053 | INSN_COND_BRANCH_DELAY
5054 | INSN_COND_BRANCH_LIKELY
)));
5058 mips_step_skips_delay (CORE_ADDR pc
)
5060 char buf
[MIPS_INSTLEN
];
5062 /* There is no branch delay slot on MIPS16. */
5063 if (pc_is_mips16 (pc
))
5066 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
5067 /* If error reading memory, guess that it is not a delayed branch. */
5069 return is_delayed ((unsigned long)
5070 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
5074 /* Given PC at the function's start address, attempt to find the
5075 prologue end using SAL information. Return zero if the skip fails.
5077 A non-optimized prologue traditionally has one SAL for the function
5078 and a second for the function body. A single line function has
5079 them both pointing at the same line.
5081 An optimized prologue is similar but the prologue may contain
5082 instructions (SALs) from the instruction body. Need to skip those
5083 while not getting into the function body.
5085 The functions end point and an increasing SAL line are used as
5086 indicators of the prologue's endpoint.
5088 This code is based on the function refine_prologue_limit (versions
5089 found in both ia64 and ppc). */
5092 skip_prologue_using_sal (CORE_ADDR func_addr
)
5094 struct symtab_and_line prologue_sal
;
5098 /* Get an initial range for the function. */
5099 find_pc_partial_function (func_addr
, NULL
, &start_pc
, &end_pc
);
5100 start_pc
+= FUNCTION_START_OFFSET
;
5102 prologue_sal
= find_pc_line (start_pc
, 0);
5103 if (prologue_sal
.line
!= 0)
5105 while (prologue_sal
.end
< end_pc
)
5107 struct symtab_and_line sal
;
5109 sal
= find_pc_line (prologue_sal
.end
, 0);
5112 /* Assume that a consecutive SAL for the same (or larger)
5113 line mark the prologue -> body transition. */
5114 if (sal
.line
>= prologue_sal
.line
)
5116 /* The case in which compiler's optimizer/scheduler has
5117 moved instructions into the prologue. We look ahead in
5118 the function looking for address ranges whose
5119 corresponding line number is less the first one that we
5120 found for the function. This is more conservative then
5121 refine_prologue_limit which scans a large number of SALs
5122 looking for any in the prologue */
5126 return prologue_sal
.end
;
5129 /* Skip the PC past function prologue instructions (32-bit version).
5130 This is a helper function for mips_skip_prologue. */
5133 mips32_skip_prologue (CORE_ADDR pc
)
5137 int seen_sp_adjust
= 0;
5138 int load_immediate_bytes
= 0;
5140 /* Find an upper bound on the prologue. */
5141 end_pc
= skip_prologue_using_sal (pc
);
5143 end_pc
= pc
+ 100; /* Magic. */
5145 /* Skip the typical prologue instructions. These are the stack adjustment
5146 instruction and the instructions that save registers on the stack
5147 or in the gcc frame. */
5148 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
5150 unsigned long high_word
;
5152 inst
= mips_fetch_instruction (pc
);
5153 high_word
= (inst
>> 16) & 0xffff;
5155 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
5156 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
5158 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
5159 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
5161 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
5162 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
5163 && (inst
& 0x001F0000)) /* reg != $zero */
5166 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
5168 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
5170 continue; /* reg != $zero */
5172 /* move $s8,$sp. With different versions of gas this will be either
5173 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
5174 Accept any one of these. */
5175 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
5178 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
5180 else if (high_word
== 0x3c1c) /* lui $gp,n */
5182 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
5184 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
5185 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
5187 /* The following instructions load $at or $t0 with an immediate
5188 value in preparation for a stack adjustment via
5189 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
5190 a local variable, so we accept them only before a stack adjustment
5191 instruction was seen. */
5192 else if (!seen_sp_adjust
)
5194 if (high_word
== 0x3c01 || /* lui $at,n */
5195 high_word
== 0x3c08) /* lui $t0,n */
5197 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5200 else if (high_word
== 0x3421 || /* ori $at,$at,n */
5201 high_word
== 0x3508 || /* ori $t0,$t0,n */
5202 high_word
== 0x3401 || /* ori $at,$zero,n */
5203 high_word
== 0x3408) /* ori $t0,$zero,n */
5205 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5215 /* In a frameless function, we might have incorrectly
5216 skipped some load immediate instructions. Undo the skipping
5217 if the load immediate was not followed by a stack adjustment. */
5218 if (load_immediate_bytes
&& !seen_sp_adjust
)
5219 pc
-= load_immediate_bytes
;
5223 /* Skip the PC past function prologue instructions (16-bit version).
5224 This is a helper function for mips_skip_prologue. */
5227 mips16_skip_prologue (CORE_ADDR pc
)
5230 int extend_bytes
= 0;
5231 int prev_extend_bytes
;
5233 /* Table of instructions likely to be found in a function prologue. */
5236 unsigned short inst
;
5237 unsigned short mask
;
5243 , /* addiu $sp,offset */
5246 , /* daddiu $sp,offset */
5249 , /* sw reg,n($sp) */
5252 , /* sd reg,n($sp) */
5255 , /* sw $ra,n($sp) */
5258 , /* sd $ra,n($sp) */
5264 , /* sw $a0-$a3,n($s1) */
5267 , /* move reg,$a0-$a3 */
5270 , /* entry pseudo-op */
5273 , /* addiu $s1,$sp,n */
5275 0, 0} /* end of table marker */
5278 /* Find an upper bound on the prologue. */
5279 end_pc
= skip_prologue_using_sal (pc
);
5281 end_pc
= pc
+ 100; /* Magic. */
5283 /* Skip the typical prologue instructions. These are the stack adjustment
5284 instruction and the instructions that save registers on the stack
5285 or in the gcc frame. */
5286 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
5288 unsigned short inst
;
5291 inst
= mips_fetch_instruction (pc
);
5293 /* Normally we ignore an extend instruction. However, if it is
5294 not followed by a valid prologue instruction, we must adjust
5295 the pc back over the extend so that it won't be considered
5296 part of the prologue. */
5297 if ((inst
& 0xf800) == 0xf000) /* extend */
5299 extend_bytes
= MIPS16_INSTLEN
;
5302 prev_extend_bytes
= extend_bytes
;
5305 /* Check for other valid prologue instructions besides extend. */
5306 for (i
= 0; table
[i
].mask
!= 0; i
++)
5307 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
5309 if (table
[i
].mask
!= 0) /* it was in table? */
5310 continue; /* ignore it */
5314 /* Return the current pc, adjusted backwards by 2 if
5315 the previous instruction was an extend. */
5316 return pc
- prev_extend_bytes
;
5322 /* To skip prologues, I use this predicate. Returns either PC itself
5323 if the code at PC does not look like a function prologue; otherwise
5324 returns an address that (if we're lucky) follows the prologue. If
5325 LENIENT, then we must skip everything which is involved in setting
5326 up the frame (it's OK to skip more, just so long as we don't skip
5327 anything which might clobber the registers which are being saved.
5328 We must skip more in the case where part of the prologue is in the
5329 delay slot of a non-prologue instruction). */
5332 mips_skip_prologue (CORE_ADDR pc
)
5334 /* See if we can determine the end of the prologue via the symbol table.
5335 If so, then return either PC, or the PC after the prologue, whichever
5338 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
5340 if (post_prologue_pc
!= 0)
5341 return max (pc
, post_prologue_pc
);
5343 /* Can't determine prologue from the symbol table, need to examine
5346 if (pc_is_mips16 (pc
))
5347 return mips16_skip_prologue (pc
);
5349 return mips32_skip_prologue (pc
);
5352 /* Exported procedure: Is PC in the signal trampoline code */
5355 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
5357 if (sigtramp_address
== 0)
5359 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
5362 /* Root of all "set mips "/"show mips " commands. This will eventually be
5363 used for all MIPS-specific commands. */
5366 show_mips_command (char *args
, int from_tty
)
5368 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5372 set_mips_command (char *args
, int from_tty
)
5375 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5376 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5379 /* Commands to show/set the MIPS FPU type. */
5382 show_mipsfpu_command (char *args
, int from_tty
)
5385 switch (MIPS_FPU_TYPE
)
5387 case MIPS_FPU_SINGLE
:
5388 fpu
= "single-precision";
5390 case MIPS_FPU_DOUBLE
:
5391 fpu
= "double-precision";
5394 fpu
= "absent (none)";
5397 internal_error (__FILE__
, __LINE__
, "bad switch");
5399 if (mips_fpu_type_auto
)
5401 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5405 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5410 set_mipsfpu_command (char *args
, int from_tty
)
5413 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5414 show_mipsfpu_command (args
, from_tty
);
5418 set_mipsfpu_single_command (char *args
, int from_tty
)
5420 struct gdbarch_info info
;
5421 gdbarch_info_init (&info
);
5422 mips_fpu_type
= MIPS_FPU_SINGLE
;
5423 mips_fpu_type_auto
= 0;
5424 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5425 instead of relying on globals. Doing that would let generic code
5426 handle the search for this specific architecture. */
5427 if (!gdbarch_update_p (info
))
5428 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5432 set_mipsfpu_double_command (char *args
, int from_tty
)
5434 struct gdbarch_info info
;
5435 gdbarch_info_init (&info
);
5436 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5437 mips_fpu_type_auto
= 0;
5438 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5439 instead of relying on globals. Doing that would let generic code
5440 handle the search for this specific architecture. */
5441 if (!gdbarch_update_p (info
))
5442 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5446 set_mipsfpu_none_command (char *args
, int from_tty
)
5448 struct gdbarch_info info
;
5449 gdbarch_info_init (&info
);
5450 mips_fpu_type
= MIPS_FPU_NONE
;
5451 mips_fpu_type_auto
= 0;
5452 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5453 instead of relying on globals. Doing that would let generic code
5454 handle the search for this specific architecture. */
5455 if (!gdbarch_update_p (info
))
5456 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5460 set_mipsfpu_auto_command (char *args
, int from_tty
)
5462 mips_fpu_type_auto
= 1;
5465 /* Attempt to identify the particular processor model by reading the
5466 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5467 the relevant processor still exists (it dates back to '94) and
5468 secondly this is not the way to do this. The processor type should
5469 be set by forcing an architecture change. */
5472 deprecated_mips_set_processor_regs_hack (void)
5474 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5477 prid
= read_register (PRID_REGNUM
);
5479 if ((prid
& ~0xf) == 0x700)
5480 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5483 /* Just like reinit_frame_cache, but with the right arguments to be
5484 callable as an sfunc. */
5487 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5488 struct cmd_list_element
*c
)
5490 reinit_frame_cache ();
5494 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5496 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5497 mips_extra_func_info_t proc_desc
;
5499 /* Search for the function containing this address. Set the low bit
5500 of the address when searching, in case we were given an even address
5501 that is the start of a 16-bit function. If we didn't do this,
5502 the search would fail because the symbol table says the function
5503 starts at an odd address, i.e. 1 byte past the given address. */
5504 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5505 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5507 /* Make an attempt to determine if this is a 16-bit function. If
5508 the procedure descriptor exists and the address therein is odd,
5509 it's definitely a 16-bit function. Otherwise, we have to just
5510 guess that if the address passed in is odd, it's 16-bits. */
5511 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5512 disassembler needs to be able to locally determine the ISA, and
5513 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5517 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5518 info
->mach
= bfd_mach_mips16
;
5522 if (pc_is_mips16 (memaddr
))
5523 info
->mach
= bfd_mach_mips16
;
5526 /* Round down the instruction address to the appropriate boundary. */
5527 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5529 /* Set the disassembler options. */
5530 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5532 /* Set up the disassembler info, so that we get the right
5533 register names from libopcodes. */
5534 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5535 info
->disassembler_options
= "gpr-names=n32";
5537 info
->disassembler_options
= "gpr-names=64";
5538 info
->flavour
= bfd_target_elf_flavour
;
5541 /* This string is not recognized explicitly by the disassembler,
5542 but it tells the disassembler to not try to guess the ABI from
5543 the bfd elf headers, such that, if the user overrides the ABI
5544 of a program linked as NewABI, the disassembly will follow the
5545 register naming conventions specified by the user. */
5546 info
->disassembler_options
= "gpr-names=32";
5548 /* Call the appropriate disassembler based on the target endian-ness. */
5549 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5550 return print_insn_big_mips (memaddr
, info
);
5552 return print_insn_little_mips (memaddr
, info
);
5555 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5556 counter value to determine whether a 16- or 32-bit breakpoint should be
5557 used. It returns a pointer to a string of bytes that encode a breakpoint
5558 instruction, stores the length of the string to *lenptr, and adjusts pc
5559 (if necessary) to point to the actual memory location where the
5560 breakpoint should be inserted. */
5562 static const unsigned char *
5563 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5565 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5567 if (pc_is_mips16 (*pcptr
))
5569 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5570 *pcptr
= unmake_mips16_addr (*pcptr
);
5571 *lenptr
= sizeof (mips16_big_breakpoint
);
5572 return mips16_big_breakpoint
;
5576 /* The IDT board uses an unusual breakpoint value, and
5577 sometimes gets confused when it sees the usual MIPS
5578 breakpoint instruction. */
5579 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5580 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5581 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5583 *lenptr
= sizeof (big_breakpoint
);
5585 if (strcmp (target_shortname
, "mips") == 0)
5586 return idt_big_breakpoint
;
5587 else if (strcmp (target_shortname
, "ddb") == 0
5588 || strcmp (target_shortname
, "pmon") == 0
5589 || strcmp (target_shortname
, "lsi") == 0)
5590 return pmon_big_breakpoint
;
5592 return big_breakpoint
;
5597 if (pc_is_mips16 (*pcptr
))
5599 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5600 *pcptr
= unmake_mips16_addr (*pcptr
);
5601 *lenptr
= sizeof (mips16_little_breakpoint
);
5602 return mips16_little_breakpoint
;
5606 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5607 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5608 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5610 *lenptr
= sizeof (little_breakpoint
);
5612 if (strcmp (target_shortname
, "mips") == 0)
5613 return idt_little_breakpoint
;
5614 else if (strcmp (target_shortname
, "ddb") == 0
5615 || strcmp (target_shortname
, "pmon") == 0
5616 || strcmp (target_shortname
, "lsi") == 0)
5617 return pmon_little_breakpoint
;
5619 return little_breakpoint
;
5624 /* If PC is in a mips16 call or return stub, return the address of the target
5625 PC, which is either the callee or the caller. There are several
5626 cases which must be handled:
5628 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5629 target PC is in $31 ($ra).
5630 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5631 and the target PC is in $2.
5632 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5633 before the jal instruction, this is effectively a call stub
5634 and the the target PC is in $2. Otherwise this is effectively
5635 a return stub and the target PC is in $18.
5637 See the source code for the stubs in gcc/config/mips/mips16.S for
5640 This function implements the SKIP_TRAMPOLINE_CODE macro.
5644 mips_skip_stub (CORE_ADDR pc
)
5647 CORE_ADDR start_addr
;
5649 /* Find the starting address and name of the function containing the PC. */
5650 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5653 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5654 target PC is in $31 ($ra). */
5655 if (strcmp (name
, "__mips16_ret_sf") == 0
5656 || strcmp (name
, "__mips16_ret_df") == 0)
5657 return read_signed_register (RA_REGNUM
);
5659 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5661 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5662 and the target PC is in $2. */
5663 if (name
[19] >= '0' && name
[19] <= '9')
5664 return read_signed_register (2);
5666 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5667 before the jal instruction, this is effectively a call stub
5668 and the the target PC is in $2. Otherwise this is effectively
5669 a return stub and the target PC is in $18. */
5670 else if (name
[19] == 's' || name
[19] == 'd')
5672 if (pc
== start_addr
)
5674 /* Check if the target of the stub is a compiler-generated
5675 stub. Such a stub for a function bar might have a name
5676 like __fn_stub_bar, and might look like this:
5681 la $1,bar (becomes a lui/addiu pair)
5683 So scan down to the lui/addi and extract the target
5684 address from those two instructions. */
5686 CORE_ADDR target_pc
= read_signed_register (2);
5690 /* See if the name of the target function is __fn_stub_*. */
5691 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5694 if (strncmp (name
, "__fn_stub_", 10) != 0
5695 && strcmp (name
, "etext") != 0
5696 && strcmp (name
, "_etext") != 0)
5699 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5700 The limit on the search is arbitrarily set to 20
5701 instructions. FIXME. */
5702 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5704 inst
= mips_fetch_instruction (target_pc
);
5705 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5706 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5707 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5708 return pc
| (inst
& 0xffff); /* low word */
5711 /* Couldn't find the lui/addui pair, so return stub address. */
5715 /* This is the 'return' part of a call stub. The return
5716 address is in $r18. */
5717 return read_signed_register (18);
5720 return 0; /* not a stub */
5724 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5725 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5728 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5730 CORE_ADDR start_addr
;
5732 /* Find the starting address of the function containing the PC. If the
5733 caller didn't give us a name, look it up at the same time. */
5734 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5738 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5740 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5741 if (name
[19] >= '0' && name
[19] <= '9')
5743 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5744 before the jal instruction, this is effectively a call stub. */
5745 else if (name
[19] == 's' || name
[19] == 'd')
5746 return pc
== start_addr
;
5749 return 0; /* not a stub */
5753 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5754 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5757 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5759 CORE_ADDR start_addr
;
5761 /* Find the starting address of the function containing the PC. */
5762 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5765 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5766 if (strcmp (name
, "__mips16_ret_sf") == 0
5767 || strcmp (name
, "__mips16_ret_df") == 0)
5770 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5771 i.e. after the jal instruction, this is effectively a return stub. */
5772 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5773 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5776 return 0; /* not a stub */
5780 /* Return non-zero if the PC is in a library helper function that should
5781 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5784 mips_ignore_helper (CORE_ADDR pc
)
5788 /* Find the starting address and name of the function containing the PC. */
5789 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5792 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5793 that we want to ignore. */
5794 return (strcmp (name
, "__mips16_ret_sf") == 0
5795 || strcmp (name
, "__mips16_ret_df") == 0);
5799 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5800 the register stored on the stack (32) is different to its real raw
5801 size (64). The below ensures that registers are fetched from the
5802 stack using their ABI size and then stored into the RAW_BUFFER
5803 using their raw size.
5805 The alternative to adding this function would be to add an ABI
5806 macro - REGISTER_STACK_SIZE(). */
5809 mips_get_saved_register (char *raw_buffer
,
5812 struct frame_info
*frame
,
5813 int regnum
, enum lval_type
*lvalp
)
5816 enum lval_type lvalx
;
5820 /* Always a pseudo. */
5821 gdb_assert (regnum
>= NUM_REGS
);
5823 /* Make certain that all needed parameters are present. */
5828 if (optimizedp
== NULL
)
5829 optimizedp
= &optimizedx
;
5831 if ((regnum
% NUM_REGS
) == SP_REGNUM
)
5832 /* The SP_REGNUM is special, its value is stored in saved_regs.
5833 In fact, it is so special that it can even only be fetched
5834 using a raw register number! Once this code as been converted
5835 to frame-unwind the problem goes away. */
5836 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5837 regnum
% NUM_REGS
, optimizedp
, lvalp
, addrp
,
5838 &realnumx
, raw_buffer
);
5840 /* Get it from the next frame. */
5841 frame_register_unwind (deprecated_get_next_frame_hack (frame
),
5842 regnum
, optimizedp
, lvalp
, addrp
,
5843 &realnumx
, raw_buffer
);
5846 /* Immediately after a function call, return the saved pc.
5847 Can't always go through the frames for this because on some machines
5848 the new frame is not set up until the new function executes
5849 some instructions. */
5852 mips_saved_pc_after_call (struct frame_info
*frame
)
5854 return read_signed_register (RA_REGNUM
);
5858 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5859 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5862 mips_stab_reg_to_regnum (int num
)
5865 if (num
>= 0 && num
< 32)
5867 else if (num
>= 38 && num
< 70)
5868 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5870 regnum
= mips_regnum (current_gdbarch
)->hi
;
5872 regnum
= mips_regnum (current_gdbarch
)->lo
;
5874 /* This will hopefully (eventually) provoke a warning. Should
5875 we be calling complaint() here? */
5876 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5877 return NUM_REGS
+ regnum
;
5881 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5882 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5885 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5888 if (num
>= 0 && num
< 32)
5890 else if (num
>= 32 && num
< 64)
5891 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5893 regnum
= mips_regnum (current_gdbarch
)->hi
;
5895 regnum
= mips_regnum (current_gdbarch
)->lo
;
5897 /* This will hopefully (eventually) provoke a warning. Should we
5898 be calling complaint() here? */
5899 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5900 return NUM_REGS
+ regnum
;
5904 mips_register_sim_regno (int regnum
)
5906 /* Only makes sense to supply raw registers. */
5907 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5908 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5909 decide if it is valid. Should instead define a standard sim/gdb
5910 register numbering scheme. */
5911 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5912 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5915 return LEGACY_SIM_REGNO_IGNORE
;
5919 /* Convert an integer into an address. By first converting the value
5920 into a pointer and then extracting it signed, the address is
5921 guarenteed to be correctly sign extended. */
5924 mips_integer_to_address (struct type
*type
, void *buf
)
5926 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5927 LONGEST val
= unpack_long (type
, buf
);
5928 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5929 return extract_signed_integer (tmp
,
5930 TYPE_LENGTH (builtin_type_void_data_ptr
));
5934 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5936 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5937 const char *name
= bfd_get_section_name (abfd
, sect
);
5939 if (*abip
!= MIPS_ABI_UNKNOWN
)
5942 if (strncmp (name
, ".mdebug.", 8) != 0)
5945 if (strcmp (name
, ".mdebug.abi32") == 0)
5946 *abip
= MIPS_ABI_O32
;
5947 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5948 *abip
= MIPS_ABI_N32
;
5949 else if (strcmp (name
, ".mdebug.abi64") == 0)
5950 *abip
= MIPS_ABI_N64
;
5951 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5952 *abip
= MIPS_ABI_O64
;
5953 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5954 *abip
= MIPS_ABI_EABI32
;
5955 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5956 *abip
= MIPS_ABI_EABI64
;
5958 warning ("unsupported ABI %s.", name
+ 8);
5961 static enum mips_abi
5962 global_mips_abi (void)
5966 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5967 if (mips_abi_strings
[i
] == mips_abi_string
)
5968 return (enum mips_abi
) i
;
5970 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5973 static struct gdbarch
*
5974 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5976 struct gdbarch
*gdbarch
;
5977 struct gdbarch_tdep
*tdep
;
5979 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5981 enum mips_fpu_type fpu_type
;
5983 /* First of all, extract the elf_flags, if available. */
5984 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5985 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5986 else if (arches
!= NULL
)
5987 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5991 fprintf_unfiltered (gdb_stdlog
,
5992 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5994 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5995 switch ((elf_flags
& EF_MIPS_ABI
))
5997 case E_MIPS_ABI_O32
:
5998 found_abi
= MIPS_ABI_O32
;
6000 case E_MIPS_ABI_O64
:
6001 found_abi
= MIPS_ABI_O64
;
6003 case E_MIPS_ABI_EABI32
:
6004 found_abi
= MIPS_ABI_EABI32
;
6006 case E_MIPS_ABI_EABI64
:
6007 found_abi
= MIPS_ABI_EABI64
;
6010 if ((elf_flags
& EF_MIPS_ABI2
))
6011 found_abi
= MIPS_ABI_N32
;
6013 found_abi
= MIPS_ABI_UNKNOWN
;
6017 /* GCC creates a pseudo-section whose name describes the ABI. */
6018 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
6019 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6021 /* If we have no usefu BFD information, use the ABI from the last
6022 MIPS architecture (if there is one). */
6023 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6024 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6026 /* Try the architecture for any hint of the correct ABI. */
6027 if (found_abi
== MIPS_ABI_UNKNOWN
6028 && info
.bfd_arch_info
!= NULL
6029 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6031 switch (info
.bfd_arch_info
->mach
)
6033 case bfd_mach_mips3900
:
6034 found_abi
= MIPS_ABI_EABI32
;
6036 case bfd_mach_mips4100
:
6037 case bfd_mach_mips5000
:
6038 found_abi
= MIPS_ABI_EABI64
;
6040 case bfd_mach_mips8000
:
6041 case bfd_mach_mips10000
:
6042 /* On Irix, ELF64 executables use the N64 ABI. The
6043 pseudo-sections which describe the ABI aren't present
6044 on IRIX. (Even for executables created by gcc.) */
6045 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6046 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6047 found_abi
= MIPS_ABI_N64
;
6049 found_abi
= MIPS_ABI_N32
;
6055 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6058 /* What has the user specified from the command line? */
6059 wanted_abi
= global_mips_abi ();
6061 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6064 /* Now that we have found what the ABI for this binary would be,
6065 check whether the user is overriding it. */
6066 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6067 mips_abi
= wanted_abi
;
6068 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6069 mips_abi
= found_abi
;
6071 mips_abi
= MIPS_ABI_O32
;
6073 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6076 /* Also used when doing an architecture lookup. */
6078 fprintf_unfiltered (gdb_stdlog
,
6079 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
6080 mips64_transfers_32bit_regs_p
);
6082 /* Determine the MIPS FPU type. */
6083 if (!mips_fpu_type_auto
)
6084 fpu_type
= mips_fpu_type
;
6085 else if (info
.bfd_arch_info
!= NULL
6086 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6087 switch (info
.bfd_arch_info
->mach
)
6089 case bfd_mach_mips3900
:
6090 case bfd_mach_mips4100
:
6091 case bfd_mach_mips4111
:
6092 fpu_type
= MIPS_FPU_NONE
;
6094 case bfd_mach_mips4650
:
6095 fpu_type
= MIPS_FPU_SINGLE
;
6098 fpu_type
= MIPS_FPU_DOUBLE
;
6101 else if (arches
!= NULL
)
6102 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6104 fpu_type
= MIPS_FPU_DOUBLE
;
6106 fprintf_unfiltered (gdb_stdlog
,
6107 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6109 /* try to find a pre-existing architecture */
6110 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6112 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6114 /* MIPS needs to be pedantic about which ABI the object is
6116 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6118 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6120 /* Need to be pedantic about which register virtual size is
6122 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6123 != mips64_transfers_32bit_regs_p
)
6125 /* Be pedantic about which FPU is selected. */
6126 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6128 return arches
->gdbarch
;
6131 /* Need a new architecture. Fill in a target specific vector. */
6132 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6133 gdbarch
= gdbarch_alloc (&info
, tdep
);
6134 tdep
->elf_flags
= elf_flags
;
6135 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6136 tdep
->found_abi
= found_abi
;
6137 tdep
->mips_abi
= mips_abi
;
6138 tdep
->mips_fpu_type
= fpu_type
;
6140 /* Initially set everything according to the default ABI/ISA. */
6141 set_gdbarch_short_bit (gdbarch
, 16);
6142 set_gdbarch_int_bit (gdbarch
, 32);
6143 set_gdbarch_float_bit (gdbarch
, 32);
6144 set_gdbarch_double_bit (gdbarch
, 64);
6145 set_gdbarch_long_double_bit (gdbarch
, 64);
6146 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6147 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6148 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6150 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6151 mips_elf_make_msymbol_special
);
6153 /* Fill in the OS dependant register numbers and names. */
6155 const char **reg_names
;
6156 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
6157 struct mips_regnum
);
6158 if (info
.osabi
== GDB_OSABI_IRIX
)
6163 regnum
->badvaddr
= 66;
6166 regnum
->fp_control_status
= 69;
6167 regnum
->fp_implementation_revision
= 70;
6169 reg_names
= mips_irix_reg_names
;
6173 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6174 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6175 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6176 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6177 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6178 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6179 regnum
->fp_control_status
= 70;
6180 regnum
->fp_implementation_revision
= 71;
6182 if (info
.bfd_arch_info
!= NULL
6183 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6184 reg_names
= mips_tx39_reg_names
;
6186 reg_names
= mips_generic_reg_names
;
6188 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
6189 replaced by read_pc? */
6190 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
);
6191 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6192 set_gdbarch_num_regs (gdbarch
, num_regs
);
6193 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6194 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6195 tdep
->mips_processor_reg_names
= reg_names
;
6196 tdep
->regnum
= regnum
;
6202 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6203 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6204 tdep
->mips_default_saved_regsize
= 4;
6205 tdep
->mips_default_stack_argsize
= 4;
6206 tdep
->mips_fp_register_double
= 0;
6207 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6208 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6209 tdep
->default_mask_address_p
= 0;
6210 set_gdbarch_long_bit (gdbarch
, 32);
6211 set_gdbarch_ptr_bit (gdbarch
, 32);
6212 set_gdbarch_long_long_bit (gdbarch
, 64);
6215 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6216 set_gdbarch_deprecated_store_return_value (gdbarch
,
6217 mips_o64_store_return_value
);
6218 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6219 mips_o64_extract_return_value
);
6220 tdep
->mips_default_saved_regsize
= 8;
6221 tdep
->mips_default_stack_argsize
= 8;
6222 tdep
->mips_fp_register_double
= 1;
6223 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6224 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6225 tdep
->default_mask_address_p
= 0;
6226 set_gdbarch_long_bit (gdbarch
, 32);
6227 set_gdbarch_ptr_bit (gdbarch
, 32);
6228 set_gdbarch_long_long_bit (gdbarch
, 64);
6229 set_gdbarch_use_struct_convention (gdbarch
,
6230 always_use_struct_convention
);
6232 case MIPS_ABI_EABI32
:
6233 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6234 set_gdbarch_deprecated_store_return_value (gdbarch
,
6235 mips_eabi_store_return_value
);
6236 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6237 mips_eabi_extract_return_value
);
6238 tdep
->mips_default_saved_regsize
= 4;
6239 tdep
->mips_default_stack_argsize
= 4;
6240 tdep
->mips_fp_register_double
= 0;
6241 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6242 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6243 tdep
->default_mask_address_p
= 0;
6244 set_gdbarch_long_bit (gdbarch
, 32);
6245 set_gdbarch_ptr_bit (gdbarch
, 32);
6246 set_gdbarch_long_long_bit (gdbarch
, 64);
6247 set_gdbarch_deprecated_reg_struct_has_addr
6248 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6249 set_gdbarch_use_struct_convention (gdbarch
,
6250 mips_eabi_use_struct_convention
);
6252 case MIPS_ABI_EABI64
:
6253 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6254 set_gdbarch_deprecated_store_return_value (gdbarch
,
6255 mips_eabi_store_return_value
);
6256 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6257 mips_eabi_extract_return_value
);
6258 tdep
->mips_default_saved_regsize
= 8;
6259 tdep
->mips_default_stack_argsize
= 8;
6260 tdep
->mips_fp_register_double
= 1;
6261 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6262 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6263 tdep
->default_mask_address_p
= 0;
6264 set_gdbarch_long_bit (gdbarch
, 64);
6265 set_gdbarch_ptr_bit (gdbarch
, 64);
6266 set_gdbarch_long_long_bit (gdbarch
, 64);
6267 set_gdbarch_deprecated_reg_struct_has_addr
6268 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6269 set_gdbarch_use_struct_convention (gdbarch
,
6270 mips_eabi_use_struct_convention
);
6273 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6274 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6275 tdep
->mips_default_saved_regsize
= 8;
6276 tdep
->mips_default_stack_argsize
= 8;
6277 tdep
->mips_fp_register_double
= 1;
6278 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6279 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6280 tdep
->default_mask_address_p
= 0;
6281 set_gdbarch_long_bit (gdbarch
, 32);
6282 set_gdbarch_ptr_bit (gdbarch
, 32);
6283 set_gdbarch_long_long_bit (gdbarch
, 64);
6286 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6287 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6288 tdep
->mips_default_saved_regsize
= 8;
6289 tdep
->mips_default_stack_argsize
= 8;
6290 tdep
->mips_fp_register_double
= 1;
6291 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6292 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6293 tdep
->default_mask_address_p
= 0;
6294 set_gdbarch_long_bit (gdbarch
, 64);
6295 set_gdbarch_ptr_bit (gdbarch
, 64);
6296 set_gdbarch_long_long_bit (gdbarch
, 64);
6299 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
6302 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6303 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6306 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6307 flag in object files because to do so would make it impossible to
6308 link with libraries compiled without "-gp32". This is
6309 unnecessarily restrictive.
6311 We could solve this problem by adding "-gp32" multilibs to gcc,
6312 but to set this flag before gcc is built with such multilibs will
6313 break too many systems.''
6315 But even more unhelpfully, the default linker output target for
6316 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6317 for 64-bit programs - you need to change the ABI to change this,
6318 and not all gcc targets support that currently. Therefore using
6319 this flag to detect 32-bit mode would do the wrong thing given
6320 the current gcc - it would make GDB treat these 64-bit programs
6321 as 32-bit programs by default. */
6323 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6324 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6325 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6327 /* Add/remove bits from an address. The MIPS needs be careful to
6328 ensure that all 32 bit addresses are sign extended to 64 bits. */
6329 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6332 /* Unwind the frame. */
6333 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6334 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
6335 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
6336 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
6338 set_gdbarch_deprecated_target_read_fp (gdbarch
, mips_read_sp
); /* Draft FRAME base. */
6339 /* Initialize a frame */
6340 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch
,
6341 mips_find_saved_regs
);
6342 set_gdbarch_deprecated_init_extra_frame_info (gdbarch
,
6343 mips_init_extra_frame_info
);
6344 /* There's a mess in stack frame creation. See comments in
6345 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
6346 set_gdbarch_deprecated_init_frame_pc_first (gdbarch
,
6347 mips_init_frame_pc_first
);
6348 set_gdbarch_deprecated_pop_frame (gdbarch
, mips_pop_frame
);
6349 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch
,
6350 generic_save_dummy_frame_tos
);
6351 set_gdbarch_deprecated_frame_chain (gdbarch
, mips_frame_chain
);
6352 set_gdbarch_frameless_function_invocation (gdbarch
,
6353 generic_frameless_function_invocation_not
);
6354 set_gdbarch_deprecated_frame_saved_pc (gdbarch
, mips_frame_saved_pc
);
6355 set_gdbarch_deprecated_get_saved_register (gdbarch
,
6356 mips_get_saved_register
);
6357 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
,
6358 mips_saved_pc_after_call
);
6361 /* Map debug register numbers onto internal register numbers. */
6362 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6363 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6364 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6365 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
6366 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6367 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6368 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6369 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6371 /* MIPS version of CALL_DUMMY */
6373 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6374 replaced by a command, and all targets will default to on stack
6375 (regardless of the stack's execute status). */
6376 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6377 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6379 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6380 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6381 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6383 set_gdbarch_frame_args_skip (gdbarch
, 0);
6385 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6386 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6388 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6390 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6391 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6392 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6394 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6396 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6397 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
6399 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6401 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6402 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6403 need to all be folded into the target vector. Since they are
6404 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6405 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6407 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6409 /* Hook in OS ABI-specific overrides, if they have been registered. */
6410 gdbarch_init_osabi (info
, gdbarch
);
6412 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6414 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6415 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6421 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6423 struct gdbarch_info info
;
6425 /* Force the architecture to update, and (if it's a MIPS architecture)
6426 mips_gdbarch_init will take care of the rest. */
6427 gdbarch_info_init (&info
);
6428 gdbarch_update_p (info
);
6431 /* Print out which MIPS ABI is in use. */
6434 show_mips_abi (char *ignore_args
, int from_tty
)
6436 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6438 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6441 enum mips_abi global_abi
= global_mips_abi ();
6442 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6443 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6445 if (global_abi
== MIPS_ABI_UNKNOWN
)
6447 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6449 else if (global_abi
== actual_abi
)
6451 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6455 /* Probably shouldn't happen... */
6457 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6458 actual_abi_str
, mips_abi_strings
[global_abi
]);
6464 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6466 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6470 int ef_mips_32bitmode
;
6471 /* determine the ISA */
6472 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6490 /* determine the size of a pointer */
6491 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6492 fprintf_unfiltered (file
,
6493 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6495 fprintf_unfiltered (file
,
6496 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6498 fprintf_unfiltered (file
,
6499 "mips_dump_tdep: ef_mips_arch = %d\n",
6501 fprintf_unfiltered (file
,
6502 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6503 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6504 fprintf_unfiltered (file
,
6505 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6506 mips_mask_address_p (tdep
),
6507 tdep
->default_mask_address_p
);
6509 fprintf_unfiltered (file
,
6510 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6511 FP_REGISTER_DOUBLE
);
6512 fprintf_unfiltered (file
,
6513 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6514 MIPS_DEFAULT_FPU_TYPE
,
6515 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6516 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6517 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6519 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6520 fprintf_unfiltered (file
,
6521 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6523 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6524 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6525 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6527 fprintf_unfiltered (file
,
6528 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6529 FP_REGISTER_DOUBLE
);
6530 fprintf_unfiltered (file
,
6531 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6532 mips_stack_argsize (tdep
));
6533 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6534 fprintf_unfiltered (file
,
6535 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6536 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6537 fprintf_unfiltered (file
,
6538 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6539 XSTRING (ATTACH_DETACH
));
6540 fprintf_unfiltered (file
,
6541 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6542 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6543 fprintf_unfiltered (file
,
6544 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6545 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6546 fprintf_unfiltered (file
,
6547 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6548 FIRST_EMBED_REGNUM
);
6549 fprintf_unfiltered (file
,
6550 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6551 XSTRING (IGNORE_HELPER_CALL (PC
)));
6552 fprintf_unfiltered (file
,
6553 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6554 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6555 fprintf_unfiltered (file
,
6556 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6557 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6558 fprintf_unfiltered (file
,
6559 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6561 #ifdef MACHINE_CPROC_FP_OFFSET
6562 fprintf_unfiltered (file
,
6563 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6564 MACHINE_CPROC_FP_OFFSET
);
6566 #ifdef MACHINE_CPROC_PC_OFFSET
6567 fprintf_unfiltered (file
,
6568 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6569 MACHINE_CPROC_PC_OFFSET
);
6571 #ifdef MACHINE_CPROC_SP_OFFSET
6572 fprintf_unfiltered (file
,
6573 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6574 MACHINE_CPROC_SP_OFFSET
);
6576 fprintf_unfiltered (file
,
6577 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6579 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6580 fprintf_unfiltered (file
,
6581 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6582 fprintf_unfiltered (file
,
6583 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6584 fprintf_unfiltered (file
,
6585 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6586 MIPS_LAST_ARG_REGNUM
,
6587 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6588 fprintf_unfiltered (file
,
6589 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6590 fprintf_unfiltered (file
,
6591 "mips_dump_tdep: mips_saved_regsize() = %d\n",
6592 mips_saved_regsize (tdep
));
6593 fprintf_unfiltered (file
,
6594 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6595 fprintf_unfiltered (file
,
6596 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6597 fprintf_unfiltered (file
,
6598 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6599 fprintf_unfiltered (file
,
6600 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6601 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6602 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6603 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6604 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6605 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6606 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6607 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6608 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6609 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6610 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6611 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6613 fprintf_unfiltered (file
,
6614 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6617 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6620 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6622 fprintf_unfiltered (file
,
6623 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6624 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6625 fprintf_unfiltered (file
,
6626 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6627 fprintf_unfiltered (file
,
6628 "mips_dump_tdep: SIGFRAME_BASE = %d\n", SIGFRAME_BASE
);
6629 fprintf_unfiltered (file
,
6630 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6631 SIGFRAME_FPREGSAVE_OFF
);
6632 fprintf_unfiltered (file
,
6633 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6635 fprintf_unfiltered (file
,
6636 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6637 SIGFRAME_REGSAVE_OFF
);
6638 fprintf_unfiltered (file
,
6639 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6640 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6641 fprintf_unfiltered (file
,
6642 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6643 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6644 fprintf_unfiltered (file
,
6645 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6646 SOFTWARE_SINGLE_STEP_P ());
6647 fprintf_unfiltered (file
,
6648 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6649 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6650 #ifdef STACK_END_ADDR
6651 fprintf_unfiltered (file
,
6652 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6655 fprintf_unfiltered (file
,
6656 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6657 XSTRING (STEP_SKIPS_DELAY (PC
)));
6658 fprintf_unfiltered (file
,
6659 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6660 STEP_SKIPS_DELAY_P
);
6661 fprintf_unfiltered (file
,
6662 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6663 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6664 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6665 fprintf_unfiltered (file
,
6666 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6667 fprintf_unfiltered (file
,
6668 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6669 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6670 (TYPE
, CNT
, OTHERTYPE
)));
6671 fprintf_unfiltered (file
,
6672 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6673 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6675 fprintf_unfiltered (file
,
6676 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6677 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6680 fprintf_unfiltered (file
,
6681 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6683 #ifdef TRACE_FLAVOR_SIZE
6684 fprintf_unfiltered (file
,
6685 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6689 fprintf_unfiltered (file
,
6690 "mips_dump_tdep: TRACE_SET # %s\n",
6691 XSTRING (TRACE_SET (X
, STATE
)));
6693 #ifdef UNUSED_REGNUM
6694 fprintf_unfiltered (file
,
6695 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6697 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6698 fprintf_unfiltered (file
,
6699 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6700 (long) VM_MIN_ADDRESS
);
6701 fprintf_unfiltered (file
,
6702 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6703 fprintf_unfiltered (file
,
6704 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_
);
6707 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6710 _initialize_mips_tdep (void)
6712 static struct cmd_list_element
*mipsfpulist
= NULL
;
6713 struct cmd_list_element
*c
;
6715 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6716 if (MIPS_ABI_LAST
+ 1
6717 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6718 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6720 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6722 /* Add root prefix command for all "set mips"/"show mips" commands */
6723 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6724 "Various MIPS specific commands.",
6725 &setmipscmdlist
, "set mips ", 0, &setlist
);
6727 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6728 "Various MIPS specific commands.",
6729 &showmipscmdlist
, "show mips ", 0, &showlist
);
6731 /* Allow the user to override the saved register size. */
6732 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6735 &mips_saved_regsize_string
, "\
6736 Set size of general purpose registers saved on the stack.\n\
6737 This option can be set to one of:\n\
6738 32 - Force GDB to treat saved GP registers as 32-bit\n\
6739 64 - Force GDB to treat saved GP registers as 64-bit\n\
6740 auto - Allow GDB to use the target's default setting or autodetect the\n\
6741 saved GP register size from information contained in the executable.\n\
6742 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6744 /* Allow the user to override the argument stack size. */
6745 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6748 &mips_stack_argsize_string
, "\
6749 Set the amount of stack space reserved for each argument.\n\
6750 This option can be set to one of:\n\
6751 32 - Force GDB to allocate 32-bit chunks per argument\n\
6752 64 - Force GDB to allocate 64-bit chunks per argument\n\
6753 auto - Allow GDB to determine the correct setting from the current\n\
6754 target and executable (default)", &setmipscmdlist
), &showmipscmdlist
);
6756 /* Allow the user to override the ABI. */
6757 c
= add_set_enum_cmd
6758 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6759 "Set the ABI used by this program.\n"
6760 "This option can be set to one of:\n"
6761 " auto - the default ABI associated with the current binary\n"
6763 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6764 set_cmd_sfunc (c
, mips_abi_update
);
6765 add_cmd ("abi", class_obscure
, show_mips_abi
,
6766 "Show ABI in use by MIPS target", &showmipscmdlist
);
6768 /* Let the user turn off floating point and set the fence post for
6769 heuristic_proc_start. */
6771 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6772 "Set use of MIPS floating-point coprocessor.",
6773 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6774 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6775 "Select single-precision MIPS floating-point coprocessor.",
6777 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6778 "Select double-precision MIPS floating-point coprocessor.",
6780 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6781 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6782 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6783 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6784 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6785 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6786 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6787 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6788 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6789 "Select MIPS floating-point coprocessor automatically.",
6791 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6792 "Show current use of MIPS floating-point coprocessor target.",
6795 /* We really would like to have both "0" and "unlimited" work, but
6796 command.c doesn't deal with that. So make it a var_zinteger
6797 because the user can always use "999999" or some such for unlimited. */
6798 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6799 (char *) &heuristic_fence_post
, "\
6800 Set the distance searched for the start of a function.\n\
6801 If you are debugging a stripped executable, GDB needs to search through the\n\
6802 program for the start of a function. This command sets the distance of the\n\
6803 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6804 /* We need to throw away the frame cache when we set this, since it
6805 might change our ability to get backtraces. */
6806 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6807 add_show_from_set (c
, &showlist
);
6809 /* Allow the user to control whether the upper bits of 64-bit
6810 addresses should be zeroed. */
6811 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6812 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6813 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6814 allow GDB to determine the correct value.\n", "\
6815 Show zeroing of upper 32 bits of 64-bit addresses.",
6816 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6818 /* Allow the user to control the size of 32 bit registers within the
6819 raw remote packet. */
6820 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6821 var_boolean
, &mips64_transfers_32bit_regs_p
, "\
6822 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6823 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6824 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6825 64 bits for others. Use \"off\" to disable compatibility mode", "\
6826 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6827 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6828 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6829 64 bits for others. Use \"off\" to disable compatibility mode", set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6831 /* Debug this files internals. */
6832 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6833 &mips_debug
, "Set mips debugging.\n\
6834 When non-zero, mips specific debugging is enabled.", &setdebuglist
), &showdebuglist
);