1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
43 #include "opcode/mips.h"
48 /* A useful bit in the CP0 status register (PS_REGNUM). */
49 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
50 #define ST0_FR (1 << 26)
52 /* The sizes of floating point registers. */
56 MIPS_FPU_SINGLE_REGSIZE
= 4,
57 MIPS_FPU_DOUBLE_REGSIZE
= 8
60 /* All the possible MIPS ABIs. */
72 struct frame_extra_info
74 mips_extra_func_info_t proc_desc
;
78 /* Various MIPS ISA options (related to stack analysis) can be
79 overridden dynamically. Establish an enum/array for managing
82 static const char size_auto
[] = "auto";
83 static const char size_32
[] = "32";
84 static const char size_64
[] = "64";
86 static const char *size_enums
[] = {
93 /* Some MIPS boards don't support floating point while others only
94 support single-precision floating-point operations. See also
95 FP_REGISTER_DOUBLE. */
99 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
100 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
101 MIPS_FPU_NONE
/* No floating point. */
104 #ifndef MIPS_DEFAULT_FPU_TYPE
105 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
107 static int mips_fpu_type_auto
= 1;
108 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
110 static int mips_debug
= 0;
112 /* MIPS specific per-architecture information */
115 /* from the elf header */
119 enum mips_abi mips_abi
;
120 const char *mips_abi_string
;
121 enum mips_fpu_type mips_fpu_type
;
122 int mips_last_arg_regnum
;
123 int mips_last_fp_arg_regnum
;
124 int mips_default_saved_regsize
;
125 int mips_fp_register_double
;
126 int mips_regs_have_home_p
;
127 int mips_default_stack_argsize
;
128 int gdb_target_is_mips64
;
129 int default_mask_address_p
;
131 enum gdb_osabi osabi
;
134 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
135 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
137 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
139 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
141 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
143 /* Return the currently configured (or set) saved register size. */
145 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
147 static const char *mips_saved_regsize_string
= size_auto
;
149 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
152 mips_saved_regsize (void)
154 if (mips_saved_regsize_string
== size_auto
)
155 return MIPS_DEFAULT_SAVED_REGSIZE
;
156 else if (mips_saved_regsize_string
== size_64
)
158 else /* if (mips_saved_regsize_string == size_32) */
162 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
163 compatiblity mode. A return value of 1 means that we have
164 physical 64-bit registers, but should treat them as 32-bit registers. */
167 mips2_fp_compat (void)
169 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
171 if (REGISTER_RAW_SIZE (FP0_REGNUM
) == 4)
175 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
176 in all the places we deal with FP registers. PR gdb/413. */
177 /* Otherwise check the FR bit in the status register - it controls
178 the FP compatiblity mode. If it is clear we are in compatibility
180 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
187 /* Indicate that the ABI makes use of double-precision registers
188 provided by the FPU (rather than combining pairs of registers to
189 form double-precision values). Do not use "TARGET_IS_MIPS64" to
190 determine if the ABI is using double-precision registers. See also
192 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
194 /* Does the caller allocate a ``home'' for each register used in the
195 function call? The N32 ABI and MIPS_EABI do not, the others do. */
197 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
199 /* The amount of space reserved on the stack for registers. This is
200 different to MIPS_SAVED_REGSIZE as it determines the alignment of
201 data allocated after the registers have run out. */
203 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
205 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
207 static const char *mips_stack_argsize_string
= size_auto
;
210 mips_stack_argsize (void)
212 if (mips_stack_argsize_string
== size_auto
)
213 return MIPS_DEFAULT_STACK_ARGSIZE
;
214 else if (mips_stack_argsize_string
== size_64
)
216 else /* if (mips_stack_argsize_string == size_32) */
220 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
222 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
224 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
226 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
228 static void mips_print_register (int, int);
230 static mips_extra_func_info_t
231 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*, int);
233 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
235 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
237 int mips_set_processor_type (char *);
239 static void mips_show_processor_type_command (char *, int);
241 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
243 static mips_extra_func_info_t
244 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
);
246 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
247 mips_extra_func_info_t proc_desc
);
249 static void mips_read_fp_register_single (int regno
, char *rare_buffer
);
250 static void mips_read_fp_register_double (int regno
, char *rare_buffer
);
252 static struct type
*mips_float_register_type (void);
253 static struct type
*mips_double_register_type (void);
255 /* This value is the model of MIPS in use. It is derived from the value
256 of the PrID register. */
258 char *mips_processor_type
;
260 char *tmp_mips_processor_type
;
262 /* The list of available "set mips " and "show mips " commands */
264 static struct cmd_list_element
*setmipscmdlist
= NULL
;
265 static struct cmd_list_element
*showmipscmdlist
= NULL
;
267 /* A set of original names, to be used when restoring back to generic
268 registers from a specific set. */
270 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
271 char **mips_processor_reg_names
= mips_generic_reg_names
;
274 mips_register_name (int i
)
276 return mips_processor_reg_names
[i
];
279 /* Names of IDT R3041 registers. */
281 char *mips_r3041_reg_names
[] = {
282 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
283 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
284 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
285 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
286 "sr", "lo", "hi", "bad", "cause","pc",
287 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
288 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
289 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
290 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
291 "fsr", "fir", "fp", "",
292 "", "", "bus", "ccfg", "", "", "", "",
293 "", "", "port", "cmp", "", "", "epc", "prid",
296 /* Names of IDT R3051 registers. */
298 char *mips_r3051_reg_names
[] = {
299 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
300 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
301 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
302 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
303 "sr", "lo", "hi", "bad", "cause","pc",
304 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
305 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
306 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
307 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
308 "fsr", "fir", "fp", "",
309 "inx", "rand", "elo", "", "ctxt", "", "", "",
310 "", "", "ehi", "", "", "", "epc", "prid",
313 /* Names of IDT R3081 registers. */
315 char *mips_r3081_reg_names
[] = {
316 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
317 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
318 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
319 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
320 "sr", "lo", "hi", "bad", "cause","pc",
321 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
322 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
323 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
324 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
325 "fsr", "fir", "fp", "",
326 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
327 "", "", "ehi", "", "", "", "epc", "prid",
330 /* Names of LSI 33k registers. */
332 char *mips_lsi33k_reg_names
[] = {
333 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
334 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
335 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
336 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
337 "epc", "hi", "lo", "sr", "cause","badvaddr",
338 "dcic", "bpc", "bda", "", "", "", "", "",
339 "", "", "", "", "", "", "", "",
340 "", "", "", "", "", "", "", "",
341 "", "", "", "", "", "", "", "",
343 "", "", "", "", "", "", "", "",
344 "", "", "", "", "", "", "", "",
350 } mips_processor_type_table
[] = {
351 { "generic", mips_generic_reg_names
},
352 { "r3041", mips_r3041_reg_names
},
353 { "r3051", mips_r3051_reg_names
},
354 { "r3071", mips_r3081_reg_names
},
355 { "r3081", mips_r3081_reg_names
},
356 { "lsi33k", mips_lsi33k_reg_names
},
364 /* Table to translate MIPS16 register field to actual register number. */
365 static int mips16_to_32_reg
[8] =
366 {16, 17, 2, 3, 4, 5, 6, 7};
368 /* Heuristic_proc_start may hunt through the text section for a long
369 time across a 2400 baud serial line. Allows the user to limit this
372 static unsigned int heuristic_fence_post
= 0;
374 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
375 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
376 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
377 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
378 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
379 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
380 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
381 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
382 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
383 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
384 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
385 this will corrupt pdr.iline. Fortunately we don't use it. */
386 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
387 #define _PROC_MAGIC_ 0x0F0F0F0F
388 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
389 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
391 struct linked_proc_info
393 struct mips_extra_func_info info
;
394 struct linked_proc_info
*next
;
396 *linked_proc_desc_table
= NULL
;
399 mips_print_extra_frame_info (struct frame_info
*fi
)
403 && fi
->extra_info
->proc_desc
404 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
405 printf_filtered (" frame pointer is at %s+%s\n",
406 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
407 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
410 /* Number of bytes of storage in the actual machine representation for
411 register N. NOTE: This indirectly defines the register size
412 transfered by the GDB protocol. */
414 static int mips64_transfers_32bit_regs_p
= 0;
417 mips_register_raw_size (int reg_nr
)
419 if (mips64_transfers_32bit_regs_p
)
420 return REGISTER_VIRTUAL_SIZE (reg_nr
);
421 else if (reg_nr
>= FP0_REGNUM
&& reg_nr
< FP0_REGNUM
+ 32
422 && FP_REGISTER_DOUBLE
)
423 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
430 /* Convert between RAW and VIRTUAL registers. The RAW register size
431 defines the remote-gdb packet. */
434 mips_register_convertible (int reg_nr
)
436 if (mips64_transfers_32bit_regs_p
)
439 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
443 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
444 char *raw_buf
, char *virt_buf
)
446 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
448 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
449 TYPE_LENGTH (virtual_type
));
453 TYPE_LENGTH (virtual_type
));
457 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
458 char *virt_buf
, char *raw_buf
)
460 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
461 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
462 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
464 TYPE_LENGTH (virtual_type
));
468 TYPE_LENGTH (virtual_type
));
471 /* Should the upper word of 64-bit addresses be zeroed? */
472 enum cmd_auto_boolean mask_address_var
= CMD_AUTO_BOOLEAN_AUTO
;
475 mips_mask_address_p (void)
477 switch (mask_address_var
)
479 case CMD_AUTO_BOOLEAN_TRUE
:
481 case CMD_AUTO_BOOLEAN_FALSE
:
484 case CMD_AUTO_BOOLEAN_AUTO
:
485 return MIPS_DEFAULT_MASK_ADDRESS_P
;
487 internal_error (__FILE__
, __LINE__
,
488 "mips_mask_address_p: bad switch");
494 show_mask_address (char *cmd
, int from_tty
)
496 switch (mask_address_var
)
498 case CMD_AUTO_BOOLEAN_TRUE
:
499 printf_filtered ("The 32 bit mips address mask is enabled\n");
501 case CMD_AUTO_BOOLEAN_FALSE
:
502 printf_filtered ("The 32 bit mips address mask is disabled\n");
504 case CMD_AUTO_BOOLEAN_AUTO
:
505 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
506 mips_mask_address_p () ? "enabled" : "disabled");
509 internal_error (__FILE__
, __LINE__
,
510 "show_mask_address: bad switch");
515 /* Should call_function allocate stack space for a struct return? */
517 mips_use_struct_convention (int gcc_p
, struct type
*type
)
520 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
522 return 1; /* Structures are returned by ref in extra arg0 */
525 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
528 pc_is_mips16 (bfd_vma memaddr
)
530 struct minimal_symbol
*sym
;
532 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
533 if (IS_MIPS16_ADDR (memaddr
))
536 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
537 the high bit of the info field. Use this to decide if the function is
538 MIPS16 or normal MIPS. */
539 sym
= lookup_minimal_symbol_by_pc (memaddr
);
541 return MSYMBOL_IS_SPECIAL (sym
);
546 /* MIPS believes that the PC has a sign extended value. Perhaphs the
547 all registers should be sign extended for simplicity? */
550 mips_read_pc (ptid_t ptid
)
552 return read_signed_register_pid (PC_REGNUM
, ptid
);
555 /* This returns the PC of the first inst after the prologue. If we can't
556 find the prologue, then return 0. */
559 after_prologue (CORE_ADDR pc
,
560 mips_extra_func_info_t proc_desc
)
562 struct symtab_and_line sal
;
563 CORE_ADDR func_addr
, func_end
;
565 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
566 to read the stack pointer from the current machine state, because
567 the current machine state has nothing to do with the information
568 we need from the proc_desc; and the process may or may not exist
571 proc_desc
= find_proc_desc (pc
, NULL
, 0);
575 /* If function is frameless, then we need to do it the hard way. I
576 strongly suspect that frameless always means prologueless... */
577 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
578 && PROC_FRAME_OFFSET (proc_desc
) == 0)
582 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
583 return 0; /* Unknown */
585 sal
= find_pc_line (func_addr
, 0);
587 if (sal
.end
< func_end
)
590 /* The line after the prologue is after the end of the function. In this
591 case, tell the caller to find the prologue the hard way. */
596 /* Decode a MIPS32 instruction that saves a register in the stack, and
597 set the appropriate bit in the general register mask or float register mask
598 to indicate which register is saved. This is a helper function
599 for mips_find_saved_regs. */
602 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
603 unsigned long *float_mask
)
607 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
608 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
609 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
611 /* It might be possible to use the instruction to
612 find the offset, rather than the code below which
613 is based on things being in a certain order in the
614 frame, but figuring out what the instruction's offset
615 is relative to might be a little tricky. */
616 reg
= (inst
& 0x001f0000) >> 16;
617 *gen_mask
|= (1 << reg
);
619 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
620 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
621 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
624 reg
= ((inst
& 0x001f0000) >> 16);
625 *float_mask
|= (1 << reg
);
629 /* Decode a MIPS16 instruction that saves a register in the stack, and
630 set the appropriate bit in the general register or float register mask
631 to indicate which register is saved. This is a helper function
632 for mips_find_saved_regs. */
635 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
637 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
639 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
640 *gen_mask
|= (1 << reg
);
642 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
644 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
645 *gen_mask
|= (1 << reg
);
647 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
648 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
649 *gen_mask
|= (1 << RA_REGNUM
);
653 /* Fetch and return instruction from the specified location. If the PC
654 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
657 mips_fetch_instruction (CORE_ADDR addr
)
659 char buf
[MIPS_INSTLEN
];
663 if (pc_is_mips16 (addr
))
665 instlen
= MIPS16_INSTLEN
;
666 addr
= UNMAKE_MIPS16_ADDR (addr
);
669 instlen
= MIPS_INSTLEN
;
670 status
= read_memory_nobpt (addr
, buf
, instlen
);
672 memory_error (status
, addr
);
673 return extract_unsigned_integer (buf
, instlen
);
677 /* These the fields of 32 bit mips instructions */
678 #define mips32_op(x) (x >> 26)
679 #define itype_op(x) (x >> 26)
680 #define itype_rs(x) ((x >> 21) & 0x1f)
681 #define itype_rt(x) ((x >> 16) & 0x1f)
682 #define itype_immediate(x) (x & 0xffff)
684 #define jtype_op(x) (x >> 26)
685 #define jtype_target(x) (x & 0x03ffffff)
687 #define rtype_op(x) (x >> 26)
688 #define rtype_rs(x) ((x >> 21) & 0x1f)
689 #define rtype_rt(x) ((x >> 16) & 0x1f)
690 #define rtype_rd(x) ((x >> 11) & 0x1f)
691 #define rtype_shamt(x) ((x >> 6) & 0x1f)
692 #define rtype_funct(x) (x & 0x3f)
695 mips32_relative_offset (unsigned long inst
)
698 x
= itype_immediate (inst
);
699 if (x
& 0x8000) /* sign bit set */
701 x
|= 0xffff0000; /* sign extension */
707 /* Determine whate to set a single step breakpoint while considering
710 mips32_next_pc (CORE_ADDR pc
)
714 inst
= mips_fetch_instruction (pc
);
715 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
717 if (itype_op (inst
) >> 2 == 5)
718 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
720 op
= (itype_op (inst
) & 0x03);
735 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
736 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
738 int tf
= itype_rt (inst
) & 0x01;
739 int cnum
= itype_rt (inst
) >> 2;
740 int fcrcs
= read_signed_register (FCRCS_REGNUM
);
741 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
743 if (((cond
>> cnum
) & 0x01) == tf
)
744 pc
+= mips32_relative_offset (inst
) + 4;
749 pc
+= 4; /* Not a branch, next instruction is easy */
752 { /* This gets way messy */
754 /* Further subdivide into SPECIAL, REGIMM and other */
755 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
757 case 0: /* SPECIAL */
758 op
= rtype_funct (inst
);
763 /* Set PC to that address */
764 pc
= read_signed_register (rtype_rs (inst
));
770 break; /* end SPECIAL */
773 op
= itype_rt (inst
); /* branch condition */
778 case 16: /* BLTZAL */
779 case 18: /* BLTZALL */
781 if (read_signed_register (itype_rs (inst
)) < 0)
782 pc
+= mips32_relative_offset (inst
) + 4;
784 pc
+= 8; /* after the delay slot */
788 case 17: /* BGEZAL */
789 case 19: /* BGEZALL */
790 greater_equal_branch
:
791 if (read_signed_register (itype_rs (inst
)) >= 0)
792 pc
+= mips32_relative_offset (inst
) + 4;
794 pc
+= 8; /* after the delay slot */
796 /* All of the other instructions in the REGIMM category */
801 break; /* end REGIMM */
806 reg
= jtype_target (inst
) << 2;
807 /* Upper four bits get never changed... */
808 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
811 /* FIXME case JALX : */
814 reg
= jtype_target (inst
) << 2;
815 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
816 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
818 break; /* The new PC will be alternate mode */
819 case 4: /* BEQ, BEQL */
821 if (read_signed_register (itype_rs (inst
)) ==
822 read_signed_register (itype_rt (inst
)))
823 pc
+= mips32_relative_offset (inst
) + 4;
827 case 5: /* BNE, BNEL */
829 if (read_signed_register (itype_rs (inst
)) !=
830 read_signed_register (itype_rt (inst
)))
831 pc
+= mips32_relative_offset (inst
) + 4;
835 case 6: /* BLEZ, BLEZL */
837 if (read_signed_register (itype_rs (inst
) <= 0))
838 pc
+= mips32_relative_offset (inst
) + 4;
844 greater_branch
: /* BGTZ, BGTZL */
845 if (read_signed_register (itype_rs (inst
) > 0))
846 pc
+= mips32_relative_offset (inst
) + 4;
853 } /* mips32_next_pc */
855 /* Decoding the next place to set a breakpoint is irregular for the
856 mips 16 variant, but fortunately, there fewer instructions. We have to cope
857 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
858 We dont want to set a single step instruction on the extend instruction
862 /* Lots of mips16 instruction formats */
863 /* Predicting jumps requires itype,ritype,i8type
864 and their extensions extItype,extritype,extI8type
866 enum mips16_inst_fmts
868 itype
, /* 0 immediate 5,10 */
869 ritype
, /* 1 5,3,8 */
870 rrtype
, /* 2 5,3,3,5 */
871 rritype
, /* 3 5,3,3,5 */
872 rrrtype
, /* 4 5,3,3,3,2 */
873 rriatype
, /* 5 5,3,3,1,4 */
874 shifttype
, /* 6 5,3,3,3,2 */
875 i8type
, /* 7 5,3,8 */
876 i8movtype
, /* 8 5,3,3,5 */
877 i8mov32rtype
, /* 9 5,3,5,3 */
878 i64type
, /* 10 5,3,8 */
879 ri64type
, /* 11 5,3,3,5 */
880 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
881 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
882 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
883 extRRItype
, /* 15 5,5,5,5,3,3,5 */
884 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
885 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
886 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
887 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
888 extRi64type
, /* 20 5,6,5,5,3,3,5 */
889 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
891 /* I am heaping all the fields of the formats into one structure and
892 then, only the fields which are involved in instruction extension */
896 unsigned int regx
; /* Function in i8 type */
901 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
902 for the bits which make up the immediatate extension. */
905 extended_offset (unsigned int extension
)
908 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
910 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
912 value
|= extension
& 0x01f; /* extract 4:0 */
916 /* Only call this function if you know that this is an extendable
917 instruction, It wont malfunction, but why make excess remote memory references?
918 If the immediate operands get sign extended or somthing, do it after
919 the extension is performed.
921 /* FIXME: Every one of these cases needs to worry about sign extension
922 when the offset is to be used in relative addressing */
926 fetch_mips_16 (CORE_ADDR pc
)
929 pc
&= 0xfffffffe; /* clear the low order bit */
930 target_read_memory (pc
, buf
, 2);
931 return extract_unsigned_integer (buf
, 2);
935 unpack_mips16 (CORE_ADDR pc
,
936 unsigned int extension
,
938 enum mips16_inst_fmts insn_format
,
939 struct upk_mips16
*upk
)
951 value
= extended_offset (extension
);
952 value
= value
<< 11; /* rom for the original value */
953 value
|= inst
& 0x7ff; /* eleven bits from instruction */
957 value
= inst
& 0x7ff;
958 /* FIXME : Consider sign extension */
967 { /* A register identifier and an offset */
968 /* Most of the fields are the same as I type but the
969 immediate value is of a different length */
973 value
= extended_offset (extension
);
974 value
= value
<< 8; /* from the original instruction */
975 value
|= inst
& 0xff; /* eleven bits from instruction */
976 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
977 if (value
& 0x4000) /* test the sign bit , bit 26 */
979 value
&= ~0x3fff; /* remove the sign bit */
985 value
= inst
& 0xff; /* 8 bits */
986 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
987 /* FIXME: Do sign extension , this format needs it */
988 if (value
& 0x80) /* THIS CONFUSES ME */
990 value
&= 0xef; /* remove the sign bit */
1000 unsigned long value
;
1001 unsigned int nexthalf
;
1002 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1003 value
= value
<< 16;
1004 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1012 internal_error (__FILE__
, __LINE__
,
1015 upk
->offset
= offset
;
1022 add_offset_16 (CORE_ADDR pc
, int offset
)
1024 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1029 extended_mips16_next_pc (CORE_ADDR pc
,
1030 unsigned int extension
,
1033 int op
= (insn
>> 11);
1036 case 2: /* Branch */
1039 struct upk_mips16 upk
;
1040 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1041 offset
= upk
.offset
;
1047 pc
+= (offset
<< 1) + 2;
1050 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1052 struct upk_mips16 upk
;
1053 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1054 pc
= add_offset_16 (pc
, upk
.offset
);
1055 if ((insn
>> 10) & 0x01) /* Exchange mode */
1056 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1063 struct upk_mips16 upk
;
1065 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1066 reg
= read_signed_register (upk
.regx
);
1068 pc
+= (upk
.offset
<< 1) + 2;
1075 struct upk_mips16 upk
;
1077 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1078 reg
= read_signed_register (upk
.regx
);
1080 pc
+= (upk
.offset
<< 1) + 2;
1085 case 12: /* I8 Formats btez btnez */
1087 struct upk_mips16 upk
;
1089 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1090 /* upk.regx contains the opcode */
1091 reg
= read_signed_register (24); /* Test register is 24 */
1092 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1093 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1094 /* pc = add_offset_16(pc,upk.offset) ; */
1095 pc
+= (upk
.offset
<< 1) + 2;
1100 case 29: /* RR Formats JR, JALR, JALR-RA */
1102 struct upk_mips16 upk
;
1103 /* upk.fmt = rrtype; */
1108 upk
.regx
= (insn
>> 8) & 0x07;
1109 upk
.regy
= (insn
>> 5) & 0x07;
1117 break; /* Function return instruction */
1123 break; /* BOGUS Guess */
1125 pc
= read_signed_register (reg
);
1132 /* This is an instruction extension. Fetch the real instruction
1133 (which follows the extension) and decode things based on
1137 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1150 mips16_next_pc (CORE_ADDR pc
)
1152 unsigned int insn
= fetch_mips_16 (pc
);
1153 return extended_mips16_next_pc (pc
, 0, insn
);
1156 /* The mips_next_pc function supports single_step when the remote
1157 target monitor or stub is not developed enough to do a single_step.
1158 It works by decoding the current instruction and predicting where a
1159 branch will go. This isnt hard because all the data is available.
1160 The MIPS32 and MIPS16 variants are quite different */
1162 mips_next_pc (CORE_ADDR pc
)
1165 return mips16_next_pc (pc
);
1167 return mips32_next_pc (pc
);
1170 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1174 mips_find_saved_regs (struct frame_info
*fci
)
1177 CORE_ADDR reg_position
;
1178 /* r0 bit means kernel trap */
1180 /* What registers have been saved? Bitmasks. */
1181 unsigned long gen_mask
, float_mask
;
1182 mips_extra_func_info_t proc_desc
;
1185 frame_saved_regs_zalloc (fci
);
1187 /* If it is the frame for sigtramp, the saved registers are located
1188 in a sigcontext structure somewhere on the stack.
1189 If the stack layout for sigtramp changes we might have to change these
1190 constants and the companion fixup_sigtramp in mdebugread.c */
1191 #ifndef SIGFRAME_BASE
1192 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1193 above the sigtramp frame. */
1194 #define SIGFRAME_BASE MIPS_REGSIZE
1195 /* FIXME! Are these correct?? */
1196 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1197 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1198 #define SIGFRAME_FPREGSAVE_OFF \
1199 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1201 #ifndef SIGFRAME_REG_SIZE
1202 /* FIXME! Is this correct?? */
1203 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1205 if (fci
->signal_handler_caller
)
1207 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1209 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1210 + ireg
* SIGFRAME_REG_SIZE
;
1211 fci
->saved_regs
[ireg
] = reg_position
;
1213 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1215 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1216 + ireg
* SIGFRAME_REG_SIZE
;
1217 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1219 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1223 proc_desc
= fci
->extra_info
->proc_desc
;
1224 if (proc_desc
== NULL
)
1225 /* I'm not sure how/whether this can happen. Normally when we can't
1226 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1227 and set the saved_regs right away. */
1230 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1231 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1232 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1234 if ( /* In any frame other than the innermost or a frame interrupted by
1235 a signal, we assume that all registers have been saved.
1236 This assumes that all register saves in a function happen before
1237 the first function call. */
1238 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1240 /* In a dummy frame we know exactly where things are saved. */
1241 && !PROC_DESC_IS_DUMMY (proc_desc
)
1243 /* Don't bother unless we are inside a function prologue. Outside the
1244 prologue, we know where everything is. */
1246 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1248 /* Not sure exactly what kernel_trap means, but if it means
1249 the kernel saves the registers without a prologue doing it,
1250 we better not examine the prologue to see whether registers
1251 have been saved yet. */
1254 /* We need to figure out whether the registers that the proc_desc
1255 claims are saved have been saved yet. */
1259 /* Bitmasks; set if we have found a save for the register. */
1260 unsigned long gen_save_found
= 0;
1261 unsigned long float_save_found
= 0;
1264 /* If the address is odd, assume this is MIPS16 code. */
1265 addr
= PROC_LOW_ADDR (proc_desc
);
1266 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1268 /* Scan through this function's instructions preceding the current
1269 PC, and look for those that save registers. */
1270 while (addr
< fci
->pc
)
1272 inst
= mips_fetch_instruction (addr
);
1273 if (pc_is_mips16 (addr
))
1274 mips16_decode_reg_save (inst
, &gen_save_found
);
1276 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1279 gen_mask
= gen_save_found
;
1280 float_mask
= float_save_found
;
1283 /* Fill in the offsets for the registers which gen_mask says
1285 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1286 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1287 if (gen_mask
& 0x80000000)
1289 fci
->saved_regs
[ireg
] = reg_position
;
1290 reg_position
-= MIPS_SAVED_REGSIZE
;
1293 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1294 of that normally used by gcc. Therefore, we have to fetch the first
1295 instruction of the function, and if it's an entry instruction that
1296 saves $s0 or $s1, correct their saved addresses. */
1297 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1299 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1300 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1303 int sreg_count
= (inst
>> 6) & 3;
1305 /* Check if the ra register was pushed on the stack. */
1306 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1308 reg_position
-= MIPS_SAVED_REGSIZE
;
1310 /* Check if the s0 and s1 registers were pushed on the stack. */
1311 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1313 fci
->saved_regs
[reg
] = reg_position
;
1314 reg_position
-= MIPS_SAVED_REGSIZE
;
1319 /* Fill in the offsets for the registers which float_mask says
1321 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1323 /* The freg_offset points to where the first *double* register
1324 is saved. So skip to the high-order word. */
1325 if (!GDB_TARGET_IS_MIPS64
)
1326 reg_position
+= MIPS_SAVED_REGSIZE
;
1328 /* Fill in the offsets for the float registers which float_mask says
1330 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1331 if (float_mask
& 0x80000000)
1333 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1334 reg_position
-= MIPS_SAVED_REGSIZE
;
1337 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1341 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1343 for (; fi
; fi
= fi
->next
)
1345 /* We have to get the saved sp from the sigcontext
1346 if it is a signal handler frame. */
1347 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1351 if (fi
->saved_regs
== NULL
)
1352 mips_find_saved_regs (fi
);
1353 if (fi
->saved_regs
[regno
])
1354 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1357 return read_signed_register (regno
);
1360 /* mips_addr_bits_remove - remove useless address bits */
1363 mips_addr_bits_remove (CORE_ADDR addr
)
1365 if (GDB_TARGET_IS_MIPS64
)
1367 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1369 /* This hack is a work-around for existing boards using
1370 PMON, the simulator, and any other 64-bit targets that
1371 doesn't have true 64-bit addressing. On these targets,
1372 the upper 32 bits of addresses are ignored by the
1373 hardware. Thus, the PC or SP are likely to have been
1374 sign extended to all 1s by instruction sequences that
1375 load 32-bit addresses. For example, a typical piece of
1376 code that loads an address is this:
1377 lui $r2, <upper 16 bits>
1378 ori $r2, <lower 16 bits>
1379 But the lui sign-extends the value such that the upper 32
1380 bits may be all 1s. The workaround is simply to mask off
1381 these bits. In the future, gcc may be changed to support
1382 true 64-bit addressing, and this masking will have to be
1384 addr
&= (CORE_ADDR
) 0xffffffff;
1387 else if (mips_mask_address_p ())
1389 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1390 masking off bits, instead, the actual target should be asking
1391 for the address to be converted to a valid pointer. */
1392 /* Even when GDB is configured for some 32-bit targets
1393 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1394 so CORE_ADDR is 64 bits. So we still have to mask off
1395 useless bits from addresses. */
1396 addr
&= (CORE_ADDR
) 0xffffffff;
1401 /* mips_software_single_step() is called just before we want to resume
1402 the inferior, if we want to single-step it but there is no hardware
1403 or kernel single-step support (MIPS on GNU/Linux for example). We find
1404 the target of the coming instruction and breakpoint it.
1406 single_step is also called just after the inferior stops. If we had
1407 set up a simulated single-step, we undo our damage. */
1410 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1412 static CORE_ADDR next_pc
;
1413 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1414 static binsn_quantum break_mem
;
1417 if (insert_breakpoints_p
)
1419 pc
= read_register (PC_REGNUM
);
1420 next_pc
= mips_next_pc (pc
);
1422 target_insert_breakpoint (next_pc
, break_mem
);
1425 target_remove_breakpoint (next_pc
, break_mem
);
1429 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1433 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1434 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1435 tmp
= mips_skip_stub (pc
);
1436 prev
->pc
= tmp
? tmp
: pc
;
1441 mips_frame_saved_pc (struct frame_info
*frame
)
1444 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1445 /* We have to get the saved pc from the sigcontext
1446 if it is a signal handler frame. */
1447 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1448 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1450 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1451 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1453 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1455 return ADDR_BITS_REMOVE (saved_pc
);
1458 static struct mips_extra_func_info temp_proc_desc
;
1459 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1461 /* Set a register's saved stack address in temp_saved_regs. If an address
1462 has already been set for this register, do nothing; this way we will
1463 only recognize the first save of a given register in a function prologue.
1464 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1467 set_reg_offset (int regno
, CORE_ADDR offset
)
1469 if (temp_saved_regs
[regno
] == 0)
1470 temp_saved_regs
[regno
] = offset
;
1474 /* Test whether the PC points to the return instruction at the
1475 end of a function. */
1478 mips_about_to_return (CORE_ADDR pc
)
1480 if (pc_is_mips16 (pc
))
1481 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1482 generates a "jr $ra"; other times it generates code to load
1483 the return address from the stack to an accessible register (such
1484 as $a3), then a "jr" using that register. This second case
1485 is almost impossible to distinguish from an indirect jump
1486 used for switch statements, so we don't even try. */
1487 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1489 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1493 /* This fencepost looks highly suspicious to me. Removing it also
1494 seems suspicious as it could affect remote debugging across serial
1498 heuristic_proc_start (CORE_ADDR pc
)
1505 pc
= ADDR_BITS_REMOVE (pc
);
1507 fence
= start_pc
- heuristic_fence_post
;
1511 if (heuristic_fence_post
== UINT_MAX
1512 || fence
< VM_MIN_ADDRESS
)
1513 fence
= VM_MIN_ADDRESS
;
1515 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1517 /* search back for previous return */
1518 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1519 if (start_pc
< fence
)
1521 /* It's not clear to me why we reach this point when
1522 stop_soon_quietly, but with this test, at least we
1523 don't print out warnings for every child forked (eg, on
1524 decstation). 22apr93 rich@cygnus.com. */
1525 if (!stop_soon_quietly
)
1527 static int blurb_printed
= 0;
1529 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1534 /* This actually happens frequently in embedded
1535 development, when you first connect to a board
1536 and your stack pointer and pc are nowhere in
1537 particular. This message needs to give people
1538 in that situation enough information to
1539 determine that it's no big deal. */
1540 printf_filtered ("\n\
1541 GDB is unable to find the start of the function at 0x%s\n\
1542 and thus can't determine the size of that function's stack frame.\n\
1543 This means that GDB may be unable to access that stack frame, or\n\
1544 the frames below it.\n\
1545 This problem is most likely caused by an invalid program counter or\n\
1547 However, if you think GDB should simply search farther back\n\
1548 from 0x%s for code which looks like the beginning of a\n\
1549 function, you can increase the range of the search using the `set\n\
1550 heuristic-fence-post' command.\n",
1551 paddr_nz (pc
), paddr_nz (pc
));
1558 else if (pc_is_mips16 (start_pc
))
1560 unsigned short inst
;
1562 /* On MIPS16, any one of the following is likely to be the
1563 start of a function:
1567 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1568 inst
= mips_fetch_instruction (start_pc
);
1569 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1570 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1571 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1572 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1574 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1575 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1580 else if (mips_about_to_return (start_pc
))
1582 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1589 /* Fetch the immediate value from a MIPS16 instruction.
1590 If the previous instruction was an EXTEND, use it to extend
1591 the upper bits of the immediate value. This is a helper function
1592 for mips16_heuristic_proc_desc. */
1595 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1596 unsigned short inst
, /* current instruction */
1597 int nbits
, /* number of bits in imm field */
1598 int scale
, /* scale factor to be applied to imm */
1599 int is_signed
) /* is the imm field signed? */
1603 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1605 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1606 if (offset
& 0x8000) /* check for negative extend */
1607 offset
= 0 - (0x10000 - (offset
& 0xffff));
1608 return offset
| (inst
& 0x1f);
1612 int max_imm
= 1 << nbits
;
1613 int mask
= max_imm
- 1;
1614 int sign_bit
= max_imm
>> 1;
1616 offset
= inst
& mask
;
1617 if (is_signed
&& (offset
& sign_bit
))
1618 offset
= 0 - (max_imm
- offset
);
1619 return offset
* scale
;
1624 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1625 stream from start_pc to limit_pc. */
1628 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1629 struct frame_info
*next_frame
, CORE_ADDR sp
)
1632 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1633 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1634 unsigned inst
= 0; /* current instruction */
1635 unsigned entry_inst
= 0; /* the entry instruction */
1638 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1639 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1641 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1643 /* Save the previous instruction. If it's an EXTEND, we'll extract
1644 the immediate offset extension from it in mips16_get_imm. */
1647 /* Fetch and decode the instruction. */
1648 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1649 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1650 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1652 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1653 if (offset
< 0) /* negative stack adjustment? */
1654 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1656 /* Exit loop if a positive stack adjustment is found, which
1657 usually means that the stack cleanup code in the function
1658 epilogue is reached. */
1661 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1663 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1664 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1665 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1666 set_reg_offset (reg
, sp
+ offset
);
1668 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1670 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1671 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1672 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1673 set_reg_offset (reg
, sp
+ offset
);
1675 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1677 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1678 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1679 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1681 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1683 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1684 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1685 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1687 else if (inst
== 0x673d) /* move $s1, $sp */
1690 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1692 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1694 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1695 frame_addr
= sp
+ offset
;
1696 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1697 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1699 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1701 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1702 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1703 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1704 set_reg_offset (reg
, frame_addr
+ offset
);
1706 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1708 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1709 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1710 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1711 set_reg_offset (reg
, frame_addr
+ offset
);
1713 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1714 entry_inst
= inst
; /* save for later processing */
1715 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1716 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1719 /* The entry instruction is typically the first instruction in a function,
1720 and it stores registers at offsets relative to the value of the old SP
1721 (before the prologue). But the value of the sp parameter to this
1722 function is the new SP (after the prologue has been executed). So we
1723 can't calculate those offsets until we've seen the entire prologue,
1724 and can calculate what the old SP must have been. */
1725 if (entry_inst
!= 0)
1727 int areg_count
= (entry_inst
>> 8) & 7;
1728 int sreg_count
= (entry_inst
>> 6) & 3;
1730 /* The entry instruction always subtracts 32 from the SP. */
1731 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1733 /* Now we can calculate what the SP must have been at the
1734 start of the function prologue. */
1735 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1737 /* Check if a0-a3 were saved in the caller's argument save area. */
1738 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1740 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1741 set_reg_offset (reg
, sp
+ offset
);
1742 offset
+= MIPS_SAVED_REGSIZE
;
1745 /* Check if the ra register was pushed on the stack. */
1747 if (entry_inst
& 0x20)
1749 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1750 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1751 offset
-= MIPS_SAVED_REGSIZE
;
1754 /* Check if the s0 and s1 registers were pushed on the stack. */
1755 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1757 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1758 set_reg_offset (reg
, sp
+ offset
);
1759 offset
-= MIPS_SAVED_REGSIZE
;
1765 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1766 struct frame_info
*next_frame
, CORE_ADDR sp
)
1769 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1771 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1772 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1773 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1774 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1776 unsigned long inst
, high_word
, low_word
;
1779 /* Fetch the instruction. */
1780 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1782 /* Save some code by pre-extracting some useful fields. */
1783 high_word
= (inst
>> 16) & 0xffff;
1784 low_word
= inst
& 0xffff;
1785 reg
= high_word
& 0x1f;
1787 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1788 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1789 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1791 if (low_word
& 0x8000) /* negative stack adjustment? */
1792 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1794 /* Exit loop if a positive stack adjustment is found, which
1795 usually means that the stack cleanup code in the function
1796 epilogue is reached. */
1799 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1801 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1802 set_reg_offset (reg
, sp
+ low_word
);
1804 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1806 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1807 but the register size used is only 32 bits. Make the address
1808 for the saved register point to the lower 32 bits. */
1809 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1810 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1812 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1814 /* Old gcc frame, r30 is virtual frame pointer. */
1815 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1816 frame_addr
= sp
+ low_word
;
1817 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1819 unsigned alloca_adjust
;
1820 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1821 frame_addr
= read_next_frame_reg (next_frame
, 30);
1822 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1823 if (alloca_adjust
> 0)
1825 /* FP > SP + frame_size. This may be because
1826 * of an alloca or somethings similar.
1827 * Fix sp to "pre-alloca" value, and try again.
1829 sp
+= alloca_adjust
;
1834 /* move $30,$sp. With different versions of gas this will be either
1835 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1836 Accept any one of these. */
1837 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1839 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1840 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1842 unsigned alloca_adjust
;
1843 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1844 frame_addr
= read_next_frame_reg (next_frame
, 30);
1845 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1846 if (alloca_adjust
> 0)
1848 /* FP > SP + frame_size. This may be because
1849 * of an alloca or somethings similar.
1850 * Fix sp to "pre-alloca" value, and try again.
1852 sp
+= alloca_adjust
;
1857 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1859 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1860 set_reg_offset (reg
, frame_addr
+ low_word
);
1865 static mips_extra_func_info_t
1866 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1867 struct frame_info
*next_frame
, int cur_frame
)
1872 sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1878 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1879 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1880 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1881 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1882 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1884 if (start_pc
+ 200 < limit_pc
)
1885 limit_pc
= start_pc
+ 200;
1886 if (pc_is_mips16 (start_pc
))
1887 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1889 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1890 return &temp_proc_desc
;
1893 struct mips_objfile_private
1899 /* Global used to communicate between non_heuristic_proc_desc and
1900 compare_pdr_entries within qsort (). */
1901 static bfd
*the_bfd
;
1904 compare_pdr_entries (const void *a
, const void *b
)
1906 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
1907 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
1911 else if (lhs
== rhs
)
1917 static mips_extra_func_info_t
1918 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
1920 CORE_ADDR startaddr
;
1921 mips_extra_func_info_t proc_desc
;
1922 struct block
*b
= block_for_pc (pc
);
1924 struct obj_section
*sec
;
1925 struct mips_objfile_private
*priv
;
1927 if (PC_IN_CALL_DUMMY (pc
, 0, 0))
1930 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1932 *addrptr
= startaddr
;
1936 sec
= find_pc_section (pc
);
1939 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
1941 /* Search the ".pdr" section generated by GAS. This includes most of
1942 the information normally found in ECOFF PDRs. */
1944 the_bfd
= sec
->objfile
->obfd
;
1946 && (the_bfd
->format
== bfd_object
1947 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
1948 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
1950 /* Right now GAS only outputs the address as a four-byte sequence.
1951 This means that we should not bother with this method on 64-bit
1952 targets (until that is fixed). */
1954 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
1955 sizeof (struct mips_objfile_private
));
1957 sec
->objfile
->obj_private
= priv
;
1959 else if (priv
== NULL
)
1963 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
1964 sizeof (struct mips_objfile_private
));
1966 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
1969 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
1970 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
1972 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
1973 priv
->contents
, 0, priv
->size
);
1975 /* In general, the .pdr section is sorted. However, in the
1976 presence of multiple code sections (and other corner cases)
1977 it can become unsorted. Sort it so that we can use a faster
1979 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
1984 sec
->objfile
->obj_private
= priv
;
1988 if (priv
->size
!= 0)
1994 high
= priv
->size
/ 32;
2000 mid
= (low
+ high
) / 2;
2002 ptr
= priv
->contents
+ mid
* 32;
2003 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2004 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2005 SECT_OFF_TEXT (sec
->objfile
));
2006 if (pdr_pc
== startaddr
)
2008 if (pdr_pc
> startaddr
)
2013 while (low
!= high
);
2017 struct symbol
*sym
= find_pc_function (pc
);
2019 /* Fill in what we need of the proc_desc. */
2020 proc_desc
= (mips_extra_func_info_t
)
2021 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2022 sizeof (struct mips_extra_func_info
));
2023 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2025 /* Only used for dummy frames. */
2026 PROC_HIGH_ADDR (proc_desc
) = 0;
2028 PROC_FRAME_OFFSET (proc_desc
)
2029 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2030 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2032 PROC_FRAME_ADJUST (proc_desc
) = 0;
2033 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2035 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2037 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2039 PROC_FREG_OFFSET (proc_desc
)
2040 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2041 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2043 proc_desc
->pdr
.isym
= (long) sym
;
2053 if (startaddr
> BLOCK_START (b
))
2055 /* This is the "pathological" case referred to in a comment in
2056 print_frame_info. It might be better to move this check into
2061 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
2063 /* If we never found a PDR for this function in symbol reading, then
2064 examine prologues to find the information. */
2067 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2068 if (PROC_FRAME_REG (proc_desc
) == -1)
2078 static mips_extra_func_info_t
2079 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2081 mips_extra_func_info_t proc_desc
;
2082 CORE_ADDR startaddr
;
2084 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2088 /* IF this is the topmost frame AND
2089 * (this proc does not have debugging information OR
2090 * the PC is in the procedure prologue)
2091 * THEN create a "heuristic" proc_desc (by analyzing
2092 * the actual code) to replace the "official" proc_desc.
2094 if (next_frame
== NULL
)
2096 struct symtab_and_line val
;
2097 struct symbol
*proc_symbol
=
2098 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2102 val
= find_pc_line (BLOCK_START
2103 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2105 val
.pc
= val
.end
? val
.end
: pc
;
2107 if (!proc_symbol
|| pc
< val
.pc
)
2109 mips_extra_func_info_t found_heuristic
=
2110 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2111 pc
, next_frame
, cur_frame
);
2112 if (found_heuristic
)
2113 proc_desc
= found_heuristic
;
2119 /* Is linked_proc_desc_table really necessary? It only seems to be used
2120 by procedure call dummys. However, the procedures being called ought
2121 to have their own proc_descs, and even if they don't,
2122 heuristic_proc_desc knows how to create them! */
2124 register struct linked_proc_info
*link
;
2126 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2127 if (PROC_LOW_ADDR (&link
->info
) <= pc
2128 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2132 startaddr
= heuristic_proc_start (pc
);
2135 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2141 get_frame_pointer (struct frame_info
*frame
,
2142 mips_extra_func_info_t proc_desc
)
2144 return ADDR_BITS_REMOVE (
2145 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
2146 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2149 mips_extra_func_info_t cached_proc_desc
;
2152 mips_frame_chain (struct frame_info
*frame
)
2154 mips_extra_func_info_t proc_desc
;
2156 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
2158 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
2161 /* Check if the PC is inside a call stub. If it is, fetch the
2162 PC of the caller of that stub. */
2163 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
2166 /* Look up the procedure descriptor for this PC. */
2167 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2171 cached_proc_desc
= proc_desc
;
2173 /* If no frame pointer and frame size is zero, we must be at end
2174 of stack (or otherwise hosed). If we don't check frame size,
2175 we loop forever if we see a zero size frame. */
2176 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2177 && PROC_FRAME_OFFSET (proc_desc
) == 0
2178 /* The previous frame from a sigtramp frame might be frameless
2179 and have frame size zero. */
2180 && !frame
->signal_handler_caller
)
2183 return get_frame_pointer (frame
, proc_desc
);
2187 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2191 /* Use proc_desc calculated in frame_chain */
2192 mips_extra_func_info_t proc_desc
=
2193 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
, 1);
2195 fci
->extra_info
= (struct frame_extra_info
*)
2196 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2198 fci
->saved_regs
= NULL
;
2199 fci
->extra_info
->proc_desc
=
2200 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2203 /* Fixup frame-pointer - only needed for top frame */
2204 /* This may not be quite right, if proc has a real frame register.
2205 Get the value of the frame relative sp, procedure might have been
2206 interrupted by a signal at it's very start. */
2207 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2208 && !PROC_DESC_IS_DUMMY (proc_desc
))
2209 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2211 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2213 if (proc_desc
== &temp_proc_desc
)
2217 /* Do not set the saved registers for a sigtramp frame,
2218 mips_find_saved_registers will do that for us.
2219 We can't use fci->signal_handler_caller, it is not yet set. */
2220 find_pc_partial_function (fci
->pc
, &name
,
2221 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2222 if (!PC_IN_SIGTRAMP (fci
->pc
, name
))
2224 frame_saved_regs_zalloc (fci
);
2225 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2226 fci
->saved_regs
[PC_REGNUM
]
2227 = fci
->saved_regs
[RA_REGNUM
];
2231 /* hack: if argument regs are saved, guess these contain args */
2232 /* assume we can't tell how many args for now */
2233 fci
->extra_info
->num_args
= -1;
2234 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2236 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2238 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2245 /* MIPS stack frames are almost impenetrable. When execution stops,
2246 we basically have to look at symbol information for the function
2247 that we stopped in, which tells us *which* register (if any) is
2248 the base of the frame pointer, and what offset from that register
2249 the frame itself is at.
2251 This presents a problem when trying to examine a stack in memory
2252 (that isn't executing at the moment), using the "frame" command. We
2253 don't have a PC, nor do we have any registers except SP.
2255 This routine takes two arguments, SP and PC, and tries to make the
2256 cached frames look as if these two arguments defined a frame on the
2257 cache. This allows the rest of info frame to extract the important
2258 arguments without difficulty. */
2261 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2264 error ("MIPS frame specifications require two arguments: sp and pc");
2266 return create_new_frame (argv
[0], argv
[1]);
2269 /* According to the current ABI, should the type be passed in a
2270 floating-point register (assuming that there is space)? When there
2271 is no FPU, FP are not even considered as possibile candidates for
2272 FP registers and, consequently this returns false - forces FP
2273 arguments into integer registers. */
2276 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2278 return ((typecode
== TYPE_CODE_FLT
2280 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2281 && TYPE_NFIELDS (arg_type
) == 1
2282 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2283 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2286 /* On o32, argument passing in GPRs depends on the alignment of the type being
2287 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2290 mips_type_needs_double_align (struct type
*type
)
2292 enum type_code typecode
= TYPE_CODE (type
);
2294 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2296 else if (typecode
== TYPE_CODE_STRUCT
)
2298 if (TYPE_NFIELDS (type
) < 1)
2300 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2302 else if (typecode
== TYPE_CODE_UNION
)
2306 n
= TYPE_NFIELDS (type
);
2307 for (i
= 0; i
< n
; i
++)
2308 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2316 mips_push_arguments (int nargs
,
2317 struct value
**args
,
2320 CORE_ADDR struct_addr
)
2326 int stack_offset
= 0;
2328 /* Macros to round N up or down to the next A boundary; A must be
2330 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2331 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2333 /* First ensure that the stack and structure return address (if any)
2334 are properly aligned. The stack has to be at least 64-bit aligned
2335 even on 32-bit machines, because doubles must be 64-bit aligned.
2336 On at least one MIPS variant, stack frames need to be 128-bit
2337 aligned, so we round to this widest known alignment. */
2338 sp
= ROUND_DOWN (sp
, 16);
2339 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2341 /* Now make space on the stack for the args. We allocate more
2342 than necessary for EABI, because the first few arguments are
2343 passed in registers, but that's OK. */
2344 for (argnum
= 0; argnum
< nargs
; argnum
++)
2345 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_STACK_ARGSIZE
);
2346 sp
-= ROUND_UP (len
, 16);
2349 fprintf_unfiltered (gdb_stdlog
, "mips_push_arguments: sp=0x%lx allocated %d\n",
2350 (long) sp
, ROUND_UP (len
, 16));
2352 /* Initialize the integer and float register pointers. */
2354 float_argreg
= FPA0_REGNUM
;
2356 /* the struct_return pointer occupies the first parameter-passing reg */
2360 fprintf_unfiltered (gdb_stdlog
,
2361 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2362 argreg
, (long) struct_addr
);
2363 write_register (argreg
++, struct_addr
);
2364 if (MIPS_REGS_HAVE_HOME_P
)
2365 stack_offset
+= MIPS_STACK_ARGSIZE
;
2368 /* Now load as many as possible of the first arguments into
2369 registers, and push the rest onto the stack. Loop thru args
2370 from first to last. */
2371 for (argnum
= 0; argnum
< nargs
; argnum
++)
2374 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2375 struct value
*arg
= args
[argnum
];
2376 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2377 int len
= TYPE_LENGTH (arg_type
);
2378 enum type_code typecode
= TYPE_CODE (arg_type
);
2381 fprintf_unfiltered (gdb_stdlog
,
2382 "mips_push_arguments: %d len=%d type=%d",
2383 argnum
+ 1, len
, (int) typecode
);
2385 /* The EABI passes structures that do not fit in a register by
2386 reference. In all other cases, pass the structure by value. */
2388 && len
> MIPS_SAVED_REGSIZE
2389 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2391 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2392 typecode
= TYPE_CODE_PTR
;
2393 len
= MIPS_SAVED_REGSIZE
;
2396 fprintf_unfiltered (gdb_stdlog
, " push");
2399 val
= (char *) VALUE_CONTENTS (arg
);
2401 /* 32-bit ABIs always start floating point arguments in an
2402 even-numbered floating point register. Round the FP register
2403 up before the check to see if there are any FP registers
2404 left. Non MIPS_EABI targets also pass the FP in the integer
2405 registers so also round up normal registers. */
2406 if (!FP_REGISTER_DOUBLE
2407 && fp_register_arg_p (typecode
, arg_type
))
2409 if ((float_argreg
& 1))
2413 /* Floating point arguments passed in registers have to be
2414 treated specially. On 32-bit architectures, doubles
2415 are passed in register pairs; the even register gets
2416 the low word, and the odd register gets the high word.
2417 On non-EABI processors, the first two floating point arguments are
2418 also copied to general registers, because MIPS16 functions
2419 don't use float registers for arguments. This duplication of
2420 arguments in general registers can't hurt non-MIPS16 functions
2421 because those registers are normally skipped. */
2422 /* MIPS_EABI squeezes a struct that contains a single floating
2423 point value into an FP register instead of pushing it onto the
2425 if (fp_register_arg_p (typecode
, arg_type
)
2426 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2428 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2430 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2431 unsigned long regval
;
2433 /* Write the low word of the double to the even register(s). */
2434 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2436 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2437 float_argreg
, phex (regval
, 4));
2438 write_register (float_argreg
++, regval
);
2442 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2443 argreg
, phex (regval
, 4));
2444 write_register (argreg
++, regval
);
2447 /* Write the high word of the double to the odd register(s). */
2448 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2450 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2451 float_argreg
, phex (regval
, 4));
2452 write_register (float_argreg
++, regval
);
2456 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2457 argreg
, phex (regval
, 4));
2458 write_register (argreg
++, regval
);
2464 /* This is a floating point value that fits entirely
2465 in a single register. */
2466 /* On 32 bit ABI's the float_argreg is further adjusted
2467 above to ensure that it is even register aligned. */
2468 LONGEST regval
= extract_unsigned_integer (val
, len
);
2470 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2471 float_argreg
, phex (regval
, len
));
2472 write_register (float_argreg
++, regval
);
2475 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2476 registers for each argument. The below is (my
2477 guess) to ensure that the corresponding integer
2478 register has reserved the same space. */
2480 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2481 argreg
, phex (regval
, len
));
2482 write_register (argreg
, regval
);
2483 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2486 /* Reserve space for the FP register. */
2487 if (MIPS_REGS_HAVE_HOME_P
)
2488 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
2492 /* Copy the argument to general registers or the stack in
2493 register-sized pieces. Large arguments are split between
2494 registers and stack. */
2495 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2496 are treated specially: Irix cc passes them in registers
2497 where gcc sometimes puts them on the stack. For maximum
2498 compatibility, we will put them in both places. */
2499 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2500 (len
% MIPS_SAVED_REGSIZE
!= 0));
2501 /* Structures should be aligned to eight bytes (even arg registers)
2502 on MIPS_ABI_O32 if their first member has double precision. */
2503 if (gdbarch_tdep (current_gdbarch
)->mips_abi
== MIPS_ABI_O32
2504 && mips_type_needs_double_align (arg_type
))
2509 /* Note: Floating-point values that didn't fit into an FP
2510 register are only written to memory. */
2513 /* Rememer if the argument was written to the stack. */
2514 int stack_used_p
= 0;
2515 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2518 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2521 /* Write this portion of the argument to the stack. */
2522 if (argreg
> MIPS_LAST_ARG_REGNUM
2524 || fp_register_arg_p (typecode
, arg_type
))
2526 /* Should shorter than int integer values be
2527 promoted to int before being stored? */
2528 int longword_offset
= 0;
2531 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2533 if (MIPS_STACK_ARGSIZE
== 8 &&
2534 (typecode
== TYPE_CODE_INT
||
2535 typecode
== TYPE_CODE_PTR
||
2536 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2537 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2538 else if ((typecode
== TYPE_CODE_STRUCT
||
2539 typecode
== TYPE_CODE_UNION
) &&
2540 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2541 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2546 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%lx",
2547 (long) stack_offset
);
2548 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%lx",
2549 (long) longword_offset
);
2552 addr
= sp
+ stack_offset
+ longword_offset
;
2557 fprintf_unfiltered (gdb_stdlog
, " @0x%lx ", (long) addr
);
2558 for (i
= 0; i
< partial_len
; i
++)
2560 fprintf_unfiltered (gdb_stdlog
, "%02x", val
[i
] & 0xff);
2563 write_memory (addr
, val
, partial_len
);
2566 /* Note!!! This is NOT an else clause. Odd sized
2567 structs may go thru BOTH paths. Floating point
2568 arguments will not. */
2569 /* Write this portion of the argument to a general
2570 purpose register. */
2571 if (argreg
<= MIPS_LAST_ARG_REGNUM
2572 && !fp_register_arg_p (typecode
, arg_type
))
2574 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2576 /* A non-floating-point argument being passed in a
2577 general register. If a struct or union, and if
2578 the remaining length is smaller than the register
2579 size, we have to adjust the register value on
2582 It does not seem to be necessary to do the
2583 same for integral types.
2585 Also don't do this adjustment on EABI and O64
2588 cagney/2001-07-23: gdb/179: Also, GCC, when
2589 outputting LE O32 with sizeof (struct) <
2590 MIPS_SAVED_REGSIZE, generates a left shift as
2591 part of storing the argument in a register a
2592 register (the left shift isn't generated when
2593 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
2594 is quite possible that this is GCC contradicting
2595 the LE/O32 ABI, GDB has not been adjusted to
2596 accommodate this. Either someone needs to
2597 demonstrate that the LE/O32 ABI specifies such a
2598 left shift OR this new ABI gets identified as
2599 such and GDB gets tweaked accordingly. */
2602 && MIPS_SAVED_REGSIZE
< 8
2603 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2604 && partial_len
< MIPS_SAVED_REGSIZE
2605 && (typecode
== TYPE_CODE_STRUCT
||
2606 typecode
== TYPE_CODE_UNION
))
2607 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2611 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2613 phex (regval
, MIPS_SAVED_REGSIZE
));
2614 write_register (argreg
, regval
);
2617 /* If this is the old ABI, prevent subsequent floating
2618 point arguments from being passed in floating point
2621 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2627 /* Compute the the offset into the stack at which we
2628 will copy the next parameter.
2630 In older ABIs, the caller reserved space for
2631 registers that contained arguments. This was loosely
2632 refered to as their "home". Consequently, space is
2635 In the new EABI (and the NABI32), the stack_offset
2636 only needs to be adjusted when it has been used.. */
2638 if (MIPS_REGS_HAVE_HOME_P
|| stack_used_p
)
2639 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2643 fprintf_unfiltered (gdb_stdlog
, "\n");
2646 /* Return adjusted stack pointer. */
2651 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2653 /* Set the return address register to point to the entry
2654 point of the program, where a breakpoint lies in wait. */
2655 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2660 mips_push_register (CORE_ADDR
* sp
, int regno
)
2662 char buffer
[MAX_REGISTER_RAW_SIZE
];
2665 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2667 regsize
= MIPS_SAVED_REGSIZE
;
2668 offset
= (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2669 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2674 regsize
= REGISTER_RAW_SIZE (regno
);
2678 read_register_gen (regno
, buffer
);
2679 write_memory (*sp
, buffer
+ offset
, regsize
);
2682 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2683 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2686 mips_push_dummy_frame (void)
2689 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2690 xmalloc (sizeof (struct linked_proc_info
));
2691 mips_extra_func_info_t proc_desc
= &link
->info
;
2692 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
2693 CORE_ADDR old_sp
= sp
;
2694 link
->next
= linked_proc_desc_table
;
2695 linked_proc_desc_table
= link
;
2697 /* FIXME! are these correct ? */
2698 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2699 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2700 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2701 #define FLOAT_SINGLE_REG_SAVE_MASK \
2702 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2704 * The registers we must save are all those not preserved across
2705 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2706 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2707 * and FP Control/Status registers.
2710 * Dummy frame layout:
2713 * Saved MMHI, MMLO, FPC_CSR
2718 * Saved D18 (i.e. F19, F18)
2720 * Saved D0 (i.e. F1, F0)
2721 * Argument build area and stack arguments written via mips_push_arguments
2725 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2726 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2727 PROC_FRAME_OFFSET (proc_desc
) = 0;
2728 PROC_FRAME_ADJUST (proc_desc
) = 0;
2729 mips_push_register (&sp
, PC_REGNUM
);
2730 mips_push_register (&sp
, HI_REGNUM
);
2731 mips_push_register (&sp
, LO_REGNUM
);
2732 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2734 /* Save general CPU registers */
2735 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2736 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2737 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2738 for (ireg
= 32; --ireg
>= 0;)
2739 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2740 mips_push_register (&sp
, ireg
);
2742 /* Save floating point registers starting with high order word */
2743 PROC_FREG_MASK (proc_desc
) =
2744 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2745 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2746 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2748 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2749 for (ireg
= 32; --ireg
>= 0;)
2750 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2751 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2753 /* Update the frame pointer for the call dummy and the stack pointer.
2754 Set the procedure's starting and ending addresses to point to the
2755 call dummy address at the entry point. */
2756 write_register (PUSH_FP_REGNUM
, old_sp
);
2757 write_register (SP_REGNUM
, sp
);
2758 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2759 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2760 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2761 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2765 mips_pop_frame (void)
2767 register int regnum
;
2768 struct frame_info
*frame
= get_current_frame ();
2769 CORE_ADDR new_sp
= FRAME_FP (frame
);
2771 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2773 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2774 if (frame
->saved_regs
== NULL
)
2775 mips_find_saved_regs (frame
);
2776 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2778 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2779 && frame
->saved_regs
[regnum
])
2780 write_register (regnum
,
2781 read_memory_integer (frame
->saved_regs
[regnum
],
2782 MIPS_SAVED_REGSIZE
));
2784 write_register (SP_REGNUM
, new_sp
);
2785 flush_cached_frames ();
2787 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2789 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2791 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2793 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2795 if (&pi_ptr
->info
== proc_desc
)
2800 error ("Can't locate dummy extra frame info\n");
2802 if (prev_ptr
!= NULL
)
2803 prev_ptr
->next
= pi_ptr
->next
;
2805 linked_proc_desc_table
= pi_ptr
->next
;
2809 write_register (HI_REGNUM
,
2810 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2811 MIPS_SAVED_REGSIZE
));
2812 write_register (LO_REGNUM
,
2813 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2814 MIPS_SAVED_REGSIZE
));
2815 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2816 write_register (FCRCS_REGNUM
,
2817 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2818 MIPS_SAVED_REGSIZE
));
2822 /* Floating point register management.
2824 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
2825 64bit operations, these early MIPS cpus treat fp register pairs
2826 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
2827 registers and offer a compatibility mode that emulates the MIPS2 fp
2828 model. When operating in MIPS2 fp compat mode, later cpu's split
2829 double precision floats into two 32-bit chunks and store them in
2830 consecutive fp regs. To display 64-bit floats stored in this
2831 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
2832 Throw in user-configurable endianness and you have a real mess.
2834 The way this works is:
2835 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
2836 double-precision value will be split across two logical registers.
2837 The lower-numbered logical register will hold the low-order bits,
2838 regardless of the processor's endianness.
2839 - If we are on a 64-bit processor, and we are looking for a
2840 single-precision value, it will be in the low ordered bits
2841 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
2842 save slot in memory.
2843 - If we are in 64-bit mode, everything is straightforward.
2845 Note that this code only deals with "live" registers at the top of the
2846 stack. We will attempt to deal with saved registers later, when
2847 the raw/cooked register interface is in place. (We need a general
2848 interface that can deal with dynamic saved register sizes -- fp
2849 regs could be 32 bits wide in one frame and 64 on the frame above
2852 static struct type
*
2853 mips_float_register_type (void)
2855 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2856 return builtin_type_ieee_single_big
;
2858 return builtin_type_ieee_single_little
;
2861 static struct type
*
2862 mips_double_register_type (void)
2864 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2865 return builtin_type_ieee_double_big
;
2867 return builtin_type_ieee_double_little
;
2870 /* Copy a 32-bit single-precision value from the current frame
2871 into rare_buffer. */
2874 mips_read_fp_register_single (int regno
, char *rare_buffer
)
2876 int raw_size
= REGISTER_RAW_SIZE (regno
);
2877 char *raw_buffer
= alloca (raw_size
);
2879 if (!frame_register_read (selected_frame
, regno
, raw_buffer
))
2880 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
2883 /* We have a 64-bit value for this register. Find the low-order
2887 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2892 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
2896 memcpy (rare_buffer
, raw_buffer
, 4);
2900 /* Copy a 64-bit double-precision value from the current frame into
2901 rare_buffer. This may include getting half of it from the next
2905 mips_read_fp_register_double (int regno
, char *rare_buffer
)
2907 int raw_size
= REGISTER_RAW_SIZE (regno
);
2909 if (raw_size
== 8 && !mips2_fp_compat ())
2911 /* We have a 64-bit value for this register, and we should use
2913 if (!frame_register_read (selected_frame
, regno
, rare_buffer
))
2914 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
2918 if ((regno
- FP0_REGNUM
) & 1)
2919 internal_error (__FILE__
, __LINE__
,
2920 "mips_read_fp_register_double: bad access to "
2921 "odd-numbered FP register");
2923 /* mips_read_fp_register_single will find the correct 32 bits from
2925 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2927 mips_read_fp_register_single (regno
, rare_buffer
+ 4);
2928 mips_read_fp_register_single (regno
+ 1, rare_buffer
);
2932 mips_read_fp_register_single (regno
, rare_buffer
);
2933 mips_read_fp_register_single (regno
+ 1, rare_buffer
+ 4);
2939 mips_print_register (int regnum
, int all
)
2941 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2943 /* Get the data in raw format. */
2944 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
2946 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2950 /* If we have a actual 32-bit floating point register (or we are in
2951 32-bit compatibility mode), and the register is even-numbered,
2952 also print it as a double (spanning two registers). */
2953 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2954 && (REGISTER_RAW_SIZE (regnum
) == 4
2955 || mips2_fp_compat ())
2956 && !((regnum
- FP0_REGNUM
) & 1))
2958 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2960 mips_read_fp_register_double (regnum
, dbuffer
);
2962 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2963 val_print (mips_double_register_type (), dbuffer
, 0, 0,
2964 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2965 printf_filtered ("); ");
2967 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2969 /* The problem with printing numeric register names (r26, etc.) is that
2970 the user can't use them on input. Probably the best solution is to
2971 fix it so that either the numeric or the funky (a2, etc.) names
2972 are accepted on input. */
2973 if (regnum
< MIPS_NUMREGS
)
2974 printf_filtered ("(r%d): ", regnum
);
2976 printf_filtered (": ");
2978 /* If virtual format is floating, print it that way. */
2979 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2980 if (REGISTER_RAW_SIZE (regnum
) == 8 && !mips2_fp_compat ())
2982 /* We have a meaningful 64-bit value in this register. Show
2983 it as a 32-bit float and a 64-bit double. */
2984 int offset
= 4 * (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
);
2986 printf_filtered (" (float) ");
2987 val_print (mips_float_register_type (), raw_buffer
+ offset
, 0, 0,
2988 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2989 printf_filtered (", (double) ");
2990 val_print (mips_double_register_type (), raw_buffer
, 0, 0,
2991 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2994 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2995 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2996 /* Else print as integer in hex. */
3001 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3002 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3006 print_scalar_formatted (raw_buffer
+ offset
,
3007 REGISTER_VIRTUAL_TYPE (regnum
),
3008 'x', 0, gdb_stdout
);
3012 /* Replacement for generic do_registers_info.
3013 Print regs in pretty columns. */
3016 do_fp_register_row (int regnum
)
3017 { /* do values for FP (float) regs */
3019 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
3020 int inv1
, inv2
, inv3
;
3022 raw_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
3024 if (REGISTER_RAW_SIZE (regnum
) == 4 || mips2_fp_compat ())
3026 /* 4-byte registers: we can fit two registers per row. */
3027 /* Also print every pair of 4-byte regs as an 8-byte double. */
3028 mips_read_fp_register_single (regnum
, raw_buffer
);
3029 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3031 mips_read_fp_register_single (regnum
+ 1, raw_buffer
);
3032 flt2
= unpack_double (mips_float_register_type (), raw_buffer
, &inv2
);
3034 mips_read_fp_register_double (regnum
, raw_buffer
);
3035 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
3037 printf_filtered (" %-5s", REGISTER_NAME (regnum
));
3039 printf_filtered (": <invalid float>");
3041 printf_filtered ("%-17.9g", flt1
);
3043 printf_filtered (" %-5s", REGISTER_NAME (regnum
+ 1));
3045 printf_filtered (": <invalid float>");
3047 printf_filtered ("%-17.9g", flt2
);
3049 printf_filtered (" dbl: ");
3051 printf_filtered ("<invalid double>");
3053 printf_filtered ("%-24.17g", doub
);
3054 printf_filtered ("\n");
3056 /* may want to do hex display here (future enhancement) */
3061 /* Eight byte registers: print each one as float AND as double. */
3062 mips_read_fp_register_single (regnum
, raw_buffer
);
3063 flt1
= unpack_double (mips_double_register_type (), raw_buffer
, &inv1
);
3065 mips_read_fp_register_double (regnum
, raw_buffer
);
3066 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
3068 printf_filtered (" %-5s: ", REGISTER_NAME (regnum
));
3070 printf_filtered ("<invalid float>");
3072 printf_filtered ("flt: %-17.9g", flt1
);
3074 printf_filtered (" dbl: ");
3076 printf_filtered ("<invalid double>");
3078 printf_filtered ("%-24.17g", doub
);
3080 printf_filtered ("\n");
3081 /* may want to do hex display here (future enhancement) */
3087 /* Print a row's worth of GP (int) registers, with name labels above */
3090 do_gp_register_row (int regnum
)
3092 /* do values for GP (int) regs */
3093 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3094 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
3096 int start_regnum
= regnum
;
3097 int numregs
= NUM_REGS
;
3100 /* For GP registers, we print a separate row of names above the vals */
3101 printf_filtered (" ");
3102 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
3104 if (*REGISTER_NAME (regnum
) == '\0')
3105 continue; /* unused register */
3106 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3107 break; /* end the row: reached FP register */
3108 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
3109 REGISTER_NAME (regnum
));
3112 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
3113 start_regnum
); /* print the R0 to R31 names */
3115 regnum
= start_regnum
; /* go back to start of row */
3116 /* now print the values in hex, 4 or 8 to the row */
3117 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
3119 if (*REGISTER_NAME (regnum
) == '\0')
3120 continue; /* unused register */
3121 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3122 break; /* end row: reached FP register */
3123 /* OK: get the data in raw format. */
3124 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3125 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
3126 /* pad small registers */
3127 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
3128 printf_filtered (" ");
3129 /* Now print the register value in hex, endian order. */
3130 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3131 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3132 byte
< REGISTER_RAW_SIZE (regnum
);
3134 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3136 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
3139 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3140 printf_filtered (" ");
3143 if (col
> 0) /* ie. if we actually printed anything... */
3144 printf_filtered ("\n");
3149 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
3152 mips_do_registers_info (int regnum
, int fpregs
)
3154 if (regnum
!= -1) /* do one specified register */
3156 if (*(REGISTER_NAME (regnum
)) == '\0')
3157 error ("Not a valid register for the current processor type");
3159 mips_print_register (regnum
, 0);
3160 printf_filtered ("\n");
3163 /* do all (or most) registers */
3166 while (regnum
< NUM_REGS
)
3168 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3169 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
3170 regnum
= do_fp_register_row (regnum
); /* FP regs */
3172 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
3174 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
3179 /* Return number of args passed to a frame. described by FIP.
3180 Can return -1, meaning no way to tell. */
3183 mips_frame_num_args (struct frame_info
*frame
)
3188 /* Is this a branch with a delay slot? */
3190 static int is_delayed (unsigned long);
3193 is_delayed (unsigned long insn
)
3196 for (i
= 0; i
< NUMOPCODES
; ++i
)
3197 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
3198 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
3200 return (i
< NUMOPCODES
3201 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
3202 | INSN_COND_BRANCH_DELAY
3203 | INSN_COND_BRANCH_LIKELY
)));
3207 mips_step_skips_delay (CORE_ADDR pc
)
3209 char buf
[MIPS_INSTLEN
];
3211 /* There is no branch delay slot on MIPS16. */
3212 if (pc_is_mips16 (pc
))
3215 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
3216 /* If error reading memory, guess that it is not a delayed branch. */
3218 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
3222 /* Skip the PC past function prologue instructions (32-bit version).
3223 This is a helper function for mips_skip_prologue. */
3226 mips32_skip_prologue (CORE_ADDR pc
)
3230 int seen_sp_adjust
= 0;
3231 int load_immediate_bytes
= 0;
3233 /* Skip the typical prologue instructions. These are the stack adjustment
3234 instruction and the instructions that save registers on the stack
3235 or in the gcc frame. */
3236 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
3238 unsigned long high_word
;
3240 inst
= mips_fetch_instruction (pc
);
3241 high_word
= (inst
>> 16) & 0xffff;
3243 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
3244 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
3246 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
3247 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
3249 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
3250 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
3251 && (inst
& 0x001F0000)) /* reg != $zero */
3254 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
3256 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
3258 continue; /* reg != $zero */
3260 /* move $s8,$sp. With different versions of gas this will be either
3261 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
3262 Accept any one of these. */
3263 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3266 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
3268 else if (high_word
== 0x3c1c) /* lui $gp,n */
3270 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
3272 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3273 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
3275 /* The following instructions load $at or $t0 with an immediate
3276 value in preparation for a stack adjustment via
3277 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
3278 a local variable, so we accept them only before a stack adjustment
3279 instruction was seen. */
3280 else if (!seen_sp_adjust
)
3282 if (high_word
== 0x3c01 || /* lui $at,n */
3283 high_word
== 0x3c08) /* lui $t0,n */
3285 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3288 else if (high_word
== 0x3421 || /* ori $at,$at,n */
3289 high_word
== 0x3508 || /* ori $t0,$t0,n */
3290 high_word
== 0x3401 || /* ori $at,$zero,n */
3291 high_word
== 0x3408) /* ori $t0,$zero,n */
3293 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3303 /* In a frameless function, we might have incorrectly
3304 skipped some load immediate instructions. Undo the skipping
3305 if the load immediate was not followed by a stack adjustment. */
3306 if (load_immediate_bytes
&& !seen_sp_adjust
)
3307 pc
-= load_immediate_bytes
;
3311 /* Skip the PC past function prologue instructions (16-bit version).
3312 This is a helper function for mips_skip_prologue. */
3315 mips16_skip_prologue (CORE_ADDR pc
)
3318 int extend_bytes
= 0;
3319 int prev_extend_bytes
;
3321 /* Table of instructions likely to be found in a function prologue. */
3324 unsigned short inst
;
3325 unsigned short mask
;
3332 , /* addiu $sp,offset */
3336 , /* daddiu $sp,offset */
3340 , /* sw reg,n($sp) */
3344 , /* sd reg,n($sp) */
3348 , /* sw $ra,n($sp) */
3352 , /* sd $ra,n($sp) */
3360 , /* sw $a0-$a3,n($s1) */
3364 , /* move reg,$a0-$a3 */
3368 , /* entry pseudo-op */
3372 , /* addiu $s1,$sp,n */
3375 } /* end of table marker */
3378 /* Skip the typical prologue instructions. These are the stack adjustment
3379 instruction and the instructions that save registers on the stack
3380 or in the gcc frame. */
3381 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
3383 unsigned short inst
;
3386 inst
= mips_fetch_instruction (pc
);
3388 /* Normally we ignore an extend instruction. However, if it is
3389 not followed by a valid prologue instruction, we must adjust
3390 the pc back over the extend so that it won't be considered
3391 part of the prologue. */
3392 if ((inst
& 0xf800) == 0xf000) /* extend */
3394 extend_bytes
= MIPS16_INSTLEN
;
3397 prev_extend_bytes
= extend_bytes
;
3400 /* Check for other valid prologue instructions besides extend. */
3401 for (i
= 0; table
[i
].mask
!= 0; i
++)
3402 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
3404 if (table
[i
].mask
!= 0) /* it was in table? */
3405 continue; /* ignore it */
3409 /* Return the current pc, adjusted backwards by 2 if
3410 the previous instruction was an extend. */
3411 return pc
- prev_extend_bytes
;
3417 /* To skip prologues, I use this predicate. Returns either PC itself
3418 if the code at PC does not look like a function prologue; otherwise
3419 returns an address that (if we're lucky) follows the prologue. If
3420 LENIENT, then we must skip everything which is involved in setting
3421 up the frame (it's OK to skip more, just so long as we don't skip
3422 anything which might clobber the registers which are being saved.
3423 We must skip more in the case where part of the prologue is in the
3424 delay slot of a non-prologue instruction). */
3427 mips_skip_prologue (CORE_ADDR pc
)
3429 /* See if we can determine the end of the prologue via the symbol table.
3430 If so, then return either PC, or the PC after the prologue, whichever
3433 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
3435 if (post_prologue_pc
!= 0)
3436 return max (pc
, post_prologue_pc
);
3438 /* Can't determine prologue from the symbol table, need to examine
3441 if (pc_is_mips16 (pc
))
3442 return mips16_skip_prologue (pc
);
3444 return mips32_skip_prologue (pc
);
3447 /* Determine how a return value is stored within the MIPS register
3448 file, given the return type `valtype'. */
3450 struct return_value_word
3459 return_value_location (struct type
*valtype
,
3460 struct return_value_word
*hi
,
3461 struct return_value_word
*lo
)
3463 int len
= TYPE_LENGTH (valtype
);
3465 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3466 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3467 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3469 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3471 /* We need to break a 64bit float in two 32 bit halves and
3472 spread them across a floating-point register pair. */
3473 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3474 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3475 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3476 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3478 hi
->reg_offset
= lo
->reg_offset
;
3479 lo
->reg
= FP0_REGNUM
+ 0;
3480 hi
->reg
= FP0_REGNUM
+ 1;
3486 /* The floating point value fits in a single floating-point
3488 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3489 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3492 lo
->reg
= FP0_REGNUM
;
3503 /* Locate a result possibly spread across two registers. */
3505 lo
->reg
= regnum
+ 0;
3506 hi
->reg
= regnum
+ 1;
3507 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3508 && len
< MIPS_SAVED_REGSIZE
)
3510 /* "un-left-justify" the value in the low register */
3511 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3516 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3517 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3518 && len
< MIPS_SAVED_REGSIZE
* 2
3519 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3520 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3522 /* "un-left-justify" the value spread across two registers. */
3523 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3524 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3526 hi
->len
= len
- lo
->len
;
3530 /* Only perform a partial copy of the second register. */
3533 if (len
> MIPS_SAVED_REGSIZE
)
3535 lo
->len
= MIPS_SAVED_REGSIZE
;
3536 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3544 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3545 && REGISTER_RAW_SIZE (regnum
) == 8
3546 && MIPS_SAVED_REGSIZE
== 4)
3548 /* Account for the fact that only the least-signficant part
3549 of the register is being used */
3550 lo
->reg_offset
+= 4;
3551 hi
->reg_offset
+= 4;
3554 hi
->buf_offset
= lo
->len
;
3558 /* Given a return value in `regbuf' with a type `valtype', extract and
3559 copy its value into `valbuf'. */
3562 mips_extract_return_value (struct type
*valtype
,
3563 char regbuf
[REGISTER_BYTES
],
3566 struct return_value_word lo
;
3567 struct return_value_word hi
;
3568 return_value_location (valtype
, &hi
, &lo
);
3570 memcpy (valbuf
+ lo
.buf_offset
,
3571 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3575 memcpy (valbuf
+ hi
.buf_offset
,
3576 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3580 /* Given a return value in `valbuf' with a type `valtype', write it's
3581 value into the appropriate register. */
3584 mips_store_return_value (struct type
*valtype
, char *valbuf
)
3586 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3587 struct return_value_word lo
;
3588 struct return_value_word hi
;
3589 return_value_location (valtype
, &hi
, &lo
);
3591 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3592 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3593 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3595 REGISTER_RAW_SIZE (lo
.reg
));
3599 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3600 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3601 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3603 REGISTER_RAW_SIZE (hi
.reg
));
3607 /* Exported procedure: Is PC in the signal trampoline code */
3610 in_sigtramp (CORE_ADDR pc
, char *ignore
)
3612 if (sigtramp_address
== 0)
3614 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3617 /* Root of all "set mips "/"show mips " commands. This will eventually be
3618 used for all MIPS-specific commands. */
3621 show_mips_command (char *args
, int from_tty
)
3623 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3627 set_mips_command (char *args
, int from_tty
)
3629 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3630 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3633 /* Commands to show/set the MIPS FPU type. */
3636 show_mipsfpu_command (char *args
, int from_tty
)
3639 switch (MIPS_FPU_TYPE
)
3641 case MIPS_FPU_SINGLE
:
3642 fpu
= "single-precision";
3644 case MIPS_FPU_DOUBLE
:
3645 fpu
= "double-precision";
3648 fpu
= "absent (none)";
3651 internal_error (__FILE__
, __LINE__
, "bad switch");
3653 if (mips_fpu_type_auto
)
3654 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3657 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3663 set_mipsfpu_command (char *args
, int from_tty
)
3665 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3666 show_mipsfpu_command (args
, from_tty
);
3670 set_mipsfpu_single_command (char *args
, int from_tty
)
3672 mips_fpu_type
= MIPS_FPU_SINGLE
;
3673 mips_fpu_type_auto
= 0;
3674 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3678 set_mipsfpu_double_command (char *args
, int from_tty
)
3680 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3681 mips_fpu_type_auto
= 0;
3682 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3686 set_mipsfpu_none_command (char *args
, int from_tty
)
3688 mips_fpu_type
= MIPS_FPU_NONE
;
3689 mips_fpu_type_auto
= 0;
3690 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3694 set_mipsfpu_auto_command (char *args
, int from_tty
)
3696 mips_fpu_type_auto
= 1;
3699 /* Command to set the processor type. */
3702 mips_set_processor_type_command (char *args
, int from_tty
)
3706 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3708 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3709 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3710 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3712 /* Restore the value. */
3713 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3718 if (!mips_set_processor_type (tmp_mips_processor_type
))
3720 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3721 /* Restore its value. */
3722 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3727 mips_show_processor_type_command (char *args
, int from_tty
)
3731 /* Modify the actual processor type. */
3734 mips_set_processor_type (char *str
)
3741 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3743 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3745 mips_processor_type
= str
;
3746 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3748 /* FIXME tweak fpu flag too */
3755 /* Attempt to identify the particular processor model by reading the
3759 mips_read_processor_type (void)
3763 prid
= read_register (PRID_REGNUM
);
3765 if ((prid
& ~0xf) == 0x700)
3766 return savestring ("r3041", strlen ("r3041"));
3771 /* Just like reinit_frame_cache, but with the right arguments to be
3772 callable as an sfunc. */
3775 reinit_frame_cache_sfunc (char *args
, int from_tty
,
3776 struct cmd_list_element
*c
)
3778 reinit_frame_cache ();
3782 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
3784 mips_extra_func_info_t proc_desc
;
3786 /* Search for the function containing this address. Set the low bit
3787 of the address when searching, in case we were given an even address
3788 that is the start of a 16-bit function. If we didn't do this,
3789 the search would fail because the symbol table says the function
3790 starts at an odd address, i.e. 1 byte past the given address. */
3791 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3792 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3794 /* Make an attempt to determine if this is a 16-bit function. If
3795 the procedure descriptor exists and the address therein is odd,
3796 it's definitely a 16-bit function. Otherwise, we have to just
3797 guess that if the address passed in is odd, it's 16-bits. */
3799 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
3800 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3802 info
->mach
= pc_is_mips16 (memaddr
) ?
3803 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3805 /* Round down the instruction address to the appropriate boundary. */
3806 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
3808 /* Call the appropriate disassembler based on the target endian-ness. */
3809 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3810 return print_insn_big_mips (memaddr
, info
);
3812 return print_insn_little_mips (memaddr
, info
);
3815 /* Old-style breakpoint macros.
3816 The IDT board uses an unusual breakpoint value, and sometimes gets
3817 confused when it sees the usual MIPS breakpoint instruction. */
3819 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3820 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3821 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3822 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3823 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3824 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3825 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3826 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3828 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3829 counter value to determine whether a 16- or 32-bit breakpoint should be
3830 used. It returns a pointer to a string of bytes that encode a breakpoint
3831 instruction, stores the length of the string to *lenptr, and adjusts pc
3832 (if necessary) to point to the actual memory location where the
3833 breakpoint should be inserted. */
3835 const unsigned char *
3836 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
3838 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3840 if (pc_is_mips16 (*pcptr
))
3842 static unsigned char mips16_big_breakpoint
[] =
3843 MIPS16_BIG_BREAKPOINT
;
3844 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3845 *lenptr
= sizeof (mips16_big_breakpoint
);
3846 return mips16_big_breakpoint
;
3850 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
3851 static unsigned char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3852 static unsigned char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3854 *lenptr
= sizeof (big_breakpoint
);
3856 if (strcmp (target_shortname
, "mips") == 0)
3857 return idt_big_breakpoint
;
3858 else if (strcmp (target_shortname
, "ddb") == 0
3859 || strcmp (target_shortname
, "pmon") == 0
3860 || strcmp (target_shortname
, "lsi") == 0)
3861 return pmon_big_breakpoint
;
3863 return big_breakpoint
;
3868 if (pc_is_mips16 (*pcptr
))
3870 static unsigned char mips16_little_breakpoint
[] =
3871 MIPS16_LITTLE_BREAKPOINT
;
3872 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3873 *lenptr
= sizeof (mips16_little_breakpoint
);
3874 return mips16_little_breakpoint
;
3878 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3879 static unsigned char pmon_little_breakpoint
[] =
3880 PMON_LITTLE_BREAKPOINT
;
3881 static unsigned char idt_little_breakpoint
[] =
3882 IDT_LITTLE_BREAKPOINT
;
3884 *lenptr
= sizeof (little_breakpoint
);
3886 if (strcmp (target_shortname
, "mips") == 0)
3887 return idt_little_breakpoint
;
3888 else if (strcmp (target_shortname
, "ddb") == 0
3889 || strcmp (target_shortname
, "pmon") == 0
3890 || strcmp (target_shortname
, "lsi") == 0)
3891 return pmon_little_breakpoint
;
3893 return little_breakpoint
;
3898 /* If PC is in a mips16 call or return stub, return the address of the target
3899 PC, which is either the callee or the caller. There are several
3900 cases which must be handled:
3902 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3903 target PC is in $31 ($ra).
3904 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3905 and the target PC is in $2.
3906 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3907 before the jal instruction, this is effectively a call stub
3908 and the the target PC is in $2. Otherwise this is effectively
3909 a return stub and the target PC is in $18.
3911 See the source code for the stubs in gcc/config/mips/mips16.S for
3914 This function implements the SKIP_TRAMPOLINE_CODE macro.
3918 mips_skip_stub (CORE_ADDR pc
)
3921 CORE_ADDR start_addr
;
3923 /* Find the starting address and name of the function containing the PC. */
3924 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3927 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3928 target PC is in $31 ($ra). */
3929 if (strcmp (name
, "__mips16_ret_sf") == 0
3930 || strcmp (name
, "__mips16_ret_df") == 0)
3931 return read_signed_register (RA_REGNUM
);
3933 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3935 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3936 and the target PC is in $2. */
3937 if (name
[19] >= '0' && name
[19] <= '9')
3938 return read_signed_register (2);
3940 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3941 before the jal instruction, this is effectively a call stub
3942 and the the target PC is in $2. Otherwise this is effectively
3943 a return stub and the target PC is in $18. */
3944 else if (name
[19] == 's' || name
[19] == 'd')
3946 if (pc
== start_addr
)
3948 /* Check if the target of the stub is a compiler-generated
3949 stub. Such a stub for a function bar might have a name
3950 like __fn_stub_bar, and might look like this:
3955 la $1,bar (becomes a lui/addiu pair)
3957 So scan down to the lui/addi and extract the target
3958 address from those two instructions. */
3960 CORE_ADDR target_pc
= read_signed_register (2);
3964 /* See if the name of the target function is __fn_stub_*. */
3965 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3967 if (strncmp (name
, "__fn_stub_", 10) != 0
3968 && strcmp (name
, "etext") != 0
3969 && strcmp (name
, "_etext") != 0)
3972 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3973 The limit on the search is arbitrarily set to 20
3974 instructions. FIXME. */
3975 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3977 inst
= mips_fetch_instruction (target_pc
);
3978 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3979 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3980 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3981 return pc
| (inst
& 0xffff); /* low word */
3984 /* Couldn't find the lui/addui pair, so return stub address. */
3988 /* This is the 'return' part of a call stub. The return
3989 address is in $r18. */
3990 return read_signed_register (18);
3993 return 0; /* not a stub */
3997 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3998 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
4001 mips_in_call_stub (CORE_ADDR pc
, char *name
)
4003 CORE_ADDR start_addr
;
4005 /* Find the starting address of the function containing the PC. If the
4006 caller didn't give us a name, look it up at the same time. */
4007 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
4010 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4012 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
4013 if (name
[19] >= '0' && name
[19] <= '9')
4015 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4016 before the jal instruction, this is effectively a call stub. */
4017 else if (name
[19] == 's' || name
[19] == 'd')
4018 return pc
== start_addr
;
4021 return 0; /* not a stub */
4025 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
4026 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
4029 mips_in_return_stub (CORE_ADDR pc
, char *name
)
4031 CORE_ADDR start_addr
;
4033 /* Find the starting address of the function containing the PC. */
4034 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
4037 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
4038 if (strcmp (name
, "__mips16_ret_sf") == 0
4039 || strcmp (name
, "__mips16_ret_df") == 0)
4042 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
4043 i.e. after the jal instruction, this is effectively a return stub. */
4044 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
4045 && (name
[19] == 's' || name
[19] == 'd')
4046 && pc
!= start_addr
)
4049 return 0; /* not a stub */
4053 /* Return non-zero if the PC is in a library helper function that should
4054 be ignored. This implements the IGNORE_HELPER_CALL macro. */
4057 mips_ignore_helper (CORE_ADDR pc
)
4061 /* Find the starting address and name of the function containing the PC. */
4062 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
4065 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
4066 that we want to ignore. */
4067 return (strcmp (name
, "__mips16_ret_sf") == 0
4068 || strcmp (name
, "__mips16_ret_df") == 0);
4072 /* Return a location where we can set a breakpoint that will be hit
4073 when an inferior function call returns. This is normally the
4074 program's entry point. Executables that don't have an entry
4075 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
4076 whose address is the location where the breakpoint should be placed. */
4079 mips_call_dummy_address (void)
4081 struct minimal_symbol
*sym
;
4083 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
4085 return SYMBOL_VALUE_ADDRESS (sym
);
4087 return entry_point_address ();
4091 /* If the current gcc for this target does not produce correct debugging
4092 information for float parameters, both prototyped and unprototyped, then
4093 define this macro. This forces gdb to always assume that floats are
4094 passed as doubles and then converted in the callee.
4096 For the mips chip, it appears that the debug info marks the parameters as
4097 floats regardless of whether the function is prototyped, but the actual
4098 values are passed as doubles for the non-prototyped case and floats for
4099 the prototyped case. Thus we choose to make the non-prototyped case work
4100 for C and break the prototyped case, since the non-prototyped case is
4101 probably much more common. (FIXME). */
4104 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
4106 return current_language
->la_language
== language_c
;
4109 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
4110 the register stored on the stack (32) is different to its real raw
4111 size (64). The below ensures that registers are fetched from the
4112 stack using their ABI size and then stored into the RAW_BUFFER
4113 using their raw size.
4115 The alternative to adding this function would be to add an ABI
4116 macro - REGISTER_STACK_SIZE(). */
4119 mips_get_saved_register (char *raw_buffer
,
4122 struct frame_info
*frame
,
4124 enum lval_type
*lval
)
4128 if (!target_has_registers
)
4129 error ("No registers.");
4131 /* Normal systems don't optimize out things with register numbers. */
4132 if (optimized
!= NULL
)
4134 addr
= find_saved_register (frame
, regnum
);
4138 *lval
= lval_memory
;
4139 if (regnum
== SP_REGNUM
)
4141 if (raw_buffer
!= NULL
)
4143 /* Put it back in target format. */
4144 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
4151 if (raw_buffer
!= NULL
)
4155 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
4157 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
4159 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
4160 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
4166 *lval
= lval_register
;
4167 addr
= REGISTER_BYTE (regnum
);
4168 if (raw_buffer
!= NULL
)
4169 read_register_gen (regnum
, raw_buffer
);
4175 /* Immediately after a function call, return the saved pc.
4176 Can't always go through the frames for this because on some machines
4177 the new frame is not set up until the new function executes
4178 some instructions. */
4181 mips_saved_pc_after_call (struct frame_info
*frame
)
4183 return read_signed_register (RA_REGNUM
);
4187 /* Convert a dbx stab register number (from `r' declaration) to a gdb
4191 mips_stab_reg_to_regnum (int num
)
4196 return num
+ FP0_REGNUM
- 38;
4199 /* Convert a ecoff register number to a gdb REGNUM */
4202 mips_ecoff_reg_to_regnum (int num
)
4207 return num
+ FP0_REGNUM
- 32;
4210 /* Convert an integer into an address. By first converting the value
4211 into a pointer and then extracting it signed, the address is
4212 guarenteed to be correctly sign extended. */
4215 mips_integer_to_address (struct type
*type
, void *buf
)
4217 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
4218 LONGEST val
= unpack_long (type
, buf
);
4219 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
4220 return extract_signed_integer (tmp
,
4221 TYPE_LENGTH (builtin_type_void_data_ptr
));
4225 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4227 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4228 const char *name
= bfd_get_section_name (abfd
, sect
);
4230 if (*abip
!= MIPS_ABI_UNKNOWN
)
4233 if (strncmp (name
, ".mdebug.", 8) != 0)
4236 if (strcmp (name
, ".mdebug.abi32") == 0)
4237 *abip
= MIPS_ABI_O32
;
4238 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4239 *abip
= MIPS_ABI_N32
;
4240 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4241 *abip
= MIPS_ABI_O64
;
4242 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4243 *abip
= MIPS_ABI_EABI32
;
4244 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4245 *abip
= MIPS_ABI_EABI64
;
4247 warning ("unsupported ABI %s.", name
+ 8);
4250 static struct gdbarch
*
4251 mips_gdbarch_init (struct gdbarch_info info
,
4252 struct gdbarch_list
*arches
)
4254 static LONGEST mips_call_dummy_words
[] =
4256 struct gdbarch
*gdbarch
;
4257 struct gdbarch_tdep
*tdep
;
4259 enum mips_abi mips_abi
;
4260 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
4262 /* Reset the disassembly info, in case it was set to something
4264 tm_print_insn_info
.flavour
= bfd_target_unknown_flavour
;
4265 tm_print_insn_info
.arch
= bfd_arch_unknown
;
4266 tm_print_insn_info
.mach
= 0;
4272 /* First of all, extract the elf_flags, if available. */
4273 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4274 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4276 /* Try to determine the OS ABI of the object we are loading. If
4277 we end up with `unknown', just leave it that way. */
4278 osabi
= gdbarch_lookup_osabi (info
.abfd
);
4281 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4282 switch ((elf_flags
& EF_MIPS_ABI
))
4284 case E_MIPS_ABI_O32
:
4285 mips_abi
= MIPS_ABI_O32
;
4287 case E_MIPS_ABI_O64
:
4288 mips_abi
= MIPS_ABI_O64
;
4290 case E_MIPS_ABI_EABI32
:
4291 mips_abi
= MIPS_ABI_EABI32
;
4293 case E_MIPS_ABI_EABI64
:
4294 mips_abi
= MIPS_ABI_EABI64
;
4297 if ((elf_flags
& EF_MIPS_ABI2
))
4298 mips_abi
= MIPS_ABI_N32
;
4300 mips_abi
= MIPS_ABI_UNKNOWN
;
4304 /* GCC creates a pseudo-section whose name describes the ABI. */
4305 if (mips_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4306 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &mips_abi
);
4308 /* Try the architecture for any hint of the corect ABI */
4309 if (mips_abi
== MIPS_ABI_UNKNOWN
4310 && info
.bfd_arch_info
!= NULL
4311 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4313 switch (info
.bfd_arch_info
->mach
)
4315 case bfd_mach_mips3900
:
4316 mips_abi
= MIPS_ABI_EABI32
;
4318 case bfd_mach_mips4100
:
4319 case bfd_mach_mips5000
:
4320 mips_abi
= MIPS_ABI_EABI64
;
4322 case bfd_mach_mips8000
:
4323 case bfd_mach_mips10000
:
4324 mips_abi
= MIPS_ABI_N32
;
4328 #ifdef MIPS_DEFAULT_ABI
4329 if (mips_abi
== MIPS_ABI_UNKNOWN
)
4330 mips_abi
= MIPS_DEFAULT_ABI
;
4335 fprintf_unfiltered (gdb_stdlog
,
4336 "mips_gdbarch_init: elf_flags = 0x%08x\n",
4338 fprintf_unfiltered (gdb_stdlog
,
4339 "mips_gdbarch_init: mips_abi = %d\n",
4343 /* try to find a pre-existing architecture */
4344 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4346 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4348 /* MIPS needs to be pedantic about which ABI the object is
4350 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4352 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4354 if (gdbarch_tdep (arches
->gdbarch
)->osabi
== osabi
)
4355 return arches
->gdbarch
;
4358 /* Need a new architecture. Fill in a target specific vector. */
4359 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4360 gdbarch
= gdbarch_alloc (&info
, tdep
);
4361 tdep
->elf_flags
= elf_flags
;
4362 tdep
->osabi
= osabi
;
4364 /* Initially set everything according to the default ABI/ISA. */
4365 set_gdbarch_short_bit (gdbarch
, 16);
4366 set_gdbarch_int_bit (gdbarch
, 32);
4367 set_gdbarch_float_bit (gdbarch
, 32);
4368 set_gdbarch_double_bit (gdbarch
, 64);
4369 set_gdbarch_long_double_bit (gdbarch
, 64);
4370 set_gdbarch_register_raw_size (gdbarch
, mips_register_raw_size
);
4371 tdep
->mips_abi
= mips_abi
;
4376 tdep
->mips_abi_string
= "o32";
4377 tdep
->mips_default_saved_regsize
= 4;
4378 tdep
->mips_default_stack_argsize
= 4;
4379 tdep
->mips_fp_register_double
= 0;
4380 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4381 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4382 tdep
->mips_regs_have_home_p
= 1;
4383 tdep
->gdb_target_is_mips64
= 0;
4384 tdep
->default_mask_address_p
= 0;
4385 set_gdbarch_long_bit (gdbarch
, 32);
4386 set_gdbarch_ptr_bit (gdbarch
, 32);
4387 set_gdbarch_long_long_bit (gdbarch
, 64);
4390 tdep
->mips_abi_string
= "o64";
4391 tdep
->mips_default_saved_regsize
= 8;
4392 tdep
->mips_default_stack_argsize
= 8;
4393 tdep
->mips_fp_register_double
= 1;
4394 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4395 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4396 tdep
->mips_regs_have_home_p
= 1;
4397 tdep
->gdb_target_is_mips64
= 1;
4398 tdep
->default_mask_address_p
= 0;
4399 set_gdbarch_long_bit (gdbarch
, 32);
4400 set_gdbarch_ptr_bit (gdbarch
, 32);
4401 set_gdbarch_long_long_bit (gdbarch
, 64);
4403 case MIPS_ABI_EABI32
:
4404 tdep
->mips_abi_string
= "eabi32";
4405 tdep
->mips_default_saved_regsize
= 4;
4406 tdep
->mips_default_stack_argsize
= 4;
4407 tdep
->mips_fp_register_double
= 0;
4408 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4409 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4410 tdep
->mips_regs_have_home_p
= 0;
4411 tdep
->gdb_target_is_mips64
= 0;
4412 tdep
->default_mask_address_p
= 0;
4413 set_gdbarch_long_bit (gdbarch
, 32);
4414 set_gdbarch_ptr_bit (gdbarch
, 32);
4415 set_gdbarch_long_long_bit (gdbarch
, 64);
4417 case MIPS_ABI_EABI64
:
4418 tdep
->mips_abi_string
= "eabi64";
4419 tdep
->mips_default_saved_regsize
= 8;
4420 tdep
->mips_default_stack_argsize
= 8;
4421 tdep
->mips_fp_register_double
= 1;
4422 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4423 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4424 tdep
->mips_regs_have_home_p
= 0;
4425 tdep
->gdb_target_is_mips64
= 1;
4426 tdep
->default_mask_address_p
= 0;
4427 set_gdbarch_long_bit (gdbarch
, 64);
4428 set_gdbarch_ptr_bit (gdbarch
, 64);
4429 set_gdbarch_long_long_bit (gdbarch
, 64);
4432 tdep
->mips_abi_string
= "n32";
4433 tdep
->mips_default_saved_regsize
= 4;
4434 tdep
->mips_default_stack_argsize
= 8;
4435 tdep
->mips_fp_register_double
= 1;
4436 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4437 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4438 tdep
->mips_regs_have_home_p
= 0;
4439 tdep
->gdb_target_is_mips64
= 0;
4440 tdep
->default_mask_address_p
= 0;
4441 set_gdbarch_long_bit (gdbarch
, 32);
4442 set_gdbarch_ptr_bit (gdbarch
, 32);
4443 set_gdbarch_long_long_bit (gdbarch
, 64);
4445 /* Set up the disassembler info, so that we get the right
4446 register names from libopcodes. */
4447 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
4448 tm_print_insn_info
.arch
= bfd_arch_mips
;
4449 if (info
.bfd_arch_info
!= NULL
4450 && info
.bfd_arch_info
->arch
== bfd_arch_mips
4451 && info
.bfd_arch_info
->mach
)
4452 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
4454 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
4457 tdep
->mips_abi_string
= "default";
4458 tdep
->mips_default_saved_regsize
= MIPS_REGSIZE
;
4459 tdep
->mips_default_stack_argsize
= MIPS_REGSIZE
;
4460 tdep
->mips_fp_register_double
= (REGISTER_VIRTUAL_SIZE (FP0_REGNUM
) == 8);
4461 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4462 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4463 tdep
->mips_regs_have_home_p
= 1;
4464 tdep
->gdb_target_is_mips64
= 0;
4465 tdep
->default_mask_address_p
= 0;
4466 set_gdbarch_long_bit (gdbarch
, 32);
4467 set_gdbarch_ptr_bit (gdbarch
, 32);
4468 set_gdbarch_long_long_bit (gdbarch
, 64);
4472 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4473 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4476 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4477 flag in object files because to do so would make it impossible to
4478 link with libraries compiled without "-gp32". This is
4479 unnecessarily restrictive.
4481 We could solve this problem by adding "-gp32" multilibs to gcc,
4482 but to set this flag before gcc is built with such multilibs will
4483 break too many systems.''
4485 But even more unhelpfully, the default linker output target for
4486 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4487 for 64-bit programs - you need to change the ABI to change this,
4488 and not all gcc targets support that currently. Therefore using
4489 this flag to detect 32-bit mode would do the wrong thing given
4490 the current gcc - it would make GDB treat these 64-bit programs
4491 as 32-bit programs by default. */
4493 /* enable/disable the MIPS FPU */
4494 if (!mips_fpu_type_auto
)
4495 tdep
->mips_fpu_type
= mips_fpu_type
;
4496 else if (info
.bfd_arch_info
!= NULL
4497 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4498 switch (info
.bfd_arch_info
->mach
)
4500 case bfd_mach_mips3900
:
4501 case bfd_mach_mips4100
:
4502 case bfd_mach_mips4111
:
4503 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
4505 case bfd_mach_mips4650
:
4506 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
4509 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4513 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4515 /* MIPS version of register names. NOTE: At present the MIPS
4516 register name management is part way between the old -
4517 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4518 Further work on it is required. */
4519 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4520 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
4521 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4522 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4523 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4524 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4526 /* Add/remove bits from an address. The MIPS needs be careful to
4527 ensure that all 32 bit addresses are sign extended to 64 bits. */
4528 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
4530 /* There's a mess in stack frame creation. See comments in
4531 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
4532 set_gdbarch_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
4533 set_gdbarch_init_frame_pc (gdbarch
, init_frame_pc_noop
);
4535 /* Map debug register numbers onto internal register numbers. */
4536 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
4537 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_ecoff_reg_to_regnum
);
4539 /* Initialize a frame */
4540 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
4542 /* MIPS version of CALL_DUMMY */
4544 set_gdbarch_call_dummy_p (gdbarch
, 1);
4545 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4546 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
4547 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4548 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4549 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4550 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4551 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4552 set_gdbarch_call_dummy_length (gdbarch
, 0);
4553 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4554 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4555 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4556 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4557 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4558 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4559 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4561 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4562 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
4564 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4565 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
4566 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4568 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
4569 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
4571 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
4572 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
4573 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
4575 /* Hook in OS ABI-specific overrides, if they have been registered. */
4576 gdbarch_init_osabi (info
, gdbarch
, osabi
);
4582 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4584 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4588 int ef_mips_32bitmode
;
4589 /* determine the ISA */
4590 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
4608 /* determine the size of a pointer */
4609 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
4610 fprintf_unfiltered (file
,
4611 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4613 fprintf_unfiltered (file
,
4614 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4616 fprintf_unfiltered (file
,
4617 "mips_dump_tdep: ef_mips_arch = %d\n",
4619 fprintf_unfiltered (file
,
4620 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4622 tdep
->mips_abi_string
);
4623 fprintf_unfiltered (file
,
4624 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4625 mips_mask_address_p (),
4626 tdep
->default_mask_address_p
);
4628 fprintf_unfiltered (file
,
4629 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4630 FP_REGISTER_DOUBLE
);
4631 fprintf_unfiltered (file
,
4632 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4633 MIPS_DEFAULT_FPU_TYPE
,
4634 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4635 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4636 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4638 fprintf_unfiltered (file
,
4639 "mips_dump_tdep: MIPS_EABI = %d\n",
4641 fprintf_unfiltered (file
,
4642 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4643 MIPS_LAST_FP_ARG_REGNUM
,
4644 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
4645 fprintf_unfiltered (file
,
4646 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4648 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4649 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4650 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4652 fprintf_unfiltered (file
,
4653 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4654 MIPS_DEFAULT_SAVED_REGSIZE
);
4655 fprintf_unfiltered (file
,
4656 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4657 FP_REGISTER_DOUBLE
);
4658 fprintf_unfiltered (file
,
4659 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4660 MIPS_REGS_HAVE_HOME_P
);
4661 fprintf_unfiltered (file
,
4662 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4663 MIPS_DEFAULT_STACK_ARGSIZE
);
4664 fprintf_unfiltered (file
,
4665 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4666 MIPS_STACK_ARGSIZE
);
4667 fprintf_unfiltered (file
,
4668 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4670 fprintf_unfiltered (file
,
4671 "mips_dump_tdep: A0_REGNUM = %d\n",
4673 fprintf_unfiltered (file
,
4674 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4675 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
4676 fprintf_unfiltered (file
,
4677 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4678 XSTRING (ATTACH_DETACH
));
4679 fprintf_unfiltered (file
,
4680 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4682 fprintf_unfiltered (file
,
4683 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4684 fprintf_unfiltered (file
,
4685 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4687 fprintf_unfiltered (file
,
4688 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4690 fprintf_unfiltered (file
,
4691 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4693 fprintf_unfiltered (file
,
4694 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4695 XSTRING (DO_REGISTERS_INFO
));
4696 fprintf_unfiltered (file
,
4697 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4698 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
4699 fprintf_unfiltered (file
,
4700 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4701 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
4702 fprintf_unfiltered (file
,
4703 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4704 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
4705 fprintf_unfiltered (file
,
4706 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4708 fprintf_unfiltered (file
,
4709 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4711 fprintf_unfiltered (file
,
4712 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4713 FIRST_EMBED_REGNUM
);
4714 fprintf_unfiltered (file
,
4715 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4717 fprintf_unfiltered (file
,
4718 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4719 GDB_TARGET_IS_MIPS64
);
4720 fprintf_unfiltered (file
,
4721 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4722 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
4723 fprintf_unfiltered (file
,
4724 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4725 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
4726 fprintf_unfiltered (file
,
4727 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4729 fprintf_unfiltered (file
,
4730 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4731 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
4732 fprintf_unfiltered (file
,
4733 "mips_dump_tdep: HI_REGNUM = %d\n",
4735 fprintf_unfiltered (file
,
4736 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4737 fprintf_unfiltered (file
,
4738 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4739 fprintf_unfiltered (file
,
4740 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4741 XSTRING (IGNORE_HELPER_CALL (PC
)));
4742 fprintf_unfiltered (file
,
4743 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4744 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
4745 fprintf_unfiltered (file
,
4746 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4747 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
4748 fprintf_unfiltered (file
,
4749 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4750 fprintf_unfiltered (file
,
4751 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4753 fprintf_unfiltered (file
,
4754 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4755 fprintf_unfiltered (file
,
4756 "mips_dump_tdep: LO_REGNUM = %d\n",
4758 #ifdef MACHINE_CPROC_FP_OFFSET
4759 fprintf_unfiltered (file
,
4760 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4761 MACHINE_CPROC_FP_OFFSET
);
4763 #ifdef MACHINE_CPROC_PC_OFFSET
4764 fprintf_unfiltered (file
,
4765 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4766 MACHINE_CPROC_PC_OFFSET
);
4768 #ifdef MACHINE_CPROC_SP_OFFSET
4769 fprintf_unfiltered (file
,
4770 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4771 MACHINE_CPROC_SP_OFFSET
);
4773 fprintf_unfiltered (file
,
4774 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4775 fprintf_unfiltered (file
,
4776 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4777 fprintf_unfiltered (file
,
4778 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4780 fprintf_unfiltered (file
,
4781 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4782 fprintf_unfiltered (file
,
4783 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4784 fprintf_unfiltered (file
,
4785 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4786 fprintf_unfiltered (file
,
4787 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4789 fprintf_unfiltered (file
,
4790 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
4791 MIPS_LAST_ARG_REGNUM
,
4792 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
4793 fprintf_unfiltered (file
,
4794 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4796 fprintf_unfiltered (file
,
4797 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4798 fprintf_unfiltered (file
,
4799 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4800 MIPS_SAVED_REGSIZE
);
4801 fprintf_unfiltered (file
,
4802 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4803 fprintf_unfiltered (file
,
4804 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4805 XSTRING (MSYMBOL_SIZE (MSYM
)));
4806 fprintf_unfiltered (file
,
4807 "mips_dump_tdep: OP_LDFPR = used?\n");
4808 fprintf_unfiltered (file
,
4809 "mips_dump_tdep: OP_LDGPR = used?\n");
4810 fprintf_unfiltered (file
,
4811 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4812 fprintf_unfiltered (file
,
4813 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4814 fprintf_unfiltered (file
,
4815 "mips_dump_tdep: PRID_REGNUM = %d\n",
4817 fprintf_unfiltered (file
,
4818 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4819 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
4820 fprintf_unfiltered (file
,
4821 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4822 fprintf_unfiltered (file
,
4823 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4824 fprintf_unfiltered (file
,
4825 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4826 fprintf_unfiltered (file
,
4827 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4828 fprintf_unfiltered (file
,
4829 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4830 fprintf_unfiltered (file
,
4831 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4832 fprintf_unfiltered (file
,
4833 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4834 fprintf_unfiltered (file
,
4835 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4836 fprintf_unfiltered (file
,
4837 "mips_dump_tdep: PROC_PC_REG = function?\n");
4838 fprintf_unfiltered (file
,
4839 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4840 fprintf_unfiltered (file
,
4841 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4842 fprintf_unfiltered (file
,
4843 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4844 fprintf_unfiltered (file
,
4845 "mips_dump_tdep: PS_REGNUM = %d\n",
4847 fprintf_unfiltered (file
,
4848 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4850 fprintf_unfiltered (file
,
4851 "mips_dump_tdep: RA_REGNUM = %d\n",
4853 fprintf_unfiltered (file
,
4854 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4855 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4856 fprintf_unfiltered (file
,
4857 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4858 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4859 fprintf_unfiltered (file
,
4860 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4861 fprintf_unfiltered (file
,
4862 "mips_dump_tdep: ROUND_DOWN = function?\n");
4863 fprintf_unfiltered (file
,
4864 "mips_dump_tdep: ROUND_UP = function?\n");
4866 fprintf_unfiltered (file
,
4867 "mips_dump_tdep: SAVED_BYTES = %d\n",
4871 fprintf_unfiltered (file
,
4872 "mips_dump_tdep: SAVED_FP = %d\n",
4876 fprintf_unfiltered (file
,
4877 "mips_dump_tdep: SAVED_PC = %d\n",
4880 fprintf_unfiltered (file
,
4881 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
4882 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
4883 fprintf_unfiltered (file
,
4884 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
4885 fprintf_unfiltered (file
,
4886 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
4888 fprintf_unfiltered (file
,
4889 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
4890 SIGFRAME_FPREGSAVE_OFF
);
4891 fprintf_unfiltered (file
,
4892 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
4894 fprintf_unfiltered (file
,
4895 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
4896 SIGFRAME_REGSAVE_OFF
);
4897 fprintf_unfiltered (file
,
4898 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
4900 fprintf_unfiltered (file
,
4901 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
4902 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
4903 fprintf_unfiltered (file
,
4904 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
4905 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
4906 fprintf_unfiltered (file
,
4907 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
4908 SOFTWARE_SINGLE_STEP_P ());
4909 fprintf_unfiltered (file
,
4910 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
4911 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
4912 #ifdef STACK_END_ADDR
4913 fprintf_unfiltered (file
,
4914 "mips_dump_tdep: STACK_END_ADDR = %d\n",
4917 fprintf_unfiltered (file
,
4918 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
4919 XSTRING (STEP_SKIPS_DELAY (PC
)));
4920 fprintf_unfiltered (file
,
4921 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
4922 STEP_SKIPS_DELAY_P
);
4923 fprintf_unfiltered (file
,
4924 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
4925 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
4926 fprintf_unfiltered (file
,
4927 "mips_dump_tdep: T9_REGNUM = %d\n",
4929 fprintf_unfiltered (file
,
4930 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
4931 fprintf_unfiltered (file
,
4932 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
4933 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
4934 fprintf_unfiltered (file
,
4935 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
4936 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
4937 fprintf_unfiltered (file
,
4938 "mips_dump_tdep: TARGET_MIPS = used?\n");
4939 fprintf_unfiltered (file
,
4940 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
4941 XSTRING (TM_PRINT_INSN_MACH
));
4943 fprintf_unfiltered (file
,
4944 "mips_dump_tdep: TRACE_CLEAR # %s\n",
4945 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
4948 fprintf_unfiltered (file
,
4949 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
4952 #ifdef TRACE_FLAVOR_SIZE
4953 fprintf_unfiltered (file
,
4954 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
4958 fprintf_unfiltered (file
,
4959 "mips_dump_tdep: TRACE_SET # %s\n",
4960 XSTRING (TRACE_SET (X
,STATE
)));
4962 fprintf_unfiltered (file
,
4963 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
4964 #ifdef UNUSED_REGNUM
4965 fprintf_unfiltered (file
,
4966 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
4969 fprintf_unfiltered (file
,
4970 "mips_dump_tdep: V0_REGNUM = %d\n",
4972 fprintf_unfiltered (file
,
4973 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
4974 (long) VM_MIN_ADDRESS
);
4976 fprintf_unfiltered (file
,
4977 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
4980 fprintf_unfiltered (file
,
4981 "mips_dump_tdep: ZERO_REGNUM = %d\n",
4983 fprintf_unfiltered (file
,
4984 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
4987 fprintf_unfiltered (file
,
4988 "mips_dump_tdep: OS ABI = %s\n",
4989 gdbarch_osabi_name (tdep
->osabi
));
4993 _initialize_mips_tdep (void)
4995 static struct cmd_list_element
*mipsfpulist
= NULL
;
4996 struct cmd_list_element
*c
;
4998 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
4999 if (!tm_print_insn
) /* Someone may have already set it */
5000 tm_print_insn
= gdb_print_insn_mips
;
5002 /* Add root prefix command for all "set mips"/"show mips" commands */
5003 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5004 "Various MIPS specific commands.",
5005 &setmipscmdlist
, "set mips ", 0, &setlist
);
5007 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5008 "Various MIPS specific commands.",
5009 &showmipscmdlist
, "show mips ", 0, &showlist
);
5011 /* Allow the user to override the saved register size. */
5012 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
5015 &mips_saved_regsize_string
, "\
5016 Set size of general purpose registers saved on the stack.\n\
5017 This option can be set to one of:\n\
5018 32 - Force GDB to treat saved GP registers as 32-bit\n\
5019 64 - Force GDB to treat saved GP registers as 64-bit\n\
5020 auto - Allow GDB to use the target's default setting or autodetect the\n\
5021 saved GP register size from information contained in the executable.\n\
5026 /* Allow the user to override the argument stack size. */
5027 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
5030 &mips_stack_argsize_string
, "\
5031 Set the amount of stack space reserved for each argument.\n\
5032 This option can be set to one of:\n\
5033 32 - Force GDB to allocate 32-bit chunks per argument\n\
5034 64 - Force GDB to allocate 64-bit chunks per argument\n\
5035 auto - Allow GDB to determine the correct setting from the current\n\
5036 target and executable (default)",
5040 /* Let the user turn off floating point and set the fence post for
5041 heuristic_proc_start. */
5043 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5044 "Set use of MIPS floating-point coprocessor.",
5045 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5046 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5047 "Select single-precision MIPS floating-point coprocessor.",
5049 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5050 "Select double-precision MIPS floating-point coprocessor.",
5052 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5053 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5054 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5055 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5056 "Select no MIPS floating-point coprocessor.",
5058 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5059 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5060 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5061 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5062 "Select MIPS floating-point coprocessor automatically.",
5064 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5065 "Show current use of MIPS floating-point coprocessor target.",
5068 /* We really would like to have both "0" and "unlimited" work, but
5069 command.c doesn't deal with that. So make it a var_zinteger
5070 because the user can always use "999999" or some such for unlimited. */
5071 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
5072 (char *) &heuristic_fence_post
,
5074 Set the distance searched for the start of a function.\n\
5075 If you are debugging a stripped executable, GDB needs to search through the\n\
5076 program for the start of a function. This command sets the distance of the\n\
5077 search. The only need to set it is when debugging a stripped executable.",
5079 /* We need to throw away the frame cache when we set this, since it
5080 might change our ability to get backtraces. */
5081 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
5082 add_show_from_set (c
, &showlist
);
5084 /* Allow the user to control whether the upper bits of 64-bit
5085 addresses should be zeroed. */
5086 c
= add_set_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
,
5087 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
5088 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\
5089 the correct value.\n",
5091 add_cmd ("mask-address", no_class
, show_mask_address
,
5092 "Show current mask-address value", &showmipscmdlist
);
5094 /* Allow the user to control the size of 32 bit registers within the
5095 raw remote packet. */
5096 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
5099 (char *)&mips64_transfers_32bit_regs_p
, "\
5100 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
5101 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5102 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5103 64 bits for others. Use \"off\" to disable compatibility mode",
5107 /* Debug this files internals. */
5108 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
5109 &mips_debug
, "Set mips debugging.\n\
5110 When non-zero, mips specific debugging is enabled.", &setdebuglist
),