1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
43 #include "opcode/mips.h"
48 /* A useful bit in the CP0 status register (PS_REGNUM). */
49 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
50 #define ST0_FR (1 << 26)
52 /* The sizes of floating point registers. */
56 MIPS_FPU_SINGLE_REGSIZE
= 4,
57 MIPS_FPU_DOUBLE_REGSIZE
= 8
60 /* All the possible MIPS ABIs. */
74 static const char *mips_abi_string
;
76 static const char *mips_abi_strings
[] = {
87 struct frame_extra_info
89 mips_extra_func_info_t proc_desc
;
93 /* Various MIPS ISA options (related to stack analysis) can be
94 overridden dynamically. Establish an enum/array for managing
97 static const char size_auto
[] = "auto";
98 static const char size_32
[] = "32";
99 static const char size_64
[] = "64";
101 static const char *size_enums
[] = {
108 /* Some MIPS boards don't support floating point while others only
109 support single-precision floating-point operations. See also
110 FP_REGISTER_DOUBLE. */
114 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
115 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
116 MIPS_FPU_NONE
/* No floating point. */
119 #ifndef MIPS_DEFAULT_FPU_TYPE
120 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
122 static int mips_fpu_type_auto
= 1;
123 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
125 static int mips_debug
= 0;
127 /* MIPS specific per-architecture information */
130 /* from the elf header */
134 enum mips_abi mips_abi
;
135 enum mips_abi found_abi
;
136 enum mips_fpu_type mips_fpu_type
;
137 int mips_last_arg_regnum
;
138 int mips_last_fp_arg_regnum
;
139 int mips_default_saved_regsize
;
140 int mips_fp_register_double
;
141 int mips_regs_have_home_p
;
142 int mips_default_stack_argsize
;
143 int gdb_target_is_mips64
;
144 int default_mask_address_p
;
146 enum gdb_osabi osabi
;
149 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
150 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
152 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
154 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
156 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
158 /* Return the currently configured (or set) saved register size. */
160 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
162 static const char *mips_saved_regsize_string
= size_auto
;
164 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
167 mips_saved_regsize (void)
169 if (mips_saved_regsize_string
== size_auto
)
170 return MIPS_DEFAULT_SAVED_REGSIZE
;
171 else if (mips_saved_regsize_string
== size_64
)
173 else /* if (mips_saved_regsize_string == size_32) */
177 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
178 compatiblity mode. A return value of 1 means that we have
179 physical 64-bit registers, but should treat them as 32-bit registers. */
182 mips2_fp_compat (void)
184 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
186 if (REGISTER_RAW_SIZE (FP0_REGNUM
) == 4)
190 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
191 in all the places we deal with FP registers. PR gdb/413. */
192 /* Otherwise check the FR bit in the status register - it controls
193 the FP compatiblity mode. If it is clear we are in compatibility
195 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
202 /* Indicate that the ABI makes use of double-precision registers
203 provided by the FPU (rather than combining pairs of registers to
204 form double-precision values). Do not use "TARGET_IS_MIPS64" to
205 determine if the ABI is using double-precision registers. See also
207 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
209 /* Does the caller allocate a ``home'' for each register used in the
210 function call? The N32 ABI and MIPS_EABI do not, the others do. */
212 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
214 /* The amount of space reserved on the stack for registers. This is
215 different to MIPS_SAVED_REGSIZE as it determines the alignment of
216 data allocated after the registers have run out. */
218 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
220 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
222 static const char *mips_stack_argsize_string
= size_auto
;
225 mips_stack_argsize (void)
227 if (mips_stack_argsize_string
== size_auto
)
228 return MIPS_DEFAULT_STACK_ARGSIZE
;
229 else if (mips_stack_argsize_string
== size_64
)
231 else /* if (mips_stack_argsize_string == size_32) */
235 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
237 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
239 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
241 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
243 static void mips_print_register (int, int);
245 static mips_extra_func_info_t
246 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*, int);
248 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
250 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
252 int mips_set_processor_type (char *);
254 static void mips_show_processor_type_command (char *, int);
256 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
258 static mips_extra_func_info_t
259 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
);
261 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
262 mips_extra_func_info_t proc_desc
);
264 static void mips_read_fp_register_single (int regno
, char *rare_buffer
);
265 static void mips_read_fp_register_double (int regno
, char *rare_buffer
);
267 static struct type
*mips_float_register_type (void);
268 static struct type
*mips_double_register_type (void);
270 /* This value is the model of MIPS in use. It is derived from the value
271 of the PrID register. */
273 char *mips_processor_type
;
275 char *tmp_mips_processor_type
;
277 /* The list of available "set mips " and "show mips " commands */
279 static struct cmd_list_element
*setmipscmdlist
= NULL
;
280 static struct cmd_list_element
*showmipscmdlist
= NULL
;
282 /* A set of original names, to be used when restoring back to generic
283 registers from a specific set. */
285 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
286 char **mips_processor_reg_names
= mips_generic_reg_names
;
289 mips_register_name (int i
)
291 return mips_processor_reg_names
[i
];
294 /* Names of IDT R3041 registers. */
296 char *mips_r3041_reg_names
[] = {
297 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
298 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
299 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
300 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
301 "sr", "lo", "hi", "bad", "cause","pc",
302 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
303 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
304 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
305 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
306 "fsr", "fir", "fp", "",
307 "", "", "bus", "ccfg", "", "", "", "",
308 "", "", "port", "cmp", "", "", "epc", "prid",
311 /* Names of IDT R3051 registers. */
313 char *mips_r3051_reg_names
[] = {
314 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
315 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
316 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
317 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
318 "sr", "lo", "hi", "bad", "cause","pc",
319 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
320 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
321 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
322 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
323 "fsr", "fir", "fp", "",
324 "inx", "rand", "elo", "", "ctxt", "", "", "",
325 "", "", "ehi", "", "", "", "epc", "prid",
328 /* Names of IDT R3081 registers. */
330 char *mips_r3081_reg_names
[] = {
331 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
332 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
333 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
334 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
335 "sr", "lo", "hi", "bad", "cause","pc",
336 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
337 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
338 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
339 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
340 "fsr", "fir", "fp", "",
341 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
342 "", "", "ehi", "", "", "", "epc", "prid",
345 /* Names of LSI 33k registers. */
347 char *mips_lsi33k_reg_names
[] = {
348 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
349 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
350 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
351 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
352 "epc", "hi", "lo", "sr", "cause","badvaddr",
353 "dcic", "bpc", "bda", "", "", "", "", "",
354 "", "", "", "", "", "", "", "",
355 "", "", "", "", "", "", "", "",
356 "", "", "", "", "", "", "", "",
358 "", "", "", "", "", "", "", "",
359 "", "", "", "", "", "", "", "",
365 } mips_processor_type_table
[] = {
366 { "generic", mips_generic_reg_names
},
367 { "r3041", mips_r3041_reg_names
},
368 { "r3051", mips_r3051_reg_names
},
369 { "r3071", mips_r3081_reg_names
},
370 { "r3081", mips_r3081_reg_names
},
371 { "lsi33k", mips_lsi33k_reg_names
},
379 /* Table to translate MIPS16 register field to actual register number. */
380 static int mips16_to_32_reg
[8] =
381 {16, 17, 2, 3, 4, 5, 6, 7};
383 /* Heuristic_proc_start may hunt through the text section for a long
384 time across a 2400 baud serial line. Allows the user to limit this
387 static unsigned int heuristic_fence_post
= 0;
389 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
390 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
391 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
392 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
393 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
394 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
395 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
396 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
397 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
398 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
399 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
400 this will corrupt pdr.iline. Fortunately we don't use it. */
401 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
402 #define _PROC_MAGIC_ 0x0F0F0F0F
403 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
404 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
406 struct linked_proc_info
408 struct mips_extra_func_info info
;
409 struct linked_proc_info
*next
;
411 *linked_proc_desc_table
= NULL
;
414 mips_print_extra_frame_info (struct frame_info
*fi
)
418 && fi
->extra_info
->proc_desc
419 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
420 printf_filtered (" frame pointer is at %s+%s\n",
421 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
422 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
425 /* Number of bytes of storage in the actual machine representation for
426 register N. NOTE: This indirectly defines the register size
427 transfered by the GDB protocol. */
429 static int mips64_transfers_32bit_regs_p
= 0;
432 mips_register_raw_size (int reg_nr
)
434 if (mips64_transfers_32bit_regs_p
)
435 return REGISTER_VIRTUAL_SIZE (reg_nr
);
436 else if (reg_nr
>= FP0_REGNUM
&& reg_nr
< FP0_REGNUM
+ 32
437 && FP_REGISTER_DOUBLE
)
438 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
445 /* Convert between RAW and VIRTUAL registers. The RAW register size
446 defines the remote-gdb packet. */
449 mips_register_convertible (int reg_nr
)
451 if (mips64_transfers_32bit_regs_p
)
454 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
458 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
459 char *raw_buf
, char *virt_buf
)
461 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
463 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
464 TYPE_LENGTH (virtual_type
));
468 TYPE_LENGTH (virtual_type
));
472 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
473 char *virt_buf
, char *raw_buf
)
475 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
476 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
477 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
479 TYPE_LENGTH (virtual_type
));
483 TYPE_LENGTH (virtual_type
));
486 /* Return the GDB type object for the "standard" data type
487 of data in register REG.
489 Note: kevinb/2002-08-01: The definition below should faithfully
490 reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE
491 definitions found in config/mips/tm-*.h. I'm concerned about
492 the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause
493 though. In some cases FP_REGNUM is in this range, and I doubt
494 that this code is correct for the 64-bit case. */
497 mips_register_virtual_type (int reg
)
499 if (FP0_REGNUM
<= reg
&& reg
< FP0_REGNUM
+ 32)
500 return builtin_type_double
;
501 else if (reg
== PS_REGNUM
/* CR */)
502 return builtin_type_uint32
;
503 else if (FCRCS_REGNUM
<= reg
&& reg
<= LAST_EMBED_REGNUM
)
504 return builtin_type_uint32
;
507 /* Everything else... return ``long long'' when registers
508 are 64-bits wide, ``int'' otherwise. */
509 if (MIPS_REGSIZE
== TYPE_LENGTH (builtin_type_long_long
))
510 return builtin_type_long_long
;
512 return builtin_type_int
;
516 /* Should the upper word of 64-bit addresses be zeroed? */
517 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
520 mips_mask_address_p (void)
522 switch (mask_address_var
)
524 case AUTO_BOOLEAN_TRUE
:
526 case AUTO_BOOLEAN_FALSE
:
529 case AUTO_BOOLEAN_AUTO
:
530 return MIPS_DEFAULT_MASK_ADDRESS_P
;
532 internal_error (__FILE__
, __LINE__
,
533 "mips_mask_address_p: bad switch");
539 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
541 switch (mask_address_var
)
543 case AUTO_BOOLEAN_TRUE
:
544 printf_filtered ("The 32 bit mips address mask is enabled\n");
546 case AUTO_BOOLEAN_FALSE
:
547 printf_filtered ("The 32 bit mips address mask is disabled\n");
549 case AUTO_BOOLEAN_AUTO
:
550 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
551 mips_mask_address_p () ? "enabled" : "disabled");
554 internal_error (__FILE__
, __LINE__
,
555 "show_mask_address: bad switch");
560 /* Should call_function allocate stack space for a struct return? */
562 mips_use_struct_convention (int gcc_p
, struct type
*type
)
565 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
567 return 1; /* Structures are returned by ref in extra arg0 */
570 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
573 pc_is_mips16 (bfd_vma memaddr
)
575 struct minimal_symbol
*sym
;
577 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
578 if (IS_MIPS16_ADDR (memaddr
))
581 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
582 the high bit of the info field. Use this to decide if the function is
583 MIPS16 or normal MIPS. */
584 sym
= lookup_minimal_symbol_by_pc (memaddr
);
586 return MSYMBOL_IS_SPECIAL (sym
);
591 /* MIPS believes that the PC has a sign extended value. Perhaphs the
592 all registers should be sign extended for simplicity? */
595 mips_read_pc (ptid_t ptid
)
597 return read_signed_register_pid (PC_REGNUM
, ptid
);
600 /* This returns the PC of the first inst after the prologue. If we can't
601 find the prologue, then return 0. */
604 after_prologue (CORE_ADDR pc
,
605 mips_extra_func_info_t proc_desc
)
607 struct symtab_and_line sal
;
608 CORE_ADDR func_addr
, func_end
;
610 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
611 to read the stack pointer from the current machine state, because
612 the current machine state has nothing to do with the information
613 we need from the proc_desc; and the process may or may not exist
616 proc_desc
= find_proc_desc (pc
, NULL
, 0);
620 /* If function is frameless, then we need to do it the hard way. I
621 strongly suspect that frameless always means prologueless... */
622 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
623 && PROC_FRAME_OFFSET (proc_desc
) == 0)
627 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
628 return 0; /* Unknown */
630 sal
= find_pc_line (func_addr
, 0);
632 if (sal
.end
< func_end
)
635 /* The line after the prologue is after the end of the function. In this
636 case, tell the caller to find the prologue the hard way. */
641 /* Decode a MIPS32 instruction that saves a register in the stack, and
642 set the appropriate bit in the general register mask or float register mask
643 to indicate which register is saved. This is a helper function
644 for mips_find_saved_regs. */
647 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
648 unsigned long *float_mask
)
652 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
653 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
654 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
656 /* It might be possible to use the instruction to
657 find the offset, rather than the code below which
658 is based on things being in a certain order in the
659 frame, but figuring out what the instruction's offset
660 is relative to might be a little tricky. */
661 reg
= (inst
& 0x001f0000) >> 16;
662 *gen_mask
|= (1 << reg
);
664 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
665 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
666 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
669 reg
= ((inst
& 0x001f0000) >> 16);
670 *float_mask
|= (1 << reg
);
674 /* Decode a MIPS16 instruction that saves a register in the stack, and
675 set the appropriate bit in the general register or float register mask
676 to indicate which register is saved. This is a helper function
677 for mips_find_saved_regs. */
680 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
682 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
684 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
685 *gen_mask
|= (1 << reg
);
687 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
689 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
690 *gen_mask
|= (1 << reg
);
692 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
693 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
694 *gen_mask
|= (1 << RA_REGNUM
);
698 /* Fetch and return instruction from the specified location. If the PC
699 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
702 mips_fetch_instruction (CORE_ADDR addr
)
704 char buf
[MIPS_INSTLEN
];
708 if (pc_is_mips16 (addr
))
710 instlen
= MIPS16_INSTLEN
;
711 addr
= UNMAKE_MIPS16_ADDR (addr
);
714 instlen
= MIPS_INSTLEN
;
715 status
= read_memory_nobpt (addr
, buf
, instlen
);
717 memory_error (status
, addr
);
718 return extract_unsigned_integer (buf
, instlen
);
722 /* These the fields of 32 bit mips instructions */
723 #define mips32_op(x) (x >> 26)
724 #define itype_op(x) (x >> 26)
725 #define itype_rs(x) ((x >> 21) & 0x1f)
726 #define itype_rt(x) ((x >> 16) & 0x1f)
727 #define itype_immediate(x) (x & 0xffff)
729 #define jtype_op(x) (x >> 26)
730 #define jtype_target(x) (x & 0x03ffffff)
732 #define rtype_op(x) (x >> 26)
733 #define rtype_rs(x) ((x >> 21) & 0x1f)
734 #define rtype_rt(x) ((x >> 16) & 0x1f)
735 #define rtype_rd(x) ((x >> 11) & 0x1f)
736 #define rtype_shamt(x) ((x >> 6) & 0x1f)
737 #define rtype_funct(x) (x & 0x3f)
740 mips32_relative_offset (unsigned long inst
)
743 x
= itype_immediate (inst
);
744 if (x
& 0x8000) /* sign bit set */
746 x
|= 0xffff0000; /* sign extension */
752 /* Determine whate to set a single step breakpoint while considering
755 mips32_next_pc (CORE_ADDR pc
)
759 inst
= mips_fetch_instruction (pc
);
760 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
762 if (itype_op (inst
) >> 2 == 5)
763 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
765 op
= (itype_op (inst
) & 0x03);
780 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
781 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
783 int tf
= itype_rt (inst
) & 0x01;
784 int cnum
= itype_rt (inst
) >> 2;
785 int fcrcs
= read_signed_register (FCRCS_REGNUM
);
786 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
788 if (((cond
>> cnum
) & 0x01) == tf
)
789 pc
+= mips32_relative_offset (inst
) + 4;
794 pc
+= 4; /* Not a branch, next instruction is easy */
797 { /* This gets way messy */
799 /* Further subdivide into SPECIAL, REGIMM and other */
800 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
802 case 0: /* SPECIAL */
803 op
= rtype_funct (inst
);
808 /* Set PC to that address */
809 pc
= read_signed_register (rtype_rs (inst
));
815 break; /* end SPECIAL */
818 op
= itype_rt (inst
); /* branch condition */
823 case 16: /* BLTZAL */
824 case 18: /* BLTZALL */
826 if (read_signed_register (itype_rs (inst
)) < 0)
827 pc
+= mips32_relative_offset (inst
) + 4;
829 pc
+= 8; /* after the delay slot */
833 case 17: /* BGEZAL */
834 case 19: /* BGEZALL */
835 greater_equal_branch
:
836 if (read_signed_register (itype_rs (inst
)) >= 0)
837 pc
+= mips32_relative_offset (inst
) + 4;
839 pc
+= 8; /* after the delay slot */
841 /* All of the other instructions in the REGIMM category */
846 break; /* end REGIMM */
851 reg
= jtype_target (inst
) << 2;
852 /* Upper four bits get never changed... */
853 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
856 /* FIXME case JALX : */
859 reg
= jtype_target (inst
) << 2;
860 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
861 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
863 break; /* The new PC will be alternate mode */
864 case 4: /* BEQ, BEQL */
866 if (read_signed_register (itype_rs (inst
)) ==
867 read_signed_register (itype_rt (inst
)))
868 pc
+= mips32_relative_offset (inst
) + 4;
872 case 5: /* BNE, BNEL */
874 if (read_signed_register (itype_rs (inst
)) !=
875 read_signed_register (itype_rt (inst
)))
876 pc
+= mips32_relative_offset (inst
) + 4;
880 case 6: /* BLEZ, BLEZL */
882 if (read_signed_register (itype_rs (inst
) <= 0))
883 pc
+= mips32_relative_offset (inst
) + 4;
889 greater_branch
: /* BGTZ, BGTZL */
890 if (read_signed_register (itype_rs (inst
) > 0))
891 pc
+= mips32_relative_offset (inst
) + 4;
898 } /* mips32_next_pc */
900 /* Decoding the next place to set a breakpoint is irregular for the
901 mips 16 variant, but fortunately, there fewer instructions. We have to cope
902 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
903 We dont want to set a single step instruction on the extend instruction
907 /* Lots of mips16 instruction formats */
908 /* Predicting jumps requires itype,ritype,i8type
909 and their extensions extItype,extritype,extI8type
911 enum mips16_inst_fmts
913 itype
, /* 0 immediate 5,10 */
914 ritype
, /* 1 5,3,8 */
915 rrtype
, /* 2 5,3,3,5 */
916 rritype
, /* 3 5,3,3,5 */
917 rrrtype
, /* 4 5,3,3,3,2 */
918 rriatype
, /* 5 5,3,3,1,4 */
919 shifttype
, /* 6 5,3,3,3,2 */
920 i8type
, /* 7 5,3,8 */
921 i8movtype
, /* 8 5,3,3,5 */
922 i8mov32rtype
, /* 9 5,3,5,3 */
923 i64type
, /* 10 5,3,8 */
924 ri64type
, /* 11 5,3,3,5 */
925 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
926 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
927 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
928 extRRItype
, /* 15 5,5,5,5,3,3,5 */
929 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
930 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
931 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
932 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
933 extRi64type
, /* 20 5,6,5,5,3,3,5 */
934 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
936 /* I am heaping all the fields of the formats into one structure and
937 then, only the fields which are involved in instruction extension */
941 unsigned int regx
; /* Function in i8 type */
946 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
947 for the bits which make up the immediatate extension. */
950 extended_offset (unsigned int extension
)
953 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
955 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
957 value
|= extension
& 0x01f; /* extract 4:0 */
961 /* Only call this function if you know that this is an extendable
962 instruction, It wont malfunction, but why make excess remote memory references?
963 If the immediate operands get sign extended or somthing, do it after
964 the extension is performed.
966 /* FIXME: Every one of these cases needs to worry about sign extension
967 when the offset is to be used in relative addressing */
971 fetch_mips_16 (CORE_ADDR pc
)
974 pc
&= 0xfffffffe; /* clear the low order bit */
975 target_read_memory (pc
, buf
, 2);
976 return extract_unsigned_integer (buf
, 2);
980 unpack_mips16 (CORE_ADDR pc
,
981 unsigned int extension
,
983 enum mips16_inst_fmts insn_format
,
984 struct upk_mips16
*upk
)
996 value
= extended_offset (extension
);
997 value
= value
<< 11; /* rom for the original value */
998 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1002 value
= inst
& 0x7ff;
1003 /* FIXME : Consider sign extension */
1012 { /* A register identifier and an offset */
1013 /* Most of the fields are the same as I type but the
1014 immediate value is of a different length */
1018 value
= extended_offset (extension
);
1019 value
= value
<< 8; /* from the original instruction */
1020 value
|= inst
& 0xff; /* eleven bits from instruction */
1021 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1022 if (value
& 0x4000) /* test the sign bit , bit 26 */
1024 value
&= ~0x3fff; /* remove the sign bit */
1030 value
= inst
& 0xff; /* 8 bits */
1031 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1032 /* FIXME: Do sign extension , this format needs it */
1033 if (value
& 0x80) /* THIS CONFUSES ME */
1035 value
&= 0xef; /* remove the sign bit */
1045 unsigned long value
;
1046 unsigned int nexthalf
;
1047 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1048 value
= value
<< 16;
1049 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1057 internal_error (__FILE__
, __LINE__
,
1060 upk
->offset
= offset
;
1067 add_offset_16 (CORE_ADDR pc
, int offset
)
1069 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1074 extended_mips16_next_pc (CORE_ADDR pc
,
1075 unsigned int extension
,
1078 int op
= (insn
>> 11);
1081 case 2: /* Branch */
1084 struct upk_mips16 upk
;
1085 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1086 offset
= upk
.offset
;
1092 pc
+= (offset
<< 1) + 2;
1095 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1097 struct upk_mips16 upk
;
1098 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1099 pc
= add_offset_16 (pc
, upk
.offset
);
1100 if ((insn
>> 10) & 0x01) /* Exchange mode */
1101 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1108 struct upk_mips16 upk
;
1110 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1111 reg
= read_signed_register (upk
.regx
);
1113 pc
+= (upk
.offset
<< 1) + 2;
1120 struct upk_mips16 upk
;
1122 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1123 reg
= read_signed_register (upk
.regx
);
1125 pc
+= (upk
.offset
<< 1) + 2;
1130 case 12: /* I8 Formats btez btnez */
1132 struct upk_mips16 upk
;
1134 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1135 /* upk.regx contains the opcode */
1136 reg
= read_signed_register (24); /* Test register is 24 */
1137 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1138 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1139 /* pc = add_offset_16(pc,upk.offset) ; */
1140 pc
+= (upk
.offset
<< 1) + 2;
1145 case 29: /* RR Formats JR, JALR, JALR-RA */
1147 struct upk_mips16 upk
;
1148 /* upk.fmt = rrtype; */
1153 upk
.regx
= (insn
>> 8) & 0x07;
1154 upk
.regy
= (insn
>> 5) & 0x07;
1162 break; /* Function return instruction */
1168 break; /* BOGUS Guess */
1170 pc
= read_signed_register (reg
);
1177 /* This is an instruction extension. Fetch the real instruction
1178 (which follows the extension) and decode things based on
1182 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1195 mips16_next_pc (CORE_ADDR pc
)
1197 unsigned int insn
= fetch_mips_16 (pc
);
1198 return extended_mips16_next_pc (pc
, 0, insn
);
1201 /* The mips_next_pc function supports single_step when the remote
1202 target monitor or stub is not developed enough to do a single_step.
1203 It works by decoding the current instruction and predicting where a
1204 branch will go. This isnt hard because all the data is available.
1205 The MIPS32 and MIPS16 variants are quite different */
1207 mips_next_pc (CORE_ADDR pc
)
1210 return mips16_next_pc (pc
);
1212 return mips32_next_pc (pc
);
1215 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1219 mips_find_saved_regs (struct frame_info
*fci
)
1222 CORE_ADDR reg_position
;
1223 /* r0 bit means kernel trap */
1225 /* What registers have been saved? Bitmasks. */
1226 unsigned long gen_mask
, float_mask
;
1227 mips_extra_func_info_t proc_desc
;
1230 frame_saved_regs_zalloc (fci
);
1232 /* If it is the frame for sigtramp, the saved registers are located
1233 in a sigcontext structure somewhere on the stack.
1234 If the stack layout for sigtramp changes we might have to change these
1235 constants and the companion fixup_sigtramp in mdebugread.c */
1236 #ifndef SIGFRAME_BASE
1237 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1238 above the sigtramp frame. */
1239 #define SIGFRAME_BASE MIPS_REGSIZE
1240 /* FIXME! Are these correct?? */
1241 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1242 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1243 #define SIGFRAME_FPREGSAVE_OFF \
1244 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1246 #ifndef SIGFRAME_REG_SIZE
1247 /* FIXME! Is this correct?? */
1248 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1250 if (fci
->signal_handler_caller
)
1252 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1254 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1255 + ireg
* SIGFRAME_REG_SIZE
;
1256 fci
->saved_regs
[ireg
] = reg_position
;
1258 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1260 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1261 + ireg
* SIGFRAME_REG_SIZE
;
1262 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1264 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1268 proc_desc
= fci
->extra_info
->proc_desc
;
1269 if (proc_desc
== NULL
)
1270 /* I'm not sure how/whether this can happen. Normally when we can't
1271 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1272 and set the saved_regs right away. */
1275 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1276 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1277 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1279 if ( /* In any frame other than the innermost or a frame interrupted by
1280 a signal, we assume that all registers have been saved.
1281 This assumes that all register saves in a function happen before
1282 the first function call. */
1283 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1285 /* In a dummy frame we know exactly where things are saved. */
1286 && !PROC_DESC_IS_DUMMY (proc_desc
)
1288 /* Don't bother unless we are inside a function prologue. Outside the
1289 prologue, we know where everything is. */
1291 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1293 /* Not sure exactly what kernel_trap means, but if it means
1294 the kernel saves the registers without a prologue doing it,
1295 we better not examine the prologue to see whether registers
1296 have been saved yet. */
1299 /* We need to figure out whether the registers that the proc_desc
1300 claims are saved have been saved yet. */
1304 /* Bitmasks; set if we have found a save for the register. */
1305 unsigned long gen_save_found
= 0;
1306 unsigned long float_save_found
= 0;
1309 /* If the address is odd, assume this is MIPS16 code. */
1310 addr
= PROC_LOW_ADDR (proc_desc
);
1311 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1313 /* Scan through this function's instructions preceding the current
1314 PC, and look for those that save registers. */
1315 while (addr
< fci
->pc
)
1317 inst
= mips_fetch_instruction (addr
);
1318 if (pc_is_mips16 (addr
))
1319 mips16_decode_reg_save (inst
, &gen_save_found
);
1321 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1324 gen_mask
= gen_save_found
;
1325 float_mask
= float_save_found
;
1328 /* Fill in the offsets for the registers which gen_mask says
1330 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1331 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1332 if (gen_mask
& 0x80000000)
1334 fci
->saved_regs
[ireg
] = reg_position
;
1335 reg_position
-= MIPS_SAVED_REGSIZE
;
1338 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1339 of that normally used by gcc. Therefore, we have to fetch the first
1340 instruction of the function, and if it's an entry instruction that
1341 saves $s0 or $s1, correct their saved addresses. */
1342 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1344 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1345 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1348 int sreg_count
= (inst
>> 6) & 3;
1350 /* Check if the ra register was pushed on the stack. */
1351 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1353 reg_position
-= MIPS_SAVED_REGSIZE
;
1355 /* Check if the s0 and s1 registers were pushed on the stack. */
1356 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1358 fci
->saved_regs
[reg
] = reg_position
;
1359 reg_position
-= MIPS_SAVED_REGSIZE
;
1364 /* Fill in the offsets for the registers which float_mask says
1366 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1368 /* The freg_offset points to where the first *double* register
1369 is saved. So skip to the high-order word. */
1370 if (!GDB_TARGET_IS_MIPS64
)
1371 reg_position
+= MIPS_SAVED_REGSIZE
;
1373 /* Fill in the offsets for the float registers which float_mask says
1375 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1376 if (float_mask
& 0x80000000)
1378 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1379 reg_position
-= MIPS_SAVED_REGSIZE
;
1382 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1386 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1388 for (; fi
; fi
= fi
->next
)
1390 /* We have to get the saved sp from the sigcontext
1391 if it is a signal handler frame. */
1392 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1396 if (fi
->saved_regs
== NULL
)
1397 mips_find_saved_regs (fi
);
1398 if (fi
->saved_regs
[regno
])
1399 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1402 return read_signed_register (regno
);
1405 /* mips_addr_bits_remove - remove useless address bits */
1408 mips_addr_bits_remove (CORE_ADDR addr
)
1410 if (GDB_TARGET_IS_MIPS64
)
1412 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1414 /* This hack is a work-around for existing boards using
1415 PMON, the simulator, and any other 64-bit targets that
1416 doesn't have true 64-bit addressing. On these targets,
1417 the upper 32 bits of addresses are ignored by the
1418 hardware. Thus, the PC or SP are likely to have been
1419 sign extended to all 1s by instruction sequences that
1420 load 32-bit addresses. For example, a typical piece of
1421 code that loads an address is this:
1422 lui $r2, <upper 16 bits>
1423 ori $r2, <lower 16 bits>
1424 But the lui sign-extends the value such that the upper 32
1425 bits may be all 1s. The workaround is simply to mask off
1426 these bits. In the future, gcc may be changed to support
1427 true 64-bit addressing, and this masking will have to be
1429 addr
&= (CORE_ADDR
) 0xffffffff;
1432 else if (mips_mask_address_p ())
1434 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1435 masking off bits, instead, the actual target should be asking
1436 for the address to be converted to a valid pointer. */
1437 /* Even when GDB is configured for some 32-bit targets
1438 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1439 so CORE_ADDR is 64 bits. So we still have to mask off
1440 useless bits from addresses. */
1441 addr
&= (CORE_ADDR
) 0xffffffff;
1446 /* mips_software_single_step() is called just before we want to resume
1447 the inferior, if we want to single-step it but there is no hardware
1448 or kernel single-step support (MIPS on GNU/Linux for example). We find
1449 the target of the coming instruction and breakpoint it.
1451 single_step is also called just after the inferior stops. If we had
1452 set up a simulated single-step, we undo our damage. */
1455 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1457 static CORE_ADDR next_pc
;
1458 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1459 static binsn_quantum break_mem
;
1462 if (insert_breakpoints_p
)
1464 pc
= read_register (PC_REGNUM
);
1465 next_pc
= mips_next_pc (pc
);
1467 target_insert_breakpoint (next_pc
, break_mem
);
1470 target_remove_breakpoint (next_pc
, break_mem
);
1474 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1478 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1479 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1480 tmp
= mips_skip_stub (pc
);
1481 prev
->pc
= tmp
? tmp
: pc
;
1486 mips_frame_saved_pc (struct frame_info
*frame
)
1489 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1490 /* We have to get the saved pc from the sigcontext
1491 if it is a signal handler frame. */
1492 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1493 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1495 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1496 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1498 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1500 return ADDR_BITS_REMOVE (saved_pc
);
1503 static struct mips_extra_func_info temp_proc_desc
;
1504 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1506 /* Set a register's saved stack address in temp_saved_regs. If an address
1507 has already been set for this register, do nothing; this way we will
1508 only recognize the first save of a given register in a function prologue.
1509 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1512 set_reg_offset (int regno
, CORE_ADDR offset
)
1514 if (temp_saved_regs
[regno
] == 0)
1515 temp_saved_regs
[regno
] = offset
;
1519 /* Test whether the PC points to the return instruction at the
1520 end of a function. */
1523 mips_about_to_return (CORE_ADDR pc
)
1525 if (pc_is_mips16 (pc
))
1526 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1527 generates a "jr $ra"; other times it generates code to load
1528 the return address from the stack to an accessible register (such
1529 as $a3), then a "jr" using that register. This second case
1530 is almost impossible to distinguish from an indirect jump
1531 used for switch statements, so we don't even try. */
1532 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1534 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1538 /* This fencepost looks highly suspicious to me. Removing it also
1539 seems suspicious as it could affect remote debugging across serial
1543 heuristic_proc_start (CORE_ADDR pc
)
1550 pc
= ADDR_BITS_REMOVE (pc
);
1552 fence
= start_pc
- heuristic_fence_post
;
1556 if (heuristic_fence_post
== UINT_MAX
1557 || fence
< VM_MIN_ADDRESS
)
1558 fence
= VM_MIN_ADDRESS
;
1560 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1562 /* search back for previous return */
1563 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1564 if (start_pc
< fence
)
1566 /* It's not clear to me why we reach this point when
1567 stop_soon_quietly, but with this test, at least we
1568 don't print out warnings for every child forked (eg, on
1569 decstation). 22apr93 rich@cygnus.com. */
1570 if (!stop_soon_quietly
)
1572 static int blurb_printed
= 0;
1574 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1579 /* This actually happens frequently in embedded
1580 development, when you first connect to a board
1581 and your stack pointer and pc are nowhere in
1582 particular. This message needs to give people
1583 in that situation enough information to
1584 determine that it's no big deal. */
1585 printf_filtered ("\n\
1586 GDB is unable to find the start of the function at 0x%s\n\
1587 and thus can't determine the size of that function's stack frame.\n\
1588 This means that GDB may be unable to access that stack frame, or\n\
1589 the frames below it.\n\
1590 This problem is most likely caused by an invalid program counter or\n\
1592 However, if you think GDB should simply search farther back\n\
1593 from 0x%s for code which looks like the beginning of a\n\
1594 function, you can increase the range of the search using the `set\n\
1595 heuristic-fence-post' command.\n",
1596 paddr_nz (pc
), paddr_nz (pc
));
1603 else if (pc_is_mips16 (start_pc
))
1605 unsigned short inst
;
1607 /* On MIPS16, any one of the following is likely to be the
1608 start of a function:
1612 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1613 inst
= mips_fetch_instruction (start_pc
);
1614 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1615 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1616 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1617 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1619 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1620 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1625 else if (mips_about_to_return (start_pc
))
1627 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1634 /* Fetch the immediate value from a MIPS16 instruction.
1635 If the previous instruction was an EXTEND, use it to extend
1636 the upper bits of the immediate value. This is a helper function
1637 for mips16_heuristic_proc_desc. */
1640 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1641 unsigned short inst
, /* current instruction */
1642 int nbits
, /* number of bits in imm field */
1643 int scale
, /* scale factor to be applied to imm */
1644 int is_signed
) /* is the imm field signed? */
1648 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1650 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1651 if (offset
& 0x8000) /* check for negative extend */
1652 offset
= 0 - (0x10000 - (offset
& 0xffff));
1653 return offset
| (inst
& 0x1f);
1657 int max_imm
= 1 << nbits
;
1658 int mask
= max_imm
- 1;
1659 int sign_bit
= max_imm
>> 1;
1661 offset
= inst
& mask
;
1662 if (is_signed
&& (offset
& sign_bit
))
1663 offset
= 0 - (max_imm
- offset
);
1664 return offset
* scale
;
1669 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1670 stream from start_pc to limit_pc. */
1673 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1674 struct frame_info
*next_frame
, CORE_ADDR sp
)
1677 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1678 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1679 unsigned inst
= 0; /* current instruction */
1680 unsigned entry_inst
= 0; /* the entry instruction */
1683 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1684 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1686 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1688 /* Save the previous instruction. If it's an EXTEND, we'll extract
1689 the immediate offset extension from it in mips16_get_imm. */
1692 /* Fetch and decode the instruction. */
1693 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1694 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1695 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1697 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1698 if (offset
< 0) /* negative stack adjustment? */
1699 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1701 /* Exit loop if a positive stack adjustment is found, which
1702 usually means that the stack cleanup code in the function
1703 epilogue is reached. */
1706 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1708 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1709 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1710 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1711 set_reg_offset (reg
, sp
+ offset
);
1713 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1715 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1716 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1717 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1718 set_reg_offset (reg
, sp
+ offset
);
1720 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1722 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1723 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1724 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1726 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1728 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1729 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1730 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1732 else if (inst
== 0x673d) /* move $s1, $sp */
1735 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1737 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1739 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1740 frame_addr
= sp
+ offset
;
1741 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1742 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1744 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1746 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1747 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1748 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1749 set_reg_offset (reg
, frame_addr
+ offset
);
1751 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1753 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1754 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1755 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1756 set_reg_offset (reg
, frame_addr
+ offset
);
1758 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1759 entry_inst
= inst
; /* save for later processing */
1760 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1761 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1764 /* The entry instruction is typically the first instruction in a function,
1765 and it stores registers at offsets relative to the value of the old SP
1766 (before the prologue). But the value of the sp parameter to this
1767 function is the new SP (after the prologue has been executed). So we
1768 can't calculate those offsets until we've seen the entire prologue,
1769 and can calculate what the old SP must have been. */
1770 if (entry_inst
!= 0)
1772 int areg_count
= (entry_inst
>> 8) & 7;
1773 int sreg_count
= (entry_inst
>> 6) & 3;
1775 /* The entry instruction always subtracts 32 from the SP. */
1776 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1778 /* Now we can calculate what the SP must have been at the
1779 start of the function prologue. */
1780 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1782 /* Check if a0-a3 were saved in the caller's argument save area. */
1783 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1785 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1786 set_reg_offset (reg
, sp
+ offset
);
1787 offset
+= MIPS_SAVED_REGSIZE
;
1790 /* Check if the ra register was pushed on the stack. */
1792 if (entry_inst
& 0x20)
1794 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1795 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1796 offset
-= MIPS_SAVED_REGSIZE
;
1799 /* Check if the s0 and s1 registers were pushed on the stack. */
1800 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1802 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1803 set_reg_offset (reg
, sp
+ offset
);
1804 offset
-= MIPS_SAVED_REGSIZE
;
1810 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1811 struct frame_info
*next_frame
, CORE_ADDR sp
)
1814 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1816 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1817 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1818 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1819 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1821 unsigned long inst
, high_word
, low_word
;
1824 /* Fetch the instruction. */
1825 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1827 /* Save some code by pre-extracting some useful fields. */
1828 high_word
= (inst
>> 16) & 0xffff;
1829 low_word
= inst
& 0xffff;
1830 reg
= high_word
& 0x1f;
1832 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1833 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1834 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1836 if (low_word
& 0x8000) /* negative stack adjustment? */
1837 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1839 /* Exit loop if a positive stack adjustment is found, which
1840 usually means that the stack cleanup code in the function
1841 epilogue is reached. */
1844 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1846 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1847 set_reg_offset (reg
, sp
+ low_word
);
1849 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1851 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1852 but the register size used is only 32 bits. Make the address
1853 for the saved register point to the lower 32 bits. */
1854 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1855 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1857 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1859 /* Old gcc frame, r30 is virtual frame pointer. */
1860 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1861 frame_addr
= sp
+ low_word
;
1862 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1864 unsigned alloca_adjust
;
1865 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1866 frame_addr
= read_next_frame_reg (next_frame
, 30);
1867 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1868 if (alloca_adjust
> 0)
1870 /* FP > SP + frame_size. This may be because
1871 * of an alloca or somethings similar.
1872 * Fix sp to "pre-alloca" value, and try again.
1874 sp
+= alloca_adjust
;
1879 /* move $30,$sp. With different versions of gas this will be either
1880 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1881 Accept any one of these. */
1882 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1884 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1885 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1887 unsigned alloca_adjust
;
1888 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1889 frame_addr
= read_next_frame_reg (next_frame
, 30);
1890 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1891 if (alloca_adjust
> 0)
1893 /* FP > SP + frame_size. This may be because
1894 * of an alloca or somethings similar.
1895 * Fix sp to "pre-alloca" value, and try again.
1897 sp
+= alloca_adjust
;
1902 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1904 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1905 set_reg_offset (reg
, frame_addr
+ low_word
);
1910 static mips_extra_func_info_t
1911 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1912 struct frame_info
*next_frame
, int cur_frame
)
1917 sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1923 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1924 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1925 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1926 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1927 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1929 if (start_pc
+ 200 < limit_pc
)
1930 limit_pc
= start_pc
+ 200;
1931 if (pc_is_mips16 (start_pc
))
1932 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1934 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1935 return &temp_proc_desc
;
1938 struct mips_objfile_private
1944 /* Global used to communicate between non_heuristic_proc_desc and
1945 compare_pdr_entries within qsort (). */
1946 static bfd
*the_bfd
;
1949 compare_pdr_entries (const void *a
, const void *b
)
1951 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
1952 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
1956 else if (lhs
== rhs
)
1962 static mips_extra_func_info_t
1963 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
1965 CORE_ADDR startaddr
;
1966 mips_extra_func_info_t proc_desc
;
1967 struct block
*b
= block_for_pc (pc
);
1969 struct obj_section
*sec
;
1970 struct mips_objfile_private
*priv
;
1972 if (PC_IN_CALL_DUMMY (pc
, 0, 0))
1975 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1977 *addrptr
= startaddr
;
1981 sec
= find_pc_section (pc
);
1984 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
1986 /* Search the ".pdr" section generated by GAS. This includes most of
1987 the information normally found in ECOFF PDRs. */
1989 the_bfd
= sec
->objfile
->obfd
;
1991 && (the_bfd
->format
== bfd_object
1992 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
1993 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
1995 /* Right now GAS only outputs the address as a four-byte sequence.
1996 This means that we should not bother with this method on 64-bit
1997 targets (until that is fixed). */
1999 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2000 sizeof (struct mips_objfile_private
));
2002 sec
->objfile
->obj_private
= priv
;
2004 else if (priv
== NULL
)
2008 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2009 sizeof (struct mips_objfile_private
));
2011 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2014 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2015 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2017 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2018 priv
->contents
, 0, priv
->size
);
2020 /* In general, the .pdr section is sorted. However, in the
2021 presence of multiple code sections (and other corner cases)
2022 it can become unsorted. Sort it so that we can use a faster
2024 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
2029 sec
->objfile
->obj_private
= priv
;
2033 if (priv
->size
!= 0)
2039 high
= priv
->size
/ 32;
2045 mid
= (low
+ high
) / 2;
2047 ptr
= priv
->contents
+ mid
* 32;
2048 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2049 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2050 SECT_OFF_TEXT (sec
->objfile
));
2051 if (pdr_pc
== startaddr
)
2053 if (pdr_pc
> startaddr
)
2058 while (low
!= high
);
2062 struct symbol
*sym
= find_pc_function (pc
);
2064 /* Fill in what we need of the proc_desc. */
2065 proc_desc
= (mips_extra_func_info_t
)
2066 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2067 sizeof (struct mips_extra_func_info
));
2068 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2070 /* Only used for dummy frames. */
2071 PROC_HIGH_ADDR (proc_desc
) = 0;
2073 PROC_FRAME_OFFSET (proc_desc
)
2074 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2075 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2077 PROC_FRAME_ADJUST (proc_desc
) = 0;
2078 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2080 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2082 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2084 PROC_FREG_OFFSET (proc_desc
)
2085 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2086 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2088 proc_desc
->pdr
.isym
= (long) sym
;
2098 if (startaddr
> BLOCK_START (b
))
2100 /* This is the "pathological" case referred to in a comment in
2101 print_frame_info. It might be better to move this check into
2106 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
2108 /* If we never found a PDR for this function in symbol reading, then
2109 examine prologues to find the information. */
2112 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2113 if (PROC_FRAME_REG (proc_desc
) == -1)
2123 static mips_extra_func_info_t
2124 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2126 mips_extra_func_info_t proc_desc
;
2127 CORE_ADDR startaddr
;
2129 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2133 /* IF this is the topmost frame AND
2134 * (this proc does not have debugging information OR
2135 * the PC is in the procedure prologue)
2136 * THEN create a "heuristic" proc_desc (by analyzing
2137 * the actual code) to replace the "official" proc_desc.
2139 if (next_frame
== NULL
)
2141 struct symtab_and_line val
;
2142 struct symbol
*proc_symbol
=
2143 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2147 val
= find_pc_line (BLOCK_START
2148 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2150 val
.pc
= val
.end
? val
.end
: pc
;
2152 if (!proc_symbol
|| pc
< val
.pc
)
2154 mips_extra_func_info_t found_heuristic
=
2155 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2156 pc
, next_frame
, cur_frame
);
2157 if (found_heuristic
)
2158 proc_desc
= found_heuristic
;
2164 /* Is linked_proc_desc_table really necessary? It only seems to be used
2165 by procedure call dummys. However, the procedures being called ought
2166 to have their own proc_descs, and even if they don't,
2167 heuristic_proc_desc knows how to create them! */
2169 register struct linked_proc_info
*link
;
2171 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2172 if (PROC_LOW_ADDR (&link
->info
) <= pc
2173 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2177 startaddr
= heuristic_proc_start (pc
);
2180 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2186 get_frame_pointer (struct frame_info
*frame
,
2187 mips_extra_func_info_t proc_desc
)
2189 return ADDR_BITS_REMOVE (
2190 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
2191 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2194 mips_extra_func_info_t cached_proc_desc
;
2197 mips_frame_chain (struct frame_info
*frame
)
2199 mips_extra_func_info_t proc_desc
;
2201 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
2203 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
2206 /* Check if the PC is inside a call stub. If it is, fetch the
2207 PC of the caller of that stub. */
2208 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
2211 /* Look up the procedure descriptor for this PC. */
2212 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2216 cached_proc_desc
= proc_desc
;
2218 /* If no frame pointer and frame size is zero, we must be at end
2219 of stack (or otherwise hosed). If we don't check frame size,
2220 we loop forever if we see a zero size frame. */
2221 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2222 && PROC_FRAME_OFFSET (proc_desc
) == 0
2223 /* The previous frame from a sigtramp frame might be frameless
2224 and have frame size zero. */
2225 && !frame
->signal_handler_caller
)
2228 return get_frame_pointer (frame
, proc_desc
);
2232 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2236 /* Use proc_desc calculated in frame_chain */
2237 mips_extra_func_info_t proc_desc
=
2238 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
, 1);
2240 fci
->extra_info
= (struct frame_extra_info
*)
2241 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2243 fci
->saved_regs
= NULL
;
2244 fci
->extra_info
->proc_desc
=
2245 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2248 /* Fixup frame-pointer - only needed for top frame */
2249 /* This may not be quite right, if proc has a real frame register.
2250 Get the value of the frame relative sp, procedure might have been
2251 interrupted by a signal at it's very start. */
2252 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2253 && !PROC_DESC_IS_DUMMY (proc_desc
))
2254 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2256 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2258 if (proc_desc
== &temp_proc_desc
)
2262 /* Do not set the saved registers for a sigtramp frame,
2263 mips_find_saved_registers will do that for us.
2264 We can't use fci->signal_handler_caller, it is not yet set. */
2265 find_pc_partial_function (fci
->pc
, &name
,
2266 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2267 if (!PC_IN_SIGTRAMP (fci
->pc
, name
))
2269 frame_saved_regs_zalloc (fci
);
2270 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2271 fci
->saved_regs
[PC_REGNUM
]
2272 = fci
->saved_regs
[RA_REGNUM
];
2276 /* hack: if argument regs are saved, guess these contain args */
2277 /* assume we can't tell how many args for now */
2278 fci
->extra_info
->num_args
= -1;
2279 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2281 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2283 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2290 /* MIPS stack frames are almost impenetrable. When execution stops,
2291 we basically have to look at symbol information for the function
2292 that we stopped in, which tells us *which* register (if any) is
2293 the base of the frame pointer, and what offset from that register
2294 the frame itself is at.
2296 This presents a problem when trying to examine a stack in memory
2297 (that isn't executing at the moment), using the "frame" command. We
2298 don't have a PC, nor do we have any registers except SP.
2300 This routine takes two arguments, SP and PC, and tries to make the
2301 cached frames look as if these two arguments defined a frame on the
2302 cache. This allows the rest of info frame to extract the important
2303 arguments without difficulty. */
2306 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2309 error ("MIPS frame specifications require two arguments: sp and pc");
2311 return create_new_frame (argv
[0], argv
[1]);
2314 /* According to the current ABI, should the type be passed in a
2315 floating-point register (assuming that there is space)? When there
2316 is no FPU, FP are not even considered as possibile candidates for
2317 FP registers and, consequently this returns false - forces FP
2318 arguments into integer registers. */
2321 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2323 return ((typecode
== TYPE_CODE_FLT
2325 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2326 && TYPE_NFIELDS (arg_type
) == 1
2327 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2328 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2331 /* On o32, argument passing in GPRs depends on the alignment of the type being
2332 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2335 mips_type_needs_double_align (struct type
*type
)
2337 enum type_code typecode
= TYPE_CODE (type
);
2339 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2341 else if (typecode
== TYPE_CODE_STRUCT
)
2343 if (TYPE_NFIELDS (type
) < 1)
2345 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2347 else if (typecode
== TYPE_CODE_UNION
)
2351 n
= TYPE_NFIELDS (type
);
2352 for (i
= 0; i
< n
; i
++)
2353 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2361 mips_push_arguments (int nargs
,
2362 struct value
**args
,
2365 CORE_ADDR struct_addr
)
2371 int stack_offset
= 0;
2372 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2374 /* Macros to round N up or down to the next A boundary; A must be
2376 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2377 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2379 /* First ensure that the stack and structure return address (if any)
2380 are properly aligned. The stack has to be at least 64-bit aligned
2381 even on 32-bit machines, because doubles must be 64-bit aligned.
2382 On at least one MIPS variant, stack frames need to be 128-bit
2383 aligned, so we round to this widest known alignment. */
2384 sp
= ROUND_DOWN (sp
, 16);
2385 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2387 /* Now make space on the stack for the args. We allocate more
2388 than necessary for EABI, because the first few arguments are
2389 passed in registers, but that's OK. */
2390 for (argnum
= 0; argnum
< nargs
; argnum
++)
2391 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_STACK_ARGSIZE
);
2392 sp
-= ROUND_UP (len
, 16);
2395 fprintf_unfiltered (gdb_stdlog
, "mips_push_arguments: sp=0x%lx allocated %d\n",
2396 (long) sp
, ROUND_UP (len
, 16));
2398 /* Initialize the integer and float register pointers. */
2400 float_argreg
= FPA0_REGNUM
;
2402 /* the struct_return pointer occupies the first parameter-passing reg */
2406 fprintf_unfiltered (gdb_stdlog
,
2407 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2408 argreg
, (long) struct_addr
);
2409 write_register (argreg
++, struct_addr
);
2410 if (MIPS_REGS_HAVE_HOME_P
)
2411 stack_offset
+= MIPS_STACK_ARGSIZE
;
2414 /* Now load as many as possible of the first arguments into
2415 registers, and push the rest onto the stack. Loop thru args
2416 from first to last. */
2417 for (argnum
= 0; argnum
< nargs
; argnum
++)
2420 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2421 struct value
*arg
= args
[argnum
];
2422 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2423 int len
= TYPE_LENGTH (arg_type
);
2424 enum type_code typecode
= TYPE_CODE (arg_type
);
2427 fprintf_unfiltered (gdb_stdlog
,
2428 "mips_push_arguments: %d len=%d type=%d",
2429 argnum
+ 1, len
, (int) typecode
);
2431 /* The EABI passes structures that do not fit in a register by
2432 reference. In all other cases, pass the structure by value. */
2434 && len
> MIPS_SAVED_REGSIZE
2435 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2437 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2438 typecode
= TYPE_CODE_PTR
;
2439 len
= MIPS_SAVED_REGSIZE
;
2442 fprintf_unfiltered (gdb_stdlog
, " push");
2445 val
= (char *) VALUE_CONTENTS (arg
);
2447 /* 32-bit ABIs always start floating point arguments in an
2448 even-numbered floating point register. Round the FP register
2449 up before the check to see if there are any FP registers
2450 left. Non MIPS_EABI targets also pass the FP in the integer
2451 registers so also round up normal registers. */
2452 if (!FP_REGISTER_DOUBLE
2453 && fp_register_arg_p (typecode
, arg_type
))
2455 if ((float_argreg
& 1))
2459 /* Floating point arguments passed in registers have to be
2460 treated specially. On 32-bit architectures, doubles
2461 are passed in register pairs; the even register gets
2462 the low word, and the odd register gets the high word.
2463 On non-EABI processors, the first two floating point arguments are
2464 also copied to general registers, because MIPS16 functions
2465 don't use float registers for arguments. This duplication of
2466 arguments in general registers can't hurt non-MIPS16 functions
2467 because those registers are normally skipped. */
2468 /* MIPS_EABI squeezes a struct that contains a single floating
2469 point value into an FP register instead of pushing it onto the
2471 if (fp_register_arg_p (typecode
, arg_type
)
2472 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2474 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2476 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2477 unsigned long regval
;
2479 /* Write the low word of the double to the even register(s). */
2480 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2482 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2483 float_argreg
, phex (regval
, 4));
2484 write_register (float_argreg
++, regval
);
2488 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2489 argreg
, phex (regval
, 4));
2490 write_register (argreg
++, regval
);
2493 /* Write the high word of the double to the odd register(s). */
2494 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2496 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2497 float_argreg
, phex (regval
, 4));
2498 write_register (float_argreg
++, regval
);
2502 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2503 argreg
, phex (regval
, 4));
2504 write_register (argreg
++, regval
);
2510 /* This is a floating point value that fits entirely
2511 in a single register. */
2512 /* On 32 bit ABI's the float_argreg is further adjusted
2513 above to ensure that it is even register aligned. */
2514 LONGEST regval
= extract_unsigned_integer (val
, len
);
2516 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2517 float_argreg
, phex (regval
, len
));
2518 write_register (float_argreg
++, regval
);
2521 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2522 registers for each argument. The below is (my
2523 guess) to ensure that the corresponding integer
2524 register has reserved the same space. */
2526 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2527 argreg
, phex (regval
, len
));
2528 write_register (argreg
, regval
);
2529 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2532 /* Reserve space for the FP register. */
2533 if (MIPS_REGS_HAVE_HOME_P
)
2534 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
2538 /* Copy the argument to general registers or the stack in
2539 register-sized pieces. Large arguments are split between
2540 registers and stack. */
2541 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2542 are treated specially: Irix cc passes them in registers
2543 where gcc sometimes puts them on the stack. For maximum
2544 compatibility, we will put them in both places. */
2545 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2546 (len
% MIPS_SAVED_REGSIZE
!= 0));
2547 /* Structures should be aligned to eight bytes (even arg registers)
2548 on MIPS_ABI_O32 if their first member has double precision. */
2549 if (tdep
->mips_abi
== MIPS_ABI_O32
2550 && mips_type_needs_double_align (arg_type
))
2555 /* Note: Floating-point values that didn't fit into an FP
2556 register are only written to memory. */
2559 /* Rememer if the argument was written to the stack. */
2560 int stack_used_p
= 0;
2561 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2564 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2567 /* Write this portion of the argument to the stack. */
2568 if (argreg
> MIPS_LAST_ARG_REGNUM
2570 || fp_register_arg_p (typecode
, arg_type
))
2572 /* Should shorter than int integer values be
2573 promoted to int before being stored? */
2574 int longword_offset
= 0;
2577 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2579 if (MIPS_STACK_ARGSIZE
== 8 &&
2580 (typecode
== TYPE_CODE_INT
||
2581 typecode
== TYPE_CODE_PTR
||
2582 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2583 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2584 else if ((typecode
== TYPE_CODE_STRUCT
||
2585 typecode
== TYPE_CODE_UNION
) &&
2586 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2587 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2592 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%lx",
2593 (long) stack_offset
);
2594 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%lx",
2595 (long) longword_offset
);
2598 addr
= sp
+ stack_offset
+ longword_offset
;
2603 fprintf_unfiltered (gdb_stdlog
, " @0x%lx ", (long) addr
);
2604 for (i
= 0; i
< partial_len
; i
++)
2606 fprintf_unfiltered (gdb_stdlog
, "%02x", val
[i
] & 0xff);
2609 write_memory (addr
, val
, partial_len
);
2612 /* Note!!! This is NOT an else clause. Odd sized
2613 structs may go thru BOTH paths. Floating point
2614 arguments will not. */
2615 /* Write this portion of the argument to a general
2616 purpose register. */
2617 if (argreg
<= MIPS_LAST_ARG_REGNUM
2618 && !fp_register_arg_p (typecode
, arg_type
))
2620 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2622 /* A non-floating-point argument being passed in a
2623 general register. If a struct or union, and if
2624 the remaining length is smaller than the register
2625 size, we have to adjust the register value on
2628 It does not seem to be necessary to do the
2629 same for integral types.
2631 Also don't do this adjustment on EABI and O64
2634 cagney/2001-07-23: gdb/179: Also, GCC, when
2635 outputting LE O32 with sizeof (struct) <
2636 MIPS_SAVED_REGSIZE, generates a left shift as
2637 part of storing the argument in a register a
2638 register (the left shift isn't generated when
2639 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
2640 is quite possible that this is GCC contradicting
2641 the LE/O32 ABI, GDB has not been adjusted to
2642 accommodate this. Either someone needs to
2643 demonstrate that the LE/O32 ABI specifies such a
2644 left shift OR this new ABI gets identified as
2645 such and GDB gets tweaked accordingly. */
2648 && MIPS_SAVED_REGSIZE
< 8
2649 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2650 && partial_len
< MIPS_SAVED_REGSIZE
2651 && (typecode
== TYPE_CODE_STRUCT
||
2652 typecode
== TYPE_CODE_UNION
))
2653 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2657 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2659 phex (regval
, MIPS_SAVED_REGSIZE
));
2660 write_register (argreg
, regval
);
2663 /* If this is the old ABI, prevent subsequent floating
2664 point arguments from being passed in floating point
2667 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2673 /* Compute the the offset into the stack at which we
2674 will copy the next parameter.
2676 In older ABIs, the caller reserved space for
2677 registers that contained arguments. This was loosely
2678 refered to as their "home". Consequently, space is
2681 In the new EABI (and the NABI32), the stack_offset
2682 only needs to be adjusted when it has been used.. */
2684 if (MIPS_REGS_HAVE_HOME_P
|| stack_used_p
)
2685 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2689 fprintf_unfiltered (gdb_stdlog
, "\n");
2692 /* Return adjusted stack pointer. */
2697 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2699 /* Set the return address register to point to the entry
2700 point of the program, where a breakpoint lies in wait. */
2701 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2706 mips_push_register (CORE_ADDR
* sp
, int regno
)
2708 char buffer
[MAX_REGISTER_RAW_SIZE
];
2711 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2713 regsize
= MIPS_SAVED_REGSIZE
;
2714 offset
= (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2715 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2720 regsize
= REGISTER_RAW_SIZE (regno
);
2724 read_register_gen (regno
, buffer
);
2725 write_memory (*sp
, buffer
+ offset
, regsize
);
2728 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2729 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2732 mips_push_dummy_frame (void)
2735 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2736 xmalloc (sizeof (struct linked_proc_info
));
2737 mips_extra_func_info_t proc_desc
= &link
->info
;
2738 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
2739 CORE_ADDR old_sp
= sp
;
2740 link
->next
= linked_proc_desc_table
;
2741 linked_proc_desc_table
= link
;
2743 /* FIXME! are these correct ? */
2744 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2745 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2746 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2747 #define FLOAT_SINGLE_REG_SAVE_MASK \
2748 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2750 * The registers we must save are all those not preserved across
2751 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2752 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2753 * and FP Control/Status registers.
2756 * Dummy frame layout:
2759 * Saved MMHI, MMLO, FPC_CSR
2764 * Saved D18 (i.e. F19, F18)
2766 * Saved D0 (i.e. F1, F0)
2767 * Argument build area and stack arguments written via mips_push_arguments
2771 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2772 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2773 PROC_FRAME_OFFSET (proc_desc
) = 0;
2774 PROC_FRAME_ADJUST (proc_desc
) = 0;
2775 mips_push_register (&sp
, PC_REGNUM
);
2776 mips_push_register (&sp
, HI_REGNUM
);
2777 mips_push_register (&sp
, LO_REGNUM
);
2778 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2780 /* Save general CPU registers */
2781 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2782 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2783 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2784 for (ireg
= 32; --ireg
>= 0;)
2785 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2786 mips_push_register (&sp
, ireg
);
2788 /* Save floating point registers starting with high order word */
2789 PROC_FREG_MASK (proc_desc
) =
2790 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2791 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2792 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2794 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2795 for (ireg
= 32; --ireg
>= 0;)
2796 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2797 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2799 /* Update the frame pointer for the call dummy and the stack pointer.
2800 Set the procedure's starting and ending addresses to point to the
2801 call dummy address at the entry point. */
2802 write_register (PUSH_FP_REGNUM
, old_sp
);
2803 write_register (SP_REGNUM
, sp
);
2804 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2805 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2806 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2807 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2811 mips_pop_frame (void)
2813 register int regnum
;
2814 struct frame_info
*frame
= get_current_frame ();
2815 CORE_ADDR new_sp
= FRAME_FP (frame
);
2817 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2819 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2820 if (frame
->saved_regs
== NULL
)
2821 mips_find_saved_regs (frame
);
2822 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2824 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2825 && frame
->saved_regs
[regnum
])
2826 write_register (regnum
,
2827 read_memory_integer (frame
->saved_regs
[regnum
],
2828 MIPS_SAVED_REGSIZE
));
2830 write_register (SP_REGNUM
, new_sp
);
2831 flush_cached_frames ();
2833 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2835 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2837 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2839 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2841 if (&pi_ptr
->info
== proc_desc
)
2846 error ("Can't locate dummy extra frame info\n");
2848 if (prev_ptr
!= NULL
)
2849 prev_ptr
->next
= pi_ptr
->next
;
2851 linked_proc_desc_table
= pi_ptr
->next
;
2855 write_register (HI_REGNUM
,
2856 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2857 MIPS_SAVED_REGSIZE
));
2858 write_register (LO_REGNUM
,
2859 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2860 MIPS_SAVED_REGSIZE
));
2861 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2862 write_register (FCRCS_REGNUM
,
2863 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2864 MIPS_SAVED_REGSIZE
));
2868 /* Floating point register management.
2870 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
2871 64bit operations, these early MIPS cpus treat fp register pairs
2872 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
2873 registers and offer a compatibility mode that emulates the MIPS2 fp
2874 model. When operating in MIPS2 fp compat mode, later cpu's split
2875 double precision floats into two 32-bit chunks and store them in
2876 consecutive fp regs. To display 64-bit floats stored in this
2877 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
2878 Throw in user-configurable endianness and you have a real mess.
2880 The way this works is:
2881 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
2882 double-precision value will be split across two logical registers.
2883 The lower-numbered logical register will hold the low-order bits,
2884 regardless of the processor's endianness.
2885 - If we are on a 64-bit processor, and we are looking for a
2886 single-precision value, it will be in the low ordered bits
2887 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
2888 save slot in memory.
2889 - If we are in 64-bit mode, everything is straightforward.
2891 Note that this code only deals with "live" registers at the top of the
2892 stack. We will attempt to deal with saved registers later, when
2893 the raw/cooked register interface is in place. (We need a general
2894 interface that can deal with dynamic saved register sizes -- fp
2895 regs could be 32 bits wide in one frame and 64 on the frame above
2898 static struct type
*
2899 mips_float_register_type (void)
2901 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2902 return builtin_type_ieee_single_big
;
2904 return builtin_type_ieee_single_little
;
2907 static struct type
*
2908 mips_double_register_type (void)
2910 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2911 return builtin_type_ieee_double_big
;
2913 return builtin_type_ieee_double_little
;
2916 /* Copy a 32-bit single-precision value from the current frame
2917 into rare_buffer. */
2920 mips_read_fp_register_single (int regno
, char *rare_buffer
)
2922 int raw_size
= REGISTER_RAW_SIZE (regno
);
2923 char *raw_buffer
= alloca (raw_size
);
2925 if (!frame_register_read (selected_frame
, regno
, raw_buffer
))
2926 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
2929 /* We have a 64-bit value for this register. Find the low-order
2933 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2938 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
2942 memcpy (rare_buffer
, raw_buffer
, 4);
2946 /* Copy a 64-bit double-precision value from the current frame into
2947 rare_buffer. This may include getting half of it from the next
2951 mips_read_fp_register_double (int regno
, char *rare_buffer
)
2953 int raw_size
= REGISTER_RAW_SIZE (regno
);
2955 if (raw_size
== 8 && !mips2_fp_compat ())
2957 /* We have a 64-bit value for this register, and we should use
2959 if (!frame_register_read (selected_frame
, regno
, rare_buffer
))
2960 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
2964 if ((regno
- FP0_REGNUM
) & 1)
2965 internal_error (__FILE__
, __LINE__
,
2966 "mips_read_fp_register_double: bad access to "
2967 "odd-numbered FP register");
2969 /* mips_read_fp_register_single will find the correct 32 bits from
2971 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2973 mips_read_fp_register_single (regno
, rare_buffer
+ 4);
2974 mips_read_fp_register_single (regno
+ 1, rare_buffer
);
2978 mips_read_fp_register_single (regno
, rare_buffer
);
2979 mips_read_fp_register_single (regno
+ 1, rare_buffer
+ 4);
2985 mips_print_register (int regnum
, int all
)
2987 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2989 /* Get the data in raw format. */
2990 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
2992 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2996 /* If we have a actual 32-bit floating point register (or we are in
2997 32-bit compatibility mode), and the register is even-numbered,
2998 also print it as a double (spanning two registers). */
2999 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
3000 && (REGISTER_RAW_SIZE (regnum
) == 4
3001 || mips2_fp_compat ())
3002 && !((regnum
- FP0_REGNUM
) & 1))
3004 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
3006 mips_read_fp_register_double (regnum
, dbuffer
);
3008 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
3009 val_print (mips_double_register_type (), dbuffer
, 0, 0,
3010 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3011 printf_filtered ("); ");
3013 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
3015 /* The problem with printing numeric register names (r26, etc.) is that
3016 the user can't use them on input. Probably the best solution is to
3017 fix it so that either the numeric or the funky (a2, etc.) names
3018 are accepted on input. */
3019 if (regnum
< MIPS_NUMREGS
)
3020 printf_filtered ("(r%d): ", regnum
);
3022 printf_filtered (": ");
3024 /* If virtual format is floating, print it that way. */
3025 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3026 if (REGISTER_RAW_SIZE (regnum
) == 8 && !mips2_fp_compat ())
3028 /* We have a meaningful 64-bit value in this register. Show
3029 it as a 32-bit float and a 64-bit double. */
3030 int offset
= 4 * (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
);
3032 printf_filtered (" (float) ");
3033 val_print (mips_float_register_type (), raw_buffer
+ offset
, 0, 0,
3034 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3035 printf_filtered (", (double) ");
3036 val_print (mips_double_register_type (), raw_buffer
, 0, 0,
3037 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3040 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
3041 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3042 /* Else print as integer in hex. */
3047 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3048 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3052 print_scalar_formatted (raw_buffer
+ offset
,
3053 REGISTER_VIRTUAL_TYPE (regnum
),
3054 'x', 0, gdb_stdout
);
3058 /* Replacement for generic do_registers_info.
3059 Print regs in pretty columns. */
3062 do_fp_register_row (int regnum
)
3063 { /* do values for FP (float) regs */
3065 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
3066 int inv1
, inv2
, inv3
;
3068 raw_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
3070 if (REGISTER_RAW_SIZE (regnum
) == 4 || mips2_fp_compat ())
3072 /* 4-byte registers: we can fit two registers per row. */
3073 /* Also print every pair of 4-byte regs as an 8-byte double. */
3074 mips_read_fp_register_single (regnum
, raw_buffer
);
3075 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3077 mips_read_fp_register_single (regnum
+ 1, raw_buffer
);
3078 flt2
= unpack_double (mips_float_register_type (), raw_buffer
, &inv2
);
3080 mips_read_fp_register_double (regnum
, raw_buffer
);
3081 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
3083 printf_filtered (" %-5s", REGISTER_NAME (regnum
));
3085 printf_filtered (": <invalid float>");
3087 printf_filtered ("%-17.9g", flt1
);
3089 printf_filtered (" %-5s", REGISTER_NAME (regnum
+ 1));
3091 printf_filtered (": <invalid float>");
3093 printf_filtered ("%-17.9g", flt2
);
3095 printf_filtered (" dbl: ");
3097 printf_filtered ("<invalid double>");
3099 printf_filtered ("%-24.17g", doub
);
3100 printf_filtered ("\n");
3102 /* may want to do hex display here (future enhancement) */
3107 /* Eight byte registers: print each one as float AND as double. */
3108 mips_read_fp_register_single (regnum
, raw_buffer
);
3109 flt1
= unpack_double (mips_double_register_type (), raw_buffer
, &inv1
);
3111 mips_read_fp_register_double (regnum
, raw_buffer
);
3112 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
3114 printf_filtered (" %-5s: ", REGISTER_NAME (regnum
));
3116 printf_filtered ("<invalid float>");
3118 printf_filtered ("flt: %-17.9g", flt1
);
3120 printf_filtered (" dbl: ");
3122 printf_filtered ("<invalid double>");
3124 printf_filtered ("%-24.17g", doub
);
3126 printf_filtered ("\n");
3127 /* may want to do hex display here (future enhancement) */
3133 /* Print a row's worth of GP (int) registers, with name labels above */
3136 do_gp_register_row (int regnum
)
3138 /* do values for GP (int) regs */
3139 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3140 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
3142 int start_regnum
= regnum
;
3143 int numregs
= NUM_REGS
;
3146 /* For GP registers, we print a separate row of names above the vals */
3147 printf_filtered (" ");
3148 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
3150 if (*REGISTER_NAME (regnum
) == '\0')
3151 continue; /* unused register */
3152 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3153 break; /* end the row: reached FP register */
3154 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
3155 REGISTER_NAME (regnum
));
3158 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
3159 start_regnum
); /* print the R0 to R31 names */
3161 regnum
= start_regnum
; /* go back to start of row */
3162 /* now print the values in hex, 4 or 8 to the row */
3163 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
3165 if (*REGISTER_NAME (regnum
) == '\0')
3166 continue; /* unused register */
3167 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3168 break; /* end row: reached FP register */
3169 /* OK: get the data in raw format. */
3170 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3171 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
3172 /* pad small registers */
3173 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
3174 printf_filtered (" ");
3175 /* Now print the register value in hex, endian order. */
3176 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3177 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3178 byte
< REGISTER_RAW_SIZE (regnum
);
3180 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3182 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
3185 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3186 printf_filtered (" ");
3189 if (col
> 0) /* ie. if we actually printed anything... */
3190 printf_filtered ("\n");
3195 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
3198 mips_do_registers_info (int regnum
, int fpregs
)
3200 if (regnum
!= -1) /* do one specified register */
3202 if (*(REGISTER_NAME (regnum
)) == '\0')
3203 error ("Not a valid register for the current processor type");
3205 mips_print_register (regnum
, 0);
3206 printf_filtered ("\n");
3209 /* do all (or most) registers */
3212 while (regnum
< NUM_REGS
)
3214 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3215 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
3216 regnum
= do_fp_register_row (regnum
); /* FP regs */
3218 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
3220 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
3225 /* Return number of args passed to a frame. described by FIP.
3226 Can return -1, meaning no way to tell. */
3229 mips_frame_num_args (struct frame_info
*frame
)
3234 /* Is this a branch with a delay slot? */
3236 static int is_delayed (unsigned long);
3239 is_delayed (unsigned long insn
)
3242 for (i
= 0; i
< NUMOPCODES
; ++i
)
3243 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
3244 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
3246 return (i
< NUMOPCODES
3247 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
3248 | INSN_COND_BRANCH_DELAY
3249 | INSN_COND_BRANCH_LIKELY
)));
3253 mips_step_skips_delay (CORE_ADDR pc
)
3255 char buf
[MIPS_INSTLEN
];
3257 /* There is no branch delay slot on MIPS16. */
3258 if (pc_is_mips16 (pc
))
3261 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
3262 /* If error reading memory, guess that it is not a delayed branch. */
3264 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
3268 /* Skip the PC past function prologue instructions (32-bit version).
3269 This is a helper function for mips_skip_prologue. */
3272 mips32_skip_prologue (CORE_ADDR pc
)
3276 int seen_sp_adjust
= 0;
3277 int load_immediate_bytes
= 0;
3279 /* Skip the typical prologue instructions. These are the stack adjustment
3280 instruction and the instructions that save registers on the stack
3281 or in the gcc frame. */
3282 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
3284 unsigned long high_word
;
3286 inst
= mips_fetch_instruction (pc
);
3287 high_word
= (inst
>> 16) & 0xffff;
3289 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
3290 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
3292 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
3293 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
3295 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
3296 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
3297 && (inst
& 0x001F0000)) /* reg != $zero */
3300 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
3302 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
3304 continue; /* reg != $zero */
3306 /* move $s8,$sp. With different versions of gas this will be either
3307 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
3308 Accept any one of these. */
3309 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3312 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
3314 else if (high_word
== 0x3c1c) /* lui $gp,n */
3316 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
3318 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3319 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
3321 /* The following instructions load $at or $t0 with an immediate
3322 value in preparation for a stack adjustment via
3323 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
3324 a local variable, so we accept them only before a stack adjustment
3325 instruction was seen. */
3326 else if (!seen_sp_adjust
)
3328 if (high_word
== 0x3c01 || /* lui $at,n */
3329 high_word
== 0x3c08) /* lui $t0,n */
3331 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3334 else if (high_word
== 0x3421 || /* ori $at,$at,n */
3335 high_word
== 0x3508 || /* ori $t0,$t0,n */
3336 high_word
== 0x3401 || /* ori $at,$zero,n */
3337 high_word
== 0x3408) /* ori $t0,$zero,n */
3339 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3349 /* In a frameless function, we might have incorrectly
3350 skipped some load immediate instructions. Undo the skipping
3351 if the load immediate was not followed by a stack adjustment. */
3352 if (load_immediate_bytes
&& !seen_sp_adjust
)
3353 pc
-= load_immediate_bytes
;
3357 /* Skip the PC past function prologue instructions (16-bit version).
3358 This is a helper function for mips_skip_prologue. */
3361 mips16_skip_prologue (CORE_ADDR pc
)
3364 int extend_bytes
= 0;
3365 int prev_extend_bytes
;
3367 /* Table of instructions likely to be found in a function prologue. */
3370 unsigned short inst
;
3371 unsigned short mask
;
3378 , /* addiu $sp,offset */
3382 , /* daddiu $sp,offset */
3386 , /* sw reg,n($sp) */
3390 , /* sd reg,n($sp) */
3394 , /* sw $ra,n($sp) */
3398 , /* sd $ra,n($sp) */
3406 , /* sw $a0-$a3,n($s1) */
3410 , /* move reg,$a0-$a3 */
3414 , /* entry pseudo-op */
3418 , /* addiu $s1,$sp,n */
3421 } /* end of table marker */
3424 /* Skip the typical prologue instructions. These are the stack adjustment
3425 instruction and the instructions that save registers on the stack
3426 or in the gcc frame. */
3427 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
3429 unsigned short inst
;
3432 inst
= mips_fetch_instruction (pc
);
3434 /* Normally we ignore an extend instruction. However, if it is
3435 not followed by a valid prologue instruction, we must adjust
3436 the pc back over the extend so that it won't be considered
3437 part of the prologue. */
3438 if ((inst
& 0xf800) == 0xf000) /* extend */
3440 extend_bytes
= MIPS16_INSTLEN
;
3443 prev_extend_bytes
= extend_bytes
;
3446 /* Check for other valid prologue instructions besides extend. */
3447 for (i
= 0; table
[i
].mask
!= 0; i
++)
3448 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
3450 if (table
[i
].mask
!= 0) /* it was in table? */
3451 continue; /* ignore it */
3455 /* Return the current pc, adjusted backwards by 2 if
3456 the previous instruction was an extend. */
3457 return pc
- prev_extend_bytes
;
3463 /* To skip prologues, I use this predicate. Returns either PC itself
3464 if the code at PC does not look like a function prologue; otherwise
3465 returns an address that (if we're lucky) follows the prologue. If
3466 LENIENT, then we must skip everything which is involved in setting
3467 up the frame (it's OK to skip more, just so long as we don't skip
3468 anything which might clobber the registers which are being saved.
3469 We must skip more in the case where part of the prologue is in the
3470 delay slot of a non-prologue instruction). */
3473 mips_skip_prologue (CORE_ADDR pc
)
3475 /* See if we can determine the end of the prologue via the symbol table.
3476 If so, then return either PC, or the PC after the prologue, whichever
3479 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
3481 if (post_prologue_pc
!= 0)
3482 return max (pc
, post_prologue_pc
);
3484 /* Can't determine prologue from the symbol table, need to examine
3487 if (pc_is_mips16 (pc
))
3488 return mips16_skip_prologue (pc
);
3490 return mips32_skip_prologue (pc
);
3493 /* Determine how a return value is stored within the MIPS register
3494 file, given the return type `valtype'. */
3496 struct return_value_word
3505 return_value_location (struct type
*valtype
,
3506 struct return_value_word
*hi
,
3507 struct return_value_word
*lo
)
3509 int len
= TYPE_LENGTH (valtype
);
3511 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3512 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3513 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3515 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3517 /* We need to break a 64bit float in two 32 bit halves and
3518 spread them across a floating-point register pair. */
3519 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3520 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3521 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3522 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3524 hi
->reg_offset
= lo
->reg_offset
;
3525 lo
->reg
= FP0_REGNUM
+ 0;
3526 hi
->reg
= FP0_REGNUM
+ 1;
3532 /* The floating point value fits in a single floating-point
3534 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3535 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3538 lo
->reg
= FP0_REGNUM
;
3549 /* Locate a result possibly spread across two registers. */
3551 lo
->reg
= regnum
+ 0;
3552 hi
->reg
= regnum
+ 1;
3553 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3554 && len
< MIPS_SAVED_REGSIZE
)
3556 /* "un-left-justify" the value in the low register */
3557 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3562 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3563 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3564 && len
< MIPS_SAVED_REGSIZE
* 2
3565 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3566 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3568 /* "un-left-justify" the value spread across two registers. */
3569 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3570 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3572 hi
->len
= len
- lo
->len
;
3576 /* Only perform a partial copy of the second register. */
3579 if (len
> MIPS_SAVED_REGSIZE
)
3581 lo
->len
= MIPS_SAVED_REGSIZE
;
3582 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3590 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3591 && REGISTER_RAW_SIZE (regnum
) == 8
3592 && MIPS_SAVED_REGSIZE
== 4)
3594 /* Account for the fact that only the least-signficant part
3595 of the register is being used */
3596 lo
->reg_offset
+= 4;
3597 hi
->reg_offset
+= 4;
3600 hi
->buf_offset
= lo
->len
;
3604 /* Given a return value in `regbuf' with a type `valtype', extract and
3605 copy its value into `valbuf'. */
3608 mips_extract_return_value (struct type
*valtype
,
3609 char regbuf
[REGISTER_BYTES
],
3612 struct return_value_word lo
;
3613 struct return_value_word hi
;
3614 return_value_location (valtype
, &hi
, &lo
);
3616 memcpy (valbuf
+ lo
.buf_offset
,
3617 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3621 memcpy (valbuf
+ hi
.buf_offset
,
3622 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3626 /* Given a return value in `valbuf' with a type `valtype', write it's
3627 value into the appropriate register. */
3630 mips_store_return_value (struct type
*valtype
, char *valbuf
)
3632 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3633 struct return_value_word lo
;
3634 struct return_value_word hi
;
3635 return_value_location (valtype
, &hi
, &lo
);
3637 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3638 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3639 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3641 REGISTER_RAW_SIZE (lo
.reg
));
3645 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3646 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3647 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3649 REGISTER_RAW_SIZE (hi
.reg
));
3653 /* Exported procedure: Is PC in the signal trampoline code */
3656 in_sigtramp (CORE_ADDR pc
, char *ignore
)
3658 if (sigtramp_address
== 0)
3660 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3663 /* Root of all "set mips "/"show mips " commands. This will eventually be
3664 used for all MIPS-specific commands. */
3667 show_mips_command (char *args
, int from_tty
)
3669 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3673 set_mips_command (char *args
, int from_tty
)
3675 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3676 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3679 /* Commands to show/set the MIPS FPU type. */
3682 show_mipsfpu_command (char *args
, int from_tty
)
3685 switch (MIPS_FPU_TYPE
)
3687 case MIPS_FPU_SINGLE
:
3688 fpu
= "single-precision";
3690 case MIPS_FPU_DOUBLE
:
3691 fpu
= "double-precision";
3694 fpu
= "absent (none)";
3697 internal_error (__FILE__
, __LINE__
, "bad switch");
3699 if (mips_fpu_type_auto
)
3700 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3703 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3709 set_mipsfpu_command (char *args
, int from_tty
)
3711 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3712 show_mipsfpu_command (args
, from_tty
);
3716 set_mipsfpu_single_command (char *args
, int from_tty
)
3718 mips_fpu_type
= MIPS_FPU_SINGLE
;
3719 mips_fpu_type_auto
= 0;
3720 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3724 set_mipsfpu_double_command (char *args
, int from_tty
)
3726 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3727 mips_fpu_type_auto
= 0;
3728 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3732 set_mipsfpu_none_command (char *args
, int from_tty
)
3734 mips_fpu_type
= MIPS_FPU_NONE
;
3735 mips_fpu_type_auto
= 0;
3736 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3740 set_mipsfpu_auto_command (char *args
, int from_tty
)
3742 mips_fpu_type_auto
= 1;
3745 /* Command to set the processor type. */
3748 mips_set_processor_type_command (char *args
, int from_tty
)
3752 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3754 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3755 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3756 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3758 /* Restore the value. */
3759 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3764 if (!mips_set_processor_type (tmp_mips_processor_type
))
3766 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3767 /* Restore its value. */
3768 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3773 mips_show_processor_type_command (char *args
, int from_tty
)
3777 /* Modify the actual processor type. */
3780 mips_set_processor_type (char *str
)
3787 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3789 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3791 mips_processor_type
= str
;
3792 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3794 /* FIXME tweak fpu flag too */
3801 /* Attempt to identify the particular processor model by reading the
3805 mips_read_processor_type (void)
3809 prid
= read_register (PRID_REGNUM
);
3811 if ((prid
& ~0xf) == 0x700)
3812 return savestring ("r3041", strlen ("r3041"));
3817 /* Just like reinit_frame_cache, but with the right arguments to be
3818 callable as an sfunc. */
3821 reinit_frame_cache_sfunc (char *args
, int from_tty
,
3822 struct cmd_list_element
*c
)
3824 reinit_frame_cache ();
3828 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
3830 mips_extra_func_info_t proc_desc
;
3832 /* Search for the function containing this address. Set the low bit
3833 of the address when searching, in case we were given an even address
3834 that is the start of a 16-bit function. If we didn't do this,
3835 the search would fail because the symbol table says the function
3836 starts at an odd address, i.e. 1 byte past the given address. */
3837 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3838 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3840 /* Make an attempt to determine if this is a 16-bit function. If
3841 the procedure descriptor exists and the address therein is odd,
3842 it's definitely a 16-bit function. Otherwise, we have to just
3843 guess that if the address passed in is odd, it's 16-bits. */
3845 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
3846 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3848 info
->mach
= pc_is_mips16 (memaddr
) ?
3849 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3851 /* Round down the instruction address to the appropriate boundary. */
3852 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
3854 /* Call the appropriate disassembler based on the target endian-ness. */
3855 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3856 return print_insn_big_mips (memaddr
, info
);
3858 return print_insn_little_mips (memaddr
, info
);
3861 /* Old-style breakpoint macros.
3862 The IDT board uses an unusual breakpoint value, and sometimes gets
3863 confused when it sees the usual MIPS breakpoint instruction. */
3865 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3866 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3867 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3868 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3869 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3870 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3871 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3872 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3874 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3875 counter value to determine whether a 16- or 32-bit breakpoint should be
3876 used. It returns a pointer to a string of bytes that encode a breakpoint
3877 instruction, stores the length of the string to *lenptr, and adjusts pc
3878 (if necessary) to point to the actual memory location where the
3879 breakpoint should be inserted. */
3881 const unsigned char *
3882 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
3884 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3886 if (pc_is_mips16 (*pcptr
))
3888 static unsigned char mips16_big_breakpoint
[] =
3889 MIPS16_BIG_BREAKPOINT
;
3890 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3891 *lenptr
= sizeof (mips16_big_breakpoint
);
3892 return mips16_big_breakpoint
;
3896 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
3897 static unsigned char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3898 static unsigned char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3900 *lenptr
= sizeof (big_breakpoint
);
3902 if (strcmp (target_shortname
, "mips") == 0)
3903 return idt_big_breakpoint
;
3904 else if (strcmp (target_shortname
, "ddb") == 0
3905 || strcmp (target_shortname
, "pmon") == 0
3906 || strcmp (target_shortname
, "lsi") == 0)
3907 return pmon_big_breakpoint
;
3909 return big_breakpoint
;
3914 if (pc_is_mips16 (*pcptr
))
3916 static unsigned char mips16_little_breakpoint
[] =
3917 MIPS16_LITTLE_BREAKPOINT
;
3918 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3919 *lenptr
= sizeof (mips16_little_breakpoint
);
3920 return mips16_little_breakpoint
;
3924 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3925 static unsigned char pmon_little_breakpoint
[] =
3926 PMON_LITTLE_BREAKPOINT
;
3927 static unsigned char idt_little_breakpoint
[] =
3928 IDT_LITTLE_BREAKPOINT
;
3930 *lenptr
= sizeof (little_breakpoint
);
3932 if (strcmp (target_shortname
, "mips") == 0)
3933 return idt_little_breakpoint
;
3934 else if (strcmp (target_shortname
, "ddb") == 0
3935 || strcmp (target_shortname
, "pmon") == 0
3936 || strcmp (target_shortname
, "lsi") == 0)
3937 return pmon_little_breakpoint
;
3939 return little_breakpoint
;
3944 /* If PC is in a mips16 call or return stub, return the address of the target
3945 PC, which is either the callee or the caller. There are several
3946 cases which must be handled:
3948 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3949 target PC is in $31 ($ra).
3950 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3951 and the target PC is in $2.
3952 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3953 before the jal instruction, this is effectively a call stub
3954 and the the target PC is in $2. Otherwise this is effectively
3955 a return stub and the target PC is in $18.
3957 See the source code for the stubs in gcc/config/mips/mips16.S for
3960 This function implements the SKIP_TRAMPOLINE_CODE macro.
3964 mips_skip_stub (CORE_ADDR pc
)
3967 CORE_ADDR start_addr
;
3969 /* Find the starting address and name of the function containing the PC. */
3970 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3973 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3974 target PC is in $31 ($ra). */
3975 if (strcmp (name
, "__mips16_ret_sf") == 0
3976 || strcmp (name
, "__mips16_ret_df") == 0)
3977 return read_signed_register (RA_REGNUM
);
3979 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3981 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3982 and the target PC is in $2. */
3983 if (name
[19] >= '0' && name
[19] <= '9')
3984 return read_signed_register (2);
3986 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3987 before the jal instruction, this is effectively a call stub
3988 and the the target PC is in $2. Otherwise this is effectively
3989 a return stub and the target PC is in $18. */
3990 else if (name
[19] == 's' || name
[19] == 'd')
3992 if (pc
== start_addr
)
3994 /* Check if the target of the stub is a compiler-generated
3995 stub. Such a stub for a function bar might have a name
3996 like __fn_stub_bar, and might look like this:
4001 la $1,bar (becomes a lui/addiu pair)
4003 So scan down to the lui/addi and extract the target
4004 address from those two instructions. */
4006 CORE_ADDR target_pc
= read_signed_register (2);
4010 /* See if the name of the target function is __fn_stub_*. */
4011 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
4013 if (strncmp (name
, "__fn_stub_", 10) != 0
4014 && strcmp (name
, "etext") != 0
4015 && strcmp (name
, "_etext") != 0)
4018 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4019 The limit on the search is arbitrarily set to 20
4020 instructions. FIXME. */
4021 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
4023 inst
= mips_fetch_instruction (target_pc
);
4024 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4025 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4026 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4027 return pc
| (inst
& 0xffff); /* low word */
4030 /* Couldn't find the lui/addui pair, so return stub address. */
4034 /* This is the 'return' part of a call stub. The return
4035 address is in $r18. */
4036 return read_signed_register (18);
4039 return 0; /* not a stub */
4043 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
4044 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
4047 mips_in_call_stub (CORE_ADDR pc
, char *name
)
4049 CORE_ADDR start_addr
;
4051 /* Find the starting address of the function containing the PC. If the
4052 caller didn't give us a name, look it up at the same time. */
4053 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
4056 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4058 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
4059 if (name
[19] >= '0' && name
[19] <= '9')
4061 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4062 before the jal instruction, this is effectively a call stub. */
4063 else if (name
[19] == 's' || name
[19] == 'd')
4064 return pc
== start_addr
;
4067 return 0; /* not a stub */
4071 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
4072 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
4075 mips_in_return_stub (CORE_ADDR pc
, char *name
)
4077 CORE_ADDR start_addr
;
4079 /* Find the starting address of the function containing the PC. */
4080 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
4083 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
4084 if (strcmp (name
, "__mips16_ret_sf") == 0
4085 || strcmp (name
, "__mips16_ret_df") == 0)
4088 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
4089 i.e. after the jal instruction, this is effectively a return stub. */
4090 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
4091 && (name
[19] == 's' || name
[19] == 'd')
4092 && pc
!= start_addr
)
4095 return 0; /* not a stub */
4099 /* Return non-zero if the PC is in a library helper function that should
4100 be ignored. This implements the IGNORE_HELPER_CALL macro. */
4103 mips_ignore_helper (CORE_ADDR pc
)
4107 /* Find the starting address and name of the function containing the PC. */
4108 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
4111 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
4112 that we want to ignore. */
4113 return (strcmp (name
, "__mips16_ret_sf") == 0
4114 || strcmp (name
, "__mips16_ret_df") == 0);
4118 /* Return a location where we can set a breakpoint that will be hit
4119 when an inferior function call returns. This is normally the
4120 program's entry point. Executables that don't have an entry
4121 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
4122 whose address is the location where the breakpoint should be placed. */
4125 mips_call_dummy_address (void)
4127 struct minimal_symbol
*sym
;
4129 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
4131 return SYMBOL_VALUE_ADDRESS (sym
);
4133 return entry_point_address ();
4137 /* If the current gcc for this target does not produce correct debugging
4138 information for float parameters, both prototyped and unprototyped, then
4139 define this macro. This forces gdb to always assume that floats are
4140 passed as doubles and then converted in the callee.
4142 For the mips chip, it appears that the debug info marks the parameters as
4143 floats regardless of whether the function is prototyped, but the actual
4144 values are passed as doubles for the non-prototyped case and floats for
4145 the prototyped case. Thus we choose to make the non-prototyped case work
4146 for C and break the prototyped case, since the non-prototyped case is
4147 probably much more common. (FIXME). */
4150 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
4152 return current_language
->la_language
== language_c
;
4155 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
4156 the register stored on the stack (32) is different to its real raw
4157 size (64). The below ensures that registers are fetched from the
4158 stack using their ABI size and then stored into the RAW_BUFFER
4159 using their raw size.
4161 The alternative to adding this function would be to add an ABI
4162 macro - REGISTER_STACK_SIZE(). */
4165 mips_get_saved_register (char *raw_buffer
,
4168 struct frame_info
*frame
,
4170 enum lval_type
*lval
)
4174 if (!target_has_registers
)
4175 error ("No registers.");
4177 /* Normal systems don't optimize out things with register numbers. */
4178 if (optimized
!= NULL
)
4180 addr
= find_saved_register (frame
, regnum
);
4184 *lval
= lval_memory
;
4185 if (regnum
== SP_REGNUM
)
4187 if (raw_buffer
!= NULL
)
4189 /* Put it back in target format. */
4190 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
4197 if (raw_buffer
!= NULL
)
4201 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
4203 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
4205 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
4206 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
4212 *lval
= lval_register
;
4213 addr
= REGISTER_BYTE (regnum
);
4214 if (raw_buffer
!= NULL
)
4215 read_register_gen (regnum
, raw_buffer
);
4221 /* Immediately after a function call, return the saved pc.
4222 Can't always go through the frames for this because on some machines
4223 the new frame is not set up until the new function executes
4224 some instructions. */
4227 mips_saved_pc_after_call (struct frame_info
*frame
)
4229 return read_signed_register (RA_REGNUM
);
4233 /* Convert a dbx stab register number (from `r' declaration) to a gdb
4237 mips_stab_reg_to_regnum (int num
)
4242 return num
+ FP0_REGNUM
- 38;
4245 /* Convert a ecoff register number to a gdb REGNUM */
4248 mips_ecoff_reg_to_regnum (int num
)
4253 return num
+ FP0_REGNUM
- 32;
4256 /* Convert an integer into an address. By first converting the value
4257 into a pointer and then extracting it signed, the address is
4258 guarenteed to be correctly sign extended. */
4261 mips_integer_to_address (struct type
*type
, void *buf
)
4263 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
4264 LONGEST val
= unpack_long (type
, buf
);
4265 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
4266 return extract_signed_integer (tmp
,
4267 TYPE_LENGTH (builtin_type_void_data_ptr
));
4271 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4273 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4274 const char *name
= bfd_get_section_name (abfd
, sect
);
4276 if (*abip
!= MIPS_ABI_UNKNOWN
)
4279 if (strncmp (name
, ".mdebug.", 8) != 0)
4282 if (strcmp (name
, ".mdebug.abi32") == 0)
4283 *abip
= MIPS_ABI_O32
;
4284 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4285 *abip
= MIPS_ABI_N32
;
4286 else if (strcmp (name
, ".mdebug.abiN64") == 0)
4287 *abip
= MIPS_ABI_N64
;
4288 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4289 *abip
= MIPS_ABI_O64
;
4290 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4291 *abip
= MIPS_ABI_EABI32
;
4292 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4293 *abip
= MIPS_ABI_EABI64
;
4295 warning ("unsupported ABI %s.", name
+ 8);
4298 static enum mips_abi
4299 global_mips_abi (void)
4303 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4304 if (mips_abi_strings
[i
] == mips_abi_string
)
4305 return (enum mips_abi
) i
;
4307 internal_error (__FILE__
, __LINE__
,
4308 "unknown ABI string");
4311 static struct gdbarch
*
4312 mips_gdbarch_init (struct gdbarch_info info
,
4313 struct gdbarch_list
*arches
)
4315 static LONGEST mips_call_dummy_words
[] =
4317 struct gdbarch
*gdbarch
;
4318 struct gdbarch_tdep
*tdep
;
4320 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4321 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
4323 /* Reset the disassembly info, in case it was set to something
4325 tm_print_insn_info
.flavour
= bfd_target_unknown_flavour
;
4326 tm_print_insn_info
.arch
= bfd_arch_unknown
;
4327 tm_print_insn_info
.mach
= 0;
4333 /* First of all, extract the elf_flags, if available. */
4334 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4335 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4337 /* Try to determine the OS ABI of the object we are loading. If
4338 we end up with `unknown', just leave it that way. */
4339 osabi
= gdbarch_lookup_osabi (info
.abfd
);
4342 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4343 switch ((elf_flags
& EF_MIPS_ABI
))
4345 case E_MIPS_ABI_O32
:
4346 mips_abi
= MIPS_ABI_O32
;
4348 case E_MIPS_ABI_O64
:
4349 mips_abi
= MIPS_ABI_O64
;
4351 case E_MIPS_ABI_EABI32
:
4352 mips_abi
= MIPS_ABI_EABI32
;
4354 case E_MIPS_ABI_EABI64
:
4355 mips_abi
= MIPS_ABI_EABI64
;
4358 if ((elf_flags
& EF_MIPS_ABI2
))
4359 mips_abi
= MIPS_ABI_N32
;
4361 mips_abi
= MIPS_ABI_UNKNOWN
;
4365 /* GCC creates a pseudo-section whose name describes the ABI. */
4366 if (mips_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4367 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &mips_abi
);
4369 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
4370 Use the ABI from the last architecture if there is one. */
4371 if (info
.abfd
== NULL
&& arches
!= NULL
)
4372 mips_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
4374 /* Try the architecture for any hint of the correct ABI. */
4375 if (mips_abi
== MIPS_ABI_UNKNOWN
4376 && info
.bfd_arch_info
!= NULL
4377 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4379 switch (info
.bfd_arch_info
->mach
)
4381 case bfd_mach_mips3900
:
4382 mips_abi
= MIPS_ABI_EABI32
;
4384 case bfd_mach_mips4100
:
4385 case bfd_mach_mips5000
:
4386 mips_abi
= MIPS_ABI_EABI64
;
4388 case bfd_mach_mips8000
:
4389 case bfd_mach_mips10000
:
4390 /* On Irix, ELF64 executables use the N64 ABI. The
4391 pseudo-sections which describe the ABI aren't present
4392 on IRIX. (Even for executables created by gcc.) */
4393 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4394 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4395 mips_abi
= MIPS_ABI_N64
;
4397 mips_abi
= MIPS_ABI_N32
;
4402 #ifdef MIPS_DEFAULT_ABI
4403 if (mips_abi
== MIPS_ABI_UNKNOWN
)
4404 mips_abi
= MIPS_DEFAULT_ABI
;
4407 if (mips_abi
== MIPS_ABI_UNKNOWN
)
4408 mips_abi
= MIPS_ABI_O32
;
4410 /* Now that we have found what the ABI for this binary would be,
4411 check whether the user is overriding it. */
4412 found_abi
= mips_abi
;
4413 wanted_abi
= global_mips_abi ();
4414 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
4415 mips_abi
= wanted_abi
;
4419 fprintf_unfiltered (gdb_stdlog
,
4420 "mips_gdbarch_init: elf_flags = 0x%08x\n",
4422 fprintf_unfiltered (gdb_stdlog
,
4423 "mips_gdbarch_init: mips_abi = %d\n",
4425 fprintf_unfiltered (gdb_stdlog
,
4426 "mips_gdbarch_init: found_mips_abi = %d\n",
4430 /* try to find a pre-existing architecture */
4431 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4433 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4435 /* MIPS needs to be pedantic about which ABI the object is
4437 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4439 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4441 if (gdbarch_tdep (arches
->gdbarch
)->osabi
== osabi
)
4442 return arches
->gdbarch
;
4445 /* Need a new architecture. Fill in a target specific vector. */
4446 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4447 gdbarch
= gdbarch_alloc (&info
, tdep
);
4448 tdep
->elf_flags
= elf_flags
;
4449 tdep
->osabi
= osabi
;
4451 /* Initially set everything according to the default ABI/ISA. */
4452 set_gdbarch_short_bit (gdbarch
, 16);
4453 set_gdbarch_int_bit (gdbarch
, 32);
4454 set_gdbarch_float_bit (gdbarch
, 32);
4455 set_gdbarch_double_bit (gdbarch
, 64);
4456 set_gdbarch_long_double_bit (gdbarch
, 64);
4457 set_gdbarch_register_raw_size (gdbarch
, mips_register_raw_size
);
4458 tdep
->found_abi
= found_abi
;
4459 tdep
->mips_abi
= mips_abi
;
4464 tdep
->mips_default_saved_regsize
= 4;
4465 tdep
->mips_default_stack_argsize
= 4;
4466 tdep
->mips_fp_register_double
= 0;
4467 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4468 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4469 tdep
->mips_regs_have_home_p
= 1;
4470 tdep
->gdb_target_is_mips64
= 0;
4471 tdep
->default_mask_address_p
= 0;
4472 set_gdbarch_long_bit (gdbarch
, 32);
4473 set_gdbarch_ptr_bit (gdbarch
, 32);
4474 set_gdbarch_long_long_bit (gdbarch
, 64);
4477 tdep
->mips_default_saved_regsize
= 8;
4478 tdep
->mips_default_stack_argsize
= 8;
4479 tdep
->mips_fp_register_double
= 1;
4480 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4481 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4482 tdep
->mips_regs_have_home_p
= 1;
4483 tdep
->gdb_target_is_mips64
= 1;
4484 tdep
->default_mask_address_p
= 0;
4485 set_gdbarch_long_bit (gdbarch
, 32);
4486 set_gdbarch_ptr_bit (gdbarch
, 32);
4487 set_gdbarch_long_long_bit (gdbarch
, 64);
4489 case MIPS_ABI_EABI32
:
4490 tdep
->mips_default_saved_regsize
= 4;
4491 tdep
->mips_default_stack_argsize
= 4;
4492 tdep
->mips_fp_register_double
= 0;
4493 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4494 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4495 tdep
->mips_regs_have_home_p
= 0;
4496 tdep
->gdb_target_is_mips64
= 0;
4497 tdep
->default_mask_address_p
= 0;
4498 set_gdbarch_long_bit (gdbarch
, 32);
4499 set_gdbarch_ptr_bit (gdbarch
, 32);
4500 set_gdbarch_long_long_bit (gdbarch
, 64);
4502 case MIPS_ABI_EABI64
:
4503 tdep
->mips_default_saved_regsize
= 8;
4504 tdep
->mips_default_stack_argsize
= 8;
4505 tdep
->mips_fp_register_double
= 1;
4506 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4507 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4508 tdep
->mips_regs_have_home_p
= 0;
4509 tdep
->gdb_target_is_mips64
= 1;
4510 tdep
->default_mask_address_p
= 0;
4511 set_gdbarch_long_bit (gdbarch
, 64);
4512 set_gdbarch_ptr_bit (gdbarch
, 64);
4513 set_gdbarch_long_long_bit (gdbarch
, 64);
4516 tdep
->mips_default_saved_regsize
= 4;
4517 tdep
->mips_default_stack_argsize
= 8;
4518 tdep
->mips_fp_register_double
= 1;
4519 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4520 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4521 tdep
->mips_regs_have_home_p
= 0;
4522 tdep
->gdb_target_is_mips64
= 0;
4523 tdep
->default_mask_address_p
= 0;
4524 set_gdbarch_long_bit (gdbarch
, 32);
4525 set_gdbarch_ptr_bit (gdbarch
, 32);
4526 set_gdbarch_long_long_bit (gdbarch
, 64);
4528 /* Set up the disassembler info, so that we get the right
4529 register names from libopcodes. */
4530 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
4531 tm_print_insn_info
.arch
= bfd_arch_mips
;
4532 if (info
.bfd_arch_info
!= NULL
4533 && info
.bfd_arch_info
->arch
== bfd_arch_mips
4534 && info
.bfd_arch_info
->mach
)
4535 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
4537 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
4540 tdep
->mips_default_saved_regsize
= 8;
4541 tdep
->mips_default_stack_argsize
= 8;
4542 tdep
->mips_fp_register_double
= 1;
4543 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4544 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4545 tdep
->mips_regs_have_home_p
= 0;
4546 tdep
->gdb_target_is_mips64
= 1;
4547 tdep
->default_mask_address_p
= 0;
4548 set_gdbarch_long_bit (gdbarch
, 64);
4549 set_gdbarch_ptr_bit (gdbarch
, 64);
4550 set_gdbarch_long_long_bit (gdbarch
, 64);
4552 /* Set up the disassembler info, so that we get the right
4553 register names from libopcodes. */
4554 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
4555 tm_print_insn_info
.arch
= bfd_arch_mips
;
4556 if (info
.bfd_arch_info
!= NULL
4557 && info
.bfd_arch_info
->arch
== bfd_arch_mips
4558 && info
.bfd_arch_info
->mach
)
4559 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
4561 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
4564 internal_error (__FILE__
, __LINE__
,
4565 "unknown ABI in switch");
4568 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4569 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4572 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4573 flag in object files because to do so would make it impossible to
4574 link with libraries compiled without "-gp32". This is
4575 unnecessarily restrictive.
4577 We could solve this problem by adding "-gp32" multilibs to gcc,
4578 but to set this flag before gcc is built with such multilibs will
4579 break too many systems.''
4581 But even more unhelpfully, the default linker output target for
4582 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4583 for 64-bit programs - you need to change the ABI to change this,
4584 and not all gcc targets support that currently. Therefore using
4585 this flag to detect 32-bit mode would do the wrong thing given
4586 the current gcc - it would make GDB treat these 64-bit programs
4587 as 32-bit programs by default. */
4589 /* enable/disable the MIPS FPU */
4590 if (!mips_fpu_type_auto
)
4591 tdep
->mips_fpu_type
= mips_fpu_type
;
4592 else if (info
.bfd_arch_info
!= NULL
4593 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4594 switch (info
.bfd_arch_info
->mach
)
4596 case bfd_mach_mips3900
:
4597 case bfd_mach_mips4100
:
4598 case bfd_mach_mips4111
:
4599 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
4601 case bfd_mach_mips4650
:
4602 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
4605 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4609 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4611 /* MIPS version of register names. NOTE: At present the MIPS
4612 register name management is part way between the old -
4613 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4614 Further work on it is required. */
4615 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4616 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
4617 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4618 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4619 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4620 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4622 /* Add/remove bits from an address. The MIPS needs be careful to
4623 ensure that all 32 bit addresses are sign extended to 64 bits. */
4624 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
4626 /* There's a mess in stack frame creation. See comments in
4627 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
4628 set_gdbarch_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
4629 set_gdbarch_init_frame_pc (gdbarch
, init_frame_pc_noop
);
4631 /* Map debug register numbers onto internal register numbers. */
4632 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
4633 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_ecoff_reg_to_regnum
);
4635 /* Initialize a frame */
4636 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
4638 /* MIPS version of CALL_DUMMY */
4640 set_gdbarch_call_dummy_p (gdbarch
, 1);
4641 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4642 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
4643 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4644 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4645 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4646 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4647 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4648 set_gdbarch_call_dummy_length (gdbarch
, 0);
4649 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4650 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4651 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4652 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4653 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4654 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4655 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4657 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4658 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
4660 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4661 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
4662 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4664 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
4665 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
4667 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
4668 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
4669 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
4671 /* There are MIPS targets which do not yet use this since they still
4672 define REGISTER_VIRTUAL_TYPE. */
4673 set_gdbarch_register_virtual_type (gdbarch
, mips_register_virtual_type
);
4675 /* Hook in OS ABI-specific overrides, if they have been registered. */
4676 gdbarch_init_osabi (info
, gdbarch
, osabi
);
4682 mips_abi_update (char *ignore_args
, int from_tty
,
4683 struct cmd_list_element
*c
)
4685 struct gdbarch_info info
;
4687 /* Force the architecture to update, and (if it's a MIPS architecture)
4688 mips_gdbarch_init will take care of the rest. */
4689 gdbarch_info_init (&info
);
4690 gdbarch_update_p (info
);
4694 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4696 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4700 int ef_mips_32bitmode
;
4701 /* determine the ISA */
4702 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
4720 /* determine the size of a pointer */
4721 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
4722 fprintf_unfiltered (file
,
4723 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4725 fprintf_unfiltered (file
,
4726 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4728 fprintf_unfiltered (file
,
4729 "mips_dump_tdep: ef_mips_arch = %d\n",
4731 fprintf_unfiltered (file
,
4732 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4734 mips_abi_strings
[tdep
->mips_abi
]);
4735 fprintf_unfiltered (file
,
4736 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4737 mips_mask_address_p (),
4738 tdep
->default_mask_address_p
);
4740 fprintf_unfiltered (file
,
4741 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4742 FP_REGISTER_DOUBLE
);
4743 fprintf_unfiltered (file
,
4744 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4745 MIPS_DEFAULT_FPU_TYPE
,
4746 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4747 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4748 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4750 fprintf_unfiltered (file
,
4751 "mips_dump_tdep: MIPS_EABI = %d\n",
4753 fprintf_unfiltered (file
,
4754 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4755 MIPS_LAST_FP_ARG_REGNUM
,
4756 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
4757 fprintf_unfiltered (file
,
4758 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4760 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4761 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4762 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4764 fprintf_unfiltered (file
,
4765 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4766 MIPS_DEFAULT_SAVED_REGSIZE
);
4767 fprintf_unfiltered (file
,
4768 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4769 FP_REGISTER_DOUBLE
);
4770 fprintf_unfiltered (file
,
4771 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4772 MIPS_REGS_HAVE_HOME_P
);
4773 fprintf_unfiltered (file
,
4774 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4775 MIPS_DEFAULT_STACK_ARGSIZE
);
4776 fprintf_unfiltered (file
,
4777 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4778 MIPS_STACK_ARGSIZE
);
4779 fprintf_unfiltered (file
,
4780 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4782 fprintf_unfiltered (file
,
4783 "mips_dump_tdep: A0_REGNUM = %d\n",
4785 fprintf_unfiltered (file
,
4786 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4787 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
4788 fprintf_unfiltered (file
,
4789 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4790 XSTRING (ATTACH_DETACH
));
4791 fprintf_unfiltered (file
,
4792 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4794 fprintf_unfiltered (file
,
4795 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4796 fprintf_unfiltered (file
,
4797 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4799 fprintf_unfiltered (file
,
4800 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4802 fprintf_unfiltered (file
,
4803 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4805 fprintf_unfiltered (file
,
4806 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4807 XSTRING (DO_REGISTERS_INFO
));
4808 fprintf_unfiltered (file
,
4809 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4810 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
4811 fprintf_unfiltered (file
,
4812 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4813 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
4814 fprintf_unfiltered (file
,
4815 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4816 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
4817 fprintf_unfiltered (file
,
4818 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4820 fprintf_unfiltered (file
,
4821 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4823 fprintf_unfiltered (file
,
4824 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4825 FIRST_EMBED_REGNUM
);
4826 fprintf_unfiltered (file
,
4827 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4829 fprintf_unfiltered (file
,
4830 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4831 GDB_TARGET_IS_MIPS64
);
4832 fprintf_unfiltered (file
,
4833 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4834 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
4835 fprintf_unfiltered (file
,
4836 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4837 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
4838 fprintf_unfiltered (file
,
4839 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4841 fprintf_unfiltered (file
,
4842 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4843 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
4844 fprintf_unfiltered (file
,
4845 "mips_dump_tdep: HI_REGNUM = %d\n",
4847 fprintf_unfiltered (file
,
4848 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4849 fprintf_unfiltered (file
,
4850 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4851 fprintf_unfiltered (file
,
4852 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4853 XSTRING (IGNORE_HELPER_CALL (PC
)));
4854 fprintf_unfiltered (file
,
4855 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4856 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
4857 fprintf_unfiltered (file
,
4858 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4859 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
4860 fprintf_unfiltered (file
,
4861 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4862 fprintf_unfiltered (file
,
4863 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4865 fprintf_unfiltered (file
,
4866 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4867 fprintf_unfiltered (file
,
4868 "mips_dump_tdep: LO_REGNUM = %d\n",
4870 #ifdef MACHINE_CPROC_FP_OFFSET
4871 fprintf_unfiltered (file
,
4872 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4873 MACHINE_CPROC_FP_OFFSET
);
4875 #ifdef MACHINE_CPROC_PC_OFFSET
4876 fprintf_unfiltered (file
,
4877 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4878 MACHINE_CPROC_PC_OFFSET
);
4880 #ifdef MACHINE_CPROC_SP_OFFSET
4881 fprintf_unfiltered (file
,
4882 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4883 MACHINE_CPROC_SP_OFFSET
);
4885 fprintf_unfiltered (file
,
4886 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4887 fprintf_unfiltered (file
,
4888 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4889 fprintf_unfiltered (file
,
4890 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4892 fprintf_unfiltered (file
,
4893 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4894 fprintf_unfiltered (file
,
4895 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4896 fprintf_unfiltered (file
,
4897 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4898 fprintf_unfiltered (file
,
4899 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4901 fprintf_unfiltered (file
,
4902 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
4903 MIPS_LAST_ARG_REGNUM
,
4904 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
4905 fprintf_unfiltered (file
,
4906 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4908 fprintf_unfiltered (file
,
4909 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4910 fprintf_unfiltered (file
,
4911 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4912 MIPS_SAVED_REGSIZE
);
4913 fprintf_unfiltered (file
,
4914 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4915 fprintf_unfiltered (file
,
4916 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4917 XSTRING (MSYMBOL_SIZE (MSYM
)));
4918 fprintf_unfiltered (file
,
4919 "mips_dump_tdep: OP_LDFPR = used?\n");
4920 fprintf_unfiltered (file
,
4921 "mips_dump_tdep: OP_LDGPR = used?\n");
4922 fprintf_unfiltered (file
,
4923 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4924 fprintf_unfiltered (file
,
4925 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4926 fprintf_unfiltered (file
,
4927 "mips_dump_tdep: PRID_REGNUM = %d\n",
4929 fprintf_unfiltered (file
,
4930 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4931 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
4932 fprintf_unfiltered (file
,
4933 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4934 fprintf_unfiltered (file
,
4935 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4936 fprintf_unfiltered (file
,
4937 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4938 fprintf_unfiltered (file
,
4939 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4940 fprintf_unfiltered (file
,
4941 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4942 fprintf_unfiltered (file
,
4943 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4944 fprintf_unfiltered (file
,
4945 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4946 fprintf_unfiltered (file
,
4947 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4948 fprintf_unfiltered (file
,
4949 "mips_dump_tdep: PROC_PC_REG = function?\n");
4950 fprintf_unfiltered (file
,
4951 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4952 fprintf_unfiltered (file
,
4953 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4954 fprintf_unfiltered (file
,
4955 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4956 fprintf_unfiltered (file
,
4957 "mips_dump_tdep: PS_REGNUM = %d\n",
4959 fprintf_unfiltered (file
,
4960 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4962 fprintf_unfiltered (file
,
4963 "mips_dump_tdep: RA_REGNUM = %d\n",
4965 fprintf_unfiltered (file
,
4966 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4967 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4968 fprintf_unfiltered (file
,
4969 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4970 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4971 fprintf_unfiltered (file
,
4972 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4973 fprintf_unfiltered (file
,
4974 "mips_dump_tdep: ROUND_DOWN = function?\n");
4975 fprintf_unfiltered (file
,
4976 "mips_dump_tdep: ROUND_UP = function?\n");
4978 fprintf_unfiltered (file
,
4979 "mips_dump_tdep: SAVED_BYTES = %d\n",
4983 fprintf_unfiltered (file
,
4984 "mips_dump_tdep: SAVED_FP = %d\n",
4988 fprintf_unfiltered (file
,
4989 "mips_dump_tdep: SAVED_PC = %d\n",
4992 fprintf_unfiltered (file
,
4993 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
4994 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
4995 fprintf_unfiltered (file
,
4996 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
4997 fprintf_unfiltered (file
,
4998 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
5000 fprintf_unfiltered (file
,
5001 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
5002 SIGFRAME_FPREGSAVE_OFF
);
5003 fprintf_unfiltered (file
,
5004 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
5006 fprintf_unfiltered (file
,
5007 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
5008 SIGFRAME_REGSAVE_OFF
);
5009 fprintf_unfiltered (file
,
5010 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
5012 fprintf_unfiltered (file
,
5013 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
5014 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
5015 fprintf_unfiltered (file
,
5016 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
5017 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
5018 fprintf_unfiltered (file
,
5019 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
5020 SOFTWARE_SINGLE_STEP_P ());
5021 fprintf_unfiltered (file
,
5022 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
5023 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
5024 #ifdef STACK_END_ADDR
5025 fprintf_unfiltered (file
,
5026 "mips_dump_tdep: STACK_END_ADDR = %d\n",
5029 fprintf_unfiltered (file
,
5030 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
5031 XSTRING (STEP_SKIPS_DELAY (PC
)));
5032 fprintf_unfiltered (file
,
5033 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
5034 STEP_SKIPS_DELAY_P
);
5035 fprintf_unfiltered (file
,
5036 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
5037 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
5038 fprintf_unfiltered (file
,
5039 "mips_dump_tdep: T9_REGNUM = %d\n",
5041 fprintf_unfiltered (file
,
5042 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
5043 fprintf_unfiltered (file
,
5044 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
5045 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
5046 fprintf_unfiltered (file
,
5047 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
5048 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
5049 fprintf_unfiltered (file
,
5050 "mips_dump_tdep: TARGET_MIPS = used?\n");
5051 fprintf_unfiltered (file
,
5052 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
5053 XSTRING (TM_PRINT_INSN_MACH
));
5055 fprintf_unfiltered (file
,
5056 "mips_dump_tdep: TRACE_CLEAR # %s\n",
5057 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
5060 fprintf_unfiltered (file
,
5061 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
5064 #ifdef TRACE_FLAVOR_SIZE
5065 fprintf_unfiltered (file
,
5066 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
5070 fprintf_unfiltered (file
,
5071 "mips_dump_tdep: TRACE_SET # %s\n",
5072 XSTRING (TRACE_SET (X
,STATE
)));
5074 fprintf_unfiltered (file
,
5075 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
5076 #ifdef UNUSED_REGNUM
5077 fprintf_unfiltered (file
,
5078 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
5081 fprintf_unfiltered (file
,
5082 "mips_dump_tdep: V0_REGNUM = %d\n",
5084 fprintf_unfiltered (file
,
5085 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
5086 (long) VM_MIN_ADDRESS
);
5088 fprintf_unfiltered (file
,
5089 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
5092 fprintf_unfiltered (file
,
5093 "mips_dump_tdep: ZERO_REGNUM = %d\n",
5095 fprintf_unfiltered (file
,
5096 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
5099 fprintf_unfiltered (file
,
5100 "mips_dump_tdep: OS ABI = %s\n",
5101 gdbarch_osabi_name (tdep
->osabi
));
5105 _initialize_mips_tdep (void)
5107 static struct cmd_list_element
*mipsfpulist
= NULL
;
5108 struct cmd_list_element
*c
;
5110 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5111 if (MIPS_ABI_LAST
+ 1
5112 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5113 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
5115 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5116 if (!tm_print_insn
) /* Someone may have already set it */
5117 tm_print_insn
= gdb_print_insn_mips
;
5119 /* Add root prefix command for all "set mips"/"show mips" commands */
5120 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5121 "Various MIPS specific commands.",
5122 &setmipscmdlist
, "set mips ", 0, &setlist
);
5124 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5125 "Various MIPS specific commands.",
5126 &showmipscmdlist
, "show mips ", 0, &showlist
);
5128 /* Allow the user to override the saved register size. */
5129 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
5132 &mips_saved_regsize_string
, "\
5133 Set size of general purpose registers saved on the stack.\n\
5134 This option can be set to one of:\n\
5135 32 - Force GDB to treat saved GP registers as 32-bit\n\
5136 64 - Force GDB to treat saved GP registers as 64-bit\n\
5137 auto - Allow GDB to use the target's default setting or autodetect the\n\
5138 saved GP register size from information contained in the executable.\n\
5143 /* Allow the user to override the argument stack size. */
5144 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
5147 &mips_stack_argsize_string
, "\
5148 Set the amount of stack space reserved for each argument.\n\
5149 This option can be set to one of:\n\
5150 32 - Force GDB to allocate 32-bit chunks per argument\n\
5151 64 - Force GDB to allocate 64-bit chunks per argument\n\
5152 auto - Allow GDB to determine the correct setting from the current\n\
5153 target and executable (default)",
5157 /* Allow the user to override the ABI. */
5158 c
= add_set_enum_cmd
5159 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
5160 "Set the ABI used by this program.\n"
5161 "This option can be set to one of:\n"
5162 " auto - the default ABI associated with the current binary\n"
5170 add_show_from_set (c
, &showmipscmdlist
);
5171 set_cmd_sfunc (c
, mips_abi_update
);
5173 /* Let the user turn off floating point and set the fence post for
5174 heuristic_proc_start. */
5176 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5177 "Set use of MIPS floating-point coprocessor.",
5178 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5179 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5180 "Select single-precision MIPS floating-point coprocessor.",
5182 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5183 "Select double-precision MIPS floating-point coprocessor.",
5185 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5186 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5187 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5188 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5189 "Select no MIPS floating-point coprocessor.",
5191 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5192 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5193 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5194 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5195 "Select MIPS floating-point coprocessor automatically.",
5197 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5198 "Show current use of MIPS floating-point coprocessor target.",
5201 /* We really would like to have both "0" and "unlimited" work, but
5202 command.c doesn't deal with that. So make it a var_zinteger
5203 because the user can always use "999999" or some such for unlimited. */
5204 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
5205 (char *) &heuristic_fence_post
,
5207 Set the distance searched for the start of a function.\n\
5208 If you are debugging a stripped executable, GDB needs to search through the\n\
5209 program for the start of a function. This command sets the distance of the\n\
5210 search. The only need to set it is when debugging a stripped executable.",
5212 /* We need to throw away the frame cache when we set this, since it
5213 might change our ability to get backtraces. */
5214 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
5215 add_show_from_set (c
, &showlist
);
5217 /* Allow the user to control whether the upper bits of 64-bit
5218 addresses should be zeroed. */
5219 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
5220 Set zeroing of upper 32 bits of 64-bit addresses.\n\
5221 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5222 allow GDB to determine the correct value.\n", "\
5223 Show zeroing of upper 32 bits of 64-bit addresses.",
5224 NULL
, show_mask_address
,
5225 &setmipscmdlist
, &showmipscmdlist
);
5227 /* Allow the user to control the size of 32 bit registers within the
5228 raw remote packet. */
5229 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
5232 (char *)&mips64_transfers_32bit_regs_p
, "\
5233 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
5234 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5235 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5236 64 bits for others. Use \"off\" to disable compatibility mode",
5240 /* Debug this files internals. */
5241 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
5242 &mips_debug
, "Set mips debugging.\n\
5243 When non-zero, mips specific debugging is enabled.", &setdebuglist
),