1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
63 static const struct objfile_data
*mips_pdr_data
;
65 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
67 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
68 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
69 #define ST0_FR (1 << 26)
71 /* The sizes of floating point registers. */
75 MIPS_FPU_SINGLE_REGSIZE
= 4,
76 MIPS_FPU_DOUBLE_REGSIZE
= 8
85 static const char *mips_abi_string
;
87 static const char *mips_abi_strings
[] = {
98 /* The standard register names, and all the valid aliases for them. */
105 /* Aliases for o32 and most other ABIs. */
106 const struct register_alias mips_o32_aliases
[] = {
113 /* Aliases for n32 and n64. */
114 const struct register_alias mips_n32_n64_aliases
[] = {
121 /* Aliases for ABI-independent registers. */
122 const struct register_alias mips_register_aliases
[] = {
123 /* The architecture manuals specify these ABI-independent names for
125 #define R(n) { "r" #n, n }
126 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
127 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
128 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
129 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
132 /* k0 and k1 are sometimes called these instead (for "kernel
137 /* This is the traditional GDB name for the CP0 status register. */
138 { "sr", MIPS_PS_REGNUM
},
140 /* This is the traditional GDB name for the CP0 BadVAddr register. */
141 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
143 /* This is the traditional GDB name for the FCSR. */
144 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
147 const struct register_alias mips_numeric_register_aliases
[] = {
148 #define R(n) { #n, n }
149 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
150 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
151 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
152 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
156 #ifndef MIPS_DEFAULT_FPU_TYPE
157 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
159 static int mips_fpu_type_auto
= 1;
160 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
162 static int mips_debug
= 0;
164 /* Properties (for struct target_desc) describing the g/G packet
166 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
167 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
169 struct target_desc
*mips_tdesc_gp32
;
170 struct target_desc
*mips_tdesc_gp64
;
172 const struct mips_regnum
*
173 mips_regnum (struct gdbarch
*gdbarch
)
175 return gdbarch_tdep (gdbarch
)->regnum
;
179 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
181 return mips_regnum (gdbarch
)->fp0
+ 12;
184 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
186 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
188 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
189 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
191 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
192 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
194 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
196 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
197 functions to test, set, or clear bit 0 of addresses. */
200 is_mips16_addr (CORE_ADDR addr
)
206 unmake_mips16_addr (CORE_ADDR addr
)
208 return ((addr
) & ~(CORE_ADDR
) 1);
212 make_mips16_addr (CORE_ADDR addr
)
214 return ((addr
) | (CORE_ADDR
) 1);
217 /* Return the MIPS ABI associated with GDBARCH. */
219 mips_abi (struct gdbarch
*gdbarch
)
221 return gdbarch_tdep (gdbarch
)->mips_abi
;
225 mips_isa_regsize (struct gdbarch
*gdbarch
)
227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
229 /* If we know how big the registers are, use that size. */
230 if (tdep
->register_size_valid_p
)
231 return tdep
->register_size
;
233 /* Fall back to the previous behavior. */
234 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
235 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
238 /* Return the currently configured (or set) saved register size. */
241 mips_abi_regsize (struct gdbarch
*gdbarch
)
243 switch (mips_abi (gdbarch
))
245 case MIPS_ABI_EABI32
:
251 case MIPS_ABI_EABI64
:
253 case MIPS_ABI_UNKNOWN
:
256 internal_error (__FILE__
, __LINE__
, _("bad switch"));
260 /* Functions for setting and testing a bit in a minimal symbol that
261 marks it as 16-bit function. The MSB of the minimal symbol's
262 "info" field is used for this purpose.
264 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
265 i.e. refers to a 16-bit function, and sets a "special" bit in a
266 minimal symbol to mark it as a 16-bit function
268 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
271 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
273 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
275 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
280 msymbol_is_special (struct minimal_symbol
*msym
)
282 return MSYMBOL_TARGET_FLAG_1 (msym
);
285 /* XFER a value from the big/little/left end of the register.
286 Depending on the size of the value it might occupy the entire
287 register or just part of it. Make an allowance for this, aligning
288 things accordingly. */
291 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
292 int reg_num
, int length
,
293 enum bfd_endian endian
, gdb_byte
*in
,
294 const gdb_byte
*out
, int buf_offset
)
298 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
299 /* Need to transfer the left or right part of the register, based on
300 the targets byte order. */
304 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
306 case BFD_ENDIAN_LITTLE
:
309 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
313 internal_error (__FILE__
, __LINE__
, _("bad switch"));
316 fprintf_unfiltered (gdb_stderr
,
317 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
318 reg_num
, reg_offset
, buf_offset
, length
);
319 if (mips_debug
&& out
!= NULL
)
322 fprintf_unfiltered (gdb_stdlog
, "out ");
323 for (i
= 0; i
< length
; i
++)
324 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
327 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
330 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
332 if (mips_debug
&& in
!= NULL
)
335 fprintf_unfiltered (gdb_stdlog
, "in ");
336 for (i
= 0; i
< length
; i
++)
337 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
340 fprintf_unfiltered (gdb_stdlog
, "\n");
343 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
344 compatiblity mode. A return value of 1 means that we have
345 physical 64-bit registers, but should treat them as 32-bit registers. */
348 mips2_fp_compat (struct frame_info
*frame
)
350 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
351 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
353 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
357 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
358 in all the places we deal with FP registers. PR gdb/413. */
359 /* Otherwise check the FR bit in the status register - it controls
360 the FP compatiblity mode. If it is clear we are in compatibility
362 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
369 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
371 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
373 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
375 /* The list of available "set mips " and "show mips " commands. */
377 static struct cmd_list_element
*setmipscmdlist
= NULL
;
378 static struct cmd_list_element
*showmipscmdlist
= NULL
;
380 /* Integer registers 0 thru 31 are handled explicitly by
381 mips_register_name(). Processor specific registers 32 and above
382 are listed in the following tables. */
385 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
389 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
390 "sr", "lo", "hi", "bad", "cause", "pc",
391 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
392 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
393 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
394 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
395 "fsr", "fir", "" /*"fp" */ , "",
396 "", "", "", "", "", "", "", "",
397 "", "", "", "", "", "", "", "",
400 /* Names of IDT R3041 registers. */
402 static const char *mips_r3041_reg_names
[] = {
403 "sr", "lo", "hi", "bad", "cause", "pc",
404 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
405 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
406 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
407 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
408 "fsr", "fir", "", /*"fp" */ "",
409 "", "", "bus", "ccfg", "", "", "", "",
410 "", "", "port", "cmp", "", "", "epc", "prid",
413 /* Names of tx39 registers. */
415 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
416 "sr", "lo", "hi", "bad", "cause", "pc",
417 "", "", "", "", "", "", "", "",
418 "", "", "", "", "", "", "", "",
419 "", "", "", "", "", "", "", "",
420 "", "", "", "", "", "", "", "",
422 "", "", "", "", "", "", "", "",
423 "", "", "config", "cache", "debug", "depc", "epc", ""
426 /* Names of IRIX registers. */
427 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
428 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
429 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
430 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
431 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
432 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
436 /* Return the name of the register corresponding to REGNO. */
438 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
440 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
441 /* GPR names for all ABIs other than n32/n64. */
442 static char *mips_gpr_names
[] = {
443 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
444 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
445 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
446 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
449 /* GPR names for n32 and n64 ABIs. */
450 static char *mips_n32_n64_gpr_names
[] = {
451 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
452 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
453 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
454 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
457 enum mips_abi abi
= mips_abi (gdbarch
);
459 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
460 but then don't make the raw register names visible. This (upper)
461 range of user visible register numbers are the pseudo-registers.
463 This approach was adopted accommodate the following scenario:
464 It is possible to debug a 64-bit device using a 32-bit
465 programming model. In such instances, the raw registers are
466 configured to be 64-bits wide, while the pseudo registers are
467 configured to be 32-bits wide. The registers that the user
468 sees - the pseudo registers - match the users expectations
469 given the programming model being used. */
470 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
471 if (regno
< gdbarch_num_regs (gdbarch
))
474 /* The MIPS integer registers are always mapped from 0 to 31. The
475 names of the registers (which reflects the conventions regarding
476 register use) vary depending on the ABI. */
477 if (0 <= rawnum
&& rawnum
< 32)
479 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
480 return mips_n32_n64_gpr_names
[rawnum
];
482 return mips_gpr_names
[rawnum
];
484 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
485 return tdesc_register_name (gdbarch
, rawnum
);
486 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
488 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
489 return tdep
->mips_processor_reg_names
[rawnum
- 32];
492 internal_error (__FILE__
, __LINE__
,
493 _("mips_register_name: bad register number %d"), rawnum
);
496 /* Return the groups that a MIPS register can be categorised into. */
499 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
500 struct reggroup
*reggroup
)
505 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
506 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
507 if (reggroup
== all_reggroup
)
509 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
510 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
511 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
512 (gdbarch), as not all architectures are multi-arch. */
513 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
514 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
515 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
517 if (reggroup
== float_reggroup
)
518 return float_p
&& pseudo
;
519 if (reggroup
== vector_reggroup
)
520 return vector_p
&& pseudo
;
521 if (reggroup
== general_reggroup
)
522 return (!vector_p
&& !float_p
) && pseudo
;
523 /* Save the pseudo registers. Need to make certain that any code
524 extracting register values from a saved register cache also uses
526 if (reggroup
== save_reggroup
)
527 return raw_p
&& pseudo
;
528 /* Restore the same pseudo register. */
529 if (reggroup
== restore_reggroup
)
530 return raw_p
&& pseudo
;
534 /* Return the groups that a MIPS register can be categorised into.
535 This version is only used if we have a target description which
536 describes real registers (and their groups). */
539 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
540 struct reggroup
*reggroup
)
542 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
543 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
546 /* Only save, restore, and display the pseudo registers. Need to
547 make certain that any code extracting register values from a
548 saved register cache also uses pseudo registers.
550 Note: saving and restoring the pseudo registers is slightly
551 strange; if we have 64 bits, we should save and restore all
552 64 bits. But this is hard and has little benefit. */
556 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
560 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
563 /* Map the symbol table registers which live in the range [1 *
564 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
565 registers. Take care of alignment and size problems. */
567 static enum register_status
568 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
569 int cookednum
, gdb_byte
*buf
)
571 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
572 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
573 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
574 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
575 return regcache_raw_read (regcache
, rawnum
, buf
);
576 else if (register_size (gdbarch
, rawnum
) >
577 register_size (gdbarch
, cookednum
))
579 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
580 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
583 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
585 enum register_status status
;
587 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
588 if (status
== REG_VALID
)
589 store_signed_integer (buf
, 4, byte_order
, regval
);
594 internal_error (__FILE__
, __LINE__
, _("bad register size"));
598 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
599 struct regcache
*regcache
, int cookednum
,
602 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
603 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
604 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
605 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
606 regcache_raw_write (regcache
, rawnum
, buf
);
607 else if (register_size (gdbarch
, rawnum
) >
608 register_size (gdbarch
, cookednum
))
610 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
611 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
614 /* Sign extend the shortened version of the register prior
615 to placing it in the raw register. This is required for
616 some mips64 parts in order to avoid unpredictable behavior. */
617 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
618 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
619 regcache_raw_write_signed (regcache
, rawnum
, regval
);
623 internal_error (__FILE__
, __LINE__
, _("bad register size"));
627 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
628 struct agent_expr
*ax
, int reg
)
630 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
631 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
632 && reg
< 2 * gdbarch_num_regs (gdbarch
));
634 ax_reg_mask (ax
, rawnum
);
640 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
641 struct agent_expr
*ax
, int reg
)
643 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
644 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
645 && reg
< 2 * gdbarch_num_regs (gdbarch
));
646 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
650 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
652 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
653 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
656 ax_simple (ax
, aop_lsh
);
659 ax_simple (ax
, aop_rsh_signed
);
663 internal_error (__FILE__
, __LINE__
, _("bad register size"));
668 /* Table to translate MIPS16 register field to actual register number. */
669 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
671 /* Heuristic_proc_start may hunt through the text section for a long
672 time across a 2400 baud serial line. Allows the user to limit this
675 static unsigned int heuristic_fence_post
= 0;
677 /* Number of bytes of storage in the actual machine representation for
678 register N. NOTE: This defines the pseudo register type so need to
679 rebuild the architecture vector. */
681 static int mips64_transfers_32bit_regs_p
= 0;
684 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
685 struct cmd_list_element
*c
)
687 struct gdbarch_info info
;
688 gdbarch_info_init (&info
);
689 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
690 instead of relying on globals. Doing that would let generic code
691 handle the search for this specific architecture. */
692 if (!gdbarch_update_p (info
))
694 mips64_transfers_32bit_regs_p
= 0;
695 error (_("32-bit compatibility mode not supported"));
699 /* Convert to/from a register and the corresponding memory value. */
701 /* This predicate tests for the case of an 8 byte floating point
702 value that is being transferred to or from a pair of floating point
703 registers each of which are (or are considered to be) only 4 bytes
706 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
709 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
710 && register_size (gdbarch
, regnum
) == 4
711 && (regnum
% gdbarch_num_regs (gdbarch
))
712 >= mips_regnum (gdbarch
)->fp0
713 && (regnum
% gdbarch_num_regs (gdbarch
))
714 < mips_regnum (gdbarch
)->fp0
+ 32
715 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
718 /* This predicate tests for the case of a value of less than 8
719 bytes in width that is being transfered to or from an 8 byte
720 general purpose register. */
722 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
725 int num_regs
= gdbarch_num_regs (gdbarch
);
727 return (register_size (gdbarch
, regnum
) == 8
728 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
729 && TYPE_LENGTH (type
) < 8);
733 mips_convert_register_p (struct gdbarch
*gdbarch
,
734 int regnum
, struct type
*type
)
736 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
737 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
741 mips_register_to_value (struct frame_info
*frame
, int regnum
,
742 struct type
*type
, gdb_byte
*to
,
743 int *optimizedp
, int *unavailablep
)
745 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
747 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
749 get_frame_register (frame
, regnum
+ 0, to
+ 4);
750 get_frame_register (frame
, regnum
+ 1, to
+ 0);
752 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
753 optimizedp
, unavailablep
))
756 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
757 optimizedp
, unavailablep
))
759 *optimizedp
= *unavailablep
= 0;
762 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
764 int len
= TYPE_LENGTH (type
);
767 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
768 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
769 optimizedp
, unavailablep
))
772 *optimizedp
= *unavailablep
= 0;
777 internal_error (__FILE__
, __LINE__
,
778 _("mips_register_to_value: unrecognized case"));
783 mips_value_to_register (struct frame_info
*frame
, int regnum
,
784 struct type
*type
, const gdb_byte
*from
)
786 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
788 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
790 put_frame_register (frame
, regnum
+ 0, from
+ 4);
791 put_frame_register (frame
, regnum
+ 1, from
+ 0);
793 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
796 int len
= TYPE_LENGTH (type
);
798 /* Sign extend values, irrespective of type, that are stored to
799 a 64-bit general purpose register. (32-bit unsigned values
800 are stored as signed quantities within a 64-bit register.
801 When performing an operation, in compiled code, that combines
802 a 32-bit unsigned value with a signed 64-bit value, a type
803 conversion is first performed that zeroes out the high 32 bits.) */
804 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
807 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
809 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
810 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
811 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
815 if (from
[len
-1] & 0x80)
816 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
818 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
819 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
820 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
825 internal_error (__FILE__
, __LINE__
,
826 _("mips_value_to_register: unrecognized case"));
830 /* Return the GDB type object for the "standard" data type of data in
834 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
836 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
837 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
838 && (regnum
% gdbarch_num_regs (gdbarch
))
839 < mips_regnum (gdbarch
)->fp0
+ 32)
841 /* The floating-point registers raw, or cooked, always match
842 mips_isa_regsize(), and also map 1:1, byte for byte. */
843 if (mips_isa_regsize (gdbarch
) == 4)
844 return builtin_type (gdbarch
)->builtin_float
;
846 return builtin_type (gdbarch
)->builtin_double
;
848 else if (regnum
< gdbarch_num_regs (gdbarch
))
850 /* The raw or ISA registers. These are all sized according to
852 if (mips_isa_regsize (gdbarch
) == 4)
853 return builtin_type (gdbarch
)->builtin_int32
;
855 return builtin_type (gdbarch
)->builtin_int64
;
859 /* The cooked or ABI registers. These are sized according to
860 the ABI (with a few complications). */
861 if (regnum
>= (gdbarch_num_regs (gdbarch
)
862 + mips_regnum (gdbarch
)->fp_control_status
)
863 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
864 /* The pseudo/cooked view of the embedded registers is always
865 32-bit. The raw view is handled below. */
866 return builtin_type (gdbarch
)->builtin_int32
;
867 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
868 /* The target, while possibly using a 64-bit register buffer,
869 is only transfering 32-bits of each integer register.
870 Reflect this in the cooked/pseudo (ABI) register value. */
871 return builtin_type (gdbarch
)->builtin_int32
;
872 else if (mips_abi_regsize (gdbarch
) == 4)
873 /* The ABI is restricted to 32-bit registers (the ISA could be
875 return builtin_type (gdbarch
)->builtin_int32
;
878 return builtin_type (gdbarch
)->builtin_int64
;
882 /* Return the GDB type for the pseudo register REGNUM, which is the
883 ABI-level view. This function is only called if there is a target
884 description which includes registers, so we know precisely the
885 types of hardware registers. */
888 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
890 const int num_regs
= gdbarch_num_regs (gdbarch
);
891 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
892 int rawnum
= regnum
% num_regs
;
893 struct type
*rawtype
;
895 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
897 /* Absent registers are still absent. */
898 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
899 if (TYPE_LENGTH (rawtype
) == 0)
902 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
903 /* Present the floating point registers however the hardware did;
904 do not try to convert between FPU layouts. */
907 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
909 /* The pseudo/cooked view of embedded registers is always
910 32-bit, even if the target transfers 64-bit values for them.
911 New targets relying on XML descriptions should only transfer
912 the necessary 32 bits, but older versions of GDB expected 64,
913 so allow the target to provide 64 bits without interfering
914 with the displayed type. */
915 return builtin_type (gdbarch
)->builtin_int32
;
918 /* Use pointer types for registers if we can. For n32 we can not,
919 since we do not have a 64-bit pointer type. */
920 if (mips_abi_regsize (gdbarch
)
921 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
923 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
924 return builtin_type (gdbarch
)->builtin_data_ptr
;
925 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
926 return builtin_type (gdbarch
)->builtin_func_ptr
;
929 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
930 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
931 return builtin_type (gdbarch
)->builtin_int32
;
933 /* For all other registers, pass through the hardware type. */
937 /* Should the upper word of 64-bit addresses be zeroed? */
938 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
941 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
943 switch (mask_address_var
)
945 case AUTO_BOOLEAN_TRUE
:
947 case AUTO_BOOLEAN_FALSE
:
950 case AUTO_BOOLEAN_AUTO
:
951 return tdep
->default_mask_address_p
;
953 internal_error (__FILE__
, __LINE__
,
954 _("mips_mask_address_p: bad switch"));
960 show_mask_address (struct ui_file
*file
, int from_tty
,
961 struct cmd_list_element
*c
, const char *value
)
963 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
965 deprecated_show_value_hack (file
, from_tty
, c
, value
);
966 switch (mask_address_var
)
968 case AUTO_BOOLEAN_TRUE
:
969 printf_filtered ("The 32 bit mips address mask is enabled\n");
971 case AUTO_BOOLEAN_FALSE
:
972 printf_filtered ("The 32 bit mips address mask is disabled\n");
974 case AUTO_BOOLEAN_AUTO
:
976 ("The 32 bit address mask is set automatically. Currently %s\n",
977 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
980 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
985 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
988 mips_pc_is_mips16 (CORE_ADDR memaddr
)
990 struct minimal_symbol
*sym
;
992 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
993 if (is_mips16_addr (memaddr
))
996 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
997 the high bit of the info field. Use this to decide if the function is
998 MIPS16 or normal MIPS. */
999 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1001 return msymbol_is_special (sym
);
1006 /* MIPS believes that the PC has a sign extended value. Perhaps the
1007 all registers should be sign extended for simplicity? */
1010 mips_read_pc (struct regcache
*regcache
)
1013 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1014 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1015 if (is_mips16_addr (pc
))
1016 pc
= unmake_mips16_addr (pc
);
1021 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1025 pc
= frame_unwind_register_signed
1026 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
1027 if (is_mips16_addr (pc
))
1028 pc
= unmake_mips16_addr (pc
);
1033 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1035 return frame_unwind_register_signed
1036 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1039 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1040 dummy frame. The frame ID's base needs to match the TOS value
1041 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1044 static struct frame_id
1045 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1047 return frame_id_build
1048 (get_frame_register_signed (this_frame
,
1049 gdbarch_num_regs (gdbarch
)
1051 get_frame_pc (this_frame
));
1055 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1057 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1058 if (mips_pc_is_mips16 (pc
))
1059 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
1061 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1064 /* Fetch and return instruction from the specified location. If the PC
1065 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1068 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1070 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1071 gdb_byte buf
[MIPS_INSN32_SIZE
];
1075 if (mips_pc_is_mips16 (addr
))
1077 instlen
= MIPS_INSN16_SIZE
;
1078 addr
= unmake_mips16_addr (addr
);
1081 instlen
= MIPS_INSN32_SIZE
;
1082 status
= target_read_memory (addr
, buf
, instlen
);
1084 memory_error (status
, addr
);
1085 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1088 /* These are the fields of 32 bit mips instructions. */
1089 #define mips32_op(x) (x >> 26)
1090 #define itype_op(x) (x >> 26)
1091 #define itype_rs(x) ((x >> 21) & 0x1f)
1092 #define itype_rt(x) ((x >> 16) & 0x1f)
1093 #define itype_immediate(x) (x & 0xffff)
1095 #define jtype_op(x) (x >> 26)
1096 #define jtype_target(x) (x & 0x03ffffff)
1098 #define rtype_op(x) (x >> 26)
1099 #define rtype_rs(x) ((x >> 21) & 0x1f)
1100 #define rtype_rt(x) ((x >> 16) & 0x1f)
1101 #define rtype_rd(x) ((x >> 11) & 0x1f)
1102 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1103 #define rtype_funct(x) (x & 0x3f)
1106 mips32_relative_offset (ULONGEST inst
)
1108 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1111 /* Determine where to set a single step breakpoint while considering
1112 branch prediction. */
1114 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1116 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1119 inst
= mips_fetch_instruction (gdbarch
, pc
);
1120 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1123 if (itype_op (inst
) >> 2 == 5)
1124 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1126 op
= (itype_op (inst
) & 0x03);
1136 goto greater_branch
;
1141 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1142 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1144 int tf
= itype_rt (inst
) & 0x01;
1145 int cnum
= itype_rt (inst
) >> 2;
1147 get_frame_register_signed (frame
,
1148 mips_regnum (get_frame_arch (frame
))->
1150 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1152 if (((cond
>> cnum
) & 0x01) == tf
)
1153 pc
+= mips32_relative_offset (inst
) + 4;
1158 pc
+= 4; /* Not a branch, next instruction is easy. */
1161 { /* This gets way messy. */
1163 /* Further subdivide into SPECIAL, REGIMM and other. */
1164 switch (op
= itype_op (inst
) & 0x07) /* Extract bits 28,27,26. */
1166 case 0: /* SPECIAL */
1167 op
= rtype_funct (inst
);
1172 /* Set PC to that address. */
1173 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1175 case 12: /* SYSCALL */
1177 struct gdbarch_tdep
*tdep
;
1179 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1180 if (tdep
->syscall_next_pc
!= NULL
)
1181 pc
= tdep
->syscall_next_pc (frame
);
1190 break; /* end SPECIAL */
1191 case 1: /* REGIMM */
1193 op
= itype_rt (inst
); /* branch condition */
1198 case 16: /* BLTZAL */
1199 case 18: /* BLTZALL */
1201 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1202 pc
+= mips32_relative_offset (inst
) + 4;
1204 pc
+= 8; /* after the delay slot */
1208 case 17: /* BGEZAL */
1209 case 19: /* BGEZALL */
1210 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1211 pc
+= mips32_relative_offset (inst
) + 4;
1213 pc
+= 8; /* after the delay slot */
1215 /* All of the other instructions in the REGIMM category */
1220 break; /* end REGIMM */
1225 reg
= jtype_target (inst
) << 2;
1226 /* Upper four bits get never changed... */
1227 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1230 /* FIXME case JALX : */
1233 reg
= jtype_target (inst
) << 2;
1234 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1235 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1237 break; /* The new PC will be alternate mode */
1238 case 4: /* BEQ, BEQL */
1240 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1241 get_frame_register_signed (frame
, itype_rt (inst
)))
1242 pc
+= mips32_relative_offset (inst
) + 4;
1246 case 5: /* BNE, BNEL */
1248 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1249 get_frame_register_signed (frame
, itype_rt (inst
)))
1250 pc
+= mips32_relative_offset (inst
) + 4;
1254 case 6: /* BLEZ, BLEZL */
1255 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1256 pc
+= mips32_relative_offset (inst
) + 4;
1262 greater_branch
: /* BGTZ, BGTZL */
1263 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1264 pc
+= mips32_relative_offset (inst
) + 4;
1271 } /* mips32_next_pc */
1273 /* Decoding the next place to set a breakpoint is irregular for the
1274 mips 16 variant, but fortunately, there fewer instructions. We have
1275 to cope ith extensions for 16 bit instructions and a pair of actual
1276 32 bit instructions. We dont want to set a single step instruction
1277 on the extend instruction either. */
1279 /* Lots of mips16 instruction formats */
1280 /* Predicting jumps requires itype,ritype,i8type
1281 and their extensions extItype,extritype,extI8type. */
1282 enum mips16_inst_fmts
1284 itype
, /* 0 immediate 5,10 */
1285 ritype
, /* 1 5,3,8 */
1286 rrtype
, /* 2 5,3,3,5 */
1287 rritype
, /* 3 5,3,3,5 */
1288 rrrtype
, /* 4 5,3,3,3,2 */
1289 rriatype
, /* 5 5,3,3,1,4 */
1290 shifttype
, /* 6 5,3,3,3,2 */
1291 i8type
, /* 7 5,3,8 */
1292 i8movtype
, /* 8 5,3,3,5 */
1293 i8mov32rtype
, /* 9 5,3,5,3 */
1294 i64type
, /* 10 5,3,8 */
1295 ri64type
, /* 11 5,3,3,5 */
1296 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1297 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1298 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1299 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1300 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1301 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1302 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1303 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1304 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1305 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1307 /* I am heaping all the fields of the formats into one structure and
1308 then, only the fields which are involved in instruction extension. */
1312 unsigned int regx
; /* Function in i8 type. */
1317 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1318 for the bits which make up the immediate extension. */
1321 extended_offset (unsigned int extension
)
1324 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1326 value
|= (extension
>> 16) & 0x1f; /* extract 10:5 */
1328 value
|= extension
& 0x01f; /* extract 4:0 */
1332 /* Only call this function if you know that this is an extendable
1333 instruction. It won't malfunction, but why make excess remote memory
1334 references? If the immediate operands get sign extended or something,
1335 do it after the extension is performed. */
1336 /* FIXME: Every one of these cases needs to worry about sign extension
1337 when the offset is to be used in relative addressing. */
1340 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1342 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1344 pc
&= 0xfffffffe; /* Clear the low order bit. */
1345 target_read_memory (pc
, buf
, 2);
1346 return extract_unsigned_integer (buf
, 2, byte_order
);
1350 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1351 unsigned int extension
,
1353 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1358 switch (insn_format
)
1365 value
= extended_offset (extension
);
1366 value
= value
<< 11; /* rom for the original value */
1367 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1371 value
= inst
& 0x7ff;
1372 /* FIXME : Consider sign extension. */
1381 { /* A register identifier and an offset. */
1382 /* Most of the fields are the same as I type but the
1383 immediate value is of a different length. */
1387 value
= extended_offset (extension
);
1388 value
= value
<< 8; /* from the original instruction */
1389 value
|= inst
& 0xff; /* eleven bits from instruction */
1390 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1391 if (value
& 0x4000) /* Test the sign bit, bit 26. */
1393 value
&= ~0x3fff; /* Remove the sign bit. */
1399 value
= inst
& 0xff; /* 8 bits */
1400 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1401 /* FIXME: Do sign extension, this format needs it. */
1402 if (value
& 0x80) /* THIS CONFUSES ME. */
1404 value
&= 0xef; /* Remove the sign bit. */
1414 unsigned long value
;
1415 unsigned int nexthalf
;
1416 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1417 value
= value
<< 16;
1418 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit
1427 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1429 upk
->offset
= offset
;
1436 add_offset_16 (CORE_ADDR pc
, int offset
)
1438 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1442 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1443 unsigned int extension
, unsigned int insn
)
1445 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1446 int op
= (insn
>> 11);
1449 case 2: /* Branch */
1452 struct upk_mips16 upk
;
1453 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1454 offset
= upk
.offset
;
1460 pc
+= (offset
<< 1) + 2;
1463 case 3: /* JAL , JALX - Watch out, these are 32 bit
1466 struct upk_mips16 upk
;
1467 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1468 pc
= add_offset_16 (pc
, upk
.offset
);
1469 if ((insn
>> 10) & 0x01) /* Exchange mode */
1470 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
1477 struct upk_mips16 upk
;
1479 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1480 reg
= get_frame_register_signed (frame
, upk
.regx
);
1482 pc
+= (upk
.offset
<< 1) + 2;
1489 struct upk_mips16 upk
;
1491 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1492 reg
= get_frame_register_signed (frame
, upk
.regx
);
1494 pc
+= (upk
.offset
<< 1) + 2;
1499 case 12: /* I8 Formats btez btnez */
1501 struct upk_mips16 upk
;
1503 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1504 /* upk.regx contains the opcode */
1505 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1506 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1507 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1508 /* pc = add_offset_16(pc,upk.offset) ; */
1509 pc
+= (upk
.offset
<< 1) + 2;
1514 case 29: /* RR Formats JR, JALR, JALR-RA */
1516 struct upk_mips16 upk
;
1517 /* upk.fmt = rrtype; */
1522 upk
.regx
= (insn
>> 8) & 0x07;
1523 upk
.regy
= (insn
>> 5) & 0x07;
1531 break; /* Function return instruction. */
1537 break; /* BOGUS Guess */
1539 pc
= get_frame_register_signed (frame
, reg
);
1546 /* This is an instruction extension. Fetch the real instruction
1547 (which follows the extension) and decode things based on
1551 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1552 fetch_mips_16 (gdbarch
, pc
));
1565 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1567 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1568 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1569 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1572 /* The mips_next_pc function supports single_step when the remote
1573 target monitor or stub is not developed enough to do a single_step.
1574 It works by decoding the current instruction and predicting where a
1575 branch will go. This isnt hard because all the data is available.
1576 The MIPS32 and MIPS16 variants are quite different. */
1578 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1580 if (is_mips16_addr (pc
))
1581 return mips16_next_pc (frame
, pc
);
1583 return mips32_next_pc (frame
, pc
);
1586 struct mips_frame_cache
1589 struct trad_frame_saved_reg
*saved_regs
;
1592 /* Set a register's saved stack address in temp_saved_regs. If an
1593 address has already been set for this register, do nothing; this
1594 way we will only recognize the first save of a given register in a
1597 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1598 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1599 Strictly speaking, only the second range is used as it is only second
1600 range (the ABI instead of ISA registers) that comes into play when finding
1601 saved registers in a frame. */
1604 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1605 int regnum
, CORE_ADDR offset
)
1607 if (this_cache
!= NULL
1608 && this_cache
->saved_regs
[regnum
].addr
== -1)
1610 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1612 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1618 /* Fetch the immediate value from a MIPS16 instruction.
1619 If the previous instruction was an EXTEND, use it to extend
1620 the upper bits of the immediate value. This is a helper function
1621 for mips16_scan_prologue. */
1624 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1625 unsigned short inst
, /* current instruction */
1626 int nbits
, /* number of bits in imm field */
1627 int scale
, /* scale factor to be applied to imm */
1628 int is_signed
) /* is the imm field signed? */
1632 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1634 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1635 if (offset
& 0x8000) /* check for negative extend */
1636 offset
= 0 - (0x10000 - (offset
& 0xffff));
1637 return offset
| (inst
& 0x1f);
1641 int max_imm
= 1 << nbits
;
1642 int mask
= max_imm
- 1;
1643 int sign_bit
= max_imm
>> 1;
1645 offset
= inst
& mask
;
1646 if (is_signed
&& (offset
& sign_bit
))
1647 offset
= 0 - (max_imm
- offset
);
1648 return offset
* scale
;
1653 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1654 the associated FRAME_CACHE if not null.
1655 Return the address of the first instruction past the prologue. */
1658 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1659 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1660 struct frame_info
*this_frame
,
1661 struct mips_frame_cache
*this_cache
)
1664 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
1666 long frame_offset
= 0; /* Size of stack frame. */
1667 long frame_adjust
= 0; /* Offset of FP from SP. */
1668 int frame_reg
= MIPS_SP_REGNUM
;
1669 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
1670 unsigned inst
= 0; /* current instruction */
1671 unsigned entry_inst
= 0; /* the entry instruction */
1672 unsigned save_inst
= 0; /* the save instruction */
1675 int extend_bytes
= 0;
1676 int prev_extend_bytes
;
1677 CORE_ADDR end_prologue_addr
= 0;
1679 /* Can be called when there's no process, and hence when there's no
1681 if (this_frame
!= NULL
)
1682 sp
= get_frame_register_signed (this_frame
,
1683 gdbarch_num_regs (gdbarch
)
1688 if (limit_pc
> start_pc
+ 200)
1689 limit_pc
= start_pc
+ 200;
1691 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1693 /* Save the previous instruction. If it's an EXTEND, we'll extract
1694 the immediate offset extension from it in mips16_get_imm. */
1697 /* Fetch and decode the instruction. */
1698 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1700 /* Normally we ignore extend instructions. However, if it is
1701 not followed by a valid prologue instruction, then this
1702 instruction is not part of the prologue either. We must
1703 remember in this case to adjust the end_prologue_addr back
1705 if ((inst
& 0xf800) == 0xf000) /* extend */
1707 extend_bytes
= MIPS_INSN16_SIZE
;
1711 prev_extend_bytes
= extend_bytes
;
1714 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1715 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1717 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1718 if (offset
< 0) /* Negative stack adjustment? */
1719 frame_offset
-= offset
;
1721 /* Exit loop if a positive stack adjustment is found, which
1722 usually means that the stack cleanup code in the function
1723 epilogue is reached. */
1726 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1728 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1729 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1730 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1732 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1734 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1735 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1736 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1738 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1740 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1741 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1743 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1745 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1746 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1748 else if (inst
== 0x673d) /* move $s1, $sp */
1753 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1755 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1756 frame_addr
= sp
+ offset
;
1758 frame_adjust
= offset
;
1760 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1762 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1763 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1764 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1766 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1768 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1769 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1770 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1772 else if ((inst
& 0xf81f) == 0xe809
1773 && (inst
& 0x700) != 0x700) /* entry */
1774 entry_inst
= inst
; /* Save for later processing. */
1775 else if ((inst
& 0xff80) == 0x6480) /* save */
1777 save_inst
= inst
; /* Save for later processing. */
1778 if (prev_extend_bytes
) /* extend */
1779 save_inst
|= prev_inst
<< 16;
1781 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1782 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1783 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1785 /* This instruction is part of the prologue, but we don't
1786 need to do anything special to handle it. */
1790 /* This instruction is not an instruction typically found
1791 in a prologue, so we must have reached the end of the
1793 if (end_prologue_addr
== 0)
1794 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1798 /* The entry instruction is typically the first instruction in a function,
1799 and it stores registers at offsets relative to the value of the old SP
1800 (before the prologue). But the value of the sp parameter to this
1801 function is the new SP (after the prologue has been executed). So we
1802 can't calculate those offsets until we've seen the entire prologue,
1803 and can calculate what the old SP must have been. */
1804 if (entry_inst
!= 0)
1806 int areg_count
= (entry_inst
>> 8) & 7;
1807 int sreg_count
= (entry_inst
>> 6) & 3;
1809 /* The entry instruction always subtracts 32 from the SP. */
1812 /* Now we can calculate what the SP must have been at the
1813 start of the function prologue. */
1816 /* Check if a0-a3 were saved in the caller's argument save area. */
1817 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1819 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1820 offset
+= mips_abi_regsize (gdbarch
);
1823 /* Check if the ra register was pushed on the stack. */
1825 if (entry_inst
& 0x20)
1827 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1828 offset
-= mips_abi_regsize (gdbarch
);
1831 /* Check if the s0 and s1 registers were pushed on the stack. */
1832 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1834 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1835 offset
-= mips_abi_regsize (gdbarch
);
1839 /* The SAVE instruction is similar to ENTRY, except that defined by the
1840 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1841 size of the frame is specified as an immediate field of instruction
1842 and an extended variation exists which lets additional registers and
1843 frame space to be specified. The instruction always treats registers
1844 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1845 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1847 static int args_table
[16] = {
1848 0, 0, 0, 0, 1, 1, 1, 1,
1849 2, 2, 2, 0, 3, 3, 4, -1,
1851 static int astatic_table
[16] = {
1852 0, 1, 2, 3, 0, 1, 2, 3,
1853 0, 1, 2, 4, 0, 1, 0, -1,
1855 int aregs
= (save_inst
>> 16) & 0xf;
1856 int xsregs
= (save_inst
>> 24) & 0x7;
1857 int args
= args_table
[aregs
];
1858 int astatic
= astatic_table
[aregs
];
1863 warning (_("Invalid number of argument registers encoded in SAVE."));
1868 warning (_("Invalid number of static registers encoded in SAVE."));
1872 /* For standard SAVE the frame size of 0 means 128. */
1873 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1874 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1877 frame_offset
+= frame_size
;
1879 /* Now we can calculate what the SP must have been at the
1880 start of the function prologue. */
1883 /* Check if A0-A3 were saved in the caller's argument save area. */
1884 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1886 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1887 offset
+= mips_abi_regsize (gdbarch
);
1892 /* Check if the RA register was pushed on the stack. */
1893 if (save_inst
& 0x40)
1895 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1896 offset
-= mips_abi_regsize (gdbarch
);
1899 /* Check if the S8 register was pushed on the stack. */
1902 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1903 offset
-= mips_abi_regsize (gdbarch
);
1906 /* Check if S2-S7 were pushed on the stack. */
1907 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1909 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1910 offset
-= mips_abi_regsize (gdbarch
);
1913 /* Check if the S1 register was pushed on the stack. */
1914 if (save_inst
& 0x10)
1916 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1917 offset
-= mips_abi_regsize (gdbarch
);
1919 /* Check if the S0 register was pushed on the stack. */
1920 if (save_inst
& 0x20)
1922 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1923 offset
-= mips_abi_regsize (gdbarch
);
1926 /* Check if A0-A3 were pushed on the stack. */
1927 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1929 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1930 offset
-= mips_abi_regsize (gdbarch
);
1934 if (this_cache
!= NULL
)
1937 (get_frame_register_signed (this_frame
,
1938 gdbarch_num_regs (gdbarch
) + frame_reg
)
1939 + frame_offset
- frame_adjust
);
1940 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1941 be able to get rid of the assignment below, evetually. But it's
1942 still needed for now. */
1943 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1944 + mips_regnum (gdbarch
)->pc
]
1945 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1948 /* If we didn't reach the end of the prologue when scanning the function
1949 instructions, then set end_prologue_addr to the address of the
1950 instruction immediately after the last one we scanned. */
1951 if (end_prologue_addr
== 0)
1952 end_prologue_addr
= cur_pc
;
1954 return end_prologue_addr
;
1957 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1958 Procedures that use the 32-bit instruction set are handled by the
1959 mips_insn32 unwinder. */
1961 static struct mips_frame_cache
*
1962 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1964 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1965 struct mips_frame_cache
*cache
;
1967 if ((*this_cache
) != NULL
)
1968 return (*this_cache
);
1969 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1970 (*this_cache
) = cache
;
1971 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1973 /* Analyze the function prologue. */
1975 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1976 CORE_ADDR start_addr
;
1978 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1979 if (start_addr
== 0)
1980 start_addr
= heuristic_proc_start (gdbarch
, pc
);
1981 /* We can't analyze the prologue if we couldn't find the begining
1983 if (start_addr
== 0)
1986 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
1989 /* gdbarch_sp_regnum contains the value and not the address. */
1990 trad_frame_set_value (cache
->saved_regs
,
1991 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
1994 return (*this_cache
);
1998 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1999 struct frame_id
*this_id
)
2001 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2003 /* This marks the outermost frame. */
2004 if (info
->base
== 0)
2006 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2009 static struct value
*
2010 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2011 void **this_cache
, int regnum
)
2013 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2015 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2019 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2020 struct frame_info
*this_frame
, void **this_cache
)
2022 CORE_ADDR pc
= get_frame_pc (this_frame
);
2023 if (mips_pc_is_mips16 (pc
))
2028 static const struct frame_unwind mips_insn16_frame_unwind
=
2031 mips_insn16_frame_this_id
,
2032 mips_insn16_frame_prev_register
,
2034 mips_insn16_frame_sniffer
2038 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2041 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2046 static const struct frame_base mips_insn16_frame_base
=
2048 &mips_insn16_frame_unwind
,
2049 mips_insn16_frame_base_address
,
2050 mips_insn16_frame_base_address
,
2051 mips_insn16_frame_base_address
2054 static const struct frame_base
*
2055 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2057 CORE_ADDR pc
= get_frame_pc (this_frame
);
2058 if (mips_pc_is_mips16 (pc
))
2059 return &mips_insn16_frame_base
;
2064 /* Mark all the registers as unset in the saved_regs array
2065 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2068 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
2070 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2074 const int num_regs
= gdbarch_num_regs (gdbarch
);
2077 for (i
= 0; i
< num_regs
; i
++)
2079 this_cache
->saved_regs
[i
].addr
= -1;
2084 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2085 the associated FRAME_CACHE if not null.
2086 Return the address of the first instruction past the prologue. */
2089 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2090 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2091 struct frame_info
*this_frame
,
2092 struct mips_frame_cache
*this_cache
)
2095 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
2099 int frame_reg
= MIPS_SP_REGNUM
;
2101 CORE_ADDR end_prologue_addr
= 0;
2102 int seen_sp_adjust
= 0;
2103 int load_immediate_bytes
= 0;
2104 int in_delay_slot
= 0;
2105 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2107 /* Can be called when there's no process, and hence when there's no
2109 if (this_frame
!= NULL
)
2110 sp
= get_frame_register_signed (this_frame
,
2111 gdbarch_num_regs (gdbarch
)
2116 if (limit_pc
> start_pc
+ 200)
2117 limit_pc
= start_pc
+ 200;
2122 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2124 unsigned long inst
, high_word
, low_word
;
2127 /* Fetch the instruction. */
2128 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2130 /* Save some code by pre-extracting some useful fields. */
2131 high_word
= (inst
>> 16) & 0xffff;
2132 low_word
= inst
& 0xffff;
2133 reg
= high_word
& 0x1f;
2135 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2136 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2137 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2139 if (low_word
& 0x8000) /* Negative stack adjustment? */
2140 frame_offset
+= 0x10000 - low_word
;
2142 /* Exit loop if a positive stack adjustment is found, which
2143 usually means that the stack cleanup code in the function
2144 epilogue is reached. */
2148 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2149 && !regsize_is_64_bits
)
2151 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2153 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2154 && regsize_is_64_bits
)
2156 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2157 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2159 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2161 /* Old gcc frame, r30 is virtual frame pointer. */
2162 if ((long) low_word
!= frame_offset
)
2163 frame_addr
= sp
+ low_word
;
2164 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2166 unsigned alloca_adjust
;
2169 frame_addr
= get_frame_register_signed
2170 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2172 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2173 if (alloca_adjust
> 0)
2175 /* FP > SP + frame_size. This may be because of
2176 an alloca or somethings similar. Fix sp to
2177 "pre-alloca" value, and try again. */
2178 sp
+= alloca_adjust
;
2179 /* Need to reset the status of all registers. Otherwise,
2180 we will hit a guard that prevents the new address
2181 for each register to be recomputed during the second
2183 reset_saved_regs (gdbarch
, this_cache
);
2188 /* move $30,$sp. With different versions of gas this will be either
2189 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2190 Accept any one of these. */
2191 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2193 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2194 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2196 unsigned alloca_adjust
;
2199 frame_addr
= get_frame_register_signed
2200 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2202 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2203 if (alloca_adjust
> 0)
2205 /* FP > SP + frame_size. This may be because of
2206 an alloca or somethings similar. Fix sp to
2207 "pre-alloca" value, and try again. */
2209 /* Need to reset the status of all registers. Otherwise,
2210 we will hit a guard that prevents the new address
2211 for each register to be recomputed during the second
2213 reset_saved_regs (gdbarch
, this_cache
);
2218 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2219 && !regsize_is_64_bits
)
2221 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2223 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2224 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2225 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2226 || high_word
== 0x3c1c /* lui $gp,n */
2227 || high_word
== 0x279c /* addiu $gp,$gp,n */
2228 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2229 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2232 /* These instructions are part of the prologue, but we don't
2233 need to do anything special to handle them. */
2235 /* The instructions below load $at or $t0 with an immediate
2236 value in preparation for a stack adjustment via
2237 subu $sp,$sp,[$at,$t0]. These instructions could also
2238 initialize a local variable, so we accept them only before
2239 a stack adjustment instruction was seen. */
2240 else if (!seen_sp_adjust
2241 && (high_word
== 0x3c01 /* lui $at,n */
2242 || high_word
== 0x3c08 /* lui $t0,n */
2243 || high_word
== 0x3421 /* ori $at,$at,n */
2244 || high_word
== 0x3508 /* ori $t0,$t0,n */
2245 || high_word
== 0x3401 /* ori $at,$zero,n */
2246 || high_word
== 0x3408 /* ori $t0,$zero,n */
2249 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2253 /* This instruction is not an instruction typically found
2254 in a prologue, so we must have reached the end of the
2256 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2257 loop now? Why would we need to continue scanning the function
2259 if (end_prologue_addr
== 0)
2260 end_prologue_addr
= cur_pc
;
2262 /* Check for branches and jumps. For now, only jump to
2263 register are caught (i.e. returns). */
2264 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2268 /* If the previous instruction was a jump, we must have reached
2269 the end of the prologue by now. Stop scanning so that we do
2270 not go past the function return. */
2275 if (this_cache
!= NULL
)
2278 (get_frame_register_signed (this_frame
,
2279 gdbarch_num_regs (gdbarch
) + frame_reg
)
2281 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2282 this assignment below, eventually. But it's still needed
2284 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2285 + mips_regnum (gdbarch
)->pc
]
2286 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2290 /* If we didn't reach the end of the prologue when scanning the function
2291 instructions, then set end_prologue_addr to the address of the
2292 instruction immediately after the last one we scanned. */
2293 /* brobecker/2004-10-10: I don't think this would ever happen, but
2294 we may as well be careful and do our best if we have a null
2295 end_prologue_addr. */
2296 if (end_prologue_addr
== 0)
2297 end_prologue_addr
= cur_pc
;
2299 /* In a frameless function, we might have incorrectly
2300 skipped some load immediate instructions. Undo the skipping
2301 if the load immediate was not followed by a stack adjustment. */
2302 if (load_immediate_bytes
&& !seen_sp_adjust
)
2303 end_prologue_addr
-= load_immediate_bytes
;
2305 return end_prologue_addr
;
2308 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2309 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2310 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2313 static struct mips_frame_cache
*
2314 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2316 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2317 struct mips_frame_cache
*cache
;
2319 if ((*this_cache
) != NULL
)
2320 return (*this_cache
);
2322 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2323 (*this_cache
) = cache
;
2324 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2326 /* Analyze the function prologue. */
2328 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2329 CORE_ADDR start_addr
;
2331 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2332 if (start_addr
== 0)
2333 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2334 /* We can't analyze the prologue if we couldn't find the begining
2336 if (start_addr
== 0)
2339 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2342 /* gdbarch_sp_regnum contains the value and not the address. */
2343 trad_frame_set_value (cache
->saved_regs
,
2344 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2347 return (*this_cache
);
2351 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2352 struct frame_id
*this_id
)
2354 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2356 /* This marks the outermost frame. */
2357 if (info
->base
== 0)
2359 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2362 static struct value
*
2363 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2364 void **this_cache
, int regnum
)
2366 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2368 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2372 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2373 struct frame_info
*this_frame
, void **this_cache
)
2375 CORE_ADDR pc
= get_frame_pc (this_frame
);
2376 if (! mips_pc_is_mips16 (pc
))
2381 static const struct frame_unwind mips_insn32_frame_unwind
=
2384 mips_insn32_frame_this_id
,
2385 mips_insn32_frame_prev_register
,
2387 mips_insn32_frame_sniffer
2391 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2394 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2399 static const struct frame_base mips_insn32_frame_base
=
2401 &mips_insn32_frame_unwind
,
2402 mips_insn32_frame_base_address
,
2403 mips_insn32_frame_base_address
,
2404 mips_insn32_frame_base_address
2407 static const struct frame_base
*
2408 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2410 CORE_ADDR pc
= get_frame_pc (this_frame
);
2411 if (! mips_pc_is_mips16 (pc
))
2412 return &mips_insn32_frame_base
;
2417 static struct trad_frame_cache
*
2418 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2421 CORE_ADDR start_addr
;
2422 CORE_ADDR stack_addr
;
2423 struct trad_frame_cache
*this_trad_cache
;
2424 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2425 int num_regs
= gdbarch_num_regs (gdbarch
);
2427 if ((*this_cache
) != NULL
)
2428 return (*this_cache
);
2429 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2430 (*this_cache
) = this_trad_cache
;
2432 /* The return address is in the link register. */
2433 trad_frame_set_reg_realreg (this_trad_cache
,
2434 gdbarch_pc_regnum (gdbarch
),
2435 num_regs
+ MIPS_RA_REGNUM
);
2437 /* Frame ID, since it's a frameless / stackless function, no stack
2438 space is allocated and SP on entry is the current SP. */
2439 pc
= get_frame_pc (this_frame
);
2440 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2441 stack_addr
= get_frame_register_signed (this_frame
,
2442 num_regs
+ MIPS_SP_REGNUM
);
2443 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2445 /* Assume that the frame's base is the same as the
2447 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2449 return this_trad_cache
;
2453 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2454 struct frame_id
*this_id
)
2456 struct trad_frame_cache
*this_trad_cache
2457 = mips_stub_frame_cache (this_frame
, this_cache
);
2458 trad_frame_get_id (this_trad_cache
, this_id
);
2461 static struct value
*
2462 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2463 void **this_cache
, int regnum
)
2465 struct trad_frame_cache
*this_trad_cache
2466 = mips_stub_frame_cache (this_frame
, this_cache
);
2467 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2471 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2472 struct frame_info
*this_frame
, void **this_cache
)
2475 struct obj_section
*s
;
2476 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2477 struct minimal_symbol
*msym
;
2479 /* Use the stub unwinder for unreadable code. */
2480 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2483 if (in_plt_section (pc
, NULL
))
2486 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2487 s
= find_pc_section (pc
);
2490 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2491 ".MIPS.stubs") == 0)
2494 /* Calling a PIC function from a non-PIC function passes through a
2495 stub. The stub for foo is named ".pic.foo". */
2496 msym
= lookup_minimal_symbol_by_pc (pc
);
2498 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2499 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2505 static const struct frame_unwind mips_stub_frame_unwind
=
2508 mips_stub_frame_this_id
,
2509 mips_stub_frame_prev_register
,
2511 mips_stub_frame_sniffer
2515 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2518 struct trad_frame_cache
*this_trad_cache
2519 = mips_stub_frame_cache (this_frame
, this_cache
);
2520 return trad_frame_get_this_base (this_trad_cache
);
2523 static const struct frame_base mips_stub_frame_base
=
2525 &mips_stub_frame_unwind
,
2526 mips_stub_frame_base_address
,
2527 mips_stub_frame_base_address
,
2528 mips_stub_frame_base_address
2531 static const struct frame_base
*
2532 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2534 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2535 return &mips_stub_frame_base
;
2540 /* mips_addr_bits_remove - remove useless address bits */
2543 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2545 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2547 if (is_mips16_addr (addr
))
2548 addr
= unmake_mips16_addr (addr
);
2550 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2551 /* This hack is a work-around for existing boards using PMON, the
2552 simulator, and any other 64-bit targets that doesn't have true
2553 64-bit addressing. On these targets, the upper 32 bits of
2554 addresses are ignored by the hardware. Thus, the PC or SP are
2555 likely to have been sign extended to all 1s by instruction
2556 sequences that load 32-bit addresses. For example, a typical
2557 piece of code that loads an address is this:
2559 lui $r2, <upper 16 bits>
2560 ori $r2, <lower 16 bits>
2562 But the lui sign-extends the value such that the upper 32 bits
2563 may be all 1s. The workaround is simply to mask off these
2564 bits. In the future, gcc may be changed to support true 64-bit
2565 addressing, and this masking will have to be disabled. */
2566 return addr
&= 0xffffffffUL
;
2571 /* Instructions used during single-stepping of atomic sequences. */
2572 #define LL_OPCODE 0x30
2573 #define LLD_OPCODE 0x34
2574 #define SC_OPCODE 0x38
2575 #define SCD_OPCODE 0x3c
2577 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2578 instruction and ending with a SC/SCD instruction. If such a sequence
2579 is found, attempt to step through it. A breakpoint is placed at the end of
2583 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2584 struct address_space
*aspace
, CORE_ADDR pc
)
2586 CORE_ADDR breaks
[2] = {-1, -1};
2588 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2592 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2593 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2598 insn
= mips_fetch_instruction (gdbarch
, loc
);
2599 /* Assume all atomic sequences start with a ll/lld instruction. */
2600 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2603 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2605 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2608 loc
+= MIPS_INSN32_SIZE
;
2609 insn
= mips_fetch_instruction (gdbarch
, loc
);
2611 /* Assume that there is at most one branch in the atomic
2612 sequence. If a branch is found, put a breakpoint in its
2613 destination address. */
2614 switch (itype_op (insn
))
2616 case 0: /* SPECIAL */
2617 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2618 return 0; /* fallback to the standard single-step code. */
2620 case 1: /* REGIMM */
2621 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2625 return 0; /* fallback to the standard single-step code. */
2632 case 22: /* BLEZL */
2633 case 23: /* BGTTL */
2639 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2644 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2645 if (last_breakpoint
>= 1)
2646 return 0; /* More than one branch found, fallback to the
2647 standard single-step code. */
2648 breaks
[1] = branch_bp
;
2652 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2656 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2657 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2660 loc
+= MIPS_INSN32_SIZE
;
2662 /* Insert a breakpoint right after the end of the atomic sequence. */
2665 /* Check for duplicated breakpoints. Check also for a breakpoint
2666 placed (branch instruction's destination) in the atomic sequence. */
2667 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2668 last_breakpoint
= 0;
2670 /* Effectively inserts the breakpoints. */
2671 for (index
= 0; index
<= last_breakpoint
; index
++)
2672 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2677 /* mips_software_single_step() is called just before we want to resume
2678 the inferior, if we want to single-step it but there is no hardware
2679 or kernel single-step support (MIPS on GNU/Linux for example). We find
2680 the target of the coming instruction and breakpoint it. */
2683 mips_software_single_step (struct frame_info
*frame
)
2685 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2686 struct address_space
*aspace
= get_frame_address_space (frame
);
2687 CORE_ADDR pc
, next_pc
;
2689 pc
= get_frame_pc (frame
);
2690 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2693 next_pc
= mips_next_pc (frame
, pc
);
2695 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2699 /* Test whether the PC points to the return instruction at the
2700 end of a function. */
2703 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2705 if (mips_pc_is_mips16 (pc
))
2706 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2707 generates a "jr $ra"; other times it generates code to load
2708 the return address from the stack to an accessible register (such
2709 as $a3), then a "jr" using that register. This second case
2710 is almost impossible to distinguish from an indirect jump
2711 used for switch statements, so we don't even try. */
2712 return mips_fetch_instruction (gdbarch
, pc
) == 0xe820; /* jr $ra */
2714 return mips_fetch_instruction (gdbarch
, pc
) == 0x3e00008; /* jr $ra */
2718 /* This fencepost looks highly suspicious to me. Removing it also
2719 seems suspicious as it could affect remote debugging across serial
2723 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2729 struct inferior
*inf
;
2731 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2733 fence
= start_pc
- heuristic_fence_post
;
2737 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2738 fence
= VM_MIN_ADDRESS
;
2740 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2742 inf
= current_inferior ();
2744 /* Search back for previous return. */
2745 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2746 if (start_pc
< fence
)
2748 /* It's not clear to me why we reach this point when
2749 stop_soon, but with this test, at least we
2750 don't print out warnings for every child forked (eg, on
2751 decstation). 22apr93 rich@cygnus.com. */
2752 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2754 static int blurb_printed
= 0;
2756 warning (_("GDB can't find the start of the function at %s."),
2757 paddress (gdbarch
, pc
));
2761 /* This actually happens frequently in embedded
2762 development, when you first connect to a board
2763 and your stack pointer and pc are nowhere in
2764 particular. This message needs to give people
2765 in that situation enough information to
2766 determine that it's no big deal. */
2767 printf_filtered ("\n\
2768 GDB is unable to find the start of the function at %s\n\
2769 and thus can't determine the size of that function's stack frame.\n\
2770 This means that GDB may be unable to access that stack frame, or\n\
2771 the frames below it.\n\
2772 This problem is most likely caused by an invalid program counter or\n\
2774 However, if you think GDB should simply search farther back\n\
2775 from %s for code which looks like the beginning of a\n\
2776 function, you can increase the range of the search using the `set\n\
2777 heuristic-fence-post' command.\n",
2778 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2785 else if (mips_pc_is_mips16 (start_pc
))
2787 unsigned short inst
;
2789 /* On MIPS16, any one of the following is likely to be the
2790 start of a function:
2796 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
2797 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2798 if ((inst
& 0xff80) == 0x6480) /* save */
2800 if (start_pc
- instlen
>= fence
)
2802 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2803 if ((inst
& 0xf800) == 0xf000) /* extend */
2804 start_pc
-= instlen
;
2808 else if (((inst
& 0xf81f) == 0xe809
2809 && (inst
& 0x700) != 0x700) /* entry */
2810 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2811 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2812 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2814 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2815 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2820 else if (mips_about_to_return (gdbarch
, start_pc
))
2822 /* Skip return and its delay slot. */
2823 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2830 struct mips_objfile_private
2836 /* According to the current ABI, should the type be passed in a
2837 floating-point register (assuming that there is space)? When there
2838 is no FPU, FP are not even considered as possible candidates for
2839 FP registers and, consequently this returns false - forces FP
2840 arguments into integer registers. */
2843 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2844 struct type
*arg_type
)
2846 return ((typecode
== TYPE_CODE_FLT
2847 || (MIPS_EABI (gdbarch
)
2848 && (typecode
== TYPE_CODE_STRUCT
2849 || typecode
== TYPE_CODE_UNION
)
2850 && TYPE_NFIELDS (arg_type
) == 1
2851 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2853 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2856 /* On o32, argument passing in GPRs depends on the alignment of the type being
2857 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2860 mips_type_needs_double_align (struct type
*type
)
2862 enum type_code typecode
= TYPE_CODE (type
);
2864 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2866 else if (typecode
== TYPE_CODE_STRUCT
)
2868 if (TYPE_NFIELDS (type
) < 1)
2870 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2872 else if (typecode
== TYPE_CODE_UNION
)
2876 n
= TYPE_NFIELDS (type
);
2877 for (i
= 0; i
< n
; i
++)
2878 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2885 /* Adjust the address downward (direction of stack growth) so that it
2886 is correctly aligned for a new stack frame. */
2888 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2890 return align_down (addr
, 16);
2894 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2895 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2896 int nargs
, struct value
**args
, CORE_ADDR sp
,
2897 int struct_return
, CORE_ADDR struct_addr
)
2903 int stack_offset
= 0;
2904 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2905 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2906 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2907 int regsize
= mips_abi_regsize (gdbarch
);
2909 /* For shared libraries, "t9" needs to point at the function
2911 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2913 /* Set the return address register to point to the entry point of
2914 the program, where a breakpoint lies in wait. */
2915 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2917 /* First ensure that the stack and structure return address (if any)
2918 are properly aligned. The stack has to be at least 64-bit
2919 aligned even on 32-bit machines, because doubles must be 64-bit
2920 aligned. For n32 and n64, stack frames need to be 128-bit
2921 aligned, so we round to this widest known alignment. */
2923 sp
= align_down (sp
, 16);
2924 struct_addr
= align_down (struct_addr
, 16);
2926 /* Now make space on the stack for the args. We allocate more
2927 than necessary for EABI, because the first few arguments are
2928 passed in registers, but that's OK. */
2929 for (argnum
= 0; argnum
< nargs
; argnum
++)
2930 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2931 sp
-= align_up (len
, 16);
2934 fprintf_unfiltered (gdb_stdlog
,
2935 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2936 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2938 /* Initialize the integer and float register pointers. */
2939 argreg
= MIPS_A0_REGNUM
;
2940 float_argreg
= mips_fpa0_regnum (gdbarch
);
2942 /* The struct_return pointer occupies the first parameter-passing reg. */
2946 fprintf_unfiltered (gdb_stdlog
,
2947 "mips_eabi_push_dummy_call: "
2948 "struct_return reg=%d %s\n",
2949 argreg
, paddress (gdbarch
, struct_addr
));
2950 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2953 /* Now load as many as possible of the first arguments into
2954 registers, and push the rest onto the stack. Loop thru args
2955 from first to last. */
2956 for (argnum
= 0; argnum
< nargs
; argnum
++)
2958 const gdb_byte
*val
;
2959 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2960 struct value
*arg
= args
[argnum
];
2961 struct type
*arg_type
= check_typedef (value_type (arg
));
2962 int len
= TYPE_LENGTH (arg_type
);
2963 enum type_code typecode
= TYPE_CODE (arg_type
);
2966 fprintf_unfiltered (gdb_stdlog
,
2967 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2968 argnum
+ 1, len
, (int) typecode
);
2970 /* Function pointer arguments to mips16 code need to be made into
2972 if (typecode
== TYPE_CODE_PTR
2973 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
2975 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
2977 if (mips_pc_is_mips16 (addr
))
2979 store_signed_integer (valbuf
, len
, byte_order
,
2980 make_mips16_addr (addr
));
2984 val
= value_contents (arg
);
2986 /* The EABI passes structures that do not fit in a register by
2988 else if (len
> regsize
2989 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2991 store_unsigned_integer (valbuf
, regsize
, byte_order
,
2992 value_address (arg
));
2993 typecode
= TYPE_CODE_PTR
;
2997 fprintf_unfiltered (gdb_stdlog
, " push");
3000 val
= value_contents (arg
);
3002 /* 32-bit ABIs always start floating point arguments in an
3003 even-numbered floating point register. Round the FP register
3004 up before the check to see if there are any FP registers
3005 left. Non MIPS_EABI targets also pass the FP in the integer
3006 registers so also round up normal registers. */
3007 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3009 if ((float_argreg
& 1))
3013 /* Floating point arguments passed in registers have to be
3014 treated specially. On 32-bit architectures, doubles
3015 are passed in register pairs; the even register gets
3016 the low word, and the odd register gets the high word.
3017 On non-EABI processors, the first two floating point arguments are
3018 also copied to general registers, because MIPS16 functions
3019 don't use float registers for arguments. This duplication of
3020 arguments in general registers can't hurt non-MIPS16 functions
3021 because those registers are normally skipped. */
3022 /* MIPS_EABI squeezes a struct that contains a single floating
3023 point value into an FP register instead of pushing it onto the
3025 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3026 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3028 /* EABI32 will pass doubles in consecutive registers, even on
3029 64-bit cores. At one time, we used to check the size of
3030 `float_argreg' to determine whether or not to pass doubles
3031 in consecutive registers, but this is not sufficient for
3032 making the ABI determination. */
3033 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
3035 int low_offset
= gdbarch_byte_order (gdbarch
)
3036 == BFD_ENDIAN_BIG
? 4 : 0;
3039 /* Write the low word of the double to the even register(s). */
3040 regval
= extract_signed_integer (val
+ low_offset
,
3043 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3044 float_argreg
, phex (regval
, 4));
3045 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3047 /* Write the high word of the double to the odd register(s). */
3048 regval
= extract_signed_integer (val
+ 4 - low_offset
,
3051 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3052 float_argreg
, phex (regval
, 4));
3053 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3057 /* This is a floating point value that fits entirely
3058 in a single register. */
3059 /* On 32 bit ABI's the float_argreg is further adjusted
3060 above to ensure that it is even register aligned. */
3061 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
3063 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3064 float_argreg
, phex (regval
, len
));
3065 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3070 /* Copy the argument to general registers or the stack in
3071 register-sized pieces. Large arguments are split between
3072 registers and stack. */
3073 /* Note: structs whose size is not a multiple of regsize
3074 are treated specially: Irix cc passes
3075 them in registers where gcc sometimes puts them on the
3076 stack. For maximum compatibility, we will put them in
3078 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3080 /* Note: Floating-point values that didn't fit into an FP
3081 register are only written to memory. */
3084 /* Remember if the argument was written to the stack. */
3085 int stack_used_p
= 0;
3086 int partial_len
= (len
< regsize
? len
: regsize
);
3089 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3092 /* Write this portion of the argument to the stack. */
3093 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3095 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3097 /* Should shorter than int integer values be
3098 promoted to int before being stored? */
3099 int longword_offset
= 0;
3102 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3105 && (typecode
== TYPE_CODE_INT
3106 || typecode
== TYPE_CODE_PTR
3107 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3108 longword_offset
= regsize
- len
;
3109 else if ((typecode
== TYPE_CODE_STRUCT
3110 || typecode
== TYPE_CODE_UNION
)
3111 && TYPE_LENGTH (arg_type
) < regsize
)
3112 longword_offset
= regsize
- len
;
3117 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3118 paddress (gdbarch
, stack_offset
));
3119 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3120 paddress (gdbarch
, longword_offset
));
3123 addr
= sp
+ stack_offset
+ longword_offset
;
3128 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3129 paddress (gdbarch
, addr
));
3130 for (i
= 0; i
< partial_len
; i
++)
3132 fprintf_unfiltered (gdb_stdlog
, "%02x",
3136 write_memory (addr
, val
, partial_len
);
3139 /* Note!!! This is NOT an else clause. Odd sized
3140 structs may go thru BOTH paths. Floating point
3141 arguments will not. */
3142 /* Write this portion of the argument to a general
3143 purpose register. */
3144 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3145 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3148 extract_signed_integer (val
, partial_len
, byte_order
);
3151 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3153 phex (regval
, regsize
));
3154 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3161 /* Compute the offset into the stack at which we will
3162 copy the next parameter.
3164 In the new EABI (and the NABI32), the stack_offset
3165 only needs to be adjusted when it has been used. */
3168 stack_offset
+= align_up (partial_len
, regsize
);
3172 fprintf_unfiltered (gdb_stdlog
, "\n");
3175 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3177 /* Return adjusted stack pointer. */
3181 /* Determine the return value convention being used. */
3183 static enum return_value_convention
3184 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3185 struct type
*type
, struct regcache
*regcache
,
3186 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3188 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3189 int fp_return_type
= 0;
3190 int offset
, regnum
, xfer
;
3192 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3193 return RETURN_VALUE_STRUCT_CONVENTION
;
3195 /* Floating point type? */
3196 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3198 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3200 /* Structs with a single field of float type
3201 are returned in a floating point register. */
3202 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3203 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3204 && TYPE_NFIELDS (type
) == 1)
3206 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3208 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3215 /* A floating-point value belongs in the least significant part
3218 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3219 regnum
= mips_regnum (gdbarch
)->fp0
;
3223 /* An integer value goes in V0/V1. */
3225 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3226 regnum
= MIPS_V0_REGNUM
;
3229 offset
< TYPE_LENGTH (type
);
3230 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3232 xfer
= mips_abi_regsize (gdbarch
);
3233 if (offset
+ xfer
> TYPE_LENGTH (type
))
3234 xfer
= TYPE_LENGTH (type
) - offset
;
3235 mips_xfer_register (gdbarch
, regcache
,
3236 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3237 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3241 return RETURN_VALUE_REGISTER_CONVENTION
;
3245 /* N32/N64 ABI stuff. */
3247 /* Search for a naturally aligned double at OFFSET inside a struct
3248 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3252 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3257 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3260 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3263 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3266 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3269 struct type
*field_type
;
3271 /* We're only looking at normal fields. */
3272 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3273 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3276 /* If we have gone past the offset, there is no double to pass. */
3277 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3281 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3283 /* If this field is entirely before the requested offset, go
3284 on to the next one. */
3285 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3288 /* If this is our special aligned double, we can stop. */
3289 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3290 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3293 /* This field starts at or before the requested offset, and
3294 overlaps it. If it is a structure, recurse inwards. */
3295 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3302 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3303 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3304 int nargs
, struct value
**args
, CORE_ADDR sp
,
3305 int struct_return
, CORE_ADDR struct_addr
)
3311 int stack_offset
= 0;
3312 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3313 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3314 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3316 /* For shared libraries, "t9" needs to point at the function
3318 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3320 /* Set the return address register to point to the entry point of
3321 the program, where a breakpoint lies in wait. */
3322 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3324 /* First ensure that the stack and structure return address (if any)
3325 are properly aligned. The stack has to be at least 64-bit
3326 aligned even on 32-bit machines, because doubles must be 64-bit
3327 aligned. For n32 and n64, stack frames need to be 128-bit
3328 aligned, so we round to this widest known alignment. */
3330 sp
= align_down (sp
, 16);
3331 struct_addr
= align_down (struct_addr
, 16);
3333 /* Now make space on the stack for the args. */
3334 for (argnum
= 0; argnum
< nargs
; argnum
++)
3335 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3336 sp
-= align_up (len
, 16);
3339 fprintf_unfiltered (gdb_stdlog
,
3340 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3341 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3343 /* Initialize the integer and float register pointers. */
3344 argreg
= MIPS_A0_REGNUM
;
3345 float_argreg
= mips_fpa0_regnum (gdbarch
);
3347 /* The struct_return pointer occupies the first parameter-passing reg. */
3351 fprintf_unfiltered (gdb_stdlog
,
3352 "mips_n32n64_push_dummy_call: "
3353 "struct_return reg=%d %s\n",
3354 argreg
, paddress (gdbarch
, struct_addr
));
3355 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3358 /* Now load as many as possible of the first arguments into
3359 registers, and push the rest onto the stack. Loop thru args
3360 from first to last. */
3361 for (argnum
= 0; argnum
< nargs
; argnum
++)
3363 const gdb_byte
*val
;
3364 struct value
*arg
= args
[argnum
];
3365 struct type
*arg_type
= check_typedef (value_type (arg
));
3366 int len
= TYPE_LENGTH (arg_type
);
3367 enum type_code typecode
= TYPE_CODE (arg_type
);
3370 fprintf_unfiltered (gdb_stdlog
,
3371 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3372 argnum
+ 1, len
, (int) typecode
);
3374 val
= value_contents (arg
);
3376 /* A 128-bit long double value requires an even-odd pair of
3377 floating-point registers. */
3379 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3380 && (float_argreg
& 1))
3386 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3387 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3389 /* This is a floating point value that fits entirely
3390 in a single register or a pair of registers. */
3391 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3392 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3394 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3395 float_argreg
, phex (regval
, reglen
));
3396 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3399 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3400 argreg
, phex (regval
, reglen
));
3401 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3406 regval
= extract_unsigned_integer (val
+ reglen
,
3407 reglen
, byte_order
);
3409 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3410 float_argreg
, phex (regval
, reglen
));
3411 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3414 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3415 argreg
, phex (regval
, reglen
));
3416 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3423 /* Copy the argument to general registers or the stack in
3424 register-sized pieces. Large arguments are split between
3425 registers and stack. */
3426 /* For N32/N64, structs, unions, or other composite types are
3427 treated as a sequence of doublewords, and are passed in integer
3428 or floating point registers as though they were simple scalar
3429 parameters to the extent that they fit, with any excess on the
3430 stack packed according to the normal memory layout of the
3432 The caller does not reserve space for the register arguments;
3433 the callee is responsible for reserving it if required. */
3434 /* Note: Floating-point values that didn't fit into an FP
3435 register are only written to memory. */
3438 /* Remember if the argument was written to the stack. */
3439 int stack_used_p
= 0;
3440 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3443 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3446 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3447 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3449 /* Write this portion of the argument to the stack. */
3450 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3452 /* Should shorter than int integer values be
3453 promoted to int before being stored? */
3454 int longword_offset
= 0;
3457 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3459 if ((typecode
== TYPE_CODE_INT
3460 || typecode
== TYPE_CODE_PTR
)
3462 longword_offset
= MIPS64_REGSIZE
- len
;
3467 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3468 paddress (gdbarch
, stack_offset
));
3469 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3470 paddress (gdbarch
, longword_offset
));
3473 addr
= sp
+ stack_offset
+ longword_offset
;
3478 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3479 paddress (gdbarch
, addr
));
3480 for (i
= 0; i
< partial_len
; i
++)
3482 fprintf_unfiltered (gdb_stdlog
, "%02x",
3486 write_memory (addr
, val
, partial_len
);
3489 /* Note!!! This is NOT an else clause. Odd sized
3490 structs may go thru BOTH paths. */
3491 /* Write this portion of the argument to a general
3492 purpose register. */
3493 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3497 /* Sign extend pointers, 32-bit integers and signed
3498 16-bit and 8-bit integers; everything else is taken
3501 if ((partial_len
== 4
3502 && (typecode
== TYPE_CODE_PTR
3503 || typecode
== TYPE_CODE_INT
))
3505 && typecode
== TYPE_CODE_INT
3506 && !TYPE_UNSIGNED (arg_type
)))
3507 regval
= extract_signed_integer (val
, partial_len
,
3510 regval
= extract_unsigned_integer (val
, partial_len
,
3513 /* A non-floating-point argument being passed in a
3514 general register. If a struct or union, and if
3515 the remaining length is smaller than the register
3516 size, we have to adjust the register value on
3519 It does not seem to be necessary to do the
3520 same for integral types. */
3522 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3523 && partial_len
< MIPS64_REGSIZE
3524 && (typecode
== TYPE_CODE_STRUCT
3525 || typecode
== TYPE_CODE_UNION
))
3526 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3530 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3532 phex (regval
, MIPS64_REGSIZE
));
3533 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3535 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3536 TYPE_LENGTH (arg_type
) - len
))
3539 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3541 phex (regval
, MIPS64_REGSIZE
));
3542 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3553 /* Compute the offset into the stack at which we will
3554 copy the next parameter.
3556 In N32 (N64?), the stack_offset only needs to be
3557 adjusted when it has been used. */
3560 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3564 fprintf_unfiltered (gdb_stdlog
, "\n");
3567 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3569 /* Return adjusted stack pointer. */
3573 static enum return_value_convention
3574 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3575 struct type
*type
, struct regcache
*regcache
,
3576 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3578 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3580 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3582 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3583 if needed), as appropriate for the type. Composite results (struct,
3584 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3587 * A struct with only one or two floating point fields is returned in $f0
3588 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3591 * Any other composite results of at most 128 bits are returned in
3592 $2 (first 64 bits) and $3 (remainder, if necessary).
3594 * Larger composite results are handled by converting the function to a
3595 procedure with an implicit first parameter, which is a pointer to an area
3596 reserved by the caller to receive the result. [The o32-bit ABI requires
3597 that all composite results be handled by conversion to implicit first
3598 parameters. The MIPS/SGI Fortran implementation has always made a
3599 specific exception to return COMPLEX results in the floating point
3602 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3603 return RETURN_VALUE_STRUCT_CONVENTION
;
3604 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3605 && TYPE_LENGTH (type
) == 16
3606 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3608 /* A 128-bit floating-point value fills both $f0 and $f2. The
3609 two registers are used in the same as memory order, so the
3610 eight bytes with the lower memory address are in $f0. */
3612 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3613 mips_xfer_register (gdbarch
, regcache
,
3614 gdbarch_num_regs (gdbarch
)
3615 + mips_regnum (gdbarch
)->fp0
,
3616 8, gdbarch_byte_order (gdbarch
),
3617 readbuf
, writebuf
, 0);
3618 mips_xfer_register (gdbarch
, regcache
,
3619 gdbarch_num_regs (gdbarch
)
3620 + mips_regnum (gdbarch
)->fp0
+ 2,
3621 8, gdbarch_byte_order (gdbarch
),
3622 readbuf
? readbuf
+ 8 : readbuf
,
3623 writebuf
? writebuf
+ 8 : writebuf
, 0);
3624 return RETURN_VALUE_REGISTER_CONVENTION
;
3626 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3627 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3629 /* A single or double floating-point value that fits in FP0. */
3631 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3632 mips_xfer_register (gdbarch
, regcache
,
3633 gdbarch_num_regs (gdbarch
)
3634 + mips_regnum (gdbarch
)->fp0
,
3636 gdbarch_byte_order (gdbarch
),
3637 readbuf
, writebuf
, 0);
3638 return RETURN_VALUE_REGISTER_CONVENTION
;
3640 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3641 && TYPE_NFIELDS (type
) <= 2
3642 && TYPE_NFIELDS (type
) >= 1
3643 && ((TYPE_NFIELDS (type
) == 1
3644 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3646 || (TYPE_NFIELDS (type
) == 2
3647 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3649 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3650 == TYPE_CODE_FLT
))))
3652 /* A struct that contains one or two floats. Each value is part
3653 in the least significant part of their floating point
3654 register (or GPR, for soft float). */
3657 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3658 ? mips_regnum (gdbarch
)->fp0
3660 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3662 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3665 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3667 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3669 /* A 16-byte long double field goes in two consecutive
3671 mips_xfer_register (gdbarch
, regcache
,
3672 gdbarch_num_regs (gdbarch
) + regnum
,
3674 gdbarch_byte_order (gdbarch
),
3675 readbuf
, writebuf
, offset
);
3676 mips_xfer_register (gdbarch
, regcache
,
3677 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3679 gdbarch_byte_order (gdbarch
),
3680 readbuf
, writebuf
, offset
+ 8);
3683 mips_xfer_register (gdbarch
, regcache
,
3684 gdbarch_num_regs (gdbarch
) + regnum
,
3685 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3686 gdbarch_byte_order (gdbarch
),
3687 readbuf
, writebuf
, offset
);
3689 return RETURN_VALUE_REGISTER_CONVENTION
;
3691 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3692 || TYPE_CODE (type
) == TYPE_CODE_UNION
3693 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3695 /* A composite type. Extract the left justified value,
3696 regardless of the byte order. I.e. DO NOT USE
3700 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3701 offset
< TYPE_LENGTH (type
);
3702 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3704 int xfer
= register_size (gdbarch
, regnum
);
3705 if (offset
+ xfer
> TYPE_LENGTH (type
))
3706 xfer
= TYPE_LENGTH (type
) - offset
;
3708 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3709 offset
, xfer
, regnum
);
3710 mips_xfer_register (gdbarch
, regcache
,
3711 gdbarch_num_regs (gdbarch
) + regnum
,
3712 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3715 return RETURN_VALUE_REGISTER_CONVENTION
;
3719 /* A scalar extract each part but least-significant-byte
3723 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3724 offset
< TYPE_LENGTH (type
);
3725 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3727 int xfer
= register_size (gdbarch
, regnum
);
3728 if (offset
+ xfer
> TYPE_LENGTH (type
))
3729 xfer
= TYPE_LENGTH (type
) - offset
;
3731 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3732 offset
, xfer
, regnum
);
3733 mips_xfer_register (gdbarch
, regcache
,
3734 gdbarch_num_regs (gdbarch
) + regnum
,
3735 xfer
, gdbarch_byte_order (gdbarch
),
3736 readbuf
, writebuf
, offset
);
3738 return RETURN_VALUE_REGISTER_CONVENTION
;
3742 /* O32 ABI stuff. */
3745 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3746 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3747 int nargs
, struct value
**args
, CORE_ADDR sp
,
3748 int struct_return
, CORE_ADDR struct_addr
)
3754 int stack_offset
= 0;
3755 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3756 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3757 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3759 /* For shared libraries, "t9" needs to point at the function
3761 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3763 /* Set the return address register to point to the entry point of
3764 the program, where a breakpoint lies in wait. */
3765 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3767 /* First ensure that the stack and structure return address (if any)
3768 are properly aligned. The stack has to be at least 64-bit
3769 aligned even on 32-bit machines, because doubles must be 64-bit
3770 aligned. For n32 and n64, stack frames need to be 128-bit
3771 aligned, so we round to this widest known alignment. */
3773 sp
= align_down (sp
, 16);
3774 struct_addr
= align_down (struct_addr
, 16);
3776 /* Now make space on the stack for the args. */
3777 for (argnum
= 0; argnum
< nargs
; argnum
++)
3779 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3780 int arglen
= TYPE_LENGTH (arg_type
);
3782 /* Align to double-word if necessary. */
3783 if (mips_type_needs_double_align (arg_type
))
3784 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3785 /* Allocate space on the stack. */
3786 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3788 sp
-= align_up (len
, 16);
3791 fprintf_unfiltered (gdb_stdlog
,
3792 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3793 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3795 /* Initialize the integer and float register pointers. */
3796 argreg
= MIPS_A0_REGNUM
;
3797 float_argreg
= mips_fpa0_regnum (gdbarch
);
3799 /* The struct_return pointer occupies the first parameter-passing reg. */
3803 fprintf_unfiltered (gdb_stdlog
,
3804 "mips_o32_push_dummy_call: "
3805 "struct_return reg=%d %s\n",
3806 argreg
, paddress (gdbarch
, struct_addr
));
3807 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3808 stack_offset
+= MIPS32_REGSIZE
;
3811 /* Now load as many as possible of the first arguments into
3812 registers, and push the rest onto the stack. Loop thru args
3813 from first to last. */
3814 for (argnum
= 0; argnum
< nargs
; argnum
++)
3816 const gdb_byte
*val
;
3817 struct value
*arg
= args
[argnum
];
3818 struct type
*arg_type
= check_typedef (value_type (arg
));
3819 int len
= TYPE_LENGTH (arg_type
);
3820 enum type_code typecode
= TYPE_CODE (arg_type
);
3823 fprintf_unfiltered (gdb_stdlog
,
3824 "mips_o32_push_dummy_call: %d len=%d type=%d",
3825 argnum
+ 1, len
, (int) typecode
);
3827 val
= value_contents (arg
);
3829 /* 32-bit ABIs always start floating point arguments in an
3830 even-numbered floating point register. Round the FP register
3831 up before the check to see if there are any FP registers
3832 left. O32/O64 targets also pass the FP in the integer
3833 registers so also round up normal registers. */
3834 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3836 if ((float_argreg
& 1))
3840 /* Floating point arguments passed in registers have to be
3841 treated specially. On 32-bit architectures, doubles
3842 are passed in register pairs; the even register gets
3843 the low word, and the odd register gets the high word.
3844 On O32/O64, the first two floating point arguments are
3845 also copied to general registers, because MIPS16 functions
3846 don't use float registers for arguments. This duplication of
3847 arguments in general registers can't hurt non-MIPS16 functions
3848 because those registers are normally skipped. */
3850 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3851 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3853 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3855 int low_offset
= gdbarch_byte_order (gdbarch
)
3856 == BFD_ENDIAN_BIG
? 4 : 0;
3857 unsigned long regval
;
3859 /* Write the low word of the double to the even register(s). */
3860 regval
= extract_unsigned_integer (val
+ low_offset
,
3863 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3864 float_argreg
, phex (regval
, 4));
3865 regcache_cooked_write_unsigned (regcache
,
3866 float_argreg
++, regval
);
3868 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3869 argreg
, phex (regval
, 4));
3870 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3872 /* Write the high word of the double to the odd register(s). */
3873 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3876 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3877 float_argreg
, phex (regval
, 4));
3878 regcache_cooked_write_unsigned (regcache
,
3879 float_argreg
++, regval
);
3882 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3883 argreg
, phex (regval
, 4));
3884 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3888 /* This is a floating point value that fits entirely
3889 in a single register. */
3890 /* On 32 bit ABI's the float_argreg is further adjusted
3891 above to ensure that it is even register aligned. */
3892 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
3894 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3895 float_argreg
, phex (regval
, len
));
3896 regcache_cooked_write_unsigned (regcache
,
3897 float_argreg
++, regval
);
3898 /* Although two FP registers are reserved for each
3899 argument, only one corresponding integer register is
3902 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3903 argreg
, phex (regval
, len
));
3904 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3906 /* Reserve space for the FP register. */
3907 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3911 /* Copy the argument to general registers or the stack in
3912 register-sized pieces. Large arguments are split between
3913 registers and stack. */
3914 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3915 are treated specially: Irix cc passes
3916 them in registers where gcc sometimes puts them on the
3917 stack. For maximum compatibility, we will put them in
3919 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3920 && len
% MIPS32_REGSIZE
!= 0);
3921 /* Structures should be aligned to eight bytes (even arg registers)
3922 on MIPS_ABI_O32, if their first member has double precision. */
3923 if (mips_type_needs_double_align (arg_type
))
3928 stack_offset
+= MIPS32_REGSIZE
;
3933 /* Remember if the argument was written to the stack. */
3934 int stack_used_p
= 0;
3935 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3938 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3941 /* Write this portion of the argument to the stack. */
3942 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3943 || odd_sized_struct
)
3945 /* Should shorter than int integer values be
3946 promoted to int before being stored? */
3947 int longword_offset
= 0;
3953 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3954 paddress (gdbarch
, stack_offset
));
3955 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3956 paddress (gdbarch
, longword_offset
));
3959 addr
= sp
+ stack_offset
+ longword_offset
;
3964 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3965 paddress (gdbarch
, addr
));
3966 for (i
= 0; i
< partial_len
; i
++)
3968 fprintf_unfiltered (gdb_stdlog
, "%02x",
3972 write_memory (addr
, val
, partial_len
);
3975 /* Note!!! This is NOT an else clause. Odd sized
3976 structs may go thru BOTH paths. */
3977 /* Write this portion of the argument to a general
3978 purpose register. */
3979 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3981 LONGEST regval
= extract_signed_integer (val
, partial_len
,
3983 /* Value may need to be sign extended, because
3984 mips_isa_regsize() != mips_abi_regsize(). */
3986 /* A non-floating-point argument being passed in a
3987 general register. If a struct or union, and if
3988 the remaining length is smaller than the register
3989 size, we have to adjust the register value on
3992 It does not seem to be necessary to do the
3993 same for integral types.
3995 Also don't do this adjustment on O64 binaries.
3997 cagney/2001-07-23: gdb/179: Also, GCC, when
3998 outputting LE O32 with sizeof (struct) <
3999 mips_abi_regsize(), generates a left shift
4000 as part of storing the argument in a register
4001 (the left shift isn't generated when
4002 sizeof (struct) >= mips_abi_regsize()). Since
4003 it is quite possible that this is GCC
4004 contradicting the LE/O32 ABI, GDB has not been
4005 adjusted to accommodate this. Either someone
4006 needs to demonstrate that the LE/O32 ABI
4007 specifies such a left shift OR this new ABI gets
4008 identified as such and GDB gets tweaked
4011 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4012 && partial_len
< MIPS32_REGSIZE
4013 && (typecode
== TYPE_CODE_STRUCT
4014 || typecode
== TYPE_CODE_UNION
))
4015 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
4019 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4021 phex (regval
, MIPS32_REGSIZE
));
4022 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4025 /* Prevent subsequent floating point arguments from
4026 being passed in floating point registers. */
4027 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4033 /* Compute the offset into the stack at which we will
4034 copy the next parameter.
4036 In older ABIs, the caller reserved space for
4037 registers that contained arguments. This was loosely
4038 refered to as their "home". Consequently, space is
4039 always allocated. */
4041 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
4045 fprintf_unfiltered (gdb_stdlog
, "\n");
4048 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4050 /* Return adjusted stack pointer. */
4054 static enum return_value_convention
4055 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4056 struct type
*type
, struct regcache
*regcache
,
4057 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4059 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4061 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4062 || TYPE_CODE (type
) == TYPE_CODE_UNION
4063 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4064 return RETURN_VALUE_STRUCT_CONVENTION
;
4065 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4066 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4068 /* A single-precision floating-point value. It fits in the
4069 least significant part of FP0. */
4071 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4072 mips_xfer_register (gdbarch
, regcache
,
4073 gdbarch_num_regs (gdbarch
)
4074 + mips_regnum (gdbarch
)->fp0
,
4076 gdbarch_byte_order (gdbarch
),
4077 readbuf
, writebuf
, 0);
4078 return RETURN_VALUE_REGISTER_CONVENTION
;
4080 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4081 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4083 /* A double-precision floating-point value. The most
4084 significant part goes in FP1, and the least significant in
4087 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4088 switch (gdbarch_byte_order (gdbarch
))
4090 case BFD_ENDIAN_LITTLE
:
4091 mips_xfer_register (gdbarch
, regcache
,
4092 gdbarch_num_regs (gdbarch
)
4093 + mips_regnum (gdbarch
)->fp0
+
4094 0, 4, gdbarch_byte_order (gdbarch
),
4095 readbuf
, writebuf
, 0);
4096 mips_xfer_register (gdbarch
, regcache
,
4097 gdbarch_num_regs (gdbarch
)
4098 + mips_regnum (gdbarch
)->fp0
+ 1,
4099 4, gdbarch_byte_order (gdbarch
),
4100 readbuf
, writebuf
, 4);
4102 case BFD_ENDIAN_BIG
:
4103 mips_xfer_register (gdbarch
, regcache
,
4104 gdbarch_num_regs (gdbarch
)
4105 + mips_regnum (gdbarch
)->fp0
+ 1,
4106 4, gdbarch_byte_order (gdbarch
),
4107 readbuf
, writebuf
, 0);
4108 mips_xfer_register (gdbarch
, regcache
,
4109 gdbarch_num_regs (gdbarch
)
4110 + mips_regnum (gdbarch
)->fp0
+ 0,
4111 4, gdbarch_byte_order (gdbarch
),
4112 readbuf
, writebuf
, 4);
4115 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4117 return RETURN_VALUE_REGISTER_CONVENTION
;
4120 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4121 && TYPE_NFIELDS (type
) <= 2
4122 && TYPE_NFIELDS (type
) >= 1
4123 && ((TYPE_NFIELDS (type
) == 1
4124 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4126 || (TYPE_NFIELDS (type
) == 2
4127 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4129 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4131 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4133 /* A struct that contains one or two floats. Each value is part
4134 in the least significant part of their floating point
4136 gdb_byte reg
[MAX_REGISTER_SIZE
];
4139 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4140 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4142 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4145 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4147 mips_xfer_register (gdbarch
, regcache
,
4148 gdbarch_num_regs (gdbarch
) + regnum
,
4149 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4150 gdbarch_byte_order (gdbarch
),
4151 readbuf
, writebuf
, offset
);
4153 return RETURN_VALUE_REGISTER_CONVENTION
;
4157 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4158 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4160 /* A structure or union. Extract the left justified value,
4161 regardless of the byte order. I.e. DO NOT USE
4165 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4166 offset
< TYPE_LENGTH (type
);
4167 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4169 int xfer
= register_size (gdbarch
, regnum
);
4170 if (offset
+ xfer
> TYPE_LENGTH (type
))
4171 xfer
= TYPE_LENGTH (type
) - offset
;
4173 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4174 offset
, xfer
, regnum
);
4175 mips_xfer_register (gdbarch
, regcache
,
4176 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4177 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4179 return RETURN_VALUE_REGISTER_CONVENTION
;
4184 /* A scalar extract each part but least-significant-byte
4185 justified. o32 thinks registers are 4 byte, regardless of
4189 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4190 offset
< TYPE_LENGTH (type
);
4191 offset
+= MIPS32_REGSIZE
, regnum
++)
4193 int xfer
= MIPS32_REGSIZE
;
4194 if (offset
+ xfer
> TYPE_LENGTH (type
))
4195 xfer
= TYPE_LENGTH (type
) - offset
;
4197 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4198 offset
, xfer
, regnum
);
4199 mips_xfer_register (gdbarch
, regcache
,
4200 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4201 gdbarch_byte_order (gdbarch
),
4202 readbuf
, writebuf
, offset
);
4204 return RETURN_VALUE_REGISTER_CONVENTION
;
4208 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4212 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4213 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4215 struct value
**args
, CORE_ADDR sp
,
4216 int struct_return
, CORE_ADDR struct_addr
)
4222 int stack_offset
= 0;
4223 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4224 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4225 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4227 /* For shared libraries, "t9" needs to point at the function
4229 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4231 /* Set the return address register to point to the entry point of
4232 the program, where a breakpoint lies in wait. */
4233 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4235 /* First ensure that the stack and structure return address (if any)
4236 are properly aligned. The stack has to be at least 64-bit
4237 aligned even on 32-bit machines, because doubles must be 64-bit
4238 aligned. For n32 and n64, stack frames need to be 128-bit
4239 aligned, so we round to this widest known alignment. */
4241 sp
= align_down (sp
, 16);
4242 struct_addr
= align_down (struct_addr
, 16);
4244 /* Now make space on the stack for the args. */
4245 for (argnum
= 0; argnum
< nargs
; argnum
++)
4247 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4248 int arglen
= TYPE_LENGTH (arg_type
);
4250 /* Allocate space on the stack. */
4251 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4253 sp
-= align_up (len
, 16);
4256 fprintf_unfiltered (gdb_stdlog
,
4257 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4258 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4260 /* Initialize the integer and float register pointers. */
4261 argreg
= MIPS_A0_REGNUM
;
4262 float_argreg
= mips_fpa0_regnum (gdbarch
);
4264 /* The struct_return pointer occupies the first parameter-passing reg. */
4268 fprintf_unfiltered (gdb_stdlog
,
4269 "mips_o64_push_dummy_call: "
4270 "struct_return reg=%d %s\n",
4271 argreg
, paddress (gdbarch
, struct_addr
));
4272 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4273 stack_offset
+= MIPS64_REGSIZE
;
4276 /* Now load as many as possible of the first arguments into
4277 registers, and push the rest onto the stack. Loop thru args
4278 from first to last. */
4279 for (argnum
= 0; argnum
< nargs
; argnum
++)
4281 const gdb_byte
*val
;
4282 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4283 struct value
*arg
= args
[argnum
];
4284 struct type
*arg_type
= check_typedef (value_type (arg
));
4285 int len
= TYPE_LENGTH (arg_type
);
4286 enum type_code typecode
= TYPE_CODE (arg_type
);
4289 fprintf_unfiltered (gdb_stdlog
,
4290 "mips_o64_push_dummy_call: %d len=%d type=%d",
4291 argnum
+ 1, len
, (int) typecode
);
4293 val
= value_contents (arg
);
4295 /* Function pointer arguments to mips16 code need to be made into
4297 if (typecode
== TYPE_CODE_PTR
4298 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4300 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4302 if (mips_pc_is_mips16 (addr
))
4304 store_signed_integer (valbuf
, len
, byte_order
,
4305 make_mips16_addr (addr
));
4310 /* Floating point arguments passed in registers have to be
4311 treated specially. On 32-bit architectures, doubles
4312 are passed in register pairs; the even register gets
4313 the low word, and the odd register gets the high word.
4314 On O32/O64, the first two floating point arguments are
4315 also copied to general registers, because MIPS16 functions
4316 don't use float registers for arguments. This duplication of
4317 arguments in general registers can't hurt non-MIPS16 functions
4318 because those registers are normally skipped. */
4320 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4321 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4323 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4325 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4326 float_argreg
, phex (regval
, len
));
4327 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4329 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4330 argreg
, phex (regval
, len
));
4331 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4333 /* Reserve space for the FP register. */
4334 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4338 /* Copy the argument to general registers or the stack in
4339 register-sized pieces. Large arguments are split between
4340 registers and stack. */
4341 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4342 are treated specially: Irix cc passes them in registers
4343 where gcc sometimes puts them on the stack. For maximum
4344 compatibility, we will put them in both places. */
4345 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4346 && len
% MIPS64_REGSIZE
!= 0);
4349 /* Remember if the argument was written to the stack. */
4350 int stack_used_p
= 0;
4351 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4354 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4357 /* Write this portion of the argument to the stack. */
4358 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4359 || odd_sized_struct
)
4361 /* Should shorter than int integer values be
4362 promoted to int before being stored? */
4363 int longword_offset
= 0;
4366 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4368 if ((typecode
== TYPE_CODE_INT
4369 || typecode
== TYPE_CODE_PTR
4370 || typecode
== TYPE_CODE_FLT
)
4372 longword_offset
= MIPS64_REGSIZE
- len
;
4377 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4378 paddress (gdbarch
, stack_offset
));
4379 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4380 paddress (gdbarch
, longword_offset
));
4383 addr
= sp
+ stack_offset
+ longword_offset
;
4388 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4389 paddress (gdbarch
, addr
));
4390 for (i
= 0; i
< partial_len
; i
++)
4392 fprintf_unfiltered (gdb_stdlog
, "%02x",
4396 write_memory (addr
, val
, partial_len
);
4399 /* Note!!! This is NOT an else clause. Odd sized
4400 structs may go thru BOTH paths. */
4401 /* Write this portion of the argument to a general
4402 purpose register. */
4403 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4405 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4407 /* Value may need to be sign extended, because
4408 mips_isa_regsize() != mips_abi_regsize(). */
4410 /* A non-floating-point argument being passed in a
4411 general register. If a struct or union, and if
4412 the remaining length is smaller than the register
4413 size, we have to adjust the register value on
4416 It does not seem to be necessary to do the
4417 same for integral types. */
4419 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4420 && partial_len
< MIPS64_REGSIZE
4421 && (typecode
== TYPE_CODE_STRUCT
4422 || typecode
== TYPE_CODE_UNION
))
4423 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4427 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4429 phex (regval
, MIPS64_REGSIZE
));
4430 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4433 /* Prevent subsequent floating point arguments from
4434 being passed in floating point registers. */
4435 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4441 /* Compute the offset into the stack at which we will
4442 copy the next parameter.
4444 In older ABIs, the caller reserved space for
4445 registers that contained arguments. This was loosely
4446 refered to as their "home". Consequently, space is
4447 always allocated. */
4449 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4453 fprintf_unfiltered (gdb_stdlog
, "\n");
4456 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4458 /* Return adjusted stack pointer. */
4462 static enum return_value_convention
4463 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4464 struct type
*type
, struct regcache
*regcache
,
4465 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4467 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4469 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4470 || TYPE_CODE (type
) == TYPE_CODE_UNION
4471 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4472 return RETURN_VALUE_STRUCT_CONVENTION
;
4473 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4475 /* A floating-point value. It fits in the least significant
4478 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4479 mips_xfer_register (gdbarch
, regcache
,
4480 gdbarch_num_regs (gdbarch
)
4481 + mips_regnum (gdbarch
)->fp0
,
4483 gdbarch_byte_order (gdbarch
),
4484 readbuf
, writebuf
, 0);
4485 return RETURN_VALUE_REGISTER_CONVENTION
;
4489 /* A scalar extract each part but least-significant-byte
4493 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4494 offset
< TYPE_LENGTH (type
);
4495 offset
+= MIPS64_REGSIZE
, regnum
++)
4497 int xfer
= MIPS64_REGSIZE
;
4498 if (offset
+ xfer
> TYPE_LENGTH (type
))
4499 xfer
= TYPE_LENGTH (type
) - offset
;
4501 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4502 offset
, xfer
, regnum
);
4503 mips_xfer_register (gdbarch
, regcache
,
4504 gdbarch_num_regs (gdbarch
) + regnum
,
4505 xfer
, gdbarch_byte_order (gdbarch
),
4506 readbuf
, writebuf
, offset
);
4508 return RETURN_VALUE_REGISTER_CONVENTION
;
4512 /* Floating point register management.
4514 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4515 64bit operations, these early MIPS cpus treat fp register pairs
4516 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4517 registers and offer a compatibility mode that emulates the MIPS2 fp
4518 model. When operating in MIPS2 fp compat mode, later cpu's split
4519 double precision floats into two 32-bit chunks and store them in
4520 consecutive fp regs. To display 64-bit floats stored in this
4521 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4522 Throw in user-configurable endianness and you have a real mess.
4524 The way this works is:
4525 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4526 double-precision value will be split across two logical registers.
4527 The lower-numbered logical register will hold the low-order bits,
4528 regardless of the processor's endianness.
4529 - If we are on a 64-bit processor, and we are looking for a
4530 single-precision value, it will be in the low ordered bits
4531 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4532 save slot in memory.
4533 - If we are in 64-bit mode, everything is straightforward.
4535 Note that this code only deals with "live" registers at the top of the
4536 stack. We will attempt to deal with saved registers later, when
4537 the raw/cooked register interface is in place. (We need a general
4538 interface that can deal with dynamic saved register sizes -- fp
4539 regs could be 32 bits wide in one frame and 64 on the frame above
4542 /* Copy a 32-bit single-precision value from the current frame
4543 into rare_buffer. */
4546 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4547 gdb_byte
*rare_buffer
)
4549 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4550 int raw_size
= register_size (gdbarch
, regno
);
4551 gdb_byte
*raw_buffer
= alloca (raw_size
);
4553 if (!frame_register_read (frame
, regno
, raw_buffer
))
4554 error (_("can't read register %d (%s)"),
4555 regno
, gdbarch_register_name (gdbarch
, regno
));
4558 /* We have a 64-bit value for this register. Find the low-order
4562 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4567 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4571 memcpy (rare_buffer
, raw_buffer
, 4);
4575 /* Copy a 64-bit double-precision value from the current frame into
4576 rare_buffer. This may include getting half of it from the next
4580 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4581 gdb_byte
*rare_buffer
)
4583 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4584 int raw_size
= register_size (gdbarch
, regno
);
4586 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4588 /* We have a 64-bit value for this register, and we should use
4590 if (!frame_register_read (frame
, regno
, rare_buffer
))
4591 error (_("can't read register %d (%s)"),
4592 regno
, gdbarch_register_name (gdbarch
, regno
));
4596 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4598 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4599 internal_error (__FILE__
, __LINE__
,
4600 _("mips_read_fp_register_double: bad access to "
4601 "odd-numbered FP register"));
4603 /* mips_read_fp_register_single will find the correct 32 bits from
4605 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4607 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4608 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4612 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4613 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4619 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4621 { /* Do values for FP (float) regs. */
4622 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4623 gdb_byte
*raw_buffer
;
4624 double doub
, flt1
; /* Doubles extracted from raw hex data. */
4627 raw_buffer
= alloca (2 * register_size (gdbarch
,
4628 mips_regnum (gdbarch
)->fp0
));
4630 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4631 fprintf_filtered (file
, "%*s",
4632 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4635 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4637 struct value_print_options opts
;
4639 /* 4-byte registers: Print hex and floating. Also print even
4640 numbered registers as doubles. */
4641 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4642 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4645 get_formatted_print_options (&opts
, 'x');
4646 print_scalar_formatted (raw_buffer
,
4647 builtin_type (gdbarch
)->builtin_uint32
,
4650 fprintf_filtered (file
, " flt: ");
4652 fprintf_filtered (file
, " <invalid float> ");
4654 fprintf_filtered (file
, "%-17.9g", flt1
);
4656 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4658 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4659 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4662 fprintf_filtered (file
, " dbl: ");
4664 fprintf_filtered (file
, "<invalid double>");
4666 fprintf_filtered (file
, "%-24.17g", doub
);
4671 struct value_print_options opts
;
4673 /* Eight byte registers: print each one as hex, float and double. */
4674 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4675 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4678 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4679 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4682 get_formatted_print_options (&opts
, 'x');
4683 print_scalar_formatted (raw_buffer
,
4684 builtin_type (gdbarch
)->builtin_uint64
,
4687 fprintf_filtered (file
, " flt: ");
4689 fprintf_filtered (file
, "<invalid float>");
4691 fprintf_filtered (file
, "%-17.9g", flt1
);
4693 fprintf_filtered (file
, " dbl: ");
4695 fprintf_filtered (file
, "<invalid double>");
4697 fprintf_filtered (file
, "%-24.17g", doub
);
4702 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4705 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4707 struct value_print_options opts
;
4710 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4712 mips_print_fp_register (file
, frame
, regnum
);
4716 val
= get_frame_register_value (frame
, regnum
);
4717 if (value_optimized_out (val
))
4719 fprintf_filtered (file
, "%s: [Invalid]",
4720 gdbarch_register_name (gdbarch
, regnum
));
4724 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4726 /* The problem with printing numeric register names (r26, etc.) is that
4727 the user can't use them on input. Probably the best solution is to
4728 fix it so that either the numeric or the funky (a2, etc.) names
4729 are accepted on input. */
4730 if (regnum
< MIPS_NUMREGS
)
4731 fprintf_filtered (file
, "(r%d): ", regnum
);
4733 fprintf_filtered (file
, ": ");
4735 get_formatted_print_options (&opts
, 'x');
4736 val_print_scalar_formatted (value_type (val
),
4737 value_contents_for_printing (val
),
4738 value_embedded_offset (val
),
4743 /* Replacement for generic do_registers_info.
4744 Print regs in pretty columns. */
4747 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4750 fprintf_filtered (file
, " ");
4751 mips_print_fp_register (file
, frame
, regnum
);
4752 fprintf_filtered (file
, "\n");
4757 /* Print a row's worth of GP (int) registers, with name labels above. */
4760 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4763 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4764 /* Do values for GP (int) regs. */
4765 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4766 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
4771 /* For GP registers, we print a separate row of names above the vals. */
4772 for (col
= 0, regnum
= start_regnum
;
4773 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4774 + gdbarch_num_pseudo_regs (gdbarch
);
4777 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4778 continue; /* unused register */
4779 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4781 break; /* End the row: reached FP register. */
4782 /* Large registers are handled separately. */
4783 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4786 break; /* End the row before this register. */
4788 /* Print this register on a row by itself. */
4789 mips_print_register (file
, frame
, regnum
);
4790 fprintf_filtered (file
, "\n");
4794 fprintf_filtered (file
, " ");
4795 fprintf_filtered (file
,
4796 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4797 gdbarch_register_name (gdbarch
, regnum
));
4804 /* Print the R0 to R31 names. */
4805 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4806 fprintf_filtered (file
, "\n R%-4d",
4807 start_regnum
% gdbarch_num_regs (gdbarch
));
4809 fprintf_filtered (file
, "\n ");
4811 /* Now print the values in hex, 4 or 8 to the row. */
4812 for (col
= 0, regnum
= start_regnum
;
4813 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4814 + gdbarch_num_pseudo_regs (gdbarch
);
4817 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4818 continue; /* unused register */
4819 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4821 break; /* End row: reached FP register. */
4822 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4823 break; /* End row: large register. */
4825 /* OK: get the data in raw format. */
4826 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4827 error (_("can't read register %d (%s)"),
4828 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4829 /* pad small registers */
4831 byte
< (mips_abi_regsize (gdbarch
)
4832 - register_size (gdbarch
, regnum
)); byte
++)
4833 printf_filtered (" ");
4834 /* Now print the register value in hex, endian order. */
4835 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4837 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4838 byte
< register_size (gdbarch
, regnum
); byte
++)
4839 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4841 for (byte
= register_size (gdbarch
, regnum
) - 1;
4843 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4844 fprintf_filtered (file
, " ");
4847 if (col
> 0) /* ie. if we actually printed anything... */
4848 fprintf_filtered (file
, "\n");
4853 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
4856 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4857 struct frame_info
*frame
, int regnum
, int all
)
4859 if (regnum
!= -1) /* Do one specified register. */
4861 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4862 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4863 error (_("Not a valid register for the current processor type"));
4865 mips_print_register (file
, frame
, regnum
);
4866 fprintf_filtered (file
, "\n");
4869 /* Do all (or most) registers. */
4871 regnum
= gdbarch_num_regs (gdbarch
);
4872 while (regnum
< gdbarch_num_regs (gdbarch
)
4873 + gdbarch_num_pseudo_regs (gdbarch
))
4875 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4878 if (all
) /* True for "INFO ALL-REGISTERS" command. */
4879 regnum
= print_fp_register_row (file
, frame
, regnum
);
4881 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
4884 regnum
= print_gp_register_row (file
, frame
, regnum
);
4889 /* Is this a branch with a delay slot? */
4892 is_delayed (unsigned long insn
)
4895 for (i
= 0; i
< NUMOPCODES
; ++i
)
4896 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4897 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4899 return (i
< NUMOPCODES
4900 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4901 | INSN_COND_BRANCH_DELAY
4902 | INSN_COND_BRANCH_LIKELY
)));
4906 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4907 struct frame_info
*frame
)
4909 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4910 CORE_ADDR pc
= get_frame_pc (frame
);
4911 gdb_byte buf
[MIPS_INSN32_SIZE
];
4913 /* There is no branch delay slot on MIPS16. */
4914 if (mips_pc_is_mips16 (pc
))
4917 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
4920 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4921 /* If error reading memory, guess that it is not a delayed
4924 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
4927 /* To skip prologues, I use this predicate. Returns either PC itself
4928 if the code at PC does not look like a function prologue; otherwise
4929 returns an address that (if we're lucky) follows the prologue. If
4930 LENIENT, then we must skip everything which is involved in setting
4931 up the frame (it's OK to skip more, just so long as we don't skip
4932 anything which might clobber the registers which are being saved.
4933 We must skip more in the case where part of the prologue is in the
4934 delay slot of a non-prologue instruction). */
4937 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4940 CORE_ADDR func_addr
;
4942 /* See if we can determine the end of the prologue via the symbol table.
4943 If so, then return either PC, or the PC after the prologue, whichever
4945 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4947 CORE_ADDR post_prologue_pc
4948 = skip_prologue_using_sal (gdbarch
, func_addr
);
4949 if (post_prologue_pc
!= 0)
4950 return max (pc
, post_prologue_pc
);
4953 /* Can't determine prologue from the symbol table, need to examine
4956 /* Find an upper limit on the function prologue using the debug
4957 information. If the debug information could not be used to provide
4958 that bound, then use an arbitrary large number as the upper bound. */
4959 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
4961 limit_pc
= pc
+ 100; /* Magic. */
4963 if (mips_pc_is_mips16 (pc
))
4964 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4966 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4969 /* Check whether the PC is in a function epilogue (32-bit version).
4970 This is a helper function for mips_in_function_epilogue_p. */
4972 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4974 CORE_ADDR func_addr
= 0, func_end
= 0;
4976 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4978 /* The MIPS epilogue is max. 12 bytes long. */
4979 CORE_ADDR addr
= func_end
- 12;
4981 if (addr
< func_addr
+ 4)
4982 addr
= func_addr
+ 4;
4986 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4988 unsigned long high_word
;
4991 inst
= mips_fetch_instruction (gdbarch
, pc
);
4992 high_word
= (inst
>> 16) & 0xffff;
4994 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4995 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4996 && inst
!= 0x03e00008 /* jr $ra */
4997 && inst
!= 0x00000000) /* nop */
5007 /* Check whether the PC is in a function epilogue (16-bit version).
5008 This is a helper function for mips_in_function_epilogue_p. */
5010 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5012 CORE_ADDR func_addr
= 0, func_end
= 0;
5014 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5016 /* The MIPS epilogue is max. 12 bytes long. */
5017 CORE_ADDR addr
= func_end
- 12;
5019 if (addr
< func_addr
+ 4)
5020 addr
= func_addr
+ 4;
5024 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
5026 unsigned short inst
;
5028 inst
= mips_fetch_instruction (gdbarch
, pc
);
5030 if ((inst
& 0xf800) == 0xf000) /* extend */
5033 if (inst
!= 0x6300 /* addiu $sp,offset */
5034 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
5035 && inst
!= 0xe820 /* jr $ra */
5036 && inst
!= 0xe8a0 /* jrc $ra */
5037 && inst
!= 0x6500) /* nop */
5047 /* The epilogue is defined here as the area at the end of a function,
5048 after an instruction which destroys the function's stack frame. */
5050 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5052 if (mips_pc_is_mips16 (pc
))
5053 return mips16_in_function_epilogue_p (gdbarch
, pc
);
5055 return mips32_in_function_epilogue_p (gdbarch
, pc
);
5058 /* Root of all "set mips "/"show mips " commands. This will eventually be
5059 used for all MIPS-specific commands. */
5062 show_mips_command (char *args
, int from_tty
)
5064 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5068 set_mips_command (char *args
, int from_tty
)
5071 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5072 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5075 /* Commands to show/set the MIPS FPU type. */
5078 show_mipsfpu_command (char *args
, int from_tty
)
5082 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5085 ("The MIPS floating-point coprocessor is unknown "
5086 "because the current architecture is not MIPS.\n");
5090 switch (MIPS_FPU_TYPE (target_gdbarch
))
5092 case MIPS_FPU_SINGLE
:
5093 fpu
= "single-precision";
5095 case MIPS_FPU_DOUBLE
:
5096 fpu
= "double-precision";
5099 fpu
= "absent (none)";
5102 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5104 if (mips_fpu_type_auto
)
5105 printf_unfiltered ("The MIPS floating-point coprocessor "
5106 "is set automatically (currently %s)\n",
5110 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5115 set_mipsfpu_command (char *args
, int from_tty
)
5117 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
5118 "\"single\",\"none\" or \"auto\".\n");
5119 show_mipsfpu_command (args
, from_tty
);
5123 set_mipsfpu_single_command (char *args
, int from_tty
)
5125 struct gdbarch_info info
;
5126 gdbarch_info_init (&info
);
5127 mips_fpu_type
= MIPS_FPU_SINGLE
;
5128 mips_fpu_type_auto
= 0;
5129 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5130 instead of relying on globals. Doing that would let generic code
5131 handle the search for this specific architecture. */
5132 if (!gdbarch_update_p (info
))
5133 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5137 set_mipsfpu_double_command (char *args
, int from_tty
)
5139 struct gdbarch_info info
;
5140 gdbarch_info_init (&info
);
5141 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5142 mips_fpu_type_auto
= 0;
5143 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5144 instead of relying on globals. Doing that would let generic code
5145 handle the search for this specific architecture. */
5146 if (!gdbarch_update_p (info
))
5147 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5151 set_mipsfpu_none_command (char *args
, int from_tty
)
5153 struct gdbarch_info info
;
5154 gdbarch_info_init (&info
);
5155 mips_fpu_type
= MIPS_FPU_NONE
;
5156 mips_fpu_type_auto
= 0;
5157 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5158 instead of relying on globals. Doing that would let generic code
5159 handle the search for this specific architecture. */
5160 if (!gdbarch_update_p (info
))
5161 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5165 set_mipsfpu_auto_command (char *args
, int from_tty
)
5167 mips_fpu_type_auto
= 1;
5170 /* Attempt to identify the particular processor model by reading the
5171 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5172 the relevant processor still exists (it dates back to '94) and
5173 secondly this is not the way to do this. The processor type should
5174 be set by forcing an architecture change. */
5177 deprecated_mips_set_processor_regs_hack (void)
5179 struct regcache
*regcache
= get_current_regcache ();
5180 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5181 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5184 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5185 if ((prid
& ~0xf) == 0x700)
5186 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5189 /* Just like reinit_frame_cache, but with the right arguments to be
5190 callable as an sfunc. */
5193 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5194 struct cmd_list_element
*c
)
5196 reinit_frame_cache ();
5200 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5202 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5203 disassembler needs to be able to locally determine the ISA, and
5204 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5206 if (mips_pc_is_mips16 (memaddr
))
5207 info
->mach
= bfd_mach_mips16
;
5209 /* Round down the instruction address to the appropriate boundary. */
5210 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5212 /* Set the disassembler options. */
5213 if (!info
->disassembler_options
)
5214 /* This string is not recognized explicitly by the disassembler,
5215 but it tells the disassembler to not try to guess the ABI from
5216 the bfd elf headers, such that, if the user overrides the ABI
5217 of a program linked as NewABI, the disassembly will follow the
5218 register naming conventions specified by the user. */
5219 info
->disassembler_options
= "gpr-names=32";
5221 /* Call the appropriate disassembler based on the target endian-ness. */
5222 if (info
->endian
== BFD_ENDIAN_BIG
)
5223 return print_insn_big_mips (memaddr
, info
);
5225 return print_insn_little_mips (memaddr
, info
);
5229 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5231 /* Set up the disassembler info, so that we get the right
5232 register names from libopcodes. */
5233 info
->disassembler_options
= "gpr-names=n32";
5234 info
->flavour
= bfd_target_elf_flavour
;
5236 return gdb_print_insn_mips (memaddr
, info
);
5240 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5242 /* Set up the disassembler info, so that we get the right
5243 register names from libopcodes. */
5244 info
->disassembler_options
= "gpr-names=64";
5245 info
->flavour
= bfd_target_elf_flavour
;
5247 return gdb_print_insn_mips (memaddr
, info
);
5250 /* This function implements gdbarch_breakpoint_from_pc. It uses the
5251 program counter value to determine whether a 16- or 32-bit breakpoint
5252 should be used. It returns a pointer to a string of bytes that encode a
5253 breakpoint instruction, stores the length of the string to *lenptr, and
5254 adjusts pc (if necessary) to point to the actual memory location where
5255 the breakpoint should be inserted. */
5257 static const gdb_byte
*
5258 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
5259 CORE_ADDR
*pcptr
, int *lenptr
)
5261 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5263 if (mips_pc_is_mips16 (*pcptr
))
5265 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5266 *pcptr
= unmake_mips16_addr (*pcptr
);
5267 *lenptr
= sizeof (mips16_big_breakpoint
);
5268 return mips16_big_breakpoint
;
5272 /* The IDT board uses an unusual breakpoint value, and
5273 sometimes gets confused when it sees the usual MIPS
5274 breakpoint instruction. */
5275 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5276 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5277 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5278 /* Likewise, IRIX appears to expect a different breakpoint,
5279 although this is not apparent until you try to use pthreads. */
5280 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5282 *lenptr
= sizeof (big_breakpoint
);
5284 if (strcmp (target_shortname
, "mips") == 0)
5285 return idt_big_breakpoint
;
5286 else if (strcmp (target_shortname
, "ddb") == 0
5287 || strcmp (target_shortname
, "pmon") == 0
5288 || strcmp (target_shortname
, "lsi") == 0)
5289 return pmon_big_breakpoint
;
5290 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5291 return irix_big_breakpoint
;
5293 return big_breakpoint
;
5298 if (mips_pc_is_mips16 (*pcptr
))
5300 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5301 *pcptr
= unmake_mips16_addr (*pcptr
);
5302 *lenptr
= sizeof (mips16_little_breakpoint
);
5303 return mips16_little_breakpoint
;
5307 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5308 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5309 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5311 *lenptr
= sizeof (little_breakpoint
);
5313 if (strcmp (target_shortname
, "mips") == 0)
5314 return idt_little_breakpoint
;
5315 else if (strcmp (target_shortname
, "ddb") == 0
5316 || strcmp (target_shortname
, "pmon") == 0
5317 || strcmp (target_shortname
, "lsi") == 0)
5318 return pmon_little_breakpoint
;
5320 return little_breakpoint
;
5325 /* If PC is in a mips16 call or return stub, return the address of the target
5326 PC, which is either the callee or the caller. There are several
5327 cases which must be handled:
5329 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5330 target PC is in $31 ($ra).
5331 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5332 and the target PC is in $2.
5333 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5334 before the jal instruction, this is effectively a call stub
5335 and the target PC is in $2. Otherwise this is effectively
5336 a return stub and the target PC is in $18.
5338 See the source code for the stubs in gcc/config/mips/mips16.S for
5342 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5344 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5346 CORE_ADDR start_addr
;
5348 /* Find the starting address and name of the function containing the PC. */
5349 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5352 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5353 target PC is in $31 ($ra). */
5354 if (strcmp (name
, "__mips16_ret_sf") == 0
5355 || strcmp (name
, "__mips16_ret_df") == 0)
5356 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5358 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5360 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5361 and the target PC is in $2. */
5362 if (name
[19] >= '0' && name
[19] <= '9')
5363 return get_frame_register_signed (frame
, 2);
5365 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5366 before the jal instruction, this is effectively a call stub
5367 and the target PC is in $2. Otherwise this is effectively
5368 a return stub and the target PC is in $18. */
5369 else if (name
[19] == 's' || name
[19] == 'd')
5371 if (pc
== start_addr
)
5373 /* Check if the target of the stub is a compiler-generated
5374 stub. Such a stub for a function bar might have a name
5375 like __fn_stub_bar, and might look like this:
5380 la $1,bar (becomes a lui/addiu pair)
5382 So scan down to the lui/addi and extract the target
5383 address from those two instructions. */
5385 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5389 /* See if the name of the target function is __fn_stub_*. */
5390 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5393 if (strncmp (name
, "__fn_stub_", 10) != 0
5394 && strcmp (name
, "etext") != 0
5395 && strcmp (name
, "_etext") != 0)
5398 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5399 The limit on the search is arbitrarily set to 20
5400 instructions. FIXME. */
5401 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5403 inst
= mips_fetch_instruction (gdbarch
, target_pc
);
5404 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5405 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5406 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5407 return pc
| (inst
& 0xffff); /* low word */
5410 /* Couldn't find the lui/addui pair, so return stub address. */
5414 /* This is the 'return' part of a call stub. The return
5415 address is in $r18. */
5416 return get_frame_register_signed (frame
, 18);
5419 return 0; /* not a stub */
5422 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5423 PC of the stub target. The stub just loads $t9 and jumps to it,
5424 so that $t9 has the correct value at function entry. */
5427 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5429 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5430 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5431 struct minimal_symbol
*msym
;
5433 gdb_byte stub_code
[16];
5434 int32_t stub_words
[4];
5436 /* The stub for foo is named ".pic.foo", and is either two
5437 instructions inserted before foo or a three instruction sequence
5438 which jumps to foo. */
5439 msym
= lookup_minimal_symbol_by_pc (pc
);
5441 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5442 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5443 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5446 /* A two-instruction header. */
5447 if (MSYMBOL_SIZE (msym
) == 8)
5450 /* A three-instruction (plus delay slot) trampoline. */
5451 if (MSYMBOL_SIZE (msym
) == 16)
5453 if (target_read_memory (pc
, stub_code
, 16) != 0)
5455 for (i
= 0; i
< 4; i
++)
5456 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
5459 /* A stub contains these instructions:
5462 addiu t9, t9, %lo(target)
5465 This works even for N64, since stubs are only generated with
5467 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5468 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5469 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5470 && stub_words
[3] == 0x00000000)
5471 return (((stub_words
[0] & 0x0000ffff) << 16)
5472 + (stub_words
[2] & 0x0000ffff));
5475 /* Not a recognized stub. */
5480 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5482 CORE_ADDR target_pc
;
5484 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5488 target_pc
= find_solib_trampoline_target (frame
, pc
);
5492 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5499 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5500 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5503 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5506 if (num
>= 0 && num
< 32)
5508 else if (num
>= 38 && num
< 70)
5509 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5511 regnum
= mips_regnum (gdbarch
)->hi
;
5513 regnum
= mips_regnum (gdbarch
)->lo
;
5515 /* This will hopefully (eventually) provoke a warning. Should
5516 we be calling complaint() here? */
5517 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5518 return gdbarch_num_regs (gdbarch
) + regnum
;
5522 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5523 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5526 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5529 if (num
>= 0 && num
< 32)
5531 else if (num
>= 32 && num
< 64)
5532 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5534 regnum
= mips_regnum (gdbarch
)->hi
;
5536 regnum
= mips_regnum (gdbarch
)->lo
;
5538 /* This will hopefully (eventually) provoke a warning. Should we
5539 be calling complaint() here? */
5540 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5541 return gdbarch_num_regs (gdbarch
) + regnum
;
5545 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5547 /* Only makes sense to supply raw registers. */
5548 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5549 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5550 decide if it is valid. Should instead define a standard sim/gdb
5551 register numbering scheme. */
5552 if (gdbarch_register_name (gdbarch
,
5553 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5554 && gdbarch_register_name (gdbarch
,
5555 gdbarch_num_regs (gdbarch
)
5556 + regnum
)[0] != '\0')
5559 return LEGACY_SIM_REGNO_IGNORE
;
5563 /* Convert an integer into an address. Extracting the value signed
5564 guarantees a correctly sign extended address. */
5567 mips_integer_to_address (struct gdbarch
*gdbarch
,
5568 struct type
*type
, const gdb_byte
*buf
)
5570 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5571 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
5574 /* Dummy virtual frame pointer method. This is no more or less accurate
5575 than most other architectures; we just need to be explicit about it,
5576 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5577 an assertion failure. */
5580 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5581 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5583 *reg
= MIPS_SP_REGNUM
;
5588 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5590 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5591 const char *name
= bfd_get_section_name (abfd
, sect
);
5593 if (*abip
!= MIPS_ABI_UNKNOWN
)
5596 if (strncmp (name
, ".mdebug.", 8) != 0)
5599 if (strcmp (name
, ".mdebug.abi32") == 0)
5600 *abip
= MIPS_ABI_O32
;
5601 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5602 *abip
= MIPS_ABI_N32
;
5603 else if (strcmp (name
, ".mdebug.abi64") == 0)
5604 *abip
= MIPS_ABI_N64
;
5605 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5606 *abip
= MIPS_ABI_O64
;
5607 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5608 *abip
= MIPS_ABI_EABI32
;
5609 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5610 *abip
= MIPS_ABI_EABI64
;
5612 warning (_("unsupported ABI %s."), name
+ 8);
5616 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5618 int *lbp
= (int *) obj
;
5619 const char *name
= bfd_get_section_name (abfd
, sect
);
5621 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5623 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5625 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5626 warning (_("unrecognized .gcc_compiled_longXX"));
5629 static enum mips_abi
5630 global_mips_abi (void)
5634 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5635 if (mips_abi_strings
[i
] == mips_abi_string
)
5636 return (enum mips_abi
) i
;
5638 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5642 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5644 /* If the size matches the set of 32-bit or 64-bit integer registers,
5645 assume that's what we've got. */
5646 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5647 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5649 /* If the size matches the full set of registers GDB traditionally
5650 knows about, including floating point, for either 32-bit or
5651 64-bit, assume that's what we've got. */
5652 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5653 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5655 /* Otherwise we don't have a useful guess. */
5658 static struct value
*
5659 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5661 const int *reg_p
= baton
;
5662 return value_of_register (*reg_p
, frame
);
5665 static struct gdbarch
*
5666 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5668 struct gdbarch
*gdbarch
;
5669 struct gdbarch_tdep
*tdep
;
5671 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5673 enum mips_fpu_type fpu_type
;
5674 struct tdesc_arch_data
*tdesc_data
= NULL
;
5675 int elf_fpu_type
= 0;
5677 /* Check any target description for validity. */
5678 if (tdesc_has_registers (info
.target_desc
))
5680 static const char *const mips_gprs
[] = {
5681 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5682 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5683 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5684 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5686 static const char *const mips_fprs
[] = {
5687 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5688 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5689 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5690 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5693 const struct tdesc_feature
*feature
;
5696 feature
= tdesc_find_feature (info
.target_desc
,
5697 "org.gnu.gdb.mips.cpu");
5698 if (feature
== NULL
)
5701 tdesc_data
= tdesc_data_alloc ();
5704 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5705 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5709 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5710 MIPS_EMBED_LO_REGNUM
, "lo");
5711 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5712 MIPS_EMBED_HI_REGNUM
, "hi");
5713 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5714 MIPS_EMBED_PC_REGNUM
, "pc");
5718 tdesc_data_cleanup (tdesc_data
);
5722 feature
= tdesc_find_feature (info
.target_desc
,
5723 "org.gnu.gdb.mips.cp0");
5724 if (feature
== NULL
)
5726 tdesc_data_cleanup (tdesc_data
);
5731 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5732 MIPS_EMBED_BADVADDR_REGNUM
,
5734 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5735 MIPS_PS_REGNUM
, "status");
5736 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5737 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5741 tdesc_data_cleanup (tdesc_data
);
5745 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5746 backend is not prepared for that, though. */
5747 feature
= tdesc_find_feature (info
.target_desc
,
5748 "org.gnu.gdb.mips.fpu");
5749 if (feature
== NULL
)
5751 tdesc_data_cleanup (tdesc_data
);
5756 for (i
= 0; i
< 32; i
++)
5757 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5758 i
+ MIPS_EMBED_FP0_REGNUM
,
5761 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5762 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5763 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5764 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5768 tdesc_data_cleanup (tdesc_data
);
5772 /* It would be nice to detect an attempt to use a 64-bit ABI
5773 when only 32-bit registers are provided. */
5776 /* First of all, extract the elf_flags, if available. */
5777 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5778 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5779 else if (arches
!= NULL
)
5780 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5784 fprintf_unfiltered (gdb_stdlog
,
5785 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5787 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5788 switch ((elf_flags
& EF_MIPS_ABI
))
5790 case E_MIPS_ABI_O32
:
5791 found_abi
= MIPS_ABI_O32
;
5793 case E_MIPS_ABI_O64
:
5794 found_abi
= MIPS_ABI_O64
;
5796 case E_MIPS_ABI_EABI32
:
5797 found_abi
= MIPS_ABI_EABI32
;
5799 case E_MIPS_ABI_EABI64
:
5800 found_abi
= MIPS_ABI_EABI64
;
5803 if ((elf_flags
& EF_MIPS_ABI2
))
5804 found_abi
= MIPS_ABI_N32
;
5806 found_abi
= MIPS_ABI_UNKNOWN
;
5810 /* GCC creates a pseudo-section whose name describes the ABI. */
5811 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5812 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5814 /* If we have no useful BFD information, use the ABI from the last
5815 MIPS architecture (if there is one). */
5816 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5817 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5819 /* Try the architecture for any hint of the correct ABI. */
5820 if (found_abi
== MIPS_ABI_UNKNOWN
5821 && info
.bfd_arch_info
!= NULL
5822 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5824 switch (info
.bfd_arch_info
->mach
)
5826 case bfd_mach_mips3900
:
5827 found_abi
= MIPS_ABI_EABI32
;
5829 case bfd_mach_mips4100
:
5830 case bfd_mach_mips5000
:
5831 found_abi
= MIPS_ABI_EABI64
;
5833 case bfd_mach_mips8000
:
5834 case bfd_mach_mips10000
:
5835 /* On Irix, ELF64 executables use the N64 ABI. The
5836 pseudo-sections which describe the ABI aren't present
5837 on IRIX. (Even for executables created by gcc.) */
5838 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5839 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5840 found_abi
= MIPS_ABI_N64
;
5842 found_abi
= MIPS_ABI_N32
;
5847 /* Default 64-bit objects to N64 instead of O32. */
5848 if (found_abi
== MIPS_ABI_UNKNOWN
5849 && info
.abfd
!= NULL
5850 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5851 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5852 found_abi
= MIPS_ABI_N64
;
5855 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5858 /* What has the user specified from the command line? */
5859 wanted_abi
= global_mips_abi ();
5861 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5864 /* Now that we have found what the ABI for this binary would be,
5865 check whether the user is overriding it. */
5866 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5867 mips_abi
= wanted_abi
;
5868 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5869 mips_abi
= found_abi
;
5871 mips_abi
= MIPS_ABI_O32
;
5873 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5876 /* Also used when doing an architecture lookup. */
5878 fprintf_unfiltered (gdb_stdlog
,
5879 "mips_gdbarch_init: "
5880 "mips64_transfers_32bit_regs_p = %d\n",
5881 mips64_transfers_32bit_regs_p
);
5883 /* Determine the MIPS FPU type. */
5886 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5887 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5888 Tag_GNU_MIPS_ABI_FP
);
5889 #endif /* HAVE_ELF */
5891 if (!mips_fpu_type_auto
)
5892 fpu_type
= mips_fpu_type
;
5893 else if (elf_fpu_type
!= 0)
5895 switch (elf_fpu_type
)
5898 fpu_type
= MIPS_FPU_DOUBLE
;
5901 fpu_type
= MIPS_FPU_SINGLE
;
5905 /* Soft float or unknown. */
5906 fpu_type
= MIPS_FPU_NONE
;
5910 else if (info
.bfd_arch_info
!= NULL
5911 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5912 switch (info
.bfd_arch_info
->mach
)
5914 case bfd_mach_mips3900
:
5915 case bfd_mach_mips4100
:
5916 case bfd_mach_mips4111
:
5917 case bfd_mach_mips4120
:
5918 fpu_type
= MIPS_FPU_NONE
;
5920 case bfd_mach_mips4650
:
5921 fpu_type
= MIPS_FPU_SINGLE
;
5924 fpu_type
= MIPS_FPU_DOUBLE
;
5927 else if (arches
!= NULL
)
5928 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5930 fpu_type
= MIPS_FPU_DOUBLE
;
5932 fprintf_unfiltered (gdb_stdlog
,
5933 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5935 /* Check for blatant incompatibilities. */
5937 /* If we have only 32-bit registers, then we can't debug a 64-bit
5939 if (info
.target_desc
5940 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5941 && mips_abi
!= MIPS_ABI_EABI32
5942 && mips_abi
!= MIPS_ABI_O32
)
5944 if (tdesc_data
!= NULL
)
5945 tdesc_data_cleanup (tdesc_data
);
5949 /* Try to find a pre-existing architecture. */
5950 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5952 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5954 /* MIPS needs to be pedantic about which ABI the object is
5956 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5958 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5960 /* Need to be pedantic about which register virtual size is
5962 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5963 != mips64_transfers_32bit_regs_p
)
5965 /* Be pedantic about which FPU is selected. */
5966 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5969 if (tdesc_data
!= NULL
)
5970 tdesc_data_cleanup (tdesc_data
);
5971 return arches
->gdbarch
;
5974 /* Need a new architecture. Fill in a target specific vector. */
5975 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5976 gdbarch
= gdbarch_alloc (&info
, tdep
);
5977 tdep
->elf_flags
= elf_flags
;
5978 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5979 tdep
->found_abi
= found_abi
;
5980 tdep
->mips_abi
= mips_abi
;
5981 tdep
->mips_fpu_type
= fpu_type
;
5982 tdep
->register_size_valid_p
= 0;
5983 tdep
->register_size
= 0;
5984 tdep
->gregset
= NULL
;
5985 tdep
->gregset64
= NULL
;
5986 tdep
->fpregset
= NULL
;
5987 tdep
->fpregset64
= NULL
;
5989 if (info
.target_desc
)
5991 /* Some useful properties can be inferred from the target. */
5992 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5994 tdep
->register_size_valid_p
= 1;
5995 tdep
->register_size
= 4;
5997 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5999 tdep
->register_size_valid_p
= 1;
6000 tdep
->register_size
= 8;
6004 /* Initially set everything according to the default ABI/ISA. */
6005 set_gdbarch_short_bit (gdbarch
, 16);
6006 set_gdbarch_int_bit (gdbarch
, 32);
6007 set_gdbarch_float_bit (gdbarch
, 32);
6008 set_gdbarch_double_bit (gdbarch
, 64);
6009 set_gdbarch_long_double_bit (gdbarch
, 64);
6010 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6011 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6012 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6014 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6015 mips_ax_pseudo_register_collect
);
6016 set_gdbarch_ax_pseudo_register_push_stack
6017 (gdbarch
, mips_ax_pseudo_register_push_stack
);
6019 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6020 mips_elf_make_msymbol_special
);
6022 /* Fill in the OS dependant register numbers and names. */
6024 const char **reg_names
;
6025 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
6026 struct mips_regnum
);
6027 if (tdesc_has_registers (info
.target_desc
))
6029 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6030 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6031 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6032 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6033 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6034 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6035 regnum
->fp_control_status
= 70;
6036 regnum
->fp_implementation_revision
= 71;
6037 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
6040 else if (info
.osabi
== GDB_OSABI_IRIX
)
6045 regnum
->badvaddr
= 66;
6048 regnum
->fp_control_status
= 69;
6049 regnum
->fp_implementation_revision
= 70;
6051 reg_names
= mips_irix_reg_names
;
6055 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6056 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6057 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6058 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6059 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6060 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6061 regnum
->fp_control_status
= 70;
6062 regnum
->fp_implementation_revision
= 71;
6064 if (info
.bfd_arch_info
!= NULL
6065 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6066 reg_names
= mips_tx39_reg_names
;
6068 reg_names
= mips_generic_reg_names
;
6070 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
6071 replaced by gdbarch_read_pc? */
6072 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6073 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6074 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6075 set_gdbarch_num_regs (gdbarch
, num_regs
);
6076 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6077 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6078 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
6079 tdep
->mips_processor_reg_names
= reg_names
;
6080 tdep
->regnum
= regnum
;
6086 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6087 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6088 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6089 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6090 tdep
->default_mask_address_p
= 0;
6091 set_gdbarch_long_bit (gdbarch
, 32);
6092 set_gdbarch_ptr_bit (gdbarch
, 32);
6093 set_gdbarch_long_long_bit (gdbarch
, 64);
6096 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6097 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6098 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6099 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6100 tdep
->default_mask_address_p
= 0;
6101 set_gdbarch_long_bit (gdbarch
, 32);
6102 set_gdbarch_ptr_bit (gdbarch
, 32);
6103 set_gdbarch_long_long_bit (gdbarch
, 64);
6105 case MIPS_ABI_EABI32
:
6106 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6107 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6108 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6109 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6110 tdep
->default_mask_address_p
= 0;
6111 set_gdbarch_long_bit (gdbarch
, 32);
6112 set_gdbarch_ptr_bit (gdbarch
, 32);
6113 set_gdbarch_long_long_bit (gdbarch
, 64);
6115 case MIPS_ABI_EABI64
:
6116 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6117 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6118 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6119 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6120 tdep
->default_mask_address_p
= 0;
6121 set_gdbarch_long_bit (gdbarch
, 64);
6122 set_gdbarch_ptr_bit (gdbarch
, 64);
6123 set_gdbarch_long_long_bit (gdbarch
, 64);
6126 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6127 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6128 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6129 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6130 tdep
->default_mask_address_p
= 0;
6131 set_gdbarch_long_bit (gdbarch
, 32);
6132 set_gdbarch_ptr_bit (gdbarch
, 32);
6133 set_gdbarch_long_long_bit (gdbarch
, 64);
6134 set_gdbarch_long_double_bit (gdbarch
, 128);
6135 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6138 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6139 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6140 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6141 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6142 tdep
->default_mask_address_p
= 0;
6143 set_gdbarch_long_bit (gdbarch
, 64);
6144 set_gdbarch_ptr_bit (gdbarch
, 64);
6145 set_gdbarch_long_long_bit (gdbarch
, 64);
6146 set_gdbarch_long_double_bit (gdbarch
, 128);
6147 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6150 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6153 /* GCC creates a pseudo-section whose name specifies the size of
6154 longs, since -mlong32 or -mlong64 may be used independent of
6155 other options. How those options affect pointer sizes is ABI and
6156 architecture dependent, so use them to override the default sizes
6157 set by the ABI. This table shows the relationship between ABI,
6158 -mlongXX, and size of pointers:
6160 ABI -mlongXX ptr bits
6161 --- -------- --------
6175 Note that for o32 and eabi32, pointers are always 32 bits
6176 regardless of any -mlongXX option. For all others, pointers and
6177 longs are the same, as set by -mlongXX or set by defaults. */
6179 if (info
.abfd
!= NULL
)
6183 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6186 set_gdbarch_long_bit (gdbarch
, long_bit
);
6190 case MIPS_ABI_EABI32
:
6195 case MIPS_ABI_EABI64
:
6196 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6199 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6204 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6205 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6208 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6209 flag in object files because to do so would make it impossible to
6210 link with libraries compiled without "-gp32". This is
6211 unnecessarily restrictive.
6213 We could solve this problem by adding "-gp32" multilibs to gcc,
6214 but to set this flag before gcc is built with such multilibs will
6215 break too many systems.''
6217 But even more unhelpfully, the default linker output target for
6218 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6219 for 64-bit programs - you need to change the ABI to change this,
6220 and not all gcc targets support that currently. Therefore using
6221 this flag to detect 32-bit mode would do the wrong thing given
6222 the current gcc - it would make GDB treat these 64-bit programs
6223 as 32-bit programs by default. */
6225 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6226 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6228 /* Add/remove bits from an address. The MIPS needs be careful to
6229 ensure that all 32 bit addresses are sign extended to 64 bits. */
6230 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6232 /* Unwind the frame. */
6233 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6234 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
6235 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
6237 /* Map debug register numbers onto internal register numbers. */
6238 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6239 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6240 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6241 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6242 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6243 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6245 /* MIPS version of CALL_DUMMY. */
6247 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6248 replaced by a command, and all targets will default to on stack
6249 (regardless of the stack's execute status). */
6250 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6251 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6253 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6254 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6255 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6257 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6258 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6260 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6262 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6264 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6265 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6266 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6268 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6270 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6272 if (mips_abi
== MIPS_ABI_N32
)
6273 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6274 else if (mips_abi
== MIPS_ABI_N64
)
6275 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6277 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6279 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6280 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6281 need to all be folded into the target vector. Since they are
6282 being used as guards for target_stopped_by_watchpoint, why not have
6283 target_stopped_by_watchpoint return the type of watchpoint that the code
6285 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6287 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6289 set_gdbarch_single_step_through_delay (gdbarch
,
6290 mips_single_step_through_delay
);
6292 /* Virtual tables. */
6293 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6295 mips_register_g_packet_guesses (gdbarch
);
6297 /* Hook in OS ABI-specific overrides, if they have been registered. */
6298 info
.tdep_info
= (void *) tdesc_data
;
6299 gdbarch_init_osabi (info
, gdbarch
);
6301 /* Unwind the frame. */
6302 dwarf2_append_unwinders (gdbarch
);
6303 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6304 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6305 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6306 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6307 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6308 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6309 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6313 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6314 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6316 /* Override the normal target description methods to handle our
6317 dual real and pseudo registers. */
6318 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6319 set_gdbarch_register_reggroup_p (gdbarch
,
6320 mips_tdesc_register_reggroup_p
);
6322 num_regs
= gdbarch_num_regs (gdbarch
);
6323 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6324 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6325 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6328 /* Add ABI-specific aliases for the registers. */
6329 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6330 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6331 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6332 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6334 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6335 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6336 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6338 /* Add some other standard aliases. */
6339 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6340 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6341 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6343 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6344 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6345 value_of_mips_user_reg
,
6346 &mips_numeric_register_aliases
[i
].regnum
);
6352 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6354 struct gdbarch_info info
;
6356 /* Force the architecture to update, and (if it's a MIPS architecture)
6357 mips_gdbarch_init will take care of the rest. */
6358 gdbarch_info_init (&info
);
6359 gdbarch_update_p (info
);
6362 /* Print out which MIPS ABI is in use. */
6365 show_mips_abi (struct ui_file
*file
,
6367 struct cmd_list_element
*ignored_cmd
,
6368 const char *ignored_value
)
6370 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6373 "The MIPS ABI is unknown because the current architecture "
6377 enum mips_abi global_abi
= global_mips_abi ();
6378 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6379 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6381 if (global_abi
== MIPS_ABI_UNKNOWN
)
6384 "The MIPS ABI is set automatically (currently \"%s\").\n",
6386 else if (global_abi
== actual_abi
)
6389 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6393 /* Probably shouldn't happen... */
6394 fprintf_filtered (file
,
6395 "The (auto detected) MIPS ABI \"%s\" is in use "
6396 "even though the user setting was \"%s\".\n",
6397 actual_abi_str
, mips_abi_strings
[global_abi
]);
6403 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6405 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6409 int ef_mips_32bitmode
;
6410 /* Determine the ISA. */
6411 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6429 /* Determine the size of a pointer. */
6430 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6431 fprintf_unfiltered (file
,
6432 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6434 fprintf_unfiltered (file
,
6435 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6437 fprintf_unfiltered (file
,
6438 "mips_dump_tdep: ef_mips_arch = %d\n",
6440 fprintf_unfiltered (file
,
6441 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6442 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6443 fprintf_unfiltered (file
,
6445 "mips_mask_address_p() %d (default %d)\n",
6446 mips_mask_address_p (tdep
),
6447 tdep
->default_mask_address_p
);
6449 fprintf_unfiltered (file
,
6450 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6451 MIPS_DEFAULT_FPU_TYPE
,
6452 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6453 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6454 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6456 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6457 MIPS_EABI (gdbarch
));
6458 fprintf_unfiltered (file
,
6459 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6460 MIPS_FPU_TYPE (gdbarch
),
6461 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6462 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6463 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6467 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6470 _initialize_mips_tdep (void)
6472 static struct cmd_list_element
*mipsfpulist
= NULL
;
6473 struct cmd_list_element
*c
;
6475 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6476 if (MIPS_ABI_LAST
+ 1
6477 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6478 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6480 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6482 mips_pdr_data
= register_objfile_data ();
6484 /* Create feature sets with the appropriate properties. The values
6485 are not important. */
6486 mips_tdesc_gp32
= allocate_target_description ();
6487 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6489 mips_tdesc_gp64
= allocate_target_description ();
6490 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6492 /* Add root prefix command for all "set mips"/"show mips" commands. */
6493 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6494 _("Various MIPS specific commands."),
6495 &setmipscmdlist
, "set mips ", 0, &setlist
);
6497 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6498 _("Various MIPS specific commands."),
6499 &showmipscmdlist
, "show mips ", 0, &showlist
);
6501 /* Allow the user to override the ABI. */
6502 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6503 &mips_abi_string
, _("\
6504 Set the MIPS ABI used by this program."), _("\
6505 Show the MIPS ABI used by this program."), _("\
6506 This option can be set to one of:\n\
6507 auto - the default ABI associated with the current binary\n\
6516 &setmipscmdlist
, &showmipscmdlist
);
6518 /* Let the user turn off floating point and set the fence post for
6519 heuristic_proc_start. */
6521 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6522 _("Set use of MIPS floating-point coprocessor."),
6523 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6524 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6525 _("Select single-precision MIPS floating-point coprocessor."),
6527 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6528 _("Select double-precision MIPS floating-point coprocessor."),
6530 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6531 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6532 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6533 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6534 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6535 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6536 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6537 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6538 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6539 _("Select MIPS floating-point coprocessor automatically."),
6541 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6542 _("Show current use of MIPS floating-point coprocessor target."),
6545 /* We really would like to have both "0" and "unlimited" work, but
6546 command.c doesn't deal with that. So make it a var_zinteger
6547 because the user can always use "999999" or some such for unlimited. */
6548 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6549 &heuristic_fence_post
, _("\
6550 Set the distance searched for the start of a function."), _("\
6551 Show the distance searched for the start of a function."), _("\
6552 If you are debugging a stripped executable, GDB needs to search through the\n\
6553 program for the start of a function. This command sets the distance of the\n\
6554 search. The only need to set it is when debugging a stripped executable."),
6555 reinit_frame_cache_sfunc
,
6556 NULL
, /* FIXME: i18n: The distance searched for
6557 the start of a function is %s. */
6558 &setlist
, &showlist
);
6560 /* Allow the user to control whether the upper bits of 64-bit
6561 addresses should be zeroed. */
6562 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6563 &mask_address_var
, _("\
6564 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6565 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6566 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
6567 allow GDB to determine the correct value."),
6568 NULL
, show_mask_address
,
6569 &setmipscmdlist
, &showmipscmdlist
);
6571 /* Allow the user to control the size of 32 bit registers within the
6572 raw remote packet. */
6573 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6574 &mips64_transfers_32bit_regs_p
, _("\
6575 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6577 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6579 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6580 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6581 64 bits for others. Use \"off\" to disable compatibility mode"),
6582 set_mips64_transfers_32bit_regs
,
6583 NULL
, /* FIXME: i18n: Compatibility with 64-bit
6584 MIPS target that transfers 32-bit
6585 quantities is %s. */
6586 &setlist
, &showlist
);
6588 /* Debug this files internals. */
6589 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6591 Set mips debugging."), _("\
6592 Show mips debugging."), _("\
6593 When non-zero, mips specific debugging is enabled."),
6595 NULL
, /* FIXME: i18n: Mips debugging is
6597 &setdebuglist
, &showdebuglist
);