1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 /* A useful bit in the CP0 status register (PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE
= 4,
72 MIPS_FPU_DOUBLE_REGSIZE
= 8
76 static const char *mips_abi_string
;
78 static const char *mips_abi_strings
[] = {
89 struct frame_extra_info
91 mips_extra_func_info_t proc_desc
;
95 /* Various MIPS ISA options (related to stack analysis) can be
96 overridden dynamically. Establish an enum/array for managing
99 static const char size_auto
[] = "auto";
100 static const char size_32
[] = "32";
101 static const char size_64
[] = "64";
103 static const char *size_enums
[] = {
110 /* Some MIPS boards don't support floating point while others only
111 support single-precision floating-point operations. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int default_mask_address_p
;
141 /* Is the target using 64-bit raw integer registers but only
142 storing a left-aligned 32-bit value in each? */
143 int mips64_transfers_32bit_regs_p
;
144 /* Indexes for various registers. IRIX and embedded have
145 different values. This contains the "public" fields. Don't
146 add any that do not need to be public. */
147 const struct mips_regnum
*regnum
;
148 /* Register names table for the current register set. */
149 const char **mips_processor_reg_names
;
153 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
159 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
160 They are implemented as a pair of 64bit doubles where the high
161 part holds the result of the operation rounded to double, and
162 the low double holds the difference between the exact result and
163 the rounded result. So "high" + "low" contains the result with
164 added precision. Unfortunately, the floatformat structure used
165 by GDB is not powerful enough to describe this format. As a temporary
166 measure, we define a 128bit floatformat that only uses the high part.
167 We lose a bit of precision but that's probably the best we can do
168 for now with the current infrastructure. */
170 static const struct floatformat floatformat_n32n64_long_double_big
=
172 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
173 floatformat_intbit_no
,
174 "floatformat_ieee_double_big",
175 n32n64_floatformat_always_valid
178 const struct mips_regnum
*
179 mips_regnum (struct gdbarch
*gdbarch
)
181 return gdbarch_tdep (gdbarch
)->regnum
;
185 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
187 return mips_regnum (gdbarch
)->fp0
+ 12;
190 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
191 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
193 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
195 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
197 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
199 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
200 functions to test, set, or clear bit 0 of addresses. */
203 is_mips16_addr (CORE_ADDR addr
)
209 make_mips16_addr (CORE_ADDR addr
)
215 unmake_mips16_addr (CORE_ADDR addr
)
217 return ((addr
) & ~1);
220 /* Return the contents of register REGNUM as a signed integer. */
223 read_signed_register (int regnum
)
225 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
226 deprecated_read_register_gen (regnum
, buf
);
227 return (extract_signed_integer
228 (buf
, register_size (current_gdbarch
, regnum
)));
232 read_signed_register_pid (int regnum
, ptid_t ptid
)
237 if (ptid_equal (ptid
, inferior_ptid
))
238 return read_signed_register (regnum
);
240 save_ptid
= inferior_ptid
;
242 inferior_ptid
= ptid
;
244 retval
= read_signed_register (regnum
);
246 inferior_ptid
= save_ptid
;
251 /* Return the MIPS ABI associated with GDBARCH. */
253 mips_abi (struct gdbarch
*gdbarch
)
255 return gdbarch_tdep (gdbarch
)->mips_abi
;
259 mips_isa_regsize (struct gdbarch
*gdbarch
)
261 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
262 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
265 /* Return the currently configured (or set) saved register size. */
267 static const char *mips_abi_regsize_string
= size_auto
;
270 mips_abi_regsize (struct gdbarch
*gdbarch
)
272 if (mips_abi_regsize_string
== size_auto
)
273 switch (mips_abi (gdbarch
))
275 case MIPS_ABI_EABI32
:
281 case MIPS_ABI_EABI64
:
283 case MIPS_ABI_UNKNOWN
:
286 internal_error (__FILE__
, __LINE__
, "bad switch");
288 else if (mips_abi_regsize_string
== size_64
)
290 else /* if (mips_abi_regsize_string == size_32) */
294 /* Functions for setting and testing a bit in a minimal symbol that
295 marks it as 16-bit function. The MSB of the minimal symbol's
296 "info" field is used for this purpose.
298 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
299 i.e. refers to a 16-bit function, and sets a "special" bit in a
300 minimal symbol to mark it as a 16-bit function
302 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
305 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
307 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
309 MSYMBOL_INFO (msym
) = (char *)
310 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
311 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
316 msymbol_is_special (struct minimal_symbol
*msym
)
318 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
321 /* XFER a value from the big/little/left end of the register.
322 Depending on the size of the value it might occupy the entire
323 register or just part of it. Make an allowance for this, aligning
324 things accordingly. */
327 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
328 enum bfd_endian endian
, bfd_byte
* in
,
329 const bfd_byte
* out
, int buf_offset
)
332 gdb_assert (reg_num
>= NUM_REGS
);
333 /* Need to transfer the left or right part of the register, based on
334 the targets byte order. */
338 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
340 case BFD_ENDIAN_LITTLE
:
343 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
347 internal_error (__FILE__
, __LINE__
, "bad switch");
350 fprintf_unfiltered (gdb_stderr
,
351 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
352 reg_num
, reg_offset
, buf_offset
, length
);
353 if (mips_debug
&& out
!= NULL
)
356 fprintf_unfiltered (gdb_stdlog
, "out ");
357 for (i
= 0; i
< length
; i
++)
358 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
361 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
364 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
366 if (mips_debug
&& in
!= NULL
)
369 fprintf_unfiltered (gdb_stdlog
, "in ");
370 for (i
= 0; i
< length
; i
++)
371 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
374 fprintf_unfiltered (gdb_stdlog
, "\n");
377 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
378 compatiblity mode. A return value of 1 means that we have
379 physical 64-bit registers, but should treat them as 32-bit registers. */
382 mips2_fp_compat (void)
384 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
386 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
391 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
392 in all the places we deal with FP registers. PR gdb/413. */
393 /* Otherwise check the FR bit in the status register - it controls
394 the FP compatiblity mode. If it is clear we are in compatibility
396 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
403 /* The amount of space reserved on the stack for registers. This is
404 different to MIPS_ABI_REGSIZE as it determines the alignment of
405 data allocated after the registers have run out. */
407 static const char *mips_stack_argsize_string
= size_auto
;
410 mips_stack_argsize (struct gdbarch
*gdbarch
)
412 if (mips_stack_argsize_string
== size_auto
)
413 return mips_abi_regsize (gdbarch
);
414 else if (mips_stack_argsize_string
== size_64
)
416 else /* if (mips_stack_argsize_string == size_32) */
420 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
422 struct mips_frame_cache
;
423 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
425 struct mips_frame_cache
*);
426 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
429 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
431 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
433 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
435 static CORE_ADDR
after_prologue (CORE_ADDR pc
);
437 static struct type
*mips_float_register_type (void);
438 static struct type
*mips_double_register_type (void);
440 /* The list of available "set mips " and "show mips " commands */
442 static struct cmd_list_element
*setmipscmdlist
= NULL
;
443 static struct cmd_list_element
*showmipscmdlist
= NULL
;
445 /* Integer registers 0 thru 31 are handled explicitly by
446 mips_register_name(). Processor specific registers 32 and above
447 are listed in the followign tables. */
450 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
454 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
455 "sr", "lo", "hi", "bad", "cause", "pc",
456 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
457 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
458 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
459 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
460 "fsr", "fir", "" /*"fp" */ , "",
461 "", "", "", "", "", "", "", "",
462 "", "", "", "", "", "", "", "",
465 /* Names of IDT R3041 registers. */
467 static const char *mips_r3041_reg_names
[] = {
468 "sr", "lo", "hi", "bad", "cause", "pc",
469 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
470 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
471 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
472 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
473 "fsr", "fir", "", /*"fp" */ "",
474 "", "", "bus", "ccfg", "", "", "", "",
475 "", "", "port", "cmp", "", "", "epc", "prid",
478 /* Names of tx39 registers. */
480 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
481 "sr", "lo", "hi", "bad", "cause", "pc",
482 "", "", "", "", "", "", "", "",
483 "", "", "", "", "", "", "", "",
484 "", "", "", "", "", "", "", "",
485 "", "", "", "", "", "", "", "",
487 "", "", "", "", "", "", "", "",
488 "", "", "config", "cache", "debug", "depc", "epc", ""
491 /* Names of IRIX registers. */
492 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
493 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
494 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
495 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
496 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
497 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
501 /* Return the name of the register corresponding to REGNO. */
503 mips_register_name (int regno
)
505 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
506 /* GPR names for all ABIs other than n32/n64. */
507 static char *mips_gpr_names
[] = {
508 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
509 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
510 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
511 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
514 /* GPR names for n32 and n64 ABIs. */
515 static char *mips_n32_n64_gpr_names
[] = {
516 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
517 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
518 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
519 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
522 enum mips_abi abi
= mips_abi (current_gdbarch
);
524 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
525 don't make the raw register names visible. */
526 int rawnum
= regno
% NUM_REGS
;
527 if (regno
< NUM_REGS
)
530 /* The MIPS integer registers are always mapped from 0 to 31. The
531 names of the registers (which reflects the conventions regarding
532 register use) vary depending on the ABI. */
533 if (0 <= rawnum
&& rawnum
< 32)
535 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
536 return mips_n32_n64_gpr_names
[rawnum
];
538 return mips_gpr_names
[rawnum
];
540 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
542 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
543 return tdep
->mips_processor_reg_names
[rawnum
- 32];
546 internal_error (__FILE__
, __LINE__
,
547 "mips_register_name: bad register number %d", rawnum
);
550 /* Return the groups that a MIPS register can be categorised into. */
553 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
554 struct reggroup
*reggroup
)
559 int rawnum
= regnum
% NUM_REGS
;
560 int pseudo
= regnum
/ NUM_REGS
;
561 if (reggroup
== all_reggroup
)
563 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
564 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
565 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
566 (gdbarch), as not all architectures are multi-arch. */
567 raw_p
= rawnum
< NUM_REGS
;
568 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
570 if (reggroup
== float_reggroup
)
571 return float_p
&& pseudo
;
572 if (reggroup
== vector_reggroup
)
573 return vector_p
&& pseudo
;
574 if (reggroup
== general_reggroup
)
575 return (!vector_p
&& !float_p
) && pseudo
;
576 /* Save the pseudo registers. Need to make certain that any code
577 extracting register values from a saved register cache also uses
579 if (reggroup
== save_reggroup
)
580 return raw_p
&& pseudo
;
581 /* Restore the same pseudo register. */
582 if (reggroup
== restore_reggroup
)
583 return raw_p
&& pseudo
;
587 /* Map the symbol table registers which live in the range [1 *
588 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
589 registers. Take care of alignment and size problems. */
592 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
593 int cookednum
, void *buf
)
595 int rawnum
= cookednum
% NUM_REGS
;
596 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
597 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
598 regcache_raw_read (regcache
, rawnum
, buf
);
599 else if (register_size (gdbarch
, rawnum
) >
600 register_size (gdbarch
, cookednum
))
602 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
603 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
604 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
606 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
609 internal_error (__FILE__
, __LINE__
, "bad register size");
613 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
614 struct regcache
*regcache
, int cookednum
,
617 int rawnum
= cookednum
% NUM_REGS
;
618 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
619 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
620 regcache_raw_write (regcache
, rawnum
, buf
);
621 else if (register_size (gdbarch
, rawnum
) >
622 register_size (gdbarch
, cookednum
))
624 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
625 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
626 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
628 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
631 internal_error (__FILE__
, __LINE__
, "bad register size");
634 /* Table to translate MIPS16 register field to actual register number. */
635 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
637 /* Heuristic_proc_start may hunt through the text section for a long
638 time across a 2400 baud serial line. Allows the user to limit this
641 static unsigned int heuristic_fence_post
= 0;
643 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
644 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
645 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
646 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
647 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
648 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
649 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
650 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
651 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
652 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
653 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
654 this will corrupt pdr.iline. Fortunately we don't use it. */
655 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
656 #define _PROC_MAGIC_ 0x0F0F0F0F
658 /* Number of bytes of storage in the actual machine representation for
659 register N. NOTE: This defines the pseudo register type so need to
660 rebuild the architecture vector. */
662 static int mips64_transfers_32bit_regs_p
= 0;
665 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
666 struct cmd_list_element
*c
)
668 struct gdbarch_info info
;
669 gdbarch_info_init (&info
);
670 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
671 instead of relying on globals. Doing that would let generic code
672 handle the search for this specific architecture. */
673 if (!gdbarch_update_p (info
))
675 mips64_transfers_32bit_regs_p
= 0;
676 error ("32-bit compatibility mode not supported");
680 /* Convert to/from a register and the corresponding memory value. */
683 mips_convert_register_p (int regnum
, struct type
*type
)
685 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
686 && register_size (current_gdbarch
, regnum
) == 4
687 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
688 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
689 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
693 mips_register_to_value (struct frame_info
*frame
, int regnum
,
694 struct type
*type
, void *to
)
696 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
697 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
701 mips_value_to_register (struct frame_info
*frame
, int regnum
,
702 struct type
*type
, const void *from
)
704 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
705 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
708 /* Return the GDB type object for the "standard" data type of data in
712 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
714 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
715 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
716 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
718 /* The floating-point registers raw, or cooked, always match
719 mips_isa_regsize(), and also map 1:1, byte for byte. */
720 switch (gdbarch_byte_order (gdbarch
))
723 if (mips_isa_regsize (gdbarch
) == 4)
724 return builtin_type_ieee_single_big
;
726 return builtin_type_ieee_double_big
;
727 case BFD_ENDIAN_LITTLE
:
728 if (mips_isa_regsize (gdbarch
) == 4)
729 return builtin_type_ieee_single_little
;
731 return builtin_type_ieee_double_little
;
732 case BFD_ENDIAN_UNKNOWN
:
734 internal_error (__FILE__
, __LINE__
, "bad switch");
737 else if (regnum
< NUM_REGS
)
739 /* The raw or ISA registers. These are all sized according to
741 if (mips_isa_regsize (gdbarch
) == 4)
742 return builtin_type_int32
;
744 return builtin_type_int64
;
748 /* The cooked or ABI registers. These are sized according to
749 the ABI (with a few complications). */
750 if (regnum
>= (NUM_REGS
751 + mips_regnum (current_gdbarch
)->fp_control_status
)
752 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
753 /* The pseudo/cooked view of the embedded registers is always
754 32-bit. The raw view is handled below. */
755 return builtin_type_int32
;
756 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
757 /* The target, while possibly using a 64-bit register buffer,
758 is only transfering 32-bits of each integer register.
759 Reflect this in the cooked/pseudo (ABI) register value. */
760 return builtin_type_int32
;
761 else if (mips_abi_regsize (gdbarch
) == 4)
762 /* The ABI is restricted to 32-bit registers (the ISA could be
764 return builtin_type_int32
;
767 return builtin_type_int64
;
771 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
776 return read_signed_register (MIPS_SP_REGNUM
);
779 /* Should the upper word of 64-bit addresses be zeroed? */
780 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
783 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
785 switch (mask_address_var
)
787 case AUTO_BOOLEAN_TRUE
:
789 case AUTO_BOOLEAN_FALSE
:
792 case AUTO_BOOLEAN_AUTO
:
793 return tdep
->default_mask_address_p
;
795 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
801 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
803 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
804 switch (mask_address_var
)
806 case AUTO_BOOLEAN_TRUE
:
807 printf_filtered ("The 32 bit mips address mask is enabled\n");
809 case AUTO_BOOLEAN_FALSE
:
810 printf_filtered ("The 32 bit mips address mask is disabled\n");
812 case AUTO_BOOLEAN_AUTO
:
814 ("The 32 bit address mask is set automatically. Currently %s\n",
815 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
818 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
823 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
826 pc_is_mips16 (bfd_vma memaddr
)
828 struct minimal_symbol
*sym
;
830 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
831 if (is_mips16_addr (memaddr
))
834 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
835 the high bit of the info field. Use this to decide if the function is
836 MIPS16 or normal MIPS. */
837 sym
= lookup_minimal_symbol_by_pc (memaddr
);
839 return msymbol_is_special (sym
);
844 /* MIPS believes that the PC has a sign extended value. Perhaps the
845 all registers should be sign extended for simplicity? */
848 mips_read_pc (ptid_t ptid
)
850 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
854 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
856 return frame_unwind_register_signed (next_frame
,
857 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
860 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
861 dummy frame. The frame ID's base needs to match the TOS value
862 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
865 static struct frame_id
866 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
868 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
869 frame_pc_unwind (next_frame
));
873 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
875 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
878 /* This returns the PC of the first inst after the prologue. If we can't
879 find the prologue, then return 0. */
882 after_prologue (CORE_ADDR pc
)
884 mips_extra_func_info_t proc_desc
;
885 struct symtab_and_line sal
;
886 CORE_ADDR func_addr
, func_end
;
887 CORE_ADDR startaddr
= 0;
889 /* Pass a NULL next_frame to heuristic_proc_desc. We should not
890 attempt to read the stack pointer from the current machine state,
891 because the current machine state has nothing to do with the
892 information we need from the proc_desc; and the process may or
893 may not exist right now. */
894 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
897 /* IF this is the topmost frame AND (this proc does not have
898 debugging information OR the PC is in the procedure prologue)
899 THEN create a "heuristic" proc_desc (by analyzing the actual
900 code) to replace the "official" proc_desc. */
901 struct symtab_and_line val
;
902 if (PROC_SYMBOL (proc_desc
))
904 val
= find_pc_line (BLOCK_START
905 (SYMBOL_BLOCK_VALUE (PROC_SYMBOL (proc_desc
))),
907 val
.pc
= val
.end
? val
.end
: pc
;
909 if (!PROC_SYMBOL (proc_desc
) || pc
< val
.pc
)
911 mips_extra_func_info_t found_heuristic
=
912 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
), pc
, NULL
, NULL
);
914 proc_desc
= found_heuristic
;
920 startaddr
= heuristic_proc_start (pc
);
922 proc_desc
= heuristic_proc_desc (startaddr
, pc
, NULL
, NULL
);
927 /* If function is frameless, then we need to do it the hard way. I
928 strongly suspect that frameless always means prologueless... */
929 if (PROC_FRAME_REG (proc_desc
) == MIPS_SP_REGNUM
930 && PROC_FRAME_OFFSET (proc_desc
) == 0)
934 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
935 return 0; /* Unknown */
937 sal
= find_pc_line (func_addr
, 0);
939 if (sal
.end
< func_end
)
942 /* The line after the prologue is after the end of the function. In this
943 case, tell the caller to find the prologue the hard way. */
948 /* Decode a MIPS32 instruction that saves a register in the stack, and
949 set the appropriate bit in the general register mask or float register mask
950 to indicate which register is saved. This is a helper function
951 for mips_find_saved_regs. */
954 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
955 unsigned long *float_mask
)
959 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
960 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
961 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
963 /* It might be possible to use the instruction to
964 find the offset, rather than the code below which
965 is based on things being in a certain order in the
966 frame, but figuring out what the instruction's offset
967 is relative to might be a little tricky. */
968 reg
= (inst
& 0x001f0000) >> 16;
969 *gen_mask
|= (1 << reg
);
971 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
972 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
973 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
976 reg
= ((inst
& 0x001f0000) >> 16);
977 *float_mask
|= (1 << reg
);
981 /* Decode a MIPS16 instruction that saves a register in the stack, and
982 set the appropriate bit in the general register or float register mask
983 to indicate which register is saved. This is a helper function
984 for mips_find_saved_regs. */
987 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
989 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
991 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
992 *gen_mask
|= (1 << reg
);
994 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
996 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
997 *gen_mask
|= (1 << reg
);
999 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
1000 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1001 *gen_mask
|= (1 << RA_REGNUM
);
1005 /* Fetch and return instruction from the specified location. If the PC
1006 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1009 mips_fetch_instruction (CORE_ADDR addr
)
1011 char buf
[MIPS_INSTLEN
];
1015 if (pc_is_mips16 (addr
))
1017 instlen
= MIPS16_INSTLEN
;
1018 addr
= unmake_mips16_addr (addr
);
1021 instlen
= MIPS_INSTLEN
;
1022 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1024 memory_error (status
, addr
);
1025 return extract_unsigned_integer (buf
, instlen
);
1029 mips16_fetch_instruction (CORE_ADDR addr
)
1031 char buf
[MIPS_INSTLEN
];
1035 instlen
= MIPS16_INSTLEN
;
1036 addr
= unmake_mips16_addr (addr
);
1037 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1039 memory_error (status
, addr
);
1040 return extract_unsigned_integer (buf
, instlen
);
1044 mips32_fetch_instruction (CORE_ADDR addr
)
1046 char buf
[MIPS_INSTLEN
];
1049 instlen
= MIPS_INSTLEN
;
1050 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1052 memory_error (status
, addr
);
1053 return extract_unsigned_integer (buf
, instlen
);
1057 /* These the fields of 32 bit mips instructions */
1058 #define mips32_op(x) (x >> 26)
1059 #define itype_op(x) (x >> 26)
1060 #define itype_rs(x) ((x >> 21) & 0x1f)
1061 #define itype_rt(x) ((x >> 16) & 0x1f)
1062 #define itype_immediate(x) (x & 0xffff)
1064 #define jtype_op(x) (x >> 26)
1065 #define jtype_target(x) (x & 0x03ffffff)
1067 #define rtype_op(x) (x >> 26)
1068 #define rtype_rs(x) ((x >> 21) & 0x1f)
1069 #define rtype_rt(x) ((x >> 16) & 0x1f)
1070 #define rtype_rd(x) ((x >> 11) & 0x1f)
1071 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1072 #define rtype_funct(x) (x & 0x3f)
1075 mips32_relative_offset (unsigned long inst
)
1078 x
= itype_immediate (inst
);
1079 if (x
& 0x8000) /* sign bit set */
1081 x
|= 0xffff0000; /* sign extension */
1087 /* Determine whate to set a single step breakpoint while considering
1088 branch prediction */
1090 mips32_next_pc (CORE_ADDR pc
)
1094 inst
= mips_fetch_instruction (pc
);
1095 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1097 if (itype_op (inst
) >> 2 == 5)
1098 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1100 op
= (itype_op (inst
) & 0x03);
1110 goto greater_branch
;
1115 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1116 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1118 int tf
= itype_rt (inst
) & 0x01;
1119 int cnum
= itype_rt (inst
) >> 2;
1121 read_signed_register (mips_regnum (current_gdbarch
)->
1123 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1125 if (((cond
>> cnum
) & 0x01) == tf
)
1126 pc
+= mips32_relative_offset (inst
) + 4;
1131 pc
+= 4; /* Not a branch, next instruction is easy */
1134 { /* This gets way messy */
1136 /* Further subdivide into SPECIAL, REGIMM and other */
1137 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1139 case 0: /* SPECIAL */
1140 op
= rtype_funct (inst
);
1145 /* Set PC to that address */
1146 pc
= read_signed_register (rtype_rs (inst
));
1152 break; /* end SPECIAL */
1153 case 1: /* REGIMM */
1155 op
= itype_rt (inst
); /* branch condition */
1160 case 16: /* BLTZAL */
1161 case 18: /* BLTZALL */
1163 if (read_signed_register (itype_rs (inst
)) < 0)
1164 pc
+= mips32_relative_offset (inst
) + 4;
1166 pc
+= 8; /* after the delay slot */
1170 case 17: /* BGEZAL */
1171 case 19: /* BGEZALL */
1172 if (read_signed_register (itype_rs (inst
)) >= 0)
1173 pc
+= mips32_relative_offset (inst
) + 4;
1175 pc
+= 8; /* after the delay slot */
1177 /* All of the other instructions in the REGIMM category */
1182 break; /* end REGIMM */
1187 reg
= jtype_target (inst
) << 2;
1188 /* Upper four bits get never changed... */
1189 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1192 /* FIXME case JALX : */
1195 reg
= jtype_target (inst
) << 2;
1196 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1197 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1199 break; /* The new PC will be alternate mode */
1200 case 4: /* BEQ, BEQL */
1202 if (read_signed_register (itype_rs (inst
)) ==
1203 read_signed_register (itype_rt (inst
)))
1204 pc
+= mips32_relative_offset (inst
) + 4;
1208 case 5: /* BNE, BNEL */
1210 if (read_signed_register (itype_rs (inst
)) !=
1211 read_signed_register (itype_rt (inst
)))
1212 pc
+= mips32_relative_offset (inst
) + 4;
1216 case 6: /* BLEZ, BLEZL */
1217 if (read_signed_register (itype_rs (inst
) <= 0))
1218 pc
+= mips32_relative_offset (inst
) + 4;
1224 greater_branch
: /* BGTZ, BGTZL */
1225 if (read_signed_register (itype_rs (inst
) > 0))
1226 pc
+= mips32_relative_offset (inst
) + 4;
1233 } /* mips32_next_pc */
1235 /* Decoding the next place to set a breakpoint is irregular for the
1236 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1237 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1238 We dont want to set a single step instruction on the extend instruction
1242 /* Lots of mips16 instruction formats */
1243 /* Predicting jumps requires itype,ritype,i8type
1244 and their extensions extItype,extritype,extI8type
1246 enum mips16_inst_fmts
1248 itype
, /* 0 immediate 5,10 */
1249 ritype
, /* 1 5,3,8 */
1250 rrtype
, /* 2 5,3,3,5 */
1251 rritype
, /* 3 5,3,3,5 */
1252 rrrtype
, /* 4 5,3,3,3,2 */
1253 rriatype
, /* 5 5,3,3,1,4 */
1254 shifttype
, /* 6 5,3,3,3,2 */
1255 i8type
, /* 7 5,3,8 */
1256 i8movtype
, /* 8 5,3,3,5 */
1257 i8mov32rtype
, /* 9 5,3,5,3 */
1258 i64type
, /* 10 5,3,8 */
1259 ri64type
, /* 11 5,3,3,5 */
1260 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1261 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1262 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1263 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1264 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1265 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1266 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1267 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1268 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1269 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1271 /* I am heaping all the fields of the formats into one structure and
1272 then, only the fields which are involved in instruction extension */
1276 unsigned int regx
; /* Function in i8 type */
1281 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1282 for the bits which make up the immediatate extension. */
1285 extended_offset (unsigned int extension
)
1288 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1290 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1292 value
|= extension
& 0x01f; /* extract 4:0 */
1296 /* Only call this function if you know that this is an extendable
1297 instruction, It wont malfunction, but why make excess remote memory references?
1298 If the immediate operands get sign extended or somthing, do it after
1299 the extension is performed.
1301 /* FIXME: Every one of these cases needs to worry about sign extension
1302 when the offset is to be used in relative addressing */
1306 fetch_mips_16 (CORE_ADDR pc
)
1309 pc
&= 0xfffffffe; /* clear the low order bit */
1310 target_read_memory (pc
, buf
, 2);
1311 return extract_unsigned_integer (buf
, 2);
1315 unpack_mips16 (CORE_ADDR pc
,
1316 unsigned int extension
,
1318 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1323 switch (insn_format
)
1330 value
= extended_offset (extension
);
1331 value
= value
<< 11; /* rom for the original value */
1332 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1336 value
= inst
& 0x7ff;
1337 /* FIXME : Consider sign extension */
1346 { /* A register identifier and an offset */
1347 /* Most of the fields are the same as I type but the
1348 immediate value is of a different length */
1352 value
= extended_offset (extension
);
1353 value
= value
<< 8; /* from the original instruction */
1354 value
|= inst
& 0xff; /* eleven bits from instruction */
1355 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1356 if (value
& 0x4000) /* test the sign bit , bit 26 */
1358 value
&= ~0x3fff; /* remove the sign bit */
1364 value
= inst
& 0xff; /* 8 bits */
1365 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1366 /* FIXME: Do sign extension , this format needs it */
1367 if (value
& 0x80) /* THIS CONFUSES ME */
1369 value
&= 0xef; /* remove the sign bit */
1379 unsigned long value
;
1380 unsigned int nexthalf
;
1381 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1382 value
= value
<< 16;
1383 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1391 internal_error (__FILE__
, __LINE__
, "bad switch");
1393 upk
->offset
= offset
;
1400 add_offset_16 (CORE_ADDR pc
, int offset
)
1402 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1406 extended_mips16_next_pc (CORE_ADDR pc
,
1407 unsigned int extension
, unsigned int insn
)
1409 int op
= (insn
>> 11);
1412 case 2: /* Branch */
1415 struct upk_mips16 upk
;
1416 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1417 offset
= upk
.offset
;
1423 pc
+= (offset
<< 1) + 2;
1426 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1428 struct upk_mips16 upk
;
1429 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1430 pc
= add_offset_16 (pc
, upk
.offset
);
1431 if ((insn
>> 10) & 0x01) /* Exchange mode */
1432 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1439 struct upk_mips16 upk
;
1441 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1442 reg
= read_signed_register (upk
.regx
);
1444 pc
+= (upk
.offset
<< 1) + 2;
1451 struct upk_mips16 upk
;
1453 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1454 reg
= read_signed_register (upk
.regx
);
1456 pc
+= (upk
.offset
<< 1) + 2;
1461 case 12: /* I8 Formats btez btnez */
1463 struct upk_mips16 upk
;
1465 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1466 /* upk.regx contains the opcode */
1467 reg
= read_signed_register (24); /* Test register is 24 */
1468 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1469 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1470 /* pc = add_offset_16(pc,upk.offset) ; */
1471 pc
+= (upk
.offset
<< 1) + 2;
1476 case 29: /* RR Formats JR, JALR, JALR-RA */
1478 struct upk_mips16 upk
;
1479 /* upk.fmt = rrtype; */
1484 upk
.regx
= (insn
>> 8) & 0x07;
1485 upk
.regy
= (insn
>> 5) & 0x07;
1493 break; /* Function return instruction */
1499 break; /* BOGUS Guess */
1501 pc
= read_signed_register (reg
);
1508 /* This is an instruction extension. Fetch the real instruction
1509 (which follows the extension) and decode things based on
1513 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1526 mips16_next_pc (CORE_ADDR pc
)
1528 unsigned int insn
= fetch_mips_16 (pc
);
1529 return extended_mips16_next_pc (pc
, 0, insn
);
1532 /* The mips_next_pc function supports single_step when the remote
1533 target monitor or stub is not developed enough to do a single_step.
1534 It works by decoding the current instruction and predicting where a
1535 branch will go. This isnt hard because all the data is available.
1536 The MIPS32 and MIPS16 variants are quite different */
1538 mips_next_pc (CORE_ADDR pc
)
1541 return mips16_next_pc (pc
);
1543 return mips32_next_pc (pc
);
1546 struct mips_frame_cache
1549 struct trad_frame_saved_reg
*saved_regs
;
1553 static struct mips_frame_cache
*
1554 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1556 CORE_ADDR startaddr
= 0;
1557 mips_extra_func_info_t proc_desc
;
1558 struct mips_frame_cache
*cache
;
1559 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1560 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1561 /* r0 bit means kernel trap */
1563 /* What registers have been saved? Bitmasks. */
1564 unsigned long gen_mask
, float_mask
;
1566 if ((*this_cache
) != NULL
)
1567 return (*this_cache
);
1568 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1569 (*this_cache
) = cache
;
1570 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1572 /* Get the mdebug proc descriptor. */
1573 proc_desc
= non_heuristic_proc_desc (frame_pc_unwind (next_frame
),
1575 /* Must be true. This is only called when the sniffer detected a
1577 gdb_assert (proc_desc
!= NULL
);
1579 /* Extract the frame's base. */
1580 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1581 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1583 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1584 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1585 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1587 /* Must be true. The in_prologue case is left for the heuristic
1588 unwinder. This is always used on kernel traps. */
1589 gdb_assert (!in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1592 /* Fill in the offsets for the registers which gen_mask says were
1595 CORE_ADDR reg_position
= (cache
->base
+ PROC_REG_OFFSET (proc_desc
));
1598 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1599 if (gen_mask
& 0x80000000)
1601 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1602 reg_position
-= mips_abi_regsize (gdbarch
);
1606 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1607 order of that normally used by gcc. Therefore, we have to fetch
1608 the first instruction of the function, and if it's an entry
1609 instruction that saves $s0 or $s1, correct their saved addresses. */
1610 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1612 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1613 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1617 int sreg_count
= (inst
>> 6) & 3;
1619 /* Check if the ra register was pushed on the stack. */
1620 CORE_ADDR reg_position
= (cache
->base
1621 + PROC_REG_OFFSET (proc_desc
));
1623 reg_position
-= mips_abi_regsize (gdbarch
);
1625 /* Check if the s0 and s1 registers were pushed on the
1627 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1629 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1631 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1632 reg_position
-= mips_abi_regsize (gdbarch
);
1637 /* Fill in the offsets for the registers which float_mask says were
1640 CORE_ADDR reg_position
= (cache
->base
1641 + PROC_FREG_OFFSET (proc_desc
));
1643 /* Fill in the offsets for the float registers which float_mask
1645 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1646 if (float_mask
& 0x80000000)
1648 if (mips_abi_regsize (gdbarch
) == 4
1649 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1651 /* On a big endian 32 bit ABI, floating point registers
1652 are paired to form doubles such that the most
1653 significant part is in $f[N+1] and the least
1654 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1655 registers are also spilled as a pair and stored as a
1658 When little-endian the least significant part is
1659 stored first leading to the memory order $f[N] and
1662 Unfortunately, when big-endian the most significant
1663 part of the double is stored first, and the least
1664 significant is stored second. This leads to the
1665 registers being ordered in memory as firt $f[N+1] and
1668 For the big-endian case make certain that the
1669 addresses point at the correct (swapped) locations
1670 $f[N] and $f[N+1] pair (keep in mind that
1671 reg_position is decremented each time through the
1674 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1675 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1677 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1678 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1681 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1682 .addr
= reg_position
;
1683 reg_position
-= mips_abi_regsize (gdbarch
);
1686 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1687 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1690 /* SP_REGNUM, contains the value and not the address. */
1691 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1693 return (*this_cache
);
1697 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1698 struct frame_id
*this_id
)
1700 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1702 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1706 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1708 int regnum
, int *optimizedp
,
1709 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1710 int *realnump
, void *valuep
)
1712 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1714 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1715 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1718 static const struct frame_unwind mips_mdebug_frame_unwind
=
1721 mips_mdebug_frame_this_id
,
1722 mips_mdebug_frame_prev_register
1725 static const struct frame_unwind
*
1726 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1728 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1729 CORE_ADDR startaddr
= 0;
1730 mips_extra_func_info_t proc_desc
;
1733 /* Only use the mdebug frame unwinder on mdebug frames where all the
1734 registers have been saved. Leave hard cases such as no mdebug or
1735 in prologue for the heuristic unwinders. */
1737 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1738 if (proc_desc
== NULL
)
1741 /* Not sure exactly what kernel_trap means, but if it means the
1742 kernel saves the registers without a prologue doing it, we better
1743 not examine the prologue to see whether registers have been saved
1745 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1747 return &mips_mdebug_frame_unwind
;
1749 /* In any frame other than the innermost or a frame interrupted by a
1750 signal, we assume that all registers have been saved. This
1751 assumes that all register saves in a function happen before the
1752 first function call. */
1753 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1754 return &mips_mdebug_frame_unwind
;
1760 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1763 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1768 static const struct frame_base mips_mdebug_frame_base
= {
1769 &mips_mdebug_frame_unwind
,
1770 mips_mdebug_frame_base_address
,
1771 mips_mdebug_frame_base_address
,
1772 mips_mdebug_frame_base_address
1775 static const struct frame_base
*
1776 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1778 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1779 return &mips_mdebug_frame_base
;
1784 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1785 Procedures that use the 32-bit instruction set are handled by the
1786 mips_insn32 unwinder. */
1788 static struct mips_frame_cache
*
1789 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1791 mips_extra_func_info_t proc_desc
;
1792 struct mips_frame_cache
*cache
;
1793 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1794 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1795 /* r0 bit means kernel trap */
1797 /* What registers have been saved? Bitmasks. */
1798 unsigned long gen_mask
, float_mask
;
1800 if ((*this_cache
) != NULL
)
1801 return (*this_cache
);
1802 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1803 (*this_cache
) = cache
;
1804 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1806 /* Synthesize a proc descriptor. */
1808 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1809 CORE_ADDR start_addr
;
1811 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1812 if (start_addr
== 0)
1813 start_addr
= heuristic_proc_start (pc
);
1816 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, *this_cache
);
1818 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, NULL
);
1822 /* Extract the frame's base. */
1823 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1824 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1826 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1827 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1828 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1830 /* In any frame other than the innermost or a frame interrupted by a
1831 signal, we assume that all registers have been saved. This
1832 assumes that all register saves in a function happen before the
1833 first function call. */
1834 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1835 /* Not sure exactly what kernel_trap means, but if it means the
1836 kernel saves the registers without a prologue doing it, we
1837 better not examine the prologue to see whether registers
1838 have been saved yet. */
1841 /* We need to figure out whether the registers that the
1842 proc_desc claims are saved have been saved yet. */
1846 /* Bitmasks; set if we have found a save for the register. */
1847 unsigned long gen_save_found
= 0;
1848 unsigned long float_save_found
= 0;
1851 /* If the address is odd, assume this is MIPS16 code. */
1852 addr
= PROC_LOW_ADDR (proc_desc
);
1853 mips16
= pc_is_mips16 (addr
);
1855 /* Scan through this function's instructions preceding the
1856 current PC, and look for those that save registers. */
1857 while (addr
< frame_pc_unwind (next_frame
))
1861 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1863 addr
+= MIPS16_INSTLEN
;
1867 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1868 &gen_save_found
, &float_save_found
);
1869 addr
+= MIPS_INSTLEN
;
1872 gen_mask
= gen_save_found
;
1873 float_mask
= float_save_found
;
1876 /* Fill in the offsets for the registers which gen_mask says were
1879 CORE_ADDR reg_position
= (cache
->base
1880 + PROC_REG_OFFSET (proc_desc
));
1882 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1883 if (gen_mask
& 0x80000000)
1885 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1886 reg_position
-= mips_abi_regsize (gdbarch
);
1890 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1891 order of that normally used by gcc. Therefore, we have to fetch
1892 the first instruction of the function, and if it's an entry
1893 instruction that saves $s0 or $s1, correct their saved addresses. */
1894 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1896 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1897 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1901 int sreg_count
= (inst
>> 6) & 3;
1903 /* Check if the ra register was pushed on the stack. */
1904 CORE_ADDR reg_position
= (cache
->base
1905 + PROC_REG_OFFSET (proc_desc
));
1907 reg_position
-= mips_abi_regsize (gdbarch
);
1909 /* Check if the s0 and s1 registers were pushed on the
1911 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1913 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1915 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1916 reg_position
-= mips_abi_regsize (gdbarch
);
1921 /* Fill in the offsets for the registers which float_mask says were
1924 CORE_ADDR reg_position
= (cache
->base
1925 + PROC_FREG_OFFSET (proc_desc
));
1927 /* Fill in the offsets for the float registers which float_mask
1929 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1930 if (float_mask
& 0x80000000)
1932 if (mips_abi_regsize (gdbarch
) == 4
1933 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1935 /* On a big endian 32 bit ABI, floating point registers
1936 are paired to form doubles such that the most
1937 significant part is in $f[N+1] and the least
1938 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1939 registers are also spilled as a pair and stored as a
1942 When little-endian the least significant part is
1943 stored first leading to the memory order $f[N] and
1946 Unfortunately, when big-endian the most significant
1947 part of the double is stored first, and the least
1948 significant is stored second. This leads to the
1949 registers being ordered in memory as firt $f[N+1] and
1952 For the big-endian case make certain that the
1953 addresses point at the correct (swapped) locations
1954 $f[N] and $f[N+1] pair (keep in mind that
1955 reg_position is decremented each time through the
1958 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1959 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1961 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1962 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1965 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1966 .addr
= reg_position
;
1967 reg_position
-= mips_abi_regsize (gdbarch
);
1970 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1971 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1974 /* SP_REGNUM, contains the value and not the address. */
1975 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1977 return (*this_cache
);
1981 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1982 struct frame_id
*this_id
)
1984 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1986 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1990 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1992 int regnum
, int *optimizedp
,
1993 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1994 int *realnump
, void *valuep
)
1996 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1998 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1999 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2002 static const struct frame_unwind mips_insn16_frame_unwind
=
2005 mips_insn16_frame_this_id
,
2006 mips_insn16_frame_prev_register
2009 static const struct frame_unwind
*
2010 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
2012 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2013 if (pc_is_mips16 (pc
))
2014 return &mips_insn16_frame_unwind
;
2019 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
2022 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2027 static const struct frame_base mips_insn16_frame_base
=
2029 &mips_insn16_frame_unwind
,
2030 mips_insn16_frame_base_address
,
2031 mips_insn16_frame_base_address
,
2032 mips_insn16_frame_base_address
2035 static const struct frame_base
*
2036 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
2038 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
2039 return &mips_insn16_frame_base
;
2044 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2045 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2046 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2049 static struct mips_frame_cache
*
2050 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2052 mips_extra_func_info_t proc_desc
;
2053 struct mips_frame_cache
*cache
;
2054 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2055 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2056 /* r0 bit means kernel trap */
2058 /* What registers have been saved? Bitmasks. */
2059 unsigned long gen_mask
, float_mask
;
2061 if ((*this_cache
) != NULL
)
2062 return (*this_cache
);
2064 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2065 (*this_cache
) = cache
;
2066 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2068 /* Synthesize a proc descriptor. */
2070 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2071 CORE_ADDR start_addr
;
2073 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2074 if (start_addr
== 0)
2075 start_addr
= heuristic_proc_start (pc
);
2077 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, *this_cache
);
2080 if (proc_desc
== NULL
)
2081 /* I'm not sure how/whether this can happen. Normally when we
2082 can't find a proc_desc, we "synthesize" one using
2083 heuristic_proc_desc and set the saved_regs right away. */
2086 /* SP_REGNUM, contains the value and not the address. */
2087 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2089 return (*this_cache
);
2093 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2094 struct frame_id
*this_id
)
2096 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2098 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2102 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2104 int regnum
, int *optimizedp
,
2105 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2106 int *realnump
, void *valuep
)
2108 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2110 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2111 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2114 static const struct frame_unwind mips_insn32_frame_unwind
=
2117 mips_insn32_frame_this_id
,
2118 mips_insn32_frame_prev_register
2121 static const struct frame_unwind
*
2122 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2124 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2125 if (! pc_is_mips16 (pc
))
2126 return &mips_insn32_frame_unwind
;
2131 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2134 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2139 static const struct frame_base mips_insn32_frame_base
=
2141 &mips_insn32_frame_unwind
,
2142 mips_insn32_frame_base_address
,
2143 mips_insn32_frame_base_address
,
2144 mips_insn32_frame_base_address
2147 static const struct frame_base
*
2148 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2150 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2151 return &mips_insn32_frame_base
;
2156 static struct trad_frame_cache
*
2157 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2160 CORE_ADDR start_addr
;
2161 CORE_ADDR stack_addr
;
2162 struct trad_frame_cache
*this_trad_cache
;
2164 if ((*this_cache
) != NULL
)
2165 return (*this_cache
);
2166 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2167 (*this_cache
) = this_trad_cache
;
2169 /* The return address is in the link register. */
2170 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, RA_REGNUM
);
2172 /* Frame ID, since it's a frameless / stackless function, no stack
2173 space is allocated and SP on entry is the current SP. */
2174 pc
= frame_pc_unwind (next_frame
);
2175 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2176 stack_addr
= frame_unwind_register_signed (next_frame
, SP_REGNUM
);
2177 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2179 /* Assume that the frame's base is the same as the
2181 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2183 return this_trad_cache
;
2187 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2188 struct frame_id
*this_id
)
2190 struct trad_frame_cache
*this_trad_cache
2191 = mips_stub_frame_cache (next_frame
, this_cache
);
2192 trad_frame_get_id (this_trad_cache
, this_id
);
2196 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2198 int regnum
, int *optimizedp
,
2199 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2200 int *realnump
, void *valuep
)
2202 struct trad_frame_cache
*this_trad_cache
2203 = mips_stub_frame_cache (next_frame
, this_cache
);
2204 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2205 lvalp
, addrp
, realnump
, valuep
);
2208 static const struct frame_unwind mips_stub_frame_unwind
=
2211 mips_stub_frame_this_id
,
2212 mips_stub_frame_prev_register
2215 static const struct frame_unwind
*
2216 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2218 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2219 if (in_plt_section (pc
, NULL
))
2220 return &mips_stub_frame_unwind
;
2226 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2229 struct trad_frame_cache
*this_trad_cache
2230 = mips_stub_frame_cache (next_frame
, this_cache
);
2231 return trad_frame_get_this_base (this_trad_cache
);
2234 static const struct frame_base mips_stub_frame_base
=
2236 &mips_stub_frame_unwind
,
2237 mips_stub_frame_base_address
,
2238 mips_stub_frame_base_address
,
2239 mips_stub_frame_base_address
2242 static const struct frame_base
*
2243 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2245 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2246 return &mips_stub_frame_base
;
2252 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2254 /* Always a pseudo. */
2255 gdb_assert (regno
>= NUM_REGS
);
2259 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2263 return frame_unwind_register_signed (fi
, regno
);
2267 /* mips_addr_bits_remove - remove useless address bits */
2270 mips_addr_bits_remove (CORE_ADDR addr
)
2272 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2273 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2274 /* This hack is a work-around for existing boards using PMON, the
2275 simulator, and any other 64-bit targets that doesn't have true
2276 64-bit addressing. On these targets, the upper 32 bits of
2277 addresses are ignored by the hardware. Thus, the PC or SP are
2278 likely to have been sign extended to all 1s by instruction
2279 sequences that load 32-bit addresses. For example, a typical
2280 piece of code that loads an address is this:
2282 lui $r2, <upper 16 bits>
2283 ori $r2, <lower 16 bits>
2285 But the lui sign-extends the value such that the upper 32 bits
2286 may be all 1s. The workaround is simply to mask off these
2287 bits. In the future, gcc may be changed to support true 64-bit
2288 addressing, and this masking will have to be disabled. */
2289 return addr
&= 0xffffffffUL
;
2294 /* mips_software_single_step() is called just before we want to resume
2295 the inferior, if we want to single-step it but there is no hardware
2296 or kernel single-step support (MIPS on GNU/Linux for example). We find
2297 the target of the coming instruction and breakpoint it.
2299 single_step is also called just after the inferior stops. If we had
2300 set up a simulated single-step, we undo our damage. */
2303 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2305 static CORE_ADDR next_pc
;
2306 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2307 static binsn_quantum break_mem
;
2310 if (insert_breakpoints_p
)
2312 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2313 next_pc
= mips_next_pc (pc
);
2315 target_insert_breakpoint (next_pc
, break_mem
);
2318 target_remove_breakpoint (next_pc
, break_mem
);
2321 static struct mips_extra_func_info temp_proc_desc
;
2323 /* Set a register's saved stack address in temp_saved_regs. If an
2324 address has already been set for this register, do nothing; this
2325 way we will only recognize the first save of a given register in a
2328 For simplicity, save the address in both [0 .. NUM_REGS) and
2329 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
2330 is used as it is only second range (the ABI instead of ISA
2331 registers) that comes into play when finding saved registers in a
2335 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
2338 if (this_cache
!= NULL
2339 && this_cache
->saved_regs
[regnum
].addr
== -1)
2341 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
2342 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
2347 /* Test whether the PC points to the return instruction at the
2348 end of a function. */
2351 mips_about_to_return (CORE_ADDR pc
)
2353 if (pc_is_mips16 (pc
))
2354 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2355 generates a "jr $ra"; other times it generates code to load
2356 the return address from the stack to an accessible register (such
2357 as $a3), then a "jr" using that register. This second case
2358 is almost impossible to distinguish from an indirect jump
2359 used for switch statements, so we don't even try. */
2360 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2362 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2366 /* This fencepost looks highly suspicious to me. Removing it also
2367 seems suspicious as it could affect remote debugging across serial
2371 heuristic_proc_start (CORE_ADDR pc
)
2378 pc
= ADDR_BITS_REMOVE (pc
);
2380 fence
= start_pc
- heuristic_fence_post
;
2384 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2385 fence
= VM_MIN_ADDRESS
;
2387 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
2389 /* search back for previous return */
2390 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2391 if (start_pc
< fence
)
2393 /* It's not clear to me why we reach this point when
2394 stop_soon, but with this test, at least we
2395 don't print out warnings for every child forked (eg, on
2396 decstation). 22apr93 rich@cygnus.com. */
2397 if (stop_soon
== NO_STOP_QUIETLY
)
2399 static int blurb_printed
= 0;
2401 warning ("GDB can't find the start of the function at 0x%s.",
2406 /* This actually happens frequently in embedded
2407 development, when you first connect to a board
2408 and your stack pointer and pc are nowhere in
2409 particular. This message needs to give people
2410 in that situation enough information to
2411 determine that it's no big deal. */
2412 printf_filtered ("\n\
2413 GDB is unable to find the start of the function at 0x%s\n\
2414 and thus can't determine the size of that function's stack frame.\n\
2415 This means that GDB may be unable to access that stack frame, or\n\
2416 the frames below it.\n\
2417 This problem is most likely caused by an invalid program counter or\n\
2419 However, if you think GDB should simply search farther back\n\
2420 from 0x%s for code which looks like the beginning of a\n\
2421 function, you can increase the range of the search using the `set\n\
2422 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2429 else if (pc_is_mips16 (start_pc
))
2431 unsigned short inst
;
2433 /* On MIPS16, any one of the following is likely to be the
2434 start of a function:
2438 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2439 inst
= mips_fetch_instruction (start_pc
);
2440 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2441 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2442 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2443 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2445 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2446 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2451 else if (mips_about_to_return (start_pc
))
2453 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2460 /* Fetch the immediate value from a MIPS16 instruction.
2461 If the previous instruction was an EXTEND, use it to extend
2462 the upper bits of the immediate value. This is a helper function
2463 for mips16_heuristic_proc_desc. */
2466 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2467 unsigned short inst
, /* current instruction */
2468 int nbits
, /* number of bits in imm field */
2469 int scale
, /* scale factor to be applied to imm */
2470 int is_signed
) /* is the imm field signed? */
2474 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2476 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2477 if (offset
& 0x8000) /* check for negative extend */
2478 offset
= 0 - (0x10000 - (offset
& 0xffff));
2479 return offset
| (inst
& 0x1f);
2483 int max_imm
= 1 << nbits
;
2484 int mask
= max_imm
- 1;
2485 int sign_bit
= max_imm
>> 1;
2487 offset
= inst
& mask
;
2488 if (is_signed
&& (offset
& sign_bit
))
2489 offset
= 0 - (max_imm
- offset
);
2490 return offset
* scale
;
2495 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2496 stream from start_pc to limit_pc. */
2499 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2501 struct frame_info
*next_frame
,
2502 struct mips_frame_cache
*this_cache
)
2505 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2506 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2507 unsigned inst
= 0; /* current instruction */
2508 unsigned entry_inst
= 0; /* the entry instruction */
2510 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2512 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2513 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2515 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2517 /* Save the previous instruction. If it's an EXTEND, we'll extract
2518 the immediate offset extension from it in mips16_get_imm. */
2521 /* Fetch and decode the instruction. */
2522 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2523 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2524 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2526 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2527 if (offset
< 0) /* negative stack adjustment? */
2528 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2530 /* Exit loop if a positive stack adjustment is found, which
2531 usually means that the stack cleanup code in the function
2532 epilogue is reached. */
2535 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2537 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2538 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2539 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2540 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2542 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2544 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2545 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2546 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2547 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2549 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2551 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2552 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2553 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2555 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2557 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2558 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2559 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2561 else if (inst
== 0x673d) /* move $s1, $sp */
2564 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2566 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2568 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2569 frame_addr
= sp
+ offset
;
2570 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2571 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2573 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2575 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2576 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2577 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2578 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
2580 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2582 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2583 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2584 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2585 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
2587 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2588 entry_inst
= inst
; /* save for later processing */
2589 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2590 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2593 /* The entry instruction is typically the first instruction in a function,
2594 and it stores registers at offsets relative to the value of the old SP
2595 (before the prologue). But the value of the sp parameter to this
2596 function is the new SP (after the prologue has been executed). So we
2597 can't calculate those offsets until we've seen the entire prologue,
2598 and can calculate what the old SP must have been. */
2599 if (entry_inst
!= 0)
2601 int areg_count
= (entry_inst
>> 8) & 7;
2602 int sreg_count
= (entry_inst
>> 6) & 3;
2604 /* The entry instruction always subtracts 32 from the SP. */
2605 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2607 /* Now we can calculate what the SP must have been at the
2608 start of the function prologue. */
2609 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2611 /* Check if a0-a3 were saved in the caller's argument save area. */
2612 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2614 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2615 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2616 offset
+= mips_abi_regsize (current_gdbarch
);
2619 /* Check if the ra register was pushed on the stack. */
2621 if (entry_inst
& 0x20)
2623 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2624 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2625 offset
-= mips_abi_regsize (current_gdbarch
);
2628 /* Check if the s0 and s1 registers were pushed on the stack. */
2629 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2631 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2632 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2633 offset
-= mips_abi_regsize (current_gdbarch
);
2638 /* Mark all the registers as unset in the saved_regs array
2639 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2642 reset_saved_regs (struct mips_frame_cache
*this_cache
)
2644 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2648 const int num_regs
= NUM_REGS
;
2651 for (i
= 0; i
< num_regs
; i
++)
2653 this_cache
->saved_regs
[i
].addr
= -1;
2659 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2660 CORE_ADDR sp
, struct frame_info
*next_frame
,
2661 struct mips_frame_cache
*this_cache
)
2664 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2666 int frame_reg
= MIPS_SP_REGNUM
;
2671 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2673 unsigned long inst
, high_word
, low_word
;
2676 /* Fetch the instruction. */
2677 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2679 /* Save some code by pre-extracting some useful fields. */
2680 high_word
= (inst
>> 16) & 0xffff;
2681 low_word
= inst
& 0xffff;
2682 reg
= high_word
& 0x1f;
2684 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2685 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2686 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2688 if (low_word
& 0x8000) /* negative stack adjustment? */
2689 frame_offset
+= 0x10000 - low_word
;
2691 /* Exit loop if a positive stack adjustment is found, which
2692 usually means that the stack cleanup code in the function
2693 epilogue is reached. */
2696 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2698 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2700 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2702 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and
2704 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2706 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2708 /* Old gcc frame, r30 is virtual frame pointer. */
2709 if ((long) low_word
!= frame_offset
)
2710 frame_addr
= sp
+ low_word
;
2711 else if (frame_reg
== MIPS_SP_REGNUM
)
2713 unsigned alloca_adjust
;
2716 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2717 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2718 if (alloca_adjust
> 0)
2720 /* FP > SP + frame_size. This may be because of
2721 an alloca or somethings similar. Fix sp to
2722 "pre-alloca" value, and try again. */
2723 sp
+= alloca_adjust
;
2724 /* Need to reset the status of all registers. Otherwise,
2725 we will hit a guard that prevents the new address
2726 for each register to be recomputed during the second
2728 reset_saved_regs (this_cache
);
2733 /* move $30,$sp. With different versions of gas this will be either
2734 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2735 Accept any one of these. */
2736 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2738 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2739 if (frame_reg
== MIPS_SP_REGNUM
)
2741 unsigned alloca_adjust
;
2744 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2745 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2746 if (alloca_adjust
> 0)
2748 /* FP > SP + frame_size. This may be because of
2749 an alloca or somethings similar. Fix sp to
2750 "pre-alloca" value, and try again. */
2752 /* Need to reset the status of all registers. Otherwise,
2753 we will hit a guard that prevents the new address
2754 for each register to be recomputed during the second
2756 reset_saved_regs (this_cache
);
2761 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2763 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
2767 if (this_cache
!= NULL
)
2770 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
2772 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2773 this assignment below, eventually. But it's still needed
2775 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2776 = this_cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2780 static mips_extra_func_info_t
2781 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2782 struct frame_info
*next_frame
,
2783 struct mips_frame_cache
*this_cache
)
2787 /* Can be called when there's no process, and hence when there's no
2789 if (next_frame
!= NULL
)
2790 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2796 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2797 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2798 PROC_FRAME_REG (&temp_proc_desc
) = MIPS_SP_REGNUM
;
2799 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2801 if (start_pc
+ 200 < limit_pc
)
2802 limit_pc
= start_pc
+ 200;
2803 if (pc_is_mips16 (start_pc
))
2804 mips16_heuristic_proc_desc (start_pc
, limit_pc
, sp
,
2805 next_frame
, this_cache
);
2807 mips32_heuristic_proc_desc (start_pc
, limit_pc
, sp
,
2808 next_frame
, this_cache
);
2809 return &temp_proc_desc
;
2812 struct mips_objfile_private
2818 /* Global used to communicate between non_heuristic_proc_desc and
2819 compare_pdr_entries within qsort (). */
2820 static bfd
*the_bfd
;
2823 compare_pdr_entries (const void *a
, const void *b
)
2825 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2826 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2830 else if (lhs
== rhs
)
2836 static mips_extra_func_info_t
2837 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2839 CORE_ADDR startaddr
;
2840 mips_extra_func_info_t proc_desc
;
2841 struct block
*b
= block_for_pc (pc
);
2843 struct obj_section
*sec
;
2844 struct mips_objfile_private
*priv
;
2846 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2848 *addrptr
= startaddr
;
2852 sec
= find_pc_section (pc
);
2855 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2857 /* Search the ".pdr" section generated by GAS. This includes most of
2858 the information normally found in ECOFF PDRs. */
2860 the_bfd
= sec
->objfile
->obfd
;
2862 && (the_bfd
->format
== bfd_object
2863 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2864 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2866 /* Right now GAS only outputs the address as a four-byte sequence.
2867 This means that we should not bother with this method on 64-bit
2868 targets (until that is fixed). */
2870 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2871 sizeof (struct mips_objfile_private
));
2873 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2875 else if (priv
== NULL
)
2879 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2880 sizeof (struct mips_objfile_private
));
2882 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2885 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2886 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2888 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2889 priv
->contents
, 0, priv
->size
);
2891 /* In general, the .pdr section is sorted. However, in the
2892 presence of multiple code sections (and other corner cases)
2893 it can become unsorted. Sort it so that we can use a faster
2895 qsort (priv
->contents
, priv
->size
/ 32, 32,
2896 compare_pdr_entries
);
2901 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2905 if (priv
->size
!= 0)
2912 high
= priv
->size
/ 32;
2914 /* We've found a .pdr section describing this objfile. We want to
2915 find the entry which describes this code address. The .pdr
2916 information is not very descriptive; we have only a function
2917 start address. We have to look for the closest entry, because
2918 the local symbol at the beginning of this function may have
2919 been stripped - so if we ask the symbol table for the start
2920 address we may get a preceding global function. */
2922 /* First, find the last .pdr entry starting at or before PC. */
2925 mid
= (low
+ high
) / 2;
2927 ptr
= priv
->contents
+ mid
* 32;
2928 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2929 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2930 SECT_OFF_TEXT (sec
->objfile
));
2937 while (low
!= high
);
2939 /* Both low and high point one past the PDR of interest. If
2940 both are zero, that means this PC is before any region
2941 covered by a PDR, i.e. pdr_pc for the first PDR entry is
2945 ptr
= priv
->contents
+ (low
- 1) * 32;
2946 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2947 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2948 SECT_OFF_TEXT (sec
->objfile
));
2951 /* We don't have a range, so we have no way to know for sure
2952 whether we're in the correct PDR or a PDR for a preceding
2953 function and the current function was a stripped local
2954 symbol. But if the PDR's PC is at least as great as the
2955 best guess from the symbol table, assume that it does cover
2956 the right area; if a .pdr section is present at all then
2957 nearly every function will have an entry. The biggest exception
2958 will be the dynamic linker stubs; conveniently these are
2959 placed before .text instead of after. */
2961 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
2963 struct symbol
*sym
= find_pc_function (pc
);
2968 /* Fill in what we need of the proc_desc. */
2969 proc_desc
= (mips_extra_func_info_t
)
2970 obstack_alloc (&sec
->objfile
->objfile_obstack
,
2971 sizeof (struct mips_extra_func_info
));
2972 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
2974 /* Only used for dummy frames. */
2975 PROC_HIGH_ADDR (proc_desc
) = 0;
2977 PROC_FRAME_OFFSET (proc_desc
)
2978 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2979 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2981 PROC_FRAME_ADJUST (proc_desc
) = 0;
2982 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2984 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2986 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2988 PROC_FREG_OFFSET (proc_desc
)
2989 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2990 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2992 proc_desc
->pdr
.isym
= (long) sym
;
3002 if (startaddr
> BLOCK_START (b
))
3004 /* This is the "pathological" case referred to in a comment in
3005 print_frame_info. It might be better to move this check into
3010 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
3012 /* If we never found a PDR for this function in symbol reading, then
3013 examine prologues to find the information. */
3016 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
3017 if (PROC_FRAME_REG (proc_desc
) == -1)
3026 /* MIPS stack frames are almost impenetrable. When execution stops,
3027 we basically have to look at symbol information for the function
3028 that we stopped in, which tells us *which* register (if any) is
3029 the base of the frame pointer, and what offset from that register
3030 the frame itself is at.
3032 This presents a problem when trying to examine a stack in memory
3033 (that isn't executing at the moment), using the "frame" command. We
3034 don't have a PC, nor do we have any registers except SP.
3036 This routine takes two arguments, SP and PC, and tries to make the
3037 cached frames look as if these two arguments defined a frame on the
3038 cache. This allows the rest of info frame to extract the important
3039 arguments without difficulty. */
3042 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
3045 error ("MIPS frame specifications require two arguments: sp and pc");
3047 return create_new_frame (argv
[0], argv
[1]);
3050 /* According to the current ABI, should the type be passed in a
3051 floating-point register (assuming that there is space)? When there
3052 is no FPU, FP are not even considered as possibile candidates for
3053 FP registers and, consequently this returns false - forces FP
3054 arguments into integer registers. */
3057 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
3059 return ((typecode
== TYPE_CODE_FLT
3061 && (typecode
== TYPE_CODE_STRUCT
3062 || typecode
== TYPE_CODE_UNION
)
3063 && TYPE_NFIELDS (arg_type
) == 1
3064 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
3065 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
3068 /* On o32, argument passing in GPRs depends on the alignment of the type being
3069 passed. Return 1 if this type must be aligned to a doubleword boundary. */
3072 mips_type_needs_double_align (struct type
*type
)
3074 enum type_code typecode
= TYPE_CODE (type
);
3076 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
3078 else if (typecode
== TYPE_CODE_STRUCT
)
3080 if (TYPE_NFIELDS (type
) < 1)
3082 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
3084 else if (typecode
== TYPE_CODE_UNION
)
3088 n
= TYPE_NFIELDS (type
);
3089 for (i
= 0; i
< n
; i
++)
3090 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
3097 /* Adjust the address downward (direction of stack growth) so that it
3098 is correctly aligned for a new stack frame. */
3100 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3102 return align_down (addr
, 16);
3105 /* Determine how a return value is stored within the MIPS register
3106 file, given the return type `valtype'. */
3108 struct return_value_word
3117 return_value_location (struct type
*valtype
,
3118 struct return_value_word
*hi
,
3119 struct return_value_word
*lo
)
3121 int len
= TYPE_LENGTH (valtype
);
3122 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3124 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3125 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3126 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3128 if (mips_abi_regsize (current_gdbarch
) < 8 && len
== 8)
3130 /* We need to break a 64bit float in two 32 bit halves and
3131 spread them across a floating-point register pair. */
3132 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3133 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3134 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3135 && register_size (current_gdbarch
,
3136 mips_regnum (current_gdbarch
)->
3137 fp0
) == 8) ? 4 : 0);
3138 hi
->reg_offset
= lo
->reg_offset
;
3139 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
3140 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
3146 /* The floating point value fits in a single floating-point
3148 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3149 && register_size (current_gdbarch
,
3150 mips_regnum (current_gdbarch
)->
3152 && len
== 4) ? 4 : 0);
3153 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
3164 /* Locate a result possibly spread across two registers. */
3166 lo
->reg
= regnum
+ 0;
3167 hi
->reg
= regnum
+ 1;
3168 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3169 && len
< mips_abi_regsize (current_gdbarch
))
3171 /* "un-left-justify" the value in the low register */
3172 lo
->reg_offset
= mips_abi_regsize (current_gdbarch
) - len
;
3177 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (current_gdbarch
) /* odd-size structs */
3178 && len
< mips_abi_regsize (current_gdbarch
) * 2
3179 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3180 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3182 /* "un-left-justify" the value spread across two registers. */
3183 lo
->reg_offset
= 2 * mips_abi_regsize (current_gdbarch
) - len
;
3184 lo
->len
= mips_abi_regsize (current_gdbarch
) - lo
->reg_offset
;
3186 hi
->len
= len
- lo
->len
;
3190 /* Only perform a partial copy of the second register. */
3193 if (len
> mips_abi_regsize (current_gdbarch
))
3195 lo
->len
= mips_abi_regsize (current_gdbarch
);
3196 hi
->len
= len
- mips_abi_regsize (current_gdbarch
);
3204 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3205 && register_size (current_gdbarch
, regnum
) == 8
3206 && mips_abi_regsize (current_gdbarch
) == 4)
3208 /* Account for the fact that only the least-signficant part
3209 of the register is being used */
3210 lo
->reg_offset
+= 4;
3211 hi
->reg_offset
+= 4;
3214 hi
->buf_offset
= lo
->len
;
3218 /* Should call_function allocate stack space for a struct return? */
3221 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
3223 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3224 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (current_gdbarch
));
3227 /* Should call_function pass struct by reference?
3228 For each architecture, structs are passed either by
3229 value or by reference, depending on their size. */
3232 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
3234 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
3235 int len
= TYPE_LENGTH (check_typedef (type
));
3236 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3238 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
3239 return (len
> mips_abi_regsize (current_gdbarch
));
3245 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3246 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3247 int nargs
, struct value
**args
, CORE_ADDR sp
,
3248 int struct_return
, CORE_ADDR struct_addr
)
3254 int stack_offset
= 0;
3255 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3256 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3258 /* For shared libraries, "t9" needs to point at the function
3260 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3262 /* Set the return address register to point to the entry point of
3263 the program, where a breakpoint lies in wait. */
3264 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3266 /* First ensure that the stack and structure return address (if any)
3267 are properly aligned. The stack has to be at least 64-bit
3268 aligned even on 32-bit machines, because doubles must be 64-bit
3269 aligned. For n32 and n64, stack frames need to be 128-bit
3270 aligned, so we round to this widest known alignment. */
3272 sp
= align_down (sp
, 16);
3273 struct_addr
= align_down (struct_addr
, 16);
3275 /* Now make space on the stack for the args. We allocate more
3276 than necessary for EABI, because the first few arguments are
3277 passed in registers, but that's OK. */
3278 for (argnum
= 0; argnum
< nargs
; argnum
++)
3279 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3280 mips_stack_argsize (gdbarch
));
3281 sp
-= align_up (len
, 16);
3284 fprintf_unfiltered (gdb_stdlog
,
3285 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
3286 paddr_nz (sp
), (long) align_up (len
, 16));
3288 /* Initialize the integer and float register pointers. */
3290 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3292 /* The struct_return pointer occupies the first parameter-passing reg. */
3296 fprintf_unfiltered (gdb_stdlog
,
3297 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
3298 argreg
, paddr_nz (struct_addr
));
3299 write_register (argreg
++, struct_addr
);
3302 /* Now load as many as possible of the first arguments into
3303 registers, and push the rest onto the stack. Loop thru args
3304 from first to last. */
3305 for (argnum
= 0; argnum
< nargs
; argnum
++)
3308 char valbuf
[MAX_REGISTER_SIZE
];
3309 struct value
*arg
= args
[argnum
];
3310 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3311 int len
= TYPE_LENGTH (arg_type
);
3312 enum type_code typecode
= TYPE_CODE (arg_type
);
3315 fprintf_unfiltered (gdb_stdlog
,
3316 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3317 argnum
+ 1, len
, (int) typecode
);
3319 /* The EABI passes structures that do not fit in a register by
3321 if (len
> mips_abi_regsize (gdbarch
)
3322 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3324 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
3325 VALUE_ADDRESS (arg
));
3326 typecode
= TYPE_CODE_PTR
;
3327 len
= mips_abi_regsize (gdbarch
);
3330 fprintf_unfiltered (gdb_stdlog
, " push");
3333 val
= (char *) VALUE_CONTENTS (arg
);
3335 /* 32-bit ABIs always start floating point arguments in an
3336 even-numbered floating point register. Round the FP register
3337 up before the check to see if there are any FP registers
3338 left. Non MIPS_EABI targets also pass the FP in the integer
3339 registers so also round up normal registers. */
3340 if (mips_abi_regsize (gdbarch
) < 8
3341 && fp_register_arg_p (typecode
, arg_type
))
3343 if ((float_argreg
& 1))
3347 /* Floating point arguments passed in registers have to be
3348 treated specially. On 32-bit architectures, doubles
3349 are passed in register pairs; the even register gets
3350 the low word, and the odd register gets the high word.
3351 On non-EABI processors, the first two floating point arguments are
3352 also copied to general registers, because MIPS16 functions
3353 don't use float registers for arguments. This duplication of
3354 arguments in general registers can't hurt non-MIPS16 functions
3355 because those registers are normally skipped. */
3356 /* MIPS_EABI squeezes a struct that contains a single floating
3357 point value into an FP register instead of pushing it onto the
3359 if (fp_register_arg_p (typecode
, arg_type
)
3360 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3362 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3364 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3365 unsigned long regval
;
3367 /* Write the low word of the double to the even register(s). */
3368 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3370 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3371 float_argreg
, phex (regval
, 4));
3372 write_register (float_argreg
++, regval
);
3374 /* Write the high word of the double to the odd register(s). */
3375 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3377 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3378 float_argreg
, phex (regval
, 4));
3379 write_register (float_argreg
++, regval
);
3383 /* This is a floating point value that fits entirely
3384 in a single register. */
3385 /* On 32 bit ABI's the float_argreg is further adjusted
3386 above to ensure that it is even register aligned. */
3387 LONGEST regval
= extract_unsigned_integer (val
, len
);
3389 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3390 float_argreg
, phex (regval
, len
));
3391 write_register (float_argreg
++, regval
);
3396 /* Copy the argument to general registers or the stack in
3397 register-sized pieces. Large arguments are split between
3398 registers and stack. */
3399 /* Note: structs whose size is not a multiple of
3400 mips_abi_regsize() are treated specially: Irix cc passes
3401 them in registers where gcc sometimes puts them on the
3402 stack. For maximum compatibility, we will put them in
3404 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3405 && (len
% mips_abi_regsize (gdbarch
) != 0));
3407 /* Note: Floating-point values that didn't fit into an FP
3408 register are only written to memory. */
3411 /* Remember if the argument was written to the stack. */
3412 int stack_used_p
= 0;
3413 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3414 ? len
: mips_abi_regsize (gdbarch
));
3417 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3420 /* Write this portion of the argument to the stack. */
3421 if (argreg
> MIPS_LAST_ARG_REGNUM
3423 || fp_register_arg_p (typecode
, arg_type
))
3425 /* Should shorter than int integer values be
3426 promoted to int before being stored? */
3427 int longword_offset
= 0;
3430 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3432 if (mips_stack_argsize (gdbarch
) == 8
3433 && (typecode
== TYPE_CODE_INT
3434 || typecode
== TYPE_CODE_PTR
3435 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3436 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3437 else if ((typecode
== TYPE_CODE_STRUCT
3438 || typecode
== TYPE_CODE_UNION
)
3439 && (TYPE_LENGTH (arg_type
)
3440 < mips_stack_argsize (gdbarch
)))
3441 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3446 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3447 paddr_nz (stack_offset
));
3448 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3449 paddr_nz (longword_offset
));
3452 addr
= sp
+ stack_offset
+ longword_offset
;
3457 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3459 for (i
= 0; i
< partial_len
; i
++)
3461 fprintf_unfiltered (gdb_stdlog
, "%02x",
3465 write_memory (addr
, val
, partial_len
);
3468 /* Note!!! This is NOT an else clause. Odd sized
3469 structs may go thru BOTH paths. Floating point
3470 arguments will not. */
3471 /* Write this portion of the argument to a general
3472 purpose register. */
3473 if (argreg
<= MIPS_LAST_ARG_REGNUM
3474 && !fp_register_arg_p (typecode
, arg_type
))
3477 extract_unsigned_integer (val
, partial_len
);
3480 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3483 mips_abi_regsize (gdbarch
)));
3484 write_register (argreg
, regval
);
3491 /* Compute the the offset into the stack at which we
3492 will copy the next parameter.
3494 In the new EABI (and the NABI32), the stack_offset
3495 only needs to be adjusted when it has been used. */
3498 stack_offset
+= align_up (partial_len
,
3499 mips_stack_argsize (gdbarch
));
3503 fprintf_unfiltered (gdb_stdlog
, "\n");
3506 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3508 /* Return adjusted stack pointer. */
3512 /* Given a return value in `regbuf' with a type `valtype', extract and
3513 copy its value into `valbuf'. */
3516 mips_eabi_extract_return_value (struct type
*valtype
,
3517 char regbuf
[], char *valbuf
)
3519 struct return_value_word lo
;
3520 struct return_value_word hi
;
3521 return_value_location (valtype
, &hi
, &lo
);
3523 memcpy (valbuf
+ lo
.buf_offset
,
3524 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3525 lo
.reg_offset
, lo
.len
);
3528 memcpy (valbuf
+ hi
.buf_offset
,
3529 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3530 hi
.reg_offset
, hi
.len
);
3533 /* Given a return value in `valbuf' with a type `valtype', write it's
3534 value into the appropriate register. */
3537 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3539 char raw_buffer
[MAX_REGISTER_SIZE
];
3540 struct return_value_word lo
;
3541 struct return_value_word hi
;
3542 return_value_location (valtype
, &hi
, &lo
);
3544 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3545 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3546 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3547 raw_buffer
, register_size (current_gdbarch
,
3552 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3553 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3554 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3556 register_size (current_gdbarch
,
3561 /* N32/N64 ABI stuff. */
3564 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3565 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3566 int nargs
, struct value
**args
, CORE_ADDR sp
,
3567 int struct_return
, CORE_ADDR struct_addr
)
3573 int stack_offset
= 0;
3574 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3575 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3577 /* For shared libraries, "t9" needs to point at the function
3579 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3581 /* Set the return address register to point to the entry point of
3582 the program, where a breakpoint lies in wait. */
3583 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3585 /* First ensure that the stack and structure return address (if any)
3586 are properly aligned. The stack has to be at least 64-bit
3587 aligned even on 32-bit machines, because doubles must be 64-bit
3588 aligned. For n32 and n64, stack frames need to be 128-bit
3589 aligned, so we round to this widest known alignment. */
3591 sp
= align_down (sp
, 16);
3592 struct_addr
= align_down (struct_addr
, 16);
3594 /* Now make space on the stack for the args. */
3595 for (argnum
= 0; argnum
< nargs
; argnum
++)
3596 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3597 mips_stack_argsize (gdbarch
));
3598 sp
-= align_up (len
, 16);
3601 fprintf_unfiltered (gdb_stdlog
,
3602 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3603 paddr_nz (sp
), (long) align_up (len
, 16));
3605 /* Initialize the integer and float register pointers. */
3607 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3609 /* The struct_return pointer occupies the first parameter-passing reg. */
3613 fprintf_unfiltered (gdb_stdlog
,
3614 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3615 argreg
, paddr_nz (struct_addr
));
3616 write_register (argreg
++, struct_addr
);
3619 /* Now load as many as possible of the first arguments into
3620 registers, and push the rest onto the stack. Loop thru args
3621 from first to last. */
3622 for (argnum
= 0; argnum
< nargs
; argnum
++)
3625 struct value
*arg
= args
[argnum
];
3626 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3627 int len
= TYPE_LENGTH (arg_type
);
3628 enum type_code typecode
= TYPE_CODE (arg_type
);
3631 fprintf_unfiltered (gdb_stdlog
,
3632 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3633 argnum
+ 1, len
, (int) typecode
);
3635 val
= (char *) VALUE_CONTENTS (arg
);
3637 if (fp_register_arg_p (typecode
, arg_type
)
3638 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3640 /* This is a floating point value that fits entirely
3641 in a single register. */
3642 /* On 32 bit ABI's the float_argreg is further adjusted
3643 above to ensure that it is even register aligned. */
3644 LONGEST regval
= extract_unsigned_integer (val
, len
);
3646 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3647 float_argreg
, phex (regval
, len
));
3648 write_register (float_argreg
++, regval
);
3651 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3652 argreg
, phex (regval
, len
));
3653 write_register (argreg
, regval
);
3658 /* Copy the argument to general registers or the stack in
3659 register-sized pieces. Large arguments are split between
3660 registers and stack. */
3661 /* Note: structs whose size is not a multiple of
3662 mips_abi_regsize() are treated specially: Irix cc passes
3663 them in registers where gcc sometimes puts them on the
3664 stack. For maximum compatibility, we will put them in
3666 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3667 && (len
% mips_abi_regsize (gdbarch
) != 0));
3668 /* Note: Floating-point values that didn't fit into an FP
3669 register are only written to memory. */
3672 /* Rememer if the argument was written to the stack. */
3673 int stack_used_p
= 0;
3674 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3675 ? len
: mips_abi_regsize (gdbarch
));
3678 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3681 /* Write this portion of the argument to the stack. */
3682 if (argreg
> MIPS_LAST_ARG_REGNUM
3684 || fp_register_arg_p (typecode
, arg_type
))
3686 /* Should shorter than int integer values be
3687 promoted to int before being stored? */
3688 int longword_offset
= 0;
3691 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3693 if (mips_stack_argsize (gdbarch
) == 8
3694 && (typecode
== TYPE_CODE_INT
3695 || typecode
== TYPE_CODE_PTR
3696 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3697 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3702 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3703 paddr_nz (stack_offset
));
3704 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3705 paddr_nz (longword_offset
));
3708 addr
= sp
+ stack_offset
+ longword_offset
;
3713 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3715 for (i
= 0; i
< partial_len
; i
++)
3717 fprintf_unfiltered (gdb_stdlog
, "%02x",
3721 write_memory (addr
, val
, partial_len
);
3724 /* Note!!! This is NOT an else clause. Odd sized
3725 structs may go thru BOTH paths. Floating point
3726 arguments will not. */
3727 /* Write this portion of the argument to a general
3728 purpose register. */
3729 if (argreg
<= MIPS_LAST_ARG_REGNUM
3730 && !fp_register_arg_p (typecode
, arg_type
))
3733 extract_unsigned_integer (val
, partial_len
);
3735 /* A non-floating-point argument being passed in a
3736 general register. If a struct or union, and if
3737 the remaining length is smaller than the register
3738 size, we have to adjust the register value on
3741 It does not seem to be necessary to do the
3742 same for integral types.
3744 cagney/2001-07-23: gdb/179: Also, GCC, when
3745 outputting LE O32 with sizeof (struct) <
3746 mips_abi_regsize(), generates a left shift as
3747 part of storing the argument in a register a
3748 register (the left shift isn't generated when
3749 sizeof (struct) >= mips_abi_regsize()). Since
3750 it is quite possible that this is GCC
3751 contradicting the LE/O32 ABI, GDB has not been
3752 adjusted to accommodate this. Either someone
3753 needs to demonstrate that the LE/O32 ABI
3754 specifies such a left shift OR this new ABI gets
3755 identified as such and GDB gets tweaked
3758 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3759 && partial_len
< mips_abi_regsize (gdbarch
)
3760 && (typecode
== TYPE_CODE_STRUCT
||
3761 typecode
== TYPE_CODE_UNION
))
3762 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3766 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3769 mips_abi_regsize (gdbarch
)));
3770 write_register (argreg
, regval
);
3777 /* Compute the the offset into the stack at which we
3778 will copy the next parameter.
3780 In N32 (N64?), the stack_offset only needs to be
3781 adjusted when it has been used. */
3784 stack_offset
+= align_up (partial_len
,
3785 mips_stack_argsize (gdbarch
));
3789 fprintf_unfiltered (gdb_stdlog
, "\n");
3792 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3794 /* Return adjusted stack pointer. */
3798 static enum return_value_convention
3799 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3800 struct type
*type
, struct regcache
*regcache
,
3801 void *readbuf
, const void *writebuf
)
3803 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3804 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3805 || TYPE_CODE (type
) == TYPE_CODE_UNION
3806 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3807 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3808 return RETURN_VALUE_STRUCT_CONVENTION
;
3809 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3810 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3812 /* A floating-point value belongs in the least significant part
3815 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3816 mips_xfer_register (regcache
,
3817 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3819 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3820 return RETURN_VALUE_REGISTER_CONVENTION
;
3822 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3823 && TYPE_NFIELDS (type
) <= 2
3824 && TYPE_NFIELDS (type
) >= 1
3825 && ((TYPE_NFIELDS (type
) == 1
3826 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3828 || (TYPE_NFIELDS (type
) == 2
3829 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3831 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3833 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3835 /* A struct that contains one or two floats. Each value is part
3836 in the least significant part of their floating point
3840 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3841 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3843 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3846 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3848 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3849 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3850 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3852 return RETURN_VALUE_REGISTER_CONVENTION
;
3854 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3855 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3857 /* A structure or union. Extract the left justified value,
3858 regardless of the byte order. I.e. DO NOT USE
3862 for (offset
= 0, regnum
= V0_REGNUM
;
3863 offset
< TYPE_LENGTH (type
);
3864 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3866 int xfer
= register_size (current_gdbarch
, regnum
);
3867 if (offset
+ xfer
> TYPE_LENGTH (type
))
3868 xfer
= TYPE_LENGTH (type
) - offset
;
3870 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3871 offset
, xfer
, regnum
);
3872 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3873 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3875 return RETURN_VALUE_REGISTER_CONVENTION
;
3879 /* A scalar extract each part but least-significant-byte
3883 for (offset
= 0, regnum
= V0_REGNUM
;
3884 offset
< TYPE_LENGTH (type
);
3885 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3887 int xfer
= register_size (current_gdbarch
, regnum
);
3888 if (offset
+ xfer
> TYPE_LENGTH (type
))
3889 xfer
= TYPE_LENGTH (type
) - offset
;
3891 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3892 offset
, xfer
, regnum
);
3893 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3894 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3896 return RETURN_VALUE_REGISTER_CONVENTION
;
3900 /* O32 ABI stuff. */
3903 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3904 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3905 int nargs
, struct value
**args
, CORE_ADDR sp
,
3906 int struct_return
, CORE_ADDR struct_addr
)
3912 int stack_offset
= 0;
3913 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3914 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3916 /* For shared libraries, "t9" needs to point at the function
3918 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3920 /* Set the return address register to point to the entry point of
3921 the program, where a breakpoint lies in wait. */
3922 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3924 /* First ensure that the stack and structure return address (if any)
3925 are properly aligned. The stack has to be at least 64-bit
3926 aligned even on 32-bit machines, because doubles must be 64-bit
3927 aligned. For n32 and n64, stack frames need to be 128-bit
3928 aligned, so we round to this widest known alignment. */
3930 sp
= align_down (sp
, 16);
3931 struct_addr
= align_down (struct_addr
, 16);
3933 /* Now make space on the stack for the args. */
3934 for (argnum
= 0; argnum
< nargs
; argnum
++)
3935 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3936 mips_stack_argsize (gdbarch
));
3937 sp
-= align_up (len
, 16);
3940 fprintf_unfiltered (gdb_stdlog
,
3941 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3942 paddr_nz (sp
), (long) align_up (len
, 16));
3944 /* Initialize the integer and float register pointers. */
3946 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3948 /* The struct_return pointer occupies the first parameter-passing reg. */
3952 fprintf_unfiltered (gdb_stdlog
,
3953 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3954 argreg
, paddr_nz (struct_addr
));
3955 write_register (argreg
++, struct_addr
);
3956 stack_offset
+= mips_stack_argsize (gdbarch
);
3959 /* Now load as many as possible of the first arguments into
3960 registers, and push the rest onto the stack. Loop thru args
3961 from first to last. */
3962 for (argnum
= 0; argnum
< nargs
; argnum
++)
3965 struct value
*arg
= args
[argnum
];
3966 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3967 int len
= TYPE_LENGTH (arg_type
);
3968 enum type_code typecode
= TYPE_CODE (arg_type
);
3971 fprintf_unfiltered (gdb_stdlog
,
3972 "mips_o32_push_dummy_call: %d len=%d type=%d",
3973 argnum
+ 1, len
, (int) typecode
);
3975 val
= (char *) VALUE_CONTENTS (arg
);
3977 /* 32-bit ABIs always start floating point arguments in an
3978 even-numbered floating point register. Round the FP register
3979 up before the check to see if there are any FP registers
3980 left. O32/O64 targets also pass the FP in the integer
3981 registers so also round up normal registers. */
3982 if (mips_abi_regsize (gdbarch
) < 8
3983 && fp_register_arg_p (typecode
, arg_type
))
3985 if ((float_argreg
& 1))
3989 /* Floating point arguments passed in registers have to be
3990 treated specially. On 32-bit architectures, doubles
3991 are passed in register pairs; the even register gets
3992 the low word, and the odd register gets the high word.
3993 On O32/O64, the first two floating point arguments are
3994 also copied to general registers, because MIPS16 functions
3995 don't use float registers for arguments. This duplication of
3996 arguments in general registers can't hurt non-MIPS16 functions
3997 because those registers are normally skipped. */
3999 if (fp_register_arg_p (typecode
, arg_type
)
4000 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4002 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4004 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4005 unsigned long regval
;
4007 /* Write the low word of the double to the even register(s). */
4008 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4010 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4011 float_argreg
, phex (regval
, 4));
4012 write_register (float_argreg
++, regval
);
4014 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4015 argreg
, phex (regval
, 4));
4016 write_register (argreg
++, regval
);
4018 /* Write the high word of the double to the odd register(s). */
4019 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4021 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4022 float_argreg
, phex (regval
, 4));
4023 write_register (float_argreg
++, regval
);
4026 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4027 argreg
, phex (regval
, 4));
4028 write_register (argreg
++, regval
);
4032 /* This is a floating point value that fits entirely
4033 in a single register. */
4034 /* On 32 bit ABI's the float_argreg is further adjusted
4035 above to ensure that it is even register aligned. */
4036 LONGEST regval
= extract_unsigned_integer (val
, len
);
4038 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4039 float_argreg
, phex (regval
, len
));
4040 write_register (float_argreg
++, regval
);
4041 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4042 registers for each argument. The below is (my
4043 guess) to ensure that the corresponding integer
4044 register has reserved the same space. */
4046 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4047 argreg
, phex (regval
, len
));
4048 write_register (argreg
, regval
);
4049 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4051 /* Reserve space for the FP register. */
4052 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4056 /* Copy the argument to general registers or the stack in
4057 register-sized pieces. Large arguments are split between
4058 registers and stack. */
4059 /* Note: structs whose size is not a multiple of
4060 mips_abi_regsize() are treated specially: Irix cc passes
4061 them in registers where gcc sometimes puts them on the
4062 stack. For maximum compatibility, we will put them in
4064 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4065 && (len
% mips_abi_regsize (gdbarch
) != 0));
4066 /* Structures should be aligned to eight bytes (even arg registers)
4067 on MIPS_ABI_O32, if their first member has double precision. */
4068 if (mips_abi_regsize (gdbarch
) < 8
4069 && mips_type_needs_double_align (arg_type
))
4074 /* Note: Floating-point values that didn't fit into an FP
4075 register are only written to memory. */
4078 /* Remember if the argument was written to the stack. */
4079 int stack_used_p
= 0;
4080 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4081 ? len
: mips_abi_regsize (gdbarch
));
4084 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4087 /* Write this portion of the argument to the stack. */
4088 if (argreg
> MIPS_LAST_ARG_REGNUM
4090 || fp_register_arg_p (typecode
, arg_type
))
4092 /* Should shorter than int integer values be
4093 promoted to int before being stored? */
4094 int longword_offset
= 0;
4097 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4099 if (mips_stack_argsize (gdbarch
) == 8
4100 && (typecode
== TYPE_CODE_INT
4101 || typecode
== TYPE_CODE_PTR
4102 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4103 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4108 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4109 paddr_nz (stack_offset
));
4110 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4111 paddr_nz (longword_offset
));
4114 addr
= sp
+ stack_offset
+ longword_offset
;
4119 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4121 for (i
= 0; i
< partial_len
; i
++)
4123 fprintf_unfiltered (gdb_stdlog
, "%02x",
4127 write_memory (addr
, val
, partial_len
);
4130 /* Note!!! This is NOT an else clause. Odd sized
4131 structs may go thru BOTH paths. Floating point
4132 arguments will not. */
4133 /* Write this portion of the argument to a general
4134 purpose register. */
4135 if (argreg
<= MIPS_LAST_ARG_REGNUM
4136 && !fp_register_arg_p (typecode
, arg_type
))
4138 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4139 /* Value may need to be sign extended, because
4140 mips_isa_regsize() != mips_abi_regsize(). */
4142 /* A non-floating-point argument being passed in a
4143 general register. If a struct or union, and if
4144 the remaining length is smaller than the register
4145 size, we have to adjust the register value on
4148 It does not seem to be necessary to do the
4149 same for integral types.
4151 Also don't do this adjustment on O64 binaries.
4153 cagney/2001-07-23: gdb/179: Also, GCC, when
4154 outputting LE O32 with sizeof (struct) <
4155 mips_abi_regsize(), generates a left shift as
4156 part of storing the argument in a register a
4157 register (the left shift isn't generated when
4158 sizeof (struct) >= mips_abi_regsize()). Since
4159 it is quite possible that this is GCC
4160 contradicting the LE/O32 ABI, GDB has not been
4161 adjusted to accommodate this. Either someone
4162 needs to demonstrate that the LE/O32 ABI
4163 specifies such a left shift OR this new ABI gets
4164 identified as such and GDB gets tweaked
4167 if (mips_abi_regsize (gdbarch
) < 8
4168 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4169 && partial_len
< mips_abi_regsize (gdbarch
)
4170 && (typecode
== TYPE_CODE_STRUCT
||
4171 typecode
== TYPE_CODE_UNION
))
4172 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4176 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4179 mips_abi_regsize (gdbarch
)));
4180 write_register (argreg
, regval
);
4183 /* Prevent subsequent floating point arguments from
4184 being passed in floating point registers. */
4185 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4191 /* Compute the the offset into the stack at which we
4192 will copy the next parameter.
4194 In older ABIs, the caller reserved space for
4195 registers that contained arguments. This was loosely
4196 refered to as their "home". Consequently, space is
4197 always allocated. */
4199 stack_offset
+= align_up (partial_len
,
4200 mips_stack_argsize (gdbarch
));
4204 fprintf_unfiltered (gdb_stdlog
, "\n");
4207 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4209 /* Return adjusted stack pointer. */
4213 static enum return_value_convention
4214 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4215 struct regcache
*regcache
,
4216 void *readbuf
, const void *writebuf
)
4218 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4220 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4221 || TYPE_CODE (type
) == TYPE_CODE_UNION
4222 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4223 return RETURN_VALUE_STRUCT_CONVENTION
;
4224 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4225 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4227 /* A single-precision floating-point value. It fits in the
4228 least significant part of FP0. */
4230 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4231 mips_xfer_register (regcache
,
4232 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4234 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4235 return RETURN_VALUE_REGISTER_CONVENTION
;
4237 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4238 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4240 /* A double-precision floating-point value. The most
4241 significant part goes in FP1, and the least significant in
4244 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4245 switch (TARGET_BYTE_ORDER
)
4247 case BFD_ENDIAN_LITTLE
:
4248 mips_xfer_register (regcache
,
4249 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4250 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4251 mips_xfer_register (regcache
,
4252 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4253 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4255 case BFD_ENDIAN_BIG
:
4256 mips_xfer_register (regcache
,
4257 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4258 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4259 mips_xfer_register (regcache
,
4260 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4261 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4264 internal_error (__FILE__
, __LINE__
, "bad switch");
4266 return RETURN_VALUE_REGISTER_CONVENTION
;
4269 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4270 && TYPE_NFIELDS (type
) <= 2
4271 && TYPE_NFIELDS (type
) >= 1
4272 && ((TYPE_NFIELDS (type
) == 1
4273 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4275 || (TYPE_NFIELDS (type
) == 2
4276 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4278 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4280 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4282 /* A struct that contains one or two floats. Each value is part
4283 in the least significant part of their floating point
4285 bfd_byte reg
[MAX_REGISTER_SIZE
];
4288 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4289 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4291 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4294 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4296 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4297 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4298 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4300 return RETURN_VALUE_REGISTER_CONVENTION
;
4304 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4305 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4307 /* A structure or union. Extract the left justified value,
4308 regardless of the byte order. I.e. DO NOT USE
4312 for (offset
= 0, regnum
= V0_REGNUM
;
4313 offset
< TYPE_LENGTH (type
);
4314 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4316 int xfer
= register_size (current_gdbarch
, regnum
);
4317 if (offset
+ xfer
> TYPE_LENGTH (type
))
4318 xfer
= TYPE_LENGTH (type
) - offset
;
4320 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4321 offset
, xfer
, regnum
);
4322 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4323 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4325 return RETURN_VALUE_REGISTER_CONVENTION
;
4330 /* A scalar extract each part but least-significant-byte
4331 justified. o32 thinks registers are 4 byte, regardless of
4332 the ISA. mips_stack_argsize controls this. */
4335 for (offset
= 0, regnum
= V0_REGNUM
;
4336 offset
< TYPE_LENGTH (type
);
4337 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
4339 int xfer
= mips_stack_argsize (gdbarch
);
4340 if (offset
+ xfer
> TYPE_LENGTH (type
))
4341 xfer
= TYPE_LENGTH (type
) - offset
;
4343 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4344 offset
, xfer
, regnum
);
4345 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4346 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4348 return RETURN_VALUE_REGISTER_CONVENTION
;
4352 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4356 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4357 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4359 struct value
**args
, CORE_ADDR sp
,
4360 int struct_return
, CORE_ADDR struct_addr
)
4366 int stack_offset
= 0;
4367 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4368 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4370 /* For shared libraries, "t9" needs to point at the function
4372 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4374 /* Set the return address register to point to the entry point of
4375 the program, where a breakpoint lies in wait. */
4376 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4378 /* First ensure that the stack and structure return address (if any)
4379 are properly aligned. The stack has to be at least 64-bit
4380 aligned even on 32-bit machines, because doubles must be 64-bit
4381 aligned. For n32 and n64, stack frames need to be 128-bit
4382 aligned, so we round to this widest known alignment. */
4384 sp
= align_down (sp
, 16);
4385 struct_addr
= align_down (struct_addr
, 16);
4387 /* Now make space on the stack for the args. */
4388 for (argnum
= 0; argnum
< nargs
; argnum
++)
4389 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4390 mips_stack_argsize (gdbarch
));
4391 sp
-= align_up (len
, 16);
4394 fprintf_unfiltered (gdb_stdlog
,
4395 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4396 paddr_nz (sp
), (long) align_up (len
, 16));
4398 /* Initialize the integer and float register pointers. */
4400 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4402 /* The struct_return pointer occupies the first parameter-passing reg. */
4406 fprintf_unfiltered (gdb_stdlog
,
4407 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4408 argreg
, paddr_nz (struct_addr
));
4409 write_register (argreg
++, struct_addr
);
4410 stack_offset
+= mips_stack_argsize (gdbarch
);
4413 /* Now load as many as possible of the first arguments into
4414 registers, and push the rest onto the stack. Loop thru args
4415 from first to last. */
4416 for (argnum
= 0; argnum
< nargs
; argnum
++)
4419 struct value
*arg
= args
[argnum
];
4420 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4421 int len
= TYPE_LENGTH (arg_type
);
4422 enum type_code typecode
= TYPE_CODE (arg_type
);
4425 fprintf_unfiltered (gdb_stdlog
,
4426 "mips_o64_push_dummy_call: %d len=%d type=%d",
4427 argnum
+ 1, len
, (int) typecode
);
4429 val
= (char *) VALUE_CONTENTS (arg
);
4431 /* 32-bit ABIs always start floating point arguments in an
4432 even-numbered floating point register. Round the FP register
4433 up before the check to see if there are any FP registers
4434 left. O32/O64 targets also pass the FP in the integer
4435 registers so also round up normal registers. */
4436 if (mips_abi_regsize (gdbarch
) < 8
4437 && fp_register_arg_p (typecode
, arg_type
))
4439 if ((float_argreg
& 1))
4443 /* Floating point arguments passed in registers have to be
4444 treated specially. On 32-bit architectures, doubles
4445 are passed in register pairs; the even register gets
4446 the low word, and the odd register gets the high word.
4447 On O32/O64, the first two floating point arguments are
4448 also copied to general registers, because MIPS16 functions
4449 don't use float registers for arguments. This duplication of
4450 arguments in general registers can't hurt non-MIPS16 functions
4451 because those registers are normally skipped. */
4453 if (fp_register_arg_p (typecode
, arg_type
)
4454 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4456 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4458 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4459 unsigned long regval
;
4461 /* Write the low word of the double to the even register(s). */
4462 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4464 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4465 float_argreg
, phex (regval
, 4));
4466 write_register (float_argreg
++, regval
);
4468 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4469 argreg
, phex (regval
, 4));
4470 write_register (argreg
++, regval
);
4472 /* Write the high word of the double to the odd register(s). */
4473 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4475 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4476 float_argreg
, phex (regval
, 4));
4477 write_register (float_argreg
++, regval
);
4480 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4481 argreg
, phex (regval
, 4));
4482 write_register (argreg
++, regval
);
4486 /* This is a floating point value that fits entirely
4487 in a single register. */
4488 /* On 32 bit ABI's the float_argreg is further adjusted
4489 above to ensure that it is even register aligned. */
4490 LONGEST regval
= extract_unsigned_integer (val
, len
);
4492 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4493 float_argreg
, phex (regval
, len
));
4494 write_register (float_argreg
++, regval
);
4495 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4496 registers for each argument. The below is (my
4497 guess) to ensure that the corresponding integer
4498 register has reserved the same space. */
4500 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4501 argreg
, phex (regval
, len
));
4502 write_register (argreg
, regval
);
4503 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4505 /* Reserve space for the FP register. */
4506 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4510 /* Copy the argument to general registers or the stack in
4511 register-sized pieces. Large arguments are split between
4512 registers and stack. */
4513 /* Note: structs whose size is not a multiple of
4514 mips_abi_regsize() are treated specially: Irix cc passes
4515 them in registers where gcc sometimes puts them on the
4516 stack. For maximum compatibility, we will put them in
4518 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4519 && (len
% mips_abi_regsize (gdbarch
) != 0));
4520 /* Structures should be aligned to eight bytes (even arg registers)
4521 on MIPS_ABI_O32, if their first member has double precision. */
4522 if (mips_abi_regsize (gdbarch
) < 8
4523 && mips_type_needs_double_align (arg_type
))
4528 /* Note: Floating-point values that didn't fit into an FP
4529 register are only written to memory. */
4532 /* Remember if the argument was written to the stack. */
4533 int stack_used_p
= 0;
4534 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4535 ? len
: mips_abi_regsize (gdbarch
));
4538 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4541 /* Write this portion of the argument to the stack. */
4542 if (argreg
> MIPS_LAST_ARG_REGNUM
4544 || fp_register_arg_p (typecode
, arg_type
))
4546 /* Should shorter than int integer values be
4547 promoted to int before being stored? */
4548 int longword_offset
= 0;
4551 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4553 if (mips_stack_argsize (gdbarch
) == 8
4554 && (typecode
== TYPE_CODE_INT
4555 || typecode
== TYPE_CODE_PTR
4556 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4557 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4562 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4563 paddr_nz (stack_offset
));
4564 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4565 paddr_nz (longword_offset
));
4568 addr
= sp
+ stack_offset
+ longword_offset
;
4573 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4575 for (i
= 0; i
< partial_len
; i
++)
4577 fprintf_unfiltered (gdb_stdlog
, "%02x",
4581 write_memory (addr
, val
, partial_len
);
4584 /* Note!!! This is NOT an else clause. Odd sized
4585 structs may go thru BOTH paths. Floating point
4586 arguments will not. */
4587 /* Write this portion of the argument to a general
4588 purpose register. */
4589 if (argreg
<= MIPS_LAST_ARG_REGNUM
4590 && !fp_register_arg_p (typecode
, arg_type
))
4592 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4593 /* Value may need to be sign extended, because
4594 mips_isa_regsize() != mips_abi_regsize(). */
4596 /* A non-floating-point argument being passed in a
4597 general register. If a struct or union, and if
4598 the remaining length is smaller than the register
4599 size, we have to adjust the register value on
4602 It does not seem to be necessary to do the
4603 same for integral types.
4605 Also don't do this adjustment on O64 binaries.
4607 cagney/2001-07-23: gdb/179: Also, GCC, when
4608 outputting LE O32 with sizeof (struct) <
4609 mips_abi_regsize(), generates a left shift as
4610 part of storing the argument in a register a
4611 register (the left shift isn't generated when
4612 sizeof (struct) >= mips_abi_regsize()). Since
4613 it is quite possible that this is GCC
4614 contradicting the LE/O32 ABI, GDB has not been
4615 adjusted to accommodate this. Either someone
4616 needs to demonstrate that the LE/O32 ABI
4617 specifies such a left shift OR this new ABI gets
4618 identified as such and GDB gets tweaked
4621 if (mips_abi_regsize (gdbarch
) < 8
4622 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4623 && partial_len
< mips_abi_regsize (gdbarch
)
4624 && (typecode
== TYPE_CODE_STRUCT
||
4625 typecode
== TYPE_CODE_UNION
))
4626 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4630 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4633 mips_abi_regsize (gdbarch
)));
4634 write_register (argreg
, regval
);
4637 /* Prevent subsequent floating point arguments from
4638 being passed in floating point registers. */
4639 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4645 /* Compute the the offset into the stack at which we
4646 will copy the next parameter.
4648 In older ABIs, the caller reserved space for
4649 registers that contained arguments. This was loosely
4650 refered to as their "home". Consequently, space is
4651 always allocated. */
4653 stack_offset
+= align_up (partial_len
,
4654 mips_stack_argsize (gdbarch
));
4658 fprintf_unfiltered (gdb_stdlog
, "\n");
4661 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4663 /* Return adjusted stack pointer. */
4668 mips_o64_extract_return_value (struct type
*valtype
,
4669 char regbuf
[], char *valbuf
)
4671 struct return_value_word lo
;
4672 struct return_value_word hi
;
4673 return_value_location (valtype
, &hi
, &lo
);
4675 memcpy (valbuf
+ lo
.buf_offset
,
4676 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4677 lo
.reg_offset
, lo
.len
);
4680 memcpy (valbuf
+ hi
.buf_offset
,
4681 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4682 hi
.reg_offset
, hi
.len
);
4686 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4688 char raw_buffer
[MAX_REGISTER_SIZE
];
4689 struct return_value_word lo
;
4690 struct return_value_word hi
;
4691 return_value_location (valtype
, &hi
, &lo
);
4693 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4694 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4695 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4696 raw_buffer
, register_size (current_gdbarch
,
4701 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4702 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4703 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4705 register_size (current_gdbarch
,
4710 /* Floating point register management.
4712 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4713 64bit operations, these early MIPS cpus treat fp register pairs
4714 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4715 registers and offer a compatibility mode that emulates the MIPS2 fp
4716 model. When operating in MIPS2 fp compat mode, later cpu's split
4717 double precision floats into two 32-bit chunks and store them in
4718 consecutive fp regs. To display 64-bit floats stored in this
4719 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4720 Throw in user-configurable endianness and you have a real mess.
4722 The way this works is:
4723 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4724 double-precision value will be split across two logical registers.
4725 The lower-numbered logical register will hold the low-order bits,
4726 regardless of the processor's endianness.
4727 - If we are on a 64-bit processor, and we are looking for a
4728 single-precision value, it will be in the low ordered bits
4729 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4730 save slot in memory.
4731 - If we are in 64-bit mode, everything is straightforward.
4733 Note that this code only deals with "live" registers at the top of the
4734 stack. We will attempt to deal with saved registers later, when
4735 the raw/cooked register interface is in place. (We need a general
4736 interface that can deal with dynamic saved register sizes -- fp
4737 regs could be 32 bits wide in one frame and 64 on the frame above
4740 static struct type
*
4741 mips_float_register_type (void)
4743 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4744 return builtin_type_ieee_single_big
;
4746 return builtin_type_ieee_single_little
;
4749 static struct type
*
4750 mips_double_register_type (void)
4752 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4753 return builtin_type_ieee_double_big
;
4755 return builtin_type_ieee_double_little
;
4758 /* Copy a 32-bit single-precision value from the current frame
4759 into rare_buffer. */
4762 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4765 int raw_size
= register_size (current_gdbarch
, regno
);
4766 char *raw_buffer
= alloca (raw_size
);
4768 if (!frame_register_read (frame
, regno
, raw_buffer
))
4769 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4772 /* We have a 64-bit value for this register. Find the low-order
4776 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4781 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4785 memcpy (rare_buffer
, raw_buffer
, 4);
4789 /* Copy a 64-bit double-precision value from the current frame into
4790 rare_buffer. This may include getting half of it from the next
4794 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4797 int raw_size
= register_size (current_gdbarch
, regno
);
4799 if (raw_size
== 8 && !mips2_fp_compat ())
4801 /* We have a 64-bit value for this register, and we should use
4803 if (!frame_register_read (frame
, regno
, rare_buffer
))
4804 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4808 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4809 internal_error (__FILE__
, __LINE__
,
4810 "mips_read_fp_register_double: bad access to "
4811 "odd-numbered FP register");
4813 /* mips_read_fp_register_single will find the correct 32 bits from
4815 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4817 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4818 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4822 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4823 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4829 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4831 { /* do values for FP (float) regs */
4833 double doub
, flt1
; /* doubles extracted from raw hex data */
4837 (char *) alloca (2 *
4838 register_size (current_gdbarch
,
4839 mips_regnum (current_gdbarch
)->fp0
));
4841 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4842 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4845 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4847 /* 4-byte registers: Print hex and floating. Also print even
4848 numbered registers as doubles. */
4849 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4850 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4852 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4855 fprintf_filtered (file
, " flt: ");
4857 fprintf_filtered (file
, " <invalid float> ");
4859 fprintf_filtered (file
, "%-17.9g", flt1
);
4861 if (regnum
% 2 == 0)
4863 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4864 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4867 fprintf_filtered (file
, " dbl: ");
4869 fprintf_filtered (file
, "<invalid double>");
4871 fprintf_filtered (file
, "%-24.17g", doub
);
4876 /* Eight byte registers: print each one as hex, float and double. */
4877 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4878 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4880 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4881 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4884 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4887 fprintf_filtered (file
, " flt: ");
4889 fprintf_filtered (file
, "<invalid float>");
4891 fprintf_filtered (file
, "%-17.9g", flt1
);
4893 fprintf_filtered (file
, " dbl: ");
4895 fprintf_filtered (file
, "<invalid double>");
4897 fprintf_filtered (file
, "%-24.17g", doub
);
4902 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4903 int regnum
, int all
)
4905 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4906 char raw_buffer
[MAX_REGISTER_SIZE
];
4909 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4911 mips_print_fp_register (file
, frame
, regnum
);
4915 /* Get the data in raw format. */
4916 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4918 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4922 fputs_filtered (REGISTER_NAME (regnum
), file
);
4924 /* The problem with printing numeric register names (r26, etc.) is that
4925 the user can't use them on input. Probably the best solution is to
4926 fix it so that either the numeric or the funky (a2, etc.) names
4927 are accepted on input. */
4928 if (regnum
< MIPS_NUMREGS
)
4929 fprintf_filtered (file
, "(r%d): ", regnum
);
4931 fprintf_filtered (file
, ": ");
4933 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4935 register_size (current_gdbarch
,
4936 regnum
) - register_size (current_gdbarch
, regnum
);
4940 print_scalar_formatted (raw_buffer
+ offset
,
4941 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4945 /* Replacement for generic do_registers_info.
4946 Print regs in pretty columns. */
4949 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4952 fprintf_filtered (file
, " ");
4953 mips_print_fp_register (file
, frame
, regnum
);
4954 fprintf_filtered (file
, "\n");
4959 /* Print a row's worth of GP (int) registers, with name labels above */
4962 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4965 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4966 /* do values for GP (int) regs */
4967 char raw_buffer
[MAX_REGISTER_SIZE
];
4968 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4972 /* For GP registers, we print a separate row of names above the vals */
4973 fprintf_filtered (file
, " ");
4974 for (col
= 0, regnum
= start_regnum
;
4975 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4977 if (*REGISTER_NAME (regnum
) == '\0')
4978 continue; /* unused register */
4979 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4981 break; /* end the row: reached FP register */
4982 fprintf_filtered (file
,
4983 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4984 REGISTER_NAME (regnum
));
4987 /* print the R0 to R31 names */
4988 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4989 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4991 fprintf_filtered (file
, "\n ");
4993 /* now print the values in hex, 4 or 8 to the row */
4994 for (col
= 0, regnum
= start_regnum
;
4995 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4997 if (*REGISTER_NAME (regnum
) == '\0')
4998 continue; /* unused register */
4999 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5001 break; /* end row: reached FP register */
5002 /* OK: get the data in raw format. */
5003 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5004 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
5005 /* pad small registers */
5007 byte
< (mips_abi_regsize (current_gdbarch
)
5008 - register_size (current_gdbarch
, regnum
)); byte
++)
5009 printf_filtered (" ");
5010 /* Now print the register value in hex, endian order. */
5011 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5013 register_size (current_gdbarch
,
5014 regnum
) - register_size (current_gdbarch
, regnum
);
5015 byte
< register_size (current_gdbarch
, regnum
); byte
++)
5016 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5018 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
5020 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5021 fprintf_filtered (file
, " ");
5024 if (col
> 0) /* ie. if we actually printed anything... */
5025 fprintf_filtered (file
, "\n");
5030 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
5033 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
5034 struct frame_info
*frame
, int regnum
, int all
)
5036 if (regnum
!= -1) /* do one specified register */
5038 gdb_assert (regnum
>= NUM_REGS
);
5039 if (*(REGISTER_NAME (regnum
)) == '\0')
5040 error ("Not a valid register for the current processor type");
5042 mips_print_register (file
, frame
, regnum
, 0);
5043 fprintf_filtered (file
, "\n");
5046 /* do all (or most) registers */
5049 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
5051 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5054 if (all
) /* true for "INFO ALL-REGISTERS" command */
5055 regnum
= print_fp_register_row (file
, frame
, regnum
);
5057 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
5060 regnum
= print_gp_register_row (file
, frame
, regnum
);
5065 /* Is this a branch with a delay slot? */
5067 static int is_delayed (unsigned long);
5070 is_delayed (unsigned long insn
)
5073 for (i
= 0; i
< NUMOPCODES
; ++i
)
5074 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
5075 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
5077 return (i
< NUMOPCODES
5078 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
5079 | INSN_COND_BRANCH_DELAY
5080 | INSN_COND_BRANCH_LIKELY
)));
5084 mips_step_skips_delay (CORE_ADDR pc
)
5086 char buf
[MIPS_INSTLEN
];
5088 /* There is no branch delay slot on MIPS16. */
5089 if (pc_is_mips16 (pc
))
5092 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
5093 /* If error reading memory, guess that it is not a delayed branch. */
5095 return is_delayed ((unsigned long)
5096 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
5099 /* Skip the PC past function prologue instructions (32-bit version).
5100 This is a helper function for mips_skip_prologue. */
5103 mips32_skip_prologue (CORE_ADDR pc
)
5107 int seen_sp_adjust
= 0;
5108 int load_immediate_bytes
= 0;
5110 /* Find an upper bound on the prologue. */
5111 end_pc
= skip_prologue_using_sal (pc
);
5113 end_pc
= pc
+ 100; /* Magic. */
5115 /* Skip the typical prologue instructions. These are the stack adjustment
5116 instruction and the instructions that save registers on the stack
5117 or in the gcc frame. */
5118 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
5120 unsigned long high_word
;
5122 inst
= mips_fetch_instruction (pc
);
5123 high_word
= (inst
>> 16) & 0xffff;
5125 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
5126 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
5128 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
5129 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
5131 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
5132 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
5133 && (inst
& 0x001F0000)) /* reg != $zero */
5136 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
5138 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
5140 continue; /* reg != $zero */
5142 /* move $s8,$sp. With different versions of gas this will be either
5143 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
5144 Accept any one of these. */
5145 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
5148 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
5150 else if (high_word
== 0x3c1c) /* lui $gp,n */
5152 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
5154 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
5155 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
5157 /* The following instructions load $at or $t0 with an immediate
5158 value in preparation for a stack adjustment via
5159 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
5160 a local variable, so we accept them only before a stack adjustment
5161 instruction was seen. */
5162 else if (!seen_sp_adjust
)
5164 if (high_word
== 0x3c01 || /* lui $at,n */
5165 high_word
== 0x3c08) /* lui $t0,n */
5167 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5170 else if (high_word
== 0x3421 || /* ori $at,$at,n */
5171 high_word
== 0x3508 || /* ori $t0,$t0,n */
5172 high_word
== 0x3401 || /* ori $at,$zero,n */
5173 high_word
== 0x3408) /* ori $t0,$zero,n */
5175 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5185 /* In a frameless function, we might have incorrectly
5186 skipped some load immediate instructions. Undo the skipping
5187 if the load immediate was not followed by a stack adjustment. */
5188 if (load_immediate_bytes
&& !seen_sp_adjust
)
5189 pc
-= load_immediate_bytes
;
5193 /* Skip the PC past function prologue instructions (16-bit version).
5194 This is a helper function for mips_skip_prologue. */
5197 mips16_skip_prologue (CORE_ADDR pc
)
5200 int extend_bytes
= 0;
5201 int prev_extend_bytes
;
5203 /* Table of instructions likely to be found in a function prologue. */
5206 unsigned short inst
;
5207 unsigned short mask
;
5213 , /* addiu $sp,offset */
5216 , /* daddiu $sp,offset */
5219 , /* sw reg,n($sp) */
5222 , /* sd reg,n($sp) */
5225 , /* sw $ra,n($sp) */
5228 , /* sd $ra,n($sp) */
5234 , /* sw $a0-$a3,n($s1) */
5237 , /* move reg,$a0-$a3 */
5240 , /* entry pseudo-op */
5243 , /* addiu $s1,$sp,n */
5245 0, 0} /* end of table marker */
5248 /* Find an upper bound on the prologue. */
5249 end_pc
= skip_prologue_using_sal (pc
);
5251 end_pc
= pc
+ 100; /* Magic. */
5253 /* Skip the typical prologue instructions. These are the stack adjustment
5254 instruction and the instructions that save registers on the stack
5255 or in the gcc frame. */
5256 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
5258 unsigned short inst
;
5261 inst
= mips_fetch_instruction (pc
);
5263 /* Normally we ignore an extend instruction. However, if it is
5264 not followed by a valid prologue instruction, we must adjust
5265 the pc back over the extend so that it won't be considered
5266 part of the prologue. */
5267 if ((inst
& 0xf800) == 0xf000) /* extend */
5269 extend_bytes
= MIPS16_INSTLEN
;
5272 prev_extend_bytes
= extend_bytes
;
5275 /* Check for other valid prologue instructions besides extend. */
5276 for (i
= 0; table
[i
].mask
!= 0; i
++)
5277 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
5279 if (table
[i
].mask
!= 0) /* it was in table? */
5280 continue; /* ignore it */
5284 /* Return the current pc, adjusted backwards by 2 if
5285 the previous instruction was an extend. */
5286 return pc
- prev_extend_bytes
;
5292 /* To skip prologues, I use this predicate. Returns either PC itself
5293 if the code at PC does not look like a function prologue; otherwise
5294 returns an address that (if we're lucky) follows the prologue. If
5295 LENIENT, then we must skip everything which is involved in setting
5296 up the frame (it's OK to skip more, just so long as we don't skip
5297 anything which might clobber the registers which are being saved.
5298 We must skip more in the case where part of the prologue is in the
5299 delay slot of a non-prologue instruction). */
5302 mips_skip_prologue (CORE_ADDR pc
)
5304 /* See if we can determine the end of the prologue via the symbol table.
5305 If so, then return either PC, or the PC after the prologue, whichever
5308 CORE_ADDR post_prologue_pc
= after_prologue (pc
);
5310 if (post_prologue_pc
!= 0)
5311 return max (pc
, post_prologue_pc
);
5313 /* Can't determine prologue from the symbol table, need to examine
5316 if (pc_is_mips16 (pc
))
5317 return mips16_skip_prologue (pc
);
5319 return mips32_skip_prologue (pc
);
5322 /* Root of all "set mips "/"show mips " commands. This will eventually be
5323 used for all MIPS-specific commands. */
5326 show_mips_command (char *args
, int from_tty
)
5328 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5332 set_mips_command (char *args
, int from_tty
)
5335 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5336 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5339 /* Commands to show/set the MIPS FPU type. */
5342 show_mipsfpu_command (char *args
, int from_tty
)
5345 switch (MIPS_FPU_TYPE
)
5347 case MIPS_FPU_SINGLE
:
5348 fpu
= "single-precision";
5350 case MIPS_FPU_DOUBLE
:
5351 fpu
= "double-precision";
5354 fpu
= "absent (none)";
5357 internal_error (__FILE__
, __LINE__
, "bad switch");
5359 if (mips_fpu_type_auto
)
5361 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5365 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5370 set_mipsfpu_command (char *args
, int from_tty
)
5373 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5374 show_mipsfpu_command (args
, from_tty
);
5378 set_mipsfpu_single_command (char *args
, int from_tty
)
5380 struct gdbarch_info info
;
5381 gdbarch_info_init (&info
);
5382 mips_fpu_type
= MIPS_FPU_SINGLE
;
5383 mips_fpu_type_auto
= 0;
5384 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5385 instead of relying on globals. Doing that would let generic code
5386 handle the search for this specific architecture. */
5387 if (!gdbarch_update_p (info
))
5388 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5392 set_mipsfpu_double_command (char *args
, int from_tty
)
5394 struct gdbarch_info info
;
5395 gdbarch_info_init (&info
);
5396 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5397 mips_fpu_type_auto
= 0;
5398 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5399 instead of relying on globals. Doing that would let generic code
5400 handle the search for this specific architecture. */
5401 if (!gdbarch_update_p (info
))
5402 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5406 set_mipsfpu_none_command (char *args
, int from_tty
)
5408 struct gdbarch_info info
;
5409 gdbarch_info_init (&info
);
5410 mips_fpu_type
= MIPS_FPU_NONE
;
5411 mips_fpu_type_auto
= 0;
5412 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5413 instead of relying on globals. Doing that would let generic code
5414 handle the search for this specific architecture. */
5415 if (!gdbarch_update_p (info
))
5416 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5420 set_mipsfpu_auto_command (char *args
, int from_tty
)
5422 mips_fpu_type_auto
= 1;
5425 /* Attempt to identify the particular processor model by reading the
5426 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5427 the relevant processor still exists (it dates back to '94) and
5428 secondly this is not the way to do this. The processor type should
5429 be set by forcing an architecture change. */
5432 deprecated_mips_set_processor_regs_hack (void)
5434 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5437 prid
= read_register (PRID_REGNUM
);
5439 if ((prid
& ~0xf) == 0x700)
5440 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5443 /* Just like reinit_frame_cache, but with the right arguments to be
5444 callable as an sfunc. */
5447 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5448 struct cmd_list_element
*c
)
5450 reinit_frame_cache ();
5454 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5456 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5457 mips_extra_func_info_t proc_desc
;
5459 /* Search for the function containing this address. Set the low bit
5460 of the address when searching, in case we were given an even address
5461 that is the start of a 16-bit function. If we didn't do this,
5462 the search would fail because the symbol table says the function
5463 starts at an odd address, i.e. 1 byte past the given address. */
5464 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5465 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5467 /* Make an attempt to determine if this is a 16-bit function. If
5468 the procedure descriptor exists and the address therein is odd,
5469 it's definitely a 16-bit function. Otherwise, we have to just
5470 guess that if the address passed in is odd, it's 16-bits. */
5471 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5472 disassembler needs to be able to locally determine the ISA, and
5473 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5477 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5478 info
->mach
= bfd_mach_mips16
;
5482 if (pc_is_mips16 (memaddr
))
5483 info
->mach
= bfd_mach_mips16
;
5486 /* Round down the instruction address to the appropriate boundary. */
5487 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5489 /* Set the disassembler options. */
5490 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5492 /* Set up the disassembler info, so that we get the right
5493 register names from libopcodes. */
5494 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5495 info
->disassembler_options
= "gpr-names=n32";
5497 info
->disassembler_options
= "gpr-names=64";
5498 info
->flavour
= bfd_target_elf_flavour
;
5501 /* This string is not recognized explicitly by the disassembler,
5502 but it tells the disassembler to not try to guess the ABI from
5503 the bfd elf headers, such that, if the user overrides the ABI
5504 of a program linked as NewABI, the disassembly will follow the
5505 register naming conventions specified by the user. */
5506 info
->disassembler_options
= "gpr-names=32";
5508 /* Call the appropriate disassembler based on the target endian-ness. */
5509 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5510 return print_insn_big_mips (memaddr
, info
);
5512 return print_insn_little_mips (memaddr
, info
);
5515 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5516 counter value to determine whether a 16- or 32-bit breakpoint should be
5517 used. It returns a pointer to a string of bytes that encode a breakpoint
5518 instruction, stores the length of the string to *lenptr, and adjusts pc
5519 (if necessary) to point to the actual memory location where the
5520 breakpoint should be inserted. */
5522 static const unsigned char *
5523 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5525 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5527 if (pc_is_mips16 (*pcptr
))
5529 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5530 *pcptr
= unmake_mips16_addr (*pcptr
);
5531 *lenptr
= sizeof (mips16_big_breakpoint
);
5532 return mips16_big_breakpoint
;
5536 /* The IDT board uses an unusual breakpoint value, and
5537 sometimes gets confused when it sees the usual MIPS
5538 breakpoint instruction. */
5539 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5540 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5541 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5543 *lenptr
= sizeof (big_breakpoint
);
5545 if (strcmp (target_shortname
, "mips") == 0)
5546 return idt_big_breakpoint
;
5547 else if (strcmp (target_shortname
, "ddb") == 0
5548 || strcmp (target_shortname
, "pmon") == 0
5549 || strcmp (target_shortname
, "lsi") == 0)
5550 return pmon_big_breakpoint
;
5552 return big_breakpoint
;
5557 if (pc_is_mips16 (*pcptr
))
5559 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5560 *pcptr
= unmake_mips16_addr (*pcptr
);
5561 *lenptr
= sizeof (mips16_little_breakpoint
);
5562 return mips16_little_breakpoint
;
5566 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5567 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5568 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5570 *lenptr
= sizeof (little_breakpoint
);
5572 if (strcmp (target_shortname
, "mips") == 0)
5573 return idt_little_breakpoint
;
5574 else if (strcmp (target_shortname
, "ddb") == 0
5575 || strcmp (target_shortname
, "pmon") == 0
5576 || strcmp (target_shortname
, "lsi") == 0)
5577 return pmon_little_breakpoint
;
5579 return little_breakpoint
;
5584 /* If PC is in a mips16 call or return stub, return the address of the target
5585 PC, which is either the callee or the caller. There are several
5586 cases which must be handled:
5588 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5589 target PC is in $31 ($ra).
5590 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5591 and the target PC is in $2.
5592 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5593 before the jal instruction, this is effectively a call stub
5594 and the the target PC is in $2. Otherwise this is effectively
5595 a return stub and the target PC is in $18.
5597 See the source code for the stubs in gcc/config/mips/mips16.S for
5600 This function implements the SKIP_TRAMPOLINE_CODE macro.
5604 mips_skip_stub (CORE_ADDR pc
)
5607 CORE_ADDR start_addr
;
5609 /* Find the starting address and name of the function containing the PC. */
5610 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5613 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5614 target PC is in $31 ($ra). */
5615 if (strcmp (name
, "__mips16_ret_sf") == 0
5616 || strcmp (name
, "__mips16_ret_df") == 0)
5617 return read_signed_register (RA_REGNUM
);
5619 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5621 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5622 and the target PC is in $2. */
5623 if (name
[19] >= '0' && name
[19] <= '9')
5624 return read_signed_register (2);
5626 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5627 before the jal instruction, this is effectively a call stub
5628 and the the target PC is in $2. Otherwise this is effectively
5629 a return stub and the target PC is in $18. */
5630 else if (name
[19] == 's' || name
[19] == 'd')
5632 if (pc
== start_addr
)
5634 /* Check if the target of the stub is a compiler-generated
5635 stub. Such a stub for a function bar might have a name
5636 like __fn_stub_bar, and might look like this:
5641 la $1,bar (becomes a lui/addiu pair)
5643 So scan down to the lui/addi and extract the target
5644 address from those two instructions. */
5646 CORE_ADDR target_pc
= read_signed_register (2);
5650 /* See if the name of the target function is __fn_stub_*. */
5651 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5654 if (strncmp (name
, "__fn_stub_", 10) != 0
5655 && strcmp (name
, "etext") != 0
5656 && strcmp (name
, "_etext") != 0)
5659 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5660 The limit on the search is arbitrarily set to 20
5661 instructions. FIXME. */
5662 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5664 inst
= mips_fetch_instruction (target_pc
);
5665 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5666 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5667 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5668 return pc
| (inst
& 0xffff); /* low word */
5671 /* Couldn't find the lui/addui pair, so return stub address. */
5675 /* This is the 'return' part of a call stub. The return
5676 address is in $r18. */
5677 return read_signed_register (18);
5680 return 0; /* not a stub */
5684 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5685 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5688 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5690 CORE_ADDR start_addr
;
5692 /* Find the starting address of the function containing the PC. If the
5693 caller didn't give us a name, look it up at the same time. */
5694 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5698 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5700 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5701 if (name
[19] >= '0' && name
[19] <= '9')
5703 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5704 before the jal instruction, this is effectively a call stub. */
5705 else if (name
[19] == 's' || name
[19] == 'd')
5706 return pc
== start_addr
;
5709 return 0; /* not a stub */
5713 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5714 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5717 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5719 CORE_ADDR start_addr
;
5721 /* Find the starting address of the function containing the PC. */
5722 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5725 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5726 if (strcmp (name
, "__mips16_ret_sf") == 0
5727 || strcmp (name
, "__mips16_ret_df") == 0)
5730 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5731 i.e. after the jal instruction, this is effectively a return stub. */
5732 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5733 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5736 return 0; /* not a stub */
5740 /* Return non-zero if the PC is in a library helper function that
5741 should be ignored. This implements the
5742 DEPRECATED_IGNORE_HELPER_CALL macro. */
5745 mips_ignore_helper (CORE_ADDR pc
)
5749 /* Find the starting address and name of the function containing the PC. */
5750 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5753 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5754 that we want to ignore. */
5755 return (strcmp (name
, "__mips16_ret_sf") == 0
5756 || strcmp (name
, "__mips16_ret_df") == 0);
5760 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5761 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5764 mips_stab_reg_to_regnum (int num
)
5767 if (num
>= 0 && num
< 32)
5769 else if (num
>= 38 && num
< 70)
5770 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5772 regnum
= mips_regnum (current_gdbarch
)->hi
;
5774 regnum
= mips_regnum (current_gdbarch
)->lo
;
5776 /* This will hopefully (eventually) provoke a warning. Should
5777 we be calling complaint() here? */
5778 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5779 return NUM_REGS
+ regnum
;
5783 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5784 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5787 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5790 if (num
>= 0 && num
< 32)
5792 else if (num
>= 32 && num
< 64)
5793 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5795 regnum
= mips_regnum (current_gdbarch
)->hi
;
5797 regnum
= mips_regnum (current_gdbarch
)->lo
;
5799 /* This will hopefully (eventually) provoke a warning. Should we
5800 be calling complaint() here? */
5801 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5802 return NUM_REGS
+ regnum
;
5806 mips_register_sim_regno (int regnum
)
5808 /* Only makes sense to supply raw registers. */
5809 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5810 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5811 decide if it is valid. Should instead define a standard sim/gdb
5812 register numbering scheme. */
5813 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5814 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5817 return LEGACY_SIM_REGNO_IGNORE
;
5821 /* Convert an integer into an address. By first converting the value
5822 into a pointer and then extracting it signed, the address is
5823 guarenteed to be correctly sign extended. */
5826 mips_integer_to_address (struct type
*type
, void *buf
)
5828 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5829 LONGEST val
= unpack_long (type
, buf
);
5830 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5831 return extract_signed_integer (tmp
,
5832 TYPE_LENGTH (builtin_type_void_data_ptr
));
5836 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5838 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5839 const char *name
= bfd_get_section_name (abfd
, sect
);
5841 if (*abip
!= MIPS_ABI_UNKNOWN
)
5844 if (strncmp (name
, ".mdebug.", 8) != 0)
5847 if (strcmp (name
, ".mdebug.abi32") == 0)
5848 *abip
= MIPS_ABI_O32
;
5849 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5850 *abip
= MIPS_ABI_N32
;
5851 else if (strcmp (name
, ".mdebug.abi64") == 0)
5852 *abip
= MIPS_ABI_N64
;
5853 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5854 *abip
= MIPS_ABI_O64
;
5855 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5856 *abip
= MIPS_ABI_EABI32
;
5857 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5858 *abip
= MIPS_ABI_EABI64
;
5860 warning ("unsupported ABI %s.", name
+ 8);
5863 static enum mips_abi
5864 global_mips_abi (void)
5868 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5869 if (mips_abi_strings
[i
] == mips_abi_string
)
5870 return (enum mips_abi
) i
;
5872 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5875 static struct gdbarch
*
5876 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5878 struct gdbarch
*gdbarch
;
5879 struct gdbarch_tdep
*tdep
;
5881 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5883 enum mips_fpu_type fpu_type
;
5885 /* First of all, extract the elf_flags, if available. */
5886 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5887 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5888 else if (arches
!= NULL
)
5889 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5893 fprintf_unfiltered (gdb_stdlog
,
5894 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5896 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5897 switch ((elf_flags
& EF_MIPS_ABI
))
5899 case E_MIPS_ABI_O32
:
5900 found_abi
= MIPS_ABI_O32
;
5902 case E_MIPS_ABI_O64
:
5903 found_abi
= MIPS_ABI_O64
;
5905 case E_MIPS_ABI_EABI32
:
5906 found_abi
= MIPS_ABI_EABI32
;
5908 case E_MIPS_ABI_EABI64
:
5909 found_abi
= MIPS_ABI_EABI64
;
5912 if ((elf_flags
& EF_MIPS_ABI2
))
5913 found_abi
= MIPS_ABI_N32
;
5915 found_abi
= MIPS_ABI_UNKNOWN
;
5919 /* GCC creates a pseudo-section whose name describes the ABI. */
5920 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5921 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5923 /* If we have no useful BFD information, use the ABI from the last
5924 MIPS architecture (if there is one). */
5925 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5926 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5928 /* Try the architecture for any hint of the correct ABI. */
5929 if (found_abi
== MIPS_ABI_UNKNOWN
5930 && info
.bfd_arch_info
!= NULL
5931 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5933 switch (info
.bfd_arch_info
->mach
)
5935 case bfd_mach_mips3900
:
5936 found_abi
= MIPS_ABI_EABI32
;
5938 case bfd_mach_mips4100
:
5939 case bfd_mach_mips5000
:
5940 found_abi
= MIPS_ABI_EABI64
;
5942 case bfd_mach_mips8000
:
5943 case bfd_mach_mips10000
:
5944 /* On Irix, ELF64 executables use the N64 ABI. The
5945 pseudo-sections which describe the ABI aren't present
5946 on IRIX. (Even for executables created by gcc.) */
5947 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5948 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5949 found_abi
= MIPS_ABI_N64
;
5951 found_abi
= MIPS_ABI_N32
;
5957 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5960 /* What has the user specified from the command line? */
5961 wanted_abi
= global_mips_abi ();
5963 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5966 /* Now that we have found what the ABI for this binary would be,
5967 check whether the user is overriding it. */
5968 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5969 mips_abi
= wanted_abi
;
5970 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5971 mips_abi
= found_abi
;
5973 mips_abi
= MIPS_ABI_O32
;
5975 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5978 /* Also used when doing an architecture lookup. */
5980 fprintf_unfiltered (gdb_stdlog
,
5981 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5982 mips64_transfers_32bit_regs_p
);
5984 /* Determine the MIPS FPU type. */
5985 if (!mips_fpu_type_auto
)
5986 fpu_type
= mips_fpu_type
;
5987 else if (info
.bfd_arch_info
!= NULL
5988 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5989 switch (info
.bfd_arch_info
->mach
)
5991 case bfd_mach_mips3900
:
5992 case bfd_mach_mips4100
:
5993 case bfd_mach_mips4111
:
5994 case bfd_mach_mips4120
:
5995 fpu_type
= MIPS_FPU_NONE
;
5997 case bfd_mach_mips4650
:
5998 fpu_type
= MIPS_FPU_SINGLE
;
6001 fpu_type
= MIPS_FPU_DOUBLE
;
6004 else if (arches
!= NULL
)
6005 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6007 fpu_type
= MIPS_FPU_DOUBLE
;
6009 fprintf_unfiltered (gdb_stdlog
,
6010 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6012 /* try to find a pre-existing architecture */
6013 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6015 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6017 /* MIPS needs to be pedantic about which ABI the object is
6019 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6021 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6023 /* Need to be pedantic about which register virtual size is
6025 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6026 != mips64_transfers_32bit_regs_p
)
6028 /* Be pedantic about which FPU is selected. */
6029 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6031 return arches
->gdbarch
;
6034 /* Need a new architecture. Fill in a target specific vector. */
6035 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6036 gdbarch
= gdbarch_alloc (&info
, tdep
);
6037 tdep
->elf_flags
= elf_flags
;
6038 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6039 tdep
->found_abi
= found_abi
;
6040 tdep
->mips_abi
= mips_abi
;
6041 tdep
->mips_fpu_type
= fpu_type
;
6043 /* Initially set everything according to the default ABI/ISA. */
6044 set_gdbarch_short_bit (gdbarch
, 16);
6045 set_gdbarch_int_bit (gdbarch
, 32);
6046 set_gdbarch_float_bit (gdbarch
, 32);
6047 set_gdbarch_double_bit (gdbarch
, 64);
6048 set_gdbarch_long_double_bit (gdbarch
, 64);
6049 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6050 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6051 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6053 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6054 mips_elf_make_msymbol_special
);
6056 /* Fill in the OS dependant register numbers and names. */
6058 const char **reg_names
;
6059 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
6060 struct mips_regnum
);
6061 if (info
.osabi
== GDB_OSABI_IRIX
)
6066 regnum
->badvaddr
= 66;
6069 regnum
->fp_control_status
= 69;
6070 regnum
->fp_implementation_revision
= 70;
6072 reg_names
= mips_irix_reg_names
;
6076 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6077 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6078 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6079 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6080 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6081 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6082 regnum
->fp_control_status
= 70;
6083 regnum
->fp_implementation_revision
= 71;
6085 if (info
.bfd_arch_info
!= NULL
6086 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6087 reg_names
= mips_tx39_reg_names
;
6089 reg_names
= mips_generic_reg_names
;
6091 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
6092 replaced by read_pc? */
6093 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6094 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6095 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6096 set_gdbarch_num_regs (gdbarch
, num_regs
);
6097 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6098 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6099 tdep
->mips_processor_reg_names
= reg_names
;
6100 tdep
->regnum
= regnum
;
6106 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6107 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6108 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6109 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6110 tdep
->default_mask_address_p
= 0;
6111 set_gdbarch_long_bit (gdbarch
, 32);
6112 set_gdbarch_ptr_bit (gdbarch
, 32);
6113 set_gdbarch_long_long_bit (gdbarch
, 64);
6116 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6117 set_gdbarch_deprecated_store_return_value (gdbarch
,
6118 mips_o64_store_return_value
);
6119 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6120 mips_o64_extract_return_value
);
6121 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6122 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6123 tdep
->default_mask_address_p
= 0;
6124 set_gdbarch_long_bit (gdbarch
, 32);
6125 set_gdbarch_ptr_bit (gdbarch
, 32);
6126 set_gdbarch_long_long_bit (gdbarch
, 64);
6127 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
6129 case MIPS_ABI_EABI32
:
6130 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6131 set_gdbarch_deprecated_store_return_value (gdbarch
,
6132 mips_eabi_store_return_value
);
6133 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6134 mips_eabi_extract_return_value
);
6135 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6136 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6137 tdep
->default_mask_address_p
= 0;
6138 set_gdbarch_long_bit (gdbarch
, 32);
6139 set_gdbarch_ptr_bit (gdbarch
, 32);
6140 set_gdbarch_long_long_bit (gdbarch
, 64);
6141 set_gdbarch_deprecated_reg_struct_has_addr
6142 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6143 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6145 case MIPS_ABI_EABI64
:
6146 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6147 set_gdbarch_deprecated_store_return_value (gdbarch
,
6148 mips_eabi_store_return_value
);
6149 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6150 mips_eabi_extract_return_value
);
6151 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6152 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6153 tdep
->default_mask_address_p
= 0;
6154 set_gdbarch_long_bit (gdbarch
, 64);
6155 set_gdbarch_ptr_bit (gdbarch
, 64);
6156 set_gdbarch_long_long_bit (gdbarch
, 64);
6157 set_gdbarch_deprecated_reg_struct_has_addr
6158 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6159 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6162 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6163 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6164 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6165 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6166 tdep
->default_mask_address_p
= 0;
6167 set_gdbarch_long_bit (gdbarch
, 32);
6168 set_gdbarch_ptr_bit (gdbarch
, 32);
6169 set_gdbarch_long_long_bit (gdbarch
, 64);
6170 set_gdbarch_long_double_bit (gdbarch
, 128);
6171 set_gdbarch_long_double_format (gdbarch
,
6172 &floatformat_n32n64_long_double_big
);
6175 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6176 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6177 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6178 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6179 tdep
->default_mask_address_p
= 0;
6180 set_gdbarch_long_bit (gdbarch
, 64);
6181 set_gdbarch_ptr_bit (gdbarch
, 64);
6182 set_gdbarch_long_long_bit (gdbarch
, 64);
6183 set_gdbarch_long_double_bit (gdbarch
, 128);
6184 set_gdbarch_long_double_format (gdbarch
,
6185 &floatformat_n32n64_long_double_big
);
6188 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
6191 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6192 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6195 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6196 flag in object files because to do so would make it impossible to
6197 link with libraries compiled without "-gp32". This is
6198 unnecessarily restrictive.
6200 We could solve this problem by adding "-gp32" multilibs to gcc,
6201 but to set this flag before gcc is built with such multilibs will
6202 break too many systems.''
6204 But even more unhelpfully, the default linker output target for
6205 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6206 for 64-bit programs - you need to change the ABI to change this,
6207 and not all gcc targets support that currently. Therefore using
6208 this flag to detect 32-bit mode would do the wrong thing given
6209 the current gcc - it would make GDB treat these 64-bit programs
6210 as 32-bit programs by default. */
6212 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6213 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6214 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6216 /* Add/remove bits from an address. The MIPS needs be careful to
6217 ensure that all 32 bit addresses are sign extended to 64 bits. */
6218 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6220 /* Unwind the frame. */
6221 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6222 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
6224 /* Map debug register numbers onto internal register numbers. */
6225 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6226 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6227 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6228 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
6229 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6230 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6231 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6232 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6234 /* MIPS version of CALL_DUMMY */
6236 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6237 replaced by a command, and all targets will default to on stack
6238 (regardless of the stack's execute status). */
6239 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6240 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6242 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6243 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6244 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6246 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6247 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6249 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6251 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6252 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6253 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6255 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6257 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6259 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6261 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6262 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6263 need to all be folded into the target vector. Since they are
6264 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6265 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6267 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6269 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6271 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
6272 to support MIPS16. This is a bad thing. Make sure not to do it
6273 if we have an OS ABI that actually supports shared libraries, since
6274 shared library support is more important. If we have an OS someday
6275 that supports both shared libraries and MIPS16, we'll have to find
6276 a better place for these. */
6277 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
6279 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6280 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6283 /* Hook in OS ABI-specific overrides, if they have been registered. */
6284 gdbarch_init_osabi (info
, gdbarch
);
6286 /* Unwind the frame. */
6287 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
6288 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
6289 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
6290 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
6291 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6292 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
6293 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6294 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6300 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6302 struct gdbarch_info info
;
6304 /* Force the architecture to update, and (if it's a MIPS architecture)
6305 mips_gdbarch_init will take care of the rest. */
6306 gdbarch_info_init (&info
);
6307 gdbarch_update_p (info
);
6310 /* Print out which MIPS ABI is in use. */
6313 show_mips_abi (char *ignore_args
, int from_tty
)
6315 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6317 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6320 enum mips_abi global_abi
= global_mips_abi ();
6321 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6322 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6324 if (global_abi
== MIPS_ABI_UNKNOWN
)
6326 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6328 else if (global_abi
== actual_abi
)
6330 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6334 /* Probably shouldn't happen... */
6336 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6337 actual_abi_str
, mips_abi_strings
[global_abi
]);
6343 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6345 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6349 int ef_mips_32bitmode
;
6350 /* determine the ISA */
6351 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6369 /* determine the size of a pointer */
6370 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6371 fprintf_unfiltered (file
,
6372 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6374 fprintf_unfiltered (file
,
6375 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6377 fprintf_unfiltered (file
,
6378 "mips_dump_tdep: ef_mips_arch = %d\n",
6380 fprintf_unfiltered (file
,
6381 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6382 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6383 fprintf_unfiltered (file
,
6384 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6385 mips_mask_address_p (tdep
),
6386 tdep
->default_mask_address_p
);
6388 fprintf_unfiltered (file
,
6389 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6390 MIPS_DEFAULT_FPU_TYPE
,
6391 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6392 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6393 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6395 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6396 fprintf_unfiltered (file
,
6397 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6399 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6400 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6401 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6403 fprintf_unfiltered (file
,
6404 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6405 mips_stack_argsize (current_gdbarch
));
6406 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6407 fprintf_unfiltered (file
,
6408 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6409 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6410 fprintf_unfiltered (file
,
6411 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6412 XSTRING (ATTACH_DETACH
));
6413 fprintf_unfiltered (file
,
6414 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6415 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6416 fprintf_unfiltered (file
,
6417 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6418 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6419 fprintf_unfiltered (file
,
6420 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6421 FIRST_EMBED_REGNUM
);
6422 fprintf_unfiltered (file
,
6423 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
6424 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
6425 fprintf_unfiltered (file
,
6426 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6427 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6428 fprintf_unfiltered (file
,
6429 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6430 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6431 fprintf_unfiltered (file
,
6432 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6434 #ifdef MACHINE_CPROC_FP_OFFSET
6435 fprintf_unfiltered (file
,
6436 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6437 MACHINE_CPROC_FP_OFFSET
);
6439 #ifdef MACHINE_CPROC_PC_OFFSET
6440 fprintf_unfiltered (file
,
6441 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6442 MACHINE_CPROC_PC_OFFSET
);
6444 #ifdef MACHINE_CPROC_SP_OFFSET
6445 fprintf_unfiltered (file
,
6446 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6447 MACHINE_CPROC_SP_OFFSET
);
6449 fprintf_unfiltered (file
,
6450 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6452 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6453 fprintf_unfiltered (file
,
6454 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6455 fprintf_unfiltered (file
,
6456 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6457 fprintf_unfiltered (file
,
6458 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6459 MIPS_LAST_ARG_REGNUM
,
6460 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6461 fprintf_unfiltered (file
,
6462 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6463 fprintf_unfiltered (file
,
6464 "mips_dump_tdep: mips_abi_regsize() = %d\n",
6465 mips_abi_regsize (current_gdbarch
));
6466 fprintf_unfiltered (file
,
6467 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6468 fprintf_unfiltered (file
,
6469 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6470 fprintf_unfiltered (file
,
6471 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6472 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6473 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6474 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6475 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6476 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6477 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6478 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6479 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6480 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6481 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6482 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6484 fprintf_unfiltered (file
,
6485 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6488 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6491 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6493 fprintf_unfiltered (file
,
6494 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6495 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6496 fprintf_unfiltered (file
,
6497 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6498 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6499 fprintf_unfiltered (file
,
6500 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6501 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6502 fprintf_unfiltered (file
,
6503 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6504 SOFTWARE_SINGLE_STEP_P ());
6505 fprintf_unfiltered (file
,
6506 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6507 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6508 #ifdef STACK_END_ADDR
6509 fprintf_unfiltered (file
,
6510 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6513 fprintf_unfiltered (file
,
6514 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6515 XSTRING (STEP_SKIPS_DELAY (PC
)));
6516 fprintf_unfiltered (file
,
6517 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6518 STEP_SKIPS_DELAY_P
);
6519 fprintf_unfiltered (file
,
6520 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6521 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6522 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6523 fprintf_unfiltered (file
,
6524 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6525 fprintf_unfiltered (file
,
6526 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6527 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6528 (TYPE
, CNT
, OTHERTYPE
)));
6530 fprintf_unfiltered (file
,
6531 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6532 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6535 fprintf_unfiltered (file
,
6536 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6538 #ifdef TRACE_FLAVOR_SIZE
6539 fprintf_unfiltered (file
,
6540 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6544 fprintf_unfiltered (file
,
6545 "mips_dump_tdep: TRACE_SET # %s\n",
6546 XSTRING (TRACE_SET (X
, STATE
)));
6548 #ifdef UNUSED_REGNUM
6549 fprintf_unfiltered (file
,
6550 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6552 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6553 fprintf_unfiltered (file
,
6554 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6555 (long) VM_MIN_ADDRESS
);
6556 fprintf_unfiltered (file
,
6557 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6560 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6563 _initialize_mips_tdep (void)
6565 static struct cmd_list_element
*mipsfpulist
= NULL
;
6566 struct cmd_list_element
*c
;
6568 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6569 if (MIPS_ABI_LAST
+ 1
6570 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6571 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6573 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6575 mips_pdr_data
= register_objfile_data ();
6577 /* Add root prefix command for all "set mips"/"show mips" commands */
6578 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6579 "Various MIPS specific commands.",
6580 &setmipscmdlist
, "set mips ", 0, &setlist
);
6582 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6583 "Various MIPS specific commands.",
6584 &showmipscmdlist
, "show mips ", 0, &showlist
);
6586 /* Allow the user to override the saved register size. */
6587 deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6590 &mips_abi_regsize_string
, "\
6591 Set size of general purpose registers saved on the stack.\n\
6592 This option can be set to one of:\n\
6593 32 - Force GDB to treat saved GP registers as 32-bit\n\
6594 64 - Force GDB to treat saved GP registers as 64-bit\n\
6595 auto - Allow GDB to use the target's default setting or autodetect the\n\
6596 saved GP register size from information contained in the executable.\n\
6597 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6599 /* Allow the user to override the argument stack size. */
6600 deprecated_add_show_from_set
6601 (add_set_enum_cmd ("stack-arg-size",
6604 &mips_stack_argsize_string
, "\
6605 Set the amount of stack space reserved for each argument.\n\
6606 This option can be set to one of:\n\
6607 32 - Force GDB to allocate 32-bit chunks per argument\n\
6608 64 - Force GDB to allocate 64-bit chunks per argument\n\
6609 auto - Allow GDB to determine the correct setting from the current\n\
6610 target and executable (default)", &setmipscmdlist
),
6613 /* Allow the user to override the ABI. */
6614 c
= add_set_enum_cmd
6615 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6616 "Set the ABI used by this program.\n"
6617 "This option can be set to one of:\n"
6618 " auto - the default ABI associated with the current binary\n"
6620 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6621 set_cmd_sfunc (c
, mips_abi_update
);
6622 add_cmd ("abi", class_obscure
, show_mips_abi
,
6623 "Show ABI in use by MIPS target", &showmipscmdlist
);
6625 /* Let the user turn off floating point and set the fence post for
6626 heuristic_proc_start. */
6628 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6629 "Set use of MIPS floating-point coprocessor.",
6630 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6631 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6632 "Select single-precision MIPS floating-point coprocessor.",
6634 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6635 "Select double-precision MIPS floating-point coprocessor.",
6637 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6638 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6639 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6640 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6641 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6642 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6643 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6644 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6645 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6646 "Select MIPS floating-point coprocessor automatically.",
6648 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6649 "Show current use of MIPS floating-point coprocessor target.",
6652 /* We really would like to have both "0" and "unlimited" work, but
6653 command.c doesn't deal with that. So make it a var_zinteger
6654 because the user can always use "999999" or some such for unlimited. */
6655 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6656 (char *) &heuristic_fence_post
, "\
6657 Set the distance searched for the start of a function.\n\
6658 If you are debugging a stripped executable, GDB needs to search through the\n\
6659 program for the start of a function. This command sets the distance of the\n\
6660 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6661 /* We need to throw away the frame cache when we set this, since it
6662 might change our ability to get backtraces. */
6663 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6664 deprecated_add_show_from_set (c
, &showlist
);
6666 /* Allow the user to control whether the upper bits of 64-bit
6667 addresses should be zeroed. */
6668 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6669 Set zeroing of upper 32 bits of 64-bit addresses.", "\
6670 Show zeroing of upper 32 bits of 64-bit addresses.", "\
6671 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6672 allow GDB to determine the correct value.\n", "\
6673 Zerroing of upper 32 bits of 64-bit address is %s.",
6674 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6676 /* Allow the user to control the size of 32 bit registers within the
6677 raw remote packet. */
6678 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6679 &mips64_transfers_32bit_regs_p
, "\
6680 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6681 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6682 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6683 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6684 64 bits for others. Use \"off\" to disable compatibility mode", "\
6685 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6686 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6688 /* Debug this files internals. */
6689 deprecated_add_show_from_set
6690 (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6691 &mips_debug
, "Set mips debugging.\n\
6692 When non-zero, mips specific debugging is enabled.", &setdebuglist
),