1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 /* A useful bit in the CP0 status register (PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE
= 4,
72 MIPS_FPU_DOUBLE_REGSIZE
= 8
76 static const char *mips_abi_string
;
78 static const char *mips_abi_strings
[] = {
89 struct frame_extra_info
91 mips_extra_func_info_t proc_desc
;
95 /* Various MIPS ISA options (related to stack analysis) can be
96 overridden dynamically. Establish an enum/array for managing
99 static const char size_auto
[] = "auto";
100 static const char size_32
[] = "32";
101 static const char size_64
[] = "64";
103 static const char *size_enums
[] = {
110 /* Some MIPS boards don't support floating point while others only
111 support single-precision floating-point operations. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int default_mask_address_p
;
141 /* Is the target using 64-bit raw integer registers but only
142 storing a left-aligned 32-bit value in each? */
143 int mips64_transfers_32bit_regs_p
;
144 /* Indexes for various registers. IRIX and embedded have
145 different values. This contains the "public" fields. Don't
146 add any that do not need to be public. */
147 const struct mips_regnum
*regnum
;
148 /* Register names table for the current register set. */
149 const char **mips_processor_reg_names
;
153 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
159 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
160 They are implemented as a pair of 64bit doubles where the high
161 part holds the result of the operation rounded to double, and
162 the low double holds the difference between the exact result and
163 the rounded result. So "high" + "low" contains the result with
164 added precision. Unfortunately, the floatformat structure used
165 by GDB is not powerful enough to describe this format. As a temporary
166 measure, we define a 128bit floatformat that only uses the high part.
167 We lose a bit of precision but that's probably the best we can do
168 for now with the current infrastructure. */
170 static const struct floatformat floatformat_n32n64_long_double_big
=
172 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
173 floatformat_intbit_no
,
174 "floatformat_ieee_double_big",
175 n32n64_floatformat_always_valid
178 const struct mips_regnum
*
179 mips_regnum (struct gdbarch
*gdbarch
)
181 return gdbarch_tdep (gdbarch
)->regnum
;
185 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
187 return mips_regnum (gdbarch
)->fp0
+ 12;
190 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
191 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
193 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
195 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
197 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
199 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
200 functions to test, set, or clear bit 0 of addresses. */
203 is_mips16_addr (CORE_ADDR addr
)
209 unmake_mips16_addr (CORE_ADDR addr
)
211 return ((addr
) & ~1);
214 /* Return the contents of register REGNUM as a signed integer. */
217 read_signed_register (int regnum
)
220 regcache_cooked_read_signed (current_regcache
, regnum
, &val
);
225 read_signed_register_pid (int regnum
, ptid_t ptid
)
230 if (ptid_equal (ptid
, inferior_ptid
))
231 return read_signed_register (regnum
);
233 save_ptid
= inferior_ptid
;
235 inferior_ptid
= ptid
;
237 retval
= read_signed_register (regnum
);
239 inferior_ptid
= save_ptid
;
244 /* Return the MIPS ABI associated with GDBARCH. */
246 mips_abi (struct gdbarch
*gdbarch
)
248 return gdbarch_tdep (gdbarch
)->mips_abi
;
252 mips_isa_regsize (struct gdbarch
*gdbarch
)
254 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
255 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
258 /* Return the currently configured (or set) saved register size. */
260 static const char *mips_abi_regsize_string
= size_auto
;
263 mips_abi_regsize (struct gdbarch
*gdbarch
)
265 if (mips_abi_regsize_string
== size_auto
)
266 switch (mips_abi (gdbarch
))
268 case MIPS_ABI_EABI32
:
274 case MIPS_ABI_EABI64
:
276 case MIPS_ABI_UNKNOWN
:
279 internal_error (__FILE__
, __LINE__
, "bad switch");
281 else if (mips_abi_regsize_string
== size_64
)
283 else /* if (mips_abi_regsize_string == size_32) */
287 /* Functions for setting and testing a bit in a minimal symbol that
288 marks it as 16-bit function. The MSB of the minimal symbol's
289 "info" field is used for this purpose.
291 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
292 i.e. refers to a 16-bit function, and sets a "special" bit in a
293 minimal symbol to mark it as a 16-bit function
295 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
298 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
300 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
302 MSYMBOL_INFO (msym
) = (char *)
303 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
304 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
309 msymbol_is_special (struct minimal_symbol
*msym
)
311 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
314 /* XFER a value from the big/little/left end of the register.
315 Depending on the size of the value it might occupy the entire
316 register or just part of it. Make an allowance for this, aligning
317 things accordingly. */
320 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
321 enum bfd_endian endian
, bfd_byte
* in
,
322 const bfd_byte
* out
, int buf_offset
)
325 gdb_assert (reg_num
>= NUM_REGS
);
326 /* Need to transfer the left or right part of the register, based on
327 the targets byte order. */
331 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
333 case BFD_ENDIAN_LITTLE
:
336 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
340 internal_error (__FILE__
, __LINE__
, "bad switch");
343 fprintf_unfiltered (gdb_stderr
,
344 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
345 reg_num
, reg_offset
, buf_offset
, length
);
346 if (mips_debug
&& out
!= NULL
)
349 fprintf_unfiltered (gdb_stdlog
, "out ");
350 for (i
= 0; i
< length
; i
++)
351 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
354 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
357 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
359 if (mips_debug
&& in
!= NULL
)
362 fprintf_unfiltered (gdb_stdlog
, "in ");
363 for (i
= 0; i
< length
; i
++)
364 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
367 fprintf_unfiltered (gdb_stdlog
, "\n");
370 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
371 compatiblity mode. A return value of 1 means that we have
372 physical 64-bit registers, but should treat them as 32-bit registers. */
375 mips2_fp_compat (void)
377 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
379 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
384 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
385 in all the places we deal with FP registers. PR gdb/413. */
386 /* Otherwise check the FR bit in the status register - it controls
387 the FP compatiblity mode. If it is clear we are in compatibility
389 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
396 /* The amount of space reserved on the stack for registers. This is
397 different to MIPS_ABI_REGSIZE as it determines the alignment of
398 data allocated after the registers have run out. */
400 static const char *mips_stack_argsize_string
= size_auto
;
403 mips_stack_argsize (struct gdbarch
*gdbarch
)
405 if (mips_stack_argsize_string
== size_auto
)
406 return mips_abi_regsize (gdbarch
);
407 else if (mips_stack_argsize_string
== size_64
)
409 else /* if (mips_stack_argsize_string == size_32) */
413 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
415 struct mips_frame_cache
;
416 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
419 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
421 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
423 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
425 static struct type
*mips_float_register_type (void);
426 static struct type
*mips_double_register_type (void);
428 /* The list of available "set mips " and "show mips " commands */
430 static struct cmd_list_element
*setmipscmdlist
= NULL
;
431 static struct cmd_list_element
*showmipscmdlist
= NULL
;
433 /* Integer registers 0 thru 31 are handled explicitly by
434 mips_register_name(). Processor specific registers 32 and above
435 are listed in the followign tables. */
438 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
442 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
443 "sr", "lo", "hi", "bad", "cause", "pc",
444 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
445 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
446 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
447 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
448 "fsr", "fir", "" /*"fp" */ , "",
449 "", "", "", "", "", "", "", "",
450 "", "", "", "", "", "", "", "",
453 /* Names of IDT R3041 registers. */
455 static const char *mips_r3041_reg_names
[] = {
456 "sr", "lo", "hi", "bad", "cause", "pc",
457 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
458 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
459 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
460 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
461 "fsr", "fir", "", /*"fp" */ "",
462 "", "", "bus", "ccfg", "", "", "", "",
463 "", "", "port", "cmp", "", "", "epc", "prid",
466 /* Names of tx39 registers. */
468 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
469 "sr", "lo", "hi", "bad", "cause", "pc",
470 "", "", "", "", "", "", "", "",
471 "", "", "", "", "", "", "", "",
472 "", "", "", "", "", "", "", "",
473 "", "", "", "", "", "", "", "",
475 "", "", "", "", "", "", "", "",
476 "", "", "config", "cache", "debug", "depc", "epc", ""
479 /* Names of IRIX registers. */
480 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
481 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
482 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
483 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
484 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
485 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
489 /* Return the name of the register corresponding to REGNO. */
491 mips_register_name (int regno
)
493 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
494 /* GPR names for all ABIs other than n32/n64. */
495 static char *mips_gpr_names
[] = {
496 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
497 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
498 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
499 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
502 /* GPR names for n32 and n64 ABIs. */
503 static char *mips_n32_n64_gpr_names
[] = {
504 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
505 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
506 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
507 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
510 enum mips_abi abi
= mips_abi (current_gdbarch
);
512 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
513 don't make the raw register names visible. */
514 int rawnum
= regno
% NUM_REGS
;
515 if (regno
< NUM_REGS
)
518 /* The MIPS integer registers are always mapped from 0 to 31. The
519 names of the registers (which reflects the conventions regarding
520 register use) vary depending on the ABI. */
521 if (0 <= rawnum
&& rawnum
< 32)
523 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
524 return mips_n32_n64_gpr_names
[rawnum
];
526 return mips_gpr_names
[rawnum
];
528 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
530 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
531 return tdep
->mips_processor_reg_names
[rawnum
- 32];
534 internal_error (__FILE__
, __LINE__
,
535 "mips_register_name: bad register number %d", rawnum
);
538 /* Return the groups that a MIPS register can be categorised into. */
541 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
542 struct reggroup
*reggroup
)
547 int rawnum
= regnum
% NUM_REGS
;
548 int pseudo
= regnum
/ NUM_REGS
;
549 if (reggroup
== all_reggroup
)
551 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
552 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
553 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
554 (gdbarch), as not all architectures are multi-arch. */
555 raw_p
= rawnum
< NUM_REGS
;
556 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
558 if (reggroup
== float_reggroup
)
559 return float_p
&& pseudo
;
560 if (reggroup
== vector_reggroup
)
561 return vector_p
&& pseudo
;
562 if (reggroup
== general_reggroup
)
563 return (!vector_p
&& !float_p
) && pseudo
;
564 /* Save the pseudo registers. Need to make certain that any code
565 extracting register values from a saved register cache also uses
567 if (reggroup
== save_reggroup
)
568 return raw_p
&& pseudo
;
569 /* Restore the same pseudo register. */
570 if (reggroup
== restore_reggroup
)
571 return raw_p
&& pseudo
;
575 /* Map the symbol table registers which live in the range [1 *
576 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
577 registers. Take care of alignment and size problems. */
580 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
581 int cookednum
, void *buf
)
583 int rawnum
= cookednum
% NUM_REGS
;
584 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
585 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
586 regcache_raw_read (regcache
, rawnum
, buf
);
587 else if (register_size (gdbarch
, rawnum
) >
588 register_size (gdbarch
, cookednum
))
590 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
591 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
592 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
594 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
597 internal_error (__FILE__
, __LINE__
, "bad register size");
601 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
602 struct regcache
*regcache
, int cookednum
,
605 int rawnum
= cookednum
% NUM_REGS
;
606 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
607 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
608 regcache_raw_write (regcache
, rawnum
, buf
);
609 else if (register_size (gdbarch
, rawnum
) >
610 register_size (gdbarch
, cookednum
))
612 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
613 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
614 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
616 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
619 internal_error (__FILE__
, __LINE__
, "bad register size");
622 /* Table to translate MIPS16 register field to actual register number. */
623 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
625 /* Heuristic_proc_start may hunt through the text section for a long
626 time across a 2400 baud serial line. Allows the user to limit this
629 static unsigned int heuristic_fence_post
= 0;
631 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
632 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
633 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
634 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
635 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
636 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
637 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
638 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
639 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
640 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
641 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
642 this will corrupt pdr.iline. Fortunately we don't use it. */
643 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
644 #define _PROC_MAGIC_ 0x0F0F0F0F
646 /* Number of bytes of storage in the actual machine representation for
647 register N. NOTE: This defines the pseudo register type so need to
648 rebuild the architecture vector. */
650 static int mips64_transfers_32bit_regs_p
= 0;
653 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
654 struct cmd_list_element
*c
)
656 struct gdbarch_info info
;
657 gdbarch_info_init (&info
);
658 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
659 instead of relying on globals. Doing that would let generic code
660 handle the search for this specific architecture. */
661 if (!gdbarch_update_p (info
))
663 mips64_transfers_32bit_regs_p
= 0;
664 error ("32-bit compatibility mode not supported");
668 /* Convert to/from a register and the corresponding memory value. */
671 mips_convert_register_p (int regnum
, struct type
*type
)
673 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
674 && register_size (current_gdbarch
, regnum
) == 4
675 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
676 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
677 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
681 mips_register_to_value (struct frame_info
*frame
, int regnum
,
682 struct type
*type
, void *to
)
684 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
685 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
689 mips_value_to_register (struct frame_info
*frame
, int regnum
,
690 struct type
*type
, const void *from
)
692 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
693 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
696 /* Return the GDB type object for the "standard" data type of data in
700 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
702 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
703 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
704 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
706 /* The floating-point registers raw, or cooked, always match
707 mips_isa_regsize(), and also map 1:1, byte for byte. */
708 switch (gdbarch_byte_order (gdbarch
))
711 if (mips_isa_regsize (gdbarch
) == 4)
712 return builtin_type_ieee_single_big
;
714 return builtin_type_ieee_double_big
;
715 case BFD_ENDIAN_LITTLE
:
716 if (mips_isa_regsize (gdbarch
) == 4)
717 return builtin_type_ieee_single_little
;
719 return builtin_type_ieee_double_little
;
720 case BFD_ENDIAN_UNKNOWN
:
722 internal_error (__FILE__
, __LINE__
, "bad switch");
725 else if (regnum
< NUM_REGS
)
727 /* The raw or ISA registers. These are all sized according to
729 if (mips_isa_regsize (gdbarch
) == 4)
730 return builtin_type_int32
;
732 return builtin_type_int64
;
736 /* The cooked or ABI registers. These are sized according to
737 the ABI (with a few complications). */
738 if (regnum
>= (NUM_REGS
739 + mips_regnum (current_gdbarch
)->fp_control_status
)
740 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
741 /* The pseudo/cooked view of the embedded registers is always
742 32-bit. The raw view is handled below. */
743 return builtin_type_int32
;
744 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
745 /* The target, while possibly using a 64-bit register buffer,
746 is only transfering 32-bits of each integer register.
747 Reflect this in the cooked/pseudo (ABI) register value. */
748 return builtin_type_int32
;
749 else if (mips_abi_regsize (gdbarch
) == 4)
750 /* The ABI is restricted to 32-bit registers (the ISA could be
752 return builtin_type_int32
;
755 return builtin_type_int64
;
759 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
764 return read_signed_register (MIPS_SP_REGNUM
);
767 /* Should the upper word of 64-bit addresses be zeroed? */
768 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
771 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
773 switch (mask_address_var
)
775 case AUTO_BOOLEAN_TRUE
:
777 case AUTO_BOOLEAN_FALSE
:
780 case AUTO_BOOLEAN_AUTO
:
781 return tdep
->default_mask_address_p
;
783 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
789 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
791 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
792 switch (mask_address_var
)
794 case AUTO_BOOLEAN_TRUE
:
795 printf_filtered ("The 32 bit mips address mask is enabled\n");
797 case AUTO_BOOLEAN_FALSE
:
798 printf_filtered ("The 32 bit mips address mask is disabled\n");
800 case AUTO_BOOLEAN_AUTO
:
802 ("The 32 bit address mask is set automatically. Currently %s\n",
803 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
806 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
811 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
814 mips_pc_is_mips16 (CORE_ADDR memaddr
)
816 struct minimal_symbol
*sym
;
818 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
819 if (is_mips16_addr (memaddr
))
822 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
823 the high bit of the info field. Use this to decide if the function is
824 MIPS16 or normal MIPS. */
825 sym
= lookup_minimal_symbol_by_pc (memaddr
);
827 return msymbol_is_special (sym
);
832 /* MIPS believes that the PC has a sign extended value. Perhaps the
833 all registers should be sign extended for simplicity? */
836 mips_read_pc (ptid_t ptid
)
838 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
842 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
844 return frame_unwind_register_signed (next_frame
,
845 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
848 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
849 dummy frame. The frame ID's base needs to match the TOS value
850 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
853 static struct frame_id
854 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
856 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
857 frame_pc_unwind (next_frame
));
861 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
863 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
866 /* Fetch and return instruction from the specified location. If the PC
867 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
870 mips_fetch_instruction (CORE_ADDR addr
)
872 char buf
[MIPS32_INSN_SIZE
];
876 if (mips_pc_is_mips16 (addr
))
878 instlen
= MIPS16_INSN_SIZE
;
879 addr
= unmake_mips16_addr (addr
);
882 instlen
= MIPS32_INSN_SIZE
;
883 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
885 memory_error (status
, addr
);
886 return extract_unsigned_integer (buf
, instlen
);
890 mips16_fetch_instruction (CORE_ADDR addr
)
892 char buf
[MIPS16_INSN_SIZE
];
895 addr
= unmake_mips16_addr (addr
);
896 status
= deprecated_read_memory_nobpt (addr
, buf
, sizeof (buf
));
898 memory_error (status
, addr
);
899 return extract_unsigned_integer (buf
, sizeof (buf
));
902 /* These the fields of 32 bit mips instructions */
903 #define mips32_op(x) (x >> 26)
904 #define itype_op(x) (x >> 26)
905 #define itype_rs(x) ((x >> 21) & 0x1f)
906 #define itype_rt(x) ((x >> 16) & 0x1f)
907 #define itype_immediate(x) (x & 0xffff)
909 #define jtype_op(x) (x >> 26)
910 #define jtype_target(x) (x & 0x03ffffff)
912 #define rtype_op(x) (x >> 26)
913 #define rtype_rs(x) ((x >> 21) & 0x1f)
914 #define rtype_rt(x) ((x >> 16) & 0x1f)
915 #define rtype_rd(x) ((x >> 11) & 0x1f)
916 #define rtype_shamt(x) ((x >> 6) & 0x1f)
917 #define rtype_funct(x) (x & 0x3f)
920 mips32_relative_offset (unsigned long inst
)
923 x
= itype_immediate (inst
);
924 if (x
& 0x8000) /* sign bit set */
926 x
|= 0xffff0000; /* sign extension */
932 /* Determine whate to set a single step breakpoint while considering
935 mips32_next_pc (CORE_ADDR pc
)
939 inst
= mips_fetch_instruction (pc
);
940 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
942 if (itype_op (inst
) >> 2 == 5)
943 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
945 op
= (itype_op (inst
) & 0x03);
960 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
961 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
963 int tf
= itype_rt (inst
) & 0x01;
964 int cnum
= itype_rt (inst
) >> 2;
966 read_signed_register (mips_regnum (current_gdbarch
)->
968 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
970 if (((cond
>> cnum
) & 0x01) == tf
)
971 pc
+= mips32_relative_offset (inst
) + 4;
976 pc
+= 4; /* Not a branch, next instruction is easy */
979 { /* This gets way messy */
981 /* Further subdivide into SPECIAL, REGIMM and other */
982 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
984 case 0: /* SPECIAL */
985 op
= rtype_funct (inst
);
990 /* Set PC to that address */
991 pc
= read_signed_register (rtype_rs (inst
));
997 break; /* end SPECIAL */
1000 op
= itype_rt (inst
); /* branch condition */
1005 case 16: /* BLTZAL */
1006 case 18: /* BLTZALL */
1008 if (read_signed_register (itype_rs (inst
)) < 0)
1009 pc
+= mips32_relative_offset (inst
) + 4;
1011 pc
+= 8; /* after the delay slot */
1015 case 17: /* BGEZAL */
1016 case 19: /* BGEZALL */
1017 if (read_signed_register (itype_rs (inst
)) >= 0)
1018 pc
+= mips32_relative_offset (inst
) + 4;
1020 pc
+= 8; /* after the delay slot */
1022 /* All of the other instructions in the REGIMM category */
1027 break; /* end REGIMM */
1032 reg
= jtype_target (inst
) << 2;
1033 /* Upper four bits get never changed... */
1034 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1037 /* FIXME case JALX : */
1040 reg
= jtype_target (inst
) << 2;
1041 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1042 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1044 break; /* The new PC will be alternate mode */
1045 case 4: /* BEQ, BEQL */
1047 if (read_signed_register (itype_rs (inst
)) ==
1048 read_signed_register (itype_rt (inst
)))
1049 pc
+= mips32_relative_offset (inst
) + 4;
1053 case 5: /* BNE, BNEL */
1055 if (read_signed_register (itype_rs (inst
)) !=
1056 read_signed_register (itype_rt (inst
)))
1057 pc
+= mips32_relative_offset (inst
) + 4;
1061 case 6: /* BLEZ, BLEZL */
1062 if (read_signed_register (itype_rs (inst
)) <= 0)
1063 pc
+= mips32_relative_offset (inst
) + 4;
1069 greater_branch
: /* BGTZ, BGTZL */
1070 if (read_signed_register (itype_rs (inst
)) > 0)
1071 pc
+= mips32_relative_offset (inst
) + 4;
1078 } /* mips32_next_pc */
1080 /* Decoding the next place to set a breakpoint is irregular for the
1081 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1082 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1083 We dont want to set a single step instruction on the extend instruction
1087 /* Lots of mips16 instruction formats */
1088 /* Predicting jumps requires itype,ritype,i8type
1089 and their extensions extItype,extritype,extI8type
1091 enum mips16_inst_fmts
1093 itype
, /* 0 immediate 5,10 */
1094 ritype
, /* 1 5,3,8 */
1095 rrtype
, /* 2 5,3,3,5 */
1096 rritype
, /* 3 5,3,3,5 */
1097 rrrtype
, /* 4 5,3,3,3,2 */
1098 rriatype
, /* 5 5,3,3,1,4 */
1099 shifttype
, /* 6 5,3,3,3,2 */
1100 i8type
, /* 7 5,3,8 */
1101 i8movtype
, /* 8 5,3,3,5 */
1102 i8mov32rtype
, /* 9 5,3,5,3 */
1103 i64type
, /* 10 5,3,8 */
1104 ri64type
, /* 11 5,3,3,5 */
1105 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1106 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1107 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1108 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1109 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1110 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1111 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1112 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1113 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1114 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1116 /* I am heaping all the fields of the formats into one structure and
1117 then, only the fields which are involved in instruction extension */
1121 unsigned int regx
; /* Function in i8 type */
1126 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1127 for the bits which make up the immediatate extension. */
1130 extended_offset (unsigned int extension
)
1133 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1135 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1137 value
|= extension
& 0x01f; /* extract 4:0 */
1141 /* Only call this function if you know that this is an extendable
1142 instruction, It wont malfunction, but why make excess remote memory references?
1143 If the immediate operands get sign extended or somthing, do it after
1144 the extension is performed.
1146 /* FIXME: Every one of these cases needs to worry about sign extension
1147 when the offset is to be used in relative addressing */
1151 fetch_mips_16 (CORE_ADDR pc
)
1154 pc
&= 0xfffffffe; /* clear the low order bit */
1155 target_read_memory (pc
, buf
, 2);
1156 return extract_unsigned_integer (buf
, 2);
1160 unpack_mips16 (CORE_ADDR pc
,
1161 unsigned int extension
,
1163 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1168 switch (insn_format
)
1175 value
= extended_offset (extension
);
1176 value
= value
<< 11; /* rom for the original value */
1177 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1181 value
= inst
& 0x7ff;
1182 /* FIXME : Consider sign extension */
1191 { /* A register identifier and an offset */
1192 /* Most of the fields are the same as I type but the
1193 immediate value is of a different length */
1197 value
= extended_offset (extension
);
1198 value
= value
<< 8; /* from the original instruction */
1199 value
|= inst
& 0xff; /* eleven bits from instruction */
1200 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1201 if (value
& 0x4000) /* test the sign bit , bit 26 */
1203 value
&= ~0x3fff; /* remove the sign bit */
1209 value
= inst
& 0xff; /* 8 bits */
1210 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1211 /* FIXME: Do sign extension , this format needs it */
1212 if (value
& 0x80) /* THIS CONFUSES ME */
1214 value
&= 0xef; /* remove the sign bit */
1224 unsigned long value
;
1225 unsigned int nexthalf
;
1226 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1227 value
= value
<< 16;
1228 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1236 internal_error (__FILE__
, __LINE__
, "bad switch");
1238 upk
->offset
= offset
;
1245 add_offset_16 (CORE_ADDR pc
, int offset
)
1247 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1251 extended_mips16_next_pc (CORE_ADDR pc
,
1252 unsigned int extension
, unsigned int insn
)
1254 int op
= (insn
>> 11);
1257 case 2: /* Branch */
1260 struct upk_mips16 upk
;
1261 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1262 offset
= upk
.offset
;
1268 pc
+= (offset
<< 1) + 2;
1271 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1273 struct upk_mips16 upk
;
1274 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1275 pc
= add_offset_16 (pc
, upk
.offset
);
1276 if ((insn
>> 10) & 0x01) /* Exchange mode */
1277 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1284 struct upk_mips16 upk
;
1286 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1287 reg
= read_signed_register (upk
.regx
);
1289 pc
+= (upk
.offset
<< 1) + 2;
1296 struct upk_mips16 upk
;
1298 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1299 reg
= read_signed_register (upk
.regx
);
1301 pc
+= (upk
.offset
<< 1) + 2;
1306 case 12: /* I8 Formats btez btnez */
1308 struct upk_mips16 upk
;
1310 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1311 /* upk.regx contains the opcode */
1312 reg
= read_signed_register (24); /* Test register is 24 */
1313 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1314 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1315 /* pc = add_offset_16(pc,upk.offset) ; */
1316 pc
+= (upk
.offset
<< 1) + 2;
1321 case 29: /* RR Formats JR, JALR, JALR-RA */
1323 struct upk_mips16 upk
;
1324 /* upk.fmt = rrtype; */
1329 upk
.regx
= (insn
>> 8) & 0x07;
1330 upk
.regy
= (insn
>> 5) & 0x07;
1338 break; /* Function return instruction */
1344 break; /* BOGUS Guess */
1346 pc
= read_signed_register (reg
);
1353 /* This is an instruction extension. Fetch the real instruction
1354 (which follows the extension) and decode things based on
1358 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1371 mips16_next_pc (CORE_ADDR pc
)
1373 unsigned int insn
= fetch_mips_16 (pc
);
1374 return extended_mips16_next_pc (pc
, 0, insn
);
1377 /* The mips_next_pc function supports single_step when the remote
1378 target monitor or stub is not developed enough to do a single_step.
1379 It works by decoding the current instruction and predicting where a
1380 branch will go. This isnt hard because all the data is available.
1381 The MIPS32 and MIPS16 variants are quite different */
1383 mips_next_pc (CORE_ADDR pc
)
1386 return mips16_next_pc (pc
);
1388 return mips32_next_pc (pc
);
1391 struct mips_frame_cache
1394 struct trad_frame_saved_reg
*saved_regs
;
1398 static struct mips_frame_cache
*
1399 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1401 CORE_ADDR startaddr
= 0;
1402 mips_extra_func_info_t proc_desc
;
1403 struct mips_frame_cache
*cache
;
1404 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1405 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1406 /* r0 bit means kernel trap */
1408 /* What registers have been saved? Bitmasks. */
1409 unsigned long gen_mask
, float_mask
;
1411 if ((*this_cache
) != NULL
)
1412 return (*this_cache
);
1413 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1414 (*this_cache
) = cache
;
1415 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1417 /* Get the mdebug proc descriptor. */
1418 proc_desc
= non_heuristic_proc_desc (frame_pc_unwind (next_frame
),
1420 /* Must be true. This is only called when the sniffer detected a
1422 gdb_assert (proc_desc
!= NULL
);
1424 /* Extract the frame's base. */
1425 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1426 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1428 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1429 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1430 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1432 /* Must be true. The in_prologue case is left for the heuristic
1433 unwinder. This is always used on kernel traps. */
1434 gdb_assert (!in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1437 /* Fill in the offsets for the registers which gen_mask says were
1440 CORE_ADDR reg_position
= (cache
->base
+ PROC_REG_OFFSET (proc_desc
));
1443 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1444 if (gen_mask
& 0x80000000)
1446 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1447 reg_position
-= mips_abi_regsize (gdbarch
);
1451 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1452 order of that normally used by gcc. Therefore, we have to fetch
1453 the first instruction of the function, and if it's an entry
1454 instruction that saves $s0 or $s1, correct their saved addresses. */
1455 if (mips_pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1457 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1458 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1462 int sreg_count
= (inst
>> 6) & 3;
1464 /* Check if the ra register was pushed on the stack. */
1465 CORE_ADDR reg_position
= (cache
->base
1466 + PROC_REG_OFFSET (proc_desc
));
1468 reg_position
-= mips_abi_regsize (gdbarch
);
1470 /* Check if the s0 and s1 registers were pushed on the
1472 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1474 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1476 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1477 reg_position
-= mips_abi_regsize (gdbarch
);
1482 /* Fill in the offsets for the registers which float_mask says were
1485 CORE_ADDR reg_position
= (cache
->base
1486 + PROC_FREG_OFFSET (proc_desc
));
1488 /* Fill in the offsets for the float registers which float_mask
1490 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1491 if (float_mask
& 0x80000000)
1493 if (mips_abi_regsize (gdbarch
) == 4
1494 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1496 /* On a big endian 32 bit ABI, floating point registers
1497 are paired to form doubles such that the most
1498 significant part is in $f[N+1] and the least
1499 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1500 registers are also spilled as a pair and stored as a
1503 When little-endian the least significant part is
1504 stored first leading to the memory order $f[N] and
1507 Unfortunately, when big-endian the most significant
1508 part of the double is stored first, and the least
1509 significant is stored second. This leads to the
1510 registers being ordered in memory as firt $f[N+1] and
1513 For the big-endian case make certain that the
1514 addresses point at the correct (swapped) locations
1515 $f[N] and $f[N+1] pair (keep in mind that
1516 reg_position is decremented each time through the
1519 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1520 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1522 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1523 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1526 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1527 .addr
= reg_position
;
1528 reg_position
-= mips_abi_regsize (gdbarch
);
1531 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1532 = cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1535 /* SP_REGNUM, contains the value and not the address. */
1536 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1538 return (*this_cache
);
1542 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1543 struct frame_id
*this_id
)
1545 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1547 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1551 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1553 int regnum
, int *optimizedp
,
1554 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1555 int *realnump
, void *valuep
)
1557 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1559 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1560 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1563 static const struct frame_unwind mips_mdebug_frame_unwind
=
1566 mips_mdebug_frame_this_id
,
1567 mips_mdebug_frame_prev_register
1570 static const struct frame_unwind
*
1571 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1573 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1574 CORE_ADDR startaddr
= 0;
1575 mips_extra_func_info_t proc_desc
;
1578 /* Only use the mdebug frame unwinder on mdebug frames where all the
1579 registers have been saved. Leave hard cases such as no mdebug or
1580 in prologue for the heuristic unwinders. */
1582 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1583 if (proc_desc
== NULL
)
1586 /* Not sure exactly what kernel_trap means, but if it means the
1587 kernel saves the registers without a prologue doing it, we better
1588 not examine the prologue to see whether registers have been saved
1590 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1592 return &mips_mdebug_frame_unwind
;
1594 /* In any frame other than the innermost or a frame interrupted by a
1595 signal, we assume that all registers have been saved. This
1596 assumes that all register saves in a function happen before the
1597 first function call. */
1598 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1599 return &mips_mdebug_frame_unwind
;
1605 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1608 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1613 static const struct frame_base mips_mdebug_frame_base
= {
1614 &mips_mdebug_frame_unwind
,
1615 mips_mdebug_frame_base_address
,
1616 mips_mdebug_frame_base_address
,
1617 mips_mdebug_frame_base_address
1620 static const struct frame_base
*
1621 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1623 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1624 return &mips_mdebug_frame_base
;
1629 /* Set a register's saved stack address in temp_saved_regs. If an
1630 address has already been set for this register, do nothing; this
1631 way we will only recognize the first save of a given register in a
1634 For simplicity, save the address in both [0 .. NUM_REGS) and
1635 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1636 is used as it is only second range (the ABI instead of ISA
1637 registers) that comes into play when finding saved registers in a
1641 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1644 if (this_cache
!= NULL
1645 && this_cache
->saved_regs
[regnum
].addr
== -1)
1647 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
1648 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
1653 /* Fetch the immediate value from a MIPS16 instruction.
1654 If the previous instruction was an EXTEND, use it to extend
1655 the upper bits of the immediate value. This is a helper function
1656 for mips16_scan_prologue. */
1659 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1660 unsigned short inst
, /* current instruction */
1661 int nbits
, /* number of bits in imm field */
1662 int scale
, /* scale factor to be applied to imm */
1663 int is_signed
) /* is the imm field signed? */
1667 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1669 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1670 if (offset
& 0x8000) /* check for negative extend */
1671 offset
= 0 - (0x10000 - (offset
& 0xffff));
1672 return offset
| (inst
& 0x1f);
1676 int max_imm
= 1 << nbits
;
1677 int mask
= max_imm
- 1;
1678 int sign_bit
= max_imm
>> 1;
1680 offset
= inst
& mask
;
1681 if (is_signed
&& (offset
& sign_bit
))
1682 offset
= 0 - (max_imm
- offset
);
1683 return offset
* scale
;
1688 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1689 the associated FRAME_CACHE if not null.
1690 Return the address of the first instruction past the prologue. */
1693 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1694 struct frame_info
*next_frame
,
1695 struct mips_frame_cache
*this_cache
)
1698 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1700 long frame_offset
= 0; /* Size of stack frame. */
1701 long frame_adjust
= 0; /* Offset of FP from SP. */
1702 int frame_reg
= MIPS_SP_REGNUM
;
1703 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1704 unsigned inst
= 0; /* current instruction */
1705 unsigned entry_inst
= 0; /* the entry instruction */
1708 int extend_bytes
= 0;
1709 int prev_extend_bytes
;
1710 CORE_ADDR end_prologue_addr
= 0;
1712 /* Can be called when there's no process, and hence when there's no
1714 if (next_frame
!= NULL
)
1715 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1719 if (limit_pc
> start_pc
+ 200)
1720 limit_pc
= start_pc
+ 200;
1722 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSN_SIZE
)
1724 /* Save the previous instruction. If it's an EXTEND, we'll extract
1725 the immediate offset extension from it in mips16_get_imm. */
1728 /* Fetch and decode the instruction. */
1729 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1731 /* Normally we ignore extend instructions. However, if it is
1732 not followed by a valid prologue instruction, then this
1733 instruction is not part of the prologue either. We must
1734 remember in this case to adjust the end_prologue_addr back
1736 if ((inst
& 0xf800) == 0xf000) /* extend */
1738 extend_bytes
= MIPS16_INSN_SIZE
;
1742 prev_extend_bytes
= extend_bytes
;
1745 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1746 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1748 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1749 if (offset
< 0) /* negative stack adjustment? */
1750 frame_offset
-= offset
;
1752 /* Exit loop if a positive stack adjustment is found, which
1753 usually means that the stack cleanup code in the function
1754 epilogue is reached. */
1757 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1759 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1760 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1761 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1763 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1765 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1766 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1767 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1769 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1771 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1772 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1774 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1776 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1777 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1779 else if (inst
== 0x673d) /* move $s1, $sp */
1784 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1786 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1787 frame_addr
= sp
+ offset
;
1789 frame_adjust
= offset
;
1791 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1793 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1794 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1795 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1797 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1799 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1800 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1801 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1803 else if ((inst
& 0xf81f) == 0xe809
1804 && (inst
& 0x700) != 0x700) /* entry */
1805 entry_inst
= inst
; /* save for later processing */
1806 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1807 cur_pc
+= MIPS16_INSN_SIZE
; /* 32-bit instruction */
1808 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1810 /* This instruction is part of the prologue, but we don't
1811 need to do anything special to handle it. */
1815 /* This instruction is not an instruction typically found
1816 in a prologue, so we must have reached the end of the
1818 if (end_prologue_addr
== 0)
1819 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1823 /* The entry instruction is typically the first instruction in a function,
1824 and it stores registers at offsets relative to the value of the old SP
1825 (before the prologue). But the value of the sp parameter to this
1826 function is the new SP (after the prologue has been executed). So we
1827 can't calculate those offsets until we've seen the entire prologue,
1828 and can calculate what the old SP must have been. */
1829 if (entry_inst
!= 0)
1831 int areg_count
= (entry_inst
>> 8) & 7;
1832 int sreg_count
= (entry_inst
>> 6) & 3;
1834 /* The entry instruction always subtracts 32 from the SP. */
1837 /* Now we can calculate what the SP must have been at the
1838 start of the function prologue. */
1841 /* Check if a0-a3 were saved in the caller's argument save area. */
1842 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1844 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1845 offset
+= mips_abi_regsize (current_gdbarch
);
1848 /* Check if the ra register was pushed on the stack. */
1850 if (entry_inst
& 0x20)
1852 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1853 offset
-= mips_abi_regsize (current_gdbarch
);
1856 /* Check if the s0 and s1 registers were pushed on the stack. */
1857 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1859 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1860 offset
-= mips_abi_regsize (current_gdbarch
);
1864 if (this_cache
!= NULL
)
1867 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1868 + frame_offset
- frame_adjust
);
1869 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1870 be able to get rid of the assignment below, evetually. But it's
1871 still needed for now. */
1872 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1873 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1876 /* If we didn't reach the end of the prologue when scanning the function
1877 instructions, then set end_prologue_addr to the address of the
1878 instruction immediately after the last one we scanned. */
1879 if (end_prologue_addr
== 0)
1880 end_prologue_addr
= cur_pc
;
1882 return end_prologue_addr
;
1885 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1886 Procedures that use the 32-bit instruction set are handled by the
1887 mips_insn32 unwinder. */
1889 static struct mips_frame_cache
*
1890 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1892 struct mips_frame_cache
*cache
;
1894 if ((*this_cache
) != NULL
)
1895 return (*this_cache
);
1896 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1897 (*this_cache
) = cache
;
1898 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1900 /* Analyze the function prologue. */
1902 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1903 CORE_ADDR start_addr
;
1905 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1906 if (start_addr
== 0)
1907 start_addr
= heuristic_proc_start (pc
);
1908 /* We can't analyze the prologue if we couldn't find the begining
1910 if (start_addr
== 0)
1913 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1916 /* SP_REGNUM, contains the value and not the address. */
1917 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1919 return (*this_cache
);
1923 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1924 struct frame_id
*this_id
)
1926 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1928 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1932 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1934 int regnum
, int *optimizedp
,
1935 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1936 int *realnump
, void *valuep
)
1938 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1940 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1941 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1944 static const struct frame_unwind mips_insn16_frame_unwind
=
1947 mips_insn16_frame_this_id
,
1948 mips_insn16_frame_prev_register
1951 static const struct frame_unwind
*
1952 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1954 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1955 if (mips_pc_is_mips16 (pc
))
1956 return &mips_insn16_frame_unwind
;
1961 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1964 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1969 static const struct frame_base mips_insn16_frame_base
=
1971 &mips_insn16_frame_unwind
,
1972 mips_insn16_frame_base_address
,
1973 mips_insn16_frame_base_address
,
1974 mips_insn16_frame_base_address
1977 static const struct frame_base
*
1978 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1980 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1981 return &mips_insn16_frame_base
;
1986 /* Mark all the registers as unset in the saved_regs array
1987 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1990 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1992 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1996 const int num_regs
= NUM_REGS
;
1999 for (i
= 0; i
< num_regs
; i
++)
2001 this_cache
->saved_regs
[i
].addr
= -1;
2006 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2007 the associated FRAME_CACHE if not null.
2008 Return the address of the first instruction past the prologue. */
2011 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2012 struct frame_info
*next_frame
,
2013 struct mips_frame_cache
*this_cache
)
2016 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2019 int frame_reg
= MIPS_SP_REGNUM
;
2021 CORE_ADDR end_prologue_addr
= 0;
2022 int seen_sp_adjust
= 0;
2023 int load_immediate_bytes
= 0;
2025 /* Can be called when there's no process, and hence when there's no
2027 if (next_frame
!= NULL
)
2028 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2032 if (limit_pc
> start_pc
+ 200)
2033 limit_pc
= start_pc
+ 200;
2038 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS32_INSN_SIZE
)
2040 unsigned long inst
, high_word
, low_word
;
2043 /* Fetch the instruction. */
2044 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2046 /* Save some code by pre-extracting some useful fields. */
2047 high_word
= (inst
>> 16) & 0xffff;
2048 low_word
= inst
& 0xffff;
2049 reg
= high_word
& 0x1f;
2051 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2052 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2053 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2055 if (low_word
& 0x8000) /* negative stack adjustment? */
2056 frame_offset
+= 0x10000 - low_word
;
2058 /* Exit loop if a positive stack adjustment is found, which
2059 usually means that the stack cleanup code in the function
2060 epilogue is reached. */
2064 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2066 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2068 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2070 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2071 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2073 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2075 /* Old gcc frame, r30 is virtual frame pointer. */
2076 if ((long) low_word
!= frame_offset
)
2077 frame_addr
= sp
+ low_word
;
2078 else if (frame_reg
== MIPS_SP_REGNUM
)
2080 unsigned alloca_adjust
;
2083 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2084 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2085 if (alloca_adjust
> 0)
2087 /* FP > SP + frame_size. This may be because of
2088 an alloca or somethings similar. Fix sp to
2089 "pre-alloca" value, and try again. */
2090 sp
+= alloca_adjust
;
2091 /* Need to reset the status of all registers. Otherwise,
2092 we will hit a guard that prevents the new address
2093 for each register to be recomputed during the second
2095 reset_saved_regs (this_cache
);
2100 /* move $30,$sp. With different versions of gas this will be either
2101 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2102 Accept any one of these. */
2103 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2105 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2106 if (frame_reg
== MIPS_SP_REGNUM
)
2108 unsigned alloca_adjust
;
2111 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2112 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2113 if (alloca_adjust
> 0)
2115 /* FP > SP + frame_size. This may be because of
2116 an alloca or somethings similar. Fix sp to
2117 "pre-alloca" value, and try again. */
2119 /* Need to reset the status of all registers. Otherwise,
2120 we will hit a guard that prevents the new address
2121 for each register to be recomputed during the second
2123 reset_saved_regs (this_cache
);
2128 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2130 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
2132 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2133 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2134 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2135 || high_word
== 0x3c1c /* lui $gp,n */
2136 || high_word
== 0x279c /* addiu $gp,$gp,n */
2137 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2138 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2141 /* These instructions are part of the prologue, but we don't
2142 need to do anything special to handle them. */
2144 /* The instructions below load $at or $t0 with an immediate
2145 value in preparation for a stack adjustment via
2146 subu $sp,$sp,[$at,$t0]. These instructions could also
2147 initialize a local variable, so we accept them only before
2148 a stack adjustment instruction was seen. */
2149 else if (!seen_sp_adjust
2150 && (high_word
== 0x3c01 /* lui $at,n */
2151 || high_word
== 0x3c08 /* lui $t0,n */
2152 || high_word
== 0x3421 /* ori $at,$at,n */
2153 || high_word
== 0x3508 /* ori $t0,$t0,n */
2154 || high_word
== 0x3401 /* ori $at,$zero,n */
2155 || high_word
== 0x3408 /* ori $t0,$zero,n */
2158 load_immediate_bytes
+= MIPS32_INSN_SIZE
; /* FIXME! */
2162 /* This instruction is not an instruction typically found
2163 in a prologue, so we must have reached the end of the
2165 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2166 loop now? Why would we need to continue scanning the function
2168 if (end_prologue_addr
== 0)
2169 end_prologue_addr
= cur_pc
;
2173 if (this_cache
!= NULL
)
2176 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
2178 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2179 this assignment below, eventually. But it's still needed
2181 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2182 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
2185 /* If we didn't reach the end of the prologue when scanning the function
2186 instructions, then set end_prologue_addr to the address of the
2187 instruction immediately after the last one we scanned. */
2188 /* brobecker/2004-10-10: I don't think this would ever happen, but
2189 we may as well be careful and do our best if we have a null
2190 end_prologue_addr. */
2191 if (end_prologue_addr
== 0)
2192 end_prologue_addr
= cur_pc
;
2194 /* In a frameless function, we might have incorrectly
2195 skipped some load immediate instructions. Undo the skipping
2196 if the load immediate was not followed by a stack adjustment. */
2197 if (load_immediate_bytes
&& !seen_sp_adjust
)
2198 end_prologue_addr
-= load_immediate_bytes
;
2200 return end_prologue_addr
;
2203 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2204 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2205 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2208 static struct mips_frame_cache
*
2209 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2211 struct mips_frame_cache
*cache
;
2213 if ((*this_cache
) != NULL
)
2214 return (*this_cache
);
2216 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2217 (*this_cache
) = cache
;
2218 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2220 /* Analyze the function prologue. */
2222 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2223 CORE_ADDR start_addr
;
2225 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2226 if (start_addr
== 0)
2227 start_addr
= heuristic_proc_start (pc
);
2228 /* We can't analyze the prologue if we couldn't find the begining
2230 if (start_addr
== 0)
2233 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
2236 /* SP_REGNUM, contains the value and not the address. */
2237 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2239 return (*this_cache
);
2243 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2244 struct frame_id
*this_id
)
2246 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2248 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2252 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2254 int regnum
, int *optimizedp
,
2255 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2256 int *realnump
, void *valuep
)
2258 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2260 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2261 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2264 static const struct frame_unwind mips_insn32_frame_unwind
=
2267 mips_insn32_frame_this_id
,
2268 mips_insn32_frame_prev_register
2271 static const struct frame_unwind
*
2272 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2274 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2275 if (! mips_pc_is_mips16 (pc
))
2276 return &mips_insn32_frame_unwind
;
2281 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2284 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2289 static const struct frame_base mips_insn32_frame_base
=
2291 &mips_insn32_frame_unwind
,
2292 mips_insn32_frame_base_address
,
2293 mips_insn32_frame_base_address
,
2294 mips_insn32_frame_base_address
2297 static const struct frame_base
*
2298 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2300 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2301 return &mips_insn32_frame_base
;
2306 static struct trad_frame_cache
*
2307 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2310 CORE_ADDR start_addr
;
2311 CORE_ADDR stack_addr
;
2312 struct trad_frame_cache
*this_trad_cache
;
2314 if ((*this_cache
) != NULL
)
2315 return (*this_cache
);
2316 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2317 (*this_cache
) = this_trad_cache
;
2319 /* The return address is in the link register. */
2320 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, MIPS_RA_REGNUM
);
2322 /* Frame ID, since it's a frameless / stackless function, no stack
2323 space is allocated and SP on entry is the current SP. */
2324 pc
= frame_pc_unwind (next_frame
);
2325 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2326 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2327 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2329 /* Assume that the frame's base is the same as the
2331 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2333 return this_trad_cache
;
2337 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2338 struct frame_id
*this_id
)
2340 struct trad_frame_cache
*this_trad_cache
2341 = mips_stub_frame_cache (next_frame
, this_cache
);
2342 trad_frame_get_id (this_trad_cache
, this_id
);
2346 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2348 int regnum
, int *optimizedp
,
2349 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2350 int *realnump
, void *valuep
)
2352 struct trad_frame_cache
*this_trad_cache
2353 = mips_stub_frame_cache (next_frame
, this_cache
);
2354 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2355 lvalp
, addrp
, realnump
, valuep
);
2358 static const struct frame_unwind mips_stub_frame_unwind
=
2361 mips_stub_frame_this_id
,
2362 mips_stub_frame_prev_register
2365 static const struct frame_unwind
*
2366 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2368 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2369 if (in_plt_section (pc
, NULL
))
2370 return &mips_stub_frame_unwind
;
2376 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2379 struct trad_frame_cache
*this_trad_cache
2380 = mips_stub_frame_cache (next_frame
, this_cache
);
2381 return trad_frame_get_this_base (this_trad_cache
);
2384 static const struct frame_base mips_stub_frame_base
=
2386 &mips_stub_frame_unwind
,
2387 mips_stub_frame_base_address
,
2388 mips_stub_frame_base_address
,
2389 mips_stub_frame_base_address
2392 static const struct frame_base
*
2393 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2395 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2396 return &mips_stub_frame_base
;
2402 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2404 /* Always a pseudo. */
2405 gdb_assert (regno
>= NUM_REGS
);
2409 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2413 return frame_unwind_register_signed (fi
, regno
);
2417 /* mips_addr_bits_remove - remove useless address bits */
2420 mips_addr_bits_remove (CORE_ADDR addr
)
2422 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2423 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2424 /* This hack is a work-around for existing boards using PMON, the
2425 simulator, and any other 64-bit targets that doesn't have true
2426 64-bit addressing. On these targets, the upper 32 bits of
2427 addresses are ignored by the hardware. Thus, the PC or SP are
2428 likely to have been sign extended to all 1s by instruction
2429 sequences that load 32-bit addresses. For example, a typical
2430 piece of code that loads an address is this:
2432 lui $r2, <upper 16 bits>
2433 ori $r2, <lower 16 bits>
2435 But the lui sign-extends the value such that the upper 32 bits
2436 may be all 1s. The workaround is simply to mask off these
2437 bits. In the future, gcc may be changed to support true 64-bit
2438 addressing, and this masking will have to be disabled. */
2439 return addr
&= 0xffffffffUL
;
2444 /* mips_software_single_step() is called just before we want to resume
2445 the inferior, if we want to single-step it but there is no hardware
2446 or kernel single-step support (MIPS on GNU/Linux for example). We find
2447 the target of the coming instruction and breakpoint it.
2449 single_step is also called just after the inferior stops. If we had
2450 set up a simulated single-step, we undo our damage. */
2453 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2455 static CORE_ADDR next_pc
;
2456 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2457 static binsn_quantum break_mem
;
2460 if (insert_breakpoints_p
)
2462 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2463 next_pc
= mips_next_pc (pc
);
2465 target_insert_breakpoint (next_pc
, break_mem
);
2468 target_remove_breakpoint (next_pc
, break_mem
);
2471 static struct mips_extra_func_info temp_proc_desc
;
2473 /* Test whether the PC points to the return instruction at the
2474 end of a function. */
2477 mips_about_to_return (CORE_ADDR pc
)
2479 if (mips_pc_is_mips16 (pc
))
2480 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2481 generates a "jr $ra"; other times it generates code to load
2482 the return address from the stack to an accessible register (such
2483 as $a3), then a "jr" using that register. This second case
2484 is almost impossible to distinguish from an indirect jump
2485 used for switch statements, so we don't even try. */
2486 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2488 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2492 /* This fencepost looks highly suspicious to me. Removing it also
2493 seems suspicious as it could affect remote debugging across serial
2497 heuristic_proc_start (CORE_ADDR pc
)
2504 pc
= ADDR_BITS_REMOVE (pc
);
2506 fence
= start_pc
- heuristic_fence_post
;
2510 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2511 fence
= VM_MIN_ADDRESS
;
2513 instlen
= mips_pc_is_mips16 (pc
) ? MIPS16_INSN_SIZE
: MIPS32_INSN_SIZE
;
2515 /* search back for previous return */
2516 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2517 if (start_pc
< fence
)
2519 /* It's not clear to me why we reach this point when
2520 stop_soon, but with this test, at least we
2521 don't print out warnings for every child forked (eg, on
2522 decstation). 22apr93 rich@cygnus.com. */
2523 if (stop_soon
== NO_STOP_QUIETLY
)
2525 static int blurb_printed
= 0;
2527 warning ("GDB can't find the start of the function at 0x%s.",
2532 /* This actually happens frequently in embedded
2533 development, when you first connect to a board
2534 and your stack pointer and pc are nowhere in
2535 particular. This message needs to give people
2536 in that situation enough information to
2537 determine that it's no big deal. */
2538 printf_filtered ("\n\
2539 GDB is unable to find the start of the function at 0x%s\n\
2540 and thus can't determine the size of that function's stack frame.\n\
2541 This means that GDB may be unable to access that stack frame, or\n\
2542 the frames below it.\n\
2543 This problem is most likely caused by an invalid program counter or\n\
2545 However, if you think GDB should simply search farther back\n\
2546 from 0x%s for code which looks like the beginning of a\n\
2547 function, you can increase the range of the search using the `set\n\
2548 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2555 else if (mips_pc_is_mips16 (start_pc
))
2557 unsigned short inst
;
2559 /* On MIPS16, any one of the following is likely to be the
2560 start of a function:
2564 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2565 inst
= mips_fetch_instruction (start_pc
);
2566 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2567 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2568 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2569 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2571 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2572 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2577 else if (mips_about_to_return (start_pc
))
2579 /* Skip return and its delay slot. */
2580 start_pc
+= 2 * MIPS32_INSN_SIZE
;
2587 struct mips_objfile_private
2593 /* Global used to communicate between non_heuristic_proc_desc and
2594 compare_pdr_entries within qsort (). */
2595 static bfd
*the_bfd
;
2598 compare_pdr_entries (const void *a
, const void *b
)
2600 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2601 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2605 else if (lhs
== rhs
)
2611 static mips_extra_func_info_t
2612 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2614 CORE_ADDR startaddr
;
2615 mips_extra_func_info_t proc_desc
;
2616 struct block
*b
= block_for_pc (pc
);
2618 struct obj_section
*sec
;
2619 struct mips_objfile_private
*priv
;
2621 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2623 *addrptr
= startaddr
;
2627 sec
= find_pc_section (pc
);
2630 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2632 /* Search the ".pdr" section generated by GAS. This includes most of
2633 the information normally found in ECOFF PDRs. */
2635 the_bfd
= sec
->objfile
->obfd
;
2637 && (the_bfd
->format
== bfd_object
2638 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2639 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2641 /* Right now GAS only outputs the address as a four-byte sequence.
2642 This means that we should not bother with this method on 64-bit
2643 targets (until that is fixed). */
2645 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2646 sizeof (struct mips_objfile_private
));
2648 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2650 else if (priv
== NULL
)
2654 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2655 sizeof (struct mips_objfile_private
));
2657 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2660 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2661 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2663 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2664 priv
->contents
, 0, priv
->size
);
2666 /* In general, the .pdr section is sorted. However, in the
2667 presence of multiple code sections (and other corner cases)
2668 it can become unsorted. Sort it so that we can use a faster
2670 qsort (priv
->contents
, priv
->size
/ 32, 32,
2671 compare_pdr_entries
);
2676 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2680 if (priv
->size
!= 0)
2687 high
= priv
->size
/ 32;
2689 /* We've found a .pdr section describing this objfile. We want to
2690 find the entry which describes this code address. The .pdr
2691 information is not very descriptive; we have only a function
2692 start address. We have to look for the closest entry, because
2693 the local symbol at the beginning of this function may have
2694 been stripped - so if we ask the symbol table for the start
2695 address we may get a preceding global function. */
2697 /* First, find the last .pdr entry starting at or before PC. */
2700 mid
= (low
+ high
) / 2;
2702 ptr
= priv
->contents
+ mid
* 32;
2703 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2704 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2705 SECT_OFF_TEXT (sec
->objfile
));
2712 while (low
!= high
);
2714 /* Both low and high point one past the PDR of interest. If
2715 both are zero, that means this PC is before any region
2716 covered by a PDR, i.e. pdr_pc for the first PDR entry is
2720 ptr
= priv
->contents
+ (low
- 1) * 32;
2721 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2722 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2723 SECT_OFF_TEXT (sec
->objfile
));
2726 /* We don't have a range, so we have no way to know for sure
2727 whether we're in the correct PDR or a PDR for a preceding
2728 function and the current function was a stripped local
2729 symbol. But if the PDR's PC is at least as great as the
2730 best guess from the symbol table, assume that it does cover
2731 the right area; if a .pdr section is present at all then
2732 nearly every function will have an entry. The biggest exception
2733 will be the dynamic linker stubs; conveniently these are
2734 placed before .text instead of after. */
2736 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
2738 struct symbol
*sym
= find_pc_function (pc
);
2743 /* Fill in what we need of the proc_desc. */
2744 proc_desc
= (mips_extra_func_info_t
)
2745 obstack_alloc (&sec
->objfile
->objfile_obstack
,
2746 sizeof (struct mips_extra_func_info
));
2747 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
2749 /* Only used for dummy frames. */
2750 PROC_HIGH_ADDR (proc_desc
) = 0;
2752 PROC_FRAME_OFFSET (proc_desc
)
2753 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2754 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2756 PROC_FRAME_ADJUST (proc_desc
) = 0;
2757 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2759 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2761 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2763 PROC_FREG_OFFSET (proc_desc
)
2764 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2765 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2767 proc_desc
->pdr
.isym
= (long) sym
;
2777 if (startaddr
> BLOCK_START (b
))
2779 /* This is the "pathological" case referred to in a comment in
2780 print_frame_info. It might be better to move this check into
2785 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2787 /* If we never found a PDR for this function in symbol reading, then
2788 examine prologues to find the information. */
2791 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2792 if (PROC_FRAME_REG (proc_desc
) == -1)
2801 /* MIPS stack frames are almost impenetrable. When execution stops,
2802 we basically have to look at symbol information for the function
2803 that we stopped in, which tells us *which* register (if any) is
2804 the base of the frame pointer, and what offset from that register
2805 the frame itself is at.
2807 This presents a problem when trying to examine a stack in memory
2808 (that isn't executing at the moment), using the "frame" command. We
2809 don't have a PC, nor do we have any registers except SP.
2811 This routine takes two arguments, SP and PC, and tries to make the
2812 cached frames look as if these two arguments defined a frame on the
2813 cache. This allows the rest of info frame to extract the important
2814 arguments without difficulty. */
2817 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2820 error ("MIPS frame specifications require two arguments: sp and pc");
2822 return create_new_frame (argv
[0], argv
[1]);
2825 /* According to the current ABI, should the type be passed in a
2826 floating-point register (assuming that there is space)? When there
2827 is no FPU, FP are not even considered as possibile candidates for
2828 FP registers and, consequently this returns false - forces FP
2829 arguments into integer registers. */
2832 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2834 return ((typecode
== TYPE_CODE_FLT
2836 && (typecode
== TYPE_CODE_STRUCT
2837 || typecode
== TYPE_CODE_UNION
)
2838 && TYPE_NFIELDS (arg_type
) == 1
2839 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2840 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2843 /* On o32, argument passing in GPRs depends on the alignment of the type being
2844 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2847 mips_type_needs_double_align (struct type
*type
)
2849 enum type_code typecode
= TYPE_CODE (type
);
2851 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2853 else if (typecode
== TYPE_CODE_STRUCT
)
2855 if (TYPE_NFIELDS (type
) < 1)
2857 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2859 else if (typecode
== TYPE_CODE_UNION
)
2863 n
= TYPE_NFIELDS (type
);
2864 for (i
= 0; i
< n
; i
++)
2865 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2872 /* Adjust the address downward (direction of stack growth) so that it
2873 is correctly aligned for a new stack frame. */
2875 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2877 return align_down (addr
, 16);
2881 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2882 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2883 int nargs
, struct value
**args
, CORE_ADDR sp
,
2884 int struct_return
, CORE_ADDR struct_addr
)
2890 int stack_offset
= 0;
2891 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2892 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2894 /* For shared libraries, "t9" needs to point at the function
2896 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2898 /* Set the return address register to point to the entry point of
2899 the program, where a breakpoint lies in wait. */
2900 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2902 /* First ensure that the stack and structure return address (if any)
2903 are properly aligned. The stack has to be at least 64-bit
2904 aligned even on 32-bit machines, because doubles must be 64-bit
2905 aligned. For n32 and n64, stack frames need to be 128-bit
2906 aligned, so we round to this widest known alignment. */
2908 sp
= align_down (sp
, 16);
2909 struct_addr
= align_down (struct_addr
, 16);
2911 /* Now make space on the stack for the args. We allocate more
2912 than necessary for EABI, because the first few arguments are
2913 passed in registers, but that's OK. */
2914 for (argnum
= 0; argnum
< nargs
; argnum
++)
2915 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2916 mips_stack_argsize (gdbarch
));
2917 sp
-= align_up (len
, 16);
2920 fprintf_unfiltered (gdb_stdlog
,
2921 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2922 paddr_nz (sp
), (long) align_up (len
, 16));
2924 /* Initialize the integer and float register pointers. */
2925 argreg
= MIPS_A0_REGNUM
;
2926 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2928 /* The struct_return pointer occupies the first parameter-passing reg. */
2932 fprintf_unfiltered (gdb_stdlog
,
2933 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2934 argreg
, paddr_nz (struct_addr
));
2935 write_register (argreg
++, struct_addr
);
2938 /* Now load as many as possible of the first arguments into
2939 registers, and push the rest onto the stack. Loop thru args
2940 from first to last. */
2941 for (argnum
= 0; argnum
< nargs
; argnum
++)
2944 char valbuf
[MAX_REGISTER_SIZE
];
2945 struct value
*arg
= args
[argnum
];
2946 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2947 int len
= TYPE_LENGTH (arg_type
);
2948 enum type_code typecode
= TYPE_CODE (arg_type
);
2951 fprintf_unfiltered (gdb_stdlog
,
2952 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2953 argnum
+ 1, len
, (int) typecode
);
2955 /* The EABI passes structures that do not fit in a register by
2957 if (len
> mips_abi_regsize (gdbarch
)
2958 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2960 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
2961 VALUE_ADDRESS (arg
));
2962 typecode
= TYPE_CODE_PTR
;
2963 len
= mips_abi_regsize (gdbarch
);
2966 fprintf_unfiltered (gdb_stdlog
, " push");
2969 val
= (char *) VALUE_CONTENTS (arg
);
2971 /* 32-bit ABIs always start floating point arguments in an
2972 even-numbered floating point register. Round the FP register
2973 up before the check to see if there are any FP registers
2974 left. Non MIPS_EABI targets also pass the FP in the integer
2975 registers so also round up normal registers. */
2976 if (mips_abi_regsize (gdbarch
) < 8
2977 && fp_register_arg_p (typecode
, arg_type
))
2979 if ((float_argreg
& 1))
2983 /* Floating point arguments passed in registers have to be
2984 treated specially. On 32-bit architectures, doubles
2985 are passed in register pairs; the even register gets
2986 the low word, and the odd register gets the high word.
2987 On non-EABI processors, the first two floating point arguments are
2988 also copied to general registers, because MIPS16 functions
2989 don't use float registers for arguments. This duplication of
2990 arguments in general registers can't hurt non-MIPS16 functions
2991 because those registers are normally skipped. */
2992 /* MIPS_EABI squeezes a struct that contains a single floating
2993 point value into an FP register instead of pushing it onto the
2995 if (fp_register_arg_p (typecode
, arg_type
)
2996 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2998 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3000 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3001 unsigned long regval
;
3003 /* Write the low word of the double to the even register(s). */
3004 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3006 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3007 float_argreg
, phex (regval
, 4));
3008 write_register (float_argreg
++, regval
);
3010 /* Write the high word of the double to the odd register(s). */
3011 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3013 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3014 float_argreg
, phex (regval
, 4));
3015 write_register (float_argreg
++, regval
);
3019 /* This is a floating point value that fits entirely
3020 in a single register. */
3021 /* On 32 bit ABI's the float_argreg is further adjusted
3022 above to ensure that it is even register aligned. */
3023 LONGEST regval
= extract_unsigned_integer (val
, len
);
3025 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3026 float_argreg
, phex (regval
, len
));
3027 write_register (float_argreg
++, regval
);
3032 /* Copy the argument to general registers or the stack in
3033 register-sized pieces. Large arguments are split between
3034 registers and stack. */
3035 /* Note: structs whose size is not a multiple of
3036 mips_abi_regsize() are treated specially: Irix cc passes
3037 them in registers where gcc sometimes puts them on the
3038 stack. For maximum compatibility, we will put them in
3040 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3041 && (len
% mips_abi_regsize (gdbarch
) != 0));
3043 /* Note: Floating-point values that didn't fit into an FP
3044 register are only written to memory. */
3047 /* Remember if the argument was written to the stack. */
3048 int stack_used_p
= 0;
3049 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3050 ? len
: mips_abi_regsize (gdbarch
));
3053 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3056 /* Write this portion of the argument to the stack. */
3057 if (argreg
> MIPS_LAST_ARG_REGNUM
3059 || fp_register_arg_p (typecode
, arg_type
))
3061 /* Should shorter than int integer values be
3062 promoted to int before being stored? */
3063 int longword_offset
= 0;
3066 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3068 if (mips_stack_argsize (gdbarch
) == 8
3069 && (typecode
== TYPE_CODE_INT
3070 || typecode
== TYPE_CODE_PTR
3071 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3072 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3073 else if ((typecode
== TYPE_CODE_STRUCT
3074 || typecode
== TYPE_CODE_UNION
)
3075 && (TYPE_LENGTH (arg_type
)
3076 < mips_stack_argsize (gdbarch
)))
3077 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3082 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3083 paddr_nz (stack_offset
));
3084 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3085 paddr_nz (longword_offset
));
3088 addr
= sp
+ stack_offset
+ longword_offset
;
3093 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3095 for (i
= 0; i
< partial_len
; i
++)
3097 fprintf_unfiltered (gdb_stdlog
, "%02x",
3101 write_memory (addr
, val
, partial_len
);
3104 /* Note!!! This is NOT an else clause. Odd sized
3105 structs may go thru BOTH paths. Floating point
3106 arguments will not. */
3107 /* Write this portion of the argument to a general
3108 purpose register. */
3109 if (argreg
<= MIPS_LAST_ARG_REGNUM
3110 && !fp_register_arg_p (typecode
, arg_type
))
3113 extract_unsigned_integer (val
, partial_len
);
3116 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3119 mips_abi_regsize (gdbarch
)));
3120 write_register (argreg
, regval
);
3127 /* Compute the the offset into the stack at which we
3128 will copy the next parameter.
3130 In the new EABI (and the NABI32), the stack_offset
3131 only needs to be adjusted when it has been used. */
3134 stack_offset
+= align_up (partial_len
,
3135 mips_stack_argsize (gdbarch
));
3139 fprintf_unfiltered (gdb_stdlog
, "\n");
3142 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3144 /* Return adjusted stack pointer. */
3148 /* Determin the return value convention being used. */
3150 static enum return_value_convention
3151 mips_eabi_return_value (struct gdbarch
*gdbarch
,
3152 struct type
*type
, struct regcache
*regcache
,
3153 void *readbuf
, const void *writebuf
)
3155 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3156 return RETURN_VALUE_STRUCT_CONVENTION
;
3158 memset (readbuf
, 0, TYPE_LENGTH (type
));
3159 return RETURN_VALUE_REGISTER_CONVENTION
;
3163 /* N32/N64 ABI stuff. */
3166 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3167 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3168 int nargs
, struct value
**args
, CORE_ADDR sp
,
3169 int struct_return
, CORE_ADDR struct_addr
)
3175 int stack_offset
= 0;
3176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3177 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3179 /* For shared libraries, "t9" needs to point at the function
3181 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3183 /* Set the return address register to point to the entry point of
3184 the program, where a breakpoint lies in wait. */
3185 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3187 /* First ensure that the stack and structure return address (if any)
3188 are properly aligned. The stack has to be at least 64-bit
3189 aligned even on 32-bit machines, because doubles must be 64-bit
3190 aligned. For n32 and n64, stack frames need to be 128-bit
3191 aligned, so we round to this widest known alignment. */
3193 sp
= align_down (sp
, 16);
3194 struct_addr
= align_down (struct_addr
, 16);
3196 /* Now make space on the stack for the args. */
3197 for (argnum
= 0; argnum
< nargs
; argnum
++)
3198 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3199 mips_stack_argsize (gdbarch
));
3200 sp
-= align_up (len
, 16);
3203 fprintf_unfiltered (gdb_stdlog
,
3204 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3205 paddr_nz (sp
), (long) align_up (len
, 16));
3207 /* Initialize the integer and float register pointers. */
3208 argreg
= MIPS_A0_REGNUM
;
3209 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3211 /* The struct_return pointer occupies the first parameter-passing reg. */
3215 fprintf_unfiltered (gdb_stdlog
,
3216 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3217 argreg
, paddr_nz (struct_addr
));
3218 write_register (argreg
++, struct_addr
);
3221 /* Now load as many as possible of the first arguments into
3222 registers, and push the rest onto the stack. Loop thru args
3223 from first to last. */
3224 for (argnum
= 0; argnum
< nargs
; argnum
++)
3227 struct value
*arg
= args
[argnum
];
3228 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3229 int len
= TYPE_LENGTH (arg_type
);
3230 enum type_code typecode
= TYPE_CODE (arg_type
);
3233 fprintf_unfiltered (gdb_stdlog
,
3234 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3235 argnum
+ 1, len
, (int) typecode
);
3237 val
= (char *) VALUE_CONTENTS (arg
);
3239 if (fp_register_arg_p (typecode
, arg_type
)
3240 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3242 /* This is a floating point value that fits entirely
3243 in a single register. */
3244 /* On 32 bit ABI's the float_argreg is further adjusted
3245 above to ensure that it is even register aligned. */
3246 LONGEST regval
= extract_unsigned_integer (val
, len
);
3248 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3249 float_argreg
, phex (regval
, len
));
3250 write_register (float_argreg
++, regval
);
3253 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3254 argreg
, phex (regval
, len
));
3255 write_register (argreg
, regval
);
3260 /* Copy the argument to general registers or the stack in
3261 register-sized pieces. Large arguments are split between
3262 registers and stack. */
3263 /* Note: structs whose size is not a multiple of
3264 mips_abi_regsize() are treated specially: Irix cc passes
3265 them in registers where gcc sometimes puts them on the
3266 stack. For maximum compatibility, we will put them in
3268 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3269 && (len
% mips_abi_regsize (gdbarch
) != 0));
3270 /* Note: Floating-point values that didn't fit into an FP
3271 register are only written to memory. */
3274 /* Rememer if the argument was written to the stack. */
3275 int stack_used_p
= 0;
3276 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3277 ? len
: mips_abi_regsize (gdbarch
));
3280 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3283 /* Write this portion of the argument to the stack. */
3284 if (argreg
> MIPS_LAST_ARG_REGNUM
3286 || fp_register_arg_p (typecode
, arg_type
))
3288 /* Should shorter than int integer values be
3289 promoted to int before being stored? */
3290 int longword_offset
= 0;
3293 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3295 if (mips_stack_argsize (gdbarch
) == 8
3296 && (typecode
== TYPE_CODE_INT
3297 || typecode
== TYPE_CODE_PTR
3298 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3299 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3304 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3305 paddr_nz (stack_offset
));
3306 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3307 paddr_nz (longword_offset
));
3310 addr
= sp
+ stack_offset
+ longword_offset
;
3315 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3317 for (i
= 0; i
< partial_len
; i
++)
3319 fprintf_unfiltered (gdb_stdlog
, "%02x",
3323 write_memory (addr
, val
, partial_len
);
3326 /* Note!!! This is NOT an else clause. Odd sized
3327 structs may go thru BOTH paths. Floating point
3328 arguments will not. */
3329 /* Write this portion of the argument to a general
3330 purpose register. */
3331 if (argreg
<= MIPS_LAST_ARG_REGNUM
3332 && !fp_register_arg_p (typecode
, arg_type
))
3335 extract_unsigned_integer (val
, partial_len
);
3337 /* A non-floating-point argument being passed in a
3338 general register. If a struct or union, and if
3339 the remaining length is smaller than the register
3340 size, we have to adjust the register value on
3343 It does not seem to be necessary to do the
3344 same for integral types.
3346 cagney/2001-07-23: gdb/179: Also, GCC, when
3347 outputting LE O32 with sizeof (struct) <
3348 mips_abi_regsize(), generates a left shift as
3349 part of storing the argument in a register a
3350 register (the left shift isn't generated when
3351 sizeof (struct) >= mips_abi_regsize()). Since
3352 it is quite possible that this is GCC
3353 contradicting the LE/O32 ABI, GDB has not been
3354 adjusted to accommodate this. Either someone
3355 needs to demonstrate that the LE/O32 ABI
3356 specifies such a left shift OR this new ABI gets
3357 identified as such and GDB gets tweaked
3360 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3361 && partial_len
< mips_abi_regsize (gdbarch
)
3362 && (typecode
== TYPE_CODE_STRUCT
||
3363 typecode
== TYPE_CODE_UNION
))
3364 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3368 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3371 mips_abi_regsize (gdbarch
)));
3372 write_register (argreg
, regval
);
3379 /* Compute the the offset into the stack at which we
3380 will copy the next parameter.
3382 In N32 (N64?), the stack_offset only needs to be
3383 adjusted when it has been used. */
3386 stack_offset
+= align_up (partial_len
,
3387 mips_stack_argsize (gdbarch
));
3391 fprintf_unfiltered (gdb_stdlog
, "\n");
3394 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3396 /* Return adjusted stack pointer. */
3400 static enum return_value_convention
3401 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3402 struct type
*type
, struct regcache
*regcache
,
3403 void *readbuf
, const void *writebuf
)
3405 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3406 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3407 || TYPE_CODE (type
) == TYPE_CODE_UNION
3408 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3409 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3410 return RETURN_VALUE_STRUCT_CONVENTION
;
3411 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3412 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3414 /* A floating-point value belongs in the least significant part
3417 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3418 mips_xfer_register (regcache
,
3419 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3421 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3422 return RETURN_VALUE_REGISTER_CONVENTION
;
3424 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3425 && TYPE_NFIELDS (type
) <= 2
3426 && TYPE_NFIELDS (type
) >= 1
3427 && ((TYPE_NFIELDS (type
) == 1
3428 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3430 || (TYPE_NFIELDS (type
) == 2
3431 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3433 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3435 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3437 /* A struct that contains one or two floats. Each value is part
3438 in the least significant part of their floating point
3442 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3443 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3445 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3448 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3450 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3451 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3452 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3454 return RETURN_VALUE_REGISTER_CONVENTION
;
3456 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3457 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3459 /* A structure or union. Extract the left justified value,
3460 regardless of the byte order. I.e. DO NOT USE
3464 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3465 offset
< TYPE_LENGTH (type
);
3466 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3468 int xfer
= register_size (current_gdbarch
, regnum
);
3469 if (offset
+ xfer
> TYPE_LENGTH (type
))
3470 xfer
= TYPE_LENGTH (type
) - offset
;
3472 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3473 offset
, xfer
, regnum
);
3474 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3475 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3477 return RETURN_VALUE_REGISTER_CONVENTION
;
3481 /* A scalar extract each part but least-significant-byte
3485 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3486 offset
< TYPE_LENGTH (type
);
3487 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3489 int xfer
= register_size (current_gdbarch
, regnum
);
3490 if (offset
+ xfer
> TYPE_LENGTH (type
))
3491 xfer
= TYPE_LENGTH (type
) - offset
;
3493 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3494 offset
, xfer
, regnum
);
3495 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3496 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3498 return RETURN_VALUE_REGISTER_CONVENTION
;
3502 /* O32 ABI stuff. */
3505 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3506 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3507 int nargs
, struct value
**args
, CORE_ADDR sp
,
3508 int struct_return
, CORE_ADDR struct_addr
)
3514 int stack_offset
= 0;
3515 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3516 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3518 /* For shared libraries, "t9" needs to point at the function
3520 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3522 /* Set the return address register to point to the entry point of
3523 the program, where a breakpoint lies in wait. */
3524 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3526 /* First ensure that the stack and structure return address (if any)
3527 are properly aligned. The stack has to be at least 64-bit
3528 aligned even on 32-bit machines, because doubles must be 64-bit
3529 aligned. For n32 and n64, stack frames need to be 128-bit
3530 aligned, so we round to this widest known alignment. */
3532 sp
= align_down (sp
, 16);
3533 struct_addr
= align_down (struct_addr
, 16);
3535 /* Now make space on the stack for the args. */
3536 for (argnum
= 0; argnum
< nargs
; argnum
++)
3537 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3538 mips_stack_argsize (gdbarch
));
3539 sp
-= align_up (len
, 16);
3542 fprintf_unfiltered (gdb_stdlog
,
3543 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3544 paddr_nz (sp
), (long) align_up (len
, 16));
3546 /* Initialize the integer and float register pointers. */
3547 argreg
= MIPS_A0_REGNUM
;
3548 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3550 /* The struct_return pointer occupies the first parameter-passing reg. */
3554 fprintf_unfiltered (gdb_stdlog
,
3555 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3556 argreg
, paddr_nz (struct_addr
));
3557 write_register (argreg
++, struct_addr
);
3558 stack_offset
+= mips_stack_argsize (gdbarch
);
3561 /* Now load as many as possible of the first arguments into
3562 registers, and push the rest onto the stack. Loop thru args
3563 from first to last. */
3564 for (argnum
= 0; argnum
< nargs
; argnum
++)
3567 struct value
*arg
= args
[argnum
];
3568 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3569 int len
= TYPE_LENGTH (arg_type
);
3570 enum type_code typecode
= TYPE_CODE (arg_type
);
3573 fprintf_unfiltered (gdb_stdlog
,
3574 "mips_o32_push_dummy_call: %d len=%d type=%d",
3575 argnum
+ 1, len
, (int) typecode
);
3577 val
= (char *) VALUE_CONTENTS (arg
);
3579 /* 32-bit ABIs always start floating point arguments in an
3580 even-numbered floating point register. Round the FP register
3581 up before the check to see if there are any FP registers
3582 left. O32/O64 targets also pass the FP in the integer
3583 registers so also round up normal registers. */
3584 if (mips_abi_regsize (gdbarch
) < 8
3585 && fp_register_arg_p (typecode
, arg_type
))
3587 if ((float_argreg
& 1))
3591 /* Floating point arguments passed in registers have to be
3592 treated specially. On 32-bit architectures, doubles
3593 are passed in register pairs; the even register gets
3594 the low word, and the odd register gets the high word.
3595 On O32/O64, the first two floating point arguments are
3596 also copied to general registers, because MIPS16 functions
3597 don't use float registers for arguments. This duplication of
3598 arguments in general registers can't hurt non-MIPS16 functions
3599 because those registers are normally skipped. */
3601 if (fp_register_arg_p (typecode
, arg_type
)
3602 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3604 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3606 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3607 unsigned long regval
;
3609 /* Write the low word of the double to the even register(s). */
3610 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3612 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3613 float_argreg
, phex (regval
, 4));
3614 write_register (float_argreg
++, regval
);
3616 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3617 argreg
, phex (regval
, 4));
3618 write_register (argreg
++, regval
);
3620 /* Write the high word of the double to the odd register(s). */
3621 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3623 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3624 float_argreg
, phex (regval
, 4));
3625 write_register (float_argreg
++, regval
);
3628 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3629 argreg
, phex (regval
, 4));
3630 write_register (argreg
++, regval
);
3634 /* This is a floating point value that fits entirely
3635 in a single register. */
3636 /* On 32 bit ABI's the float_argreg is further adjusted
3637 above to ensure that it is even register aligned. */
3638 LONGEST regval
= extract_unsigned_integer (val
, len
);
3640 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3641 float_argreg
, phex (regval
, len
));
3642 write_register (float_argreg
++, regval
);
3643 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3644 registers for each argument. The below is (my
3645 guess) to ensure that the corresponding integer
3646 register has reserved the same space. */
3648 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3649 argreg
, phex (regval
, len
));
3650 write_register (argreg
, regval
);
3651 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3653 /* Reserve space for the FP register. */
3654 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3658 /* Copy the argument to general registers or the stack in
3659 register-sized pieces. Large arguments are split between
3660 registers and stack. */
3661 /* Note: structs whose size is not a multiple of
3662 mips_abi_regsize() are treated specially: Irix cc passes
3663 them in registers where gcc sometimes puts them on the
3664 stack. For maximum compatibility, we will put them in
3666 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3667 && (len
% mips_abi_regsize (gdbarch
) != 0));
3668 /* Structures should be aligned to eight bytes (even arg registers)
3669 on MIPS_ABI_O32, if their first member has double precision. */
3670 if (mips_abi_regsize (gdbarch
) < 8
3671 && mips_type_needs_double_align (arg_type
))
3676 /* Note: Floating-point values that didn't fit into an FP
3677 register are only written to memory. */
3680 /* Remember if the argument was written to the stack. */
3681 int stack_used_p
= 0;
3682 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3683 ? len
: mips_abi_regsize (gdbarch
));
3686 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3689 /* Write this portion of the argument to the stack. */
3690 if (argreg
> MIPS_LAST_ARG_REGNUM
3692 || fp_register_arg_p (typecode
, arg_type
))
3694 /* Should shorter than int integer values be
3695 promoted to int before being stored? */
3696 int longword_offset
= 0;
3699 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3701 if (mips_stack_argsize (gdbarch
) == 8
3702 && (typecode
== TYPE_CODE_INT
3703 || typecode
== TYPE_CODE_PTR
3704 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3705 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3710 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3711 paddr_nz (stack_offset
));
3712 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3713 paddr_nz (longword_offset
));
3716 addr
= sp
+ stack_offset
+ longword_offset
;
3721 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3723 for (i
= 0; i
< partial_len
; i
++)
3725 fprintf_unfiltered (gdb_stdlog
, "%02x",
3729 write_memory (addr
, val
, partial_len
);
3732 /* Note!!! This is NOT an else clause. Odd sized
3733 structs may go thru BOTH paths. Floating point
3734 arguments will not. */
3735 /* Write this portion of the argument to a general
3736 purpose register. */
3737 if (argreg
<= MIPS_LAST_ARG_REGNUM
3738 && !fp_register_arg_p (typecode
, arg_type
))
3740 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3741 /* Value may need to be sign extended, because
3742 mips_isa_regsize() != mips_abi_regsize(). */
3744 /* A non-floating-point argument being passed in a
3745 general register. If a struct or union, and if
3746 the remaining length is smaller than the register
3747 size, we have to adjust the register value on
3750 It does not seem to be necessary to do the
3751 same for integral types.
3753 Also don't do this adjustment on O64 binaries.
3755 cagney/2001-07-23: gdb/179: Also, GCC, when
3756 outputting LE O32 with sizeof (struct) <
3757 mips_abi_regsize(), generates a left shift as
3758 part of storing the argument in a register a
3759 register (the left shift isn't generated when
3760 sizeof (struct) >= mips_abi_regsize()). Since
3761 it is quite possible that this is GCC
3762 contradicting the LE/O32 ABI, GDB has not been
3763 adjusted to accommodate this. Either someone
3764 needs to demonstrate that the LE/O32 ABI
3765 specifies such a left shift OR this new ABI gets
3766 identified as such and GDB gets tweaked
3769 if (mips_abi_regsize (gdbarch
) < 8
3770 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3771 && partial_len
< mips_abi_regsize (gdbarch
)
3772 && (typecode
== TYPE_CODE_STRUCT
||
3773 typecode
== TYPE_CODE_UNION
))
3774 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3778 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3781 mips_abi_regsize (gdbarch
)));
3782 write_register (argreg
, regval
);
3785 /* Prevent subsequent floating point arguments from
3786 being passed in floating point registers. */
3787 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3793 /* Compute the the offset into the stack at which we
3794 will copy the next parameter.
3796 In older ABIs, the caller reserved space for
3797 registers that contained arguments. This was loosely
3798 refered to as their "home". Consequently, space is
3799 always allocated. */
3801 stack_offset
+= align_up (partial_len
,
3802 mips_stack_argsize (gdbarch
));
3806 fprintf_unfiltered (gdb_stdlog
, "\n");
3809 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3811 /* Return adjusted stack pointer. */
3815 static enum return_value_convention
3816 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3817 struct regcache
*regcache
,
3818 void *readbuf
, const void *writebuf
)
3820 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3822 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3823 || TYPE_CODE (type
) == TYPE_CODE_UNION
3824 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3825 return RETURN_VALUE_STRUCT_CONVENTION
;
3826 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3827 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3829 /* A single-precision floating-point value. It fits in the
3830 least significant part of FP0. */
3832 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3833 mips_xfer_register (regcache
,
3834 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3836 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3837 return RETURN_VALUE_REGISTER_CONVENTION
;
3839 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3840 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3842 /* A double-precision floating-point value. The most
3843 significant part goes in FP1, and the least significant in
3846 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3847 switch (TARGET_BYTE_ORDER
)
3849 case BFD_ENDIAN_LITTLE
:
3850 mips_xfer_register (regcache
,
3851 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3852 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3853 mips_xfer_register (regcache
,
3854 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3855 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3857 case BFD_ENDIAN_BIG
:
3858 mips_xfer_register (regcache
,
3859 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3860 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3861 mips_xfer_register (regcache
,
3862 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3863 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3866 internal_error (__FILE__
, __LINE__
, "bad switch");
3868 return RETURN_VALUE_REGISTER_CONVENTION
;
3871 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3872 && TYPE_NFIELDS (type
) <= 2
3873 && TYPE_NFIELDS (type
) >= 1
3874 && ((TYPE_NFIELDS (type
) == 1
3875 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3877 || (TYPE_NFIELDS (type
) == 2
3878 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3880 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3882 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3884 /* A struct that contains one or two floats. Each value is part
3885 in the least significant part of their floating point
3887 bfd_byte reg
[MAX_REGISTER_SIZE
];
3890 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3891 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3893 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3896 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3898 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3899 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3900 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3902 return RETURN_VALUE_REGISTER_CONVENTION
;
3906 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3907 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3909 /* A structure or union. Extract the left justified value,
3910 regardless of the byte order. I.e. DO NOT USE
3914 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3915 offset
< TYPE_LENGTH (type
);
3916 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3918 int xfer
= register_size (current_gdbarch
, regnum
);
3919 if (offset
+ xfer
> TYPE_LENGTH (type
))
3920 xfer
= TYPE_LENGTH (type
) - offset
;
3922 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3923 offset
, xfer
, regnum
);
3924 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3925 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3927 return RETURN_VALUE_REGISTER_CONVENTION
;
3932 /* A scalar extract each part but least-significant-byte
3933 justified. o32 thinks registers are 4 byte, regardless of
3934 the ISA. mips_stack_argsize controls this. */
3937 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3938 offset
< TYPE_LENGTH (type
);
3939 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
3941 int xfer
= mips_stack_argsize (gdbarch
);
3942 if (offset
+ xfer
> TYPE_LENGTH (type
))
3943 xfer
= TYPE_LENGTH (type
) - offset
;
3945 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3946 offset
, xfer
, regnum
);
3947 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3948 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3950 return RETURN_VALUE_REGISTER_CONVENTION
;
3954 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3958 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3959 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3961 struct value
**args
, CORE_ADDR sp
,
3962 int struct_return
, CORE_ADDR struct_addr
)
3968 int stack_offset
= 0;
3969 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3970 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3972 /* For shared libraries, "t9" needs to point at the function
3974 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3976 /* Set the return address register to point to the entry point of
3977 the program, where a breakpoint lies in wait. */
3978 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3980 /* First ensure that the stack and structure return address (if any)
3981 are properly aligned. The stack has to be at least 64-bit
3982 aligned even on 32-bit machines, because doubles must be 64-bit
3983 aligned. For n32 and n64, stack frames need to be 128-bit
3984 aligned, so we round to this widest known alignment. */
3986 sp
= align_down (sp
, 16);
3987 struct_addr
= align_down (struct_addr
, 16);
3989 /* Now make space on the stack for the args. */
3990 for (argnum
= 0; argnum
< nargs
; argnum
++)
3991 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3992 mips_stack_argsize (gdbarch
));
3993 sp
-= align_up (len
, 16);
3996 fprintf_unfiltered (gdb_stdlog
,
3997 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3998 paddr_nz (sp
), (long) align_up (len
, 16));
4000 /* Initialize the integer and float register pointers. */
4001 argreg
= MIPS_A0_REGNUM
;
4002 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4004 /* The struct_return pointer occupies the first parameter-passing reg. */
4008 fprintf_unfiltered (gdb_stdlog
,
4009 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4010 argreg
, paddr_nz (struct_addr
));
4011 write_register (argreg
++, struct_addr
);
4012 stack_offset
+= mips_stack_argsize (gdbarch
);
4015 /* Now load as many as possible of the first arguments into
4016 registers, and push the rest onto the stack. Loop thru args
4017 from first to last. */
4018 for (argnum
= 0; argnum
< nargs
; argnum
++)
4021 struct value
*arg
= args
[argnum
];
4022 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4023 int len
= TYPE_LENGTH (arg_type
);
4024 enum type_code typecode
= TYPE_CODE (arg_type
);
4027 fprintf_unfiltered (gdb_stdlog
,
4028 "mips_o64_push_dummy_call: %d len=%d type=%d",
4029 argnum
+ 1, len
, (int) typecode
);
4031 val
= (char *) VALUE_CONTENTS (arg
);
4033 /* 32-bit ABIs always start floating point arguments in an
4034 even-numbered floating point register. Round the FP register
4035 up before the check to see if there are any FP registers
4036 left. O32/O64 targets also pass the FP in the integer
4037 registers so also round up normal registers. */
4038 if (mips_abi_regsize (gdbarch
) < 8
4039 && fp_register_arg_p (typecode
, arg_type
))
4041 if ((float_argreg
& 1))
4045 /* Floating point arguments passed in registers have to be
4046 treated specially. On 32-bit architectures, doubles
4047 are passed in register pairs; the even register gets
4048 the low word, and the odd register gets the high word.
4049 On O32/O64, the first two floating point arguments are
4050 also copied to general registers, because MIPS16 functions
4051 don't use float registers for arguments. This duplication of
4052 arguments in general registers can't hurt non-MIPS16 functions
4053 because those registers are normally skipped. */
4055 if (fp_register_arg_p (typecode
, arg_type
)
4056 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4058 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4060 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4061 unsigned long regval
;
4063 /* Write the low word of the double to the even register(s). */
4064 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4066 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4067 float_argreg
, phex (regval
, 4));
4068 write_register (float_argreg
++, regval
);
4070 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4071 argreg
, phex (regval
, 4));
4072 write_register (argreg
++, regval
);
4074 /* Write the high word of the double to the odd register(s). */
4075 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4077 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4078 float_argreg
, phex (regval
, 4));
4079 write_register (float_argreg
++, regval
);
4082 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4083 argreg
, phex (regval
, 4));
4084 write_register (argreg
++, regval
);
4088 /* This is a floating point value that fits entirely
4089 in a single register. */
4090 /* On 32 bit ABI's the float_argreg is further adjusted
4091 above to ensure that it is even register aligned. */
4092 LONGEST regval
= extract_unsigned_integer (val
, len
);
4094 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4095 float_argreg
, phex (regval
, len
));
4096 write_register (float_argreg
++, regval
);
4097 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4098 registers for each argument. The below is (my
4099 guess) to ensure that the corresponding integer
4100 register has reserved the same space. */
4102 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4103 argreg
, phex (regval
, len
));
4104 write_register (argreg
, regval
);
4105 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4107 /* Reserve space for the FP register. */
4108 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4112 /* Copy the argument to general registers or the stack in
4113 register-sized pieces. Large arguments are split between
4114 registers and stack. */
4115 /* Note: structs whose size is not a multiple of
4116 mips_abi_regsize() are treated specially: Irix cc passes
4117 them in registers where gcc sometimes puts them on the
4118 stack. For maximum compatibility, we will put them in
4120 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4121 && (len
% mips_abi_regsize (gdbarch
) != 0));
4122 /* Structures should be aligned to eight bytes (even arg registers)
4123 on MIPS_ABI_O32, if their first member has double precision. */
4124 if (mips_abi_regsize (gdbarch
) < 8
4125 && mips_type_needs_double_align (arg_type
))
4130 /* Note: Floating-point values that didn't fit into an FP
4131 register are only written to memory. */
4134 /* Remember if the argument was written to the stack. */
4135 int stack_used_p
= 0;
4136 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4137 ? len
: mips_abi_regsize (gdbarch
));
4140 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4143 /* Write this portion of the argument to the stack. */
4144 if (argreg
> MIPS_LAST_ARG_REGNUM
4146 || fp_register_arg_p (typecode
, arg_type
))
4148 /* Should shorter than int integer values be
4149 promoted to int before being stored? */
4150 int longword_offset
= 0;
4153 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4155 if (mips_stack_argsize (gdbarch
) == 8
4156 && (typecode
== TYPE_CODE_INT
4157 || typecode
== TYPE_CODE_PTR
4158 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4159 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4164 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4165 paddr_nz (stack_offset
));
4166 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4167 paddr_nz (longword_offset
));
4170 addr
= sp
+ stack_offset
+ longword_offset
;
4175 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4177 for (i
= 0; i
< partial_len
; i
++)
4179 fprintf_unfiltered (gdb_stdlog
, "%02x",
4183 write_memory (addr
, val
, partial_len
);
4186 /* Note!!! This is NOT an else clause. Odd sized
4187 structs may go thru BOTH paths. Floating point
4188 arguments will not. */
4189 /* Write this portion of the argument to a general
4190 purpose register. */
4191 if (argreg
<= MIPS_LAST_ARG_REGNUM
4192 && !fp_register_arg_p (typecode
, arg_type
))
4194 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4195 /* Value may need to be sign extended, because
4196 mips_isa_regsize() != mips_abi_regsize(). */
4198 /* A non-floating-point argument being passed in a
4199 general register. If a struct or union, and if
4200 the remaining length is smaller than the register
4201 size, we have to adjust the register value on
4204 It does not seem to be necessary to do the
4205 same for integral types.
4207 Also don't do this adjustment on O64 binaries.
4209 cagney/2001-07-23: gdb/179: Also, GCC, when
4210 outputting LE O32 with sizeof (struct) <
4211 mips_abi_regsize(), generates a left shift as
4212 part of storing the argument in a register a
4213 register (the left shift isn't generated when
4214 sizeof (struct) >= mips_abi_regsize()). Since
4215 it is quite possible that this is GCC
4216 contradicting the LE/O32 ABI, GDB has not been
4217 adjusted to accommodate this. Either someone
4218 needs to demonstrate that the LE/O32 ABI
4219 specifies such a left shift OR this new ABI gets
4220 identified as such and GDB gets tweaked
4223 if (mips_abi_regsize (gdbarch
) < 8
4224 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4225 && partial_len
< mips_abi_regsize (gdbarch
)
4226 && (typecode
== TYPE_CODE_STRUCT
||
4227 typecode
== TYPE_CODE_UNION
))
4228 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4232 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4235 mips_abi_regsize (gdbarch
)));
4236 write_register (argreg
, regval
);
4239 /* Prevent subsequent floating point arguments from
4240 being passed in floating point registers. */
4241 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4247 /* Compute the the offset into the stack at which we
4248 will copy the next parameter.
4250 In older ABIs, the caller reserved space for
4251 registers that contained arguments. This was loosely
4252 refered to as their "home". Consequently, space is
4253 always allocated. */
4255 stack_offset
+= align_up (partial_len
,
4256 mips_stack_argsize (gdbarch
));
4260 fprintf_unfiltered (gdb_stdlog
, "\n");
4263 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4265 /* Return adjusted stack pointer. */
4269 static enum return_value_convention
4270 mips_o64_return_value (struct gdbarch
*gdbarch
,
4271 struct type
*type
, struct regcache
*regcache
,
4272 void *readbuf
, const void *writebuf
)
4274 return RETURN_VALUE_STRUCT_CONVENTION
;
4277 /* Floating point register management.
4279 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4280 64bit operations, these early MIPS cpus treat fp register pairs
4281 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4282 registers and offer a compatibility mode that emulates the MIPS2 fp
4283 model. When operating in MIPS2 fp compat mode, later cpu's split
4284 double precision floats into two 32-bit chunks and store them in
4285 consecutive fp regs. To display 64-bit floats stored in this
4286 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4287 Throw in user-configurable endianness and you have a real mess.
4289 The way this works is:
4290 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4291 double-precision value will be split across two logical registers.
4292 The lower-numbered logical register will hold the low-order bits,
4293 regardless of the processor's endianness.
4294 - If we are on a 64-bit processor, and we are looking for a
4295 single-precision value, it will be in the low ordered bits
4296 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4297 save slot in memory.
4298 - If we are in 64-bit mode, everything is straightforward.
4300 Note that this code only deals with "live" registers at the top of the
4301 stack. We will attempt to deal with saved registers later, when
4302 the raw/cooked register interface is in place. (We need a general
4303 interface that can deal with dynamic saved register sizes -- fp
4304 regs could be 32 bits wide in one frame and 64 on the frame above
4307 static struct type
*
4308 mips_float_register_type (void)
4310 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4311 return builtin_type_ieee_single_big
;
4313 return builtin_type_ieee_single_little
;
4316 static struct type
*
4317 mips_double_register_type (void)
4319 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4320 return builtin_type_ieee_double_big
;
4322 return builtin_type_ieee_double_little
;
4325 /* Copy a 32-bit single-precision value from the current frame
4326 into rare_buffer. */
4329 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4332 int raw_size
= register_size (current_gdbarch
, regno
);
4333 char *raw_buffer
= alloca (raw_size
);
4335 if (!frame_register_read (frame
, regno
, raw_buffer
))
4336 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4339 /* We have a 64-bit value for this register. Find the low-order
4343 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4348 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4352 memcpy (rare_buffer
, raw_buffer
, 4);
4356 /* Copy a 64-bit double-precision value from the current frame into
4357 rare_buffer. This may include getting half of it from the next
4361 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4364 int raw_size
= register_size (current_gdbarch
, regno
);
4366 if (raw_size
== 8 && !mips2_fp_compat ())
4368 /* We have a 64-bit value for this register, and we should use
4370 if (!frame_register_read (frame
, regno
, rare_buffer
))
4371 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4375 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4376 internal_error (__FILE__
, __LINE__
,
4377 "mips_read_fp_register_double: bad access to "
4378 "odd-numbered FP register");
4380 /* mips_read_fp_register_single will find the correct 32 bits from
4382 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4384 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4385 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4389 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4390 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4396 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4398 { /* do values for FP (float) regs */
4400 double doub
, flt1
; /* doubles extracted from raw hex data */
4404 (char *) alloca (2 *
4405 register_size (current_gdbarch
,
4406 mips_regnum (current_gdbarch
)->fp0
));
4408 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4409 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4412 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4414 /* 4-byte registers: Print hex and floating. Also print even
4415 numbered registers as doubles. */
4416 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4417 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4419 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4422 fprintf_filtered (file
, " flt: ");
4424 fprintf_filtered (file
, " <invalid float> ");
4426 fprintf_filtered (file
, "%-17.9g", flt1
);
4428 if (regnum
% 2 == 0)
4430 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4431 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4434 fprintf_filtered (file
, " dbl: ");
4436 fprintf_filtered (file
, "<invalid double>");
4438 fprintf_filtered (file
, "%-24.17g", doub
);
4443 /* Eight byte registers: print each one as hex, float and double. */
4444 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4445 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4447 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4448 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4451 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4454 fprintf_filtered (file
, " flt: ");
4456 fprintf_filtered (file
, "<invalid float>");
4458 fprintf_filtered (file
, "%-17.9g", flt1
);
4460 fprintf_filtered (file
, " dbl: ");
4462 fprintf_filtered (file
, "<invalid double>");
4464 fprintf_filtered (file
, "%-24.17g", doub
);
4469 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4470 int regnum
, int all
)
4472 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4473 char raw_buffer
[MAX_REGISTER_SIZE
];
4476 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4478 mips_print_fp_register (file
, frame
, regnum
);
4482 /* Get the data in raw format. */
4483 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4485 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4489 fputs_filtered (REGISTER_NAME (regnum
), file
);
4491 /* The problem with printing numeric register names (r26, etc.) is that
4492 the user can't use them on input. Probably the best solution is to
4493 fix it so that either the numeric or the funky (a2, etc.) names
4494 are accepted on input. */
4495 if (regnum
< MIPS_NUMREGS
)
4496 fprintf_filtered (file
, "(r%d): ", regnum
);
4498 fprintf_filtered (file
, ": ");
4500 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4502 register_size (current_gdbarch
,
4503 regnum
) - register_size (current_gdbarch
, regnum
);
4507 print_scalar_formatted (raw_buffer
+ offset
,
4508 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4512 /* Replacement for generic do_registers_info.
4513 Print regs in pretty columns. */
4516 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4519 fprintf_filtered (file
, " ");
4520 mips_print_fp_register (file
, frame
, regnum
);
4521 fprintf_filtered (file
, "\n");
4526 /* Print a row's worth of GP (int) registers, with name labels above */
4529 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4532 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4533 /* do values for GP (int) regs */
4534 char raw_buffer
[MAX_REGISTER_SIZE
];
4535 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4539 /* For GP registers, we print a separate row of names above the vals */
4540 fprintf_filtered (file
, " ");
4541 for (col
= 0, regnum
= start_regnum
;
4542 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4544 if (*REGISTER_NAME (regnum
) == '\0')
4545 continue; /* unused register */
4546 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4548 break; /* end the row: reached FP register */
4549 fprintf_filtered (file
,
4550 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4551 REGISTER_NAME (regnum
));
4554 /* print the R0 to R31 names */
4555 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4556 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4558 fprintf_filtered (file
, "\n ");
4560 /* now print the values in hex, 4 or 8 to the row */
4561 for (col
= 0, regnum
= start_regnum
;
4562 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4564 if (*REGISTER_NAME (regnum
) == '\0')
4565 continue; /* unused register */
4566 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4568 break; /* end row: reached FP register */
4569 /* OK: get the data in raw format. */
4570 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4571 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4572 /* pad small registers */
4574 byte
< (mips_abi_regsize (current_gdbarch
)
4575 - register_size (current_gdbarch
, regnum
)); byte
++)
4576 printf_filtered (" ");
4577 /* Now print the register value in hex, endian order. */
4578 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4580 register_size (current_gdbarch
,
4581 regnum
) - register_size (current_gdbarch
, regnum
);
4582 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4583 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4585 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4587 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4588 fprintf_filtered (file
, " ");
4591 if (col
> 0) /* ie. if we actually printed anything... */
4592 fprintf_filtered (file
, "\n");
4597 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4600 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4601 struct frame_info
*frame
, int regnum
, int all
)
4603 if (regnum
!= -1) /* do one specified register */
4605 gdb_assert (regnum
>= NUM_REGS
);
4606 if (*(REGISTER_NAME (regnum
)) == '\0')
4607 error ("Not a valid register for the current processor type");
4609 mips_print_register (file
, frame
, regnum
, 0);
4610 fprintf_filtered (file
, "\n");
4613 /* do all (or most) registers */
4616 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4618 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4621 if (all
) /* true for "INFO ALL-REGISTERS" command */
4622 regnum
= print_fp_register_row (file
, frame
, regnum
);
4624 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4627 regnum
= print_gp_register_row (file
, frame
, regnum
);
4632 /* Is this a branch with a delay slot? */
4635 is_delayed (unsigned long insn
)
4638 for (i
= 0; i
< NUMOPCODES
; ++i
)
4639 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4640 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4642 return (i
< NUMOPCODES
4643 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4644 | INSN_COND_BRANCH_DELAY
4645 | INSN_COND_BRANCH_LIKELY
)));
4649 mips_step_skips_delay (CORE_ADDR pc
)
4651 char buf
[MIPS32_INSN_SIZE
];
4653 /* There is no branch delay slot on MIPS16. */
4654 if (mips_pc_is_mips16 (pc
))
4657 if (target_read_memory (pc
, buf
, sizeof buf
) != 0)
4658 /* If error reading memory, guess that it is not a delayed branch. */
4660 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4663 /* To skip prologues, I use this predicate. Returns either PC itself
4664 if the code at PC does not look like a function prologue; otherwise
4665 returns an address that (if we're lucky) follows the prologue. If
4666 LENIENT, then we must skip everything which is involved in setting
4667 up the frame (it's OK to skip more, just so long as we don't skip
4668 anything which might clobber the registers which are being saved.
4669 We must skip more in the case where part of the prologue is in the
4670 delay slot of a non-prologue instruction). */
4673 mips_skip_prologue (CORE_ADDR pc
)
4676 CORE_ADDR func_addr
;
4678 /* See if we can determine the end of the prologue via the symbol table.
4679 If so, then return either PC, or the PC after the prologue, whichever
4681 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4683 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4684 if (post_prologue_pc
!= 0)
4685 return max (pc
, post_prologue_pc
);
4688 /* Can't determine prologue from the symbol table, need to examine
4691 /* Find an upper limit on the function prologue using the debug
4692 information. If the debug information could not be used to provide
4693 that bound, then use an arbitrary large number as the upper bound. */
4694 limit_pc
= skip_prologue_using_sal (pc
);
4696 limit_pc
= pc
+ 100; /* Magic. */
4698 if (mips_pc_is_mips16 (pc
))
4699 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4701 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4704 /* Root of all "set mips "/"show mips " commands. This will eventually be
4705 used for all MIPS-specific commands. */
4708 show_mips_command (char *args
, int from_tty
)
4710 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4714 set_mips_command (char *args
, int from_tty
)
4717 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4718 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4721 /* Commands to show/set the MIPS FPU type. */
4724 show_mipsfpu_command (char *args
, int from_tty
)
4727 switch (MIPS_FPU_TYPE
)
4729 case MIPS_FPU_SINGLE
:
4730 fpu
= "single-precision";
4732 case MIPS_FPU_DOUBLE
:
4733 fpu
= "double-precision";
4736 fpu
= "absent (none)";
4739 internal_error (__FILE__
, __LINE__
, "bad switch");
4741 if (mips_fpu_type_auto
)
4743 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4747 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4752 set_mipsfpu_command (char *args
, int from_tty
)
4755 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4756 show_mipsfpu_command (args
, from_tty
);
4760 set_mipsfpu_single_command (char *args
, int from_tty
)
4762 struct gdbarch_info info
;
4763 gdbarch_info_init (&info
);
4764 mips_fpu_type
= MIPS_FPU_SINGLE
;
4765 mips_fpu_type_auto
= 0;
4766 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4767 instead of relying on globals. Doing that would let generic code
4768 handle the search for this specific architecture. */
4769 if (!gdbarch_update_p (info
))
4770 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4774 set_mipsfpu_double_command (char *args
, int from_tty
)
4776 struct gdbarch_info info
;
4777 gdbarch_info_init (&info
);
4778 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4779 mips_fpu_type_auto
= 0;
4780 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4781 instead of relying on globals. Doing that would let generic code
4782 handle the search for this specific architecture. */
4783 if (!gdbarch_update_p (info
))
4784 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4788 set_mipsfpu_none_command (char *args
, int from_tty
)
4790 struct gdbarch_info info
;
4791 gdbarch_info_init (&info
);
4792 mips_fpu_type
= MIPS_FPU_NONE
;
4793 mips_fpu_type_auto
= 0;
4794 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4795 instead of relying on globals. Doing that would let generic code
4796 handle the search for this specific architecture. */
4797 if (!gdbarch_update_p (info
))
4798 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4802 set_mipsfpu_auto_command (char *args
, int from_tty
)
4804 mips_fpu_type_auto
= 1;
4807 /* Attempt to identify the particular processor model by reading the
4808 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4809 the relevant processor still exists (it dates back to '94) and
4810 secondly this is not the way to do this. The processor type should
4811 be set by forcing an architecture change. */
4814 deprecated_mips_set_processor_regs_hack (void)
4816 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4819 prid
= read_register (PRID_REGNUM
);
4821 if ((prid
& ~0xf) == 0x700)
4822 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4825 /* Just like reinit_frame_cache, but with the right arguments to be
4826 callable as an sfunc. */
4829 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4830 struct cmd_list_element
*c
)
4832 reinit_frame_cache ();
4836 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4838 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4840 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4841 disassembler needs to be able to locally determine the ISA, and
4842 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4844 if (mips_pc_is_mips16 (memaddr
))
4845 info
->mach
= bfd_mach_mips16
;
4847 /* Round down the instruction address to the appropriate boundary. */
4848 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4850 /* Set the disassembler options. */
4851 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4853 /* Set up the disassembler info, so that we get the right
4854 register names from libopcodes. */
4855 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4856 info
->disassembler_options
= "gpr-names=n32";
4858 info
->disassembler_options
= "gpr-names=64";
4859 info
->flavour
= bfd_target_elf_flavour
;
4862 /* This string is not recognized explicitly by the disassembler,
4863 but it tells the disassembler to not try to guess the ABI from
4864 the bfd elf headers, such that, if the user overrides the ABI
4865 of a program linked as NewABI, the disassembly will follow the
4866 register naming conventions specified by the user. */
4867 info
->disassembler_options
= "gpr-names=32";
4869 /* Call the appropriate disassembler based on the target endian-ness. */
4870 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4871 return print_insn_big_mips (memaddr
, info
);
4873 return print_insn_little_mips (memaddr
, info
);
4876 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4877 counter value to determine whether a 16- or 32-bit breakpoint should be
4878 used. It returns a pointer to a string of bytes that encode a breakpoint
4879 instruction, stores the length of the string to *lenptr, and adjusts pc
4880 (if necessary) to point to the actual memory location where the
4881 breakpoint should be inserted. */
4883 static const unsigned char *
4884 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4886 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4888 if (mips_pc_is_mips16 (*pcptr
))
4890 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4891 *pcptr
= unmake_mips16_addr (*pcptr
);
4892 *lenptr
= sizeof (mips16_big_breakpoint
);
4893 return mips16_big_breakpoint
;
4897 /* The IDT board uses an unusual breakpoint value, and
4898 sometimes gets confused when it sees the usual MIPS
4899 breakpoint instruction. */
4900 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4901 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4902 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4904 *lenptr
= sizeof (big_breakpoint
);
4906 if (strcmp (target_shortname
, "mips") == 0)
4907 return idt_big_breakpoint
;
4908 else if (strcmp (target_shortname
, "ddb") == 0
4909 || strcmp (target_shortname
, "pmon") == 0
4910 || strcmp (target_shortname
, "lsi") == 0)
4911 return pmon_big_breakpoint
;
4913 return big_breakpoint
;
4918 if (mips_pc_is_mips16 (*pcptr
))
4920 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4921 *pcptr
= unmake_mips16_addr (*pcptr
);
4922 *lenptr
= sizeof (mips16_little_breakpoint
);
4923 return mips16_little_breakpoint
;
4927 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4928 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4929 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4931 *lenptr
= sizeof (little_breakpoint
);
4933 if (strcmp (target_shortname
, "mips") == 0)
4934 return idt_little_breakpoint
;
4935 else if (strcmp (target_shortname
, "ddb") == 0
4936 || strcmp (target_shortname
, "pmon") == 0
4937 || strcmp (target_shortname
, "lsi") == 0)
4938 return pmon_little_breakpoint
;
4940 return little_breakpoint
;
4945 /* If PC is in a mips16 call or return stub, return the address of the target
4946 PC, which is either the callee or the caller. There are several
4947 cases which must be handled:
4949 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4950 target PC is in $31 ($ra).
4951 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4952 and the target PC is in $2.
4953 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4954 before the jal instruction, this is effectively a call stub
4955 and the the target PC is in $2. Otherwise this is effectively
4956 a return stub and the target PC is in $18.
4958 See the source code for the stubs in gcc/config/mips/mips16.S for
4962 mips_skip_trampoline_code (CORE_ADDR pc
)
4965 CORE_ADDR start_addr
;
4967 /* Find the starting address and name of the function containing the PC. */
4968 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4971 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4972 target PC is in $31 ($ra). */
4973 if (strcmp (name
, "__mips16_ret_sf") == 0
4974 || strcmp (name
, "__mips16_ret_df") == 0)
4975 return read_signed_register (MIPS_RA_REGNUM
);
4977 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4979 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4980 and the target PC is in $2. */
4981 if (name
[19] >= '0' && name
[19] <= '9')
4982 return read_signed_register (2);
4984 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4985 before the jal instruction, this is effectively a call stub
4986 and the the target PC is in $2. Otherwise this is effectively
4987 a return stub and the target PC is in $18. */
4988 else if (name
[19] == 's' || name
[19] == 'd')
4990 if (pc
== start_addr
)
4992 /* Check if the target of the stub is a compiler-generated
4993 stub. Such a stub for a function bar might have a name
4994 like __fn_stub_bar, and might look like this:
4999 la $1,bar (becomes a lui/addiu pair)
5001 So scan down to the lui/addi and extract the target
5002 address from those two instructions. */
5004 CORE_ADDR target_pc
= read_signed_register (2);
5008 /* See if the name of the target function is __fn_stub_*. */
5009 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5012 if (strncmp (name
, "__fn_stub_", 10) != 0
5013 && strcmp (name
, "etext") != 0
5014 && strcmp (name
, "_etext") != 0)
5017 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5018 The limit on the search is arbitrarily set to 20
5019 instructions. FIXME. */
5020 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS32_INSN_SIZE
)
5022 inst
= mips_fetch_instruction (target_pc
);
5023 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5024 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5025 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5026 return pc
| (inst
& 0xffff); /* low word */
5029 /* Couldn't find the lui/addui pair, so return stub address. */
5033 /* This is the 'return' part of a call stub. The return
5034 address is in $r18. */
5035 return read_signed_register (18);
5038 return 0; /* not a stub */
5042 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5043 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5046 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5048 CORE_ADDR start_addr
;
5050 /* Find the starting address of the function containing the PC. If the
5051 caller didn't give us a name, look it up at the same time. */
5052 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5056 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5058 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5059 if (name
[19] >= '0' && name
[19] <= '9')
5061 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5062 before the jal instruction, this is effectively a call stub. */
5063 else if (name
[19] == 's' || name
[19] == 'd')
5064 return pc
== start_addr
;
5067 return 0; /* not a stub */
5071 /* Return non-zero if the PC is inside a return thunk (aka stub or
5075 mips_in_solib_return_trampoline (CORE_ADDR pc
, char *name
)
5077 CORE_ADDR start_addr
;
5079 /* Find the starting address of the function containing the PC. */
5080 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5083 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5084 if (strcmp (name
, "__mips16_ret_sf") == 0
5085 || strcmp (name
, "__mips16_ret_df") == 0)
5088 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5089 i.e. after the jal instruction, this is effectively a return stub. */
5090 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5091 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5094 return 0; /* not a stub */
5098 /* Return non-zero if the PC is in a library helper function that
5099 should be ignored. This implements the
5100 DEPRECATED_IGNORE_HELPER_CALL macro. */
5103 mips_ignore_helper (CORE_ADDR pc
)
5107 /* Find the starting address and name of the function containing the PC. */
5108 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5111 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5112 that we want to ignore. */
5113 return (strcmp (name
, "__mips16_ret_sf") == 0
5114 || strcmp (name
, "__mips16_ret_df") == 0);
5118 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5119 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5122 mips_stab_reg_to_regnum (int num
)
5125 if (num
>= 0 && num
< 32)
5127 else if (num
>= 38 && num
< 70)
5128 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5130 regnum
= mips_regnum (current_gdbarch
)->hi
;
5132 regnum
= mips_regnum (current_gdbarch
)->lo
;
5134 /* This will hopefully (eventually) provoke a warning. Should
5135 we be calling complaint() here? */
5136 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5137 return NUM_REGS
+ regnum
;
5141 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5142 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5145 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5148 if (num
>= 0 && num
< 32)
5150 else if (num
>= 32 && num
< 64)
5151 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5153 regnum
= mips_regnum (current_gdbarch
)->hi
;
5155 regnum
= mips_regnum (current_gdbarch
)->lo
;
5157 /* This will hopefully (eventually) provoke a warning. Should we
5158 be calling complaint() here? */
5159 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5160 return NUM_REGS
+ regnum
;
5164 mips_register_sim_regno (int regnum
)
5166 /* Only makes sense to supply raw registers. */
5167 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5168 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5169 decide if it is valid. Should instead define a standard sim/gdb
5170 register numbering scheme. */
5171 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5172 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5175 return LEGACY_SIM_REGNO_IGNORE
;
5179 /* Convert an integer into an address. By first converting the value
5180 into a pointer and then extracting it signed, the address is
5181 guarenteed to be correctly sign extended. */
5184 mips_integer_to_address (struct type
*type
, void *buf
)
5186 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5187 LONGEST val
= unpack_long (type
, buf
);
5188 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5189 return extract_signed_integer (tmp
,
5190 TYPE_LENGTH (builtin_type_void_data_ptr
));
5194 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5196 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5197 const char *name
= bfd_get_section_name (abfd
, sect
);
5199 if (*abip
!= MIPS_ABI_UNKNOWN
)
5202 if (strncmp (name
, ".mdebug.", 8) != 0)
5205 if (strcmp (name
, ".mdebug.abi32") == 0)
5206 *abip
= MIPS_ABI_O32
;
5207 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5208 *abip
= MIPS_ABI_N32
;
5209 else if (strcmp (name
, ".mdebug.abi64") == 0)
5210 *abip
= MIPS_ABI_N64
;
5211 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5212 *abip
= MIPS_ABI_O64
;
5213 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5214 *abip
= MIPS_ABI_EABI32
;
5215 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5216 *abip
= MIPS_ABI_EABI64
;
5218 warning ("unsupported ABI %s.", name
+ 8);
5221 static enum mips_abi
5222 global_mips_abi (void)
5226 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5227 if (mips_abi_strings
[i
] == mips_abi_string
)
5228 return (enum mips_abi
) i
;
5230 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5233 static struct gdbarch
*
5234 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5236 struct gdbarch
*gdbarch
;
5237 struct gdbarch_tdep
*tdep
;
5239 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5241 enum mips_fpu_type fpu_type
;
5243 /* First of all, extract the elf_flags, if available. */
5244 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5245 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5246 else if (arches
!= NULL
)
5247 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5251 fprintf_unfiltered (gdb_stdlog
,
5252 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5254 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5255 switch ((elf_flags
& EF_MIPS_ABI
))
5257 case E_MIPS_ABI_O32
:
5258 found_abi
= MIPS_ABI_O32
;
5260 case E_MIPS_ABI_O64
:
5261 found_abi
= MIPS_ABI_O64
;
5263 case E_MIPS_ABI_EABI32
:
5264 found_abi
= MIPS_ABI_EABI32
;
5266 case E_MIPS_ABI_EABI64
:
5267 found_abi
= MIPS_ABI_EABI64
;
5270 if ((elf_flags
& EF_MIPS_ABI2
))
5271 found_abi
= MIPS_ABI_N32
;
5273 found_abi
= MIPS_ABI_UNKNOWN
;
5277 /* GCC creates a pseudo-section whose name describes the ABI. */
5278 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5279 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5281 /* If we have no useful BFD information, use the ABI from the last
5282 MIPS architecture (if there is one). */
5283 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5284 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5286 /* Try the architecture for any hint of the correct ABI. */
5287 if (found_abi
== MIPS_ABI_UNKNOWN
5288 && info
.bfd_arch_info
!= NULL
5289 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5291 switch (info
.bfd_arch_info
->mach
)
5293 case bfd_mach_mips3900
:
5294 found_abi
= MIPS_ABI_EABI32
;
5296 case bfd_mach_mips4100
:
5297 case bfd_mach_mips5000
:
5298 found_abi
= MIPS_ABI_EABI64
;
5300 case bfd_mach_mips8000
:
5301 case bfd_mach_mips10000
:
5302 /* On Irix, ELF64 executables use the N64 ABI. The
5303 pseudo-sections which describe the ABI aren't present
5304 on IRIX. (Even for executables created by gcc.) */
5305 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5306 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5307 found_abi
= MIPS_ABI_N64
;
5309 found_abi
= MIPS_ABI_N32
;
5315 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5318 /* What has the user specified from the command line? */
5319 wanted_abi
= global_mips_abi ();
5321 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5324 /* Now that we have found what the ABI for this binary would be,
5325 check whether the user is overriding it. */
5326 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5327 mips_abi
= wanted_abi
;
5328 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5329 mips_abi
= found_abi
;
5331 mips_abi
= MIPS_ABI_O32
;
5333 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5336 /* Also used when doing an architecture lookup. */
5338 fprintf_unfiltered (gdb_stdlog
,
5339 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5340 mips64_transfers_32bit_regs_p
);
5342 /* Determine the MIPS FPU type. */
5343 if (!mips_fpu_type_auto
)
5344 fpu_type
= mips_fpu_type
;
5345 else if (info
.bfd_arch_info
!= NULL
5346 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5347 switch (info
.bfd_arch_info
->mach
)
5349 case bfd_mach_mips3900
:
5350 case bfd_mach_mips4100
:
5351 case bfd_mach_mips4111
:
5352 case bfd_mach_mips4120
:
5353 fpu_type
= MIPS_FPU_NONE
;
5355 case bfd_mach_mips4650
:
5356 fpu_type
= MIPS_FPU_SINGLE
;
5359 fpu_type
= MIPS_FPU_DOUBLE
;
5362 else if (arches
!= NULL
)
5363 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5365 fpu_type
= MIPS_FPU_DOUBLE
;
5367 fprintf_unfiltered (gdb_stdlog
,
5368 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5370 /* try to find a pre-existing architecture */
5371 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5373 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5375 /* MIPS needs to be pedantic about which ABI the object is
5377 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5379 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5381 /* Need to be pedantic about which register virtual size is
5383 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5384 != mips64_transfers_32bit_regs_p
)
5386 /* Be pedantic about which FPU is selected. */
5387 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5389 return arches
->gdbarch
;
5392 /* Need a new architecture. Fill in a target specific vector. */
5393 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5394 gdbarch
= gdbarch_alloc (&info
, tdep
);
5395 tdep
->elf_flags
= elf_flags
;
5396 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5397 tdep
->found_abi
= found_abi
;
5398 tdep
->mips_abi
= mips_abi
;
5399 tdep
->mips_fpu_type
= fpu_type
;
5401 /* Initially set everything according to the default ABI/ISA. */
5402 set_gdbarch_short_bit (gdbarch
, 16);
5403 set_gdbarch_int_bit (gdbarch
, 32);
5404 set_gdbarch_float_bit (gdbarch
, 32);
5405 set_gdbarch_double_bit (gdbarch
, 64);
5406 set_gdbarch_long_double_bit (gdbarch
, 64);
5407 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5408 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5409 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5411 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5412 mips_elf_make_msymbol_special
);
5414 /* Fill in the OS dependant register numbers and names. */
5416 const char **reg_names
;
5417 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5418 struct mips_regnum
);
5419 if (info
.osabi
== GDB_OSABI_IRIX
)
5424 regnum
->badvaddr
= 66;
5427 regnum
->fp_control_status
= 69;
5428 regnum
->fp_implementation_revision
= 70;
5430 reg_names
= mips_irix_reg_names
;
5434 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5435 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5436 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5437 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5438 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5439 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5440 regnum
->fp_control_status
= 70;
5441 regnum
->fp_implementation_revision
= 71;
5443 if (info
.bfd_arch_info
!= NULL
5444 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5445 reg_names
= mips_tx39_reg_names
;
5447 reg_names
= mips_generic_reg_names
;
5449 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5450 replaced by read_pc? */
5451 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5452 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5453 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5454 set_gdbarch_num_regs (gdbarch
, num_regs
);
5455 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5456 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5457 tdep
->mips_processor_reg_names
= reg_names
;
5458 tdep
->regnum
= regnum
;
5464 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5465 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5466 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5467 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5468 tdep
->default_mask_address_p
= 0;
5469 set_gdbarch_long_bit (gdbarch
, 32);
5470 set_gdbarch_ptr_bit (gdbarch
, 32);
5471 set_gdbarch_long_long_bit (gdbarch
, 64);
5474 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5475 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5476 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5477 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5478 tdep
->default_mask_address_p
= 0;
5479 set_gdbarch_long_bit (gdbarch
, 32);
5480 set_gdbarch_ptr_bit (gdbarch
, 32);
5481 set_gdbarch_long_long_bit (gdbarch
, 64);
5483 case MIPS_ABI_EABI32
:
5484 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5485 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5486 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5487 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5488 tdep
->default_mask_address_p
= 0;
5489 set_gdbarch_long_bit (gdbarch
, 32);
5490 set_gdbarch_ptr_bit (gdbarch
, 32);
5491 set_gdbarch_long_long_bit (gdbarch
, 64);
5493 case MIPS_ABI_EABI64
:
5494 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5495 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5496 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5497 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5498 tdep
->default_mask_address_p
= 0;
5499 set_gdbarch_long_bit (gdbarch
, 64);
5500 set_gdbarch_ptr_bit (gdbarch
, 64);
5501 set_gdbarch_long_long_bit (gdbarch
, 64);
5504 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5505 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5506 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5507 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5508 tdep
->default_mask_address_p
= 0;
5509 set_gdbarch_long_bit (gdbarch
, 32);
5510 set_gdbarch_ptr_bit (gdbarch
, 32);
5511 set_gdbarch_long_long_bit (gdbarch
, 64);
5512 set_gdbarch_long_double_bit (gdbarch
, 128);
5513 set_gdbarch_long_double_format (gdbarch
,
5514 &floatformat_n32n64_long_double_big
);
5517 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5518 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5519 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5520 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5521 tdep
->default_mask_address_p
= 0;
5522 set_gdbarch_long_bit (gdbarch
, 64);
5523 set_gdbarch_ptr_bit (gdbarch
, 64);
5524 set_gdbarch_long_long_bit (gdbarch
, 64);
5525 set_gdbarch_long_double_bit (gdbarch
, 128);
5526 set_gdbarch_long_double_format (gdbarch
,
5527 &floatformat_n32n64_long_double_big
);
5530 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
5533 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5534 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5537 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5538 flag in object files because to do so would make it impossible to
5539 link with libraries compiled without "-gp32". This is
5540 unnecessarily restrictive.
5542 We could solve this problem by adding "-gp32" multilibs to gcc,
5543 but to set this flag before gcc is built with such multilibs will
5544 break too many systems.''
5546 But even more unhelpfully, the default linker output target for
5547 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5548 for 64-bit programs - you need to change the ABI to change this,
5549 and not all gcc targets support that currently. Therefore using
5550 this flag to detect 32-bit mode would do the wrong thing given
5551 the current gcc - it would make GDB treat these 64-bit programs
5552 as 32-bit programs by default. */
5554 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5555 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5556 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5558 /* Add/remove bits from an address. The MIPS needs be careful to
5559 ensure that all 32 bit addresses are sign extended to 64 bits. */
5560 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5562 /* Unwind the frame. */
5563 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5564 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5566 /* Map debug register numbers onto internal register numbers. */
5567 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5568 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5569 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5570 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5571 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5572 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5573 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5574 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5576 /* MIPS version of CALL_DUMMY */
5578 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5579 replaced by a command, and all targets will default to on stack
5580 (regardless of the stack's execute status). */
5581 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5582 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5584 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5585 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5586 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5588 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5589 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5591 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5593 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5594 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5595 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5597 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5599 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5601 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5603 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5604 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5605 need to all be folded into the target vector. Since they are
5606 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5607 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5609 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5611 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5613 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
5614 to support MIPS16. This is a bad thing. Make sure not to do it
5615 if we have an OS ABI that actually supports shared libraries, since
5616 shared library support is more important. If we have an OS someday
5617 that supports both shared libraries and MIPS16, we'll have to find
5618 a better place for these. */
5619 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
5621 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
5622 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_solib_return_trampoline
);
5625 /* Hook in OS ABI-specific overrides, if they have been registered. */
5626 gdbarch_init_osabi (info
, gdbarch
);
5628 /* Unwind the frame. */
5629 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5630 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
5631 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5632 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5633 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5634 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
5635 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5636 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5642 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5644 struct gdbarch_info info
;
5646 /* Force the architecture to update, and (if it's a MIPS architecture)
5647 mips_gdbarch_init will take care of the rest. */
5648 gdbarch_info_init (&info
);
5649 gdbarch_update_p (info
);
5652 /* Print out which MIPS ABI is in use. */
5655 show_mips_abi (char *ignore_args
, int from_tty
)
5657 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5659 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
5662 enum mips_abi global_abi
= global_mips_abi ();
5663 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5664 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5666 if (global_abi
== MIPS_ABI_UNKNOWN
)
5668 ("The MIPS ABI is set automatically (currently \"%s\").\n",
5670 else if (global_abi
== actual_abi
)
5672 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5676 /* Probably shouldn't happen... */
5678 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5679 actual_abi_str
, mips_abi_strings
[global_abi
]);
5685 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5687 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5691 int ef_mips_32bitmode
;
5692 /* determine the ISA */
5693 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5711 /* determine the size of a pointer */
5712 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5713 fprintf_unfiltered (file
,
5714 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5716 fprintf_unfiltered (file
,
5717 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5719 fprintf_unfiltered (file
,
5720 "mips_dump_tdep: ef_mips_arch = %d\n",
5722 fprintf_unfiltered (file
,
5723 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5724 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5725 fprintf_unfiltered (file
,
5726 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5727 mips_mask_address_p (tdep
),
5728 tdep
->default_mask_address_p
);
5730 fprintf_unfiltered (file
,
5731 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5732 MIPS_DEFAULT_FPU_TYPE
,
5733 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5734 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5735 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5737 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5738 fprintf_unfiltered (file
,
5739 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5741 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5742 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5743 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5745 fprintf_unfiltered (file
,
5746 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5747 mips_stack_argsize (current_gdbarch
));
5748 fprintf_unfiltered (file
,
5749 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
5750 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
5751 fprintf_unfiltered (file
,
5752 "mips_dump_tdep: ATTACH_DETACH # %s\n",
5753 XSTRING (ATTACH_DETACH
));
5754 fprintf_unfiltered (file
,
5755 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
5756 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
5757 fprintf_unfiltered (file
,
5758 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
5759 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
5760 fprintf_unfiltered (file
,
5761 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
5762 FIRST_EMBED_REGNUM
);
5763 fprintf_unfiltered (file
,
5764 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
5765 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
5766 fprintf_unfiltered (file
,
5767 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
5768 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
5769 fprintf_unfiltered (file
,
5770 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
5772 #ifdef MACHINE_CPROC_FP_OFFSET
5773 fprintf_unfiltered (file
,
5774 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
5775 MACHINE_CPROC_FP_OFFSET
);
5777 #ifdef MACHINE_CPROC_PC_OFFSET
5778 fprintf_unfiltered (file
,
5779 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
5780 MACHINE_CPROC_PC_OFFSET
);
5782 #ifdef MACHINE_CPROC_SP_OFFSET
5783 fprintf_unfiltered (file
,
5784 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
5785 MACHINE_CPROC_SP_OFFSET
);
5787 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
5788 fprintf_unfiltered (file
,
5789 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
5790 fprintf_unfiltered (file
,
5791 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
5792 MIPS_LAST_ARG_REGNUM
,
5793 MIPS_LAST_ARG_REGNUM
- MIPS_A0_REGNUM
+ 1);
5794 fprintf_unfiltered (file
,
5795 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
5796 fprintf_unfiltered (file
,
5797 "mips_dump_tdep: mips_abi_regsize() = %d\n",
5798 mips_abi_regsize (current_gdbarch
));
5799 fprintf_unfiltered (file
,
5800 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
5801 fprintf_unfiltered (file
,
5802 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
5803 fprintf_unfiltered (file
,
5804 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
5805 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
5806 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
5807 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
5808 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
5809 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
5810 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
5811 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
5812 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
5813 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
5814 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
5816 fprintf_unfiltered (file
,
5817 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
5820 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
5823 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
5825 fprintf_unfiltered (file
,
5826 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
5827 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
5828 fprintf_unfiltered (file
,
5829 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
5830 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
5831 fprintf_unfiltered (file
,
5832 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
5833 SOFTWARE_SINGLE_STEP_P ());
5834 fprintf_unfiltered (file
,
5835 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
5836 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
5837 #ifdef STACK_END_ADDR
5838 fprintf_unfiltered (file
,
5839 "mips_dump_tdep: STACK_END_ADDR = %d\n",
5842 fprintf_unfiltered (file
,
5843 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
5844 XSTRING (STEP_SKIPS_DELAY (PC
)));
5845 fprintf_unfiltered (file
,
5846 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
5847 STEP_SKIPS_DELAY_P
);
5848 fprintf_unfiltered (file
,
5849 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
5850 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
5851 fprintf_unfiltered (file
,
5852 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
5853 fprintf_unfiltered (file
,
5854 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
5855 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
5856 (TYPE
, CNT
, OTHERTYPE
)));
5858 fprintf_unfiltered (file
,
5859 "mips_dump_tdep: TRACE_CLEAR # %s\n",
5860 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
5863 fprintf_unfiltered (file
,
5864 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
5866 #ifdef TRACE_FLAVOR_SIZE
5867 fprintf_unfiltered (file
,
5868 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
5872 fprintf_unfiltered (file
,
5873 "mips_dump_tdep: TRACE_SET # %s\n",
5874 XSTRING (TRACE_SET (X
, STATE
)));
5876 #ifdef UNUSED_REGNUM
5877 fprintf_unfiltered (file
,
5878 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
5880 fprintf_unfiltered (file
,
5881 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
5882 (long) VM_MIN_ADDRESS
);
5885 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5888 _initialize_mips_tdep (void)
5890 static struct cmd_list_element
*mipsfpulist
= NULL
;
5891 struct cmd_list_element
*c
;
5893 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5894 if (MIPS_ABI_LAST
+ 1
5895 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5896 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
5898 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5900 mips_pdr_data
= register_objfile_data ();
5902 /* Add root prefix command for all "set mips"/"show mips" commands */
5903 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5904 "Various MIPS specific commands.",
5905 &setmipscmdlist
, "set mips ", 0, &setlist
);
5907 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5908 "Various MIPS specific commands.",
5909 &showmipscmdlist
, "show mips ", 0, &showlist
);
5911 /* Allow the user to override the saved register size. */
5912 add_setshow_enum_cmd ("saved-gpreg-size", class_obscure
,
5913 size_enums
, &mips_abi_regsize_string
, "\
5914 Set size of general purpose registers saved on the stack.\n", "\
5915 Show size of general purpose registers saved on the stack.\n", "\
5916 This option can be set to one of:\n\
5917 32 - Force GDB to treat saved GP registers as 32-bit\n\
5918 64 - Force GDB to treat saved GP registers as 64-bit\n\
5919 auto - Allow GDB to use the target's default setting or autodetect the\n\
5920 saved GP register size from information contained in the executable.\n\
5921 (default: auto)", "\
5922 Size of general purpose registers saved on the stack is %s.\n",
5923 NULL
, NULL
, &setmipscmdlist
, &showmipscmdlist
);
5925 /* Allow the user to override the argument stack size. */
5926 add_setshow_enum_cmd ("stack-arg-size", class_obscure
,
5927 size_enums
, &mips_stack_argsize_string
, "\
5928 Set the amount of stack space reserved for each argument.\n", "\
5929 Show the amount of stack space reserved for each argument.\n", "\
5930 This option can be set to one of:\n\
5931 32 - Force GDB to allocate 32-bit chunks per argument\n\
5932 64 - Force GDB to allocate 64-bit chunks per argument\n\
5933 auto - Allow GDB to determine the correct setting from the current\n\
5934 target and executable (default)", "\
5935 The amount of stack space reserved for each argument is %s.\n",
5936 NULL
, NULL
, &setmipscmdlist
, &showmipscmdlist
);
5938 /* Allow the user to override the ABI. */
5939 c
= add_set_enum_cmd
5940 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
5941 "Set the ABI used by this program.\n"
5942 "This option can be set to one of:\n"
5943 " auto - the default ABI associated with the current binary\n"
5945 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
5946 set_cmd_sfunc (c
, mips_abi_update
);
5947 add_cmd ("abi", class_obscure
, show_mips_abi
,
5948 "Show ABI in use by MIPS target", &showmipscmdlist
);
5950 /* Let the user turn off floating point and set the fence post for
5951 heuristic_proc_start. */
5953 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5954 "Set use of MIPS floating-point coprocessor.",
5955 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5956 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5957 "Select single-precision MIPS floating-point coprocessor.",
5959 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5960 "Select double-precision MIPS floating-point coprocessor.",
5962 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5963 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5964 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5965 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5966 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
5967 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5968 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5969 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5970 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5971 "Select MIPS floating-point coprocessor automatically.",
5973 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5974 "Show current use of MIPS floating-point coprocessor target.",
5977 /* We really would like to have both "0" and "unlimited" work, but
5978 command.c doesn't deal with that. So make it a var_zinteger
5979 because the user can always use "999999" or some such for unlimited. */
5980 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5981 &heuristic_fence_post
, "\
5982 Set the distance searched for the start of a function.\n", "\
5983 Show the distance searched for the start of a function.\n", "\
5984 If you are debugging a stripped executable, GDB needs to search through the\n\
5985 program for the start of a function. This command sets the distance of the\n\
5986 search. The only need to set it is when debugging a stripped executable.", "\
5987 The distance searched for the start of a function is %s.\n",
5988 reinit_frame_cache_sfunc
, NULL
,
5989 &setlist
, &showlist
);
5991 /* Allow the user to control whether the upper bits of 64-bit
5992 addresses should be zeroed. */
5993 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
5994 Set zeroing of upper 32 bits of 64-bit addresses.", "\
5995 Show zeroing of upper 32 bits of 64-bit addresses.", "\
5996 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5997 allow GDB to determine the correct value.\n", "\
5998 Zerroing of upper 32 bits of 64-bit address is %s.",
5999 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6001 /* Allow the user to control the size of 32 bit registers within the
6002 raw remote packet. */
6003 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6004 &mips64_transfers_32bit_regs_p
, "\
6005 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6006 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6007 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6008 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6009 64 bits for others. Use \"off\" to disable compatibility mode", "\
6010 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6011 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6013 /* Debug this files internals. */
6014 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6016 Set mips debugging.\n", "\
6017 Show mips debugging.\n", "\
6018 When non-zero, mips specific debugging is enabled.\n", "\
6019 Mips debugging is currently %s.\n",
6021 &setdebuglist
, &showdebuglist
);