1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
41 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
42 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
44 /* FIXME: Put this declaration in frame.h. */
45 extern struct obstack frame_cache_obstack
;
48 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
51 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
53 static void mips_print_register
PARAMS ((int, int));
55 static mips_extra_func_info_t
56 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
58 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
60 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
62 static void mips_set_fpu_command
PARAMS ((char *, int,
63 struct cmd_list_element
*));
65 static void mips_show_fpu_command
PARAMS ((char *, int,
66 struct cmd_list_element
*));
68 void mips_set_processor_type_command
PARAMS ((char *, int));
70 int mips_set_processor_type
PARAMS ((char *));
72 static void mips_show_processor_type_command
PARAMS ((char *, int));
74 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
75 struct cmd_list_element
*));
77 static mips_extra_func_info_t
78 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
*next_frame
));
80 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
81 mips_extra_func_info_t proc_desc
));
83 /* This value is the model of MIPS in use. It is derived from the value
84 of the PrID register. */
86 char *mips_processor_type
;
88 char *tmp_mips_processor_type
;
90 /* Some MIPS boards don't support floating point, so we permit the
91 user to turn it off. */
93 enum mips_fpu_type mips_fpu
;
95 static char *mips_fpu_string
;
97 /* A set of original names, to be used when restoring back to generic
98 registers from a specific set. */
100 char *mips_generic_reg_names
[] = REGISTER_NAMES
;
102 /* Names of IDT R3041 registers. */
104 char *mips_r3041_reg_names
[] = {
105 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
106 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
107 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
108 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
109 "sr", "lo", "hi", "bad", "cause","pc",
110 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
111 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
112 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
113 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
114 "fsr", "fir", "fp", "",
115 "", "", "bus", "ccfg", "", "", "", "",
116 "", "", "port", "cmp", "", "", "epc", "prid",
119 /* Names of IDT R3051 registers. */
121 char *mips_r3051_reg_names
[] = {
122 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
123 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
124 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
125 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
126 "sr", "lo", "hi", "bad", "cause","pc",
127 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
128 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
129 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
130 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
131 "fsr", "fir", "fp", "",
132 "inx", "rand", "elo", "", "ctxt", "", "", "",
133 "", "", "ehi", "", "", "", "epc", "prid",
136 /* Names of IDT R3081 registers. */
138 char *mips_r3081_reg_names
[] = {
139 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
140 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
141 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
142 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
143 "sr", "lo", "hi", "bad", "cause","pc",
144 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
145 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
146 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
147 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
148 "fsr", "fir", "fp", "",
149 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
150 "", "", "ehi", "", "", "", "epc", "prid",
153 /* Names of LSI 33k registers. */
155 char *mips_lsi33k_reg_names
[] = {
156 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
157 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
158 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
159 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
160 "epc", "hi", "lo", "sr", "cause","badvaddr",
161 "dcic", "bpc", "bda", "", "", "", "", "",
162 "", "", "", "", "", "", "", "",
163 "", "", "", "", "", "", "", "",
164 "", "", "", "", "", "", "", "",
166 "", "", "", "", "", "", "", "",
167 "", "", "", "", "", "", "", "",
173 } mips_processor_type_table
[] = {
174 { "generic", mips_generic_reg_names
},
175 { "r3041", mips_r3041_reg_names
},
176 { "r3051", mips_r3051_reg_names
},
177 { "r3071", mips_r3081_reg_names
},
178 { "r3081", mips_r3081_reg_names
},
179 { "lsi33k", mips_lsi33k_reg_names
},
183 /* Table to translate MIPS16 register field to actual register number. */
184 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
186 /* Heuristic_proc_start may hunt through the text section for a long
187 time across a 2400 baud serial line. Allows the user to limit this
190 static unsigned int heuristic_fence_post
= 0;
192 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
193 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
194 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
195 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
196 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
197 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
198 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
199 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
200 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
201 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
202 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
203 #define _PROC_MAGIC_ 0x0F0F0F0F
204 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
205 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
207 struct linked_proc_info
209 struct mips_extra_func_info info
;
210 struct linked_proc_info
*next
;
211 } *linked_proc_desc_table
= NULL
;
214 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
217 pc_is_mips16 (bfd_vma memaddr
)
219 struct minimal_symbol
*sym
;
221 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
222 if (IS_MIPS16_ADDR (memaddr
))
225 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
226 the high bit of the info field. Use this to decide if the function is
227 MIPS16 or normal MIPS. */
228 sym
= lookup_minimal_symbol_by_pc (memaddr
);
230 return MSYMBOL_IS_SPECIAL (sym
);
236 /* This returns the PC of the first inst after the prologue. If we can't
237 find the prologue, then return 0. */
240 after_prologue (pc
, proc_desc
)
242 mips_extra_func_info_t proc_desc
;
244 struct symtab_and_line sal
;
245 CORE_ADDR func_addr
, func_end
;
248 proc_desc
= find_proc_desc (pc
, NULL
);
252 /* If function is frameless, then we need to do it the hard way. I
253 strongly suspect that frameless always means prologueless... */
254 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
255 && PROC_FRAME_OFFSET (proc_desc
) == 0)
259 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
260 return 0; /* Unknown */
262 sal
= find_pc_line (func_addr
, 0);
264 if (sal
.end
< func_end
)
267 /* The line after the prologue is after the end of the function. In this
268 case, tell the caller to find the prologue the hard way. */
273 /* Decode a MIPS32 instruction that saves a register in the stack, and
274 set the appropriate bit in the general register mask or float register mask
275 to indicate which register is saved. This is a helper function
276 for mips_find_saved_regs. */
279 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
281 unsigned long *gen_mask
;
282 unsigned long *float_mask
;
286 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
287 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
288 /* start-sanitize-r5900 */
289 || (inst
& 0xffe00000) == 0x7fa00000 /* sq reg,n($sp) */
290 /* end-sanitize-r5900 */
291 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
293 /* It might be possible to use the instruction to
294 find the offset, rather than the code below which
295 is based on things being in a certain order in the
296 frame, but figuring out what the instruction's offset
297 is relative to might be a little tricky. */
298 reg
= (inst
& 0x001f0000) >> 16;
299 *gen_mask
|= (1 << reg
);
301 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
302 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
303 || (inst
& 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */
306 reg
= ((inst
& 0x001f0000) >> 16);
307 *float_mask
|= (1 << reg
);
311 /* Decode a MIPS16 instruction that saves a register in the stack, and
312 set the appropriate bit in the general register or float register mask
313 to indicate which register is saved. This is a helper function
314 for mips_find_saved_regs. */
317 mips16_decode_reg_save (inst
, gen_mask
)
319 unsigned long *gen_mask
;
321 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
323 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
324 *gen_mask
|= (1 << reg
);
326 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
328 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
329 *gen_mask
|= (1 << reg
);
331 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
332 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
333 *gen_mask
|= (1 << RA_REGNUM
);
337 /* Fetch and return instruction from the specified location. If the PC
338 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
341 mips_fetch_instruction (addr
)
344 char buf
[MIPS_INSTLEN
];
348 if (pc_is_mips16 (addr
))
350 instlen
= MIPS16_INSTLEN
;
351 addr
= UNMAKE_MIPS16_ADDR (addr
);
354 instlen
= MIPS_INSTLEN
;
355 status
= read_memory_nobpt (addr
, buf
, instlen
);
357 memory_error (status
, addr
);
358 return extract_unsigned_integer (buf
, instlen
);
362 /* These the fields of 32 bit mips instructions */
363 #define mips32_op(x) (x >> 25)
364 #define itype_op(x) (x >> 25)
365 #define itype_rs(x) ((x >> 21)& 0x1f)
366 #define itype_rt(x) ((x >> 16) & 0x1f)
367 #define itype_immediate(x) ( x & 0xffff)
369 #define jtype_op(x) (x >> 25)
370 #define jtype_target(x) ( x & 0x03fffff)
372 #define rtype_op(x) (x >>25)
373 #define rtype_rs(x) ((x>>21) & 0x1f)
374 #define rtype_rt(x) ((x>>16) & 0x1f)
375 #define rtype_rd(x) ((x>>11) & 0x1f)
376 #define rtype_shamt(x) ((x>>6) & 0x1f)
377 #define rtype_funct(x) (x & 0x3f )
380 mips32_relative_offset(unsigned long inst
)
382 x
= itype_immediate(inst
) ;
383 if (x
& 0x8000) /* sign bit set */
385 x
|= 0xffff0000 ; /* sign extension */
391 /* Determine whate to set a single step breakpoint while considering
394 mips32_next_pc(CORE_ADDR pc
)
398 inst
= mips_fetch_instruction(pc
) ;
399 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
400 { if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
401 { op
= ((inst
>> 25) & 0x03) ;
404 case 0 : goto equal_branch
; /* BEQL */
405 case 1 : goto neq_branch
; /* BNEZ */
406 case 2 : goto less_branch
; /* BLEZ */
407 case 3 : goto greater_branch
; /* BGTZ */
411 else pc
+= 4 ; /* Not a branch, next instruction is easy */
414 { /* This gets way messy */
416 /* Further subdivide into SPECIAL, REGIMM and other */
417 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
419 case 0 : /* SPECIAL */
420 op
= rtype_funct(inst
) ;
425 pc
= read_register(rtype_rs(inst
)) ; /* Set PC to that address */
430 break ; /* end special */
431 case 1 : /* REGIMM */
433 op
= jtype_op(inst
) ; /* branch condition */
434 switch (jtype_op(inst
))
438 case 16 : /* BLTZALL */
439 case 18 : /* BLTZALL */
441 if (read_register(itype_rs(inst
)) < 0)
442 pc
+= mips32_relative_offset(inst
) + 4 ;
443 else pc
+= 8 ; /* after the delay slot */
447 case 17 : /* BGEZAL */
448 case 19 : /* BGEZALL */
449 greater_equal_branch
:
450 if (read_register(itype_rs(inst
)) >= 0)
451 pc
+= mips32_relative_offset(inst
) + 4 ;
452 else pc
+= 8 ; /* after the delay slot */
454 /* All of the other intructions in the REGIMM catagory */
458 break ; /* end REGIMM */
461 { unsigned long reg
;
462 reg
= jtype_target(inst
) << 2 ;
463 pc
= reg
+ ((pc
+4) & 0xf0000000) ;
464 /* Whats this mysterious 0xf000000 adjustment ??? */
467 /* FIXME case JALX :*/
468 { unsigned long reg
;
469 reg
= jtype_target(inst
) << 2 ;
470 pc
= reg
+ ((pc
+4) & 0xf0000000) + 1 ; /* yes, +1 */
471 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
473 break ; /* The new PC will be alternate mode */
474 case 4 : /* BEQ , BEQL */
476 if (read_register(itype_rs(inst
)) ==
477 read_register(itype_rt(inst
)))
478 pc
+= mips32_relative_offset(inst
) + 4 ;
481 case 5 : /* BNE , BNEL */
483 if (read_register(itype_rs(inst
)) !=
484 read_register(itype_rs(inst
)))
485 pc
+= mips32_relative_offset(inst
) + 4 ;
488 case 6 : /* BLEZ , BLEZL */
490 if (read_register(itype_rs(inst
) <= 0))
491 pc
+= mips32_relative_offset(inst
) + 4 ;
495 greater_branch
: /* BGTZ BGTZL */
496 if (read_register(itype_rs(inst
) > 0))
497 pc
+= mips32_relative_offset(inst
) + 4 ;
504 } /* mips32_next_pc */
506 /* Decoding the next place to set a breakpoint is irregular for the
507 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
508 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
509 We dont want to set a single step instruction on the extend instruction
513 /* Lots of mips16 instruction formats */
514 /* Predicting jumps requires itype,ritype,i8type
515 and their extensions extItype,extritype,extI8type
517 enum mips16_inst_fmts
519 itype
, /* 0 immediate 5,10 */
520 ritype
, /* 1 5,3,8 */
521 rrtype
, /* 2 5,3,3,5 */
522 rritype
, /* 3 5,3,3,5 */
523 rrrtype
, /* 4 5,3,3,3,2 */
524 rriatype
, /* 5 5,3,3,1,4 */
525 shifttype
, /* 6 5,3,3,3,2 */
526 i8type
, /* 7 5,3,8 */
527 i8movtype
, /* 8 5,3,3,5 */
528 i8mov32rtype
, /* 9 5,3,5,3 */
529 i64type
, /* 10 5,3,8 */
530 ri64type
, /* 11 5,3,3,5 */
531 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
532 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
533 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
534 extRRItype
, /* 15 5,5,5,5,3,3,5 */
535 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
536 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
537 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
538 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
539 extRi64type
, /* 20 5,6,5,5,3,3,5 */
540 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
542 /* I am heaping all the fields of the formats into one structure and then,
543 only the fields which are involved in instruction extension */
546 unsigned short inst
;
547 enum mips16_inst_fmts fmt
;
548 unsigned long offset
;
549 unsigned int regx
; /* Function in i8 type */
555 static void print_unpack(char * comment
,
556 struct upk_mips16
* u
)
558 printf("%s %04x ,f(%d) off(%08x) (x(%x) y(%x)\n",
559 comment
,u
->inst
,u
->fmt
,u
->offset
,u
->regx
,u
->regy
) ;
562 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
563 format for the bits which make up the immediatate extension.
566 extended_offset(unsigned long extension
)
568 unsigned long value
;
569 value
= (extension
>> 21) & 0x3f ; /* * extract 15:11 */
571 value
|= (extension
>> 16) & 0x1f ; /* extrace 10:5 */
573 value
|= extension
& 0x01f ; /* extract 4:0 */
577 /* Only call this function if you know that this is an extendable
578 instruction, It wont malfunction, but why make excess remote memory references?
579 If the immediate operands get sign extended or somthing, do it after
580 the extension is performed.
582 /* FIXME: Every one of these cases needs to worry about sign extension
583 when the offset is to be used in relative addressing */
586 static unsigned short fetch_mips_16(CORE_ADDR pc
)
589 pc
&= 0xfffffffe ; /* clear the low order bit */
590 target_read_memory(pc
,buf
,2) ;
591 return extract_unsigned_integer(buf
,2) ;
595 unpack_mips16(CORE_ADDR pc
,
596 struct upk_mips16
* upk
)
599 unsigned long extension
;
601 extpc
= (pc
- 4) & ~0x01 ; /* Extensions are 32 bit instructions */
602 /* Decrement to previous address and loose the 16bit mode flag */
603 /* return if the instruction was extendable, but not actually extended */
604 extended
= ((mips32_op(extension
) == 30) ? 1 : 0) ;
605 if (extended
) { extension
= mips_fetch_instruction(extpc
) ;}
610 unsigned long value
;
612 { value
= extended_offset(extension
) ;
613 value
= value
<< 11 ; /* rom for the original value */
614 value
|= upk
->inst
& 0x7ff ; /* eleven bits from instruction */
617 { value
= upk
->inst
& 0x7ff ;
618 /* FIXME : Consider sign extension */
620 upk
->offset
= value
;
625 { /* A register identifier and an offset */
626 /* Most of the fields are the same as I type but the
627 immediate value is of a different length */
628 unsigned long value
;
631 value
= extended_offset(extension
) ;
632 value
= value
<< 8 ; /* from the original instruction */
633 value
|= upk
->inst
& 0xff ; /* eleven bits from instruction */
634 upk
->regx
= (extension
>> 8) & 0x07 ; /* or i8 funct */
635 if (value
& 0x4000) /* test the sign bit , bit 26 */
636 { value
&= ~ 0x3fff ; /* remove the sign bit */
641 value
= upk
->inst
& 0xff ; /* 8 bits */
642 upk
->regx
= (upk
->inst
>> 8) & 0x07 ; /* or i8 funct */
643 /* FIXME: Do sign extension , this format needs it */
644 if (value
& 0x80) /* THIS CONFUSES ME */
645 { value
&= 0xef ; /* remove the sign bit */
650 upk
->offset
= value
;
655 unsigned long value
;
656 unsigned short nexthalf
;
657 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f) ;
658 value
= value
<< 16 ;
659 nexthalf
= mips_fetch_instruction(pc
+2) ; /* low bit still set */
661 upk
->offset
= value
;
665 printf_filtered("Decoding unimplemented instruction format type\n") ;
668 /* print_unpack("UPK",upk) ; */
672 #define mips16_op(x) (x >> 11)
674 /* This is a map of the opcodes which ae known to perform branches */
675 static unsigned char map16
[32] =
682 static CORE_ADDR
add_offset_16(CORE_ADDR pc
, int offset
)
684 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000))) ;
690 static struct upk_mips16 upk
;
692 CORE_ADDR
mips16_next_pc(CORE_ADDR pc
)
696 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
697 inst
= fetch_mips_16(pc
) ;
699 op
= mips16_op(upk
.inst
) ;
705 case 2 : /* Branch */
707 unpack_mips16(pc
,&upk
) ;
709 offset
= upk
.offset
;
714 pc
+= (offset
<< 1) + 2 ;
717 case 3 : /* JAL , JALX - Watch out, these are 32 bit instruction*/
719 unpack_mips16(pc
,&upk
) ;
720 pc
= add_offset_16(pc
,upk
.offset
) ;
721 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
722 pc
= pc
& ~ 0x01 ; /* Clear low bit, indicate 32 bit mode */
727 unpack_mips16(pc
,&upk
) ;
728 reg
= read_register(upk
.regx
) ;
730 pc
+= (upk
.offset
<< 1) + 2 ;
735 unpack_mips16(pc
,&upk
) ;
736 reg
= read_register(upk
.regx
) ;
738 pc
+= (upk
.offset
<< 1) + 2 ;
741 case 12 : /* I8 Formats btez btnez */
743 unpack_mips16(pc
,&upk
) ;
744 /* upk.regx contains the opcode */
745 reg
= read_register(24) ; /* Test register is 24 */
746 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
747 || ((upk
.regx
== 1 ) && (reg
!= 0))) /* BTNEZ */
748 /* pc = add_offset_16(pc,upk.offset) ; */
749 pc
+= (upk
.offset
<< 1) + 2 ;
752 case 29 : /* RR Formats JR, JALR, JALR-RA */
754 op
= upk
.inst
& 0x1f ;
757 upk
.regx
= (upk
.inst
>> 8) & 0x07 ;
758 upk
.regy
= (upk
.inst
>> 5) & 0x07 ;
761 case 0 : reg
= upk
.regx
; break ;
762 case 1 : reg
= 31 ; break ; /* Function return instruction*/
763 case 2 : reg
= upk
.regx
; break ;
764 default: reg
= 31 ; break ; /* BOGUS Guess */
766 pc
= read_register(reg
) ;
770 case 30 : /* This is an extend instruction */
771 pc
+= 4 ; /* Dont be setting breakpints on the second half */
774 printf("Filtered - next PC probably incorrrect due to jump inst\n");
779 else pc
+= 2 ; /* just a good old instruction */
780 /* See if we CAN actually break on the next instruction */
781 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
783 } /* mips16_next_pc */
785 /* The mips_next_pc function supports single_tep when the remote target monitor or
786 stub is not developed enough to so a single_step.
787 It works by decoding the current instruction and predicting where a branch
788 will go. This isnt hard because all the data is available.
789 The MIPS32 and MIPS16 variants are quite different
791 CORE_ADDR
mips_next_pc(CORE_ADDR pc
)
794 /* inst = mips_fetch_instruction(pc) ; */
795 /* if (pc_is_mips16) <----- This is failing */
797 return mips16_next_pc(pc
) ;
798 else return mips32_next_pc(pc
) ;
801 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
805 mips_find_saved_regs (fci
)
806 struct frame_info
*fci
;
809 CORE_ADDR reg_position
;
810 /* r0 bit means kernel trap */
812 /* What registers have been saved? Bitmasks. */
813 unsigned long gen_mask
, float_mask
;
814 mips_extra_func_info_t proc_desc
;
817 fci
->saved_regs
= (struct frame_saved_regs
*)
818 obstack_alloc (&frame_cache_obstack
, sizeof(struct frame_saved_regs
));
819 memset (fci
->saved_regs
, 0, sizeof (struct frame_saved_regs
));
821 /* If it is the frame for sigtramp, the saved registers are located
822 in a sigcontext structure somewhere on the stack.
823 If the stack layout for sigtramp changes we might have to change these
824 constants and the companion fixup_sigtramp in mdebugread.c */
825 #ifndef SIGFRAME_BASE
826 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
827 above the sigtramp frame. */
828 #define SIGFRAME_BASE MIPS_REGSIZE
829 /* FIXME! Are these correct?? */
830 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
831 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
832 #define SIGFRAME_FPREGSAVE_OFF \
833 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
835 #ifndef SIGFRAME_REG_SIZE
836 /* FIXME! Is this correct?? */
837 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
839 if (fci
->signal_handler_caller
)
841 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
843 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
844 + ireg
* SIGFRAME_REG_SIZE
;
845 fci
->saved_regs
->regs
[ireg
] = reg_position
;
847 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
849 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
850 + ireg
* SIGFRAME_REG_SIZE
;
851 fci
->saved_regs
->regs
[FP0_REGNUM
+ ireg
] = reg_position
;
853 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
857 proc_desc
= fci
->proc_desc
;
858 if (proc_desc
== NULL
)
859 /* I'm not sure how/whether this can happen. Normally when we can't
860 find a proc_desc, we "synthesize" one using heuristic_proc_desc
861 and set the saved_regs right away. */
864 kernel_trap
= PROC_REG_MASK(proc_desc
) & 1;
865 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK(proc_desc
);
866 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc
);
868 if (/* In any frame other than the innermost or a frame interrupted by
869 a signal, we assume that all registers have been saved.
870 This assumes that all register saves in a function happen before
871 the first function call. */
872 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
874 /* In a dummy frame we know exactly where things are saved. */
875 && !PROC_DESC_IS_DUMMY (proc_desc
)
877 /* Don't bother unless we are inside a function prologue. Outside the
878 prologue, we know where everything is. */
880 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
882 /* Not sure exactly what kernel_trap means, but if it means
883 the kernel saves the registers without a prologue doing it,
884 we better not examine the prologue to see whether registers
885 have been saved yet. */
888 /* We need to figure out whether the registers that the proc_desc
889 claims are saved have been saved yet. */
893 /* Bitmasks; set if we have found a save for the register. */
894 unsigned long gen_save_found
= 0;
895 unsigned long float_save_found
= 0;
898 /* If the address is odd, assume this is MIPS16 code. */
899 addr
= PROC_LOW_ADDR (proc_desc
);
900 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
902 /* Scan through this function's instructions preceding the current
903 PC, and look for those that save registers. */
904 while (addr
< fci
->pc
)
906 inst
= mips_fetch_instruction (addr
);
907 if (pc_is_mips16 (addr
))
908 mips16_decode_reg_save (inst
, &gen_save_found
);
910 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
913 gen_mask
= gen_save_found
;
914 float_mask
= float_save_found
;
917 /* Fill in the offsets for the registers which gen_mask says
919 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
920 for (ireg
= MIPS_NUMREGS
-1; gen_mask
; --ireg
, gen_mask
<<= 1)
921 if (gen_mask
& 0x80000000)
923 fci
->saved_regs
->regs
[ireg
] = reg_position
;
924 reg_position
-= MIPS_REGSIZE
;
925 /* start-sanitize-r5900 */
926 #ifdef R5900_128BIT_GPR_HACK
927 /* Gross. The r5900 has 128bit wide registers, but MIPS_REGSIZE is
928 still 64bits. See the comments in tm.h for a discussion of the
929 various problems this causes. */
930 if (ireg
<= RA_REGNUM
)
931 reg_position
-= MIPS_REGSIZE
;
933 /* end-sanitize-r5900 */
936 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
937 of that normally used by gcc. Therefore, we have to fetch the first
938 instruction of the function, and if it's an entry instruction that
939 saves $s0 or $s1, correct their saved addresses. */
940 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
942 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
943 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
946 int sreg_count
= (inst
>> 6) & 3;
948 /* Check if the ra register was pushed on the stack. */
949 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
951 reg_position
-= MIPS_REGSIZE
;
953 /* Check if the s0 and s1 registers were pushed on the stack. */
954 for (reg
= 16; reg
< sreg_count
+16; reg
++)
956 fci
->saved_regs
->regs
[reg
] = reg_position
;
957 reg_position
-= MIPS_REGSIZE
;
962 /* Fill in the offsets for the registers which float_mask says
964 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
966 /* The freg_offset points to where the first *double* register
967 is saved. So skip to the high-order word. */
968 if (! GDB_TARGET_IS_MIPS64
)
969 reg_position
+= MIPS_REGSIZE
;
971 /* Fill in the offsets for the float registers which float_mask says
973 for (ireg
= MIPS_NUMREGS
-1; float_mask
; --ireg
, float_mask
<<= 1)
974 if (float_mask
& 0x80000000)
976 fci
->saved_regs
->regs
[FP0_REGNUM
+ireg
] = reg_position
;
977 reg_position
-= MIPS_REGSIZE
;
980 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->saved_regs
->regs
[RA_REGNUM
];
984 read_next_frame_reg(fi
, regno
)
985 struct frame_info
*fi
;
988 for (; fi
; fi
= fi
->next
)
990 /* We have to get the saved sp from the sigcontext
991 if it is a signal handler frame. */
992 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
996 if (fi
->saved_regs
== NULL
)
997 mips_find_saved_regs (fi
);
998 if (fi
->saved_regs
->regs
[regno
])
999 return read_memory_integer(fi
->saved_regs
->regs
[regno
], MIPS_REGSIZE
);
1002 return read_register (regno
);
1005 /* mips_addr_bits_remove - remove useless address bits */
1008 mips_addr_bits_remove (addr
)
1011 #if GDB_TARGET_IS_MIPS64
1012 if ((addr
>> 32 == (CORE_ADDR
)0xffffffff)
1013 && (strcmp (target_shortname
,"pmon")==0
1014 || strcmp (target_shortname
,"ddb")==0
1015 || strcmp (target_shortname
,"sim")==0))
1017 /* This hack is a work-around for existing boards using PMON,
1018 the simulator, and any other 64-bit targets that doesn't have
1019 true 64-bit addressing. On these targets, the upper 32 bits
1020 of addresses are ignored by the hardware. Thus, the PC or SP
1021 are likely to have been sign extended to all 1s by instruction
1022 sequences that load 32-bit addresses. For example, a typical
1023 piece of code that loads an address is this:
1024 lui $r2, <upper 16 bits>
1025 ori $r2, <lower 16 bits>
1026 But the lui sign-extends the value such that the upper 32 bits
1027 may be all 1s. The workaround is simply to mask off these bits.
1028 In the future, gcc may be changed to support true 64-bit
1029 addressing, and this masking will have to be disabled. */
1030 addr
&= (CORE_ADDR
)0xffffffff;
1033 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1034 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1035 So we still have to mask off useless bits from addresses. */
1036 addr
&= (CORE_ADDR
)0xffffffff;
1043 mips_init_frame_pc_first (fromleaf
, prev
)
1045 struct frame_info
*prev
;
1049 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1050 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1051 tmp
= mips_skip_stub (pc
);
1052 prev
->pc
= tmp
? tmp
: pc
;
1057 mips_frame_saved_pc(frame
)
1058 struct frame_info
*frame
;
1061 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
1062 /* We have to get the saved pc from the sigcontext
1063 if it is a signal handler frame. */
1064 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1065 : (proc_desc
? PROC_PC_REG(proc_desc
) : RA_REGNUM
);
1067 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
1068 saved_pc
= read_memory_integer(frame
->frame
- MIPS_REGSIZE
, MIPS_REGSIZE
);
1070 saved_pc
= read_next_frame_reg(frame
, pcreg
);
1072 return ADDR_BITS_REMOVE (saved_pc
);
1075 static struct mips_extra_func_info temp_proc_desc
;
1076 static struct frame_saved_regs temp_saved_regs
;
1078 /* Set a register's saved stack address in temp_saved_regs. If an address
1079 has already been set for this register, do nothing; this way we will
1080 only recognize the first save of a given register in a function prologue.
1081 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1084 set_reg_offset (regno
, offset
)
1088 if (temp_saved_regs
.regs
[regno
] == 0)
1089 temp_saved_regs
.regs
[regno
] = offset
;
1093 /* This fencepost looks highly suspicious to me. Removing it also
1094 seems suspicious as it could affect remote debugging across serial
1098 heuristic_proc_start(pc
)
1106 pc
= ADDR_BITS_REMOVE (pc
);
1108 fence
= start_pc
- heuristic_fence_post
;
1109 if (start_pc
== 0) return 0;
1111 if (heuristic_fence_post
== UINT_MAX
1112 || fence
< VM_MIN_ADDRESS
)
1113 fence
= VM_MIN_ADDRESS
;
1115 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1117 /* search back for previous return */
1118 for (start_pc
-= instlen
; ; start_pc
-= instlen
)
1119 if (start_pc
< fence
)
1121 /* It's not clear to me why we reach this point when
1122 stop_soon_quietly, but with this test, at least we
1123 don't print out warnings for every child forked (eg, on
1124 decstation). 22apr93 rich@cygnus.com. */
1125 if (!stop_soon_quietly
)
1127 static int blurb_printed
= 0;
1129 if (fence
== VM_MIN_ADDRESS
)
1130 warning("Hit beginning of text section without finding");
1132 warning("Hit heuristic-fence-post without finding");
1134 warning("enclosing function for address 0x%s", paddr_nz (pc
));
1138 This warning occurs if you are debugging a function without any symbols\n\
1139 (for example, in a stripped executable). In that case, you may wish to\n\
1140 increase the size of the search with the `set heuristic-fence-post' command.\n\
1142 Otherwise, you told GDB there was a function where there isn't one, or\n\
1143 (more likely) you have encountered a bug in GDB.\n");
1150 else if (pc_is_mips16 (start_pc
))
1152 unsigned short inst
;
1154 /* On MIPS16, any one of the following is likely to be the
1155 start of a function:
1159 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1160 inst
= mips_fetch_instruction (start_pc
);
1161 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1162 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1163 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1164 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1166 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1167 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1172 else if (ABOUT_TO_RETURN(start_pc
))
1174 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1179 /* skip nops (usually 1) 0 - is this */
1180 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1181 start_pc
+= MIPS_INSTLEN
;
1186 /* Fetch the immediate value from a MIPS16 instruction.
1187 If the previous instruction was an EXTEND, use it to extend
1188 the upper bits of the immediate value. This is a helper function
1189 for mips16_heuristic_proc_desc. */
1192 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1193 unsigned short prev_inst
; /* previous instruction */
1194 unsigned short inst
; /* current instruction */
1195 int nbits
; /* number of bits in imm field */
1196 int scale
; /* scale factor to be applied to imm */
1197 int is_signed
; /* is the imm field signed? */
1201 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1203 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1204 if (offset
& 0x8000) /* check for negative extend */
1205 offset
= 0 - (0x10000 - (offset
& 0xffff));
1206 return offset
| (inst
& 0x1f);
1210 int max_imm
= 1 << nbits
;
1211 int mask
= max_imm
- 1;
1212 int sign_bit
= max_imm
>> 1;
1214 offset
= inst
& mask
;
1215 if (is_signed
&& (offset
& sign_bit
))
1216 offset
= 0 - (max_imm
- offset
);
1217 return offset
* scale
;
1222 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1223 stream from start_pc to limit_pc. */
1226 mips16_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1227 CORE_ADDR start_pc
, limit_pc
;
1228 struct frame_info
*next_frame
;
1232 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1233 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1234 unsigned inst
= 0; /* current instruction */
1235 unsigned entry_inst
= 0; /* the entry instruction */
1238 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0; /* size of stack frame */
1239 PROC_FRAME_ADJUST(&temp_proc_desc
) = 0; /* offset of FP from SP */
1241 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1243 /* Save the previous instruction. If it's an EXTEND, we'll extract
1244 the immediate offset extension from it in mips16_get_imm. */
1247 /* Fetch and decode the instruction. */
1248 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1249 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1250 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1252 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1253 if (offset
< 0) /* negative stack adjustment? */
1254 PROC_FRAME_OFFSET(&temp_proc_desc
) -= offset
;
1256 /* Exit loop if a positive stack adjustment is found, which
1257 usually means that the stack cleanup code in the function
1258 epilogue is reached. */
1261 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1263 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1264 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1265 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1266 set_reg_offset (reg
, sp
+ offset
);
1268 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1270 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1271 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1272 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1273 set_reg_offset (reg
, sp
+ offset
);
1275 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1277 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1278 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1279 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1281 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1283 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1284 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1285 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1287 else if (inst
== 0x673d) /* move $s1, $sp */
1290 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1292 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1294 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1295 frame_addr
= sp
+ offset
;
1296 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1297 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1299 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1301 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1302 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1303 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1304 set_reg_offset (reg
, frame_addr
+ offset
);
1306 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1308 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1309 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1310 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1311 set_reg_offset (reg
, frame_addr
+ offset
);
1313 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1314 entry_inst
= inst
; /* save for later processing */
1315 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1316 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1319 /* The entry instruction is typically the first instruction in a function,
1320 and it stores registers at offsets relative to the value of the old SP
1321 (before the prologue). But the value of the sp parameter to this
1322 function is the new SP (after the prologue has been executed). So we
1323 can't calculate those offsets until we've seen the entire prologue,
1324 and can calculate what the old SP must have been. */
1325 if (entry_inst
!= 0)
1327 int areg_count
= (entry_inst
>> 8) & 7;
1328 int sreg_count
= (entry_inst
>> 6) & 3;
1330 /* The entry instruction always subtracts 32 from the SP. */
1331 PROC_FRAME_OFFSET(&temp_proc_desc
) += 32;
1333 /* Now we can calculate what the SP must have been at the
1334 start of the function prologue. */
1335 sp
+= PROC_FRAME_OFFSET(&temp_proc_desc
);
1337 /* Check if a0-a3 were saved in the caller's argument save area. */
1338 for (reg
= 4, offset
= 0; reg
< areg_count
+4; reg
++)
1340 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1341 set_reg_offset (reg
, sp
+ offset
);
1342 offset
+= MIPS_REGSIZE
;
1345 /* Check if the ra register was pushed on the stack. */
1347 if (entry_inst
& 0x20)
1349 PROC_REG_MASK(&temp_proc_desc
) |= 1 << RA_REGNUM
;
1350 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1351 offset
-= MIPS_REGSIZE
;
1354 /* Check if the s0 and s1 registers were pushed on the stack. */
1355 for (reg
= 16; reg
< sreg_count
+16; reg
++)
1357 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1358 set_reg_offset (reg
, sp
+ offset
);
1359 offset
-= MIPS_REGSIZE
;
1365 mips32_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1366 CORE_ADDR start_pc
, limit_pc
;
1367 struct frame_info
*next_frame
;
1371 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1373 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
1374 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1375 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1377 unsigned long inst
, high_word
, low_word
;
1380 /* Fetch the instruction. */
1381 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1383 /* Save some code by pre-extracting some useful fields. */
1384 high_word
= (inst
>> 16) & 0xffff;
1385 low_word
= inst
& 0xffff;
1386 reg
= high_word
& 0x1f;
1388 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1389 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1390 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1392 if (low_word
& 0x8000) /* negative stack adjustment? */
1393 PROC_FRAME_OFFSET(&temp_proc_desc
) += 0x10000 - low_word
;
1395 /* Exit loop if a positive stack adjustment is found, which
1396 usually means that the stack cleanup code in the function
1397 epilogue is reached. */
1400 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1402 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1403 set_reg_offset (reg
, sp
+ low_word
);
1405 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1407 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1408 but the register size used is only 32 bits. Make the address
1409 for the saved register point to the lower 32 bits. */
1410 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1411 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1413 /* start-sanitize-r5900 */
1414 else if ((high_word
& 0xFFE0) == 0x7fa0) /* sq reg,offset($sp) */
1416 /* I don't think we have to worry about the Irix 6.2 N32 ABI
1417 issue noted int he sd reg, offset($sp) case above. */
1418 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1419 set_reg_offset (reg
, sp
+ low_word
);
1421 /* end-sanitize-r5900 */
1422 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1424 /* Old gcc frame, r30 is virtual frame pointer. */
1425 if ((long)low_word
!= PROC_FRAME_OFFSET(&temp_proc_desc
))
1426 frame_addr
= sp
+ low_word
;
1427 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1429 unsigned alloca_adjust
;
1430 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1431 frame_addr
= read_next_frame_reg(next_frame
, 30);
1432 alloca_adjust
= (unsigned)(frame_addr
- (sp
+ low_word
));
1433 if (alloca_adjust
> 0)
1435 /* FP > SP + frame_size. This may be because
1436 * of an alloca or somethings similar.
1437 * Fix sp to "pre-alloca" value, and try again.
1439 sp
+= alloca_adjust
;
1444 /* move $30,$sp. With different versions of gas this will be either
1445 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1446 Accept any one of these. */
1447 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1449 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1450 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1452 unsigned alloca_adjust
;
1453 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1454 frame_addr
= read_next_frame_reg(next_frame
, 30);
1455 alloca_adjust
= (unsigned)(frame_addr
- sp
);
1456 if (alloca_adjust
> 0)
1458 /* FP > SP + frame_size. This may be because
1459 * of an alloca or somethings similar.
1460 * Fix sp to "pre-alloca" value, and try again.
1462 sp
+= alloca_adjust
;
1467 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1469 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1470 set_reg_offset (reg
, frame_addr
+ low_word
);
1475 static mips_extra_func_info_t
1476 heuristic_proc_desc(start_pc
, limit_pc
, next_frame
)
1477 CORE_ADDR start_pc
, limit_pc
;
1478 struct frame_info
*next_frame
;
1480 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1482 if (start_pc
== 0) return NULL
;
1483 memset (&temp_proc_desc
, '\0', sizeof(temp_proc_desc
));
1484 memset (&temp_saved_regs
, '\0', sizeof(struct frame_saved_regs
));
1485 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1486 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1487 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1489 if (start_pc
+ 200 < limit_pc
)
1490 limit_pc
= start_pc
+ 200;
1491 if (pc_is_mips16 (start_pc
))
1492 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1494 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1495 return &temp_proc_desc
;
1498 static mips_extra_func_info_t
1499 non_heuristic_proc_desc (pc
, addrptr
)
1503 CORE_ADDR startaddr
;
1504 mips_extra_func_info_t proc_desc
;
1505 struct block
*b
= block_for_pc(pc
);
1508 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1510 *addrptr
= startaddr
;
1511 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1515 if (startaddr
> BLOCK_START (b
))
1516 /* This is the "pathological" case referred to in a comment in
1517 print_frame_info. It might be better to move this check into
1521 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1524 /* If we never found a PDR for this function in symbol reading, then
1525 examine prologues to find the information. */
1528 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1529 if (PROC_FRAME_REG (proc_desc
) == -1)
1539 static mips_extra_func_info_t
1540 find_proc_desc (pc
, next_frame
)
1542 struct frame_info
*next_frame
;
1544 mips_extra_func_info_t proc_desc
;
1545 CORE_ADDR startaddr
;
1547 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1551 /* IF this is the topmost frame AND
1552 * (this proc does not have debugging information OR
1553 * the PC is in the procedure prologue)
1554 * THEN create a "heuristic" proc_desc (by analyzing
1555 * the actual code) to replace the "official" proc_desc.
1557 if (next_frame
== NULL
)
1559 struct symtab_and_line val
;
1560 struct symbol
*proc_symbol
=
1561 PROC_DESC_IS_DUMMY(proc_desc
) ? 0 : PROC_SYMBOL(proc_desc
);
1565 val
= find_pc_line (BLOCK_START
1566 (SYMBOL_BLOCK_VALUE(proc_symbol
)),
1568 val
.pc
= val
.end
? val
.end
: pc
;
1570 if (!proc_symbol
|| pc
< val
.pc
)
1572 mips_extra_func_info_t found_heuristic
=
1573 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1575 if (found_heuristic
)
1576 proc_desc
= found_heuristic
;
1582 /* Is linked_proc_desc_table really necessary? It only seems to be used
1583 by procedure call dummys. However, the procedures being called ought
1584 to have their own proc_descs, and even if they don't,
1585 heuristic_proc_desc knows how to create them! */
1587 register struct linked_proc_info
*link
;
1589 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1590 if (PROC_LOW_ADDR(&link
->info
) <= pc
1591 && PROC_HIGH_ADDR(&link
->info
) > pc
)
1595 startaddr
= heuristic_proc_start (pc
);
1598 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1604 get_frame_pointer(frame
, proc_desc
)
1605 struct frame_info
*frame
;
1606 mips_extra_func_info_t proc_desc
;
1608 return ADDR_BITS_REMOVE (
1609 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1610 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1613 mips_extra_func_info_t cached_proc_desc
;
1616 mips_frame_chain(frame
)
1617 struct frame_info
*frame
;
1619 mips_extra_func_info_t proc_desc
;
1621 CORE_ADDR saved_pc
= FRAME_SAVED_PC(frame
);
1623 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1626 /* Check if the PC is inside a call stub. If it is, fetch the
1627 PC of the caller of that stub. */
1628 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1631 /* Look up the procedure descriptor for this PC. */
1632 proc_desc
= find_proc_desc(saved_pc
, frame
);
1636 cached_proc_desc
= proc_desc
;
1638 /* If no frame pointer and frame size is zero, we must be at end
1639 of stack (or otherwise hosed). If we don't check frame size,
1640 we loop forever if we see a zero size frame. */
1641 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1642 && PROC_FRAME_OFFSET (proc_desc
) == 0
1643 /* The previous frame from a sigtramp frame might be frameless
1644 and have frame size zero. */
1645 && !frame
->signal_handler_caller
)
1648 return get_frame_pointer (frame
, proc_desc
);
1652 init_extra_frame_info(fci
)
1653 struct frame_info
*fci
;
1657 /* Use proc_desc calculated in frame_chain */
1658 mips_extra_func_info_t proc_desc
=
1659 fci
->next
? cached_proc_desc
: find_proc_desc(fci
->pc
, fci
->next
);
1661 fci
->saved_regs
= NULL
;
1663 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1666 /* Fixup frame-pointer - only needed for top frame */
1667 /* This may not be quite right, if proc has a real frame register.
1668 Get the value of the frame relative sp, procedure might have been
1669 interrupted by a signal at it's very start. */
1670 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1671 && !PROC_DESC_IS_DUMMY (proc_desc
))
1672 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1674 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1676 if (proc_desc
== &temp_proc_desc
)
1680 /* Do not set the saved registers for a sigtramp frame,
1681 mips_find_saved_registers will do that for us.
1682 We can't use fci->signal_handler_caller, it is not yet set. */
1683 find_pc_partial_function (fci
->pc
, &name
,
1684 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
1685 if (!IN_SIGTRAMP (fci
->pc
, name
))
1687 fci
->saved_regs
= (struct frame_saved_regs
*)
1688 obstack_alloc (&frame_cache_obstack
,
1689 sizeof (struct frame_saved_regs
));
1690 *fci
->saved_regs
= temp_saved_regs
;
1691 fci
->saved_regs
->regs
[PC_REGNUM
]
1692 = fci
->saved_regs
->regs
[RA_REGNUM
];
1696 /* hack: if argument regs are saved, guess these contain args */
1697 fci
->num_args
= -1; /* assume we can't tell how many args for now */
1698 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1700 if (PROC_REG_MASK(proc_desc
) & (1 << regnum
))
1702 fci
->num_args
= regnum
- A0_REGNUM
+ 1;
1709 /* MIPS stack frames are almost impenetrable. When execution stops,
1710 we basically have to look at symbol information for the function
1711 that we stopped in, which tells us *which* register (if any) is
1712 the base of the frame pointer, and what offset from that register
1713 the frame itself is at.
1715 This presents a problem when trying to examine a stack in memory
1716 (that isn't executing at the moment), using the "frame" command. We
1717 don't have a PC, nor do we have any registers except SP.
1719 This routine takes two arguments, SP and PC, and tries to make the
1720 cached frames look as if these two arguments defined a frame on the
1721 cache. This allows the rest of info frame to extract the important
1722 arguments without difficulty. */
1725 setup_arbitrary_frame (argc
, argv
)
1730 error ("MIPS frame specifications require two arguments: sp and pc");
1732 return create_new_frame (argv
[0], argv
[1]);
1736 * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack?
1738 * For n32 ABI, eight.
1739 * For all others, he same as the size of a general register.
1741 #if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
1742 #define MIPS_NABI32 1
1743 #define STACK_ARGSIZE 8
1745 #define MIPS_NABI32 0
1746 #define STACK_ARGSIZE MIPS_REGSIZE
1750 mips_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
1755 CORE_ADDR struct_addr
;
1761 int stack_offset
= 0;
1763 /* Macros to round N up or down to the next A boundary; A must be
1765 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1766 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1768 /* First ensure that the stack and structure return address (if any)
1769 are properly aligned. The stack has to be 64-bit aligned even
1770 on 32-bit machines, because doubles must be 64-bit aligned. */
1771 sp
= ROUND_DOWN (sp
, 8);
1772 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_REGSIZE
);
1774 /* Now make space on the stack for the args. We allocate more
1775 than necessary for EABI, because the first few arguments are
1776 passed in registers, but that's OK. */
1777 for (argnum
= 0; argnum
< nargs
; argnum
++)
1778 len
+= ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args
[argnum
])), MIPS_REGSIZE
);
1779 sp
-= ROUND_UP (len
, 8);
1781 /* Initialize the integer and float register pointers. */
1783 float_argreg
= FPA0_REGNUM
;
1785 /* the struct_return pointer occupies the first parameter-passing reg */
1787 write_register (argreg
++, struct_addr
);
1789 /* Now load as many as possible of the first arguments into
1790 registers, and push the rest onto the stack. Loop thru args
1791 from first to last. */
1792 for (argnum
= 0; argnum
< nargs
; argnum
++)
1795 char valbuf
[MAX_REGISTER_RAW_SIZE
];
1796 value_ptr arg
= args
[argnum
];
1797 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1798 int len
= TYPE_LENGTH (arg_type
);
1799 enum type_code typecode
= TYPE_CODE (arg_type
);
1801 /* The EABI passes structures that do not fit in a register by
1802 reference. In all other cases, pass the structure by value. */
1803 if (MIPS_EABI
&& len
> MIPS_REGSIZE
&&
1804 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1806 store_address (valbuf
, MIPS_REGSIZE
, VALUE_ADDRESS (arg
));
1807 typecode
= TYPE_CODE_PTR
;
1812 val
= (char *)VALUE_CONTENTS (arg
);
1814 /* 32-bit ABIs always start floating point arguments in an
1815 even-numbered floating point register. */
1816 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
1817 && (float_argreg
& 1))
1820 /* Floating point arguments passed in registers have to be
1821 treated specially. On 32-bit architectures, doubles
1822 are passed in register pairs; the even register gets
1823 the low word, and the odd register gets the high word.
1824 On non-EABI processors, the first two floating point arguments are
1825 also copied to general registers, because MIPS16 functions
1826 don't use float registers for arguments. This duplication of
1827 arguments in general registers can't hurt non-MIPS16 functions
1828 because those registers are normally skipped. */
1829 if (typecode
== TYPE_CODE_FLT
1830 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
1831 && mips_fpu
!= MIPS_FPU_NONE
)
1833 if (!FP_REGISTER_DOUBLE
&& len
== 8)
1835 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
1836 unsigned long regval
;
1838 /* Write the low word of the double to the even register(s). */
1839 regval
= extract_unsigned_integer (val
+low_offset
, 4);
1840 write_register (float_argreg
++, regval
);
1842 write_register (argreg
+1, regval
);
1844 /* Write the high word of the double to the odd register(s). */
1845 regval
= extract_unsigned_integer (val
+4-low_offset
, 4);
1846 write_register (float_argreg
++, regval
);
1849 write_register (argreg
, regval
);
1856 /* This is a floating point value that fits entirely
1857 in a single register. */
1858 CORE_ADDR regval
= extract_address (val
, len
);
1859 write_register (float_argreg
++, regval
);
1862 write_register (argreg
, regval
);
1863 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
1869 /* Copy the argument to general registers or the stack in
1870 register-sized pieces. Large arguments are split between
1871 registers and stack. */
1872 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
1873 are treated specially: Irix cc passes them in registers
1874 where gcc sometimes puts them on the stack. For maximum
1875 compatibility, we will put them in both places. */
1877 int odd_sized_struct
= ((len
> MIPS_REGSIZE
) &&
1878 (len
% MIPS_REGSIZE
!= 0));
1881 int partial_len
= len
< MIPS_REGSIZE
? len
: MIPS_REGSIZE
;
1883 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
1885 /* Write this portion of the argument to the stack. */
1886 /* Should shorter than int integer values be
1887 promoted to int before being stored? */
1889 int longword_offset
= 0;
1890 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1891 if (STACK_ARGSIZE
== 8 &&
1892 (typecode
== TYPE_CODE_INT
||
1893 typecode
== TYPE_CODE_PTR
||
1894 typecode
== TYPE_CODE_FLT
) && len
<= 4)
1895 longword_offset
= STACK_ARGSIZE
- len
;
1896 else if ((typecode
== TYPE_CODE_STRUCT
||
1897 typecode
== TYPE_CODE_UNION
) &&
1898 TYPE_LENGTH (arg_type
) < STACK_ARGSIZE
)
1899 longword_offset
= STACK_ARGSIZE
- len
;
1901 write_memory (sp
+ stack_offset
+ longword_offset
,
1905 /* Note!!! This is NOT an else clause.
1906 Odd sized structs may go thru BOTH paths. */
1907 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
1909 CORE_ADDR regval
= extract_address (val
, partial_len
);
1911 /* A non-floating-point argument being passed in a
1912 general register. If a struct or union, and if
1913 the remaining length is smaller than the register
1914 size, we have to adjust the register value on
1917 It does not seem to be necessary to do the
1918 same for integral types.
1920 Also don't do this adjustment on EABI targets. */
1923 TARGET_BYTE_ORDER
== BIG_ENDIAN
&&
1924 partial_len
< MIPS_REGSIZE
&&
1925 (typecode
== TYPE_CODE_STRUCT
||
1926 typecode
== TYPE_CODE_UNION
))
1927 regval
<<= ((MIPS_REGSIZE
- partial_len
) *
1930 write_register (argreg
, regval
);
1933 /* If this is the old ABI, prevent subsequent floating
1934 point arguments from being passed in floating point
1937 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
1943 /* The offset onto the stack at which we will start
1944 copying parameters (after the registers are used up)
1945 begins at (4 * MIPS_REGSIZE) in the old ABI. This
1946 leaves room for the "home" area for register parameters.
1948 In the new EABI (and the NABI32), the 8 register parameters
1949 do not have "home" stack space reserved for them, so the
1950 stack offset does not get incremented until after
1951 we have used up the 8 parameter registers. */
1953 if (!(MIPS_EABI
|| MIPS_NABI32
) ||
1955 stack_offset
+= ROUND_UP (partial_len
, STACK_ARGSIZE
);
1960 /* Set the return address register to point to the entry
1961 point of the program, where a breakpoint lies in wait. */
1962 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS());
1964 /* Return adjusted stack pointer. */
1969 mips_push_register(CORE_ADDR
*sp
, int regno
)
1971 char buffer
[MAX_REGISTER_RAW_SIZE
];
1972 int regsize
= REGISTER_RAW_SIZE (regno
);
1975 read_register_gen (regno
, buffer
);
1976 write_memory (*sp
, buffer
, regsize
);
1979 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
1980 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
1983 mips_push_dummy_frame()
1986 struct linked_proc_info
*link
= (struct linked_proc_info
*)
1987 xmalloc(sizeof(struct linked_proc_info
));
1988 mips_extra_func_info_t proc_desc
= &link
->info
;
1989 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
1990 CORE_ADDR old_sp
= sp
;
1991 link
->next
= linked_proc_desc_table
;
1992 linked_proc_desc_table
= link
;
1994 /* FIXME! are these correct ? */
1995 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
1996 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
1997 #define FLOAT_REG_SAVE_MASK MASK(0,19)
1998 #define FLOAT_SINGLE_REG_SAVE_MASK \
1999 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2001 * The registers we must save are all those not preserved across
2002 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2003 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2004 * and FP Control/Status registers.
2007 * Dummy frame layout:
2010 * Saved MMHI, MMLO, FPC_CSR
2015 * Saved D18 (i.e. F19, F18)
2017 * Saved D0 (i.e. F1, F0)
2018 * Argument build area and stack arguments written via mips_push_arguments
2022 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2023 PROC_FRAME_REG(proc_desc
) = PUSH_FP_REGNUM
;
2024 PROC_FRAME_OFFSET(proc_desc
) = 0;
2025 PROC_FRAME_ADJUST(proc_desc
) = 0;
2026 mips_push_register (&sp
, PC_REGNUM
);
2027 mips_push_register (&sp
, HI_REGNUM
);
2028 mips_push_register (&sp
, LO_REGNUM
);
2029 mips_push_register (&sp
, mips_fpu
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2031 /* Save general CPU registers */
2032 PROC_REG_MASK(proc_desc
) = GEN_REG_SAVE_MASK
;
2033 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2034 PROC_REG_OFFSET(proc_desc
) = sp
- old_sp
- MIPS_REGSIZE
;
2035 for (ireg
= 32; --ireg
>= 0; )
2036 if (PROC_REG_MASK(proc_desc
) & (1 << ireg
))
2037 mips_push_register (&sp
, ireg
);
2039 /* Save floating point registers starting with high order word */
2040 PROC_FREG_MASK(proc_desc
) =
2041 mips_fpu
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2042 : mips_fpu
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2043 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2045 PROC_FREG_OFFSET(proc_desc
) = sp
- old_sp
- 8;
2046 for (ireg
= 32; --ireg
>= 0; )
2047 if (PROC_FREG_MASK(proc_desc
) & (1 << ireg
))
2048 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2050 /* Update the frame pointer for the call dummy and the stack pointer.
2051 Set the procedure's starting and ending addresses to point to the
2052 call dummy address at the entry point. */
2053 write_register (PUSH_FP_REGNUM
, old_sp
);
2054 write_register (SP_REGNUM
, sp
);
2055 PROC_LOW_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS();
2056 PROC_HIGH_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS() + 4;
2057 SET_PROC_DESC_IS_DUMMY(proc_desc
);
2058 PROC_PC_REG(proc_desc
) = RA_REGNUM
;
2064 register int regnum
;
2065 struct frame_info
*frame
= get_current_frame ();
2066 CORE_ADDR new_sp
= FRAME_FP (frame
);
2068 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
2070 write_register (PC_REGNUM
, FRAME_SAVED_PC(frame
));
2071 if (frame
->saved_regs
== NULL
)
2072 mips_find_saved_regs (frame
);
2073 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2075 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2076 && frame
->saved_regs
->regs
[regnum
])
2077 write_register (regnum
,
2078 read_memory_integer (frame
->saved_regs
->regs
[regnum
],
2081 write_register (SP_REGNUM
, new_sp
);
2082 flush_cached_frames ();
2084 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
2086 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2088 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2090 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2092 if (&pi_ptr
->info
== proc_desc
)
2097 error ("Can't locate dummy extra frame info\n");
2099 if (prev_ptr
!= NULL
)
2100 prev_ptr
->next
= pi_ptr
->next
;
2102 linked_proc_desc_table
= pi_ptr
->next
;
2106 write_register (HI_REGNUM
,
2107 read_memory_integer (new_sp
- 2*MIPS_REGSIZE
, MIPS_REGSIZE
));
2108 write_register (LO_REGNUM
,
2109 read_memory_integer (new_sp
- 3*MIPS_REGSIZE
, MIPS_REGSIZE
));
2110 if (mips_fpu
!= MIPS_FPU_NONE
)
2111 write_register (FCRCS_REGNUM
,
2112 read_memory_integer (new_sp
- 4*MIPS_REGSIZE
, MIPS_REGSIZE
));
2117 mips_print_register (regnum
, all
)
2120 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2122 /* Get the data in raw format. */
2123 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2125 printf_filtered ("%s: [Invalid]", reg_names
[regnum
]);
2129 /* If an even floating point register, also print as double. */
2130 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2131 && !((regnum
-FP0_REGNUM
) & 1))
2132 if (REGISTER_RAW_SIZE(regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2134 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2136 read_relative_register_raw_bytes (regnum
, dbuffer
);
2137 read_relative_register_raw_bytes (regnum
+1, dbuffer
+MIPS_REGSIZE
);
2138 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2140 printf_filtered ("(d%d: ", regnum
-FP0_REGNUM
);
2141 val_print (builtin_type_double
, dbuffer
, 0,
2142 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2143 printf_filtered ("); ");
2145 fputs_filtered (reg_names
[regnum
], gdb_stdout
);
2147 /* The problem with printing numeric register names (r26, etc.) is that
2148 the user can't use them on input. Probably the best solution is to
2149 fix it so that either the numeric or the funky (a2, etc.) names
2150 are accepted on input. */
2151 if (regnum
< MIPS_NUMREGS
)
2152 printf_filtered ("(r%d): ", regnum
);
2154 printf_filtered (": ");
2156 /* If virtual format is floating, print it that way. */
2157 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2158 if (FP_REGISTER_DOUBLE
)
2159 { /* show 8-byte floats as float AND double: */
2160 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2162 printf_filtered (" (float) ");
2163 val_print (builtin_type_float
, raw_buffer
+ offset
, 0,
2164 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2165 printf_filtered (", (double) ");
2166 val_print (builtin_type_double
, raw_buffer
, 0,
2167 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2170 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0,
2171 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2172 /* Else print as integer in hex. */
2174 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
2175 'x', 0, gdb_stdout
);
2178 /* Replacement for generic do_registers_info.
2179 Print regs in pretty columns. */
2182 do_fp_register_row (regnum
)
2184 { /* do values for FP (float) regs */
2185 char *raw_buffer
[2];
2187 /* use HI and LO to control the order of combining two flt regs */
2188 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2189 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2190 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2191 int inv1
, inv2
, inv3
;
2193 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2194 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2195 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2197 /* Get the data in raw format. */
2198 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2199 error ("can't read register %d (%s)", regnum
, reg_names
[regnum
]);
2200 if (REGISTER_RAW_SIZE(regnum
) == 4)
2202 /* 4-byte registers: we can fit two registers per row. */
2203 /* Also print every pair of 4-byte regs as an 8-byte double. */
2204 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2205 error ("can't read register %d (%s)",
2206 regnum
+ 1, reg_names
[regnum
+ 1]);
2208 /* copy the two floats into one double, and unpack both */
2209 memcpy (dbl_buffer
, raw_buffer
, sizeof(dbl_buffer
));
2210 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2211 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2212 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2214 printf_filtered (inv1
? " %-5s: <invalid float>" :
2215 " %-5s%-17.9g", reg_names
[regnum
], flt1
);
2216 printf_filtered (inv2
? " %-5s: <invalid float>" :
2217 " %-5s%-17.9g", reg_names
[regnum
+ 1], flt2
);
2218 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2219 " dbl: %-24.17g\n", doub
);
2220 /* may want to do hex display here (future enhancement) */
2224 { /* eight byte registers: print each one as float AND as double. */
2225 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2227 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof(dbl_buffer
));
2228 flt1
= unpack_double (builtin_type_float
,
2229 &raw_buffer
[HI
][offset
], &inv1
);
2230 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2232 printf_filtered (inv1
? " %-5s: <invalid float>" :
2233 " %-5s flt: %-17.9g", reg_names
[regnum
], flt1
);
2234 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2235 " dbl: %-24.17g\n", doub
);
2236 /* may want to do hex display here (future enhancement) */
2242 /* Print a row's worth of GP (int) registers, with name labels above */
2245 do_gp_register_row (regnum
)
2248 /* do values for GP (int) regs */
2249 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2250 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2252 int start_regnum
= regnum
;
2253 int numregs
= NUM_REGS
;
2255 /* start-sanitize-sky */
2256 #ifdef NUM_R5900_REGS
2257 numregs
= NUM_R5900_REGS
;
2259 /* end-sanitize-sky */
2261 /* For GP registers, we print a separate row of names above the vals */
2262 printf_filtered (" ");
2263 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2265 if (*reg_names
[regnum
] == '\0')
2266 continue; /* unused register */
2267 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2268 break; /* end the row: reached FP register */
2269 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2273 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2274 start_regnum
); /* print the R0 to R31 names */
2276 regnum
= start_regnum
; /* go back to start of row */
2277 /* now print the values in hex, 4 or 8 to the row */
2278 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2280 if (*reg_names
[regnum
] == '\0')
2281 continue; /* unused register */
2282 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2283 break; /* end row: reached FP register */
2284 /* OK: get the data in raw format. */
2285 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2286 error ("can't read register %d (%s)", regnum
, reg_names
[regnum
]);
2287 /* pad small registers */
2288 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_RAW_SIZE (regnum
)); byte
++)
2289 printf_filtered (" ");
2290 /* Now print the register value in hex, endian order. */
2291 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2292 for (byte
= 0; byte
< REGISTER_RAW_SIZE (regnum
); byte
++)
2293 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2295 for (byte
= REGISTER_RAW_SIZE (regnum
) - 1; byte
>= 0; byte
--)
2296 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2297 printf_filtered (" ");
2300 if (col
> 0) /* ie. if we actually printed anything... */
2301 printf_filtered ("\n");
2306 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2309 mips_do_registers_info (regnum
, fpregs
)
2313 if (regnum
!= -1) /* do one specified register */
2315 if (*(reg_names
[regnum
]) == '\0')
2316 error ("Not a valid register for the current processor type");
2318 mips_print_register (regnum
, 0);
2319 printf_filtered ("\n");
2321 else /* do all (or most) registers */
2324 while (regnum
< NUM_REGS
)
2326 if (TYPE_CODE(REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2327 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2328 regnum
= do_fp_register_row (regnum
); /* FP regs */
2330 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2332 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2333 /* start-sanitize-sky */
2334 #ifdef NUM_R5900_REGS
2335 /* For the sky project, NUM_REGS includes the vector slaves,
2336 which are handled elsewhere */
2337 if (regnum
>= NUM_R5900_REGS
)
2340 /* end-sanitize-sky */
2345 /* Return number of args passed to a frame. described by FIP.
2346 Can return -1, meaning no way to tell. */
2349 mips_frame_num_args (frame
)
2350 struct frame_info
*frame
;
2352 #if 0 /* FIXME Use or lose this! */
2353 struct chain_info_t
*p
;
2355 p
= mips_find_cached_frame (FRAME_FP (frame
));
2357 return p
->the_info
.numargs
;
2362 /* Is this a branch with a delay slot? */
2364 static int is_delayed
PARAMS ((unsigned long));
2371 for (i
= 0; i
< NUMOPCODES
; ++i
)
2372 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2373 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2375 return (i
< NUMOPCODES
2376 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2377 | INSN_COND_BRANCH_DELAY
2378 | INSN_COND_BRANCH_LIKELY
)));
2382 mips_step_skips_delay (pc
)
2385 char buf
[MIPS_INSTLEN
];
2387 /* There is no branch delay slot on MIPS16. */
2388 if (pc_is_mips16 (pc
))
2391 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2392 /* If error reading memory, guess that it is not a delayed branch. */
2394 return is_delayed ((unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2398 /* Skip the PC past function prologue instructions (32-bit version).
2399 This is a helper function for mips_skip_prologue. */
2402 mips32_skip_prologue (pc
, lenient
)
2403 CORE_ADDR pc
; /* starting PC to search from */
2408 int seen_sp_adjust
= 0;
2409 int load_immediate_bytes
= 0;
2411 /* Skip the typical prologue instructions. These are the stack adjustment
2412 instruction and the instructions that save registers on the stack
2413 or in the gcc frame. */
2414 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2416 unsigned long high_word
;
2418 inst
= mips_fetch_instruction (pc
);
2419 high_word
= (inst
>> 16) & 0xffff;
2422 if (lenient
&& is_delayed (inst
))
2426 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2427 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2429 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2430 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2432 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2433 /* start-sanitize-r5900 */
2434 || (inst
& 0xFFE00000) == 0x7FA00000 /* sq reg,n($sp) */
2435 /* end-sanitize-r5900 */
2436 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2437 && (inst
& 0x001F0000)) /* reg != $zero */
2440 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2442 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2444 continue; /* reg != $zero */
2446 /* move $s8,$sp. With different versions of gas this will be either
2447 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2448 Accept any one of these. */
2449 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2452 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2454 else if (high_word
== 0x3c1c) /* lui $gp,n */
2456 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2458 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2459 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2461 /* The following instructions load $at or $t0 with an immediate
2462 value in preparation for a stack adjustment via
2463 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2464 a local variable, so we accept them only before a stack adjustment
2465 instruction was seen. */
2466 else if (!seen_sp_adjust
)
2468 if (high_word
== 0x3c01 || /* lui $at,n */
2469 high_word
== 0x3c08) /* lui $t0,n */
2471 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2474 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2475 high_word
== 0x3508 || /* ori $t0,$t0,n */
2476 high_word
== 0x3401 || /* ori $at,$zero,n */
2477 high_word
== 0x3408) /* ori $t0,$zero,n */
2479 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2489 /* In a frameless function, we might have incorrectly
2490 skipped some load immediate instructions. Undo the skipping
2491 if the load immediate was not followed by a stack adjustment. */
2492 if (load_immediate_bytes
&& !seen_sp_adjust
)
2493 pc
-= load_immediate_bytes
;
2497 /* Skip the PC past function prologue instructions (16-bit version).
2498 This is a helper function for mips_skip_prologue. */
2501 mips16_skip_prologue (pc
, lenient
)
2502 CORE_ADDR pc
; /* starting PC to search from */
2506 int extend_bytes
= 0;
2507 int prev_extend_bytes
;
2509 /* Table of instructions likely to be found in a function prologue. */
2512 unsigned short inst
;
2513 unsigned short mask
;
2516 { 0x6300, 0xff00 }, /* addiu $sp,offset */
2517 { 0xfb00, 0xff00 }, /* daddiu $sp,offset */
2518 { 0xd000, 0xf800 }, /* sw reg,n($sp) */
2519 { 0xf900, 0xff00 }, /* sd reg,n($sp) */
2520 { 0x6200, 0xff00 }, /* sw $ra,n($sp) */
2521 { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */
2522 { 0x673d, 0xffff }, /* move $s1,sp */
2523 { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */
2524 { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */
2525 { 0xe809, 0xf81f }, /* entry pseudo-op */
2526 { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */
2527 { 0, 0 } /* end of table marker */
2530 /* Skip the typical prologue instructions. These are the stack adjustment
2531 instruction and the instructions that save registers on the stack
2532 or in the gcc frame. */
2533 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2535 unsigned short inst
;
2538 inst
= mips_fetch_instruction (pc
);
2540 /* Normally we ignore an extend instruction. However, if it is
2541 not followed by a valid prologue instruction, we must adjust
2542 the pc back over the extend so that it won't be considered
2543 part of the prologue. */
2544 if ((inst
& 0xf800) == 0xf000) /* extend */
2546 extend_bytes
= MIPS16_INSTLEN
;
2549 prev_extend_bytes
= extend_bytes
;
2552 /* Check for other valid prologue instructions besides extend. */
2553 for (i
= 0; table
[i
].mask
!= 0; i
++)
2554 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2556 if (table
[i
].mask
!= 0) /* it was in table? */
2557 continue; /* ignore it */
2558 else /* non-prologue */
2560 /* Return the current pc, adjusted backwards by 2 if
2561 the previous instruction was an extend. */
2562 return pc
- prev_extend_bytes
;
2568 /* To skip prologues, I use this predicate. Returns either PC itself
2569 if the code at PC does not look like a function prologue; otherwise
2570 returns an address that (if we're lucky) follows the prologue. If
2571 LENIENT, then we must skip everything which is involved in setting
2572 up the frame (it's OK to skip more, just so long as we don't skip
2573 anything which might clobber the registers which are being saved.
2574 We must skip more in the case where part of the prologue is in the
2575 delay slot of a non-prologue instruction). */
2578 mips_skip_prologue (pc
, lenient
)
2582 /* See if we can determine the end of the prologue via the symbol table.
2583 If so, then return either PC, or the PC after the prologue, whichever
2586 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2588 if (post_prologue_pc
!= 0)
2589 return max (pc
, post_prologue_pc
);
2591 /* Can't determine prologue from the symbol table, need to examine
2594 if (pc_is_mips16 (pc
))
2595 return mips16_skip_prologue (pc
, lenient
);
2597 return mips32_skip_prologue (pc
, lenient
);
2601 /* The lenient prologue stuff should be superseded by the code in
2602 init_extra_frame_info which looks to see whether the stores mentioned
2603 in the proc_desc have actually taken place. */
2605 /* Is address PC in the prologue (loosely defined) for function at
2609 mips_in_lenient_prologue (startaddr
, pc
)
2610 CORE_ADDR startaddr
;
2613 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2614 return pc
>= startaddr
&& pc
< end_prologue
;
2618 /* Given a return value in `regbuf' with a type `valtype',
2619 extract and copy its value into `valbuf'. */
2621 mips_extract_return_value (valtype
, regbuf
, valbuf
)
2622 struct type
*valtype
;
2623 char regbuf
[REGISTER_BYTES
];
2628 int len
= TYPE_LENGTH (valtype
);
2631 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2632 && (mips_fpu
== MIPS_FPU_DOUBLE
2633 || (mips_fpu
== MIPS_FPU_SINGLE
&& len
<= MIPS_FPU_SINGLE_REGSIZE
)))
2634 regnum
= FP0_REGNUM
;
2636 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2637 { /* "un-left-justify" the value from the register */
2638 if (len
< REGISTER_RAW_SIZE (regnum
))
2639 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2640 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2641 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2642 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2643 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2644 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2646 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
2647 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
2650 /* Given a return value in `regbuf' with a type `valtype',
2651 write it's value into the appropriate register. */
2653 mips_store_return_value (valtype
, valbuf
)
2654 struct type
*valtype
;
2659 int len
= TYPE_LENGTH (valtype
);
2660 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2663 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2664 && (mips_fpu
== MIPS_FPU_DOUBLE
2665 || (mips_fpu
== MIPS_FPU_SINGLE
&& len
<= MIPS_REGSIZE
)))
2666 regnum
= FP0_REGNUM
;
2668 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2669 { /* "left-justify" the value in the register */
2670 if (len
< REGISTER_RAW_SIZE (regnum
))
2671 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2672 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2673 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2674 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2675 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2676 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2678 memcpy(raw_buffer
+ offset
, valbuf
, len
);
2679 REGISTER_CONVERT_FROM_TYPE(regnum
, valtype
, raw_buffer
);
2680 write_register_bytes(REGISTER_BYTE (regnum
), raw_buffer
,
2681 len
> REGISTER_RAW_SIZE (regnum
) ?
2682 len
: REGISTER_RAW_SIZE (regnum
));
2685 /* Exported procedure: Is PC in the signal trampoline code */
2688 in_sigtramp (pc
, ignore
)
2690 char *ignore
; /* function name */
2692 if (sigtramp_address
== 0)
2694 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
2697 /* Command to set FPU type. mips_fpu_string will have been set to the
2698 user's argument. Set mips_fpu based on mips_fpu_string, and then
2699 canonicalize mips_fpu_string. */
2703 mips_set_fpu_command (args
, from_tty
, c
)
2706 struct cmd_list_element
*c
;
2710 if (mips_fpu_string
== NULL
|| *mips_fpu_string
== '\0')
2711 mips_fpu
= MIPS_FPU_DOUBLE
;
2712 else if (strcasecmp (mips_fpu_string
, "double") == 0
2713 || strcasecmp (mips_fpu_string
, "on") == 0
2714 || strcasecmp (mips_fpu_string
, "1") == 0
2715 || strcasecmp (mips_fpu_string
, "yes") == 0)
2716 mips_fpu
= MIPS_FPU_DOUBLE
;
2717 else if (strcasecmp (mips_fpu_string
, "none") == 0
2718 || strcasecmp (mips_fpu_string
, "off") == 0
2719 || strcasecmp (mips_fpu_string
, "0") == 0
2720 || strcasecmp (mips_fpu_string
, "no") == 0)
2721 mips_fpu
= MIPS_FPU_NONE
;
2722 else if (strcasecmp (mips_fpu_string
, "single") == 0)
2723 mips_fpu
= MIPS_FPU_SINGLE
;
2725 err
= strsave (mips_fpu_string
);
2727 if (mips_fpu_string
!= NULL
)
2728 free (mips_fpu_string
);
2732 case MIPS_FPU_DOUBLE
:
2733 mips_fpu_string
= strsave ("double");
2735 case MIPS_FPU_SINGLE
:
2736 mips_fpu_string
= strsave ("single");
2739 mips_fpu_string
= strsave ("none");
2745 struct cleanup
*cleanups
= make_cleanup (free
, err
);
2746 error ("Unknown FPU type `%s'. Use `double', `none', or `single'.",
2748 do_cleanups (cleanups
);
2753 mips_show_fpu_command (args
, from_tty
, c
)
2756 struct cmd_list_element
*c
;
2760 /* Command to set the processor type. */
2763 mips_set_processor_type_command (args
, from_tty
)
2769 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
2771 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
2772 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2773 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
2775 /* Restore the value. */
2776 tmp_mips_processor_type
= strsave (mips_processor_type
);
2781 if (!mips_set_processor_type (tmp_mips_processor_type
))
2783 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
2784 /* Restore its value. */
2785 tmp_mips_processor_type
= strsave (mips_processor_type
);
2790 mips_show_processor_type_command (args
, from_tty
)
2796 /* Modify the actual processor type. */
2799 mips_set_processor_type (str
)
2807 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2809 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
2811 mips_processor_type
= str
;
2813 for (j
= 0; j
< NUM_REGS
; ++j
)
2814 reg_names
[j
] = mips_processor_type_table
[i
].regnames
[j
];
2818 /* FIXME tweak fpu flag too */
2825 /* Attempt to identify the particular processor model by reading the
2829 mips_read_processor_type ()
2833 prid
= read_register (PRID_REGNUM
);
2835 if ((prid
& ~0xf) == 0x700)
2836 return savestring ("r3041", strlen("r3041"));
2841 /* Just like reinit_frame_cache, but with the right arguments to be
2842 callable as an sfunc. */
2845 reinit_frame_cache_sfunc (args
, from_tty
, c
)
2848 struct cmd_list_element
*c
;
2850 reinit_frame_cache ();
2854 gdb_print_insn_mips (memaddr
, info
)
2856 disassemble_info
*info
;
2858 mips_extra_func_info_t proc_desc
;
2860 /* Search for the function containing this address. Set the low bit
2861 of the address when searching, in case we were given an even address
2862 that is the start of a 16-bit function. If we didn't do this,
2863 the search would fail because the symbol table says the function
2864 starts at an odd address, i.e. 1 byte past the given address. */
2865 memaddr
= ADDR_BITS_REMOVE (memaddr
);
2866 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
2868 /* Make an attempt to determine if this is a 16-bit function. If
2869 the procedure descriptor exists and the address therein is odd,
2870 it's definitely a 16-bit function. Otherwise, we have to just
2871 guess that if the address passed in is odd, it's 16-bits. */
2873 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
2875 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
2877 /* Round down the instruction address to the appropriate boundary. */
2878 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
2880 /* Call the appropriate disassembler based on the target endian-ness. */
2881 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2882 return print_insn_big_mips (memaddr
, info
);
2884 return print_insn_little_mips (memaddr
, info
);
2887 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
2888 counter value to determine whether a 16- or 32-bit breakpoint should be
2889 used. It returns a pointer to a string of bytes that encode a breakpoint
2890 instruction, stores the length of the string to *lenptr, and adjusts pc
2891 (if necessary) to point to the actual memory location where the
2892 breakpoint should be inserted. */
2894 unsigned char *mips_breakpoint_from_pc (pcptr
, lenptr
)
2898 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2900 if (pc_is_mips16 (*pcptr
))
2902 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
2903 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2904 *lenptr
= sizeof(mips16_big_breakpoint
);
2905 return mips16_big_breakpoint
;
2909 static char big_breakpoint
[] = BIG_BREAKPOINT
;
2910 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
2911 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
2913 *lenptr
= sizeof(big_breakpoint
);
2915 if (strcmp (target_shortname
, "mips") == 0)
2916 return idt_big_breakpoint
;
2917 else if (strcmp (target_shortname
, "ddb") == 0
2918 || strcmp (target_shortname
, "pmon") == 0
2919 || strcmp (target_shortname
, "lsi") == 0)
2920 return pmon_big_breakpoint
;
2922 return big_breakpoint
;
2927 if (pc_is_mips16 (*pcptr
))
2929 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
2930 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2931 *lenptr
= sizeof(mips16_little_breakpoint
);
2932 return mips16_little_breakpoint
;
2936 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
2937 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
2938 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
2940 *lenptr
= sizeof(little_breakpoint
);
2942 if (strcmp (target_shortname
, "mips") == 0)
2943 return idt_little_breakpoint
;
2944 else if (strcmp (target_shortname
, "ddb") == 0
2945 || strcmp (target_shortname
, "pmon") == 0
2946 || strcmp (target_shortname
, "lsi") == 0)
2947 return pmon_little_breakpoint
;
2949 return little_breakpoint
;
2954 /* Test whether the PC points to the return instruction at the
2955 end of a function. This implements the ABOUT_TO_RETURN macro. */
2958 mips_about_to_return (pc
)
2961 if (pc_is_mips16 (pc
))
2962 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2963 generates a "jr $ra"; other times it generates code to load
2964 the return address from the stack to an accessible register (such
2965 as $a3), then a "jr" using that register. This second case
2966 is almost impossible to distinguish from an indirect jump
2967 used for switch statements, so we don't even try. */
2968 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2970 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2974 /* If PC is in a mips16 call or return stub, return the address of the target
2975 PC, which is either the callee or the caller. There are several
2976 cases which must be handled:
2978 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
2979 target PC is in $31 ($ra).
2980 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
2981 and the target PC is in $2.
2982 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2983 before the jal instruction, this is effectively a call stub
2984 and the the target PC is in $2. Otherwise this is effectively
2985 a return stub and the target PC is in $18.
2987 See the source code for the stubs in gcc/config/mips/mips16.S for
2990 This function implements the SKIP_TRAMPOLINE_CODE macro.
2998 CORE_ADDR start_addr
;
3000 /* Find the starting address and name of the function containing the PC. */
3001 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3004 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3005 target PC is in $31 ($ra). */
3006 if (strcmp (name
, "__mips16_ret_sf") == 0
3007 || strcmp (name
, "__mips16_ret_df") == 0)
3008 return read_register (RA_REGNUM
);
3010 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3012 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3013 and the target PC is in $2. */
3014 if (name
[19] >= '0' && name
[19] <= '9')
3015 return read_register (2);
3017 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3018 before the jal instruction, this is effectively a call stub
3019 and the the target PC is in $2. Otherwise this is effectively
3020 a return stub and the target PC is in $18. */
3021 else if (name
[19] == 's' || name
[19] == 'd')
3023 if (pc
== start_addr
)
3025 /* Check if the target of the stub is a compiler-generated
3026 stub. Such a stub for a function bar might have a name
3027 like __fn_stub_bar, and might look like this:
3032 la $1,bar (becomes a lui/addiu pair)
3034 So scan down to the lui/addi and extract the target
3035 address from those two instructions. */
3037 CORE_ADDR target_pc
= read_register (2);
3041 /* See if the name of the target function is __fn_stub_*. */
3042 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3044 if (strncmp (name
, "__fn_stub_", 10) != 0
3045 && strcmp (name
, "etext") != 0
3046 && strcmp (name
, "_etext") != 0)
3049 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3050 The limit on the search is arbitrarily set to 20
3051 instructions. FIXME. */
3052 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3054 inst
= mips_fetch_instruction (target_pc
);
3055 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3056 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3057 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3058 return pc
| (inst
& 0xffff); /* low word */
3061 /* Couldn't find the lui/addui pair, so return stub address. */
3065 /* This is the 'return' part of a call stub. The return
3066 address is in $r18. */
3067 return read_register (18);
3070 return 0; /* not a stub */
3074 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3075 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3078 mips_in_call_stub (pc
, name
)
3082 CORE_ADDR start_addr
;
3084 /* Find the starting address of the function containing the PC. If the
3085 caller didn't give us a name, look it up at the same time. */
3086 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3089 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3091 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3092 if (name
[19] >= '0' && name
[19] <= '9')
3094 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3095 before the jal instruction, this is effectively a call stub. */
3096 else if (name
[19] == 's' || name
[19] == 'd')
3097 return pc
== start_addr
;
3100 return 0; /* not a stub */
3104 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3105 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3108 mips_in_return_stub (pc
, name
)
3112 CORE_ADDR start_addr
;
3114 /* Find the starting address of the function containing the PC. */
3115 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3118 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3119 if (strcmp (name
, "__mips16_ret_sf") == 0
3120 || strcmp (name
, "__mips16_ret_df") == 0)
3123 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3124 i.e. after the jal instruction, this is effectively a return stub. */
3125 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3126 && (name
[19] == 's' || name
[19] == 'd')
3127 && pc
!= start_addr
)
3130 return 0; /* not a stub */
3134 /* Return non-zero if the PC is in a library helper function that should
3135 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3138 mips_ignore_helper (pc
)
3143 /* Find the starting address and name of the function containing the PC. */
3144 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3147 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3148 that we want to ignore. */
3149 return (strcmp (name
, "__mips16_ret_sf") == 0
3150 || strcmp (name
, "__mips16_ret_df") == 0);
3155 _initialize_mips_tdep ()
3157 struct cmd_list_element
*c
;
3159 if (!tm_print_insn
) /* Someone may have already set it */
3160 tm_print_insn
= gdb_print_insn_mips
;
3162 /* Let the user turn off floating point and set the fence post for
3163 heuristic_proc_start. */
3165 c
= add_set_cmd ("mipsfpu", class_support
, var_string_noescape
,
3166 (char *) &mips_fpu_string
,
3167 "Set use of floating point coprocessor.\n\
3168 Set to `none' to avoid using floating point instructions when calling\n\
3169 functions or dealing with return values. Set to `single' to use only\n\
3170 single precision floating point as on the R4650. Set to `double' for\n\
3171 normal floating point support.",
3173 c
->function
.sfunc
= mips_set_fpu_command
;
3174 c
= add_show_from_set (c
, &showlist
);
3175 c
->function
.sfunc
= mips_show_fpu_command
;
3177 #ifndef MIPS_DEFAULT_FPU_TYPE
3178 mips_fpu
= MIPS_FPU_DOUBLE
;
3179 mips_fpu_string
= strsave ("double");
3181 mips_fpu
= MIPS_DEFAULT_FPU_TYPE
;
3184 case MIPS_FPU_DOUBLE
: mips_fpu_string
= strsave ("double"); break;
3185 case MIPS_FPU_SINGLE
: mips_fpu_string
= strsave ("single"); break;
3186 case MIPS_FPU_NONE
: mips_fpu_string
= strsave ("none"); break;
3190 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
3191 (char *) &tmp_mips_processor_type
,
3192 "Set the type of MIPS processor in use.\n\
3193 Set this to be able to access processor-type-specific registers.\n\
3196 c
->function
.cfunc
= mips_set_processor_type_command
;
3197 c
= add_show_from_set (c
, &showlist
);
3198 c
->function
.cfunc
= mips_show_processor_type_command
;
3200 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
3201 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
3203 /* We really would like to have both "0" and "unlimited" work, but
3204 command.c doesn't deal with that. So make it a var_zinteger
3205 because the user can always use "999999" or some such for unlimited. */
3206 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
3207 (char *) &heuristic_fence_post
,
3209 Set the distance searched for the start of a function.\n\
3210 If you are debugging a stripped executable, GDB needs to search through the\n\
3211 program for the start of a function. This command sets the distance of the\n\
3212 search. The only need to set it is when debugging a stripped executable.",
3214 /* We need to throw away the frame cache when we set this, since it
3215 might change our ability to get backtraces. */
3216 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
3217 add_show_from_set (c
, &showlist
);