1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 #include "target-descriptions.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
78 static const char *mips_abi_string
;
80 static const char *mips_abi_strings
[] = {
91 /* Various MIPS ISA options (related to stack analysis) can be
92 overridden dynamically. Establish an enum/array for managing
95 static const char size_auto
[] = "auto";
96 static const char size_32
[] = "32";
97 static const char size_64
[] = "64";
99 static const char *size_enums
[] = {
106 /* Some MIPS boards don't support floating point while others only
107 support single-precision floating-point operations. */
111 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
112 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
113 MIPS_FPU_NONE
/* No floating point. */
116 #ifndef MIPS_DEFAULT_FPU_TYPE
117 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
119 static int mips_fpu_type_auto
= 1;
120 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
122 static int mips_debug
= 0;
124 /* Properties (for struct target_desc) describing the g/G packet
126 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
127 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
129 /* MIPS specific per-architecture information */
132 /* from the elf header */
136 enum mips_abi mips_abi
;
137 enum mips_abi found_abi
;
138 enum mips_fpu_type mips_fpu_type
;
139 int mips_last_arg_regnum
;
140 int mips_last_fp_arg_regnum
;
141 int default_mask_address_p
;
142 /* Is the target using 64-bit raw integer registers but only
143 storing a left-aligned 32-bit value in each? */
144 int mips64_transfers_32bit_regs_p
;
145 /* Indexes for various registers. IRIX and embedded have
146 different values. This contains the "public" fields. Don't
147 add any that do not need to be public. */
148 const struct mips_regnum
*regnum
;
149 /* Register names table for the current register set. */
150 const char **mips_processor_reg_names
;
152 /* The size of register data available from the target, if known.
153 This doesn't quite obsolete the manual
154 mips64_transfers_32bit_regs_p, since that is documented to force
155 left alignment even for big endian (very strange). */
156 int register_size_valid_p
;
161 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
167 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
168 They are implemented as a pair of 64bit doubles where the high
169 part holds the result of the operation rounded to double, and
170 the low double holds the difference between the exact result and
171 the rounded result. So "high" + "low" contains the result with
172 added precision. Unfortunately, the floatformat structure used
173 by GDB is not powerful enough to describe this format. As a temporary
174 measure, we define a 128bit floatformat that only uses the high part.
175 We lose a bit of precision but that's probably the best we can do
176 for now with the current infrastructure. */
178 static const struct floatformat floatformat_n32n64_long_double_big
=
180 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
181 floatformat_intbit_no
,
182 "floatformat_n32n64_long_double_big",
183 n32n64_floatformat_always_valid
186 static const struct floatformat
*floatformats_n32n64_long
[BFD_ENDIAN_UNKNOWN
] =
188 &floatformat_n32n64_long_double_big
,
189 &floatformat_n32n64_long_double_big
192 const struct mips_regnum
*
193 mips_regnum (struct gdbarch
*gdbarch
)
195 return gdbarch_tdep (gdbarch
)->regnum
;
199 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
201 return mips_regnum (gdbarch
)->fp0
+ 12;
204 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
205 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
207 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
209 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
211 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
213 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
214 functions to test, set, or clear bit 0 of addresses. */
217 is_mips16_addr (CORE_ADDR addr
)
223 unmake_mips16_addr (CORE_ADDR addr
)
225 return ((addr
) & ~(CORE_ADDR
) 1);
228 /* Return the contents of register REGNUM as a signed integer. */
231 read_signed_register (int regnum
)
234 regcache_cooked_read_signed (current_regcache
, regnum
, &val
);
239 read_signed_register_pid (int regnum
, ptid_t ptid
)
244 if (ptid_equal (ptid
, inferior_ptid
))
245 return read_signed_register (regnum
);
247 save_ptid
= inferior_ptid
;
249 inferior_ptid
= ptid
;
251 retval
= read_signed_register (regnum
);
253 inferior_ptid
= save_ptid
;
258 /* Return the MIPS ABI associated with GDBARCH. */
260 mips_abi (struct gdbarch
*gdbarch
)
262 return gdbarch_tdep (gdbarch
)->mips_abi
;
266 mips_isa_regsize (struct gdbarch
*gdbarch
)
268 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
270 /* If we know how big the registers are, use that size. */
271 if (tdep
->register_size_valid_p
)
272 return tdep
->register_size
;
274 /* Fall back to the previous behavior. */
275 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
276 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
279 /* Return the currently configured (or set) saved register size. */
281 static const char *mips_abi_regsize_string
= size_auto
;
284 mips_abi_regsize (struct gdbarch
*gdbarch
)
286 if (mips_abi_regsize_string
== size_auto
)
287 switch (mips_abi (gdbarch
))
289 case MIPS_ABI_EABI32
:
295 case MIPS_ABI_EABI64
:
297 case MIPS_ABI_UNKNOWN
:
300 internal_error (__FILE__
, __LINE__
, _("bad switch"));
302 else if (mips_abi_regsize_string
== size_64
)
304 else /* if (mips_abi_regsize_string == size_32) */
308 /* Functions for setting and testing a bit in a minimal symbol that
309 marks it as 16-bit function. The MSB of the minimal symbol's
310 "info" field is used for this purpose.
312 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
313 i.e. refers to a 16-bit function, and sets a "special" bit in a
314 minimal symbol to mark it as a 16-bit function
316 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
319 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
321 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
323 MSYMBOL_INFO (msym
) = (char *)
324 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
325 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
330 msymbol_is_special (struct minimal_symbol
*msym
)
332 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
335 /* XFER a value from the big/little/left end of the register.
336 Depending on the size of the value it might occupy the entire
337 register or just part of it. Make an allowance for this, aligning
338 things accordingly. */
341 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
342 enum bfd_endian endian
, gdb_byte
*in
,
343 const gdb_byte
*out
, int buf_offset
)
346 gdb_assert (reg_num
>= NUM_REGS
);
347 /* Need to transfer the left or right part of the register, based on
348 the targets byte order. */
352 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
354 case BFD_ENDIAN_LITTLE
:
357 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
361 internal_error (__FILE__
, __LINE__
, _("bad switch"));
364 fprintf_unfiltered (gdb_stderr
,
365 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
366 reg_num
, reg_offset
, buf_offset
, length
);
367 if (mips_debug
&& out
!= NULL
)
370 fprintf_unfiltered (gdb_stdlog
, "out ");
371 for (i
= 0; i
< length
; i
++)
372 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
375 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
378 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
380 if (mips_debug
&& in
!= NULL
)
383 fprintf_unfiltered (gdb_stdlog
, "in ");
384 for (i
= 0; i
< length
; i
++)
385 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
388 fprintf_unfiltered (gdb_stdlog
, "\n");
391 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
392 compatiblity mode. A return value of 1 means that we have
393 physical 64-bit registers, but should treat them as 32-bit registers. */
396 mips2_fp_compat (void)
398 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
400 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
405 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
406 in all the places we deal with FP registers. PR gdb/413. */
407 /* Otherwise check the FR bit in the status register - it controls
408 the FP compatiblity mode. If it is clear we are in compatibility
410 if ((read_register (MIPS_PS_REGNUM
) & ST0_FR
) == 0)
417 /* The amount of space reserved on the stack for registers. This is
418 different to MIPS_ABI_REGSIZE as it determines the alignment of
419 data allocated after the registers have run out. */
421 static const char *mips_stack_argsize_string
= size_auto
;
424 mips_stack_argsize (struct gdbarch
*gdbarch
)
426 if (mips_stack_argsize_string
== size_auto
)
427 return mips_abi_regsize (gdbarch
);
428 else if (mips_stack_argsize_string
== size_64
)
430 else /* if (mips_stack_argsize_string == size_32) */
434 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
436 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
438 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
440 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
442 static struct type
*mips_float_register_type (void);
443 static struct type
*mips_double_register_type (void);
445 /* The list of available "set mips " and "show mips " commands */
447 static struct cmd_list_element
*setmipscmdlist
= NULL
;
448 static struct cmd_list_element
*showmipscmdlist
= NULL
;
450 /* Integer registers 0 thru 31 are handled explicitly by
451 mips_register_name(). Processor specific registers 32 and above
452 are listed in the followign tables. */
455 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
459 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
460 "sr", "lo", "hi", "bad", "cause", "pc",
461 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
462 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
463 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
464 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
465 "fsr", "fir", "" /*"fp" */ , "",
466 "", "", "", "", "", "", "", "",
467 "", "", "", "", "", "", "", "",
470 /* Names of IDT R3041 registers. */
472 static const char *mips_r3041_reg_names
[] = {
473 "sr", "lo", "hi", "bad", "cause", "pc",
474 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
475 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
476 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
477 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
478 "fsr", "fir", "", /*"fp" */ "",
479 "", "", "bus", "ccfg", "", "", "", "",
480 "", "", "port", "cmp", "", "", "epc", "prid",
483 /* Names of tx39 registers. */
485 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
486 "sr", "lo", "hi", "bad", "cause", "pc",
487 "", "", "", "", "", "", "", "",
488 "", "", "", "", "", "", "", "",
489 "", "", "", "", "", "", "", "",
490 "", "", "", "", "", "", "", "",
492 "", "", "", "", "", "", "", "",
493 "", "", "config", "cache", "debug", "depc", "epc", ""
496 /* Names of IRIX registers. */
497 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
498 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
499 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
500 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
501 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
502 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
506 /* Return the name of the register corresponding to REGNO. */
508 mips_register_name (int regno
)
510 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
511 /* GPR names for all ABIs other than n32/n64. */
512 static char *mips_gpr_names
[] = {
513 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
514 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
515 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
516 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
519 /* GPR names for n32 and n64 ABIs. */
520 static char *mips_n32_n64_gpr_names
[] = {
521 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
522 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
523 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
524 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
527 enum mips_abi abi
= mips_abi (current_gdbarch
);
529 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
530 don't make the raw register names visible. */
531 int rawnum
= regno
% NUM_REGS
;
532 if (regno
< NUM_REGS
)
535 /* The MIPS integer registers are always mapped from 0 to 31. The
536 names of the registers (which reflects the conventions regarding
537 register use) vary depending on the ABI. */
538 if (0 <= rawnum
&& rawnum
< 32)
540 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
541 return mips_n32_n64_gpr_names
[rawnum
];
543 return mips_gpr_names
[rawnum
];
545 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
547 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
548 return tdep
->mips_processor_reg_names
[rawnum
- 32];
551 internal_error (__FILE__
, __LINE__
,
552 _("mips_register_name: bad register number %d"), rawnum
);
555 /* Return the groups that a MIPS register can be categorised into. */
558 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
559 struct reggroup
*reggroup
)
564 int rawnum
= regnum
% NUM_REGS
;
565 int pseudo
= regnum
/ NUM_REGS
;
566 if (reggroup
== all_reggroup
)
568 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
569 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
570 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
571 (gdbarch), as not all architectures are multi-arch. */
572 raw_p
= rawnum
< NUM_REGS
;
573 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
575 if (reggroup
== float_reggroup
)
576 return float_p
&& pseudo
;
577 if (reggroup
== vector_reggroup
)
578 return vector_p
&& pseudo
;
579 if (reggroup
== general_reggroup
)
580 return (!vector_p
&& !float_p
) && pseudo
;
581 /* Save the pseudo registers. Need to make certain that any code
582 extracting register values from a saved register cache also uses
584 if (reggroup
== save_reggroup
)
585 return raw_p
&& pseudo
;
586 /* Restore the same pseudo register. */
587 if (reggroup
== restore_reggroup
)
588 return raw_p
&& pseudo
;
592 /* Map the symbol table registers which live in the range [1 *
593 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
594 registers. Take care of alignment and size problems. */
597 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
598 int cookednum
, gdb_byte
*buf
)
600 int rawnum
= cookednum
% NUM_REGS
;
601 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
602 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
603 regcache_raw_read (regcache
, rawnum
, buf
);
604 else if (register_size (gdbarch
, rawnum
) >
605 register_size (gdbarch
, cookednum
))
607 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
608 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
609 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
611 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
614 internal_error (__FILE__
, __LINE__
, _("bad register size"));
618 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
619 struct regcache
*regcache
, int cookednum
,
622 int rawnum
= cookednum
% NUM_REGS
;
623 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
624 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
625 regcache_raw_write (regcache
, rawnum
, buf
);
626 else if (register_size (gdbarch
, rawnum
) >
627 register_size (gdbarch
, cookednum
))
629 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
630 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
631 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
633 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
636 internal_error (__FILE__
, __LINE__
, _("bad register size"));
639 /* Table to translate MIPS16 register field to actual register number. */
640 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
642 /* Heuristic_proc_start may hunt through the text section for a long
643 time across a 2400 baud serial line. Allows the user to limit this
646 static unsigned int heuristic_fence_post
= 0;
648 /* Number of bytes of storage in the actual machine representation for
649 register N. NOTE: This defines the pseudo register type so need to
650 rebuild the architecture vector. */
652 static int mips64_transfers_32bit_regs_p
= 0;
655 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
656 struct cmd_list_element
*c
)
658 struct gdbarch_info info
;
659 gdbarch_info_init (&info
);
660 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
661 instead of relying on globals. Doing that would let generic code
662 handle the search for this specific architecture. */
663 if (!gdbarch_update_p (info
))
665 mips64_transfers_32bit_regs_p
= 0;
666 error (_("32-bit compatibility mode not supported"));
670 /* Convert to/from a register and the corresponding memory value. */
673 mips_convert_register_p (int regnum
, struct type
*type
)
675 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
676 && register_size (current_gdbarch
, regnum
) == 4
677 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
678 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
679 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
683 mips_register_to_value (struct frame_info
*frame
, int regnum
,
684 struct type
*type
, gdb_byte
*to
)
686 get_frame_register (frame
, regnum
+ 0, to
+ 4);
687 get_frame_register (frame
, regnum
+ 1, to
+ 0);
691 mips_value_to_register (struct frame_info
*frame
, int regnum
,
692 struct type
*type
, const gdb_byte
*from
)
694 put_frame_register (frame
, regnum
+ 0, from
+ 4);
695 put_frame_register (frame
, regnum
+ 1, from
+ 0);
698 /* Return the GDB type object for the "standard" data type of data in
702 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
704 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
705 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
706 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
708 /* The floating-point registers raw, or cooked, always match
709 mips_isa_regsize(), and also map 1:1, byte for byte. */
710 if (mips_isa_regsize (gdbarch
) == 4)
711 return builtin_type_ieee_single
;
713 return builtin_type_ieee_double
;
715 else if (regnum
< NUM_REGS
)
717 /* The raw or ISA registers. These are all sized according to
719 if (mips_isa_regsize (gdbarch
) == 4)
720 return builtin_type_int32
;
722 return builtin_type_int64
;
726 /* The cooked or ABI registers. These are sized according to
727 the ABI (with a few complications). */
728 if (regnum
>= (NUM_REGS
729 + mips_regnum (current_gdbarch
)->fp_control_status
)
730 && regnum
<= NUM_REGS
+ MIPS_LAST_EMBED_REGNUM
)
731 /* The pseudo/cooked view of the embedded registers is always
732 32-bit. The raw view is handled below. */
733 return builtin_type_int32
;
734 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
735 /* The target, while possibly using a 64-bit register buffer,
736 is only transfering 32-bits of each integer register.
737 Reflect this in the cooked/pseudo (ABI) register value. */
738 return builtin_type_int32
;
739 else if (mips_abi_regsize (gdbarch
) == 4)
740 /* The ABI is restricted to 32-bit registers (the ISA could be
742 return builtin_type_int32
;
745 return builtin_type_int64
;
749 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
754 return read_signed_register (MIPS_SP_REGNUM
);
757 /* Should the upper word of 64-bit addresses be zeroed? */
758 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
761 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
763 switch (mask_address_var
)
765 case AUTO_BOOLEAN_TRUE
:
767 case AUTO_BOOLEAN_FALSE
:
770 case AUTO_BOOLEAN_AUTO
:
771 return tdep
->default_mask_address_p
;
773 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
779 show_mask_address (struct ui_file
*file
, int from_tty
,
780 struct cmd_list_element
*c
, const char *value
)
782 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
784 deprecated_show_value_hack (file
, from_tty
, c
, value
);
785 switch (mask_address_var
)
787 case AUTO_BOOLEAN_TRUE
:
788 printf_filtered ("The 32 bit mips address mask is enabled\n");
790 case AUTO_BOOLEAN_FALSE
:
791 printf_filtered ("The 32 bit mips address mask is disabled\n");
793 case AUTO_BOOLEAN_AUTO
:
795 ("The 32 bit address mask is set automatically. Currently %s\n",
796 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
799 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
804 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
807 mips_pc_is_mips16 (CORE_ADDR memaddr
)
809 struct minimal_symbol
*sym
;
811 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
812 if (is_mips16_addr (memaddr
))
815 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
816 the high bit of the info field. Use this to decide if the function is
817 MIPS16 or normal MIPS. */
818 sym
= lookup_minimal_symbol_by_pc (memaddr
);
820 return msymbol_is_special (sym
);
825 /* MIPS believes that the PC has a sign extended value. Perhaps the
826 all registers should be sign extended for simplicity? */
829 mips_read_pc (ptid_t ptid
)
831 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
835 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
837 return frame_unwind_register_signed (next_frame
,
838 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
841 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
842 dummy frame. The frame ID's base needs to match the TOS value
843 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
846 static struct frame_id
847 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
849 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
850 frame_pc_unwind (next_frame
));
854 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
856 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
859 /* Fetch and return instruction from the specified location. If the PC
860 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
863 mips_fetch_instruction (CORE_ADDR addr
)
865 gdb_byte buf
[MIPS_INSN32_SIZE
];
869 if (mips_pc_is_mips16 (addr
))
871 instlen
= MIPS_INSN16_SIZE
;
872 addr
= unmake_mips16_addr (addr
);
875 instlen
= MIPS_INSN32_SIZE
;
876 status
= read_memory_nobpt (addr
, buf
, instlen
);
878 memory_error (status
, addr
);
879 return extract_unsigned_integer (buf
, instlen
);
882 /* These the fields of 32 bit mips instructions */
883 #define mips32_op(x) (x >> 26)
884 #define itype_op(x) (x >> 26)
885 #define itype_rs(x) ((x >> 21) & 0x1f)
886 #define itype_rt(x) ((x >> 16) & 0x1f)
887 #define itype_immediate(x) (x & 0xffff)
889 #define jtype_op(x) (x >> 26)
890 #define jtype_target(x) (x & 0x03ffffff)
892 #define rtype_op(x) (x >> 26)
893 #define rtype_rs(x) ((x >> 21) & 0x1f)
894 #define rtype_rt(x) ((x >> 16) & 0x1f)
895 #define rtype_rd(x) ((x >> 11) & 0x1f)
896 #define rtype_shamt(x) ((x >> 6) & 0x1f)
897 #define rtype_funct(x) (x & 0x3f)
900 mips32_relative_offset (ULONGEST inst
)
902 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
905 /* Determine where to set a single step breakpoint while considering
906 branch prediction. */
908 mips32_next_pc (CORE_ADDR pc
)
912 inst
= mips_fetch_instruction (pc
);
913 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
915 if (itype_op (inst
) >> 2 == 5)
916 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
918 op
= (itype_op (inst
) & 0x03);
933 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
934 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
936 int tf
= itype_rt (inst
) & 0x01;
937 int cnum
= itype_rt (inst
) >> 2;
939 read_signed_register (mips_regnum (current_gdbarch
)->
941 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
943 if (((cond
>> cnum
) & 0x01) == tf
)
944 pc
+= mips32_relative_offset (inst
) + 4;
949 pc
+= 4; /* Not a branch, next instruction is easy */
952 { /* This gets way messy */
954 /* Further subdivide into SPECIAL, REGIMM and other */
955 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
957 case 0: /* SPECIAL */
958 op
= rtype_funct (inst
);
963 /* Set PC to that address */
964 pc
= read_signed_register (rtype_rs (inst
));
970 break; /* end SPECIAL */
973 op
= itype_rt (inst
); /* branch condition */
978 case 16: /* BLTZAL */
979 case 18: /* BLTZALL */
981 if (read_signed_register (itype_rs (inst
)) < 0)
982 pc
+= mips32_relative_offset (inst
) + 4;
984 pc
+= 8; /* after the delay slot */
988 case 17: /* BGEZAL */
989 case 19: /* BGEZALL */
990 if (read_signed_register (itype_rs (inst
)) >= 0)
991 pc
+= mips32_relative_offset (inst
) + 4;
993 pc
+= 8; /* after the delay slot */
995 /* All of the other instructions in the REGIMM category */
1000 break; /* end REGIMM */
1005 reg
= jtype_target (inst
) << 2;
1006 /* Upper four bits get never changed... */
1007 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1010 /* FIXME case JALX : */
1013 reg
= jtype_target (inst
) << 2;
1014 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1015 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1017 break; /* The new PC will be alternate mode */
1018 case 4: /* BEQ, BEQL */
1020 if (read_signed_register (itype_rs (inst
)) ==
1021 read_signed_register (itype_rt (inst
)))
1022 pc
+= mips32_relative_offset (inst
) + 4;
1026 case 5: /* BNE, BNEL */
1028 if (read_signed_register (itype_rs (inst
)) !=
1029 read_signed_register (itype_rt (inst
)))
1030 pc
+= mips32_relative_offset (inst
) + 4;
1034 case 6: /* BLEZ, BLEZL */
1035 if (read_signed_register (itype_rs (inst
)) <= 0)
1036 pc
+= mips32_relative_offset (inst
) + 4;
1042 greater_branch
: /* BGTZ, BGTZL */
1043 if (read_signed_register (itype_rs (inst
)) > 0)
1044 pc
+= mips32_relative_offset (inst
) + 4;
1051 } /* mips32_next_pc */
1053 /* Decoding the next place to set a breakpoint is irregular for the
1054 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1055 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1056 We dont want to set a single step instruction on the extend instruction
1060 /* Lots of mips16 instruction formats */
1061 /* Predicting jumps requires itype,ritype,i8type
1062 and their extensions extItype,extritype,extI8type
1064 enum mips16_inst_fmts
1066 itype
, /* 0 immediate 5,10 */
1067 ritype
, /* 1 5,3,8 */
1068 rrtype
, /* 2 5,3,3,5 */
1069 rritype
, /* 3 5,3,3,5 */
1070 rrrtype
, /* 4 5,3,3,3,2 */
1071 rriatype
, /* 5 5,3,3,1,4 */
1072 shifttype
, /* 6 5,3,3,3,2 */
1073 i8type
, /* 7 5,3,8 */
1074 i8movtype
, /* 8 5,3,3,5 */
1075 i8mov32rtype
, /* 9 5,3,5,3 */
1076 i64type
, /* 10 5,3,8 */
1077 ri64type
, /* 11 5,3,3,5 */
1078 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1079 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1080 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1081 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1082 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1083 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1084 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1085 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1086 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1087 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1089 /* I am heaping all the fields of the formats into one structure and
1090 then, only the fields which are involved in instruction extension */
1094 unsigned int regx
; /* Function in i8 type */
1099 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1100 for the bits which make up the immediatate extension. */
1103 extended_offset (unsigned int extension
)
1106 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1108 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1110 value
|= extension
& 0x01f; /* extract 4:0 */
1114 /* Only call this function if you know that this is an extendable
1115 instruction, It wont malfunction, but why make excess remote memory references?
1116 If the immediate operands get sign extended or somthing, do it after
1117 the extension is performed.
1119 /* FIXME: Every one of these cases needs to worry about sign extension
1120 when the offset is to be used in relative addressing */
1124 fetch_mips_16 (CORE_ADDR pc
)
1127 pc
&= 0xfffffffe; /* clear the low order bit */
1128 target_read_memory (pc
, buf
, 2);
1129 return extract_unsigned_integer (buf
, 2);
1133 unpack_mips16 (CORE_ADDR pc
,
1134 unsigned int extension
,
1136 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1141 switch (insn_format
)
1148 value
= extended_offset (extension
);
1149 value
= value
<< 11; /* rom for the original value */
1150 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1154 value
= inst
& 0x7ff;
1155 /* FIXME : Consider sign extension */
1164 { /* A register identifier and an offset */
1165 /* Most of the fields are the same as I type but the
1166 immediate value is of a different length */
1170 value
= extended_offset (extension
);
1171 value
= value
<< 8; /* from the original instruction */
1172 value
|= inst
& 0xff; /* eleven bits from instruction */
1173 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1174 if (value
& 0x4000) /* test the sign bit , bit 26 */
1176 value
&= ~0x3fff; /* remove the sign bit */
1182 value
= inst
& 0xff; /* 8 bits */
1183 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1184 /* FIXME: Do sign extension , this format needs it */
1185 if (value
& 0x80) /* THIS CONFUSES ME */
1187 value
&= 0xef; /* remove the sign bit */
1197 unsigned long value
;
1198 unsigned int nexthalf
;
1199 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1200 value
= value
<< 16;
1201 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1209 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1211 upk
->offset
= offset
;
1218 add_offset_16 (CORE_ADDR pc
, int offset
)
1220 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1224 extended_mips16_next_pc (CORE_ADDR pc
,
1225 unsigned int extension
, unsigned int insn
)
1227 int op
= (insn
>> 11);
1230 case 2: /* Branch */
1233 struct upk_mips16 upk
;
1234 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1235 offset
= upk
.offset
;
1241 pc
+= (offset
<< 1) + 2;
1244 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1246 struct upk_mips16 upk
;
1247 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1248 pc
= add_offset_16 (pc
, upk
.offset
);
1249 if ((insn
>> 10) & 0x01) /* Exchange mode */
1250 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1257 struct upk_mips16 upk
;
1259 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1260 reg
= read_signed_register (upk
.regx
);
1262 pc
+= (upk
.offset
<< 1) + 2;
1269 struct upk_mips16 upk
;
1271 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1272 reg
= read_signed_register (upk
.regx
);
1274 pc
+= (upk
.offset
<< 1) + 2;
1279 case 12: /* I8 Formats btez btnez */
1281 struct upk_mips16 upk
;
1283 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1284 /* upk.regx contains the opcode */
1285 reg
= read_signed_register (24); /* Test register is 24 */
1286 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1287 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1288 /* pc = add_offset_16(pc,upk.offset) ; */
1289 pc
+= (upk
.offset
<< 1) + 2;
1294 case 29: /* RR Formats JR, JALR, JALR-RA */
1296 struct upk_mips16 upk
;
1297 /* upk.fmt = rrtype; */
1302 upk
.regx
= (insn
>> 8) & 0x07;
1303 upk
.regy
= (insn
>> 5) & 0x07;
1311 break; /* Function return instruction */
1317 break; /* BOGUS Guess */
1319 pc
= read_signed_register (reg
);
1326 /* This is an instruction extension. Fetch the real instruction
1327 (which follows the extension) and decode things based on
1331 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1344 mips16_next_pc (CORE_ADDR pc
)
1346 unsigned int insn
= fetch_mips_16 (pc
);
1347 return extended_mips16_next_pc (pc
, 0, insn
);
1350 /* The mips_next_pc function supports single_step when the remote
1351 target monitor or stub is not developed enough to do a single_step.
1352 It works by decoding the current instruction and predicting where a
1353 branch will go. This isnt hard because all the data is available.
1354 The MIPS32 and MIPS16 variants are quite different */
1356 mips_next_pc (CORE_ADDR pc
)
1359 return mips16_next_pc (pc
);
1361 return mips32_next_pc (pc
);
1364 struct mips_frame_cache
1367 struct trad_frame_saved_reg
*saved_regs
;
1370 /* Set a register's saved stack address in temp_saved_regs. If an
1371 address has already been set for this register, do nothing; this
1372 way we will only recognize the first save of a given register in a
1375 For simplicity, save the address in both [0 .. NUM_REGS) and
1376 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1377 is used as it is only second range (the ABI instead of ISA
1378 registers) that comes into play when finding saved registers in a
1382 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1385 if (this_cache
!= NULL
1386 && this_cache
->saved_regs
[regnum
].addr
== -1)
1388 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
1389 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
1394 /* Fetch the immediate value from a MIPS16 instruction.
1395 If the previous instruction was an EXTEND, use it to extend
1396 the upper bits of the immediate value. This is a helper function
1397 for mips16_scan_prologue. */
1400 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1401 unsigned short inst
, /* current instruction */
1402 int nbits
, /* number of bits in imm field */
1403 int scale
, /* scale factor to be applied to imm */
1404 int is_signed
) /* is the imm field signed? */
1408 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1410 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1411 if (offset
& 0x8000) /* check for negative extend */
1412 offset
= 0 - (0x10000 - (offset
& 0xffff));
1413 return offset
| (inst
& 0x1f);
1417 int max_imm
= 1 << nbits
;
1418 int mask
= max_imm
- 1;
1419 int sign_bit
= max_imm
>> 1;
1421 offset
= inst
& mask
;
1422 if (is_signed
&& (offset
& sign_bit
))
1423 offset
= 0 - (max_imm
- offset
);
1424 return offset
* scale
;
1429 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1430 the associated FRAME_CACHE if not null.
1431 Return the address of the first instruction past the prologue. */
1434 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1435 struct frame_info
*next_frame
,
1436 struct mips_frame_cache
*this_cache
)
1439 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1441 long frame_offset
= 0; /* Size of stack frame. */
1442 long frame_adjust
= 0; /* Offset of FP from SP. */
1443 int frame_reg
= MIPS_SP_REGNUM
;
1444 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1445 unsigned inst
= 0; /* current instruction */
1446 unsigned entry_inst
= 0; /* the entry instruction */
1449 int extend_bytes
= 0;
1450 int prev_extend_bytes
;
1451 CORE_ADDR end_prologue_addr
= 0;
1453 /* Can be called when there's no process, and hence when there's no
1455 if (next_frame
!= NULL
)
1456 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1460 if (limit_pc
> start_pc
+ 200)
1461 limit_pc
= start_pc
+ 200;
1463 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1465 /* Save the previous instruction. If it's an EXTEND, we'll extract
1466 the immediate offset extension from it in mips16_get_imm. */
1469 /* Fetch and decode the instruction. */
1470 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1472 /* Normally we ignore extend instructions. However, if it is
1473 not followed by a valid prologue instruction, then this
1474 instruction is not part of the prologue either. We must
1475 remember in this case to adjust the end_prologue_addr back
1477 if ((inst
& 0xf800) == 0xf000) /* extend */
1479 extend_bytes
= MIPS_INSN16_SIZE
;
1483 prev_extend_bytes
= extend_bytes
;
1486 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1487 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1489 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1490 if (offset
< 0) /* negative stack adjustment? */
1491 frame_offset
-= offset
;
1493 /* Exit loop if a positive stack adjustment is found, which
1494 usually means that the stack cleanup code in the function
1495 epilogue is reached. */
1498 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1500 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1501 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1502 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1504 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1506 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1507 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1508 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1510 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1512 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1513 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1515 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1517 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1518 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1520 else if (inst
== 0x673d) /* move $s1, $sp */
1525 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1527 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1528 frame_addr
= sp
+ offset
;
1530 frame_adjust
= offset
;
1532 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1534 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1535 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1536 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1538 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1540 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1541 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1542 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1544 else if ((inst
& 0xf81f) == 0xe809
1545 && (inst
& 0x700) != 0x700) /* entry */
1546 entry_inst
= inst
; /* save for later processing */
1547 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1548 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1549 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1551 /* This instruction is part of the prologue, but we don't
1552 need to do anything special to handle it. */
1556 /* This instruction is not an instruction typically found
1557 in a prologue, so we must have reached the end of the
1559 if (end_prologue_addr
== 0)
1560 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1564 /* The entry instruction is typically the first instruction in a function,
1565 and it stores registers at offsets relative to the value of the old SP
1566 (before the prologue). But the value of the sp parameter to this
1567 function is the new SP (after the prologue has been executed). So we
1568 can't calculate those offsets until we've seen the entire prologue,
1569 and can calculate what the old SP must have been. */
1570 if (entry_inst
!= 0)
1572 int areg_count
= (entry_inst
>> 8) & 7;
1573 int sreg_count
= (entry_inst
>> 6) & 3;
1575 /* The entry instruction always subtracts 32 from the SP. */
1578 /* Now we can calculate what the SP must have been at the
1579 start of the function prologue. */
1582 /* Check if a0-a3 were saved in the caller's argument save area. */
1583 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1585 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1586 offset
+= mips_abi_regsize (current_gdbarch
);
1589 /* Check if the ra register was pushed on the stack. */
1591 if (entry_inst
& 0x20)
1593 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1594 offset
-= mips_abi_regsize (current_gdbarch
);
1597 /* Check if the s0 and s1 registers were pushed on the stack. */
1598 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1600 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1601 offset
-= mips_abi_regsize (current_gdbarch
);
1605 if (this_cache
!= NULL
)
1608 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1609 + frame_offset
- frame_adjust
);
1610 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1611 be able to get rid of the assignment below, evetually. But it's
1612 still needed for now. */
1613 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1614 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1617 /* If we didn't reach the end of the prologue when scanning the function
1618 instructions, then set end_prologue_addr to the address of the
1619 instruction immediately after the last one we scanned. */
1620 if (end_prologue_addr
== 0)
1621 end_prologue_addr
= cur_pc
;
1623 return end_prologue_addr
;
1626 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1627 Procedures that use the 32-bit instruction set are handled by the
1628 mips_insn32 unwinder. */
1630 static struct mips_frame_cache
*
1631 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1633 struct mips_frame_cache
*cache
;
1635 if ((*this_cache
) != NULL
)
1636 return (*this_cache
);
1637 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1638 (*this_cache
) = cache
;
1639 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1641 /* Analyze the function prologue. */
1643 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1644 CORE_ADDR start_addr
;
1646 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1647 if (start_addr
== 0)
1648 start_addr
= heuristic_proc_start (pc
);
1649 /* We can't analyze the prologue if we couldn't find the begining
1651 if (start_addr
== 0)
1654 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1657 /* SP_REGNUM, contains the value and not the address. */
1658 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1660 return (*this_cache
);
1664 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1665 struct frame_id
*this_id
)
1667 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1669 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1673 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1675 int regnum
, int *optimizedp
,
1676 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1677 int *realnump
, gdb_byte
*valuep
)
1679 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1681 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1682 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1685 static const struct frame_unwind mips_insn16_frame_unwind
=
1688 mips_insn16_frame_this_id
,
1689 mips_insn16_frame_prev_register
1692 static const struct frame_unwind
*
1693 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1695 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1696 if (mips_pc_is_mips16 (pc
))
1697 return &mips_insn16_frame_unwind
;
1702 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1705 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1710 static const struct frame_base mips_insn16_frame_base
=
1712 &mips_insn16_frame_unwind
,
1713 mips_insn16_frame_base_address
,
1714 mips_insn16_frame_base_address
,
1715 mips_insn16_frame_base_address
1718 static const struct frame_base
*
1719 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1721 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1722 return &mips_insn16_frame_base
;
1727 /* Mark all the registers as unset in the saved_regs array
1728 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1731 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1733 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1737 const int num_regs
= NUM_REGS
;
1740 for (i
= 0; i
< num_regs
; i
++)
1742 this_cache
->saved_regs
[i
].addr
= -1;
1747 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1748 the associated FRAME_CACHE if not null.
1749 Return the address of the first instruction past the prologue. */
1752 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1753 struct frame_info
*next_frame
,
1754 struct mips_frame_cache
*this_cache
)
1757 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1760 int frame_reg
= MIPS_SP_REGNUM
;
1762 CORE_ADDR end_prologue_addr
= 0;
1763 int seen_sp_adjust
= 0;
1764 int load_immediate_bytes
= 0;
1766 /* Can be called when there's no process, and hence when there's no
1768 if (next_frame
!= NULL
)
1769 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1773 if (limit_pc
> start_pc
+ 200)
1774 limit_pc
= start_pc
+ 200;
1779 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1781 unsigned long inst
, high_word
, low_word
;
1784 /* Fetch the instruction. */
1785 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1787 /* Save some code by pre-extracting some useful fields. */
1788 high_word
= (inst
>> 16) & 0xffff;
1789 low_word
= inst
& 0xffff;
1790 reg
= high_word
& 0x1f;
1792 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1793 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1794 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1796 if (low_word
& 0x8000) /* negative stack adjustment? */
1797 frame_offset
+= 0x10000 - low_word
;
1799 /* Exit loop if a positive stack adjustment is found, which
1800 usually means that the stack cleanup code in the function
1801 epilogue is reached. */
1805 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1807 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1809 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1811 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1812 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1814 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1816 /* Old gcc frame, r30 is virtual frame pointer. */
1817 if ((long) low_word
!= frame_offset
)
1818 frame_addr
= sp
+ low_word
;
1819 else if (frame_reg
== MIPS_SP_REGNUM
)
1821 unsigned alloca_adjust
;
1824 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
1825 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1826 if (alloca_adjust
> 0)
1828 /* FP > SP + frame_size. This may be because of
1829 an alloca or somethings similar. Fix sp to
1830 "pre-alloca" value, and try again. */
1831 sp
+= alloca_adjust
;
1832 /* Need to reset the status of all registers. Otherwise,
1833 we will hit a guard that prevents the new address
1834 for each register to be recomputed during the second
1836 reset_saved_regs (this_cache
);
1841 /* move $30,$sp. With different versions of gas this will be either
1842 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1843 Accept any one of these. */
1844 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1846 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1847 if (frame_reg
== MIPS_SP_REGNUM
)
1849 unsigned alloca_adjust
;
1852 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
1853 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1854 if (alloca_adjust
> 0)
1856 /* FP > SP + frame_size. This may be because of
1857 an alloca or somethings similar. Fix sp to
1858 "pre-alloca" value, and try again. */
1860 /* Need to reset the status of all registers. Otherwise,
1861 we will hit a guard that prevents the new address
1862 for each register to be recomputed during the second
1864 reset_saved_regs (this_cache
);
1869 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1871 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
1873 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1874 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1875 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1876 || high_word
== 0x3c1c /* lui $gp,n */
1877 || high_word
== 0x279c /* addiu $gp,$gp,n */
1878 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1879 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
1882 /* These instructions are part of the prologue, but we don't
1883 need to do anything special to handle them. */
1885 /* The instructions below load $at or $t0 with an immediate
1886 value in preparation for a stack adjustment via
1887 subu $sp,$sp,[$at,$t0]. These instructions could also
1888 initialize a local variable, so we accept them only before
1889 a stack adjustment instruction was seen. */
1890 else if (!seen_sp_adjust
1891 && (high_word
== 0x3c01 /* lui $at,n */
1892 || high_word
== 0x3c08 /* lui $t0,n */
1893 || high_word
== 0x3421 /* ori $at,$at,n */
1894 || high_word
== 0x3508 /* ori $t0,$t0,n */
1895 || high_word
== 0x3401 /* ori $at,$zero,n */
1896 || high_word
== 0x3408 /* ori $t0,$zero,n */
1899 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
1903 /* This instruction is not an instruction typically found
1904 in a prologue, so we must have reached the end of the
1906 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
1907 loop now? Why would we need to continue scanning the function
1909 if (end_prologue_addr
== 0)
1910 end_prologue_addr
= cur_pc
;
1914 if (this_cache
!= NULL
)
1917 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1919 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
1920 this assignment below, eventually. But it's still needed
1922 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1923 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1926 /* If we didn't reach the end of the prologue when scanning the function
1927 instructions, then set end_prologue_addr to the address of the
1928 instruction immediately after the last one we scanned. */
1929 /* brobecker/2004-10-10: I don't think this would ever happen, but
1930 we may as well be careful and do our best if we have a null
1931 end_prologue_addr. */
1932 if (end_prologue_addr
== 0)
1933 end_prologue_addr
= cur_pc
;
1935 /* In a frameless function, we might have incorrectly
1936 skipped some load immediate instructions. Undo the skipping
1937 if the load immediate was not followed by a stack adjustment. */
1938 if (load_immediate_bytes
&& !seen_sp_adjust
)
1939 end_prologue_addr
-= load_immediate_bytes
;
1941 return end_prologue_addr
;
1944 /* Heuristic unwinder for procedures using 32-bit instructions (covers
1945 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
1946 instructions (a.k.a. MIPS16) are handled by the mips_insn16
1949 static struct mips_frame_cache
*
1950 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1952 struct mips_frame_cache
*cache
;
1954 if ((*this_cache
) != NULL
)
1955 return (*this_cache
);
1957 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1958 (*this_cache
) = cache
;
1959 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1961 /* Analyze the function prologue. */
1963 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1964 CORE_ADDR start_addr
;
1966 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1967 if (start_addr
== 0)
1968 start_addr
= heuristic_proc_start (pc
);
1969 /* We can't analyze the prologue if we couldn't find the begining
1971 if (start_addr
== 0)
1974 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1977 /* SP_REGNUM, contains the value and not the address. */
1978 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1980 return (*this_cache
);
1984 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1985 struct frame_id
*this_id
)
1987 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1989 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1993 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
1995 int regnum
, int *optimizedp
,
1996 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1997 int *realnump
, gdb_byte
*valuep
)
1999 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2001 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2002 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2005 static const struct frame_unwind mips_insn32_frame_unwind
=
2008 mips_insn32_frame_this_id
,
2009 mips_insn32_frame_prev_register
2012 static const struct frame_unwind
*
2013 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2015 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2016 if (! mips_pc_is_mips16 (pc
))
2017 return &mips_insn32_frame_unwind
;
2022 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2025 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2030 static const struct frame_base mips_insn32_frame_base
=
2032 &mips_insn32_frame_unwind
,
2033 mips_insn32_frame_base_address
,
2034 mips_insn32_frame_base_address
,
2035 mips_insn32_frame_base_address
2038 static const struct frame_base
*
2039 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2041 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2042 return &mips_insn32_frame_base
;
2047 static struct trad_frame_cache
*
2048 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2051 CORE_ADDR start_addr
;
2052 CORE_ADDR stack_addr
;
2053 struct trad_frame_cache
*this_trad_cache
;
2055 if ((*this_cache
) != NULL
)
2056 return (*this_cache
);
2057 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2058 (*this_cache
) = this_trad_cache
;
2060 /* The return address is in the link register. */
2061 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, MIPS_RA_REGNUM
);
2063 /* Frame ID, since it's a frameless / stackless function, no stack
2064 space is allocated and SP on entry is the current SP. */
2065 pc
= frame_pc_unwind (next_frame
);
2066 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2067 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2068 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2070 /* Assume that the frame's base is the same as the
2072 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2074 return this_trad_cache
;
2078 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2079 struct frame_id
*this_id
)
2081 struct trad_frame_cache
*this_trad_cache
2082 = mips_stub_frame_cache (next_frame
, this_cache
);
2083 trad_frame_get_id (this_trad_cache
, this_id
);
2087 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2089 int regnum
, int *optimizedp
,
2090 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2091 int *realnump
, gdb_byte
*valuep
)
2093 struct trad_frame_cache
*this_trad_cache
2094 = mips_stub_frame_cache (next_frame
, this_cache
);
2095 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2096 lvalp
, addrp
, realnump
, valuep
);
2099 static const struct frame_unwind mips_stub_frame_unwind
=
2102 mips_stub_frame_this_id
,
2103 mips_stub_frame_prev_register
2106 static const struct frame_unwind
*
2107 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2109 struct obj_section
*s
;
2110 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2112 if (in_plt_section (pc
, NULL
))
2113 return &mips_stub_frame_unwind
;
2115 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2116 s
= find_pc_section (pc
);
2119 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2120 ".MIPS.stubs") == 0)
2121 return &mips_stub_frame_unwind
;
2127 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2130 struct trad_frame_cache
*this_trad_cache
2131 = mips_stub_frame_cache (next_frame
, this_cache
);
2132 return trad_frame_get_this_base (this_trad_cache
);
2135 static const struct frame_base mips_stub_frame_base
=
2137 &mips_stub_frame_unwind
,
2138 mips_stub_frame_base_address
,
2139 mips_stub_frame_base_address
,
2140 mips_stub_frame_base_address
2143 static const struct frame_base
*
2144 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2146 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2147 return &mips_stub_frame_base
;
2153 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2155 /* Always a pseudo. */
2156 gdb_assert (regno
>= NUM_REGS
);
2160 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2164 return frame_unwind_register_signed (fi
, regno
);
2168 /* mips_addr_bits_remove - remove useless address bits */
2171 mips_addr_bits_remove (CORE_ADDR addr
)
2173 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2174 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2175 /* This hack is a work-around for existing boards using PMON, the
2176 simulator, and any other 64-bit targets that doesn't have true
2177 64-bit addressing. On these targets, the upper 32 bits of
2178 addresses are ignored by the hardware. Thus, the PC or SP are
2179 likely to have been sign extended to all 1s by instruction
2180 sequences that load 32-bit addresses. For example, a typical
2181 piece of code that loads an address is this:
2183 lui $r2, <upper 16 bits>
2184 ori $r2, <lower 16 bits>
2186 But the lui sign-extends the value such that the upper 32 bits
2187 may be all 1s. The workaround is simply to mask off these
2188 bits. In the future, gcc may be changed to support true 64-bit
2189 addressing, and this masking will have to be disabled. */
2190 return addr
&= 0xffffffffUL
;
2195 /* mips_software_single_step() is called just before we want to resume
2196 the inferior, if we want to single-step it but there is no hardware
2197 or kernel single-step support (MIPS on GNU/Linux for example). We find
2198 the target of the coming instruction and breakpoint it.
2200 single_step is also called just after the inferior stops. If we had
2201 set up a simulated single-step, we undo our damage. */
2204 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2206 CORE_ADDR pc
, next_pc
;
2208 if (insert_breakpoints_p
)
2210 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2211 next_pc
= mips_next_pc (pc
);
2213 insert_single_step_breakpoint (next_pc
);
2216 remove_single_step_breakpoints ();
2219 /* Test whether the PC points to the return instruction at the
2220 end of a function. */
2223 mips_about_to_return (CORE_ADDR pc
)
2225 if (mips_pc_is_mips16 (pc
))
2226 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2227 generates a "jr $ra"; other times it generates code to load
2228 the return address from the stack to an accessible register (such
2229 as $a3), then a "jr" using that register. This second case
2230 is almost impossible to distinguish from an indirect jump
2231 used for switch statements, so we don't even try. */
2232 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2234 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2238 /* This fencepost looks highly suspicious to me. Removing it also
2239 seems suspicious as it could affect remote debugging across serial
2243 heuristic_proc_start (CORE_ADDR pc
)
2250 pc
= ADDR_BITS_REMOVE (pc
);
2252 fence
= start_pc
- heuristic_fence_post
;
2256 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2257 fence
= VM_MIN_ADDRESS
;
2259 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2261 /* search back for previous return */
2262 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2263 if (start_pc
< fence
)
2265 /* It's not clear to me why we reach this point when
2266 stop_soon, but with this test, at least we
2267 don't print out warnings for every child forked (eg, on
2268 decstation). 22apr93 rich@cygnus.com. */
2269 if (stop_soon
== NO_STOP_QUIETLY
)
2271 static int blurb_printed
= 0;
2273 warning (_("GDB can't find the start of the function at 0x%s."),
2278 /* This actually happens frequently in embedded
2279 development, when you first connect to a board
2280 and your stack pointer and pc are nowhere in
2281 particular. This message needs to give people
2282 in that situation enough information to
2283 determine that it's no big deal. */
2284 printf_filtered ("\n\
2285 GDB is unable to find the start of the function at 0x%s\n\
2286 and thus can't determine the size of that function's stack frame.\n\
2287 This means that GDB may be unable to access that stack frame, or\n\
2288 the frames below it.\n\
2289 This problem is most likely caused by an invalid program counter or\n\
2291 However, if you think GDB should simply search farther back\n\
2292 from 0x%s for code which looks like the beginning of a\n\
2293 function, you can increase the range of the search using the `set\n\
2294 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2301 else if (mips_pc_is_mips16 (start_pc
))
2303 unsigned short inst
;
2305 /* On MIPS16, any one of the following is likely to be the
2306 start of a function:
2310 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2311 inst
= mips_fetch_instruction (start_pc
);
2312 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2313 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2314 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2315 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2317 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2318 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2323 else if (mips_about_to_return (start_pc
))
2325 /* Skip return and its delay slot. */
2326 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2333 struct mips_objfile_private
2339 /* According to the current ABI, should the type be passed in a
2340 floating-point register (assuming that there is space)? When there
2341 is no FPU, FP are not even considered as possible candidates for
2342 FP registers and, consequently this returns false - forces FP
2343 arguments into integer registers. */
2346 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2348 return ((typecode
== TYPE_CODE_FLT
2350 && (typecode
== TYPE_CODE_STRUCT
2351 || typecode
== TYPE_CODE_UNION
)
2352 && TYPE_NFIELDS (arg_type
) == 1
2353 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2355 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2358 /* On o32, argument passing in GPRs depends on the alignment of the type being
2359 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2362 mips_type_needs_double_align (struct type
*type
)
2364 enum type_code typecode
= TYPE_CODE (type
);
2366 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2368 else if (typecode
== TYPE_CODE_STRUCT
)
2370 if (TYPE_NFIELDS (type
) < 1)
2372 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2374 else if (typecode
== TYPE_CODE_UNION
)
2378 n
= TYPE_NFIELDS (type
);
2379 for (i
= 0; i
< n
; i
++)
2380 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2387 /* Adjust the address downward (direction of stack growth) so that it
2388 is correctly aligned for a new stack frame. */
2390 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2392 return align_down (addr
, 16);
2396 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2397 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2398 int nargs
, struct value
**args
, CORE_ADDR sp
,
2399 int struct_return
, CORE_ADDR struct_addr
)
2405 int stack_offset
= 0;
2406 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2407 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2409 /* For shared libraries, "t9" needs to point at the function
2411 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2413 /* Set the return address register to point to the entry point of
2414 the program, where a breakpoint lies in wait. */
2415 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2417 /* First ensure that the stack and structure return address (if any)
2418 are properly aligned. The stack has to be at least 64-bit
2419 aligned even on 32-bit machines, because doubles must be 64-bit
2420 aligned. For n32 and n64, stack frames need to be 128-bit
2421 aligned, so we round to this widest known alignment. */
2423 sp
= align_down (sp
, 16);
2424 struct_addr
= align_down (struct_addr
, 16);
2426 /* Now make space on the stack for the args. We allocate more
2427 than necessary for EABI, because the first few arguments are
2428 passed in registers, but that's OK. */
2429 for (argnum
= 0; argnum
< nargs
; argnum
++)
2430 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])),
2431 mips_stack_argsize (gdbarch
));
2432 sp
-= align_up (len
, 16);
2435 fprintf_unfiltered (gdb_stdlog
,
2436 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2437 paddr_nz (sp
), (long) align_up (len
, 16));
2439 /* Initialize the integer and float register pointers. */
2440 argreg
= MIPS_A0_REGNUM
;
2441 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2443 /* The struct_return pointer occupies the first parameter-passing reg. */
2447 fprintf_unfiltered (gdb_stdlog
,
2448 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2449 argreg
, paddr_nz (struct_addr
));
2450 write_register (argreg
++, struct_addr
);
2453 /* Now load as many as possible of the first arguments into
2454 registers, and push the rest onto the stack. Loop thru args
2455 from first to last. */
2456 for (argnum
= 0; argnum
< nargs
; argnum
++)
2458 const gdb_byte
*val
;
2459 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2460 struct value
*arg
= args
[argnum
];
2461 struct type
*arg_type
= check_typedef (value_type (arg
));
2462 int len
= TYPE_LENGTH (arg_type
);
2463 enum type_code typecode
= TYPE_CODE (arg_type
);
2466 fprintf_unfiltered (gdb_stdlog
,
2467 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2468 argnum
+ 1, len
, (int) typecode
);
2470 /* The EABI passes structures that do not fit in a register by
2472 if (len
> mips_abi_regsize (gdbarch
)
2473 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2475 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
2476 VALUE_ADDRESS (arg
));
2477 typecode
= TYPE_CODE_PTR
;
2478 len
= mips_abi_regsize (gdbarch
);
2481 fprintf_unfiltered (gdb_stdlog
, " push");
2484 val
= value_contents (arg
);
2486 /* 32-bit ABIs always start floating point arguments in an
2487 even-numbered floating point register. Round the FP register
2488 up before the check to see if there are any FP registers
2489 left. Non MIPS_EABI targets also pass the FP in the integer
2490 registers so also round up normal registers. */
2491 if (mips_abi_regsize (gdbarch
) < 8
2492 && fp_register_arg_p (typecode
, arg_type
))
2494 if ((float_argreg
& 1))
2498 /* Floating point arguments passed in registers have to be
2499 treated specially. On 32-bit architectures, doubles
2500 are passed in register pairs; the even register gets
2501 the low word, and the odd register gets the high word.
2502 On non-EABI processors, the first two floating point arguments are
2503 also copied to general registers, because MIPS16 functions
2504 don't use float registers for arguments. This duplication of
2505 arguments in general registers can't hurt non-MIPS16 functions
2506 because those registers are normally skipped. */
2507 /* MIPS_EABI squeezes a struct that contains a single floating
2508 point value into an FP register instead of pushing it onto the
2510 if (fp_register_arg_p (typecode
, arg_type
)
2511 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2513 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
2515 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2516 unsigned long regval
;
2518 /* Write the low word of the double to the even register(s). */
2519 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2521 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2522 float_argreg
, phex (regval
, 4));
2523 write_register (float_argreg
++, regval
);
2525 /* Write the high word of the double to the odd register(s). */
2526 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2528 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2529 float_argreg
, phex (regval
, 4));
2530 write_register (float_argreg
++, regval
);
2534 /* This is a floating point value that fits entirely
2535 in a single register. */
2536 /* On 32 bit ABI's the float_argreg is further adjusted
2537 above to ensure that it is even register aligned. */
2538 LONGEST regval
= extract_unsigned_integer (val
, len
);
2540 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2541 float_argreg
, phex (regval
, len
));
2542 write_register (float_argreg
++, regval
);
2547 /* Copy the argument to general registers or the stack in
2548 register-sized pieces. Large arguments are split between
2549 registers and stack. */
2550 /* Note: structs whose size is not a multiple of
2551 mips_abi_regsize() are treated specially: Irix cc passes
2552 them in registers where gcc sometimes puts them on the
2553 stack. For maximum compatibility, we will put them in
2555 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
2556 && (len
% mips_abi_regsize (gdbarch
) != 0));
2558 /* Note: Floating-point values that didn't fit into an FP
2559 register are only written to memory. */
2562 /* Remember if the argument was written to the stack. */
2563 int stack_used_p
= 0;
2564 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
2565 ? len
: mips_abi_regsize (gdbarch
));
2568 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2571 /* Write this portion of the argument to the stack. */
2572 if (argreg
> MIPS_LAST_ARG_REGNUM
2574 || fp_register_arg_p (typecode
, arg_type
))
2576 /* Should shorter than int integer values be
2577 promoted to int before being stored? */
2578 int longword_offset
= 0;
2581 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2583 if (mips_stack_argsize (gdbarch
) == 8
2584 && (typecode
== TYPE_CODE_INT
2585 || typecode
== TYPE_CODE_PTR
2586 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2587 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2588 else if ((typecode
== TYPE_CODE_STRUCT
2589 || typecode
== TYPE_CODE_UNION
)
2590 && (TYPE_LENGTH (arg_type
)
2591 < mips_stack_argsize (gdbarch
)))
2592 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2597 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2598 paddr_nz (stack_offset
));
2599 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2600 paddr_nz (longword_offset
));
2603 addr
= sp
+ stack_offset
+ longword_offset
;
2608 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2610 for (i
= 0; i
< partial_len
; i
++)
2612 fprintf_unfiltered (gdb_stdlog
, "%02x",
2616 write_memory (addr
, val
, partial_len
);
2619 /* Note!!! This is NOT an else clause. Odd sized
2620 structs may go thru BOTH paths. Floating point
2621 arguments will not. */
2622 /* Write this portion of the argument to a general
2623 purpose register. */
2624 if (argreg
<= MIPS_LAST_ARG_REGNUM
2625 && !fp_register_arg_p (typecode
, arg_type
))
2628 extract_unsigned_integer (val
, partial_len
);
2631 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2634 mips_abi_regsize (gdbarch
)));
2635 write_register (argreg
, regval
);
2642 /* Compute the the offset into the stack at which we
2643 will copy the next parameter.
2645 In the new EABI (and the NABI32), the stack_offset
2646 only needs to be adjusted when it has been used. */
2649 stack_offset
+= align_up (partial_len
,
2650 mips_stack_argsize (gdbarch
));
2654 fprintf_unfiltered (gdb_stdlog
, "\n");
2657 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2659 /* Return adjusted stack pointer. */
2663 /* Determine the return value convention being used. */
2665 static enum return_value_convention
2666 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2667 struct type
*type
, struct regcache
*regcache
,
2668 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2670 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2671 return RETURN_VALUE_STRUCT_CONVENTION
;
2673 memset (readbuf
, 0, TYPE_LENGTH (type
));
2674 return RETURN_VALUE_REGISTER_CONVENTION
;
2678 /* N32/N64 ABI stuff. */
2681 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2682 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2683 int nargs
, struct value
**args
, CORE_ADDR sp
,
2684 int struct_return
, CORE_ADDR struct_addr
)
2690 int stack_offset
= 0;
2691 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2692 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2694 /* For shared libraries, "t9" needs to point at the function
2696 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2698 /* Set the return address register to point to the entry point of
2699 the program, where a breakpoint lies in wait. */
2700 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2702 /* First ensure that the stack and structure return address (if any)
2703 are properly aligned. The stack has to be at least 64-bit
2704 aligned even on 32-bit machines, because doubles must be 64-bit
2705 aligned. For n32 and n64, stack frames need to be 128-bit
2706 aligned, so we round to this widest known alignment. */
2708 sp
= align_down (sp
, 16);
2709 struct_addr
= align_down (struct_addr
, 16);
2711 /* Now make space on the stack for the args. */
2712 for (argnum
= 0; argnum
< nargs
; argnum
++)
2713 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])),
2714 mips_stack_argsize (gdbarch
));
2715 sp
-= align_up (len
, 16);
2718 fprintf_unfiltered (gdb_stdlog
,
2719 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2720 paddr_nz (sp
), (long) align_up (len
, 16));
2722 /* Initialize the integer and float register pointers. */
2723 argreg
= MIPS_A0_REGNUM
;
2724 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2726 /* The struct_return pointer occupies the first parameter-passing reg. */
2730 fprintf_unfiltered (gdb_stdlog
,
2731 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2732 argreg
, paddr_nz (struct_addr
));
2733 write_register (argreg
++, struct_addr
);
2736 /* Now load as many as possible of the first arguments into
2737 registers, and push the rest onto the stack. Loop thru args
2738 from first to last. */
2739 for (argnum
= 0; argnum
< nargs
; argnum
++)
2741 const gdb_byte
*val
;
2742 struct value
*arg
= args
[argnum
];
2743 struct type
*arg_type
= check_typedef (value_type (arg
));
2744 int len
= TYPE_LENGTH (arg_type
);
2745 enum type_code typecode
= TYPE_CODE (arg_type
);
2748 fprintf_unfiltered (gdb_stdlog
,
2749 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2750 argnum
+ 1, len
, (int) typecode
);
2752 val
= value_contents (arg
);
2754 if (fp_register_arg_p (typecode
, arg_type
)
2755 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2757 /* This is a floating point value that fits entirely
2758 in a single register. */
2759 /* On 32 bit ABI's the float_argreg is further adjusted
2760 above to ensure that it is even register aligned. */
2761 LONGEST regval
= extract_unsigned_integer (val
, len
);
2763 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2764 float_argreg
, phex (regval
, len
));
2765 write_register (float_argreg
++, regval
);
2768 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2769 argreg
, phex (regval
, len
));
2770 write_register (argreg
, regval
);
2775 /* Copy the argument to general registers or the stack in
2776 register-sized pieces. Large arguments are split between
2777 registers and stack. */
2778 /* Note: structs whose size is not a multiple of
2779 mips_abi_regsize() are treated specially: Irix cc passes
2780 them in registers where gcc sometimes puts them on the
2781 stack. For maximum compatibility, we will put them in
2783 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
2784 && (len
% mips_abi_regsize (gdbarch
) != 0));
2785 /* Note: Floating-point values that didn't fit into an FP
2786 register are only written to memory. */
2789 /* Rememer if the argument was written to the stack. */
2790 int stack_used_p
= 0;
2791 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
2792 ? len
: mips_abi_regsize (gdbarch
));
2795 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2798 /* Write this portion of the argument to the stack. */
2799 if (argreg
> MIPS_LAST_ARG_REGNUM
2801 || fp_register_arg_p (typecode
, arg_type
))
2803 /* Should shorter than int integer values be
2804 promoted to int before being stored? */
2805 int longword_offset
= 0;
2808 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2810 if (mips_stack_argsize (gdbarch
) == 8
2811 && (typecode
== TYPE_CODE_INT
2812 || typecode
== TYPE_CODE_PTR
2813 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2814 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2819 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2820 paddr_nz (stack_offset
));
2821 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2822 paddr_nz (longword_offset
));
2825 addr
= sp
+ stack_offset
+ longword_offset
;
2830 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2832 for (i
= 0; i
< partial_len
; i
++)
2834 fprintf_unfiltered (gdb_stdlog
, "%02x",
2838 write_memory (addr
, val
, partial_len
);
2841 /* Note!!! This is NOT an else clause. Odd sized
2842 structs may go thru BOTH paths. Floating point
2843 arguments will not. */
2844 /* Write this portion of the argument to a general
2845 purpose register. */
2846 if (argreg
<= MIPS_LAST_ARG_REGNUM
2847 && !fp_register_arg_p (typecode
, arg_type
))
2850 extract_unsigned_integer (val
, partial_len
);
2852 /* A non-floating-point argument being passed in a
2853 general register. If a struct or union, and if
2854 the remaining length is smaller than the register
2855 size, we have to adjust the register value on
2858 It does not seem to be necessary to do the
2859 same for integral types.
2861 cagney/2001-07-23: gdb/179: Also, GCC, when
2862 outputting LE O32 with sizeof (struct) <
2863 mips_abi_regsize(), generates a left shift as
2864 part of storing the argument in a register a
2865 register (the left shift isn't generated when
2866 sizeof (struct) >= mips_abi_regsize()). Since
2867 it is quite possible that this is GCC
2868 contradicting the LE/O32 ABI, GDB has not been
2869 adjusted to accommodate this. Either someone
2870 needs to demonstrate that the LE/O32 ABI
2871 specifies such a left shift OR this new ABI gets
2872 identified as such and GDB gets tweaked
2875 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2876 && partial_len
< mips_abi_regsize (gdbarch
)
2877 && (typecode
== TYPE_CODE_STRUCT
||
2878 typecode
== TYPE_CODE_UNION
))
2879 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
2883 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2886 mips_abi_regsize (gdbarch
)));
2887 write_register (argreg
, regval
);
2894 /* Compute the the offset into the stack at which we
2895 will copy the next parameter.
2897 In N32 (N64?), the stack_offset only needs to be
2898 adjusted when it has been used. */
2901 stack_offset
+= align_up (partial_len
,
2902 mips_stack_argsize (gdbarch
));
2906 fprintf_unfiltered (gdb_stdlog
, "\n");
2909 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2911 /* Return adjusted stack pointer. */
2915 static enum return_value_convention
2916 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
2917 struct type
*type
, struct regcache
*regcache
,
2918 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2920 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2921 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2922 || TYPE_CODE (type
) == TYPE_CODE_UNION
2923 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
2924 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2925 return RETURN_VALUE_STRUCT_CONVENTION
;
2926 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2927 && TYPE_LENGTH (type
) == 16
2928 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2930 /* A 128-bit floating-point value fills both $f0 and $f2. The
2931 two registers are used in the same as memory order, so the
2932 eight bytes with the lower memory address are in $f0. */
2934 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
2935 mips_xfer_register (regcache
,
2936 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
2937 8, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
2938 mips_xfer_register (regcache
,
2939 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 2,
2940 8, TARGET_BYTE_ORDER
, readbuf
? readbuf
+ 8 : readbuf
,
2941 writebuf
? writebuf
+ 8 : writebuf
, 0);
2942 return RETURN_VALUE_REGISTER_CONVENTION
;
2944 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2945 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2947 /* A floating-point value belongs in the least significant part
2950 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
2951 mips_xfer_register (regcache
,
2952 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
2954 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
2955 return RETURN_VALUE_REGISTER_CONVENTION
;
2957 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2958 && TYPE_NFIELDS (type
) <= 2
2959 && TYPE_NFIELDS (type
) >= 1
2960 && ((TYPE_NFIELDS (type
) == 1
2961 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2963 || (TYPE_NFIELDS (type
) == 2
2964 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2966 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
2968 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2970 /* A struct that contains one or two floats. Each value is part
2971 in the least significant part of their floating point
2975 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
2976 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
2978 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
2981 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
2983 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
2984 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
2985 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
2987 return RETURN_VALUE_REGISTER_CONVENTION
;
2989 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2990 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2992 /* A structure or union. Extract the left justified value,
2993 regardless of the byte order. I.e. DO NOT USE
2997 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
2998 offset
< TYPE_LENGTH (type
);
2999 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3001 int xfer
= register_size (current_gdbarch
, regnum
);
3002 if (offset
+ xfer
> TYPE_LENGTH (type
))
3003 xfer
= TYPE_LENGTH (type
) - offset
;
3005 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3006 offset
, xfer
, regnum
);
3007 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3008 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3010 return RETURN_VALUE_REGISTER_CONVENTION
;
3014 /* A scalar extract each part but least-significant-byte
3018 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3019 offset
< TYPE_LENGTH (type
);
3020 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3022 int xfer
= register_size (current_gdbarch
, regnum
);
3023 if (offset
+ xfer
> TYPE_LENGTH (type
))
3024 xfer
= TYPE_LENGTH (type
) - offset
;
3026 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3027 offset
, xfer
, regnum
);
3028 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3029 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3031 return RETURN_VALUE_REGISTER_CONVENTION
;
3035 /* O32 ABI stuff. */
3038 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3039 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3040 int nargs
, struct value
**args
, CORE_ADDR sp
,
3041 int struct_return
, CORE_ADDR struct_addr
)
3047 int stack_offset
= 0;
3048 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3049 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3051 /* For shared libraries, "t9" needs to point at the function
3053 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3055 /* Set the return address register to point to the entry point of
3056 the program, where a breakpoint lies in wait. */
3057 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3059 /* First ensure that the stack and structure return address (if any)
3060 are properly aligned. The stack has to be at least 64-bit
3061 aligned even on 32-bit machines, because doubles must be 64-bit
3062 aligned. For n32 and n64, stack frames need to be 128-bit
3063 aligned, so we round to this widest known alignment. */
3065 sp
= align_down (sp
, 16);
3066 struct_addr
= align_down (struct_addr
, 16);
3068 /* Now make space on the stack for the args. */
3069 for (argnum
= 0; argnum
< nargs
; argnum
++)
3070 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])),
3071 mips_stack_argsize (gdbarch
));
3072 sp
-= align_up (len
, 16);
3075 fprintf_unfiltered (gdb_stdlog
,
3076 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3077 paddr_nz (sp
), (long) align_up (len
, 16));
3079 /* Initialize the integer and float register pointers. */
3080 argreg
= MIPS_A0_REGNUM
;
3081 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3083 /* The struct_return pointer occupies the first parameter-passing reg. */
3087 fprintf_unfiltered (gdb_stdlog
,
3088 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3089 argreg
, paddr_nz (struct_addr
));
3090 write_register (argreg
++, struct_addr
);
3091 stack_offset
+= mips_stack_argsize (gdbarch
);
3094 /* Now load as many as possible of the first arguments into
3095 registers, and push the rest onto the stack. Loop thru args
3096 from first to last. */
3097 for (argnum
= 0; argnum
< nargs
; argnum
++)
3099 const gdb_byte
*val
;
3100 struct value
*arg
= args
[argnum
];
3101 struct type
*arg_type
= check_typedef (value_type (arg
));
3102 int len
= TYPE_LENGTH (arg_type
);
3103 enum type_code typecode
= TYPE_CODE (arg_type
);
3106 fprintf_unfiltered (gdb_stdlog
,
3107 "mips_o32_push_dummy_call: %d len=%d type=%d",
3108 argnum
+ 1, len
, (int) typecode
);
3110 val
= value_contents (arg
);
3112 /* 32-bit ABIs always start floating point arguments in an
3113 even-numbered floating point register. Round the FP register
3114 up before the check to see if there are any FP registers
3115 left. O32/O64 targets also pass the FP in the integer
3116 registers so also round up normal registers. */
3117 if (mips_abi_regsize (gdbarch
) < 8
3118 && fp_register_arg_p (typecode
, arg_type
))
3120 if ((float_argreg
& 1))
3124 /* Floating point arguments passed in registers have to be
3125 treated specially. On 32-bit architectures, doubles
3126 are passed in register pairs; the even register gets
3127 the low word, and the odd register gets the high word.
3128 On O32/O64, the first two floating point arguments are
3129 also copied to general registers, because MIPS16 functions
3130 don't use float registers for arguments. This duplication of
3131 arguments in general registers can't hurt non-MIPS16 functions
3132 because those registers are normally skipped. */
3134 if (fp_register_arg_p (typecode
, arg_type
)
3135 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3137 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3139 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3140 unsigned long regval
;
3142 /* Write the low word of the double to the even register(s). */
3143 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3145 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3146 float_argreg
, phex (regval
, 4));
3147 write_register (float_argreg
++, regval
);
3149 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3150 argreg
, phex (regval
, 4));
3151 write_register (argreg
++, regval
);
3153 /* Write the high word of the double to the odd register(s). */
3154 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3156 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3157 float_argreg
, phex (regval
, 4));
3158 write_register (float_argreg
++, regval
);
3161 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3162 argreg
, phex (regval
, 4));
3163 write_register (argreg
++, regval
);
3167 /* This is a floating point value that fits entirely
3168 in a single register. */
3169 /* On 32 bit ABI's the float_argreg is further adjusted
3170 above to ensure that it is even register aligned. */
3171 LONGEST regval
= extract_unsigned_integer (val
, len
);
3173 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3174 float_argreg
, phex (regval
, len
));
3175 write_register (float_argreg
++, regval
);
3176 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3177 registers for each argument. The below is (my
3178 guess) to ensure that the corresponding integer
3179 register has reserved the same space. */
3181 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3182 argreg
, phex (regval
, len
));
3183 write_register (argreg
, regval
);
3184 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3186 /* Reserve space for the FP register. */
3187 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3191 /* Copy the argument to general registers or the stack in
3192 register-sized pieces. Large arguments are split between
3193 registers and stack. */
3194 /* Note: structs whose size is not a multiple of
3195 mips_abi_regsize() are treated specially: Irix cc passes
3196 them in registers where gcc sometimes puts them on the
3197 stack. For maximum compatibility, we will put them in
3199 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3200 && (len
% mips_abi_regsize (gdbarch
) != 0));
3201 /* Structures should be aligned to eight bytes (even arg registers)
3202 on MIPS_ABI_O32, if their first member has double precision. */
3203 if (mips_abi_regsize (gdbarch
) < 8
3204 && mips_type_needs_double_align (arg_type
))
3209 /* Note: Floating-point values that didn't fit into an FP
3210 register are only written to memory. */
3213 /* Remember if the argument was written to the stack. */
3214 int stack_used_p
= 0;
3215 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3216 ? len
: mips_abi_regsize (gdbarch
));
3219 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3222 /* Write this portion of the argument to the stack. */
3223 if (argreg
> MIPS_LAST_ARG_REGNUM
3225 || fp_register_arg_p (typecode
, arg_type
))
3227 /* Should shorter than int integer values be
3228 promoted to int before being stored? */
3229 int longword_offset
= 0;
3232 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3234 if (mips_stack_argsize (gdbarch
) == 8
3235 && (typecode
== TYPE_CODE_INT
3236 || typecode
== TYPE_CODE_PTR
3237 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3238 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3243 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3244 paddr_nz (stack_offset
));
3245 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3246 paddr_nz (longword_offset
));
3249 addr
= sp
+ stack_offset
+ longword_offset
;
3254 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3256 for (i
= 0; i
< partial_len
; i
++)
3258 fprintf_unfiltered (gdb_stdlog
, "%02x",
3262 write_memory (addr
, val
, partial_len
);
3265 /* Note!!! This is NOT an else clause. Odd sized
3266 structs may go thru BOTH paths. Floating point
3267 arguments will not. */
3268 /* Write this portion of the argument to a general
3269 purpose register. */
3270 if (argreg
<= MIPS_LAST_ARG_REGNUM
3271 && !fp_register_arg_p (typecode
, arg_type
))
3273 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3274 /* Value may need to be sign extended, because
3275 mips_isa_regsize() != mips_abi_regsize(). */
3277 /* A non-floating-point argument being passed in a
3278 general register. If a struct or union, and if
3279 the remaining length is smaller than the register
3280 size, we have to adjust the register value on
3283 It does not seem to be necessary to do the
3284 same for integral types.
3286 Also don't do this adjustment on O64 binaries.
3288 cagney/2001-07-23: gdb/179: Also, GCC, when
3289 outputting LE O32 with sizeof (struct) <
3290 mips_abi_regsize(), generates a left shift as
3291 part of storing the argument in a register a
3292 register (the left shift isn't generated when
3293 sizeof (struct) >= mips_abi_regsize()). Since
3294 it is quite possible that this is GCC
3295 contradicting the LE/O32 ABI, GDB has not been
3296 adjusted to accommodate this. Either someone
3297 needs to demonstrate that the LE/O32 ABI
3298 specifies such a left shift OR this new ABI gets
3299 identified as such and GDB gets tweaked
3302 if (mips_abi_regsize (gdbarch
) < 8
3303 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3304 && partial_len
< mips_abi_regsize (gdbarch
)
3305 && (typecode
== TYPE_CODE_STRUCT
||
3306 typecode
== TYPE_CODE_UNION
))
3307 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3311 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3314 mips_abi_regsize (gdbarch
)));
3315 write_register (argreg
, regval
);
3318 /* Prevent subsequent floating point arguments from
3319 being passed in floating point registers. */
3320 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3326 /* Compute the the offset into the stack at which we
3327 will copy the next parameter.
3329 In older ABIs, the caller reserved space for
3330 registers that contained arguments. This was loosely
3331 refered to as their "home". Consequently, space is
3332 always allocated. */
3334 stack_offset
+= align_up (partial_len
,
3335 mips_stack_argsize (gdbarch
));
3339 fprintf_unfiltered (gdb_stdlog
, "\n");
3342 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3344 /* Return adjusted stack pointer. */
3348 static enum return_value_convention
3349 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3350 struct regcache
*regcache
,
3351 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3353 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3355 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3356 || TYPE_CODE (type
) == TYPE_CODE_UNION
3357 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3358 return RETURN_VALUE_STRUCT_CONVENTION
;
3359 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3360 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3362 /* A single-precision floating-point value. It fits in the
3363 least significant part of FP0. */
3365 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3366 mips_xfer_register (regcache
,
3367 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3369 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3370 return RETURN_VALUE_REGISTER_CONVENTION
;
3372 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3373 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3375 /* A double-precision floating-point value. The most
3376 significant part goes in FP1, and the least significant in
3379 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3380 switch (TARGET_BYTE_ORDER
)
3382 case BFD_ENDIAN_LITTLE
:
3383 mips_xfer_register (regcache
,
3384 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3385 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3386 mips_xfer_register (regcache
,
3387 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3388 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3390 case BFD_ENDIAN_BIG
:
3391 mips_xfer_register (regcache
,
3392 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3393 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3394 mips_xfer_register (regcache
,
3395 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3396 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3399 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3401 return RETURN_VALUE_REGISTER_CONVENTION
;
3404 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3405 && TYPE_NFIELDS (type
) <= 2
3406 && TYPE_NFIELDS (type
) >= 1
3407 && ((TYPE_NFIELDS (type
) == 1
3408 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3410 || (TYPE_NFIELDS (type
) == 2
3411 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3413 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3415 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3417 /* A struct that contains one or two floats. Each value is part
3418 in the least significant part of their floating point
3420 gdb_byte reg
[MAX_REGISTER_SIZE
];
3423 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3424 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3426 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3429 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3431 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3432 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3433 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3435 return RETURN_VALUE_REGISTER_CONVENTION
;
3439 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3440 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3442 /* A structure or union. Extract the left justified value,
3443 regardless of the byte order. I.e. DO NOT USE
3447 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3448 offset
< TYPE_LENGTH (type
);
3449 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3451 int xfer
= register_size (current_gdbarch
, regnum
);
3452 if (offset
+ xfer
> TYPE_LENGTH (type
))
3453 xfer
= TYPE_LENGTH (type
) - offset
;
3455 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3456 offset
, xfer
, regnum
);
3457 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3458 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3460 return RETURN_VALUE_REGISTER_CONVENTION
;
3465 /* A scalar extract each part but least-significant-byte
3466 justified. o32 thinks registers are 4 byte, regardless of
3467 the ISA. mips_stack_argsize controls this. */
3470 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3471 offset
< TYPE_LENGTH (type
);
3472 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
3474 int xfer
= mips_stack_argsize (gdbarch
);
3475 if (offset
+ xfer
> TYPE_LENGTH (type
))
3476 xfer
= TYPE_LENGTH (type
) - offset
;
3478 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3479 offset
, xfer
, regnum
);
3480 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3481 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3483 return RETURN_VALUE_REGISTER_CONVENTION
;
3487 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3491 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3492 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3494 struct value
**args
, CORE_ADDR sp
,
3495 int struct_return
, CORE_ADDR struct_addr
)
3501 int stack_offset
= 0;
3502 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3503 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3505 /* For shared libraries, "t9" needs to point at the function
3507 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3509 /* Set the return address register to point to the entry point of
3510 the program, where a breakpoint lies in wait. */
3511 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3513 /* First ensure that the stack and structure return address (if any)
3514 are properly aligned. The stack has to be at least 64-bit
3515 aligned even on 32-bit machines, because doubles must be 64-bit
3516 aligned. For n32 and n64, stack frames need to be 128-bit
3517 aligned, so we round to this widest known alignment. */
3519 sp
= align_down (sp
, 16);
3520 struct_addr
= align_down (struct_addr
, 16);
3522 /* Now make space on the stack for the args. */
3523 for (argnum
= 0; argnum
< nargs
; argnum
++)
3524 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])),
3525 mips_stack_argsize (gdbarch
));
3526 sp
-= align_up (len
, 16);
3529 fprintf_unfiltered (gdb_stdlog
,
3530 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3531 paddr_nz (sp
), (long) align_up (len
, 16));
3533 /* Initialize the integer and float register pointers. */
3534 argreg
= MIPS_A0_REGNUM
;
3535 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3537 /* The struct_return pointer occupies the first parameter-passing reg. */
3541 fprintf_unfiltered (gdb_stdlog
,
3542 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3543 argreg
, paddr_nz (struct_addr
));
3544 write_register (argreg
++, struct_addr
);
3545 stack_offset
+= mips_stack_argsize (gdbarch
);
3548 /* Now load as many as possible of the first arguments into
3549 registers, and push the rest onto the stack. Loop thru args
3550 from first to last. */
3551 for (argnum
= 0; argnum
< nargs
; argnum
++)
3553 const gdb_byte
*val
;
3554 struct value
*arg
= args
[argnum
];
3555 struct type
*arg_type
= check_typedef (value_type (arg
));
3556 int len
= TYPE_LENGTH (arg_type
);
3557 enum type_code typecode
= TYPE_CODE (arg_type
);
3560 fprintf_unfiltered (gdb_stdlog
,
3561 "mips_o64_push_dummy_call: %d len=%d type=%d",
3562 argnum
+ 1, len
, (int) typecode
);
3564 val
= value_contents (arg
);
3566 /* 32-bit ABIs always start floating point arguments in an
3567 even-numbered floating point register. Round the FP register
3568 up before the check to see if there are any FP registers
3569 left. O32/O64 targets also pass the FP in the integer
3570 registers so also round up normal registers. */
3571 if (mips_abi_regsize (gdbarch
) < 8
3572 && fp_register_arg_p (typecode
, arg_type
))
3574 if ((float_argreg
& 1))
3578 /* Floating point arguments passed in registers have to be
3579 treated specially. On 32-bit architectures, doubles
3580 are passed in register pairs; the even register gets
3581 the low word, and the odd register gets the high word.
3582 On O32/O64, the first two floating point arguments are
3583 also copied to general registers, because MIPS16 functions
3584 don't use float registers for arguments. This duplication of
3585 arguments in general registers can't hurt non-MIPS16 functions
3586 because those registers are normally skipped. */
3588 if (fp_register_arg_p (typecode
, arg_type
)
3589 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3591 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3593 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3594 unsigned long regval
;
3596 /* Write the low word of the double to the even register(s). */
3597 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3599 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3600 float_argreg
, phex (regval
, 4));
3601 write_register (float_argreg
++, regval
);
3603 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3604 argreg
, phex (regval
, 4));
3605 write_register (argreg
++, regval
);
3607 /* Write the high word of the double to the odd register(s). */
3608 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3610 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3611 float_argreg
, phex (regval
, 4));
3612 write_register (float_argreg
++, regval
);
3615 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3616 argreg
, phex (regval
, 4));
3617 write_register (argreg
++, regval
);
3621 /* This is a floating point value that fits entirely
3622 in a single register. */
3623 /* On 32 bit ABI's the float_argreg is further adjusted
3624 above to ensure that it is even register aligned. */
3625 LONGEST regval
= extract_unsigned_integer (val
, len
);
3627 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3628 float_argreg
, phex (regval
, len
));
3629 write_register (float_argreg
++, regval
);
3630 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3631 registers for each argument. The below is (my
3632 guess) to ensure that the corresponding integer
3633 register has reserved the same space. */
3635 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3636 argreg
, phex (regval
, len
));
3637 write_register (argreg
, regval
);
3638 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3640 /* Reserve space for the FP register. */
3641 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3645 /* Copy the argument to general registers or the stack in
3646 register-sized pieces. Large arguments are split between
3647 registers and stack. */
3648 /* Note: structs whose size is not a multiple of
3649 mips_abi_regsize() are treated specially: Irix cc passes
3650 them in registers where gcc sometimes puts them on the
3651 stack. For maximum compatibility, we will put them in
3653 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3654 && (len
% mips_abi_regsize (gdbarch
) != 0));
3655 /* Structures should be aligned to eight bytes (even arg registers)
3656 on MIPS_ABI_O32, if their first member has double precision. */
3657 if (mips_abi_regsize (gdbarch
) < 8
3658 && mips_type_needs_double_align (arg_type
))
3663 /* Note: Floating-point values that didn't fit into an FP
3664 register are only written to memory. */
3667 /* Remember if the argument was written to the stack. */
3668 int stack_used_p
= 0;
3669 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3670 ? len
: mips_abi_regsize (gdbarch
));
3673 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3676 /* Write this portion of the argument to the stack. */
3677 if (argreg
> MIPS_LAST_ARG_REGNUM
3679 || fp_register_arg_p (typecode
, arg_type
))
3681 /* Should shorter than int integer values be
3682 promoted to int before being stored? */
3683 int longword_offset
= 0;
3686 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3688 if (mips_stack_argsize (gdbarch
) == 8
3689 && (typecode
== TYPE_CODE_INT
3690 || typecode
== TYPE_CODE_PTR
3691 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3692 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3697 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3698 paddr_nz (stack_offset
));
3699 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3700 paddr_nz (longword_offset
));
3703 addr
= sp
+ stack_offset
+ longword_offset
;
3708 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3710 for (i
= 0; i
< partial_len
; i
++)
3712 fprintf_unfiltered (gdb_stdlog
, "%02x",
3716 write_memory (addr
, val
, partial_len
);
3719 /* Note!!! This is NOT an else clause. Odd sized
3720 structs may go thru BOTH paths. Floating point
3721 arguments will not. */
3722 /* Write this portion of the argument to a general
3723 purpose register. */
3724 if (argreg
<= MIPS_LAST_ARG_REGNUM
3725 && !fp_register_arg_p (typecode
, arg_type
))
3727 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3728 /* Value may need to be sign extended, because
3729 mips_isa_regsize() != mips_abi_regsize(). */
3731 /* A non-floating-point argument being passed in a
3732 general register. If a struct or union, and if
3733 the remaining length is smaller than the register
3734 size, we have to adjust the register value on
3737 It does not seem to be necessary to do the
3738 same for integral types. */
3740 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3741 && partial_len
< mips_abi_regsize (gdbarch
)
3742 && (typecode
== TYPE_CODE_STRUCT
||
3743 typecode
== TYPE_CODE_UNION
))
3744 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3748 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3751 mips_abi_regsize (gdbarch
)));
3752 write_register (argreg
, regval
);
3755 /* Prevent subsequent floating point arguments from
3756 being passed in floating point registers. */
3757 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3763 /* Compute the the offset into the stack at which we
3764 will copy the next parameter.
3766 In older ABIs, the caller reserved space for
3767 registers that contained arguments. This was loosely
3768 refered to as their "home". Consequently, space is
3769 always allocated. */
3771 stack_offset
+= align_up (partial_len
,
3772 mips_stack_argsize (gdbarch
));
3776 fprintf_unfiltered (gdb_stdlog
, "\n");
3779 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3781 /* Return adjusted stack pointer. */
3785 static enum return_value_convention
3786 mips_o64_return_value (struct gdbarch
*gdbarch
,
3787 struct type
*type
, struct regcache
*regcache
,
3788 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3790 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3792 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3793 || TYPE_CODE (type
) == TYPE_CODE_UNION
3794 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3795 return RETURN_VALUE_STRUCT_CONVENTION
;
3796 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
3798 /* A floating-point value. It fits in the least significant
3801 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3802 mips_xfer_register (regcache
,
3803 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3805 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3806 return RETURN_VALUE_REGISTER_CONVENTION
;
3810 /* A scalar extract each part but least-significant-byte
3814 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3815 offset
< TYPE_LENGTH (type
);
3816 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
3818 int xfer
= mips_stack_argsize (gdbarch
);
3819 if (offset
+ xfer
> TYPE_LENGTH (type
))
3820 xfer
= TYPE_LENGTH (type
) - offset
;
3822 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3823 offset
, xfer
, regnum
);
3824 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3825 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3827 return RETURN_VALUE_REGISTER_CONVENTION
;
3831 /* Floating point register management.
3833 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3834 64bit operations, these early MIPS cpus treat fp register pairs
3835 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3836 registers and offer a compatibility mode that emulates the MIPS2 fp
3837 model. When operating in MIPS2 fp compat mode, later cpu's split
3838 double precision floats into two 32-bit chunks and store them in
3839 consecutive fp regs. To display 64-bit floats stored in this
3840 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3841 Throw in user-configurable endianness and you have a real mess.
3843 The way this works is:
3844 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3845 double-precision value will be split across two logical registers.
3846 The lower-numbered logical register will hold the low-order bits,
3847 regardless of the processor's endianness.
3848 - If we are on a 64-bit processor, and we are looking for a
3849 single-precision value, it will be in the low ordered bits
3850 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3851 save slot in memory.
3852 - If we are in 64-bit mode, everything is straightforward.
3854 Note that this code only deals with "live" registers at the top of the
3855 stack. We will attempt to deal with saved registers later, when
3856 the raw/cooked register interface is in place. (We need a general
3857 interface that can deal with dynamic saved register sizes -- fp
3858 regs could be 32 bits wide in one frame and 64 on the frame above
3861 static struct type
*
3862 mips_float_register_type (void)
3864 return builtin_type_ieee_single
;
3867 static struct type
*
3868 mips_double_register_type (void)
3870 return builtin_type_ieee_double
;
3873 /* Copy a 32-bit single-precision value from the current frame
3874 into rare_buffer. */
3877 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3878 gdb_byte
*rare_buffer
)
3880 int raw_size
= register_size (current_gdbarch
, regno
);
3881 gdb_byte
*raw_buffer
= alloca (raw_size
);
3883 if (!frame_register_read (frame
, regno
, raw_buffer
))
3884 error (_("can't read register %d (%s)"), regno
, REGISTER_NAME (regno
));
3887 /* We have a 64-bit value for this register. Find the low-order
3891 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3896 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3900 memcpy (rare_buffer
, raw_buffer
, 4);
3904 /* Copy a 64-bit double-precision value from the current frame into
3905 rare_buffer. This may include getting half of it from the next
3909 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
3910 gdb_byte
*rare_buffer
)
3912 int raw_size
= register_size (current_gdbarch
, regno
);
3914 if (raw_size
== 8 && !mips2_fp_compat ())
3916 /* We have a 64-bit value for this register, and we should use
3918 if (!frame_register_read (frame
, regno
, rare_buffer
))
3919 error (_("can't read register %d (%s)"), regno
, REGISTER_NAME (regno
));
3923 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
3924 internal_error (__FILE__
, __LINE__
,
3925 _("mips_read_fp_register_double: bad access to "
3926 "odd-numbered FP register"));
3928 /* mips_read_fp_register_single will find the correct 32 bits from
3930 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3932 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
3933 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
3937 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
3938 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
3944 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
3946 { /* do values for FP (float) regs */
3947 gdb_byte
*raw_buffer
;
3948 double doub
, flt1
; /* doubles extracted from raw hex data */
3951 raw_buffer
= alloca (2 * register_size (current_gdbarch
,
3952 mips_regnum (current_gdbarch
)->fp0
));
3954 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
3955 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
3958 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
3960 /* 4-byte registers: Print hex and floating. Also print even
3961 numbered registers as doubles. */
3962 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3963 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3965 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
3968 fprintf_filtered (file
, " flt: ");
3970 fprintf_filtered (file
, " <invalid float> ");
3972 fprintf_filtered (file
, "%-17.9g", flt1
);
3974 if (regnum
% 2 == 0)
3976 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3977 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
3980 fprintf_filtered (file
, " dbl: ");
3982 fprintf_filtered (file
, "<invalid double>");
3984 fprintf_filtered (file
, "%-24.17g", doub
);
3989 /* Eight byte registers: print each one as hex, float and double. */
3990 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3991 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3993 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3994 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
3997 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4000 fprintf_filtered (file
, " flt: ");
4002 fprintf_filtered (file
, "<invalid float>");
4004 fprintf_filtered (file
, "%-17.9g", flt1
);
4006 fprintf_filtered (file
, " dbl: ");
4008 fprintf_filtered (file
, "<invalid double>");
4010 fprintf_filtered (file
, "%-24.17g", doub
);
4015 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4016 int regnum
, int all
)
4018 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4019 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4022 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4024 mips_print_fp_register (file
, frame
, regnum
);
4028 /* Get the data in raw format. */
4029 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4031 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4035 fputs_filtered (REGISTER_NAME (regnum
), file
);
4037 /* The problem with printing numeric register names (r26, etc.) is that
4038 the user can't use them on input. Probably the best solution is to
4039 fix it so that either the numeric or the funky (a2, etc.) names
4040 are accepted on input. */
4041 if (regnum
< MIPS_NUMREGS
)
4042 fprintf_filtered (file
, "(r%d): ", regnum
);
4044 fprintf_filtered (file
, ": ");
4046 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4048 register_size (current_gdbarch
,
4049 regnum
) - register_size (current_gdbarch
, regnum
);
4053 print_scalar_formatted (raw_buffer
+ offset
,
4054 register_type (gdbarch
, regnum
), 'x', 0,
4058 /* Replacement for generic do_registers_info.
4059 Print regs in pretty columns. */
4062 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4065 fprintf_filtered (file
, " ");
4066 mips_print_fp_register (file
, frame
, regnum
);
4067 fprintf_filtered (file
, "\n");
4072 /* Print a row's worth of GP (int) registers, with name labels above */
4075 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4078 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4079 /* do values for GP (int) regs */
4080 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4081 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4085 /* For GP registers, we print a separate row of names above the vals */
4086 for (col
= 0, regnum
= start_regnum
;
4087 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4089 if (*REGISTER_NAME (regnum
) == '\0')
4090 continue; /* unused register */
4091 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4093 break; /* end the row: reached FP register */
4095 fprintf_filtered (file
, " ");
4096 fprintf_filtered (file
,
4097 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4098 REGISTER_NAME (regnum
));
4105 /* print the R0 to R31 names */
4106 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4107 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4109 fprintf_filtered (file
, "\n ");
4111 /* now print the values in hex, 4 or 8 to the row */
4112 for (col
= 0, regnum
= start_regnum
;
4113 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4115 if (*REGISTER_NAME (regnum
) == '\0')
4116 continue; /* unused register */
4117 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4119 break; /* end row: reached FP register */
4120 /* OK: get the data in raw format. */
4121 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4122 error (_("can't read register %d (%s)"), regnum
, REGISTER_NAME (regnum
));
4123 /* pad small registers */
4125 byte
< (mips_abi_regsize (current_gdbarch
)
4126 - register_size (current_gdbarch
, regnum
)); byte
++)
4127 printf_filtered (" ");
4128 /* Now print the register value in hex, endian order. */
4129 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4131 register_size (current_gdbarch
,
4132 regnum
) - register_size (current_gdbarch
, regnum
);
4133 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4134 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4136 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4138 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4139 fprintf_filtered (file
, " ");
4142 if (col
> 0) /* ie. if we actually printed anything... */
4143 fprintf_filtered (file
, "\n");
4148 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4151 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4152 struct frame_info
*frame
, int regnum
, int all
)
4154 if (regnum
!= -1) /* do one specified register */
4156 gdb_assert (regnum
>= NUM_REGS
);
4157 if (*(REGISTER_NAME (regnum
)) == '\0')
4158 error (_("Not a valid register for the current processor type"));
4160 mips_print_register (file
, frame
, regnum
, 0);
4161 fprintf_filtered (file
, "\n");
4164 /* do all (or most) registers */
4167 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4169 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4172 if (all
) /* true for "INFO ALL-REGISTERS" command */
4173 regnum
= print_fp_register_row (file
, frame
, regnum
);
4175 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4178 regnum
= print_gp_register_row (file
, frame
, regnum
);
4183 /* Is this a branch with a delay slot? */
4186 is_delayed (unsigned long insn
)
4189 for (i
= 0; i
< NUMOPCODES
; ++i
)
4190 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4191 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4193 return (i
< NUMOPCODES
4194 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4195 | INSN_COND_BRANCH_DELAY
4196 | INSN_COND_BRANCH_LIKELY
)));
4200 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4201 struct frame_info
*frame
)
4203 CORE_ADDR pc
= get_frame_pc (frame
);
4204 gdb_byte buf
[MIPS_INSN32_SIZE
];
4206 /* There is no branch delay slot on MIPS16. */
4207 if (mips_pc_is_mips16 (pc
))
4210 if (!breakpoint_here_p (pc
+ 4))
4213 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4214 /* If error reading memory, guess that it is not a delayed
4217 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4220 /* To skip prologues, I use this predicate. Returns either PC itself
4221 if the code at PC does not look like a function prologue; otherwise
4222 returns an address that (if we're lucky) follows the prologue. If
4223 LENIENT, then we must skip everything which is involved in setting
4224 up the frame (it's OK to skip more, just so long as we don't skip
4225 anything which might clobber the registers which are being saved.
4226 We must skip more in the case where part of the prologue is in the
4227 delay slot of a non-prologue instruction). */
4230 mips_skip_prologue (CORE_ADDR pc
)
4233 CORE_ADDR func_addr
;
4235 /* See if we can determine the end of the prologue via the symbol table.
4236 If so, then return either PC, or the PC after the prologue, whichever
4238 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4240 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4241 if (post_prologue_pc
!= 0)
4242 return max (pc
, post_prologue_pc
);
4245 /* Can't determine prologue from the symbol table, need to examine
4248 /* Find an upper limit on the function prologue using the debug
4249 information. If the debug information could not be used to provide
4250 that bound, then use an arbitrary large number as the upper bound. */
4251 limit_pc
= skip_prologue_using_sal (pc
);
4253 limit_pc
= pc
+ 100; /* Magic. */
4255 if (mips_pc_is_mips16 (pc
))
4256 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4258 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4261 /* Root of all "set mips "/"show mips " commands. This will eventually be
4262 used for all MIPS-specific commands. */
4265 show_mips_command (char *args
, int from_tty
)
4267 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4271 set_mips_command (char *args
, int from_tty
)
4274 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4275 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4278 /* Commands to show/set the MIPS FPU type. */
4281 show_mipsfpu_command (char *args
, int from_tty
)
4284 switch (MIPS_FPU_TYPE
)
4286 case MIPS_FPU_SINGLE
:
4287 fpu
= "single-precision";
4289 case MIPS_FPU_DOUBLE
:
4290 fpu
= "double-precision";
4293 fpu
= "absent (none)";
4296 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4298 if (mips_fpu_type_auto
)
4300 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4304 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4309 set_mipsfpu_command (char *args
, int from_tty
)
4312 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4313 show_mipsfpu_command (args
, from_tty
);
4317 set_mipsfpu_single_command (char *args
, int from_tty
)
4319 struct gdbarch_info info
;
4320 gdbarch_info_init (&info
);
4321 mips_fpu_type
= MIPS_FPU_SINGLE
;
4322 mips_fpu_type_auto
= 0;
4323 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4324 instead of relying on globals. Doing that would let generic code
4325 handle the search for this specific architecture. */
4326 if (!gdbarch_update_p (info
))
4327 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4331 set_mipsfpu_double_command (char *args
, int from_tty
)
4333 struct gdbarch_info info
;
4334 gdbarch_info_init (&info
);
4335 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4336 mips_fpu_type_auto
= 0;
4337 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4338 instead of relying on globals. Doing that would let generic code
4339 handle the search for this specific architecture. */
4340 if (!gdbarch_update_p (info
))
4341 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4345 set_mipsfpu_none_command (char *args
, int from_tty
)
4347 struct gdbarch_info info
;
4348 gdbarch_info_init (&info
);
4349 mips_fpu_type
= MIPS_FPU_NONE
;
4350 mips_fpu_type_auto
= 0;
4351 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4352 instead of relying on globals. Doing that would let generic code
4353 handle the search for this specific architecture. */
4354 if (!gdbarch_update_p (info
))
4355 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4359 set_mipsfpu_auto_command (char *args
, int from_tty
)
4361 mips_fpu_type_auto
= 1;
4364 /* Attempt to identify the particular processor model by reading the
4365 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4366 the relevant processor still exists (it dates back to '94) and
4367 secondly this is not the way to do this. The processor type should
4368 be set by forcing an architecture change. */
4371 deprecated_mips_set_processor_regs_hack (void)
4373 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4376 prid
= read_register (MIPS_PRID_REGNUM
);
4378 if ((prid
& ~0xf) == 0x700)
4379 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4382 /* Just like reinit_frame_cache, but with the right arguments to be
4383 callable as an sfunc. */
4386 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4387 struct cmd_list_element
*c
)
4389 reinit_frame_cache ();
4393 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4395 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4397 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4398 disassembler needs to be able to locally determine the ISA, and
4399 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4401 if (mips_pc_is_mips16 (memaddr
))
4402 info
->mach
= bfd_mach_mips16
;
4404 /* Round down the instruction address to the appropriate boundary. */
4405 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4407 /* Set the disassembler options. */
4408 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4410 /* Set up the disassembler info, so that we get the right
4411 register names from libopcodes. */
4412 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4413 info
->disassembler_options
= "gpr-names=n32";
4415 info
->disassembler_options
= "gpr-names=64";
4416 info
->flavour
= bfd_target_elf_flavour
;
4419 /* This string is not recognized explicitly by the disassembler,
4420 but it tells the disassembler to not try to guess the ABI from
4421 the bfd elf headers, such that, if the user overrides the ABI
4422 of a program linked as NewABI, the disassembly will follow the
4423 register naming conventions specified by the user. */
4424 info
->disassembler_options
= "gpr-names=32";
4426 /* Call the appropriate disassembler based on the target endian-ness. */
4427 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4428 return print_insn_big_mips (memaddr
, info
);
4430 return print_insn_little_mips (memaddr
, info
);
4433 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4434 counter value to determine whether a 16- or 32-bit breakpoint should be
4435 used. It returns a pointer to a string of bytes that encode a breakpoint
4436 instruction, stores the length of the string to *lenptr, and adjusts pc
4437 (if necessary) to point to the actual memory location where the
4438 breakpoint should be inserted. */
4440 static const gdb_byte
*
4441 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4443 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4445 if (mips_pc_is_mips16 (*pcptr
))
4447 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4448 *pcptr
= unmake_mips16_addr (*pcptr
);
4449 *lenptr
= sizeof (mips16_big_breakpoint
);
4450 return mips16_big_breakpoint
;
4454 /* The IDT board uses an unusual breakpoint value, and
4455 sometimes gets confused when it sees the usual MIPS
4456 breakpoint instruction. */
4457 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4458 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4459 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4461 *lenptr
= sizeof (big_breakpoint
);
4463 if (strcmp (target_shortname
, "mips") == 0)
4464 return idt_big_breakpoint
;
4465 else if (strcmp (target_shortname
, "ddb") == 0
4466 || strcmp (target_shortname
, "pmon") == 0
4467 || strcmp (target_shortname
, "lsi") == 0)
4468 return pmon_big_breakpoint
;
4470 return big_breakpoint
;
4475 if (mips_pc_is_mips16 (*pcptr
))
4477 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4478 *pcptr
= unmake_mips16_addr (*pcptr
);
4479 *lenptr
= sizeof (mips16_little_breakpoint
);
4480 return mips16_little_breakpoint
;
4484 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4485 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4486 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4488 *lenptr
= sizeof (little_breakpoint
);
4490 if (strcmp (target_shortname
, "mips") == 0)
4491 return idt_little_breakpoint
;
4492 else if (strcmp (target_shortname
, "ddb") == 0
4493 || strcmp (target_shortname
, "pmon") == 0
4494 || strcmp (target_shortname
, "lsi") == 0)
4495 return pmon_little_breakpoint
;
4497 return little_breakpoint
;
4502 /* If PC is in a mips16 call or return stub, return the address of the target
4503 PC, which is either the callee or the caller. There are several
4504 cases which must be handled:
4506 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4507 target PC is in $31 ($ra).
4508 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4509 and the target PC is in $2.
4510 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4511 before the jal instruction, this is effectively a call stub
4512 and the the target PC is in $2. Otherwise this is effectively
4513 a return stub and the target PC is in $18.
4515 See the source code for the stubs in gcc/config/mips/mips16.S for
4519 mips_skip_trampoline_code (CORE_ADDR pc
)
4522 CORE_ADDR start_addr
;
4524 /* Find the starting address and name of the function containing the PC. */
4525 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4528 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4529 target PC is in $31 ($ra). */
4530 if (strcmp (name
, "__mips16_ret_sf") == 0
4531 || strcmp (name
, "__mips16_ret_df") == 0)
4532 return read_signed_register (MIPS_RA_REGNUM
);
4534 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4536 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4537 and the target PC is in $2. */
4538 if (name
[19] >= '0' && name
[19] <= '9')
4539 return read_signed_register (2);
4541 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4542 before the jal instruction, this is effectively a call stub
4543 and the the target PC is in $2. Otherwise this is effectively
4544 a return stub and the target PC is in $18. */
4545 else if (name
[19] == 's' || name
[19] == 'd')
4547 if (pc
== start_addr
)
4549 /* Check if the target of the stub is a compiler-generated
4550 stub. Such a stub for a function bar might have a name
4551 like __fn_stub_bar, and might look like this:
4556 la $1,bar (becomes a lui/addiu pair)
4558 So scan down to the lui/addi and extract the target
4559 address from those two instructions. */
4561 CORE_ADDR target_pc
= read_signed_register (2);
4565 /* See if the name of the target function is __fn_stub_*. */
4566 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4569 if (strncmp (name
, "__fn_stub_", 10) != 0
4570 && strcmp (name
, "etext") != 0
4571 && strcmp (name
, "_etext") != 0)
4574 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4575 The limit on the search is arbitrarily set to 20
4576 instructions. FIXME. */
4577 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
4579 inst
= mips_fetch_instruction (target_pc
);
4580 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4581 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4582 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4583 return pc
| (inst
& 0xffff); /* low word */
4586 /* Couldn't find the lui/addui pair, so return stub address. */
4590 /* This is the 'return' part of a call stub. The return
4591 address is in $r18. */
4592 return read_signed_register (18);
4595 return 0; /* not a stub */
4598 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4599 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4602 mips_stab_reg_to_regnum (int num
)
4605 if (num
>= 0 && num
< 32)
4607 else if (num
>= 38 && num
< 70)
4608 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4610 regnum
= mips_regnum (current_gdbarch
)->hi
;
4612 regnum
= mips_regnum (current_gdbarch
)->lo
;
4614 /* This will hopefully (eventually) provoke a warning. Should
4615 we be calling complaint() here? */
4616 return NUM_REGS
+ NUM_PSEUDO_REGS
;
4617 return NUM_REGS
+ regnum
;
4621 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4622 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4625 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4628 if (num
>= 0 && num
< 32)
4630 else if (num
>= 32 && num
< 64)
4631 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4633 regnum
= mips_regnum (current_gdbarch
)->hi
;
4635 regnum
= mips_regnum (current_gdbarch
)->lo
;
4637 /* This will hopefully (eventually) provoke a warning. Should we
4638 be calling complaint() here? */
4639 return NUM_REGS
+ NUM_PSEUDO_REGS
;
4640 return NUM_REGS
+ regnum
;
4644 mips_register_sim_regno (int regnum
)
4646 /* Only makes sense to supply raw registers. */
4647 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
4648 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4649 decide if it is valid. Should instead define a standard sim/gdb
4650 register numbering scheme. */
4651 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
4652 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
4655 return LEGACY_SIM_REGNO_IGNORE
;
4659 /* Convert an integer into an address. Extracting the value signed
4660 guarantees a correctly sign extended address. */
4663 mips_integer_to_address (struct gdbarch
*gdbarch
,
4664 struct type
*type
, const gdb_byte
*buf
)
4666 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
4670 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4672 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4673 const char *name
= bfd_get_section_name (abfd
, sect
);
4675 if (*abip
!= MIPS_ABI_UNKNOWN
)
4678 if (strncmp (name
, ".mdebug.", 8) != 0)
4681 if (strcmp (name
, ".mdebug.abi32") == 0)
4682 *abip
= MIPS_ABI_O32
;
4683 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4684 *abip
= MIPS_ABI_N32
;
4685 else if (strcmp (name
, ".mdebug.abi64") == 0)
4686 *abip
= MIPS_ABI_N64
;
4687 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4688 *abip
= MIPS_ABI_O64
;
4689 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4690 *abip
= MIPS_ABI_EABI32
;
4691 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4692 *abip
= MIPS_ABI_EABI64
;
4694 warning (_("unsupported ABI %s."), name
+ 8);
4698 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
4700 int *lbp
= (int *) obj
;
4701 const char *name
= bfd_get_section_name (abfd
, sect
);
4703 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
4705 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
4707 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
4708 warning (_("unrecognized .gcc_compiled_longXX"));
4711 static enum mips_abi
4712 global_mips_abi (void)
4716 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4717 if (mips_abi_strings
[i
] == mips_abi_string
)
4718 return (enum mips_abi
) i
;
4720 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
4724 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
4726 static struct target_desc
*tdesc_gp32
, *tdesc_gp64
;
4728 if (tdesc_gp32
== NULL
)
4730 /* Create feature sets with the appropriate properties. The values
4731 are not important. */
4733 tdesc_gp32
= allocate_target_description ();
4734 set_tdesc_property (tdesc_gp32
, PROPERTY_GP32
, "");
4736 tdesc_gp64
= allocate_target_description ();
4737 set_tdesc_property (tdesc_gp64
, PROPERTY_GP64
, "");
4740 /* If the size matches the set of 32-bit or 64-bit integer registers,
4741 assume that's what we've got. */
4742 register_remote_g_packet_guess (gdbarch
, 38 * 4, tdesc_gp32
);
4743 register_remote_g_packet_guess (gdbarch
, 38 * 8, tdesc_gp64
);
4745 /* If the size matches the full set of registers GDB traditionally
4746 knows about, including floating point, for either 32-bit or
4747 64-bit, assume that's what we've got. */
4748 register_remote_g_packet_guess (gdbarch
, 90 * 4, tdesc_gp32
);
4749 register_remote_g_packet_guess (gdbarch
, 90 * 8, tdesc_gp64
);
4751 /* Otherwise we don't have a useful guess. */
4754 static struct gdbarch
*
4755 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4757 struct gdbarch
*gdbarch
;
4758 struct gdbarch_tdep
*tdep
;
4760 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4762 enum mips_fpu_type fpu_type
;
4764 /* First of all, extract the elf_flags, if available. */
4765 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4766 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4767 else if (arches
!= NULL
)
4768 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
4772 fprintf_unfiltered (gdb_stdlog
,
4773 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
4775 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4776 switch ((elf_flags
& EF_MIPS_ABI
))
4778 case E_MIPS_ABI_O32
:
4779 found_abi
= MIPS_ABI_O32
;
4781 case E_MIPS_ABI_O64
:
4782 found_abi
= MIPS_ABI_O64
;
4784 case E_MIPS_ABI_EABI32
:
4785 found_abi
= MIPS_ABI_EABI32
;
4787 case E_MIPS_ABI_EABI64
:
4788 found_abi
= MIPS_ABI_EABI64
;
4791 if ((elf_flags
& EF_MIPS_ABI2
))
4792 found_abi
= MIPS_ABI_N32
;
4794 found_abi
= MIPS_ABI_UNKNOWN
;
4798 /* GCC creates a pseudo-section whose name describes the ABI. */
4799 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4800 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
4802 /* If we have no useful BFD information, use the ABI from the last
4803 MIPS architecture (if there is one). */
4804 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
4805 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
4807 /* Try the architecture for any hint of the correct ABI. */
4808 if (found_abi
== MIPS_ABI_UNKNOWN
4809 && info
.bfd_arch_info
!= NULL
4810 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4812 switch (info
.bfd_arch_info
->mach
)
4814 case bfd_mach_mips3900
:
4815 found_abi
= MIPS_ABI_EABI32
;
4817 case bfd_mach_mips4100
:
4818 case bfd_mach_mips5000
:
4819 found_abi
= MIPS_ABI_EABI64
;
4821 case bfd_mach_mips8000
:
4822 case bfd_mach_mips10000
:
4823 /* On Irix, ELF64 executables use the N64 ABI. The
4824 pseudo-sections which describe the ABI aren't present
4825 on IRIX. (Even for executables created by gcc.) */
4826 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4827 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4828 found_abi
= MIPS_ABI_N64
;
4830 found_abi
= MIPS_ABI_N32
;
4835 /* Default 64-bit objects to N64 instead of O32. */
4836 if (found_abi
== MIPS_ABI_UNKNOWN
4837 && info
.abfd
!= NULL
4838 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4839 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4840 found_abi
= MIPS_ABI_N64
;
4843 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
4846 /* What has the user specified from the command line? */
4847 wanted_abi
= global_mips_abi ();
4849 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
4852 /* Now that we have found what the ABI for this binary would be,
4853 check whether the user is overriding it. */
4854 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
4855 mips_abi
= wanted_abi
;
4856 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
4857 mips_abi
= found_abi
;
4859 mips_abi
= MIPS_ABI_O32
;
4861 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
4864 /* Also used when doing an architecture lookup. */
4866 fprintf_unfiltered (gdb_stdlog
,
4867 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
4868 mips64_transfers_32bit_regs_p
);
4870 /* Determine the MIPS FPU type. */
4871 if (!mips_fpu_type_auto
)
4872 fpu_type
= mips_fpu_type
;
4873 else if (info
.bfd_arch_info
!= NULL
4874 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4875 switch (info
.bfd_arch_info
->mach
)
4877 case bfd_mach_mips3900
:
4878 case bfd_mach_mips4100
:
4879 case bfd_mach_mips4111
:
4880 case bfd_mach_mips4120
:
4881 fpu_type
= MIPS_FPU_NONE
;
4883 case bfd_mach_mips4650
:
4884 fpu_type
= MIPS_FPU_SINGLE
;
4887 fpu_type
= MIPS_FPU_DOUBLE
;
4890 else if (arches
!= NULL
)
4891 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
4893 fpu_type
= MIPS_FPU_DOUBLE
;
4895 fprintf_unfiltered (gdb_stdlog
,
4896 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
4898 /* Check for blatant incompatibilities. */
4900 /* If we have only 32-bit registers, then we can't debug a 64-bit
4902 if (info
.target_desc
4903 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
4904 && mips_abi
!= MIPS_ABI_EABI32
4905 && mips_abi
!= MIPS_ABI_O32
)
4908 /* try to find a pre-existing architecture */
4909 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4911 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4913 /* MIPS needs to be pedantic about which ABI the object is
4915 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4917 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4919 /* Need to be pedantic about which register virtual size is
4921 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
4922 != mips64_transfers_32bit_regs_p
)
4924 /* Be pedantic about which FPU is selected. */
4925 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
4927 return arches
->gdbarch
;
4930 /* Need a new architecture. Fill in a target specific vector. */
4931 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4932 gdbarch
= gdbarch_alloc (&info
, tdep
);
4933 tdep
->elf_flags
= elf_flags
;
4934 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
4935 tdep
->found_abi
= found_abi
;
4936 tdep
->mips_abi
= mips_abi
;
4937 tdep
->mips_fpu_type
= fpu_type
;
4938 tdep
->register_size_valid_p
= 0;
4939 tdep
->register_size
= 0;
4941 if (info
.target_desc
)
4943 /* Some useful properties can be inferred from the target. */
4944 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
4946 tdep
->register_size_valid_p
= 1;
4947 tdep
->register_size
= 4;
4949 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
4951 tdep
->register_size_valid_p
= 1;
4952 tdep
->register_size
= 8;
4956 /* Initially set everything according to the default ABI/ISA. */
4957 set_gdbarch_short_bit (gdbarch
, 16);
4958 set_gdbarch_int_bit (gdbarch
, 32);
4959 set_gdbarch_float_bit (gdbarch
, 32);
4960 set_gdbarch_double_bit (gdbarch
, 64);
4961 set_gdbarch_long_double_bit (gdbarch
, 64);
4962 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
4963 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
4964 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
4966 set_gdbarch_elf_make_msymbol_special (gdbarch
,
4967 mips_elf_make_msymbol_special
);
4969 /* Fill in the OS dependant register numbers and names. */
4971 const char **reg_names
;
4972 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
4973 struct mips_regnum
);
4974 if (info
.osabi
== GDB_OSABI_IRIX
)
4979 regnum
->badvaddr
= 66;
4982 regnum
->fp_control_status
= 69;
4983 regnum
->fp_implementation_revision
= 70;
4985 reg_names
= mips_irix_reg_names
;
4989 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
4990 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
4991 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
4992 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
4993 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
4994 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
4995 regnum
->fp_control_status
= 70;
4996 regnum
->fp_implementation_revision
= 71;
4998 if (info
.bfd_arch_info
!= NULL
4999 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5000 reg_names
= mips_tx39_reg_names
;
5002 reg_names
= mips_generic_reg_names
;
5004 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5005 replaced by read_pc? */
5006 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5007 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5008 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5009 set_gdbarch_num_regs (gdbarch
, num_regs
);
5010 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5011 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5012 tdep
->mips_processor_reg_names
= reg_names
;
5013 tdep
->regnum
= regnum
;
5019 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5020 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5021 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5022 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5023 tdep
->default_mask_address_p
= 0;
5024 set_gdbarch_long_bit (gdbarch
, 32);
5025 set_gdbarch_ptr_bit (gdbarch
, 32);
5026 set_gdbarch_long_long_bit (gdbarch
, 64);
5029 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5030 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5031 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5032 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5033 tdep
->default_mask_address_p
= 0;
5034 set_gdbarch_long_bit (gdbarch
, 32);
5035 set_gdbarch_ptr_bit (gdbarch
, 32);
5036 set_gdbarch_long_long_bit (gdbarch
, 64);
5038 case MIPS_ABI_EABI32
:
5039 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5040 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5041 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5042 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5043 tdep
->default_mask_address_p
= 0;
5044 set_gdbarch_long_bit (gdbarch
, 32);
5045 set_gdbarch_ptr_bit (gdbarch
, 32);
5046 set_gdbarch_long_long_bit (gdbarch
, 64);
5048 case MIPS_ABI_EABI64
:
5049 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5050 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5051 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5052 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5053 tdep
->default_mask_address_p
= 0;
5054 set_gdbarch_long_bit (gdbarch
, 64);
5055 set_gdbarch_ptr_bit (gdbarch
, 64);
5056 set_gdbarch_long_long_bit (gdbarch
, 64);
5059 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5060 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5061 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5062 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5063 tdep
->default_mask_address_p
= 0;
5064 set_gdbarch_long_bit (gdbarch
, 32);
5065 set_gdbarch_ptr_bit (gdbarch
, 32);
5066 set_gdbarch_long_long_bit (gdbarch
, 64);
5067 set_gdbarch_long_double_bit (gdbarch
, 128);
5068 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5071 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5072 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5073 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5074 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5075 tdep
->default_mask_address_p
= 0;
5076 set_gdbarch_long_bit (gdbarch
, 64);
5077 set_gdbarch_ptr_bit (gdbarch
, 64);
5078 set_gdbarch_long_long_bit (gdbarch
, 64);
5079 set_gdbarch_long_double_bit (gdbarch
, 128);
5080 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5083 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5086 /* GCC creates a pseudo-section whose name specifies the size of
5087 longs, since -mlong32 or -mlong64 may be used independent of
5088 other options. How those options affect pointer sizes is ABI and
5089 architecture dependent, so use them to override the default sizes
5090 set by the ABI. This table shows the relationship between ABI,
5091 -mlongXX, and size of pointers:
5093 ABI -mlongXX ptr bits
5094 --- -------- --------
5108 Note that for o32 and eabi32, pointers are always 32 bits
5109 regardless of any -mlongXX option. For all others, pointers and
5110 longs are the same, as set by -mlongXX or set by defaults.
5113 if (info
.abfd
!= NULL
)
5117 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5120 set_gdbarch_long_bit (gdbarch
, long_bit
);
5124 case MIPS_ABI_EABI32
:
5129 case MIPS_ABI_EABI64
:
5130 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5133 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5138 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5139 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5142 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5143 flag in object files because to do so would make it impossible to
5144 link with libraries compiled without "-gp32". This is
5145 unnecessarily restrictive.
5147 We could solve this problem by adding "-gp32" multilibs to gcc,
5148 but to set this flag before gcc is built with such multilibs will
5149 break too many systems.''
5151 But even more unhelpfully, the default linker output target for
5152 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5153 for 64-bit programs - you need to change the ABI to change this,
5154 and not all gcc targets support that currently. Therefore using
5155 this flag to detect 32-bit mode would do the wrong thing given
5156 the current gcc - it would make GDB treat these 64-bit programs
5157 as 32-bit programs by default. */
5159 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5160 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5161 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5163 /* Add/remove bits from an address. The MIPS needs be careful to
5164 ensure that all 32 bit addresses are sign extended to 64 bits. */
5165 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5167 /* Unwind the frame. */
5168 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5169 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5171 /* Map debug register numbers onto internal register numbers. */
5172 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5173 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5174 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5175 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5176 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5177 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5178 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5179 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5181 /* MIPS version of CALL_DUMMY */
5183 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5184 replaced by a command, and all targets will default to on stack
5185 (regardless of the stack's execute status). */
5186 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5187 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5189 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5190 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5191 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5193 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5194 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5196 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5198 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5199 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5200 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5202 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5204 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5206 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5208 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5209 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5210 need to all be folded into the target vector. Since they are
5211 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5212 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5214 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5216 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5218 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5220 /* Virtual tables. */
5221 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5223 mips_register_g_packet_guesses (gdbarch
);
5225 /* Hook in OS ABI-specific overrides, if they have been registered. */
5226 gdbarch_init_osabi (info
, gdbarch
);
5228 /* Unwind the frame. */
5229 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5230 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5231 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5232 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5233 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5234 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5240 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5242 struct gdbarch_info info
;
5244 /* Force the architecture to update, and (if it's a MIPS architecture)
5245 mips_gdbarch_init will take care of the rest. */
5246 gdbarch_info_init (&info
);
5247 gdbarch_update_p (info
);
5250 /* Print out which MIPS ABI is in use. */
5253 show_mips_abi (struct ui_file
*file
,
5255 struct cmd_list_element
*ignored_cmd
,
5256 const char *ignored_value
)
5258 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5261 "The MIPS ABI is unknown because the current architecture "
5265 enum mips_abi global_abi
= global_mips_abi ();
5266 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5267 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5269 if (global_abi
== MIPS_ABI_UNKNOWN
)
5272 "The MIPS ABI is set automatically (currently \"%s\").\n",
5274 else if (global_abi
== actual_abi
)
5277 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5281 /* Probably shouldn't happen... */
5284 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5285 actual_abi_str
, mips_abi_strings
[global_abi
]);
5291 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5293 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5297 int ef_mips_32bitmode
;
5298 /* Determine the ISA. */
5299 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5317 /* Determine the size of a pointer. */
5318 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5319 fprintf_unfiltered (file
,
5320 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5322 fprintf_unfiltered (file
,
5323 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5325 fprintf_unfiltered (file
,
5326 "mips_dump_tdep: ef_mips_arch = %d\n",
5328 fprintf_unfiltered (file
,
5329 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5330 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5331 fprintf_unfiltered (file
,
5332 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5333 mips_mask_address_p (tdep
),
5334 tdep
->default_mask_address_p
);
5336 fprintf_unfiltered (file
,
5337 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5338 MIPS_DEFAULT_FPU_TYPE
,
5339 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5340 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5341 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5343 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5344 fprintf_unfiltered (file
,
5345 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5347 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5348 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5349 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5351 fprintf_unfiltered (file
,
5352 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5353 mips_stack_argsize (current_gdbarch
));
5356 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5359 _initialize_mips_tdep (void)
5361 static struct cmd_list_element
*mipsfpulist
= NULL
;
5362 struct cmd_list_element
*c
;
5364 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5365 if (MIPS_ABI_LAST
+ 1
5366 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5367 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
5369 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5371 mips_pdr_data
= register_objfile_data ();
5373 /* Add root prefix command for all "set mips"/"show mips" commands */
5374 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5375 _("Various MIPS specific commands."),
5376 &setmipscmdlist
, "set mips ", 0, &setlist
);
5378 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5379 _("Various MIPS specific commands."),
5380 &showmipscmdlist
, "show mips ", 0, &showlist
);
5382 /* Allow the user to override the saved register size. */
5383 add_setshow_enum_cmd ("saved-gpreg-size", class_obscure
,
5384 size_enums
, &mips_abi_regsize_string
, _("\
5385 Set size of general purpose registers saved on the stack."), _("\
5386 Show size of general purpose registers saved on the stack."), _("\
5387 This option can be set to one of:\n\
5388 32 - Force GDB to treat saved GP registers as 32-bit\n\
5389 64 - Force GDB to treat saved GP registers as 64-bit\n\
5390 auto - Allow GDB to use the target's default setting or autodetect the\n\
5391 saved GP register size from information contained in the\n\
5392 executable (default)."),
5394 NULL
, /* FIXME: i18n: Size of general purpose registers saved on the stack is %s. */
5395 &setmipscmdlist
, &showmipscmdlist
);
5397 /* Allow the user to override the argument stack size. */
5398 add_setshow_enum_cmd ("stack-arg-size", class_obscure
,
5399 size_enums
, &mips_stack_argsize_string
, _("\
5400 Set the amount of stack space reserved for each argument."), _("\
5401 Show the amount of stack space reserved for each argument."), _("\
5402 This option can be set to one of:\n\
5403 32 - Force GDB to allocate 32-bit chunks per argument\n\
5404 64 - Force GDB to allocate 64-bit chunks per argument\n\
5405 auto - Allow GDB to determine the correct setting from the current\n\
5406 target and executable (default)"),
5408 NULL
, /* FIXME: i18n: The amount of stack space reserved for each argument is %s. */
5409 &setmipscmdlist
, &showmipscmdlist
);
5411 /* Allow the user to override the ABI. */
5412 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
5413 &mips_abi_string
, _("\
5414 Set the MIPS ABI used by this program."), _("\
5415 Show the MIPS ABI used by this program."), _("\
5416 This option can be set to one of:\n\
5417 auto - the default ABI associated with the current binary\n\
5426 &setmipscmdlist
, &showmipscmdlist
);
5428 /* Let the user turn off floating point and set the fence post for
5429 heuristic_proc_start. */
5431 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5432 _("Set use of MIPS floating-point coprocessor."),
5433 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5434 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5435 _("Select single-precision MIPS floating-point coprocessor."),
5437 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5438 _("Select double-precision MIPS floating-point coprocessor."),
5440 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5441 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5442 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5443 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5444 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
5445 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5446 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5447 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5448 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5449 _("Select MIPS floating-point coprocessor automatically."),
5451 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5452 _("Show current use of MIPS floating-point coprocessor target."),
5455 /* We really would like to have both "0" and "unlimited" work, but
5456 command.c doesn't deal with that. So make it a var_zinteger
5457 because the user can always use "999999" or some such for unlimited. */
5458 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5459 &heuristic_fence_post
, _("\
5460 Set the distance searched for the start of a function."), _("\
5461 Show the distance searched for the start of a function."), _("\
5462 If you are debugging a stripped executable, GDB needs to search through the\n\
5463 program for the start of a function. This command sets the distance of the\n\
5464 search. The only need to set it is when debugging a stripped executable."),
5465 reinit_frame_cache_sfunc
,
5466 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5467 &setlist
, &showlist
);
5469 /* Allow the user to control whether the upper bits of 64-bit
5470 addresses should be zeroed. */
5471 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
5472 &mask_address_var
, _("\
5473 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5474 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5475 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5476 allow GDB to determine the correct value."),
5477 NULL
, show_mask_address
,
5478 &setmipscmdlist
, &showmipscmdlist
);
5480 /* Allow the user to control the size of 32 bit registers within the
5481 raw remote packet. */
5482 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
5483 &mips64_transfers_32bit_regs_p
, _("\
5484 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5486 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5488 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5489 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5490 64 bits for others. Use \"off\" to disable compatibility mode"),
5491 set_mips64_transfers_32bit_regs
,
5492 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
5493 &setlist
, &showlist
);
5495 /* Debug this files internals. */
5496 add_setshow_zinteger_cmd ("mips", class_maintenance
,
5498 Set mips debugging."), _("\
5499 Show mips debugging."), _("\
5500 When non-zero, mips specific debugging is enabled."),
5502 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
5503 &setdebuglist
, &showdebuglist
);