1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
63 static const struct objfile_data
*mips_pdr_data
;
65 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
67 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
68 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
69 #define ST0_FR (1 << 26)
71 /* The sizes of floating point registers. */
75 MIPS_FPU_SINGLE_REGSIZE
= 4,
76 MIPS_FPU_DOUBLE_REGSIZE
= 8
85 static const char *mips_abi_string
;
87 static const char *mips_abi_strings
[] = {
98 /* The standard register names, and all the valid aliases for them. */
105 /* Aliases for o32 and most other ABIs. */
106 const struct register_alias mips_o32_aliases
[] = {
113 /* Aliases for n32 and n64. */
114 const struct register_alias mips_n32_n64_aliases
[] = {
121 /* Aliases for ABI-independent registers. */
122 const struct register_alias mips_register_aliases
[] = {
123 /* The architecture manuals specify these ABI-independent names for
125 #define R(n) { "r" #n, n }
126 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
127 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
128 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
129 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
132 /* k0 and k1 are sometimes called these instead (for "kernel
137 /* This is the traditional GDB name for the CP0 status register. */
138 { "sr", MIPS_PS_REGNUM
},
140 /* This is the traditional GDB name for the CP0 BadVAddr register. */
141 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
143 /* This is the traditional GDB name for the FCSR. */
144 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
147 const struct register_alias mips_numeric_register_aliases
[] = {
148 #define R(n) { #n, n }
149 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
150 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
151 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
152 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
156 #ifndef MIPS_DEFAULT_FPU_TYPE
157 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
159 static int mips_fpu_type_auto
= 1;
160 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
162 static int mips_debug
= 0;
164 /* Properties (for struct target_desc) describing the g/G packet
166 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
167 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
169 struct target_desc
*mips_tdesc_gp32
;
170 struct target_desc
*mips_tdesc_gp64
;
172 const struct mips_regnum
*
173 mips_regnum (struct gdbarch
*gdbarch
)
175 return gdbarch_tdep (gdbarch
)->regnum
;
179 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
181 return mips_regnum (gdbarch
)->fp0
+ 12;
184 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
186 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
188 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
190 #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
192 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
194 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
195 functions to test, set, or clear bit 0 of addresses. */
198 is_mips16_addr (CORE_ADDR addr
)
204 unmake_mips16_addr (CORE_ADDR addr
)
206 return ((addr
) & ~(CORE_ADDR
) 1);
210 make_mips16_addr (CORE_ADDR addr
)
212 return ((addr
) | (CORE_ADDR
) 1);
215 /* Return the MIPS ABI associated with GDBARCH. */
217 mips_abi (struct gdbarch
*gdbarch
)
219 return gdbarch_tdep (gdbarch
)->mips_abi
;
223 mips_isa_regsize (struct gdbarch
*gdbarch
)
225 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
227 /* If we know how big the registers are, use that size. */
228 if (tdep
->register_size_valid_p
)
229 return tdep
->register_size
;
231 /* Fall back to the previous behavior. */
232 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
233 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
236 /* Return the currently configured (or set) saved register size. */
239 mips_abi_regsize (struct gdbarch
*gdbarch
)
241 switch (mips_abi (gdbarch
))
243 case MIPS_ABI_EABI32
:
249 case MIPS_ABI_EABI64
:
251 case MIPS_ABI_UNKNOWN
:
254 internal_error (__FILE__
, __LINE__
, _("bad switch"));
258 /* Functions for setting and testing a bit in a minimal symbol that
259 marks it as 16-bit function. The MSB of the minimal symbol's
260 "info" field is used for this purpose.
262 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
263 i.e. refers to a 16-bit function, and sets a "special" bit in a
264 minimal symbol to mark it as a 16-bit function
266 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
269 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
271 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
273 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
278 msymbol_is_special (struct minimal_symbol
*msym
)
280 return MSYMBOL_TARGET_FLAG_1 (msym
);
283 /* XFER a value from the big/little/left end of the register.
284 Depending on the size of the value it might occupy the entire
285 register or just part of it. Make an allowance for this, aligning
286 things accordingly. */
289 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
290 int reg_num
, int length
,
291 enum bfd_endian endian
, gdb_byte
*in
,
292 const gdb_byte
*out
, int buf_offset
)
296 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
297 /* Need to transfer the left or right part of the register, based on
298 the targets byte order. */
302 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
304 case BFD_ENDIAN_LITTLE
:
307 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
311 internal_error (__FILE__
, __LINE__
, _("bad switch"));
314 fprintf_unfiltered (gdb_stderr
,
315 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
316 reg_num
, reg_offset
, buf_offset
, length
);
317 if (mips_debug
&& out
!= NULL
)
320 fprintf_unfiltered (gdb_stdlog
, "out ");
321 for (i
= 0; i
< length
; i
++)
322 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
325 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
328 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
330 if (mips_debug
&& in
!= NULL
)
333 fprintf_unfiltered (gdb_stdlog
, "in ");
334 for (i
= 0; i
< length
; i
++)
335 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
338 fprintf_unfiltered (gdb_stdlog
, "\n");
341 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
342 compatiblity mode. A return value of 1 means that we have
343 physical 64-bit registers, but should treat them as 32-bit registers. */
346 mips2_fp_compat (struct frame_info
*frame
)
348 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
349 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
351 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
355 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
356 in all the places we deal with FP registers. PR gdb/413. */
357 /* Otherwise check the FR bit in the status register - it controls
358 the FP compatiblity mode. If it is clear we are in compatibility
360 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
367 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
369 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
371 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
373 /* The list of available "set mips " and "show mips " commands */
375 static struct cmd_list_element
*setmipscmdlist
= NULL
;
376 static struct cmd_list_element
*showmipscmdlist
= NULL
;
378 /* Integer registers 0 thru 31 are handled explicitly by
379 mips_register_name(). Processor specific registers 32 and above
380 are listed in the following tables. */
383 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
387 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
388 "sr", "lo", "hi", "bad", "cause", "pc",
389 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
390 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
391 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
392 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
393 "fsr", "fir", "" /*"fp" */ , "",
394 "", "", "", "", "", "", "", "",
395 "", "", "", "", "", "", "", "",
398 /* Names of IDT R3041 registers. */
400 static const char *mips_r3041_reg_names
[] = {
401 "sr", "lo", "hi", "bad", "cause", "pc",
402 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
403 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
404 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
405 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
406 "fsr", "fir", "", /*"fp" */ "",
407 "", "", "bus", "ccfg", "", "", "", "",
408 "", "", "port", "cmp", "", "", "epc", "prid",
411 /* Names of tx39 registers. */
413 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
414 "sr", "lo", "hi", "bad", "cause", "pc",
415 "", "", "", "", "", "", "", "",
416 "", "", "", "", "", "", "", "",
417 "", "", "", "", "", "", "", "",
418 "", "", "", "", "", "", "", "",
420 "", "", "", "", "", "", "", "",
421 "", "", "config", "cache", "debug", "depc", "epc", ""
424 /* Names of IRIX registers. */
425 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
426 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
427 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
428 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
429 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
430 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
434 /* Return the name of the register corresponding to REGNO. */
436 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
438 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
439 /* GPR names for all ABIs other than n32/n64. */
440 static char *mips_gpr_names
[] = {
441 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
442 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
443 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
444 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
447 /* GPR names for n32 and n64 ABIs. */
448 static char *mips_n32_n64_gpr_names
[] = {
449 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
450 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
451 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
452 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
455 enum mips_abi abi
= mips_abi (gdbarch
);
457 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
458 but then don't make the raw register names visible. This (upper)
459 range of user visible register numbers are the pseudo-registers.
461 This approach was adopted accommodate the following scenario:
462 It is possible to debug a 64-bit device using a 32-bit
463 programming model. In such instances, the raw registers are
464 configured to be 64-bits wide, while the pseudo registers are
465 configured to be 32-bits wide. The registers that the user
466 sees - the pseudo registers - match the users expectations
467 given the programming model being used. */
468 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
469 if (regno
< gdbarch_num_regs (gdbarch
))
472 /* The MIPS integer registers are always mapped from 0 to 31. The
473 names of the registers (which reflects the conventions regarding
474 register use) vary depending on the ABI. */
475 if (0 <= rawnum
&& rawnum
< 32)
477 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
478 return mips_n32_n64_gpr_names
[rawnum
];
480 return mips_gpr_names
[rawnum
];
482 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
483 return tdesc_register_name (gdbarch
, rawnum
);
484 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
486 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
487 return tdep
->mips_processor_reg_names
[rawnum
- 32];
490 internal_error (__FILE__
, __LINE__
,
491 _("mips_register_name: bad register number %d"), rawnum
);
494 /* Return the groups that a MIPS register can be categorised into. */
497 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
498 struct reggroup
*reggroup
)
503 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
504 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
505 if (reggroup
== all_reggroup
)
507 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
508 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
509 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
510 (gdbarch), as not all architectures are multi-arch. */
511 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
512 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
513 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
515 if (reggroup
== float_reggroup
)
516 return float_p
&& pseudo
;
517 if (reggroup
== vector_reggroup
)
518 return vector_p
&& pseudo
;
519 if (reggroup
== general_reggroup
)
520 return (!vector_p
&& !float_p
) && pseudo
;
521 /* Save the pseudo registers. Need to make certain that any code
522 extracting register values from a saved register cache also uses
524 if (reggroup
== save_reggroup
)
525 return raw_p
&& pseudo
;
526 /* Restore the same pseudo register. */
527 if (reggroup
== restore_reggroup
)
528 return raw_p
&& pseudo
;
532 /* Return the groups that a MIPS register can be categorised into.
533 This version is only used if we have a target description which
534 describes real registers (and their groups). */
537 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
538 struct reggroup
*reggroup
)
540 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
541 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
544 /* Only save, restore, and display the pseudo registers. Need to
545 make certain that any code extracting register values from a
546 saved register cache also uses pseudo registers.
548 Note: saving and restoring the pseudo registers is slightly
549 strange; if we have 64 bits, we should save and restore all
550 64 bits. But this is hard and has little benefit. */
554 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
558 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
561 /* Map the symbol table registers which live in the range [1 *
562 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
563 registers. Take care of alignment and size problems. */
566 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
567 int cookednum
, gdb_byte
*buf
)
569 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
570 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
571 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
572 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
573 regcache_raw_read (regcache
, rawnum
, buf
);
574 else if (register_size (gdbarch
, rawnum
) >
575 register_size (gdbarch
, cookednum
))
577 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
578 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
581 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
583 regcache_raw_read_signed (regcache
, rawnum
, ®val
);
584 store_signed_integer (buf
, 4, byte_order
, regval
);
588 internal_error (__FILE__
, __LINE__
, _("bad register size"));
592 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
593 struct regcache
*regcache
, int cookednum
,
596 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
597 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
598 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
599 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
600 regcache_raw_write (regcache
, rawnum
, buf
);
601 else if (register_size (gdbarch
, rawnum
) >
602 register_size (gdbarch
, cookednum
))
604 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
605 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
608 /* Sign extend the shortened version of the register prior
609 to placing it in the raw register. This is required for
610 some mips64 parts in order to avoid unpredictable behavior. */
611 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
612 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
613 regcache_raw_write_signed (regcache
, rawnum
, regval
);
617 internal_error (__FILE__
, __LINE__
, _("bad register size"));
621 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
622 struct agent_expr
*ax
, int reg
)
624 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
625 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
626 && reg
< 2 * gdbarch_num_regs (gdbarch
));
628 ax_reg_mask (ax
, rawnum
);
634 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
635 struct agent_expr
*ax
, int reg
)
637 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
638 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
639 && reg
< 2 * gdbarch_num_regs (gdbarch
));
640 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
644 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
646 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
647 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
650 ax_simple (ax
, aop_lsh
);
653 ax_simple (ax
, aop_rsh_signed
);
657 internal_error (__FILE__
, __LINE__
, _("bad register size"));
662 /* Table to translate MIPS16 register field to actual register number. */
663 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
665 /* Heuristic_proc_start may hunt through the text section for a long
666 time across a 2400 baud serial line. Allows the user to limit this
669 static unsigned int heuristic_fence_post
= 0;
671 /* Number of bytes of storage in the actual machine representation for
672 register N. NOTE: This defines the pseudo register type so need to
673 rebuild the architecture vector. */
675 static int mips64_transfers_32bit_regs_p
= 0;
678 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
679 struct cmd_list_element
*c
)
681 struct gdbarch_info info
;
682 gdbarch_info_init (&info
);
683 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
684 instead of relying on globals. Doing that would let generic code
685 handle the search for this specific architecture. */
686 if (!gdbarch_update_p (info
))
688 mips64_transfers_32bit_regs_p
= 0;
689 error (_("32-bit compatibility mode not supported"));
693 /* Convert to/from a register and the corresponding memory value. */
695 /* This predicate tests for the case of an 8 byte floating point
696 value that is being transferred to or from a pair of floating point
697 registers each of which are (or are considered to be) only 4 bytes
700 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
703 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
704 && register_size (gdbarch
, regnum
) == 4
705 && (regnum
% gdbarch_num_regs (gdbarch
))
706 >= mips_regnum (gdbarch
)->fp0
707 && (regnum
% gdbarch_num_regs (gdbarch
))
708 < mips_regnum (gdbarch
)->fp0
+ 32
709 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
712 /* This predicate tests for the case of a value of less than 8
713 bytes in width that is being transfered to or from an 8 byte
714 general purpose register. */
716 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
719 int num_regs
= gdbarch_num_regs (gdbarch
);
721 return (register_size (gdbarch
, regnum
) == 8
722 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
723 && TYPE_LENGTH (type
) < 8);
727 mips_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
729 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
730 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
734 mips_register_to_value (struct frame_info
*frame
, int regnum
,
735 struct type
*type
, gdb_byte
*to
)
737 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
739 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
741 get_frame_register (frame
, regnum
+ 0, to
+ 4);
742 get_frame_register (frame
, regnum
+ 1, to
+ 0);
744 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
746 int len
= TYPE_LENGTH (type
);
747 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
748 get_frame_register_bytes (frame
, regnum
, 8 - len
, len
, to
);
750 get_frame_register_bytes (frame
, regnum
, 0, len
, to
);
754 internal_error (__FILE__
, __LINE__
,
755 _("mips_register_to_value: unrecognized case"));
760 mips_value_to_register (struct frame_info
*frame
, int regnum
,
761 struct type
*type
, const gdb_byte
*from
)
763 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
765 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
767 put_frame_register (frame
, regnum
+ 0, from
+ 4);
768 put_frame_register (frame
, regnum
+ 1, from
+ 0);
770 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
773 int len
= TYPE_LENGTH (type
);
775 /* Sign extend values, irrespective of type, that are stored to
776 a 64-bit general purpose register. (32-bit unsigned values
777 are stored as signed quantities within a 64-bit register.
778 When performing an operation, in compiled code, that combines
779 a 32-bit unsigned value with a signed 64-bit value, a type
780 conversion is first performed that zeroes out the high 32 bits.) */
781 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
784 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
786 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
787 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
788 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
792 if (from
[len
-1] & 0x80)
793 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
795 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
796 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
797 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
802 internal_error (__FILE__
, __LINE__
,
803 _("mips_value_to_register: unrecognized case"));
807 /* Return the GDB type object for the "standard" data type of data in
811 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
813 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
814 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
815 && (regnum
% gdbarch_num_regs (gdbarch
))
816 < mips_regnum (gdbarch
)->fp0
+ 32)
818 /* The floating-point registers raw, or cooked, always match
819 mips_isa_regsize(), and also map 1:1, byte for byte. */
820 if (mips_isa_regsize (gdbarch
) == 4)
821 return builtin_type (gdbarch
)->builtin_float
;
823 return builtin_type (gdbarch
)->builtin_double
;
825 else if (regnum
< gdbarch_num_regs (gdbarch
))
827 /* The raw or ISA registers. These are all sized according to
829 if (mips_isa_regsize (gdbarch
) == 4)
830 return builtin_type (gdbarch
)->builtin_int32
;
832 return builtin_type (gdbarch
)->builtin_int64
;
836 /* The cooked or ABI registers. These are sized according to
837 the ABI (with a few complications). */
838 if (regnum
>= (gdbarch_num_regs (gdbarch
)
839 + mips_regnum (gdbarch
)->fp_control_status
)
840 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
841 /* The pseudo/cooked view of the embedded registers is always
842 32-bit. The raw view is handled below. */
843 return builtin_type (gdbarch
)->builtin_int32
;
844 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
845 /* The target, while possibly using a 64-bit register buffer,
846 is only transfering 32-bits of each integer register.
847 Reflect this in the cooked/pseudo (ABI) register value. */
848 return builtin_type (gdbarch
)->builtin_int32
;
849 else if (mips_abi_regsize (gdbarch
) == 4)
850 /* The ABI is restricted to 32-bit registers (the ISA could be
852 return builtin_type (gdbarch
)->builtin_int32
;
855 return builtin_type (gdbarch
)->builtin_int64
;
859 /* Return the GDB type for the pseudo register REGNUM, which is the
860 ABI-level view. This function is only called if there is a target
861 description which includes registers, so we know precisely the
862 types of hardware registers. */
865 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
867 const int num_regs
= gdbarch_num_regs (gdbarch
);
868 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
869 int rawnum
= regnum
% num_regs
;
870 struct type
*rawtype
;
872 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
874 /* Absent registers are still absent. */
875 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
876 if (TYPE_LENGTH (rawtype
) == 0)
879 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
880 /* Present the floating point registers however the hardware did;
881 do not try to convert between FPU layouts. */
884 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
886 /* The pseudo/cooked view of embedded registers is always
887 32-bit, even if the target transfers 64-bit values for them.
888 New targets relying on XML descriptions should only transfer
889 the necessary 32 bits, but older versions of GDB expected 64,
890 so allow the target to provide 64 bits without interfering
891 with the displayed type. */
892 return builtin_type (gdbarch
)->builtin_int32
;
895 /* Use pointer types for registers if we can. For n32 we can not,
896 since we do not have a 64-bit pointer type. */
897 if (mips_abi_regsize (gdbarch
)
898 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
900 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
901 return builtin_type (gdbarch
)->builtin_data_ptr
;
902 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
903 return builtin_type (gdbarch
)->builtin_func_ptr
;
906 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
907 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
908 return builtin_type (gdbarch
)->builtin_int32
;
910 /* For all other registers, pass through the hardware type. */
914 /* Should the upper word of 64-bit addresses be zeroed? */
915 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
918 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
920 switch (mask_address_var
)
922 case AUTO_BOOLEAN_TRUE
:
924 case AUTO_BOOLEAN_FALSE
:
927 case AUTO_BOOLEAN_AUTO
:
928 return tdep
->default_mask_address_p
;
930 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
936 show_mask_address (struct ui_file
*file
, int from_tty
,
937 struct cmd_list_element
*c
, const char *value
)
939 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
941 deprecated_show_value_hack (file
, from_tty
, c
, value
);
942 switch (mask_address_var
)
944 case AUTO_BOOLEAN_TRUE
:
945 printf_filtered ("The 32 bit mips address mask is enabled\n");
947 case AUTO_BOOLEAN_FALSE
:
948 printf_filtered ("The 32 bit mips address mask is disabled\n");
950 case AUTO_BOOLEAN_AUTO
:
952 ("The 32 bit address mask is set automatically. Currently %s\n",
953 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
956 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
961 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
964 mips_pc_is_mips16 (CORE_ADDR memaddr
)
966 struct minimal_symbol
*sym
;
968 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
969 if (is_mips16_addr (memaddr
))
972 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
973 the high bit of the info field. Use this to decide if the function is
974 MIPS16 or normal MIPS. */
975 sym
= lookup_minimal_symbol_by_pc (memaddr
);
977 return msymbol_is_special (sym
);
982 /* MIPS believes that the PC has a sign extended value. Perhaps the
983 all registers should be sign extended for simplicity? */
986 mips_read_pc (struct regcache
*regcache
)
989 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
990 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
991 if (is_mips16_addr (pc
))
992 pc
= unmake_mips16_addr (pc
);
997 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1001 pc
= frame_unwind_register_signed
1002 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
1003 if (is_mips16_addr (pc
))
1004 pc
= unmake_mips16_addr (pc
);
1009 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1011 return frame_unwind_register_signed
1012 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1015 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1016 dummy frame. The frame ID's base needs to match the TOS value
1017 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1020 static struct frame_id
1021 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1023 return frame_id_build
1024 (get_frame_register_signed (this_frame
,
1025 gdbarch_num_regs (gdbarch
)
1027 get_frame_pc (this_frame
));
1031 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1033 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1034 if (mips_pc_is_mips16 (pc
))
1035 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
1037 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1040 /* Fetch and return instruction from the specified location. If the PC
1041 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1044 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1046 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1047 gdb_byte buf
[MIPS_INSN32_SIZE
];
1051 if (mips_pc_is_mips16 (addr
))
1053 instlen
= MIPS_INSN16_SIZE
;
1054 addr
= unmake_mips16_addr (addr
);
1057 instlen
= MIPS_INSN32_SIZE
;
1058 status
= target_read_memory (addr
, buf
, instlen
);
1060 memory_error (status
, addr
);
1061 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1064 /* These the fields of 32 bit mips instructions */
1065 #define mips32_op(x) (x >> 26)
1066 #define itype_op(x) (x >> 26)
1067 #define itype_rs(x) ((x >> 21) & 0x1f)
1068 #define itype_rt(x) ((x >> 16) & 0x1f)
1069 #define itype_immediate(x) (x & 0xffff)
1071 #define jtype_op(x) (x >> 26)
1072 #define jtype_target(x) (x & 0x03ffffff)
1074 #define rtype_op(x) (x >> 26)
1075 #define rtype_rs(x) ((x >> 21) & 0x1f)
1076 #define rtype_rt(x) ((x >> 16) & 0x1f)
1077 #define rtype_rd(x) ((x >> 11) & 0x1f)
1078 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1079 #define rtype_funct(x) (x & 0x3f)
1082 mips32_relative_offset (ULONGEST inst
)
1084 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1087 /* Determine where to set a single step breakpoint while considering
1088 branch prediction. */
1090 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1092 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1095 inst
= mips_fetch_instruction (gdbarch
, pc
);
1096 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1098 if (itype_op (inst
) >> 2 == 5)
1099 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1101 op
= (itype_op (inst
) & 0x03);
1111 goto greater_branch
;
1116 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1117 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1119 int tf
= itype_rt (inst
) & 0x01;
1120 int cnum
= itype_rt (inst
) >> 2;
1122 get_frame_register_signed (frame
,
1123 mips_regnum (get_frame_arch (frame
))->
1125 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1127 if (((cond
>> cnum
) & 0x01) == tf
)
1128 pc
+= mips32_relative_offset (inst
) + 4;
1133 pc
+= 4; /* Not a branch, next instruction is easy */
1136 { /* This gets way messy */
1138 /* Further subdivide into SPECIAL, REGIMM and other */
1139 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1141 case 0: /* SPECIAL */
1142 op
= rtype_funct (inst
);
1147 /* Set PC to that address */
1148 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1150 case 12: /* SYSCALL */
1152 struct gdbarch_tdep
*tdep
;
1154 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1155 if (tdep
->syscall_next_pc
!= NULL
)
1156 pc
= tdep
->syscall_next_pc (frame
);
1165 break; /* end SPECIAL */
1166 case 1: /* REGIMM */
1168 op
= itype_rt (inst
); /* branch condition */
1173 case 16: /* BLTZAL */
1174 case 18: /* BLTZALL */
1176 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1177 pc
+= mips32_relative_offset (inst
) + 4;
1179 pc
+= 8; /* after the delay slot */
1183 case 17: /* BGEZAL */
1184 case 19: /* BGEZALL */
1185 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1186 pc
+= mips32_relative_offset (inst
) + 4;
1188 pc
+= 8; /* after the delay slot */
1190 /* All of the other instructions in the REGIMM category */
1195 break; /* end REGIMM */
1200 reg
= jtype_target (inst
) << 2;
1201 /* Upper four bits get never changed... */
1202 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1205 /* FIXME case JALX : */
1208 reg
= jtype_target (inst
) << 2;
1209 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1210 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1212 break; /* The new PC will be alternate mode */
1213 case 4: /* BEQ, BEQL */
1215 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1216 get_frame_register_signed (frame
, itype_rt (inst
)))
1217 pc
+= mips32_relative_offset (inst
) + 4;
1221 case 5: /* BNE, BNEL */
1223 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1224 get_frame_register_signed (frame
, itype_rt (inst
)))
1225 pc
+= mips32_relative_offset (inst
) + 4;
1229 case 6: /* BLEZ, BLEZL */
1230 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1231 pc
+= mips32_relative_offset (inst
) + 4;
1237 greater_branch
: /* BGTZ, BGTZL */
1238 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1239 pc
+= mips32_relative_offset (inst
) + 4;
1246 } /* mips32_next_pc */
1248 /* Decoding the next place to set a breakpoint is irregular for the
1249 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1250 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1251 We dont want to set a single step instruction on the extend instruction
1255 /* Lots of mips16 instruction formats */
1256 /* Predicting jumps requires itype,ritype,i8type
1257 and their extensions extItype,extritype,extI8type
1259 enum mips16_inst_fmts
1261 itype
, /* 0 immediate 5,10 */
1262 ritype
, /* 1 5,3,8 */
1263 rrtype
, /* 2 5,3,3,5 */
1264 rritype
, /* 3 5,3,3,5 */
1265 rrrtype
, /* 4 5,3,3,3,2 */
1266 rriatype
, /* 5 5,3,3,1,4 */
1267 shifttype
, /* 6 5,3,3,3,2 */
1268 i8type
, /* 7 5,3,8 */
1269 i8movtype
, /* 8 5,3,3,5 */
1270 i8mov32rtype
, /* 9 5,3,5,3 */
1271 i64type
, /* 10 5,3,8 */
1272 ri64type
, /* 11 5,3,3,5 */
1273 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1274 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1275 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1276 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1277 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1278 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1279 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1280 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1281 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1282 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1284 /* I am heaping all the fields of the formats into one structure and
1285 then, only the fields which are involved in instruction extension */
1289 unsigned int regx
; /* Function in i8 type */
1294 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1295 for the bits which make up the immediate extension. */
1298 extended_offset (unsigned int extension
)
1301 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1303 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1305 value
|= extension
& 0x01f; /* extract 4:0 */
1309 /* Only call this function if you know that this is an extendable
1310 instruction. It won't malfunction, but why make excess remote memory
1311 references? If the immediate operands get sign extended or something,
1312 do it after the extension is performed. */
1313 /* FIXME: Every one of these cases needs to worry about sign extension
1314 when the offset is to be used in relative addressing. */
1317 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1319 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1321 pc
&= 0xfffffffe; /* clear the low order bit */
1322 target_read_memory (pc
, buf
, 2);
1323 return extract_unsigned_integer (buf
, 2, byte_order
);
1327 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1328 unsigned int extension
,
1330 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1335 switch (insn_format
)
1342 value
= extended_offset (extension
);
1343 value
= value
<< 11; /* rom for the original value */
1344 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1348 value
= inst
& 0x7ff;
1349 /* FIXME : Consider sign extension */
1358 { /* A register identifier and an offset */
1359 /* Most of the fields are the same as I type but the
1360 immediate value is of a different length */
1364 value
= extended_offset (extension
);
1365 value
= value
<< 8; /* from the original instruction */
1366 value
|= inst
& 0xff; /* eleven bits from instruction */
1367 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1368 if (value
& 0x4000) /* test the sign bit , bit 26 */
1370 value
&= ~0x3fff; /* remove the sign bit */
1376 value
= inst
& 0xff; /* 8 bits */
1377 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1378 /* FIXME: Do sign extension , this format needs it */
1379 if (value
& 0x80) /* THIS CONFUSES ME */
1381 value
&= 0xef; /* remove the sign bit */
1391 unsigned long value
;
1392 unsigned int nexthalf
;
1393 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1394 value
= value
<< 16;
1395 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit still set */
1403 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1405 upk
->offset
= offset
;
1412 add_offset_16 (CORE_ADDR pc
, int offset
)
1414 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1418 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1419 unsigned int extension
, unsigned int insn
)
1421 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1422 int op
= (insn
>> 11);
1425 case 2: /* Branch */
1428 struct upk_mips16 upk
;
1429 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1430 offset
= upk
.offset
;
1436 pc
+= (offset
<< 1) + 2;
1439 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1441 struct upk_mips16 upk
;
1442 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1443 pc
= add_offset_16 (pc
, upk
.offset
);
1444 if ((insn
>> 10) & 0x01) /* Exchange mode */
1445 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1452 struct upk_mips16 upk
;
1454 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1455 reg
= get_frame_register_signed (frame
, upk
.regx
);
1457 pc
+= (upk
.offset
<< 1) + 2;
1464 struct upk_mips16 upk
;
1466 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1467 reg
= get_frame_register_signed (frame
, upk
.regx
);
1469 pc
+= (upk
.offset
<< 1) + 2;
1474 case 12: /* I8 Formats btez btnez */
1476 struct upk_mips16 upk
;
1478 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1479 /* upk.regx contains the opcode */
1480 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1481 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1482 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1483 /* pc = add_offset_16(pc,upk.offset) ; */
1484 pc
+= (upk
.offset
<< 1) + 2;
1489 case 29: /* RR Formats JR, JALR, JALR-RA */
1491 struct upk_mips16 upk
;
1492 /* upk.fmt = rrtype; */
1497 upk
.regx
= (insn
>> 8) & 0x07;
1498 upk
.regy
= (insn
>> 5) & 0x07;
1506 break; /* Function return instruction */
1512 break; /* BOGUS Guess */
1514 pc
= get_frame_register_signed (frame
, reg
);
1521 /* This is an instruction extension. Fetch the real instruction
1522 (which follows the extension) and decode things based on
1526 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1527 fetch_mips_16 (gdbarch
, pc
));
1540 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1542 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1543 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1544 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1547 /* The mips_next_pc function supports single_step when the remote
1548 target monitor or stub is not developed enough to do a single_step.
1549 It works by decoding the current instruction and predicting where a
1550 branch will go. This isnt hard because all the data is available.
1551 The MIPS32 and MIPS16 variants are quite different. */
1553 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1555 if (is_mips16_addr (pc
))
1556 return mips16_next_pc (frame
, pc
);
1558 return mips32_next_pc (frame
, pc
);
1561 struct mips_frame_cache
1564 struct trad_frame_saved_reg
*saved_regs
;
1567 /* Set a register's saved stack address in temp_saved_regs. If an
1568 address has already been set for this register, do nothing; this
1569 way we will only recognize the first save of a given register in a
1572 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1573 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1574 Strictly speaking, only the second range is used as it is only second
1575 range (the ABI instead of ISA registers) that comes into play when finding
1576 saved registers in a frame. */
1579 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1580 int regnum
, CORE_ADDR offset
)
1582 if (this_cache
!= NULL
1583 && this_cache
->saved_regs
[regnum
].addr
== -1)
1585 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1587 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1593 /* Fetch the immediate value from a MIPS16 instruction.
1594 If the previous instruction was an EXTEND, use it to extend
1595 the upper bits of the immediate value. This is a helper function
1596 for mips16_scan_prologue. */
1599 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1600 unsigned short inst
, /* current instruction */
1601 int nbits
, /* number of bits in imm field */
1602 int scale
, /* scale factor to be applied to imm */
1603 int is_signed
) /* is the imm field signed? */
1607 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1609 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1610 if (offset
& 0x8000) /* check for negative extend */
1611 offset
= 0 - (0x10000 - (offset
& 0xffff));
1612 return offset
| (inst
& 0x1f);
1616 int max_imm
= 1 << nbits
;
1617 int mask
= max_imm
- 1;
1618 int sign_bit
= max_imm
>> 1;
1620 offset
= inst
& mask
;
1621 if (is_signed
&& (offset
& sign_bit
))
1622 offset
= 0 - (max_imm
- offset
);
1623 return offset
* scale
;
1628 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1629 the associated FRAME_CACHE if not null.
1630 Return the address of the first instruction past the prologue. */
1633 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1634 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1635 struct frame_info
*this_frame
,
1636 struct mips_frame_cache
*this_cache
)
1639 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1641 long frame_offset
= 0; /* Size of stack frame. */
1642 long frame_adjust
= 0; /* Offset of FP from SP. */
1643 int frame_reg
= MIPS_SP_REGNUM
;
1644 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1645 unsigned inst
= 0; /* current instruction */
1646 unsigned entry_inst
= 0; /* the entry instruction */
1647 unsigned save_inst
= 0; /* the save instruction */
1650 int extend_bytes
= 0;
1651 int prev_extend_bytes
;
1652 CORE_ADDR end_prologue_addr
= 0;
1654 /* Can be called when there's no process, and hence when there's no
1656 if (this_frame
!= NULL
)
1657 sp
= get_frame_register_signed (this_frame
,
1658 gdbarch_num_regs (gdbarch
)
1663 if (limit_pc
> start_pc
+ 200)
1664 limit_pc
= start_pc
+ 200;
1666 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1668 /* Save the previous instruction. If it's an EXTEND, we'll extract
1669 the immediate offset extension from it in mips16_get_imm. */
1672 /* Fetch and decode the instruction. */
1673 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1675 /* Normally we ignore extend instructions. However, if it is
1676 not followed by a valid prologue instruction, then this
1677 instruction is not part of the prologue either. We must
1678 remember in this case to adjust the end_prologue_addr back
1680 if ((inst
& 0xf800) == 0xf000) /* extend */
1682 extend_bytes
= MIPS_INSN16_SIZE
;
1686 prev_extend_bytes
= extend_bytes
;
1689 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1690 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1692 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1693 if (offset
< 0) /* negative stack adjustment? */
1694 frame_offset
-= offset
;
1696 /* Exit loop if a positive stack adjustment is found, which
1697 usually means that the stack cleanup code in the function
1698 epilogue is reached. */
1701 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1703 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1704 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1705 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1707 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1709 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1710 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1711 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1713 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1715 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1716 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1718 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1720 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1721 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1723 else if (inst
== 0x673d) /* move $s1, $sp */
1728 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1730 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1731 frame_addr
= sp
+ offset
;
1733 frame_adjust
= offset
;
1735 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1737 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1738 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1739 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1741 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1743 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1744 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1745 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1747 else if ((inst
& 0xf81f) == 0xe809
1748 && (inst
& 0x700) != 0x700) /* entry */
1749 entry_inst
= inst
; /* save for later processing */
1750 else if ((inst
& 0xff80) == 0x6480) /* save */
1752 save_inst
= inst
; /* save for later processing */
1753 if (prev_extend_bytes
) /* extend */
1754 save_inst
|= prev_inst
<< 16;
1756 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1757 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1758 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1760 /* This instruction is part of the prologue, but we don't
1761 need to do anything special to handle it. */
1765 /* This instruction is not an instruction typically found
1766 in a prologue, so we must have reached the end of the
1768 if (end_prologue_addr
== 0)
1769 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1773 /* The entry instruction is typically the first instruction in a function,
1774 and it stores registers at offsets relative to the value of the old SP
1775 (before the prologue). But the value of the sp parameter to this
1776 function is the new SP (after the prologue has been executed). So we
1777 can't calculate those offsets until we've seen the entire prologue,
1778 and can calculate what the old SP must have been. */
1779 if (entry_inst
!= 0)
1781 int areg_count
= (entry_inst
>> 8) & 7;
1782 int sreg_count
= (entry_inst
>> 6) & 3;
1784 /* The entry instruction always subtracts 32 from the SP. */
1787 /* Now we can calculate what the SP must have been at the
1788 start of the function prologue. */
1791 /* Check if a0-a3 were saved in the caller's argument save area. */
1792 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1794 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1795 offset
+= mips_abi_regsize (gdbarch
);
1798 /* Check if the ra register was pushed on the stack. */
1800 if (entry_inst
& 0x20)
1802 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1803 offset
-= mips_abi_regsize (gdbarch
);
1806 /* Check if the s0 and s1 registers were pushed on the stack. */
1807 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1809 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1810 offset
-= mips_abi_regsize (gdbarch
);
1814 /* The SAVE instruction is similar to ENTRY, except that defined by the
1815 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1816 size of the frame is specified as an immediate field of instruction
1817 and an extended variation exists which lets additional registers and
1818 frame space to be specified. The instruction always treats registers
1819 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1820 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1822 static int args_table
[16] = {
1823 0, 0, 0, 0, 1, 1, 1, 1,
1824 2, 2, 2, 0, 3, 3, 4, -1,
1826 static int astatic_table
[16] = {
1827 0, 1, 2, 3, 0, 1, 2, 3,
1828 0, 1, 2, 4, 0, 1, 0, -1,
1830 int aregs
= (save_inst
>> 16) & 0xf;
1831 int xsregs
= (save_inst
>> 24) & 0x7;
1832 int args
= args_table
[aregs
];
1833 int astatic
= astatic_table
[aregs
];
1838 warning (_("Invalid number of argument registers encoded in SAVE."));
1843 warning (_("Invalid number of static registers encoded in SAVE."));
1847 /* For standard SAVE the frame size of 0 means 128. */
1848 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1849 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1852 frame_offset
+= frame_size
;
1854 /* Now we can calculate what the SP must have been at the
1855 start of the function prologue. */
1858 /* Check if A0-A3 were saved in the caller's argument save area. */
1859 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1861 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1862 offset
+= mips_abi_regsize (gdbarch
);
1867 /* Check if the RA register was pushed on the stack. */
1868 if (save_inst
& 0x40)
1870 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1871 offset
-= mips_abi_regsize (gdbarch
);
1874 /* Check if the S8 register was pushed on the stack. */
1877 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1878 offset
-= mips_abi_regsize (gdbarch
);
1881 /* Check if S2-S7 were pushed on the stack. */
1882 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1884 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1885 offset
-= mips_abi_regsize (gdbarch
);
1888 /* Check if the S1 register was pushed on the stack. */
1889 if (save_inst
& 0x10)
1891 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1892 offset
-= mips_abi_regsize (gdbarch
);
1894 /* Check if the S0 register was pushed on the stack. */
1895 if (save_inst
& 0x20)
1897 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1898 offset
-= mips_abi_regsize (gdbarch
);
1901 /* Check if A0-A3 were pushed on the stack. */
1902 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1904 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1905 offset
-= mips_abi_regsize (gdbarch
);
1909 if (this_cache
!= NULL
)
1912 (get_frame_register_signed (this_frame
,
1913 gdbarch_num_regs (gdbarch
) + frame_reg
)
1914 + frame_offset
- frame_adjust
);
1915 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1916 be able to get rid of the assignment below, evetually. But it's
1917 still needed for now. */
1918 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1919 + mips_regnum (gdbarch
)->pc
]
1920 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1923 /* If we didn't reach the end of the prologue when scanning the function
1924 instructions, then set end_prologue_addr to the address of the
1925 instruction immediately after the last one we scanned. */
1926 if (end_prologue_addr
== 0)
1927 end_prologue_addr
= cur_pc
;
1929 return end_prologue_addr
;
1932 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1933 Procedures that use the 32-bit instruction set are handled by the
1934 mips_insn32 unwinder. */
1936 static struct mips_frame_cache
*
1937 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1939 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1940 struct mips_frame_cache
*cache
;
1942 if ((*this_cache
) != NULL
)
1943 return (*this_cache
);
1944 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1945 (*this_cache
) = cache
;
1946 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1948 /* Analyze the function prologue. */
1950 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1951 CORE_ADDR start_addr
;
1953 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1954 if (start_addr
== 0)
1955 start_addr
= heuristic_proc_start (gdbarch
, pc
);
1956 /* We can't analyze the prologue if we couldn't find the begining
1958 if (start_addr
== 0)
1961 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
1964 /* gdbarch_sp_regnum contains the value and not the address. */
1965 trad_frame_set_value (cache
->saved_regs
,
1966 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
1969 return (*this_cache
);
1973 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1974 struct frame_id
*this_id
)
1976 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1978 /* This marks the outermost frame. */
1979 if (info
->base
== 0)
1981 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
1984 static struct value
*
1985 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
1986 void **this_cache
, int regnum
)
1988 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1990 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1994 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
1995 struct frame_info
*this_frame
, void **this_cache
)
1997 CORE_ADDR pc
= get_frame_pc (this_frame
);
1998 if (mips_pc_is_mips16 (pc
))
2003 static const struct frame_unwind mips_insn16_frame_unwind
=
2006 mips_insn16_frame_this_id
,
2007 mips_insn16_frame_prev_register
,
2009 mips_insn16_frame_sniffer
2013 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2016 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2021 static const struct frame_base mips_insn16_frame_base
=
2023 &mips_insn16_frame_unwind
,
2024 mips_insn16_frame_base_address
,
2025 mips_insn16_frame_base_address
,
2026 mips_insn16_frame_base_address
2029 static const struct frame_base
*
2030 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2032 CORE_ADDR pc
= get_frame_pc (this_frame
);
2033 if (mips_pc_is_mips16 (pc
))
2034 return &mips_insn16_frame_base
;
2039 /* Mark all the registers as unset in the saved_regs array
2040 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2043 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
2045 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2049 const int num_regs
= gdbarch_num_regs (gdbarch
);
2052 for (i
= 0; i
< num_regs
; i
++)
2054 this_cache
->saved_regs
[i
].addr
= -1;
2059 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2060 the associated FRAME_CACHE if not null.
2061 Return the address of the first instruction past the prologue. */
2064 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2065 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2066 struct frame_info
*this_frame
,
2067 struct mips_frame_cache
*this_cache
)
2070 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2073 int frame_reg
= MIPS_SP_REGNUM
;
2075 CORE_ADDR end_prologue_addr
= 0;
2076 int seen_sp_adjust
= 0;
2077 int load_immediate_bytes
= 0;
2078 int in_delay_slot
= 0;
2079 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2081 /* Can be called when there's no process, and hence when there's no
2083 if (this_frame
!= NULL
)
2084 sp
= get_frame_register_signed (this_frame
,
2085 gdbarch_num_regs (gdbarch
)
2090 if (limit_pc
> start_pc
+ 200)
2091 limit_pc
= start_pc
+ 200;
2096 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2098 unsigned long inst
, high_word
, low_word
;
2101 /* Fetch the instruction. */
2102 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2104 /* Save some code by pre-extracting some useful fields. */
2105 high_word
= (inst
>> 16) & 0xffff;
2106 low_word
= inst
& 0xffff;
2107 reg
= high_word
& 0x1f;
2109 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2110 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2111 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2113 if (low_word
& 0x8000) /* negative stack adjustment? */
2114 frame_offset
+= 0x10000 - low_word
;
2116 /* Exit loop if a positive stack adjustment is found, which
2117 usually means that the stack cleanup code in the function
2118 epilogue is reached. */
2122 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2123 && !regsize_is_64_bits
)
2125 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2127 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2128 && regsize_is_64_bits
)
2130 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2131 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2133 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2135 /* Old gcc frame, r30 is virtual frame pointer. */
2136 if ((long) low_word
!= frame_offset
)
2137 frame_addr
= sp
+ low_word
;
2138 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2140 unsigned alloca_adjust
;
2143 frame_addr
= get_frame_register_signed
2144 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2146 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2147 if (alloca_adjust
> 0)
2149 /* FP > SP + frame_size. This may be because of
2150 an alloca or somethings similar. Fix sp to
2151 "pre-alloca" value, and try again. */
2152 sp
+= alloca_adjust
;
2153 /* Need to reset the status of all registers. Otherwise,
2154 we will hit a guard that prevents the new address
2155 for each register to be recomputed during the second
2157 reset_saved_regs (gdbarch
, this_cache
);
2162 /* move $30,$sp. With different versions of gas this will be either
2163 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2164 Accept any one of these. */
2165 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2167 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2168 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2170 unsigned alloca_adjust
;
2173 frame_addr
= get_frame_register_signed
2174 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2176 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2177 if (alloca_adjust
> 0)
2179 /* FP > SP + frame_size. This may be because of
2180 an alloca or somethings similar. Fix sp to
2181 "pre-alloca" value, and try again. */
2183 /* Need to reset the status of all registers. Otherwise,
2184 we will hit a guard that prevents the new address
2185 for each register to be recomputed during the second
2187 reset_saved_regs (gdbarch
, this_cache
);
2192 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2193 && !regsize_is_64_bits
)
2195 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2197 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2198 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2199 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2200 || high_word
== 0x3c1c /* lui $gp,n */
2201 || high_word
== 0x279c /* addiu $gp,$gp,n */
2202 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2203 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2206 /* These instructions are part of the prologue, but we don't
2207 need to do anything special to handle them. */
2209 /* The instructions below load $at or $t0 with an immediate
2210 value in preparation for a stack adjustment via
2211 subu $sp,$sp,[$at,$t0]. These instructions could also
2212 initialize a local variable, so we accept them only before
2213 a stack adjustment instruction was seen. */
2214 else if (!seen_sp_adjust
2215 && (high_word
== 0x3c01 /* lui $at,n */
2216 || high_word
== 0x3c08 /* lui $t0,n */
2217 || high_word
== 0x3421 /* ori $at,$at,n */
2218 || high_word
== 0x3508 /* ori $t0,$t0,n */
2219 || high_word
== 0x3401 /* ori $at,$zero,n */
2220 || high_word
== 0x3408 /* ori $t0,$zero,n */
2223 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2227 /* This instruction is not an instruction typically found
2228 in a prologue, so we must have reached the end of the
2230 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2231 loop now? Why would we need to continue scanning the function
2233 if (end_prologue_addr
== 0)
2234 end_prologue_addr
= cur_pc
;
2236 /* Check for branches and jumps. For now, only jump to
2237 register are caught (i.e. returns). */
2238 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2242 /* If the previous instruction was a jump, we must have reached
2243 the end of the prologue by now. Stop scanning so that we do
2244 not go past the function return. */
2249 if (this_cache
!= NULL
)
2252 (get_frame_register_signed (this_frame
,
2253 gdbarch_num_regs (gdbarch
) + frame_reg
)
2255 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2256 this assignment below, eventually. But it's still needed
2258 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2259 + mips_regnum (gdbarch
)->pc
]
2260 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2264 /* If we didn't reach the end of the prologue when scanning the function
2265 instructions, then set end_prologue_addr to the address of the
2266 instruction immediately after the last one we scanned. */
2267 /* brobecker/2004-10-10: I don't think this would ever happen, but
2268 we may as well be careful and do our best if we have a null
2269 end_prologue_addr. */
2270 if (end_prologue_addr
== 0)
2271 end_prologue_addr
= cur_pc
;
2273 /* In a frameless function, we might have incorrectly
2274 skipped some load immediate instructions. Undo the skipping
2275 if the load immediate was not followed by a stack adjustment. */
2276 if (load_immediate_bytes
&& !seen_sp_adjust
)
2277 end_prologue_addr
-= load_immediate_bytes
;
2279 return end_prologue_addr
;
2282 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2283 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2284 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2287 static struct mips_frame_cache
*
2288 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2290 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2291 struct mips_frame_cache
*cache
;
2293 if ((*this_cache
) != NULL
)
2294 return (*this_cache
);
2296 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2297 (*this_cache
) = cache
;
2298 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2300 /* Analyze the function prologue. */
2302 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2303 CORE_ADDR start_addr
;
2305 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2306 if (start_addr
== 0)
2307 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2308 /* We can't analyze the prologue if we couldn't find the begining
2310 if (start_addr
== 0)
2313 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2316 /* gdbarch_sp_regnum contains the value and not the address. */
2317 trad_frame_set_value (cache
->saved_regs
,
2318 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2321 return (*this_cache
);
2325 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2326 struct frame_id
*this_id
)
2328 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2330 /* This marks the outermost frame. */
2331 if (info
->base
== 0)
2333 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2336 static struct value
*
2337 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2338 void **this_cache
, int regnum
)
2340 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2342 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2346 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2347 struct frame_info
*this_frame
, void **this_cache
)
2349 CORE_ADDR pc
= get_frame_pc (this_frame
);
2350 if (! mips_pc_is_mips16 (pc
))
2355 static const struct frame_unwind mips_insn32_frame_unwind
=
2358 mips_insn32_frame_this_id
,
2359 mips_insn32_frame_prev_register
,
2361 mips_insn32_frame_sniffer
2365 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2368 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2373 static const struct frame_base mips_insn32_frame_base
=
2375 &mips_insn32_frame_unwind
,
2376 mips_insn32_frame_base_address
,
2377 mips_insn32_frame_base_address
,
2378 mips_insn32_frame_base_address
2381 static const struct frame_base
*
2382 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2384 CORE_ADDR pc
= get_frame_pc (this_frame
);
2385 if (! mips_pc_is_mips16 (pc
))
2386 return &mips_insn32_frame_base
;
2391 static struct trad_frame_cache
*
2392 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2395 CORE_ADDR start_addr
;
2396 CORE_ADDR stack_addr
;
2397 struct trad_frame_cache
*this_trad_cache
;
2398 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2399 int num_regs
= gdbarch_num_regs (gdbarch
);
2401 if ((*this_cache
) != NULL
)
2402 return (*this_cache
);
2403 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2404 (*this_cache
) = this_trad_cache
;
2406 /* The return address is in the link register. */
2407 trad_frame_set_reg_realreg (this_trad_cache
,
2408 gdbarch_pc_regnum (gdbarch
),
2409 num_regs
+ MIPS_RA_REGNUM
);
2411 /* Frame ID, since it's a frameless / stackless function, no stack
2412 space is allocated and SP on entry is the current SP. */
2413 pc
= get_frame_pc (this_frame
);
2414 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2415 stack_addr
= get_frame_register_signed (this_frame
,
2416 num_regs
+ MIPS_SP_REGNUM
);
2417 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2419 /* Assume that the frame's base is the same as the
2421 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2423 return this_trad_cache
;
2427 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2428 struct frame_id
*this_id
)
2430 struct trad_frame_cache
*this_trad_cache
2431 = mips_stub_frame_cache (this_frame
, this_cache
);
2432 trad_frame_get_id (this_trad_cache
, this_id
);
2435 static struct value
*
2436 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2437 void **this_cache
, int regnum
)
2439 struct trad_frame_cache
*this_trad_cache
2440 = mips_stub_frame_cache (this_frame
, this_cache
);
2441 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2445 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2446 struct frame_info
*this_frame
, void **this_cache
)
2449 struct obj_section
*s
;
2450 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2451 struct minimal_symbol
*msym
;
2453 /* Use the stub unwinder for unreadable code. */
2454 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2457 if (in_plt_section (pc
, NULL
))
2460 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2461 s
= find_pc_section (pc
);
2464 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2465 ".MIPS.stubs") == 0)
2468 /* Calling a PIC function from a non-PIC function passes through a
2469 stub. The stub for foo is named ".pic.foo". */
2470 msym
= lookup_minimal_symbol_by_pc (pc
);
2472 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2473 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2479 static const struct frame_unwind mips_stub_frame_unwind
=
2482 mips_stub_frame_this_id
,
2483 mips_stub_frame_prev_register
,
2485 mips_stub_frame_sniffer
2489 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2492 struct trad_frame_cache
*this_trad_cache
2493 = mips_stub_frame_cache (this_frame
, this_cache
);
2494 return trad_frame_get_this_base (this_trad_cache
);
2497 static const struct frame_base mips_stub_frame_base
=
2499 &mips_stub_frame_unwind
,
2500 mips_stub_frame_base_address
,
2501 mips_stub_frame_base_address
,
2502 mips_stub_frame_base_address
2505 static const struct frame_base
*
2506 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2508 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2509 return &mips_stub_frame_base
;
2514 /* mips_addr_bits_remove - remove useless address bits */
2517 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2519 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2521 if (is_mips16_addr (addr
))
2522 addr
= unmake_mips16_addr (addr
);
2524 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2525 /* This hack is a work-around for existing boards using PMON, the
2526 simulator, and any other 64-bit targets that doesn't have true
2527 64-bit addressing. On these targets, the upper 32 bits of
2528 addresses are ignored by the hardware. Thus, the PC or SP are
2529 likely to have been sign extended to all 1s by instruction
2530 sequences that load 32-bit addresses. For example, a typical
2531 piece of code that loads an address is this:
2533 lui $r2, <upper 16 bits>
2534 ori $r2, <lower 16 bits>
2536 But the lui sign-extends the value such that the upper 32 bits
2537 may be all 1s. The workaround is simply to mask off these
2538 bits. In the future, gcc may be changed to support true 64-bit
2539 addressing, and this masking will have to be disabled. */
2540 return addr
&= 0xffffffffUL
;
2545 /* Instructions used during single-stepping of atomic sequences. */
2546 #define LL_OPCODE 0x30
2547 #define LLD_OPCODE 0x34
2548 #define SC_OPCODE 0x38
2549 #define SCD_OPCODE 0x3c
2551 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2552 instruction and ending with a SC/SCD instruction. If such a sequence
2553 is found, attempt to step through it. A breakpoint is placed at the end of
2557 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2558 struct address_space
*aspace
, CORE_ADDR pc
)
2560 CORE_ADDR breaks
[2] = {-1, -1};
2562 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2566 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2567 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2572 insn
= mips_fetch_instruction (gdbarch
, loc
);
2573 /* Assume all atomic sequences start with a ll/lld instruction. */
2574 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2577 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2579 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2582 loc
+= MIPS_INSN32_SIZE
;
2583 insn
= mips_fetch_instruction (gdbarch
, loc
);
2585 /* Assume that there is at most one branch in the atomic
2586 sequence. If a branch is found, put a breakpoint in its
2587 destination address. */
2588 switch (itype_op (insn
))
2590 case 0: /* SPECIAL */
2591 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2592 return 0; /* fallback to the standard single-step code. */
2594 case 1: /* REGIMM */
2595 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2599 return 0; /* fallback to the standard single-step code. */
2606 case 22: /* BLEZL */
2607 case 23: /* BGTTL */
2613 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2618 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2619 if (last_breakpoint
>= 1)
2620 return 0; /* More than one branch found, fallback to the
2621 standard single-step code. */
2622 breaks
[1] = branch_bp
;
2626 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2630 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2631 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2634 loc
+= MIPS_INSN32_SIZE
;
2636 /* Insert a breakpoint right after the end of the atomic sequence. */
2639 /* Check for duplicated breakpoints. Check also for a breakpoint
2640 placed (branch instruction's destination) in the atomic sequence */
2641 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2642 last_breakpoint
= 0;
2644 /* Effectively inserts the breakpoints. */
2645 for (index
= 0; index
<= last_breakpoint
; index
++)
2646 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2651 /* mips_software_single_step() is called just before we want to resume
2652 the inferior, if we want to single-step it but there is no hardware
2653 or kernel single-step support (MIPS on GNU/Linux for example). We find
2654 the target of the coming instruction and breakpoint it. */
2657 mips_software_single_step (struct frame_info
*frame
)
2659 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2660 struct address_space
*aspace
= get_frame_address_space (frame
);
2661 CORE_ADDR pc
, next_pc
;
2663 pc
= get_frame_pc (frame
);
2664 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2667 next_pc
= mips_next_pc (frame
, pc
);
2669 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2673 /* Test whether the PC points to the return instruction at the
2674 end of a function. */
2677 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2679 if (mips_pc_is_mips16 (pc
))
2680 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2681 generates a "jr $ra"; other times it generates code to load
2682 the return address from the stack to an accessible register (such
2683 as $a3), then a "jr" using that register. This second case
2684 is almost impossible to distinguish from an indirect jump
2685 used for switch statements, so we don't even try. */
2686 return mips_fetch_instruction (gdbarch
, pc
) == 0xe820; /* jr $ra */
2688 return mips_fetch_instruction (gdbarch
, pc
) == 0x3e00008; /* jr $ra */
2692 /* This fencepost looks highly suspicious to me. Removing it also
2693 seems suspicious as it could affect remote debugging across serial
2697 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2703 struct inferior
*inf
;
2705 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2707 fence
= start_pc
- heuristic_fence_post
;
2711 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2712 fence
= VM_MIN_ADDRESS
;
2714 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2716 inf
= current_inferior ();
2718 /* search back for previous return */
2719 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2720 if (start_pc
< fence
)
2722 /* It's not clear to me why we reach this point when
2723 stop_soon, but with this test, at least we
2724 don't print out warnings for every child forked (eg, on
2725 decstation). 22apr93 rich@cygnus.com. */
2726 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2728 static int blurb_printed
= 0;
2730 warning (_("GDB can't find the start of the function at %s."),
2731 paddress (gdbarch
, pc
));
2735 /* This actually happens frequently in embedded
2736 development, when you first connect to a board
2737 and your stack pointer and pc are nowhere in
2738 particular. This message needs to give people
2739 in that situation enough information to
2740 determine that it's no big deal. */
2741 printf_filtered ("\n\
2742 GDB is unable to find the start of the function at %s\n\
2743 and thus can't determine the size of that function's stack frame.\n\
2744 This means that GDB may be unable to access that stack frame, or\n\
2745 the frames below it.\n\
2746 This problem is most likely caused by an invalid program counter or\n\
2748 However, if you think GDB should simply search farther back\n\
2749 from %s for code which looks like the beginning of a\n\
2750 function, you can increase the range of the search using the `set\n\
2751 heuristic-fence-post' command.\n",
2752 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2759 else if (mips_pc_is_mips16 (start_pc
))
2761 unsigned short inst
;
2763 /* On MIPS16, any one of the following is likely to be the
2764 start of a function:
2770 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2771 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2772 if ((inst
& 0xff80) == 0x6480) /* save */
2774 if (start_pc
- instlen
>= fence
)
2776 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2777 if ((inst
& 0xf800) == 0xf000) /* extend */
2778 start_pc
-= instlen
;
2782 else if (((inst
& 0xf81f) == 0xe809
2783 && (inst
& 0x700) != 0x700) /* entry */
2784 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2785 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2786 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2788 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2789 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2794 else if (mips_about_to_return (gdbarch
, start_pc
))
2796 /* Skip return and its delay slot. */
2797 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2804 struct mips_objfile_private
2810 /* According to the current ABI, should the type be passed in a
2811 floating-point register (assuming that there is space)? When there
2812 is no FPU, FP are not even considered as possible candidates for
2813 FP registers and, consequently this returns false - forces FP
2814 arguments into integer registers. */
2817 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2818 struct type
*arg_type
)
2820 return ((typecode
== TYPE_CODE_FLT
2821 || (MIPS_EABI (gdbarch
)
2822 && (typecode
== TYPE_CODE_STRUCT
2823 || typecode
== TYPE_CODE_UNION
)
2824 && TYPE_NFIELDS (arg_type
) == 1
2825 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2827 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2830 /* On o32, argument passing in GPRs depends on the alignment of the type being
2831 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2834 mips_type_needs_double_align (struct type
*type
)
2836 enum type_code typecode
= TYPE_CODE (type
);
2838 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2840 else if (typecode
== TYPE_CODE_STRUCT
)
2842 if (TYPE_NFIELDS (type
) < 1)
2844 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2846 else if (typecode
== TYPE_CODE_UNION
)
2850 n
= TYPE_NFIELDS (type
);
2851 for (i
= 0; i
< n
; i
++)
2852 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2859 /* Adjust the address downward (direction of stack growth) so that it
2860 is correctly aligned for a new stack frame. */
2862 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2864 return align_down (addr
, 16);
2868 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2869 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2870 int nargs
, struct value
**args
, CORE_ADDR sp
,
2871 int struct_return
, CORE_ADDR struct_addr
)
2877 int stack_offset
= 0;
2878 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2879 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2880 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2881 int regsize
= mips_abi_regsize (gdbarch
);
2883 /* For shared libraries, "t9" needs to point at the function
2885 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2887 /* Set the return address register to point to the entry point of
2888 the program, where a breakpoint lies in wait. */
2889 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2891 /* First ensure that the stack and structure return address (if any)
2892 are properly aligned. The stack has to be at least 64-bit
2893 aligned even on 32-bit machines, because doubles must be 64-bit
2894 aligned. For n32 and n64, stack frames need to be 128-bit
2895 aligned, so we round to this widest known alignment. */
2897 sp
= align_down (sp
, 16);
2898 struct_addr
= align_down (struct_addr
, 16);
2900 /* Now make space on the stack for the args. We allocate more
2901 than necessary for EABI, because the first few arguments are
2902 passed in registers, but that's OK. */
2903 for (argnum
= 0; argnum
< nargs
; argnum
++)
2904 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2905 sp
-= align_up (len
, 16);
2908 fprintf_unfiltered (gdb_stdlog
,
2909 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2910 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2912 /* Initialize the integer and float register pointers. */
2913 argreg
= MIPS_A0_REGNUM
;
2914 float_argreg
= mips_fpa0_regnum (gdbarch
);
2916 /* The struct_return pointer occupies the first parameter-passing reg. */
2920 fprintf_unfiltered (gdb_stdlog
,
2921 "mips_eabi_push_dummy_call: struct_return reg=%d %s\n",
2922 argreg
, paddress (gdbarch
, struct_addr
));
2923 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2926 /* Now load as many as possible of the first arguments into
2927 registers, and push the rest onto the stack. Loop thru args
2928 from first to last. */
2929 for (argnum
= 0; argnum
< nargs
; argnum
++)
2931 const gdb_byte
*val
;
2932 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2933 struct value
*arg
= args
[argnum
];
2934 struct type
*arg_type
= check_typedef (value_type (arg
));
2935 int len
= TYPE_LENGTH (arg_type
);
2936 enum type_code typecode
= TYPE_CODE (arg_type
);
2939 fprintf_unfiltered (gdb_stdlog
,
2940 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2941 argnum
+ 1, len
, (int) typecode
);
2943 /* Function pointer arguments to mips16 code need to be made into
2945 if (typecode
== TYPE_CODE_PTR
2946 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
2948 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
2950 if (mips_pc_is_mips16 (addr
))
2952 store_signed_integer (valbuf
, len
, byte_order
,
2953 make_mips16_addr (addr
));
2957 val
= value_contents (arg
);
2959 /* The EABI passes structures that do not fit in a register by
2961 else if (len
> regsize
2962 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2964 store_unsigned_integer (valbuf
, regsize
, byte_order
,
2965 value_address (arg
));
2966 typecode
= TYPE_CODE_PTR
;
2970 fprintf_unfiltered (gdb_stdlog
, " push");
2973 val
= value_contents (arg
);
2975 /* 32-bit ABIs always start floating point arguments in an
2976 even-numbered floating point register. Round the FP register
2977 up before the check to see if there are any FP registers
2978 left. Non MIPS_EABI targets also pass the FP in the integer
2979 registers so also round up normal registers. */
2980 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2982 if ((float_argreg
& 1))
2986 /* Floating point arguments passed in registers have to be
2987 treated specially. On 32-bit architectures, doubles
2988 are passed in register pairs; the even register gets
2989 the low word, and the odd register gets the high word.
2990 On non-EABI processors, the first two floating point arguments are
2991 also copied to general registers, because MIPS16 functions
2992 don't use float registers for arguments. This duplication of
2993 arguments in general registers can't hurt non-MIPS16 functions
2994 because those registers are normally skipped. */
2995 /* MIPS_EABI squeezes a struct that contains a single floating
2996 point value into an FP register instead of pushing it onto the
2998 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
2999 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3001 /* EABI32 will pass doubles in consecutive registers, even on
3002 64-bit cores. At one time, we used to check the size of
3003 `float_argreg' to determine whether or not to pass doubles
3004 in consecutive registers, but this is not sufficient for
3005 making the ABI determination. */
3006 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
3008 int low_offset
= gdbarch_byte_order (gdbarch
)
3009 == BFD_ENDIAN_BIG
? 4 : 0;
3012 /* Write the low word of the double to the even register(s). */
3013 regval
= extract_signed_integer (val
+ low_offset
,
3016 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3017 float_argreg
, phex (regval
, 4));
3018 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3020 /* Write the high word of the double to the odd register(s). */
3021 regval
= extract_signed_integer (val
+ 4 - low_offset
,
3024 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3025 float_argreg
, phex (regval
, 4));
3026 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3030 /* This is a floating point value that fits entirely
3031 in a single register. */
3032 /* On 32 bit ABI's the float_argreg is further adjusted
3033 above to ensure that it is even register aligned. */
3034 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
3036 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3037 float_argreg
, phex (regval
, len
));
3038 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3043 /* Copy the argument to general registers or the stack in
3044 register-sized pieces. Large arguments are split between
3045 registers and stack. */
3046 /* Note: structs whose size is not a multiple of regsize
3047 are treated specially: Irix cc passes
3048 them in registers where gcc sometimes puts them on the
3049 stack. For maximum compatibility, we will put them in
3051 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3053 /* Note: Floating-point values that didn't fit into an FP
3054 register are only written to memory. */
3057 /* Remember if the argument was written to the stack. */
3058 int stack_used_p
= 0;
3059 int partial_len
= (len
< regsize
? len
: regsize
);
3062 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3065 /* Write this portion of the argument to the stack. */
3066 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3068 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3070 /* Should shorter than int integer values be
3071 promoted to int before being stored? */
3072 int longword_offset
= 0;
3075 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3078 && (typecode
== TYPE_CODE_INT
3079 || typecode
== TYPE_CODE_PTR
3080 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3081 longword_offset
= regsize
- len
;
3082 else if ((typecode
== TYPE_CODE_STRUCT
3083 || typecode
== TYPE_CODE_UNION
)
3084 && TYPE_LENGTH (arg_type
) < regsize
)
3085 longword_offset
= regsize
- len
;
3090 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3091 paddress (gdbarch
, stack_offset
));
3092 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3093 paddress (gdbarch
, longword_offset
));
3096 addr
= sp
+ stack_offset
+ longword_offset
;
3101 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3102 paddress (gdbarch
, addr
));
3103 for (i
= 0; i
< partial_len
; i
++)
3105 fprintf_unfiltered (gdb_stdlog
, "%02x",
3109 write_memory (addr
, val
, partial_len
);
3112 /* Note!!! This is NOT an else clause. Odd sized
3113 structs may go thru BOTH paths. Floating point
3114 arguments will not. */
3115 /* Write this portion of the argument to a general
3116 purpose register. */
3117 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3118 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3121 extract_signed_integer (val
, partial_len
, byte_order
);
3124 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3126 phex (regval
, regsize
));
3127 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3134 /* Compute the the offset into the stack at which we
3135 will copy the next parameter.
3137 In the new EABI (and the NABI32), the stack_offset
3138 only needs to be adjusted when it has been used. */
3141 stack_offset
+= align_up (partial_len
, regsize
);
3145 fprintf_unfiltered (gdb_stdlog
, "\n");
3148 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3150 /* Return adjusted stack pointer. */
3154 /* Determine the return value convention being used. */
3156 static enum return_value_convention
3157 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3158 struct type
*type
, struct regcache
*regcache
,
3159 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3161 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3162 int fp_return_type
= 0;
3163 int offset
, regnum
, xfer
;
3165 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3166 return RETURN_VALUE_STRUCT_CONVENTION
;
3168 /* Floating point type? */
3169 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3171 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3173 /* Structs with a single field of float type
3174 are returned in a floating point register. */
3175 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3176 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3177 && TYPE_NFIELDS (type
) == 1)
3179 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3181 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3188 /* A floating-point value belongs in the least significant part
3191 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3192 regnum
= mips_regnum (gdbarch
)->fp0
;
3196 /* An integer value goes in V0/V1. */
3198 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3199 regnum
= MIPS_V0_REGNUM
;
3202 offset
< TYPE_LENGTH (type
);
3203 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3205 xfer
= mips_abi_regsize (gdbarch
);
3206 if (offset
+ xfer
> TYPE_LENGTH (type
))
3207 xfer
= TYPE_LENGTH (type
) - offset
;
3208 mips_xfer_register (gdbarch
, regcache
,
3209 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3210 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3214 return RETURN_VALUE_REGISTER_CONVENTION
;
3218 /* N32/N64 ABI stuff. */
3220 /* Search for a naturally aligned double at OFFSET inside a struct
3221 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3225 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3230 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3233 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3236 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3239 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3242 struct type
*field_type
;
3244 /* We're only looking at normal fields. */
3245 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3246 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3249 /* If we have gone past the offset, there is no double to pass. */
3250 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3254 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3256 /* If this field is entirely before the requested offset, go
3257 on to the next one. */
3258 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3261 /* If this is our special aligned double, we can stop. */
3262 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3263 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3266 /* This field starts at or before the requested offset, and
3267 overlaps it. If it is a structure, recurse inwards. */
3268 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3275 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3276 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3277 int nargs
, struct value
**args
, CORE_ADDR sp
,
3278 int struct_return
, CORE_ADDR struct_addr
)
3284 int stack_offset
= 0;
3285 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3286 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3287 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3289 /* For shared libraries, "t9" needs to point at the function
3291 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3293 /* Set the return address register to point to the entry point of
3294 the program, where a breakpoint lies in wait. */
3295 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3297 /* First ensure that the stack and structure return address (if any)
3298 are properly aligned. The stack has to be at least 64-bit
3299 aligned even on 32-bit machines, because doubles must be 64-bit
3300 aligned. For n32 and n64, stack frames need to be 128-bit
3301 aligned, so we round to this widest known alignment. */
3303 sp
= align_down (sp
, 16);
3304 struct_addr
= align_down (struct_addr
, 16);
3306 /* Now make space on the stack for the args. */
3307 for (argnum
= 0; argnum
< nargs
; argnum
++)
3308 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3309 sp
-= align_up (len
, 16);
3312 fprintf_unfiltered (gdb_stdlog
,
3313 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3314 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3316 /* Initialize the integer and float register pointers. */
3317 argreg
= MIPS_A0_REGNUM
;
3318 float_argreg
= mips_fpa0_regnum (gdbarch
);
3320 /* The struct_return pointer occupies the first parameter-passing reg. */
3324 fprintf_unfiltered (gdb_stdlog
,
3325 "mips_n32n64_push_dummy_call: struct_return reg=%d %s\n",
3326 argreg
, paddress (gdbarch
, struct_addr
));
3327 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3330 /* Now load as many as possible of the first arguments into
3331 registers, and push the rest onto the stack. Loop thru args
3332 from first to last. */
3333 for (argnum
= 0; argnum
< nargs
; argnum
++)
3335 const gdb_byte
*val
;
3336 struct value
*arg
= args
[argnum
];
3337 struct type
*arg_type
= check_typedef (value_type (arg
));
3338 int len
= TYPE_LENGTH (arg_type
);
3339 enum type_code typecode
= TYPE_CODE (arg_type
);
3342 fprintf_unfiltered (gdb_stdlog
,
3343 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3344 argnum
+ 1, len
, (int) typecode
);
3346 val
= value_contents (arg
);
3348 /* A 128-bit long double value requires an even-odd pair of
3349 floating-point registers. */
3351 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3352 && (float_argreg
& 1))
3358 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3359 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3361 /* This is a floating point value that fits entirely
3362 in a single register or a pair of registers. */
3363 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3364 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3366 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3367 float_argreg
, phex (regval
, reglen
));
3368 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3371 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3372 argreg
, phex (regval
, reglen
));
3373 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3378 regval
= extract_unsigned_integer (val
+ reglen
,
3379 reglen
, byte_order
);
3381 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3382 float_argreg
, phex (regval
, reglen
));
3383 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3386 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3387 argreg
, phex (regval
, reglen
));
3388 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3395 /* Copy the argument to general registers or the stack in
3396 register-sized pieces. Large arguments are split between
3397 registers and stack. */
3398 /* For N32/N64, structs, unions, or other composite types are
3399 treated as a sequence of doublewords, and are passed in integer
3400 or floating point registers as though they were simple scalar
3401 parameters to the extent that they fit, with any excess on the
3402 stack packed according to the normal memory layout of the
3404 The caller does not reserve space for the register arguments;
3405 the callee is responsible for reserving it if required. */
3406 /* Note: Floating-point values that didn't fit into an FP
3407 register are only written to memory. */
3410 /* Remember if the argument was written to the stack. */
3411 int stack_used_p
= 0;
3412 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3415 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3418 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3419 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3421 /* Write this portion of the argument to the stack. */
3422 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3424 /* Should shorter than int integer values be
3425 promoted to int before being stored? */
3426 int longword_offset
= 0;
3429 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3431 if ((typecode
== TYPE_CODE_INT
3432 || typecode
== TYPE_CODE_PTR
)
3434 longword_offset
= MIPS64_REGSIZE
- len
;
3439 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3440 paddress (gdbarch
, stack_offset
));
3441 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3442 paddress (gdbarch
, longword_offset
));
3445 addr
= sp
+ stack_offset
+ longword_offset
;
3450 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3451 paddress (gdbarch
, addr
));
3452 for (i
= 0; i
< partial_len
; i
++)
3454 fprintf_unfiltered (gdb_stdlog
, "%02x",
3458 write_memory (addr
, val
, partial_len
);
3461 /* Note!!! This is NOT an else clause. Odd sized
3462 structs may go thru BOTH paths. */
3463 /* Write this portion of the argument to a general
3464 purpose register. */
3465 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3469 /* Sign extend pointers, 32-bit integers and signed
3470 16-bit and 8-bit integers; everything else is taken
3473 if ((partial_len
== 4
3474 && (typecode
== TYPE_CODE_PTR
3475 || typecode
== TYPE_CODE_INT
))
3477 && typecode
== TYPE_CODE_INT
3478 && !TYPE_UNSIGNED (arg_type
)))
3479 regval
= extract_signed_integer (val
, partial_len
,
3482 regval
= extract_unsigned_integer (val
, partial_len
,
3485 /* A non-floating-point argument being passed in a
3486 general register. If a struct or union, and if
3487 the remaining length is smaller than the register
3488 size, we have to adjust the register value on
3491 It does not seem to be necessary to do the
3492 same for integral types. */
3494 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3495 && partial_len
< MIPS64_REGSIZE
3496 && (typecode
== TYPE_CODE_STRUCT
3497 || typecode
== TYPE_CODE_UNION
))
3498 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3502 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3504 phex (regval
, MIPS64_REGSIZE
));
3505 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3507 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3508 TYPE_LENGTH (arg_type
) - len
))
3511 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3513 phex (regval
, MIPS64_REGSIZE
));
3514 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3525 /* Compute the the offset into the stack at which we
3526 will copy the next parameter.
3528 In N32 (N64?), the stack_offset only needs to be
3529 adjusted when it has been used. */
3532 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3536 fprintf_unfiltered (gdb_stdlog
, "\n");
3539 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3541 /* Return adjusted stack pointer. */
3545 static enum return_value_convention
3546 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3547 struct type
*type
, struct regcache
*regcache
,
3548 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3550 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3552 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3554 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3555 if needed), as appropriate for the type. Composite results (struct,
3556 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3559 * A struct with only one or two floating point fields is returned in $f0
3560 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3563 * Any other composite results of at most 128 bits are returned in
3564 $2 (first 64 bits) and $3 (remainder, if necessary).
3566 * Larger composite results are handled by converting the function to a
3567 procedure with an implicit first parameter, which is a pointer to an area
3568 reserved by the caller to receive the result. [The o32-bit ABI requires
3569 that all composite results be handled by conversion to implicit first
3570 parameters. The MIPS/SGI Fortran implementation has always made a
3571 specific exception to return COMPLEX results in the floating point
3574 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3575 return RETURN_VALUE_STRUCT_CONVENTION
;
3576 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3577 && TYPE_LENGTH (type
) == 16
3578 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3580 /* A 128-bit floating-point value fills both $f0 and $f2. The
3581 two registers are used in the same as memory order, so the
3582 eight bytes with the lower memory address are in $f0. */
3584 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3585 mips_xfer_register (gdbarch
, regcache
,
3586 gdbarch_num_regs (gdbarch
)
3587 + mips_regnum (gdbarch
)->fp0
,
3588 8, gdbarch_byte_order (gdbarch
),
3589 readbuf
, writebuf
, 0);
3590 mips_xfer_register (gdbarch
, regcache
,
3591 gdbarch_num_regs (gdbarch
)
3592 + mips_regnum (gdbarch
)->fp0
+ 2,
3593 8, gdbarch_byte_order (gdbarch
),
3594 readbuf
? readbuf
+ 8 : readbuf
,
3595 writebuf
? writebuf
+ 8 : writebuf
, 0);
3596 return RETURN_VALUE_REGISTER_CONVENTION
;
3598 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3599 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3601 /* A single or double floating-point value that fits in FP0. */
3603 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3604 mips_xfer_register (gdbarch
, regcache
,
3605 gdbarch_num_regs (gdbarch
)
3606 + mips_regnum (gdbarch
)->fp0
,
3608 gdbarch_byte_order (gdbarch
),
3609 readbuf
, writebuf
, 0);
3610 return RETURN_VALUE_REGISTER_CONVENTION
;
3612 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3613 && TYPE_NFIELDS (type
) <= 2
3614 && TYPE_NFIELDS (type
) >= 1
3615 && ((TYPE_NFIELDS (type
) == 1
3616 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3618 || (TYPE_NFIELDS (type
) == 2
3619 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3621 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3622 == TYPE_CODE_FLT
))))
3624 /* A struct that contains one or two floats. Each value is part
3625 in the least significant part of their floating point
3626 register (or GPR, for soft float). */
3629 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3630 ? mips_regnum (gdbarch
)->fp0
3632 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3634 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3637 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3639 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3641 /* A 16-byte long double field goes in two consecutive
3643 mips_xfer_register (gdbarch
, regcache
,
3644 gdbarch_num_regs (gdbarch
) + regnum
,
3646 gdbarch_byte_order (gdbarch
),
3647 readbuf
, writebuf
, offset
);
3648 mips_xfer_register (gdbarch
, regcache
,
3649 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3651 gdbarch_byte_order (gdbarch
),
3652 readbuf
, writebuf
, offset
+ 8);
3655 mips_xfer_register (gdbarch
, regcache
,
3656 gdbarch_num_regs (gdbarch
) + regnum
,
3657 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3658 gdbarch_byte_order (gdbarch
),
3659 readbuf
, writebuf
, offset
);
3661 return RETURN_VALUE_REGISTER_CONVENTION
;
3663 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3664 || TYPE_CODE (type
) == TYPE_CODE_UNION
3665 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3667 /* A composite type. Extract the left justified value,
3668 regardless of the byte order. I.e. DO NOT USE
3672 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3673 offset
< TYPE_LENGTH (type
);
3674 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3676 int xfer
= register_size (gdbarch
, regnum
);
3677 if (offset
+ xfer
> TYPE_LENGTH (type
))
3678 xfer
= TYPE_LENGTH (type
) - offset
;
3680 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3681 offset
, xfer
, regnum
);
3682 mips_xfer_register (gdbarch
, regcache
,
3683 gdbarch_num_regs (gdbarch
) + regnum
,
3684 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3687 return RETURN_VALUE_REGISTER_CONVENTION
;
3691 /* A scalar extract each part but least-significant-byte
3695 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3696 offset
< TYPE_LENGTH (type
);
3697 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3699 int xfer
= register_size (gdbarch
, regnum
);
3700 if (offset
+ xfer
> TYPE_LENGTH (type
))
3701 xfer
= TYPE_LENGTH (type
) - offset
;
3703 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3704 offset
, xfer
, regnum
);
3705 mips_xfer_register (gdbarch
, regcache
,
3706 gdbarch_num_regs (gdbarch
) + regnum
,
3707 xfer
, gdbarch_byte_order (gdbarch
),
3708 readbuf
, writebuf
, offset
);
3710 return RETURN_VALUE_REGISTER_CONVENTION
;
3714 /* O32 ABI stuff. */
3717 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3718 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3719 int nargs
, struct value
**args
, CORE_ADDR sp
,
3720 int struct_return
, CORE_ADDR struct_addr
)
3726 int stack_offset
= 0;
3727 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3728 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3729 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3731 /* For shared libraries, "t9" needs to point at the function
3733 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3735 /* Set the return address register to point to the entry point of
3736 the program, where a breakpoint lies in wait. */
3737 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3739 /* First ensure that the stack and structure return address (if any)
3740 are properly aligned. The stack has to be at least 64-bit
3741 aligned even on 32-bit machines, because doubles must be 64-bit
3742 aligned. For n32 and n64, stack frames need to be 128-bit
3743 aligned, so we round to this widest known alignment. */
3745 sp
= align_down (sp
, 16);
3746 struct_addr
= align_down (struct_addr
, 16);
3748 /* Now make space on the stack for the args. */
3749 for (argnum
= 0; argnum
< nargs
; argnum
++)
3751 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3752 int arglen
= TYPE_LENGTH (arg_type
);
3754 /* Align to double-word if necessary. */
3755 if (mips_type_needs_double_align (arg_type
))
3756 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3757 /* Allocate space on the stack. */
3758 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3760 sp
-= align_up (len
, 16);
3763 fprintf_unfiltered (gdb_stdlog
,
3764 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3765 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3767 /* Initialize the integer and float register pointers. */
3768 argreg
= MIPS_A0_REGNUM
;
3769 float_argreg
= mips_fpa0_regnum (gdbarch
);
3771 /* The struct_return pointer occupies the first parameter-passing reg. */
3775 fprintf_unfiltered (gdb_stdlog
,
3776 "mips_o32_push_dummy_call: struct_return reg=%d %s\n",
3777 argreg
, paddress (gdbarch
, struct_addr
));
3778 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3779 stack_offset
+= MIPS32_REGSIZE
;
3782 /* Now load as many as possible of the first arguments into
3783 registers, and push the rest onto the stack. Loop thru args
3784 from first to last. */
3785 for (argnum
= 0; argnum
< nargs
; argnum
++)
3787 const gdb_byte
*val
;
3788 struct value
*arg
= args
[argnum
];
3789 struct type
*arg_type
= check_typedef (value_type (arg
));
3790 int len
= TYPE_LENGTH (arg_type
);
3791 enum type_code typecode
= TYPE_CODE (arg_type
);
3794 fprintf_unfiltered (gdb_stdlog
,
3795 "mips_o32_push_dummy_call: %d len=%d type=%d",
3796 argnum
+ 1, len
, (int) typecode
);
3798 val
= value_contents (arg
);
3800 /* 32-bit ABIs always start floating point arguments in an
3801 even-numbered floating point register. Round the FP register
3802 up before the check to see if there are any FP registers
3803 left. O32/O64 targets also pass the FP in the integer
3804 registers so also round up normal registers. */
3805 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3807 if ((float_argreg
& 1))
3811 /* Floating point arguments passed in registers have to be
3812 treated specially. On 32-bit architectures, doubles
3813 are passed in register pairs; the even register gets
3814 the low word, and the odd register gets the high word.
3815 On O32/O64, the first two floating point arguments are
3816 also copied to general registers, because MIPS16 functions
3817 don't use float registers for arguments. This duplication of
3818 arguments in general registers can't hurt non-MIPS16 functions
3819 because those registers are normally skipped. */
3821 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3822 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3824 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3826 int low_offset
= gdbarch_byte_order (gdbarch
)
3827 == BFD_ENDIAN_BIG
? 4 : 0;
3828 unsigned long regval
;
3830 /* Write the low word of the double to the even register(s). */
3831 regval
= extract_unsigned_integer (val
+ low_offset
,
3834 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3835 float_argreg
, phex (regval
, 4));
3836 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3838 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3839 argreg
, phex (regval
, 4));
3840 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3842 /* Write the high word of the double to the odd register(s). */
3843 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3846 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3847 float_argreg
, phex (regval
, 4));
3848 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3851 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3852 argreg
, phex (regval
, 4));
3853 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3857 /* This is a floating point value that fits entirely
3858 in a single register. */
3859 /* On 32 bit ABI's the float_argreg is further adjusted
3860 above to ensure that it is even register aligned. */
3861 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
3863 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3864 float_argreg
, phex (regval
, len
));
3865 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3866 /* Although two FP registers are reserved for each
3867 argument, only one corresponding integer register is
3870 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3871 argreg
, phex (regval
, len
));
3872 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3874 /* Reserve space for the FP register. */
3875 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3879 /* Copy the argument to general registers or the stack in
3880 register-sized pieces. Large arguments are split between
3881 registers and stack. */
3882 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3883 are treated specially: Irix cc passes
3884 them in registers where gcc sometimes puts them on the
3885 stack. For maximum compatibility, we will put them in
3887 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3888 && len
% MIPS32_REGSIZE
!= 0);
3889 /* Structures should be aligned to eight bytes (even arg registers)
3890 on MIPS_ABI_O32, if their first member has double precision. */
3891 if (mips_type_needs_double_align (arg_type
))
3896 stack_offset
+= MIPS32_REGSIZE
;
3901 /* Remember if the argument was written to the stack. */
3902 int stack_used_p
= 0;
3903 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3906 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3909 /* Write this portion of the argument to the stack. */
3910 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3911 || odd_sized_struct
)
3913 /* Should shorter than int integer values be
3914 promoted to int before being stored? */
3915 int longword_offset
= 0;
3921 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3922 paddress (gdbarch
, stack_offset
));
3923 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3924 paddress (gdbarch
, longword_offset
));
3927 addr
= sp
+ stack_offset
+ longword_offset
;
3932 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3933 paddress (gdbarch
, addr
));
3934 for (i
= 0; i
< partial_len
; i
++)
3936 fprintf_unfiltered (gdb_stdlog
, "%02x",
3940 write_memory (addr
, val
, partial_len
);
3943 /* Note!!! This is NOT an else clause. Odd sized
3944 structs may go thru BOTH paths. */
3945 /* Write this portion of the argument to a general
3946 purpose register. */
3947 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3949 LONGEST regval
= extract_signed_integer (val
, partial_len
,
3951 /* Value may need to be sign extended, because
3952 mips_isa_regsize() != mips_abi_regsize(). */
3954 /* A non-floating-point argument being passed in a
3955 general register. If a struct or union, and if
3956 the remaining length is smaller than the register
3957 size, we have to adjust the register value on
3960 It does not seem to be necessary to do the
3961 same for integral types.
3963 Also don't do this adjustment on O64 binaries.
3965 cagney/2001-07-23: gdb/179: Also, GCC, when
3966 outputting LE O32 with sizeof (struct) <
3967 mips_abi_regsize(), generates a left shift
3968 as part of storing the argument in a register
3969 (the left shift isn't generated when
3970 sizeof (struct) >= mips_abi_regsize()). Since
3971 it is quite possible that this is GCC
3972 contradicting the LE/O32 ABI, GDB has not been
3973 adjusted to accommodate this. Either someone
3974 needs to demonstrate that the LE/O32 ABI
3975 specifies such a left shift OR this new ABI gets
3976 identified as such and GDB gets tweaked
3979 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3980 && partial_len
< MIPS32_REGSIZE
3981 && (typecode
== TYPE_CODE_STRUCT
3982 || typecode
== TYPE_CODE_UNION
))
3983 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3987 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3989 phex (regval
, MIPS32_REGSIZE
));
3990 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3993 /* Prevent subsequent floating point arguments from
3994 being passed in floating point registers. */
3995 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4001 /* Compute the the offset into the stack at which we
4002 will copy the next parameter.
4004 In older ABIs, the caller reserved space for
4005 registers that contained arguments. This was loosely
4006 refered to as their "home". Consequently, space is
4007 always allocated. */
4009 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
4013 fprintf_unfiltered (gdb_stdlog
, "\n");
4016 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4018 /* Return adjusted stack pointer. */
4022 static enum return_value_convention
4023 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4024 struct type
*type
, struct regcache
*regcache
,
4025 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4027 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4029 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4030 || TYPE_CODE (type
) == TYPE_CODE_UNION
4031 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4032 return RETURN_VALUE_STRUCT_CONVENTION
;
4033 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4034 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4036 /* A single-precision floating-point value. It fits in the
4037 least significant part of FP0. */
4039 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4040 mips_xfer_register (gdbarch
, regcache
,
4041 gdbarch_num_regs (gdbarch
)
4042 + mips_regnum (gdbarch
)->fp0
,
4044 gdbarch_byte_order (gdbarch
),
4045 readbuf
, writebuf
, 0);
4046 return RETURN_VALUE_REGISTER_CONVENTION
;
4048 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4049 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4051 /* A double-precision floating-point value. The most
4052 significant part goes in FP1, and the least significant in
4055 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4056 switch (gdbarch_byte_order (gdbarch
))
4058 case BFD_ENDIAN_LITTLE
:
4059 mips_xfer_register (gdbarch
, regcache
,
4060 gdbarch_num_regs (gdbarch
)
4061 + mips_regnum (gdbarch
)->fp0
+
4062 0, 4, gdbarch_byte_order (gdbarch
),
4063 readbuf
, writebuf
, 0);
4064 mips_xfer_register (gdbarch
, regcache
,
4065 gdbarch_num_regs (gdbarch
)
4066 + mips_regnum (gdbarch
)->fp0
+ 1,
4067 4, gdbarch_byte_order (gdbarch
),
4068 readbuf
, writebuf
, 4);
4070 case BFD_ENDIAN_BIG
:
4071 mips_xfer_register (gdbarch
, regcache
,
4072 gdbarch_num_regs (gdbarch
)
4073 + mips_regnum (gdbarch
)->fp0
+ 1,
4074 4, gdbarch_byte_order (gdbarch
),
4075 readbuf
, writebuf
, 0);
4076 mips_xfer_register (gdbarch
, regcache
,
4077 gdbarch_num_regs (gdbarch
)
4078 + mips_regnum (gdbarch
)->fp0
+ 0,
4079 4, gdbarch_byte_order (gdbarch
),
4080 readbuf
, writebuf
, 4);
4083 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4085 return RETURN_VALUE_REGISTER_CONVENTION
;
4088 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4089 && TYPE_NFIELDS (type
) <= 2
4090 && TYPE_NFIELDS (type
) >= 1
4091 && ((TYPE_NFIELDS (type
) == 1
4092 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4094 || (TYPE_NFIELDS (type
) == 2
4095 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4097 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4099 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4101 /* A struct that contains one or two floats. Each value is part
4102 in the least significant part of their floating point
4104 gdb_byte reg
[MAX_REGISTER_SIZE
];
4107 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4108 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4110 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4113 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4115 mips_xfer_register (gdbarch
, regcache
,
4116 gdbarch_num_regs (gdbarch
) + regnum
,
4117 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4118 gdbarch_byte_order (gdbarch
),
4119 readbuf
, writebuf
, offset
);
4121 return RETURN_VALUE_REGISTER_CONVENTION
;
4125 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4126 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4128 /* A structure or union. Extract the left justified value,
4129 regardless of the byte order. I.e. DO NOT USE
4133 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4134 offset
< TYPE_LENGTH (type
);
4135 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4137 int xfer
= register_size (gdbarch
, regnum
);
4138 if (offset
+ xfer
> TYPE_LENGTH (type
))
4139 xfer
= TYPE_LENGTH (type
) - offset
;
4141 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4142 offset
, xfer
, regnum
);
4143 mips_xfer_register (gdbarch
, regcache
,
4144 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4145 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4147 return RETURN_VALUE_REGISTER_CONVENTION
;
4152 /* A scalar extract each part but least-significant-byte
4153 justified. o32 thinks registers are 4 byte, regardless of
4157 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4158 offset
< TYPE_LENGTH (type
);
4159 offset
+= MIPS32_REGSIZE
, regnum
++)
4161 int xfer
= MIPS32_REGSIZE
;
4162 if (offset
+ xfer
> TYPE_LENGTH (type
))
4163 xfer
= TYPE_LENGTH (type
) - offset
;
4165 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4166 offset
, xfer
, regnum
);
4167 mips_xfer_register (gdbarch
, regcache
,
4168 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4169 gdbarch_byte_order (gdbarch
),
4170 readbuf
, writebuf
, offset
);
4172 return RETURN_VALUE_REGISTER_CONVENTION
;
4176 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4180 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4181 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4183 struct value
**args
, CORE_ADDR sp
,
4184 int struct_return
, CORE_ADDR struct_addr
)
4190 int stack_offset
= 0;
4191 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4192 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4193 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4195 /* For shared libraries, "t9" needs to point at the function
4197 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4199 /* Set the return address register to point to the entry point of
4200 the program, where a breakpoint lies in wait. */
4201 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4203 /* First ensure that the stack and structure return address (if any)
4204 are properly aligned. The stack has to be at least 64-bit
4205 aligned even on 32-bit machines, because doubles must be 64-bit
4206 aligned. For n32 and n64, stack frames need to be 128-bit
4207 aligned, so we round to this widest known alignment. */
4209 sp
= align_down (sp
, 16);
4210 struct_addr
= align_down (struct_addr
, 16);
4212 /* Now make space on the stack for the args. */
4213 for (argnum
= 0; argnum
< nargs
; argnum
++)
4215 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4216 int arglen
= TYPE_LENGTH (arg_type
);
4218 /* Allocate space on the stack. */
4219 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4221 sp
-= align_up (len
, 16);
4224 fprintf_unfiltered (gdb_stdlog
,
4225 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4226 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4228 /* Initialize the integer and float register pointers. */
4229 argreg
= MIPS_A0_REGNUM
;
4230 float_argreg
= mips_fpa0_regnum (gdbarch
);
4232 /* The struct_return pointer occupies the first parameter-passing reg. */
4236 fprintf_unfiltered (gdb_stdlog
,
4237 "mips_o64_push_dummy_call: struct_return reg=%d %s\n",
4238 argreg
, paddress (gdbarch
, struct_addr
));
4239 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4240 stack_offset
+= MIPS64_REGSIZE
;
4243 /* Now load as many as possible of the first arguments into
4244 registers, and push the rest onto the stack. Loop thru args
4245 from first to last. */
4246 for (argnum
= 0; argnum
< nargs
; argnum
++)
4248 const gdb_byte
*val
;
4249 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4250 struct value
*arg
= args
[argnum
];
4251 struct type
*arg_type
= check_typedef (value_type (arg
));
4252 int len
= TYPE_LENGTH (arg_type
);
4253 enum type_code typecode
= TYPE_CODE (arg_type
);
4256 fprintf_unfiltered (gdb_stdlog
,
4257 "mips_o64_push_dummy_call: %d len=%d type=%d",
4258 argnum
+ 1, len
, (int) typecode
);
4260 val
= value_contents (arg
);
4262 /* Function pointer arguments to mips16 code need to be made into
4264 if (typecode
== TYPE_CODE_PTR
4265 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4267 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4269 if (mips_pc_is_mips16 (addr
))
4271 store_signed_integer (valbuf
, len
, byte_order
,
4272 make_mips16_addr (addr
));
4277 /* Floating point arguments passed in registers have to be
4278 treated specially. On 32-bit architectures, doubles
4279 are passed in register pairs; the even register gets
4280 the low word, and the odd register gets the high word.
4281 On O32/O64, the first two floating point arguments are
4282 also copied to general registers, because MIPS16 functions
4283 don't use float registers for arguments. This duplication of
4284 arguments in general registers can't hurt non-MIPS16 functions
4285 because those registers are normally skipped. */
4287 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4288 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4290 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4292 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4293 float_argreg
, phex (regval
, len
));
4294 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4296 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4297 argreg
, phex (regval
, len
));
4298 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4300 /* Reserve space for the FP register. */
4301 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4305 /* Copy the argument to general registers or the stack in
4306 register-sized pieces. Large arguments are split between
4307 registers and stack. */
4308 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4309 are treated specially: Irix cc passes them in registers
4310 where gcc sometimes puts them on the stack. For maximum
4311 compatibility, we will put them in both places. */
4312 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4313 && len
% MIPS64_REGSIZE
!= 0);
4316 /* Remember if the argument was written to the stack. */
4317 int stack_used_p
= 0;
4318 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4321 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4324 /* Write this portion of the argument to the stack. */
4325 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4326 || odd_sized_struct
)
4328 /* Should shorter than int integer values be
4329 promoted to int before being stored? */
4330 int longword_offset
= 0;
4333 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4335 if ((typecode
== TYPE_CODE_INT
4336 || typecode
== TYPE_CODE_PTR
4337 || typecode
== TYPE_CODE_FLT
)
4339 longword_offset
= MIPS64_REGSIZE
- len
;
4344 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4345 paddress (gdbarch
, stack_offset
));
4346 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4347 paddress (gdbarch
, longword_offset
));
4350 addr
= sp
+ stack_offset
+ longword_offset
;
4355 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4356 paddress (gdbarch
, addr
));
4357 for (i
= 0; i
< partial_len
; i
++)
4359 fprintf_unfiltered (gdb_stdlog
, "%02x",
4363 write_memory (addr
, val
, partial_len
);
4366 /* Note!!! This is NOT an else clause. Odd sized
4367 structs may go thru BOTH paths. */
4368 /* Write this portion of the argument to a general
4369 purpose register. */
4370 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4372 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4374 /* Value may need to be sign extended, because
4375 mips_isa_regsize() != mips_abi_regsize(). */
4377 /* A non-floating-point argument being passed in a
4378 general register. If a struct or union, and if
4379 the remaining length is smaller than the register
4380 size, we have to adjust the register value on
4383 It does not seem to be necessary to do the
4384 same for integral types. */
4386 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4387 && partial_len
< MIPS64_REGSIZE
4388 && (typecode
== TYPE_CODE_STRUCT
4389 || typecode
== TYPE_CODE_UNION
))
4390 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4394 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4396 phex (regval
, MIPS64_REGSIZE
));
4397 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4400 /* Prevent subsequent floating point arguments from
4401 being passed in floating point registers. */
4402 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4408 /* Compute the the offset into the stack at which we
4409 will copy the next parameter.
4411 In older ABIs, the caller reserved space for
4412 registers that contained arguments. This was loosely
4413 refered to as their "home". Consequently, space is
4414 always allocated. */
4416 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4420 fprintf_unfiltered (gdb_stdlog
, "\n");
4423 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4425 /* Return adjusted stack pointer. */
4429 static enum return_value_convention
4430 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4431 struct type
*type
, struct regcache
*regcache
,
4432 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4434 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4436 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4437 || TYPE_CODE (type
) == TYPE_CODE_UNION
4438 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4439 return RETURN_VALUE_STRUCT_CONVENTION
;
4440 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4442 /* A floating-point value. It fits in the least significant
4445 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4446 mips_xfer_register (gdbarch
, regcache
,
4447 gdbarch_num_regs (gdbarch
)
4448 + mips_regnum (gdbarch
)->fp0
,
4450 gdbarch_byte_order (gdbarch
),
4451 readbuf
, writebuf
, 0);
4452 return RETURN_VALUE_REGISTER_CONVENTION
;
4456 /* A scalar extract each part but least-significant-byte
4460 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4461 offset
< TYPE_LENGTH (type
);
4462 offset
+= MIPS64_REGSIZE
, regnum
++)
4464 int xfer
= MIPS64_REGSIZE
;
4465 if (offset
+ xfer
> TYPE_LENGTH (type
))
4466 xfer
= TYPE_LENGTH (type
) - offset
;
4468 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4469 offset
, xfer
, regnum
);
4470 mips_xfer_register (gdbarch
, regcache
,
4471 gdbarch_num_regs (gdbarch
) + regnum
,
4472 xfer
, gdbarch_byte_order (gdbarch
),
4473 readbuf
, writebuf
, offset
);
4475 return RETURN_VALUE_REGISTER_CONVENTION
;
4479 /* Floating point register management.
4481 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4482 64bit operations, these early MIPS cpus treat fp register pairs
4483 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4484 registers and offer a compatibility mode that emulates the MIPS2 fp
4485 model. When operating in MIPS2 fp compat mode, later cpu's split
4486 double precision floats into two 32-bit chunks and store them in
4487 consecutive fp regs. To display 64-bit floats stored in this
4488 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4489 Throw in user-configurable endianness and you have a real mess.
4491 The way this works is:
4492 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4493 double-precision value will be split across two logical registers.
4494 The lower-numbered logical register will hold the low-order bits,
4495 regardless of the processor's endianness.
4496 - If we are on a 64-bit processor, and we are looking for a
4497 single-precision value, it will be in the low ordered bits
4498 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4499 save slot in memory.
4500 - If we are in 64-bit mode, everything is straightforward.
4502 Note that this code only deals with "live" registers at the top of the
4503 stack. We will attempt to deal with saved registers later, when
4504 the raw/cooked register interface is in place. (We need a general
4505 interface that can deal with dynamic saved register sizes -- fp
4506 regs could be 32 bits wide in one frame and 64 on the frame above
4509 /* Copy a 32-bit single-precision value from the current frame
4510 into rare_buffer. */
4513 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4514 gdb_byte
*rare_buffer
)
4516 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4517 int raw_size
= register_size (gdbarch
, regno
);
4518 gdb_byte
*raw_buffer
= alloca (raw_size
);
4520 if (!frame_register_read (frame
, regno
, raw_buffer
))
4521 error (_("can't read register %d (%s)"),
4522 regno
, gdbarch_register_name (gdbarch
, regno
));
4525 /* We have a 64-bit value for this register. Find the low-order
4529 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4534 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4538 memcpy (rare_buffer
, raw_buffer
, 4);
4542 /* Copy a 64-bit double-precision value from the current frame into
4543 rare_buffer. This may include getting half of it from the next
4547 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4548 gdb_byte
*rare_buffer
)
4550 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4551 int raw_size
= register_size (gdbarch
, regno
);
4553 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4555 /* We have a 64-bit value for this register, and we should use
4557 if (!frame_register_read (frame
, regno
, rare_buffer
))
4558 error (_("can't read register %d (%s)"),
4559 regno
, gdbarch_register_name (gdbarch
, regno
));
4563 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4565 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4566 internal_error (__FILE__
, __LINE__
,
4567 _("mips_read_fp_register_double: bad access to "
4568 "odd-numbered FP register"));
4570 /* mips_read_fp_register_single will find the correct 32 bits from
4572 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4574 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4575 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4579 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4580 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4586 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4588 { /* do values for FP (float) regs */
4589 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4590 gdb_byte
*raw_buffer
;
4591 double doub
, flt1
; /* doubles extracted from raw hex data */
4594 raw_buffer
= alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
));
4596 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4597 fprintf_filtered (file
, "%*s",
4598 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4601 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4603 struct value_print_options opts
;
4605 /* 4-byte registers: Print hex and floating. Also print even
4606 numbered registers as doubles. */
4607 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4608 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
, raw_buffer
, &inv1
);
4610 get_formatted_print_options (&opts
, 'x');
4611 print_scalar_formatted (raw_buffer
,
4612 builtin_type (gdbarch
)->builtin_uint32
,
4615 fprintf_filtered (file
, " flt: ");
4617 fprintf_filtered (file
, " <invalid float> ");
4619 fprintf_filtered (file
, "%-17.9g", flt1
);
4621 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4623 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4624 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4627 fprintf_filtered (file
, " dbl: ");
4629 fprintf_filtered (file
, "<invalid double>");
4631 fprintf_filtered (file
, "%-24.17g", doub
);
4636 struct value_print_options opts
;
4638 /* Eight byte registers: print each one as hex, float and double. */
4639 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4640 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4643 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4644 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4647 get_formatted_print_options (&opts
, 'x');
4648 print_scalar_formatted (raw_buffer
,
4649 builtin_type (gdbarch
)->builtin_uint64
,
4652 fprintf_filtered (file
, " flt: ");
4654 fprintf_filtered (file
, "<invalid float>");
4656 fprintf_filtered (file
, "%-17.9g", flt1
);
4658 fprintf_filtered (file
, " dbl: ");
4660 fprintf_filtered (file
, "<invalid double>");
4662 fprintf_filtered (file
, "%-24.17g", doub
);
4667 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4670 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4671 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4673 struct value_print_options opts
;
4675 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4677 mips_print_fp_register (file
, frame
, regnum
);
4681 /* Get the data in raw format. */
4682 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4684 fprintf_filtered (file
, "%s: [Invalid]",
4685 gdbarch_register_name (gdbarch
, regnum
));
4689 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4691 /* The problem with printing numeric register names (r26, etc.) is that
4692 the user can't use them on input. Probably the best solution is to
4693 fix it so that either the numeric or the funky (a2, etc.) names
4694 are accepted on input. */
4695 if (regnum
< MIPS_NUMREGS
)
4696 fprintf_filtered (file
, "(r%d): ", regnum
);
4698 fprintf_filtered (file
, ": ");
4700 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4702 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4706 get_formatted_print_options (&opts
, 'x');
4707 print_scalar_formatted (raw_buffer
+ offset
,
4708 register_type (gdbarch
, regnum
), &opts
, 0,
4712 /* Replacement for generic do_registers_info.
4713 Print regs in pretty columns. */
4716 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4719 fprintf_filtered (file
, " ");
4720 mips_print_fp_register (file
, frame
, regnum
);
4721 fprintf_filtered (file
, "\n");
4726 /* Print a row's worth of GP (int) registers, with name labels above */
4729 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4732 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4733 /* do values for GP (int) regs */
4734 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4735 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4739 /* For GP registers, we print a separate row of names above the vals */
4740 for (col
= 0, regnum
= start_regnum
;
4741 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4742 + gdbarch_num_pseudo_regs (gdbarch
);
4745 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4746 continue; /* unused register */
4747 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4749 break; /* end the row: reached FP register */
4750 /* Large registers are handled separately. */
4751 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4754 break; /* End the row before this register. */
4756 /* Print this register on a row by itself. */
4757 mips_print_register (file
, frame
, regnum
);
4758 fprintf_filtered (file
, "\n");
4762 fprintf_filtered (file
, " ");
4763 fprintf_filtered (file
,
4764 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4765 gdbarch_register_name (gdbarch
, regnum
));
4772 /* print the R0 to R31 names */
4773 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4774 fprintf_filtered (file
, "\n R%-4d",
4775 start_regnum
% gdbarch_num_regs (gdbarch
));
4777 fprintf_filtered (file
, "\n ");
4779 /* now print the values in hex, 4 or 8 to the row */
4780 for (col
= 0, regnum
= start_regnum
;
4781 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4782 + gdbarch_num_pseudo_regs (gdbarch
);
4785 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4786 continue; /* unused register */
4787 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4789 break; /* end row: reached FP register */
4790 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4791 break; /* End row: large register. */
4793 /* OK: get the data in raw format. */
4794 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4795 error (_("can't read register %d (%s)"),
4796 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4797 /* pad small registers */
4799 byte
< (mips_abi_regsize (gdbarch
)
4800 - register_size (gdbarch
, regnum
)); byte
++)
4801 printf_filtered (" ");
4802 /* Now print the register value in hex, endian order. */
4803 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4805 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4806 byte
< register_size (gdbarch
, regnum
); byte
++)
4807 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4809 for (byte
= register_size (gdbarch
, regnum
) - 1;
4811 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4812 fprintf_filtered (file
, " ");
4815 if (col
> 0) /* ie. if we actually printed anything... */
4816 fprintf_filtered (file
, "\n");
4821 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4824 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4825 struct frame_info
*frame
, int regnum
, int all
)
4827 if (regnum
!= -1) /* do one specified register */
4829 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4830 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4831 error (_("Not a valid register for the current processor type"));
4833 mips_print_register (file
, frame
, regnum
);
4834 fprintf_filtered (file
, "\n");
4837 /* do all (or most) registers */
4839 regnum
= gdbarch_num_regs (gdbarch
);
4840 while (regnum
< gdbarch_num_regs (gdbarch
)
4841 + gdbarch_num_pseudo_regs (gdbarch
))
4843 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4846 if (all
) /* true for "INFO ALL-REGISTERS" command */
4847 regnum
= print_fp_register_row (file
, frame
, regnum
);
4849 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4852 regnum
= print_gp_register_row (file
, frame
, regnum
);
4857 /* Is this a branch with a delay slot? */
4860 is_delayed (unsigned long insn
)
4863 for (i
= 0; i
< NUMOPCODES
; ++i
)
4864 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4865 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4867 return (i
< NUMOPCODES
4868 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4869 | INSN_COND_BRANCH_DELAY
4870 | INSN_COND_BRANCH_LIKELY
)));
4874 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4875 struct frame_info
*frame
)
4877 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4878 CORE_ADDR pc
= get_frame_pc (frame
);
4879 gdb_byte buf
[MIPS_INSN32_SIZE
];
4881 /* There is no branch delay slot on MIPS16. */
4882 if (mips_pc_is_mips16 (pc
))
4885 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
4888 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4889 /* If error reading memory, guess that it is not a delayed
4892 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
4895 /* To skip prologues, I use this predicate. Returns either PC itself
4896 if the code at PC does not look like a function prologue; otherwise
4897 returns an address that (if we're lucky) follows the prologue. If
4898 LENIENT, then we must skip everything which is involved in setting
4899 up the frame (it's OK to skip more, just so long as we don't skip
4900 anything which might clobber the registers which are being saved.
4901 We must skip more in the case where part of the prologue is in the
4902 delay slot of a non-prologue instruction). */
4905 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4908 CORE_ADDR func_addr
;
4910 /* See if we can determine the end of the prologue via the symbol table.
4911 If so, then return either PC, or the PC after the prologue, whichever
4913 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4915 CORE_ADDR post_prologue_pc
4916 = skip_prologue_using_sal (gdbarch
, func_addr
);
4917 if (post_prologue_pc
!= 0)
4918 return max (pc
, post_prologue_pc
);
4921 /* Can't determine prologue from the symbol table, need to examine
4924 /* Find an upper limit on the function prologue using the debug
4925 information. If the debug information could not be used to provide
4926 that bound, then use an arbitrary large number as the upper bound. */
4927 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
4929 limit_pc
= pc
+ 100; /* Magic. */
4931 if (mips_pc_is_mips16 (pc
))
4932 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4934 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4937 /* Check whether the PC is in a function epilogue (32-bit version).
4938 This is a helper function for mips_in_function_epilogue_p. */
4940 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4942 CORE_ADDR func_addr
= 0, func_end
= 0;
4944 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4946 /* The MIPS epilogue is max. 12 bytes long. */
4947 CORE_ADDR addr
= func_end
- 12;
4949 if (addr
< func_addr
+ 4)
4950 addr
= func_addr
+ 4;
4954 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4956 unsigned long high_word
;
4959 inst
= mips_fetch_instruction (gdbarch
, pc
);
4960 high_word
= (inst
>> 16) & 0xffff;
4962 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4963 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4964 && inst
!= 0x03e00008 /* jr $ra */
4965 && inst
!= 0x00000000) /* nop */
4975 /* Check whether the PC is in a function epilogue (16-bit version).
4976 This is a helper function for mips_in_function_epilogue_p. */
4978 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4980 CORE_ADDR func_addr
= 0, func_end
= 0;
4982 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4984 /* The MIPS epilogue is max. 12 bytes long. */
4985 CORE_ADDR addr
= func_end
- 12;
4987 if (addr
< func_addr
+ 4)
4988 addr
= func_addr
+ 4;
4992 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4994 unsigned short inst
;
4996 inst
= mips_fetch_instruction (gdbarch
, pc
);
4998 if ((inst
& 0xf800) == 0xf000) /* extend */
5001 if (inst
!= 0x6300 /* addiu $sp,offset */
5002 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
5003 && inst
!= 0xe820 /* jr $ra */
5004 && inst
!= 0xe8a0 /* jrc $ra */
5005 && inst
!= 0x6500) /* nop */
5015 /* The epilogue is defined here as the area at the end of a function,
5016 after an instruction which destroys the function's stack frame. */
5018 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5020 if (mips_pc_is_mips16 (pc
))
5021 return mips16_in_function_epilogue_p (gdbarch
, pc
);
5023 return mips32_in_function_epilogue_p (gdbarch
, pc
);
5026 /* Root of all "set mips "/"show mips " commands. This will eventually be
5027 used for all MIPS-specific commands. */
5030 show_mips_command (char *args
, int from_tty
)
5032 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5036 set_mips_command (char *args
, int from_tty
)
5039 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5040 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5043 /* Commands to show/set the MIPS FPU type. */
5046 show_mipsfpu_command (char *args
, int from_tty
)
5050 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5053 ("The MIPS floating-point coprocessor is unknown "
5054 "because the current architecture is not MIPS.\n");
5058 switch (MIPS_FPU_TYPE (target_gdbarch
))
5060 case MIPS_FPU_SINGLE
:
5061 fpu
= "single-precision";
5063 case MIPS_FPU_DOUBLE
:
5064 fpu
= "double-precision";
5067 fpu
= "absent (none)";
5070 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5072 if (mips_fpu_type_auto
)
5074 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5078 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5083 set_mipsfpu_command (char *args
, int from_tty
)
5086 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5087 show_mipsfpu_command (args
, from_tty
);
5091 set_mipsfpu_single_command (char *args
, int from_tty
)
5093 struct gdbarch_info info
;
5094 gdbarch_info_init (&info
);
5095 mips_fpu_type
= MIPS_FPU_SINGLE
;
5096 mips_fpu_type_auto
= 0;
5097 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5098 instead of relying on globals. Doing that would let generic code
5099 handle the search for this specific architecture. */
5100 if (!gdbarch_update_p (info
))
5101 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5105 set_mipsfpu_double_command (char *args
, int from_tty
)
5107 struct gdbarch_info info
;
5108 gdbarch_info_init (&info
);
5109 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5110 mips_fpu_type_auto
= 0;
5111 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5112 instead of relying on globals. Doing that would let generic code
5113 handle the search for this specific architecture. */
5114 if (!gdbarch_update_p (info
))
5115 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5119 set_mipsfpu_none_command (char *args
, int from_tty
)
5121 struct gdbarch_info info
;
5122 gdbarch_info_init (&info
);
5123 mips_fpu_type
= MIPS_FPU_NONE
;
5124 mips_fpu_type_auto
= 0;
5125 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5126 instead of relying on globals. Doing that would let generic code
5127 handle the search for this specific architecture. */
5128 if (!gdbarch_update_p (info
))
5129 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5133 set_mipsfpu_auto_command (char *args
, int from_tty
)
5135 mips_fpu_type_auto
= 1;
5138 /* Attempt to identify the particular processor model by reading the
5139 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5140 the relevant processor still exists (it dates back to '94) and
5141 secondly this is not the way to do this. The processor type should
5142 be set by forcing an architecture change. */
5145 deprecated_mips_set_processor_regs_hack (void)
5147 struct regcache
*regcache
= get_current_regcache ();
5148 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5149 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5152 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5153 if ((prid
& ~0xf) == 0x700)
5154 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5157 /* Just like reinit_frame_cache, but with the right arguments to be
5158 callable as an sfunc. */
5161 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5162 struct cmd_list_element
*c
)
5164 reinit_frame_cache ();
5168 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5170 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5171 disassembler needs to be able to locally determine the ISA, and
5172 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5174 if (mips_pc_is_mips16 (memaddr
))
5175 info
->mach
= bfd_mach_mips16
;
5177 /* Round down the instruction address to the appropriate boundary. */
5178 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5180 /* Set the disassembler options. */
5181 if (!info
->disassembler_options
)
5182 /* This string is not recognized explicitly by the disassembler,
5183 but it tells the disassembler to not try to guess the ABI from
5184 the bfd elf headers, such that, if the user overrides the ABI
5185 of a program linked as NewABI, the disassembly will follow the
5186 register naming conventions specified by the user. */
5187 info
->disassembler_options
= "gpr-names=32";
5189 /* Call the appropriate disassembler based on the target endian-ness. */
5190 if (info
->endian
== BFD_ENDIAN_BIG
)
5191 return print_insn_big_mips (memaddr
, info
);
5193 return print_insn_little_mips (memaddr
, info
);
5197 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5199 /* Set up the disassembler info, so that we get the right
5200 register names from libopcodes. */
5201 info
->disassembler_options
= "gpr-names=n32";
5202 info
->flavour
= bfd_target_elf_flavour
;
5204 return gdb_print_insn_mips (memaddr
, info
);
5208 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5210 /* Set up the disassembler info, so that we get the right
5211 register names from libopcodes. */
5212 info
->disassembler_options
= "gpr-names=64";
5213 info
->flavour
= bfd_target_elf_flavour
;
5215 return gdb_print_insn_mips (memaddr
, info
);
5218 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
5219 counter value to determine whether a 16- or 32-bit breakpoint should be used.
5220 It returns a pointer to a string of bytes that encode a breakpoint
5221 instruction, stores the length of the string to *lenptr, and adjusts pc (if
5222 necessary) to point to the actual memory location where the breakpoint
5223 should be inserted. */
5225 static const gdb_byte
*
5226 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
5228 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5230 if (mips_pc_is_mips16 (*pcptr
))
5232 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5233 *pcptr
= unmake_mips16_addr (*pcptr
);
5234 *lenptr
= sizeof (mips16_big_breakpoint
);
5235 return mips16_big_breakpoint
;
5239 /* The IDT board uses an unusual breakpoint value, and
5240 sometimes gets confused when it sees the usual MIPS
5241 breakpoint instruction. */
5242 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5243 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5244 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5245 /* Likewise, IRIX appears to expect a different breakpoint,
5246 although this is not apparent until you try to use pthreads. */
5247 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5249 *lenptr
= sizeof (big_breakpoint
);
5251 if (strcmp (target_shortname
, "mips") == 0)
5252 return idt_big_breakpoint
;
5253 else if (strcmp (target_shortname
, "ddb") == 0
5254 || strcmp (target_shortname
, "pmon") == 0
5255 || strcmp (target_shortname
, "lsi") == 0)
5256 return pmon_big_breakpoint
;
5257 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5258 return irix_big_breakpoint
;
5260 return big_breakpoint
;
5265 if (mips_pc_is_mips16 (*pcptr
))
5267 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5268 *pcptr
= unmake_mips16_addr (*pcptr
);
5269 *lenptr
= sizeof (mips16_little_breakpoint
);
5270 return mips16_little_breakpoint
;
5274 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5275 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5276 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5278 *lenptr
= sizeof (little_breakpoint
);
5280 if (strcmp (target_shortname
, "mips") == 0)
5281 return idt_little_breakpoint
;
5282 else if (strcmp (target_shortname
, "ddb") == 0
5283 || strcmp (target_shortname
, "pmon") == 0
5284 || strcmp (target_shortname
, "lsi") == 0)
5285 return pmon_little_breakpoint
;
5287 return little_breakpoint
;
5292 /* If PC is in a mips16 call or return stub, return the address of the target
5293 PC, which is either the callee or the caller. There are several
5294 cases which must be handled:
5296 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5297 target PC is in $31 ($ra).
5298 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5299 and the target PC is in $2.
5300 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5301 before the jal instruction, this is effectively a call stub
5302 and the the target PC is in $2. Otherwise this is effectively
5303 a return stub and the target PC is in $18.
5305 See the source code for the stubs in gcc/config/mips/mips16.S for
5309 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5311 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5313 CORE_ADDR start_addr
;
5315 /* Find the starting address and name of the function containing the PC. */
5316 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5319 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5320 target PC is in $31 ($ra). */
5321 if (strcmp (name
, "__mips16_ret_sf") == 0
5322 || strcmp (name
, "__mips16_ret_df") == 0)
5323 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5325 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5327 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5328 and the target PC is in $2. */
5329 if (name
[19] >= '0' && name
[19] <= '9')
5330 return get_frame_register_signed (frame
, 2);
5332 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5333 before the jal instruction, this is effectively a call stub
5334 and the the target PC is in $2. Otherwise this is effectively
5335 a return stub and the target PC is in $18. */
5336 else if (name
[19] == 's' || name
[19] == 'd')
5338 if (pc
== start_addr
)
5340 /* Check if the target of the stub is a compiler-generated
5341 stub. Such a stub for a function bar might have a name
5342 like __fn_stub_bar, and might look like this:
5347 la $1,bar (becomes a lui/addiu pair)
5349 So scan down to the lui/addi and extract the target
5350 address from those two instructions. */
5352 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5356 /* See if the name of the target function is __fn_stub_*. */
5357 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5360 if (strncmp (name
, "__fn_stub_", 10) != 0
5361 && strcmp (name
, "etext") != 0
5362 && strcmp (name
, "_etext") != 0)
5365 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5366 The limit on the search is arbitrarily set to 20
5367 instructions. FIXME. */
5368 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5370 inst
= mips_fetch_instruction (gdbarch
, target_pc
);
5371 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5372 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5373 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5374 return pc
| (inst
& 0xffff); /* low word */
5377 /* Couldn't find the lui/addui pair, so return stub address. */
5381 /* This is the 'return' part of a call stub. The return
5382 address is in $r18. */
5383 return get_frame_register_signed (frame
, 18);
5386 return 0; /* not a stub */
5389 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5390 PC of the stub target. The stub just loads $t9 and jumps to it,
5391 so that $t9 has the correct value at function entry. */
5394 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5396 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5397 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5398 struct minimal_symbol
*msym
;
5400 gdb_byte stub_code
[16];
5401 int32_t stub_words
[4];
5403 /* The stub for foo is named ".pic.foo", and is either two
5404 instructions inserted before foo or a three instruction sequence
5405 which jumps to foo. */
5406 msym
= lookup_minimal_symbol_by_pc (pc
);
5408 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5409 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5410 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5413 /* A two-instruction header. */
5414 if (MSYMBOL_SIZE (msym
) == 8)
5417 /* A three-instruction (plus delay slot) trampoline. */
5418 if (MSYMBOL_SIZE (msym
) == 16)
5420 if (target_read_memory (pc
, stub_code
, 16) != 0)
5422 for (i
= 0; i
< 4; i
++)
5423 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
5426 /* A stub contains these instructions:
5429 addiu t9, t9, %lo(target)
5432 This works even for N64, since stubs are only generated with
5434 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5435 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5436 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5437 && stub_words
[3] == 0x00000000)
5438 return (((stub_words
[0] & 0x0000ffff) << 16)
5439 + (stub_words
[2] & 0x0000ffff));
5442 /* Not a recognized stub. */
5447 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5449 CORE_ADDR target_pc
;
5451 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5455 target_pc
= find_solib_trampoline_target (frame
, pc
);
5459 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5466 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5467 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5470 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5473 if (num
>= 0 && num
< 32)
5475 else if (num
>= 38 && num
< 70)
5476 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5478 regnum
= mips_regnum (gdbarch
)->hi
;
5480 regnum
= mips_regnum (gdbarch
)->lo
;
5482 /* This will hopefully (eventually) provoke a warning. Should
5483 we be calling complaint() here? */
5484 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5485 return gdbarch_num_regs (gdbarch
) + regnum
;
5489 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5490 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5493 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5496 if (num
>= 0 && num
< 32)
5498 else if (num
>= 32 && num
< 64)
5499 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5501 regnum
= mips_regnum (gdbarch
)->hi
;
5503 regnum
= mips_regnum (gdbarch
)->lo
;
5505 /* This will hopefully (eventually) provoke a warning. Should we
5506 be calling complaint() here? */
5507 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5508 return gdbarch_num_regs (gdbarch
) + regnum
;
5512 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5514 /* Only makes sense to supply raw registers. */
5515 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5516 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5517 decide if it is valid. Should instead define a standard sim/gdb
5518 register numbering scheme. */
5519 if (gdbarch_register_name (gdbarch
,
5520 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5521 && gdbarch_register_name (gdbarch
,
5522 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
5525 return LEGACY_SIM_REGNO_IGNORE
;
5529 /* Convert an integer into an address. Extracting the value signed
5530 guarantees a correctly sign extended address. */
5533 mips_integer_to_address (struct gdbarch
*gdbarch
,
5534 struct type
*type
, const gdb_byte
*buf
)
5536 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5537 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
5540 /* Dummy virtual frame pointer method. This is no more or less accurate
5541 than most other architectures; we just need to be explicit about it,
5542 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5543 an assertion failure. */
5546 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5547 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5549 *reg
= MIPS_SP_REGNUM
;
5554 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5556 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5557 const char *name
= bfd_get_section_name (abfd
, sect
);
5559 if (*abip
!= MIPS_ABI_UNKNOWN
)
5562 if (strncmp (name
, ".mdebug.", 8) != 0)
5565 if (strcmp (name
, ".mdebug.abi32") == 0)
5566 *abip
= MIPS_ABI_O32
;
5567 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5568 *abip
= MIPS_ABI_N32
;
5569 else if (strcmp (name
, ".mdebug.abi64") == 0)
5570 *abip
= MIPS_ABI_N64
;
5571 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5572 *abip
= MIPS_ABI_O64
;
5573 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5574 *abip
= MIPS_ABI_EABI32
;
5575 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5576 *abip
= MIPS_ABI_EABI64
;
5578 warning (_("unsupported ABI %s."), name
+ 8);
5582 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5584 int *lbp
= (int *) obj
;
5585 const char *name
= bfd_get_section_name (abfd
, sect
);
5587 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5589 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5591 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5592 warning (_("unrecognized .gcc_compiled_longXX"));
5595 static enum mips_abi
5596 global_mips_abi (void)
5600 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5601 if (mips_abi_strings
[i
] == mips_abi_string
)
5602 return (enum mips_abi
) i
;
5604 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5608 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5610 /* If the size matches the set of 32-bit or 64-bit integer registers,
5611 assume that's what we've got. */
5612 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5613 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5615 /* If the size matches the full set of registers GDB traditionally
5616 knows about, including floating point, for either 32-bit or
5617 64-bit, assume that's what we've got. */
5618 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5619 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5621 /* Otherwise we don't have a useful guess. */
5624 static struct value
*
5625 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5627 const int *reg_p
= baton
;
5628 return value_of_register (*reg_p
, frame
);
5631 static struct gdbarch
*
5632 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5634 struct gdbarch
*gdbarch
;
5635 struct gdbarch_tdep
*tdep
;
5637 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5639 enum mips_fpu_type fpu_type
;
5640 struct tdesc_arch_data
*tdesc_data
= NULL
;
5641 int elf_fpu_type
= 0;
5643 /* Check any target description for validity. */
5644 if (tdesc_has_registers (info
.target_desc
))
5646 static const char *const mips_gprs
[] = {
5647 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5648 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5649 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5650 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5652 static const char *const mips_fprs
[] = {
5653 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5654 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5655 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5656 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5659 const struct tdesc_feature
*feature
;
5662 feature
= tdesc_find_feature (info
.target_desc
,
5663 "org.gnu.gdb.mips.cpu");
5664 if (feature
== NULL
)
5667 tdesc_data
= tdesc_data_alloc ();
5670 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5671 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5675 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5676 MIPS_EMBED_LO_REGNUM
, "lo");
5677 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5678 MIPS_EMBED_HI_REGNUM
, "hi");
5679 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5680 MIPS_EMBED_PC_REGNUM
, "pc");
5684 tdesc_data_cleanup (tdesc_data
);
5688 feature
= tdesc_find_feature (info
.target_desc
,
5689 "org.gnu.gdb.mips.cp0");
5690 if (feature
== NULL
)
5692 tdesc_data_cleanup (tdesc_data
);
5697 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5698 MIPS_EMBED_BADVADDR_REGNUM
,
5700 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5701 MIPS_PS_REGNUM
, "status");
5702 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5703 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5707 tdesc_data_cleanup (tdesc_data
);
5711 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5712 backend is not prepared for that, though. */
5713 feature
= tdesc_find_feature (info
.target_desc
,
5714 "org.gnu.gdb.mips.fpu");
5715 if (feature
== NULL
)
5717 tdesc_data_cleanup (tdesc_data
);
5722 for (i
= 0; i
< 32; i
++)
5723 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5724 i
+ MIPS_EMBED_FP0_REGNUM
,
5727 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5728 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5729 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5730 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5734 tdesc_data_cleanup (tdesc_data
);
5738 /* It would be nice to detect an attempt to use a 64-bit ABI
5739 when only 32-bit registers are provided. */
5742 /* First of all, extract the elf_flags, if available. */
5743 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5744 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5745 else if (arches
!= NULL
)
5746 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5750 fprintf_unfiltered (gdb_stdlog
,
5751 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5753 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5754 switch ((elf_flags
& EF_MIPS_ABI
))
5756 case E_MIPS_ABI_O32
:
5757 found_abi
= MIPS_ABI_O32
;
5759 case E_MIPS_ABI_O64
:
5760 found_abi
= MIPS_ABI_O64
;
5762 case E_MIPS_ABI_EABI32
:
5763 found_abi
= MIPS_ABI_EABI32
;
5765 case E_MIPS_ABI_EABI64
:
5766 found_abi
= MIPS_ABI_EABI64
;
5769 if ((elf_flags
& EF_MIPS_ABI2
))
5770 found_abi
= MIPS_ABI_N32
;
5772 found_abi
= MIPS_ABI_UNKNOWN
;
5776 /* GCC creates a pseudo-section whose name describes the ABI. */
5777 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5778 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5780 /* If we have no useful BFD information, use the ABI from the last
5781 MIPS architecture (if there is one). */
5782 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5783 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5785 /* Try the architecture for any hint of the correct ABI. */
5786 if (found_abi
== MIPS_ABI_UNKNOWN
5787 && info
.bfd_arch_info
!= NULL
5788 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5790 switch (info
.bfd_arch_info
->mach
)
5792 case bfd_mach_mips3900
:
5793 found_abi
= MIPS_ABI_EABI32
;
5795 case bfd_mach_mips4100
:
5796 case bfd_mach_mips5000
:
5797 found_abi
= MIPS_ABI_EABI64
;
5799 case bfd_mach_mips8000
:
5800 case bfd_mach_mips10000
:
5801 /* On Irix, ELF64 executables use the N64 ABI. The
5802 pseudo-sections which describe the ABI aren't present
5803 on IRIX. (Even for executables created by gcc.) */
5804 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5805 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5806 found_abi
= MIPS_ABI_N64
;
5808 found_abi
= MIPS_ABI_N32
;
5813 /* Default 64-bit objects to N64 instead of O32. */
5814 if (found_abi
== MIPS_ABI_UNKNOWN
5815 && info
.abfd
!= NULL
5816 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5817 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5818 found_abi
= MIPS_ABI_N64
;
5821 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5824 /* What has the user specified from the command line? */
5825 wanted_abi
= global_mips_abi ();
5827 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5830 /* Now that we have found what the ABI for this binary would be,
5831 check whether the user is overriding it. */
5832 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5833 mips_abi
= wanted_abi
;
5834 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5835 mips_abi
= found_abi
;
5837 mips_abi
= MIPS_ABI_O32
;
5839 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5842 /* Also used when doing an architecture lookup. */
5844 fprintf_unfiltered (gdb_stdlog
,
5845 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5846 mips64_transfers_32bit_regs_p
);
5848 /* Determine the MIPS FPU type. */
5851 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5852 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5853 Tag_GNU_MIPS_ABI_FP
);
5854 #endif /* HAVE_ELF */
5856 if (!mips_fpu_type_auto
)
5857 fpu_type
= mips_fpu_type
;
5858 else if (elf_fpu_type
!= 0)
5860 switch (elf_fpu_type
)
5863 fpu_type
= MIPS_FPU_DOUBLE
;
5866 fpu_type
= MIPS_FPU_SINGLE
;
5870 /* Soft float or unknown. */
5871 fpu_type
= MIPS_FPU_NONE
;
5875 else if (info
.bfd_arch_info
!= NULL
5876 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5877 switch (info
.bfd_arch_info
->mach
)
5879 case bfd_mach_mips3900
:
5880 case bfd_mach_mips4100
:
5881 case bfd_mach_mips4111
:
5882 case bfd_mach_mips4120
:
5883 fpu_type
= MIPS_FPU_NONE
;
5885 case bfd_mach_mips4650
:
5886 fpu_type
= MIPS_FPU_SINGLE
;
5889 fpu_type
= MIPS_FPU_DOUBLE
;
5892 else if (arches
!= NULL
)
5893 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5895 fpu_type
= MIPS_FPU_DOUBLE
;
5897 fprintf_unfiltered (gdb_stdlog
,
5898 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5900 /* Check for blatant incompatibilities. */
5902 /* If we have only 32-bit registers, then we can't debug a 64-bit
5904 if (info
.target_desc
5905 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5906 && mips_abi
!= MIPS_ABI_EABI32
5907 && mips_abi
!= MIPS_ABI_O32
)
5909 if (tdesc_data
!= NULL
)
5910 tdesc_data_cleanup (tdesc_data
);
5914 /* try to find a pre-existing architecture */
5915 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5917 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5919 /* MIPS needs to be pedantic about which ABI the object is
5921 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5923 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5925 /* Need to be pedantic about which register virtual size is
5927 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5928 != mips64_transfers_32bit_regs_p
)
5930 /* Be pedantic about which FPU is selected. */
5931 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5934 if (tdesc_data
!= NULL
)
5935 tdesc_data_cleanup (tdesc_data
);
5936 return arches
->gdbarch
;
5939 /* Need a new architecture. Fill in a target specific vector. */
5940 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5941 gdbarch
= gdbarch_alloc (&info
, tdep
);
5942 tdep
->elf_flags
= elf_flags
;
5943 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5944 tdep
->found_abi
= found_abi
;
5945 tdep
->mips_abi
= mips_abi
;
5946 tdep
->mips_fpu_type
= fpu_type
;
5947 tdep
->register_size_valid_p
= 0;
5948 tdep
->register_size
= 0;
5949 tdep
->gregset
= NULL
;
5950 tdep
->gregset64
= NULL
;
5951 tdep
->fpregset
= NULL
;
5952 tdep
->fpregset64
= NULL
;
5954 if (info
.target_desc
)
5956 /* Some useful properties can be inferred from the target. */
5957 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5959 tdep
->register_size_valid_p
= 1;
5960 tdep
->register_size
= 4;
5962 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5964 tdep
->register_size_valid_p
= 1;
5965 tdep
->register_size
= 8;
5969 /* Initially set everything according to the default ABI/ISA. */
5970 set_gdbarch_short_bit (gdbarch
, 16);
5971 set_gdbarch_int_bit (gdbarch
, 32);
5972 set_gdbarch_float_bit (gdbarch
, 32);
5973 set_gdbarch_double_bit (gdbarch
, 64);
5974 set_gdbarch_long_double_bit (gdbarch
, 64);
5975 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5976 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5977 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5979 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
5980 mips_ax_pseudo_register_collect
);
5981 set_gdbarch_ax_pseudo_register_push_stack
5982 (gdbarch
, mips_ax_pseudo_register_push_stack
);
5984 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5985 mips_elf_make_msymbol_special
);
5987 /* Fill in the OS dependant register numbers and names. */
5989 const char **reg_names
;
5990 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5991 struct mips_regnum
);
5992 if (tdesc_has_registers (info
.target_desc
))
5994 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5995 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5996 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5997 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5998 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5999 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6000 regnum
->fp_control_status
= 70;
6001 regnum
->fp_implementation_revision
= 71;
6002 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
6005 else if (info
.osabi
== GDB_OSABI_IRIX
)
6010 regnum
->badvaddr
= 66;
6013 regnum
->fp_control_status
= 69;
6014 regnum
->fp_implementation_revision
= 70;
6016 reg_names
= mips_irix_reg_names
;
6020 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6021 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6022 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6023 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6024 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6025 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6026 regnum
->fp_control_status
= 70;
6027 regnum
->fp_implementation_revision
= 71;
6029 if (info
.bfd_arch_info
!= NULL
6030 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6031 reg_names
= mips_tx39_reg_names
;
6033 reg_names
= mips_generic_reg_names
;
6035 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
6036 replaced by gdbarch_read_pc? */
6037 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6038 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6039 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6040 set_gdbarch_num_regs (gdbarch
, num_regs
);
6041 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6042 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6043 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
6044 tdep
->mips_processor_reg_names
= reg_names
;
6045 tdep
->regnum
= regnum
;
6051 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6052 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6053 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6054 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6055 tdep
->default_mask_address_p
= 0;
6056 set_gdbarch_long_bit (gdbarch
, 32);
6057 set_gdbarch_ptr_bit (gdbarch
, 32);
6058 set_gdbarch_long_long_bit (gdbarch
, 64);
6061 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6062 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6063 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6064 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6065 tdep
->default_mask_address_p
= 0;
6066 set_gdbarch_long_bit (gdbarch
, 32);
6067 set_gdbarch_ptr_bit (gdbarch
, 32);
6068 set_gdbarch_long_long_bit (gdbarch
, 64);
6070 case MIPS_ABI_EABI32
:
6071 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6072 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6073 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6074 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6075 tdep
->default_mask_address_p
= 0;
6076 set_gdbarch_long_bit (gdbarch
, 32);
6077 set_gdbarch_ptr_bit (gdbarch
, 32);
6078 set_gdbarch_long_long_bit (gdbarch
, 64);
6080 case MIPS_ABI_EABI64
:
6081 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6082 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6083 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6084 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6085 tdep
->default_mask_address_p
= 0;
6086 set_gdbarch_long_bit (gdbarch
, 64);
6087 set_gdbarch_ptr_bit (gdbarch
, 64);
6088 set_gdbarch_long_long_bit (gdbarch
, 64);
6091 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6092 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6093 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6094 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6095 tdep
->default_mask_address_p
= 0;
6096 set_gdbarch_long_bit (gdbarch
, 32);
6097 set_gdbarch_ptr_bit (gdbarch
, 32);
6098 set_gdbarch_long_long_bit (gdbarch
, 64);
6099 set_gdbarch_long_double_bit (gdbarch
, 128);
6100 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6103 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6104 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6105 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6106 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6107 tdep
->default_mask_address_p
= 0;
6108 set_gdbarch_long_bit (gdbarch
, 64);
6109 set_gdbarch_ptr_bit (gdbarch
, 64);
6110 set_gdbarch_long_long_bit (gdbarch
, 64);
6111 set_gdbarch_long_double_bit (gdbarch
, 128);
6112 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6115 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6118 /* GCC creates a pseudo-section whose name specifies the size of
6119 longs, since -mlong32 or -mlong64 may be used independent of
6120 other options. How those options affect pointer sizes is ABI and
6121 architecture dependent, so use them to override the default sizes
6122 set by the ABI. This table shows the relationship between ABI,
6123 -mlongXX, and size of pointers:
6125 ABI -mlongXX ptr bits
6126 --- -------- --------
6140 Note that for o32 and eabi32, pointers are always 32 bits
6141 regardless of any -mlongXX option. For all others, pointers and
6142 longs are the same, as set by -mlongXX or set by defaults.
6145 if (info
.abfd
!= NULL
)
6149 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6152 set_gdbarch_long_bit (gdbarch
, long_bit
);
6156 case MIPS_ABI_EABI32
:
6161 case MIPS_ABI_EABI64
:
6162 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6165 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6170 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6171 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6174 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6175 flag in object files because to do so would make it impossible to
6176 link with libraries compiled without "-gp32". This is
6177 unnecessarily restrictive.
6179 We could solve this problem by adding "-gp32" multilibs to gcc,
6180 but to set this flag before gcc is built with such multilibs will
6181 break too many systems.''
6183 But even more unhelpfully, the default linker output target for
6184 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6185 for 64-bit programs - you need to change the ABI to change this,
6186 and not all gcc targets support that currently. Therefore using
6187 this flag to detect 32-bit mode would do the wrong thing given
6188 the current gcc - it would make GDB treat these 64-bit programs
6189 as 32-bit programs by default. */
6191 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6192 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6194 /* Add/remove bits from an address. The MIPS needs be careful to
6195 ensure that all 32 bit addresses are sign extended to 64 bits. */
6196 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6198 /* Unwind the frame. */
6199 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6200 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
6201 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
6203 /* Map debug register numbers onto internal register numbers. */
6204 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6205 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6206 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6207 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6208 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6209 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6211 /* MIPS version of CALL_DUMMY */
6213 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6214 replaced by a command, and all targets will default to on stack
6215 (regardless of the stack's execute status). */
6216 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6217 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6219 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6220 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6221 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6223 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6224 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6226 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6228 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6230 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6231 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6232 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6234 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6236 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6238 if (mips_abi
== MIPS_ABI_N32
)
6239 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6240 else if (mips_abi
== MIPS_ABI_N64
)
6241 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6243 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6245 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6246 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6247 need to all be folded into the target vector. Since they are
6248 being used as guards for target_stopped_by_watchpoint, why not have
6249 target_stopped_by_watchpoint return the type of watchpoint that the code
6251 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6253 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6255 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
6257 /* Virtual tables. */
6258 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6260 mips_register_g_packet_guesses (gdbarch
);
6262 /* Hook in OS ABI-specific overrides, if they have been registered. */
6263 info
.tdep_info
= (void *) tdesc_data
;
6264 gdbarch_init_osabi (info
, gdbarch
);
6266 /* Unwind the frame. */
6267 dwarf2_append_unwinders (gdbarch
);
6268 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6269 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6270 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6271 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6272 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6273 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6274 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6278 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6279 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6281 /* Override the normal target description methods to handle our
6282 dual real and pseudo registers. */
6283 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6284 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
6286 num_regs
= gdbarch_num_regs (gdbarch
);
6287 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6288 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6289 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6292 /* Add ABI-specific aliases for the registers. */
6293 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6294 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6295 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6296 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6298 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6299 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6300 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6302 /* Add some other standard aliases. */
6303 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6304 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6305 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6307 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6308 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6309 value_of_mips_user_reg
,
6310 &mips_numeric_register_aliases
[i
].regnum
);
6316 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6318 struct gdbarch_info info
;
6320 /* Force the architecture to update, and (if it's a MIPS architecture)
6321 mips_gdbarch_init will take care of the rest. */
6322 gdbarch_info_init (&info
);
6323 gdbarch_update_p (info
);
6326 /* Print out which MIPS ABI is in use. */
6329 show_mips_abi (struct ui_file
*file
,
6331 struct cmd_list_element
*ignored_cmd
,
6332 const char *ignored_value
)
6334 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6337 "The MIPS ABI is unknown because the current architecture "
6341 enum mips_abi global_abi
= global_mips_abi ();
6342 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6343 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6345 if (global_abi
== MIPS_ABI_UNKNOWN
)
6348 "The MIPS ABI is set automatically (currently \"%s\").\n",
6350 else if (global_abi
== actual_abi
)
6353 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6357 /* Probably shouldn't happen... */
6360 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6361 actual_abi_str
, mips_abi_strings
[global_abi
]);
6367 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6369 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6373 int ef_mips_32bitmode
;
6374 /* Determine the ISA. */
6375 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6393 /* Determine the size of a pointer. */
6394 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6395 fprintf_unfiltered (file
,
6396 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6398 fprintf_unfiltered (file
,
6399 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6401 fprintf_unfiltered (file
,
6402 "mips_dump_tdep: ef_mips_arch = %d\n",
6404 fprintf_unfiltered (file
,
6405 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6406 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6407 fprintf_unfiltered (file
,
6408 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6409 mips_mask_address_p (tdep
),
6410 tdep
->default_mask_address_p
);
6412 fprintf_unfiltered (file
,
6413 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6414 MIPS_DEFAULT_FPU_TYPE
,
6415 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6416 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6417 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6419 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6420 MIPS_EABI (gdbarch
));
6421 fprintf_unfiltered (file
,
6422 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6423 MIPS_FPU_TYPE (gdbarch
),
6424 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6425 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6426 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6430 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6433 _initialize_mips_tdep (void)
6435 static struct cmd_list_element
*mipsfpulist
= NULL
;
6436 struct cmd_list_element
*c
;
6438 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6439 if (MIPS_ABI_LAST
+ 1
6440 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6441 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6443 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6445 mips_pdr_data
= register_objfile_data ();
6447 /* Create feature sets with the appropriate properties. The values
6448 are not important. */
6449 mips_tdesc_gp32
= allocate_target_description ();
6450 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6452 mips_tdesc_gp64
= allocate_target_description ();
6453 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6455 /* Add root prefix command for all "set mips"/"show mips" commands */
6456 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6457 _("Various MIPS specific commands."),
6458 &setmipscmdlist
, "set mips ", 0, &setlist
);
6460 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6461 _("Various MIPS specific commands."),
6462 &showmipscmdlist
, "show mips ", 0, &showlist
);
6464 /* Allow the user to override the ABI. */
6465 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6466 &mips_abi_string
, _("\
6467 Set the MIPS ABI used by this program."), _("\
6468 Show the MIPS ABI used by this program."), _("\
6469 This option can be set to one of:\n\
6470 auto - the default ABI associated with the current binary\n\
6479 &setmipscmdlist
, &showmipscmdlist
);
6481 /* Let the user turn off floating point and set the fence post for
6482 heuristic_proc_start. */
6484 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6485 _("Set use of MIPS floating-point coprocessor."),
6486 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6487 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6488 _("Select single-precision MIPS floating-point coprocessor."),
6490 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6491 _("Select double-precision MIPS floating-point coprocessor."),
6493 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6494 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6495 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6496 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6497 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6498 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6499 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6500 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6501 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6502 _("Select MIPS floating-point coprocessor automatically."),
6504 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6505 _("Show current use of MIPS floating-point coprocessor target."),
6508 /* We really would like to have both "0" and "unlimited" work, but
6509 command.c doesn't deal with that. So make it a var_zinteger
6510 because the user can always use "999999" or some such for unlimited. */
6511 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6512 &heuristic_fence_post
, _("\
6513 Set the distance searched for the start of a function."), _("\
6514 Show the distance searched for the start of a function."), _("\
6515 If you are debugging a stripped executable, GDB needs to search through the\n\
6516 program for the start of a function. This command sets the distance of the\n\
6517 search. The only need to set it is when debugging a stripped executable."),
6518 reinit_frame_cache_sfunc
,
6519 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
6520 &setlist
, &showlist
);
6522 /* Allow the user to control whether the upper bits of 64-bit
6523 addresses should be zeroed. */
6524 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6525 &mask_address_var
, _("\
6526 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6527 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6528 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
6529 allow GDB to determine the correct value."),
6530 NULL
, show_mask_address
,
6531 &setmipscmdlist
, &showmipscmdlist
);
6533 /* Allow the user to control the size of 32 bit registers within the
6534 raw remote packet. */
6535 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6536 &mips64_transfers_32bit_regs_p
, _("\
6537 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6539 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6541 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6542 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6543 64 bits for others. Use \"off\" to disable compatibility mode"),
6544 set_mips64_transfers_32bit_regs
,
6545 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6546 &setlist
, &showlist
);
6548 /* Debug this files internals. */
6549 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6551 Set mips debugging."), _("\
6552 Show mips debugging."), _("\
6553 When non-zero, mips specific debugging is enabled."),
6555 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
6556 &setdebuglist
, &showdebuglist
);