1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
58 static const struct objfile_data
*mips_pdr_data
;
60 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 /* A useful bit in the CP0 status register (PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE
= 4,
72 MIPS_FPU_DOUBLE_REGSIZE
= 8
76 static const char *mips_abi_string
;
78 static const char *mips_abi_strings
[] = {
89 struct frame_extra_info
91 mips_extra_func_info_t proc_desc
;
95 /* Various MIPS ISA options (related to stack analysis) can be
96 overridden dynamically. Establish an enum/array for managing
99 static const char size_auto
[] = "auto";
100 static const char size_32
[] = "32";
101 static const char size_64
[] = "64";
103 static const char *size_enums
[] = {
110 /* Some MIPS boards don't support floating point while others only
111 support single-precision floating-point operations. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int default_mask_address_p
;
141 /* Is the target using 64-bit raw integer registers but only
142 storing a left-aligned 32-bit value in each? */
143 int mips64_transfers_32bit_regs_p
;
144 /* Indexes for various registers. IRIX and embedded have
145 different values. This contains the "public" fields. Don't
146 add any that do not need to be public. */
147 const struct mips_regnum
*regnum
;
148 /* Register names table for the current register set. */
149 const char **mips_processor_reg_names
;
152 const struct mips_regnum
*
153 mips_regnum (struct gdbarch
*gdbarch
)
155 return gdbarch_tdep (gdbarch
)->regnum
;
159 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
161 return mips_regnum (gdbarch
)->fp0
+ 12;
164 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
165 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
167 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
169 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
171 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
173 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
174 functions to test, set, or clear bit 0 of addresses. */
177 is_mips16_addr (CORE_ADDR addr
)
183 make_mips16_addr (CORE_ADDR addr
)
189 unmake_mips16_addr (CORE_ADDR addr
)
191 return ((addr
) & ~1);
194 /* Return the contents of register REGNUM as a signed integer. */
197 read_signed_register (int regnum
)
199 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
200 deprecated_read_register_gen (regnum
, buf
);
201 return (extract_signed_integer
202 (buf
, register_size (current_gdbarch
, regnum
)));
206 read_signed_register_pid (int regnum
, ptid_t ptid
)
211 if (ptid_equal (ptid
, inferior_ptid
))
212 return read_signed_register (regnum
);
214 save_ptid
= inferior_ptid
;
216 inferior_ptid
= ptid
;
218 retval
= read_signed_register (regnum
);
220 inferior_ptid
= save_ptid
;
225 /* Return the MIPS ABI associated with GDBARCH. */
227 mips_abi (struct gdbarch
*gdbarch
)
229 return gdbarch_tdep (gdbarch
)->mips_abi
;
233 mips_isa_regsize (struct gdbarch
*gdbarch
)
235 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
236 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
239 /* Return the currently configured (or set) saved register size. */
241 static const char *mips_abi_regsize_string
= size_auto
;
244 mips_abi_regsize (struct gdbarch
*gdbarch
)
246 if (mips_abi_regsize_string
== size_auto
)
247 switch (mips_abi (gdbarch
))
249 case MIPS_ABI_EABI32
:
255 case MIPS_ABI_EABI64
:
257 case MIPS_ABI_UNKNOWN
:
260 internal_error (__FILE__
, __LINE__
, "bad switch");
262 else if (mips_abi_regsize_string
== size_64
)
264 else /* if (mips_abi_regsize_string == size_32) */
268 /* Functions for setting and testing a bit in a minimal symbol that
269 marks it as 16-bit function. The MSB of the minimal symbol's
270 "info" field is used for this purpose.
272 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
273 i.e. refers to a 16-bit function, and sets a "special" bit in a
274 minimal symbol to mark it as a 16-bit function
276 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
279 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
281 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
283 MSYMBOL_INFO (msym
) = (char *)
284 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
285 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
290 msymbol_is_special (struct minimal_symbol
*msym
)
292 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
295 /* XFER a value from the big/little/left end of the register.
296 Depending on the size of the value it might occupy the entire
297 register or just part of it. Make an allowance for this, aligning
298 things accordingly. */
301 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
302 enum bfd_endian endian
, bfd_byte
* in
,
303 const bfd_byte
* out
, int buf_offset
)
306 gdb_assert (reg_num
>= NUM_REGS
);
307 /* Need to transfer the left or right part of the register, based on
308 the targets byte order. */
312 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
314 case BFD_ENDIAN_LITTLE
:
317 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
321 internal_error (__FILE__
, __LINE__
, "bad switch");
324 fprintf_unfiltered (gdb_stderr
,
325 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
326 reg_num
, reg_offset
, buf_offset
, length
);
327 if (mips_debug
&& out
!= NULL
)
330 fprintf_unfiltered (gdb_stdlog
, "out ");
331 for (i
= 0; i
< length
; i
++)
332 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
335 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
338 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
340 if (mips_debug
&& in
!= NULL
)
343 fprintf_unfiltered (gdb_stdlog
, "in ");
344 for (i
= 0; i
< length
; i
++)
345 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
348 fprintf_unfiltered (gdb_stdlog
, "\n");
351 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
352 compatiblity mode. A return value of 1 means that we have
353 physical 64-bit registers, but should treat them as 32-bit registers. */
356 mips2_fp_compat (void)
358 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
360 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
365 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
366 in all the places we deal with FP registers. PR gdb/413. */
367 /* Otherwise check the FR bit in the status register - it controls
368 the FP compatiblity mode. If it is clear we are in compatibility
370 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
377 /* The amount of space reserved on the stack for registers. This is
378 different to MIPS_ABI_REGSIZE as it determines the alignment of
379 data allocated after the registers have run out. */
381 static const char *mips_stack_argsize_string
= size_auto
;
384 mips_stack_argsize (struct gdbarch
*gdbarch
)
386 if (mips_stack_argsize_string
== size_auto
)
387 return mips_abi_regsize (gdbarch
);
388 else if (mips_stack_argsize_string
== size_64
)
390 else /* if (mips_stack_argsize_string == size_32) */
394 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
396 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
397 struct frame_info
*, int);
398 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
401 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
403 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
405 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
407 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
408 struct frame_info
*next_frame
,
411 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
412 mips_extra_func_info_t proc_desc
);
414 static struct type
*mips_float_register_type (void);
415 static struct type
*mips_double_register_type (void);
417 /* The list of available "set mips " and "show mips " commands */
419 static struct cmd_list_element
*setmipscmdlist
= NULL
;
420 static struct cmd_list_element
*showmipscmdlist
= NULL
;
422 /* Integer registers 0 thru 31 are handled explicitly by
423 mips_register_name(). Processor specific registers 32 and above
424 are listed in the followign tables. */
427 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
431 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
432 "sr", "lo", "hi", "bad", "cause", "pc",
433 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
434 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
435 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
436 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
437 "fsr", "fir", "" /*"fp" */ , "",
438 "", "", "", "", "", "", "", "",
439 "", "", "", "", "", "", "", "",
442 /* Names of IDT R3041 registers. */
444 static const char *mips_r3041_reg_names
[] = {
445 "sr", "lo", "hi", "bad", "cause", "pc",
446 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
447 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
448 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
449 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
450 "fsr", "fir", "", /*"fp" */ "",
451 "", "", "bus", "ccfg", "", "", "", "",
452 "", "", "port", "cmp", "", "", "epc", "prid",
455 /* Names of tx39 registers. */
457 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
458 "sr", "lo", "hi", "bad", "cause", "pc",
459 "", "", "", "", "", "", "", "",
460 "", "", "", "", "", "", "", "",
461 "", "", "", "", "", "", "", "",
462 "", "", "", "", "", "", "", "",
464 "", "", "", "", "", "", "", "",
465 "", "", "config", "cache", "debug", "depc", "epc", ""
468 /* Names of IRIX registers. */
469 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
470 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
471 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
472 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
473 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
474 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
478 /* Return the name of the register corresponding to REGNO. */
480 mips_register_name (int regno
)
482 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
483 /* GPR names for all ABIs other than n32/n64. */
484 static char *mips_gpr_names
[] = {
485 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
486 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
487 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
488 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
491 /* GPR names for n32 and n64 ABIs. */
492 static char *mips_n32_n64_gpr_names
[] = {
493 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
494 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
495 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
496 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
499 enum mips_abi abi
= mips_abi (current_gdbarch
);
501 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
502 don't make the raw register names visible. */
503 int rawnum
= regno
% NUM_REGS
;
504 if (regno
< NUM_REGS
)
507 /* The MIPS integer registers are always mapped from 0 to 31. The
508 names of the registers (which reflects the conventions regarding
509 register use) vary depending on the ABI. */
510 if (0 <= rawnum
&& rawnum
< 32)
512 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
513 return mips_n32_n64_gpr_names
[rawnum
];
515 return mips_gpr_names
[rawnum
];
517 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
519 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
520 return tdep
->mips_processor_reg_names
[rawnum
- 32];
523 internal_error (__FILE__
, __LINE__
,
524 "mips_register_name: bad register number %d", rawnum
);
527 /* Return the groups that a MIPS register can be categorised into. */
530 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
531 struct reggroup
*reggroup
)
536 int rawnum
= regnum
% NUM_REGS
;
537 int pseudo
= regnum
/ NUM_REGS
;
538 if (reggroup
== all_reggroup
)
540 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
541 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
542 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
543 (gdbarch), as not all architectures are multi-arch. */
544 raw_p
= rawnum
< NUM_REGS
;
545 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
547 if (reggroup
== float_reggroup
)
548 return float_p
&& pseudo
;
549 if (reggroup
== vector_reggroup
)
550 return vector_p
&& pseudo
;
551 if (reggroup
== general_reggroup
)
552 return (!vector_p
&& !float_p
) && pseudo
;
553 /* Save the pseudo registers. Need to make certain that any code
554 extracting register values from a saved register cache also uses
556 if (reggroup
== save_reggroup
)
557 return raw_p
&& pseudo
;
558 /* Restore the same pseudo register. */
559 if (reggroup
== restore_reggroup
)
560 return raw_p
&& pseudo
;
564 /* Map the symbol table registers which live in the range [1 *
565 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
566 registers. Take care of alignment and size problems. */
569 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
570 int cookednum
, void *buf
)
572 int rawnum
= cookednum
% NUM_REGS
;
573 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
574 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
575 regcache_raw_read (regcache
, rawnum
, buf
);
576 else if (register_size (gdbarch
, rawnum
) >
577 register_size (gdbarch
, cookednum
))
579 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
580 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
581 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
583 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
586 internal_error (__FILE__
, __LINE__
, "bad register size");
590 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
591 struct regcache
*regcache
, int cookednum
,
594 int rawnum
= cookednum
% NUM_REGS
;
595 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
596 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
597 regcache_raw_write (regcache
, rawnum
, buf
);
598 else if (register_size (gdbarch
, rawnum
) >
599 register_size (gdbarch
, cookednum
))
601 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
602 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
603 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
605 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
608 internal_error (__FILE__
, __LINE__
, "bad register size");
611 /* Table to translate MIPS16 register field to actual register number. */
612 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
614 /* Heuristic_proc_start may hunt through the text section for a long
615 time across a 2400 baud serial line. Allows the user to limit this
618 static unsigned int heuristic_fence_post
= 0;
620 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
621 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
622 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
623 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
624 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
625 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
626 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
627 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
628 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
629 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
630 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
631 this will corrupt pdr.iline. Fortunately we don't use it. */
632 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
633 #define _PROC_MAGIC_ 0x0F0F0F0F
634 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
635 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
637 struct linked_proc_info
639 struct mips_extra_func_info info
;
640 struct linked_proc_info
*next
;
642 *linked_proc_desc_table
= NULL
;
644 /* Number of bytes of storage in the actual machine representation for
645 register N. NOTE: This defines the pseudo register type so need to
646 rebuild the architecture vector. */
648 static int mips64_transfers_32bit_regs_p
= 0;
651 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
652 struct cmd_list_element
*c
)
654 struct gdbarch_info info
;
655 gdbarch_info_init (&info
);
656 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
657 instead of relying on globals. Doing that would let generic code
658 handle the search for this specific architecture. */
659 if (!gdbarch_update_p (info
))
661 mips64_transfers_32bit_regs_p
= 0;
662 error ("32-bit compatibility mode not supported");
666 /* Convert to/from a register and the corresponding memory value. */
669 mips_convert_register_p (int regnum
, struct type
*type
)
671 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
672 && register_size (current_gdbarch
, regnum
) == 4
673 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
674 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
675 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
679 mips_register_to_value (struct frame_info
*frame
, int regnum
,
680 struct type
*type
, void *to
)
682 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
683 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
687 mips_value_to_register (struct frame_info
*frame
, int regnum
,
688 struct type
*type
, const void *from
)
690 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
691 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
694 /* Return the GDB type object for the "standard" data type of data in
698 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
700 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
701 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
702 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
704 /* The floating-point registers raw, or cooked, always match
705 mips_isa_regsize(), and also map 1:1, byte for byte. */
706 switch (gdbarch_byte_order (gdbarch
))
709 if (mips_isa_regsize (gdbarch
) == 4)
710 return builtin_type_ieee_single_big
;
712 return builtin_type_ieee_double_big
;
713 case BFD_ENDIAN_LITTLE
:
714 if (mips_isa_regsize (gdbarch
) == 4)
715 return builtin_type_ieee_single_little
;
717 return builtin_type_ieee_double_little
;
718 case BFD_ENDIAN_UNKNOWN
:
720 internal_error (__FILE__
, __LINE__
, "bad switch");
723 else if (regnum
< NUM_REGS
)
725 /* The raw or ISA registers. These are all sized according to
727 if (mips_isa_regsize (gdbarch
) == 4)
728 return builtin_type_int32
;
730 return builtin_type_int64
;
734 /* The cooked or ABI registers. These are sized according to
735 the ABI (with a few complications). */
736 if (regnum
>= (NUM_REGS
737 + mips_regnum (current_gdbarch
)->fp_control_status
)
738 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
739 /* The pseudo/cooked view of the embedded registers is always
740 32-bit. The raw view is handled below. */
741 return builtin_type_int32
;
742 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
743 /* The target, while possibly using a 64-bit register buffer,
744 is only transfering 32-bits of each integer register.
745 Reflect this in the cooked/pseudo (ABI) register value. */
746 return builtin_type_int32
;
747 else if (mips_abi_regsize (gdbarch
) == 4)
748 /* The ABI is restricted to 32-bit registers (the ISA could be
750 return builtin_type_int32
;
753 return builtin_type_int64
;
757 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
762 return read_signed_register (MIPS_SP_REGNUM
);
765 /* Should the upper word of 64-bit addresses be zeroed? */
766 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
769 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
771 switch (mask_address_var
)
773 case AUTO_BOOLEAN_TRUE
:
775 case AUTO_BOOLEAN_FALSE
:
778 case AUTO_BOOLEAN_AUTO
:
779 return tdep
->default_mask_address_p
;
781 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
787 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
789 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
790 switch (mask_address_var
)
792 case AUTO_BOOLEAN_TRUE
:
793 printf_filtered ("The 32 bit mips address mask is enabled\n");
795 case AUTO_BOOLEAN_FALSE
:
796 printf_filtered ("The 32 bit mips address mask is disabled\n");
798 case AUTO_BOOLEAN_AUTO
:
800 ("The 32 bit address mask is set automatically. Currently %s\n",
801 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
804 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
809 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
812 pc_is_mips16 (bfd_vma memaddr
)
814 struct minimal_symbol
*sym
;
816 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
817 if (is_mips16_addr (memaddr
))
820 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
821 the high bit of the info field. Use this to decide if the function is
822 MIPS16 or normal MIPS. */
823 sym
= lookup_minimal_symbol_by_pc (memaddr
);
825 return msymbol_is_special (sym
);
830 /* MIPS believes that the PC has a sign extended value. Perhaps the
831 all registers should be sign extended for simplicity? */
834 mips_read_pc (ptid_t ptid
)
836 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
840 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
842 return frame_unwind_register_signed (next_frame
,
843 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
846 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
847 dummy frame. The frame ID's base needs to match the TOS value
848 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
851 static struct frame_id
852 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
854 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
855 frame_pc_unwind (next_frame
));
859 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
861 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
864 /* This returns the PC of the first inst after the prologue. If we can't
865 find the prologue, then return 0. */
868 after_prologue (CORE_ADDR pc
, mips_extra_func_info_t proc_desc
)
870 struct symtab_and_line sal
;
871 CORE_ADDR func_addr
, func_end
;
873 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
874 to read the stack pointer from the current machine state, because
875 the current machine state has nothing to do with the information
876 we need from the proc_desc; and the process may or may not exist
879 proc_desc
= find_proc_desc (pc
, NULL
, 0);
883 /* If function is frameless, then we need to do it the hard way. I
884 strongly suspect that frameless always means prologueless... */
885 if (PROC_FRAME_REG (proc_desc
) == MIPS_SP_REGNUM
886 && PROC_FRAME_OFFSET (proc_desc
) == 0)
890 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
891 return 0; /* Unknown */
893 sal
= find_pc_line (func_addr
, 0);
895 if (sal
.end
< func_end
)
898 /* The line after the prologue is after the end of the function. In this
899 case, tell the caller to find the prologue the hard way. */
904 /* Decode a MIPS32 instruction that saves a register in the stack, and
905 set the appropriate bit in the general register mask or float register mask
906 to indicate which register is saved. This is a helper function
907 for mips_find_saved_regs. */
910 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
911 unsigned long *float_mask
)
915 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
916 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
917 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
919 /* It might be possible to use the instruction to
920 find the offset, rather than the code below which
921 is based on things being in a certain order in the
922 frame, but figuring out what the instruction's offset
923 is relative to might be a little tricky. */
924 reg
= (inst
& 0x001f0000) >> 16;
925 *gen_mask
|= (1 << reg
);
927 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
928 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
929 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
932 reg
= ((inst
& 0x001f0000) >> 16);
933 *float_mask
|= (1 << reg
);
937 /* Decode a MIPS16 instruction that saves a register in the stack, and
938 set the appropriate bit in the general register or float register mask
939 to indicate which register is saved. This is a helper function
940 for mips_find_saved_regs. */
943 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
945 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
947 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
948 *gen_mask
|= (1 << reg
);
950 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
952 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
953 *gen_mask
|= (1 << reg
);
955 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
956 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
957 *gen_mask
|= (1 << RA_REGNUM
);
961 /* Fetch and return instruction from the specified location. If the PC
962 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
965 mips_fetch_instruction (CORE_ADDR addr
)
967 char buf
[MIPS_INSTLEN
];
971 if (pc_is_mips16 (addr
))
973 instlen
= MIPS16_INSTLEN
;
974 addr
= unmake_mips16_addr (addr
);
977 instlen
= MIPS_INSTLEN
;
978 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
980 memory_error (status
, addr
);
981 return extract_unsigned_integer (buf
, instlen
);
985 mips16_fetch_instruction (CORE_ADDR addr
)
987 char buf
[MIPS_INSTLEN
];
991 instlen
= MIPS16_INSTLEN
;
992 addr
= unmake_mips16_addr (addr
);
993 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
995 memory_error (status
, addr
);
996 return extract_unsigned_integer (buf
, instlen
);
1000 mips32_fetch_instruction (CORE_ADDR addr
)
1002 char buf
[MIPS_INSTLEN
];
1005 instlen
= MIPS_INSTLEN
;
1006 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1008 memory_error (status
, addr
);
1009 return extract_unsigned_integer (buf
, instlen
);
1013 /* These the fields of 32 bit mips instructions */
1014 #define mips32_op(x) (x >> 26)
1015 #define itype_op(x) (x >> 26)
1016 #define itype_rs(x) ((x >> 21) & 0x1f)
1017 #define itype_rt(x) ((x >> 16) & 0x1f)
1018 #define itype_immediate(x) (x & 0xffff)
1020 #define jtype_op(x) (x >> 26)
1021 #define jtype_target(x) (x & 0x03ffffff)
1023 #define rtype_op(x) (x >> 26)
1024 #define rtype_rs(x) ((x >> 21) & 0x1f)
1025 #define rtype_rt(x) ((x >> 16) & 0x1f)
1026 #define rtype_rd(x) ((x >> 11) & 0x1f)
1027 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1028 #define rtype_funct(x) (x & 0x3f)
1031 mips32_relative_offset (unsigned long inst
)
1034 x
= itype_immediate (inst
);
1035 if (x
& 0x8000) /* sign bit set */
1037 x
|= 0xffff0000; /* sign extension */
1043 /* Determine whate to set a single step breakpoint while considering
1044 branch prediction */
1046 mips32_next_pc (CORE_ADDR pc
)
1050 inst
= mips_fetch_instruction (pc
);
1051 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1053 if (itype_op (inst
) >> 2 == 5)
1054 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1056 op
= (itype_op (inst
) & 0x03);
1066 goto greater_branch
;
1071 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1072 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1074 int tf
= itype_rt (inst
) & 0x01;
1075 int cnum
= itype_rt (inst
) >> 2;
1077 read_signed_register (mips_regnum (current_gdbarch
)->
1079 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1081 if (((cond
>> cnum
) & 0x01) == tf
)
1082 pc
+= mips32_relative_offset (inst
) + 4;
1087 pc
+= 4; /* Not a branch, next instruction is easy */
1090 { /* This gets way messy */
1092 /* Further subdivide into SPECIAL, REGIMM and other */
1093 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1095 case 0: /* SPECIAL */
1096 op
= rtype_funct (inst
);
1101 /* Set PC to that address */
1102 pc
= read_signed_register (rtype_rs (inst
));
1108 break; /* end SPECIAL */
1109 case 1: /* REGIMM */
1111 op
= itype_rt (inst
); /* branch condition */
1116 case 16: /* BLTZAL */
1117 case 18: /* BLTZALL */
1119 if (read_signed_register (itype_rs (inst
)) < 0)
1120 pc
+= mips32_relative_offset (inst
) + 4;
1122 pc
+= 8; /* after the delay slot */
1126 case 17: /* BGEZAL */
1127 case 19: /* BGEZALL */
1128 if (read_signed_register (itype_rs (inst
)) >= 0)
1129 pc
+= mips32_relative_offset (inst
) + 4;
1131 pc
+= 8; /* after the delay slot */
1133 /* All of the other instructions in the REGIMM category */
1138 break; /* end REGIMM */
1143 reg
= jtype_target (inst
) << 2;
1144 /* Upper four bits get never changed... */
1145 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1148 /* FIXME case JALX : */
1151 reg
= jtype_target (inst
) << 2;
1152 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1153 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1155 break; /* The new PC will be alternate mode */
1156 case 4: /* BEQ, BEQL */
1158 if (read_signed_register (itype_rs (inst
)) ==
1159 read_signed_register (itype_rt (inst
)))
1160 pc
+= mips32_relative_offset (inst
) + 4;
1164 case 5: /* BNE, BNEL */
1166 if (read_signed_register (itype_rs (inst
)) !=
1167 read_signed_register (itype_rt (inst
)))
1168 pc
+= mips32_relative_offset (inst
) + 4;
1172 case 6: /* BLEZ, BLEZL */
1173 if (read_signed_register (itype_rs (inst
) <= 0))
1174 pc
+= mips32_relative_offset (inst
) + 4;
1180 greater_branch
: /* BGTZ, BGTZL */
1181 if (read_signed_register (itype_rs (inst
) > 0))
1182 pc
+= mips32_relative_offset (inst
) + 4;
1189 } /* mips32_next_pc */
1191 /* Decoding the next place to set a breakpoint is irregular for the
1192 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1193 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1194 We dont want to set a single step instruction on the extend instruction
1198 /* Lots of mips16 instruction formats */
1199 /* Predicting jumps requires itype,ritype,i8type
1200 and their extensions extItype,extritype,extI8type
1202 enum mips16_inst_fmts
1204 itype
, /* 0 immediate 5,10 */
1205 ritype
, /* 1 5,3,8 */
1206 rrtype
, /* 2 5,3,3,5 */
1207 rritype
, /* 3 5,3,3,5 */
1208 rrrtype
, /* 4 5,3,3,3,2 */
1209 rriatype
, /* 5 5,3,3,1,4 */
1210 shifttype
, /* 6 5,3,3,3,2 */
1211 i8type
, /* 7 5,3,8 */
1212 i8movtype
, /* 8 5,3,3,5 */
1213 i8mov32rtype
, /* 9 5,3,5,3 */
1214 i64type
, /* 10 5,3,8 */
1215 ri64type
, /* 11 5,3,3,5 */
1216 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1217 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1218 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1219 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1220 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1221 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1222 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1223 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1224 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1225 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1227 /* I am heaping all the fields of the formats into one structure and
1228 then, only the fields which are involved in instruction extension */
1232 unsigned int regx
; /* Function in i8 type */
1237 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1238 for the bits which make up the immediatate extension. */
1241 extended_offset (unsigned int extension
)
1244 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1246 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1248 value
|= extension
& 0x01f; /* extract 4:0 */
1252 /* Only call this function if you know that this is an extendable
1253 instruction, It wont malfunction, but why make excess remote memory references?
1254 If the immediate operands get sign extended or somthing, do it after
1255 the extension is performed.
1257 /* FIXME: Every one of these cases needs to worry about sign extension
1258 when the offset is to be used in relative addressing */
1262 fetch_mips_16 (CORE_ADDR pc
)
1265 pc
&= 0xfffffffe; /* clear the low order bit */
1266 target_read_memory (pc
, buf
, 2);
1267 return extract_unsigned_integer (buf
, 2);
1271 unpack_mips16 (CORE_ADDR pc
,
1272 unsigned int extension
,
1274 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1279 switch (insn_format
)
1286 value
= extended_offset (extension
);
1287 value
= value
<< 11; /* rom for the original value */
1288 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1292 value
= inst
& 0x7ff;
1293 /* FIXME : Consider sign extension */
1302 { /* A register identifier and an offset */
1303 /* Most of the fields are the same as I type but the
1304 immediate value is of a different length */
1308 value
= extended_offset (extension
);
1309 value
= value
<< 8; /* from the original instruction */
1310 value
|= inst
& 0xff; /* eleven bits from instruction */
1311 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1312 if (value
& 0x4000) /* test the sign bit , bit 26 */
1314 value
&= ~0x3fff; /* remove the sign bit */
1320 value
= inst
& 0xff; /* 8 bits */
1321 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1322 /* FIXME: Do sign extension , this format needs it */
1323 if (value
& 0x80) /* THIS CONFUSES ME */
1325 value
&= 0xef; /* remove the sign bit */
1335 unsigned long value
;
1336 unsigned int nexthalf
;
1337 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1338 value
= value
<< 16;
1339 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1347 internal_error (__FILE__
, __LINE__
, "bad switch");
1349 upk
->offset
= offset
;
1356 add_offset_16 (CORE_ADDR pc
, int offset
)
1358 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1362 extended_mips16_next_pc (CORE_ADDR pc
,
1363 unsigned int extension
, unsigned int insn
)
1365 int op
= (insn
>> 11);
1368 case 2: /* Branch */
1371 struct upk_mips16 upk
;
1372 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1373 offset
= upk
.offset
;
1379 pc
+= (offset
<< 1) + 2;
1382 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1384 struct upk_mips16 upk
;
1385 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1386 pc
= add_offset_16 (pc
, upk
.offset
);
1387 if ((insn
>> 10) & 0x01) /* Exchange mode */
1388 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1395 struct upk_mips16 upk
;
1397 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1398 reg
= read_signed_register (upk
.regx
);
1400 pc
+= (upk
.offset
<< 1) + 2;
1407 struct upk_mips16 upk
;
1409 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1410 reg
= read_signed_register (upk
.regx
);
1412 pc
+= (upk
.offset
<< 1) + 2;
1417 case 12: /* I8 Formats btez btnez */
1419 struct upk_mips16 upk
;
1421 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1422 /* upk.regx contains the opcode */
1423 reg
= read_signed_register (24); /* Test register is 24 */
1424 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1425 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1426 /* pc = add_offset_16(pc,upk.offset) ; */
1427 pc
+= (upk
.offset
<< 1) + 2;
1432 case 29: /* RR Formats JR, JALR, JALR-RA */
1434 struct upk_mips16 upk
;
1435 /* upk.fmt = rrtype; */
1440 upk
.regx
= (insn
>> 8) & 0x07;
1441 upk
.regy
= (insn
>> 5) & 0x07;
1449 break; /* Function return instruction */
1455 break; /* BOGUS Guess */
1457 pc
= read_signed_register (reg
);
1464 /* This is an instruction extension. Fetch the real instruction
1465 (which follows the extension) and decode things based on
1469 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1482 mips16_next_pc (CORE_ADDR pc
)
1484 unsigned int insn
= fetch_mips_16 (pc
);
1485 return extended_mips16_next_pc (pc
, 0, insn
);
1488 /* The mips_next_pc function supports single_step when the remote
1489 target monitor or stub is not developed enough to do a single_step.
1490 It works by decoding the current instruction and predicting where a
1491 branch will go. This isnt hard because all the data is available.
1492 The MIPS32 and MIPS16 variants are quite different */
1494 mips_next_pc (CORE_ADDR pc
)
1497 return mips16_next_pc (pc
);
1499 return mips32_next_pc (pc
);
1502 struct mips_frame_cache
1505 struct trad_frame_saved_reg
*saved_regs
;
1509 static struct mips_frame_cache
*
1510 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1512 mips_extra_func_info_t proc_desc
;
1513 struct mips_frame_cache
*cache
;
1514 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1515 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1516 /* r0 bit means kernel trap */
1518 /* What registers have been saved? Bitmasks. */
1519 unsigned long gen_mask
, float_mask
;
1521 if ((*this_cache
) != NULL
)
1522 return (*this_cache
);
1523 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1524 (*this_cache
) = cache
;
1525 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1527 /* Get the mdebug proc descriptor. */
1528 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
, 1);
1529 if (proc_desc
== NULL
)
1530 /* I'm not sure how/whether this can happen. Normally when we
1531 can't find a proc_desc, we "synthesize" one using
1532 heuristic_proc_desc and set the saved_regs right away. */
1535 /* Extract the frame's base. */
1536 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1537 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1539 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1540 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1541 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1543 /* In any frame other than the innermost or a frame interrupted by a
1544 signal, we assume that all registers have been saved. This
1545 assumes that all register saves in a function happen before the
1546 first function call. */
1547 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1548 /* Not sure exactly what kernel_trap means, but if it means the
1549 kernel saves the registers without a prologue doing it, we
1550 better not examine the prologue to see whether registers
1551 have been saved yet. */
1554 /* We need to figure out whether the registers that the
1555 proc_desc claims are saved have been saved yet. */
1559 /* Bitmasks; set if we have found a save for the register. */
1560 unsigned long gen_save_found
= 0;
1561 unsigned long float_save_found
= 0;
1564 /* If the address is odd, assume this is MIPS16 code. */
1565 addr
= PROC_LOW_ADDR (proc_desc
);
1566 mips16
= pc_is_mips16 (addr
);
1568 /* Scan through this function's instructions preceding the
1569 current PC, and look for those that save registers. */
1570 while (addr
< frame_pc_unwind (next_frame
))
1574 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1576 addr
+= MIPS16_INSTLEN
;
1580 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1581 &gen_save_found
, &float_save_found
);
1582 addr
+= MIPS_INSTLEN
;
1585 gen_mask
= gen_save_found
;
1586 float_mask
= float_save_found
;
1589 /* Fill in the offsets for the registers which gen_mask says were
1592 CORE_ADDR reg_position
= (cache
->base
1593 + PROC_REG_OFFSET (proc_desc
));
1595 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1596 if (gen_mask
& 0x80000000)
1598 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1599 reg_position
-= mips_abi_regsize (gdbarch
);
1603 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1604 order of that normally used by gcc. Therefore, we have to fetch
1605 the first instruction of the function, and if it's an entry
1606 instruction that saves $s0 or $s1, correct their saved addresses. */
1607 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1609 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1610 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1614 int sreg_count
= (inst
>> 6) & 3;
1616 /* Check if the ra register was pushed on the stack. */
1617 CORE_ADDR reg_position
= (cache
->base
1618 + PROC_REG_OFFSET (proc_desc
));
1620 reg_position
-= mips_abi_regsize (gdbarch
);
1622 /* Check if the s0 and s1 registers were pushed on the
1624 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1626 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1628 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1629 reg_position
-= mips_abi_regsize (gdbarch
);
1634 /* Fill in the offsets for the registers which float_mask says were
1637 CORE_ADDR reg_position
= (cache
->base
1638 + PROC_FREG_OFFSET (proc_desc
));
1640 /* Fill in the offsets for the float registers which float_mask
1642 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1643 if (float_mask
& 0x80000000)
1645 if (mips_abi_regsize (gdbarch
) == 4
1646 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1648 /* On a big endian 32 bit ABI, floating point registers
1649 are paired to form doubles such that the most
1650 significant part is in $f[N+1] and the least
1651 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1652 registers are also spilled as a pair and stored as a
1655 When little-endian the least significant part is
1656 stored first leading to the memory order $f[N] and
1659 Unfortunately, when big-endian the most significant
1660 part of the double is stored first, and the least
1661 significant is stored second. This leads to the
1662 registers being ordered in memory as firt $f[N+1] and
1665 For the big-endian case make certain that the
1666 addresses point at the correct (swapped) locations
1667 $f[N] and $f[N+1] pair (keep in mind that
1668 reg_position is decremented each time through the
1671 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1672 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1674 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1675 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1678 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1679 .addr
= reg_position
;
1680 reg_position
-= mips_abi_regsize (gdbarch
);
1683 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1684 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1687 /* SP_REGNUM, contains the value and not the address. */
1688 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1690 return (*this_cache
);
1694 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1695 struct frame_id
*this_id
)
1697 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1699 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1703 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1705 int regnum
, int *optimizedp
,
1706 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1707 int *realnump
, void *valuep
)
1709 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1711 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1712 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1715 static const struct frame_unwind mips_mdebug_frame_unwind
=
1718 mips_mdebug_frame_this_id
,
1719 mips_mdebug_frame_prev_register
1722 static const struct frame_unwind
*
1723 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1725 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1726 CORE_ADDR startaddr
= 0;
1727 mips_extra_func_info_t proc_desc
;
1730 /* Only use the mdebug frame unwinder on mdebug frames where all the
1731 registers have been saved. Leave hard cases such as no mdebug or
1732 in prologue for the heuristic unwinders. */
1734 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1735 if (proc_desc
== NULL
)
1738 /* Not sure exactly what kernel_trap means, but if it means the
1739 kernel saves the registers without a prologue doing it, we better
1740 not examine the prologue to see whether registers have been saved
1742 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1744 return &mips_mdebug_frame_unwind
;
1746 /* In any frame other than the innermost or a frame interrupted by a
1747 signal, we assume that all registers have been saved. This
1748 assumes that all register saves in a function happen before the
1749 first function call. */
1750 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1751 return &mips_mdebug_frame_unwind
;
1757 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1760 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1765 static const struct frame_base mips_mdebug_frame_base
= {
1766 &mips_mdebug_frame_unwind
,
1767 mips_mdebug_frame_base_address
,
1768 mips_mdebug_frame_base_address
,
1769 mips_mdebug_frame_base_address
1772 static const struct frame_base
*
1773 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1775 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1776 return &mips_mdebug_frame_base
;
1781 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1782 Procedures that use the 32-bit instruction set are handled by the
1783 mips_insn32 unwinder. */
1785 static struct mips_frame_cache
*
1786 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1788 mips_extra_func_info_t proc_desc
;
1789 struct mips_frame_cache
*cache
;
1790 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1791 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1792 /* r0 bit means kernel trap */
1794 /* What registers have been saved? Bitmasks. */
1795 unsigned long gen_mask
, float_mask
;
1797 if ((*this_cache
) != NULL
)
1798 return (*this_cache
);
1799 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1800 (*this_cache
) = cache
;
1801 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1803 /* Get the mdebug proc descriptor. */
1804 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
, 1);
1805 if (proc_desc
== NULL
)
1806 /* I'm not sure how/whether this can happen. Normally when we
1807 can't find a proc_desc, we "synthesize" one using
1808 heuristic_proc_desc and set the saved_regs right away. */
1811 /* Extract the frame's base. */
1812 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1813 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1815 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1816 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1817 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1819 /* In any frame other than the innermost or a frame interrupted by a
1820 signal, we assume that all registers have been saved. This
1821 assumes that all register saves in a function happen before the
1822 first function call. */
1823 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1824 /* Not sure exactly what kernel_trap means, but if it means the
1825 kernel saves the registers without a prologue doing it, we
1826 better not examine the prologue to see whether registers
1827 have been saved yet. */
1830 /* We need to figure out whether the registers that the
1831 proc_desc claims are saved have been saved yet. */
1835 /* Bitmasks; set if we have found a save for the register. */
1836 unsigned long gen_save_found
= 0;
1837 unsigned long float_save_found
= 0;
1840 /* If the address is odd, assume this is MIPS16 code. */
1841 addr
= PROC_LOW_ADDR (proc_desc
);
1842 mips16
= pc_is_mips16 (addr
);
1844 /* Scan through this function's instructions preceding the
1845 current PC, and look for those that save registers. */
1846 while (addr
< frame_pc_unwind (next_frame
))
1850 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1852 addr
+= MIPS16_INSTLEN
;
1856 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1857 &gen_save_found
, &float_save_found
);
1858 addr
+= MIPS_INSTLEN
;
1861 gen_mask
= gen_save_found
;
1862 float_mask
= float_save_found
;
1865 /* Fill in the offsets for the registers which gen_mask says were
1868 CORE_ADDR reg_position
= (cache
->base
1869 + PROC_REG_OFFSET (proc_desc
));
1871 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1872 if (gen_mask
& 0x80000000)
1874 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1875 reg_position
-= mips_abi_regsize (gdbarch
);
1879 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1880 order of that normally used by gcc. Therefore, we have to fetch
1881 the first instruction of the function, and if it's an entry
1882 instruction that saves $s0 or $s1, correct their saved addresses. */
1883 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1885 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1886 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1890 int sreg_count
= (inst
>> 6) & 3;
1892 /* Check if the ra register was pushed on the stack. */
1893 CORE_ADDR reg_position
= (cache
->base
1894 + PROC_REG_OFFSET (proc_desc
));
1896 reg_position
-= mips_abi_regsize (gdbarch
);
1898 /* Check if the s0 and s1 registers were pushed on the
1900 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1902 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1904 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1905 reg_position
-= mips_abi_regsize (gdbarch
);
1910 /* Fill in the offsets for the registers which float_mask says were
1913 CORE_ADDR reg_position
= (cache
->base
1914 + PROC_FREG_OFFSET (proc_desc
));
1916 /* Fill in the offsets for the float registers which float_mask
1918 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1919 if (float_mask
& 0x80000000)
1921 if (mips_abi_regsize (gdbarch
) == 4
1922 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1924 /* On a big endian 32 bit ABI, floating point registers
1925 are paired to form doubles such that the most
1926 significant part is in $f[N+1] and the least
1927 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1928 registers are also spilled as a pair and stored as a
1931 When little-endian the least significant part is
1932 stored first leading to the memory order $f[N] and
1935 Unfortunately, when big-endian the most significant
1936 part of the double is stored first, and the least
1937 significant is stored second. This leads to the
1938 registers being ordered in memory as firt $f[N+1] and
1941 For the big-endian case make certain that the
1942 addresses point at the correct (swapped) locations
1943 $f[N] and $f[N+1] pair (keep in mind that
1944 reg_position is decremented each time through the
1947 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1948 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1950 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1951 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1954 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1955 .addr
= reg_position
;
1956 reg_position
-= mips_abi_regsize (gdbarch
);
1959 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1960 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1963 /* SP_REGNUM, contains the value and not the address. */
1964 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1966 return (*this_cache
);
1970 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1971 struct frame_id
*this_id
)
1973 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1975 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1979 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1981 int regnum
, int *optimizedp
,
1982 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1983 int *realnump
, void *valuep
)
1985 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1987 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1988 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1991 static const struct frame_unwind mips_insn16_frame_unwind
=
1994 mips_insn16_frame_this_id
,
1995 mips_insn16_frame_prev_register
1998 static const struct frame_unwind
*
1999 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
2001 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2002 if (pc_is_mips16 (pc
))
2003 return &mips_insn16_frame_unwind
;
2008 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
2011 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2016 static const struct frame_base mips_insn16_frame_base
=
2018 &mips_insn16_frame_unwind
,
2019 mips_insn16_frame_base_address
,
2020 mips_insn16_frame_base_address
,
2021 mips_insn16_frame_base_address
2024 static const struct frame_base
*
2025 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
2027 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
2028 return &mips_insn16_frame_base
;
2033 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2034 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2035 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2038 static struct mips_frame_cache
*
2039 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2041 mips_extra_func_info_t proc_desc
;
2042 struct mips_frame_cache
*cache
;
2043 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2044 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2045 /* r0 bit means kernel trap */
2047 /* What registers have been saved? Bitmasks. */
2048 unsigned long gen_mask
, float_mask
;
2050 if ((*this_cache
) != NULL
)
2051 return (*this_cache
);
2052 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2053 (*this_cache
) = cache
;
2054 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2056 /* Get the mdebug proc descriptor. */
2057 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
, 1);
2058 if (proc_desc
== NULL
)
2059 /* I'm not sure how/whether this can happen. Normally when we
2060 can't find a proc_desc, we "synthesize" one using
2061 heuristic_proc_desc and set the saved_regs right away. */
2064 /* Extract the frame's base. */
2065 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2066 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2068 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
2069 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
2070 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
2072 /* In any frame other than the innermost or a frame interrupted by a
2073 signal, we assume that all registers have been saved. This
2074 assumes that all register saves in a function happen before the
2075 first function call. */
2076 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
2077 /* Not sure exactly what kernel_trap means, but if it means the
2078 kernel saves the registers without a prologue doing it, we
2079 better not examine the prologue to see whether registers
2080 have been saved yet. */
2083 /* We need to figure out whether the registers that the
2084 proc_desc claims are saved have been saved yet. */
2088 /* Bitmasks; set if we have found a save for the register. */
2089 unsigned long gen_save_found
= 0;
2090 unsigned long float_save_found
= 0;
2093 /* If the address is odd, assume this is MIPS16 code. */
2094 addr
= PROC_LOW_ADDR (proc_desc
);
2095 mips16
= pc_is_mips16 (addr
);
2097 /* Scan through this function's instructions preceding the
2098 current PC, and look for those that save registers. */
2099 while (addr
< frame_pc_unwind (next_frame
))
2103 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
2105 addr
+= MIPS16_INSTLEN
;
2109 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
2110 &gen_save_found
, &float_save_found
);
2111 addr
+= MIPS_INSTLEN
;
2114 gen_mask
= gen_save_found
;
2115 float_mask
= float_save_found
;
2118 /* Fill in the offsets for the registers which gen_mask says were
2121 CORE_ADDR reg_position
= (cache
->base
2122 + PROC_REG_OFFSET (proc_desc
));
2124 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
2125 if (gen_mask
& 0x80000000)
2127 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
2128 reg_position
-= mips_abi_regsize (gdbarch
);
2132 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
2133 order of that normally used by gcc. Therefore, we have to fetch
2134 the first instruction of the function, and if it's an entry
2135 instruction that saves $s0 or $s1, correct their saved addresses. */
2136 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
2138 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
2139 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
2143 int sreg_count
= (inst
>> 6) & 3;
2145 /* Check if the ra register was pushed on the stack. */
2146 CORE_ADDR reg_position
= (cache
->base
2147 + PROC_REG_OFFSET (proc_desc
));
2149 reg_position
-= mips_abi_regsize (gdbarch
);
2151 /* Check if the s0 and s1 registers were pushed on the
2153 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
2155 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2157 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
2158 reg_position
-= mips_abi_regsize (gdbarch
);
2163 /* Fill in the offsets for the registers which float_mask says were
2166 CORE_ADDR reg_position
= (cache
->base
2167 + PROC_FREG_OFFSET (proc_desc
));
2169 /* Fill in the offsets for the float registers which float_mask
2171 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
2172 if (float_mask
& 0x80000000)
2174 if (mips_abi_regsize (gdbarch
) == 4
2175 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2177 /* On a big endian 32 bit ABI, floating point registers
2178 are paired to form doubles such that the most
2179 significant part is in $f[N+1] and the least
2180 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
2181 registers are also spilled as a pair and stored as a
2184 When little-endian the least significant part is
2185 stored first leading to the memory order $f[N] and
2188 Unfortunately, when big-endian the most significant
2189 part of the double is stored first, and the least
2190 significant is stored second. This leads to the
2191 registers being ordered in memory as firt $f[N+1] and
2194 For the big-endian case make certain that the
2195 addresses point at the correct (swapped) locations
2196 $f[N] and $f[N+1] pair (keep in mind that
2197 reg_position is decremented each time through the
2200 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
2201 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
2203 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
2204 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
2207 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
2208 .addr
= reg_position
;
2209 reg_position
-= mips_abi_regsize (gdbarch
);
2212 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2213 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2216 /* SP_REGNUM, contains the value and not the address. */
2217 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2219 return (*this_cache
);
2223 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2224 struct frame_id
*this_id
)
2226 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2228 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2232 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2234 int regnum
, int *optimizedp
,
2235 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2236 int *realnump
, void *valuep
)
2238 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2240 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2241 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2244 static const struct frame_unwind mips_insn32_frame_unwind
=
2247 mips_insn32_frame_this_id
,
2248 mips_insn32_frame_prev_register
2251 static const struct frame_unwind
*
2252 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2254 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2255 if (! pc_is_mips16 (pc
))
2256 return &mips_insn32_frame_unwind
;
2261 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2264 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2269 static const struct frame_base mips_insn32_frame_base
=
2271 &mips_insn32_frame_unwind
,
2272 mips_insn32_frame_base_address
,
2273 mips_insn32_frame_base_address
,
2274 mips_insn32_frame_base_address
2277 static const struct frame_base
*
2278 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2280 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2281 return &mips_insn32_frame_base
;
2286 static struct trad_frame_cache
*
2287 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2290 CORE_ADDR start_addr
;
2291 CORE_ADDR stack_addr
;
2292 struct trad_frame_cache
*this_trad_cache
;
2294 if ((*this_cache
) != NULL
)
2295 return (*this_cache
);
2296 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2297 (*this_cache
) = this_trad_cache
;
2299 /* The return address is in the link register. */
2300 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, RA_REGNUM
);
2302 /* Frame ID, since it's a frameless / stackless function, no stack
2303 space is allocated and SP on entry is the current SP. */
2304 pc
= frame_pc_unwind (next_frame
);
2305 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2306 stack_addr
= frame_unwind_register_signed (next_frame
, SP_REGNUM
);
2307 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2309 /* Assume that the frame's base is the same as the
2311 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2313 return this_trad_cache
;
2317 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2318 struct frame_id
*this_id
)
2320 struct trad_frame_cache
*this_trad_cache
2321 = mips_stub_frame_cache (next_frame
, this_cache
);
2322 trad_frame_get_id (this_trad_cache
, this_id
);
2326 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2328 int regnum
, int *optimizedp
,
2329 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2330 int *realnump
, void *valuep
)
2332 struct trad_frame_cache
*this_trad_cache
2333 = mips_stub_frame_cache (next_frame
, this_cache
);
2334 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2335 lvalp
, addrp
, realnump
, valuep
);
2338 static const struct frame_unwind mips_stub_frame_unwind
=
2341 mips_stub_frame_this_id
,
2342 mips_stub_frame_prev_register
2345 static const struct frame_unwind
*
2346 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2348 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2349 if (in_plt_section (pc
, NULL
))
2350 return &mips_stub_frame_unwind
;
2356 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2359 struct trad_frame_cache
*this_trad_cache
2360 = mips_stub_frame_cache (next_frame
, this_cache
);
2361 return trad_frame_get_this_base (this_trad_cache
);
2364 static const struct frame_base mips_stub_frame_base
=
2366 &mips_stub_frame_unwind
,
2367 mips_stub_frame_base_address
,
2368 mips_stub_frame_base_address
,
2369 mips_stub_frame_base_address
2372 static const struct frame_base
*
2373 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2375 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2376 return &mips_stub_frame_base
;
2382 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2384 /* Always a pseudo. */
2385 gdb_assert (regno
>= NUM_REGS
);
2389 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2392 else if ((regno
% NUM_REGS
) == MIPS_SP_REGNUM
)
2393 /* MIPS_SP_REGNUM is special, its value is stored in saved_regs.
2394 In fact, it is so special that it can even only be fetched
2395 using a raw register number! Once this code as been converted
2396 to frame-unwind the problem goes away. */
2397 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
2399 return frame_unwind_register_signed (fi
, regno
);
2403 /* mips_addr_bits_remove - remove useless address bits */
2406 mips_addr_bits_remove (CORE_ADDR addr
)
2408 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2409 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2410 /* This hack is a work-around for existing boards using PMON, the
2411 simulator, and any other 64-bit targets that doesn't have true
2412 64-bit addressing. On these targets, the upper 32 bits of
2413 addresses are ignored by the hardware. Thus, the PC or SP are
2414 likely to have been sign extended to all 1s by instruction
2415 sequences that load 32-bit addresses. For example, a typical
2416 piece of code that loads an address is this:
2418 lui $r2, <upper 16 bits>
2419 ori $r2, <lower 16 bits>
2421 But the lui sign-extends the value such that the upper 32 bits
2422 may be all 1s. The workaround is simply to mask off these
2423 bits. In the future, gcc may be changed to support true 64-bit
2424 addressing, and this masking will have to be disabled. */
2425 return addr
&= 0xffffffffUL
;
2430 /* mips_software_single_step() is called just before we want to resume
2431 the inferior, if we want to single-step it but there is no hardware
2432 or kernel single-step support (MIPS on GNU/Linux for example). We find
2433 the target of the coming instruction and breakpoint it.
2435 single_step is also called just after the inferior stops. If we had
2436 set up a simulated single-step, we undo our damage. */
2439 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2441 static CORE_ADDR next_pc
;
2442 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2443 static binsn_quantum break_mem
;
2446 if (insert_breakpoints_p
)
2448 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2449 next_pc
= mips_next_pc (pc
);
2451 target_insert_breakpoint (next_pc
, break_mem
);
2454 target_remove_breakpoint (next_pc
, break_mem
);
2457 static struct mips_extra_func_info temp_proc_desc
;
2459 /* This hack will go away once the get_prev_frame() code has been
2460 modified to set the frame's type first. That is BEFORE init extra
2461 frame info et.al. is called. This is because it will become
2462 possible to skip the init extra info call for sigtramp and dummy
2464 static CORE_ADDR
*temp_saved_regs
;
2466 /* Set a register's saved stack address in temp_saved_regs. If an
2467 address has already been set for this register, do nothing; this
2468 way we will only recognize the first save of a given register in a
2471 For simplicity, save the address in both [0 .. NUM_REGS) and
2472 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
2473 is used as it is only second range (the ABI instead of ISA
2474 registers) that comes into play when finding saved registers in a
2478 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
2480 if (saved_regs
[regno
] == 0)
2482 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
2483 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
2488 /* Test whether the PC points to the return instruction at the
2489 end of a function. */
2492 mips_about_to_return (CORE_ADDR pc
)
2494 if (pc_is_mips16 (pc
))
2495 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2496 generates a "jr $ra"; other times it generates code to load
2497 the return address from the stack to an accessible register (such
2498 as $a3), then a "jr" using that register. This second case
2499 is almost impossible to distinguish from an indirect jump
2500 used for switch statements, so we don't even try. */
2501 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2503 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2507 /* This fencepost looks highly suspicious to me. Removing it also
2508 seems suspicious as it could affect remote debugging across serial
2512 heuristic_proc_start (CORE_ADDR pc
)
2519 pc
= ADDR_BITS_REMOVE (pc
);
2521 fence
= start_pc
- heuristic_fence_post
;
2525 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2526 fence
= VM_MIN_ADDRESS
;
2528 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
2530 /* search back for previous return */
2531 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2532 if (start_pc
< fence
)
2534 /* It's not clear to me why we reach this point when
2535 stop_soon, but with this test, at least we
2536 don't print out warnings for every child forked (eg, on
2537 decstation). 22apr93 rich@cygnus.com. */
2538 if (stop_soon
== NO_STOP_QUIETLY
)
2540 static int blurb_printed
= 0;
2542 warning ("GDB can't find the start of the function at 0x%s.",
2547 /* This actually happens frequently in embedded
2548 development, when you first connect to a board
2549 and your stack pointer and pc are nowhere in
2550 particular. This message needs to give people
2551 in that situation enough information to
2552 determine that it's no big deal. */
2553 printf_filtered ("\n\
2554 GDB is unable to find the start of the function at 0x%s\n\
2555 and thus can't determine the size of that function's stack frame.\n\
2556 This means that GDB may be unable to access that stack frame, or\n\
2557 the frames below it.\n\
2558 This problem is most likely caused by an invalid program counter or\n\
2560 However, if you think GDB should simply search farther back\n\
2561 from 0x%s for code which looks like the beginning of a\n\
2562 function, you can increase the range of the search using the `set\n\
2563 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2570 else if (pc_is_mips16 (start_pc
))
2572 unsigned short inst
;
2574 /* On MIPS16, any one of the following is likely to be the
2575 start of a function:
2579 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2580 inst
= mips_fetch_instruction (start_pc
);
2581 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2582 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2583 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2584 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2586 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2587 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2592 else if (mips_about_to_return (start_pc
))
2594 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2601 /* Fetch the immediate value from a MIPS16 instruction.
2602 If the previous instruction was an EXTEND, use it to extend
2603 the upper bits of the immediate value. This is a helper function
2604 for mips16_heuristic_proc_desc. */
2607 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2608 unsigned short inst
, /* current instruction */
2609 int nbits
, /* number of bits in imm field */
2610 int scale
, /* scale factor to be applied to imm */
2611 int is_signed
) /* is the imm field signed? */
2615 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2617 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2618 if (offset
& 0x8000) /* check for negative extend */
2619 offset
= 0 - (0x10000 - (offset
& 0xffff));
2620 return offset
| (inst
& 0x1f);
2624 int max_imm
= 1 << nbits
;
2625 int mask
= max_imm
- 1;
2626 int sign_bit
= max_imm
>> 1;
2628 offset
= inst
& mask
;
2629 if (is_signed
&& (offset
& sign_bit
))
2630 offset
= 0 - (max_imm
- offset
);
2631 return offset
* scale
;
2636 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2637 stream from start_pc to limit_pc. */
2640 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2641 struct frame_info
*next_frame
, CORE_ADDR sp
)
2644 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2645 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2646 unsigned inst
= 0; /* current instruction */
2647 unsigned entry_inst
= 0; /* the entry instruction */
2649 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2651 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2652 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2654 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2656 /* Save the previous instruction. If it's an EXTEND, we'll extract
2657 the immediate offset extension from it in mips16_get_imm. */
2660 /* Fetch and decode the instruction. */
2661 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2662 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2663 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2665 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2666 if (offset
< 0) /* negative stack adjustment? */
2667 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2669 /* Exit loop if a positive stack adjustment is found, which
2670 usually means that the stack cleanup code in the function
2671 epilogue is reached. */
2674 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2676 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2677 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2678 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2679 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2681 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2683 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2684 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2685 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2686 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2688 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2690 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2691 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2692 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2694 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2696 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2697 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2698 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2700 else if (inst
== 0x673d) /* move $s1, $sp */
2703 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2705 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2707 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2708 frame_addr
= sp
+ offset
;
2709 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2710 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2712 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2714 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2715 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2716 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2717 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2719 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2721 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2722 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2723 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2724 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2726 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2727 entry_inst
= inst
; /* save for later processing */
2728 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2729 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2732 /* The entry instruction is typically the first instruction in a function,
2733 and it stores registers at offsets relative to the value of the old SP
2734 (before the prologue). But the value of the sp parameter to this
2735 function is the new SP (after the prologue has been executed). So we
2736 can't calculate those offsets until we've seen the entire prologue,
2737 and can calculate what the old SP must have been. */
2738 if (entry_inst
!= 0)
2740 int areg_count
= (entry_inst
>> 8) & 7;
2741 int sreg_count
= (entry_inst
>> 6) & 3;
2743 /* The entry instruction always subtracts 32 from the SP. */
2744 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2746 /* Now we can calculate what the SP must have been at the
2747 start of the function prologue. */
2748 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2750 /* Check if a0-a3 were saved in the caller's argument save area. */
2751 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2753 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2754 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2755 offset
+= mips_abi_regsize (current_gdbarch
);
2758 /* Check if the ra register was pushed on the stack. */
2760 if (entry_inst
& 0x20)
2762 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2763 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2764 offset
-= mips_abi_regsize (current_gdbarch
);
2767 /* Check if the s0 and s1 registers were pushed on the stack. */
2768 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2770 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2771 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2772 offset
-= mips_abi_regsize (current_gdbarch
);
2778 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2779 struct frame_info
*next_frame
, CORE_ADDR sp
)
2782 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2784 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2785 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2786 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2787 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2788 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2790 unsigned long inst
, high_word
, low_word
;
2793 /* Fetch the instruction. */
2794 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2796 /* Save some code by pre-extracting some useful fields. */
2797 high_word
= (inst
>> 16) & 0xffff;
2798 low_word
= inst
& 0xffff;
2799 reg
= high_word
& 0x1f;
2801 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2802 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2803 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2805 if (low_word
& 0x8000) /* negative stack adjustment? */
2806 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2808 /* Exit loop if a positive stack adjustment is found, which
2809 usually means that the stack cleanup code in the function
2810 epilogue is reached. */
2813 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2815 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2816 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2818 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2820 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and
2822 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2823 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2825 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2827 /* Old gcc frame, r30 is virtual frame pointer. */
2828 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2829 frame_addr
= sp
+ low_word
;
2830 else if (PROC_FRAME_REG (&temp_proc_desc
) == MIPS_SP_REGNUM
)
2832 unsigned alloca_adjust
;
2833 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2834 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2835 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2836 if (alloca_adjust
> 0)
2838 /* FP > SP + frame_size. This may be because
2839 * of an alloca or somethings similar.
2840 * Fix sp to "pre-alloca" value, and try again.
2842 sp
+= alloca_adjust
;
2847 /* move $30,$sp. With different versions of gas this will be either
2848 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2849 Accept any one of these. */
2850 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2852 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2853 if (PROC_FRAME_REG (&temp_proc_desc
) == MIPS_SP_REGNUM
)
2855 unsigned alloca_adjust
;
2856 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2857 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2858 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2859 if (alloca_adjust
> 0)
2861 /* FP > SP + frame_size. This may be because
2862 * of an alloca or somethings similar.
2863 * Fix sp to "pre-alloca" value, and try again.
2865 sp
+= alloca_adjust
;
2870 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2872 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2873 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2878 static mips_extra_func_info_t
2879 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2880 struct frame_info
*next_frame
, int cur_frame
)
2885 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2891 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2892 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2893 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2894 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2895 PROC_FRAME_REG (&temp_proc_desc
) = MIPS_SP_REGNUM
;
2896 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2898 if (start_pc
+ 200 < limit_pc
)
2899 limit_pc
= start_pc
+ 200;
2900 if (pc_is_mips16 (start_pc
))
2901 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2903 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2904 return &temp_proc_desc
;
2907 struct mips_objfile_private
2913 /* Global used to communicate between non_heuristic_proc_desc and
2914 compare_pdr_entries within qsort (). */
2915 static bfd
*the_bfd
;
2918 compare_pdr_entries (const void *a
, const void *b
)
2920 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2921 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2925 else if (lhs
== rhs
)
2931 static mips_extra_func_info_t
2932 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2934 CORE_ADDR startaddr
;
2935 mips_extra_func_info_t proc_desc
;
2936 struct block
*b
= block_for_pc (pc
);
2938 struct obj_section
*sec
;
2939 struct mips_objfile_private
*priv
;
2941 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2943 *addrptr
= startaddr
;
2947 sec
= find_pc_section (pc
);
2950 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2952 /* Search the ".pdr" section generated by GAS. This includes most of
2953 the information normally found in ECOFF PDRs. */
2955 the_bfd
= sec
->objfile
->obfd
;
2957 && (the_bfd
->format
== bfd_object
2958 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2959 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2961 /* Right now GAS only outputs the address as a four-byte sequence.
2962 This means that we should not bother with this method on 64-bit
2963 targets (until that is fixed). */
2965 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2966 sizeof (struct mips_objfile_private
));
2968 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2970 else if (priv
== NULL
)
2974 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2975 sizeof (struct mips_objfile_private
));
2977 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2980 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2981 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2983 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2984 priv
->contents
, 0, priv
->size
);
2986 /* In general, the .pdr section is sorted. However, in the
2987 presence of multiple code sections (and other corner cases)
2988 it can become unsorted. Sort it so that we can use a faster
2990 qsort (priv
->contents
, priv
->size
/ 32, 32,
2991 compare_pdr_entries
);
2996 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
3000 if (priv
->size
!= 0)
3007 high
= priv
->size
/ 32;
3009 /* We've found a .pdr section describing this objfile. We want to
3010 find the entry which describes this code address. The .pdr
3011 information is not very descriptive; we have only a function
3012 start address. We have to look for the closest entry, because
3013 the local symbol at the beginning of this function may have
3014 been stripped - so if we ask the symbol table for the start
3015 address we may get a preceding global function. */
3017 /* First, find the last .pdr entry starting at or before PC. */
3020 mid
= (low
+ high
) / 2;
3022 ptr
= priv
->contents
+ mid
* 32;
3023 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
3024 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
3025 SECT_OFF_TEXT (sec
->objfile
));
3032 while (low
!= high
);
3034 /* Both low and high point one past the PDR of interest. If
3035 both are zero, that means this PC is before any region
3036 covered by a PDR, i.e. pdr_pc for the first PDR entry is
3040 ptr
= priv
->contents
+ (low
- 1) * 32;
3041 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
3042 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
3043 SECT_OFF_TEXT (sec
->objfile
));
3046 /* We don't have a range, so we have no way to know for sure
3047 whether we're in the correct PDR or a PDR for a preceding
3048 function and the current function was a stripped local
3049 symbol. But if the PDR's PC is at least as great as the
3050 best guess from the symbol table, assume that it does cover
3051 the right area; if a .pdr section is present at all then
3052 nearly every function will have an entry. The biggest exception
3053 will be the dynamic linker stubs; conveniently these are
3054 placed before .text instead of after. */
3056 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
3058 struct symbol
*sym
= find_pc_function (pc
);
3063 /* Fill in what we need of the proc_desc. */
3064 proc_desc
= (mips_extra_func_info_t
)
3065 obstack_alloc (&sec
->objfile
->objfile_obstack
,
3066 sizeof (struct mips_extra_func_info
));
3067 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
3069 /* Only used for dummy frames. */
3070 PROC_HIGH_ADDR (proc_desc
) = 0;
3072 PROC_FRAME_OFFSET (proc_desc
)
3073 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
3074 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3076 PROC_FRAME_ADJUST (proc_desc
) = 0;
3077 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3079 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3081 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3083 PROC_FREG_OFFSET (proc_desc
)
3084 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
3085 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3087 proc_desc
->pdr
.isym
= (long) sym
;
3097 if (startaddr
> BLOCK_START (b
))
3099 /* This is the "pathological" case referred to in a comment in
3100 print_frame_info. It might be better to move this check into
3105 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
3107 /* If we never found a PDR for this function in symbol reading, then
3108 examine prologues to find the information. */
3111 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
3112 if (PROC_FRAME_REG (proc_desc
) == -1)
3122 static mips_extra_func_info_t
3123 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
3125 mips_extra_func_info_t proc_desc
;
3126 CORE_ADDR startaddr
= 0;
3128 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
3132 /* IF this is the topmost frame AND
3133 * (this proc does not have debugging information OR
3134 * the PC is in the procedure prologue)
3135 * THEN create a "heuristic" proc_desc (by analyzing
3136 * the actual code) to replace the "official" proc_desc.
3138 if (next_frame
== NULL
)
3140 struct symtab_and_line val
;
3141 struct symbol
*proc_symbol
=
3142 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
3146 val
= find_pc_line (BLOCK_START
3147 (SYMBOL_BLOCK_VALUE (proc_symbol
)), 0);
3148 val
.pc
= val
.end
? val
.end
: pc
;
3150 if (!proc_symbol
|| pc
< val
.pc
)
3152 mips_extra_func_info_t found_heuristic
=
3153 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
3154 pc
, next_frame
, cur_frame
);
3155 if (found_heuristic
)
3156 proc_desc
= found_heuristic
;
3162 /* Is linked_proc_desc_table really necessary? It only seems to be used
3163 by procedure call dummys. However, the procedures being called ought
3164 to have their own proc_descs, and even if they don't,
3165 heuristic_proc_desc knows how to create them! */
3167 struct linked_proc_info
*link
;
3169 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
3170 if (PROC_LOW_ADDR (&link
->info
) <= pc
3171 && PROC_HIGH_ADDR (&link
->info
) > pc
)
3175 startaddr
= heuristic_proc_start (pc
);
3177 proc_desc
= heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
3182 /* MIPS stack frames are almost impenetrable. When execution stops,
3183 we basically have to look at symbol information for the function
3184 that we stopped in, which tells us *which* register (if any) is
3185 the base of the frame pointer, and what offset from that register
3186 the frame itself is at.
3188 This presents a problem when trying to examine a stack in memory
3189 (that isn't executing at the moment), using the "frame" command. We
3190 don't have a PC, nor do we have any registers except SP.
3192 This routine takes two arguments, SP and PC, and tries to make the
3193 cached frames look as if these two arguments defined a frame on the
3194 cache. This allows the rest of info frame to extract the important
3195 arguments without difficulty. */
3198 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
3201 error ("MIPS frame specifications require two arguments: sp and pc");
3203 return create_new_frame (argv
[0], argv
[1]);
3206 /* According to the current ABI, should the type be passed in a
3207 floating-point register (assuming that there is space)? When there
3208 is no FPU, FP are not even considered as possibile candidates for
3209 FP registers and, consequently this returns false - forces FP
3210 arguments into integer registers. */
3213 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
3215 return ((typecode
== TYPE_CODE_FLT
3217 && (typecode
== TYPE_CODE_STRUCT
3218 || typecode
== TYPE_CODE_UNION
)
3219 && TYPE_NFIELDS (arg_type
) == 1
3220 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
3221 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
3224 /* On o32, argument passing in GPRs depends on the alignment of the type being
3225 passed. Return 1 if this type must be aligned to a doubleword boundary. */
3228 mips_type_needs_double_align (struct type
*type
)
3230 enum type_code typecode
= TYPE_CODE (type
);
3232 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
3234 else if (typecode
== TYPE_CODE_STRUCT
)
3236 if (TYPE_NFIELDS (type
) < 1)
3238 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
3240 else if (typecode
== TYPE_CODE_UNION
)
3244 n
= TYPE_NFIELDS (type
);
3245 for (i
= 0; i
< n
; i
++)
3246 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
3253 /* Adjust the address downward (direction of stack growth) so that it
3254 is correctly aligned for a new stack frame. */
3256 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3258 return align_down (addr
, 16);
3261 /* Determine how a return value is stored within the MIPS register
3262 file, given the return type `valtype'. */
3264 struct return_value_word
3273 return_value_location (struct type
*valtype
,
3274 struct return_value_word
*hi
,
3275 struct return_value_word
*lo
)
3277 int len
= TYPE_LENGTH (valtype
);
3278 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3280 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3281 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3282 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3284 if (mips_abi_regsize (current_gdbarch
) < 8 && len
== 8)
3286 /* We need to break a 64bit float in two 32 bit halves and
3287 spread them across a floating-point register pair. */
3288 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3289 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3290 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3291 && register_size (current_gdbarch
,
3292 mips_regnum (current_gdbarch
)->
3293 fp0
) == 8) ? 4 : 0);
3294 hi
->reg_offset
= lo
->reg_offset
;
3295 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
3296 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
3302 /* The floating point value fits in a single floating-point
3304 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3305 && register_size (current_gdbarch
,
3306 mips_regnum (current_gdbarch
)->
3308 && len
== 4) ? 4 : 0);
3309 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
3320 /* Locate a result possibly spread across two registers. */
3322 lo
->reg
= regnum
+ 0;
3323 hi
->reg
= regnum
+ 1;
3324 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3325 && len
< mips_abi_regsize (current_gdbarch
))
3327 /* "un-left-justify" the value in the low register */
3328 lo
->reg_offset
= mips_abi_regsize (current_gdbarch
) - len
;
3333 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (current_gdbarch
) /* odd-size structs */
3334 && len
< mips_abi_regsize (current_gdbarch
) * 2
3335 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3336 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3338 /* "un-left-justify" the value spread across two registers. */
3339 lo
->reg_offset
= 2 * mips_abi_regsize (current_gdbarch
) - len
;
3340 lo
->len
= mips_abi_regsize (current_gdbarch
) - lo
->reg_offset
;
3342 hi
->len
= len
- lo
->len
;
3346 /* Only perform a partial copy of the second register. */
3349 if (len
> mips_abi_regsize (current_gdbarch
))
3351 lo
->len
= mips_abi_regsize (current_gdbarch
);
3352 hi
->len
= len
- mips_abi_regsize (current_gdbarch
);
3360 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3361 && register_size (current_gdbarch
, regnum
) == 8
3362 && mips_abi_regsize (current_gdbarch
) == 4)
3364 /* Account for the fact that only the least-signficant part
3365 of the register is being used */
3366 lo
->reg_offset
+= 4;
3367 hi
->reg_offset
+= 4;
3370 hi
->buf_offset
= lo
->len
;
3374 /* Should call_function allocate stack space for a struct return? */
3377 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
3379 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3380 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (current_gdbarch
));
3383 /* Should call_function pass struct by reference?
3384 For each architecture, structs are passed either by
3385 value or by reference, depending on their size. */
3388 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
3390 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
3391 int len
= TYPE_LENGTH (check_typedef (type
));
3392 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3394 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
3395 return (len
> mips_abi_regsize (current_gdbarch
));
3401 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3402 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3403 int nargs
, struct value
**args
, CORE_ADDR sp
,
3404 int struct_return
, CORE_ADDR struct_addr
)
3410 int stack_offset
= 0;
3411 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3412 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3414 /* For shared libraries, "t9" needs to point at the function
3416 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3418 /* Set the return address register to point to the entry point of
3419 the program, where a breakpoint lies in wait. */
3420 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3422 /* First ensure that the stack and structure return address (if any)
3423 are properly aligned. The stack has to be at least 64-bit
3424 aligned even on 32-bit machines, because doubles must be 64-bit
3425 aligned. For n32 and n64, stack frames need to be 128-bit
3426 aligned, so we round to this widest known alignment. */
3428 sp
= align_down (sp
, 16);
3429 struct_addr
= align_down (struct_addr
, 16);
3431 /* Now make space on the stack for the args. We allocate more
3432 than necessary for EABI, because the first few arguments are
3433 passed in registers, but that's OK. */
3434 for (argnum
= 0; argnum
< nargs
; argnum
++)
3435 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3436 mips_stack_argsize (gdbarch
));
3437 sp
-= align_up (len
, 16);
3440 fprintf_unfiltered (gdb_stdlog
,
3441 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
3442 paddr_nz (sp
), (long) align_up (len
, 16));
3444 /* Initialize the integer and float register pointers. */
3446 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3448 /* The struct_return pointer occupies the first parameter-passing reg. */
3452 fprintf_unfiltered (gdb_stdlog
,
3453 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
3454 argreg
, paddr_nz (struct_addr
));
3455 write_register (argreg
++, struct_addr
);
3458 /* Now load as many as possible of the first arguments into
3459 registers, and push the rest onto the stack. Loop thru args
3460 from first to last. */
3461 for (argnum
= 0; argnum
< nargs
; argnum
++)
3464 char valbuf
[MAX_REGISTER_SIZE
];
3465 struct value
*arg
= args
[argnum
];
3466 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3467 int len
= TYPE_LENGTH (arg_type
);
3468 enum type_code typecode
= TYPE_CODE (arg_type
);
3471 fprintf_unfiltered (gdb_stdlog
,
3472 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3473 argnum
+ 1, len
, (int) typecode
);
3475 /* The EABI passes structures that do not fit in a register by
3477 if (len
> mips_abi_regsize (gdbarch
)
3478 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3480 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
3481 VALUE_ADDRESS (arg
));
3482 typecode
= TYPE_CODE_PTR
;
3483 len
= mips_abi_regsize (gdbarch
);
3486 fprintf_unfiltered (gdb_stdlog
, " push");
3489 val
= (char *) VALUE_CONTENTS (arg
);
3491 /* 32-bit ABIs always start floating point arguments in an
3492 even-numbered floating point register. Round the FP register
3493 up before the check to see if there are any FP registers
3494 left. Non MIPS_EABI targets also pass the FP in the integer
3495 registers so also round up normal registers. */
3496 if (mips_abi_regsize (gdbarch
) < 8
3497 && fp_register_arg_p (typecode
, arg_type
))
3499 if ((float_argreg
& 1))
3503 /* Floating point arguments passed in registers have to be
3504 treated specially. On 32-bit architectures, doubles
3505 are passed in register pairs; the even register gets
3506 the low word, and the odd register gets the high word.
3507 On non-EABI processors, the first two floating point arguments are
3508 also copied to general registers, because MIPS16 functions
3509 don't use float registers for arguments. This duplication of
3510 arguments in general registers can't hurt non-MIPS16 functions
3511 because those registers are normally skipped. */
3512 /* MIPS_EABI squeezes a struct that contains a single floating
3513 point value into an FP register instead of pushing it onto the
3515 if (fp_register_arg_p (typecode
, arg_type
)
3516 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3518 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3520 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3521 unsigned long regval
;
3523 /* Write the low word of the double to the even register(s). */
3524 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3526 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3527 float_argreg
, phex (regval
, 4));
3528 write_register (float_argreg
++, regval
);
3530 /* Write the high word of the double to the odd register(s). */
3531 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3533 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3534 float_argreg
, phex (regval
, 4));
3535 write_register (float_argreg
++, regval
);
3539 /* This is a floating point value that fits entirely
3540 in a single register. */
3541 /* On 32 bit ABI's the float_argreg is further adjusted
3542 above to ensure that it is even register aligned. */
3543 LONGEST regval
= extract_unsigned_integer (val
, len
);
3545 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3546 float_argreg
, phex (regval
, len
));
3547 write_register (float_argreg
++, regval
);
3552 /* Copy the argument to general registers or the stack in
3553 register-sized pieces. Large arguments are split between
3554 registers and stack. */
3555 /* Note: structs whose size is not a multiple of
3556 mips_abi_regsize() are treated specially: Irix cc passes
3557 them in registers where gcc sometimes puts them on the
3558 stack. For maximum compatibility, we will put them in
3560 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3561 && (len
% mips_abi_regsize (gdbarch
) != 0));
3563 /* Note: Floating-point values that didn't fit into an FP
3564 register are only written to memory. */
3567 /* Remember if the argument was written to the stack. */
3568 int stack_used_p
= 0;
3569 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3570 ? len
: mips_abi_regsize (gdbarch
));
3573 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3576 /* Write this portion of the argument to the stack. */
3577 if (argreg
> MIPS_LAST_ARG_REGNUM
3579 || fp_register_arg_p (typecode
, arg_type
))
3581 /* Should shorter than int integer values be
3582 promoted to int before being stored? */
3583 int longword_offset
= 0;
3586 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3588 if (mips_stack_argsize (gdbarch
) == 8
3589 && (typecode
== TYPE_CODE_INT
3590 || typecode
== TYPE_CODE_PTR
3591 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3592 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3593 else if ((typecode
== TYPE_CODE_STRUCT
3594 || typecode
== TYPE_CODE_UNION
)
3595 && (TYPE_LENGTH (arg_type
)
3596 < mips_stack_argsize (gdbarch
)))
3597 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3602 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3603 paddr_nz (stack_offset
));
3604 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3605 paddr_nz (longword_offset
));
3608 addr
= sp
+ stack_offset
+ longword_offset
;
3613 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3615 for (i
= 0; i
< partial_len
; i
++)
3617 fprintf_unfiltered (gdb_stdlog
, "%02x",
3621 write_memory (addr
, val
, partial_len
);
3624 /* Note!!! This is NOT an else clause. Odd sized
3625 structs may go thru BOTH paths. Floating point
3626 arguments will not. */
3627 /* Write this portion of the argument to a general
3628 purpose register. */
3629 if (argreg
<= MIPS_LAST_ARG_REGNUM
3630 && !fp_register_arg_p (typecode
, arg_type
))
3633 extract_unsigned_integer (val
, partial_len
);
3636 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3639 mips_abi_regsize (gdbarch
)));
3640 write_register (argreg
, regval
);
3647 /* Compute the the offset into the stack at which we
3648 will copy the next parameter.
3650 In the new EABI (and the NABI32), the stack_offset
3651 only needs to be adjusted when it has been used. */
3654 stack_offset
+= align_up (partial_len
,
3655 mips_stack_argsize (gdbarch
));
3659 fprintf_unfiltered (gdb_stdlog
, "\n");
3662 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3664 /* Return adjusted stack pointer. */
3668 /* Given a return value in `regbuf' with a type `valtype', extract and
3669 copy its value into `valbuf'. */
3672 mips_eabi_extract_return_value (struct type
*valtype
,
3673 char regbuf
[], char *valbuf
)
3675 struct return_value_word lo
;
3676 struct return_value_word hi
;
3677 return_value_location (valtype
, &hi
, &lo
);
3679 memcpy (valbuf
+ lo
.buf_offset
,
3680 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3681 lo
.reg_offset
, lo
.len
);
3684 memcpy (valbuf
+ hi
.buf_offset
,
3685 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3686 hi
.reg_offset
, hi
.len
);
3689 /* Given a return value in `valbuf' with a type `valtype', write it's
3690 value into the appropriate register. */
3693 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3695 char raw_buffer
[MAX_REGISTER_SIZE
];
3696 struct return_value_word lo
;
3697 struct return_value_word hi
;
3698 return_value_location (valtype
, &hi
, &lo
);
3700 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3701 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3702 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3703 raw_buffer
, register_size (current_gdbarch
,
3708 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3709 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3710 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3712 register_size (current_gdbarch
,
3717 /* N32/N64 ABI stuff. */
3720 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3721 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3722 int nargs
, struct value
**args
, CORE_ADDR sp
,
3723 int struct_return
, CORE_ADDR struct_addr
)
3729 int stack_offset
= 0;
3730 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3731 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3733 /* For shared libraries, "t9" needs to point at the function
3735 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3737 /* Set the return address register to point to the entry point of
3738 the program, where a breakpoint lies in wait. */
3739 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3741 /* First ensure that the stack and structure return address (if any)
3742 are properly aligned. The stack has to be at least 64-bit
3743 aligned even on 32-bit machines, because doubles must be 64-bit
3744 aligned. For n32 and n64, stack frames need to be 128-bit
3745 aligned, so we round to this widest known alignment. */
3747 sp
= align_down (sp
, 16);
3748 struct_addr
= align_down (struct_addr
, 16);
3750 /* Now make space on the stack for the args. */
3751 for (argnum
= 0; argnum
< nargs
; argnum
++)
3752 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3753 mips_stack_argsize (gdbarch
));
3754 sp
-= align_up (len
, 16);
3757 fprintf_unfiltered (gdb_stdlog
,
3758 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3759 paddr_nz (sp
), (long) align_up (len
, 16));
3761 /* Initialize the integer and float register pointers. */
3763 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3765 /* The struct_return pointer occupies the first parameter-passing reg. */
3769 fprintf_unfiltered (gdb_stdlog
,
3770 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3771 argreg
, paddr_nz (struct_addr
));
3772 write_register (argreg
++, struct_addr
);
3775 /* Now load as many as possible of the first arguments into
3776 registers, and push the rest onto the stack. Loop thru args
3777 from first to last. */
3778 for (argnum
= 0; argnum
< nargs
; argnum
++)
3781 struct value
*arg
= args
[argnum
];
3782 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3783 int len
= TYPE_LENGTH (arg_type
);
3784 enum type_code typecode
= TYPE_CODE (arg_type
);
3787 fprintf_unfiltered (gdb_stdlog
,
3788 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3789 argnum
+ 1, len
, (int) typecode
);
3791 val
= (char *) VALUE_CONTENTS (arg
);
3793 if (fp_register_arg_p (typecode
, arg_type
)
3794 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3796 /* This is a floating point value that fits entirely
3797 in a single register. */
3798 /* On 32 bit ABI's the float_argreg is further adjusted
3799 above to ensure that it is even register aligned. */
3800 LONGEST regval
= extract_unsigned_integer (val
, len
);
3802 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3803 float_argreg
, phex (regval
, len
));
3804 write_register (float_argreg
++, regval
);
3807 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3808 argreg
, phex (regval
, len
));
3809 write_register (argreg
, regval
);
3814 /* Copy the argument to general registers or the stack in
3815 register-sized pieces. Large arguments are split between
3816 registers and stack. */
3817 /* Note: structs whose size is not a multiple of
3818 mips_abi_regsize() are treated specially: Irix cc passes
3819 them in registers where gcc sometimes puts them on the
3820 stack. For maximum compatibility, we will put them in
3822 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3823 && (len
% mips_abi_regsize (gdbarch
) != 0));
3824 /* Note: Floating-point values that didn't fit into an FP
3825 register are only written to memory. */
3828 /* Rememer if the argument was written to the stack. */
3829 int stack_used_p
= 0;
3830 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3831 ? len
: mips_abi_regsize (gdbarch
));
3834 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3837 /* Write this portion of the argument to the stack. */
3838 if (argreg
> MIPS_LAST_ARG_REGNUM
3840 || fp_register_arg_p (typecode
, arg_type
))
3842 /* Should shorter than int integer values be
3843 promoted to int before being stored? */
3844 int longword_offset
= 0;
3847 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3849 if (mips_stack_argsize (gdbarch
) == 8
3850 && (typecode
== TYPE_CODE_INT
3851 || typecode
== TYPE_CODE_PTR
3852 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3853 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3858 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3859 paddr_nz (stack_offset
));
3860 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3861 paddr_nz (longword_offset
));
3864 addr
= sp
+ stack_offset
+ longword_offset
;
3869 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3871 for (i
= 0; i
< partial_len
; i
++)
3873 fprintf_unfiltered (gdb_stdlog
, "%02x",
3877 write_memory (addr
, val
, partial_len
);
3880 /* Note!!! This is NOT an else clause. Odd sized
3881 structs may go thru BOTH paths. Floating point
3882 arguments will not. */
3883 /* Write this portion of the argument to a general
3884 purpose register. */
3885 if (argreg
<= MIPS_LAST_ARG_REGNUM
3886 && !fp_register_arg_p (typecode
, arg_type
))
3889 extract_unsigned_integer (val
, partial_len
);
3891 /* A non-floating-point argument being passed in a
3892 general register. If a struct or union, and if
3893 the remaining length is smaller than the register
3894 size, we have to adjust the register value on
3897 It does not seem to be necessary to do the
3898 same for integral types.
3900 cagney/2001-07-23: gdb/179: Also, GCC, when
3901 outputting LE O32 with sizeof (struct) <
3902 mips_abi_regsize(), generates a left shift as
3903 part of storing the argument in a register a
3904 register (the left shift isn't generated when
3905 sizeof (struct) >= mips_abi_regsize()). Since
3906 it is quite possible that this is GCC
3907 contradicting the LE/O32 ABI, GDB has not been
3908 adjusted to accommodate this. Either someone
3909 needs to demonstrate that the LE/O32 ABI
3910 specifies such a left shift OR this new ABI gets
3911 identified as such and GDB gets tweaked
3914 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3915 && partial_len
< mips_abi_regsize (gdbarch
)
3916 && (typecode
== TYPE_CODE_STRUCT
||
3917 typecode
== TYPE_CODE_UNION
))
3918 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3922 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3925 mips_abi_regsize (gdbarch
)));
3926 write_register (argreg
, regval
);
3933 /* Compute the the offset into the stack at which we
3934 will copy the next parameter.
3936 In N32 (N64?), the stack_offset only needs to be
3937 adjusted when it has been used. */
3940 stack_offset
+= align_up (partial_len
,
3941 mips_stack_argsize (gdbarch
));
3945 fprintf_unfiltered (gdb_stdlog
, "\n");
3948 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3950 /* Return adjusted stack pointer. */
3954 static enum return_value_convention
3955 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3956 struct type
*type
, struct regcache
*regcache
,
3957 void *readbuf
, const void *writebuf
)
3959 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3960 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3961 || TYPE_CODE (type
) == TYPE_CODE_UNION
3962 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3963 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3964 return RETURN_VALUE_STRUCT_CONVENTION
;
3965 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3966 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3968 /* A floating-point value belongs in the least significant part
3971 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3972 mips_xfer_register (regcache
,
3973 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3975 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3976 return RETURN_VALUE_REGISTER_CONVENTION
;
3978 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3979 && TYPE_NFIELDS (type
) <= 2
3980 && TYPE_NFIELDS (type
) >= 1
3981 && ((TYPE_NFIELDS (type
) == 1
3982 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3984 || (TYPE_NFIELDS (type
) == 2
3985 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3987 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3989 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3991 /* A struct that contains one or two floats. Each value is part
3992 in the least significant part of their floating point
3996 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3997 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3999 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4002 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4004 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4005 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4006 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4008 return RETURN_VALUE_REGISTER_CONVENTION
;
4010 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4011 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4013 /* A structure or union. Extract the left justified value,
4014 regardless of the byte order. I.e. DO NOT USE
4018 for (offset
= 0, regnum
= V0_REGNUM
;
4019 offset
< TYPE_LENGTH (type
);
4020 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4022 int xfer
= register_size (current_gdbarch
, regnum
);
4023 if (offset
+ xfer
> TYPE_LENGTH (type
))
4024 xfer
= TYPE_LENGTH (type
) - offset
;
4026 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4027 offset
, xfer
, regnum
);
4028 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4029 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4031 return RETURN_VALUE_REGISTER_CONVENTION
;
4035 /* A scalar extract each part but least-significant-byte
4039 for (offset
= 0, regnum
= V0_REGNUM
;
4040 offset
< TYPE_LENGTH (type
);
4041 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4043 int xfer
= register_size (current_gdbarch
, regnum
);
4044 if (offset
+ xfer
> TYPE_LENGTH (type
))
4045 xfer
= TYPE_LENGTH (type
) - offset
;
4047 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4048 offset
, xfer
, regnum
);
4049 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4050 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4052 return RETURN_VALUE_REGISTER_CONVENTION
;
4056 /* O32 ABI stuff. */
4059 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4060 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4061 int nargs
, struct value
**args
, CORE_ADDR sp
,
4062 int struct_return
, CORE_ADDR struct_addr
)
4068 int stack_offset
= 0;
4069 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4070 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4072 /* For shared libraries, "t9" needs to point at the function
4074 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4076 /* Set the return address register to point to the entry point of
4077 the program, where a breakpoint lies in wait. */
4078 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4080 /* First ensure that the stack and structure return address (if any)
4081 are properly aligned. The stack has to be at least 64-bit
4082 aligned even on 32-bit machines, because doubles must be 64-bit
4083 aligned. For n32 and n64, stack frames need to be 128-bit
4084 aligned, so we round to this widest known alignment. */
4086 sp
= align_down (sp
, 16);
4087 struct_addr
= align_down (struct_addr
, 16);
4089 /* Now make space on the stack for the args. */
4090 for (argnum
= 0; argnum
< nargs
; argnum
++)
4091 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4092 mips_stack_argsize (gdbarch
));
4093 sp
-= align_up (len
, 16);
4096 fprintf_unfiltered (gdb_stdlog
,
4097 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
4098 paddr_nz (sp
), (long) align_up (len
, 16));
4100 /* Initialize the integer and float register pointers. */
4102 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4104 /* The struct_return pointer occupies the first parameter-passing reg. */
4108 fprintf_unfiltered (gdb_stdlog
,
4109 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
4110 argreg
, paddr_nz (struct_addr
));
4111 write_register (argreg
++, struct_addr
);
4112 stack_offset
+= mips_stack_argsize (gdbarch
);
4115 /* Now load as many as possible of the first arguments into
4116 registers, and push the rest onto the stack. Loop thru args
4117 from first to last. */
4118 for (argnum
= 0; argnum
< nargs
; argnum
++)
4121 struct value
*arg
= args
[argnum
];
4122 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4123 int len
= TYPE_LENGTH (arg_type
);
4124 enum type_code typecode
= TYPE_CODE (arg_type
);
4127 fprintf_unfiltered (gdb_stdlog
,
4128 "mips_o32_push_dummy_call: %d len=%d type=%d",
4129 argnum
+ 1, len
, (int) typecode
);
4131 val
= (char *) VALUE_CONTENTS (arg
);
4133 /* 32-bit ABIs always start floating point arguments in an
4134 even-numbered floating point register. Round the FP register
4135 up before the check to see if there are any FP registers
4136 left. O32/O64 targets also pass the FP in the integer
4137 registers so also round up normal registers. */
4138 if (mips_abi_regsize (gdbarch
) < 8
4139 && fp_register_arg_p (typecode
, arg_type
))
4141 if ((float_argreg
& 1))
4145 /* Floating point arguments passed in registers have to be
4146 treated specially. On 32-bit architectures, doubles
4147 are passed in register pairs; the even register gets
4148 the low word, and the odd register gets the high word.
4149 On O32/O64, the first two floating point arguments are
4150 also copied to general registers, because MIPS16 functions
4151 don't use float registers for arguments. This duplication of
4152 arguments in general registers can't hurt non-MIPS16 functions
4153 because those registers are normally skipped. */
4155 if (fp_register_arg_p (typecode
, arg_type
)
4156 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4158 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4160 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4161 unsigned long regval
;
4163 /* Write the low word of the double to the even register(s). */
4164 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4166 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4167 float_argreg
, phex (regval
, 4));
4168 write_register (float_argreg
++, regval
);
4170 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4171 argreg
, phex (regval
, 4));
4172 write_register (argreg
++, regval
);
4174 /* Write the high word of the double to the odd register(s). */
4175 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4177 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4178 float_argreg
, phex (regval
, 4));
4179 write_register (float_argreg
++, regval
);
4182 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4183 argreg
, phex (regval
, 4));
4184 write_register (argreg
++, regval
);
4188 /* This is a floating point value that fits entirely
4189 in a single register. */
4190 /* On 32 bit ABI's the float_argreg is further adjusted
4191 above to ensure that it is even register aligned. */
4192 LONGEST regval
= extract_unsigned_integer (val
, len
);
4194 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4195 float_argreg
, phex (regval
, len
));
4196 write_register (float_argreg
++, regval
);
4197 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4198 registers for each argument. The below is (my
4199 guess) to ensure that the corresponding integer
4200 register has reserved the same space. */
4202 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4203 argreg
, phex (regval
, len
));
4204 write_register (argreg
, regval
);
4205 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4207 /* Reserve space for the FP register. */
4208 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4212 /* Copy the argument to general registers or the stack in
4213 register-sized pieces. Large arguments are split between
4214 registers and stack. */
4215 /* Note: structs whose size is not a multiple of
4216 mips_abi_regsize() are treated specially: Irix cc passes
4217 them in registers where gcc sometimes puts them on the
4218 stack. For maximum compatibility, we will put them in
4220 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4221 && (len
% mips_abi_regsize (gdbarch
) != 0));
4222 /* Structures should be aligned to eight bytes (even arg registers)
4223 on MIPS_ABI_O32, if their first member has double precision. */
4224 if (mips_abi_regsize (gdbarch
) < 8
4225 && mips_type_needs_double_align (arg_type
))
4230 /* Note: Floating-point values that didn't fit into an FP
4231 register are only written to memory. */
4234 /* Remember if the argument was written to the stack. */
4235 int stack_used_p
= 0;
4236 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4237 ? len
: mips_abi_regsize (gdbarch
));
4240 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4243 /* Write this portion of the argument to the stack. */
4244 if (argreg
> MIPS_LAST_ARG_REGNUM
4246 || fp_register_arg_p (typecode
, arg_type
))
4248 /* Should shorter than int integer values be
4249 promoted to int before being stored? */
4250 int longword_offset
= 0;
4253 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4255 if (mips_stack_argsize (gdbarch
) == 8
4256 && (typecode
== TYPE_CODE_INT
4257 || typecode
== TYPE_CODE_PTR
4258 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4259 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4264 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4265 paddr_nz (stack_offset
));
4266 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4267 paddr_nz (longword_offset
));
4270 addr
= sp
+ stack_offset
+ longword_offset
;
4275 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4277 for (i
= 0; i
< partial_len
; i
++)
4279 fprintf_unfiltered (gdb_stdlog
, "%02x",
4283 write_memory (addr
, val
, partial_len
);
4286 /* Note!!! This is NOT an else clause. Odd sized
4287 structs may go thru BOTH paths. Floating point
4288 arguments will not. */
4289 /* Write this portion of the argument to a general
4290 purpose register. */
4291 if (argreg
<= MIPS_LAST_ARG_REGNUM
4292 && !fp_register_arg_p (typecode
, arg_type
))
4294 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4295 /* Value may need to be sign extended, because
4296 mips_isa_regsize() != mips_abi_regsize(). */
4298 /* A non-floating-point argument being passed in a
4299 general register. If a struct or union, and if
4300 the remaining length is smaller than the register
4301 size, we have to adjust the register value on
4304 It does not seem to be necessary to do the
4305 same for integral types.
4307 Also don't do this adjustment on O64 binaries.
4309 cagney/2001-07-23: gdb/179: Also, GCC, when
4310 outputting LE O32 with sizeof (struct) <
4311 mips_abi_regsize(), generates a left shift as
4312 part of storing the argument in a register a
4313 register (the left shift isn't generated when
4314 sizeof (struct) >= mips_abi_regsize()). Since
4315 it is quite possible that this is GCC
4316 contradicting the LE/O32 ABI, GDB has not been
4317 adjusted to accommodate this. Either someone
4318 needs to demonstrate that the LE/O32 ABI
4319 specifies such a left shift OR this new ABI gets
4320 identified as such and GDB gets tweaked
4323 if (mips_abi_regsize (gdbarch
) < 8
4324 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4325 && partial_len
< mips_abi_regsize (gdbarch
)
4326 && (typecode
== TYPE_CODE_STRUCT
||
4327 typecode
== TYPE_CODE_UNION
))
4328 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4332 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4335 mips_abi_regsize (gdbarch
)));
4336 write_register (argreg
, regval
);
4339 /* Prevent subsequent floating point arguments from
4340 being passed in floating point registers. */
4341 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4347 /* Compute the the offset into the stack at which we
4348 will copy the next parameter.
4350 In older ABIs, the caller reserved space for
4351 registers that contained arguments. This was loosely
4352 refered to as their "home". Consequently, space is
4353 always allocated. */
4355 stack_offset
+= align_up (partial_len
,
4356 mips_stack_argsize (gdbarch
));
4360 fprintf_unfiltered (gdb_stdlog
, "\n");
4363 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4365 /* Return adjusted stack pointer. */
4369 static enum return_value_convention
4370 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4371 struct regcache
*regcache
,
4372 void *readbuf
, const void *writebuf
)
4374 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4376 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4377 || TYPE_CODE (type
) == TYPE_CODE_UNION
4378 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4379 return RETURN_VALUE_STRUCT_CONVENTION
;
4380 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4381 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4383 /* A single-precision floating-point value. It fits in the
4384 least significant part of FP0. */
4386 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4387 mips_xfer_register (regcache
,
4388 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4390 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4391 return RETURN_VALUE_REGISTER_CONVENTION
;
4393 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4394 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4396 /* A double-precision floating-point value. The most
4397 significant part goes in FP1, and the least significant in
4400 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4401 switch (TARGET_BYTE_ORDER
)
4403 case BFD_ENDIAN_LITTLE
:
4404 mips_xfer_register (regcache
,
4405 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4406 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4407 mips_xfer_register (regcache
,
4408 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4409 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4411 case BFD_ENDIAN_BIG
:
4412 mips_xfer_register (regcache
,
4413 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4414 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4415 mips_xfer_register (regcache
,
4416 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4417 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4420 internal_error (__FILE__
, __LINE__
, "bad switch");
4422 return RETURN_VALUE_REGISTER_CONVENTION
;
4425 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4426 && TYPE_NFIELDS (type
) <= 2
4427 && TYPE_NFIELDS (type
) >= 1
4428 && ((TYPE_NFIELDS (type
) == 1
4429 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4431 || (TYPE_NFIELDS (type
) == 2
4432 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4434 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4436 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4438 /* A struct that contains one or two floats. Each value is part
4439 in the least significant part of their floating point
4441 bfd_byte reg
[MAX_REGISTER_SIZE
];
4444 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4445 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4447 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4450 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4452 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4453 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4454 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4456 return RETURN_VALUE_REGISTER_CONVENTION
;
4460 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4461 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4463 /* A structure or union. Extract the left justified value,
4464 regardless of the byte order. I.e. DO NOT USE
4468 for (offset
= 0, regnum
= V0_REGNUM
;
4469 offset
< TYPE_LENGTH (type
);
4470 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4472 int xfer
= register_size (current_gdbarch
, regnum
);
4473 if (offset
+ xfer
> TYPE_LENGTH (type
))
4474 xfer
= TYPE_LENGTH (type
) - offset
;
4476 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4477 offset
, xfer
, regnum
);
4478 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4479 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4481 return RETURN_VALUE_REGISTER_CONVENTION
;
4486 /* A scalar extract each part but least-significant-byte
4487 justified. o32 thinks registers are 4 byte, regardless of
4488 the ISA. mips_stack_argsize controls this. */
4491 for (offset
= 0, regnum
= V0_REGNUM
;
4492 offset
< TYPE_LENGTH (type
);
4493 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
4495 int xfer
= mips_stack_argsize (gdbarch
);
4496 if (offset
+ xfer
> TYPE_LENGTH (type
))
4497 xfer
= TYPE_LENGTH (type
) - offset
;
4499 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4500 offset
, xfer
, regnum
);
4501 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4502 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4504 return RETURN_VALUE_REGISTER_CONVENTION
;
4508 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4512 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4513 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4515 struct value
**args
, CORE_ADDR sp
,
4516 int struct_return
, CORE_ADDR struct_addr
)
4522 int stack_offset
= 0;
4523 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4524 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4526 /* For shared libraries, "t9" needs to point at the function
4528 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4530 /* Set the return address register to point to the entry point of
4531 the program, where a breakpoint lies in wait. */
4532 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4534 /* First ensure that the stack and structure return address (if any)
4535 are properly aligned. The stack has to be at least 64-bit
4536 aligned even on 32-bit machines, because doubles must be 64-bit
4537 aligned. For n32 and n64, stack frames need to be 128-bit
4538 aligned, so we round to this widest known alignment. */
4540 sp
= align_down (sp
, 16);
4541 struct_addr
= align_down (struct_addr
, 16);
4543 /* Now make space on the stack for the args. */
4544 for (argnum
= 0; argnum
< nargs
; argnum
++)
4545 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4546 mips_stack_argsize (gdbarch
));
4547 sp
-= align_up (len
, 16);
4550 fprintf_unfiltered (gdb_stdlog
,
4551 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4552 paddr_nz (sp
), (long) align_up (len
, 16));
4554 /* Initialize the integer and float register pointers. */
4556 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4558 /* The struct_return pointer occupies the first parameter-passing reg. */
4562 fprintf_unfiltered (gdb_stdlog
,
4563 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4564 argreg
, paddr_nz (struct_addr
));
4565 write_register (argreg
++, struct_addr
);
4566 stack_offset
+= mips_stack_argsize (gdbarch
);
4569 /* Now load as many as possible of the first arguments into
4570 registers, and push the rest onto the stack. Loop thru args
4571 from first to last. */
4572 for (argnum
= 0; argnum
< nargs
; argnum
++)
4575 struct value
*arg
= args
[argnum
];
4576 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4577 int len
= TYPE_LENGTH (arg_type
);
4578 enum type_code typecode
= TYPE_CODE (arg_type
);
4581 fprintf_unfiltered (gdb_stdlog
,
4582 "mips_o64_push_dummy_call: %d len=%d type=%d",
4583 argnum
+ 1, len
, (int) typecode
);
4585 val
= (char *) VALUE_CONTENTS (arg
);
4587 /* 32-bit ABIs always start floating point arguments in an
4588 even-numbered floating point register. Round the FP register
4589 up before the check to see if there are any FP registers
4590 left. O32/O64 targets also pass the FP in the integer
4591 registers so also round up normal registers. */
4592 if (mips_abi_regsize (gdbarch
) < 8
4593 && fp_register_arg_p (typecode
, arg_type
))
4595 if ((float_argreg
& 1))
4599 /* Floating point arguments passed in registers have to be
4600 treated specially. On 32-bit architectures, doubles
4601 are passed in register pairs; the even register gets
4602 the low word, and the odd register gets the high word.
4603 On O32/O64, the first two floating point arguments are
4604 also copied to general registers, because MIPS16 functions
4605 don't use float registers for arguments. This duplication of
4606 arguments in general registers can't hurt non-MIPS16 functions
4607 because those registers are normally skipped. */
4609 if (fp_register_arg_p (typecode
, arg_type
)
4610 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4612 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4614 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4615 unsigned long regval
;
4617 /* Write the low word of the double to the even register(s). */
4618 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4620 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4621 float_argreg
, phex (regval
, 4));
4622 write_register (float_argreg
++, regval
);
4624 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4625 argreg
, phex (regval
, 4));
4626 write_register (argreg
++, regval
);
4628 /* Write the high word of the double to the odd register(s). */
4629 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4631 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4632 float_argreg
, phex (regval
, 4));
4633 write_register (float_argreg
++, regval
);
4636 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4637 argreg
, phex (regval
, 4));
4638 write_register (argreg
++, regval
);
4642 /* This is a floating point value that fits entirely
4643 in a single register. */
4644 /* On 32 bit ABI's the float_argreg is further adjusted
4645 above to ensure that it is even register aligned. */
4646 LONGEST regval
= extract_unsigned_integer (val
, len
);
4648 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4649 float_argreg
, phex (regval
, len
));
4650 write_register (float_argreg
++, regval
);
4651 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4652 registers for each argument. The below is (my
4653 guess) to ensure that the corresponding integer
4654 register has reserved the same space. */
4656 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4657 argreg
, phex (regval
, len
));
4658 write_register (argreg
, regval
);
4659 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4661 /* Reserve space for the FP register. */
4662 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4666 /* Copy the argument to general registers or the stack in
4667 register-sized pieces. Large arguments are split between
4668 registers and stack. */
4669 /* Note: structs whose size is not a multiple of
4670 mips_abi_regsize() are treated specially: Irix cc passes
4671 them in registers where gcc sometimes puts them on the
4672 stack. For maximum compatibility, we will put them in
4674 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4675 && (len
% mips_abi_regsize (gdbarch
) != 0));
4676 /* Structures should be aligned to eight bytes (even arg registers)
4677 on MIPS_ABI_O32, if their first member has double precision. */
4678 if (mips_abi_regsize (gdbarch
) < 8
4679 && mips_type_needs_double_align (arg_type
))
4684 /* Note: Floating-point values that didn't fit into an FP
4685 register are only written to memory. */
4688 /* Remember if the argument was written to the stack. */
4689 int stack_used_p
= 0;
4690 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4691 ? len
: mips_abi_regsize (gdbarch
));
4694 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4697 /* Write this portion of the argument to the stack. */
4698 if (argreg
> MIPS_LAST_ARG_REGNUM
4700 || fp_register_arg_p (typecode
, arg_type
))
4702 /* Should shorter than int integer values be
4703 promoted to int before being stored? */
4704 int longword_offset
= 0;
4707 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4709 if (mips_stack_argsize (gdbarch
) == 8
4710 && (typecode
== TYPE_CODE_INT
4711 || typecode
== TYPE_CODE_PTR
4712 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4713 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4718 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4719 paddr_nz (stack_offset
));
4720 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4721 paddr_nz (longword_offset
));
4724 addr
= sp
+ stack_offset
+ longword_offset
;
4729 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4731 for (i
= 0; i
< partial_len
; i
++)
4733 fprintf_unfiltered (gdb_stdlog
, "%02x",
4737 write_memory (addr
, val
, partial_len
);
4740 /* Note!!! This is NOT an else clause. Odd sized
4741 structs may go thru BOTH paths. Floating point
4742 arguments will not. */
4743 /* Write this portion of the argument to a general
4744 purpose register. */
4745 if (argreg
<= MIPS_LAST_ARG_REGNUM
4746 && !fp_register_arg_p (typecode
, arg_type
))
4748 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4749 /* Value may need to be sign extended, because
4750 mips_isa_regsize() != mips_abi_regsize(). */
4752 /* A non-floating-point argument being passed in a
4753 general register. If a struct or union, and if
4754 the remaining length is smaller than the register
4755 size, we have to adjust the register value on
4758 It does not seem to be necessary to do the
4759 same for integral types.
4761 Also don't do this adjustment on O64 binaries.
4763 cagney/2001-07-23: gdb/179: Also, GCC, when
4764 outputting LE O32 with sizeof (struct) <
4765 mips_abi_regsize(), generates a left shift as
4766 part of storing the argument in a register a
4767 register (the left shift isn't generated when
4768 sizeof (struct) >= mips_abi_regsize()). Since
4769 it is quite possible that this is GCC
4770 contradicting the LE/O32 ABI, GDB has not been
4771 adjusted to accommodate this. Either someone
4772 needs to demonstrate that the LE/O32 ABI
4773 specifies such a left shift OR this new ABI gets
4774 identified as such and GDB gets tweaked
4777 if (mips_abi_regsize (gdbarch
) < 8
4778 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4779 && partial_len
< mips_abi_regsize (gdbarch
)
4780 && (typecode
== TYPE_CODE_STRUCT
||
4781 typecode
== TYPE_CODE_UNION
))
4782 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4786 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4789 mips_abi_regsize (gdbarch
)));
4790 write_register (argreg
, regval
);
4793 /* Prevent subsequent floating point arguments from
4794 being passed in floating point registers. */
4795 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4801 /* Compute the the offset into the stack at which we
4802 will copy the next parameter.
4804 In older ABIs, the caller reserved space for
4805 registers that contained arguments. This was loosely
4806 refered to as their "home". Consequently, space is
4807 always allocated. */
4809 stack_offset
+= align_up (partial_len
,
4810 mips_stack_argsize (gdbarch
));
4814 fprintf_unfiltered (gdb_stdlog
, "\n");
4817 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4819 /* Return adjusted stack pointer. */
4824 mips_o64_extract_return_value (struct type
*valtype
,
4825 char regbuf
[], char *valbuf
)
4827 struct return_value_word lo
;
4828 struct return_value_word hi
;
4829 return_value_location (valtype
, &hi
, &lo
);
4831 memcpy (valbuf
+ lo
.buf_offset
,
4832 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4833 lo
.reg_offset
, lo
.len
);
4836 memcpy (valbuf
+ hi
.buf_offset
,
4837 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4838 hi
.reg_offset
, hi
.len
);
4842 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4844 char raw_buffer
[MAX_REGISTER_SIZE
];
4845 struct return_value_word lo
;
4846 struct return_value_word hi
;
4847 return_value_location (valtype
, &hi
, &lo
);
4849 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4850 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4851 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4852 raw_buffer
, register_size (current_gdbarch
,
4857 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4858 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4859 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4861 register_size (current_gdbarch
,
4866 /* Floating point register management.
4868 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4869 64bit operations, these early MIPS cpus treat fp register pairs
4870 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4871 registers and offer a compatibility mode that emulates the MIPS2 fp
4872 model. When operating in MIPS2 fp compat mode, later cpu's split
4873 double precision floats into two 32-bit chunks and store them in
4874 consecutive fp regs. To display 64-bit floats stored in this
4875 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4876 Throw in user-configurable endianness and you have a real mess.
4878 The way this works is:
4879 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4880 double-precision value will be split across two logical registers.
4881 The lower-numbered logical register will hold the low-order bits,
4882 regardless of the processor's endianness.
4883 - If we are on a 64-bit processor, and we are looking for a
4884 single-precision value, it will be in the low ordered bits
4885 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4886 save slot in memory.
4887 - If we are in 64-bit mode, everything is straightforward.
4889 Note that this code only deals with "live" registers at the top of the
4890 stack. We will attempt to deal with saved registers later, when
4891 the raw/cooked register interface is in place. (We need a general
4892 interface that can deal with dynamic saved register sizes -- fp
4893 regs could be 32 bits wide in one frame and 64 on the frame above
4896 static struct type
*
4897 mips_float_register_type (void)
4899 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4900 return builtin_type_ieee_single_big
;
4902 return builtin_type_ieee_single_little
;
4905 static struct type
*
4906 mips_double_register_type (void)
4908 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4909 return builtin_type_ieee_double_big
;
4911 return builtin_type_ieee_double_little
;
4914 /* Copy a 32-bit single-precision value from the current frame
4915 into rare_buffer. */
4918 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4921 int raw_size
= register_size (current_gdbarch
, regno
);
4922 char *raw_buffer
= alloca (raw_size
);
4924 if (!frame_register_read (frame
, regno
, raw_buffer
))
4925 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4928 /* We have a 64-bit value for this register. Find the low-order
4932 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4937 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4941 memcpy (rare_buffer
, raw_buffer
, 4);
4945 /* Copy a 64-bit double-precision value from the current frame into
4946 rare_buffer. This may include getting half of it from the next
4950 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4953 int raw_size
= register_size (current_gdbarch
, regno
);
4955 if (raw_size
== 8 && !mips2_fp_compat ())
4957 /* We have a 64-bit value for this register, and we should use
4959 if (!frame_register_read (frame
, regno
, rare_buffer
))
4960 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4964 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4965 internal_error (__FILE__
, __LINE__
,
4966 "mips_read_fp_register_double: bad access to "
4967 "odd-numbered FP register");
4969 /* mips_read_fp_register_single will find the correct 32 bits from
4971 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4973 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4974 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4978 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4979 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4985 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4987 { /* do values for FP (float) regs */
4989 double doub
, flt1
; /* doubles extracted from raw hex data */
4993 (char *) alloca (2 *
4994 register_size (current_gdbarch
,
4995 mips_regnum (current_gdbarch
)->fp0
));
4997 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4998 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
5001 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
5003 /* 4-byte registers: Print hex and floating. Also print even
5004 numbered registers as doubles. */
5005 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
5006 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
5008 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
5011 fprintf_filtered (file
, " flt: ");
5013 fprintf_filtered (file
, " <invalid float> ");
5015 fprintf_filtered (file
, "%-17.9g", flt1
);
5017 if (regnum
% 2 == 0)
5019 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
5020 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
5023 fprintf_filtered (file
, " dbl: ");
5025 fprintf_filtered (file
, "<invalid double>");
5027 fprintf_filtered (file
, "%-24.17g", doub
);
5032 /* Eight byte registers: print each one as hex, float and double. */
5033 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
5034 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
5036 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
5037 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
5040 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
5043 fprintf_filtered (file
, " flt: ");
5045 fprintf_filtered (file
, "<invalid float>");
5047 fprintf_filtered (file
, "%-17.9g", flt1
);
5049 fprintf_filtered (file
, " dbl: ");
5051 fprintf_filtered (file
, "<invalid double>");
5053 fprintf_filtered (file
, "%-24.17g", doub
);
5058 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
5059 int regnum
, int all
)
5061 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5062 char raw_buffer
[MAX_REGISTER_SIZE
];
5065 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
5067 mips_print_fp_register (file
, frame
, regnum
);
5071 /* Get the data in raw format. */
5072 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5074 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
5078 fputs_filtered (REGISTER_NAME (regnum
), file
);
5080 /* The problem with printing numeric register names (r26, etc.) is that
5081 the user can't use them on input. Probably the best solution is to
5082 fix it so that either the numeric or the funky (a2, etc.) names
5083 are accepted on input. */
5084 if (regnum
< MIPS_NUMREGS
)
5085 fprintf_filtered (file
, "(r%d): ", regnum
);
5087 fprintf_filtered (file
, ": ");
5089 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5091 register_size (current_gdbarch
,
5092 regnum
) - register_size (current_gdbarch
, regnum
);
5096 print_scalar_formatted (raw_buffer
+ offset
,
5097 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
5101 /* Replacement for generic do_registers_info.
5102 Print regs in pretty columns. */
5105 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5108 fprintf_filtered (file
, " ");
5109 mips_print_fp_register (file
, frame
, regnum
);
5110 fprintf_filtered (file
, "\n");
5115 /* Print a row's worth of GP (int) registers, with name labels above */
5118 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5121 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5122 /* do values for GP (int) regs */
5123 char raw_buffer
[MAX_REGISTER_SIZE
];
5124 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
5128 /* For GP registers, we print a separate row of names above the vals */
5129 fprintf_filtered (file
, " ");
5130 for (col
= 0, regnum
= start_regnum
;
5131 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
5133 if (*REGISTER_NAME (regnum
) == '\0')
5134 continue; /* unused register */
5135 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5137 break; /* end the row: reached FP register */
5138 fprintf_filtered (file
,
5139 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
5140 REGISTER_NAME (regnum
));
5143 /* print the R0 to R31 names */
5144 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
5145 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
5147 fprintf_filtered (file
, "\n ");
5149 /* now print the values in hex, 4 or 8 to the row */
5150 for (col
= 0, regnum
= start_regnum
;
5151 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
5153 if (*REGISTER_NAME (regnum
) == '\0')
5154 continue; /* unused register */
5155 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5157 break; /* end row: reached FP register */
5158 /* OK: get the data in raw format. */
5159 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5160 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
5161 /* pad small registers */
5163 byte
< (mips_abi_regsize (current_gdbarch
)
5164 - register_size (current_gdbarch
, regnum
)); byte
++)
5165 printf_filtered (" ");
5166 /* Now print the register value in hex, endian order. */
5167 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5169 register_size (current_gdbarch
,
5170 regnum
) - register_size (current_gdbarch
, regnum
);
5171 byte
< register_size (current_gdbarch
, regnum
); byte
++)
5172 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5174 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
5176 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5177 fprintf_filtered (file
, " ");
5180 if (col
> 0) /* ie. if we actually printed anything... */
5181 fprintf_filtered (file
, "\n");
5186 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
5189 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
5190 struct frame_info
*frame
, int regnum
, int all
)
5192 if (regnum
!= -1) /* do one specified register */
5194 gdb_assert (regnum
>= NUM_REGS
);
5195 if (*(REGISTER_NAME (regnum
)) == '\0')
5196 error ("Not a valid register for the current processor type");
5198 mips_print_register (file
, frame
, regnum
, 0);
5199 fprintf_filtered (file
, "\n");
5202 /* do all (or most) registers */
5205 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
5207 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5210 if (all
) /* true for "INFO ALL-REGISTERS" command */
5211 regnum
= print_fp_register_row (file
, frame
, regnum
);
5213 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
5216 regnum
= print_gp_register_row (file
, frame
, regnum
);
5221 /* Is this a branch with a delay slot? */
5223 static int is_delayed (unsigned long);
5226 is_delayed (unsigned long insn
)
5229 for (i
= 0; i
< NUMOPCODES
; ++i
)
5230 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
5231 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
5233 return (i
< NUMOPCODES
5234 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
5235 | INSN_COND_BRANCH_DELAY
5236 | INSN_COND_BRANCH_LIKELY
)));
5240 mips_step_skips_delay (CORE_ADDR pc
)
5242 char buf
[MIPS_INSTLEN
];
5244 /* There is no branch delay slot on MIPS16. */
5245 if (pc_is_mips16 (pc
))
5248 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
5249 /* If error reading memory, guess that it is not a delayed branch. */
5251 return is_delayed ((unsigned long)
5252 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
5255 /* Skip the PC past function prologue instructions (32-bit version).
5256 This is a helper function for mips_skip_prologue. */
5259 mips32_skip_prologue (CORE_ADDR pc
)
5263 int seen_sp_adjust
= 0;
5264 int load_immediate_bytes
= 0;
5266 /* Find an upper bound on the prologue. */
5267 end_pc
= skip_prologue_using_sal (pc
);
5269 end_pc
= pc
+ 100; /* Magic. */
5271 /* Skip the typical prologue instructions. These are the stack adjustment
5272 instruction and the instructions that save registers on the stack
5273 or in the gcc frame. */
5274 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
5276 unsigned long high_word
;
5278 inst
= mips_fetch_instruction (pc
);
5279 high_word
= (inst
>> 16) & 0xffff;
5281 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
5282 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
5284 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
5285 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
5287 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
5288 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
5289 && (inst
& 0x001F0000)) /* reg != $zero */
5292 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
5294 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
5296 continue; /* reg != $zero */
5298 /* move $s8,$sp. With different versions of gas this will be either
5299 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
5300 Accept any one of these. */
5301 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
5304 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
5306 else if (high_word
== 0x3c1c) /* lui $gp,n */
5308 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
5310 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
5311 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
5313 /* The following instructions load $at or $t0 with an immediate
5314 value in preparation for a stack adjustment via
5315 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
5316 a local variable, so we accept them only before a stack adjustment
5317 instruction was seen. */
5318 else if (!seen_sp_adjust
)
5320 if (high_word
== 0x3c01 || /* lui $at,n */
5321 high_word
== 0x3c08) /* lui $t0,n */
5323 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5326 else if (high_word
== 0x3421 || /* ori $at,$at,n */
5327 high_word
== 0x3508 || /* ori $t0,$t0,n */
5328 high_word
== 0x3401 || /* ori $at,$zero,n */
5329 high_word
== 0x3408) /* ori $t0,$zero,n */
5331 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5341 /* In a frameless function, we might have incorrectly
5342 skipped some load immediate instructions. Undo the skipping
5343 if the load immediate was not followed by a stack adjustment. */
5344 if (load_immediate_bytes
&& !seen_sp_adjust
)
5345 pc
-= load_immediate_bytes
;
5349 /* Skip the PC past function prologue instructions (16-bit version).
5350 This is a helper function for mips_skip_prologue. */
5353 mips16_skip_prologue (CORE_ADDR pc
)
5356 int extend_bytes
= 0;
5357 int prev_extend_bytes
;
5359 /* Table of instructions likely to be found in a function prologue. */
5362 unsigned short inst
;
5363 unsigned short mask
;
5369 , /* addiu $sp,offset */
5372 , /* daddiu $sp,offset */
5375 , /* sw reg,n($sp) */
5378 , /* sd reg,n($sp) */
5381 , /* sw $ra,n($sp) */
5384 , /* sd $ra,n($sp) */
5390 , /* sw $a0-$a3,n($s1) */
5393 , /* move reg,$a0-$a3 */
5396 , /* entry pseudo-op */
5399 , /* addiu $s1,$sp,n */
5401 0, 0} /* end of table marker */
5404 /* Find an upper bound on the prologue. */
5405 end_pc
= skip_prologue_using_sal (pc
);
5407 end_pc
= pc
+ 100; /* Magic. */
5409 /* Skip the typical prologue instructions. These are the stack adjustment
5410 instruction and the instructions that save registers on the stack
5411 or in the gcc frame. */
5412 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
5414 unsigned short inst
;
5417 inst
= mips_fetch_instruction (pc
);
5419 /* Normally we ignore an extend instruction. However, if it is
5420 not followed by a valid prologue instruction, we must adjust
5421 the pc back over the extend so that it won't be considered
5422 part of the prologue. */
5423 if ((inst
& 0xf800) == 0xf000) /* extend */
5425 extend_bytes
= MIPS16_INSTLEN
;
5428 prev_extend_bytes
= extend_bytes
;
5431 /* Check for other valid prologue instructions besides extend. */
5432 for (i
= 0; table
[i
].mask
!= 0; i
++)
5433 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
5435 if (table
[i
].mask
!= 0) /* it was in table? */
5436 continue; /* ignore it */
5440 /* Return the current pc, adjusted backwards by 2 if
5441 the previous instruction was an extend. */
5442 return pc
- prev_extend_bytes
;
5448 /* To skip prologues, I use this predicate. Returns either PC itself
5449 if the code at PC does not look like a function prologue; otherwise
5450 returns an address that (if we're lucky) follows the prologue. If
5451 LENIENT, then we must skip everything which is involved in setting
5452 up the frame (it's OK to skip more, just so long as we don't skip
5453 anything which might clobber the registers which are being saved.
5454 We must skip more in the case where part of the prologue is in the
5455 delay slot of a non-prologue instruction). */
5458 mips_skip_prologue (CORE_ADDR pc
)
5460 /* See if we can determine the end of the prologue via the symbol table.
5461 If so, then return either PC, or the PC after the prologue, whichever
5464 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
5466 if (post_prologue_pc
!= 0)
5467 return max (pc
, post_prologue_pc
);
5469 /* Can't determine prologue from the symbol table, need to examine
5472 if (pc_is_mips16 (pc
))
5473 return mips16_skip_prologue (pc
);
5475 return mips32_skip_prologue (pc
);
5478 /* Root of all "set mips "/"show mips " commands. This will eventually be
5479 used for all MIPS-specific commands. */
5482 show_mips_command (char *args
, int from_tty
)
5484 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5488 set_mips_command (char *args
, int from_tty
)
5491 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5492 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5495 /* Commands to show/set the MIPS FPU type. */
5498 show_mipsfpu_command (char *args
, int from_tty
)
5501 switch (MIPS_FPU_TYPE
)
5503 case MIPS_FPU_SINGLE
:
5504 fpu
= "single-precision";
5506 case MIPS_FPU_DOUBLE
:
5507 fpu
= "double-precision";
5510 fpu
= "absent (none)";
5513 internal_error (__FILE__
, __LINE__
, "bad switch");
5515 if (mips_fpu_type_auto
)
5517 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5521 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5526 set_mipsfpu_command (char *args
, int from_tty
)
5529 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5530 show_mipsfpu_command (args
, from_tty
);
5534 set_mipsfpu_single_command (char *args
, int from_tty
)
5536 struct gdbarch_info info
;
5537 gdbarch_info_init (&info
);
5538 mips_fpu_type
= MIPS_FPU_SINGLE
;
5539 mips_fpu_type_auto
= 0;
5540 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5541 instead of relying on globals. Doing that would let generic code
5542 handle the search for this specific architecture. */
5543 if (!gdbarch_update_p (info
))
5544 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5548 set_mipsfpu_double_command (char *args
, int from_tty
)
5550 struct gdbarch_info info
;
5551 gdbarch_info_init (&info
);
5552 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5553 mips_fpu_type_auto
= 0;
5554 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5555 instead of relying on globals. Doing that would let generic code
5556 handle the search for this specific architecture. */
5557 if (!gdbarch_update_p (info
))
5558 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5562 set_mipsfpu_none_command (char *args
, int from_tty
)
5564 struct gdbarch_info info
;
5565 gdbarch_info_init (&info
);
5566 mips_fpu_type
= MIPS_FPU_NONE
;
5567 mips_fpu_type_auto
= 0;
5568 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5569 instead of relying on globals. Doing that would let generic code
5570 handle the search for this specific architecture. */
5571 if (!gdbarch_update_p (info
))
5572 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5576 set_mipsfpu_auto_command (char *args
, int from_tty
)
5578 mips_fpu_type_auto
= 1;
5581 /* Attempt to identify the particular processor model by reading the
5582 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5583 the relevant processor still exists (it dates back to '94) and
5584 secondly this is not the way to do this. The processor type should
5585 be set by forcing an architecture change. */
5588 deprecated_mips_set_processor_regs_hack (void)
5590 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5593 prid
= read_register (PRID_REGNUM
);
5595 if ((prid
& ~0xf) == 0x700)
5596 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5599 /* Just like reinit_frame_cache, but with the right arguments to be
5600 callable as an sfunc. */
5603 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5604 struct cmd_list_element
*c
)
5606 reinit_frame_cache ();
5610 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5612 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5613 mips_extra_func_info_t proc_desc
;
5615 /* Search for the function containing this address. Set the low bit
5616 of the address when searching, in case we were given an even address
5617 that is the start of a 16-bit function. If we didn't do this,
5618 the search would fail because the symbol table says the function
5619 starts at an odd address, i.e. 1 byte past the given address. */
5620 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5621 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5623 /* Make an attempt to determine if this is a 16-bit function. If
5624 the procedure descriptor exists and the address therein is odd,
5625 it's definitely a 16-bit function. Otherwise, we have to just
5626 guess that if the address passed in is odd, it's 16-bits. */
5627 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5628 disassembler needs to be able to locally determine the ISA, and
5629 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5633 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5634 info
->mach
= bfd_mach_mips16
;
5638 if (pc_is_mips16 (memaddr
))
5639 info
->mach
= bfd_mach_mips16
;
5642 /* Round down the instruction address to the appropriate boundary. */
5643 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5645 /* Set the disassembler options. */
5646 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5648 /* Set up the disassembler info, so that we get the right
5649 register names from libopcodes. */
5650 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5651 info
->disassembler_options
= "gpr-names=n32";
5653 info
->disassembler_options
= "gpr-names=64";
5654 info
->flavour
= bfd_target_elf_flavour
;
5657 /* This string is not recognized explicitly by the disassembler,
5658 but it tells the disassembler to not try to guess the ABI from
5659 the bfd elf headers, such that, if the user overrides the ABI
5660 of a program linked as NewABI, the disassembly will follow the
5661 register naming conventions specified by the user. */
5662 info
->disassembler_options
= "gpr-names=32";
5664 /* Call the appropriate disassembler based on the target endian-ness. */
5665 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5666 return print_insn_big_mips (memaddr
, info
);
5668 return print_insn_little_mips (memaddr
, info
);
5671 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5672 counter value to determine whether a 16- or 32-bit breakpoint should be
5673 used. It returns a pointer to a string of bytes that encode a breakpoint
5674 instruction, stores the length of the string to *lenptr, and adjusts pc
5675 (if necessary) to point to the actual memory location where the
5676 breakpoint should be inserted. */
5678 static const unsigned char *
5679 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5681 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5683 if (pc_is_mips16 (*pcptr
))
5685 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5686 *pcptr
= unmake_mips16_addr (*pcptr
);
5687 *lenptr
= sizeof (mips16_big_breakpoint
);
5688 return mips16_big_breakpoint
;
5692 /* The IDT board uses an unusual breakpoint value, and
5693 sometimes gets confused when it sees the usual MIPS
5694 breakpoint instruction. */
5695 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5696 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5697 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5699 *lenptr
= sizeof (big_breakpoint
);
5701 if (strcmp (target_shortname
, "mips") == 0)
5702 return idt_big_breakpoint
;
5703 else if (strcmp (target_shortname
, "ddb") == 0
5704 || strcmp (target_shortname
, "pmon") == 0
5705 || strcmp (target_shortname
, "lsi") == 0)
5706 return pmon_big_breakpoint
;
5708 return big_breakpoint
;
5713 if (pc_is_mips16 (*pcptr
))
5715 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5716 *pcptr
= unmake_mips16_addr (*pcptr
);
5717 *lenptr
= sizeof (mips16_little_breakpoint
);
5718 return mips16_little_breakpoint
;
5722 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5723 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5724 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5726 *lenptr
= sizeof (little_breakpoint
);
5728 if (strcmp (target_shortname
, "mips") == 0)
5729 return idt_little_breakpoint
;
5730 else if (strcmp (target_shortname
, "ddb") == 0
5731 || strcmp (target_shortname
, "pmon") == 0
5732 || strcmp (target_shortname
, "lsi") == 0)
5733 return pmon_little_breakpoint
;
5735 return little_breakpoint
;
5740 /* If PC is in a mips16 call or return stub, return the address of the target
5741 PC, which is either the callee or the caller. There are several
5742 cases which must be handled:
5744 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5745 target PC is in $31 ($ra).
5746 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5747 and the target PC is in $2.
5748 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5749 before the jal instruction, this is effectively a call stub
5750 and the the target PC is in $2. Otherwise this is effectively
5751 a return stub and the target PC is in $18.
5753 See the source code for the stubs in gcc/config/mips/mips16.S for
5756 This function implements the SKIP_TRAMPOLINE_CODE macro.
5760 mips_skip_stub (CORE_ADDR pc
)
5763 CORE_ADDR start_addr
;
5765 /* Find the starting address and name of the function containing the PC. */
5766 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5769 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5770 target PC is in $31 ($ra). */
5771 if (strcmp (name
, "__mips16_ret_sf") == 0
5772 || strcmp (name
, "__mips16_ret_df") == 0)
5773 return read_signed_register (RA_REGNUM
);
5775 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5777 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5778 and the target PC is in $2. */
5779 if (name
[19] >= '0' && name
[19] <= '9')
5780 return read_signed_register (2);
5782 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5783 before the jal instruction, this is effectively a call stub
5784 and the the target PC is in $2. Otherwise this is effectively
5785 a return stub and the target PC is in $18. */
5786 else if (name
[19] == 's' || name
[19] == 'd')
5788 if (pc
== start_addr
)
5790 /* Check if the target of the stub is a compiler-generated
5791 stub. Such a stub for a function bar might have a name
5792 like __fn_stub_bar, and might look like this:
5797 la $1,bar (becomes a lui/addiu pair)
5799 So scan down to the lui/addi and extract the target
5800 address from those two instructions. */
5802 CORE_ADDR target_pc
= read_signed_register (2);
5806 /* See if the name of the target function is __fn_stub_*. */
5807 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5810 if (strncmp (name
, "__fn_stub_", 10) != 0
5811 && strcmp (name
, "etext") != 0
5812 && strcmp (name
, "_etext") != 0)
5815 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5816 The limit on the search is arbitrarily set to 20
5817 instructions. FIXME. */
5818 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5820 inst
= mips_fetch_instruction (target_pc
);
5821 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5822 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5823 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5824 return pc
| (inst
& 0xffff); /* low word */
5827 /* Couldn't find the lui/addui pair, so return stub address. */
5831 /* This is the 'return' part of a call stub. The return
5832 address is in $r18. */
5833 return read_signed_register (18);
5836 return 0; /* not a stub */
5840 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5841 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5844 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5846 CORE_ADDR start_addr
;
5848 /* Find the starting address of the function containing the PC. If the
5849 caller didn't give us a name, look it up at the same time. */
5850 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5854 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5856 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5857 if (name
[19] >= '0' && name
[19] <= '9')
5859 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5860 before the jal instruction, this is effectively a call stub. */
5861 else if (name
[19] == 's' || name
[19] == 'd')
5862 return pc
== start_addr
;
5865 return 0; /* not a stub */
5869 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5870 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5873 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5875 CORE_ADDR start_addr
;
5877 /* Find the starting address of the function containing the PC. */
5878 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5881 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5882 if (strcmp (name
, "__mips16_ret_sf") == 0
5883 || strcmp (name
, "__mips16_ret_df") == 0)
5886 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5887 i.e. after the jal instruction, this is effectively a return stub. */
5888 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5889 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5892 return 0; /* not a stub */
5896 /* Return non-zero if the PC is in a library helper function that
5897 should be ignored. This implements the
5898 DEPRECATED_IGNORE_HELPER_CALL macro. */
5901 mips_ignore_helper (CORE_ADDR pc
)
5905 /* Find the starting address and name of the function containing the PC. */
5906 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5909 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5910 that we want to ignore. */
5911 return (strcmp (name
, "__mips16_ret_sf") == 0
5912 || strcmp (name
, "__mips16_ret_df") == 0);
5916 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5917 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5920 mips_stab_reg_to_regnum (int num
)
5923 if (num
>= 0 && num
< 32)
5925 else if (num
>= 38 && num
< 70)
5926 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5928 regnum
= mips_regnum (current_gdbarch
)->hi
;
5930 regnum
= mips_regnum (current_gdbarch
)->lo
;
5932 /* This will hopefully (eventually) provoke a warning. Should
5933 we be calling complaint() here? */
5934 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5935 return NUM_REGS
+ regnum
;
5939 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5940 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5943 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5946 if (num
>= 0 && num
< 32)
5948 else if (num
>= 32 && num
< 64)
5949 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5951 regnum
= mips_regnum (current_gdbarch
)->hi
;
5953 regnum
= mips_regnum (current_gdbarch
)->lo
;
5955 /* This will hopefully (eventually) provoke a warning. Should we
5956 be calling complaint() here? */
5957 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5958 return NUM_REGS
+ regnum
;
5962 mips_register_sim_regno (int regnum
)
5964 /* Only makes sense to supply raw registers. */
5965 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5966 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5967 decide if it is valid. Should instead define a standard sim/gdb
5968 register numbering scheme. */
5969 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5970 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5973 return LEGACY_SIM_REGNO_IGNORE
;
5977 /* Convert an integer into an address. By first converting the value
5978 into a pointer and then extracting it signed, the address is
5979 guarenteed to be correctly sign extended. */
5982 mips_integer_to_address (struct type
*type
, void *buf
)
5984 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5985 LONGEST val
= unpack_long (type
, buf
);
5986 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5987 return extract_signed_integer (tmp
,
5988 TYPE_LENGTH (builtin_type_void_data_ptr
));
5992 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5994 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5995 const char *name
= bfd_get_section_name (abfd
, sect
);
5997 if (*abip
!= MIPS_ABI_UNKNOWN
)
6000 if (strncmp (name
, ".mdebug.", 8) != 0)
6003 if (strcmp (name
, ".mdebug.abi32") == 0)
6004 *abip
= MIPS_ABI_O32
;
6005 else if (strcmp (name
, ".mdebug.abiN32") == 0)
6006 *abip
= MIPS_ABI_N32
;
6007 else if (strcmp (name
, ".mdebug.abi64") == 0)
6008 *abip
= MIPS_ABI_N64
;
6009 else if (strcmp (name
, ".mdebug.abiO64") == 0)
6010 *abip
= MIPS_ABI_O64
;
6011 else if (strcmp (name
, ".mdebug.eabi32") == 0)
6012 *abip
= MIPS_ABI_EABI32
;
6013 else if (strcmp (name
, ".mdebug.eabi64") == 0)
6014 *abip
= MIPS_ABI_EABI64
;
6016 warning ("unsupported ABI %s.", name
+ 8);
6019 static enum mips_abi
6020 global_mips_abi (void)
6024 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
6025 if (mips_abi_strings
[i
] == mips_abi_string
)
6026 return (enum mips_abi
) i
;
6028 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
6031 static struct gdbarch
*
6032 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6034 struct gdbarch
*gdbarch
;
6035 struct gdbarch_tdep
*tdep
;
6037 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
6039 enum mips_fpu_type fpu_type
;
6041 /* First of all, extract the elf_flags, if available. */
6042 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6043 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6044 else if (arches
!= NULL
)
6045 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
6049 fprintf_unfiltered (gdb_stdlog
,
6050 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
6052 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
6053 switch ((elf_flags
& EF_MIPS_ABI
))
6055 case E_MIPS_ABI_O32
:
6056 found_abi
= MIPS_ABI_O32
;
6058 case E_MIPS_ABI_O64
:
6059 found_abi
= MIPS_ABI_O64
;
6061 case E_MIPS_ABI_EABI32
:
6062 found_abi
= MIPS_ABI_EABI32
;
6064 case E_MIPS_ABI_EABI64
:
6065 found_abi
= MIPS_ABI_EABI64
;
6068 if ((elf_flags
& EF_MIPS_ABI2
))
6069 found_abi
= MIPS_ABI_N32
;
6071 found_abi
= MIPS_ABI_UNKNOWN
;
6075 /* GCC creates a pseudo-section whose name describes the ABI. */
6076 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
6077 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6079 /* If we have no useful BFD information, use the ABI from the last
6080 MIPS architecture (if there is one). */
6081 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6082 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6084 /* Try the architecture for any hint of the correct ABI. */
6085 if (found_abi
== MIPS_ABI_UNKNOWN
6086 && info
.bfd_arch_info
!= NULL
6087 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6089 switch (info
.bfd_arch_info
->mach
)
6091 case bfd_mach_mips3900
:
6092 found_abi
= MIPS_ABI_EABI32
;
6094 case bfd_mach_mips4100
:
6095 case bfd_mach_mips5000
:
6096 found_abi
= MIPS_ABI_EABI64
;
6098 case bfd_mach_mips8000
:
6099 case bfd_mach_mips10000
:
6100 /* On Irix, ELF64 executables use the N64 ABI. The
6101 pseudo-sections which describe the ABI aren't present
6102 on IRIX. (Even for executables created by gcc.) */
6103 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6104 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6105 found_abi
= MIPS_ABI_N64
;
6107 found_abi
= MIPS_ABI_N32
;
6113 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6116 /* What has the user specified from the command line? */
6117 wanted_abi
= global_mips_abi ();
6119 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6122 /* Now that we have found what the ABI for this binary would be,
6123 check whether the user is overriding it. */
6124 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6125 mips_abi
= wanted_abi
;
6126 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6127 mips_abi
= found_abi
;
6129 mips_abi
= MIPS_ABI_O32
;
6131 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6134 /* Also used when doing an architecture lookup. */
6136 fprintf_unfiltered (gdb_stdlog
,
6137 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
6138 mips64_transfers_32bit_regs_p
);
6140 /* Determine the MIPS FPU type. */
6141 if (!mips_fpu_type_auto
)
6142 fpu_type
= mips_fpu_type
;
6143 else if (info
.bfd_arch_info
!= NULL
6144 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6145 switch (info
.bfd_arch_info
->mach
)
6147 case bfd_mach_mips3900
:
6148 case bfd_mach_mips4100
:
6149 case bfd_mach_mips4111
:
6150 case bfd_mach_mips4120
:
6151 fpu_type
= MIPS_FPU_NONE
;
6153 case bfd_mach_mips4650
:
6154 fpu_type
= MIPS_FPU_SINGLE
;
6157 fpu_type
= MIPS_FPU_DOUBLE
;
6160 else if (arches
!= NULL
)
6161 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6163 fpu_type
= MIPS_FPU_DOUBLE
;
6165 fprintf_unfiltered (gdb_stdlog
,
6166 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6168 /* try to find a pre-existing architecture */
6169 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6171 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6173 /* MIPS needs to be pedantic about which ABI the object is
6175 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6177 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6179 /* Need to be pedantic about which register virtual size is
6181 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6182 != mips64_transfers_32bit_regs_p
)
6184 /* Be pedantic about which FPU is selected. */
6185 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6187 return arches
->gdbarch
;
6190 /* Need a new architecture. Fill in a target specific vector. */
6191 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6192 gdbarch
= gdbarch_alloc (&info
, tdep
);
6193 tdep
->elf_flags
= elf_flags
;
6194 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6195 tdep
->found_abi
= found_abi
;
6196 tdep
->mips_abi
= mips_abi
;
6197 tdep
->mips_fpu_type
= fpu_type
;
6199 /* Initially set everything according to the default ABI/ISA. */
6200 set_gdbarch_short_bit (gdbarch
, 16);
6201 set_gdbarch_int_bit (gdbarch
, 32);
6202 set_gdbarch_float_bit (gdbarch
, 32);
6203 set_gdbarch_double_bit (gdbarch
, 64);
6204 set_gdbarch_long_double_bit (gdbarch
, 64);
6205 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6206 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6207 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6209 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6210 mips_elf_make_msymbol_special
);
6212 /* Fill in the OS dependant register numbers and names. */
6214 const char **reg_names
;
6215 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
6216 struct mips_regnum
);
6217 if (info
.osabi
== GDB_OSABI_IRIX
)
6222 regnum
->badvaddr
= 66;
6225 regnum
->fp_control_status
= 69;
6226 regnum
->fp_implementation_revision
= 70;
6228 reg_names
= mips_irix_reg_names
;
6232 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6233 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6234 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6235 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6236 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6237 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6238 regnum
->fp_control_status
= 70;
6239 regnum
->fp_implementation_revision
= 71;
6241 if (info
.bfd_arch_info
!= NULL
6242 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6243 reg_names
= mips_tx39_reg_names
;
6245 reg_names
= mips_generic_reg_names
;
6247 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
6248 replaced by read_pc? */
6249 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6250 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6251 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6252 set_gdbarch_num_regs (gdbarch
, num_regs
);
6253 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6254 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6255 tdep
->mips_processor_reg_names
= reg_names
;
6256 tdep
->regnum
= regnum
;
6262 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6263 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6264 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6265 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6266 tdep
->default_mask_address_p
= 0;
6267 set_gdbarch_long_bit (gdbarch
, 32);
6268 set_gdbarch_ptr_bit (gdbarch
, 32);
6269 set_gdbarch_long_long_bit (gdbarch
, 64);
6272 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6273 set_gdbarch_deprecated_store_return_value (gdbarch
,
6274 mips_o64_store_return_value
);
6275 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6276 mips_o64_extract_return_value
);
6277 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6278 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6279 tdep
->default_mask_address_p
= 0;
6280 set_gdbarch_long_bit (gdbarch
, 32);
6281 set_gdbarch_ptr_bit (gdbarch
, 32);
6282 set_gdbarch_long_long_bit (gdbarch
, 64);
6283 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
6285 case MIPS_ABI_EABI32
:
6286 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6287 set_gdbarch_deprecated_store_return_value (gdbarch
,
6288 mips_eabi_store_return_value
);
6289 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6290 mips_eabi_extract_return_value
);
6291 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6292 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6293 tdep
->default_mask_address_p
= 0;
6294 set_gdbarch_long_bit (gdbarch
, 32);
6295 set_gdbarch_ptr_bit (gdbarch
, 32);
6296 set_gdbarch_long_long_bit (gdbarch
, 64);
6297 set_gdbarch_deprecated_reg_struct_has_addr
6298 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6299 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6301 case MIPS_ABI_EABI64
:
6302 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6303 set_gdbarch_deprecated_store_return_value (gdbarch
,
6304 mips_eabi_store_return_value
);
6305 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6306 mips_eabi_extract_return_value
);
6307 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6308 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6309 tdep
->default_mask_address_p
= 0;
6310 set_gdbarch_long_bit (gdbarch
, 64);
6311 set_gdbarch_ptr_bit (gdbarch
, 64);
6312 set_gdbarch_long_long_bit (gdbarch
, 64);
6313 set_gdbarch_deprecated_reg_struct_has_addr
6314 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6315 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6318 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6319 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6320 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6321 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6322 tdep
->default_mask_address_p
= 0;
6323 set_gdbarch_long_bit (gdbarch
, 32);
6324 set_gdbarch_ptr_bit (gdbarch
, 32);
6325 set_gdbarch_long_long_bit (gdbarch
, 64);
6328 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6329 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6330 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6331 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6332 tdep
->default_mask_address_p
= 0;
6333 set_gdbarch_long_bit (gdbarch
, 64);
6334 set_gdbarch_ptr_bit (gdbarch
, 64);
6335 set_gdbarch_long_long_bit (gdbarch
, 64);
6338 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
6341 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6342 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6345 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6346 flag in object files because to do so would make it impossible to
6347 link with libraries compiled without "-gp32". This is
6348 unnecessarily restrictive.
6350 We could solve this problem by adding "-gp32" multilibs to gcc,
6351 but to set this flag before gcc is built with such multilibs will
6352 break too many systems.''
6354 But even more unhelpfully, the default linker output target for
6355 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6356 for 64-bit programs - you need to change the ABI to change this,
6357 and not all gcc targets support that currently. Therefore using
6358 this flag to detect 32-bit mode would do the wrong thing given
6359 the current gcc - it would make GDB treat these 64-bit programs
6360 as 32-bit programs by default. */
6362 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6363 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6364 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6366 /* Add/remove bits from an address. The MIPS needs be careful to
6367 ensure that all 32 bit addresses are sign extended to 64 bits. */
6368 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6370 /* Unwind the frame. */
6371 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6372 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
6374 /* Map debug register numbers onto internal register numbers. */
6375 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6376 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6377 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6378 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
6379 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6380 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6381 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6382 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6384 /* MIPS version of CALL_DUMMY */
6386 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6387 replaced by a command, and all targets will default to on stack
6388 (regardless of the stack's execute status). */
6389 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6390 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6392 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6393 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6394 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6396 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6397 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6399 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6401 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6402 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6403 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6405 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6407 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6409 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6411 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6412 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6413 need to all be folded into the target vector. Since they are
6414 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6415 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6417 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6419 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6421 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
6422 to support MIPS16. This is a bad thing. Make sure not to do it
6423 if we have an OS ABI that actually supports shared libraries, since
6424 shared library support is more important. If we have an OS someday
6425 that supports both shared libraries and MIPS16, we'll have to find
6426 a better place for these. */
6427 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
6429 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6430 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6433 /* Hook in OS ABI-specific overrides, if they have been registered. */
6434 gdbarch_init_osabi (info
, gdbarch
);
6436 /* Unwind the frame. */
6437 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
6438 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
6439 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
6440 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
6441 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6442 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
6443 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6444 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6450 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6452 struct gdbarch_info info
;
6454 /* Force the architecture to update, and (if it's a MIPS architecture)
6455 mips_gdbarch_init will take care of the rest. */
6456 gdbarch_info_init (&info
);
6457 gdbarch_update_p (info
);
6460 /* Print out which MIPS ABI is in use. */
6463 show_mips_abi (char *ignore_args
, int from_tty
)
6465 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6467 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6470 enum mips_abi global_abi
= global_mips_abi ();
6471 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6472 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6474 if (global_abi
== MIPS_ABI_UNKNOWN
)
6476 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6478 else if (global_abi
== actual_abi
)
6480 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6484 /* Probably shouldn't happen... */
6486 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6487 actual_abi_str
, mips_abi_strings
[global_abi
]);
6493 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6495 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6499 int ef_mips_32bitmode
;
6500 /* determine the ISA */
6501 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6519 /* determine the size of a pointer */
6520 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6521 fprintf_unfiltered (file
,
6522 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6524 fprintf_unfiltered (file
,
6525 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6527 fprintf_unfiltered (file
,
6528 "mips_dump_tdep: ef_mips_arch = %d\n",
6530 fprintf_unfiltered (file
,
6531 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6532 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6533 fprintf_unfiltered (file
,
6534 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6535 mips_mask_address_p (tdep
),
6536 tdep
->default_mask_address_p
);
6538 fprintf_unfiltered (file
,
6539 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6540 MIPS_DEFAULT_FPU_TYPE
,
6541 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6542 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6543 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6545 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6546 fprintf_unfiltered (file
,
6547 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6549 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6550 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6551 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6553 fprintf_unfiltered (file
,
6554 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6555 mips_stack_argsize (current_gdbarch
));
6556 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6557 fprintf_unfiltered (file
,
6558 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6559 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6560 fprintf_unfiltered (file
,
6561 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6562 XSTRING (ATTACH_DETACH
));
6563 fprintf_unfiltered (file
,
6564 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6565 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6566 fprintf_unfiltered (file
,
6567 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6568 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6569 fprintf_unfiltered (file
,
6570 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6571 FIRST_EMBED_REGNUM
);
6572 fprintf_unfiltered (file
,
6573 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
6574 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
6575 fprintf_unfiltered (file
,
6576 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6577 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6578 fprintf_unfiltered (file
,
6579 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6580 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6581 fprintf_unfiltered (file
,
6582 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6584 #ifdef MACHINE_CPROC_FP_OFFSET
6585 fprintf_unfiltered (file
,
6586 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6587 MACHINE_CPROC_FP_OFFSET
);
6589 #ifdef MACHINE_CPROC_PC_OFFSET
6590 fprintf_unfiltered (file
,
6591 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6592 MACHINE_CPROC_PC_OFFSET
);
6594 #ifdef MACHINE_CPROC_SP_OFFSET
6595 fprintf_unfiltered (file
,
6596 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6597 MACHINE_CPROC_SP_OFFSET
);
6599 fprintf_unfiltered (file
,
6600 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6602 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6603 fprintf_unfiltered (file
,
6604 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6605 fprintf_unfiltered (file
,
6606 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6607 fprintf_unfiltered (file
,
6608 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6609 MIPS_LAST_ARG_REGNUM
,
6610 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6611 fprintf_unfiltered (file
,
6612 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6613 fprintf_unfiltered (file
,
6614 "mips_dump_tdep: mips_abi_regsize() = %d\n",
6615 mips_abi_regsize (current_gdbarch
));
6616 fprintf_unfiltered (file
,
6617 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6618 fprintf_unfiltered (file
,
6619 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6620 fprintf_unfiltered (file
,
6621 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6622 fprintf_unfiltered (file
,
6623 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6624 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6625 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6626 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6627 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6628 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6629 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6630 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6631 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6632 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6633 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6634 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6636 fprintf_unfiltered (file
,
6637 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6640 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6643 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6645 fprintf_unfiltered (file
,
6646 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6647 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6648 fprintf_unfiltered (file
,
6649 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6650 fprintf_unfiltered (file
,
6651 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6652 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6653 fprintf_unfiltered (file
,
6654 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6655 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6656 fprintf_unfiltered (file
,
6657 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6658 SOFTWARE_SINGLE_STEP_P ());
6659 fprintf_unfiltered (file
,
6660 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6661 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6662 #ifdef STACK_END_ADDR
6663 fprintf_unfiltered (file
,
6664 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6667 fprintf_unfiltered (file
,
6668 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6669 XSTRING (STEP_SKIPS_DELAY (PC
)));
6670 fprintf_unfiltered (file
,
6671 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6672 STEP_SKIPS_DELAY_P
);
6673 fprintf_unfiltered (file
,
6674 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6675 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6676 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6677 fprintf_unfiltered (file
,
6678 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6679 fprintf_unfiltered (file
,
6680 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6681 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6682 (TYPE
, CNT
, OTHERTYPE
)));
6683 fprintf_unfiltered (file
,
6684 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6685 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6687 fprintf_unfiltered (file
,
6688 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6689 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6692 fprintf_unfiltered (file
,
6693 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6695 #ifdef TRACE_FLAVOR_SIZE
6696 fprintf_unfiltered (file
,
6697 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6701 fprintf_unfiltered (file
,
6702 "mips_dump_tdep: TRACE_SET # %s\n",
6703 XSTRING (TRACE_SET (X
, STATE
)));
6705 #ifdef UNUSED_REGNUM
6706 fprintf_unfiltered (file
,
6707 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6709 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6710 fprintf_unfiltered (file
,
6711 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6712 (long) VM_MIN_ADDRESS
);
6713 fprintf_unfiltered (file
,
6714 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6715 fprintf_unfiltered (file
,
6716 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_
);
6719 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6722 _initialize_mips_tdep (void)
6724 static struct cmd_list_element
*mipsfpulist
= NULL
;
6725 struct cmd_list_element
*c
;
6727 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6728 if (MIPS_ABI_LAST
+ 1
6729 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6730 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6732 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6734 mips_pdr_data
= register_objfile_data ();
6736 /* Add root prefix command for all "set mips"/"show mips" commands */
6737 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6738 "Various MIPS specific commands.",
6739 &setmipscmdlist
, "set mips ", 0, &setlist
);
6741 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6742 "Various MIPS specific commands.",
6743 &showmipscmdlist
, "show mips ", 0, &showlist
);
6745 /* Allow the user to override the saved register size. */
6746 deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6749 &mips_abi_regsize_string
, "\
6750 Set size of general purpose registers saved on the stack.\n\
6751 This option can be set to one of:\n\
6752 32 - Force GDB to treat saved GP registers as 32-bit\n\
6753 64 - Force GDB to treat saved GP registers as 64-bit\n\
6754 auto - Allow GDB to use the target's default setting or autodetect the\n\
6755 saved GP register size from information contained in the executable.\n\
6756 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6758 /* Allow the user to override the argument stack size. */
6759 deprecated_add_show_from_set
6760 (add_set_enum_cmd ("stack-arg-size",
6763 &mips_stack_argsize_string
, "\
6764 Set the amount of stack space reserved for each argument.\n\
6765 This option can be set to one of:\n\
6766 32 - Force GDB to allocate 32-bit chunks per argument\n\
6767 64 - Force GDB to allocate 64-bit chunks per argument\n\
6768 auto - Allow GDB to determine the correct setting from the current\n\
6769 target and executable (default)", &setmipscmdlist
),
6772 /* Allow the user to override the ABI. */
6773 c
= add_set_enum_cmd
6774 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6775 "Set the ABI used by this program.\n"
6776 "This option can be set to one of:\n"
6777 " auto - the default ABI associated with the current binary\n"
6779 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6780 set_cmd_sfunc (c
, mips_abi_update
);
6781 add_cmd ("abi", class_obscure
, show_mips_abi
,
6782 "Show ABI in use by MIPS target", &showmipscmdlist
);
6784 /* Let the user turn off floating point and set the fence post for
6785 heuristic_proc_start. */
6787 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6788 "Set use of MIPS floating-point coprocessor.",
6789 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6790 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6791 "Select single-precision MIPS floating-point coprocessor.",
6793 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6794 "Select double-precision MIPS floating-point coprocessor.",
6796 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6797 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6798 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6799 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6800 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6801 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6802 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6803 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6804 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6805 "Select MIPS floating-point coprocessor automatically.",
6807 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6808 "Show current use of MIPS floating-point coprocessor target.",
6811 /* We really would like to have both "0" and "unlimited" work, but
6812 command.c doesn't deal with that. So make it a var_zinteger
6813 because the user can always use "999999" or some such for unlimited. */
6814 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6815 (char *) &heuristic_fence_post
, "\
6816 Set the distance searched for the start of a function.\n\
6817 If you are debugging a stripped executable, GDB needs to search through the\n\
6818 program for the start of a function. This command sets the distance of the\n\
6819 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6820 /* We need to throw away the frame cache when we set this, since it
6821 might change our ability to get backtraces. */
6822 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6823 deprecated_add_show_from_set (c
, &showlist
);
6825 /* Allow the user to control whether the upper bits of 64-bit
6826 addresses should be zeroed. */
6827 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6828 Set zeroing of upper 32 bits of 64-bit addresses.", "\
6829 Show zeroing of upper 32 bits of 64-bit addresses.", "\
6830 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6831 allow GDB to determine the correct value.\n", "\
6832 Zerroing of upper 32 bits of 64-bit address is %s.",
6833 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6835 /* Allow the user to control the size of 32 bit registers within the
6836 raw remote packet. */
6837 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6838 &mips64_transfers_32bit_regs_p
, "\
6839 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6840 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6841 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6842 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6843 64 bits for others. Use \"off\" to disable compatibility mode", "\
6844 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6845 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6847 /* Debug this files internals. */
6848 deprecated_add_show_from_set
6849 (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6850 &mips_debug
, "Set mips debugging.\n\
6851 When non-zero, mips specific debugging is enabled.", &setdebuglist
),